SYNC SIGNAL DETECTION APPARATUS

Abstract: There is disclosed a sync signal detection apparatus wherein a sync signal representing the top of recorded data is composed of a plurality of marks each having a pattern dif­ ferent from that of any other mark. The apparatus is equipped with a circuit for sequentially detecting the patterns of the individual marks in a reproduction mode, and a circuit for generating, upon detection of a predetermined number of marks, a sync pulse at the top of the data in accordance with the address pattern of the mark.

Description: BACKGROUND OF THE INVENTION: Field of the Invention: The present invention relates to detection of a sync signal in a magnetic recorder, an optical recorder or the like. Description of the Prior Art: In the conventional machine for recording data on and reproducing the same from a recording medium, it is generally customary that the recording medium is so formated as shown in Fig. 2. In this diagram, SM (sector mark) is a signal representing the top of a sector; VFO SYNC is a clock signal for locking in a PLL circuit; ID is a signal of positional information relative to a track number, a sector number and so forth; and SYNC is a signal representing the top of data. Each track on the recording medium is divided into a predetermined number a of sectors as shown in Fig. 2 (a), and each sector is so formated as shown in (b). Such a sector is used as a unitary region when data is recorded. For reading out the data 12 recorded in the sector, first a PLL circuit is activated by a VFO SYNC 10 recorded in the sector, whereby a read clock for the data 12 is generated. Subsequently a SYNC signal 11 recorded in the sector is detected by reference to such read clock to generate a sync pulse which represents the top of the data 12, thereby setting next circuits (demodulation circuit and so forth) to read out the data 12. According to such a conventional read system, however, there are existent some drawbacks including that proper demodulation is not attainable in case the sync signal is not detected with accuracy, hence directly causing an increase of the error rate. Japanese patent application JP 58-121113 (Patent Abstracts of Japan, Vol. 7, No. 231 (P229)) discloses a configuration in which a plurality of different synchronizing patterns are set, and in a detection mode all of the synchronizing patterns are held in the shift register, and the contents of the shift register are simultaneously compared with a plurality of predetermined reference synchronizing patterns. The logical OR of the comparison results is used for accommodating an error in the synchronizing patterns. US-A-4 124 778 describes the use within digital information processing of a non-return to zero mark (NRZ-M), wherein a transition is provided only when a digital one occurs, and no transitions are provided when digital zeros occur. SUMMARY OF THE INVENTION: The present invention has been accomplished in an attempt to solve the problems mentioned above and in recognition of the desirability of realising exact detection of the sync signal. In accordance with a first aspect of the present invention there is provided a sync signal detection apparatus for detecting a sync signal indicating the start of recorded data, the sync signal being divided into a plurality of unique marks, characterized in that each of the plurality of marks is divided into a digital sync pattern and a digital address pattern, and said apparatus comprises: means for sequentially detecting the sync and address patterns for each of the plurality of marks in a reproduction mode; and means for generating, in response to a predetermined number of marks being detected by said means for sequentially detecting, a sync pulse at a time dependent on the address pattern of said marks and thereby at the start of the recorded data. In accordance with a second aspect of the present invention there is provided a method of recording data digitally on and reproducing from a recording medium, the data being recorded in a plurality of sections on the medium, each said section having associated therewith a recorded sync signal, characterized in that said sync signal is recorded as a plurality of sync signal portions each having a unique mark which is divided into a sync pattern and an address pattern which are individually and sequentially detected during reproduction, and a sync pulse is generated, in response to a predetermined number of marks being sequentially detected, at a time dependent on the address pattern of said marks and thereby at the start of the associated section of recorded data. BRIEF DESCRIPTION OF THE DRAWINGS: The present invention will become more fully understood from the detailed description given herein-below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: Fig. 1 is a block diagram of a sync signal detection apparatus embodying the present invention; Fig. 2 illustrates a format on a recording medium; Figs. 3 and 4 show bit patterns of sync signals; and Tables I and II show codes. DESCRIPTION OF THE PREFERRED EMBODIMENT: Hereinafter an exemplary embodiment of a sync signal detection apparatus according to the present invention will be described with reference to the accompanying drawings. Tables I and II show codes of NRZI (non-return to zero inverted) modulation system in a sync signal detection apparatus embodying the invention. In any magnetic recorder where audio signals are processed by pulse code modulation and a recording operation is performed by the use of a rotary head without forming a guard band, a low-frequency component is cut off due to the differential output characteristic in magnetic recording and also by a rotary transformer in addition to the low-frequency crosstalk from an adjacent track, so that there exists a problem of failure in achieving high-fidelity reproduction of the low-frequency component. Accordingly, in such apparatus where the recording/reproducing frequency band is narrow and the low-frequency component needs to be minimized, it is effective to process the record signal by a modulation system in which the frequency spectrum component is small in low-frequency and DC areas. One of preferred modulation systems is NRZI which causes signal inversion at "1" in a data signal but no inversion at "0". In this embodiment are employed 8 pre-modulation bits m and 10 post-modulation bits n , wherein a maximum inversion width Tmax is set to be 4T' (in which T' = minimum inversion width Tmin = detection window width Tw), and 4T' are not continuous. In a recording mode is adopted an NRZI (non-return to zero inverted) system where a signal is inverted at "1" but not inverted at "0". In Tables I and II, Q' and Q respectively denote direct-current storage data of a preceding-position code and that of a present-position code, and DC denotes a direct current component. Suppose now that a recording medium processed by the NRZI modulation system of Code Tables I and II is so formated as shown in Fig. 2. The SYNC signal in Fig. 2 is composed generally of several bytes, and in this example it is composed of 6 bytes (60 code bits) which are divided into four marks each having 15 code bits. Here, the code bit is defined as a post-modulation bit. Such 15 code bits are divided into a sync pattern of 9 code bits and an address pattern of 6 code bits. The sync pattern of 9 code bits is such as shown in Fig. 3 (a) which is not generated in the code data. Meanwhile the address pattern of 6 code bits represents the ordinal number in storage of the corresponding mark. If any address pattern becomes equal to some other address pattern due to an error, it is impossible to generate a sync pulse which is exactly coincident with the top of the data 12. Therefore, in forming four address patterns each composed fixedly of 6 code bits, initially a basic pattern 1 ○ in Fig. 3 (b) is defined as a first address pattern. In this case, the basic pattern is so formed as not to include a pattern of 4T for the purpose of attaining easy distinction from the sync pattern. A second address pattern is such as denoted by 2 ○ which is an inversion of the NRZI waveform of the foregoing pattern 1 ○. In a third address pattern 3 ○, its first three code bits are inverted with respect to the waveform of 1 ○ or 2 ○ while the remaining three code bits have the same waveform. And a fourth address pattern 4 ○ has an inverted waveform with respect to the pattern 3 ○. In detection by an NRZ (non-return to zero) system, each of the address patterns thus selected cannot become the same as any other address pattern unless there occur errors in at least three code bits. Fig. 4 shows marks formed by combining the aforementioned sync pattern (100010001) with the above four address patterns. The marks I - IV correspond to a SYNC signal and are written in a recording mode continuously with VFO SYNC 10 as shown in Fig. 2 (b). An embodiment in which the 8/10 conversion system is used in an apparatus according to the invention will be described. In the 8/10 conversion system, the pre-modulation bit number m is 8, and the post-modulation bit number n is 10, and the conversion summarized in Tables I and II is conducted. In Tables I and II, "DATA" indicates pre-modulation 8-bit strings, and "CODE" post-modulation 10-bit strings. Table I is a conversion table for the case in which the direct-current storage data Q' is "0", and Table II a conversion table for the case in which the direct-current storage data Q' is "1". For example, Table I shows that "0A(HEX)" in the DATA column is "00001010" in decimal and corresponds to "17D(HEX)" in the CODE column which is "0101111101" in decimal. The Q column indicates direct-current storage data of a present-position code for the succeeding conversion. At the succeeding conversion, the direct-current storage data Q is given as the direct-current storage data of a preceding-position code so as to suppress the direct-current component in the sequential conversion. For example, a sequential conversion of a 3-byte data of 0A/4F/AF will be described. First, "0A" is converted using Table I to "17D" in which the direct-current component DC is "0" and the direct-current storage data Q is "1". Since the direct-current storage data Q in the conversion of "0A" is "1", the direct-current storage data Q' in the conversion of "4F" is "1", and hence Table II is searched, thereby converting "4F" into "33A" in which the direct-current component DC is "-2" and the direct-current storage data Q is "0". The direct-current storage data Q' in the conversion of "AF" is set to "0" so that Table I is searched, resulting in that "AF" is converted into "2FA" in which the direct-current component DC is "+2". The addition of the three direct-current components DC shows that the resulting direct-current component DC in the sequential conversion is 0 (0 + (-2) + (+2) = 0), i.e. a selection conversion with a suppressed direct-current component is performed. In the post-modulation bit strings obtained by the 8/10 conversion system, as described above, the maximum inversion width Tmax is set to 4T' (wherein T' = minimum width Tmin = detection window width Tw), and the width of 4T' does not appear continuously. In a recording mode, the NRZI system in which a signal is inverted at "1" and not inverted at "0" is employed. Fig. 1 is a schematic block diagram of an apparatus for reproducing the signals recorded as described above. In Fig. 1, the VFO SYNC 10 is read out by a driver 100 which performs a recording/reproducing operation, and the data thus read out is synchronized by a PLL circuit 200, which then outputs read data RDDT 20 (VFO SYNC, SYNC, DATA and so forth) and a read clock RDCK 21 used for reading out the data RDDT 20. The read data RDDT 20 and the read clock RDCK 21 are fed to a demodulator 300 and a converter 400, respectively. The read data RDDT 20 inputted to the converter 400 is converted from the NRZI signal into an NRZ (non-return to zero) signal. Read data 31 obtained by such conversion into the NRZ signal is changed to a parallel form by a shift register 30. The parallel data of 15 high-order code bits included in the SYNC are introduced to a mark detection circuit 33, while the data of 6 low-order code bits is introduced to a flip-flop FF 34. In the mark detection circuit 33, a check for coincidence of mark patterns is executed with respect to every 15 code bits, and a detection pulse 37 is outputted when a predetermined number (one in this example) of marks is detected. Then the detected marks are counted and the result is outputted to a system controller 500. Meanwhile in response to the detection pulse 37, the flip-flop FF 34 latches the input data (address pattern) and feeds it to a ROM 35. In case the second address pattern 2 ○ is inputted to the ROM 35, "30" corresponding to the entire bits of the remaining marks III and IV is outputted in parallel from the ROM 35 and then is fed to a counter circuit 36. The counter circuit 36 reset by an inverted pulse of the detection pulse 37 starts counting the number of RDCK 21 inputted from the ROM 35 thereafter and generates a sync pulse 38. This sync pulse 38 represents the top of the data 12 and serves to reset the demodulation circuit 300, which is thereby rendered ready for proper demodulation of the data 12. In executing a read check immediately after write, the sync signal recorded in the sector is judged to be erroneous or not by the system controller 500 in accordance with the result of counting the output of the mark detection circuit 33 and, in case the recorded sync signal is erroneous, rerecording is performed in the other sector. Thus, the reliability of sync signal detection can be enhanced with respect to any induced error as well. In the present invention, as described hereinabove, the sync signal is divided into a plurality of marks, each of which is further divided into a sync pattern and an address pattern and then is recorded. In case any error occurs in the sync signal at the time of detection, an accurate sync pulse can still be produced if more than a predetermined number of marks are detected. Although a description has been given on NRZI modulation in the above embodiment, the same effect is attainable by some other modulation as well. It is to be understood that the aforementioned is merely illustrative with regard to the number of sync signal bytes, the number of division thereof, and the numbers of bits of an address pattern and a sync pattern. And in particular, more precise sync pulses can be produced by increasing the number of division of sync patterns and the number of bits of address patterns. As is obvious from the description given above, the present invention is capable of ensuring accurate synchronization for the reproduced data with a smaller number of bits, hence realizing further enhancement of the data reliability.

Claims: A sync signal detection apparatus for detecting a sync signal indicating the start of recorded data (12), the sync signal (11) being divided into a plurality of unique marks characterized in that each of the plurality of marks is divided into a digital sync pattern and a digital address pattern and said apparatus comprises: means (33) for sequentially detecting the sync and address patterns for each of the plurality of marks in a reproduction mode; and means (34, 35, 36) for generating, in response to a predetermined number of marks being detected by said means for sequentially detecting, a sync pulse at a time dependent on the address pattern of said marks and thereby at the start of the recorded data. The detection apparatus as defined in claim 1, wherein said sync signal is recorded in a non-return to zero inverted system. A method of recording data digitally on and reproducing from a recording medium, the data being recorded in a plurality of sections on the medium, each said section having associated therewith a recorded sync signal, characterized in that said sync signal is recorded as a plurality of sync signal portions (11) each having a unique mark which is divided into a sync pattern and an address pattern which are individually and sequentially detected during reproduction, and a sync pulse is generated, in response to a predetermined number of marks being sequentially detected, at a time dependent on the address pattern of said marks and thereby at the start of the associated section of recorded data.

Inventors: KENTARCH, TSUJI, NORIAKI, SAKAMOTO, SHIGEMI, MAEDA, SHIGEO, TERASHIMA, TAKESHI, YAMAGUCHI, TOSHIHISA, DEGUCHI C-722 DAIYA HEIGHTS GAKUENMAE
Applicants: SHARP KABUSHIKI KAISHA
Application year: 1987
Main classification: H04N5
IPC codes: G11B27, H04N5, G11B20, H04L7