Processor for the calculation of transcendental functions

Abstract: A processor for carrying out modulo reduction of a floating-point data by use of a predetermined constant is disclosed. A subtraction operation of more significant bits of the predetermined constant from a mantissa part data of the floating-point data is performed and the subtraction result is normalized. Less significant bits data of the constant is shifted and this result is subtracted from the above normalized data, this subtraction result being then normalized. Thus, a remainder caused by the modulo reduction is obtained.

Description: The present invention relates to an arithmetic processing unit of floating-point data and, more particularly, to a processor for executing arithmetic operation of a trigonometric function, an inverse trigonometric function, an exponential function and a logarithmic function. Execution of arithmetic operation of the above-mentioned functions basically includes such processing that input floating-point data is subjected to modulo reduction by use of a particular constant as a divisor and a series expansion or a so-called CORDIC is carried out with respect to a remainder obtained by the modulo reduction. The constant used in this processing is obtained by rounding an irrational number such as π, e (exponent), etc. to a finite figure. For this reason, when the binary value of a mantissa part of the input data is close to that of a mantissa part of the particular constant, the more significant bits of the remainder become zero to reduce significant digits thereof. As a result, the product by the series expansion or the CORDIC operation contains a large error. If the bit length of the input data and the particular constant is prolonged, the reduction of significant digits of the remainder can be suppressed. However, it requires a larger hardware such as an arithmetic logic unit and registers. Therefore, an object of the present invention is to provide a floating-point data processor with a small error in an arithmetic result which does not require a large hardware. Another object of the present invention is to provide a processor for executing arithmetic operation of a trigonometric function, an inverse trigonometric function, an exponential function and a logarithmic function in which the decrease in significant digits of a remainder by modulo reduction is prevented. These objects are achieved by a processor as defined in claim 1; the dependent claims are related to further developments of the invention. Thus, the bit length of the particular constant is longer than that of the input data. The input data is subjected to modulo reduction by use of the more significant bits of the particular constant, and the first data obtained by the modulo reduction is normalized to produce the second data. Since the first data is normalized, the less significant bits of the particular constant is shifted to make digits thereof coincident with thoses of the second data. The subtraction operation is carried out between the second data and the shifted less significant bits of the particular constant to produce a third data which is then normalized. The normalized data is employed as a remainder of the modulo reduction. Accordingly, the reduction in significant digits of the remainder is prevented, and an error of the resultant of arithmetic operation of the series expansion or CORDIC becomes very small. The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a block diagram representing an embodiment of the present invention; Fig. 2 is an operating flow chart in a case where a processor shown in Fig. 1 is used to carry out arithmetic operation of a trigonometic function; Fig. 3 is a data changing diagram representing a part of the operation of Fig. 2; Fig. 4 is a data changing diagram representing another part of the operation of Fig. 2; Fig. 5 is a graph representing the number of bits taking error data with respect to an input data X according to the present invention; and Figs. 6A and 6B are graphs representing the number of bits taking error data with respect to an input data X according to prior art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 1, a processor according to an embodiment of the present invention includes a read only memory (called hereinafter "ROM") 1 which stores more significant bits and less significant bits of a particular constant at first and second memory locations of first and second word addresses, respectively, this particular constant being used for modulo reduction. The ROM 1 also stores at a third memory location of a third address the number of bits of a mantissa part of an input data. A leading-1 detector 2 detects a bit position of a leading-1 of a data supplied thereto and supplies a detection data to a data shifter 3. This shifter 3 shifts leftward or rightward a data supplied thereto by bit numbers determined by the detection data supplied from the leading-1 detector 2. An arithmetic logic unit (called hereinafter ALU) 6 carries out a subtraction operation or an addition operation between data stored in an A-register 4 and a B-register 5 and supplies the resultant to a C-register 7 having a borrow bit 8. The content of a borrow bit 8 is supplied through an inverter 9 to a quotient register 10. The processor further includes a register unit 11 which has three registers 11-1 to 11-3. The data transmission among the respective blocks is carried out via an internal data bus 12. A circuit operation of the processor shown in Fig. 1 will be described below by way of example of trigonometric function arithmetic. The arithmetic algorithm of a trigonometric function is as follows: (1) Modulo Reduction of Input Data X R (remainder) = X mod. π/2 Q (quotient) = Int. (X/(π/2)) (2) Q: even → R' = R Q: odd → R' = π/2 - R (3) Calculate Sin R' More specifically, an input data X is subjected to the modulo reduction by use of a particular constant, i.e. π/2, to obtain a remainder R and a quotient Q. The remainder R is corrected in accordance with the quotient Q. Namely, in a case where the quotient Q is even, the remainder R is employed as a corrected remainder R′ as it is, but in a case where the quotient Q is odd, the data of ( π/2-R ) is employed as the corrected remainder R′. Sin R′ is calculated by making use of the series expansion or the CORDIC, and the final correction such as, for example, a sign is performed to obtain Sin X. When the value of the input data X and/or the remainder R is close to π/2, the significant digits of the corrected remainder R′ are reduced, so that the resultant of the series expansion or CORDIC includes a large error. In order to prevent the occurrence of a large error, the processor shown in Fig. 1 operates in accordance with a flow chart shown in Fig. 2. More specifically the input data X is supplied as a floating-point data having a sign part of one bit, an exponent part of 15 bits and a mantissa part of 64 bits, and its mantissa part is stored via the internal data bus 12 into the first register 11-1 of the register unit 11. On the other hand, since the value of π/2 is employed as a particular constant for the modulo reduction, the mantissa part thereof is expanded twice (i.e., 128 bits data), and its more significant bits data, i.e. π/2(U) = C90F DAA2 2168 C234(H) , and its less significant bits data, i.e. π/2(L) = C4C6 628E 80DC 10Dl(H) , are stored respectively in the first and second word addresses of the ROM 1. The mark (H) is hexadecimal representation. The ROM 1 also stores at the third address the number of bits of the mantissa part of the input data, i.e. 40(H) = 64. The mantissa part of input data X stored in the first register 11-1 and the more significant bits data π/2(U) stored in the first address of the ROM 1 are read out and then stored into the A-register 4 and B-register 5, respectively. The ALU 6 subtracts the content of the B-register 5 from that of the A-register 4 and stores the subtraction result into the C-register 7. When the value of the mantissa part of the input data X is smaller than the value of the more significant bits data π/2(U), the borrow bits 8 takes "1". The content of the borrow bit 8 is inverted by the inverter 9 and the inverted data is supplied to the quotient register 10. Therefore, the content of the register 10 is held at "0". That is, when the input data X is in a range between - π/2 and π/2, the borrow bit 8 takes 1 and the register 10 takes "0". As a result, the content of the first register 11-1, i.e. mantissa part of the input data X, is read out, and the arithmetic operation of the series expansion or the CORDIC is performed with respect to this data. When the input data X is not in the range between -π/2 and π/2, the borrow bit 8 takes "0". In this case, the subtraction result stored in the C-register 7 is outputted on the internal data bus 12 and then supplied to the first register 11-1 and the A-register 4. The ALU 6 subtracts the more significant bits data π/2(U) from the new content of the A-register 4. This sequence of steps are continued until the borrow bit 8 takes "1". When the borrow bit 8 takes "1", the content of the quotient register 10 is judged. Since the content of the register 10 is not "0" at this time, the data stored in the first register 11-1 is normalized. More specifically, assuming that the data stored in the first register 11-1 just before the borrow bit 8 takes "1" is close to the value of the upper bits data π/2(H) and takes a value of "C90F DAA2 2168 C236(H)", as shown in Fig. 3, the subtraction result by the ALU 6 is "0000 0000 0000 0002(H)". This data has been stored into the first register 11-1 when the borrow it 8 changes from "0" to "1". Therefore, the data "0000 0000 0000 0002(H)" is nomalized. For this purpose, the data stored in the first register 11-1 is read out and supplied via the leading-1 detector 2 and the shifter 3. The leading-1 detector detects that the leading-1 of the supplied data is positioned at the sixty-third bit, and hence supplies a shift-data of "62" to the shifter 3. The shifter 3 responds to the shift-data and shifts leftward the supplied data by 62 bits. As a result, a data A, "8000 0000 0000 0000(H)" shown in Fig. 3, is obtained from the shifter 3 and then stored in the first register 11-1. Thus, the data normalizing is completed. Since the leading-1 detector 2 and the shifter 3 are well known in the art, the detailed constitutions thereof are omitted. According to prior art, the data A is employed as a remainder R and the series expansion or the CORDIC is carried out. Since the number of significant digits of the data A is only one, the processing resultant contains a large error. In order to prevent this drawback, the processor according to the present embodiment carries out the subtraction operation between the data A and the less significant bits data π/2(L). At this time, since the digit of the data A is shifted, the digit of the lower bits data π/2(L) should be coincident with that of the data A. For this purpose, the data stored in the third word address of the ROM 1 and the shift-data obtained by the leading-1 detector 2 are read out and then stored into the A-register 4 and the B-register 5, respectively. The ALU 6 subtracts the content of the B-register 5 from that of the A-register 4, and the subtraction data "2" is supplied to the shifter 3 as a shift-data. The shifter 3 is also supplied with the less significant bits data π/2(L) and shifts rightward this data by two bits. As a result, a data B taking a value of "3131 98A2 E037 0734(H)" is obtained as shown in Fig. 3 and is stored in the second register 2. This data B is then read out and supplied to the B-register 5. On the other hand, the data A stored into the first register 11-1 is read out and then supplied to the A-register 4. The ALU 6 subtracts the data B from the data A. This resultant takes a value of "4E0E 675D 1FC8 F8CC(H)" as shown in Fig. 3 and is stored into the third register 11-3 as a data C. The data normalizing making use of the leading-1 detector 2 and the shifter 3 is carried out with respect to the data C in the same manner as described hereinbefore. As a result, a data D taking a value of "9D9C CEBA 3F91 F198(H)" shown in Fig. 3 is obtained and then stored into the first register 11-1. This data D is employed as a remainder R as a result of modulo reduction. As mentioned previously, the remainder R should be corrected in accordance with the quotient Q. For this purpose, the content of the quotient register 10 is judged. When the quotient Q is even, the data D is employed as the corrected remainder R'. The arithmetic operation of the series expansion or CORDIC is thereafter carried out. Since all the bits of the data D are significant, the error in the operation result becomes very small. When the quotient Q is odd, the subtraction of the data D from the value of π/2 should be performed. For this purpose, the data D stored in the first register 11-1 and the more significant bits data π/2(U) stored in the ROM 1 are read out and then supplied to the B-register 5 and A-register 4, respectively. The ALU 6 subtracts the data D from the more significant bits data π/2(U). Assuming that the data D takes a value of "C90F DAA2 2169 C233(H)" close to the value of the data π/2(U), as shown in Fig. 4, the subtraction result takes a value of "0000 0000 0000 0001(H)". The normalizing of the subtraction result is performed by making use of the leading-1 detector 2 and the shifter 3, so that a data E is obtained, which takes a value of "8000 0000 0000 0000(H)", as shown in Fig. 4. According to prior art, this data E is employed as the corrected remainder R′. For this reason, a large error occurs. According to the present invention, the less significant bits data π/2(L) is added to the data E. However, the digits of the data π/2(L) should be made coincident with those of the data E before the addition operation. For this purpose, the content at the third word address of the ROM 1 and the shift-data obtained by the leading-1 detector 2 are supplied to the A-register 4 and the B-register 5, respectively. The ALU 6 subtracts the content of the B-register 5 from that of the A-register 4 and supplied the result to the data shifter 3 as a shift-data. The shifter 3 is also supplied with the less significant bits data π/2(L) and shifts rightward this data by one bit. As a result, a data F taking a value of "6263 3145 C06E 0E69(H)" is obtained, as shown in Fig. 4. The data E and F are stored into the first and second registers 11-1 and 11-2, respectively. These data E and F are read out and supplied to the A-register 4 and the B-register 5, respectively. The ALU 6 adds the data F to the data E. As a result, a data G taking a value of "E263 3145 C06E 0E69(H)" is obtained and stored in the third register 11-3. The normalizing is performed with respect to the data G by use of the leading-1 detector 2 and the data shifter 2. In this case, the leading-1 of the data G is positioned at the first bit, and therefore the normalized data H takes the same value of the data G and is stored into the first register 11-1. Thus, the data H is employed as the corrected remainder R′ and the series expansion or the CORDIC is carried out. Since the number of significant digits of the remainder R′ is not reduced, an error of the processing result is very small. As described above, since the value of the mantissa part of π/2 is expanded twice in the present embodiment, the number of bits taking error data in the corrected remainder R′ is zero as shown in Fig. 5. Moreover, the bit length of the input data X and the value of π/2 is not increased substantially, the hardware does not become large. To the contrary, the number of bits taking error data in the remainder R′ according to prior art is shown in Fig. 6A when the quotient Q is even and in Fig. 6B when the quotient Q is odd, respectively, and a large number of bits take error data when the value of the mantissa part of the input data X is close to multiples of π/2. For example, the value of π/4 can be employed as a particular constant for the modulo reduction. Since the basic algorithm of each of a inverse trigonometric function, an exponential function and a logarithmic function is the same as that of the trigonometric function, the arithmetic technique according to the present invention is applicable to those functions.

Claims: A processor for carrying out modulo reduction of floating-point data by use of a predetermined constant, characterized by comprising first means (1) for storing more significant bits data and less significant bits data of a mantissa part of said predetermined constant, each of said more significant bits data and said less significant bits data respectively having a bit length equal to the bit length of a mantissa part of said floating-point data, register means (11) stored initially with the mantissa part of said floating-point data and then updated by data supplied thereto, second means (4-8) for performing a subtraction operation for subtracting said more significant bits data from the content of said register means (11) to produce a subtraction resultant data and supplying said subtraction resultant data to said register means (11), said second means repeating said subtraction operation until said subtraction resultant data becomes negative to thereby produce first data, third means (2) for detecting a bit position of leading-1 of said first data to produce a first shift-data, fourth means (3) for shifting said first data by the number of bits determined by said first shift-data to produce second data thus normalizing said first data, fifth means (1, 3-7) for shifting said less significant bits data by a number of bits determined by the difference between said first shift data and the bit length of the mantissa part of said floating-point data in order to align the digits of said less significant bits data on the digits of said second data for producing a third data, sixth means (4-7) for subtracting said third data from said second data to produce fourth data, means (2) for detecting a bit position of leading-1 of said fourth data to produce a second shift-data, and seventh means (3) for shifting said fourth data by the number of bits determined by said second shift-data in order to provide the resultant data. The processor as claimed in claim 1, wherein said first means (1) storing said more significant bits at a first memory location of a first word address and said less significant bits at a second memory location of a second address, respectively. The processor as claimed in claim 1, wherein a mantissa part of said predetermined constant has a bit length that is twice the bit length of a mantissa part of said input floating-point data. The processor as claimed in claim 1, wherein said fourth and seventh means (3) respectively shift said first and fourth data in a leftward direction and said fifth means (1, 3-7) shifts said less significant bits data in a rightward direction.

Inventors: SASAHARA MISAYO C O NEC CORPOR, SASAHARA, MISAYO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1987
Main classification: G06F7
IPC codes: G06F7, G06F1