DIGITAL TRANSMISSION SYSTEM

Abstract: The transmitter has a clock pulse extraction section which produces pulses phase-locked with synchronisation pulses in digital audio interface (DAI) formate signals from the receiver. These pulses time the operation of a transmitter data reader for on a recording medium and of an encoder receiving the read data and producing a second set of DAI format signals. The second set of signals are sent to the receiver where they are supplied to a decoder and a clock pulse extraction section which produces clock pulses that are phase-locked with synchronisation pulses in the 2nd DAI format signals and time decoder operation. The decoder output is supplied to a digital analog converter (9) whose operation is controlled by a master clock. The master clock output also goes to an encoder in the receiver for producing the 1st DAI format signals.

Description: This invention relates to digital transmission systems for transmitting data using a digital audio interface (DAI). A known DAI transmission system is shown in Figure 1. Since the DAI transmits L-channel and R-channel data through a single digital cable, it employs a time-division-multiplexing transmission system which permits the L-channel and R-channel data to be alternately transmitted and received, as shown in Figure 6A. If the sampling frequency is chosen to be, for example, 44.1 kHz as in the case of a compact disc, 44100 samples of the respective R-channel and L-channel data, that is, 88200 samples of data of both channels are transmitted per second. One channel data period (word) is 11.34 µsec. One word is formed of 32 bits which are divided, for example, as shown in Figure 6B. Specifically, the first four bits are assigned to be a SYNC portion for synchronization in which a preamble, later referred to, is inserted. The subsequent portion for audio data, has a capacity of 24 bits. However, in many cases audio data are formed of 16 bits, as in a compact disc, so that only 16 bits from the end are presently used. The last four bits are assigned to be a control portion for information added to the data, such as emphasis ON/OFF, a sub-code and so on. The data thus arranged are subjected to a so-called biphase mark modulation in which data '0' corresponds to one transition and data '1' corresponds to two transitions, as shown in Figure 6C. However, the SYNC portion is an exception, and is written with a particular pattern called the 'preamble'. In the preamble, the correspondent relationship between the transition and the data values is ignored, so that this portion has a high-level period longer than any other portion. Figure 1 shows a transmitter 1 such as a compact disc player, and a receiver 2 such as a digital/analogue (D/A) converter system. The transmitter 1 comprises an oscillator 3 for generating a master clock of a predetermined frequency, a data read-out circuit 4 for reading out data from a recording medium (not shown), for example a compact disc or the like, on the basis of the master clock, and an encoder 5 for encoding the data read out on the basis of the master clock in accordance with a DAI format signal. The receiver 2 comprises a detecting circuit 6 for detecting a synchronizing signal having a frequency, for example, double the frequency of the audio data sampling frequency fs from the above-mentioned DAI format signal, a PLL circuit 7 for generating a clock signal having a frequency, for example, 256 times the sampling frequency fs and phase-locked with the detected synchronizing signal, a decoder 8 for decoding the input signal on the basis of the clock signal, and a D/A converter 9 for converting the digital decoded signal to an analogue signal. The encoder 5 of the transmitter 1 supplies the receiver 2 with a DAI format signal Rx as shown in Figure 5A. The upper portion of Figure 5A shows in detail the waveform of the DAI format signal Rx, and the lower portion of Figure 5A typically shows the same DAI format signal Rx. The DAI format signal Rx is supplied to the detecting circuit 6. In the detecting circuit 6, a synchronizing signal 2FSR having one edge (a rising edge) per one SYNC as shown in Figure 5B is detected. The synchronizing signal 2FSR has the frequency double the sampling frequency fs, as described above. The synchronizing signal 2FSR from the detecting circuit 2 is supplied to a phase comparator circuit (not shown) of the PLL circuit 7, wherein it is phase-compared with a fed-back signal 2FSV (Figure 5F) from a frequency divider (not shown). Then, a phase comparison error signal is converted to a direct current voltage by a loop filter (not shown), and the oscillating frequency of an oscillator (not shown) is controlled on the basis of this direct current voltage, whereby a clock signal for decoding the DAI format signal Rx is derived at the output side of the PLL circuit 7, that is, at the output side of the oscillator. The clock signal thus derived from the PLL circuit 7 is supplied to the decoder 8 together with the DAI format signal Rx, wherein the DAI format signal Rx is decoded on the basis of the clock signal. Consequently, 16-bit serial digital data DATA, a clock BCK for shifting the same, and a signal LRCK for identifying the L-channel and the R-channel, as shown in Figure 5C, are derived at the output side of the decoder 8. These outputs are supplied to a series (parallel S/P) converting circuit (not shown), whereby parallel data PDATA having 16 bits per channel, as shown in Figure 5D, are derived at the rising edge of the clock LRCK, that is, at the end point of the R-channel at the output side of the S/P converting circuit. The parallel data PDATA are supplied to the D/A converter 9 together with the clock signal from the PLL circuit 7, and consequently an output current I OUT corresponding to the parallel data PDATA as shown in Figure 5E is taken out at the output side thereof as an analogue signal. In the case of a system as shown in Figure 1, however, the synchronizing signal is generated from the oscillator 3 of the transmitter 1 on the basis of the master clock as mentioned above, and the PLL circuit 7 of the receiver 2 generates a variety of clock signals on the basis of this synchronizing signal to operate in synchronism with the transmitter 1. One of the clock signals is supplied to the D/A converter 9 to be used as the timing for the D/A converter, so that if there occur minute variations or jitter in the clock signal, the sound quality is badly affected. In particular, in the system which generates the clocks from the DAI format signal Rx it is inevitable that jitter is mixed in the clock signal from the PLL circuit 7 of the receiver 2 in comparison with the master clock from the oscillator 3 of the transmitter 1. According to the present invention there is provided a digital transmission system comprising a transmitter and a receiver, wherein said transmitter comprises: data read-out means for reading out data from a recording medium on the basis of a first clock signal, and a first encoder means for encoding the data from the data read-out means in a digital audio interface format signal on the basis of said first clock signal; while said receiver comprises: clock extracting means for detecting a synchronizing signal contained in said digital audio interface format signal and generating a second clock signal of a predetermined frequency phase-locked with that synchronizing signal, decoding means for decoding data from said digital audio interface format signal on the basis of said second clock signal, and D/A converter means for digital-to-analogue converting the decoded data; characterized in that: said transmitter further comprises: a further clock extracting means for detecting a synchronizing signal contained in a further digital audio interface format signal from said receiver and generating said first clock signal of a predetermined frequency phase-locked with that synchronizing signal; and said receiver further comprises: oscillator means for generating a master clock, and a second encoding means for encoding said master clock to derive said further digital audio interface format signal, said D/A converter means converting said decoded data on the basis of said master clock. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a block diagram showing a previously proposed example; Figures 2 to 4 are block diagrams showing respective first, second and third embodiments of the present invention; Figure 5 comprises diagrams used for explaining the operation; and Figure 6 comprises diagrams used for explaining the DAI format. In the first embodiment shown in Figure 2, an oscillator 3 is provided in a receiver 12 in a manner that the master clock from the oscillator 3 is supplied to a D/A converter 9 as a clock signal Therefore, the clock signal is not supplied from a PLL circuit 7 to the D/A converter as shown in Figure 1. The master clock from the oscillator 3 is supplied to an encoder 15 used as a second encoding means, wherein a first DAI format signal is formed. The first DAI format signal does not include data, only the synchronizing signal having the frequency double the sampling frequency fs being inserted at a predetermined interval. A transmitter 11 is provided with a detecting circuit 13 and a PLL circuit 14 constituting a first clock extracting means, whereby the synchronizing signal contained in the first DAI format signal from the encoder 15 is detected by the detecting circuit 13. Then a clock signal having a predetermined frequency and phase-locked with the synchronizing signal is generated by the PLL circuit 14 and supplied to a data read-out circuit 4 and an encoder 5 forming a first encoding means. The encoder 5 encodes the data read out on the basis of the clock signal from the PLL circuit 14 in a second DAI format signal. The second DAI format signal is supplied to the detecting circuit 6, wherein the synchronizing signal is detected in the same manner as described above. A clock signal phase-locked with this synchronizing signal and of a predetermined frequency is generated by the PLL circuit 7, and is supplied to the decoder 8. The detecting circuit 6 and the PLL circuit 7 constitute the second clock extracting means in this case. In this embodiment, the master clock from the oscillator 3 is directly supplied to the D/A converter 9 so that the timing for D/A conversion does not contain any jitter, thereby improving the sound quality. Additionally, although the lock signal supplied to a decoder 8 is transmitted through the two DAIs, they are synchronized with the oscillator 3, so that the whole system operates substantially as a synchronized system. Figure 3 shows the second embodiment, in which a sample and hold circuit 16 is provided at the rear stage of the D/A converter 9. The remainder of the construction is the same as that of Figure 2. The sample and hold circuit 16 is supplied with a clock having substantially the same frequency as the sampling frequency fs generated at the timing of the master clock. This second embodiment can also achieve substantially the same effects as those of the first embodiment and, moreover, can remove noise which occurs in D/A conversion. Figure 4 shows the third embodiment, in which a digital filter 17 for oversampling is provided before the D/A converter 9. The remainder of the construction is the same as that of Figure 2. The digital filter 17 is supplied with a master clock having a frequency, for example, 384 times or 256 times the sampling frequency fs. The D/A converter 9 is supplied with a clock from the digital filter 17 or exclusively from the oscillator 3. This third embodiment can also achieve substantially the same effects as those of the first embodiment and, moreover, can shift harmonic noise which is caused in the D/A conversion to a high band, thereby making it possible to reduce the order of an analogue filter, not shown, arranged after the D/A converter 9, consequently to simplify the construction of the analogue filter, achieve improvement on the sound quality, and enhance the group delay characteristics.

Claims: A digital transmission system comprising a transmitter (11) and a receiver (12), wherein said transmitter (11) comprises: data read-out means (4) for reading out data from a recording medium on the basis of a first clock signal, and a first encoder means (5) for encoding the data from the data read-out means (4) in a digital audio interface format signal on the basis of said first clock signal; while said receiver (12) comprises: clock extracting means (6, 7) for detecting a synchronizing signal contained in said digital audio interface format signal and generating a second clock signal of a predetermined frequency phase-locked with that synchronizing signal, decoding means (8) for decoding data from said digital audio interface format signal on the basis of said second clock signal, and D/A converter means (9) for digital-to-analogue converting the decoded data; characterized in that: said transmitter (11) further comprises: a further clock extracting means (13, 14) for detecting a synchronizing signal contained in a further digital audio interface format signal from said receiver (12) and generating said first clock signal of a predetermined frequency phase-locked with that synchronizing signal; and said receiver (12) further comprises: oscillator means (3) for generating a master clock, and a second encoding means (15) for encoding said master clock to derive said further digital audio interface format signal, said D/A converter means (9) converting said decoded data on the basis of said master clock. A system according to claim 1 wherein a sample and hold circuit (16) is connected to the output side of said D/A converter means (9) and effects a sample and hold operation on the basis of said master clock. A system according to claim 1 wherein a digital filter (17) is connected to the input side of said D/A converter means (9) and effects a filtering operation by said master clock. A system according to claim 1, claim 2 and claim 3 wherein said first mentioned digital audio interface format signal transmits a synchronizing signal, digital audio data and control data as one frame. A system according to claim 4 wherein said digital audio signal is biphase mark modulated.

Inventors: INAYAMA MINORU SONY CORPORATIO, KANAI TAKASHI SONY CORPORATION, INAYAMA, MINORU SONY CORPORATION, KANAI, TAKASHI SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1987
Main classification: H04L7
IPC codes: H04L7, G11B20, H04B14