IMAGE PROCESSOR

Abstract: A system comprises a processor (1), a system bus (2), a random port bus (3), a serial port bus (22), a dual-port memory which consists of a random access block (5) containing a memory cell array (7) and a serial access block (6) containing a data register (8), interconnected by a data line (20), and a storage means (9). Smearing data stored in the storage means (9) are serially transferred to the data register (8) which stores one line of an image. The content of the data register is then internally transferred to the memory cell array (7) line by line so that the whole image is smeared.

Description: This invention relates to a picture processing apparatus in which a frame memory of a CRT display unit can be painted by any painting data such as luminance information and color discrimination information. In order to paint a frame buffer of a picture display unit uniformly with any data such as luminance data and color data, prescribed picture processing is required. Conventionally, in control for such picture processing, a single-access port or double-access port is used in order to connect the frame memory with a processor for control. If a single-port memory is used as a frame buffer, the operation for painting the frame buffer, namely the writing of data into the frame buffer, is performed from a single random port. If a dual-port memory is used as a frame buffer, as in e.g. EP 107010, a serial-access port is used to read data out of the memory cell array. However, when a data register for serial access of a dual port memory is equipped only with a data output function, the writing of input data, such as paint information, into the memory cell array is carried out from a random port. In a case where the single-port memory is used as the frame buffer, or in a case where the data register possesses solely an output function even if the dual-port memory is used as the frame buffer, the paint information from a processor must be written through a random port each time for every pixel when the frame buffer is painted with the predetermined information. Let T represent the time needed to write paint information in one specific row and column of the frame memory. In order to write paint information into an entire frame buffer composed of e.g. 256 x 256 pixels, the processor must access the frame buffer 256 x 256 times, so that a time equivalent to 256 x 256 x T is required in order to write all the paint information. As a result, painting is very slow and the processor is subjected to a very heavy burden required for paint. The present invention seeks to eliminate the foregoing problems of the conventional picture processing apparatus and its object is to provide a picture processing apparatus in which the burden on the processor can be lightened and paint information can be stored in the frame buffer at high speed. The present invention provides a picture processing apparatus having a picture memory comprising a dual-port memory connected to a processor via a serial port and random port, comprising a memory cell array which is randomly accessed by the processor via the random port and in which predetermined pixel information is stored, a data register, which has a serial input function, accessed via the serial port and adapted to transfer predetermined paint information to the memory cell array, and storage means accessed by the processor for storing paint information to be transferred to the data register, which internally transfers paint information stored therein to all rows of the memory cell array one row at a time. In a preferred embodiment of the present invention the dual-port memory is used as the frame buffer, paint information stored in the storage means is transferred serially to the data register of the dual-port memory, the paint information supplied to the data register is transferred internally to the memory cell array of the dual-port memory one row at a time, and the paint information is written into the frame buffer at high speed. Brief Description of the Drawings Fig. 1 is a block diagram illustrating an embodiment of a picture processing apparatus according to the invention; Fig. 2 is a view showing the system configuration of a dual-port memory in the same embodiment; Fig. 3 is a timing diagram of picture processing in the same embodiment; and Fig. 4 is a block diagram illustrating another embodiment of a picture processing apparatus according to the invention. Embodiments of the invention will now be described in detail with reference to the drawings. Fig. 1 is a block diagram illustrating an embodiment of a picture processing apparatus according to the invention, and Fig. 2 is a view showing the system configuration of a dual-port memory in the same embodiment. In Fig. 1, numeral 1 denotes a processor controlled in accordance with a control program stored in a ROM (not shown) or the like. A control signal from the processor 1 is delivered to a dual-port memory and to various other peripheral devices, not shown, via a system bus 2. Numeral 3 denotes a random port bus connecting the system bus 2 with a random-access port of a picture memory comprising a dual-port memory 4 constituting a frame buffer. The dual-port memory 4 comprises a random-access block 5 having a memory cell array 7, and a serial-access block 6 having a data register 8 in which one row of paint information of the memory cell array 7 is stored. The random-access block 5 is randomly accessed by the processor 1 via the system bus 2 and random port bus 3. The memory cell array 7 is constituted by a RAM capable of storing e.g. 256 x 256 pixels of data. The serial-access block 6 has its serial port connected to the processor 1 by a serial port bus 22 and is accessed serially by the processor. The data register 8 is constituted by a shift register which forms e.g. one row of data of memory cell array 7, i.e. one pixel of pixel data of eight bits, and which stores 256 pixels of data in a manner capable of serial input and output. The data register is connected to the memory cell array 7 via a data line 20 and is capable of input and output. Storage means 9 is constituted by e.g. an eight-bit register and stores predetermined paint information for painting the memory cell array 7 of dual-port memory 4 in one color. The paint information is e.g. display screen luminanace information or display screen color discrimination information. If the storage means is composed of an eight-bit register, then the luminance of 256 tones or 256 colors can be specified. The storage means is connected to the data register 8 of the dual-port memory 4 via a data line 21. The storage of paint information is completed with one access by the processor 1 via a control line 25. At this time, the eight-bit paint information is applied via a data bus 24. The data register 8 is constructed as set forth above. Accordingly, as for the paint information stored in the storage means 9, one row of the memory cell array 7 is stored in the data register 8 by 256 shifts performed by a microprogram control unit in bit slice manner. An internal transfer of paint information from the data register 8 to the memory serial array 7 is performed after one row of paint information is stored in the data register 8. The dual-port memory 4 of this embodiment outputs data stored in the memory cell array 7, e.g. picture information, to the system bus 2 in serial form via the data register 8 and an output line 23. The data can be displayed in the form of a picture on a CRT display. The construction of the dual-port memory 4 is shown in detail in Fig. 2. Addressing of the random-access block 5 of dual-port memory 4 is performed by well-known address multiplexing. More specifically, the processor 1 transmits a digit select strobe signal CAS , a word select strobe signal RAS , a write-enable signal WE, and an address signal ADR to the ransom-access block 5. The address signal ADR is stored in a word address buffer 10 and a digit address buffer 11. The buffers 10, 11 are divided between the word address signal RADR and digit address signal CADR, which are staggered with respect to each other in terms of timing, under the control of the word select strobe signal RAS and digit select strobe signal CAS. The word address signal RADR outputted by the buffer 10 is applied to a word select decoder 12, where the signal is decoded to designate a specific row of the memory cell array 7. Meanwhile, the digit address signal CADR outputted by the buffer 11 is applied to the digit select decoder 13, where the signal is decoded to designate a specific column of the memory cell array 7. Thus, a specific row and column can be designated by address signal ADR, word select strobe signal RAS and digit select strobe signal CAS from processor 1. The write-enable signal WE from the processor 1 is applied to the memory cell array 7. When the signal WE is "L", a write-enable state is established; when WE is "H", a read-enable state is established. Accordingly, the writing of one row of data into the memory cell array 7, namely the internal transfer from the data register 8, is performed by specifying the row of the memory cell array 7 into which the data are to be written and setting the write-enable signal WE to "L" based on the address signal ADR and word select strobe signal RAS. As for the data to be written at this time, namely the identical paint information, one row of the memory cell array 7 has already been written in the data register 8. When a data transfer signal DT assumes the ""L level, one row of paint information stored in the data register 8 is fetched one pixel at a time in serial fashion and the information is written serially into predetermined column positions of a predetermined row of the memory cell array 17 via the data line 20. Accordingly, the one row of identical paint information stored in the data register 8 by the 256 shift operations performed by the microprogram control unit is internally transferred in its entirety to a predetermined row of the memory cell array 7 serially one pixel at a time in response to a single generation of the data transfer signal DT by the processor 1, namely by a single access from the processor 1. The identical paint information can be stored over one predetermined row of the memory cell array 7. In order to perform the internal transfer to the memory cell array 7 reliably, the write-enable signal WE must be "L" at the same time that data transfer signal DT is "L". It will readily be understood from the foregoing that in order for the identical paint information to be stored over all rows of the memory cell array 7, it will suffice if the processor 1 transmits the data transfer signal DT 256 times at a predetermined timing, so that accessing is performed only 256 times. Further, since the transfer of one row of data to the memory cell array 7 is a transfer performed entirely internally of the dual-port memory 4, the transfer can be performed in a very short period of time in comparison with the conventional apparatus in which the processor 1 is required to perform an access one pixel at a time. Painting in accordance with the invention with regard to a picture memory will now be described with reference to Fig. 3. Before data are written into the memory cell array 7, the processor 1 transmits a storage signal STK to the storage means 9 via the control line 25 at the timing shown in Fig. 3(e) in order to store eight bits of paint information in the storage means 9. When the storage signal STK is "L", eight-bit paint information is stored in its entirety in the storage means 9 via the data bus 2 and data bus 24. Next, in order to store 256 pixels of paint information in the data register 8 of dual-port memory 4, the paint information just stored in the storage means 9 is shifted serially 256 times into the data register 8 (256 pixels of data are stored). The shift-in operation is performed at high speed by the microprogram control unit in bit slice manner, as mentioned above. As for the timing, the shift-in must be performed after the storage signal STK is outputted but before the data transfer signal DT shown in Fig. 3(d) is outputted, though this is not shown in Fig. 3. Next, in order to internally transfer the 256 pixels of identical write information stored in the data register 8 to the predetermined row of the memory cell array 7 of dual-port memory 4 (i.e. in order to accommodate the 256 pixels of information), first the write-enable signal WE applied to the memory cell array 7 is set to "L", as shown in Figs. 3(c), (d), and at the same time, the data transfer signal DT applied to the data register 8 is set to "L". In order to paint the first row of the memory cell array 7 at the beginning of the operation, the processor 1 sends the address signal ADR for the first row via the system bus 2 and random port bus 3. The address signal ADR is temporarily stored in the word address buffer 10 and, as shown in Figs. 3(a), (b), is transmitted to the word select decoder 12 as the row address signal RADR at the negative-going transition of the word select strope signal RAS. At this time the address value of the row address signal RADR is r₁, which designates the first row. In response to these control signals WE, DT , r₁, the 256 pixels of identical paint information in data register 8 are internally transferred to the first row of the memory cell array 7 via the data line 20. During the internal transfer of the 256 pixels of paint information, the processor 1 need not access the dual-port memory 4 each time. That is, the processor 1 need access the dual-port memory 4 only once in order to store one row of paint information in the memory cell array 7. Since it is unnecessary to perform an access 256 times from the random port bus 3, as in the prior art, processing speed can be markedly improved. In order to store identical paint information in the second row after identical paint information is stored in the first row, the write-enable signal WE and data transfer signal DT are set to "L" simultaneously, as shown in Figs. 3(c), (d), just as in storing the first row, and the row address signal RADR is set to an address value r₂ for the second row. As a result, 256 pixels of identical paint information in data register 8 are internally transferred to the second row of the memory cell array 7 via the data line 20. Thereafter, and in similar fashion, all identical paint information can be stored in the memory cell array 7 up to the 256-th row. Fig. 4 is a block diagram illustrating a second embodiment of a picture processing apparatus according to the invention. Only those points that differ from the first embodiment will be described. A first storage means 91 is composed of e.g. an eight-bit register. A second storage means 92 is constituted by e.g. a shift register which forms one row of data of memory cell array 7, i.e. one pixel of pixel data of eight bits, and which stores 256 pixels of data in a manner capable of serial input and output. The second storage means stores predetermined paint information for painting the memory cell array 7 of the dual-port memory 4 in row units with a predetermined gradation. The paint information is e.g. display screen luminanace information or display screen color discrimination information. If the storage means is composed of an eight-bit register, then the luminance of 256 tones or 256 colors can be specified. The second storage means 92 is connected to the data register 8 of the dual-port memory 4 in bit-to-bit correspondence by a data line 21' capable of a parallel/serial transfer. The storage of paint information is completed with one access by the processor 1 via a control line 251. The eight-bit paint information is stored beforehand in the second storage means 92 from the first storage means 91 through 256 shift operations performed by the microprogram control unit via the data bus 24. The data register 8 has the same construction as in the first embodiment. As for the paint information stored in the second storage means 92, one row of the memory cell array 7 is transferred collectively to the data register 8. The internal transfer of paint information from the data register 8 to the memory cell array 7 is performed after one row of paint information is stored in the data register 8. Completely identical paint information can be stored up to the 256-th row of the memory cell array 7 in a similar manner. Accordingly, when 256 rows of the paint information are stored, the processor 1 first accesses the first storage means 91 256 times via the control line 252. After one row of paint information is stored in the second storage means 92, it will suffice to access the second storage means 92, the data register 8 and the memory cell array 7 for 256 rows, i.e. 256 times. Thus, it is no longer necessary to perform access 256 x 256 times, as in the prior-art apparatus. Thus, in accordance with the picture processing apparatus as set forth above, it is possible to greatly reduce the number of times the processor accesses the dual-port memory in order to store entirely identical paint information or paint information with a predetermined gradation in row units in the memory cell array of the dual-port memory. This makes it possible to lighten the burden on the processor and to greatly shorten the time required for the paint information to be stored in the memory cell array. Accordingly, the invention is well-suited for use in picture processing in a display unit, especially a CRT display unit connected to a numerical controller controlling a machine tool or the like.

Claims: A picture processing apparatus having a picture memory comprising a dual-port memory (4) connected to a processor (1) via a serial port (22) and random port (3), comprising: a memory cell array (7) which is randomly accessed by said processor (1) via said random port (3) and in which predetermined pixel information is stored; a data register (8), which has a serial input function, accessed via said serial port (22) and adapted to transfer predetermined paint information to said memory cell array (7); characterised by: a storage means (9) accessed by said processor (1) for storing paint information to be transferred to said data register (8); and by said data register (8) internally transferring paint information stored therein to all rows of said memory cell array (7) one row at a time. A picture processing apparatus according to claim 1, characterized in that said storage means (9) comprises a register and paint information stored in said register is stored by a single access from said processor (1). A picture processing apparatus according to claim 1 or 2, characterized in that said storage means (9) comprises first storage means (91) accessed from said processor (1) in single pixel units of said paint information, and second storage means (92) connected to said data register (8) in bit-to-bit correspondence so as to be capable of a parallel/serial transfer. A picture processing apparatus according to claim 1 or 2, characterized in that transfer of paint information from said storage means (9) to the data register (8) is performed serially by a microprogram control unit in bit slice manner. A picture processing apparatus according to any one of claims 1 through 4, characterized in that said paint information is picture lumininance information. A picture processing apparatus according to any one of claims 1 through 4, characterized in that said paint information is picture color discrimination information.

Inventors: KURAKAKE, MITSUO, MURAOKA, YUTAKA, OTSUKA, SHOICHI
Applicants: FANUC LTD.
Application year: 1987
Main classification: G06F15
IPC codes: G09G5, G06T11, G11C11, G06F12