READ ONLY MEMORY DEVICE

Abstract: A ROM device including a plurality of memory cells (Q oo ,...,Q n-1,m-1 ) each storing one of three states, a cell voltage generating circuit (41) for providing a cell voltage corresponding to the state stored in a selected one of the memory cells, and a reference cell (2) for providing a reference voltage which is substantially the same as the cell voltage provided by a memory cell storing an intermediate state of the three states, also includes a comparator circuit (5) for generating a logical output signal based on the result of a comparison between the cell voltage and the reference voltage.

Description: The present invention relates to a read only memory (ROM). To increase the degree of integration of an integrated circuit, such as ROM, attention has been paid to a memory cell which is called a multi-value level memory cell. (See, for example, USP 4449203, USP 4503518, and IEEE Journal of Solid State Circuits, Vol. SC-16, No. 5, Pages 522-529). The storing of data into such a memory cell having multi-value levels is generally carried out by changing a mutual conductance (transconductance) gm of the memory cell transistor. For example, gm of a memory cell transistor can be selected from three kinds of gm. i.e., gm(1), gm(2), and gm(3), which correspond to three kinds of states: state-1, state-2, and state-3, respectively. Previously, the discrimination of these three kinds of gm has been carried out by providing a first reference transistor having a gm which is at an intermediate value between state-1 and state-2, and a second reference transistor having a gm which is at an intermediate value between state-2 and state-3, and comparing the output from the reference transistors with the output from the memory cells. In this case, problems arise in that it is difficult to further enhance the precision in manufacturing of a reference transistor, and the circuit construction of the ROM device is relatively complicated. Accordingly, the degree of integration of the ROM device cannot be easily increased. Accordingly, it is desirable to provide an improved ROM in which the number of memory cells and reference transistors are reduced, the circuit construction of the ROM device is simplified, and the degree of integration of the ROM device is increased. It is also desirable to carry out a correct reading of information stored in the memory cells in such a ROM device. According to the present invention, there is provided a read only memory device comprising:- a plurality of memory cells each storing one of three states; a cell level voltage generating circuit connected to the memory cells for providing a cell voltage corresponding to the state stored in a selected one of said memory cells; a reference cell for providing a reference voltage which is substantially the same as the cell voltage provided by said cell level voltage generating circuit for a memory cell storing the intermediate state of the three states; and a comparator circuit for generating a logical output signal based on the result of a comparison between the cell voltage and the reference voltage, said comparator circuit comprising:- a first load and a second load each connected to a voltage source; a first switching transistor connected between said first load and said cell level voltage generating circuit and controlled by said reference voltage; and a second switching transistor connected between said second load and the reference voltage and controlled by the cell voltage. Reference will now be made, by way of example, to the accompanying drawings, in which:- Fig. 1 shows an arrangement of a field effect transistor used for a read only memory embodying the present invention; Fig. 2 shows the characteristic of the field effect transistor as a function of the gate width; Fig. 3 is a diagram of the arrangement of a fundamental structure of a read only memory embodying the present invention; Fig. 4 illustrates the relationships of the potentials of nodes with respect to the states of the memory cell transistor; Fig. 5 is a diagram of a read only memory embodying the present invention; Fig. 6 shows an example of the structure of the cell level voltage generating circuit; and Fig. 7 shows an example of the structure of a decoder used in a read only memory embodying the present invention. Before describing the preferred embodiments of the present invention, a pattern of the integrated circuit used for a ROM embodying the present invention will be described with reference to Fig. 1, and the characteristic concerning the effective width of a gate of a memory cell for the ROM will be described with reference to Fig. 2. As shown in Fig. 1, the pattern of an integrated circuit of the memory cells comprises diffusion layers in a semiconductor substrate, bit lines of, for example, aluminum, and word lines of, for example, polycrystalline silicon. A field effect transistor is formed at an overlapping portion of the diffusion layer and the word line, and a gate is defined by the area of the intersection between the diffusion layer and the word line. The effective width W of the gate is the length W of the gate along the longitudinal direction of the word line. The relationship between the effective width W of the gate and the voltage level V(CELL) is illustrated in Fig. 2. In correspondence with effective widths 0, a, and b of the gate, three states: STATE-1, STATE-2, and STATE-3 corresponding to the three values of gm: gm(1), gm(2), gm(3), respectively, are defined. A higher voltage level V H is realized by STATE-1 with gm(1), an intermediate voltage level V R is realized by STATE-2 with gm(2), and a lower voltage level V L is realized by STATE-3 with gm(3). In connection with Fig. 2, it may be considered that reference voltages V(REF1) and V(REF2) are pre-selected, and by using these reference voltages, the detection of STATE-1, STATE-2, and STATE-3 is carried out. However, in such a case, a problem arises in that reference cell transistors are needed for producing the reference voltages V(REF1) and V(REF2). In the ROM according to the present invention, the need for such reference cell transistors is obviated. The basic structure of the circuit for a ROM with memory cells having three value levels, embodying the present invention, is illustrated in Fig. 3. In the circuit shown in Fig. 3, there are provided a memory cell transistor(Q), a reference transistor (Q R ), a cell level voltage generator circuit 41, a reference voltage level generator circuit 42, a comparator circuit 5, and a decoding circuit 6. The gm of the memory cell transistor Q is one of gm(1), gm(2) and gm(3). The gm of the reference transistor Q R is gm(2). The cell level voltage generator circuit 41 converts the output of the memory cell transistor 1 into the voltage V(CELL), and the reference voltage level generator circuit 42 converts the output of the reference transistor 2 into the reference voltage V R . The voltages V(CELL) and V R are supplied to a comparator circuit 5. In the comparator circuit 5, a switching transistor Q₃ is connected between a load transistor Q₁ and the cell level voltage generator circuit 41, and a switching transistor Q₄ is connected between a load transistor Q₂ and the reference voltage level generator circuit 42. The transistors Q₁ and Q₂ are p-channel type, but drain-gate connected n-channel enhancement type transistors can be used as transistors Q₁ and Q₂. Further, source-gate connected n-channel depletion type transistors can be used as the transistors Q₁ and Q₂. The switching transistors Q₃ and Q₄ are n-channel type transistors each having a threshold voltage of, for example, 0.5 volt. The switching transistor Q₃ is controlled by the V R delivered from the reference voltage level generator circuit 42, and the switching transistor Q₄ is controlled by the V(CELL) delivered from the cell level voltage generator circuit 41. The state of the memory cell transistor Q, i.e., the gm of the memory cell transistor Q, is discriminated from the logic relationships of the potentials of nodes N₁ and N₂ of the switching transistors Q₃ and Q₄. This logical relationship is shown in Fig. 4. In STATE-1, the potentials of N₃ and N₄ are V H and V R , respectively, where V H is higher than V R , the states of Q₃ and Q₄ are OFF and ON, respectively, and the potentials of N₁ and N₂ are HIGH and LOW, respectively, where HIGH is V CC and LOW is approximately V R . In STATE-2, the potentials of N₃ and N₄ are both V R , the states of Q₃ and Q₄ are both OFF, and the potentials of N₁ and N₂ are both HIGH, where HIGH is V CC . In STATE-3, the potentials of N₃ and N₄ are V L and V R , respectively, where V L is lower than V R , the states of Q₃ and Q₄ are ON and OFF, respectively, and the potentials of N₁ and N₂ are LOW and HIGH, respectively, where LOW is approximately V L and HIGH is V CC . According to the logical relationship shown in Fig. 4, the discrimination between STATE-1, STATE-2, and STATE-3 can be based on the logical relationship between the potentials of the nodes N₁ and N₂. Further, based on the extended logical relationship between the potentials of the nodes N₁, N₂, N₃, and N₄, a more reliable discrimination between STATE-1, STATE-2, and STATE-3 can be obtained. A ROM with memory cells each having three value levels embodying the present invention is shown in Fig.5. The ROM of Fig. 5 includes a memory cell array 1 having memory cells Q₀₀, Q₀₁, ... Q 0,m-1 , ...Q n-1,m-1 , bit lines BL₀, BL₁, ...BL m-1 , word lines WL₀, WL₁, ... WL n-1 , a reference transistor 2, a row address buffer 31, a row address decoder 32, a column address buffer 33, a column address decoder 34, a cell level voltage generator circuit 41, a reference voltage level generator circuit 42, a comparator circuit (sense amplifier circuit) 5, and a decoding circuit 6. The memory cell transistor (Q) in the circuit of Fig. 3 represents one of the memory cell transistors Q₀₀, Q₀₁, ...Q 0,m-1 , ... Q n-1,m-1 in Fig. 5, and the reference transistor (Q R ) in the circuit of Fig. 3 represents the reference transistor 2 in Fig. 5. A selection from the word lines WL₀, WL₁, ... WL n-1 is carried out by the row address decoder 32, which receives the row address signal from the row address buffer 31, and a selection from the bit lines BL₀, BL₁, ...BL m-1 is carried out by the column address decoder 34, which receives the column address signal from the column address buffer 33. The n-channel enhancement field effect type memory cell transistors Q₀₀, Q₀₁, ... Q 0,m-1 , ... Q n-1,m-1 are arranged at intersections between the bit lines BL₀, BL₁, ... BL m-1 and the word lines WL₀, WL₁, ... WL n-1 . Each of the memory cell transistors has one of three gm values: gm(1), gm(2), and gm(3). The designation of one of the three gm values, i.e., the storing of data into the memory cell transistor, is carried out by selecting the value of the effective width W of the memory cell transistor. This selection of the value of the effective width W can be made, for example, by changing the amount of doping of the impurities, such as boron, arsenic, phosphor, and the like, directly underneath the gate of the memory cell transistor. As an example, if the word line WL₀ is selected by the row address decoder 32 and the bit line BL₀ is selected by the column address decoder 34, the memory cell transistor Q₀₀ is selected, and accordingly, a current flows via the cell level voltage generator circuit 41 through the memory cell transistor Q₀₀. Accordingly, the potential of the bit line BL₀, which corresponds to the gm value of the memory cell transistor Q₀₀, is supplied as a voltage V(CELL) to the comparator 5. The gm of the reference transistor Q R is adjusted to the value gm(2), and the voltage V R delivered from the reference voltage level generator circuit 42 connected to the reference transistor Q R is supplied to the comparator circuit 5. The output V(CELL) of the cell level voltage generator circuit 41 and the output V R of the reference voltage level generator circuit 42 are also supplied to the decoding circuit 6. The output signals of the comparator circuit 5 are supplied to the decoding circuit 6. In the decoding circuit 6, a discrimination between STATE-1, STATE-2, and STATE-3 is carried out in accordance with the voltage V(CELL) anv V R , and based on this discrimination, three output signals X₀, X₁, and X₂ are delivered. The output signals "X₀ = 1, X₁ = 0, X₂ = 0" represent STATE-1, the output signals 1 "X₀ = 0, X₁ = 1, X₂ = 0" represent STATE-2, and the output signals "X₀ = 0, X₁ = 0, X₂ = 1" represent STATE-3. An example of the structure of the cell level voltage generator circuit 41 in Fig. 5 is shown in Fig. 6, and an example of the structure of the decoding circuit 6 in Fig. 5 is shown in Fig. 7. As shown in Fig. 6, the cell level voltage generator circuit 41 includes a memory cell transistor Q, a column gate transistor Q₆₁, and a level converting circuit constituted by transistors Q₆₂ to Q₆₆. As shown in Fig. 7, the decoding circuit 6 includes a differential amplifier 61, inverters 62, 63 and 64, a NOR gate 69, inverters 70 and 71, a differential amplifier 65, and inverters 66, 67 and 68. The differential amplifier 61 receives the voltage of node N2 as the first input and the voltage of node N₃, which is V(CELL), as the second input. The differential amplifier 65 receives the voltage of node N₁ as the first input and the voltage of node N₄, which is V R , as the second input. The differential amplifier 61, and inverters 62, 63 and 64 are connected in series to produce an output signal X₀. The NOR gate 69 receives the outputs of the inverters 62 and 66, and the NOR gate 69 and the inverters 70 and 71 are connected in series to produce an output signal X₁. The differential amplifier 65, and the inverters 66, 67 and 68 are connected in series to produce an output signal X₂. Where the memory cell transistor is in STATE-1, the potential of node N₃ is HIGH, i.e., V H , the potential of node N₂ is LOW, and thus the potential of the output of the differential amplifier 61 is LOW. Accordingly, the potential of the output of the inverter 64 is HIGH. Therefore, the output X₀ is "1". In this case, the potential of node N₁ is HIGH with respect to the voltage V R , which is the output voltage of the reference voltage level generator circuit 42. Therefore, the potential of the output of the differential amplifier 65 is HIGH, and accordingly, the potential of the inverter 68 is LOW. Therefore, the output X₂ is "0". In this case, the potential of the output of the NOR gate 69 is LOW, and thus the potential of the output of the ivnerter 71 is LOW. Therefore, the output X₁ is "0". In consequence, the outputs "X₀, X₁, X₂" are "1, 0, 0", respectively. Where the memory cell transistor is in STATE-2, the potential of node N₃ is V R , the potential of node N₂ is HIGH, i.e., V CC and thus the potential of the output of the differential amplifier 61 is HIGH. Accordingly, the potential of the output of the inverter 64 is LOW. Therefore, the output X₀ is "0". In this case, the potential of the output of the differential amplifier 65 is HIGH, and thus the potential of the output of the inverter 68 is LOW. Therefore, the output X₂ is "0". Accordingly, the potentials of the outputs of the inverters 62 and 66 are both "LOW", and thus the potential of the output of the NOR gate 69 is HIGH. Accordingly, the potential of the inverter 71 is HIGH, and therefore, the potential of the output X₁ of the inverter 71 is "1". In consequence, the outputs "X₀, X₁, X₂" are "0, 1, 0", respectively. Where the memory cell transistor is in STATE-3, the potential of node N₃ is V L , as a LOW level, the potential of node N₂ is V CC , as a HIGH level, and thus the potential of the output of the differential amplifier 61 is HIGH. Accordingly, the potential of the output of the inverter 64 is LOW, and therefore, the output X₀ is "0". In this case, the potential of the node N₁ is LOW with respect to the potential V R of the node N₄, and thus the potential of the differential amplifier 65 is LOW, and accordingly, the potential of the output of the inverter 68 is HIGH. Therefore, the output X₂ is "1". In this case, the potential of the output of the inverter 66 is HIGH, and thus the potential of the output of the NOR gate 69 is LOW. Therefore, the output X₁ is "0". In consequence, the outputs "X₀, X₁, X₂" are "0, 0, 1", respectively. Instead of the decoding circuit shown in Fig. 7, it is possible to construct a decoding circuit by a circuit for carrying out a logical combination of the potentials of only the nodes N₁ and N₂.

Claims: A read only memory device comprising:- a plurality of memory cells (Q₀₀, Q₀₁, ...) each storing one of three states; a cell level voltage generating circuit (41) connected to the memory cells for providing a cell voltage (V(cell)) corresponding to the state stored in a selected one of said memory cells; a reference cell (Q R ) for providing a reference voltage (VR) which is substantially the same as the cell voltage provided by said cell level voltage generating circuit (41) for a memory cell storing the intermediate state of the three states; and a comparator circuit (5) for generating a logical output signal based on the result of a comparison between the cell voltage and the reference voltage, said comparator circuit (5) comprising:- a first load (Q1) and a second load (Q2) each connected to a voltage source (V cc ); a first switching transistor (Q3) connected between said first load (Q1) and said cell level voltage generating circuit (41) and controlled by said reference voltage (VR); and a second switching transistor (Q4) connected between said second load and the reference voltage (VR) and controlled by the cell voltage (V(cell)). A memory device according to claim 1, wherein said memory cells comprise memory cell transistors, and said three states of said memory cell transistors are realized by changing the effective gate width of said memory cell transistors. A memory device according to claim 1, further comprising a decoding circuit (6) connected to said cell level voltage generator circuit (41), said reference voltage (VR) and said comparator circuit (5) for producing decoder output signals (X0, X1, X2) corresponding to the three states stored in said memory cells. A memory device according to claim 3, wherein said decoding circuit is constituted by a combination of differential amplifiers, inverters, and a NOR gate. A memory device according to any preceding claim, wherein said first and second loads (Q1, Q2) are constituted by transistors.

Inventors: HIRAO, HIROSHI, SUZUKI, YASUAKI, SUZUKI, YASUO
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C11
IPC codes: G11C11, G11C16