Ceramic wiring substrate and method of forming it

Abstract: A ceramic wiring substrate (11) has at least one layer of a signal line pattern (12), a ground electrode pattern layer (13), and a cavity (16) formed by a region which covers part of or completely the signal line pattern inside ceramic between the signal line pattern and the ground electrode pattern.

Description: The present invention relates to a ceramic wiring substrate. Recently, a multilayer wiring substrate has been put into practical use for high performance of a computer. In the multilayer wiring substrate, wiring is multilayered, wiring lengths between LSI elements such as a logic gate or a memory mounted to the substrate and between the LSI elements and a power source and a ground electrode are shortened to reduce delay time of transfer of a signal, thereby obtaining a high speed operation of the computer. In the multilayer substrate, the lower the permittivity of a substrate material, the better. The reason for this is as follows. In order to constitute a memory module which packages many memory chips, many memory chips must be connected in parallel, so that signal lines are elongated. As a result, a capacitance relative to ground of a signal line formed between the signal line and a ground electrode is increased. As a result, a load capacitance of a drive element for driving a memory element is increased, and a rise time of a signal is increased, thereby adversely affecting an access time. For this reason, a portion which forms a signal line of the substrate preferably has a low permittivity, and efforts have been made to obtain a low permittivity of the substrate material. However, to obtain a low permittivity is not easy because the permittivity of the substrate conflicts with mechanical characteristics such as strength and thermal characteristics such as a sintering temperature or a thermal expansion coefficient. A method of obtaining a multilayer substrate with a low permittivity by a low sintering temperature is disclosed in an article entitled "Low Firing Temperature Multilayer Glass-Ceramic Substrate" which is announced in IEEE TRANSACTION ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. CHMT-6, NO.4 DECEMBER 1983 pp. 382-388. According to this method, a multilayer wiring substrate is realized using glass-ceramic which can be sintered at a low temperature of 900°C and has a permittivity of 7.5. However, at this value the permittivity is insufficiently reduced. In IBM Technical Disclosure Bulletin Vol.17, No.3, (August 1974) pp 862-863 there is described a multilayer ceramic wiring substrate for use with high speed integrated circuits in which substrate a cavity is formed parallel to a signal line pattern with the objective of reducing inter-wiring capacitance. The cavity is directly adjacent to the signal line pattern. It is an object of the present invention to provide a multilayer wiring substrate capable of realising a low permittivity without adversely affecting the mechanical and thermal characteristics of the substrate. A ceramic wiring substrate according to the present invention is specified by Claim 1. A method of forming such a substrate is given by Claim 2 and an alternative ceramic wiring substrate according to the invention is given by Claim 6. The invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a partially cut away perspective view of a ceramic wiring substrate; Figure 2 is a sectional view of a ceramic wiring substrate having cavities formed in a plurality of layers; Figures 3(a) to 3(c) are perspective views for explaining a method of manufacturing the ceramic wiring substrate of the present invention; Figures 4(a) to 4(e) are sectional views for explaining another method of manufacturing the ceramic wiring substrate of the present invention; and Figure 5 is a sectional view of another embodiment of the ceramic wiring substrate of the present invention. Figure 1 is a partially cut away perspective view of a ceramic wiring substrate 11 of the present invention, in which a signal wiring pattern 12 and a ground electrode (may be a power source electrode) 13 are formed inside a ceramic substrate 11 and connected to a chip connecting pad 15 on the upper surface of the substrate 11 by a via hole 14. A cavity 16 is formed between the signal wiring pattern 12 and the ground electrode 13 and is parallel to the signal wiring pattern 12. By the cavity 16 formed between the signal wiring pattern 12 and the ground electrode 13, a capacitance therebetween can be reduced. If the substrate 11 is used in air, it can be assumed that the interior of the cavity 16 is substantially the air. Permittivity of air is substantially 1, and this means that a layer of a low permittivity is formed between the signal wiring pattern 12 and the ground electrode 13. Assuming that a capacitance between the signal wiring pattern 12 and the ground electrode 13 is C₀, the capacitance C₀ is a series circuit of a capacitance C₁ of the cavity 16 and a capacitance C₂ of a ceramic portion. Assuming that a permittivity and a thickness of the cavity 16 are ε r1 and t₁, respectively, that a permittivity and a thickness of the ceramic portion are ε r2 and t₂, respectively, and that the opposing area of the cavity and the ceramic portion A, C₀ = ε₀·A/(t₁/ε r1 + t₂/ε r2 ) (1) Substitution of 1 in ε r1 of the cavity 16 yields, C₀ = ε₀·A/(t₁ + t₂/ε r2 ) (2) Therefore, it is found that when the thickness of the cavity 16 is increased with respect to that of an insulator portion between the signal wiring pattern 12 and the ground electrode 13, the capacitance C₀ can be reduced. When the effective permittivity of the ceramic wiring substrate obtained in the manner as described above is calculated from a capacitance assuming that there is no cavity, it is equivalent to 50 to 80% reduction in permittivity of the substrate material. On the contrary, forming the cavity 16 in the substrate 11 weakens the strength of the substrate 11. However, since the cavity 16 is formed immediately below the signal wiring pattern 12 and need only be slightly wider than a width of the signal wiring pattern 12, a percentage of the cavity 16 with respect to the substrate 11 is small, and the flexural strength of the substrate 11 is degraded only by 2 to 3% (which varies in accordance with an area ratio of the cavity pattern and the ceramic portion). Thus, practically no problem is posed. The ceramic wiring substrate 1 described above is manufactured by the following steps. First, a mixture powder is prepared such that the amounts of a crystalline glass powder and an aluminum oxide are selected in the ranges of 40 to 60 wt.% and 60 to 40 wt.%, respectively, to obtain a total amount of 100%. The powder is mixed with a binder, organic solvent, and plasticizer to make a slurry, and a 20 to 300 µm-thick green sheet is formed on a polyester film by a slip casting film formation method such as a doctor blade method and is then removed. Then, the signal wiring pattern 12 and a pattern of the ground electrode 13 are formed on a plurality of such green sheets using a screen printer. A pattern of the cavity 16 is printed and formed in the same manner using a paste such as carbon which is decomposed and scattered before the sintering temperature of the above ceramic green sheet is reached. The pattern of the cavity 16 may be formed by pressing a film patterned by exposing and developing a photosensitive resin. Green sheets to each of which the signal wiring pattern 12, the pattern of the ground electrode 13, and the pattern of the cavity 16 are formed are stacked, heated at a temperature of about 100°C, and then pressed at a pressure of about 250kg/cm² to obtain a stacking body. Then, after the stacking body is cut in a predetermined size as needed, organic materials present in the pattern of the cavity 16 or the ceramic green sheet are gradually heated in an oxidizing atmosphere in a binder separation step to be decomposed and removed. Normally, these organic materials are completely decomposed and oxidized at 500 to 600°C. However, if a temperature is rapidly increased to the decomposition temperature, the stacking body is damaged. Therefore, the temperature is increased at a rate of 25°C/hour or less to maintain a temperature of 500 to 600°C for a long period of time so that the organic materials can be completely removed. Since no organic material remains in the stacking body after the binder separation step, the cavity pattern portion is formed as the cavity 16 in the stacking body. Thereafter, the resultant material is sintered at 800 to 1,000°C to obtain the ceramic wiring substrate 11 having the cavity between the signal wiring pattern 12 and the ground electrode 13. In the above method of printing a carbon paste to form the cavity pattern, a thickness of the paste obtained by one printing is 10 to 15 µm. Therefore, only a cavity having a thickness of about 10 µm can be obtained when the paste is printed onto a single layer sheet, so that formation of the cavity 16 results in little effect on reducing the capacitance between the signal wiring pattern 12 and the ground electrode 13. For this reason, the cavity patterns are formed in a plurality of layers. Fig. 2 is a sectional view showing this case. In Fig. 2, since cavities 21 formed in a plurality of layers are present between a signal circuit electrode 22 and a ground electrode 23, a ratio of the thickness of the cavity with respect to the thickness of a dielectric between the signal circuit electrode 22 and the ground electrode 23 can be increased even if the thickness of the cavity in a single layer is small. Therefore, similar to the case of increasing the thickness of the cavity, a capacitance between the signal circuit electrode 22 and the ground electrode 23 can be reduced. For example, assuming that a pattern area of the signal circuit electrode 22 is 25mm², that an interval constituted by five layers of green sheets,between the signal circuit 22 and the ground electrode 23 is 410 µm, and that a permittivity of an insulator is ε r = 8, values shown in Table 1 are obtained by calculating C₀ from a relationship between thicknesses of the insulator and the cavity and calculating an effective permittivity from C₀. In addition, Table 2 shows an effect when the permittivity of the insulating portion of the substrate is 15. As shown in Tables 1 and 2, when a cavity is formed in the insulator between the signal circuit and the ground electrode, the capacitance therebetween is reduced, and hence the effective permittivity obtained from the capacitance is reduced. Furthermore, it is found that the higher the permittivity of the insulator portion is, the greater the permittivity reduction effect by the cavity is. Formation of a cavity having a thickness of 50 to 100 µm provides a permittivity reduction of 50 to 80%. Figs. 3(a) to 3(c) show another method of forming a cavity. Hole 33' is opened by a punching method at a portion, immediately below a portion where signal patterns 34 of a signal circuit pattern layer 31 are concentrated, in a sheet 33 for forming a cavity between the signal circuit pattern 31 and a ground electrode 32. The sheet 33 with the hole 33' is adhered to a sheet 35 without a hole to obtain a composite sheet 36 having a groove 36' in one layer. Then, using a screen printer, a carbon paste 37 is buried in the groove 36' of the composite sheet 36 to obtain a composite sheet 38 in which the carbon paste is buried in one layer. Then, a signal circuit pattern 34, the composite sheet 38, and a ground electrode 32 are stacked and then subjected to a binder separation sintering step to obtain a ceramic wiring substrate with a cavity having a thickness of one layer. Figs. 4(a) to 4(e) show a method of forming a cavity pattern using a photosensitive resin. Photosensitive resin 42 is coated uniformly on a carrier film 41 such as a polyester to a predetermined thickness (Fig. 4(a)). Then, a photo mask 44 to which a predetermined pattern 43 is formed is brought into contact with the photosensitive resin sheet, exposed by radiation of light 45, and then subjected to a development treatment to obtain a predetermined cavity pattern 46 (Figs. 4(b) and 4(c)). The cavity pattern 46 thus obtained is pressed against a ceramic green sheet 47 and is transferred (Fig. 4(d)), and then the carrier film 41 is removed (Fig. 4(e)). The ceramic green sheet 47 thus obtained is sandwiched between the sheets of the signal wiring pattern and the ground electrode, and then the composite body is put into a press die and is pressed. In this case, the cavity pattern 46 removed from the carrier film 41 may be placed directly on the ceramic green sheet 47. At this time, in order to prevent deviation, the carrier film 41 may be temporarily pressed or fixed eg. by an adhesive. In addition, one of the reasons to use a photosensitive resin is that even a micro pattern can be obtained with high accuracy, and cavities can be easily made along the signal wiring. Therefore, in order to obtain a cavity pattern, having a relatively large area, in which portions where the signal patterns are concentrated are integrated, no photosensitive resin need be used. In this case, a resin sheet which is gasified and removed in the sintering step may be simply punched and pressed on the green sheet. An example of a substrate packaging 18 memory chips on both sides will be described below as an embodiment of the present invention. Fig. 5 is a sectional view of one side of a substrate which packages 9 memory chips on one side, i.e., 18 on both sides. In Fig. 5, reference numeral 51 denotes a signal wiring pattern; 52, a ground electrode; 53, a memory chip packaging pad; and 54, a cavity pattern. As described above, most of address and control lines of the memory chips are connected parallel to each other. If no cavity is formed, a capacitance between the signal wiring pattern 51 and the ground electrode 52 is high. In this embodiment, five cavity formation layers are formed between the signal wiring pattern 51 and the ground electrode 52, and a carbon paste is printed and formed to each layer as a cavity pattern. A thickness of the paste during printing is 10 to 15 µm. Although not shown, five similar cavity formation layers are arranged between the signal wiring pattern and the ground electrode at the side of the chip on the opposite surface of the substrate. A width of the cavity pattern is three times the pattern width of 150 µm of the signal wiring, i.e., 450 µm. At this time, a cavity 54 divided into five layers between the signal wiring pattern 51 and the ground electrode 52 has a thickness of about 10 µm for one layer, and 50 µm for five layers, and a thickness of the insulator portion for six layers is 430 µm. A capacitance of the signal wiring pattern relative to ground is 24.2 pF, and that in the case in which no cavity is formed is 40.5 pF, so that a capacitance reduction of about 40% is obtained. As is apparent from the above description, by forming a cavity in a ceramic substrate, a capacitance determined by a dielectric constant, a width of the signal circuit pattern, and an interval between the signal circuit pattern and the ground electrode can be easily reduced. Conventionally, in order to reduce the capacitance, the circuit pattern width is micropatterned or a dielectric constant of a substrate material is reduced. On the contrary, in the present invention, the substrate material need not be changed at all nor the pattern width need be micropatterned. Since the pattern capacitance can be reduced without changing the material, the present invention can be applied to a packaging substrate for a computer, e.g., a multi-chip package, which requires a high speed operation, thereby improving performance of a computer. In addition, when a material of a signal circuit portion and a high permittivity material which is a material different from that of the signal circuit portion are integrally sintered in the substrate to form a capacitor therein, a dielectric constant of the signal circuit portion is sometimes increased by a reaction of both the materials as compared with the case in which the high permittivity material is not sintered integrally. Also in this case, a cavity is formed in the substrate to reduce the effective permittivity. Note that in this embodiment, a description has been made with reference to the capacitance relative to ground of a portion between a signal line and the ground electrode. However, the same effect can be obtained with respect to not only the ground electrode but also to the power supply pattern. In addition, when the cavity is formed between the signal patterns, a reduction effect of crosstalk of the signal can be obtained.

Claims: A ceramic wiring substrate comprising at least one layer containing a signal line pattern embedded therein, a layer containing a ground electrode or a power supply electrode pattern, and a cavity which is wider than the width of the signal line pattern formed inside the substrate between said signal line pattern and said ground or power supply electrode pattern, the cavity being enclosed by the ceramic material of the substrate, and being arranged parallel to and spaced from said signal line pattern. A method of forming a substrate according to Claim 1, wherein said cavity is formed by forming on a green sheet of said ceramic a cavity pattern of a material which is decomposed and scattered at or below a sintering temperature of said green sheet, sandwiching said cavity pattern between a green sheet containing said signal line pattern and a green sheet containing said ground or power supply electrode pattern so that the cavity pattern is spaced from the signal line pattern by green sheet material, heating and pressing the green sheets to obtain a stacking body, and further gradually heating said stacking body in an oxidizing atmosphere so that said material which forms said cavity pattern is decomposed and removed. A method according to Claim 2, wherein said cavity pattern is formed by printing a carbon paste on the ceramic green sheet. A method according to Claim 2, wherein said cavity pattern is obtained by stacking a cavity formation layer having a through hole at a location at which said cavity is to be formed and a sheet without a hole, forming a composite sheet with said hole forming a groove therein, and charging a carbon paste into said groove. A method according to Claim 2, wherein said cavity pattern is formed by forming a photosensitive resin film on a carrier film, forming a cavity pattern in said resin film using a photo mask, pressing said cavity pattern against a ceramic green sheet, and removing said carrier film. A ceramic wiring substrate having a plurality of pads for connecting memory chips formed on one surface thereof and having signal lines and ground or power supply electrodes, arranged in different layers formed therein, the substrate comprising a plurality of layers of cavities formed inside and enclosed by the ceramic material of the substrate, so that a plurality of cavities is present between each signal line and one of the ground or power supply electrodes, each plurality of cavities being parallel to a corresponding one of said signal lines, the signal lines being separated from the cavities by the ceramic material of the substrate, and the width of each of said cavities being greater than the width of said corresponding signal line. A substrate according to Claim 6, wherein the width of said signal line is of the order of 150 µm or less, the width of each of said cavities is about three times that of said signal line and the thickness of each of said cavities is of the order of about 10 µm.

Inventors: IKEDA TERUYUKI, UTSUMI KAZUAKI, IKEDA, TERUYUKI, UTSUMI, KAZUAKI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1987
Main classification: H01L23
IPC codes: H01L23, H05K3, H01L21, H05K1