Display controller

Abstract: A display controller employs timing signals to control a display on a screen of a display device in respect of each of a plurality of pixel unit regions (R) as is known. However, the overall area of the display is effectively sub-divided into fixed data areas in which the data to be displayed are fixed and variable data areas in which the data to be displayed can be varied. A first ROM (3) provides, in relation to each of the unit regions (R), an area flag signal (F) indicative of whether the unit region is in the fixed data area or in the variable data area. This first ROM (3) stores fixed data representing the data to be displayed when the unit region is in the fixed data area as well as address data to access a RAM (4), which stores variable data representing the data to be displayed in the variable data area. A second ROM (6) receives the fixed data or the variable data, depending on the flag signal, and generates display pattern data held by a latching circuit (7) which drives the display device.

Description: TECHNICAL FIELD OF THE INVENTION This invention relates to a display controller for controlling the display of characters or other patterns on a screen of a display device. BACKGROUND OF THE INVENTION A known form of controller, described in more detail hereinafter, uses a RAM to store information relating to locations on a display screen and to store accessible character data. This known arrangement gives rise to certain disadvantages and a general object of the invention is to provide an improved controller. SUMMARY OF THE INVENTION In one aspect the invention provides a display controller comprising a display controller for controlling the display on a screen of a display device said display being subdivided under control of synchronised timing means into unit regions some of the areas of the display being fixed data areas in which data to be displayed are fixed and some of the areas being variable data areas in which the data to be displayed can be varied; said controller comprising a first ROM for providing, in relation to each of the unit regions, an area flag signal indicative of whether the unit region is in the fixed data area or in the variable data area, the first ROM further providing fixed data representing the data to be displayed when the unit region is in the fixed data area, and the first ROM further providing address data when the unit region is in the variable data area, a RAM for receiving the address data from the first ROM and producing variable data to be displayed in the variable data area, a second ROM for receiving the fixed data from the first ROM or the variable data from the RAM in dependence upon the area flag signal, and for providing display pattern data to be displayed on said display device and an output circuit that latches the display pattern data from said second ROM and feeds the display pattern data to the display device at a predetermined timing. The present invention also provides in a preferred embodiment a multiplexer which receives the fixed data from the first ROM and the variable data from the RAM and outputs the fixed data when the area flag signal indicates that the unit region is in the fixed data area and outputs the variable data from the RAM when the first data indicates that the unit region is in the variable data area, the second ROM being connected to receive the output of the multiplexer. Timing signals are preferably provided by timing means within the controller which access addresses in the first ROM. The first ROM responds by producing flag signals and the fixed data address data of the RAM. The invention may be understood more readily and various other aspects and features of the invention may become apparent from consideration of the following description. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings:- Figure 1 is a block diagram showing a display controller constructed in accordance with the invention; Figure 2 is a block diagram showing an example of a prior art display controller; Figure 3 is a diagram showing an example of display which can be produced by the display controller of Figure 1 or Figure 2; and Figure 4 is a diagram showing various operating regions of the display. A prior art display controller is shown in Figure 2. As illustrated in Figure 2, an oscillator circuit 1 provides a drive signal from which a timing generator 2 derives the necessary timing signals. Where the controller is used with a cathodic rag tube display the timing signals would be synchronised with the frame and line scans of the associated TV circuitry and external synchronisation signals from the TV circuitry are inputted to the circuit 1 and the generator 2. A display memory 9 is controlled by the timing signals from the generator 2 to ouput data representing characters to be displayed at various locations on the display screen. Information corresponding to characters is stored in a character ROM 6 and the data from the memory 9 addresses the desired character pattern information in the character ROM 6 and this accessed information is transferred to an output circuit 7. The output circuit 7 outputs the display pattern information to the TV circuitry to cause characters or patterns to be displayed on the screen in desired locations. The data stored in the memory 9 is altered by means of an input control circuit 8 which writes in data received from a microcomputer or some other external control device into the memory 9. Fig. 3 depicts a typical display representing a video recorder program (where the symbol " " represents a blank space, which must be treated as a type of character). When the display controller shown in Fig. 2 is used to create such a display some 240 characters (10 lines of 24 characters each) are needed. To produce each character and to turn it on and off individually some eight bits of data information are required. The display memory therefore requires 1920 bits (=240 x 8) of rewritable memory (RAM), necessitating a large chip size and high cost if the display controller is to be implemented on a single chip. Moreover, the transfer of the data requires time, resulting in image quality problems. Another problem arises when the input controller 8 attempts to control the entire contents of the display since the need to write 1920 bits of data per frame into the display memory puts an excessive load on the controller. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The general concept of the invention will first be explained with reference to Figs. 1, 3 and 4. As shown in Fig. 4, and as is customary with character displays, data are processed or controlled in respect of each of a plurality of unit regions R each composed of a group of pixels forming part of the overall display screen. According to a feature of the invention, the screen of the display device (10 Fig. 1) is further divided for data processing, into fixed character data areas or regions FA (hatched in Fig. 4) in which the data for the display are fixed and a variable character data areas or regions VA (unhatched in Fig. 4) in which the data for the display are varied. For example, relating this to the typical display of Fig. 3, characters which can be varied are circled. Codes specifying the characters in the fixed data areas FA are stored in a display ROM 3, while selectibly changeable codes specifying the characters in the variable data areas VA are stored in a RAM 4. The data for respective unit regions R are processed successively and to distinguish between data for a unit region R in a fixed data area FA or a unit region R in a variable data area VA a flag signal F is used which is stored in and produced by a display ROM (3 Fig. 1). Depending on the state of the flag signal F, either the output from the display ROM or the output from a RAM (4 Fig. 1) is inputted to a character ROM (6 Fig. 1). The display controller shown in Fig. 1 controls the display on the screen of the display device 10 in respect of each of unit regions R which is either a fixed data area FA in which the data to be displayed are fixed or a variable data area VA in which the data to be displayed can be varied. Turning now to Fig. 1, the controller again uses an oscillator circuit 1 and a timing generator 2, to create timing signals synchronized to the display timing of the device 10. Where the device 10 is a CR tube with TV circuitry the horizontal and vertical (frame and line) sync signals of the video signal of the display device 10 are provided from the circuitry of the device 10 as external sync signals to the circuit 1 and the generator 2. The timing signals provided by the generator 2 are fed to various circuits of the controller so that they operate in synchronism with each other and with the display device 10. A display ROM 3 which may be in the form of a mask ROM, stores the locations and identities of the fixed character data to be displayed on the screen of the display device 10 and locations of the variable character data while a variable RAM 4 stores identities of the variable character data of the display pattern. The display ROM 3 thus also produces output data to access addresses in the RAM 4. A character ROM 6 contains display pattern data and, under control of output data from the display ROM 3 or the output data from the RAM 4, outputs the display pattern data to be displayed on the screen of the display device 10 to an output controller or circuitry feeding the display device 10. The display ROM 3 stores, at each of its addresses (memory locations) corresponding to respective unit regions R, an area flag signal F indicative of whether the particular unit region R is in the fixed data area FA or in the variable data area VA. The display ROM 3 further stores at each address either fixed character or display pattern data i.e. a code specifying the character of display pattern if the corresponding unit region R is in the fixed data area FA, or address data for the RAM 6 if the corresponding unit region R is the variable data area VA. The timing generator 2 provides, in sequence, address data for the display ROM 3, which upon receipt of each address data, produces the area flag signal F and the fixed data or the address for the RAM 4. The RAM 4 stores at each of addresses corresponding to unit regions R in the variable data area, character or display pattern data i.e. a code for specifying a character or display pattern to be displayed in the corresponding unit region. When it receives an address data specifying one of such addresses it produces the stored variable display pattern data in the specified address. The variable display pattern data in the RAM 4 can be changed or rewritten. This can be done by use of an input control circuit 8 connected to a microcomputer or some other external controller, not shown. A multiplexer 5 receives the fixed data from the display ROM 3 and the variable data from the RAM 4 and outputs the fixed data when the area flag signal F indicates that the unit region R is the fixed data area FA and outputs the variable data from the RAM 4 when the area flag signal F indicates that the unit region R is in the variable data area VA. The character ROM 6 is connected to receive the output of the multiplexer 5. The character ROM 6 receives the fixed data from the display ROM 3 or the variable data from the RAM 4, depending on the state or contents of the area flag signal F from the display ROM 3, and provides the appropriate display pattern data to be displayed on the screen of the display device 10 to the output circuit 7. This circuit 7, which may take the form of a shift register, latches the display pattern data from the character ROM 6 and feeds the display pattern data to the display device 10 at the predetermined, correct timing. The area flag signal F may be in the form of a specific bit not used to specify the addresses in the display ROM 3. For instance, it may be the MSB (most significant bit) of the output of the display ROM 3. It may be so arranged that when the MSB of the output from the display ROM 3 is at "0" the data from the display ROM 3 specifies an address in the character ROM 6 directly, while when the MSB is at "1" the data specify an address in the variable RAM 4. Specifically, this means that on the basis of the MSB from the display ROM 3, the multiplexer 5 selects whether to use the data from the display ROM 3 or the data from the variable RAM 4 as the address of the character ROM 6. The control or processing of the signals for the display takes place successively line by line and unit by unit. For instance, the first line (the uppermost line) is processed first, and then the second line, the third line, and so on. During processing of each line, the respective unit regions R are processed or controlled successively, for instance from the left to the right. Consider for example the first line of the sample display in Fig. 3. In this line, the circled characters "12" are variable. In other words, the two unit regions for "12" are in the variable data area VA. While the address in the ROM 3 corresponding to 14 unit regions for are specified by the timing generator 2 in turn, the ROM 3 itself produces fixed data (codes) respectively specifying in turn. These fixed data are given to the character ROM 6 through the multiplexer 5, since the ROM 3 is also producing the area flag signal F, indicating the fixed data area FA. When these fixed data are supplied as addresses to the character ROM 6, the character ROM 6 produces display pattern data (character pattern data) for displaying the characters When the addresses in the ROM 3 corresponding to the unit regions for "12" are specified by the timing generator 2 in turn, the ROM 3 produces address data for the RAM 4, which stores, at the addresses (memory locations) corresponding to the given address data, the variable data (codes) specifying "1" and "2" respectively. These variable data are given to the character ROM 6 and through the multiplexer 5 since the ROM 3 is also producing the area flag signal F indicating the variable data area VA. These addresses are supplied to the character ROM 6, and the character ROM 6 produces display pattern data (character pattern data) for displaying the characters "12". When the addresses in the ROM 3 corresponding to the unit regions for in the rest of the first line are accessed, the ROM 3 itself produces fixed data for these patterns in turn. Similar operations are performed on other lines. If the variable data in the RAM is changed, this will be reflected when the address corresponding to the variable data is accessed next. For instance, the data in the RAM 4 for "12" in the first line may be changed to "01". When the addresses for such data are specified by the ROM 3, which in turn is addressed by the timing generator 2, the new data for "01" are produced and supplied to the character ROM 6. If the full character set consists of 128 characters, 7 bits are required for each character. Where the display ROM 3 is required to specify any of the 128 characters, its output should include the 7 bits plus another bit, e.g., MSB for the area flag signal F. Where it is necessary that any of the 128 characters can be displayed in the variable data area VA, the output of the RAM 6 should also include 7 bits. But where not more than 32 characters are required to be displayed on the variable data area VA, the output of the RAM 4 need only have 5 bits. Because a ROM can be used for the display memory in this embodiment, the circuit can be much smaller than in the prior art, in which a RAM must be used. For a CMOS (complementary metal oxide semiconductor) device, the ROM size is in general only 1/6 of RAM size, resulting in a major cost saving in a one-chip LSI implementation. Another advantage is that external control can be simple and fast, because the external controller only has to write data into the variable RAM. The invention is applicable to data processing for display in which data are processed in respect of each of unit regions forming part of the screen. The data pattern may be therefore include an element of a line or lines for tables, graphs and the like, and the term "character" or "character display" should be construed to cover such elements or display of such elements.

Claims: A display controller for controlling the display on a screen of a display device (10), said display being subdivided under control of synchronized timing means (1,2) into unit regions (R) some of the areas of the display being fixed data areas in which data to be displayed are fixed and some of the areas being variable data areas in which the data to be displayed can be varied; said controller comprising a first ROM (3) for providing, in relation to each of the unit regions, an area flag signal indicative of whether the unit region is in the fixed data area or in the variable data area, the first ROM (3) further providing fixed data representing the data to be displayed when the unit region is in the fixed data area, and the first ROM (3) further providing address data when the unit region is in the variable data area, a RAM (4) for receiving the address data from the first ROM (3) and producing variable data to be displayed in the variable data area, a second ROM (6) for receiving the fixed data from the first ROM (3) or the variable data from the RAM (4), dependent on the area flag signal, and for providing display pattern data to be displayed on said display device and an output circuit (7) that latches the display pattern data from said second ROM (6) and feeds the display pattern data to the display device (10) at a predetermined timing. A controller according to claim 1 and further comprising a multiplexer (5) receiving the fixed data from the first ROM (3) and the variable data from the RAM (4) and outputting the fixed data when the area flag signal indicates that the unit region is in the fixed data area and outputting the variable data from the RAM (4) when the first data indicates that the unit region is in the variable data area, the second ROM (6) being connected to receive the output of the multiplexer. A controller according to claim 1 or 2 wherein the timing means (1,2) provides timing signals which access addresses in the first ROM (3), the first ROM (3) then responding to the timing signals by producing the flag signal and the fixed data or address data of the RAM (4). A controller according to claim 1, 2 or 3, further comprising means for selectively rewriting the information stored in the RAM (4).

Inventors: KOBAYASHI HIROSHI C O MITSUBIS, SHIBASAKI TAKESHI C O MITSUBIS, SUDA SHINJI C O MITSUBISHI DEN, KOBAYASHI, HIROSHI C/O MITSUBISHI DENKI K.K., SHIBASAKI, TAKESHI C/O MITSUBISHI DENKI K.K., SUDA, SHINJI C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1987
Main classification: G09G1
IPC codes: G06F3, G09G5