Image processing apparatus having function of enlargement and/or shrinkage of image

Abstract: The image processor apparatus comprises for perform­ ing a shrinking operation and input means for receiving a plurality of bits which represent an image to be shrinked; a plurality of gate circuits gating such different numbers of bits among said bits receiving by said input means accord­ ing to a shrinking scale factor that are less than the number of the bits received by said input means; means for selecting one of said gate circuits according to the shrinking scale factor to activate the selected gate circuit and an output means for coupled to said gate circuits for out­ putting a bit or bits which pass through the selected gate circuit. For the performance of an enlarging operation the apparatus comprises an input means for receiving a plurality of input bits representing an image to be enlarged; a shift means coupled to said input means for shifting said input bits by a bit number determined by an enlargement scale factor; a plurality of gate circuits gating a plurality of bits which are same in number as said input bits and contain two or more bits having the same content as that of at least first bit of said input bits or the shifted input bits; a means for selecting one of said gate circuits according to said enlargement scale factor to activate the selected gate circuit; and an output means coupled to said gate circuits for outputting the bits which pass through the selected gate.

Description: BACKGROUND OF THE INVENTION This invention relates to an image processing apparatus having a function of enlarging and/of shrinking a source image with an arbitary scale factor. According to a conventional image processing technique, enlarging (or zooming) an image by Z times or shrinking it by 1/Z times was easily performed, if Z is an integer. However, enlargement by n/m times (n and m one integers and n > m > o) or shrinking by m/n times was difficult and required a long processing period with extremely software operations. Therefore, NH (Nearest Neighbour) method has been proposed to execute enlargement by n/m times and shrinkage by m/n times. However, it requires a large amount of complex calculations for each bit to be enlarged or shrinked. Therefore, even if the high-level software technique is employed, a long period of time must be spent. Furthermore, image data is processed word by word in general. However, since the image data must be processed bit by bit in accordance with the NN method, processed bits must be packed word by word. This packing operation also requires a long period of time. SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus which can perform enlarging operation and/or shrinking operation at a high speed without executing complex calculation. This object is achieved by the invention as set out in claim 1. An image processing apparatus of the present invention comprises means for receiving a plurality of original image data word by word, each data consisting of a fixed number of bits, an enlarging of shrinking circuit having a plurality of gating circuits each gating arbitrary bit or bits of the original image data according to a scale factor, a means for selecting one of the gating circuits in response to a signal representing a desired scale factor to open the selected gate, and means for outputting an image data which consists of bit or bits passing through the selected gating circuit. A mask circuit and a rotator may be used to perform a packing operation to pack the outputted image data into one word, if necessary. For enlargement, each gating circuit gates those bits which are same in number as those of the original image data and which contain two or more bits having the same content as one of the bits of the original image data. For shrinkage, the gating circuits gate different numbers of bits less than the number of bits of the original image data. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagramm of an image processing apparatus according to an embodiment of the present invention: Fig. 2(a) shows a diagramm illustrating a data flow when a shrinking operation is performed in the embodiment; Fig. 2(b) shows a diagramm illustrating a data flow when an enlargement operation is performed in the embodiment; Fig. 3(a) shows an output format of a shrinking circuit of the embodiment; Fig. 3(b) shows an output format of an enlargement circiut of the embodiment; Fig. 3(c) shows a data format to be entered into an input register of the embodiment; Fig. 4 shows a table of a number of bits to be rotated (or shifted); Fig. 5 shows a block diagramm of the shrinking circuit of the embodiment; and Fig. 6 shows a block diagramm of the enlargement circuit of the embodiment. Description of the Preferred Embodiment According to the present invention, pixel data of a source image to be enlarged or shrinked are processed word by word without using complex calculation. Referring to Fig.1, an image processing apparatus according to one embodiment of the present invention has an input register 1, a shrinking circuit 2, an enlarging circuit 3, a mask circuit 4 having a temporary register, a rotator 5, an output register 6 and a read only memory ROM 7, all of which are coupled to a common bus 10. The shrinking circuit 2 works to shrink a source image and may be omitted if shrinking operation is not required. The enlarging circuit 3 may be omitted if enlargement is not required. The mask circuit 4, the rotator 5 and the ROM 7 are used to simplify the packing operation. In this embodiment, it is assumed that one word consists of 8 bits (8 pixel data). The pixel data of the source image are entered into the input register 11 via a bus 11 word by word and an processed pixcel data are derived from the output register 6 to a bus 12 word by word. The source image usually consists of a plurality of words and is stored in a source memory (not shown). The source image is read out therefrom word by word. Each word consists of 8 bits of continous pixel data in horizontal direction of XY co-ordinates and is entered into the input register 1 which has a capacity of 16 bits. When the shrinking operation is to be performed a word to be shrinked is entered into the shrinking circuit 2 and thereafter a shrinked pixel data is to the rotator 5 and the mask circuit 4 as shown in fig. 2(a). While, in the enlargement operation, two consecutive words are entered into the input register 1 and sent therefrom to the rotator 5 and thereafter the rotated word is sent to the enlargement circuit 3 as shown in Fig. 2(b). SHRINKING OPERATION In the shrinking operation, arbitrary bit or bits are picked up among 8 bits of pixel data according to a shrinking scale factor S s ( S s = m/n ). The shrinking circuit 2 is formed of simple selecting circuits which are predetermined to pick up the bit or bits in accordance with the shrinking factors. If the shrinking scale factor S s is selected among seven factors 1/8, 2/8, 3/8, 4/8, 5/8, 6/8 and 7/8 and 8 bits pixcel data are represented by A B C D E F G H as shown in fig. 3(c), the bit or bits to be picked up are predetermined as shown in fig. 3(a). The pixel data (word) of fig. 3(c) is sent to the shrinking circuit 2 via the common bus 10, and the shrinking circuit 2 has a selecting function to select one of the seven outputs shown in fig. 3(a) according to the shrinking scale factor S s . Referring to fig. 5, the shrinking circuit 2 has seven gate circuits 20 to 26 and a decoder 27 to select one of the seven gate circuits according to the shrinking scale factor S s . Since the shrinking scale m/n is m/8, m (= 1, 2, ..., 7), the numerator is used instead of S s . Each bit of the input register 1 is connected to the gate circuits 20 to 26 as shown in fig. 5. When m is 1, the decoder 27 outputs a signal for the shrinking scale factor of 1/8 to activate or enable the gate circuit 20 only. Thus, the pixel data A is picked up. When m is 2, the gate circuit 21 is selectively enabled and the pixel data A and E are picked up. When m is 3, 4, 5, 6 or 7, the gate circuit 22, 23, 24, 25 or 26 is selected, respectively, and the pixcel data ADG, ACEG, ACDEFH, ABDEFH and ABCDFGH are picked up. As shown in fig. 5, the shrinking circuit 2 can be formed as a simple selector. Since mumber of bits of a shrinked pixel data is less than that of one word input data (8 bits of pixel data), packing operation is required to pack outputs of the shrinking circuit 2 into one word. The packing operation is executed by use of the rotator 5 and the masking circuit 4. The well known shiftregister having a feedback loop to return a shift out bit or bits to its input can be used as the rotator 5. A barrel shifter is suitable as the shiftregister. A number of bits to be shifted is determined according to the shrinking scale factor as shown in fig. 4. When the source image is shrinked by m/8 times, m bits are picked up from 8 bits of a first one word as shown in fig. 3(a). The picked-up m bits are entered into the mask circuit 4 through the rotator 5. At this time the picked-up m bits are not shifted and are entered into 1st to mth bit positions of the mask circuit 4. In this embodiment the mask circuit 4 and the temporary register have 16-bit positions, respectively, for the enlargement operation and 8-bit positions can only be used in the shrinking operation. An output of the mask circuit 4 is set at 1st to 8th bit positions of the temporary register. For example, when the source image is shrinked by 3/8 times, 3 bits among 8 bits of a first word are picked up by the shrinking circuit 2. These 3 bits are not shifted and are entered into 1st to 3rd bit positions of the mask circuit 4. The mask circuit 4 masks the remainder 4th to 8th bit positions. Consequently, the 3 bits picked up from the first word are set into 1st to 3rd bit positions of the temporary register. Thereafter a second word subsequent to the first word is entered into the shrinking circuit 2 and 3 bits thereof are picked up. These subsequently shrinked 3 bits are shifted by 3 bit positions in the rotator 5 and entered into 4th to 6th bit positions of the mask circuit 4. At this time, the mask circuit 4 masks the bit positions (1st to 3rd and 7th to 8th) except for the 4th to 6th bit positions. Thus, the 3 bits picked up from the second word are set into the 4th to 6th bit positions of the temporary register. Then, a third word subsequent to the second word is entered into the shrinking circuit 2 and the picked up 3 bits are sent to the rotator 5 where they are shifted by 6 bits positions as indicated in fig. 4. First two of the shifted three bits are entered into the 7th and 8th vacant bit positions of the temporary register via the mask circuit 4 which masks the 1st to 6th bit position. As a result, 8 bit postions are filled up to form one word which corresponds to 3/8 - shrinked word and which is sent to the output register 6 and then to a destination memory (not shown) which is coupled to the bus 12. The last bit of the three bits out of the input third word is shifted out from the rotator 5 and is rotated to a first bit position of the rotator 4, The rotated last bit is thereafter entered into the 1st bit position of the mask circuit 4 and is set in the 1st bit position of the temporary register. Successively, a fourth word is applied to the shrinking circuit 2 through the input register 1 and 3 bits are picked up by the shrinking circuit 2. The picked up 3 bits from the fourth word are shifted by one bit in the rotator 5 as shown in fig. 4 and are written into the 2nd to 4th bit positions of the temporary register through the mask circuit. In such manner, shrinking operation proceeds, and the shrinked pixel data of 8 bits is packed word by word. With respect to the other shrinking scale factors (m = 1, 2, 4, 5, 6, 7 or 8), m bits are picked up from each word by the shrinking circuit 2, shifted or rotated by the rotator 5 by the respective bits shown in fig. 4, and written into the temporary register from which the shrinked data is read 8 bits by 8 bits. Data shown in fig. 4 representing the number of bits to be shifted or rotated are stored in the ROM 7 and are read out thereof according to the scale factor m. ENLARGEMENT OPERATION When the source image is to be enlarged by 8/m times (m = 1, 2, ..., 7 or 8), a word entered into the input register 1 is sent to the rotator 5. In the enlargement operation 16 bit (two words) positions of the input register 1 and the rotator 5 are fully employed, while in the shrinking operation only 8 bits of the rotator and the input register are used. At first, a first word (8 bits) and a second word (8 bits) (for example, A B C D E F G H A' B' C' E' F' G' H') are entered into the input register 1 of the 16 bits. The rotator 5 of the 16 bits shifts the 16 bits of the first and second words by number of bits designated in fig. 4 in accordance with the scale factor. A start bit to be enlarged is located at the most significant bit (MSB) position. For the first enlarged word, no rotation is made as shown in fig. 4. An output of the rotator 5 is sent to the enlarging circuit 3. Referring to fig. 6, the enlarging circuit 3 contains seven 8-bit gate circuits 30 to 36 which are coupled to the respective bit positions of the 8-bit input data lines of the circuit 3 such that the eight outputs from the first 8-bits of the input data shown in fig. 3(b) may be respectively derived therefrom. A decoder 37 is also provided to receive a scale factor for which the denominator m of the enlarging scale factor S e (= n/m = 8/m) may be used and to select one of the seven gate circuits according to the inputted scale factor m. The selected one of the seven gate circuits 30 to 36 is enabled by the output of the decoder 37. If the source image is to be enlarged by 8/3 times, for example, the gate circuit 32 is enabled. Therefore, A A A B B B C C is derived from the enlarging circuit 3 as a first enlarged output for the original pixel data and directly sent to the output register 6 through which this output is sent to the destination memory (not shown). Then, the same 16-bit input data is shifted in the rotator 5 by m bits (in the above case, 3 bits) such that the (m-1)th (4th) bit locates at a first bit position. Thus, if m is 3, the data D E F G H A' B' C' E' F' G' H' (where D E F G H is remaining bits of the pixel data of the first word and A' B' C' D' E' F' G' H' is the pixel data of the second word) is obtained by the rotator 5 and inputted to the enlarging circuit 3, and from the first eight bits D E F G H A' B' C' an output data D D D E E E F F is derived through the selected gate circuit 32 for m = 3. This data is directly sent to the output register 6 as a second enlarged data for the first input word A B C D E F G H. Further, the rotator 5 performs shift operations by 2m bit (6 bits in the above case) and first eight bits G H A' B' C' D' E' F' of the 6-bit shifted input words are subjected to the enlarging operation by the enlarging circuit 3 to obtain a third output data G G G H H H A' A' through the gate circuit 32. After the enlargement of the first word is thus completed, a third word A'' B'' C'' D'' E'' F'' G'' H'' of 8 bits in the source image is newly entered into the input register 1 instead of the first word. Thereafter the rotator 5 rotates 3m (9) bits and B' C' D' E' F' G' H' A'' (B' C' D' E' F' G' H' are the remaining position of the second word and A'' belongs to the third word) obtained by the rotator 5 are inputted to the enlarging circuit 3. As a result an output data B' B' B' C' C' C' D' D' is derived through the gate circuit 32. Thus, whenever enlargement of one word is completed, a newly word is entered into the input register. When the other enlargement scale factor (m = 1, 2, 4, 5, 6, 7 or 8) is selected, x m-bit ( = 0, 1, 2, 3, ...) rotating operation is performed by the rotator and one of the seven gate circuits 30 to 36 is enabled according to the enlargement scale factor m.

Claims: An image processing apparatus for performing at least one of a shrinking operation and an enlarging operation on image data with a range of predertermined scale factors, comprising input means (1) for receiving said image data consisting of a plurality of bits and performing means (2-7) for performing said shrinking operation or said enlarging operation on said image data derived from said input means (1) to produce shrunk data or enlarged data, said performing means including a plurality of gate circuits (20-26; 30-36) each gate circuit corresponding to a predetermined scale factors, each supplied with data and, when selected and activated, allowing the supplied data to pass therethrough, supplying means (10; 5, 10) operatively coupled to said input means (1) for supplying said plurality of gate circuits (20-26; 30-36) with data that are based on said image data and have bit patterns derived from said image data, said bit patterns being different in combination from one another, respectively, the length of said bit patterns corresponding to said predetermined scale factor, the contents of said bit patterns being a predetermined choice according to the bits of the original data, and selecting means (27; 37) responsive to said predetermined scale factor for selecting one of said plurality of gate circuits (20-26; 30-36) to activate the selected gate circuit, the selected and activated gate circuit thereby producing said shrunk data or said enlarged data. The image processing apparatus as claimed in claim 1, wherein said apparatus performs said shrinking operation on the image data consisting of N-bit pixel data with a shrinking factor of M/N times, each of said N and M being an integer and said N being larger than said M, whereby said plurality of gate circuits consists of 1st to (N-1)th gate circuits (20-26), said supplying means supplies one bit to N-1 bits of said N-bit pixel data to said 1st to (N-1)th gate circuits, respectively, and said selecting means (27) selects the Mth gate circuit in response to said shrinking scale factor, said Mth gate circuit thereby producing said shrunk data having a bit length shorter than that of said image data. The image processing apparatus as claimed in claim 2, whereby said performing means further includes packing means (4, 5, 7) for packing a plurality of shrunk data derived from a plurality of selected and activated gate circuits to provide shrunk image data consisting of said N-bit. The image processing apparatus as claimed in claim 3, whereby said packing means includes a rotator (5) for shifting the shrunk data from the selected and activated gate circuit by a number of bits determined by said shrinking scale factor. The image processing apparatus as claimed in claim 1, wherein said apparatus performs said enlarging operation on the image data consisting of N-bit pixel data with an enlarging scale factor of N/M times, each of said N and M being an integer and said N being larger than said M, whereby said plurality of gate circuits consisting of 1st to (N-1)th gate circuits (30-36), that said supplying means includes a rotator (5) for shifting said image data by a number of bits determined by said enlarging scale factor to provide shifted image data and means for supplying said shifted image data to said 1st to (N-1)th gate circuits such that each of said gate circuits receives the pixel data consisting of said n-bit and containing two or more bits of the same content as each other, and that said selecting means (37) selects the Mth gate circuit in response to said enlarging scale factor to produce said enlarging data.

Inventors: OHUCHI MITSUROU C O NEC CORPOR, OHUCHI, MITSUROU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1987
Main classification: G06F15
IPC codes: H04N1, G09G5, G06T3, G06F3, G06T1