VECTOR PATTERN PROCESSING CIRCUIT FOR BIT MAP DISPLAY SYSTEM

Abstract: A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N × N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N × N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N × N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis. The circuit further includes a bit setting circuit energizing one of the word register units in response to the first and second dot data from the DDA and setting a bit defined by the dot data to the energized word register unit in each dot data generation time at the DDA; and a store control circuit addressing at least one address of a word in one of the memory unit defined by the coordinate, so that at least one of data set in one of the word register units is stored in the word defined by the address.

Description: l. Field of the Invention The present invention relates to a vector pattern processing circuit for a bit map display system. 2. Description of the Related Art Bit map display systems are used for displaying a variety of display patterns, including characters, vectors, etc., on a display unit, such as a cathode ray tube (CRT) display unit. Previously, data was stored in a video memory consisting of a plurality of words, each word composed of a plurality of bits, and each bit corresponding to a dot or a picture element in the CRT display unit. The stored data was displayed on the CRT display unit by, for example, raster scanning. In the bit map display system, a vector pattern processing circuit generates dot data in response to a start coordinate and an end coordinate and stores the data in the video memory. A variety of figures and patterns can be expressed by combining a variety of vector patterns, and therefore, the vector pattern processing circuit is frequently used for generating a variety of patterns. The prior vector pattern processing circuits, however, suffer from the disadvantages of a low speed, an irregular timing control, and a complex circuit construction. These disadvantages will be described later with reference to the drawings. An object of the present invention is to provide a vector processing circuit with a high speed operation regardless of the shape of the vector pattern. Another object of the present invention is to provide a vector processing circuit having a relatively simple circuit construction which achieves a high speed operation. According to the present invention, there is provided a vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions, memory units, word register units and a vector pattern generation circuit, in which said display unit has a plurality of quasi regions comprised of first and second quasi regions each forming N x N dots, and said first and second quasi regions are respectively arranged in a chessboard-like arrangement on a display plane of said display unit, where said first quasi regions correspond to white boxes and said second quasi regions correspond to black boxes on the chessboard, the circuit also providing first and second memory units each including a plurality of words formed in a matrix, each word having an N x N bits structure, said words in said first memory unit corresponding to said first quasi regions and said words in said second memory unit corresponding to said second quasi regions on said display plane; first and second word register units operatively connected to said first and second memory units, each having an N x N bits structure; a vector pattern generation circuit receiving start and end coordinates in said quasi regions defining a vector pattern to be processed, and generating a first dot data of a primary axis for said vector pattern and a second dot data of a subsidiary axis perpendicular to said primary axis in response to a gradient of said vector pattern with respect to said primary axis along said primary axis for every N dots in said primary axis; a bit setting circuit, operatively connected between said first and second word register units and said vector pattern generation circuit, activating one of said first and second word register units in response to said first and second dot data from said vector pattern generation circuit, and setting a bit defined by said first and second dot data in said activated word register unit in each dot data generation time at said vector pattern generation circuit; and a store control circuit which addresses said one word in said one memory unit defined by said start coordinate and a second word in the other memory unit other than said word defined by said start coordinate, where said second word corresponds to a quasi region adjacent to a quasi region of said one word in a forward direction of said subsidiary axis, when said bit setting is effected in said word register unit. The coordinate in the store control circuit is updated in response to the generation of the first and second dot data at the vector pattern generation circuit. Preferably, the vector pattern generation circuit may include a digital differential analyzer. Other objects and features of the present invention will be described below in detail with reference to the accompanying drawings, in which: Fig. 1 is a graph of an example of a display pattern in a video memory of a prior art bit map display system; Fig. 2 is a graph of another example of a display pattern in a video memory of another prior art bit map display system; Figs. 3a to 3c are timing charts of the operation of the vector pattern generation of the prior art bit map display system of Fig. 2; Fig. 4 is a graph of still another example of a display pattern in the video memory of Fig. 2; Fig. 5 is a graph representing a rectangular-coordinate in a display unit of a present invention; Fig. 6 is a graph representing sections of Fig. 5 and defining the relationship between a primary axis and a subsidiary axis of a vector pattern; Figs. 7a to 7d and Figs. 8a and 8b are graphs illustrating a pattern generation principle of the present invention; Fig. 9 is a graph representing the relationship between the structure of video memories and a layout of a display unit of the present invention; Fig. 10 is a circuit diagram of an embodiment of a vector pattern generation circuit according to the present invention; Fig. 11 is a graph representing a vector pattern to be processed by the vector pattern generation circuit of Fig. 10; Figs. 12a to 12c are timing charts of the vector pattern generation circuit of Fig. 10; and Figs. 13a to 13c are timing charts of a pipe line vector pattern generation circuit of another embodiment of the present invention. Before describing the preferred embodiments of the present invention, one example of a prior art system is described with reference to the drawings, for comparison. Figure 1 is a graph of an example of a display pattern in a video memory of a prior art bit map display system. The video memory includes a plurality of words each consisting of 16 bits in the form of a 1 × 16 bits structure. Each bit corresponds to a single dot or a single picture element (PIXEL) on a display unit. Upon receipt of a start of the coordinate (x₁ , y₁) and an end of the coordinate (x₂ , y₂), a digital differential analyzer (DDA) successively generates bit data (nine in this example). The generated bit data is placed on eight words, i.e., word 1 to word 8, as shown by a pattern L₁₁ , and a nine times memory store is carried out, namely, a memory store is effected twice for word 5 and two dots are stored therein. If another start of the coordinate (x₃ , y₃) and another end of the coordinate (x₄ , y₄) are given, the DDA successively generates three bits of data, as shown by a pattern L₁₂ , and a memory controller effects the storage of the same in the words 5 to 7 by accessing the memory three times. This type of display system successively and repeatedly carries out the generation of data and the storage of every dot. Therefore, the bit map display system of the above basic pattern generation method due to the start coordinate and the end coordinate has a defect of a low speed pattern generation. Figure 2 is a graph of another example of a display pattern in a video memory of another prior art bit map display system. The video memory includes a plurality of matrix-formed words each consisting of 16 bits, but in the form of a 4 × 4 bits structure. Each bit corresponds to a single dot. If the above single pattern generation method is applied thereto, the DDA also generates nine bit data for a pattern L₂₁ from a start coordinate (x₅ , y₅) to an end coordinate (x₆ , y₆) similar to the pattern L₁₁ in Fig. 1. In this example, the bit data is placed on words W₀₂ , W₀₃ , W₁₁ , and W₁₂. A plurality of bits (up to sixteen in a single word) is temprarily saved in a register during the data generation, and stored to the memory by a single store operation. Therefore, only a four times access of the memory is required. Compared with Fig. 1, this method realizes an improvement of the memory store time. If the pattern generation is limited to a 4 × 4 bits area for a word in each period, the memory store time is constant and is a single word store time. Nevertheless, in the pattern generation of a pattern L₂₂ , the DDA generates three bit data for a word W₂₃ , and one bit data for words W₁₄ and W₂₄. Thus, supposing one machine cycle is needed for generating a bit data at the DDA, and four machine cycles for storing a single word, and supposing a periodic data processing for every four machine cycles corresponding to a maximum pattern generation time in a single word in view of a simple circuit construction, then there is too much idle time, as shown in Figs. 3a to 3c. In addition to the second prior art example of Fig. 2, if a word can be defined freely on the basis of a start coordinate, as disclosed in US-A-3,938,102 (Morrin et al., "METHOD AND APPARATUS FOR ACCESSING HORIZONTAL SEQUENCES AND RECTANGULAR SUB-ARRAYS FROM AN ARRAY STORED IN A MODIFIED WORD ORGANIZED RANDOM ACCESS MEMORY SYSTEM", Feb. 10, 1976), i.e., a free word WF₁₁ due to the start coordinate is placed on words W₁₁, W₁₂ , W₂₁ , and W₂₂ as shown in Fig. 4, the memory control circuit becomes complex because the free word WF₁₁ consists of bits 6, 7, 10, 11, 14, and 15 of a word W₁₁ , bits 4, 5, 8, 9, 12, and 13 of a word W₁₂ , bits 2 and 3 of a word W₂₁ , and bits 0 and 1 of a word W₂₂ , and this bit sequence and word combination are not orderly. As a result, the disclosed circuit is disadvantaged by a complex circuit construction since, for example, a right and left direction circular mechanism, an overall logic circuit, a line logic circuit, etc., must be provided therefor. Moreover, the disclosed circuit suffers from another disadvantage of the construction of a memory thereof, as follows: a recent graphic display unit normally has 1280×1024 PIXELs, and thus a frame memory therefor usually has a capacity of 2048×1024 PIXELs. To realize the frame memory, when a 64 kbits memory chip is used, 32 memory chips, sixteen address systems, and a single word register are required. When a 256 kbits memory chip, now widely utilized, is used, theoretically eight memory chips are needed. However, in the disclosed circuit, the sixteen PIXELs forming each region must exist in different independently addressable memory chips. As a result, sixteen memory chips of 256 kbtis, sixteen address systems, and a single word register are needed. In other words, the capacity of the frame memory must be 2048×2048 bits for displaying the 1280×1024 PIXELs. This obviously, is an underutilization of the memory chips. Now, preferred embodiments of the present invention will be described with reference to the drawings. Figure 5 is a graph representing a rectangular-coordinate of x and y defined in a display plane of a display unit in which vectors are defined. A vector V₁ having an angle α₁ smaller than 45° with respect to the x-axis has a primary axis of a positive x and a subsidiary axis of a negative y. A vector V₂ having an angle α₂ larger than 45° with respect to the x-axis has a primary axis of a negative y and a subsidiary axis of a positive x. Similarly, the coordinate is divided into eight sections by 45°, as shown in Fig. 6. In Fig. 6, reference P represents the primary axis and reference S represents the secondary axis in each section. Figure 5 is also a graph of the dot pattern defined in the display plane of the display unit. A display area in the display unit consists of a purality of dots in a matrix form. In Fig. 5, the display areas are formed by matrix-formed quasi-display regions R₀₀ , R₀₁ , ..., R mn , each consising of 4 × 4 dots. In this embodiment, dot data is generated for a single display region or two consecutive display regions in one of the sections I to VIII in Fig. 6, defined by a gradient of a vector, in each period. Figures 7a to 7d are graphs representing vector patterns occupying section I in Fig. 6. In Figs. 7a to 7d, arrows indicate forward directions of the vector patterns. In Fig. 7a, a horizontal straight vector V₂₁ (dotted portions) havig an angle of 0° in a region R₁₁ has four dot data in the primary axis of x. Another horizontal straight vector V₂₂ (shaded portions) also has four dot data. In Fig. 7b, a vector V₂₃ having an angle of 45° (dotted portions) in the region R₁₁ has four dot data in the primary axis of x. Another vector V₂₄ having an angle of 45° (shaded portions) in the regions R₁₁ and R₀₁ has one dot data in the region R₁₁ and three dot data in the region R₀₁ adjacentt to the region R₁₁ in the forward direction of the subsidiary axis of y, and accordingly, a total of four dot data in te primary axis of x. In Fig. 7c, a vector V₂₅ having an angle of approximately 28.5° (dotted portion) has two dot data in the region R₁₁ and two dot data in the region R₀₁ adjacent to the region R₁₁ in the forward direction of the subsidiary axis of y, and thus also has a total of four dot data in the primary axis of x. Another vector V₂₆ in the region R₁₁ has four dot data. In Fig. 7d, a vector pattern V₂₇ having an angle of approximately 37° has four dot data in the region R₁₁. Another vector V₂₈ also has four dot data in the primary axis of x; one in the region R₁₁ and three in the adjacent region R₀₁. Figs. 8a and 8b are graphs representing vector patterns occupying the section II in Fig. 6. In Fig. 8a, a vertical straight vector V₃₁ (dotted portions) has four dot data in the region R₁₁. Another straight vector V₃₂ (shaded portions) also has four dot data. In Fig. 8b, a vector V₃₃ havig an angle of approximately 58° (dotted portions) has four dot data in the region R₁₁ in the primary axis of y. Another vector V₃₄ has one dot data in the region R₀₁ and three dot data in the region R₁₂ adjacent to the region R₀₁. From the above investigation using specific examples of vector patterns, the following can be derived: when quasi regions each having N × N dots are defined in the display plane of the display unit, any vector pattern, in one quasi region or two consecutive quasi regions in which region includes temporary start dot data and another region is adjacent to the first region in the forward direction of the subsidiary axis shown in Fig. 6, consists of up to N dot data in the primary axis shown in Fig. 6. As a result, it can be seen that the pattern generation at the DDA does not exceed (N + 1) dot data in each period. The present invention is primarily characterized by this feature to by which regular control is realized. On the other hand, since any vector pattern is placed on one quasi region or two consecutive quasi regions as shown in Fig. 6, in which crossed boxes are basic quasi regions and blank boxes are additional quasi regions adjacent thereto, when a single quasi region corresponds to a single word of N × N dots, one or two memory accesses may be required to store the generated dot data up to N dot data in the video memory. To shorten the memory access, even for a two times memory access, and to maintain a constant single memory access time, the present invention uses dual video memories, as shown in Fig. 9. In Fig. 9, each video memory stores data for the diagonal quasi regions in the display plane, i.e., the first video memory MEMORY-A stores data for the quasi regions R₀₀ , R₀₂ , ..., R₁₁ , R₁₃ , ..., e.g., in the pattern of black boxes of a chess board, and the second video memory MEMORY-B stores data for the quasi regions R₀₁ , R₀₃ , ..., R₁₀ , R₁₂ , ..., e.g., in the pattern of white boxes of the chess board. That is, data for adjacent quasi regions are each stored in another video memory, and this allows a parallel memory accessing at one time. Figure 10 is a circuit diagram of an embodiment of a vector pattern processing circuit of the present invention. The vector pattern processing circuit in Fig. 10 includes video memories 1a and 1b, an X address register 2a, a Y address register 2b, an X address counter 3a, a Y address counter 3b, a digital differential analyzer (DDA) 4, a controller 6, and word registers 5a and 5b. The vector pattern processing circuit also includes decoders 11 and 12 for the video memory 1a, decoders 13 and 14 for the video memory 1b, decoders 15 and 16 for the word register 5a, and decoders 17 and 18 for the word register 5b. The vector pattern processing circuit includes a multiplexer 21 for multiplexing the Y address for the video memory 1a, and a multiplexer 22 for multiplexing the X address for the video memory 1a. A multiplexer 24 and a multiplexer 25 are also provided for the video memory 1b. A multiplexer 23 is provided between the video memory 1a and the word registers 5a and 5b, and multiplexer 26 is provided between the video memory 1b and the word registers 5a and 5b. Reference 27 denotes a multiplexer; references 31 to 34 denote AND gates; reference 37 denotes an inverter; references 41 and 43 denote increment circuits; and, references 42 and 44 denote decrement circuits. The increment circuits 41 and 43 and the decrement circuits 42 and 44 are used for designating an adjacent quasi region as set forth above. The multiplexers 21 and 24 select the Y addresses for the video memories 1a and 1b in response to selector signals from the DDA 4. The multiplexers 22 and 25 select the X addresses for the video memories 1a and 1b in response to other selection signals from the DDA 4. The multiplexer 23 selects the dot data to be stored in the video memory 1a from either the word register 5a or the word register 5b, in response to a selection signal from the DDA 4. The multiplexer 26 selects the dot data to be stored in the video memory 1b from either the word register 5a or the word register 5b in response to another selection signal from the DDA 4. The operation of the vector pattern processing circuit in Fig. 10 will be described with reference to Fig. 11, which shows a vector pattern of a start coordinate (x₁₀ , y₁₀) and an end coordinate (x₁₁ , y₁₁) defined in the display plane of the display unit. In this embodiment, each quasi region consists of 4×4 dots. Accordingly, each of the word registers 5a and 5b has a word consisting of 4 × 4 bits, and each word in the video memories 1a and 1b consists of 4 × 4 bits. Upon receipt of the start coordinate (x₁₀ , y₁₀), the controller 6 sets an X coordinate x₁₀ to the X address counter 3a and a Y coordinate y₁₀ to the Y address counter 3b. Then the X coordinate x₁₀ is transferred to the X address register 2a, and the Y coordinate y₁₀ is transferred to the Y address register 2b. A start quasi region R₂₁ in Fig. 11 is defined according to the start coordinate (x₁₀ , y₁₀). Upon receipt of the end coordinate (x₁₁ , y₁₁), the controller 6 sets the same to the DDA 4 and starts the DDA 4. The DDA 4 successively generates dot data along the primary axis, i.e., the x axis for the vector pattern in Fig. 11, in the forward direction of the subsidiary axis and in response to a gradient defined by the start coordinate and the end coordinate. More specifically, first, the DDA 4 determines 1 for the x axis and 1 for the y axis in the region R₂₁. The lower three bits in the X- and Y-address counters are not updated and are maintained at one as an initial state. The lower two bits of the X-address counter 3a are supplied to the word registers 5a and 5b through the decoder 15 and 17. Also the lower two bits of the Y-address counter 3b are supplied to the word registers 5a and 5b through the decoder 16 and 18. The multiplexer 27 selects a third low bit of zero of the X-address counter 3a. The third low bit signal of zero is converted to logical "1" at the inverter and generates a write enable signal WE2 for the word register 5b, together with a clock signal CLK from the DDA 4. As a result, a lst bit, i.e., 0 bit, in the word register 5b is set. Next, the DDA 4 increases the dot pattern by one for the x axis, but does not increase or decrease the pattern for the y axis on the basis of the gradient. The above increment signal for the x axis is supplied to the X-address counter 3a synchronously with a control clock signal CLK c through the AND gate 31. The X-address counter 3a counts up by one. Similar to the above, or 2nd bit, i.e., 1 bit, in the word register 5b is set. The DDA 4 increases the dot pattern by one for the x axis. The X-address counter 3a further counts up one. Thus, the count value therein becomes three. The DDA 4 then generates a value of four, and four pulse signals from the DDA 4 are supplied to the Y-address counter 3b through the AND gate 32 and are counted to four. The third lower bit of the Y-address counter 3b is set at one. The third lower bit having a high level is selected at the multiplexer 27 and generates a write enable signal WE1 for the word register 5a. In this case, the count value of the X-address counter 3a is three and the count value of the Y-address counter 3b is four. As a result, a 15th bit, i.e., 14 bit, in the word register 5a is set. The decoders 15 and 16 determine the above bit number as, for example, 4 × (4 - 1) + (3 - 1) = 14. The DDA 4 also increases the dot pattern by one for the x axis. The count value of the X-address counter becomes four. However, the count value of the Y-address counter is not decreased but is maintained at four. A 16th bit, i.e., 15 (= 4 × (4 - 1) + (4 - 1)) bit, in the word register 5a is set. Subsequently, the controller 6 stops the DDA 4 and starts the store operation of the data in the word registers 5a to 5b into the video memories 1a and 1b, since the X-address counter 3a as the primary axis counter in this embodiment reaches four as a maximum value. During the above operation, the DDA 4 outputs the selection signals to the multiplexers 21, 22, 24, and 25 to designate the addresses to the region R₁₁ in the video memory 1a and the region R₂₁ in the video memory 1b. Also, the DDA 4 outputs the selection signals to the multiplexers 23 and 26 to supply the data in the word register 5a to the video memory 1a and the data in the word register 5b to the video memory 1b. The controller 6 energizes the video memories 1a and 1b to store the data from the word register 5a in the region R₁₁ of the video memory 1a and the data from the word register 5b in the region R₂₁ of the video memory 1b. Both data are stored in a same address in the video memories 1a and 1b. The controller 6 again starts the DDA 4, and the DDA 4 generates four dot data for a next quasi region R₁₂ in Fig. 11. The four bits of 8, 9, 6, and 7 are set in the word register 5b, and the data in the word register 5b is stored in the region R₁₂ of the video memory 1b. In this case, the video memory 1a is not energized. Finally, the DDA 4 generates two dot data for a quasi region R₁₃ in Fig. 11. The two bits of 0 and 1 are set in the word register 5a, and the data in the word register 5a is stored in the region R₁₃ of the video memory 1a. The video memory 1b is not energized. Figures 12a to 12c are timing charts of the above operation. In this embodiment, each DDA cycle is 100 ns, a memory store requires 400 ns, and a machine cycle is 100 ns. In Figs. 12a to 12c, a first calculation for four bit data of 400 ns and a store therefor of 400 ns, represents the regions R₂₁ and R₁₁ , a second calculation represents the region R₁₂ , and a third calculation represents the region R₁₃. These calculation times do not exceed 500 ns, i.e., are up to 400 ns. Each store time is a constant 400 ns. After completion of the data generation, the data stored in the video memories 1a (A) and 1b (B) is alternatively output by the following sequence, as shown in Fig. 9; the data of the region R₀₀ in the video memory 1a (A); the data of the region R₀₁ in another video memory 1b (B); the data of the region R₀₂; the data of the region R₀₃; and so on. The generated video pattern is displayed on the display unit in a conventional form. When the size of the display unit is 1280x1024 PIXELs, as the previously described, the video memories can be constructed by eight 256 kbits memory chips, each of which has a 64 kbits x 4 structure, has a common address line, and has four sets of data, because a four bits address in the primary direction of each word in common and a memory chip having a four bit structure, not a sixteen bit structure as set forth above, is used. That is, eight 256 kbits (64 kbits x 4) memory chips, two address systems, and two word registers are required. The number of the word registers is higher than that used in the prior art described with reference to Fig. 4, but the number of memory chips and the address systems are greatly reduced. The above features of the present invention can be applied to a pipe line vector pattern processing circuit in which the DDA and the memory can operate in parallel, instead of the circuit shown in Fig. 10. Figures 13a to 13c are timing charts of the pipe line vector pattern processing circuit for the vector pattern shown in Fig. 11. Here, the pattern processing time is further reduced.

Claims: A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions, memory units, word register units and a vector pattern generation circuit, characterised in that said display unit has a plurality of quasi regions comprised of first and second quasi regions (R₀₀, R₀₂, ..., R₁₁, R₁₃, ...; R₀₁, R₀₃, ..., R₁₀, R₁₂ , ... ) each forming N x N dots, and said first and second quasi regions are respectively arranged in a chessboard-like arrangement on a display plane of said display unit, where said first quasi regions correspond to white boxes and said second quasi regions correspond to black boxes on the chessboard, and by first and second memory units (1a, 1b) each including a plurality of words formed in a matrix, each word having an N x N bits structure, said words in said first memory unit (1a) corresponding to said first quasi regions and said words in said second memory unit (1b) corresponding to said second quasi regions on said display plane; first and second word register units (5a, 5b), operatively connected to said first and second memory units, each having an N x N bits structure; a vector pattern generation circuit (4) receiving start and end coordinates in said quasi regions defining a vector pattern to be processed, and generating a first dot data of a primary axis for said vector pattern and a second dot data of a subsidiary axis perpendicular to said primary axis in response to a gradient of said vector pattern with respect to said primary axis along said primary axis for every N dots in said primary axis; a bit setting circuit, operatively connected between said first and second word register units and said vector pattern generation circuit, activating one of said first and second word register units (5a,5b) in response to said first and second dot data from said vector pattern generation circuit (4), and setting a bit defined by said first and second dot data in said activated word register unit in each dot data generation time at said vector pattern generation circuit; and a store control circuit (6) which addresses said one word in said one memory unit defined by said start coordinate (X₁₀, Y₁₀) and a second word in the other memory unit other than said word defined by said start coordinate, where said second word corresponds to a quasi region adjacent to a quasi region of said one word in a forward direction of said subsidiary axis, when said bit setting is effected in said word register unit. A vector pattern processing circuit acccording to claim 1, wherein said coordinate in said store control circuit (6) is updated in response to a generation of said first and second dot data at said vector pattern generation circuit (4). A vector pattern processing circuit according to claim 1 or 2, wherein said vector pattern generation circuit (4) includes a digital differential analyser.

Inventors: ANDO, HISASHIGE, KATSUYAMA, MAKOTO, SAKURABA, TAKAHIRO
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G09G1
IPC codes: G06T11, G09G5