METHOD OF TESTING A MODIFIED BOOTH MULTIPLIER, MODIFIED BOOTH MULTIPLIER SUITABLE FOR TESTING BY MEANS OF THIS METHOD, AND INTEGRATED CIRCUIT COMPRISING SUCH A MODIFIED BOOTH MULTIPLIER

Abstract: A modified Booth multiplier for multiplying an m-bit number X by an n-bit number Y comprises a Booth encoder for converter the number Y in groups of 3 bits which ocerlap by 1 bit into series Y′ of multiplication values whose number is equal to or substantially equal to half the number of bits of Y. There is also provided a multiplex circuit for forming partial products from the number X and said series Y′ and a matrix configuration of full adders for adding the partial products in incremental positions. The design is such that the constituent compo­ nents and the operation of the modified Booth multiplier can be tested by means of a very small number of test patterns which are generated in the Booth multiplier after application of a specific series of X,Y-values. Test patterns are generated for establishing static as well as dynamic errors in the combination formed by the Booth encoder and the multiplex circuit and also test patterns which are formed by specific partial products in order to establish static errors in the matrix configuration. In practice the modified Booth multiplier is usually constructed as a multiplier accumulator; in that case test patterns formed by partial products are also used for establishing static errors in the accumulator section.

Description: The invention relates to a method of testing a modified Booth multiplier for multiplying an m-bit multiplicand X = x(m-1)..x(1) x(0), where x(0) is the least-significant bit by an n-bit multiplier Y = y(n-1) ... y(1) y(0), where y(0) is the least-significant bit, which modified Booth multiplier comprises a Booth encoder (24) in which the n-bit multiplier in groups of 3 bits y(i-1) y(i) y(i+1), where i = 0, 2, 4, ... n-2 if n is even and i = 0, 2, 4, ... n-1 if n is odd, while y(-1) and, if n is odd, y(n) have an adjustable value and where the groups overlap each time by 1 bit, is converted into a series of multiplication values Y' = y'(k-2) ... y'(2) y'(0), where k = n if n is even and k = n+1 if n is odd, a multiplex circuit (26) for forming partial products (PPi), and a matrix configuration (28) of full adders for adding the successively obtained partial products in incremental positions, according to which method a number of test patterns is obtained in the modified Booth multiplier on the basis of specifically applied X, Y values, which test patterns produce values on an output of the modified of the modified Booth multiplier which reveal whether the modified Booth multiplier is defective. The design of a modified Booth multiplier should be aimed not only at realizing specific functions in a given structure, but also the testability of the modified Booth multiplier should be taken into account; the hardware of the modified Booth multiplier should be such that its constituent components and its operation can be simply tested. It is always possible, that is to say without taking specific steps, to generate a variety of series of test patterns for supply to the modified Booth multiplier and to test an output thereof as regards the values associated with the relevant test pattern. For a modified Booth multiplier for a substantial number of bits to be processed, the number of feasible test patterns is so large that this method of testing is not very efficient and often even impracticable. The object of the invention is to use a number of test patterns that is less than the number required to test with all possible input combinations a complete modified Booth multiplier. By itself such a multiplier is known from US-A-4,153,938. The principle followed is by generating X and Y inputs for testing in a first step all possible inputs of the Booth encoders and in a second step all possible inputs of the full adders. The idea behind is to apply respective input combinations simultaneously to a maximum possible number of sub-circuits of a complex circuit such as to exhaustively test simultaneously each of the components in a minimum of steps, the test patterns of the directly accessible inputs being such that the appropriate signals at not directly accessible inputs of the components are generated. In principle, such a method is known from Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers, 7th-10th october 1985, pp. 435-438, IEEE, New York, USA; W.T. Chen et al.: A minimum test set for multiple-fault detection in ripple carry adders. However, because each time two successive encoding circuits have one signal in common, the same combinations of y(i-1) y(i) y(i+1) cannot always be simultaneously applied to all encoding circuits. For example, when the combination (110) is applied to a particular encoding circuit, the next encoding circuit that has the last bit of the foregoing encoding circuit in common therewith, must receive a combination (OXX), wherein X conventionally means "don't care", the latter combination thus allowing for four different realizations. According to one of its aspects, the invention as claimed in claim 1 realizes the purpose in that the method is characterized in that test patterns are generated at the X and the Y inputs of the multiplier in accordance with the following table: such that, simultaneously for all groups of 3 bits which overlap by 1 bit successively all 8 input signal combinations are generated, the groups of 3 bits to be simultaneously applied to the Booth encoder forming the Y-part of the test patterns for the Booth encoder and the multiplex circuit, an associated X-part of the test patterns being such that any errors occurring in the Booth encoder or the multiplex circuit are propagatable through the multiplex circuit, there being assigned to the adjustable value of y(-1) and, if n is odd, also of y(n), in the Booth encoder a first value which is associated with a respective test pattern, there being generated further test patterns at the X and the Y inputs such that all 8 input signal combinations are successively applied to the three inputs of the various full adders of the matrix configuration, each time respective input signal combinations being simultaneously applied to a plurality of full adders (FAi) to be tested, a second value which is associated with a relevant test pattern for the matrix configuration being applied to the carry input of the full adders (FA1-FA5) which constitute the first row of full adders of the matrix configuration and to the carry input of the full adder (FA27) which determines the least-significant bit of the product (X.Y) to be obtained. The number of feasible test patterns is determined by the number of bits of X and Y; in principle 2 n+m test patterns can be generated. For testing, however, a much smaller number suffices. By suitably selecting the test patterns, in accordance with the invention of the Booth encoder and the multiplex circuit can be optimally or substantially optimally tested by utilizing only 15 test patterns, for the optimum or substantially optimum testing of the matrix configuration it being sufficient to use 15+2(½k-1) test patterns, ½k being the number of partial products formed in the modified Booth multiplier. Evidently, fewer test patterns can also be used, but in that case fewer components will be tested or components will not be completely tested. Similarly, a larger number of test patterns can be used, for example due to a less favourable choice of the test patterns. Therefore, the invention is not restricted to the number of test patterns stated herein. The number of test patterns required for optimum or substantially optimum testing can also be influenced by the specific construction of the modified Booth multiplier. In a given construction, the matrix configuration can be optimally or substantially optimally tested by means of 17 test patterns, that is to say a number which is independent of the number of partial products formed in the Booth multiplier; the construction of the matrix configuration, however, in that case requires substantially more hardware. When the matrix configuration is combined with an accumulator as is customarily done in practice, in accordance with the invention it is attractive to use 3 further test patterns for optimum or substantially optimum testing. Evidently, a plurality of test patterns may also be used for testing the accumulator. The invention also relates to a modified Booth multiplier as claimed in claim 11. The invention also relates to an integrated circuit, for example a chip, provided with a modified Booth multiplier in accordance with the invention. Brief description of the Figures. The invention will be described in detail hereinafter with reference to the accompanying drawings; therein: Fig. 1 shows a block diagram of a modified Booth multiplier-accumulator; Fig. 2 shows a block diagram of a Booth encoder included in a modified Booth multiplier-accumulator; Fig. 3 shows an embodiment of one of the encoding circuits of the Booth encoder; Figs. 4 and 5 show tables illustrating the operation of the Booth encoder and of the multiplexer circuit included in the Booth multiplier-accumulator, respectively; Fig. 6 diagrammatically shows the multiplex circuit included in the Booth multiplier-accumulator; Fig. 7 shows an embodiment of one of the multiplexers included in the multiplex circuit; Fig. 8 shows the matrix configuration with the accumulator of the Booth multiplier-accumulator; Fig. 9 shows a table containing the test patterns for testing the matrix configuration; Fig. 10 shows a detail of the matrix configuration shown in Fig. 8; and Figs. 11, 12, 13 and 14 show tables containing the test patterns for testing the Booth encoder and the multiplex circuit. Corresponding parts are denoted by corresponding reference numerals in the various Figures. The invention is by no means restricted to the embodiment to be described with reference to the drawings, this embodiment merely serves to illustrate the invention. Construction and operation of a modified Booth multiplier-accumulator. Fig. 1 shows a block diagram of a modified Booth multiplier-accumulator. The multiplier-accumulator comprises an X register 20, a Y register 22, a Booth encoder 24, a multiplex circuit 26, a matrix configuration of full adders 28, and an accumulator 30. The multiplier-accumulator operates in a two's complement digital representation. In the register 20 there is stored an m-bit multiplicand X = x(m-1) ... x(1) x(0), where x(0) is the least-significant bit, and in the register 22 there is stored an n-bit multiplier Y = y(n-1) ... y(1) y(0), where y(0) is the least-significant bit. Normally a multiplication is performed by first forming partial products X.y(i), where i = 0, 1, ... n-1, and by subsequently adding the successively obtained partial products shifted by one bit with respect to one another. In a modified Booth multiplier the number of partial products is substantially reduced. In the Booth encoder 24 the value Y is converted into a series of multiplication values Y = y′(k-2) ... y′(2) y′(0), where y′(i) = y(i) + y(i-1) - 2.y(i+1), where i = 0, 2,... k-2, while in the Booth encoder a bit y(-1) = 0 is added and, if n is odd, also a bit y(n) = y(n-1). In this respect k = n if n is even and k = n+1 if n is odd. In other words, if n is even, the n-bit multiplier is converted into a series of ½n multiplication values and if n is odd, the n-bit multiplier is converted into a series of ½(n+1) multiplication values. Partial products X.y′(i) , where i = 0, 2, ... k-2, are formed by multiplying the multiplicand X by the multiplication values y′(i). This is performed in the multiplex circuit 26. Because the number of partial products is reduced by a factor two or almost two, the product formation by addition of the successively obtained partial products, be it each time shifted by two bits with respect to one another, is simpler. Because y′(i) can assume the values 0, +1, -1, +2 or -2, the partial products PP(i) are obtained by multiplying the multiplicand X by 0, +1, -1, +2, and -2, respectively; these partial products are referred to hereinafter as (0), (+X), (-X), (+2X) and (-2X), respectively. The partial products PP(i) are added in the matrix configuration of full adders 28. The values X.Y successively derived from this matrix configuration can be accumulated in the accumulator 30, if desired; the accumulator then supplies a sum value ΣX.Y . Fig. 2 shows how the Booth encoder 24 of the modified Booth multiplier-accumulator shown in Fig. 1 is composed of a number of encoding circuits which is determined by the number of bits of the multiplier Y. In the Booth encoder 24 the n-bit multiplier in groups of 3 bits which overlap each time by 1 bit is converted into said series of multiplication values Y′. To achieve this, the additional bit y(-1) = 0 and the bits y(0), y(1) are applied to the first encoding circuit, the second encoding circuit receiving the bits y(1), y(2), y(3), the third encoding circuit receiving the bits y(3), y(4), y(5) etc. If n is even, the bits y(n-3), y(n-2), y(n-1) are applied to the last encoding circuit and, if n is odd, it receives the bits y(n-2), y(n-1) and an additional bit y(n) = y(n-1). Fig. 2 shows only four encoding circuits 32, 34, 36 and 38. The multiplier Y in this case consists of 7 bits y(6) ... y(1) y(0), so that the bits y(-1) = 0 and y(7) = y(6) have been added. The bit y(7) is applied via a switch 40 whose function will be described in detail hereinafter but which occupies the position shown in the Figure in the present situation. Each of the encoding circuits 32, 34, 36 and 38 is constructed as shown in Fig. 3. An encoding circuit is composed of five sub-circuits 42, 44, 46, 48 and 50. Each of these sub-circuits receives the bits y(i+1), y(i), y(i-1) and/or their inverse values. The sub-circuit 42 is composed of a specific gate circuit, formed by FETs 52, 54, 56 and 58, a circuit 60 for keeping the output A of the gate circuit at the value 1 when the FETs are turned off, and an inverter 62. When the gate circuit is blocked, the output of the inverter is 0. The output of the inverter 62 becomes 1 if y(i+1) = 0 and the FETs 52 and 54 are turned on, i.e. if y(i) = 0 and y(i-1) = 0, and if y(i+1) = 1 and the FETs 56 and 58 are turned on, i.e. if y(i) = 1 and y(i-1 = 1. Each of the sub-circuits 44, 46, 48 and 50 comprises a specific gate circuit whose operation will be appreciated from the foregoing description of the sub-circuit 42, and also a gat circuit which is similar to the circuit 60 and an inverter which is similar to the inverter 62. The output signals of the sub-circuits 42, 44, 46, 48 and 50 represent the multiplication values 0, +1, -1, +2 and -2, respectively. In the table given in Fig. 4 the multiplication values are given as a function of the input signals of an encoding circuit. The multiplication values y′(i) supplied by the successive encoding circuits are successively applied to the multiplex circuit 26; using these multiplication values, therein an m-bit multiplicand X is converted into an (m+2)-bit partial product PP(i), that is to say in accordance with the table given in Fig. 5. Fig. 6 diagrammatically shows a multiplex circuit 26 in which the partial products can be obtained in conformity with the table shown in Fig. 5, i.e. for a 4-bit multiplicand X. This circuit in principle comprises m+2, so in this case 6, multiplexers 64, 66, 68, 70, 72 and 74, each of which has 5 input positions, corresponding to the number of multiplication values y′(i). The value y′(i) = 0 sets the multiplexers to the position a and the bits 000000 are conducted; the value y′(i) = +1 sets the multiplexers to the position b and the bits x(3) x(2) x(1) x(0) 0 are conducted; the value y′(i) = -1 sets the multiplexers to the position c and the bits are conducted; the value y′(i) = +2 sets the multiplexers to the position d and the bits x(3) x(2) x(1) x(0) 0 0 are conducted; the value y′(i) = -2 sets the multiplexers to the position e and the bits are conducted. Fig. 7 shows an embodiment of a "1-out-of-5" multiplexer. This multiplexer is composed of FETs 76, 78, 80, 82 and 84 and an inverter 86. The FETs can be turned on by the multiplication values y′(i). For example, the value y′(i) = +1 sets the multiplexer to the position b, which means that the FET 78 is turned on so that one of the relevant bits of the partial product to be obtained is conducted. Because of the presence of an inverter 86, the fact that the input signals should be replaced by their inverse values must be taken into account on the input of the 1-out-of-5 multiplexer. The partial products PP(i) successively obtained are applied to a matrix configuration of full adders 28 and are added therein, each time shifted two bits with respect to one antoher. The number of partial products amounts to ½k, where k = n if n is even and k = n+1 is n is odd. The number of bits per partial product amounts to m+2. For correct addition of these partial products, taking into account the sign propagation to be observed in the two's complement representation, use is made of (½k-1) (m+1) + (m+k) full adders which can be arranged, for example in ½k-1 rows of m+1 full adders each, plus a sum row of m+k full adders. A matrix configuration of this kind for four 6-bit partial products PP(1), PP(2), PP(3) and PP(4) is shown in Fig. 8. Therein, m = 4 and n = 7, so that k = 8, with the result that 27 full adders are provided. These full adders are denoted by the references FA1 to FA27. The full adders comprise two inputs p and q for values to be added, a carry input r, a sum output s and a carry output c, where c = (p+q)r + pq and s = c (p+q+r) + pqr . The sum value s is each time vertically passed on in the matrix configuration in known manner, the carry output value c being passed on diagonally. The initial value 0 is applied to the carry input of the full adders FA1 to FA5 and FA27. When the multiplicand X is multiplied by the value y′(i) = -1 or -2, the partial product bit added to the least-significant side will be 1 as appears from the table shown in Fig. 5. Because in two's complement representation a negative value is obtained by inverting the bits of the corresponding positive value, increased by 1, the least-significant bit of the partial products is added to the least-significant bit but one of these partial products in the present embodiment; this is realized in the full adders FA21, FA23, FA25 and FA27. Because the construction and operation of the matrix configuration itself are know, they need not be elaborated herein. The product X.Y output by the full adders FA16 to FA27 is applied to an accumulator 30 which also consists of full adders. Evidently, the number of full adders used depends on the desired capacity of the accumulator; taking into account the sign indication to be observed for the two's complement respresentation, the embodiment shown comprises 14 full adders FA28 to FA41. The construction and operation of the accumulator itself are known and need not be elaborated herein; it is only to be noted that the initial value 0 is applied to the carry input of the full adder FA41. The value output by the accumulator represents the sum of the products obtained as from a given instant, that is to say ΣX.Y . The operation of the modified Booth multiplier accumulator will be further illustrated with reference to an example. Assume that X = 1011, or -5 in two's complement representation and that Y = 1011011, or -37 in two's complement representation. The following groups of 3 bits are then applied to the encoding circuits 32, 34, 36 and 38 shown in Fig. 2: 110, 101, 011 and 110; as appears from the table shown in Fig. 4, the values y′(i): -1, -1, +2 and -1 correspond thereto. When the values are applied to the multiplex circuit as shown in Fig. 6, the partial products PP(1) = 001001, PP(2) = 001001, PP(3) = 101100 and PP(4) = 001001 will be obtained. When these products are applied to the matrix configuration 28 shown in Fig. 8, the full adders FA16 to FA27 will supply the product X.Y = 000010111001 or +185 . When this product is transferred to the accumulator and increased therein by the same value, the full adders FA28 to FA41 will supply the sum product ΣX.Y = 00000101110010 or +370 . Testing the matrix configuration of full adders. Using specifically supplied X,Y-values, in the modified Booth multiplier-accumulator there can be generated test patterns which produce values on an output thereof which reveal whether or not the multiplier-accumulator is defected. By generating a specific series of test patterns, a given set of errors can be tested; these may be errors in the Booth encoder, the multiplex circuit, the matrix configuration and the accumulator, as well as in the connections between these components. However, it will be impracticable to test all feasible errors in these components or the connections therebetween. The errors occurring may be static as well as dynamic. For the matrix configuration and the accumulator it appears to be sufficient to test only for errors of a static nature because the circuits consist of static CMOS transistor logic, while the Booth encoder and the multiplex circuit should be tested for errors having a static as well as dynamic nature because these components consist of dynamic CMOS transistor logic. First the test patterns for the matrix configuration of full adders will be considered. Specifically supplied X,Y-values generate such a number of series of test patterns in the multiplier accumulator that all 8 input signal combinations are obtained at least once on the three inputs of each full adder or at least of the majority of the full adders, groups of full adders always simulatneously receiving the same input signal combinations. In the arrangement of the full adders as shown in Fig. 8 these groups can be formed, as will be described hereinafter, by all full adders of the matrix configuration, by one or more rows of full adders of the matrix configuration, and by full adders which are situated on one or more diagonals of the matrix configuration. For testing the matrix configuration of full adders, the carry input of the first row of full adders in the matrix configuration and the carry input of the full adder which determines the least-significant bit of the product X.Y to be obtained should be accessible so that a similar value, associated with a respective test pattern for the matrix configuration, can be applied to these carry inputs. A test pattern for the matrix configuration is formed by a series of specific partial products as obtained by a normal multiplication of a corresponding specific X value and Y value in the modified Booth multiplier accumulator. Considering the described operation of the Booth encoder and the multiples circuit it will be evident how to select the X values and Y values resulting in a specific series of partial products forming a test pattern. The test patterns for the matrix configuration will be described in detail hereinafter with reference to the matrix configuration 28 shown in Fig. 8 which receives each time a test pattern of in this case four 6-bit partial products, the carry input of the full adders FA1 to FA5 and FA27 thereof receiving the same value associated with a relevant test pattern. The input signal combinations are represented by (P′, p′q′ r′), the signals of said combinations corresponding to those on the inputs p, q, r of the full adders. By applying the test pattern (#0), consisting of the partial products 000000, 000000, 000000 and 000000, the response to the input signal combination (0,0,0) is tested for all full adders FA1 to FA27. The carry input of the full adders FA1 to FA5 and FA27 is then 0. By applying the inverted test pattern (#0-), consisting of the partial products, 111111, 111111, 111111 and 111111, the response to the input signsl combination (1,1,1) is tested for all full adders FA1 to FA27. The carry input of the full adders FA1 to FA5 and FA27 is then 1. By applying the test pattern (#1), consisting of the partial products 111111, 000000, 000000 and 000000, the response to the input signal combination (0,1,0) is tested for the full adders FA1 to FA15, the carry input of the full adders FA1 to FA5 and FA27 being 0. The response to the same input signal combination (0,1,0) albeit now for the full adders FA16 to FA26, is tested by applying the inverted test pattern (#1-), consisting of the partial products 000000, 111111, 111111, and 111111, the carry input of the full adders FA1 to FA5 and FA27 being 1. For the full adder FA27 the response to the input signal combination (0,1,0) is tested by means of the test pattern (#9), consisting of the partial products 000001, 000001, 000001 and 000001, the carry input of the full adders FA1 to FA5 and FA27 being 0. By application of said test pattern (#1-) and the associated setting of the carry input of the full adders FA1 to FA5 and FA27, the response to the input signal combination (1,0,1) is tested for the full adders FA1 to FA15. The response to the same input signal combination (1,0,1) but now for the full adders FA16 to FA26 is tested by applying said test pattern (#1) and the associated setting of the carry input of the full adders FA1 to FA5 and FA27. For the full adder FA27 the response to the input signal combination (1,0,1) is tested by the inverted test pattern (#9-), consisting of the partial products 111110, 111110, 111110 and 111110, the carry input of the full adders FA1 to FA5 and FA27 being 1. By applying the test pattern (#3.1), consisting of the partial products 111111, 000000, 111111 and 111111, the response to the input signal combination (0,1,1) is tested for the first row of full adders, that is to say the full adders FA1 to FA5, the carry input of the full adders FA1 to FA5 and FA27 being 1. The response to the same input signal combination (0,1,1), but now for the second full adders, that is to say the full adders FA6 to FA10, is tested by applying the test pattern (#3.2), consisting of the partial products, 111111, 111111, 000000 and 111111, the carry input of the full adders FA1 to FA5 and FA27 again being 1. The response to the input signal combination (0,1,1), but now for the third row of full adders, that is to say the full adders FA11 to FA15, is tested by applying the test patterns (#3.3), consisting of the partial products 111111, 111111, 111111, and 000000, the carry input of the full adders FA1 to FA5 and FA27 again being 1. For the full adders FA16 to FA25 the response to the input signal combination (0,1,1) is tested by applying the test pattern (#5), consisting of the partial products 111111, 111111, 111111 and 111111, the carry input of the full adders FA1 to FA5 and FA27 being 0. Finally, for the full adders FA26 and FA27 the response to the input signal combination (0,1,1) is tested by applying the inverted test pattern (#7-), consisting of the partial products, 110001, 110001 and 110001, the carry input of the full adders FA1 to FA5 and FA27 being 1. By applying the inverted test pattern (#3.1-), consisting of the partial products 000000, 111111, 000000 and 000000, the response to the input signal combination (1,0,0) is tested for the first row of full adders, that is to say the full adders FA1 to FA5, the carry input of the full adders FA1 to FA5 and FA27 being 0. The response to the same input signal combination (1,0,0), but now for the second row of full adders, that is to say the full adders FA6 to FA10, is tested by applying the inverted test pattern (#3.2-), consisting of the partial products 000000, 000000, 111111 and 000000, the carry input of the full adders FA1 to FA5 and FA27 again being 0. The response to the input signal combination (1,0,0), but now for the third row of full adders, that is to say the full adders FA11 to FA15, is tested by applying the inverted test pattern (#3.3-), consisting of the partial products 000000, 000000, 000000 and 111111, the carry input of the full adders FA1 to FA5 and FA27 again being 0. For the full adders FA16 to FA27 the response to the input signal combination (1,0,0) is tested by applying the test pattern (#4), consisting of the partial products 111110, 000000, 000000 and 000000, the carry input of the full adders FA1 to FA5 and FA27 being 0. By applying the test pattern (#2), consisting of the partial products 000000, 000000, 111111 and 000000, the response to the input signal combination (0,0,1) is tested for the odd rows of full adders, that is to say the full adders FA1 to FA5 and FA11 to FA15, the carry input of the full adders FA1 to FA5 and FA27 being 1. The response to the same input signal combination (0,0,1), but now for the even row of full adders, that is to say the full adders FA6 to FA10, is tested by applying the inverted test pattern (#2-), consisting of the partial products 111111, 111111, 000000 and 111111, the carry input of the full adders FA1 to FA5 and FA27 being 0. For the odd full adders FA17 and FA19 of the most-significant part of the lower row of full adders of the matrix configuration the response to the input signal combination (0,0,1) is tested by applying the test pattern (#6b), consisting of the partial products 000000, 000000, 000000 and 101011, the carry input of the full adders FA1 to FA5 and FA27 being 1. For the even full adders, in this case only the full adder FA18, of said most significant part the response to the input signal combination (0,0,1) is tested by applying the test pattern (#6a), consisting of the partial products 000000, 000000, 000000 and 010111, the carry input of the full adders FA1 to FA5 and FA27 being 1. By applying the test pattern (#8), consisting of the partial products 000011, 000011, 000011 and 000011, the response to the input signal combination (0,0,1) is tested for the even full adders FA20, FA22, FA24 and FA26 of the least-significant part of the lower row of full adders of the matrix configuration, the carry input of the full adders FA1 to FA5 and FA27 being 0. By applying the inverted test pattern (#8-), consisting of the partial products 111100, 111100, 111100 and 111100, the response to the input signal combination (0,0,1) is tested for the odd full adders FA21, FA23 and FA23 of said least-significant part, the carry input of the full adders FA1 to FA5 and FA27 being 1. Finally, for the full adder FA27 the response to the input signal combination (0,0,1) is tested by applying said test pattern (#1-) and the associated value of the carry input of the full adders FA1 to FA5 and FA27. The testing of the full adder FA16 after application of the input signal combination (0,0,1) will be described in detail hereinafter. By applying said test pattern (#2-) and the associated value of the carry input of the full adders FA1 to FA5 and FA27, the response to the input signal combination (1,1,0) is tested for the odd rows of full adders, that is to say the full adders FA1 to FA5 and FA10 to FA15. By applying said test pattern (#2) and the associated value of the carry input of the full adders FA1 to FA5 and FA27, the response to the input signal combination (1,1,0) is tested for the even row of full adders, that is to say the full adders FA6 to FA10. For the odd full adders FA17 and FA19 of the most-significant part of the lower row of full adders of the matrix configuration the response to the input signal combination (1,1,0) is tested by said test pattern (#6a) and the associated value of the carry input of the full adders FA1 to FA5 and FA27. For the even full adders FA18 and FA20 of said most-significant part the response to the input signal combination (1,1,0) is tested by said test pattern (#6b) and the associated value of the carry input of the full adders FA1 to FA5 and FA27. By applying said test pattern (#8-) and the associated value of the carry input of the full adders FA1 to FA5 and FA27, the response to the input signal combination (1,1,0) is tested for the even full adders FA20, FA22, FA24 and FA26 of the least-significant part of the lower row of full adders of the matrix configuration. By applying said test pattern (#8) and the associated value of the carry input of the full adders FA1 to FA5 and FA27, the response to the input signal combination (1,1,0) is tested for the odd full adders FA21, FA23 and FA25 of said least-significant part. Finally, for the full adder FA27 the response to the input signal combination (1,1,0) is tested by said test pattern (#1) and the associated value of the carry input of the full adders Fa1 to FA5 and FA27. The testing of the full adder FA16 for the input signal combination (1,1,0) will be described in detail hereinafter. Fig. 9 shows a table in which the test patterns used are stated for the full adders FA1 to FA27 of the matrix configuration and for all input signal combinations. It appears from this table that for the testing of the full adders FA1 to FA15 and FA17 to FA27 in all eight input signal combinations and for the testing of the full adder FA16 in six of the eight input signal combinations a total number of 21 test patterns is used. Generally, 15 + 2(½k-1) test patterns are required and suffice for this purpose, where½k is the number of partial products generated in the multiplier-accumulator. In the described embodiment ½k = 4. It has been found that no test pattern can be found whereby the full adder FA16 can be tested in the input signal combinations (0,0,1) and (1,1,0). This problem can be solved by providing the modified Booth multiplier-accumulator with an inverter which, for testing the full adder FA16 in the input signal combinations (0,0,1) and (1,1,0), is inserted in the connection to one of the inputs of this full adder by means of an appropriate control signal. To this end, Fig. 8 shows an inverter 88 and a switch 90 which is controlled by a control signal T′. The switch normally occupies the position shown, but when the full adder FA16 is to be tested in the input signal combinations (0,0,1) and (1,1,0) it is set to the position which is not shown; the input signal combinations (1,0,1) and (0,1,0) are then actually applied to the assembly formed by the full adder and the inverter. The full adder FA16 is then tested by means of the test patterns (#1) and (#1-), respectively. The hardware modification introduced thus enables the full adder FA16 to be tested also in the input signal combinations (0,0,1) and (1,1,0), without new test patterns being required. It is to be noted that, in addition to the test patterns used herein, use can also be made of test patterns which have the same effect; however, the number of test patterns required will then usually be greater. For example, in the input signal combination (0,0,1) the full adders FA20, FA22 and FA24 can also be tested by means of the test pattern (#7-) instead of the test pattern (#8) and the full adders FA21, FA23 and FA25 can also be tested by means of the test patterns (#3.3), (#3.2) and (#3.1), respectively, instead of the test pattern (#8-). Similarly, in the input signal combination (1,1,0) the full adders FA20, FA22 and FA24 can also be tested by means of the not previously mentioned test pattern (#7) which consists of the partial products 001110, 001110, 001110 and 001110, the carry input of the full adders FA1 to FA5 and FA27 being 0, instead of by means of the test pattern (#8-), and the full adders FA21, FA23 and FA25 can also be tested by means of the test pattern (#3.3-), (#3.2-) and (#3.1-), respectively, instead of the test pattern (#8). For this method of testing the test pattern (#7) is added, so that for the present embodiment 22 test patterns are used for testing the matrix configuration 28. Testing the accumulator. For the testing of the full adders of the accumulator in six of the eight input signal combinations, use can be made of a number of test patterns which have also been used for testing the full adders of the matrix configuration. The carry input of the full adder determining the least-significant bit of the value to be obtained from the accumulator should then be accessible in a sense that a value associated with the relevant test pattern for the accumulator can be applied thereto. Due to the specific nature of the accumulator, the test patterns should now be supplied in a fixed sequence. The inputs (p,q,r) of the full adders of the accumulator, being the full adders FA28 to FA41 in Fig. 8, are defined as follows: p is the accumulator input, q is the input for the fed back accumulator output, and r is the carry input. For testing the full adders FA28 to FA41 in the input signal combinations (0,0,0), (1,0,0), (0,1,0), (1,1,1,), (0,1,1) and (1,0,1), corresponding to said inputs, said test patterns (#0), (#0-), (#1), (#1-), (#2-) and (#2), respectively, are used in this sequence, the carry input of the full adder FA41 being 0, 0, 0, 1, 1, 1, respectively. For testing the least-significant part of the accumulator, that is to say the full adders FA34 to FA41, in the input signal combinations (0,0,1) and (1,1,0), the test pattern (#10), consisting of the partial products 000100, 000100, 000100 and 000100, and the carry input of the full adders FA1 to FA5 and FA27 being 0, is applied to the matrix configuration twice in succession, the carry input of the full adder FA41 being 0 and 1, respectively after which the inverted test pattern (#10-), consisting of the partial products 111011, 111011, 111011 and 111001 and the carry input of the full adders FA1 to FA5 and FA27 being 1, is applied to the matrix configuration, the carry input of the full adder FA41 being 0. First the even full adders are tested in the input signal combination (1,1,0) and the odd full adders are tested in the input signal combination (0,0,1), after which the odd full adders are tested in the input signal combination (1,1,0) and the even full adders are tested in the input signal combination (0,0,1). The matrix configuration then successively applied the values 10101010, 10101010 and 01010101 to the full adders FA34 to FA41, after which the accumulator output of these full adders outputs the values 10101010, 01010101 and 10101010, respectively. For the testing of the most-significant part of the accumulator, that is to say the full adders FA28 to FA33, in the input signal combinations (0,0,1) and (1,1,0), said test pattern (#6a) is applied, the carry input of the full adders FA1 to FA5 and FA27 being 1, to the matrix configuration twice in succession, the carry input of the full adder FA41 bein 0 and 1, respectively, after which the test pattern (#11), consisting of the partial products 000000, 000000, 000000 and 101000, is applied to the matrix configuration, the carry input of the full adders FA1 to FA5 and FA27 being 0 while the carry input of the full adder FA41 is 0. Furthermore, two inverters 92 and 94 (see Fig. 10) are to be inserted into the connection to a relevant input of the full adders FA28 and FA30 by means of a specific control signal during the testing of the most-significant part of the accumulator in the input signal combinations (0,0,1) and (1,1,0). This situation is shown in Fig. 10; using the control signal "T", the inverters 92 and 94 can be included, via associated switches 96 and 98, in the connection from the full adder FA16 to the full adders FA28 and FA30. As a result, the latter full adders can be tested as if the input signal combinations (1,0,1) and (0,1,1) have been generated. For the testing of the most-significant part of the accumulator in this manner, first the even full adders are tested in the input signal combination (1,1,0) and the odd full adders are tested in the output signal combination (0,0,1), after which the odd full adders are tested in the input signal combination (1,1,0) and the even full adders are tested in the input signal combination (0,0,1). The values 101010, 101010 and 010101 are successively applied to the full adders FA28 to FA33, after which the accumulator output of these full adders outputs the values 101010, 010101 and 101010, respectively. Testing the matrix configuration by means of a constant number of test patterns. The testing of the matrix configuration in the described manner has revealed that the number of test patterns used for testing all full adders of the matrix configuration in all input signal combinations is dependent of the number of partial products. By including further inverters in the same way as described above for the testing of the full adder FA16 and the full adders FA28 and FA30 (see Fig. 10) in the connections denoted by the reference K in Fig. 8, test patterns can be found for testing the rows of full adders, in this case the full adders FA1 to FA15, whose number is independent of the number of such rows of full adders. The inverters are included, using a specific control signal to be applied during the testing of the full adders FA1 to FA15 in the input signal combinations (0,1,1) and (1,0,0), in the connections denoted by the reference K of the full adders FA1, FA2, FA3, FA5, FA6, FA7, FA11, FA12 and in the connections between the sum output of the full adder FA11 and the input of the full adder FA16. The test patterns (#12) and (#12-) used are formed by the partial products 101011, 010100, 101011 and 010100 and by the inverse values thereof, respectively, the carry input of the full adders FA1 to FA5 and FA27 being 0 and 1, respectively. First the series of even full adders, extending in diagonals in the matrix configuration, that is to say the series (FA6, FA12) (FA2, FA8, FA14) and (FA4, FA10) are tested in the input signal combination (1,0,0) and also the series of odd full adders extending in diagonals in the matrix configuration, that is to say the series (FA11), (FA1, FA7, FA13), (FA3, FA9, FA15) and (FA5) are tested in the input signal combination (0,1,1), said series of odd full adders being subsequently tested in the input signal combination (1,0,0) while said series of even full adders are tested in the input signal combination (0,1,1). In other words, two test patterns suffice, regardless of the number of partial products. In this embodiment, comprising a comparatively large amount of additional hardware, 17 test patterns suffice for testing the entire matrix configuration in all input signal combinations. The described method of testing the matrix configuration and the accumulator is independent of the length of the multiplicand X or the multiplier Y. The test patterns result from sepcific X and Y values. These specific X, Y values can be systematically expanded as regards number of bits, without the composition of the test patterns being essentially modified. As a result, the design of the multiplier-accumulator can be parameterized in the length of X and Y, which must be considered as a major advantage. Testing the Booth encoder and the multiplex circuit. The test patterns for the Booth encoder and the multiplex circuit will be described hereinafter. These two components of the multiplier-accumulator both comprise dynamic "pass" transistor logic, so that in principle a test procedure must be created for the case where a single "stuck at one" error occurs as well for the case where a single "stuck at zero" error occurs in said components. At the junction of a number of parallel transistor paths a stuck-at-one error can create an intermediate voltage level, so that the digital value thereof is unknown, while a stuck-at-zero error creates a dynamic storage function at the relevant junction. For the Booth encoder as shown in Fig. 1 and for the encoding circuits contained therein, for example as shown in Fig. 3, it holds good that, assuming the situation in which the voltage on the output of the gate circuits in the sub-circuits shown in Fig. 3 is 1, after application of successively: y(i-1) y(i) y(i+1) = 0 0 0, a stuck-at-one error can be established in the FETs 100 or 106 of the sub-circuit 44, and a stuck-at-zero error in the FETs 52 or 54 of the sub-circuit 42; y(i-1) y(i) y(i+1) = 1 1 1, a stuck-at-one error can be established in the FETs 110 or 112 of the sub-circuit 46 and a stuck-at-zero error in the FETs 56 or 58 of the sub-circuit 42; y(i-1) y(i) y(i+1) = 0 1 0, a stuck-at-one error can be established in the FETs 52 or 118 of the sub-circuits 42 and 48, respectively, and a stuck-at-zero error in the FETs 100 or 102 of the sub-circuit 44; y(i-1) y(i) y(i+1) = 1 0 1, a stuck-at-one error can be established in the FETs 56 or 122 of the sub-circuits 42 and 50, respectively, and a stuck-at-zero error in the FET 112 or 114 of the sub-circuit 46; y(i-1) y(i) y(i+1) = 1 1 0, a stuck-at-one error can be established in the FETs 102 or 104 of the sub-circuit 44 and a stuck-at-zero error in the FETs 116 or 118 of the sub-circuit 48; y(i-1) y(i) y(i+1) = 0 1 1, a stuck-at-one error can be established in the FETs 58 or 120 of the sub-circuits 42 and 50, respectively, and a stuck-at-zero error in the FETs 108 or 110 of the sub-circuit 46; y(i-1) y(i) y(i+1) = 0 0 1, a stuck-at-one error can be established in the FETs 108 or 114 of the sub-circuit 46 and a stuck-at-zero error in the FETs 120 or 122 of the sub-circuit 50; y(i-1) y(i) y(i+1) = 1 0 0, a stuck-at-one error can be established in the FETs 54 or 116 of the sub-circuits 42 and 48, respectively, and a stuck-at-zero error in the FETs 104 or 106 of the sub-circuit 44. Because each time two successive encoding circuits have one input signal in common, the same combinations of y(i-1) y(i) y(i+1) cannot always be simultaneously applied to all encoding circuits. For example, when the combination y(-1) y(0) y(1) = 1 1 0 is applied to the encoding circuit 32 (see Fig.2), a combination y(1) y(2) y(3) where 0 x x, must be applied to the encoding circuit 34. Taking into account this fact, the eight test patterns shown in Fig. 11 can be used for testing the encoding circuits in the Booth encoder. Thus, these test patterns are formed by a specifically supplied Y-value, supplemented by y(-1) and, if n is odd, also by y(n). It is to be noted that in this context no requirements are imposed as regards the X-value. Further requirements as regards the X-value, however, are imposed in view of the propagation of errors through the multiplex circuit; this aspect will be described in detail hereinafter. A single stuck-at-one error in the multiplex circuit results in two conductive FETs. If the relevant input values of these FETs differ, an intermediate voltage level will occur; the inverter 86 (see Fig. 7) of one of the multiplexers of the multiplex circuit recognizes this value as a logic 0 or a logic 1. A single stuck-at-zero error causes the situation in the multiplex circuit in which not one FET is conductive, so that a dynamic storage function arises at the junctions of the multiplexers. The testing for stuck-at-zero errors will be described with reference to the multiplexer shown in Fig. 7, use being made of signal combinations having the following appearance: (x(i-1), x(i), (0), (+1), (-1), (+2), (-2)). For example, assuming that the FET 76 exhibits a stuck-at-zero error, first the output of the inverter 86 is initialized via another FET, for example the FET 78, by applying, for example the test pattern (0,0,0,1,0,0,0), so that the output F of the inverter 86 becomes 0. A second test pattern should then have a path available through the FET 76 to be tested. To this end, for example the test pattern (d,d,1,0,0,0,0) is applied, (where d indicates a don't care state of the relevant bit), resulting in F = 1 if the FET 76 is correct and in an unmodified value of F, i.e. F = 0, if the FET 76 is faulty. Thus, two test patterns are required: one for initializing and one for error detection. A test pattern for error detection, however, can also be used as an initialization test pattern for testing a next FET in the multiplexer. Specific combinations of input values of the encoding circuits in the Booth encoder correspond to the test patterns for initializing and error detection. In the above example, it holds for the initialization test pattern that only the output signal (+1) of an encoding circuit is 1, while it holds good for the error detection pattern that only the output signal (0) is 1, so that the encoding circuit input combinations 010 (or 001) and 000 (or 111), respectively, correspond thereto. For the testing of the stuck-at-zero errors in the multiplexers, for example use can be made of test patterns in a fixed sequence as shown in Fig. 12. The total number of test patterns amounts to 9, regardless of the length of the X,Y values. The first test pattern is used for initialization, it being assumed that the FET 78 is not faulty; this test pattern results in a value F = 0. The second test pattern serves for the testing of the FET 76, but also as an initialization test pattern for the testing of the FET 78. If the FET 76 is correct, F becomes 1; if the FET 76 is faulty, F remains 0. The third test pattern serves for testing of the FET 78. Assuming that the FET 76 was correct, F = 0 if the FET 78 is correct; if the FET 78 is faulty, F remains 1. The fourth test pattern serves as the initialization test pattern for the testing of the FET 80. The FET 80 is tested by means of the fifth test pattern. The sixth test pattern serves for the testing of the FET 82 which forms part of a multiplexer which is connected to an encoding circuit whereto an odd group of 3 bits (being the groups y(-1) y(0) y(1); y(3) y(4) y(5); etc.) is applied. The seventh test pattern serves for the testing of the FET 84 which is associated with a multiplexer which is connected to an encoding circuit whereto an odd group of 3 bits is applied. The eighth test pattern serves for the testing of the FET 82 associated with a multiplexer connected to an encoding circuit whereto an even group of 3 bits is applied (being the groups y(1) y(2) y(3); y(5) y(6) y(7), etc.). Finally, the ninth test pattern serves for the testing of the FET 84 associated with a multiplexer connected to an encoding circuit whereto an even group of 3 bits is applied. This series of test patterns enables parallel testing of all multiplexers in the multiplex circuit. It is to be noted that instead of the bits x(i-1) and x(i) there may be fixed values or, in other words, x(i-1) and x(i) for i = -1, 0 and m may be 0 as appears from Fig. 6 and the table shown in Fig. 5. For stuck-at-one errors in the multiplexers, again two test patterns are used for establishing an error: first a test pattern for the assumption that the intermediate voltage level detected by the inverter 86 is recognized as a logic 0, followed by a second test pattern for the assumption that the intermediate voltage level recognized by the inverter 86 is interpreted as a logic 1. In total 14 test patterns suffice, a possible selection in this respect being shown in Fig. 13. In this case no fixed sequence of the test patterns is required. For example, when the test pattern (1,1,0,0,1,0,0) is applied F will be 0 if no faulty FET is present; however, if F = 1, one of the FETs 76, 78, 82 will be faulty. When the test pattern (0,0,0,0,1,0,0) is applied, F will be 1 if no faulty FET is present; however, if F = 0, one of the FETs 78, 82 will be faulty. Errors in the multiplex circuit should preferably be propagated through the matrix configuration and the accumulator, and errors in Booth encoder through the multiplex circuit and preferably through the matrix configuration and the accumulator. Because the latter two units are composed of full adders, error propagation therein will not be problematic and no special steps will be required. The problem is to ensure that errors in the Booth encoder can pass through the multiplex circuit. An error in the output of the Booth encoder results in an incorrect gate voltage of a FET in the multiplex circuit. A single stuck-at-one error in a gate circuit of a FET in the Booth encoder can result in two FETs in a multiplexer being turned on. A single stuck-at-zero error in a gate circuit of a FET of the Booth encoder can result in a situation in which not a single FET in a multiplexer will be turned on. The propagation problem can be solved by selecting the test patterns for the multiplex circuit and the Booth encoder so that error detection test patterns for "stuck-at" errors in the Booth encoder coincide with test patterns for equivalent "stuck-at" errors in the multiplex circuit. As has already been stated, a stuck-at-one error can be established in the Fets 102 or 104 of the subcircuit 44 of Fig. 3, for example by means of y(i-1) y(i) y(i+1) = 1 1 0. An error of this kind results in a value (+1) = 1, while normally (+2) = 1 for this encoding circuit input signal combination. As a result, the FETs 78 and 82 in the multiplexer shown in Fig. 7 will be simultaneously turned on. Thus, a stuck-at-one error in the Booth encoder has the same consequences as a stuck-at-one error in one of the FETs 78 or 82 of the multiplexer. By selecting the multiplexer test pattern associated with one of these two errors possibilities, it becomes possible to propagate said error in the Booth encoder through the multiplexer. Fig. 14 shows an aexample of test patterns which are suitable for stuck-at-one and stuck-at-zero errors and for the propagation of such errors in the Booth encoder through the multiplex circuit. The table shown in Fig. 14 contains 15 test patterns formed by combining the tables shown in the Figs. 12 and 13. Combination was made possible by the don't care states in the values of x(i-1) and x(i) in the table shown in Fig.12. The first 9 test patterns refer to stuck-at-one errors, and the next 6 patterns refer to stuck-at-zero errors. It will be apparent from the foregoing that different combinations of test patterns are feasible; however, for stuck-at-zero errors a fixed sub-sequence of test patterns will be applicable.

Claims: A method of testing a modified Booth multiplier for multiplying an m-bit multiplicand X = x(m-1)..x(1) x(0) , where x(0) is the least-significant bit by an n-bit multiplier Y = y(n-1) ... y(1) y(0) , where y(0) is the least-significant bit, which modified Booth multiplier comprises a Booth encoder (24) in which the n-bit multiplier in groups of 3 bits y(i-1) y(i) y(i+1), where i = 0, 2, 4, ... n-2 if n is even and i = 0, 2, 4, ... n-1 if n is odd, while y(-1) and, if n is odd, y(n) have an adjustable value and where the groups overlap each time by 1 bit, is converted into a series of multiplication values Y' = y'(k-2) ... y'(2) y'(0) , where k = n if n is even and k = n+1 if n is odd, a multiplex circuit (26) for forming partial products (PPi), and a matrix configuration (28) of full adders for adding the successively obtained partial products in incremental positions, according to which method a number of test patterns is obtained in the modified Booth multiplier on the basis of specifically applied X, Y values, which test patterns produce values on an output of the modified Booth multiplier which reveal whether the modified Booth multiplier is defective, characterized in that test patterns are generated at the X and the Y inputs of the multiplier in accordance with the following table: such that, simultaneously for all groups of 3 bits which overlap by 1 bit successively all 8 input signal combinations are generated, the groups of 3 bits to be simultaneously applied to the Booth encoder forming the Y-part of the test patterns for the Booth encoder and the multiplex circuit, an associated X-part of the test patterns being such that any errors occurring in the Booth encoder or the multiplex circuit are propagatable through the multiplex circuit, there being assigned to the adjustable value of y(-1) and, if n is odd, also of y (n), in the Booth encoder a first value which is associated with a respective test pattern, there being generated further test patterns at the X and the Y inputs such that all 8 input signal combinations are successively applied to the three inputs of the various full adders of the matrix configuration, each time respective input signal combinations being simultaneously applied to a plurality of full adders (FAi) to be tested, a second value which is associated with a relevant test pattern for the matrix configuration being applied to the carry input of the full adders (FA1-FA5) which constitute the first row of full adders of the matrix configuration and to the carry input of the full adder (FA27) which determines the least-significant bit of the product (X.Y) to be obtained. A method as claimed in Claim 1, in which the multiplex circuit is formed by a row of multiplexers, characterized in that or the testing of the combination formed by the Booth encoder and the multiplex circuit use is made of 14 test patterns for possibly occurring stuck-at-one errors and of 9 test patterns for possibly occurring stuck-at-zero errors, each test pattern consisting of a specifically applied Y-value, supplemented by y(-1) and, if n is odd, also by y(n), together with two successive bits x(i-1) and x(i), where i = -1, 0, 1, ... m, which are specifically applied for each multiplexer, the bits x(-2), x(-1) and x(m) having a value during testing which is permanently determined by a relevant multiplication value. A method as claimed in Claim 2, characterized in that the 14 test patterns used for possibly occurring stuck-at-one errors are formed by the values of x(i-1) x(i); y(-1) y(0) y(1) y(2) ... as follows: A method as claimed in Claim 2 or 3, characterized in that the 9 test patterns used for possibly occurring stuck-at-zero errors are formed by the values of x(-1) x(i); y(-1) y(0) y(1) y(2) ... as follows: A method as claimed in Claim 2, characterized in that the 14 test patterns used for possibly occurring stuck-at-one errors and the 9 test patterns for possibly occurring stuck-at-zero errors are combined in order to form a set of 15 test patterns for both types of errors. A method as claimed in any one of the preceding Claims, characterized in that each test pattern for the matrix configuration consists of ½k partial products, a total of 15 + 2(½k - 1) test patterns being used for the testing of all full adders of the matrix configuration, with the exception of the full adder determining the most-significant bit of the product (X.Y) to be obtained, by means of all input signal combinations and the testing of the full adder determining the most significant bit of the product (X.Y) to be obtained by means of 6 of the 8 input signal combinations. A method as claimed in Claim 6, characterized in that the full adder which determines the most-significant bit of the product (X.Y) to be obtained is tested by means of the 2 remaining input signal combinations of the 8 input signal combinations and by inverting one of the input signals of this full adder in addition to the use of 2 of said test patterns used for testing the matrix configuration. A method as claimed in any one of the preceding Claims, where the modified Booth multiplier comprises an accumulator (Figure 8) which is composed of full adders and which is connected to the matrix configuration, characterized in that for the testing of the full adders of the accumulator by means of 6 of the 8 input signal combinations use is made of 6 test patterns also used for testing the matrix configuration, the carry input of the full adder which determines the least-significant bit of the value to be obtained from the accumulator receiving a value associated with a relevant test pattern for the accumulator. A method as claimed in Claim 8, characterized in that for the testing of the full adders of the least-significant part of the accumulator by means of the 2 remaining input signal combinations of the 8 input signal combinations use is made of 2 further test patterns which are a bit-wise inverse representation of one another, a first one of these 2 test patterns being applied to the matrix configuration twice in succession, after which the second one of these 2 test patterns is applied thereto, for the testing of the full adders of the remaining, most-significant part of the accumulator by means of these 2 remaining input signal combinations use being made of a test pattern also used for testing the matrix configuration, the latter test pattern being applied to the matrix configuration twice in succession, after which the testing of the accumulator is continued by applying a further test pattern to the matrix configuration, for the testing of the most-significant part of the accumulator by means of the 2 remaining signal input combinations one of the input signals of the most-significant full adder, the most-significant full adder but two, the most-significant full adder but four, being inverted. A method as claimed in any one of the Claims 1 to 5, characterized in that the number of test patterns used for testing all full adders of the matrix configuration by means of all 18 input signal combinations is independent of the length of the multiplier Y in bits, for the testing of said full adders the following full adder input signals being inverted: the carry input signal of the most-significant full adder of each row and of the most-significant full adder but two, the most-significant full adder but four etc. of the first row of the matrix configuration, and the input signal of the most-significant full adder but one and of the full adder which determines the most-significant bit of the product to be obtained which originates from the sum output of a full adder of a preceding row of full adders, and the input signal of the most-significant full adder but one of the first row, which corresponds to the latter input signal. A modified Booth multiplier for multiplying an m-bit multiplicand X = x(m-1) ... x(1) x(0) , where x(0) is the least-significant bit by an n-bit multiplier Y = y(n-1) ... y(1) y(0) , where y(0) is the least-significant bit, which modified Booth multiplier comprises a Booth encoder (24, 32-38) in which the n-bit multiplier in groups of 3 bits y(i-1) y(i) y(i+1), where i = 0, 2, 4, ... n-2 if n is even and i = 0, 2, 4, .. n-1 if n is odd, while y(-1) and, if n is odd, y(n) have an adjustable value and where the groups overlap each time by 1 bit, is converted into a series of multiplication values Y' = y'(k-2) ... y'(2) y'(0) , where k = n if n is even and k = n + 1 if n is odd, a multiplex circuit (26) which is connected to the Booth encoder for forming partial products (PPi), and a matrix configuration (28) of full adders (FAi) which is connected to the multiplex circuit for adding the successively obtained partial products in incremental positions, characterized in that the Booth encoder comprises a connection for the adjustable value of y(-1) and, if n is odd, also for y(n) via which connection a first value associated with a relevant test pattern is applied to the Booth encoder, there also being provided a connection for the carry input of the full adders (FA1-FA5) which constitute the first row of full adders of the matrix configuration and for the carry input of the full adder (FA27) which determines the least-significant bit of the product (X.Y) to be obtained, and via which connection a second value associated with a relevant test pattern for the matrix configuration is applied to the relevant full adders, that the matrix configuration comprises an inverter (88) ad switching means (90) for switching the inverter, in the connection to one of the three inputs of the full adder (FA16), determining the most-significant bit of the product (X.Y) in order to test the full adder by means of further two predetermined input signal combinations (001, 110) of the eight feasible input signal combinations without new test patterns being required at the X and the Y inputs. A modified Booth multiplier as claimed in Claim 11, comprising an accumulator which is connected to the matrix configuration and which consists of full adders (FA28 - FA41), characterized in that there is provided a connection for the carry input of the full adder (FA41) which determines the least-significant bit of the value to be obtained from the accumulator, a value associated with a relevant test pattern for the accumulator being applied via said connection. A modified Booth multiplier as claimed in Claim 12, characterized in that the accumulator (FA28 - FA41) comprises inverters (92, 94) and switching means (96, 98) for switching these inverters, in order to test the most-significant part (FA28 - FA30) of the accumulator by means of two predetermined input signal combinations of the eight feasible input signal combinations, in the connection to the relevant inputs of the most-significant full adder, the most-significant full adder but two, the most-significant full adder but four, etc. A modified Booth multiplier as claimed in Claim 11, characterized in that the matrix configuration (28) comprises inverters and switching means (K) for switching the inverters, in order to test the matrix configuration, in the connection to the following full adder inputs: the carry input of the most-significant full adder (FA1, FA6, FA11) of each row, of the most-significant full adder (FA2, FA7, FA12, FA17) but two, of the most-significant full adder but four, etc. of the first row of the matrix configuration, and the input of the most-significant full adder but one of each row, and of the full adder which determines the most-significant bit of the product to be obtained and which is intended to receive the sum signal of a full adder of a preceding row of full adders, or a substitute signal when the first row of full adders is concerned. An integrated circuit comprising the modified Booth multiplier as claimed in any one of the Claims 11 to 14.

Inventors: BEENKER, FRANCISCUS PETRUS MARIA, HUISKEN, JOSEPHUS ANTONIUS, MATTERNE, LUC LEO GHISLAIN, STANS, RUDI JOSEPHINE JAAK, VAN MEERBERGEN, JOZEF LOUIS
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: G06F11
IPC codes: G06F11, G06F7, H01L21