PSK system and modem

Abstract: A modem system is disclosed which has an improved re­ liability of detection of PSK data using a simple signal delay detection scheme. A transmission signal is produced which has a phase reference portion provided at at least one of the front and rear portions of a time slot. In a first half of the remaining portion of the time slot the phase of the transmission signal changes stepwise in a first predetermined direction for a "mark" state while in a second half of the remaining portion it changes stepwise back to the reference value. For a "space" state the phase changes stepwise in a second predetermined direction, oppo­ site the first , in the first half of the remaining portion and then in the second half it changes stepwise back to the reference value. In a second aspect of the invention only one of the two digital states causes a corresponding phase change while for the other state the transmission signal retains the phase reference value throughout the time slot.

Description: 1. Field of the Invention This invention relates to modem systems, and more particularly to a modem system in which a PSK modulation is used for transmission of digital data and, on the signal receiving side, delay demodulation is used to obtain the original digital data. 2. Brief Discussion of the Art In a conventional PSK digital signal transmission system, a signal to be transmitted is PSK-modulated on the signal transmitting side and, on the signal receiving side, the signal is demodulated to obtain the original digital data. In PSK modulation systems, the digital signals "0" and "1" are transmitted in correspondence to the phase of a carrier, and the C/N ratio deterioration is minimized. Because of its excellent signal characteristics, the PSK modulation system is extensively employed for transmission of digital signals. The PSK modulation system will be described in more detail. Usually one of a so-called MSK system, as shown in Fig. 7, or a so-called DSK system, as shown in Fig. 8, are employed for PSK modulation. In the MSK system, when a signal is in "mark" state, the phase is linearly increased by 180° for one time slot period of the signal; and when the signal is in "space" state, the phase is linearly decreased by 180° for one time slot period. In the DSK system, when a signal is in "mark" state, the phase is increased in two steps, i.e., one time slot period of the signal is divided into two parts and, in each part, the phase is increased by 90°; and when the signal is in "space" state, the phase is decreased in two steps., i.e., in each part, the phase is decreased by 90°. The MSK system is advantageous in that the occupied bandwidth is small because the phase changes continuously. The DSK system is suitable for wideband data transmission, because it is substantially free from multi-path fading. In general, a delay detection system or a synchronous detection system are employed for demodulation of the signals which are PSK-modulated as described above. In the delay detection system, a signal received is divided into two parts. One part is applied directly to a phase comparator, while the other is supplied through a delay circuit to the phase comparator. In the delay circuit, the signal is delayed by one (1) or halt (1/2) signal period of the modulation. Thus, by comparing the relatively delayed signals the PSK-modulated signal is demodulated into the original digital signal. In an effort to improve reliability of data detection using a delay detection device, applicants proposed in EP-A-0254175 , entitled "PSK-System and - Modem", filed July 13, 1987 and claiming Convention priority of 14.07.1986, the disclosure of which is prior art in accordance with Art, 54.3 and 54.4 EPC, a modem system in which a phase reference part having a predetermined period of time in total is provided at the front and/or rear of a time slot of the digital pulse signal and the phase of the pulse signal is changed to a predetermined value according to a predetermined monotone function in the first half of the remaining period of time of the time slot, and then changed later in the time slot in the opposite direction to a reference value, with the phase change in the first half of the remaining period time being effected in a first, e.g., increasing, direction in correspondence to a "mark" state of the signal and in a second opposite, e.g., decreasing, direction in correspondence to a "space" state, and the signal thus transmitted is received and divided into two parts and one of the two parts is compared in phase with the other after being delayed, to obtain the original digital pulse signal. In the just-described system, the reference phase part is so determined as to occupy a half (1/2) or quarter (1/4) of one time slot of the digital pulse signal to perform the delay detection. However, in such a modem system, as the carrier frequency variation Δ Ω increases, the variation Δ Ω x T/2 or Δ Ω x T/4 of the reference operating point of the phase comparator increases so greatly that the stability of the delay detection is not considerably improved. Therefore, the carrier frequency should be so determined that the stability is not adversely affected by the variation Δ Ω. Also, in the demodulated signal obtained in the modem system described in aforementioned EP-A-0254 175 the positive phase part is shifted by 1/2 time slot from the negative phase part. Therefore, for instance, in the case where, as shown in Fig. 1, "mark" signals occur successively, they may be mistaken for a succession of "space" signals if the timing is shifted only a 1/2 time slot. Where, in contrast, "space" signals occur successively, they may be mistaken for a succession of "mark" signals. This difficulty may be overcome by transmitting a predetermined signal train on the transmitting side, and detecting the signal train on the receiving side to determine the timing, so that the demodulated signal is accurately identified. However, the method is not suitable for high-speed communication, because it is necessary to transmit the signal required for the determination of the timing in addition to the data which are originally to be transmitted, with the result that the data transmission density is decreased. Furthermore, on the signal receiving side, it is necessary to provide a processing time for determination of the timing. Also, the same signal must be transmitted several times as the case may be, which further increases the data transmission time. The object of this invention is to provide a modem system in which a PSK-modulated signal can be readily and accurately demodulated using a delay detection system, and the data transmission density can be increased while the data transmission time can be decreased. This object is achieved by a modem system , in which a phase modulation is carried out in such a manner that, in correspondence to one of the "mark" and "space" states of a transmission signal, reference phase parts having a predetermined period of time in total are provided in the front and/or rear part of a time slot of a digital pulse signal, and in the front half of the remaining part of the time slot the phase thereof is changed in a predetermined direction while in the rear half the phase is changed in the opposite direction to a reference phase, and, in correspondence to the other state of the transmission signal, only the reference phase part is formed over the entire time slot of the digital pulse signal. In a preferred embodiment of the invention, a signal is transmitted which is phase-modulated in such a manner that, in correspondence to one of the "mark" and "space states of a transmission signal, reference phase parts having a predetermined period of time in total are provided in the front and/or rear part of a time slot of a digital pulse signal, and in the front half of the remaining part of the time, slot the phase thereof is changed in a predetermined direction while in the rear half the phase is changed in the opposite direction to a reference phase, and in correspondence to the other state of the transmission signal, only the reference phase part is formed over the entire time slot of the digital pulse signal, and the signal thus transmitted is divided into two parts when received, so that one of the two parts is delayed and compared, in phase, with the other, to provide an output signal, which is subjected to full-wave rectification to obtain an NRZ signal. The above and other objects advantages and features of the invention will become more readily apparent from the following detailed description which is provided in connection with the accompanying drawings. Fig. 1 is a waveform diagram showing a demodulated signal in which the phase change of "mark" periods is opposite to that of "space" periods; Figs 2(A), 2(B), 2(c) and 2(D) are diagrams for a description of a modulation system according to another embodiment of this invention; Fig. 3(A), 3(B), 3(C), 3(D) and 3(E) are diagrams for a description of a demodulation system which may be used in accordance with the Fig. 2 embodiment; Fig. 4 is an electrical circuit diagram showing one example of a demodulation circuit; Figs. 5 and 6 are electrical circuit diagrams showing other examples of the demodulation circuit; Fig. 7 is a hybrid circuit for generating a modulation signal in accordance with one of the embodiments of the invention; Fig. 8 is a control circuit for the hybrid circuit of Fig. 7; and Fig. 9 are timing diagrams for explaining the operation of Fig. 7. A detailed description will now be provided of the invention. Figs. 2(A), 2(B), 2(C) and 2(D) are diagrams showing examples of a modulation system according to the invention. In Figs. 2(A) and 2(B), reference phase parts having periods of time t₁ and t₂ are provided before and after a phase variation part of a modulation signal, respectively. The periods of time t₁ and t₂ are so determined as to meet the following equation: t₁ + t₂ = Δ T where Δ T is the predetermined period of time shorter than one time slot of a digital signal. In the remaining part of the time slot, the phase is changed as follows: In the case of the "mark" state of the signal, as shown in Fig. 2(A), the phase is changed to a predetermined value ϑ at the beginning of the period and to zero at the end of the period; and in the case of the "space" state, as shown in Fig. 2(B), the phase is maintained at zero (i.e., the phase is not changed at all). Figs 2(C) and 2(D) show the case where the periods of time t₁ and t₂ are set to Δ T and 0, respectively. The phase change in the remaining part is the same as in the case of Figs. 2(A) and 2(B). It should be noted that the signal characteristic of signals of Figs. 2(A) and 2(B) are equal to those of the Figs. 2(C) and 2(D) signals. That is, the characteristic is maintained unchanged as long as the condition t₁ + t₂ = Δ T is satisfied, as described later. Therefore, to simplify description only the signals of Figs. 2(C) and 12(D) will be described, with a delay time TR set to Δ T. Fig. 2(c) shows a "mark" signal, and the phase (t) is ϑ ₀ with 0 ≦ t < Δ T, ϑ ₀ + g(t - Δ T) with ΔT ≦ t < Δ T + T'/2, and ϑ ₀ + g(T - t) with ΔT + T' /2 ≦ t < T. Fig. 2(D) shows a "space" signal, and the phase ϑ (t) is ϑ ₀ with 0 ≦ t < T . The function g(t) is the phase variation function, and includes not only a phase which changes continuously, but also a phase which changes stepwise. Furthermore, T'/2 is a half of the period of time of the remaining part of the time slot which is other than the reference phase part. Fig. 3(A), 3(B), 3(C), 3(D) and 3(E) are diagrams for a description of the demodulation of the above-described modulated signal. In this case, the signal is supplied in the order of "mark", "mark" and "space". A signal ϑ (t) corresponding to "mark", "mark" and "space" as shown in Fig. 3(A) is applied to one input terminal of a phase comparator, and a signal ϑ (t - Δ T) which lags the signal ϑ (t) by a predetermined period of time Δ T is applied to the other input terminal of the phase comparator. Accordingly the difference a (t) - ϑ (t - Δ T) between the two signals is ϑ for the first period Δ T of the time slot corresponding to the "mark" state, and -ϑ for the next period Δ T, and zero (0) for the entire time slot corresponding to the "space" state. As shown in Fig. 3(E), according to the characteristic of the phase comparator shown in Fig. 3(D), the output level is set to V₁ for the first period Δ T in the time slot corresponding to the "mark" state and to V₂ for the last period Δ T, and to V₃ for the entire time slot corresponding to the "space" state. Accordingly, when a DC component is eliminated from the output signal shown in Fig. 3(E), as shown in Fig 3(F), and an NRZ signal (Fig. 3(G)) can be formed according to the fact that, in a time slot, the level is changed from positive to negative for the "mark" state and is maintained at zero for the "space" state, the original digital data can be obtained. The above-described delay demodulation can be readily achieved with one of the demodulation circuits shown in Figs. 5 and 6. Fig. 4 is an electrical circuit diagram showing one example of a demodulation circuit according to the invention, In the circuit, an input signal V in is applied to a Schmitt trigger circuit 1, the output signal of which is applied to a delay circuit 2 having a delay time ΔT. The output signal of the Schmitt trigger circuit 1 is further applied to the clock input terminal of D-type flip-flop 3. The output signal of the delay circuit 2 is supplied to the clock input terminal of a D-type flip-flop 4. The Q output signal of the D flip-flop 3 is applied to the D input terminals of the flip-flops 3 and 4. The Q output signals of the D flip-flops 3 and 4 are supplied to an XNOR (EXCLUSIVE NOR) gate 5 for phase comparison. The output signal of the XNOR gate 5 is supplied through a low-pass filter 6 and a Schmitt trigger circuit 7 to a capacitor 8, so that a DC component is eliminated from the output signal. The output signal of the capacitor 8 is applied to a comparator 9, where it is compared with a reference voltage V n . The output signal of the comparator 9 is subjected to full-wave rectification, so that the NRZ signal as shown in Fig. 3(G) is obtained. As is apparent from the above description, in the embodiment of Fig. 4, the signal is transmitted which is modulated in such a manner that the phase is changed in correspondence to the "mark" signal and is not changed at all in correspondence to the "space" signal, and the signal thus transmitted is divided into two parts when received, to perform the delay detection. Therefore, in the digital transmission according to the invention, even if the timing is somewhat shifted, there will be no possibility that the "mark" and "space" signals are mistaken for each other. It is unnecessary for the embodiment of Fig. 4 to use a synchronizing clock reproducing circuit, a stabilizing circuit, and an NRZ demodulation section. Therefore, the system can be considerably simplified and miniaturized; that is, it is advantageous in that it can be readily installed on a vehicle. In the just described embodiment of the invention, the signal whose phase is not changed at all is transmitted for the "space" signal; however, instead, that signal may be transmitted for the "mark" signal. Furthermore, the NRZ signal can be obtained by using a D flip-flop instead of the full-wave rectifier circuit, or by using an XNOR gate. That is, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention. As was described above, according to the invention, the phase modulation is carried out in such a manner that, in correspondence to one of the "mark" and "space" state of the transmission signal, the reference phase parts having the predetermined period of time in total are provided in the front and/or rear part of the digital pulse signal, and at least in the front half of she remaining part of the time slot the phase is changed in the predetermined direction in correspondence to the "mark" state of the transmission signal, and in correspondence to the "space" state the phase is not changed at all. Therefore, the difficulty that the digital data are mistaken in identification after demodulation can be positively prevented. Furthermore, according to another aspect of the invention, a signal is transmitted which is phase-modulated in such a manner that in correspondence to one of the "mark" and "space" states of the transmission signal, reference phase parts having a predetermined period of time in total are provided in the front and/or rear part of a time slot of the digital pulse signal, and at least in the front half of the remaining part of the time slot the phase is changed in the predetermined direction in correspondence to the "mark" state of the transmission signal, and in correspondence to the other state the phase is not changed at all; and the signal thus transmitted is divided into two parts for delay detection when received. Therefore, irrespective of the timing, the "mark" and "space" signals can be accurately detected according to whether or not the phase changes in a time slot of the signal, and the data transmission density can be increased while the data transmission time can be decreased. Furthermore, since a synchronizing clock reproducing circuit, a stabilizing circuit, and an NRZ demodulation section can be eliminated, the system is simple in arrangement and small in size. Figs. 7 and 8 depict circuits suitable for generating the modulation signal patterns of Figs. 2(C) and 2(D) and 3(A), while Fig. 9 depicts the timing diagrams for signals at various points in Fig. 8. A hybrid circuit 101 is used to shift the phase of an incoming signal V in depending on the states of applied control signals D₁ and D₂ which are generated by the circuit of Fig. 8 A clock source 103 supplies clock pulses V c2 and inverter 107 also supplies inverted clock pulses V c2' . The clock pulses V c2 trigger flip-flop 105 to produce output pulses V ci which are applied to AND gate 115 together with clock pulses V c2 . The output of AND gate 115 is supplied together with data v s source 109 to AND gate 113. The inverted clock pulse V c2i and data signals V s are also supplied to AND gate 111. The output of AND gate 111 supplies the signal D₁, while the output of AND gate 113 supplies the signal D₂. The relationships of the various signals and the resultant modulated signal Θ (t) are all shown in Fig. 9.

Claims: A modem system for digital data comprising; means for producing a transmission signal which is phase-modulated in accordance with "mark" and "space" states of a digital signal in repetitive digital time slots (T), each of a predetermined duration, said transmission signal having a phase reference period of predetermined duration (t₁+t₂) provided at at least one of the front and rear portions of each of said time slot (T), and in the front half of the remaining period of each said time slot (T) a phase which changes for one of said states of said digital signals from a reference value (0) to a predetermined value (π) in a predetermined direction, while in the rear half of the remaining period a phase which changes in the opposite direction back to said reference yalue (0), and in correspondence to the other state of said digital signal, only said reference phase part is formed over the entire time slot of said transmission signal. A modem system as set forth in claim 1, comprising means for demodulating said transmission signal to reproduce said digital signal, said demodulating means comprising: means for dividing said transmission signal into two signals, means (2) for delaying one of said two signals relative to the other, and means (5) for comparing said relatively delayed signals to produce a signal representative of said digital signal. A modem system as in Claim 2 wherein said demodulating means further comprises means (6-10) receiving the output of said comparing means (5) for converting said output into an NRZ digital signal. A modem system as in Claim 3, wherein said converting means (6-10) comprises mean (8) for removing a DC component from the output of said comparing means (5), comparator (9) or comparing an output of said removing means (8) with a preset value, and means (10) responsive to the output of said comparator (9)for providing an NRZ digital signal. A modem system as in Claim 4, wherein said providing means is a full wave rectifier (10).

Inventors: SHIBANO YOSHIZO C O OSAKA WORK, SHIBANO, YOSHIZO C/O OSAKA WORKS
Applicants: SUMITOMO ELECTRIC INDUSTRIES, SUMITOMO ELECTRIC INDUSTRIES LIMITED
Application year: 1987
Main classification: H04L27
IPC codes: H04L27