PLASTIC MOLDED PIN GRID CHIP CARRIER PACKAGE

Abstract: An improved plastic molded chip carrier package for a semiconductor chip [1,40] has a plurality of I/O pins [20,60] arranged on a pin grid array. The pin grid array comprises at least two row of the I/O pins [20,60] disposed along the sides of the chip [1,40] in such a manner that the I/O pins [20,60] are staggered with respect to those in the other row. The staggered arrangement of the I/O pins [20,60] makes it easy to provide electrical interconnection between the I/O ports on the chip [1,40] and the corresponding I/O pins [20,60] without requiring an elaborate or crowded wiring or connection lines. This is particularly effective when an increased number of the I/O pins [20,60] are required to be included in the limited area of the chip carrier.

Description: The present invention is directed to a plastic molded pin grid chip carrier package with the features of the preamble of claim 1 as known from SOLID STATE TECHNOLOGY, vol. 25, no. 6, June 1982, pages 94-100, New York US. Pin grid array packages for semiconductor chips have been widely accepted in the art to replace ceramic packages for their feasibility of incorporating a plurality of I/O pins at the time of molding the package and for thermal compatibility with a conventional printed-circuit boards on which the packages are frequently required to be directly mounted. Such pin grid array plastic packages have been proposed, for example, in US-A-4 618 739 in which a chip carrier is molded from a suitable plastic material to integrally include a plurality of I/O pins. It is the object of the present invention to provide a plastic molded chip carrier package in which the plastic substrate with a pattern of conductor lines can be properly registered on the carrier member by better utilization of the soldering pits formed in the carrier member. The invention will become more apparent from the following description of an embodiment when taken in conjunction with the attached drawings, wherein Fig. 1 is a cross sectional view of a plastic chip carrier package in accordance with the present invention; Fig. 2 is a top view of the above package; Fig. 3 is a cross sectional view of the package of Fig. 1 before receiving the chip; and Fig. 4 is a bottom view of a plastic substrate employed in the package of Fig. 1. Fig. 1 shows a plastic molded plastic chip carrier package in accordance with the present invention. The package comprises a flat shaped carrier member 50 having a center recess 51 for mounting therein a semiconductor chip 40, a plurality of I/O pins 60 arranged on a pin grid to extrude from the bottom surface of carrier member 50. The carrier member 50 is molded from a suitable heat resistive thermoplastic or thermosetting plastic material into a flat rectangular configuration by a conventional injection or transfer molding technique. Suitable heat-resistive thermoplastic material includes polyphenylene sulphide, polysulphone, polyethersulphone, and polyarylsulphone. Suitable thermosetting plastic material includes phenol, polyimide, and epoxy resins. As shown in Fig. 2, the pin grid array comprises two rows of the I/O pins 60 arranged on each of the four sides of the carrier member 50. The I/O pins 60 in each row are spaced on 2,54 mm (100-mil) centers and staggered with respect to those in the adjacent row so that only one of the I/O pins 60 in one row is located along the spacing between the two adjacent I/O pins 60 in the other row. Each of the I/O pins 60 are electrically interconnected to the individual pads or I/O ports 2 on the chip 40 by wire elements 3 utilizing a known wire bonding technique. It is noted at this point that because of the staggered arrangement of the I/O pins 60, the wire elements 3 can be directed substantially straight from the I/O pins 60 to the corresponding pads 2 so as to avoid crossing of the wire elements 3, giving rise to easy and reliable wireability, which is most desirable when the carrier member 50 includes an increased number of I/O pins 60. A plastic substrate 70 is utilized for electrical interconnection between the semiconductor chip 40 and the plurality of I/O pins 60. The I/O pins 60 have their top ends recessed from the top surface of the carrier member 50 so as to provide thereat a corresponding number of solder pits 55, as shown in Fig. 3. The plastic substrate 70 is made from a thermosetting resin such as polyimide or glassfiber reinforced epoxy resin to be in the form of a thin plate or sheet having a center opening 71 smaller than the planar dimension of the chip 40. Deposited on the bottom surface of the plastic substrate 70 is a trace pattern of conductor lines 72, as shown in Fig. 4, which extend from the outer periphery of the plastic substrate 70 and terminate in individual bonding leads 73 with solder bumps spaced evenly along the four sides of the center opening 71. Respectively formed in the conductor lines 72 at the peripheral portion of the plastic substrate 70 are other solder bumps 75 which are in registration with the solder pits 55 and the I/O pins 60. The plastic substrate 70 thus formed is placed over the carrier member 50 so that the solder bumps 75 of the conductor lines 72 fit into the respective solder pits 55 at the same time the bonding leads 73 thereof are in contact with the pads 41 of the chip 40. Subsequently, the package is subjected to reflow soldering for permanent joinder at the respective connections. Since the solder pits 55 receive the respective solder bumps 75 on the conductor lines 72 they serve to easily register the conductor lines 72 with the I/O pins 60 as well as with the pads 41 on the chip 40. Additionally, with the provision of the solder pits 55, the solder bumps 75 received therein undergo the melting within the confine thereof so as to be prevented from flowing over the top surface of the carrier member 50 and reaching the adjacent conductor lines 72, thus improving the wireability. It is noted in this connection, the plastic substrate 70 itself is only secured at the soldering connections and is relatively free at the interface with the carrier member 50 so that it can well take up the thermal strain when there is a thermal mismatch between the materials forming the carrier member 50 and the plastic substrate 70. Preferably, the plastic substrate 70 is made from the same thermosetting resin as the carrier member 50. The solder connection between the I/O pins 60 and the conductor lines 72 may be made by providing solder in each of the solder pits 55 or on the top of the I/O pins 60 instead of forming the solder bumps 75 on the conductor lines 72. The package of this embodiment is sealed by a transparent plate 81 of glass or resin which is secured to the top of the carrier member 50 in spaced relation with the chip 40 and the plastic substrate 70.

Claims: A plastic molded chip carrier package comprising: a carrier member (50) made of a plastic material and provided in the center of its top surface with a rectangular chip recess for mounting an integrated circuit chip (40) therein; a plurality of I/O pins (60) having their top end portions integrally embedded into said carrier member (50) outwardly of said chip recess and protruding downwardly from the carrier member (50); and a plastic substrate (70) mounted on the top surface of the carrier member (50), said plastic substrate (70) formed on its bottom surface with a pattern of conductor lines (73) for electrical interconnection between the chip (40) and the I/O pins (60) ; characterized in that each of said I/O pins (60) has its top recessed from the top surface of the carrier member (50) so as to form thereat a solder pit (55) for receiving a solder bump (75) formed on the bottom surface of the plastic substrate (70) for reflow soldering to the corresponding I/O pin (60), whereby the I/O pin (60) is electrically connected to the corresponding conductor line (73) by the solder bump (75) in said solder pit (55) while the plastic substrate (70) rests on the top surface of the carrier member (50). Chip carrier package of claim 1, charcterized in that said I/O pins (60) being arranged in plural rows along the sides of the chip recess in such a manner that the I/O pins (60) in each of the rows are uniformly spaced apart and are staggered with respect to the I/O pins (60) in the adjacent row. Chip carrier package of claim 1 or 2, characterized in that said plastic substrate (70) is a thin plate made from a thermosetting resin. Chip carrier package of any preceding claim, characterized by including a transparent covering material (81) which is placed on the top surface of the carrier member (50) for sealing the chip (40), the plastic substrate (70), and the electrical interconnection therebetween. Chip carrier package of claim 4, characterized in that said transparent covering material (81) is a glass plate spaced from the chip (40) and its electrical connection to the I/O pins (60).

Inventors: HIRATA, ATSUOMI, MORII, KENSAKU, NAKAMURA, YOSHIHIKO
Applicants: MATSUSHITA ELECTRIC WORKS, LTD.
Application year: 1987
Main classification: H01L23
IPC codes: H01L23