HETEROJUNCTION SEMICONDUCTOR DEVICE

Abstract: A heterojunction semiconductor device comprises an unipolar transistor comprising, a collector layer (3), a base layer (5), a collector side barrier layer (4) provided between said collector layer (3) and base layer (5), an emitter layer (8), and an emitter side barrier layer (7) provided between said base layer (5) and emitter layer (8) and having a thickness for tunneling a carrier from said emitter (8) and base (5) layers, said carrier being injected into the base layer (5) according to the application of a predetermined voltage between said emitter and base, said base layer (5) having a superlattice means (6), comprising a plurality of thin barrier layers (6B) and thin well layers (6W) for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction semiconductor device, more particularly, it relates to a high speed heterojunction semiconductor device having negative resistance and multi-functions, for example, logic operation, multi-valued memory, etc. 2. Description of the Related Art Recently, the study and development of semiconductor devices using a superlattice formed by laminating barrier layers and well layers has increased. It is well known that the superlattice has interesting properties. For example, the property of a mini-band gap. Figure 1 shows an energy band diagram explaining a mini-band gap. In Fig. 1, SL denotes a superlattice, SLB a barrier layer, SLW a well layer, E C the bottom of a conduction-band, MB A and MB B mini-bands, Eg a mini-band gap, ▵E the position of the mini-band gap, DX a distance, and a and b periods. In this superlattice, the mini-band gap Eg and the position ▵E thereof are changed by changing the periods a, b and the material thereof. Conventionally, it is known that a semiconductor device using the mini-band gap in the superlattice as a barrier to electrons which are injected is a two terminal element having a modulation superlattice. Figure 2 shows an energy band diagram of a modulation superlattice wherein the same reference marks as used in Fig. 1 denote the same elements. In Fig. 2, MSL and el denote a modulation superlattice and injected electrons. As is apparent from Fig. 2, in this modulation superlattice MSL, by changing the periods a, b together with the distance DX, for example, in this case by shortening the periods a and b, the position ▵E of the mini-band gap Eg is changed. Namely, since the periods a and b are shortened, the height of the position ▵E is increased. When a voltage ▵V is applied to the two-terminal element having the modulation superlattice, i.e., between the terminals A ○ and B ○, the bottom E C of the conduction band is inclined, and thus the mini-band gap Eg becomes substantially horizontal, as shown in Fig. 3. In Fig. 3, a mark e▵V denotes energy corresponding to an applied voltage ▵V. In the state shown in Fig. 3 when an electron el is injected the mini-band gap Eg acts as a barrier against the injected electron el, and when electron el collides with the barrier, the electron el is reflected therefrom so that a current does not flow between the two terminals A ○, B ○. Figure 4 is a graph illustrating the current-voltage characteristic of the above two terminal element. As can be seen from Fig. 4, the current-voltage characteristic has an effect of negative resistance. The two terminal element explained by Figs. 1 to 4 is of course a diode and it is not a three terminal element having an amplifying function etc. Further it does not act as a control element. Since in order to produce the modulation superlattice, the periods should be continuously and controllably changed in a few Å (10 Å = 1 nm) order, the two terminal element has many technically difficult problems. J. Appl. Phys. 58(3), Resonant tunneling transistor with quantum well base and high-energy injection: A new negative differential resistance device, by Federico Capasso and Richard A. Kiehl, published 1 August 1985, disclosed a new negative conductance device consisting of a heterojunction bipolar transistor with a quantum well and a symmetric double barrier or a superlattice in the base region. In the structure disclosed in the above paper, as shown in Fig. 5, an electron is tunneled through a mini-band having height lower than a height of a barrier of a superlattice. However, in this structure, since the thickness of the GaAs well layer in the superlattice is large, i.e., 40 Å (10 Å = 1 nm), the width of the mini-band MB is very narrow and the width of the mini-band gap Eg is very narrow. Therefore, firstly, the quantity of the tunneled electrons is small so that the collector current is very small. Second, the margin of the current-voltage characteristic of the negative resistance is very small so that the design of the device becomes very difficult. Even though it is assumed that the superlattice having a thinner well layer is applied to the above device in Fig. 5 so that the superlattice in the base layer has a wider mini-band and mini-band gap, since the structure comprises a npn type bipolar transistor, the bias voltage between base and emitter must be large enough to make the injected electrons to be high energy which corresponds to the high energy mini-band gap Eg. If the bias voltage between base and emitter is so large, the holes are injected from the base to emitter so that the bipolar transistor cannot operate the amplification. JP-A-58 142 574 discloses an npn-type bipolar transistor. Since the transistor is a bipolar transistor hot electron can not be used. SUMMARY OF THE INVENTION It is an object of the present invention to provide a heterojunction semiconductor device having a three terminal element and a negative resistance. It is another object of the present invention to provide a unipolar transistor heterojunction semiconductor device wherein a current switching can be carried out by utilizing the reflection of a carrier, for example, electron, from a mini-band formed in a superlattice region. According to the present invention there is provided a heterojunction semiconductor device comprising: a collector layer, a base layer, a collector side barrier layer provided between said collector layer and base layer, an emitter layer, and an emitter side barrier layer provided between said base layer and emitter layer and having a thickness for tunneling a carrier from said emitter layer to said base layer for injecting said carrier into the base layer according to a predetermined voltage applied between said emitter layer and said base layer. According to the invention, said device is a unipolar transistor (in this connection, see EP-A-0 070 211). Moreover, said base layer consists of a superlattice means and two low resistance layers sandwiching the superlattice means, said superlattice means comprising a plurality thin barrier layers and thin well layers for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides, said injected carrier having an energy higher than the bottom of the conduction band (Ec) of the barrier layers of said superlattice means. BRIEF DESCRIPTION OF DRAWINGS Figure 1 is an energy band diagram for explaining a mini-band gap; Fig. 2 is an energy band diagram of a modulation superlattice; Fig. 3 is an energy band diagram for explaining an operation of a modulation superlattice; Fig. 4 is a graph illustrating a current-voltage characteristic; Fig. 5 is an energy band diagram of a conventional npn transistor; Fig. 6 is a main portion cross-sectional view of an first example according to the present invention; Fig. 7A is an energy band diagram seen in a first example of Fig. 6 under a bias condition; Fig. 7B is an energy band diagram of Fig. 6 under an equilibrium bias condition; Fig. 8 is a graph of a voltage (V CB between the collector and base)-current (collector current I c ) characteristic in the first example; Fig. 9 is a graph of a voltage (V BE between the base and emitter)-current (collector current I c ) characteristic in the first example; Fig. 10A is an energy band diagram of a second example under a bias condition according to the present invention; Fig. 10B is an energy band diagram of the second example under an equilibrium bias condition; Fig. 11 is an energy band diagram of the third example under a bias condition according to the present invention. Fig. 12 shows an base emitter voltage-collector current characteristic of Fig. 11; and Figs. 13A to 13D are energy band diagrams of a fourth example according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to drawings. Figure 6 shows a main portion cross-sectional view of a first example according to the present invention. As shown in Fig. 6, an n⁺-type GaAs collector contact layer 2 having a thickness of about 0.6 µm and an impurity concentration of 5 x 10¹⁸ cm⁻³ is provided on a semi-insulating layer 1. Further, on the n⁺-type GaAs collector contact layer 2 are provided an n-type GaAs collector layer 3 having a thickness of about 500 Å and an impurity concentration of about 5 x 10¹⁷ cm⁻³, an i-type Al x Ga 1-x As (x = 0.4) collector side potential barrier layer 4 having a thickness of about 2000 Å, n⁺-type GaAs base layers 5 sandwiching a superlattice 6 and having a thickness of about 500 Å respectively, an i-type Al x Ga 1-x As (x = 0.4) emitter side potential barrier layer 7 having a thickness of about 200 Å, and a n⁺-type GaAs emitter layer 8 having a thickness of about 5000 Å and an impurity concentration of about 5 x 10¹⁸ cm⁻³. The superlattice 6 consists of i-type Al x Ga 1-x As (x = 0.3) barrier layers 6B and i-type or n⁺-type GaAs well layers 6W having a thickness of 17 Å, preferably below 30 Å, respectively. The total number of barrier layers 6B and well layers 6W is 10 to 30. If there are 20 layers, the total thickness substantially thereof becomes 340 Å. An emitter electrode 9 made of Au/Ni/AuGe or Au/AuGe, etc., and having a thickness of 3000 Å, is provided on the n⁺-type GaAs emitter layer 8, base electrodes 10 made of the same material as the emitter electrode 9 and having a thickness of about 1600 Å are provided on the n⁺-type GaAs base layer 5, and collector electrodes 11 made of the same material as the emitter electrode 9 and having a thickness of about 3000 Å are provided on the n⁺-type collector contact layer 2. Figure 7A shows an energy band diagram seen in the first example of Fig. 6. In Fig. 7A the work MB denotes a mini-band, PB the barrier height of a barrier layer 6B, eV BE the energy corresponding to the voltage applied between the base and the emitter, and eV BC the energy corresponding to the voltage applied between the base and the collector. In these marks, e is an absolute value and the energy is calculated by V x e. In this embodiment, PB is about 0.3 eV, and ▵E is about 0.5 eV. And the barrier height of the barrier layers 7,4 is about 0.5 eV. Furthermore, the energy level (▵E - MB) is about half of PB. The first example is formed in such a manner that a superlattice 6 is interposed between base layers 5 in a so-called hot electron transistor (HET). Since a part of the base layers 5 having a low resistance and applied by substantially the same voltage as in the superlattice 6 is present above and below the superlattice 6, the region of the superlattice 6 has substantially the same potential, with the result that the mini-band gap Eg is horizontally maintained. In this first example as shown in Fig. 7A, a voltage V BE corresponding to the energy position ▵E of the mini-band gap Eg is applied between the base layer and emitter layer. In such a voltage condition, an electron el injected to the base layer 5 from the emitter layer 8 collides with the mini-band gap Eg and is reflected therefrom, so that it is returned to the emitter layer 8. When the thickness of the base layer 5 is designed to be sufficiently smaller than a mean free path in which the electron el is scattered, all of the returned electrons el are absorbed by the emitter layer 8, without a loss of energy incurred by the scattering in the return movement. Figure 7B is an energy bank diagram seen in the first example of Fig. 6 in an equilibrium state. Figure 8 is a graph of a current (collector current I c )-voltage (V CB between the collector and base) characteristic in the first example. In Fig. 8, the abscissa axis shows a voltage V CB between the collector and the base, and the ordinate axis shows a collector current I c . As apparent from Fig. 8, when the voltage V BE between the base and the emitter is below the voltage ▵E/e corresponding to the position of the mini-band gap Eg and above (▵E - MB)/e or above (▵E + Eg)/e, a volt-ampere characteristic in an usual HET is obtained. That is, the collection current I c becomes large. However, when the voltage V BE between the base and the emitter is in the range of ▵E to ▵E + Eg the current I c becomes substantially zero. Therefore, the transconductance, which has become standard when a transistor is used as a high speed switching element, is greatly increased. Further, the first example has special functions such that, since the thickness of the superlattice 6 is very small, an extremely high speed switching is possible. Figure 9 shows a graph of a volt (V BE between the base and emitter)-ampere (collector current I c ) characteristic in the first example. In Fig. 9, the abscissa axis shows a voltage V BE between the base and the emitter, and the ordinate axis shows a collector current I c . The ▵E/e shown in Fig. 9 is substantially 0.5 V, and the Eg is substantially 0.2 eV. As apparent from Fig. 9, the first example of a heterojunction semiconductor device, which is a three terminal element according to the present invention, has a negative resistance effect. In this embodiment, since the width of the superlattice layers 6B, 6W is so small that the width of the mini-band MB is very large, i.e., 0.35 eV and the width of mini-band gap Eg is very large, i.e., 0.2 eV, the characteristic shown in Fig. 9 has a wider N shape characteristic than the prior art in Fig. 5. Furthermore, in the present invention, since the base layer has the same conductivity as the emitter or collector layer, i.e., unipolar type transistor, it is possible to apply a large voltage between the emitter and base layers. According to the present invention, the width of the well layer of superlattice SL is so thin that the width of mini-band MB is very wide in extent that the energy level of the mini-band gap Eg is higher than the energy height of the barrier layer SLB of superlattice SL. The well width should be at least less than 30 Å. Figure 10A shows the energy band diagram of a second example under a bias condition according to the present invention. The same symbols used in Fig. 10A denote the same elements. In Fig. 10A, reference numeral 12 denotes an n⁺-type Al x Ga 1-x As (x = 0.4) emitter layer, 13 an i-type GaAs heterojunction layer, and E F the Fermi level. In the first example explained above, electrons are injected from the emitter layer 8 to the base layer 5 while tunnelling through the emitter side potential barrier layer 8, to make hot electrons. On the other hand in the second example as shown in Fig. 10A, a single heterojunction is used in place of the emitter side potential barrier layer 7. And the emitter layer 12 has a smaller electron affinity than the base layer 13, 5. Namely, in the second example, the emitter layer 12 is formed by an n⁺-type GaAlAs, and the i-type GaAs heterojunction layer 13 is interposed between the layer 12 and the n⁺-type GaAs base layer 5. In the second example, substantially the same characteristic as that of the first example can be obtained. Figure 10B is the energy band diagram of the second example in an equilibrium bias condition. Figure 11 is the energy band diagram of a third example under a bias condition according to the present invention. The same marks used in Fig. 11 denote the same elements. In Fig. 11, marks Eg₁ , Eg₂ , Eg₃ , and Eg₄ denote mini-band gaps, and ▵E1, ▵E2, ▵E3 ... denote positions of the mini-band gaps. As shown in Fig. 11, in the third example, a plurality of mini-band gaps appear near the energy level of the injected electrons. This structure shown by the energy band diagram can be obtained by selecting the material of the superlattice 6 and the period thereof. Figure 12 is a graph of volt (V BE between the base and the emitter)-ampere (collector current I c ) characteristic. The abscissa axis shows the voltage V BE between the base and the emitter, and the ordinate axis shows the collector current I c . As apparent from Fig. 12, when a base-emitter voltage V BE is applied so that the mini-band gaps Eg₁ , Eg₂ ... come to positions corresponding to the energy levels of the injected electrons, the value of the collector current I c is lowered. Figures 13A to 13D are energy band diagrams of a fourth example according to the present invention. In Figs. 13A to 13D, reference numeral 14 denotes a superlattice and Eg' denotes a mini-band gap. In the fourth example, superlattices 6 and 14 acting as current controllers are formed. The size of the current controller region is such that it is below the electron mean free path. This example forms an AND circuit consisting of two gates, while using the reflection of the electrons from the mini-band gaps Eg and Eg'. In the state of mini-band gaps Eg and Eg' shown in Fig. 13A, the gate inputs are "0" and "0" and the output is "0". In the state of the mini-band gaps Eg and Eg' shown in Fig. 13B, the gate inputs are "0" and "1" and the output is "0". In the state of the mini-band gaps Eg and Eg' shown in Fig. 13C, the gate inputs are "1" and "0" and the output is "0". In the state of the mini-band gaps Eg and Eg' shown in Fig. 13D, the gate inputs are "1" and "1" and the output is "1". In above mentioned first to fourth examples, GaAs/GaAlAs type semiconductor materials are used as the semiconductor materials. However, the semiconductor materials are not limited to such a combination and heterojunction forming semiconductor materials may be advantageously used. The semiconductor device is not limited to an HET structure, but also can be used as heterojunction semiconductor device having a transistor structure. As carriers in the present invention, both electrons and holes can be used. That is, ppp type unipolar transistor can be applied to the present invention. Of course, all emitter, base, collector layers can be not only semiconductor material but also some appropriate metal.

Claims: A heterojunction semiconductor device comprising: a collector layer (3), a base layer (5, 6, 5), a collector side barrier layer (4) provided between said collector layer and base layer, an emitter layer (8), and an emitter side barrier layer (7) provided between said base layer and emitter layer and having a thickness for tunneling a carrier from said emitter layer (8) to said base layer (5, 6, 5) and for injecting said carrier into the base layer according to a predetermined voltage applied between said emitter layer and said base layer, characterized in that said device is a unipolar transistor and that said base layer consists of a superlattice means (6) and two low resistance layers (5) sandwiching the superlattice means, said superlattice means comprising a plurality thin barrier layers (6B) and thin well layers (6W) for forming a mini-band through which said injected carrier can move and a mini-band gap with which the injected carrier collides, said injected carrier having an energy higher than the bottom of the conduction band (Ec) of the barrier layers (6B) of said superlattice means (6). A heterojunction semiconductor device according to claim 1, wherein the width of said well layers (6W) in the superlattice means (6) is so thin that the energy level of the mini-band gap is greater than the conduction band level of said thin barrier layers. A heterojunction semiconductor device according to claim 2, wherein the width of the well layers (6W) is less than 3 nm (30 Å). A heterojunction semiconductor device according to claim 1, wherein said emitter layer (8) is n-type semiconductor layer, said emitter side barrier layer (7) is intrinsic type semiconductor layer or insulator layer, said base layer (5, 6, 5) is n-type semiconductor layer, said collector side barrier layer (4) is intrinsic type semiconductor layer, and said collector layer (3) is n-type semiconductor layer. A heterojunction semiconductor device comprising: a collector layer (3), a base layer (5, 6, 5), a collector side barrier layer (4) provided between said collector layer and base layer, and an emitter layer (12) faced with the base layer and having a smaller electron affinity than that of said base layer, a carrier being injected from said emitter layer (3) into said base layer (5, 6, 5) by applying a predetermined voltage between said emitter layer and said base layer, characterized in that said device is a unipolar transistor and that said base layer consists of a superlattice means (6) and two low resistance layers (5) sandwiching the superlattice means, said superlattice means comprising a plurality thin barrier layers (6B) and thin well layers (6W) for forming a mini-band through which said injected carrier can move and a mini-band gap with which the injected carrier collides, said injected carrier having an energy higher than the bottom of the conduction band (Ec) of the barrier layers of said superlattice means. A heterojunction semiconductor device according to claim 5, wherein the width of said well layers (6W) in the superlattice means (6) is so thin that the energy level of the mini-band gap is greater than the conduction band level of said thin barrier layers. A heterojunction semiconductor device according to claim 5, wherein the width of the well layers (6W) is less than 3 nm (30 Å). A heterojunction semiconductor device according to claim 5, wherein said emitter layer (12) is n-type semiconductor layer, said emitter side barrier layer (7) is intrinsic type semiconductor layer or insulator layer, said base layer (5, 6, 5) is n-type semiconductor layer, said collector side barrier layer (4) is intrinsic type semiconductor layer, and said collector layer (3) is n-type semiconductor layer.

Inventors: AWANO, YUJI HAISHITI OMOTASANDO 312
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: H01L29
IPC codes: H01L29