Process for the formation of a monolithic high voltage semiconductor device

Abstract: The invention concerns a process for formation of a high voltage monolithic semiconductor device that contains at least one power transistor formed by emitter (14) base (8) and collector (1, 2) regions, respectively and an integrated control circuit including collector (13), base (16) and emitter (17) regions, integrated in a single chip. The device is formed by means of a triple epitaxy which utilizes the same doping agent (Phosphorus) and by growth of the third epitaxial layer (6) with a concentration of impurities grea­ ter than that in the previous epitaxial layers (5 and 6). By spreading the buried la­ yers (4) untill it penetrates inside the third epitaxial la­ yer (6), collector regions of transistors in the integrated control circuit are obtained free of unwanted interme­ diate layers or phantom layers caused by the out-­ diffusion of doping substance present in the heavily do­ ped isolation region (10, 11) with conductivity of the opposite type. Finally PN junctions (9812) are formed for the collector-base region of a power transistor and for the isolation zone (11) of the integrated control circuit, capable of withstan­ ding high voltages.

Description: The present invention concerns a method of manufacturing electronic semiconductor devices which, associated on the same chip, comprise and integrated control circuit and high voltage power components. In such monolithic devices there is the problem of having collector regions possessing different and optimum characteristics both for the transistors in the integrated control circuit and for the power transistors. As is well known, to reduce the collector series resistance of a transistor in the integrated control circuit, a buried layer is included in its collector region. If this buried layer is formed on a higly doped layer with impurities of opposite conductivity, the phenomenon of out-diffusion will occur because the dopant present in this latter layer diffuses into the buried layer and into the collector region above it. Modifications take place in that part of the collector region bordering on the buried layer since undesidered "intermediate" layers, also called "phantom" layers, form in said part. Conductivity of these layers is in fact opposite to that which there must be in a buried layer and in the collector region above it. On account of the harmful effects of the out-diffusion referred to above, a great deal of effort has been devoted to trying to reduce it or, at least, to eliminate the effects it produces. One known method lessens out-diffusion by lowering manufacturing temperatures. Another and also well known method works by controlling within a very narrow interval of variation the concentrations of doping agents and also operating times and temperatures, but manufacturing processes for making the device are so critical that industrially speaking they are anti-economic. In a further well known method, described in the patent application in the name of SGS filed in Italy on December 20 1984 under No.6633 A/84 (cf, also GB-A-2169444), the phenomenon of out-diffusion is obviated by formation of a buried layer in which a second dopant of the same conductivity, is added to the principal dopant. Within the monolithic structures mentioned above, there is also the problem of obtaining collector regions of the power transistors and collector regions of the integrated control circuit transistors with different characteristics. The main object of this invention is to suggest a method of manufacturing a high voltage monolithic semiconductor device, containing at least one power transistor and an integrated control circuit integrated in one single chip of semiconductor material, that makes it possible to avoid formation of harmful phantom layers, and which enables the best characteristics to be obtained both for the power transistors and for the transistors of the integrated control circuit. The method of manufacturing a monolithic semiconductor device according to the invention comprises the following steps: growing on a substrate (1) of a first conductivity type (N) a first epitaxial layer (2) containing a first doping impurity of the first conductivity type; forming a first region (3) by doping the first epitaxial layer (2) with a second doping impurity of a second conductivity type (P) opposite to the first type; forming at least one second region (4) in the first region (3) by doping with a third doping impurity of the first conductivity type, wherein said third doping impurity is different from said first doping impurity; forming a second epitaxial layer (5) of the first conductivity type with said first doping impurity and with the same characteristics of impurity concentration as those of the underlying first layer (2), so that the second epitaxial layer entirely covers said first layer (2), first region (3) and second region (4); forming a third epitaxial layer (6) of the first conductivity type (N) by doping with said first doping impurity so that it entirely covers the underlying second epitaxial layer (5); forming at least one isolation region (10, 11), of the second conductivity type (P), which extends through the third (6) and second (5) epitaxial layers to the first region (3) and encloses within it at least a part (13) of the aforesaid third epitaxial layer (6) lying above the second region (4), wherein said second region and said part of the aforesaid third epitaxial layer constitute the buried layer and the collector region respectively, of a transistor in the control circuit; forming a region of the second conductivity type (P), which constitutes the base (8) of a power transistor, said region extending in depth at least beyond the third epitaxial layer (6); forming additional lateral regions (9,12) onto the outer edges of said region (8), which constitutes the base of a power transistor, and onto the outer edges of the isolation region (11) of the integrated control circuit by introducing impurities of the second conductivity type (P) so that the impurity concentration decreases towards the edge in accordance with a predetermined profile; forming a region in the base region (8), of the first conductivity type which constitutes the emitter (14) of a power transistor; forming further regions inside the collector region (13) of a transistor in the integrated control circuit, so as to form active and passive elements of the integrated control circuit; forming electrodes on the front and back of the substrate and forming metal interconnection patterns between active and passive elements of the integrated control circuit and at least one power transistor; wherein the third epitaxial layer (6) doped with a first impurity has an impurity concentration which is uniform and greater than that of the first (2) and second (5) epitaxial layers, said epitaxial collector region (13) of a transistor in the intergrated control circuit is entirely comprised within the third epitaxial layer (6), and every additional lateral region, both at the base of a power transistor and in the isolation region of the integrated control circuit, extends below the third epitaxial layer. A clearer idea of the invention will be gained from the following description of one of its possible embodiments, given as a non limitative example, read making reference to the attached drawings in which: Figs.1a-1d show section views, not to scale, of a portion of monolithic device comprising a power transistor and a transistor in the integrated control circuit during various phases of the manufacturing process according to the invention; Fig.2 gives the curves representing distribution of three doping impurities in one section, not to scale and enlarged, of the device in Fig. 1d, passing through the buried layer and the adjacent regions of a transistor in the integrated control circuit; Fig.3 is a graph showing distribution, according to the invention, of the concentration of doping agents in relation to the depth x, along a section, not to scale, of the device in Fig. 1d, passing through the regions of emitter, base, collector, buried layer, insulation region, first epitaxial layer and substrate of the device. The numbers on the x axis indicate the same regions of the device as indicated in Fig. 1d. Referring to Figs. 1a-1d, a process is described according, to the invention, for manufacturing a semiconductor device realized on a single silicon chip and comprising a type NPN power transistor and an integrated control circuit of which an NPN transistor is shown. The electrodes of the two transistors are all on the front of the chip except the power transistor collector which is on the back. Association on a single chip of power transistor and of an integrated control circuit connected together makes possible the realization of a very compact and efficient monolithic device, in which the integrated circuit represents the low-energy element of control which the power transistor represents the high-energy actuator capable of directly controlling electric motors, solenoids, resistive loads and similar power devices. The process comprises the following sequence of stages. STAGE A -An initial epitaxial growth is performed on a single-crystal N⁺-type silicon substrate 1, of high conductivity so as to form a single-crystal N⁻-type layer 2, by means of phosphorus, having a doping concentration of 1x10¹⁴ atoms/cm³, typical of a collector region of a high voltage transistor. STAGE B -By means of well known operations of oxidation, photo-masking, etching and diffusion a P⁺-type region 3, doped with boron, is realized in the epitaxial layer 2, and precisely in an area of the chip destined for the integrated control circuit, having a concentration of 2x10¹⁷ atoms/cm³ on the surface. Said region 3 constitutes the horizontal isolation region of the integrated control circuit. STAGE C -By the usual operation of oxidation, photo-masking, etching and diffusion, in region 3 a N⁺-type buried layer 4 is formed, by ionic implantation of antimony at a dose of 1x10¹⁵ atoms/cm² and its subsequent diffusion inside the region 3 (Fig. 1a). STAGE D1 -Over the whole surface of the chip a second epitaxial growth of single-crystal N⁻ type silicon doped with phosphorus is performed so as to form an epitaxial layer 5 which has a concentration of 1x10¹⁴ atoms/cm³, the same as that of the underlying epitaxial layer 2 (Fig. ib). It must be clarified that the two epitaxial layers, 2 and 5, shown separated by a dashed line in Figs. 1b - 1d, in actual fact constitute a single single-crystal layer of identical characteristics. STAGE D2 -According to the invention, over the whole surface of the chip a third epitaxial layer of N-type, phosphorus-doped single-crystal silicon, is grown, so as to form an epitaxial layer 6 having a concentration of 1x10¹⁵ atoms/cm³ (Fig. 1b). This layer is different from the underlying epitaxial layers 5 and 2 on account of its higher concentration of phosphorus. It must be stated that the horizontal isolation region 3 and the buried layer 4 take on the form seen in Figs. 1b-1d as an effect of epitaxial growths and of the subsequent operations carried out at high temperature to which the silicon chip is subjected during the whole manufacturing process. Note that a buried layer 4 must preferably expand until it penetrates into the upper epitaxial layer 6 or, at least, until it reaches said layer. STAGE E -Adopting the usual techniques of oxidation, photomasking, etching and diffusion, below the surface 7 of the device, the P⁺-type base region 8 of the power transistor, doped with boron, is formed. Using the same type of dopant, formation is made of the lateral P⁺-type isolation regions 10 and 11, of the transistors in the integrated control circuit. Said regions 8 and 11, the latter constituting the perimetric lateral isolation region of the integrated control circuit, are extended onto the outer edge of said regions by means of additional lateral regions. These are formed by diffusion of boron in such a way that the concentration of P-type impurities they contain decreases towards the edge according to a previously established profile. Due to the presence of the isolation regions, the transistors in the integrated control circuit are isolated one from another and from the rest of the chip (Fig. 1c). Delimitation is therefore established, in the epitaxial layer 6 comprised between the lateral isolation regions 10 and 11 and the underlying buried layer 4, of an epitaxial region 13 of N-type conductivity constituting the collector region having the desired characteristics of a transistor in the integrated control circuit. Because of its epitaxial origin, it in fact has an allover constant concentration of impurities whose value is 1x10¹⁵ atoms/cm³. Further, at the boundary with the underlying buried layer 4, it is entirely freem of intermediate layers or phantom layers since out-diffusion of the boron, present in the heavily doped isolation region 3, is perfectly balanced by the opposite type of impurity, phosphorus, used to dope the epitaxial layer 6 during its formation and thus the region 13 comprised in it. Bringing out a further characteristic of the invention, it is worth noting that the aforesaid collector region 13 of a transistor in the integrated control circuit has a concentration of impurities ten times higher than that existing in the epitaxial layers 2 and 5 of equal concentration. These, together with the epitaxial layer 6 outside the isolation zone of the intergrated control circuit and outside substrate 1, constitute the collector region of the power transistor, destined to withstand the high voltage applied to the device (Fig. 1d). Therefore, according to the invention, with the growth of an epitaxial layer 6, more doped than the previous ones, collector regions of the transistors in the intergrated control circuits and of the power transistors are also obtained with different characteristics. According to the invention, the drawback relating to higher conductivity of the epitaxial layer 6 compared with that of the underlying epitaxial layers 5 and 2 in the collector region of the power transistor, preventing the monolithic device from withstanding high voltages applied to it, is eliminated by adopting the measures described in the patent application in the name of SGS filed in Italy on August 21 1984 under number 6616/A/84 (cf also GB-A-2163 597). For this purpose the base to collector junctions of the power transistor and isolation zone are formed, comprising the integrated control circuit in accordance with the respective shapes 9 and 12 shown in Figs. 1c-1d. STAGE F -At this point in the process, manufacture of the device continues by well-known operations, mention of which is being made to complete the explanation. Proceeding with the usual techniques, formation is made of the N⁺-type emitter region 14 of the power transistor and, with the same doping agent, of the N⁺-type high conductivity region 15 which subsequently is used to form ohmic contact between the collector region 13 of a transistor in the integrated control circuit and a metal electrode (Fig. 1d). STAGE G -Formation is then made of the P⁺-type diffused base regions 16 and of the N⁺-type emitter 17 of the transistors in the integrated control circuit (Fig. 1d). STAGE H -Finally, the metal contacts are made for the emitter 18, base 19 and collector 20 electrodes of the power transistors, for the emitter 21, base 22 and collector 23 electrodes of the transistors in the integrated control circuit, together with the interconnecting patterns, omitted for simplicity from Fig. 1d, on the silicon dioxide insulating layer 24 formed on the surface 7 of the chip (Fig. 1d). Reference should be made to Fig. 2 and Fig. 3 for a better evaluation of the process according to the invention, and of how the objects of the invention have been achieved. Fig. 2 shows three curves that represent concentration trends of boron (B), antimony (Sb) and phosphorus (P) in a section, not to scale, of the device in Fig. 1d passing along the collector region 13, the buried layer 14, the isolation region 3 and the epitaxial layer 2. Boron (curve B) is the P-type impurity used in diffusion for forming the isolation region 3 of the component parts of the integrated control circuit. Antimony (curve Sb) is the N-type impurity used in implantation and subsequent diffusion to form the buried layer 4 of the transistor in the intergrated control circuit. Phosphorus (dashed line P) is the N-type impurity used in the growth of the various epitaxial layers, and therefore of the collector region 13, to offset the damaging effect of out-diffusion of the boron used for forming the region 3. It will be seen from Fig. 2, especially if the buried layer 4 penetrates into the epitaxial layer 6, that the phosphorus (P) and the antimony (Sb) taken together are superabundant in the collector region 13 compared with the boron, thus avoiding formation of phantom layers. Fig. 3 shows the profile of impurities along a section, not to scale, of the device in Fig. 1d, passing through the emitter region 17 and the buried layer 4 of a transistor in the integrated control circuit. The numbers marked along the axis of the x-coordinate are identical to those in Fig. 1d and indicate the layers and regions constituting the monolithic device described. It should be noted how, due to the effect of the invention, the constancy of impurity concentration at any point of the collector region 13 of a transistor in the integrated control circuit is maintained. To conclude: using the design and manufacturing criteria already known together with the measures described above and which are characteristics of the present invention, a process is realized for producing a monolithic semiconductor device that avoids the drawbacks inherent in known art, making possible, therefore, the production of a monolithic device possessing optimum characteristics and offering optimum performance. Though only one possible embodiment of the present invention has been here explained and described, it is clear that numerous variations and modifications can be made to it. For example, possessing the properties already indicated, the epitaxial layers 5 and 6 are realized, according to the invention, in a single Stage D. In other words, with reference to Fig. 1b, after growing the epitaxial layer 5 with pre-established characteristics, without removing the wafers from the epitaxial reaction chamber, an epitaxial layer 6, with more dopant than the previous one, can be grown on the epitaxial layer 5 by means of a planned increase in the flow of dopant inside the reaction chamber. Under such conditions growth of the epitaxial layer 6 continues until the previously established thickness has been reached. To give another example, a variant of the invention can be made by doping the buried layer 4 with arsenic instead of antimony. As a further example, the invention may be applied to more complex power components such as transistors integrated in a Darlington configuration.

Claims: A method of manufacturing a monolithic semiconductor device comprising at least one power transistor and an integrated control circuit integrated on a semiconductor substrate, the method comprising the steps of: growing on a substrate (1) of a first conductivity type (N) a first epitaxial layer (2) containing a first doping impurity of the first conductivity type; forming a first region (3) by doping the first epitaxial layer (2) with a second doping impurity of a second conductivity type (P) opposite to the first type; forming at least one second region (4) in the first region (3) by doping with a third doping impurity of the first conductivity type, wherein said third doping impurity is different from said first doping impurity; forming a second epitaxial layer (5) of the first conductivity type with said first doping impurity and with the same characteristics of impurity concentration as those of the underlying first layer (2), so that the second epitaxial layer entirely covers said first layer (2), first region (3) and second region (4); forming a third epitaxial layer (6) of the first conductivity type (N) by doping with said first doping impurity so that it entirely covers the underlying second epitaxial layer (5); forming at least one isolation region (10, 11), of the second conductivity type (P), which extends through the third (6) and second (5) epitaxial layers to the first region (3) and encloses within it at least a part (13) of the aforesaid third epitaxial layer (6) lying above the second region (4), wherein said second region and said part of the aforesaid third epitaxial layer constitute the buried layer and the collector region respectively, of a transistor in the control circuit; forming a region of the second conductivity type (P), which constitutes the base (8) of a power transistor, said region extending in depth at least beyond the third epitaxial layer (6); forming additional lateral regions (9,12) onto the outer edges of said region (8), which constitutes the base of a power transistor, and onto the outer edges of the isolation region (11) of the integrated control circuit by introducing impurities of the second conductivity type (P) so that the impurity concentration decreases towards the edge in accordance with a predetermined profile; forming a region in the base region (8), of the first conductivity type which constitutes the emitter (14) of a power transistor; forming further regions inside the collector region (13) of a transistor in the integrated control circuit, so as to form active and passive elements of the integrated control circuit; forming electrodes on the front and back of the substrate and forming metal interconnection patterns between active and passive elements of the integrated control circuit and at least one power transistor; wherein the third epitaxial layer (6) doped with a first impurity has an impurity concentration which is uniform and greater than that of the first (2) and second (5) epitaxial layers, said epitaxial collector region (13) of a transistor in the integrated control circuit is entirely comprised within the third epitaxial layer (6), and every additional lateral region, both at the base of a power transistor and in the isolation region of the integrated control circuit, extends below the third epitaxial layer. A method according to claim 1, characterized by the fact that the third epitaxial layer (6) is formed without removing the wafers from the reaction chamber of the epitaxial reactor, causing epitaxial growth of the second layer (5) to proceed with a planned increase in the concentration of the first doping impurity. A method according to claim 1 or 2 , characterized by the fact that the concentration of impurities in the collector region (13) of a transistor in the intergreated control circuit is everywhere constant and higher than the concentration of the same doping impurity in the first (2) and second (5) epitaxial layer, constituting part of the collector region of a power transistor. A method according to the preceding claim characterized by the fact that the ratio value between the concentration of impurities in the first (2) and second (5) epitaxial layers and the concentration of impurities in the collector region (13) of a transistor in the integrated control circuit, lies between one and one hundredth. A method according to the preceding claim, characterized by the fact that the conductivity of the doping impurity of the first (2), second (5) and third (6) epitaxial layer is type N.

Inventors: MUSUMECI SALVATORE, ZAMBRANO RAFFAELE, MUSUMECI, SALVATORE, ZAMBRANO, RAFFAELE
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1987
Main classification: H01L21
IPC codes: H01L27, H01L21, H01L29