PHASE LOCKED LOOP STABILIZATION CIRCUITRY

Abstract: As used in a digital television receiver, the invention is associated with a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signal components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This digital signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signals into I and Q color difference signals. To compensate for frequency instability in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop (300) develops an output signal which is phase locked to a reference signal generated by a crystal controlled oscillator (310). Control signals (C′) from the third phase locked loop are applied (328) to the second phase locked loop to substantially compensate for frequency instabilities in the regenerated subcarrier signal that are induced by the clock signals.

Description: This invention relates to circuitry for reducing frequency instability in a digital phase locked loop that is controlled by a clock signal which may be unstable. A digital phase locked loop (PLL) includes a variable digital oscillator which generates oscillatory signals that may be locked in frequency and phase to a reference signal. The frequency and phase of the signal produced by the digital PLL may depend on the frequency of the clock signal applied to the digital oscillator as well as on the frequency and phase of the reference signal. For example, consider the digital phase locked loop used to regenerate the chrominance subcarrier signal in a line-locked digital television receiver. An exemplary system of this type is described in U.S. Patent No. 4,349,833 entitled "Apparatus For Digital Demodulation or Modulation of Television Chrominance Signals". Briefly, the system includes a discrete time oscillator (DTO) for regenerating a digital chrominance subcarrier signal locked in phase to the color reference burst component of the composite video signal. The oscillator has three components, an adder, an accumulator register and a read only memory (ROM). The value held by the accumulator register is incremented by an input signal (In) coincident with the leading edge of each pulse of the clock signal (CK). The output values of the accumulator register are applied as addresses to the ROM, which is programmed to provide a periodic output function, for example, a sine wave, as an output signal in response to the address values provided by the accumulator register. Assuming that M-1 is the largest value which may be held in the accumulator register, and that an increment signal (In) is applied to the DTO, the frequency of the signal produced by the DTO (f DTO ) may be expressed as: f DTO = (In/M)f CK . (1) When a DTO is used in a digital PLL, the range of values which may be held in the accumulator register (i.e. the modulus of the accumulator) and the frequency of a clock signal, f CK , are assumed to be invariant so that the frequency of the signal provided by the DTO may be changed only by changing the increment value In applied to the input terminal of the DTO. In the U.S. Patent No. 4,349,833 referenced above, the input signal applied to the DTO is determined by the detected phase difference between the reconstructed color subcarrier signal produced by the DTO and the color reference burst signal component of the received video signals. This phase difference signal is applied to a low-pass filter, the output signals of which are used to change the input value to the DTO so that the frequency and phase of the signal provided by the DTO remain locked to the burst signal. As set forth above, a basic assumption for this type of digital PLL is that the clock frequency is invariant. This assumption may not be valid if the clock signal is generated by a PLL which locks to the horizontal line synchronizing signal components of the input video signals (a line locked PLL) and if the input video signals are derived from a nonstandard source such as a video tape recorder (VTR) or video disc player. The signal provided by a non-standard source generally has relatively stable color burst signal components but may have horizontal line synchronizing signal components which vary significantly in frequency from line to line. This variation may be caused by stretching of the tape, defects in the disc, or motor speed variations in either the VTR or disc player. The frequency of the clock signal generated by a line locked PLL will change to track the changes in the frequency of the horizontal line synchronizing signal. The time constant of the PLL which generates the line locked clock signal is generally relatively short, on the order of ten or fifteen horizontal line periods, for example. This relatively short time constant allows the system to track the changing line frequency rapidly, to keep the number of samples per line substantially constant throughout a field or frame. This feature is desirable in television signal processing systems which include field or frame store memories. However, this tracking feature may cause sufficient variation in the frequency of the clock signal to cause color signal distortion in television systems which use a digital PLL to regenerate the color subcarrier signal. The color subcarrier frequency for composite video signals is relatively stable since it is generated by a crystal controlled oscillator either at the transmitter or in the VTR or disc player. The color information in the video signal is quadrature amplitude modulated with respect to this color subcarrier frequency. To demodulate this signal, it is desirable for the regenerated subcarrier signal developed by the PLL to closely match the original subcarrier signal in frequency and phase. Since the color subcarrier signal is suppressed in a standard composite video signal, the PLL which regenerates the color subcarrier signal locks to the color reference burst components of the video signals. These components occur only during a small portion of each horizontal line. Consequently, it is desirable for the color subcarrier PLL to accumulate phase errors over a relatively large number of horizontal line periods to ensure that any measured phase error is accurate and uncontaminated by noise in the video signal. Thus, the color subcarrier PLL preferably has a much longer time constant than the line locked PLL which generates the system clock signal. This time constant may be on the order of one frame period, for example. Because of the difference in the loop time constants and because the frequency of the signal produced by the digital color subcarrier PLL depends on the frequency of the clock signal, the combination of the two PLL's may cause instabilities in the regenerated color subcarrier signal. This instability may even cause the color subcarrier PLL to lock at the wrong frequency. In consideration of the above, the present invention provides phase locked loop stabilization circuitry for use with: a source of a sampling clock signal which exhibits frequency instabilities; and a first digital phase locked loop, clocked by said clock signal, for developing an output signal which has substantially the same frequency as a first reference signal, wherein the frequency instabilities of said clock signal tend to cause frequency instabilities in said output signal; characterized by a second digital phase locked loop, clocked by said clock signal, for developing an oscillatory signal which has substantially the same frequency as a second reference signal having a predetermined frequency, including circuitry for driving a control signal from the phase error signal developed in the second digital phase locked loop, said control signal substantially compensating said second digital phase locked loop for frequency instabilities in said clock signal and causing said oscillatory signal to be substantially independent of the frequency instabilities in said clock signal; and means, coupled to said second digital phase locked loop, with the phase error signal developed in the first digital phase locked loop to stabilize the frequency of said output signal. In a further aspect, the invention provides a digital television signal processing system comprising an input terminal for applying composite video signal, including horizontal line synchronizing signal components and chrominance signal components including a color reference burst signal component; a horizontal line phase locked loop responsive to said composite video signals and having a predetermined loop time constant for generating a sampling clock signal that is locked in phase to said horizontal line synchronizing signal components, wherein said sampling clock signal may exhibit frequency instabilities; a first digital phase locked loop, clocked by said clock signal, responsive to said composite video signals and having a loop time constant that is substantially greater than that of the horizontal line phase locked loop for developing an output signal that has substantially the same frequency as the color reference burst signal component of said composite video signals, wherein said output signal tends to exhibit frequency instabilities corresponding to frequency instabilities in said clock signal; characterized by phase locked loop stabilization circuitry comprising means for developing a reference signal having a predetermined frequency; a second digital phase locked loop, clocked by said clock signal, responsive to said reference signal and having a loop time constant that is not substantially greater than that of said horizontal line phase locked loop, for developing an oscillatory signal that is locked in frequency to said reference signal, wherein said second digital phase locked loop includes circuitry for driving a control signal from the phase error signal developed in the second digital phase locked loop; and means coupled to said second phase locked loop for combining the control signal developed by said second digital phase locked loop with the phase error signal developed in the first digital phase locked loop to substantially compensate said first digital phase locked loop for frequency instabilities in said output signal related to said clock signal. The invention will now be described with reference to the accompanying drawings, in which: FIGURE 1A is a block diagram of a discrete time oscillator and FIGURES 1B and 1C are waveform diagrams useful in explaining the operation of a discrete time oscillator. FIGURE 2 is a block diagram of a portion of a digital television receiver. FIGURE 3 is a block diagram of circuitry embodying the present invention which may be used with the portion of the television receiver shown in FIGURE 2. FIGURE 4 is a block diagram showing the structure of exemplary low-pass filters for use in FIGURES 2 and 3. In the drawings, broad arrows represent busses for multiple-bit parallel digital signals and line arrows represent connections carrying analog signals or single bit digital signals. Depending on the processing speed of the devices, compensating delays may be required in certain of the signal paths. One skilled in the art of digital circuit design would know where such delays would be needed in a particular system. FIGURE 1A illustrates a discrete time oscillator (DTO) of the type described above, comprising an adder 10, an accumulator register 20, and a read only memory (ROM) 30. The adder 10 is responsive to an input signal (In) and to the output value (V) of the accumulator register 20, and supplies the sum thereof to the input of the accumulator register 20. The value held by the accumulator register 20 is incremented by the input signal coincident with the leading edge of each pulse of the clock signal CJ. The output values of the accumulator register 20 are applied as addresses to ROM 30, which is programmed to provide a periodic output function (e.g., a sine wave) as an output signal (Out) in response to the address values provided by the accumulator register. The frequency (f DTO ) of the signal produced by the DTO may be expressed, per previous explanation, as: f DTO = (In/M) f CK Examples of the signals "V" and "Out" developed by the DTO when In/M = ¼ are shown in FIGURES 1B and 1C, respectively. The points on the sinusoidal waveform shown in FIGURE 1C represent the output values provided by the ROM 30 in response to the addresses "V" (shown in FIGURE 1B) developed in the accumulator register 20. FIGURE 2 is a block diagram of a portion of a television signal processing system which includes first and second PLL's 200 and 250 respectively. The PLL 200 develops a sampling clock signal, CK, which is phase locked to the horizontal line synchronizing signal components of the incoming video signal. The PLL 250 is a digital PLL, clocked by the sampling clock signal CK, which develops digital signals representing the color subcarrier signal at a predetermined phase and a signal that is quadrature phase related to this signal. These two signals are used to synchronously demodulate the chrominance signal components of the incoming video signals to develop two quadrature phase related color difference signals. In FIGURE 2, a source of composite video signals 210, which may, for example, include the tuner, IF amplifier, video detector and analog to digital converter of a conventional digital television receiver, provides digitized composite video signals to sync separator circuitry 212. The circuitry 212, for example, develops a signal, HSYNC, representing the horizontal line synchronizing signal component of the composite video signals. The signal HSYNC is applied to one input terminal of a phase comparator 214. An internally generated horizontal line synchronizing signal, HS, is applied to a second input terminal of the phase comparator 214. The circuitry which develops the signal HS is described below. Phase comparator 214 may, for example, be similar to the circuitry described in U.S. Patent No. 4,506,175 entitled "Digital Phase Comparator Circuit Producing Sign and Magnitude Outputs". The signal provided by the phase comparator 214 may be, for example, the time delay between the leading edges of the respective pulse signals HSYNC and HS. This signal has positive values when the leading edges of the HSYNC pulses occur before the leading edges of the HS pulses and negative values when the leading edges of the HSYNC pulses occur after the leading edges of the HS pulses. The signal provided by the phase comparator circuitry 214 is applied to a low-pass filter 216. Filter 216 is the loop filter of the PLL 200. An exemplary structure for this filter is shown in FIGURE 4. In FIGURE 4, input signals are applied to a scaling circuit 410 which multiplies the input values by a scale factor K p . The digital signals developed by the scaling circuit 410 are applied to one input port of an adder 450. The input signals to the filter are also applied to one input port of an adder 420 which, with the delay element 430, forms an integrator. The output port of the adder 420 is connected to the input port of the delay element 430, the output port of which is connected to the second input port of the adder 420. Delay element 430 may be, for example, a synchronous latch that is clocked by a signal CLK (e.g., the horizontal line synchronizing signal HS) to provide a sample delay interval of one period of the signal CLK. The signal provided by the delay element 430 is the integrated input signal (i.e. the integrated phase difference between HSYNC and HS). This signal is applied to a scaling circuit 440 which multiplies the integrated signal by a factor K I . The output signal of the scaling circuit 440 is applied to the second input port of the adder 450. The signal developed by the adder 450 is the output signal of the low-pass filter. The low-pass filter shown in FIGURE 4 is a digital embodiment of a conventional proportional plus integral control network where the factors K P and K I correspond to the proportional gain and the integral gain of the network respectively. The values of the factors K P and K I depend on the desired time constant and damping factor of the PLL and upon the gains of the other elements in the loop. Filters of this type are commonly used as loop filters in PLL's. Referring to FIGURE 2, the low-pass filtered phase difference signals provided by the filter 216 are applied to a digital to analog converter (DAC) 218. DAC 218 develops analog potential values representing the filtered phase difference signals and applies these values at a horizontal line rate to a voltage controlled oscillator (VCO) 220. The VCO 220, which may be of conventional design, produces sampling clock signal. VCO 220 is tuned to have a free running frequency of R times f H . In the present embodiment, R is the ordinal number of a harmonic of the horizontal line frequency, f H , which approximates a multiple of the color subcarrier frequency. For example, in the NTSC system, the frequency, f SC , of the color subcarrier signal is the 455th harmonic of one-half of the horizontal line frequency, and the frequency, f ck , of the sampling clock signal is four times the frequency of the color subcarrier signal 4 f SC . So the VCO used in this embodiment has a free-running frequency of approximately 910 times the horizontal line frequency (R = 910). The sinusoidal output signal of the VCO is applied to Schmitt trigger circuitry 221 which develops a square wave clock signal CK having a frequency , f CK , equal to Rf H . The signal CK is applied to frequency dividing circuitry 222. Circuitry 222 divides the frequency of the signal CK by R to develop a signal HS having a frequency substantially equal to f H . As set forth above, the signal HS is applied to the second input terminal of the phase comparator 214. The circuitry 222 may, for example, include a 10-bit counter (not shown) which is configured to be reset when a count value of 910 is achieved. The frequency dividing circuitry 222 may further include circuit elements (not shown) coupled to the counter to detect count values corresponding to the beginning and end of the burst interval and for generating a burst gate signal, BG, which spans the time interval defined by those count values in each horizontal line period. The PLL 200 generates a clock signal, CK, which tracks the varying line frequency of a non-standard signal to provide a substantially uniform number of sampling clock pulses per line. In the present embodiment, the gain factors of the phase comparator 214, low-pass filter 216, DAC 218, VCO 220, Schmitt trigger 221 and frequency divider circuitry 222 are selected to achieve a filter time constant of approximately 15 horizontal line periods and a damping factor of 2. These gain values depend on the circuit elements to be used in the PLL and may be readily calculated by one skilled in the art of phase-locked loop design. An explanation of the relationship between the gain values, the damping factor and the PLL time constant may be found in Gruen, W.J. "Theory of AFC Synchronization" Proceedings of the IRE, August 1953, pp. 1043-1048. Composite video signals from source 210 are also applied to Y/C separation filter circuitry 230. Circuitry 230 may include, for example, a low-pass filter and a band-pass filter for separating the respective luminance and chrominance signal components from the composite video signals. The luminance and chrominance signals are available at the output busses YB and CB of the circuitry 230 respectively. The separated chrominance components are applied to multipliers 232 and 234 which, using signals provided by the PLL 250, demodulate the chrominance signals into two quadrature phase related baseband color difference signals, for example, I and Q. The color difference signals are applied to a phase error detector 236. The phase error detector 236 develops an output signal representing the difference between the phase of the demodulated color reference burst signal and a reference phase value. The phase error detector 236 may include, for example, circuitry (not shown) to separately accumulate baseband I and Q sample values during the burst interval and to divide the accumulated I values by the accumulated Q values to develop values representing the phase of the burst signal relative to the sampling instants of the I and Q samples. These values may be subtracted from a reference value representing the desired burst phase to generate a phase error value to control the PLL 250. The phase error values developed by the detector 236 are applied to a low-pass filter 238. Filter 238 is clocked by the signal HS generated by the PLL 200 and may be similar to the filter 216 except for the values of the proportional and integral gain factors, K P and K I respectively. The filtered phase error signal, A, provided by the filter 238 is applied to one input port of an adder 240. A fixed increment value, K₁, supplied by a source 242, is applied to the other input port of the adder 240. The signal, B, developed by the adder 240 is applied as the input increment value to a DTO 252 which includes an adder 244, an accumulator register 246 and a ROM 248 that is programmed to provide, at respective first and second output ports, the cosine and sine of the values applied to its address input port, normalized to 2π radians. These signals, which in the present embodiment are the cosine and sine of 2πf sc t respectively, are applied to the respective multipliers 232 and 234, as set forth above, to synchronously demodulate the chrominance signal to recover the two quadrature phase related color difference signals. In the steady state, when there is no difference between the phase value of the demodulated burst signal and the reference phase value, the frequency of the signal developed by the DTO is determined by the number of bits in the accumulator register 246, the increment value K₁ supplied by the source 242, and by the frequency of the clock signal CK. Assuming that the register 246 is an twenty-bit register and that the frequency of the clock signal CK is equal to 4f SC , a K₁ equal to 262,144 (i.e. 2¹⁸) produces an output signal having a frequency of f SC . In dynamic operation, when the burst phase does not match the reference phase, the phase error values provided by the detector 236 are accumulated by the low-pass filter 238 to develop a correction term which is added to the value K₁ by the adder 240 to change the frequency of the DTO in a sense that tends to reduce the phase error. As set forth above, it is desirable for the time constant of the PLL 250 to be relatively long to reduce the effects of noise and to provide a high level of phase accuracy for the signals applied to the synchronous demodulating multipliers 232 and 234. In the present embodiment, for example, the gain factors of the various circuit elements in the PLL are set to values which produce a loop time constant of approximately one frame period (1/30th of a second for NTSC signals). Since the time constant of the PLL 250 is much long than the time constant of the PLL 200, the PLL 250 may not be able to track frequency changes in the regenerated subcarrier signal that are induced by changes in the frequency of the clock signal, CK. This deficiency in the system shown in FIGURE 2 may cause random errors in the I and Q color difference signals or may cause the PLL 250 to generate a color subcarrier signal having the wrong frequency, locked to the wrong harmonic of the line frequency. To understand this problem more completely, consider the PLL correction signals A and B. When the signals applied to the television receiver are from standard sources (e.g. broadcast signals) and the PLL 250 is locked to the color reference burst signal, the clock signal CK and regenerated subcarrier signal developed by the DTO are at their nominal frequencies, f ck nom and f sc nom respectively. Accordingly, the equation (1) may be restated as In/M = f sc nom /f ck nom . (2) In relation to FIGURE 2, the input increment signal, In, corresponds to the correction signal B. When the PLL 250 is locked to burst, the signal A is zero valued. In this instance, the input increment signal, B, applied to the DTO 252 is the value K₁. Consequently, B = K₁ = M f sc nom /f ck nom . (3) In the non-locked condition, the frequency of the signal provided by the DTO 252 differs from f sc nom by some value Δf sc and the signal A is non-zero. In this instance, the equation (3) becomes: B = A+K₁ = M(F sc nom +Δf sc )/f ck nom . (4) from which it may be deduced that: A = M Δf sc /f ck nom . (5) B is the input increment signal to the DTO. Substituting the equation (4) in the equation (1) yields: f DTO 252 = (f sc nom +Δf sc )f ck /f ck nom . (6) Thus, even when the PLL 250 has locked to the color burst signal and the term Δf sc becomes zero, the frequency of the signal generated by the DTO 252 may change by the factor f ck /f ck nom , the actual clock frequency divided by the nominal clock frequency. FIGURE 3 is a block diagram of circuitry which embodies the present invention. This circuitry modifies the signal B to develop a signal B′ which is an input increment signal that allows the signal generated by the DTO to be substantially independent of changes in f ck . The circuitry includes an oscillator 310 which develops a sinusoidal output signal having a frequency f xtl determined by the resonant crystal 312. The frequency of the signal generated by the oscillator may be fine tuned via the optional adjustment 330 (shown in phantom), the function of which is described below. The output signal of the oscillator is applied to an analog-to-digital converter (ADC) 314. ADC 314, which may, for example be a four-bit flash ADC, samples the sinusoidal signal at instants determined by the clock signal CK to develop digital signals for application to a phase detector 316. In addition to the phase detector 316, the PLL 300 also includes a low-pass filter 318, adder 320, digital value source 322, and a DTO 302 which includes an adder 324, an accumulator register 326 and a ROM 327. This PLL develops, for example, a four-bit digital signal at the output port of the ROM 327 that is locked in frequency and phase to the signal developed by the oscillator 310. The phase detector 316 compares the signal provided by the ROM 327 to the signal provided by the ADC 314. After the PLL 300 has initially locked to the reference signal, the phase difference signal developed by the phase detector 316 represents phase changes induced by the clock signal. This phase difference signal is applied to a low-pass filter 318. Filter 318 is the loop filter of the PLL 300 and may, for example, be of the same design as the filters 216 and 328 described above. The integral and proportional gain factors of the filter 318 are set, along with the gain constants of the other elements in the loop, to provide a loop time constant that is less than or approximately equal to the time constant of the PLL 200 (i.e. fifteen horizontal line periods). The filtered phase difference signal provided by the filter 318 is added to a fixed digital value, K₂, from a source 322, by the adder 320. The signal provided by the adder 320 is applied as the input increment signal to the DTO 302 as set forth above. The output signal of the DTO 302 is applied to the phase detector 316 to complete the feedback loop. The following is a more detailed analysis of the operation of the PLL 300. The frequency, f xtl , of the reference signal is substantially constant since it is generated by a crystal controlled oscillator. Consequently, the phase difference signals developed by the phase detector 316 and the phase correction signals developed by the low-pass filter 318 are proportional to the frequency and phase differences in the signal generated by the DTO 302 relative to the signal produced by the crystal oscillator. These frequency and phase differences are induced by the frequency instabilities in the clock signal CK. Thus, when the signals received via source 210 are from standard sources, the output signal C of the low-pass filter 318 is zero valued and the input increment signal to the DTO 302 is the digital value K₂ provided by the source 322. Using analysis similar to that set forth above in reference to the PLL 250, the value K₂ may be described by the equation (7). K₂ = Nf xtl /f ck nom (7) where the number N is one greater than the largest number that can be stored in the accumulator register 326. When the signals received via the source 210 are from non-standard sources, however, the frequency of the clock signal CK may vary from the nominal value f ck nom by an amount Δf ck , so the signal C is non-zero. To ensure that the PLL 300 accurately tracks the changing clock frequency, it is desirable that the factor f ck nom in the equation (7) be replaced by the factor (f ck nom +Δf ck ). This replacement produces the equation: C′ = C+K₂ = Nf xt1 /(f ck nom +Δf ck ). (8) Multiplying the right-hand side of the equation (8) by f ck nom /f ck nom yields: C+K₂ = Nf xt1 f ck nom /(f ck nom +Δf ck )f ck nom . (9) Replacing the numerator factor, f ck nom , in the equation (9) by f ck nom +Δf ck -Δf ck yields: C+K₂ = Nf xt1 /f ck nom -Nf xt1 Δf ck /(f ck nom +Δf ck )f ck nom . (10) From the equation (10), it can be deduced that C = -Nf xt1 Δf ck /(f ck nom +Δf ck )f ck nom . (11) The equation 11 describes the frequency difference signal provided by the low-pass filter 318 in response to the phase difference signals provided by the phase detector 316. The signal C′, the sum of C and K₂, when applied as the input increment signal to the DTO 302 causes the DTO 302 to accurately track the changes in f ck and, maintain the frequency of the signal provided by the DTO 302 substantially equal to f xt1 . The signal C′ is scaled by scaling circuitry 323 by a factor K S which satisfies the equation (12). K S = f ck nom /(N f xtl ) (12) to produce a signal C″ which is described by the equation (13). C″ = f ck nom /f ck . (13) The signal B, provided by the adder 240 in FIGURE 2, is multiplied by the signal C″ in the multiplier 328 to develop a signal B′ satisfying the equation (14). B′ = M(f sc nom +Δf sc )/f ck . (14) When B′ is substituted for B as the input increment of the DTO 252, the equation (6) becomes f DTO 252 = f sc nom +Δf sc . (15) So the frequency of the signal provided by the PLL 250 is substantially independent of the frequency of the clock signal CK. In the present embodiment, the frequency f xtl may have any predetermined value within the Nyquist limit of the sampling clock signal CK. It is preferable, however, that the system be designed to operate at a particular frequency since the digital constant factor K S includes a factor of 1/f xtl . The frequency f xtl may be set to the predetermined value either by using a very accurate resonant crystal 312 or by using the optional frequency adjustment circuitry 330 in the oscillator 310 and using a less accurate crystal.

Claims: Phase locked loop stabilization circuitry for use with: a source (200) of a sampling clock signal (CK) which exhibits frequency instabilities; and a first digital phase locked loop (250), clocked by said clock signal, for developing an output signal (from 248) which has substantially the same frequency as a first reference signal, wherein the frequency instabilities of said clock signal tend to cause frequency instabilities in said output signal; characterized by: a second digital phase locked loop (300), clocked by said clock signal, for developing an oscillatory signal which has substantially the same frequency as a second reference signal having a predetermined frequency, including circuitry (318-322) for deriving a control signal (C') from the phase error signal developed in the second digital phase locked loop, said control signal substantially compensating said second digital phase locked loop for frequency instabilities in said clock signal and causing said oscillatory signal to be substantially independent of the frequency instabilities in said clock signal; and means (323, 328), coupled to said second digital phase locked loop (300), for combining the control signal (C') developed by said second phase locked loop with the phase error signal developed in the first digital phase locked loop to stabilize the frequency of said output signal. The stabilization circuitry of claim 1 for use with a first digital phase locked loop (250) which includes: an input terminal for applying said first reference signal; a first discrete time oscillator (252) responsive to said clock signal (CK) and to a first input increment signal (B) for developing said output signal having substantially the same frequency as said first reference signal; means, including first phase comparison means (236) for developing a signal representing the difference in phase between said first reference signal and said output signal; and first summing means (240) coupled to said first phase comparison means for combining the signal developed thereby with a signal (K1) having a predetermined value to develop said input increment signal for application to said discrete time oscillator (252); further characterized in that: said means for combining said control signal includes signal modifying means (328) having a first input port coupled to receive the output signal of said first summing means (240), a second input port coupled to receive a second signal (C") derived from said control signal (C'), and an output port coupled to apply the signal provided by said first summing means as modified by said control signal to said discrete time oscillator (252) as a modified first input increment signal (B'). The stabilization circuitry of claim 2 characterized by: means for developing said second reference signal including: a crystal oscillator (310) for developing an output signal having a frequency substantially equal to said predetermined frequency; and an analog to digital converter (314) coupled to said crystal oscillator and to said source of clock signal (CK) for developing digital samples representing said second reference signal, said samples having values representing the values of the signal provided by said crystal oscillator at instants in time determined by said clock signal; and further characterized in that: said second digital phase locked loop (300) includes: a second discrete time oscillator (302) responsive to said clock signal and to a second input increment signal (C') for developing said oscillatory signal having substantially the same frequency as said second reference signal; means including second phase comparison means (316) coupled to said analog to digital converter (314) and to said second discrete time oscillator (302) for developing a signal representing the difference in phase between said second reference signal and said oscillatory signal; and second summing means (320) coupled to said second phase comparison means (316) for combining the signal provided thereby with a signal (K2) having a predetermined value to develop a signal (C') for application to said second discrete time oscillator as said second input increment signal and to said signal modifying means as said control signal. The stabilization circuitry as in claim 3 further characterized in that said signal modifying means includes a multiplier (328) responsive to first and second input signals provided by the first and second summing means (240, 320) of said first and second phase locked loops (250, 300) respectively for developing a signal which is proportional to the product of the first and second input signals for application to said first discrete time oscillator as said modified first input increment signal. A digital television signal processing system comprising: an input terminal for applying (from 210) composite video signal, including horizontal line synchronizing signal components and chrominance signal components including a color reference burst signal component; a horizontal line phase locked loop (200) responsive to said composite video signals and having a Predetermined loop time constant for generating a sampling clock signal (CK) that is locked in phase to said horizontal line synchronizing signal components, wherein said sampling clock signal may exhibit frequency instabilities; a first digital phase locked loop (250), clocked by said clock signal, responsive to said composite video signals and having a loop time constant that is substantially greater than that of the horizontal line phase locked loop for developing an output signal that has substantially the same frequency as the color reference burst signal component of said composite video signals, wherein said output signal tends to exhibit frequency instabilities corresponding to frequency instabilities in said clock signal; characterized by phase locked loop stabilization circuitry comprising: means (310) for developing a reference signal having a predetermined frequency; a second digital phase locked loop (300), clocked by said clock signal, responsive to said reference signal and having a loop time constant that is not substantially greater than that of said horizontal line phase locked loop, for developing an oscillatory signal that is locked in frequency to said reference signal, wherein said second digital phase locked loop includes circuitry (318-322) for deriving a control signal (C') from the phase error signal developed in the second digital phase locked loop; and means (323, 328) coupled to said second phase locked loop for combining the control signal (C') developed by said second digital phase locked loop (300) with the phase error signal developed in the first digital phase locked loop to substantially compensate said first digital phase locked loop for frequency instabilities in said output signal related to said clock signal. The system of claim 5 wherein: said first digital phase locked loop (250) includes: a first discrete time oscillator (252) responsive to said clock signal (CK) and to a first input increment signal (B) for developing said output signal having substantially the same frequency as said color reference burst signal; means including first phase comparison means (236) for developing a signal representing the difference in phase between said color reference burst signal and said output signal; and first summing means (240) coupled to said phase comparison means for combining the signal provided thereby with a signal having a predetermined value to develop said input increment signal for application to said discrete time oscillator; and characterized in that: said means (323, 328) for combining said control signal includes signal modifying means (328) for modifying the signal provided by said first summing means in accordance with a signal (C") derived from control signal (C') to produce a modified first input increment signal (B'). The circuitry set forth in claim 6 wherein: said means for developing said reference signal includes: a crystal oscillator (310) for developing an output signal having a frequency substantially equal to said predetermined frequency; and an analog to digital converter (314) coupled to said crystal oscillator and to said source of clock signals (CK) for developing digital samples representing said reference signal, said samples representing the values of the signal provided by said crystal oscillator at instants in time determined by said clock signal; and wherein said second digital phase locked loop (300) includes: a second discrete time oscillator (302) responsive to said clock signal and to a second input increment signal (C') for developing said oscillatory signal having substantially the same frequency as said reference signal; means including second phase comparison means (316) coupled to said analog to digital converter (314) and to said second discrete time oscillator (302) for developing a signal representing the difference in phase between said second reference signal and said oscillatory signal; and second summing means (320) coupled to said second phase comparison means (316) for combining the signal provided thereby with a signal (K2) having a predetermined value to develop a signal for application to said second discrete time oscillator as said second input increment signal (C') and to said signal modifying means (328) as said control signal. The apparatus set forth in claim 7 wherein said signal modifying means (328) includes a multiplier responsive to first and second input signals provided by the respective first and second summing means for developing a signal which is proportional to the product of the First and second input signals for application to said first discrete time oscillator as said modified first input increment signal.

Inventors: BALABAN, ALVIN REUBEN, DEMMER, WALTER HEINRICH, HARWOOD, LEOPOLD ALBERT, PATEL, CHANDRAKANT BHAILALBHAI
Applicants: RCA THOMSON LICENSING CORPORATION
Application year: 1987
Main classification: H03L7
IPC codes: H03L7, H04N9