A LOCAL OXIDATION OF SILICON PROCESS

Abstract: A LOCOS process, a process of the type wherein a capped recessed mesa structure (1, 3) is defined in single crystal, semiconductor grade, silicon and thereafter, and in the presence of the capping layers (5, 7), local oxide (13) is thermally grown to provide an isolation structure. This process is modified by introducing a layer (11) of passive oxide deposit to cover the substrate (3), mesa (1) and upper capping layer (7) prior to the thermal growth of further oxide (13). The resulting oxide (13) is then etched back to remove excess material. This modification results in reduced bird's head height non-planarity and also in reduced bird's beak encroachment into the active area of the silicon device (3). Re-entrancy at the base of the bird's head (13) is also eliminated.

Description: A LOCAL OXIDATION OF SILICON PROCESS TECHNICAL FIELD The present invention concerns improvements in or relating to processes which use local oxidation of silicon (LOCOS) to provide oxide isolation for silicon integrated circuit components. Following the current demand for very large scale integration (VLSI) and therefore high packing densities, there is a need to scale down current feature sizes and thus to reduce the size and extent of isolating oxide structures. The invention is intended to have application to processes for both bipolar and MOS device isolation. BACKGROUND ART Local oxidation of silicon (LOCOS) has been the standard method of isolation for large-scale integration (LSI) and very large-scale integration (VLSI) circuits for approximately ten years. See, for example Appls, J.A., et al.. Philips Research Reports Vol.25 (1970) pages 118-132 and also United Kingdom Patent No: 1208574. However, several features of the technique have since been identified as having a detrimental effect on the final device structure. The lateral encroachment of the oxide into the active area (bird's beaking) severely limits the scalability of the device and an attempt to reduce this by decreasing the thickness of the field region will cause an increase in interconnect capacitance. The standard LOCOS isolation technique currently employed involves recessing a silicon surface to form a mesa, and thermally oxidising the exposed silicon surface in steam. The top of the mesa is typically protected from oxidation by a nitride cap which is deposited on a thin stress relief oxide, to ensure minimal defect generation during oxidation. The topography presented by the isolation oxide can cause problems with photolithography prior to metal deposition, where multiple angle reflections from the bird's beak produces a 'necking' effect in subsequent metal depositions. Furthermore, the profile of the bird's head does not provide a suitable surface for metal coverage primarily due to a re-entrancy of the oxide at the bottom of the bird's head/field oxide region. The coupled effect of a large bird's head and a re-entrant step could present severe problems for metal continuity, where cracking or 'mouse-holing' may be evident. Recently, several isolation techniques have been investigated in an attempt to minimise bird's beak encroachment and produce an almost planar surface - See for example Kuang, Yi, C, Moll, J.L., Manoliu, J. , IEEE Trans. Electron Dev. vol. Ed-29, no. 4 April 1982; Teng, C, IEEE Trans. Electron Devices vol. Ed-32, no. 2 Feb. 1985 and Hui, J., Voorde, P.V., Moll, J. , IEDM 1985 p. 392. In general, these methods involve complex processing steps and are often accompanied by a high defect density during oxidation. DISCLOSURE OF THE INVENTION The present invention is intended to provide an alternative to the foregoing remedial processes, one that does not involve difficult processing operations. The aim of the inventive process, as disclosed below, is to provide a more ideal planar surface for subsequent metal coverage, this by reducing the step height of the bird's head/field oxide. A further aim of the inventive process herein, is to suppress, or at least reduce, bird's beak encroachment, allowing thus more optimal use of the active areas enclosed within the boundaries of the field oxide isolation structure. In accordance with the invention thus there is provided a local oxidation of silicon process, a process of the type wherein a capped single crystal silicon mesa is defined in a silicon substrate and thereafter an isolating structure of local field oxide is grown by thermal oxidation of the silicon; characterised in that:- a layer of passive oxide is deposited upon the surfaces of the mesa cap, the mesa sidewall, and the silicon substrate prior to said thermal oxidation; thermal oxidation is performed in the presence of this layer; and, excess oxide removed thereafter by etching. The inventive process disclosed here, addresses the problem of surface re-entrancy and bird's head height from two standpoints. Firstly, the deposited layer of oxide relies on being non-conformal to the silicon surface, and thus exaggerates the corners at the bottom and top of the mesa. Secondly, an oxide thickness 0. Sex- will put oxidation kinetics in the parabolic regiπe thus effectively reducing any differential oxidation rate between the (100) and (111) crystal planes. The height of the bird's head is significantly reduced primarily due to visco-elastic flow of the oxide around the nitride edge. The presence of an oxide layer on the nitride allows a diffusion path for the expanding surface of oxidising silicon. BRIEF INTRODUCTION OF THE DRAWINGS In the drawings accompanying this specification figures 1 to 4 show substrate-and-structure cross- sections for successive stages of this inventive process. The stages shown in figures 1 and 2 are conventional. DESCRIPTION OF PREFERRED EMBODIMENTS So that the invention may be better understood preferred embodiments thereof will now be described and SUBSTITUTE SHEET reference will be made to the accompanying drawings. The description that follows is given by way of example only. As in the conventional process, a mesa 1 is defined in a single crystal silicon substrate 3. As shown in figures 1 and 2 this is performed by growing a thin first layer 5, a layer of thermal oxide, at the surface of the substrate 3. In a typical process this layer 5 would be approx. 250A thick. This then is followed by the deposition of a second layer 7, a layer of an oxide-etch resistant material, typically nitride. Th c is preferably somewhat thicker, typically approx. 1000A. In the case of nitride this may be performed by a low-pressure chemical vapour deposition technique, the details of which are well known and not therefore detailed here. A layer 9 of resist is then spun onto the surface of the second layer 7. This then is selectively exposed and developed and the exposed part of the second layer 7 removed by an anisotropic etch - for example, by a plasma. An illustrative cross-section of the substrate-and-structure at this stage of the process is » shown in figure 1. The layer 9 of resist is now stripped off eg. by ashing and the remanent part of the second . layer 7 is used as a mask during etch removal of the exposed oxide part of the first layer 5. This may be performed using a selective wet etchant - eg. hydrofluoric acid (HF). Exposed silicon material is then SUBSTITUTESHEET removed using an anisotropic wet etchant, for example, potassium hydroxide etchant isopropyl alcohol (KOH/IPA). This step of the process thus defines a mesa 1 with sloping walls. Typically, this etching step is continued until a depth of approx. 0.6ιoιι of silicon is removed, which depth corresponds to the desired height of the mesa 1. This capped mesa 1 is shown in figure 2. Then next step is a departure from the conventional process. At this stage; and thus prior to the growth of local oxide, a passive oxide deposition (POD) is performed. A layer 11 of low-pressure chemical vapour depositon (LP CVD) oxide is blanket deposited over the recessed mesa 1 and substrate 3. This deposited layer 11 typically can be approx. 0.5pm thick and is undope . - See figure 3. In this figure, the labels D Qχ and H M are used to denote, respectively, the thickness (depth) of the deposited oxide layer 11, and, the height of the mesa 1 above the surrounding surface of the silicon substrate 3. The final steps of this process then follow in manner similar to the conventional process. At this stage the silicon is oxidised by exposing the oxide covered structure to steam at a raised temperature. Tnis, for example, can be conducted at a temperature of 1050°C for a period of 8 hours, this allowing oxidation SUBSTITUTE SHEET of the silicon to a depth of approx. 0.6pm. This may be compared with the standard process where typically oxidation is conducted at a temperature of 1000°C and for a period of 7 hours. It will be noted that due to the presence of an initial thickness of oxide, oxide layer 11, either the temperature or the time, or both, are thus increased to allow consumption of the equivalent thickness of silicon. Excess oxide - typically the same in thickness as the thickness of the original deposited oxide layer 11, approx. , may then be removed by wet etching eg. using hydrofluoric acid (HF). Active areas then are exposed by wet etch removal of oxide-etch resistant material, eg. nitride 7, and of oxide material 5. The bird's head/beak structure 13 is depicted in figure 4. In this figure, an approximation to a profile produced by this process is shown in bold outline. By way of comparison, an approximate profile produced by conventional processing is also shown, but in broken outline. The thicknes-s of the oxide, and, the penetration length of the "bird's beak"- (as measured from the edge of the second layer 7) are depicted respectively by symbols T and B. The slope angle 0 B of the "bird's head", as measured relative to the normal to the plane silicon surface, is also labelled. The inventive process is not restricted to the SUBSTITUTE SHEET dimensions specified above. In a series of experiments, conducted to characterise this modified process, various combinations of deposited oxide thickness D o (0.25 and O.Sitm), thickness of the nitride layer 7 (500 and 1000A) and thickness of the pad oxide 5 o (375 and 1000A) were investigated. For these experiments the mesa height H H was in all cases 0.6pm. A measure- of - excellence parameter, B/T, - the ratio of beak length to oxide thickness, is tabulated, for these combinations - See Table 1. By way of a guideline, a B/T value of 1.0 should be taken as typical for the conventional process:- TABLE 1 Suπtrr.ary of B/T (+0.1) values determined by experiment The improvements of reduced "bird's beack" encroach¬ ment is evident from these results - especially for the c e lowest thicknesses of pad oxide and nitride (375A; 500A). SUBSTITUTESHEET Micrograph examination also shows there to be considerable etch-back smoothing of the profile at the base of the bird's head. The angle 0 B is found to be approx. 45° compared to an angle of 15° subtended by the bird's head after conventional processing. The step height of the bird's head is also found to be 0.5pm, respresenting a 50% reduction compared with that found conventionally, typically 1 height. SUBSTITUTESHEET

Claims: CLAIMS 1. A local oxidation of silicon process, a process of the type wherein a capped single crystal silicon mesa (1) is defined in a silicon substrate (3) and thereafter an isolating structure (13) of local field oxide is grown by thermal oxidation of the silicon; characterised in that;- a layer (1 ) of passive oxide is deposited upon the surfaces of the mesa cap (7), the mesa sidewall (1), and the silicon substrate (3) prior to said thermal oxidation; thermal oxidation is performed in the presence of this layer (11); and, excess oxide (13) removed thereafter by etching. 2. A process, as claimed in claim 1, wherein the mesa (1) is capped by a layer (5) of pad oxide and on this a layer (7) of nitride, each layer (5, 7) being of ø thickness 1000A or less. 3. A process, as claimed in claim 1, wherein the pad c oxide and nitride layers (5, 7) are of thickness 375A or less and 500A or less, respectively. SUBSTITUTESHEET

Inventors: DUNCAN SHANE, DUNCAN, SHANE
Applicants: PLESSEY OVERSEAS, PLESSEY OVERSEAS LIMITED
Application year: 1987
Main classification: H01L21
IPC codes: H01L21