SIGNAL SENDING CIRCUIT OF A DISASTER PREVENTION SYSTEM

Abstract: A relay circuit (C1) in a disaster prevention system has a transmitter a receiver (Rx), a parallel-to-serial converter (62), a serial-to-parallel converter (63), a and a timer (TM). The transmitter sends a signal to a receiver terminal (10) when the timer is switched on. The timer is cleared off every time the relay receiver receives a correct signal from the transmitter. If the relay receiver fails, the timer keeps counting until a predetermined period of time (0.5 second) expires when the signal transmission is cut off. Thus the occupation of a signal line is prevented even if a failure occurs.

Description: TECHNICAL FIELD The present invention relates to a signal transmission circuit of a disaster protection system, and more particularly to such a disaster protection system which transmits a signal from a signal processing part provided in a control panel or a terminal device of the disaster protection system through a predetermined signal line, and which is designed that, even when a trouble occurs in said control panel etc., the signal line remains unoccupied by the control panel or slave unit in trouble, and other slave units etc. in normal condition can still transmit a signal to the signal line. TECHNOLOGICAL BACKGROUND Control panels and terminal devices, e.g. slave units, fire sensors, fire detectors, intrusion detectors, fire protection means, smoke venting means, or fire extinguishing means, of fire and security protection systems such as fire alarm systems and security systems are equipped with transmission circuits, and it is necessary to check if the transmission circuits have properly transmitted their predetermined signals. The following method is considered to be suitable for this check. The signal which should be transmitted from the transmission circuit is stored in the memory circuit, and the signal which has been transmitted from said transmission circuit is received by the receiving circuit. The received signal is compared with the signal stored in the memory circuit, and if they match, it means that the transmission circuit has properly transmitted the signal. Nevertheless, if a trouble occurs in the receiving circuit, it is not possible to detect the signal transmitted from the transmission circuit, and discrimination means such as a CPU judges that no signal has yet been transmitted from the transmission circuit. Therefore, even after the parallel-serial converter has completely sent the signal to be transmitted off to the transmission circuit, the CPU still keeps the transmission circuit in a state ready for signal transmission, and consequently the signal line remains occupied by the terminal device. Therefore, it is a problem that the control panel or other slave units cannot transmit signals to the signal line. DISCLOSURE OF THE INVENTION The present invention is made in view of the above circumstances and with the object of providing a signal transmission circuit which transmits a signal from a signal processing portion provided in the control panel or terminal device of a disaster protection system and which, even if trouble occurs in the control panel or a terminal device such as a slave unit, still allows the control panel or any other slave unit in normal condition to transmit the signal to the signal line without being occupied by the control panel or slave unit in trouble. The present invention has been made to achieve said object. Namely, according to the present invention, a signal transmission circuit is provided with a control panel or a terminal device of a disaster protection system so as to transmit a signal from said signal processing part in the control panel or terminal device to a signal line, said circuit comprising a signal transmitting means set to a state ready for transmitting a signal by control of said signal processing part when desired, a signal detecting means to detect the signal transmitted from said signal transmitting means to the signal line, a timer means which is set when the signal is transmitted and is reset by the detection output of said signal detecting means, and a signal transmission control means to turn off said signal transmitting means when a given time of said timer is reached. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing an embodiment according to the present invention, Figure 2 is a circuit diagram showing the transmission circuit and the receiving circuit shown in Figure 1 in more detail, and Figure 3 is a flowchart diagram showing the operation of the above embodiment. BEST MODE FOR CARRYING OUT THE INVENTION Figure 1 is a block diagram showing the present invention embodied in a slave unit as a terminal device. The slave unit C 1 is equipped with a CPU 50, a transmission supervisory timer TM, a parallel-serial converter 62 which converts a digital parallel signal to a serial signal, a serial-parallel converter 63 which converts a digital serial signal to a parallel signal, a fire signal receiving circuit 64, an interface 65, a transmission circuit TX and a receiving circuit RX. The slave unit C 1 is further equipped with a ROM 1 which stores the program shown in the flowchart of Figure 3 or another program, a ROM 2 which stores the address of the slave unit C 1, a RAM 1 which is used for working, a RAM 2 which stores a signal transmitted to the parallel-serial converter 62 by the CPU 50 (a signal henceforth transmitted from the slave unit C 1), RAM 11, RAM 12, RAM 13 which temporarily store signals to be transmitted to the control panel 10 or signals received from the control panel 10. The symbol "l" represents the signal line, and D 11 - D 1n, D 21 - D 2n, D 31 - D 3n represent fire detectors connected to the fire signal receiving circuit. The transmission circuit TX is an example of the signal transmission means which is set to a state ready for signal transmission by control of the signal processing part (CPU 50) when transmission of the signal is desired. The transmission supervisory timer TM is an example of the timer means which is triggered at the time of signal transmission and reset by the detection output of the signal detection means. The CPU 50, the receiving circuit RX, and the serial-parallel converter 63 are shown as an example of the signal detection means which detects the signal transmitted to the signal line l from the signal transmission means. The CPU 50 is an example of the signal output control means which switches off the signal transmission means when the given time of the transmission supervisory timer TM is reached. Figure 2 is a circuit diagram showing the transmission circuit TX and the receiving circuit RX in more detail. The transmission circuit TX is equipped with two inverters, two NOR's, transistors for phase conversion Q 1, Q 3, complementary transistors Q 2, Q4, and a Zener diode Z 1. The transmission circuit TX is equipped with an input terminal t 11 which receives the output signal from the serial-parallel converter 63, a control terminal t 12 which receives the control signal from the CPU 50, power supply terminals t 21, t 23, and an input/output terminal t 22. If the signal transmitted from the CPU 50 to the control terminal t 12 is L (low level state signal), one of the inputs on each of the two NOR gates goes to H (high level state), causing both transistors Q 2, Q 4 to switch off. Consequently, the output impedance of the transmission circuit TX becomes infinite, thus the transmission circuit is effectively disconnected from the signal line l. If the signal from the CPU 50 is H (high level state signal), one of the inputs on each of the two NOR gates goes to L, and the transmission circuit TX transmits the signal which is opposite to the output signal from the parallel-serial converter 62 to the signal line l. In other words, the transmission circuit TX is a sort of gate circuit which enters a non-operating state, allowing no signal to be transmitted from the parallel-serial converter 62 if the control signal from the CPU50 is L (OFF signal), and which enters a state ready for signal transmission and reverses the signal from the parallel-serial converter 62 and transmits it only if the control signal from the CPU 50 is H (ON signal). The receiving circuit RX is equipped with a transistor Q 5 for phase conversion and a Zener diode Z 2 provided across the base of the transistor Q 5 and the signal line l. Now, operation of the above mentioned embodiment will be described hereunder. Figure 3 is a flowchart diagram showing the operation of the embodiment. Firstly, the initial value is set (S 1). If it is necessary to send the signal to the control panel 10 (S 2), the address n for the selection of RAM 11 - RAM 13 is set to 1 (S 3), and the transmission circuit TX is set to the ON state (S 4). In other words, the CPU 50 sends the H signal to the terminal t 12 of the transmission circuit TX. Then, the CPU 50 sends the signal stored in the RAM 11, e.g. its own address, to the parallel-serial converter 62 and causes the RAM 2 to store the signal (S 5). The CPU 50 also sets the transmission supervisory timer TM to the ON state (S 6) and sends the transmission command to the parallel-serial converter 62 (S 7). On receipt of the transmission command, the parallel-serial converter 62 transmits a serial signal, which is reversed by the transmission circuit TX and transmitted to the signal line l via the input/output terminal t 22. The serial signal from the transmission circuit TX is detected by the receiving circuit RX and sent to the serial-parallel converter 63, generating a receiving interruption (S 11). If the signal sent to the serial-parallel converter 63 matches the signal stored in the RAM 2 (S 12), the transmission supervisory timer TM is set to the OFF state and cleared (S 13). And until the address n reaches the set value N, in other words, until transmission of e.g. fire information code and sum check code stored in RAM 12, RAM 13 are completed, the above mentioned operations are repeated (S14, 15). If the address n matches the set value N, the CPU 50 transmits the L level signal to the transmission circuit TX which goes to the OFF state (S 41). On the other hand, if there is no receiving interruption at the step S 11, and the time tm elapsed from the start of the timer TM has not reached the time T set in advance with the transmission supervisory timer (S 21), the receiving interruption is awaited (S 11). If the elapsed time tm has exceeded the set time T while awaiting the receiving interruption (S 21), the transmission circuit TX is set to the OFF state (S 22), because the control panel 10 or other slave units in normal condition cannot transmit a signal while the transmission circuit TX is in the ON state. More precisely, the timer TM transmits a transmission trouble signal to the CPU 50 if a given time, e.g. 0,5 seconds, of the timer TM has elapsed during which the receiving circuit RX is receiving no signal from the transmission circuit TX. Then, the CPU 50 transmits a L signal to the input terminal t 12 of the transmission Circuit TX, causing the transistors Q 2, Q 4 to switch off. In other words, by the transmission of the L signal from the CPU 50 and subsequently from the NOR gate in the transmission circuit TX, the collector of the transistor Q 1 goes High, and the transistor Q 2 switches off. In this case, the emitter of the transistor Q 3 goes Low, thus the transistor Q 4, too, switches off. Consequently, the output impedance of the transmission circuit TX becomes High, and the transmission circuit TX is effectively disconnected from the signal line l, which is now available to the control panal 10 or other slave units C 1. After the transmission circuit TX is set to the OFF state (S 22), the CPU 50 sets the timer TM to the OFF state for clearing the timer (S 23) and, if necessary, for operating a transmission trouble lamp (S 24) which indicates that the transmission circuit TX is in a troubled state. On the other hand, if the signal transmitted from the transmission circuit TX to the signal line l and received by the receiving circuit RX differs from the signal stored in the RAM 2 (S 12), it means that there is a fault in the transmission circuit TX or in the transmission system, in which case the transmission circuit TX is set to the OFF state (S 31), and the timer TM is set to the OFF state and cleared (S 32). When the signal from the transmission circuit TX is detected by the receiving circuit RX, is further transmitted to the serial-parallel converter 63, and the number of its input bits reaches the predetermined bit number , e.g. 8 bits, the input signal is compared with the signal stored in the RAM 2. If the result of this comparision is matching, the timer TM is set to the OFF state and is reset. Although the above embodiment shows an arrangement for triggering the timer TM when the signal to be stored in the RAM 11 - RAM 13 for transmission to the control panel 10 or slave units is transmitted to the parallel-serial converter 62, another arrangement may be made so that the timer TM can be triggered at the time of transmitting the transmission command to the parallel-serial converter 62. Further, the same signal as that transmitted to the parallel-serial converter 62 to one of RAM 11 - RAM 13 is stored in the RAM 2. Therefore, without providing a RAM 2, the RAM 11 - RAM 13 may be used in place of RAM 2. As descibed above, the present invention relates to a signal transmission circuit which transmits a signal from the signal processing portion provided in the control panel or terminal device of a disaster protection system to the signal line, and in which a timer means is triggered at the time of signal transmission, and is reset by the detection output of a signal detection means is provided so that the signal transmission means may be set to the OFF state when a given time of the timer means is reached. Therefore, the present invention has such an effect that even if the signal line is occupied as a result of occurence of an abnormality in the control panel or one of the terminal devices, it is immediately released from the occupied state and can be used by the control panel or other terminal devices being in normal condition.

Claims: A signal transmission circuit which is provided in a control panel or a terminal device of a disaster protection system and transmits a signal from a signal processing portion to a signal line, and which is equipped with a signal transmission means which is set to a state ready for signal transmission under control of the signal processing portion when transmission is desired, a signal detection means which detects the signal transmitted from the signal transmission means to the signal line, a timer means which is triggered at the time of signal transmission and reset by the output of the signal detection means, and a signal transmission control means which sets the signal transmission means to the OFF state when a given time of the timer means is reached. A signal transmission circuit of a disaster protection system as set forth in claim 1, wherein the signal transmission means is equipped with a signal transmission portion and a memory part which stores the signal sent to the signal transmission portion from the signal processing portion, and the signal detection means is equipped with a signal detection portion and a discrimination portion which generates a detection signal when the signal detected by the signal detection portion matches the signal stored in the memory portion. A signal transmission circuit of a disaster protection system as set forth in claim 1, wherein the timer means is triggered when the signal transmission means is set to a state ready for signal transmission. A signal transmission circuit of a disaster protection system as set forth in claim 1, wherein the timer means is triggered when the signal is transmitted from the signal processing portion to the signal transmission means.

Inventors: MORITA TOSHIKAZU NOHMI BOSAI K, MORITA, TOSHIKAZU NOHMI BOSAI K.K.K.
Applicants: NOHMI BOSAI LTD, NOHMI BOSAI LTD.
Application year: 1987
Main classification: G08B25
IPC codes: G08B17, A62C37, G08B25, A62C2