BOOTH'S CONVERSION CIRCUIT

Abstract: A first switch circuit (SW₁) which is supplied, at its input terminal, with signal X i of a logic level positioned in the i digit order of a multiplicand X, and which is rendered conductive or nonconductive according to the logic level of signal QX. A second switch circuit (SW₂), which is supplied, at its input terminal, with signal X i-1 of a logic level positioned in the i-1 digit order of the multiplicand X, and which is connected, at the output terminal, to the output terminal of the first switch circuit, and is rendered conductive or nonconductive accord­ ing to the logic level of signal Q2X. First and second MOS transistors (38, 39), which are connected in series between the junction of the output terminals of the first and second switch circuits and the ground, and are rendered conductive or nonconductive according to the logic levels of signals QX, Q2X. An exclusive OR circuit (14) which is connected, at its one input terminal, to the junction of fhe first and second switch circuits, and at the other input terminal, to a signal (N) of logic 1 or logic 0. The first and second transistors are ren­ dered conductive or nonconductive in an inverse relationship with the first and second switch circuits. Therefore, the number of elements and gates can be greatly reduced, with the result that the subject Booth's conversion circuit of this invention can he operated at high speed and occupies a much smaller space than the conventional Booth's conversion cir­ cuit.

Description: This invention relates to a Booth's conversion circuit involving Booth's algorithm. Generally, Booth's conversion can be expressed by the following theoretical formula: QB = N ⊕ (QX·X i + Q2X·X i-1 ) (1) where: QB = a converted value, N = logic 1 or logic 0, QX, Q2X = the logic values of multipliers, represented by logic 1 or logic 0 X i = the logic value of a signal positioned in the i digit order involved in a multiplicand X, and X i-1 = the logic value of a signal positioned in the i-1 digit order involved in a multiplicand X, and ⊕ denotes an exclusive logical sum, and · represents a logical product. Formula (1) may be converted into following formula (2) Fig. 1 represents a logic circuit in the form of a logically symbolized diagram, which operates according to theoretical formula (2). Reference numerals 11 to 13 given in Fig. 1 each denote a two-input NAND gate, and reference numeral 14, also in Fig. 1, represents a two-input exclusive OR gate. Signals QX and X i are input to the input terminals of NAND gate 11. Signals Q2X and X i-1 are input to the input terminals of NAND gate 12. Output signals of NAND gates 11 and 12 are input to input terminals of NAND gate 13. An output signal of NAND gate 13 is input to one input terminal of exclusive OR gate 14. Signal N is input to the other input terminal of exclusive OR gate 14. OR gate 14 outputs Booth-converted signal QB. Fig. 2 is a diagram of the logic circuit of Fig. 1. Referring to Fig. 2, portions therein which correspond to those of Fig. 1 are denoted by the same reference numerals. NAND gate 11 is formed of P channel type MOS transistors 15, 16 and N channel type MOS transistors 17, 18. NAND gate 12 is composed of P channel type MOS transistors 19, 20 and N channel type MOS transistors 21, 22. NAND gate 13 is composed of p channel type MOS transistors 23, 24 and N channel type MOS transistors 25, 26. Exclusive OR gate 14 comprises P channel type MOS transistors 27 to 29, and N channel type MOS transistors 30 to 32. NAND gate 11 receives signals QX, X i . NAND gate 12 is supplied with signals Q2X, X i-1 . Outputs from NAND gates 11, 12 are delivered to NAND gate 13. An output from NAND gate 13 and signal N are supplied to exclusive OR gate 14. Booth-converted output QB is obtained from exclusive OR gate 14. The operation of the Booth's conversion circuit shown in Fig. 2 will now be described. Now, let it be assumed that signals QX, X i have a high level ("H"). In this case, MOS (metal oxide semiconductor) transistors 15, 16 are rendered nonconductive, whereas MOS transistors 17, 18 are rendered conductive. As a result, the drain potential of MOS transistor 17 falls to ground potential (low potential). In other words, a low ("L") level signal is output from NAND gate 11. When signal X i has low ("L") level and QX has high ("H") level, MOS transistors 15, 17 are rendered conductive, while MOS transistors 16, 18 are rendered nonconductive. Consequently, the source potential of MOS transistor 17 is allowed to float because of the nonconductive state of MOS transistor 18. The drain potential of MOS transistor 15 is raised to high level, i.e., high power source potential V DD . As a result, an output signal from NAND gate 11 has high ("H") level. When signal QX has low ("L") level and signal X i has high ("H") level, MOS transistors 16, 18 are rendered conductive, whereas MOS transistors 15, 17 are rendered nonconductive. The drain potential of MOS transistor 18 retains floating because of the nonconductive condition of MOS transistor 17. The drain potential of MOS transistor 16 holds V DD potential, in which case an output signal from NAND gate 11 has a high potential. When signals QX, X i both have low ("L") level, MOS transistors 15, 16 are rendered conductive, and MOS transistors 17, 18 are rendered nonconductive. As a result, the drain potential of MOS transistors 15, 16 is raised to V DD potential, and an output from NAND gate 11 has high level. As is mentioned above, NAND gate 11 emits an output having low ("L") level when two input signals have high ("H") level, and outputs a signal having high ("H") level, in other cases. NAND gates 12, 13 are substantially the same in their structure and operation. Now, let it be assumed that signals Q2X, X i-1 have high level ("H"). In this case, MOS transistors 19, 20 are rendered nonconductive, whereas MOS transistors 21, 22 are rendered conductive. As a result, the drain potential of MOS transistor 21 falls to ground potential (low potential). In other words, a low ("L") level signal is output from NAND gate 12. When signal X i-1 has low ("L") level and Q2X has high ("H") level, MOS transistors 19, 21 are rendered conductive, while MOS transistors 20, 22 are rendered nonconductive. Consequently, the source potential of MOS transistor 21 is allowed to float because of the nonconductive state of MOS transistor 22. The drain potential of MOS transistor 19 is raised to high level, i.e., high power source potential V DD . As a result, an output signal from NAND gate 12 has high ("H") level. When signal Q2X has low ("L") level, and signal X i-1 has high ("H") level, MOS transistors 20, 22 are rendered conductive, whereas MOS transistors 19, 21 are rendered nonconductive. The drain potential of MOS transistor 22 retains floating because of the nonconductive condition of MOS transistor 21. The drain potential of MOS transistor 20 holes V DD potential, in which case, an output signal from NAND gate 12 has a high potential. When signals Q2X, X i-1 both have low ("L") level, MOS transistors 19, 20 are rendered conductive, and MOS transistors 21, 22 are rendered nonconductive. As a result, the drain potential of MOS transistors 19, 20 is raised to V DD potential, and an output from NAND gate 12 has high level. Now, let it be assumed that signals output from NAND gates 11, 12 have high level ("H"). In this case, MOS transistors 23, 24 are rendered nonconductive, whereas MOS transistors 25, 26 are rendered conductive. As a result, the drain potential of MOS transistor 25 falls to ground potential (low potential). In other words, a low ("L") level signal is output from NAND gate 13. When the output signal of NAND gate 11 has low ("L") level and the output signal of NAND gate 12 has high ("H") level, MOS transistors 23, 25 are rendered conductive, while MOS transistors 24, 26 are rendered nonconductive. Consequently, the source potential of MOS transistor 25 is allowed to float because of the nonconductive state of MOS transistor 26. The drain potential of MOS transistor 23 is raised to high level, i.e., high potential V DD . As a result, an output signal from NAND gate 13 has high ("H") level. When the output signal of NAND gate 11 has low ("L") level, and the output signal of NAND gate 12 has high ("H") level, MOS transistors 24, 26 are rendered conductive, whereas MOS transistors 23, 25 are rendered nonconductive. The drain potential of MOS transistor 26 retains floating because of the nonconductive condition of MOS transistor 25. The drain potential of MOS transistor 24 holds V DD potential, in which case, an output signal from NAND gate 13 has a high potential. When the output signals of NAND gates 11, 12 both have low ("L") level, MOS transistors 23, 24 are rendered conductive, and MOS transistors 25, 26 are rendered nonconductive. As a result, the drain potential of MOS transistors 23, 24 is raised to V DD potential, and an output from NAND gate 13 has high level. When an output from NAND gate 13 and signal N both have high ("H") level, MOS transistors 30, 31 are rendered conductive, and MOS transistors 27-29 are rendered nonconductive. The drain potential of MOS transistor 30 is reduced to the ground potential. The source of MOS transistor 31 and the gate of MOS transistor 32 are grounded via MOS transistor 30, and have low "L" level. As a result, MOS transistor 32 is rendered nonconductive, and the drain of MOS transistor 31 is connected to the ground potential. Therefore, exclusive OR gate 14 emits output signal QB having low ("L") level. When, on the other hand, an output signal from NAND gate 13 and signal N both have low ("L") level, MOS transistors 27-29 are rendered conductive and MOS transistors 30-31 are rendered nonconductive. As a result, the drain potential of MOS transistor 27 is raised to high potential V DD , and the high ("H") level signal is supplied to the source of MOS transistor 31 and the gate of MOS transistor 32. When MOS transistor 32 is rendered conductive upon receipt of the high ("H") level signal, the source of MOS transistor 32 is reduced to low ("L") level. The drain of transistor 32 also falls to low ("L") level. The drain potential of MOS transistor 29 is also reduced to low ("L") level because the source of MOS transistor 29 has low ("L") level. Since the drain potential of MOS transistors 29, 32 falls to low ("L") level, an output signal QB from exclusive OR gate 14 has low ("L") level. When an output signal from NAND gate 13 has high ("H") level, and signal N has low ("L") level, MOS transistors 30, 28 are rendered conductive, and MOS transistors 27, 29, 31 are rendered nonconductive. As a result, the drain potential of MOS transistor 30 falls to ground level. The gate potential of MOS transistor 32 falls to low ("L") level, causing MOS transistor 32 to be rendered nonconductive. On the other hand, the drain potential of MOS transistor 28 has high ("H") level, because the source potential of MOS transistor 28 has high ("H") level and the gate potential has low ("L") level. As a result, an output signal QB from exclusive OR gate 14 has high ("H") level. When an output signal from NAND gate 13 has low ("L") level and signal N has high ("H") level, MOS transistors 27, 29, 31 are rendered conductive, and MOS transistors 30, 28 are rendered nonconductive. When rendered conductive, MOS transistor 27 has its drain potential raised to high ("H") level. MOS transistor 32 is rendered conductive, because its gate is supplied with the high ("H") level signal from the drain of MOS transistor 27. Since, on the other hand, the sources of transistors 29, 32 are supplied with high level ("H") signal, the drain potentials of MOS transistors 29, 32 have high ("H") level. Consequently, output signal QB from exclusive OR gate 14 has high ("H") level. As can be clearly understood from the above, only when it is supplied with two input signals having different voltage levels (namely, one input signal having high ("H") level and the other signal having low ("L") level), does exclusive OR gate 14 output a high ("H") level signal. When both input signals have the same voltage level (namely, both input signals have either high ("H") or low ("L") level), exclusive OR gate 14 issues a low ("L") level signal, thereby acting as an exclusive logical sum circuit. NAND gates 11 to 13 and exclusive OR gate 14 cooperate to perform Booth's conversion. However, since, in the conventional Booth's conversion circuit, as can be seen from Figs. 1 and 2, an output signal is emitted via three logic circuit stages (a stage of NOR gates 11, 12, a stage of NOR gate 13, and a stage of exclusive OR circuit 14), a time delay corresponding to the total of the time periods spent in the three stages occurs before a Booth-converted output is produced, thus rendering the conventional Booth's conversion circuit unsuitable for high-speed operation. Since four logic circuits, i.e., 11, 12, 13, and 14 are involved, the conventional Booth's conversion circuit involves a large circuit system, occupying a considerable proportion of an integrated circuit chip. In particular, when Booth's algorithm is applied, the multiplier circuit has to be provided with numerous Booth's conversion circuits, with the result that the multiplier device occupies a large area on the semi-conductor chip. Document EP-A-0 094 234 teaches how logic networks can be fabricated using PASS transistors so as to maximize the regularity of the resulting logic circuitry. Pass transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. The resulting logical networks give significant topological, power and speed advantages over prior art logic circuits when used to form combinational logic. This invention has been accomplished in view of the above-mentioned circumstances, and is intended to provide a Booth's conversion circuit which ensures a high-speed operation and occupies a small space. According to the invention, an improved Booth's conversion circuit is provided, as claimed in claim 1. In the Booth's conversion circuit embodying the present invention, the first and second transistors are rendered conductive or nonconductive in an inverse relationship with the first and second switch circuits. The junction of the output terminals of the first and second switch circuits has the same logic level as an output from NAND gate 13 shown in Fig. 1. Therefore, the number of elements and gates can be greatly reduced, thereby enabling the Booth's conversion circuit according to the present invention to be operated at high speed and to occupy a much smaller space than the conventional Booth's conversion circuit. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a logically symbolized diagram of a Booth's conversion circuit performing the logic formula involved in Booth's conversion; Fig. 2 is a diagram showing Booth's conversion circuit of Fig. 1; Fig. 3 shows a Booth's conversion circuit according to an embodiment of the present invention; Fig. 4 is a truth table applied in the operating of the Booth's conversion circuit of Fig. 3; and Figs. 5 and 6 illustrate modifications of a switch circuit used in the Booth's conversion circuit of Fig. 3. Description may now be made with reference to Fig. 3 of Booth's conversion circuit embodying the present invention. The input terminal of switch circuit SW₁ composed of a parallel circuit of P channel type MOS (metal oxide semiconductor) transistor 33 and N channel type MOS transistor 34, namely one end of the junction of transistors 33, 34, is supplied with signal X i of a logic level, positioned in the i digit order of a multiplicand. The input terminal of a switch circuit SW₂ composed of a parallel circuit of p channel type MOS transistor 35 and N channel type MOS transistor 36, namely, one end of the junction of transistors 35, 36, is supplied with a signal X i-1 of a logic level, positioned in the i-1 digit order of the multiplicand. The gate of MOS transistor 33 is supplied with logic signal QX of logic 1 or logic 0. The gate of MOS transistor 34 is supplied with logic signal QX of logic 1 or logic 0. The gate of MOS transistor 35 is supplied with logic signal Q2X of logic 1 or logic 0, and the gate of MOS transistor 36 is supplied with logic signal Q2X of logic 1 or logic 0. The output terminal of switch circuit SW₁, namely, the other end of the junction of transistors 33, 34, is connected to the output terminal of switch circuit SW₂ namely, the other end of the junction of transistors 35, 36. N channel MOS transistor 38 whose gate is supplied with logic signal Q2X and N channel MOS transistor 39 whose gate is supplied with control signal QX are connected in series between junction 37 of the output terminals of switch circuits SW₁ and SW₂ and the ground. One of the input terminals of exclusive OR gate 14 is connected to junction 37. The output terminal of exclusive OR gate 14 outputs Booth-converted signal QB. Exclusive OR gate 14 comprises P channel type MOS transistors 27, 28, 29, and N channel type MOS transistors 30, 31, 32. Junction 37 is connected to the gates of P channel type MOS transistor 27 and N channel type transistor 30 which are connected in series between high potential power source V DD and the ground. MOS transistors 27, 30 jointly constitute CMOS (complementary MOS) inverter 40. The junction between the gates of MOS transistors 27, 30 forms one input terminal of inverter 40. The gate of P channel type MOS transistor 29 and the source of P channel type MOS transistor 28 are connected to junction 37. The gate of N channel type MOS transistor 32 and the source of N channel type MOS transistor 31 are connected to the junction of the drain-source paths of MOS transistors 27, 30. MOS transistors 29, 32 connected in parallel jointly constitute switch circuit SW₃. The input terminal of switch circuit SW₃, that is, one of the junctions of transistors 29, 32, is supplied with signal N having logic level "1" or "0". The input terminal of switch circuit SW₃ for receiving signal N constitutes the other input terminal of exclusive OR circuit 14. The drains of MOS transistors 28, 31 are connected to the output terminal of switch circuit SW₃, that is, the other junction between transistors 29, 32. The gates of MOS transistors 28, 31 are supplied with signal N. Booth-converted output signal QB is obtained from the junction of MOS transistors 28, 31, which constitutes the output terminal of exclusive OR circuit 14 and, thus, the output terminal of Booth's conversion circuit. The Booth's conversion circuit of the present invention, shown in Fig. 3, will now be described. Now, let it be assumed that signals X i and X i-1 have low ("L") level and signals QX, Q2X also have low ("L") level. In this case, MOS transistors 33-36 are rendered nonconductive, and MOS transistors 38, 39 are rendered conductive. Since MOS transistors 33-36 are rendered nonconductive, signals X i and X i-1 are not transmitted via switch circuits SW₁, SW₂. As a result, the potential of junction 37 is reduced to low ("L") level (ground level) through transistors 38, 39. The low ("L") level signal of junction 37 is supplied to the input terminal of CMOS inverter 40, namely, the junction of the gates of MOS transistors 27, 30. As a result, P channel type MOS transistor 27 is rendered conductive, and N channel type MOS transistor 30 is rendered nonconductive. Therefore, a high ("H") level signal is output from the output terminal of CMOS inverter 40, namely, the junction of the drain-source paths of transistors 27, 30. As a result, MOS transistors 29, 32 of switch circuit SW₃ are rendered conductive. If, at this time, signal N has low ("L") level, then this low signal is supplied to the junction of the drains of MOS transistors 28, 31 through switch circuit SW₃. Since, on the other hand, the gates of MOS transistors 28, 31 are supplied with signal N having low ("L") level, MOS transistor 28 is rendered conductive and MOS transistor 31 is rendered nonconductive. Since the source of MOS transistor 28 has low ("L") level and the junction of the drains of transistors 28, 31 is supplied with signal N having low ("L") level through switch circuit SW₃, output signal QB has low ("L") level. Now, let it be assumed that signal QX has a high ("H") level (signal QX has low ("L") level) and other signals have the same level as mentioned above (namely, signals Q2X, X i and X i-1 have low ("L") level). In this case, switch circuit SW₁ is rendered conductive, and switch circuit SW₂ is rendered nonconductive. Since, on the other hand, MOS transistor 39 is rendered nonconductive, signal X i is supplied to the input terminal of CMOS inverter 40 via switch circuit SW₁. If, at this time, signal N has low ("L") level, the low ("L") level signal is supplied to the Input terminal of switch SW₃. The low level N signal is also applied to the gates of MOS transistors 28, 31 causing MOS transistor 28 to be rendered conductive and MOS transistor 31 to be rendered nonconductive. Since the source of MOS transistor 28 is connected to the input terminal of CMOS inverter 40, the drain of MOS transistor 28 is supplied with low ("L") level signal X i . Since signal X i now has low ("L") level, switch SW₃ is rendered conductive. Consequently, signal X i is output as signal QB via switch circuit SW₃. When signal Q2X has high ("H") level (signal Q2X has low ("L") level), and signal QX has low ("L") level (signal QX has high ("H") level), switch circuit SW₂ is rendered conductive and switch circuit SW₁ is rendered nonconductive. MOS transistor 39 is rendered conductive, and MOS transistor 38 is rendered nonconductive. Therefore, the input terminal of CMOS inverter 40 is supplied with signal X i-1 . If, at this time, signal N has low ("L") level, MOS transistor 28 is rendered conductive, and MOS transistor 31 is rendered nonconductive. Since the source of MOS transistor 28 is connected to the input terminal of CMOS inverter 40, the drain of MOS transistor 28 is supplied with signal X i-1 . Therefore, output signal QB is represented by signal X i-1 . When both signals QX, Q2X have low ("L") level, switch circuits SW₁, SW₂ are rendered nonconductive, and MOS transistors 38, 39 are rendered conductive. Consequently, the input terminal of CMOS inverter 40 is supplied with low ("L") level signal. As a result, MOS transistors 29, 32 involved in switch circuit SW₃ are rendered conductive. If, at this time, signal N has high ("H") level, the input terminal of switch circuit SW₃ is supplied with the high ("H") level signal. MOS transistors 28, 31 are also supplied with the high ("H") N level signal. As a result, MOS transistor 31 is rendered conductive, and MOS transistor 28 is rendered nonconductive. Therefore, the output terminal of switch circuit SW₃ outputs high ("H") level signal. The source of MOS transistor 31 is supplied with the high ("H") level signal of CMOS inverter 40. Therefore, the drain of MOS transistor 31 also receives a high ("H") level signal. In other words, output signal QB has high ("H") level. When signal QX has high ("H") level, and signal Q2X has low ("L") level, switch circuit SW₁ is rendered conductive and switch circuit SW₂ is rendered nonconductive. At the same time, MOS transistor 38 is rendered conductive and MOS transistor 39 is rendered nonconductive. Consequently the input terminal of CMOS inverter 40 is supplied with signal X i . If, at this time signal N has high ("H") level, the high ("H") level signal is supplied to the input terminal of switch circuit SW₃. The high level N signal is also delivered to the gates of MOS transistors 28, 31. As a result, MOS transistor 31 is rendered conductive, and MOS transistor 28 is rendered nonconductive. Since the source of MOS transistor 31 is connected to the output terminal of CMOS inverter 40, the source of MOS transistor 31 is supplied with signal X i obtained by the inversion of signal X i , and signal X i is delivered to the drain of MOS transistor 31. When signal X i has high ("H") level, switch circuit SW₃ is rendered conductive. As a result, the high ("H") level N signal is transmitted, and output signal QB is represented by X i . When signal Q2X has high ("H") level and signal QX has low ("L") level, then switch circuit SW₂ is rendered conductive and switch circuit SW₁ is rendered nonconductive. MOS transistor 39 is rendered conductive and MOS transistor 38 is rendered nonconductive. As a result, the input terminal of CMOS inverter 40 is supplied with signal X i-1 . If, at this time, signal N has high ("H") level, the high (High) level signal is supplied to the input terminal of switch circuit SW₃. At the same time, the gates of MOS transistors 28, 31 are supplied with the high ("H") level N signal. As a result, MOS transistor 31 is rendered conductive, and MOS transistor 28 is rendered nonconductive. Since the source of MOS transistor 31 is connected to the output terminal of CMOS inverter, the source of MOS transistor 31 is supplied with signal X i-1 obtained by the inversion of signal X i-1 . The drain of MOS transistor 31 is supplied with signal X i-1 . Switch circuit SW₃ is rendered conductive when signal X i-1 has high ("H") level. At this time the high ("H") level N signal is transmitted to the output terminal of switch circuit SW₃. Therefore, output signal QB is represented by X i-1 . All the aforementioned operations are graphically illustrated in Table 4. The operations shown in the truth table of Fig. 4 are based on the aforementioned logical formula (1). The logical circuit of Fig. 3 produces a Booth-converted output. The Booth's conversion circuit of this invention offers the advantages that, though the conventional Booth's conversion circuit of Fig. 1 comprises 18 elements and entails a delay time of 4.7 n seconds, the present invention comprises only 12 elements and the delay time is reduced to 2.6 n seconds, thus making it possible to reduce the number of elements by about 33 % and shorten the delay time by about 55 %. The aforementioned embodiment of the present invention refers to the CMOS arrangement. However, the invention is not limited to this example, but is applicable in various modifications thereof. In the embodiment, switch circuits SW₁ and SW₂ each included transmission gates comprised of a P channel type MOS transistor and an N channel type MOS transistor. As is shown in Fig. 5, however, it is possible for circuit SW₁ and SW₂ each to have only one P channel type MOS transistor 51, or, as is shown in Fig. 6, only one N channel type MOS transistor 61. When only one P channel type MOS transistor 51 is used for switch circuit SW1, the gate of MOS transistor 51 is supplied with signal QX . Also when only one P channel type MOS transistor 51 is used for switch circuit SW2, the gate of MOS transistor 51 is supplied with signal Q2X . Similarly, when only one N channel type MOS transistor 61 is used for switch circuit SW1, the gate of MOS transistor 61 is supplied with signal QX. Likewise, when only one N channel type MOS transistor 61 is used for switch circuit SW2, the gate of MOS transistor 61 is supplied with signal Q2X. Further, if it is possible to obtain an exclusive logical sum, exclusive OR gate 14 may be formed of a different type. As has been described above, the present invention can provide a Booth's conversion circuit which occupies a small area and can be operated at high speed.

Claims: A Booth's conversion circuit for performing a Booth's conversion expressed by the following theoretical formula: QB = N ⊕ (QX·X i + Q2X·X i-1 ) where: QB = the converted value, N = N-signal (N) of value 0, QX, Q2X = Q X -signal and Q 2X -signal having the logic values of multipliers, represented by logic 1 or logic 0 X i = X i -signal having the logic value of a signal positioned in the i digit order involved in the multiplicand X, and X i-1 = X i-1 -signal having the logic value of a signal positioned in the i-1 digit order involved in the multiplicand X, and ⊕ denotes an exclusive logical sum, and · represents a logical product, comprising: a first switch circuit (SW₁) whose input terminal is supplied with said X i -signal, and which is rendered conductive or nonconductive according to the logic level of said QX-signal; a second switch circuit (SW₂), whose input terminal is supplied with said X i-1 -signal, whose output terminal is connected to the output terminal of said first switch circuit (SW₁), and which is rendered conductive or nonconductive according to the logic level of said Q2X-signal; first and second transistors (38, 39) which are connected in series between the junction of said output terminals of said first and second switches and a reference potential, and which are rendered conductive or nonconductive according to the logic levels of said Q X -signal and Q 2X -signal, respectively, and whose conductive and nonconductive states are reversed from those of said first and second transistors (38, 39) respectively; and an exclusive logical sum circuit (14), one of whose input terminals is connected to said junction of said first and second switch circuits, and the other of whose input terminals is supplied with said N-signal (N), whose output terminal represents said converted value (Q B ). The Booth's conversion circuit according to claim 1, wherein said first switch circuit (SW₁) comprises a parallel circuit of a P channel type MOS transistor (33) and an N channel type MOS transistor (34). The Booth's conversion circuit according to claim 1, wherein said second switch circuit (SW₂) comprises a parallel circuit of a P channel type MOS transistor (35) and an N channel type transistor (36). The Booth's conversion circuit according to claim 1, wherein said first switch circuit (SW₁) comprises a P type channel MOS transistor (51). The Booth's conversion circuit according to claim 1, wherein said first switch circuit (SW₁) comprises an N channel type MOS transistor (61). The Booth's conversion circuit according to claim 1, wherein said exclusive logical sum circuit (14) comprises: a CMOS inverter (40) which includes a P channel type transistor (27) and an N channel type transistor (30), connected in series between a high potential (V DD ) and a low potential (ground), the gates of said P and N channel type transistors (27, 30) being connected together to constitute an input terminal, and the junction (37) of the drain-source paths of said P and N channel type transistors (27, 30) constituting the output terminal of the CMOS inverter; a switch circuit (SW3) which includes a parallel-connected circuit of a P channel type MOS transistor (29) so controlled as to be rendered conductive or nonconductive according to the potential level of said input terminal of said CMOS inverter, and an N channel type MOS transistor (32) so controlled as to be rendered conductive or nonconductive according to the potential level of said output terminal of said CMOS inverter; and a circuit including a P channel type transistor (28) and an N channel type transistor (31) connected in series between said input terminal and output terminal of said CMOS inverter, said P channel type transistor (28) and N channel type transistor (31) being so controlled as to be rendered conductive or nonconductive according to the logic level "1" or "0" of said N-signal (N) supplied to the gates of said P and N channel type transistors (28, 31), and the junction of the drain-source paths of said P channel type transistor (28) and the N channel type transistor (31) being connected to the output terminal of said last-recited switch circuit (SW3).

Inventors: KAMATANI, YUKIO C/O PATENT DIVISION, SUGIMOTO, YASUHIRO C/O PATENT DIVISION, SUGIYAMA, HISASHI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: G06F7
IPC codes: G06F7