WAVEFORM GENERATOR FOR ELECTRONIC MUSICAL INSTRUMENT

Abstract: A plurality of waveforms are time-divisionally obtained from a waveform generator (6) in one sampling period un­ der the control of a controller (6). The sampling period is equally divided into a plurality of module periods. Each module period is also divided to correspond to the number of waves which are obtained time-divisionally. The waveform generator (6) includes a selector which uses waveform data produced in a preceding module in the sam­ pling period as that for waveform generation in the following module.

Description: The present invention relates to a waveform generator, which generates musical tone waveforms for an electronic musical instrument, and a method of generating a waveform. Various methods or apparatuses for generating musical tone waveforms are known. Such methods or apparatuses include: (A) A method or apparatus for storing a waveform corresponding to each tone color in a memory, and reading it out. More specifically, such a method or apparatus is described in U.S.P. No. 3,639,913 (issued on February 1, 1972), U.S.P. No. 3,882,751 (issued on May 13, 1975), and the like. (B) A method or apparatus for multiplying a sine wave of a fundamental frequency and a sine wave of each harmonic component with a Fourier coefficient and synthesizing resultant products to produce a waveform in accordance with a Fourier synthesis method, i.e., ansinnω0t (where ω0 is a fundamental frequency, such a method or apparatus is described in U.S.P. No. 3,809,786 (issued on May 7, 1974). With method or apparatus (A), various waveforms cannot be stored in a memory unless the memory has a large storage capacity. More specifically, the storage capacity poses a problem. In addition, waveforms other than those stored in the waveform memory cannot be produced. With method or apparatus (B), in order to obtain a musical tone having desired harmonic overtone components, calculations must be performed a plurality of times corresponding to the number of harmonic overtone components, or sine wave generators corresponding in number to the harmonic overtone components must be required. In addition, the following method or apparatus is known. (C) A method or apparatus in accordance with FM modulation. More specifically, waveforms are produced in accordance with the following equation: Y2 = Asin(ω c t + Isinω m t) (where ω c is a carrier angular frequency, ω m is an angular frequency of a modulated wave, I is a modulation index, and A is an amplitude.) Such a method or apparatus is disclosed in U.S.P. No. 4,018,121 (issued on April 19, 1977). With this FM modulation method, waveforms including many harmonic overtone components can be generated by a relatively small sine wave generating system. However, when resultant waveforms are evaluated in terms of their spectra, a waveform with a moderate spectrum envelope cannot be generated, and a waveform string whose spectrum distribution gradually changes, cannot be generated. (D) A method or apparatus in accordance with a PD (phase distortion) method. This method or apparatus relates to a content previously proposed by the present assignee (e.g., USSN No. 788,669 filed on October 17, 1985 issued on April 21, 1987 under US-4,658,691). With this method, phase angle signals for reading a sine wave stored in a single musical tone waveform memory are modified by a phase angle modifying circuit, and various waveforms such as a sawtooth wave and a sine wave can be generated. However, in a detailed circuit arrangement for method (D), the phase angle modifying circuit is constituted by divides, resulting in a bulky apparatus. The present invention has been made in consideration of the above situation, and has as its principal object to provide a waveform generator for an electronic musical instrument, which can generate various waveforms by a compact circuit arrangement. It is an object of the present invention to provide a waveform generator for an electronic musical instrument, wherein a waveform generator which generates a plurality of waveforms in a time-divisional manner, and outputs accumulated data of these waveforms as a final output for a unit sampling period is used, and preceding waveforms or accumulated waveforms generated in the same sampling period are selectively used as data for the next waveform generation, so as to obtain various waveforms. It is another object of the present invention to provide a waveform generator for an electronic musical instrument, which can generate various waveforms having smooth spectrum envelopes with a simple arrangement. The object is solved by the waveform generator with the features of claims 1 and 9, and by the method with features of claims 11 and 12. According to the present invention, there is provided a waveform generator for an electronic musical instrument, having control means and waveform generating means for time-divisionally generating a plurality of waveforms and accumulating the waveforms in a unit sampling period to obtain a final output under the control of the control means, wherein the waveform generating means comprises a selective operation means which is selectively operated using at least one of a preceding waveform and a sum of the waveforms already generated in the same sampling period as data used for a waveform to be generated next. According to the present invention, there is further provided a waveform generator for an electronic musical instrument, comprising: phase angle generating means for generating phase angle data which changes at a frequency corresponding to a depressed key; data setting means for generating control data for modifying the phase angle data; phase angle modifying means for modifying the phase angle data in accordance with the control data and outputting modified phase angle data; and a musical tone memory whose address is designated by the output from the phase angle modifying means, wherein the phase angle updating means has shift means for bit-shifting the phase angle data in different directions using the control data, and bit-shift direction selecting means for switching the direction of bit shifting to define an inclination of the modified phase angle data as the output from the phase angle modifying means at a timing during one cycle of the waveform. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing an electronic musical instrument to which the present invention is applied; Fig. 2 is a format showing module times and channel times in one sampling period used in an embodiment; Fig. 3 is a block diagram of waveform generator 6 as the main part of the embodiment of the present invention; Figs. 4A to 4G are graphs for explaining the function of a phase angle modifying circuit; Fig. 5 is a block diagram showing the arrangement of a phase angle modifying circuit of the embodiment of the present invention; Fig. 6 is a waveform chart showing various waveforms generated in the embodiment of the present invention; Fig. 7 is a spectrum chart showing spectra of various waveforms produced in the embodiment of the present invention; Figs. 8A and 8B show, in combination, a timing chart for explaining the operation of the waveform generator; Fig. 9 is a block diagram of a control circuit; and Fig. 10 is a block diagram of another electronic musical instrument using a phase angle modifying circuit shown in Fig. 5. Fig. 1 is a block diagram of an electronic musical instrument to which the present invention is applied. In this case, the electronic musical instrument is of an 8-tone polyphonic type for the sake of simplicity. On keyboard circuit 1, switches for detecting ON/OFF of keys are arranged in a matrix, and are scanned by key assigner 2. Key assigner 2 detects ON/OFF of the keys of keyboard circuit 1, and generates, upon detection of key depression, key code KC0 and attack start signal A0 corresponding to the detected key for a tone generation channel (assumed to be channel 0) which is not currently subjected to tone generation. Envelope generator 3, original phase angle generator 4, and waveform generator 6 process four series of data for each of eight tones, i.e., a total of 32 series of data. In Fig. 2, the four series are denoted as modules 0 to 3, to be assigned within one sampling period. Each module is divided into eight sections to serve as channels 0 to 7. Assuming that a sampling frequency is 50 kHz, the operating frequency is 32 x 50 kHz = 1.6 MHz. For the sake of simplicity, suffix for modules 0 to 3 is given by i , and suffix for channels 0 to 7 is given by j , and data Y in module i and channel j is indicated by Yij. In response to attack start signal A0, envelope generator 3 begins to generate envelope waveform Ei0 for the four series. (Note that if the above-mentioned key is turned off, key assigner 2 generates decay start signal D0 to tone generation channel 0 to release the envelope. Envelope generator 3 generates envelope end signal EFi0 upon completion of releasing. Upon reception of envelope end signal EFi0, key assigner 2 stores that the corresponding tone generation channel is empty.) Original phase angle generator 4 receives key code KC0 from key assigner 2, and accumulates four series of frequency numbers Ri0 to generate original phase angle data qRi0. Waveform generator 6 is the main feature of the present invention. Generator 6 receives clocks L, a , 1, and 2 and control signals C0 to C8 from the control circuit 5, and original phase angle data qRi0, from original phase angle generator 4, and envelope Ei0 from envelope generator 3 to generate a desired waveform, and adds the waveforms for the respective channels so as to output final waveform W. Sound system 7 receives final waveform W as digital data, and D/A converts it to generate a sound. Fig. 3 is a detailed block diagram of waveform generator 6. All FFs (flip-flops) and shift registers in Fig. 3 are operated in response to two-phase clocks 1 and 2 (not shown in Fig. 3). Selector 8 selects final phase angle data and is operated as follows: 5-stage shift register 9 delays an input signal by 5-bit time. Phase angle modifying circuit 10 switches a conversion coefficient between original phase angle data X and modified phase angle data X', so that the inclination of modified phase angle data X' changes stepwise in accordance with original phase angle data X. More specifically, Figs. 4A to 4G show the modifying method of phase angle changing circuit 10. Fig. 4G shows the relationship between original phase angle data X and modified phase angle data X' for finally accessing sine wave memory 12. As can be apparent from Fig. 4G, in a function characterizing the relationship between these two data, the inclination, i.e., a multiplier to be multiplied with X, varies in accordance with the value of X. If the multipliers are given as α (0 ≦ X < M, N - M ≦ X < N) and as β (M ≦ X < N - M) , α = (N/4)/M β = (N/4)/(N/2 - M) Therefore, 1/α + 1/β = 2. Note that N represents one period 2π of sine wave memory 12, and M represents a switching point of the multipliers. If X = M, X' = N/4 and the maximum value of the sine waves in sine wave memory 12 is accessed (see Fig. 6). For example, if β = α/2 k , α = (2 k + 1)/2 β = (1 + 2 -k )/2 Therefore, multiplication for changing phases can be executed by a bit shift method. Figs. 4A to 4G show the procedures for producing finally modified phase angle data X' from original phase angle data X. X0' in Fig. 4A is obtained by subtracting most significant bit X MSB from X; X1' and X1'' in Figs. 4B and 4C are obtained by appropriately inverting X0', X2' in Fig. 4D is obtained by multiplying X1' with β, X2'' in Fig. 4E is obtained by multiplying X1'' with α, and X3' in Fig. 4F is obtained by linking X2'' and X2' as follows: Finally modified phase angle data X' shown in Fig. 4G is obtained using X3' shown in Fig. 4F as follows: Fig. 5 shows a circuit for executing the processing explained with reference to Figs. 4A to 4G. Original phase angle data X supplied from 5-stage shift register 9 is inverted by inverting circuits 111 and 114 whose outputs are inverted when inverting control inputs R are set at "1" level in accordance with most significant bit X MSB . More specifically, since inverting circuit 111 receives X MSB through inverter 110, it is in the inverting mode if X MSB = 0, and is in noninverting mode if X MSB = 1. On the other hand, inverting circuit 114 is set in the noninverting mode if X MSB = 0, and is in the inverting mode if X MSB = 1. Therefore, the outputs from the inverting circuits 111 and 114 correspond to X1' and X1'' shown in Figs. 4B and 4C, respectively. Inverting circuits 111 and 114 preferably output a complementary number of 2 in the inverting mode in terms of precision. Alternatively, an exclusive OR group (EX-OR group) for producing a complementary number of 1 can be adopted instead. Left-shift circuit 112 and adder 113 multiply X1' with above-mentioned multiplier β in accordance with control inputs S0 to S2, i.e., C4 to C6 (binary data corresponding to k ). The input to adder 113 is left-shifted (multiplied with 1/2), and adder 113 executes the following relation: (where k = 0 to 7) Similarly, right-shift circuit 115 and adder 116 multiply X1'' with above-mentioned multiplier α, and execute: Selector 117 produces X3' shown in Fig. 4F, and selects one of outputs X2' and X2'' from adders 113 and 116. When adder 113 outputs carry out C0, i.e., only when X2' ≧ N/4 in Fig. 4D, selector 117 selects X2''; otherwise, it selects X2'. Inverting circuit 118 is set in the inverting mode when inverting control input R is "1" in the same manner as in inverting circuits 111 and 114. Inverting circuit 118 inverts X3' in accordance with an output from EX-OR gate 119 receiving X MSB and carry out C0, so that the polarity of the inclination of X3' shown in Fig. 4F becomes positive. (a) If X = 0 to M, since X MSB = 0 and C0 = 1, X3' is not inverted. (b) If X = M to N/2, since X MSB = 0 and C0 = 0, X3' is inverted. (c) If X = N/2 to N - M, since X MSB = 1 and C0 = 0, X3' is not inverted. (d) If X = N - M to N, since X MSB = 1 and C0 = 1, X3' is inverted. Furthermore, when the output from inverting circuit 118 is added to the output from the EX-OR gate 119 and X MSB as upper bits, X' shown in Fig. 4G, i.e., modified phase angle data can be obtained. Figs. 6 and 7 show waveforms and their spectra generated when sine wave memory 12 is accessed by output X' from phase angle modifying circuit 10 with respect to various values of k . As the value of k increases 0 to 7, the spectrum gradually increases in amplitude in a sawtooth wave manner. More specifically, circuit 10 of this embodiment produces output X' shown in Fig. 4G with respect to input X, and sine wave memory 12 is accessed by output X', thus obtaining a distorted waveform output shown in Fig. 6. Since the control input to phase angle modifying circuit 10 has a 3-bit configuration, waveforms distorted by eight-step depths (= k) can be obtained. More specifically, when the output from the phase angle modifying circuit 10 is used as an address of sine wave memory 12, this is equivalent to that the apparatus of this embodiment has memories for eight types of waveforms as shown in Fig. 6 (their spectra are shown in Fig. 7). Output sinX' from sine wave memory 12 is multiplied with modified envelope E'ij by multiplier 14 through FF 13. Output E'ijsinX' from multiplier 14 is input to selector 8 and adder 16 through FF 15. Adder 16 adds output E'ijsinX' from multiplier 14 and the output from gate 24, and its output is input to selectors 8, 17, and 25. Selector 17 switches whether or not the storage contents of 6-stage shift register 18 and 2-stage shift register 19 are changed. If S = 0, selector 17 selects an A input (storage content is changed) and if S = 1, a B input (storage content is held). The output from 6-stage shift register 18 is added to envelope Eij by adder 21 through gate 20 to produce changed envelope E'ij, which is input to multiplier 14. If control input G is "1", gate 20 allows input data to be output to adder 21, and if it is "0", outputs all "0" data. Thus, it can be selected whether or not the contents of shift registers 18 and 19 constituting a memory circuit, for example, preceding sine wave data for one module, is multiplied with waveform sinX' output from sine wave memory 12. Selector 23 selects one of the outputs from FF 26 or 2-stage shift register 19, and supplies the selected output to adder 16 through gate 24. Selector 23 performs selection as follows: GS = 0* → All "0" GS = 10 → output from FF 26 GS = 11 → output from 2-stage shift register 19 Selector 25, FF 26, and gate 27 store data obtained by accumulating all the output data during a unit sampling period, and the storage operation is performed by switching whether the content of FF 26 is held or changed by selector 25. Gate 27 sets preceding data to be all "0" at the beginning of the sampling period. Latch 28 latches the content of FF 26 at a timing corresponding to a sum of all the data during each sampling period, and outputs the latched data. As described above, when control signals C0 to C8 are appropriately switched, various waveform calculations are allowed. The operation timings and control signals C0 to C8 will now be described. As can be understood from the above description, the functions of control signals C0 to C8 are as follows: C0, C1: B input selection of adder 16 C2, C3: selection of final phase angle data X C4, C5, C6: designation of phase angle modifying degree C7: changing of storage data C8: whether or not waveform multiplication is performed These signals C0 to C8 are appropriately generated for each module, so as to perform a desired waveform calculation. Figs. 8A and 8B show the operation timings of the function blocks in Fig. 3 with reference to the operation start time of selector 8. Reference symbols 1 and 2 denote operation clocks. Clock 1 is a read clock, and clock 2 is an output clock. Reference symbol ACK denotes an address clock for reading out control signals C0 to C8. (1) to (6) in Figs. 8A and 8B are operation timings of the respective blocks in Fig. 3 to represent the number of bits by which the operations of the respective blocks are delayed from the operation of selector 8. Control signals C0 to C8 and the respective blocks have the following correspondences: selector 8 ↔ C2, C3 phase angle modifying circuit 10 ↔ C4, C5, C6 selector 17 ↔ C7 selector 23, 25 ↔ C0 gate 24 ↔ C1 gate 20 ↔ C8 Therefore, the timings of control signals C0 to C8 are as shown in (9) to (12) in Figs. 8A and 8B. A data reset operation by gate 27 corresponds to a timing at which FF 26 outputs a sum of all the data and signal a is supplied to the gate 27, as shown in (7) in Figs. 8A, 8B. Latch timing 0 of latch 28 for final output need only be equal to a timing for fetching final data from selector 25, i.e., data in module 3 of channel 7, as sown in (8) in Figs. 8A and 8B. Fig. 9 shows the arrangement of controller 5. Timing signal generator 28 generates reference clocks 1 and 2, timing signal a , latch timing signal L, and address clock ACK for address counter 30. Address counter 30 receives address clock ACK, and generates addresses A0 and A1 in synchronism with its leading edge. Control data memory 29 stores control data C0 to C8 in units of modules, and its content is read out in synchronism with the address clock. Shift registers 31 to 37 delay the timing of the readout control data, and generate control signals C0 to C8 as shown in (9) to (12) in Figs. 8A, 8B. With these data, desired waveform calculations can be executed. Example 1 When EijsinqRij is added to final output Table 1 shows combinations of control data C0 to C8 used in this case. Module C0 C1 C2 C3 C4 C5 C6 C7 C8 i 0 1 1 1 0 0 0 * 0 First, since C2 = 1 and C3 = 1, selector 8 selects original phase angle data = qRij. Phase angle data qRij is input to phase angle modifying circuit 10 at a timing delayed by 5 bits. However, since 5-bit delayed data C4, C5, and C6 are "0", a phase angle is not modified, and X' = X = qRij is output, so that sine wave memory 12 outputs data sinqRij. In gate 20, since 6-bit delayed data C8 is "0", adder 21 outputs data Eij, and multiplier 14 outputs data EijsinqRij. In selector 23 and gate 24, since 8-bit delayed data C0 and C1 are respectively C0 = "0" and C1 = "1", the output from FF 26 is input to a B input of adder 16 through gate 27, and the output from adder 16 is fetched by FF 26 through selector 25. As a result, the output from FF 26 is changed to data obtained by adding a current value to EijsinqRij. If i = j = "0", since the output from gate 27 is "0", FF 26 fetches EijsinqRij. Example 2 When sine wave data in module i is used as phase angle data in next module i+1 Table 2 shows combinations of control data used when Y1 = Ei+1,j·sin(EijsinqRij) is obtained. Module C0 C1 C2 C3 C4 C5 C6 C7 C8 i 1 * 1 1 0 0 0 * 0 i+1 0 1 0 1 0 0 0 * 0 In the case of module i , since C2 = "1" and C3 = "1", selector 8 selects original phase angle data qRij. Phase angle data qRij is input to phase angle modifying circuit 10 at a timing delayed by 5 bits. However, since 5-bit delayed data C4, C5, and C6 are "0", X' = X = qRij is output, and sine wave memory 12 outputs data sinqRij. Since 6-bit delayed data C8 is "0" in gate 20, adder 21 outputs data Eij, and multiplier 14 outputs data EijsinqRij. Since 8-bit delayed data C0 is "1" in selector 25, FF 26 helds the preceding data. In the case of module i+1, since C2 = 0 and C3 = 1, selector 8 selects output EijsinqRij from FF 15, i.e., sine wave data in module i . Although EijsinqRij is input to phase angle modifying circuit 10 at a timing delayed by 5 bits, since 5-bit delayed data C4, C5, and C6 are "0", X' = X = EijsinqRij is output, and the output from sine wave memory 12 becomes sin(EijsinqRij). In gate 20, since 6-bit delayed data C8 is "0", adder 21 outputs data Ei+1j, and multiplier 14 outputs data Ei+1jsin(EijsinqRij). In selector 23 and gate 24, since 8-bit delayed data C0 and C1 are respectively C0 = "0" and C1 = "1", the output from FF 26 is input to the B input of adder 16 through gate 27, and the output from adder 16 is fetched by FF 26 through selector 25. As a result, the content of FF 26 corresponds to a value obtained by adding a current value to Ei+1jsin(EijsinqRij). At this time, if the waveform produced in module i+1 is given as Y1, Y1 = Ei+1jsin(EijsinqRij) For the sake of simplicity, if Eij → Ei, Ei+1j → Ei+1, and qRij → ωit, the above equation is developed as follows: where Jn(Z) is the Bessel function. Therefore, a large number of tone strings can be produced in accordance with envelope Ei. Example 3 When sine waves obtained in modules i and i+1 are added to obtain phase angle data of sine wave in module i+2 Table 3 shows combinations of control data used when waveform Y2 = Ei+2jsin(EijsinqRij + Ei+1jsinqRi+ij) is obtained. Module C0 C1 C2 C3 C4 C5 C6 C7 C8 i 1 0 1 1 0 0 0 0 0 i+1 1 1 1 1 0 0 0 * 0 i+2 0 1 1 0 0 0 0 * 0 In the case of module i , since C2 = "1" and C3 = "1", selector 8 selects original phase angle data qRij. Original phase angle data qRij is input to phase angle modifying circuit 10 at a timing delayed by 5 bits. However, since 5-bit delayed data C4, C5, and C6 are "0", X' = X = qRij is output, and sine wave memory 12 outputs data sinqRij. In gate 20, since 6-bit delayed data C8 is "0", adder 21 outputs data Eij, and multiplier 14 outputs data EijsinqRij. In gate 24, since 8-bit delayed data C1 is "0", "0" is input to the B input of adder 16, and thus, adder 16 outputs data EijsinqRij. Since 8-bit delayed data C7 is "0", selector 17 causes output EijsinqRij from adder 16 to be fetched by 6-stage shift register 18. In selector 25, since 8-bit delayed data C0 is "1", the content of FF 26 is held. In the case of module i+1, since C2 = "1" and C3 = "1", selector 8 selects original phase angle data qRi+1j. Phase angle data qRi+1j is input to phase angle modifying circuit 10 at a timing delayed by 5 bits. However, since 5-bit delayed data C4, C5, and C6 are "0", X' = X = qRi+1j is output, and sine wave memory 12 outputs data sinqRi+1j. In gate 20, since 6-bit delayed data C8 is "0", adder 21 outputs data Ei+1j, and multiplier 14 outputs data Ei+1jsinqRi+1j. In selector 23 and gate 24, since 8-bit delayed data C0 and C1 are respectively C0 = "1" and C1 = "1", output EijsinqRij from 2-stage shift register 19, i.e., sine wave data obtained in the preceding module is supplied to the B input of adder 16. Therefore, adder 16 outputs data EijsinqRij + Ei+1jsinqRi+1j. In selector 25, since 8-bit delayed data C0 is "1", the content of FF 26 is held. In the case of module i+2, since C2 = 1 and C3 = 0, selector 8 selects output EijsinqRij + Ei+1jsinqRi+1j from adder 16 as phase angle data. Phase angle data EijsinqRij + Ei+1jsinqRi+1j is input to phase angle modifying circuit 10 at a timing delayed by 5 bits. However, since 5-bit delayed data C4, C5, and C6 are "0", X' = X = EijsinqRij + Ei+1jsinqRi+1j is output, and sine wave memory 12 outputs data sin(EijsinqRij + Ei+1jsinqRi+1j). In gate 20, since 6-bit delayed data C8 is "0", adder 21 outputs data Ei+2j, and multiplier 14 outputs data Ei+2jsin(EijsinqRij + Ei+1jsinqRi+1j). In selector 23 and gate 24, since 8-bit delayed data C0 and C1 are respectively C0 = "0" and C1 = "1", the output from FF 26 is input to the B input of adder 16 through gate 27, and the output from adder 16 is fetched by FF 26 through selector 25. As a result, the content of FF 26 becomes a value obtained by adding a current value to Ei+2jsin(EijsinqRij + Ei+1jsinqRi+1j). At this time, if the waveform produced in module i+2 is given as Y2, Y2 = Ei+2jsin(EijsinqRij + Ei+1jsinqRi+1j) For the sake of simplicity, if Eij → Ei, Ei+1j → Ei+1, Ei+2j → Ei+2, qRij → ωit, and qRi+1j → ωi+1t, the above equation is developed as follows: A large number of harmonic overtone strings can be generated in accordance with ωi, ωi+1, Ei, and Ei+1. Example 4 When sine wave in module i and sine wave in module i+1 are multiplied Table 4 shows combinations of control data used when waveform Y3 = (Ei+1j + EijsinqRij)sinqRi+1j is obtained. Module C0 C1 C2 C3 C4 C5 C6 C7 C8 i 1 0 1 1 0 0 0 0 0 i+1 0 1 1 1 0 0 0 * 1 In the case of module i , since C2 = "1" and C3 = "1", selector 8 selects original phase angle data qRij. Phase angle data qRij is input to phase angle modifying circuit 10 at a timing delayed by 5 bits. However, since 5-bit delayed data C4, C5, and C6 are "0", X' = X = qRij is output, and sine wave memory 12 outputs data sinqRij. In gate 20, since 6-bit delayed data C8 is "0", adder 21 outputs data Eij, and multiplier 14 outputs data EijsinqRij. In gate 24, since 8-bit delayed data C1 is "0", "0" is input to the B input of adder 16, and adder 16 outputs data EijsinqRij. Since 8-bit delayed data C7 is "0", selector 17 causes output EijsinqRij to be fetched by 6-stage shift register 18. In selector 25, since 8-bit delayed data C0 is "1", the content of FF 26 is held. In the case of module i+1, since C2 = "1" and C3 = "1", selector 8 selects original phase angle data qRi+1j. Phase angle data qRi+1j is input to phase angle modifying circuit 10 at a timing delayed by 5 bits. However, since 5-bit delayed data C4, C5, and C6 are "0", X' = X = qRi+1j is output, and sine wave memory 12 outputs data sinqRi+1j. In gate 20, since 6-bit delayed data C8 is "1", adder 21 outputs data Ei+1j + EijsinqRij. Therefore, multiplier 14 outputs data (Ei+1j + EijsinqRij)sinqRi+1j. In selector 23 and gate 24, since 8-bit delayed data C0 and C1 are respectively C0 = "1" and C1 = "1", the output from FF 26 is input to the B input of adder 16 through gate 27, and is added to (Ei+1j + EijsinqRij)sinqRi+1j. Thereafter, the sum data is fetched by FF 26 through selector 25. At this time, if the waveform produced in module i+1 is given as Y3, Y3 = (Ei+1j + EijsinqRij)sinqRi+1j For the sake of simplicity, if Eij → Ei, Ei+1j → Ei+1, qRij → ωit, and qRi+1j → ωi+1t, Therefore, this represents a form of amplitude modulation, and a side wave is produced. As described above, four ways of waveform generation have been described. In addition to these, various waveforms can be produced by the same control as above, and they can still be combined to obtain a large number of waveform variations. In the above description, control inputs C4, C5, and C6 to the phase angle modifying circuit are "0". However, if they are set for each module, a calculation based on a waveform other than the sine wave can be made. In this case, if sine wave sinwit in module i in equation (1) is replaced with If sine wave sin(Eisinnωit) in module 1+1 in equation (1) is replaced with Therefore, the resultant waveform includes a large number of harmonic overtone components. In the above embodiment, waveform variations can be produced by simple processing, such as processing for selecting phase angle data to be input to the sine wave memory, processing for appropriately modifying the selected phase, and the like. If amplitude modulation is selectively added, further waveform variation can be obtained. The present invention is not limited to the above embodiment, and various changes and modifications may be made. For example, in the above embodiment, multiplier 14 performs not only a multiplication of produced waveforms (amplitude modulation) but also a multiplication of the produced waveform with envelope data, i.e., application of the envelope, thus decreasing the number of circuit components. However, if necessary, the application of the envelope can be executed by analog circuit means. Alternatively, a special-purpose multiplier can be used for the envelope application. Similarly, in the above embodiment, adder 16 is used not only for adding a waveform currently produced through sine wave memory 12 and an accumulated waveform from FF 26 but also for adding a currently produced waveform to a previously produced waveform from 2-stage shift register 19. Another adder can be used if necessary. The above arrangement has a polyphonic arrangement. The present invention can also be applied to a monophonic arrangement. Although the apparatus of the present invention described above has a simple arrangement in that a waveform generator operated in a time-divisional manner selects data used for next waveform generation from preceding waveforms in the same sampling period, various waveforms can be produced. The waveform generator for an electronic musical instrument using phase angle modifying circuit 10 shown in Fig. 5 can also be arranged as shown in Fig. 10. More specifically, keyboard 201 comprises switches for detecting ON/OFF operations of keys which are arranged in a matrix. Keyboard 201 is monitored by the scanning operation of key assigner 202. If a new key-on operation is detected, key assigner 202 generates key code KC and attack start signal A corresponding to the depressed key. In response to attack start signal A, envelope generator 203 begins to generate predetermined envelope waveform E. On the other hand, phase angle generator 204 generates a frequency data corresponding to key code KC supplied from assigner 202, and accumulates it to generate phase angle data X which changes at a constant rate. Phase angle modifying circuit 10 has the same arrangement as in Fig. 5, and modifies the value of phase angle data based on control data k from data setting circuit 206, thereby producing modified phase angle data X'. Modified phase angle data X' serves as a final address signal for sine wave memory 207 so as to cause it to produce corresponding sine waveform sinX'. Sine waveform is multiplied with envelope E by multiplier 208 to obtain musical tone waveform EsinX'. Sound system 209 D/A converts musical tone waveform EsinX' as digital data, and amplifies it to generate a sound. Thereafter, when the depressed key is released, key assigner 202 generates decay start signal D to set the envelope in a released state. Upon completion of the released state, envelope generator 203 generates envelope end signal EF, and key assigner 202 is set in a tone generation end state. According to the embodiment shown in Fig. 10, tone colors unique to rubbed string instruments can be easily generated. When value k of control data is changed over time, a musical tone whose tone color delicately changes can be produced. If a plurality of musical tone generators of this embodiment are provided and are driven while their frequencies and the degrees of phase modifying are set to be slightly different from each other (a time-divisional technique is also available), deep rich sounds can be produced. The present invention is not limited to the embodiment shown in Fig. 10, and various other changes and modifications may be made. For example, in the above embodiment, the sine wave for one period stored in a waveform memory is accessed. However, the above-mentioned waveform can be produced from the sine wave for a half or quarter of the period by a simple modification. In the circuit shown in Fig. 5, two different coefficients are used. However, more coefficients can be switched to produce modified phase angle data. In the above embodiment, the switching operation of the coefficients is performed at a position at which the modified phase angle data indicates the maximum or minimum value of the waveform. However, the coefficients can be switched at other positions. According to the present invention, control data is used as bit-shift signals in different directions to select a bit-shift direction adopted as an output or to change an inclination characteristic of modified phase angle data, resulting in a simple arrangement. In addition, a waveform whose spectrum gradually changes can be produced.

Claims: A waveform generator for an electronic musical instrument, comprising: waveform generating means (9 to 16) for generating a plurality of digital musical tone, waveform signals on a time divisional basis for a a unit sampling period, said unit sampling period being divided into a plurality of module periods; and supplying means (17 to 19, 23 to 27) coupled to said waveform generating means (9 to 16) for supplying said waveform generating means (9 to 16) with one or more of the digital musical tone waveform signals already generated in preceding module periods in the same sampling period as data for a digital musical tone waveform signal to be generated in a next module period; in which said waveform generating means (9 to 16) further includes: various waveform signal generating means (10, 12) for generating the digital musical tone waveform signals having various wave shapes, the wave shapes of which are selected by an input signal (C4, C5, C6); and that said waveform generating means (9 to 16) further includes: address signal generating means (4) for generating a normal address signal as an address signal of said various waveform signal generating means (10, 12) which changes at a substantially uniform rate corresponding to a selected frequency: and further means (8) for supplying one or more of the digital musical tone waveform signals delivered from said supplying means (17 to 19, 23 to 27) as an address signal of said various waveform signal generating means (10, 12). The waveform generator according to claim 1, characterized in that said various waveform signal generating means (10, 12) includes waveform memory means (12) for storing a sine waveform signal. The waveform generator according to claim 1, characterized in that said waveform generating means (9 to 16) further includes multiplying means (14) for multiplying the digital musical tone waveform signals generated in the preceding module periods of the same sampling period or the sum of the digital musical tone waveform signals with a digital musical tone waveform signal generated in a current module period. The waveform generator according to claim 1, characterized in that said waveform generator means (9 to 16) further includes multiplying means for multiplying envelope data with the digital musical tone waveform signal. The waveform generator according to claim 1, characterized in that said further supplying means (8) includes data inputs, and wherein said waveform generating means (9 to 16) further includes: temporary storage means (17 to 19) for storing a digital music tone waveform signal of one module period obtained through said various waveform signal generating means (10, 12) for delaying said waveform signal by a time corresponding to a selected number in units of module periods; and linking means for linking the output from said temporary storage means (17 to 19) to one of said data inputs of said further supplying means (8). The waveform generator according to claim 1, characterized in that said various waveform signal generating means (10, 12) includes waveform memory means (12) for storing a sine waveform signal; said further supplying means (8) includes data inputs; and said waveform generating means (9 to 16) further includes: adding means (16) for adding a waveform signal output from said waveform memory means (12) and a waveform signal previously output therefrom; and linking means for linking the output from said adding means (16) to one of said data inputs of said means (8). The waveform generator according to claim 1, characterized in that said various waveform signal generating means (10, 12) includes waveform memory means (12) for storing a predetermined waveform, and controllable modifying means (10) coupled to said waveform memory means (12) for changing an input signal to form a modified signal, the amplitude changing rate of the modified signal being different from that of the input signal, and that said means (8) supplies the digital musical tone waveform signal or the sum of the waveform signals as said input signal to said controllable modifying means (10), and said modified signal produced by said controllable modifying means (10) is supplied to said waveform memory means (12) as an address signal. The waveform generator according to claim 7, characterized in that said waveform memory means (12) stores a sine waveform signal which is addressed by modified signal obtained from said controllable modifying means (10). A waveform generator for an electronic musical instrument, comprising: phase angle generating means (4, 204) for generating phase angle data which changes at a preselected frequency; data setting means (5, 206) for generating control data (k) designating a level of modifying said phase angle data generated by said phase angle generating means (4, 204); phase angle modifying means (10) for modifying said phase angle data, the level of the modifying being determined by said control data (k), and for outputting modified phase angle data, said phase angle modifying means (10) including; shift means (112', 115) for bit-shifting said phase angle data in different directions, the level of bit-shifting being determined by said contorl data (k); and bit-shifting direction selecting means (117) for switching the direction of bit-shifting to define an inclination of the modified phase angle data as the output from said phase modifying means (10) at a timing during one cycle of the waveform; and waveform memory means (12', 207) whose address is designated by the output from said phase angle modifying means (10); wherein said waveform memory means (12, 207) stores at least one of a sine wave and a cosine wave, and the control data (k) controls said phase angle modifying means (10) such that an inclination of the modified phase angle data with respect ot the phase angle data is switched at least twice during one cycle of the waveform, thereby determining a time elapsing from an origin (0) to a peak value (N/4, 3N/4), when at least one of the sine wave and the cosine wave is read out from said waveform memory means. A generator according to claim 9, characterized in that said phase angle modifying means (10) includes first and second inverting means (111, 114) for switching, in accordance with an inverted most significant bit ( X MSB ) and the most significant bit ( X MSB ) itself, inversion or non-inversion of remaining bits excluding said most significant bit; said shift means (112, 115) includes first and second bit shifting means (112, 115) for receiving outputs from said first and second inverting means (111, 114) and said control data (k), for bit-shifting said outputs in opposite directions by an amount in accordance with a value of said control data (k); said phase angle modifying means (10) further includes first adding means (113) for adding the output from said first inverting means (111) and the output from said first bit-shifting means (112), second adding means (116) for adding the output from said second inverting means (114) and the output from said second bit-shifting means (115), selecting means (117) for selectively switching an output from said first adding means (113) and an output from said second adding means (116) during one cycle of the waveform; and further comprising means (118) for obtaining said modified phase angle data in accordance with an output from said selecting means (117). A method of generating a waveform for an electronic musical instrument, comprising: generating, in a waveform generating means (9 to 16), a plurality of digital musical tone waveform signals on a time divisional basis basis for a unit sampling period, said unit sampling period being divided into a plurality of module periods; generating a normal address signal (qRij) which changes at a substantially uniform rate corresponding to a selected frequency; characterized by further comprising: supplying said waveform generating means (9 to 16) with the digital musical tone waveform signal or a sum of the digital musical tone waveform signals already generated in preceding module periods in the same sampling period as address data for a digital musical tone waveform signal to be generated in a next module period; and generating various digital musical tone waveform signals responsive to a selection input signal which designates various waveshapes of said digital musical tone waveform signals, and said digital musical tone waveform signals having various waveshapes being generated based on said signal selectively supplied to said waveform generating means (9 to 16). A method of generating a waveform for an electronic musical instrument, comprising the steps of: generating phase angle data which changes at a preselected frequency; generating control data (k) designating a level of modifying said phase angle data; modifying said phase angle data, the level of the modifying being determined by said control data (k) to output modified phase angle data; and designating an address of waveform memory means (12, 207) by said modified phase angle data; wherein said phase angle data modifying step includes; bit-shifting said phase angle data in defferent directions, the level of bit-shifting being determined by said control data (k); and switching the direction of bit-shifting to define an inclination of the modified phase angle data as the output from phase angle modifying means (10) at a timing during one cycle of the waveform; characterized by storing at least one of a sine wave and a cosine wave in said waveform memory means (12, 207); and by controlling by said control data (k) said phase angle modifying means (10) such that an inclination of the modified phase angle data with respect to the phase data is switched at least twice during one cycle of the waveform, thereby determining a time elapsing from an origin (0) to a peak value (N/4, 3N/4), when at least one of the sine wave and the cosine wave is read out from said waveform memory means (12, 207).

Inventors: KANEKO, YOJI PATENT DEPT. D. D. HAMURA R&D CENTER, Kaneko, Yoji Patent Dept. D. D. Hamura R&amp;D Center
Applicants: CASIO COMPUTER COMPANY LIMITED
Application year: 1987
Main classification: G10H7
IPC codes: G10H7