LEVEL SHIFT CIRCUIT FOR DIFFERENTIAL SIGNALS

Abstract: A level shift circuit for shifting the common mode level of the output signal provided by a differential amplifier has first and second input terminals for receiving the output signal from the differential amplifier, which has a Thevenin source impedance R s , and also has first and second output terminals that are connected to a reference voltage level through a load impedance R o . The circuit comprises a differential transconductance amplifier having two output terminals that are connected respectively to the first and second output terminals of the circuit. The amplifier has the property that it responds to an input voltage E e between its input terminals by providing a current equal to E e g m1 /(1+τs) (where g m1 is the transconductance of the amplifier, τ is the response time constant of the amplifier and s is the Laplace transform operator) at its output terminals. Two equal-valued capacitors are connected respectively between the first input terminal of the circuit and the first output terminal of the circuit and between the second input terminal of the circuit and the second output terminal of the circuit, the capacitance C c of each capacitor being such that R s C c is much greater than τ. The circuit also comprises two equal-valued resistors connected in series between the first input terminal of the circuit and the second output terminal of the circuit and having their connection point connected to one of the input terminals of the amplifier, and two more equal-valued resistors connected in series between the first output terminal of the circuit and the second input terminal of the circuit and having their connection point connected to the other of the two input terminals of the amplifier. The value of g m1 is selected to be equal to (1/2R s + 1/R).

Description: This invention relates to a level shift circuit for differential signals. Background of the Invention High speed differential amplifiers of conventional design, such as those which are used in the vertical channel of a cathode ray oscilloscope, are able to provide an output signal that is an accurate replica of the input signal for a wide range of frequencies, e.g., from DC up to more than 1 Ghz. It is conventional for the vertical amplifier of an oscilloscope to use several differential amplifier stages in cascade, in order to provide the desired amount of voltage gain. A characteristic of conventional differential amplifiers is that the common mode level of the output signal of the amplifier is several volts, e.g. 3 to 4 volts, higher than the common mode level of the input signal. Therefore, when three differential amplifier stages are connected in cascade, there is a common mode level shift of from 9 to 12 volts between the input of the first amplifier stage and the output of the last amplifier stage, unless level shifting circuits are interposed between the successive stages. This offset in the common mode level of the conventional differential amplifier can present a problem, since each stage requires different supply voltages. Furthermore, the different supply voltages may make it impractical to fabricate several stages on the same integrated circuit chip because of breakdown voltage limitations. Conventional level shifting circuits consume large amounts of power, requiring expensive packaging to remove the resulting heat. Also, if the oscilloscope is to operate in the internal trigger mode, in which the trigger for controlling horizontal deflection is generated by comparing the vertical deflection signal with a predetermined trigger level, it is necessary to compensate for the offset in common mode level if the vertical deflection signal is to be applied to the trigger comparator from any location other than upstream of the vertical amplifier. An example of a prior art level-shift circuit is disclosed in U.S. Patent No. US-A-3132307 (A.F. Augustine et al). Summary of the Invention A preferred embodiment of the present invention is a level shift circuit for shifting the common mode level of the output signal provided by a differential amplifier. The circuit has first and second input terminals for receiving the output signal from the differential amplifier, which has a Thevenin source impedance R s . The circuit also has first and second output terminals that are connected to a reference voltage level through a load impedance R o . The circuit comprises a differential transconductance amplifier having two input terminals and two output terminals, the two output terminals being connected respectively to the first and second output terminals of the circuit. The amplifier has the property that it responds to an input voltage E e between its input terminals by providing a current equal to E e g ml /(1+τs) (where g ml is the transconductance of the amplifier, τ is the response time constant of the amplifier and s is the Laplace transform operator) at its output terminals. Two equal-valued capacitors are connected respectively between the first input terminal of the circuit and the first output terminal of the circuit and between the second input terminal of the circuit and the second output terminal of the circuit, the capacitance C c of each capacitor being such the R s C c is much greater than τ. The circuit also comprises four equal-valued resistors, the resistance value R of each of which is much greater than R s and R o . Two of the resistors are connected in series between the first input terminal of the circuit and the second output terminal of the circuit and have their connection point connected to one of the input terminals of the amplifier. The other two resistors are connected in series between the first output terminal of the circuit and the second input terminal of the circuit and have their connection point connected to the other of the two input terminals of the amplifier. The value of g m1 is selected to be equal to (1/2R s + 1/R). Brief Description of the Drawing For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawing in which: FIG. 1 is a block diagram of a circuit that includes as one stage a level shift circuit embodying the present invention, FIG. 2 shows waveforms that are useful in explaining operation of the FIG. 1 circuit, and FIG. 3 is a schematic diagram illustrating an implementation of the FIG. 1 level shift circuit connected between two differential amplifiers. Detailed Description The circuit illustrated in FIG. 1 comprises a differential amplifier 2 that is illustrated schematically as two Thevenin voltage sources 4 and 4′ that are connected in series with respective source impedances R s and R s ′ between a source common mode voltage level V cs and circuit nodes 6 and 6′. A differential voltage signal is developed between the node 6 and 6′. The nodes 6 and 6′ are connected to a level shift circuit 8. The level shift circuit transmits differential signals faithfully while providing a high common mode DC resistance across capacitors C c and C c ′ in order to allow a large common mode voltage drop with low common mode current and power dissipation. A common mode correction amplifier 10 is used to drive the common mode level of the differential signal provided by the level shift circuit to a desired output common mode level V co . The output terminals of the amplifier 10 are connected to a load 12 that is represented schematically as output impedances R o and R o ′ connected between the output terminals of the amplifier 10 and a reference potential level, e.g. V co . If a rectangular voltage transition is generated by Thevenin sources 4 and 4′, the voltage between the nodes 6 and 6′ initially rises in step fashion and then rises in accordance with an inverse exponential function as the capacitors C c and C c ′ are charged through the source impedances R s and R s ′. The source impedances R s and R s ′ are approximately equal to the output impedances R o and R o ′, and therefore the value V f at which the voltage between the nodes 6 and 6′ stabilizes is twice the magnitude of the initial step change. See the waveform A shown in FIG. 2. In the brief interval immediately after the rising edge of the step change, the the highest frequency components of the step change are passed directly by the capacitors C c and C c′ to the load 12. Therefore, the current i c supplied through capacitor C c increases and the voltage at the node 14 rises sharply to a level determined by the voltage at the node 6, reduced by the loading effects of the resistors R₁, R₂, R₃, R₄ and R o on R s . Symmetry considerations dictate that the voltage at the node 14′ varies in equal and opposite fashion. See waveform B When the high frequency components of the step change have decayed, the current i c settles to zero. The value V f at which the voltage between the nodes 6 and 6′ stabilizes is different fro m the voltage between the nodes 14 and 14′. Since the resistors R₁, R₂, R₁′ and R₂′ are equal valued, the voltage E e between the input terminals of the differential transconductance amplifier A₁ is equal to half the difference between the voltage between the nodes 6 and 6′ and the voltage between the nodes 14 and 14′ as shown by the steady-state level of the waveform C. The transconductance of the amplifier A₁ is set equal to (1/2R s + 1/R₁), and therefore, the current i provided by the amplifier A₁ to the resistors R₂, R₃, R₄ and R o is given by i=E e (R₁+2R s )/2R s R₁(1+τs) where τ through the capacitor C c just after the leading edge of the transition. Compare waveforms D and E. It can be shown that for all intermediate times the output signal developed between the nodes 14 and 14′ matches the voltage applied between the nodes 6 and 6′ modified by a constant, and consequently that the level shift circuit provides high-fidelity transmission of the differential signal. It will be appreciated that the net load current i L (waveform F) is equal to the sum of i and i c and varies in step fashion in response to the rectangular voltage transition generated by the sources 4 and 4′. In steady state, the entire load current i L is provided by the amplifier A₁. The output impedance that is presented to the load 12 is constant over frequency and is equal to R s in parallel with R₁, R₂, R₃ and R₄. The amplifier A₂ of the common mode correction stage is a high gain amplifier which senses the output common mode level through the resistors R₃ and R₃′ and drives it to match V co through the resistors R₄ and R₄′. If V co is set to signal ground, then the signal at the node 14 is a single-ended ground-referenced signal and may be applied, for example, to a trigger level comparator. FIG. 3 illustrates how the level shift circuit of FIG. 1 may be connected between two similar differential amplifier stages 16 and 18. Voltage levels and current values are marked in FIG. 3, as are component values. In the case of FIG. 3, the transconductance amplifier A₁ is implemented as two low cost operational amplifiers A₃ and A₄ driving respective current source transistors Q₁ and Q₂. The two amplifier stages 16 and 18 operate from the same supply voltages, simplifying system design and minimizing power designation. There is no theoretical limit on the frequency of the signal components that can be passed by the FIG. 1 level shift circuit, since the only components of the level shift circuit that are in series with the signal path are capacitors. Frequency limits are imposed only by the source impedance R s , R s ′ and the accumulated shunt capacitance to ground resulting from the circuit layout and the load. The only practical speed limit is imposed by the physical size of the capacitors C c and C c ′. The response time constant τ of the amplifier A₁ need not be particularly small: it is necessary only that τ be much smaller than the coupling time constant R s C c . Provided this requirement is satisfied, the output current i of the amplifier A₁ will follow the input voltage E e with only minuscule error. It is not essential that the values of C c and C c ′ be precisely equal, so long as they do not differ from one another by more than about 20%. It is, however, important that the values of R₁, R₁′, R₂ and R₂′ be well matched, since if they are not, the response flatness errors will appear with time constants equal to T, to R s C c . In order to minimize deviation from flat pulse response, it is desired to minimize capacitive coupling between the outputs of the amplifier A₁ and the inputs thereof. It will be appreciated that the present invention is not restricted to the particular embodiment that has been described and illustrated, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims. In particular, it is not essential to use the common mode correction amplifier in conjunction with the level shift circuit, the common mode correction amplifier being required only if the common mode impedance provided by the load is too high.

Claims: A level shifting circuit for receiving a differential input signal from a source having a Thevenin source impedance R s and for applying an output signal to a load having an impedance R o , the circuit having first and second input terminals for receiving the differential input signal and first and second output terminals for connection to the load and comprising a differential transconductance amplifier having two input terminals and two output terminals, the two output terminals being connected respectively to the first and second output terminals of the circuit, and the amplifier having the property that it responds to an input voltage E e between its input terminals by providing a current equal to E e g ml /(1+τs) (where g ml is the transconductance of the amplifier, τ is the response time constant of the amplifier, and s is the Laplace transform operator) at its output terminals, characterised in that the circuit also comprises first and second substantially equal-valued capacitors connected respectively between the first input terminal of the circuit and the first output terminal of the circuit and between the second input terminal of the circuit and the second output terminal of the circuit, the capacitance C c of each capacitor being such that R s C c is such greater than τ, and four equal-valued resistors connected respectively between the first output terminal of the circuit and one of the two input terminals of the amplifier, between the second output terminal of the circuit and the other of the two input terminals of the amplifier, between the first input terminal of the circuit and said other input terminal of the amplifier and between the second input terminal of the circuit and said one input terminal of the amplifier, the transconductance of the amplifier being equal to (1/2R s + 1/R), where R is the resistance value of the four equal-valued resistors and is much greater than R o . A circuit according to claim 1, further comprising a common mode correction amplifier connected between the first and second output terminals of the circuit, the common mode correction amplifier stage comprising a high gain amplifier having a non-inverting input terminal connected to a desired common mode reference potential level and also having an inverting terminal and an output terminal, a first pair of equal-valued resistors connected in series between the output terminals of the circuit and having a connection point that is connected to the inverting terminal of the differential amplifier, and a second pair of equal-valued resistors connected in series and having a connection point that is connected to the output terminal of the differential amplifier.

Inventors: DILLER, CALVIN DEAN, GLADDEN, DONALD D.
Applicants: TEKTRONIX INC.
Application year: 1987
Main classification: H03F3
IPC codes: H03F3, H03K5