FULL DUPLEX MODEM HAVING TWO ECHO CANCELLERS FOR A NEAR END ECHO AND A FAR END ECHO

Abstract: The modem comprises a first echo canceller (100) for cancelling a near end echo and a second echo canceller (200) for a far end echo. The second echo canceller (200) has a variable delay circuit (201) responsive to the round-trip delay of the far end echo for setting the cancellation start timing of the far end echo. A comparator compares the round-trip delay and the echo cancellation time of the first echo canceller (100). A control circuit is responsive to the output of the comparator to control the echo cancellation time of the first echo canceller. This modem comprises echo cancellers whose time of convergence in echo cancellation does not decrease even where the round-trip delay is short.

Description: The present invention relates to a modem having echo cancellers, and more particularly to a modem for two-wire full-duplex communications having two echo cancellers for a near end echo and a far end echo. In EP-A-113 487 a method and apparatus are described for measuring the delay of the distant echo in an echo cancelling arrangement. The echo cancelling arrangement is incorporated in a transceiver to cancel an echo signal occuring in the receive part of the transceiver in response to a signal transmitted in the transmit path thereof. Such echo signal consists of a substantially undelayed near echo signal and a delayed distant echo signal. This known echo cancelling arrangement comprises a near echo canceller receiving the signal from the transmit path without delay and the distant echo canceller receiving such transmit path signal with a delay substantially equal to the measured delay of the distant echo signal. This document further describes how the time delay is measured. A modem for two-wire full-duplex communications (hereinafter referred to as simply "modem") has to cancel a near end echo originating from a hybrid transformer of a local modem and a far end echo which results from the return to the local modem of an echo generated at a hybrid transformer of a remote modem by data sent from the local modem. Since a change in the opposite party of communication usually entails a variation in communication roots or pathes, the round-trip delay from the time a datum is transmitted till it comes back as a far end echo also varies correspondingly. A modem by the prior art copes with such variations in round-trip delay with a variable delay circuit for delaying the start timing of far end echo cancellation, arranged before a far echo canceller. This far end echo, when passing a converter on the transmission path, undergoes phase roll due to the frequency offsetting or phase jitter of the carrier. As the phase roll increases the uncancelled residue of the far end echo, the far echo canceller is provided with a phase corrector for automatic adaptive correction of the phase roll. In the foregoing modem of the prior art, if the round-trip delay is short, the time region of near end echo cancellation and that of far end echo cancellation for one transmitted datum will overlap each other. In such an overlapped time region, two echo cancellers, one for the near end echo and the other for the far end echo, act to cancel the echoes of the same transmitted datum at the same time. As a result, the convergence velocity in training is significantly reduced, or even divergence occurs instead of convergence, to obstruct the start of communications. This problem is especially serious where the far end echo canceller is provided with a phase corrector. An object of the present invention is to solve the foregoing problem and a modem having echo cancellers whose time of convergence in echo cancellation does not decrease even where the round-trip delay is short. According to the invention, there is provided a modem comprising a first echo canceller for cancelling a near end echo and a second echo canceller for a far end echo. The second echo canceller has a variable delay circuit responsive to the round-trip delay of the far end echo for setting the cancellation start timing of the far end echo. A comparator compares the round-trip delay and the echo cancellation time of the first echo canceller. A control circuit is responsive to the output of the comparator to control the echo cancellation time of the first echo canceller. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description when taken with the accompanying drawings in which: FIG. 1 is a block diagram illustrating a preferred embodiment of the invention, and FIG. 2 is a circuit diagram illustrating an adaptive filter for use in the invention. Reference to FIG. 1, a transmit datum is modulated, for example, in a quadrature amplitude modulation scheme, by a modulator 1, and the signal modulated thereby is fed to a transmission line 20 by way of a hybrid transformer 2. A modulated signal from a remote modem (not shown) is supplied as a receive modulated signal to a demodulator 5 which produces a demodulated signal. A near end echo canceller 100 cancels, out of the demodulated signal, a near end echo which occurs when the modulated signal is transmitted through the hybrid transformer 2, and produces a near end echo residual signal to a far end echo canceller 200. The far end echo canceller cancels a far end echo from the demodulated signal and generates a far end echo residual signal. In the far end echo canceller 200, a variable delay circuit 201 gives the round-trip delay of the far end echo to the transmit datum. An adaptive filter 202 is responsive to the delayed transmit datum and the far end echo residual signal to generate a far end echo replica. A subtractor circuit 203 generates the far end echo residual signal by subtracting the far end echo replica from the demodulated signal (a near end echo cancellation signal here). The delay time of the variable delay circuit 201 is set by a first control signal C1 from a sequencer 10, indicating the round-trip delay. A phase controller 204 obtains the phase difference between the far end echo replica and the far end echo residual signal to be used for correcting the phase roll of the far end echo. Multipliers 205 and 206 multiply the far end echo replica and the far end residual signal by the phase difference to match the phases of the echo replica and the residual signal. For further details on the phase roll, reference may be made to the U.S. Patent No. 4,621,173. Meanwhile, a near end echo canceller 100 consists of an adaptive filter 101 responsive to the transmit datum and the far end echo residual signal for generating a near end echo replica, and a subtractor circuit 102 for subtracting the near end echo replica from the demodulated signal. The filter 101 is so composed as to control, when the round-trip delay is shorter than a prescribed time, the number of filter taps with a second control signal C2 from the sequencer 10. This composition will be described in further detail elsewhere with reference to FIG. 2. The modem in FIG. 1 also includes an encoder (U.S.P. 4,077,021) 6 which converts transmission data into predetermined codes which are robust to transmission errors and a decoder 7 therefor. The above modem further includes the sequencer 10 for controlling start-up procedure as defined by CCITT Recommendation V.32, a tone generator 8 for generating tones necessary for such a procedure and a tone detector 12 for detecting tones transmitted through the line 20. These tone generator and detector are used for measuring the round-trip delay. The sequencer 10 comprises a microprocessor programmed to execute the procedure including a round-trip delay measurement according to Recommendation V.32. The sequencer 10, in response to the measured delay, generates the first control signal C1 for setting the delay to be given by the variable delay circuit 201 and the second control signal C2 for altering the tap length of the filter 101. FIG. 2 is a block diagram illustrating a typical structure of the adaptive filter 101, which has N delay circuits 13 each having a prescribed delay time γ, N+1 multipliers 14 for multiplying the outputs of the delay circuits by coefficients a₀ to a N and an adder 18 for adding the products of multiplication. A coefficient generator 15 generates the coefficients a₀ to a N based on the outputs of the delay circuits and the far end echo residual signal. Between the multipliers 14, to which coefficients a₀ to a m (m ≦αµρ¨ N, m < N in FIG. 2) are given, and the adder circuit 18 are provided switches 17 for selecting either the products of multiplication by the multipliers 14 or zero. Each of the switches 17 is controlled by a switch selection signal from a decoder 16. In this structure, if the sequencer 10 judges the round-trip delay t F to be greater than the maximum response time (N+1) ` γ of the adaptive filter 101, the sequencer 10 so sends out to the decoder 16 the control signal C2 as t every switch 17 to be connected to the multiplier 14. Meanwhile, if the sequencer 10 judges the round-trip delay t F not to be greater than the maximum response time (N+1) ` γ of the adaptive filter 101, it so sends out to the decoder 16 the control signal C2 as to connect the switches 17 of the multipliers 14 receiving coefficients a₀ to a n-M to the zero and those of the multipliers 14 receiving coefficients a N-M+1 to a m to the multiplier 14. Thus the adaptive filter 101 is responsive to the second control signal C2 for so altering the filter tap number as not to let its own echo cancellation overlap the far end echo cancellation (i.e. the echo cancellation of the echo canceller 200 in FIG. 1). Incidentally, it is obvious that the switches 17 may as well be positioned midway of the signal lines of coefficients a₀ to a m or midway of the tap output. Since it is made possible to prevent the overlapping of the echo cancellation of the echo cancellers 100 and 200 for near end and far end echoes, respectively, even if the round-trip delay is short, the present invention can realize a modem having echo cancellers whose convergence velocity of echo cancellation is not retarded. Though the far end canceller is arranged after the near end echo canceller in the preferred embodiment of the invention hitherto described, the latter may as well be positioned after the former.

Claims: A full-duplex modem comprising: a first echo canceller (100) for cancelling a near end echo and a second echo canceller (200) with a variable delay circuit (201) responsive to the round-trip delay of a far end echo for setting the cancellation start timing of said far end echo, characterized by comparator means (10) for comparing said round-trip delay delay and the echo cancellation time of said first echo canceller, (100) and control means (101) responsive to the output of said comparator means (10) for controlling the echo cancellation time of said first echo canceller (100). A full-duplex modem as claimed in Claim 1, wherein: said first echo canceller (100) comprises delay circuits (13) for producing N outputs, N multiplier circuits (14) for multiplying the N outputs by N filter coefficients, and an adder circuit (18) for adding the multiplication products of said multiplier circuits, and said control circuit (101) comprises of M switches (17) connected to M multiplier circuits (14) out of said N multiplier circuits (14), and decoder means (16) responsive to the output (C2) of said comparator means (10) for controlling these M switches (17).

Inventors: HIRAGUCHI, MASAYOSHI
Applicants: NEC CORPORATION
Application year: 1987
Main classification: H04B3
IPC codes: H04B3, H04L5