CHARGE TRANSFER DEVICE

Abstract: This charge transfer device comprises transfer electrodes (700) and read electrodes (600). The read electrode operates in accordance with two modes. Where it operates based on the charge detection mode, a charge below the read electrode is read out in accordance with the floating gate system, so that a charge detection signal is produced. On the other hand, where it operates based on the charge transfer mode, the read electrode performs a function equivalent to the transfer electrode. This device further comprises selector means (400), thus permitting the read electrode to select either of two modes to operate in a selected mode. Since mode selection can be thus made according to need, crosstalk based on the charge detection signal can be suppressed.

Description: BACKGROUND OF THE INVENTION The present invention relates to a charge transfer device, and more particularly to a charge transfer device as indicated in the preamble of claim 1 and as known from US-A-3,947,705. For the charge detection at the output stage of a charge transfer device (which will be called "CTD" hereinafter), read electrodes of the floating diffusion system type or the floating gate system type are ordinarily employed. The floating diffusion system advantageously provides a large voltage gain at the output stage of the CTD, but has the drawback that signal charges are broken at the time of detection, thus making it impossible to successively transfer the charge which has been detected once. Contrary to this, while the drawback with the floating gate system is that step-up capacitor is generally required because transfer without loss to the subsequent stage is conducted, thus making it difficult to ensure the voltage gain as compared to the floating diffusion system, the advantage therewith is that because non-destructive charge detection is possible signals can be detected from several portions in the middle of the transfer unit. However, CTDs using read electrodes of the floating gate system type give rise to the problem that signals detected through floating gates are caused to interfere with other signals, resulting in occurrence of crosstalk. This comes into question particularly in the case where such read electrodes are provided at a plurality of portions of the transfer path to conduct charge detection therefrom. This is because crosstalk occurs between detection signals from the plurality of portions. In addition, CTDs using the floating gate system and the floating diffusion system in combination also give rise to the problem that crosstalk occurs between detection signals based on the respective systems. SUMMARY OF THE INVENTION With the above in view, an object of the present invention is to provide a CTD which can eliminate crosstalk between deflection signals from different read electrodes. The features of the present invention are indicated in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(a) is a simplified circuit diagram showing a typical floating gate charge detection unit, Fig. 1(b) is a cross sectional view of elements constituting the detection unit shown in Fig. 1(a), and Figs. 1(c) and 1(d) show the potential distribution diagrams, respectively; Fig. 2 shows clock waveforms used in the device shown in Fig. 1; Fig. 3(a) is a circuit diagram showing a CTD of a typical floating gate charge detection system which effects charge detection from two portions, Fig. 3(b) is a cross sectional view of elements constituting the CTD shown in Fig. 3(a), and Figs. 3(c) and 3(d) show the potential distribution diagrams, respectively; Fig. 4 is a block diagram for explaining the principle of the present invention; Fig. 5 is a schematic view illustrating an embodiment of the present invention in which the block shown in Fig. 4 is constituted with actual elements; Fig. 6(a) is a circuit diagram showing a CTD according to another embodiment of the present invention, Fig. 6(b) is a cross sectional view of elements constituting the CTD shown in Fig. 6(a), and Figs. 6(c) and 6(d) show the potential distribution diagrams, respectively; Fig. 7(a) is a circuit diagram showing a CTD according to a further embodiment of the present invention which effects charge detection from two portions, Fig. 7(b) is a cross sectional view of elements constituting the CTD shown in Fig. 7(a), and Figs. 7(c) and 7(d) show the potential distribution diagrams, respectively; Fig. 8 is a diagrammatical view showing a logic circuit which generates clocks delivered to the circuit shown in Fig. 7(a); Fig. 9 is a timing chart for explaining the operation of the circuit shown in Fig. 7(a); Fig. 10 is a circuit diagram in which the circuit shown in Fig. 7(a) is constituted with an actual transistor circuit; Fig. 11 is a circuit diagram showing a partially modified embodiment of the circuit shown in Fig. 6(a); Fig. 12 shows an operational function Table when the circuit shown in Fig. 11 is used; Fig. 13(a) is a circuit diagram showing an embodiment in which the present invention is applied to a single-phase CTD, Fig. 13(b) is a cross sectional view of elements constituting the CTD shown in Fig. 13(a), and Figs. 13(c) and 13(d) show the potential distribution diagrams, respectively; and Fig. 14 shows an operational function Table when the circuit shown in Fig. 13(a) is used. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The operational principle of the floating gate charge detection system of a typical CTD will be first described with reference to Figs. 1 and 2. Fig. 1(a) is a simplified circuit diagram showing a floating gate charge detection unit, Fig. 1(b) is a cross sectional view of elements constituting the detection unit, Figs. 1(c) and 1(d) show the potential distribution diagrams, respectively, and Fig. 2 shows waveforms of various clocks used in this device. In Fig. 1, charges are transferred below electrodes 6 and 7. Initially, when a transfer clock  represents high level, a switch 4 is turned on, so that a voltage of V L is applied from a reference voltage source 3 to a step-up capacitor 1. Thus, the floating gate electorde 6 is reset to V L . At this time, the potential distribution below the electrodes 6 and 7 is as shown in Fig. 1(c). Then, when the transfer clock  becomes low level, the switch 4 is turned off, whereby a junction 5 is in the floating state. Simultaneously with this, a voltage appearing on the junction 5 is increased to V H by the step-up capacitor 1. Accordingly, a voltage across the electrode 6 is increassed to V H . Thus, the potential distribution therebelow is changed as shown in Fig. 1(d), so that a charge 9 is transferred as indicated by an arrow. Namely, a potential P₅ appearing on the junction 5 varies in synchronism with clocks  and  as indicated by Fig. 2. In this instance, a voltage ΔV out is a potential change proportional to the charge 9 transferred. This voltage ΔV out is detected at an output circuit 8. The upper limit V H of the potential P₅ is expressed as follows: where V DD represents a power supply voltage for clocks  and  , C₂ a capacitance of the parasitic capacitor 2 of the circuit wiring etc., C₁ a capacitance of the step-up capacitor 1, and V L a reference voltage delivered from the reference voltage source 3. The voltage gain G of the floating gate charge detection circuit is expressed as follows: where C IN represents an input capacitance of the CTD. As stated above, since the step-up capacitance C₁ is added in addition to the parastic capacitance C₂ in the detection circuit of the floating gate system, the voltage gain becomes small. While the voltage gain becomes small in the floating gate charge detection system, it can provide the above-described advantage that a desired number of non-destructive charge detections are realized from the middle portions of the transfer unit. Fig. 3(a) is a circuit diagram showing a CTD provided with two charge detection units 2 each shown in Fig. 1(a), Fig. 3(b) is a cross sectional view of elements constituting the CTD, and Figs. 3(c) and 3(d) show the potential distribution diagrams, respectively. In Fig. 3, charges are transferred below the electrodes 10, 13 and 14. On floating gate electrodes 13 and 14, signals having a time difference therebetween are induced as voltage changes proportional to charges transferred. The induced voltages are detected by output circuit 17 and 18. Either of signals on the floating gate electrodes 13 and 14 is selected by switches 19 and 20. The signal thus selected is output as an output signal V₀. However, the CTD thus configured gives rise to the problem that crosstalk would occur as stated above. For instance, in the circuit shown in Fig. 3, signals having been detected by both the floating gate electrodes 13 and 14 will be transmitted by the time they have just reached the switches 19 and 20. Namely, since these two signals are transmitted on the same substrate, they interfere with each other, giving rise to a phenomenon called crosstalk such that one signal component is superimposed on the other signal as a noise. This is because both the signal transmission systems are capacitively coupled by drain-source capacitance of an element such as MOS FET, etc. constituting the circuit, capacitance through the substrate and the like. As just described above, with the device shown in Fig. 3, there occurs crosstalk phenomenon such that a non-selected signal is superimposed on a selected signal as a noise, and it is difficult to suppress noise components due to the non-selected signal to be below a predetermined value (for example, less than -60 dB). Accordingly, in the case of processing video signals, etc., there occurs the problem that crosstalk components will appear on the screen. The principle of the invention will be now described. Fig. 4 is a block diagram showing the principle of the invention. In Fig. 4, a read electrode 600 is formed between transfer electrodes 700. An arrangement in this figure includes a detector means 200 capable of detecting, in a non-destructive manner, a potential change due to charges stored below the read electrode 600 when the read electrode 600 is in floating condition, and a transfer means 300 capable of applying a voltage or a pulse such that a potential can be formed below the electrode with the read electrode 600 being as one transfer electrode alone. These means 200 and 300 are connected to the read electrode 600. Either the detector means 200 or the transfer means 300 is selected by selector means 400 according to need. Namely, the read electrode 600 is set to either the transfer mode or the charge detection mode by the selector means 400. Thus, only when the electrode 600 is in the charge detection mode, a detection signal is delivered to an output processing circuit 500. Fig. 5 is a circuit diagram showing an embodiment in which the block in Fig. 4 is constituted with actual components. The detector means 200 is composed of a reference power source 201, a switch 202 and step-up capacitor 203. The transfer means 300 is comprised of a supply source for transfer clock  . It is seen that when the selector means 400 selects the detector means 200, the device effects the same operation as that of the device shown in Fig. 1, whereby a detection signal is delivered to the output circuit 500. It is also seen that when the selector means 400 selects the transfer means 300, the electrode 600 serves as solely one transfer electrode. Fig. 6(a) is a circuit diagram showing a detection unit of a CTD according to another embodiment of the present invention, Fig. 6(b) is a cross sectional view of elements constituting the detection unit, and Figs. 6(c) and 6(d) show the potential distribution diagrams, respectively. In this example, the circuit 100 serves as the detector means 200, the transfer means 300 and the selector means 400 which are shown in Fig. 4. When the device in Fig. 6 is compared with that in Fig. 1, the feature of this device will be clearly understood. Namely, this device is characterized in that a switch 31 is provided in parallel with the step-up capacitor 1 in the floating gate charge detection circuit shown in Fig. 1, and in that a switch 32 is provided at a path for charging the step-up capacitor in the above detection circuit. In the embodiment shown in Fig. 6, the switch 32 is provided between the switch 4 and the reference voltage source 3. In addition, reciprocal configuration of the switches 4 and 32 may be implemented. The switch 31 is always subjected to an on-off control opposite to that for the switch 32. The operation of this device will be now described. First, reference is made to the case where the charge detection mode is selected. In this mode, the switch 31 is in off state, whereas the switch 32 is in on state. The circuit in this condition is the same as the device in Fig. 1. A potential change proportional to the charge 9 transferred to the portion below the floating gate electrode 6 is induced. This potential change is delivered to the output processing circuit 8 and is detected thereat. Reference is now made to the case where the transfer mode is selected. In this mode, the switch 31 is in on state, whereas the switch 32 is in off state. Since the switch 31 is in on state, the transfer clock  is delivered to the floating gate electrode 6. Thus, this electrode 6 functions as one charge transfer electrode alone. By reciprocally controlling the switches 31 and 32 in a manner stated above, the charge detection mode and the charge transfer mode can be switched. It is now assumed that, e.g., the detection unit shown in Fig. 6 is applied to the CTD capable of effecting both the operations of the floating gate system and the floating diffusion system. For causing this CTD to be operative on the basis of the floating gate system, it is sufficient that the switches 31 and 32 are caused to be in off and on states, respectively, thus allowing the detection unit to be operative on the basis of the charge detection mode. By providing a charge detection unit (not shown) of the floating diffusion system at the final transfer stage (the right in Fig. 6(b)), a charge detection signal is output therefrom. At this time, since no signal is output from the output circuit 8, there is no possibility that any crosstalk occurs. Fig. 7 shows an embodiment in which the present invention is applied to a device which selectively detects two signals having a time difference therebetween as shown in Fig. 3. By reciprocally controlling the switches 41 and 42, and 43 and 44 also in this embodiment, it is possible to select signals induced below the floating gate electrodes 13 and 14 to realize the charge detection. For making such a selection, it is sufficient to use a logic circuit, e.g., as shown in Fig. 8 to generate control pulses S and S and sample hold pulses SH₁ and SH₂. When such pulses are used, it is possible to set one of the floating gate electrodes 13 and 14 to the charge transfer mode, and to set the other electrode to the charge detection mode. For example, pulses S and S obtained in the logic circuit in Fig. 8 are used as follows. Namely, pulses S and S are delivered to S₁ of the switch 41 and S ₁ of the switch 42, respectively, and pulses S and S are delivered to S₂ of the switch 43 and S ₂ of the switch 44, respectively. Thus, when the pulse represents high level, the switches 41, 42, 43 and 44 are turned on, off, off and on, respectively. In addition, the floating gate electrodes 13 and 14 are brought into the charge transfer mode and the charge detection mode, respectively. At this time, since the sample hold pulse SH₁ shifts to low level as shown in Fig. 9, the switch 20 is turned off. The sample hold pulse SH₂ allows the switch 19 to be in on and off states. Thus, an output signal from the output circuit 17 is placed in sample-hold condition. On the other hand, when the pulse S represents low level, the floating gate electrodes 13 and 14 are, in a manner opposite to the above operation, brought into the charge detection mode and the charge transfer mode, respectivley. In addition, the switch 19 is turned off. Thus, the sample hold is performed by the switch 20. Fig. 10 is a circuit diagram showing an example where the device in Fig. 7 is constituted with an actual transistor circuit. In this example, FETs of which gate portions are indicated by solid lines denote depletion type transistors and the remaining FETs denote enhancement type transistor. Since input contacts 55 and 56 of the step-up capacitors 11 and 12 serve as output contacts of inverters 51 and 52, respectively, a signal which is 180 out of phase of  ₂, i.e., the clock  ₁ is delivered. Thus, clocks  and  in Fig. 7 correspond to  ₁ and  ₂ in Fig. 10, respectively. The switches 15, 16, 41, 42, 43, 44, 19 and 20 in Fig. 7 correspond to MOSFETs 15, 16, 41, 42, 43, 44, 19 and 20 in Fig. 10, which are the same reference numerals as those of the switches, respectively. Constant voltage sources 61 and 62 in Fig. 7 correspond to the constant voltage sources 61 and 62 in Fig. 10, respectively. The output signal processing circuits 17 and 18 in Fig. 7 correspond to source followers constituted with MOSFETs 45 and 46, and 47 and 48 in Fig. 10, in which impedance conversion of an output signal is performed. The output signal 21 which has undergone sample-hold in Fig. 7 corresponds to a voltage V₀ which has passed an amplifier constituted with MOSFETs 49 and 50 to undergo impedance conversion by the source follower constituted with MOSFETs 53 and 54, thereafter to be output to the outside. As just described above, by controlling the pulse S, a setting can be made such that only a necessary floating gate electrode or electrodes are in the charge detection mode and the remaining floating gate electrodes are in the charge transfer mode, thus making it possible to prevent an unnecessary signal from being mixed into the output signal processing circuit. Thus, since only a necessary detection signal is delivered to the signal processing circuit, there is no possibility that crosstalk occurs as in the conventional device. It is possible to inversely change the orders of the switches 42 and 44, and switches 15 and 16 in Figs. 7 and 10. In addition, it is also possible to constitute the switches 15 and 42 or the switches 16 and 44 as a unitary switch, thus making it possible to logically control them, respectively. For example, Fig. 11 is a circuit diagram showing a unitary switch comprising the switches 15 and 42, and Fig. 12 shows an operational function Table. By controlling a switch 110 using a pulse S ₁ in a manner stated above, the switches 15 and 42 in Fig. 7 can be replaced with the single switch 110. It has been described in the above-mentioned embodiments that transfer is carried out using the two-phase clock. In addition, the present invention is also applicable to the transfer using a single phase clock. Fig. 13 shows an embodiment where the present invention is applied to the single phase CTD. In the single phase CTD, the transfer is carried out under condition where one of each electrode pair is held at an intermediate fixed potential V M and a pulse  is applied to the other. To this end, a reference power sourced 111 is connected to a read electrode 113 through a switch 112 and the switch 112 is controlled by a timing pulse S+ S  having an operational function as shown in Fig. 14. When the switch 112 is in on state, a voltage V H which takes an intermediate level with respect to the transfer pulse  is delivered from the reference power source 111 to the electrode 113. Thus, the electrode 113 serves as solely the transfer electrode. In contrast, when the switch 112 is in off state, the electrode 113 is in floating condition. Thus, it functions as a detection electrode for detecting charges transferred from the preceding stage thereof to deliver a detection signal to the output circuit 8. The present invention is not limited to devices provided with two read electrodes as in the above-mentioned embodiments, but is applicable to devices generally provided with single or a plurality of read electrodes to selectively detect charges therefrom. In addition, the present invention is also applicable to devices to take out an arbitrary number of outputs from a plurality of electrodes to apply various operations thereto. When a selection is made such that non-selected electrodes are in the transfer mode, there is no possibility of occurrence of crosstalk due to signal components unnecessary for a detection signal from a selected electrode. As apparent from the foregoing description, a charge transfer device provided with a charge detection circuit according to the present invention is constituted to select either of the charge detection mode and the charge transfer mode, thus allowing the read electrode to be operation in a selected mode. Thus, a crosstalk based on a signal obtained from the detection circuit can be suppressed.

Claims: A charge transfer device comprising: a charge transfer path; a plurality of transfer electrodes (7; 10; 114; 700) provided on said charge transfer path; at least a first read electrode (600; 13) and a second read electrode (14) provided at first and second portions on said charge transfer path; clock means (,  ) for delivering a clock signal to said transfer electrodes (7; 10; 114; 700) to effect transfer on said charge transfer path; detector means (11, 15, 61; 12, 16, 62; 200) provided for each read electrode (600; 13, 14) for detecting signal components of a charge (9) below said read electrodes (6; 13, 14; 113; 600) without affecting a charge transferred on said charge transfer path; and transfer means (300) provided for each read electrode (600; 13, 14) for delivering a predetermined signal to said read electrodes (13, 14), thus allowing a charge below said read electrode (13, 14) to be transferred; characterized by selector means (400) for allowing said detector means (200) to be operative for said first read electrode (13) only and said transfer means (300) to be operative for said second read electrode (14) only or vice versa (Figs. 5, 7). A charge transfer device as set forth in claim 1, wherein read electrodes (13, 14) are provided at a plurality of portions on said charge transfer path. A charge transfer device as set forth in any one of claims 1 to 2, wherein said detector means (200) is provided with a detection circuit (201, 202, 203) of the floating gate system type. A charge transfer device as set forth in any one of claims 1 to 3, wherein said transfer means (300) delivers a clock signal (  ) used in said clock means to said read electrode or electrodes (13; 14). A charge transfer device as set forth in any one of claims 1 to 3, wherein said transfer means (300) delivers a voltage signal (V M ) of an intermediate level between high and low levels used in said clock means to said read electrode or electrodes (113).

Inventors: HOSOYA, NAOKI, IMAI, SHIN-ICHI
Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA AUDIO VIDEO ENGINEERING CO., LTD.
Application year: 1987
Main classification: G11C19
IPC codes: H01L29, H01L21, G11C19