Code converter with complementary output voltages

Abstract: A double-ended code converter (10) contains three or more like-configured amplifiers (T₀ - T M+1 ). Each has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for receiving a signal to control charge carriers moving from the first electrode to the second. The first electrodes are coupled to a circuit supply (12) which may be a current source or a voltage supply, the second electrodes are selectively coupled to one or the other of a pair of lines (L B and L BN ) which are coupled to respective load elements (14 B and 14 BN ) to provide a pair of complementary signals.

Description: FIELD OF USE This invention relates to code converters suitable for use in devices such as analog-to-digital (A/D) converters. BACKGROUND ART Speed, component count, and accuracy are important considerations in designing an A/D converter. Parallel converters provide the greatest speed in converting an analog input voltage (generally referred to as "V I ") into an n-bit digital code. A typical parallel A/D converter, such as that described in Nordstrom et al, UK Patent GB-A-1,547,918, or Fujita, EPO Publication EP-A 120,424, has 2 n input comparators for comparing V I with a like number of reference voltages. The comparators are differential devices. For example, each comparator in Nordstrom et al. employs a pair of NPN transistors whose emitters are tied to a current source. The bases of the pair follow V I and a corresponding one of the reference voltages. The collectors provide complementary signals on a pair of lines connected to respective load elements. Each comparator is in one of two states. As V I traverses an input voltage range in one direction, a progressively greater number of the comparators provide outputs representing a particular one of the states. A logic network operates on the "thermometer" output supplied by the comparators to generate 2 n circuit signals. Each circuit signal is normally logical low and reaches logical high only when V I is in a designated portion of the input range. The designated portion for each signal is separate from (i.e., does not overlap) the designated portion for each other signal. The designated portions are also spread out at approximately equal intervals across the input range. In this way, all the circuit signals are low at any time except for the one corresponding to the current value of V I . A code converter transforms the circuit signals into the digital code which is supplied on n output lines. In Nordstrom et al., the code converter consists of 2 n NPN transistors. Each has one or more emitters connected selectively to the output lines according to the desired coding. The code converter is Fujita is an array of like-polarity field-effect transistors (FET's) whose sources are grounded. The drains of the FET's are selectively connected to the output lines. Since the code converter is Fujita or Nordstrom et al is single ended, a reference must be used to determine whether each bit of the output code is logical low or logical high. The main disadvantage of a parallel A/D converter is a high component count due to the large number of input comparators. The device requires a large chip area when implemented as an integrated circuit. One of the more promising means for cutting component count is a "folding" system. See: van de Grift et al, "A Monolithic 8-bit Video A/D Converter", IEEE JSSC , Vol SC-19 No. 3, June 1984, pp. 374-378; and van de Plassche et al, "A High-Speed 7 bit A/D Converter", IEEE JSSC , Vol SC-14, No. 6, Dec. 1979, pp. 938-943. As described in each of these references, a folding A/D converter contains a coarse parallel A/D converter, a folding circuit, and a fine parallel A/D converter. The coarse converter operates directly on V I to generate the m most significant bits of the digital code. The folding circuit contains a set of input amplifiers that compare V I with at least four different reference voltages supplied from a voltage divider. The amplifiers are interconnected in such a way as to directly generate one or more pairs of complementary waveforms having a repetitive rounded triangular shape as a function of V I . Extreme values of each waveform occur at V I values dependent on selected ones of the reference voltages. The fine converter operates on these waveforms to produce the remaining n-m bits. A folding A/D converter utilizes considerably less comparators, including input amplifiers, than an equivalent parallel converter. Chip area is reduced dramatically. However, generation of the repetitive rounded triangular waveforms in the unitary way described above makes the folding converter unduly sensitive to noise. It would be desirable to have a simple technique for overcoming this problem. GENERAL DISCLOSURE OF THE INVENTION The central feature of this invention is a circuit that converts an input code into an output code consisting of one or more pairs of complementary signals. Due to the double-ended nature of the present code converter, there is no need to use a reference for ascertaining whether each bit of the output code is at a high level or a low level. Accuracy is thus better than that of the single-ended code converters discussed above. Frequency response is also better. In one aspect of the invention, the code converter is part of an electronic circuit comprising an input section for providing at least three different circuit signals that vary between a high-level value and a low-level value in response to an input parameter that varies across an input range, each circuit signal reaching its high-level value when the input parameter is in a designated portion of the input range separate from the designated portion for each other circuit signal. The code converter comprises a current source for providing a substantially constant supply current; two load elements respectively connected to two lines for providing complementary respective signals and at least three like-configured amplifiers respectively corresponding to the circuit signals, each amplifier having a first flow electrode connected to the current source, a second flow electrode, and a control electrode for receiving the corresponding circuit signal so as to cause the path between the first and second flow electrodes to become maximally conductive when the corresponding circuit signal is at its high-level value, charge carriers that move between the flow electrodes of each amplifier originating at its first flow electrode and terminating at its second flow electrode under control of its control electrode, the second flow electrodes being selectively connected to the one or the other of the lines in such a manner that each line is connected to at least one of the second flow electrodes. EP-A-0 259 932, which is prior art according to Article 54(3) EPC, discloses a similar electronic circuit. In this circuit, however, the second flow electrodes of the amplifiers are all connected to a DC voltage source and the first flow electrodes of the amplifiers are connected to the lines for providing complementary signals. EP-A-0 167 339 discloses a circuit arrangement comprising a current source, two load elements and at least three like-configured amplifiers, interconnected in a similar way. The control electrodes, however, are not connected to an input section for providing circuit signals in response to an input parameter in the manner disclosed above. The instant code converter is useful in the folding circuit of a folding A/D converter. In contrast to the unitary folding circuits of prior art folding A/D converters, the folding circuit in the present A/D converter utilizes a pair of functionally different portions for generating the repetitive triangular-like waveforms. The division into two portions reduces sensitivity to noise, thereby improving accuracy. One of the portions produces three or more circuit signals respectively associated with different pairs of four or more reference voltages. The waveform for each circuit signal has a rounded triangular shape that reaches a high-level value when the input voltage is between the associated pair of reference voltages. The other portion employs the present code converter for selectively combining these waveforms to produce the repetitive triangular waveforms. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a circuit consisting of an encoder and a double-ended code converter according to the invention. Fig. 2 is a circuit diagram of an expanded embodiment of the circuit of Fig. 1 in which the encoder produces digital signals; Figs. 3a and 3b are graphs of waveforms for certain signals in this embodiment. Fig. 4 is a circuit diagram of an expanded embodiment of the circuit of Fig. 1 in which the encoder produces linear signals; Fig. 5 is a graph of the waveforms for certain signals in this embodiment. Fig. 6 is a block diagram of a folding A/D converter utilizing the encoding and code converting circuitry of Fig. 4; Figs. 7a and 7b are graphs of waveforms for the respective input and output codes of the code converting circuitry. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, Fig. 1 illustrates a circuit containing a code converter 10 which transforms an input code consisting of M+2 circuit voltages V A0 , V A1 ... V AM+1 into an output code consisting of largely complementary main voltages V B and V BN . M is 1 or more. Voltages V A0 - V AM+1 are often referred to collectively as the "V A " signals. Likewise, voltages V B and V BN are often referred to collectively as the "V B " signals. Code converter 10 is formed with M+2 like-configured three-electrode amplifiers T₀, T₁, ...T M+1 , often referred to collectively as the "T" amplifiers. Each amplifier T j (where j runs from 0 to M+1) has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for controlling current flow between the flow electrodes (E1 and E2). Charge carriers moving between the flow electrodes originate at the first electrode and terminate at the second electrode. Each amplifier T j may be embodied with a single transistor. In the case of a bipolar transistor, its emitter, collector, and base are respectively the first, second, and control electrodes. These are the source, drain, and gate for an FET of either insulated-gate or junction type. Amplifier T j could, however, consist of more than a single transistor. One example is a bipolar Darlington circuit in which the emitter of an input transistor is connected to the base of a trailing transistor. In this instance, the control electrode is the base of the input transistor, while the first and second flow electrodes are the omitter and collector of the trailing transistor. As used in describing the T amplifiers, "like-configured" means that they have corresponding elements interconnected in the same way and that each set of corresponding elements is of the same semiconductor polarity. For example, the T amplifiers would generally be "like-configured" if they all are NPN transistors (even though of differing sizes), but not if some are NPN transistors while others are PNP devices. Likewise, Darlington circuits are "like-configured" as long as the input transistors are of the same polarity and the trailing transistors are of the same polarity (even if different from that of the input transistors). Voltages V A0 - V AM+1 are respectively supplied as input signals to the control electrodes of amplifiers T₀ - T M+1 . Their first electrodes are all connected to a circuit supply 12 which may be a current source or a voltage supply. The second electrodes of selected ones of the T amplifiers are connected to an output line L B which is connected to a load element 14 B to provide voltage V B . The second electrodes of the remainder are connected to an output line L BN which is similarly connected to a load element 14 BN to provide voltage V BN . The particular connections of the second electrodes depend on the desired output code. Each voltage V Aj varies between a low-level value and a high-level value. The adjectives "low-level" and "high-level" are used to distinguish two different signal levels. The actual voltage of the "high-level" value may be greater than or less than that of the "low-level" value, depending on the internal characterisitics of the T amplifiers. For convenience, the low-level and high-level values are respectively referred to as "0" and "1". When V Aj is at "0", amplifier T j is substantially non-conductive. Amplifier T j is maximally conductive when V Aj is at "1". The input code is normally chosen such that only one of the V A signals is at "1" at any time, the remainder all being at "0". As a result, only one of the T amplifiers is maximally conductive at any time. The maximally conductive amplifier draws current through the particular line L B or L BN connected to its second electrode. This pulls the corresponding main signal V B or V BN to a low-level value also referred to here as "0". The remainder of the T amplifiers are all turned off so that no current flows through the other line L BN or L B . The other main signal V BN or V B is at a high-level value again denoted as "1". V B and V BN are complementary because their sum is "1". Each of a pair of the V A signals may lie between "0" and "1" such that the sum of the two signals is "1". The remainder of the V A signals are all at "0". The corresponding pair of the T amplifiers are partially conductive. The pair form a differential device operating in its "linear" range. If the second electrodes of both of the partially conductive amplifiers are connected to the same line L B or L BN , it conducts current to pull the corresponding signal V B or V BN to "0". No current flows through the other line L BN or L B . Its signal V BN or V B is at "1". If the second electrode of one of the partially conductive pair is connected to line L B while the second electrode of the other is connected to line L BN , V B and V BN lie between "0" and "1". Their actual values depend on the relative values of the two "non-zero" V Aj signals. The sum of V B and V BN is, however, still "1". There are several further limitations which usually must be satisfied for V B and V BN to be complementary. If supply 12 is a current source that provides a substantially constant supply current, the sum of V B and V BN is fixed by the supply current. The current source therefore should be fully conductive. Otherwise, the sum of V B and V BN will differ from "1" because insufficient current flows through lines L B and L BN . The T amplifiers normally need not be identical. However, they should be identical if supply 12 is a voltage supply, particularly when they are embodied with FET"s. An input encoder 16 generates the V A signals in response to an input parameter which varies across an input range. The input parameter is denoted generally as "V I ". Encoder 16 preferably sets each signal V Aj at "1" only when V I is in a single portion of the input range. This portion is separate from the portions of the input range where the other V A signals reach "1". Fig. 2 shows an expanded version of Fig. 1 in which the V A signals are "digital" signals. The circuit of Fig. 2 contains two code converters 10 X and 10 Y . Each is a bipolar embodiment of converter 10 for which M is at least 2. Converters 10 X and 10 Y receive the same V A input code but have different second electrode (collector) connections so as to produce different V B output codes. Dropping the subscript "X" or "Y" that distinguishes the elements of converter 10 X from those of converter 10 Y , each amplifier T j of Fig. 1 is an NPN transistor Q j in Fig. 2. Supply 12 is a current source I B that provides a substantially constant supply current. Each load element 14 B or 14 BN is a load resistor R L . Terminals V CC and V EE respectively provide high and low supply voltages. Input encoder 16 in Fig. 2 consists of a thermometer encoder 18 and M logical AND gates G₁ - G M . In response to parameter V I , encoder 18 generates M+1 digital signals S₁ - S M+1 that have a "thermometer" variation of the type indicated in Fig. 3a. As V I moves in the positive direction through the input range here indicated as extending from 0 to M+1, each signal S j switches in sequence from logical "0" to logical "1". The S j transitions are very sharp. Encoder 18 also generates the respective digital complements S N1 - S NM+1 of signals S₁ - S M+1 . For j running from 1 to M, each gate G j logically "AND's" signals S j and S Nj+1 to produce voltage V Aj . V A0 and V AM+1 are supplied directly as signals S N1 and S M+1 . Fig. 3b illustrates how the V A signals vary as a function of V I . Except for V A0 and AM+1 , each V Aj waveform sequentially rises sharply from "0" to "1", stays at "1" for a specified interval which is largely the same for all of waveforms V A1 - V AM , and falls sharply to "0" as the next signal V Aj+1 rises from "0" to "1". Fig. 3b also shows the resulting waveforms for signals V BX and V BNX for the particular collector connections depicted in Fig. 2 for converter 10 X . Fig. 4 illustrates an expanded version of Fig. 1 in which the V A signals are "linear" signals. The circuit of Fig. 4 contains an array 20 consisting of P code converters 10₁ - 10 P . Each converter 10 k (where k runs from 1 to P) is an embodiment of converter 10 utilizing the same elements as converter 10 X or 10 Y of Fig. 2. Converters 10₁ - 10 P have the same second electrode (collector) connections relative to one another but receive different V A input codes and thereby produce different V B output codes. In Fig. 4, an input amplifier circuit 22 operates on parameter V I , which is here an analog input voltage, to produce the V A signals. Circuit 22 is formed with a resistive voltage divider 24 and an array 26 consisting of P groups 26₁ - 26 P of differential amplifiers A jk . In turn, divider 24 consists of (M+1)P-1 resistors R D connected in series between low voltage V R11 and high voltage V RM+1P . Including these two voltages, divider 24 provides amplifier array 26 with (M+1)P reference voltages V R11 - V R1P ...V RM+11 . Each amplifier group 26 k consists of M+1 amplifiers A 1k - A M+1k that jointly provide M+2 voltages V A0k - V AM+1k to respective transistors Q 0k - Q M+1k in converter 10 k - V RM+1P . Each amplifier 26 k in combination with divider 24 is thus an embodiment of encoder 16. Each amplifier A jk amplifies the difference between voltages V I and V Rjk . The core of amplifier A jk is a pair of NPN transistors Q L and Q R whose emitters are connected to a constant current source I EE Voltages V I and V Rjk are supplied to the bases of transistors Q L and Q R . Their collectors are connected to respective load resistors R C . The non-inverted output of amplifier A jk would normally be available at the Q R collector. The Q L collector would normally provide the inverted (or complementary) output. For j running from 1 to M, each signal V Ajk is taken from a connection of the Q R collector in amplifier A jk to the Q L collector in amplifier A j+1k . This acts to "linearly AND" the non-inverted A jk output and the inverted A j+1k output. Components 24 and 26 k thus perform a "linear" function similar to the "digital" function performed by components 18 and G₁ - G M in Fig. 2. Fig. 5 generally illustrates how V A0 - V AM+1k vary with V I . Except for voltages V A0k and V AM+1k , each voltage V Ajk sequentially rises from "0" to "1" in a transition portion of the input range centered around V Rjk , stays at "1" in a main portion of the V I range extending from slightly above V Rjk to slightly below V Rj+1k , and then falls to "0" in another transition portion centered around V Rj+1k as the next voltage V Aj+1k rises from "0" to "1". Voltages V A0k and V AM+1k , which each make only a single transition, respectively account for underflow and overflow. Each transistor Q jk becomes progressively more conductive as its input voltage V jk moves from "0" to "1" and vice versa. The transitions in V A0k - V AM+1k are thereby reflected in V Bk and V BNk as shown in Fig. 5. Resistors R D preferably all have the same value. Consequently, the "main" portions of the V I range all have approximately the same pulse width and are spread out at approximately equal intervals from one another. By suitably adjusting the R D values, each main portion can be compressed to a single point. Fig. 6 illustrates an application of the encoding and code converting circuitry of Fig. 4 to an A/D converter of the multiple-folding type. This device converts analog voltage V I into an 8-bit digital code. M and P are both 8 here. The input section to the A/D converter is circuit 22 in which divider 24 provides 72 reference voltages V R11 - V R98 . Amplifier array 26 in circuit 22 compares V I with each of V R11 - V R98 to produce 80 circuit voltages V A01 - V A98 . Components 20 and 22 may include some additional circuitry to assure that the V A signals produce the necessary shapes for the V B signals at the low and high ends of the V I range. For j and k each running from 1 to 8, Fig. 7a illustrates the general shape for V Ajk as a function of V I . Each V Ajk waveform would ideally have the triangular shape shown in dashed line. Due to practical amplifier characteristics, V Ajk varies according to the more rounded shape indicated in solid line. V Ajk reaches a maximum when V I is approximately half way between V Rjk and V Rj+1k . Circuit 20, here acting as a folding array, electrically combines selected V A signals in the manner described above to generate 8 voltages C B1 - V B8 and their complements V BN1 - V BN8 . Fig. 7b depicts part of the resulting V B waveforms. V B1 is shown in thicker line. The remaining waveforms have the same shape and spacing as those illustrated. Due to the roundings of the tips of the V A waveforms, each V B waveform has a repetitive rounded triangular shape. Each voltage V Bk or V BNk reaches extreme values when V I is approximately halfway between each pair of voltages V Rjk and V Rj+1k . Returning to Fig. 6, an interpolation circuit 28 interpolates by a factor of 4 between each pair of consecutive V B signals to generate 32 interpolated signals V B1 - V B32 and their complements V NB1 - V NB32 . Applicant's pending U.S. patent application Ser. No. 809,453, filed 16 December 1985, discloses a suitable resistive interpolation circuit for this purpose. A group of comparators 30 compares V B1 - V B32 respectively with V NB1 - V NB32 to produce a string of 32 bits D1 - D32. A code converter 32, which may be conventional or may follow the teachings of this invention, converts the bit string into the five least significant bits MSB-3 -- MSB-7 of the digital code. The final part of the A/D converter is a group of comparators 34 which generate the three most significant bits MSB -- MSB-2 in response to three pairs of substantially complementary further signals V C . For convenience, Fig. 6 indicates that array 20 provides the V C signals.

Claims: An electronic circuit comprising an input section (16) for providing at least three different circuit signals (V A0 .. V AM+1 ) that vary between a high-level value and a low-level value in response to an input parameter (V I ) that varies across an input range, each circuit signal (V A0 ..V AM+1 ) reaching its high-level value when the input parameter (V I ) is in a designated portion of the input range separate from the designated portion for each other circuit signal (V A0 ..V AM+1 ), characterized in that the electronic circuit further comprises: a current source (12) for providing a substantially constant supply current; two load elements (14 B , 14 BN ) respectively connected to two lines (L B , L BN ) for providing complementary respective signals (V B , V BN ) and at least three like-configured amplifiers (T₀..T M+1 ) respectively corresponding to the circuit signals (V A0 ..V AM+1 ), each amplifier having a first flow electrode (E1) connected to the current source (12), a second flow electrode (E2), and a control electrode (CE) for receiving the corresponding circuit signal (V A0 ..V AM+1 ) so as to cause the path between the first (E1) and the second (E2) flow electrodes to become maximally conductive when the corresponding circuit signal (V A0 ..V AM+1 ) is at its high-level value, charge carriers that move between the flow electrodes of each amplifier originating at its first flow electrode (E1) and terminating at its second flow electrode (E2) under control of its control electrode (CE), the second flow electrodes being selectively connected to the one or the other of the lines (L B , L BN ) in such a manner that each line is connected to at least one of the second flow electrodes. A circuit as claimed in claim 1, characterized in that each amplifier (T₀..T M+1 ) comprises a bipolar transistor having an emitter, a collector and a base, which are respectively the first flow, the second flow and the control electrodes of that amplifier. A circuit as claimed in claim 1, characterized in that each amplifier (T₀..T M+1 ) comprises a field-effect transistor having a source, a drain, and a gate, which are respectively the first flow, the second flow and the control electrodes of that amplifier. A circuit as claimed in claim 1, 2 or 3, characterized in that the circuit signals (V A0 ..V AM+1 ) are digital signals, each amplifier (T₀..T M+1 ) being turned off when the corresponding circuit signal (V A0 ..V AM+1 ) is at its low-level value, only one of the circuit signals (V A0 ..V AM+1 ) being at its high-level value at any time, whereby effectively only one of the amplifiers (T₀..T M+1 ) is turned on at any time. A circuit as claimed in claim 1, 2 or 3, characterized in that the circuit signals (V A0 ..V AM+1 ) are linear signals, each amplifier (T₀..T M+1 ) being non-conductive when the corresponding circuit signal (V A0 ..V AM+1 ) is at its low-level value, and becoming progressively more conductive as the corresponding circuit signal (V A0 ..V AM+1 ) moves to its high-level value, each signal moving to its low-level value as the input parameter (V I ) traverses either of a pair of transition portions sandwiched about the designated portion of the input range for that circuit signal, each transition portion except the two most distant transition portions overlapping precisely one of the other transition portions, whereby two of the amplifiers may be conductive at the same time. A circuit as claimed in claim 1, 2, 3, 4 or 5, characterized in that the designated portions are spread out at largely equal intervals across the input range. A circuit as claimed in claim 1, 2, 3, 4, 5 or 6, characterized in that the input section provides a fourth circuit signal (V A0 ..V AM+1 ) that varies between a high-level value and a low-level value in response to the input parameter (V I ), the fourth circuit signal reaching its high-level value when the input parameter (V I ) is in a designated portion of the input range separate from the other designated portions and in that the electronic circuit further comprises a like-configured fourth amplifier (T₀..T M+1 ) having a first flow electrode (E1) connected to the current source (12), a second flow electrode (E2) connected to a selected one of the lines (L B , L BN ), and a control electrode (CE) for receiving the fourth circuit signal so as to cause the fourth amplifier (T₀..T M+1 ) to become maximally conductive when the fourth circuit signal (V A0 ..V AM+1 ) reaches its high-level value, charge carriers that move between the flow electrodes of the fourth amplifier originating at its first flow electrode (E1) and terminating at its second flow electrode (E2) under control of its control electrode (CE). A circuit as claimed in claim 1, characterized in that the circuit further comprises: a further current source (I BY ) for providing a substantially constant supply current; two further load elements (R L ) respectively connected to two further lines (L BY , L BNY ) for providing complementary respective signals (V BY , V BNY ) and at least three further like-configured amplifiers (Q 0Y ..Q M+1Y ) respectively corresponding to the circuit signals (V A0 ..V AM+1 ), each further amplifier having a first flow electrode connected to the further current source (I BY ), a second flow electrode, and a control electrode for receiving the corresponding circuit signal (V A0 ..V AM+1 ) so as to cause that amplifier to become maximally conductive when the corresponding circuit signal is at its high-level value, charge carriers that move between the flow electrodes of each further amplifier (Q 0Y ..Q M+1Y ) originating at its first flow electrode and terminating at its second flow electrode under control of its control electrode, the second flow electrodes of the further amplifiers (Q 0Y ..Q M+1Y ) being selectively connected to the one or the other of the further lines (L BY , L BNY ) in such a manner that each further line is connected to at least one of those second flow electrodes. An analog-to-digital converter for converting an analog input voltage (V I ) which varies across an input range into a digital code (MSB..MSB-7), there being: reference means (24) for providing at least four different reference voltages (V R11 ..V RIP ..V RM+11 ..V RM+1P ) spread out across the input range; means (22, 20) responsive to the input (V I ) and reference (V R11 ..V RIP ..V RM+11 ..V RM+1P ) voltages for generating at least one pair of largely complementary main signals (V B1 - V B8 , V BN1 -V BN8 , V C ), the voltage waveform for each main signal as a function of the input voltage being of a repetitive rounded triangular shape with extreme values occurring at values of the input voltage dependent on selected ones of the reference voltages; and means (34, 28, 30, 32) for operating on the main signals (V B1 - V B8 , V BN1 -V BN8 , V C ) to generate at least part of the digital code (MSB-3 .. MSB-7, MSB .. MSB-2), characterized in that the means (20, 22) for generating comprises: an input section (A₁₁..A M+1P ) for providing at least three circuit signals (V A01 ..V AM+1P ) respectively associated with different pairs of the reference voltages (V R11 ..V RIP ..V RM+11 ..V RM+1P ), the waveform for each circuit signal (V Ajk ) as a function of the input signal (V I ) being of a rounded triangular shape, reaching a high-level value when the input voltage is at a specified value between the associated pair of reference voltages (V Rjk, V Rj+1k ) and moving to a low-level value as the input voltage moves away from the specified value; and at least one signal converter (10₁ ..10 P ), each comprising: a current source (I B1 .. I BP ) for providing a substantially constant supply current; two load elements (R L ) respectively connected to two lines (L B1 ,L BN1 ..L BP ,L BNP ); and at least three like-configured amplifiers (Q 01 ..Q M+1P ) respectively corresponding to the circuit signals (V A01 .. V AM+1P ), each amplifier having a first flow electrode, a second flow electrode and a control electrode for receiving the corresponding circuit signal, charge carriers that move between the flow electrodes of each amplifier originating at its first flow electrode and terminating at its second flow electrode under control of its control electrode, the first flow electrodes of each amplifier (Q₀₁, Q₁₁ ... Q M+11 ) being connected to the current source (I B1 ), the second electrodes of the amplifiers (Q₀₁, Q₁₁, Q M+11 ) selectively connected to the one (L BN1 ) or the other (L B1 ) of the lines in such a manner that each line is connected to the second electrode of at least one of the specified amplifiers, the lines (L B1 , L BN1 ) providing a pair of the largely complementary signals (V B1 , V BN1 ). An analog-to-digital converter as claimed in claim 9, characterized in that each amplifier is a bipolar transistor having an emitter, a collector and a base which are respectively the first flow electrode, second flow electrode and control electrode of that amplifier.

Inventors: VAN DE PLASSCHE RUDY JOHAN, VAN DE PLASSCHE, RUDY JOHAN
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: H03M1
IPC codes: H03M1