APPARATUS FOR SUPPLYING VIDEO DATA FOR REFRESHING DISPLAY ELEMENTS OF A DISPLAY DEVICE

Abstract: The present invention relates to an addressing circuit for providing character addresses for use in supplying video data for refreshing characters displayed in a plurality of lines of characters in a multi-panel display device. Such a circuit comprises character count means for providing a character count along each character line, character line count means for providing a character line count for each panel, and address generating means for combining the character count and the character line count to generate an address for each character. According to the invention the circuit is characterised in that the address generating means generates addresses for characters in successive lines alternating between the panels (10, 12). The invention also relates to a circuit providing video data to refresh all the display elements in a display device having a plurality of panels arranged to display characters comprising an addressing circuit as above.

Description: This invention relates to visual display devices and more specifically to arrangements for providing video data for refreshing each display element in a display device. Traditional display devices such as liquid crystal displays require that video data be continuously provided to them in a manner that refreshes the image on the display. For a single display containing a plurality of display elements forming picture elements (pixels or pels), the refreshing is accomplished by providing a stream of video data to the display where each individual data element represents the state of a pel. In liquid crystal displays, this series of data corresponds to consecutive series of lines on the display. A typical scheme for refreshing a liquid crystal display is disclosed in the IBM Technical Disclosure Bulletin entitled "Liquid Crystal Display System" by J. C. Elliott in Vol. 16, No. 4, page 1087 (September, 1973). A corresponding patent, US-A- 3,787,834 discloses a liquid crystal display system that provides data to five liquid crystal display panels. The panels include liquid crystal display elements which are composed of segments. The object of the present invention is to provide an improved addressing circuit for use in supplying video data for use in refreshing characters displayed in a multi-panel display device. The present invention relates to an addressing circuit for providing character addresses for use in supplying video data for refreshing characters displayed in a plurality of lines of characters in a multi-panel display device. Such a circuit comprises character count means for providing a character count along each character line, character line count means for providing a character line count for each panel, and address generating means for combining the character count and the character line count to generate an address for each character. According to the invention the circuit is characterised in that the address generating means generates addresses for characters in successive lines alternating between the panels. The invention also relates to a circuit for providing video data to refresh all the display elements in a display device having a plurality of panels arranged to display characters comprising an addressing circuit as above. In order that the invention may be more readily understood, an embodiment will now be described with reference to the accompanying drawings, in which: Figure 1 includes: Figure 1A which is an illustration of two display panels arranged to display a single image of text with which the invention may be used, and Figure 1B which is an which illustration of the refreshing sequence for two display panels utilising apparatus in accordance with the invention, Figure 2 is a block diagram illustrating the formation of the font address from the character scan code and the character scan line in the arrangement of Figure 1B, Figure 3 is a schematic block diagram of the character address circuitry in accordance with the invention, Figure 4 is a schematic block diagram of the font address circuitry, and in the apparatus of Figure 3, Figure 5 is a system block diagram illustrating the generation of the video data utilising the apparatus of Figure 3. The invention relates to a visual display device of the type illustrated in Figures 1A and 1B. Such a device includes two panels of liquid crystal display elements, an upper panel 10 and a lower panel 12. The display elements in these panels form a plurality of picture elements arranged in parallel lines extending across the panels. The picture elements in each line are energised selectively in order to display lines of characters in the display device. The height of each character is greater than the height of an individual line of picture elements so that two or more lines of picture elements are needed to display each line of characters. As illustrated in Figure 1A, each line of characters may be a relatively long line 24, 26, 28 extending across most of the width of the panel, or a relatively short line 22 extending across only a small portion of the width of the panel. Two relatively short lines 29A, 29B may be arranged end to end and spaced apart and extending across the panel. The upper and lower panels 10, 12 abut along a common boundary 11 and one line of characters 26 extends partially in each panel so that the upper part 26A of this line is in the upper panel 10 and the lower part 26B is in the lower panel 12. The liquid display elements of the display device remain energised for only short periods of time and need to be refreshed. It is therefore necessary to supply video data for refreshing each of the elements. This video data is supplied to the display elements in succession. Figure 1B illustrates how the refresh video data is supplied to each display element in succession. The data for the top line of elements 14 in the upper panel 10 is first supplied. Then the data for the top line of elements 18 in the lower panel 12 is supplied. Then the data for the second line of elements 16 in the upper panel is supplied. Then the data for the second line of elements 20 in the lower panel is supplied. This process is continued until refresh video data has been supplied to all the lines of display elements. This principle can be applied to display devices having three or more panels of display element. In such a case, first the elements in the first line of elements in each of the panels are refreshed in succession. Then, the elements in the second line of elements in each of the panels are refreshed in succession. This process is continued until all the elements in all the lines have been refreshed. Figure 1B illustrates the difference between refreshing two distinct panels of liquid crystal displays as opposed to refreshing a single panel of a liquid crystal display or of refreshing a cathode ray tube monitor according to the invention. The video data to be used in refreshing the lines of picture elements in a multi-panel display is sent line by line successively alternating between each panel. In other words, the elements of the first line of the first panel are refreshed followed by the elements of the first line of the second panel and so on until all first lines of all panels have been refreshed. The procedure is then repeated for refreshing the elements of the second line of all panels. This procedure is again repeated until all lines of all panels have been so refreshed. If the data for the image displayed in the display device is stored in a memory arrangement resembling the final displayed image, the addressing of the refresh data in the memory must proceed in this successive line alternating across the panels fashion. However, this display data is stored in memory that is addressed in sequence from the top of the image to the bottom. For this reason, generating the correct character addresses for the bottom panel lines is not straightforward. According to the invention a centre row address register provides an offset which is added to the character counter to simplify the addressing of characters on lines in the bottom panel. In a preferred embodiment, each character is defined by a character scan code which occupies all even display memory addresses. Character attributes occupy the odd addresses. The address of the first character scan code of the first position and first row of the bottom panel for an 80 character per line display (having 25 display lines) would be 19 hex divided by 2 (i.e., shift right logical) to equal 0C hex and then multiplied by 50 (80 decimal) to equal 3C0 hex which would be shifted left logical (multiplied by 2) to equal 780 hex. Since the even memory boundaries are used for the scan codes and the odd boundaries used for the attribute codes, the least significant bit is not used and only 3C0 need be stored as the offset. By using this offset, the lines of the bottom panel may be successively addressed with characters of the lines of the top panel to provide a continuous data stream in a manner prescribed by Figure 1a. Font address generation is dependent upon the scan codes that are accessed by the character addresses of the previously discussed addressing scheme. The scan code is applied to the character scan line of the character presently refreshed. Characters contained in an 8 × 8 character box are defined by 8 scan line bytes (as illustrated in Figure 2). Therefore, each successive scan line will be refreshed for each panel in a manner illustrated in Figure 1a. In an 8 × 8 matrix, each scan line byte is indexed from 0 to 7 with 0 being the top of the character box and 7 being the bottom (see Figure 2). Therefore, in this 8 × 8 embodiment, three bits define the character font scan line. Font address generation for the 3 bit character font scan line is straightforward. In a two panel liquid crystal display arrangement with an even number of text lines, the character scan line refresh for the top panel is the same one as that being refreshed for the bottom panel. However, when an odd number of text display lines are being displayed as illustrated in Figure 1b, the centre character line of the text 26 will be split in half where half 26a of the text line will be displayed in the top panel and half 26b of the text line will be displayed in the bottom panel. Therefore, the top panel bottom series of scan lines will display the top portion of the centre text line 26a and the bottom panel will display the bottom series of scan lines for the centre text line 26b. In this situation, the addressing of the scan lines for the bottom panel is not straight- forward. This addressing can be provided for by providing a character box centre register which contains an offset to generate the proper font addresses to address the correct character font data for the bottom panel. Therefore in an 8 × 8 character box, this register would be loaded with a 4. Therefore, the first scan line of the first character line of the bottom panel would display font byte 4 instead of font byte 0 (the first scan line for the top panel). By refreshing the top and bottom panel in a manner of Figure 1a, using the character box centre register, the split centre character line will be properly displayed. In the preferred embodiment for an 8 × 8 matrix, a modulo 8 counter that counts from 0 to 7 is implemented. As the character scan lines being refreshed progress from 0 to 3 in the top panel, scan lines being refreshed will progress from 4 to 7 in the bottom panel. When the top panel character scan line data reaches line 4, the bottom panel scan line data must be at line 0. In the case of an 8 × 8 character box, the 3 bit scan line counter being used for the top panel is offset by 4, the value in the character box centre register and therefore, when the top panel scan line data reaches line 4, the bottom panel line data is at line (4 + 4) or 0 in the modulo 8 adder with the overflow carry signal being ignored since 8 is a number that is an integer power of 2 having an even binary boundary. However, if the circuitry is to provide different size character boxes such as an 8 × 10 box, the scan line counter requires additional logic to provide the proper operation of a modulo 10 counter. A 10 count line character box uses 4 bits of a counter. However, to operate properly, a modulo 10 counter would have to count from 0 to 9. A 4 bit counter will not count in this manner. The arrangement being described provides a means to enable this 4 bit counter to act as a modulo N counter where N is any variable. For example, an 8 × 10 character box as the top panel scan lines increments from 0 to 10, the bottom panel scan line increments from 5 to 9 by directly adding the offset of the value 5 in the character box centre register. As the top panel scan line reaches 5, the bottom panel scan line should return to 0 indicating that a new character or text line is about to commence. Adding the offset value as before does not yield a 0, but rather an A hex. Therefore, after the bottom panel scan line has reached its maximum, the one's complement of the maximum scan line value must be added to the top panel scan line value in addition to adding of the offset value of the character box centre register. The one's complement of the maximum scan line value is obtained by inverting each of the bits. A 9 in binary format is 1001 and its one's complement is 0110. So as the top panel's scan line increments from 5 to 9, the bottom panel's goes from 0 to 4 with overflow carries that are ignored. The 4 bit modulo N counter with N will count to 9 for the 8 × 10 character box case, then resets to 0 for the top panel's scan line to begin a new text line. After the top panel scan line has reached its maximum, the initial method of adding the character box centre register offset value is reverted to. It should be understood that while this example uses an 8 × 10 character box, the arrangement described will work for any 8 × N character box where N is any variable. The addressing circuitry driving a two panel liquid crystal display which has an odd number of text character lines must also duplicate its addressing registers. If must increment its character addresses for new text lines at different intervals for the top and bottom panels because of the split in the centre character text line. The bottom panel scanning operation reaches a new text line while the top panel scanning operation has just reached the centre of its present text line. The addressing registers for the top panel are bumped when a top panel text line is completed and those for the bottom panel are bumped when the bottom panel text line is completed. Since these lines are completed at different times, separate addressing registers are required. For the case of an even number of text lines, only one set of addressing registers is required since the top text line and the bottom text line will have this same scan line count during refresh. Figure 3 illustrates a schematic block diagram of the character address circuit. In Figure 3, the maximum number of horizontal characters per line is contained in a register 30. The contents of register 30 is decremented by 1 in a decrement circuit 34 to provide a constant on lines 36 to a compare circuit 40. The maximum number of characters per line is also input to an adder 58 by line 32. The character counter 38 is clocked by a signal on line 46 (clock signal A) and increments from the 0 position to the maximum horizontal character register position that is loaded into comparator 40. When comparator 40 determines that the last character of the horizontal line has been incremented, then comparator 40 outputs the signal on line 42 which resets the character counter 38. This signal on line 42 also is input to an exclusive OR gate 48 which provides an output on line 52 to a D flip-flop 50. The output of the D flip-flop on line 54 is also input to the exclusive OR gate 48. The D flip-flop 50 is further clocked by the clock A signal on line 46. The output of the D flip-flop 50 provides the signal indication on line 54 as to whether the characters in the top panel or characters in the bottom panel are being refreshed. The adder 58 receiving the maximum horizontal character constant from register 30 provides an output to both the top panel text start line address register 64 and the bottom panel text start line address register 70. Both registers 64 and 70 contain the line number that is being refreshed for their respective top or bottom panels. When a frame or image is first being refreshed, a signal is provided on line 68 to indicate a new frame. The signal on line 68 causes registers 64 and 70 to be reset at 0. After each line has been refreshed, the contents of either register 64 or 70 is then incremented by the total number of characters in the line, i.e., the contents of register 30 through adder 58. In this manner, the correct character count is maintained in both registers for both panels. As previously discussed, the character address for the characters in the bottom panel must be offset by a constant. This constant is contained in the centre row address register 80 and is combined by a line 82 and an adder 78 with the contents of the bottom panel text start line address register 70 via line 72. The output from the bottom panel text start line address register 70 is also provided through multiplexer 74 and line 76 to the adder 58 so that the contents of the bottom panel text start line address register 70 will be incremented by the total number of horizontal characters per line, i.e., the contents of register 30. Each line address from either register 64 or register 70 is combined with the character address on that line, i.e., the output of character counter 38 on line 44 in adder 90. The top panel register 64 or bottom panel register 70 is appropriately selected by the multiplexer 86 to provide that output on line 88 to adder 90. The output of adder 90 on line 91 is the character address without the least significant bit position, which, as previously discussed, is a 0 for the scan code address or a 1 for the attribute address. Initially, the circuitry in Figure 3 starts addressing the first line of the top panel by zeroing the contents of register 64 and incrementing the character counter 38 by clock 8 on line 46. This first line address for the top panel is merely the count output from the character counter 38 that is provided on line 44 to adder 90. Since the contents of the top panel register 64 is 0, the output of adder 90 is the input on line 44 on line 91. After the last character of the first line has been addressed, the compare circuit 40 increments the character counter 38 and also the D flip-flop 50 through exclusive OR gate 48. Character counter 38 begins incrementing again from the 0 position of the character line upward. This time the character address is combined with the contents of the bottom panel register 70, which is still 0, through adder 78 which provides the offset, through multiplexer 86 to provide the appropriate character address for the first line of the bottom panel on line 91. After this first line of the bottom panel has been addressed, again the character counter 38 is reset and the output of the D flip-flop 50 changes and the top panel register 64 is loaded with the maximum horizontal character count from register 30 through adder 58 as previously discussed. After the second line has been loaded, the D flip-flop 50 again switches and the maximum horizontal character counter of register 30 is then loaded into the bottom panel of register 70. The alternating between the top panel and the bottom panel registers 64 and 70 respectively continues as each line of characters is addressed for their respective panels. The output of the circuitry in Figure 3 is a character address that accesses both the character scan code and the attribute code as previously discussed. In Figure 4, the character address output on line 91 together with a binary 0, the least significant bit (on line 93) are both input to a character scan code memory 94 which output a character scan code for that character address on line 96. This character scan code on line 96 is combined with a character scan line number on line 116 to form the font address to access the font scan line data for the character. The scan line data on line 116 is derived from the remaining circuitry in Figure 4. A register 100 contains the maximum number of scan lines for a character box. This number is provided as a constant on line 102 to a compare circuit 104 which compares this constant with the output of the character box scan line counter 110 on line 112. When the maximum character scan line occurs, the output of the compare circuit 104 provides a signal on line 106 that resets the character box scan line counter 110 and also toggles the D flip-flop 154 through an OR gate 148 and exclusive OR 150. The constant compare circuit line 120 will provide a signal on line 62 to indicate a new text line on the top panel when a zero is output on line 112. The actual count from the character box scan line counter 110 on line 112 is provided as an output on line 116 for the character scan lines in the top panel. The scan lines for the bottom panel are provided to multiplexer 114 via line 140. As previously discussed, scan line count for the character boxes in the bottom panel are computed based on whether or not there is an odd number of character text lines thus requiring a split of a centre character text line and if the maximum number of character scan lines is an even binary number. To illustrate the operation of the circuitry to compute the character scan line for the bottom panel, three examples will be discussed. In the first example, it is assumed that the number of character text lines is even and the number of scan lines per character box is an integer power of 2 or a binary number having an even boundary. In this case, the signal on line 122 would be a 0 indicating an even number of character text lines across the top and bottom panels, and therefore, the output of AND gate 126 would be a 0 on line 128. Also, since the maximum number of scan lines is a binary number having an even boundary, such as 8 or 16, the output on line 102 through inverter 160 would be 0. Therefore, the character box scan line counter 110 output on line 112 would be added in adder 130 to a 0 on line 128, and the character count in counter 110 would be output through multiplexer 134 to multiplexer 114 which provide this number on line 116. In other words, for an even number of character text lines, the character scan line count for the top panel would be the same as the character scan line count for the bottom panel. In the case where an odd number of character text lines is to be displayed, the centre text line would be split between the top and bottom panels as previously discussed. This would require that the bottom panel scan line include an offset. This offset is provided in character box centre register 124 which is input on line 125 through the AND gate 126 which is anded with the odd number of character text lines on line 122. The effect of the signal on line 122 is to gate the offset in character box centre register 124 to the adder 130 on line 128 when the centre text line would be split. In that case, the offset would be added to the character box scan line count on line 112 in adder 130 and provided on line 132. In a situation where the maximum number of character scan lines is a binary number having an even boundary, i.e., an integer power of 2, this sum from adder 130 on line 132 would be switched through multiplexer 134 on line 140 to multiplexer 114 onto line 116. When the last scan line for the character line has been addressed on line 140, the constant compare circuit 142 will increment the bottom panel text start line address register 70 (Figure 3) on line 92. If the maximum number of character scan lines is not a binary number with an even boundary, i.e., not an integer power of 2, a modulo offset must be provided to the adder to make it appear as an even binary number so that the modulo adder will automatically return to 0. In the previous example, a 10 or hex A or binary 1010 is used to illustrate this situation. According to this example, the scan lines should count from 0 to 9 and then revert back to 0. A common binary adder of 4 bits, such as would be implemented as adder 136, would not increment back to 0 after 9, but rather to A hex. For this situation, the one's complement of the maximum character scan lines is provided as an offset to adder 136 and further the maximum number of character scan lines is provided to compare circuit 144 to allow the adders to return to 0 for a non-even boundary binary number. In other words, the one's complement offset would only be used when the scan line count for the bottom panel must be returned through a 0. The following Table 1 illustrates the operation of the circuit of Figure 4 in this example. TOP PANEL SCAN LINE CHAR BOX CENTRE 1'S COMPLEMENT OF MAX SCAN LINE ADD 1'S COMPLEMENT BOTTOM PANEL SCAN LINE 0 5 6 NO 5 1 5 6 NO 6 2 5 6 NO 7 3 5 6 NO 8 4 5 6 NO 9 (MAX) 5 5 6 YES 0 6 5 6 YES 1 7 5 6 YES 2 8 5 6 YES 3 9(MAX) 5 6 YES 4 0 5 6 NO 5 Figure 5 illustrates the video circuit 168 connected to the font scan line data memory 160 and the character attribute memory 162. The font scan line data memory receives the font address on lines 96 and 116 that address the font scan data in memory 160 which is output on line 164. The attribute data is addressed by the character address on line 91 with the 1 designating the attribute address as its lowest significant bit on line 163. Therefore, for each character font scan line data output on line 64, there is corresponding character attribute data on line 166. Attributes for character displays would include such features as reverse video or blinking or other attributes. The attribute is used to qualify the character font scan line data in the video circuit 168. Once qualified, the video circuit 168 will provide a serial stream of video data on line 170 to a display 172 consisting of liquid crystal display panels 176 and 178. The video circuit may be any video circuit that combines the font scan line data and the attribute data, such as the IBM PC monochrome card which is described in the IBM PC Technical Reference Manual herein incorporated by reference.

Claims: An addressing circuit for providing character addresses for use in supplying video data for refreshing characters displayed in a plurality of lines of characters in a multi-panel display device, comprising character count means for providing a character count along each character line, character line count means for providing a character line count for each panel, and address generating means for combining said character count and said character line count to generate an address for each character, characterised in that said address generating means generates addresses for characters in successive lines alternating between said panels (10, 12). An addressing circuit as claimed in claim 1 characterised in that said address generating means comprises register means for containing the start address of the first character and the first line for each panel. An addressing circuit as claimed in claim 2 characterised in that said register means comprises a register (64, 70) for each panel and switching means to increment the contents of each panel register alternately. An addressing circuit as claimed in any one of the preceding claims characterised in that said character line count means comprises means (80) for providing the character line count for a character displayed in at least two panels. An addressing circuit as claimed in claim 5 characterised in that said character line count means includes means for providing a count for N maximum number of character scan lines where N is any variable number. A circuit providing video data to refresh all the display elements in a display device having a plurality of panels arranged to display characters, comprising an addressing circuit as claimed in any one of the preceding claims.

Inventors: ARISMENDI, ARMANDO
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: G09G3
IPC codes: G06F3, G09G3, G09G5