CHANNEL ENCODER

Abstract: On the basis of n-bit words presented, the described channel encoder generates DC-free and run length limited m-bit (m n) code words having (1 + D)⁻¹ or (1 + D²)⁻¹ precoder properties. The m-bit code words are formed each time by appending (m-n) bits to the n-bit words presented. For the determination of the (m-n) bits to be added, the amplitude density function as well as the distribution of the run length and the digital sum variation of the code words is calculated.

Description: The invention relates to Channel encoder for encoding received n-bit information words into a stream of code bits, the stream being mainly DC free and run length limited, the encoder comprising a precoder, a precoded output signal of which corresponds with the stream of code bits, an input of said precoder being coupled for serially receiving m-bit intermediate words, the intermediate words comprising the received n-bit words combined with one or more (m-n) extra bits, the extra bits being supplied to the precoder from extra bit selection means, selecting the extra bits for keeping a digital sum variation of the stream of code bits near a currently desired value and/or limiting the run length of the stream, said extra bit selection means having a digital sum prediction input for receiving the n-bit information words and a signal form a counter the counter being arranged for determining a digital sum variation corresponding with the stream of code bits. Channel encoders are widely used in digital magnetic recording and playback apparatus in order to adapt the inputted data stream to the characteristics of the data transmission channels. In such apparatus the flux is differentiated in time by the read head. Ignoring some high-frequency losses, this flux has the same shape as the write current applied to the write head. The output signal of the read head then consists of positive and negative pulses at the areas where transitions occur in the write current. In order to obtain a replica of the write current at the playback side in said apparatus, so-called pulse amplitude detection methods can be used in addition to the detection by so-called "write current restoration", that is to say by integration of the output signal of the read head. In the pulse amplitude detection methods the pulses in the output signal of the read head are detected. Even though the signal reproduced is always DC-free as a result of the differentiation, for the latter detection methods preferably the write current is also mainly DC-free, because otherwise problems could arise when (rotating) transformers are arranged between the write amplifier and the write head or when other signals (tracking tones) must also be recorded at low frequencies. A channel encoder of this kind is known from the French Patent Application No. 2,469,047. In this known channel encoder, the counter receives a stream of code bits and determines the digital sum variation between two successively supplied information words. The digital sum variation (DSV) is determined in order to form the m-bits codeword. If the digital sum variation of the stream of bits is of the same sign as the digital sum contribution of the received n-bit word, the n-bit word is inverted and the m-n extra bits indicate whether inversion has occurred. This serves the purpose of making the stream of bits mainly DC free. Another channel encoder of this kind is known from a publication in the Journal of the Society of Motion Picture and Television Engineers (SMPTE) September 1983, pages 918-922: "8-9 Block Code: A DC-Free Channel Code for Digital Magnetic Recording", by H. Yoshida et al. According to this publication the DSV and the received n-bit word are used to select an m-bit intermediate code word from alternative code words corresponding to the n-bit code word in order to minimize the DSV after transmitting the selected code word. This publication also teaches the use of a precoder receiving the intermediate code word for precoding it into the stream of code bits. The known channel encoders have the drawback that they are restricted to precoders that form the stream of code bits only from the immediately available code bits. In particular, they are not suitable for keeping a mainly DC-free stream of bits when precoders are used in which the precoded bits from one word depend also on bits from an earlier precoded word, because such precoders affect the DC content of the stream of code bits. It is an object of the present invention to provide an encoder which outputs a coded signal which is mainly DC-free and run length limited (RLL) wherein a precoder is used in which the precoded bits from one word depend also on bits from an earlier precoded word. To achieve this, the channel encoder according to the invention is characterized, in that the precoder has a transfer function in which each code bit of the serially output stream of code bits is a function of a respective bit of the serially input intermediate word and of a preceding code bit, preceding the said code bit by a fixed number of successive preceding code bits, the counter and a further input of said extra bit selection means receiving the stream of code bits output from the precoder, the extra bit selection of a new intermediate word being also in response to at least the last code bit derived from the preceding intermediate word. By feeding back at least the last code bit derived from the preceding intermediate word, the effect of the preceding words it is possible to correct for the effect of these words on the DC content of the stream of bits through the precoder as described. An embodiment of the channel encoder according to the invention is characterized in that, the extra bit selection means comprises a memory (24), the received n-bit words being coupled to an address input, the memory storing a digital sum indication, indicative of the change to be obtained in digital sum variation in the counter after precoding an addressed n-bit information word when combined with predetermined extra bits and when the fixed number of successive preceding bits have a predetermined value. The use of the memory enables a simple realization of the channel encoder for example, the (m-n) bits word "O" may be assumed to have been added to the n-bit information word, while a "O" is also assumed to have been applied to the precoder as the bit of the m-bit code word supplied thereby. Using these two assumptions, the DS values in the memory are defined, the first assumption being corrected, if necessary, by the feedback via the DSV counter, the second assumption being corrected, if necessary, by the feedback of the last bit of the last m-bit code word actually supplied by the precoder. Thus, the memory is filled in advance so that, when the device is in operation, an as much as possible DC-free m-bit code word is supplied on the output of the channel encoder, with correction possibilities for each assumption in the determination of the DS values. An embodiment of the channel encoder according to the invention is characterized in that, there is just one extra bit ( m-n=1 ) and the preceding code bit is only a last code bit, the function corresponding to an exclusive OR of the respective intermediate bit and the last code bit. When a precoder having a (1+D)⁻¹ is used only the last bit of the preceding m-bit intermediate code word has to be taken into account. An embodiment of the channel encoder according to the invention is characterized in that a single bit data output (X1) of the memory, for carrying a sign signal indicative of the sign of the change in digital sum variation, is coupled as extra bit to the precoder via a logic (25,26), for inverting the sign signal if either the last code bit differs from the predetermined value or (exclusively) the sign of the digital sum variation determined by the counter agrees with the indicated sign. An embodiment of the channel encoder according to the invention is characterized in that said extra bit selection means comprises a zero detector, for detecting n-bit information words consisting of only zero bits, an output of the zero detector being coupled to the logic circuit for forcing the extra bit to a logic one upon zero detection. In this way, it is assured that no intermediate words on only zeroes are formed, thus assuring run length limitation. An embodiment of the channel encoder according to the invention is characterized in that there are two extra bits ( m-n=2 ) and that the preceding code bit is the one before fast preceding code bit, the function corresponding to an exclusive OR of the respective intermediate bit and the before last code bit. When m-n=2 , use is made of a precoder having a transfer function (1+D²)⁻¹, only the last two bits of the preceding m-bit code word being used for determining the 2-bit encoding signal to be added to the n-bit information word. In that case the memory circuit again includes a memory in which digital sum values (DS) are stored which have been determined by making assumptions analogous to those used in the former case where m-n=1 . An embodiment of the channel encoder according to the invention is characterized in that the extra bit selection means comprises an even and an odd submemory (33, 34), with address inputs coupled to even bits and odd bits of the received information words respectively, the even and the odd submemories storing an even and an odd digital sum indication respectively, the odd digital sum indication being indicative of a change in the digital sum variation in the counter after precoding addressed odd bits combined with a predetermined odd extra bit following an odd preceding code bit of predetermined value, the even digital sum indication being indicative of a change in the digital sum variation in the counter after precoding addressed even bits combined with a predetermined even extra bit following an even preceding code bit of predetermined value, data outputs of the even and odd submemories being coupled to a combining memory. By using separate memories for even and odd bits storage space is saved in storing a digital sum indication. An embodiment of the channel encoder according to the invention is characterized in that even and an odd bit data outputs (Xa, Xb) of the combining memory are coupled as even and odd extra bits respectively to the precoder via a logic circuit (36, 37), for inverting a bit signal (Xa', Xb') on the bit data output in response to the last two code bits (Xm, Xm-1) derived from the preceding intermediate word. Using precoders of this kind, a channel encoder can be obtained which supplies a mainly DC-free and RLL code, in which error propagation is prevented, in which the output signal of the relevant apparatus can be rendered independent of the polarity of the connection of the write head and/or read head, and in which a limited bandwidth can be realized, so that only little noise occurs. Further details of the channel encoder in accordance with the invention are given in the dependent Claims. A number of embodiments in accordance with the invention will be described in detail hereinafter with reference to the accompanying diagrammatic drawings. Therein: Fig. 1 shows a block diagram of the part of a digital magnetic recording and playback apparatus which is important for the description of a channel encoder; Fig. 2 shows a number of diagrams in support of the description of the operation of the circuit shown in fig. 1; Fig. 3 shows three simplified circuits for illustrating the use of a precoder in a channel encoder; Fig. 4 shows an embodiment of a channel encoder in accordance with the invention; Fig. 5 shows a second embodiment of a channel encoder in accordance with the invention; and Figs. 6a and 6b show tables for the memory circuit in the second embodiment of the channel encoder. Fig. 1 shows a block diagram of the part of a digital magnetic recording and playback apparatus which is of importance for the description of the channel encoder. The channel encoder is denoted by the reference numeral 1 in fig. 1: in the encoder an n-bit data stream is encoded so that an m-bit, mainly DC-free and run length limited (RLL) code is obtained, where m > n. The DC level in the encoded bit stream is determined by the difference between the number of "ones" and "zeroes" in this bit stream; the run length is determined by the distance between the transitions in the encoded bit stream. The encoded bit stream, being the write current, is applied, via a write amplifier (not shown) and possibly a (rotating) transformer (not shown), to the write head 2 in order to record the encoded bit stream on a medium. During playback, this bit stream is read by means of the read head 3; the signal recorded on the medium is then differentiated in time. The differentiated signal is applied to a filter unit 4 in which, ignoring high-frequency losses, a more or less flat frequency response curve is obtained, resulting in δ-pulse shaped signals at the transitions in the signal read, after which such an output signal is supplied, using a Nyquist pulse shaping filter, that the detection in the detection unit 5 produces a signal which corresponds to the differentiated write current. A restored bit stream is further derived from this signal in the detector. This bit stream should subsequently be decoded again; this operation takes place in the decoder 6, after which the n-bit data stream has been obtained again. The reference A in fig. 2 denotes the write current to be applied to the write head; the reference B denotes the δ-pulse shaped signals obtained in the filter unit 4; the reference C denotes the signal obtained after Nyquist pulse shaping and supplied by the filter unit 4; the reference D denotes the detected output signal corresponding to the differentiated write current; and the reference E denotes the restored encoded bit stream. In as far as is relevant, the described circuit can be simplified to the circuit shown in fig. 3a, from a digital and time discrete point of view. Upon playback, differentiation of the bit stream occurs, implying a multiplication by (1 + D), where D represents the delay operator; this operation is indicated by the functional network 7. The restoration of the encoded bit stream takes place in the detector, implying a multiplication by (1+D)⁻¹; this operation is indicated by the functional network 8. When a transition is missed in the detector during playback or when the write head and/or the read head is connected with the wrong polarity, error propagation occurs. When the encoded bit stream is multiplied by (1+D)⁻¹ at the recording side where not errors have occurred yet, instead of in the detector at the playback side, the detector receives directly the original encoded bit stream instead of the signal corresponding to the differentiated write current. This situation is shown in fig. 3b. In this figure the functional network 8 is inserted in the recording transmission channel. In this configuration the functional network 8 forms a so-called precoder which is connected directly to the channel encoder 1 or is integrated therein. In the figures 3a and 3b, each of the functional networks 7 and 8 is composed of a delay element 9, 10, respectively, and an EXCLUSIVE-OR gate 11, 12, respectively. The delay time T corresponds to one bit cell of the bit stream. In the configuration shown in fig. 3b, the missing of a transition does not lead to error propagation and the polarity of the signal read with respect to the write current is no longer of importance. This will be explained on the basis of an example. For example, when the bit series 001100101 is applied to the network 8 in fig. 3b, the write current will be formed by the bit series 001000110 if the delay element 10 initially supplies the bit value 0; if the delay element 10 initially supplies the bit value 1, the write current will be formed by the bit series 110111001. Upon differentiation in the network 7, the bit series which are the inverse of one another, the bit series 001000110 preceded by the bit value 0 and the bit series 110111001 preceded by the bit value 1, are converted into the same bit series 001100101. In other words, the polarity of the bit current read with respect to the write current is no longer important. The missing of a transition during the detection of the signal differentiated in the read head will no longer cause error propagation. Fig. 3c shows a circuit whichis analogous to that shown in fig. 3b. Therein, the functional network 13, consisting of two delay elements 14 and 15 and an EXCLUSIVE-OR gate 16 acts as a precoder, the functional network 17 which is composed of two delay elements 18 and 19 and an EXCLUSIVE-OR gate 20 indicating the differentiation taking place in the playback channel. In this case the write current is multiplied by (1+D²)⁻¹, a multiplication by (1+D²) taking place in the playback channel. When, for example the bit series 001100101 is applied to the network 13 in fig. 3c, the write current will be formed by the bit series 001111011 if the delay elements 14, 15 initially supply the bit values 00; if the delay elements 14, 15 initially supply the bit values 10, the write current will be formed by the bit series 011010001; if the delay elements 14, 15 initially supply the bit values 01, the write current will be formed by the bit series 100101110; if the delay elements 14, 15 initially supply the bit values 11, the write current will be formed by the bit series 110000100. Two by two, these bit series are the inverse of one another. Upon differentiation in the network 17, all four bit series, each series with the associated preceding two bit values, is converted into the same bit series 001100101. The circuit shown in fig. 3c not only has the same attractive properties as the circuit shown in fig. 3b, but offers the additional advantage that the bandwidth is smaller so that the noise is less. Fig. 4 shows a first embodiment of a channel encoder in accordance with the invention. The construction and operation of this channel encoder will be described, by way of example, on the basis of an 8 → 9 channel encoder, which means that an 8-bit information word is converted into a 9-bit code word mainly DC-free and RLL. However, this construction is in principle suitable for any n → n+1 channel encoder. The 8-bit information word to be encoded is written into a register 21. From this register these 8 bits are applied in parallel to a register cum parallel-series converter 22 as well as to a memory circuit 23. In the present embodiment, this memory circuit comprises an 8 → 1 PROM 24 in which there are stored the digital sum values DS of the 9-bit words which have been composed by appending each time a 1-bit encoding signal of predetermined fixed value, in this case, for example 0, to the 8-bit information word and where the combination thus obtained has passed the precoder connected thereto via the register cum parallel-series converter 22, and where a last bit of fixed value, in this case, for example 0, of the preceding 9-bit code word supplied by the precoder 8 is applied to the precoder 8. For example, when the 8-bit word 01100101 is applied to the PROM 24, a DS value -3 is addressed in this memory. This value has been determined in advance as follows: a 9-bit word is assumed by assuming the 1-bit encoding signal 0 to have been appended, i.e. 001100101; when this 9-bit word is assumed to have passed through the precoder 8, it also being assumed that the delay element 10 initially supplies the bit value 0, the precoder would supply the 9-bit word 001000110 and, because the digital sum value DS of a word is to be understood to mean the difference between the number of "ones" and the number of "zeroes" of this word, in this case DS = -3. Thus, for any feasible 8-bit data word a DS value is present in the PROM 24. The following holds for the signal x₁ to be output by PROM 24: x₁ = 0 if DS ≧ 0, and x₁ = 1 if DS < 0. The assumptions built into the signal x₁, however, may require correction. To this end, the memory circuit 23 also comprises two EXCLUSIVE-OR gates 25 and 26. The EXCLUSIVE-OR gate 25 not only reacts to the signal x₁ from the 8 → 1 PROM 24, but also to the signal x₂; this is the last bit of the last 9-bit code supplied by the precoder 8. The EXCLUSIVE-OR gate 26 reacts not only to the output signal of the EXCLUSIVE-OR gate 25, but also to the output signal x₃ of a DSV counter 27; this is the counter in which the digital sum variation DSV of the encoded bit word each time obtained thus far is determined. To this end, the DSV counter 27 each time receives the 9-bit code from the precoder 8. The output signal x₃ of the DSV counter 27 is 1 if the digital sum variation DSV is larger than or equal to 0; x₃ = 0 if DSV is smaller than 0. The transfer function of the logic circuit formed by the two EXCLUSIVE-OR gates 25 and 26 can be expressed in Boolean form as follows: y = x₁x₂x₃ + x₁ x ₂ x ₃ + x ₁x₂ x ₃ + x ₁ x ₂x₃ and determined the bit which is added to the 8-bit information word in order to obtain a 9-bit encoded word. The embodiment shown in fig. 4 also comprises a further logic circuit 28 and an OR gate 29. The 8-bit information word is applied to the logic circuit 28; in reaction thereto, this logic circuit supplies a zero detection signal "1" if the 8-bit information word consists only of "zeroes". This zero detection signal as well as the cited signal y is applied to the OR-gate 29. The output signal of the OR-gate forms the 1-bit encoding signal to be added to the 8-bit information word. Thus, an excessive run length is prevented. Regardless of the DC deviation of the encoded bit stream obtained thus far, a 1 is added to an 8-bit word which consists only of "zeroes", so that at least one transition occurs per 9-bit word in the encoded bit stream. It is assumed , by way of example, that the word 01100101 is supplied as the 8-bit data stream. As has already been demonstrated, for this word DS = -3, so that x₁ = 1. Four cases then occur: For the DSV of the encoded bit stream obtained thus far it holds good that DSV < 0, so x₃ = 0, while the last bit x₂ output by the precoder is 0. In that case y = 1. The 9-bit signal applied to the precoder is then 101100101. In response thereto, the precoder supplies the signal 110111001. Upon differentiation during playback, this signal produces the bit series 101100101, while the original word 01100101 is obtained again by omission of the bit added during recording. The value of DSV which was negative is now incremented by the digital sum value of the 9 bits supplied by the precoder, in this example +3. For the DSV of the encoded bit stream obtained thus far, DSV < 0, so x₃ = 0, while the last bit x₂ supplied by the precoder is 1. In that case y = 0. The 9-bit word applied to the precoder is then 001100101. In response thereto, the precoder supplies the word 110111001. Upon differentiation during playback, this signal produces the bit series 001100101, while the original word 01100101 is obtained again by omission of the bit added during recording. The value of DSV which was negative is increased again by +3. For the DSV of the encoded bit stream obtained thus far, DSV ≧ 0, so x₃ = 1, while the last bit x₂ supplied by the precoder is 0. In that case y = 0. The 9-bit word applied to the precoder is then 001100101. In response thereto, the precoder supplies the word 001000110. Upon differentiation, this word forms the bit series 001100101, while the original signal is obtained again by omission of the previously added bit. The DSV is increased by -3. For the DSV of the encoded bit stream obtained thus far DSV ≧ 0, so x₃ = 1, while the last bit x₂ supplied by the precoder is 1. In that case y = 1. The 9-bit word applied to the precoder is then 101100101. In response thereto, the precoder supplies the word 001000110. Upon differentiation, this word form the bit series 101100101, while the original word is obtained again by omission of the previously added bit. The DSV is increased again by -3. When a series of 8-bit words is applied to the channel encoder, the DSV will fluctuate around 0 as much as possible in order to obtain a mainly DC-free code. It is assumed that, starting with the initial situation DSV = 0, so x₃ = 1 and x₂ = 0, the 8-bit words 11110000, 00000000, 00011111, 01100101 are successively applied. If a 0 were added to the second word and the third word, 17 "zeroes" would succeed one another, so that an excessive run length would occur. Therefore, this situation is avoided by the circuit shown. After application of the first word to the PROM 24, for which DS = -5, the signal x₁ = 1 is output. For x₂, x₃ = 0, 1 this results in y = 0. 011110000 is applied to the precoder. In response thereto, the precoder supplies the bit series 010100000, so that DSV assumes the value -5 and x₃ becomes 0; x₂ remains 0. For the second word, the circuit 28 outputs the zero detection signal 1, so that the 9-bit word applied to the precoder becomes 100000000. In response thereto, the precoder supplies the word 111111111, so that DSV is increased by +9 and assumes the value +4. Furthermore, x₂, x₃ = 1, 1. For the third word, DS = -3, so that x₁ = 1. In that case y = 1; thus, between the second word and the third word a 1 is added, so that the run length remains limited to 9 in this case. After application of the bit series 100011111 to the precoder, the precoder supplies the word 000010101, so that DSV is increased by -3 and assumes the value +1. After the third word, x₂, x₃ = 1, 1. After application of the fourth word, for which DS = -3 and hence x₁ = 1, y will become 1 and the bit series 101100101 will be applied to the precoder; in response thereto, the precoder supplies the word 001000110, so that DSV changes from +1 to -2. Fig. 5 shows a second embodiment of a channel encoder in accordance with the invention. The construction and operation of this channel encoder will be described, by way of example, on the basis of an 8 → 10 channel encoder, which means that an 8-bit information word is converted into a 10-bit mainly DC-free RLL code. This embodiment, however, is in principle also suitable for any n → n+2 channel encoder. The 8-bit information word to be encoded is written into a register 30. From this register the 8 bits are applied in parallel to a register cum parallel/series converter 31 as well as to a memory circuit 32. The memory circuit includes a PROM for outputting two bits x a , x b on the basis of the applied 8-bit data and the in this case 3-bit encoded DSV output signal. Thus, use can be made of an 11 → 2 PROM. In order to save storage space, however, the present embodiment utilizes a first sub-memory 33 which responds to the even bits of the 8-bit information word by supplying a 2-bit partial digital sum value DS a , and a second sub-memory 34 which responds to the odd bits of the 8-bit information word by supplying a 2-bit partial digital sum value DS b ; there is also provided a third sub-memory 35 in which said bits x a , x b are formed from the partial digital sum values DS a and DS b and from the 3-bit DSV value. The present embodiment, therefore, utilizes two 4 → 2 PROMs and one 7 → 2 PROM. The partial digital sum values DS a and DS b are determined in the same way as the digital sum values DS in the first embodiment. This means that the sub-memories 33 and 34 store the digital sum values DS a and DS b , respectively, of the (in the present case) 5-bit words which are assumed to have been composed by assuming a bit x′ a = 0 and a bit x′ b = 0 to have been added to the 4-bit words applied to the sub-memories 33 and 34, respectively, and by assuming the assumed combination thus obtained to have passed the precoder 13, the last bits x m-1 = 0 and x m = 0 of the 10-bit code last supplied by the precoder being assumed to have been applied to the precoder. For example, when the 8-bit information word 01100101 is output by the register 30, the sub-word 0100 is applied to the sub-memory 33; thus, a digital sum value DS a = +1 is addressed which is determined in advance as follows: the bit X′ a = 0 is assumed to be added, so that the word 00100 is assumed to have been applied to the precoder; for x m = 0, the precoder would then output the word 00111 having a digital sum value DS a = +1. The sub-word 1011 is applied to the sub-memory 34; thus, a digital sum value DS b = +1 is addressed which is determined in advance as follows: the bit x′ b = 0 is assumed to have been added, so that the word 01011 is assumed to have been applied to the precoder; for x m-1 = 0, the precoder would then output the word 01101 having a digital sum value DS b = +1. In the present embodiment, n is even so that the sub-memories 33 and 34 have the same capacity; evidently, this will not be the case when n is odd. The memory circuit 32 furthermore comprises two EXCLUSIVE-OR gates 36 and 37 which respond to the signals x a , x b and the signals x m-1 and x m originating from the precoder 13, respectively, by supplying the bits x′ a and x′ b , respectively, to be added, so that a 10-bit word is applied to the decoder 13 from the register cum parallel/series converter 31. The precoder to be used herein is of the type shown in fig. 3c. The bits x m and x m-1 form each time the last two bits of the last word supplied by this precoder. The 10-bit code of the precoder is also applied to the DSV counter 38 which applies the DSV value, encoded in 3 bits, to the memory circuit 32. The memory circuit of this embodiment is again constructed so that the PROMs are filled so that the encoded bit stream has a minimum DSV and a limited run length. Fig. 6a shows an example of a table contained in the PROMs 33 and 34. For the 4-bit input signal of these PROMs, the DS values -5, -3, ... -1 hold good for the increasing decimal values 0, 1, 2, ... 15. These DS values have been determined in the described manner. For the 2-bit signal DS a (or DS b ) supplied, it holds that DS a (or DS b ) = 1, 1 if DS = +3; DS a (or DS b ) = 1, 0 if DS = +1; DS a (or DS b ) = 0, 1 if DS = -1, and DS a (or DS b ) = 0, 0 if DS = -3 or -5. Fig. 6b shows an example of a table contained in thePROM 35. This memory receives the 2-bit signals DS a and DS b and also the 3-bit DSV values. For 10-bit words the DSV counter 38 supplies an output signal 111 if DSV ≧ +6, 110 if DSV = +4, 101 if DSV = +2, 100 if DSV = 0, 001 if DSV = -2, 010 if DSV = -4, and 011 if DSV ≦ -6; the value 000 is not used in this case. In the present embodiment DSV remains within the limits [4, -4], so that the table of fig. 6b contains only the bits x a , x b for the DSV values +4, +2, 0, -2, -4 and the DS a and DS b values 00, 01, 10 and 11. Assumed that, using the initial situation DSV = 0 and x m , x m-1 = 0, 0, the 8-bit words 11110000, 00000000, 00011111 and 00100101 are successively supplied again. The bit groups 1100, 0000, 0011 and 0100 are then successively applied to the PROM 33, so that DS a successively assumes the values 00, 00, 00 and 10. The bit groups 1100, 0000, 0111 and 0011 are applied to the PROM 34, so that DS b successively assumes the values 00, 00, 01 and 00. When the first 8-bit word is applied, DSV = 0, so that x a , x b = 1, 0 and x′ a , x′ b = 1,0. The bit series 1011110000 is then applied to the precoder; in response thereto, the precoder supplies the signal 1001101010, so that x m , x m-1 = 0, 1 and DSV remains 0. When the second 8-bit word has been applied, x a , x b remains 1, 0 and x′ a , x′ b = 1, 1. The bit series 1100000000 is then applied to the precoder; in response thereto, the precoder supplies the signal 0101010101, so that x m , x m-1 = 1, 0 and DSV remains 0. When the third 8-bit word has been applied, x a , x b remains 1, 0 and x′ a , x′ b = 0, 0. The bit series 0000011111 is then applied to the precoder, which then supplies the signal 0101001100, so that x m , x m-1 = 0, 0 and DSV changes from 0 to -2. When the fourth 8-bit word has been applied, x a , x b = 0, 1 and x′ a , x′ b = 0, 1. The bit series 0100100101 is then applied to the precoder; in response thereto, the precoder supplies the signal 0101111011 so that x m , x m-1 = 1, 1 and DSV changes from -2 to +2. It will be apparent from this example that DSV remains between the limits [+4, -4] and hence that the DC value remains minimum; the bits 11 are added between the first and the second word so that the run length remains limited. In determining the contents of the sub-memories, the criterion that the DSV must remain minimum as well as the criterion that the run length must remain limited has been taken into account. When the deviation of DSV from 0 is excessive, the first criterion will be decisive; when the run length becomes too large, the second criterion will be decisive. In the second embodiment, utilizing a precoder having a transfer function (1 + D²)⁻¹, 2 bits were added to the n-bit data stream. For a 8 → 10 conversion this implies a 25 % increase in channel bits. If this increase is to be limited, an 8 → 9 conversion may be adopted; however, if it is desirable to retain the properties of the precoder used in the second embodiment, use can be made of a precoder having the transfer function (1 + D)⁻¹, be it that interleaving with an interleave factor 2 must be used. In the described embodiments of the channel encoder in accordance with the invention the digital sum variation of the encoded bit stream is readjusted to 0 in order to obtain a signal which is as DC-free as possible. However, it may also to be desirable to introduce so-called tracking frequencies into the encoded bit stream. This can be realized by readjusting the digital sum variation of the encoded bit stream to alternately a positive value and a negative value instead of to 0. To this end, for example the memory circuit can be constructed so as to be double, so that the desired frequency to be inserted into the encoded bit stream can be used to switch between these two memory circuits. The PROMs of the relevant memory circuits are filled so that bits to be added are obtained which readjust the encoded bit stream to the desired positive and negative value. The digital sum variation each time found can also be periodically corrected.

Claims: Channel encoder for encoding received n-bit information words into a stream of code bits, the stream being mainly DC free and run length limited, the encoder comprising a precoder (8; 13), a precoded output signal of which corresponds with the stream of code bits, an input of said precoder being coupled for serially receiving m-bit intermediate words, the intermediate words comprising the received n-bit words combined with one or more (m-n) extra bits, the extra bits being supplied to the precoder from extra bit selection means (23, 29; 32), selecting the extra bits for keeping a digital sum variation of the stream of code bits near a currently desired value and/or limiting the run length of the stream, said extra bit selection means having a digital sum prediction input for receiving the n-bit information words and a signal from a counter (27; 38) the counter being arranged for determining a digital sum variation corresponding with the stream of code bits, characterized in that the precoder has a transfer function in which each code bit of the serially output stream of code bits is a function of a respective bit of the serially input intermediate word and of a preceding code bit, preceding the said code bit by a fixed number of successive preceding code bits, the counter and a further input of said extra bit selection means receiving the stream of code bits output from the precoder, the extra bit selection of a new intermediate word being also in response to at least the last code bit derived from the preceding intermediate word. Channel encoder according to Claim 1, characterized in that the extra bit selection means comprises a memory (24), the received n-bit words being coupled to an address input, the memory storing a digital sum indication, indicative of the change to be obtained in digital sum variation in the counter after precoding an addressed n-bit information word when combined with predetermined extra bits and when the fixed number of successive preceding bits have a predetermined value. Channel encoder according to Claim 1, characterized in that there is just one extra bit ( m-n=1 ) and the preceding code bit is only a last code bit, the function corresponding to an exclusive OR of the respective intermediate bit and the last code bit. Channel encoder according to Claim 3, characterized in that a single bit data output (X1) of the memory, for carrying a sign signal indicative of the sign of the change in digital sum variation, is coupled as extra bit to the precoder via a logic (25, 26), for inverting the sign signal if either the last code bit differs from the predetermined value or (exclusively) the sign of the digital sum variation determined by the counter agrees with the indicated sign. Channel encoder according to Claim 4, characterized in that said extra bit selection means comprises a zero detector, for detecting n-bit information words consisting of only zero bits, output of the zero detector being coupled to the logic circuit for forcing the extra bit to a logic one upon zero detection. Channel encoder according to Claim 1, characterized in that there are two extra bits ( m-n=2 ) and that the preceding code bit is the second last preceding code bit, the function corresponding to an exclusive OR of the respective intermediate bit and the second last code bit. Channel encoder according to Claim 6, characterized in that the extra bit selection means comprises an even and an odd submemory (33, 34), with address inputs coupled to even bits and odd bits of the received information words respectively, the even and the odd submemories storing an even and an odd digital sum indication respectively, the odd digital sum indication being indicative of a change in the digital sum variation in the counter after precoding addressed odd bits combined with a predetermined odd extra bit following an odd preceding bit of predetermined value, the even digital sum indication being indicative of a change in the digital sum variation in the counter after precoding addressed even bits combined with a predetermined even extra bit following an even preceding code bit of predetermined value, data outputs of the even and odd submemories being coupled to a combining memory. Channel encoder according to Claim 7, characterized in that even and an odd bit data outputs (Xa, Xb) of the combining memory are coupled as even and odd extra bits respectively to the precoder via a logic circuit (36, 37), for inverting a bit signal (Xa', Xb') on the bit data output in response to the last two code bits (Xm, Xm-1) derived from the preceding intermediate word.

Inventors: VAN GESTEL, WILHELMUS JACOBUS
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: G11B20
IPC codes: H03M7, G11B20, H03M5