SEMAPHORE CIRCUIT FOR SHARED MEMORY CELLS

Abstract: A semaphore circuit is disclosed which employs a pair of storage elements; an arbitrator, which is driven by the storage elements; and another pair of storage elements, which are driven by the arbitrator. The arbitrator includes a first and a second NOR gate. One of the inputs of the first NOR gate is connected to the output of the second NOR gate one of the inputs of which is connected to the output of the first NOR gate.

Description: The present invention relates to a semaphore system as recited in the preamble of claim 1. In a known semaphore system of that kind (US-A-4,594,657) an arbitrator and four storage elements (flip-flops) are used to produce a binary semaphore signal indicating whether or not the semaphore is owned and a binary ownership signal indicating which of the two users (asynchronous microcomuters) previously owned the owner ship flip-flop. A read signal loads the semaphore signal and the ownership signal into flip-flops whose outputs are applied to the respective user data bus. Often times it is useful to share resources, such as, for example, buses, peripherals, and/or memory cells. However, in some situations, it is also necessary to provide some restrictions on that use. One method of limiting the use of a resource is by means of a "software semaphore" of the type which was disclosed by E.W. Dijkstra in the "Communications of ACM" 11,5 of May 1968 on pages 341-346. As an example of such a (simple, binary) semaphore, consider the situation in which it is desired that the use of a resource be shared by two processors, but access to the resource be limited to one processor at a time. A certain cell (location) in memory, which is accessible (shared) by both of the processors, could be designated for use in controlling access to the resource. A certain number (zero, for example) could be stored in the memory cell when the resource is not in use (available); and, another number (one, for example) could be stored in the memory cell when the resource is in use (busy). Before a processor is allowed to use the resource, the processor could be required to do the following tasks. First, the processor could be required to "read" from the memory cell (to obtain the number stored therein). Second, the processor could be required to "test" the number read (to determine its value, whether it is a zero or a one). Third, if the results of the test indicate that processor could be required to "write" (a one) into the memory cell to indicate that the resource is in use. (If the results of the test indicate that the resource is in use (the number read is a one), the processor could be required to continue reading and testing until the resource is not in use (the number read is a zero).) Finally, when the processor is through with the resource, the processor could be required to "write" (a zero) into the memory cell to indicate that the resource is no longer in use. Unfortunately, a period of time elapses between the time when one of the processors reads (a zero) from the memory cell and the time when that processor writes (a one) into the memory cell. During this period of time, the other processor could read from the memory cell and conclude that the resource is not in use, and, thus, available. As a consequence, both processors could attempt to use the resource at the same time. (The period of time can be reduced, but not eliminated, if the order of the tasks is changed to require that the processor write before testing.) Memory devices of the type which are designated IDT7132 by Integrated Device Technology Inc., AMD2130 by Advanced Micro Devices Inc., and 5132 by Vitalic are suitable for shared use by two processors. The IDT7132 device employs what is referred to in the specification sheet for the device as an "arbitration circuit", a circuit for preventing both processors from using the same memory cell at the same time. Included in the arbitration circuit is what is referred to herein as an "arbitrator", specifically, a first and a second NOR gate. One of the inputs of the first NOR gate is connected to the output of the second NOR gate one of the inputs of which is connected to the output of the first NOR gate. In the arbitration circuit, signals developed by the NOR gates are used to develop a pair of (active low) "busy" signals. The busy signals are used to make one of two processors wait while the other processor is using the same memory cell. Unfortunately, use of the above mentioned memory device and/or arbitration circuit does not solve the above mentioned problem with the software semaphore. Also, for proper operation, the above mentioned arbitration circuit requires the use of processors which have wait capability. Further, the above mentioned memory device and/or arbitration circuit only prevents the simultaneous use of the same memory cell. Some applications require that the use, by a processor, of a series of memory cells be uninterrupted. In some of these applications timing is critical. For example, once a processor has started reading data from a series of memory cells and writing the data onto a disk or has started reading data from a disk and writing the data into a series of memory cells, it is important that the processor not be interrupted (since the disk won't wait). In other applications it is important that the use of a series of memory cells by a processor be uninterrupted so as to prevent the use of incomplete and/or erroneous data. As an example, consider video displays in which a master processor generates a picture layout in the form of a display list and a slave processor reads the display list, interprets the list, and generates a raster image in a display buffer. As the raster image in the display buffer is put onto a video screen, the display buffer is wiped clean (in order to achieve high speed animation). As a consequence, the slave processor must continually update the display buffer. To prevent the slave processor from using an incomplete display list, two display lists are used each stored in a separate series of memory cells. While the slave processor is using one display list to generate the raster image in the display buffer, over and over again, the master processor is generating and/or updating the other display list. Thus, a need exists for an unambiguous semaphore suitable for insuring the uninterrupted use, by a processor, of a series of memory cells. SUMMARY OF THE PRESENT INVENTION It is therefore the primary object of the present invention as claimed in claim 1 to provide an unambiguous semaphore suitable for use in limiting access to a resource. Another object of the present invention is to provide a semaphore circuit which does not require the use of processors which have wait capability. Another object of the present invention is to provide a semaphore circuit suitable for integration with other semaphore circuits, multiplexing circuits, and memory cells all within a single device. Briefly, the presently preferred embodiment of the present invention employs a pair of storage elements; an arbitrator, which is driven by the storage elements; and another pair of storage elements, which are driven by the arbitrator. The arbitrator includes a first and a second NOR gate. One of the inputs of the first NOR gate is connected to the output of the second NOR gate one of the inputs of which is connected to the output of the first NOR gate. The ability to provide an unambiguous semaphore suitable for use in limiting access to a resource is the principal advantage of the present invention. Another advantage of the present invention is the ability it affords to provide a semaphore circuit which does not require the use of processors which have wait capability. Another advantage of the present invention is the ability it affords to provide a semaphore circuit suitable for integration with other semaphore circuits, multiplexing circuits, and memory cells all within a single device. These and other objects and advantages of the present invention will no doubt be obvious to those skilled in the art after having read the following detailed description of the presently preferred embodiment which is illustrated in the figure of the drawing. IN THE DRAWING FIGURE 1 is a combined schematic and block diagram of the presently preferred embodiment in accordance with the present invention of eight semaphore circuits and their associated pair of multiplexing circuits. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In the presently preferred embodiment of the invention, eight similar semaphore circuits, a pair of similar multiplexing circuits, and 2K by 8 memory cells are all integrated into a single device using CMOS technology. One of the semaphore circuits is illustrated in detail in FIGURE 1 of the drawing generally designated by the number 10. The additional semaphore circuits are represented by a block which is designated 12. The multiplexing circuits are shown, one represented by a block (MUX) which is designated 14 and the other illustrated in detail generally designated 16. Semaphore circuit 10 is shown to employ as principal components four storage elements, which are respectively designated 20, 22, 24, and 26, and an arbitrator, which is generally designated 28. Storage element 20 is configured with the data (D) input connected to a line 30, the clock input connected to a line 32, and the data (Y) output connected to a line 34. For convenience, signals received from the first user are termed "first and second write clocking signals" (on line 32) marking "first and second write times" and "a first data input" (on line 30). Similarly, storage element 22 is configured with the data input connected to a line 40, the clock input connected to a line 42, and the data output connected to a line 44. For convenience, signals received from the second user are termed "third and fourth write clocking signals" (on line 42) marking "third and fourth write times" and "a second data input" (on line 40). In the presently preferred embodiment, storage elements 20 and 22 are implemented as (low) level-triggered D-type registers, i.e. "low" is the active state of the first and second data input signals. In another embodiment, registers of the type which are commonly designated 7474 are used. Arbitrator 28 includes a pair of two-input NOR gates, which are respectively designated 50 and 52. One of the inputs of NOR gate 50 is connected by a line 56 to the output of NOR gate 52 one of the inputs of which is connected by a line 54 to the output of NOR gate 50. The other input of NOR gate 50 is coupled by line 34 to the data output of storage element 20; and, similarly, the other input of NOR gate 52 is coupled by line 44 to the data output of storage element 22. Finally, the output of NOR gate 50 is additionally connected by line 54 to the input of an inverter 60 the output of which is connected to a line 64; and, the output of NOR gate 52 is additionally connected by line 56 to the input of an inverter 66 the output of which is connected to a line 68. Storage element 24 is configured with the data input connected to line 64, the clock input connected to a line 70, and the data output connected to a line 72. Similarly, storage element 26 is configured with the data input connected to line 68, the clock input connected to a line 74, and the data output connected to a line 76. In the presently preferred embodiment, storage elements 24 and 26 are implemented as latches. In another embodiment, latches of the type which are commonly designated 74373 are used. As previously indicated, block 12 represents the seven additional semaphore circuits which are similar to semaphore circuit 10. Also, as previously indicated, block 14 represent the multiplexing circuit which is similar to multiplexing circuit 16. Multiplexing circuit 16 is shown to employ a two-input negative-input NAND gate (OR gate) 100, a two-input negative input NAND gate (OR gate) 102, and a three-line-to-eight-line decoder 104, all for developing a signal (the third or the fourth write clocking signal) for driving the clock input of storage element 22 (marking the third or the fourth write time). Gate 100 is configured with the gate output coupled to the clock input of storage element 22 by line 42, with one of the gate inputs connected to a line 110, and with the other gate input connected to a line 112. Gate 102 is configured with the gate output connected to line 110 and with each of the two gate inputs coupled by a respective one of two lines, which are designated 114 and 118, to a respective one of two pads, to receive a respective one of two, externally developed, semaphore circuit 10 write enabling signals. Specifically, the gate 102 is driven by a read/write signal and an (active low) semaphore signal. The eight decoder 104 outputs are connected, the lowest order output to line 112 and the highest order output to a line 120. The three inputs of decoder 104 are coupled by a respective one of three lines, which are designated 122, 124, and 126, to a respective one of three pads, to receive a respective one of three, externally developed, semaphore circuit 10 addressing signals. For developing a signal for driving the clock input of storage element 26, multiplexer 16 employs a two-input negative-input AND gate (NOR gate) 130. Gate 130 is configured with the gate output coupled by line 74 to the clock input of storage element 26, with one of the gate inputs connected to line 118, and with the other gate input coupled by a line 132 to a pad for receiving an externally developed (active low) semaphore circuit 10 output enabling signal. A buffer 140 is employed configured with the buffer output coupled by line 40 to the data input of storage element 22 and with the buffer input coupled by a line 142 to a pad to couple an externally developed semaphore circuit 10 input data signal to the storage element. For coupling a signal developed at the data output of storage element 26 to the pad connected to line 142, multiplexer 16 employs an eight-line-to-one-line multiplexer (MUX) 150, a two-line-to-one-line multiplexer (MUX) 152, and a buffer 154. The eight data inputs of multiplexer 150 are connected, the lowest order input to line 76 and the highest order input to a line 160. The three select (control) inputs of multiplexer 150 are connected each to a respective one of the three lines 122, 124, and 126; and, the data output of the multiplexer is connected to a line 162. Multiplexer 152 is configured with one of the data inputs connected to line 162, the select (control) input connected to line 118, and the data output connected to a line 164. The other data input of multiplexer 152 is connected to a line 166 to receive a signal developed by the memory cells which, for clarity, are not shown. Finally, buffer 154 is configured with the buffer input connected to line 164, the buffer tri-state output controlling input connected to line 132, and the buffer output connected to a line 142. Additionally, for semaphore circuit 12, multiplexer 16 employs a another two-input negative-input NAND gate (OR gate) 170, another two-line-to-one-line multiplexer (MUX) 174, and another buffer 176. Gate 170 is configured with the gate output coupled by a line 180 to the clock input of the corresponding storage element of semaphore circuit 12, with one of the gate inputs connected to line 110, and with the other gate input connected to line 120. Multiplexer 174 is configured with one of the data inputs connected to line 162, with the select (control) input connected to line 118, and with the data output connected to a line 186. Finally, buffer 176 is configured with the buffer input connected to line 186, the buffer tri-state output controlling input connected to line 132, and the buffer output coupled by a line 188 to a pad. Operationally, before a processor is allowed to use a resource, the processor is required to do the following tasks. First, the processor is required to "write" a zero as the first or second data input signal having an active state into the appropriate storage element. In other words, before the processor which is connected to multiplexer 16 is allowed to use the resource, the processor is required to generate signals on the pads that are connected to the multiplexer such that a low-logic-level signal (a zero) is developed on line 40 (as the second data input signal having an active state). Simultaneously, the processor is required to generate signals such that a signal having a low logic level (the third write clocking signal) is generated on line 42, developing a signal having a low logic level (as the active state) on line 44. Second, the processor is required to "read" from the appropriate storage element (24 or 26). The processor which is connected to multiplexer 16 is required to generate signals on the pads that are connected to the multiplexer such that a signal which represents the state of storage element 26 is developed on the pad that is connected to line 142. (In so doing, a signal having a low logic level is generated on line 74 (as the second read clocking signal) causing storage element 26 to store (latch) the state of the signal developed on line 68 and to develop a signal of similar state on line 76. It is necessary to store (latch) the state of the signal developed on line 68 to prevent the state of the signal from changing while it is being read, as would occur if the other processor were to relinquish the resource at this time.) Third, the processor is required to "test" the number read (to determine its value, whether it is a zero - the active state - or a one - the inactive state -). If the results of the test indicate that the resource is not in use (the number read is a zero), the processor is free to use the resource as long as desired and as often as desired. (If the results of the test indicate that the resource is in use (the number read is a one), the processor is required to continue reading and testing until the resource is not in use (the number read is a zero). It is not necessary to continue writing, unless required to allow the state of the signal developed on line 74 to go high.) Finally, when the processor is through with the resource, the processor is required to "write" (a one) into the appropriate storage element to indicate that the resource is no longer in use. The processor which is connected to multiplexer 16 is required to generate signals on the pads that are connected to the multiplexer such that a high-logic-level signal (a one) is developed on line 40 (as the second data input signal having an inactive state). Simultaneously, the processor is required to generate signals such that a signal having a low logic level is generated on line 42 (as the fourth write clocking signal).

Claims: A semaphore system for use in limiting access to a resource by a first and a second user, comprising a first semaphore circuit (10) employing first, second, third and fourth storage element means (20, 22, 24, 26) each including a clock input, a data input (D) and a data output (Y), and arbitrator means (28) having a first input (at 34), a second input (at 44), a first output (at 64) and a second output (at 68), said arbitrator means (28) having a first state delineating when only said first user is permitted access to said resource and a second state delineating when only said second user is permitted access to said resource, CHARACTERIZED IN THAT said first storage element means (20) includes said clock input (at 32) which is for receiving first and second write clocking signals from said first user marking first and second write times, said data input (D, at 30) is for receiving a first data input signal having an active state at said first write time when said first user is requesting access to the resource and an inactive state at said second write time when said first user is relinquishing access to said resource, and said data output (Y, at 34) has an active state when said first user has requested access to said resource and an inactive state when said first user has relinquished access to said resource; said second storage element means (22) includes said clock input (at 42) which is for receiving third and fourth write clocking signals from said second user marking third and fourth write times, said data input (D, at 40) is for receiving a second data input signal having an active state at said third write time when the second user is requesting access to said resource and an inactive state at said fourth write time when said second user is relinquishing access to said resource, and said data output (Y, at 44) has an active state when said second user has requested access to said resource and an inactive state when said second user has relinquished access to said resource; said arbitrator means (28) has said first input coupled (34) to said data output (Y) of said first storage element means (20) to receive the developed signal thereof, said second input is coupled (44) to said data output of said second storage element means (22) to receive the developed signal thereof, said arbitrator means assumes said first state when said developed signal of said first storage element means (20) has said active state and said developed signal of said second storage element means (22) has said inactive state, said arbitrator means assumes said second state when said developed signal of said first storage element means (20) has said inactive state and said developed signal of said second storage element means (22) has said active state and said arbitrator means (28) does not change its state when said developed signals received by said inputs change from one active to both active; said third storage element means (24) includes said data input which is coupled (64) to said first output of said arbitrator means, said clock input (at 70) is for receiving a first read clocking signal from said first user marking a first read time between said first and second write times, and said data output (at 72) has an active state following said first read time if said first user is permitted access to said resource and an inactive state following said first read time if said first user is not permitted access to said resource; and said fourth storage element means (26) includes said data input which is coupled (68) to said second output of said arbitrator means; said clock input (at 74) is for receiving a second read clocking signal from said second user marking a second read time between said third said fourth write times, and said data output (at 76) has an active state following said second read time if said second user is permitted access to said resource and an inactive state following said second read time if said second user is not permitted access to said resource. A semaphore system as recited in claim 1 wherein each of said first and said second storage element means (20 and 22) includes a D-type register. A semaphore system as recited in claim 1 or 2 wherein said arbitrator means (28) includes first NOR gate means (50) having a first input coupled (34) to said first storage element means data output, a second input (56), and a output (54), and second NOR gate means (52) having a first input coupled (44) to said second storage element means data output, a second input coupled (54) to said first NOR gate means output, and an output coupled (56) to said first NOR gate means second input. A semaphore system as recited in claim 3 wherein said arbitrator means (28) further includes a first inverter (60) having an input coupled (54) to said first NOR gate means output and an output coupled (64) to said third storage element means data input and a second inverter (66) having an input coupled (56) to said second NOR gate means output and an output coupled (68) to said fourth storage element means data input. A semaphore system as recited in any of claims 1 to 4 wherein each of said third and said fourth storage element means (24 and 26) includes a latch. A semaphore system as recited in any of claims 1 to 5 further comprising a second semaphore circuit (12). A semaphore system as recited in claim 6 further comprising a first and a second multiplexer (14 and 16) each connected to each of said semaphore circuits (10, 12). A semaphore system as recited in claim 7 wherein said second multiplexer (16) includes means for coupling (140) an externally generated data signal (142) to said data input of said second storage element means (22). A semaphore system as recited in claim 7 or 8 wherein said second multiplexer (16) includes selecting means (100, 104, 150, and 170), said selecting means being responsive to at least one externally generated addressing signal (122 or 124 or 126) and operative to select one of said semaphore circuits. A semaphore system as recited in claim 9 wherein said selecting means (100, 104, 150, and 170) is connected (42) to said clock input of said second storage element means (22) and wherein said selecting means is further operative to develop a signal (42) for clocking said second storage element means (22) during each of said third and fourth write times when said first semaphore circuit (10) is selected. A semaphore system as recited in claim 9 or 10 wherein said selecting means (100, 104, 150, and 170) is connected (74) to said clock input of said fourth storage element means (26) and wherein said selecting means is further operative to develop a signal (74) for clocking said fourth storage element means (26) during said second read time when said first semaphore circuit (10) is selected.

Inventors: MILLER, MICHAEL J.
Applicants: INTEGRATED DEVICE TECHNOLOGY, INC.
Application year: 1987
Main classification: G06F9
IPC codes: G06F9, G06F12, G06F13, G06F15