Master slice type integrated circuit

Abstract: A semiconductor circuit comprises basic cells formed in an internal cell region on an integrated-circuit chip and pads (22₁, 22₂, ..., 22 n ) for input/output cells, the pads being arranged in peripheral regions on said chip. The semiconductor circuit further comprises first logic circuit means (23₁, 23₂, ..., 23 n ) provided for each of the input/output cells, each including logic circuits formed by transistors of relatively high drive capability which are a part of said respective input/output cells, the first logic circuit means being positioned in the peripheral regions. The present invention also comprises second logic circuit means (25₁, 25₂, ..., 25 n ) provided for each of the input/output cells, each including remaining logic circuits of the respective input/output cells, the second logic circuit being formed by the basic cells formed in the internal cell regions, so that each of said input/output cells is formed by one pad and the combination of the first and second logic circuit means.

Description: BACKGROUND OF THE INVENTION The present invention relates to master slice type integrated-circuit devices, which are capable of providing many kinds of logic circuits by carrying out desired interconnection for chips which are manufactured by common processes except a final interconnecting process. The present invention more particularly relates to improvements in input/output cells formed on chips in master slice type integrated-circuit devices such as a complementary metal oxide semiconductor gate array. This type of semiconductor integrated-circuit devices has a chip on which there are formed basic cells which are arranged like matrix as well as input/output cells arranged around the basic cells. Each basic cell is generally composed of a plurality of transistors. The final interconnecting process has not yet been carried out for the basic cells. Therefore, desired logic circuits may be formed by interconnecting the transistors included in the basic cells. Input/output cells (hereafter referred to as I/O cells), which supply the logic circuits on the chip with signals from external circuits and/or feed output signals of the logic circuits to the external circuits, are arranged in peripheral regions on the chip. One I/O cell is generally made up of a protection circuit for absorbing over-voltage due to electrostatic discharge, a logic circuit having logic functions of an input buffer and/or an output buffer, and a bonding pad. However, as will be described in detail later, the semiconductor devices aforementioned have disadvantages in that the number of I/O cells capable of being arranged in the chip peripheral regions is subject to some limitations and does not necessarily satisfy needs of customers. This is because all of the components forming the I/O cells are arranged in the peripheral regions on the chip, and therefore the size of each I/O cell is relatively large. In addition, it is difficult to arrange the I/O cells in regions on the chip very close to its corners, and to therefore utilize the chip corner regions efficiently. This leads to degradation in accuracy of a bonding process for connecting the bonding pads with corresponding lead patterns. EP-A-0 136 952 discloses a gate array having a plurality of basic cells arranged in the inner cell region. Outside the inner cell region, there is the input/output cell region and at the outermost region, bonding pads are formed being used as terminals. Some of the basic cells at specified positions are replaced by basic cells having transistors with a lower gm to reduce the basic cells necessary for constituting a delay circuit and to eliminate need for the external resistive component which is formerly requisite when a pull-up or pull-down circuit or monostable multivibrator is built in the gate array. The lower gm transistors may be combined with transistors of the input/output cell region to form an input circuit. GB-A-2 143 990 discloses a semiconductor integrated circuit device with buffer circuits. This device includes input and output buffers each provided in correspondence with a bonding pad and is made usable for either the input buffer or the output buffer in accordance with a wiring pattern to be formed therein using the same circuit elements. Thus, the circuit elements which contain MISFETs used for inputting and outputting need not be separately formed, and the occupying area of the buffers is reduced to that extent, to realize increase in the number of pins or reduction in the size of a chip. Patent Abstracts of Japan vol. 8, no. 155 (E-256)[1592] discloses a gate array type semiconductor integrated circuit device which reduces the input/output region to the essential elements, such as an input buffer, a protective diode and output drive transistors. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device, in which the above described problems have been eliminated. Another and more specific object of the present invention is to provide a semiconductor device in which each I/O cell is divided into two logic circuits, one being located in chip peripheral regions and the other being formed by basic cells which are arranged in an internal cell region. A semiconductor device according to the present invention is described in claim 1. Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a plan view of a conventional semiconductor integrated-circuit device, FIG.2 is a plan view of one example of a semiconductor integrated-circuit device incorporating the present invention, FIG. 3(A) is a plan view of part of the device shown integrated-circuit in FIG. 2, FIG. 3(B) is a plan view of a basic cell arranged in an internal cell region in the semiconductor device in FIG.2, FIG. 4 is a circuit diagram of a protection circuit in the semiconductor device in FIG.2, FIGS. 5(A) and 5(B) are respectively a circuit diagram and its equivalent circuit diagram of an I/O cell forming an input buffer according to the present invention employed in the semiconductor device in FIG.2, FIG. 6 is a plan view of a chip corner part of the semiconductor device in FIG.2, and FIG. 7 is a plan view of another example of a semiconductor device incorporating the advantages of the present invention. DETAILED DESCRIPTION Description will first be given of a conventional semiconductor integrated-circuit device to ensure a better understanding of the present invention which will be described in detail later. Referring to FIG.1, an integrated-circuit chip 11 mounted on a die stage 10 of a package 100 has I/O cells 12₁, 12₂, ..., 12 i , which are arranged in peripheral regions on the chip 11. Each I/O cell consists of a protection circuit for absorbing over-voltage resulting from electrostatic discharge, a logic circuit (not shown) having logic functions of an input buffer and/or an output buffer, and a bonding pad 13₁, 13₂, ..., 13 i . In an internal region on the chip 11 which is surrounded by the arrangement of the I/O cells 12₁, 12₂, ..., 12 i , there are arranged basic cell columns 15₁, 15₂, ..., 15 j , each of which is formed by arranging basic cells in a predetermined direction. Each basic cell is composed of elements such as transistors. The interconnecting process for the basic cells is carried out according to customer requirements to form desired logic circuits such as NAND gates, flip-flops, and so on. The I/O cells 12₁, 12₂, ...,12 i are each connected to the respective basic cells by lines 14. The bonding pads 13₁, 13₂, ..., 13 i are connected to relative lead patterns 16₁, 16₂,... with bonding wires 17₁, 17₂ .... However, the above conventional semiconductor device has the disadvantages aforementioned. That is, the number of the I/O cells 12₁, 12₂, ... , 12 i is subject to limitations, as the size of each I/O cell is not necessarily small. This is because all the elements forming one I/O cell are positioned in the chip peripheral regions. Therefore, it is also impossible to locate the I/O cells 12₁ and 12 i at positions closer to a chip corner 11a than their respective positions in FIG.1. This means that the four chip corner areas 11a remain wasteful. Thus, the conventional semiconductor device cannot sufficiently satisfy customer requirement for the number of the I/O cell pins corresponding to the number of the I/O cells. In addition, the length of the bonding wires and an incident angle of the bonding wires with respect to the chip are limited to prevent bonding failure, because reliability of bonding is degraded due to dip of the bonding wires when the bonding wires are too long. In the configuration shown in FIG.1, the I/O cells 12₁ and 12 i are away from the corresponding interconnection patterns 16₁ and 16₂, and therefore the wires 17₁ and 17₂ are liable to be lengthened. Therefore, it is desirable to shorten these bonding wires and make the incident angle obtuse in the light of facility and reliability of bonding. The present invention mainly provides a semiconductor device in which the above problems have been eliminated. Description will now be given of one example of a semiconductor device with reference to FIG.2, which is a plan view thereof. A device according to the present invention is obtained by connection of the input/output cell as shown in Fig. 5A. In peripheral regions on an integrated-circuit chip 21 mounted on a platform 20 of a semiconductor device 200, there are provided bonding pads 22₁, 22₂, ..., 22 n and first logic circuits 23₁, 23₂, ..., 23 n . The bonding pads 22₁, 22₂, ..., 22 n are connected to corresponding interconnection patterns 26₁, 26₂,... by bonding wires 27₁, 27₂,.... Each first logic circuit consists of a part of all the elements forming one I/O cell, and a protection circuit for absorbing over-voltage resulting from electrostatic discharge. The protection circuit is not necessarily needed especially for an output buffer. The bonding pads 22₁, 22₂, ..., 22 n are aligned with the corresponding first logic circuits 23₁, 23₂, ..., 23 n . For example, the pad 22₁ is aligned with the first logic circuit 23₁ in the Y direction. In an internal cell region surrounded by the first logic circuits, there are formed basic cell columns 24₁, 24₂, ..., 24 m discretely arranged in the X direction. Each basic cell column is made up of a plurality of basic cells aligned in the Y direction. The basic cell columns 24₁, 24₂, ..., 24 m include second logic circuits 25₁, 25₂, ..., 25 n , each of which consists of the remaining elements other than the elements of one I/O cell which are included in each of the first logic circuits 23₁, 23₂, ..., 23 n . In other words, each second logic circuit is formed by the basic cells. The second logic circuits 25₁, 25₂, ..., 25 n are each connected to the respective first logic circuits 23₁, 23₂, ..., 23 n . As described previously, the circuit forming one I/O cell is divided into two parts, that is, the first logic circuit positioned in the chip peripheral regions and the second logic circuit formed by the basic cell or the basic cells in the basic cell columns. This arrangement makes it possible to increase the number of I/O cells mounted on the chip and to effectively reduce bonding failure, as will be described in detail later. FIG.3(A) and 3(B) is an enlarged plan view of a part of the chip illustrated in FIG.2. The first logic circuit 23 n includes a n-channel MOS transistor region 32 in which drains/sources are formed, and a p-channel MOS transistor region 33 in which drains/sources are formed. The width of these regions is nearly equal to that of the pad 22 n . Gate electrodes 34 are mounted on the n- and p-channel regions 32 and 33. Symbols indicated by characters CH represent contact holes, which form contacts between a first layer metallization illustrated by solid lines and source/drain regions 32 and 33. Also, symbols indicated by characters TH represent through holes, which forms contacts between the first layer metallization and a second layer metallization illustrated by broken lines. As illustrated in FIG.3(A), the first logic circuit 23 n is formed by mutually connecting the gate electrodes 34 and commonly connecting drains in the n- and p-channel regions 32 and 33. A plurality of transistors (six in this example) in each of n- and p-channel regions 32 and 33 are connected in parallel. The interconnection described above is carried out by using masks for the contact holes CH, the through holes TH, the first metallization and the second metallization. It is very effective to prepare several n-channel and p-channel transistors for each I/O cell and to connect some or all of these transistors with each other in parallel. This is because the capability of the I/O cell for driving loads can be enhanced, and also the degree of freedom of design of the I/O cells can be made high. Of course, it is possible to arrange a single n-channel transistor of the relatively high drive capability in the n-channel transistor region 32, and a single p-channel transistor of the relatively high drive capability in the p-channel transistor region 33. The second logic circuit 25 n of the I/O cell is formed as shown in FIG. 3(B). One basic cell has a n-channel region 35, a p-channel region 36 and gate electrodes 37 laid over these regions. In this example, one basic cell is formed by the combination of two n-channel transistors and two p-channel transistors. Turning now FIG. 3(A), a protection circuit area 38 is provided between the bonding pad 22 n of substantially square shape and the n-channel transistor region 32. For absorbing over-voltage resulting from electrostatic discharge, it is preferable to provide the protection circuit in the protection circuit area 38 for each I/O cell. This is why the structure shown in FIG.3(A) is applicable to an input buffer, which will be described later. FIG. 4 is a circuit diagram of one example of a protection circuit formed in the protection circuit area 38. The protection circuit illustrated is formed by series-connected diodes D₁ and D₂ between the earth and the power supply (not shown). That is, the anode of the diode D₂ and the cathode of the diode D₁ are connected to the earth and the power source, respectively. The anode of the diode D₁ and the cathode of the diode D₂ is connected to the pad 22 n and the first logic circuit 23 n . FIGS. 5(A) and 5(B) are respectively a circuit diagram and its equivalent circuit diagram of an I/O cell forming an input buffer according to the invention in the semiconductor device in FIG.2. An input buffer 60 is of a four stage cascade configuration with MOS transistors. Each stage of the input buffer 60 is composed of a pair of a p-channel MOS transistor and a n-channel MOS transistor. The first logic circuit 23 n of the input buffer 60 consists of a protection circuit 62 connected to the pad 22 n and a transistor logic circuit 63 at the final (or fourth) stage, whereas the second logic circuit 25 n consists of transistor logic circuits 64a, 64b and 64c at the first, second and third stages. An output terminal 71 of the final stage is connected to logic circuits (not shown) such as flip-flops. The input buffer 60 in FIG. 5(A) is a clock input buffer which drives flip-flops formed by the basic cells in the basic cell columns. In general, one clock input buffer supplies approximately 50-100 flip-flops with a clock signal. Therefore, the load of the final stage transistors of the clock input buffer is relatively high, so that it becomes necessary to use the transistors of the relatively high drive capability. For example, the mutual conductance of the final stage transistors is approximately ten to twenty times larger than the transistors of the first stage. Therefore, it is difficult to form the final stage transistors with the combination of the basic cells. Also, this leads to the reduction of the number of the basic cells which form many kinds of logic circuits such as NAND gates, flip-flops and so on in accordance with customer requirements. Therefore, according to the present invention, the first logic circuit 23 n consisting of the protection circuit 62 and the transistor circuit 63 are arranged in the chip peripheral regions, whereas the second logic circuit 25 n consisting of the transistor circuits 64a, 64b and 64c is positioned at the first through third stages in the basic cell column 24 m . The transistor circuit 63 at the final stage of the input buffer 60 may be formed in a similar manner as in the transistor circuit at the final stage shown in FIG. 3 (A). That is, the n-channel and p-channel transistors of the transistor circuit 63 in FIG. 5(A) are respectively formed with a plurality of n-channel transistors connected in parallel and a plurality of p-channel transistors connected in parallel. Of course, a single n-channel transistor and a single p-channel transistor may be employed. However, the degree of freedom of design of the semiconductor device where the parallel connection of the transistors is employed to form the final stage transistors is higher than that of the semiconductor device using a single transistor for each channel. The protection circuit 62 may have the same circuit structure as that in FIG. 4. Further, the transistor circuit 64a at the first stage acts as a level shifter, and the transistor circuits 64b and 64c act as amplifier circuits. Each of the transistor circuits 64a, 64b and 64c may be formed by the basic cell shown in FIG. 3(B) or its combination. In particular, the transistor circuit 64c at the third stage needs transistors more powerful than the transistors at the first or second stage, because the transistor circuit 64c drives the transistor circuit 63 at the final stage. Therefore, the transistor circuit 64c is preferably formed by the combination of the basic cells connected in parallel. The arrangements discussed in the foregoing, in which one I/O cell is divided into two logic circuits provides the following advantages. Referring to FIG. 6, which is an enlarged plan view of one chip corner part of the semiconductor device shown in FIG.2, the first logic circuit 23n arranged in the chip peripheral regions consists of the transistors of the relatively high drive capability and the protection circuit. Therefore, according to the present invention, it is possible to reduce the size of the I/O cells arranged in the chip peripheral regions. In detail, the width w and the length l of the I/O cell 23₁ can be made small, as compared with the I/O cell 12₁. Therefore, it is possible to arrange many more I/O cells on the chip. In other words, the present invention makes it possible to position the I/O cells in the chip corner regions more closely to the chip corners. This means that the area S₂ of the chip corner region 21a can be made smaller than the area S₁ of the chip corner region 11a. Thus, it is also possible to utilize the chip corner regions 21a efficiently. Moreover, the above arrangements make it possible to shorten the length of the bonding wire 27₁ (FIG.2) extending between the pad 22₁ of the I/O cell in the chip corner region 21a and the corresponding interconnection pattern 26₁, compared with the conventional arrangement of the I/O cell. In other words, it is possible to decrease the incident angle of the bonding wire and to thus improve accuracy of the bonding process. The improvement in accuracy of the bonding process is very important to the master slice type semiconductor devices, which can provide many kinds of the logic circuits by using the chip having common configurations but different interconnections. FIG. 7 is a plan view of a variation of the semiconductor device illustrated in FIG.2. One of the essential features of this variation is to position only the pads in the chip corner regions 21a and their vicinity closer to the chip corners than the arrangement in FIG.2. For example, the pad 22₁ in FIG. 7 is positioned closer to the chip corner than the pad 22₁ in FIG.2. However, the first logic circuit 23₁ of the I/O cell corresponding to the pad 22₁ remains at its original location shown in FIG.2. The arrangement in FIG. 7 makes it possible to further improve accuracy of the bonding process, as compared with that in FIG.2. Of course, the variation includes all of the essential features provided by the configuration in FIG.2. Embodiments according to the present invention have been described in detail. In the embodiment aforementioned, the first logic circuit 23 n consists of the transistors of relatively high drive capability and the protection circuit if necessary. However, when the present invention is applied to a semiconductor device which has pull-up/-down resistors in the I/O cells, it is preferable to include them in the first logic circuit located in the chip peripheral regions. This is why these resistors are of the size considerably larger than the basic cells.

Claims: A master slice type semiconductor integrated circuit device comprising: a basic cell array (24, ....24n) having a plurality of basic cells each having first MOS transistors; and a plurality of input/output cells (23,..., 23n) arranged around said basic cell array, each of said input/output cells including a pad (22), a protection circuit (38, 62, 72) for absorbing an over-voltage and second MOS transistors with a relatively large drive capability having mutual conductance approximately ten to twenty times larger than that of said first MOS transistors of said basic cells, characterized in that an input buffer circuit (60) for a relatively high load is formed by said protection circuit (62) connected to said pad (22), a first input circuit (25) connected to said protection circuit and a second input circuit (23) connected to an output of said first input circuit wherein said first input circuit is formed by said first MOS transistors of said basic cells and said second input circuit is formed by said second transistors of said input/output cell, and the output terminal of said second input circuit (23) is connected to logic circuits in said basic cell array. A semiconductor device as claimed in claim 1, characterized in that at least one (22₁, 22₂) of said pads which is located in the vicinity of a corner of the chip is located at a position closer to both edges forming that corner than a position of said input/output cell connected to said pad. A semiconductor device as claimed in claim 1, characterized in that said transistors of said input/output cell include transistors connected in parallel. A semiconductor device as claimed in claim 1, characterized in that: said protection circuit protectss said first and second MOS transistors against an over-voltage resulting from electrostatic discharge, said buffer circuit having cascaded CMOS inverters, and said protection circuit being connected in series with said pad and said buffer circuit;

Inventors: SUEHIRO YOSHIYUKI, SUEHIRO, YOSHIYUKI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1987
Main classification: H01L27
IPC codes: H01L21, H01L27, H03K19, H03K5