DYNAMIC RANDOM ACCESS MEMORY

Abstract: A dynamic random access memory with a folded bit line structure (BLL j1 , BLL j1 , BLR j1 , BLR j1 ), , each pair of bit lines being divided into a plurality of blocks (MCB j1 , MCB j2 ), comprises equalizing transistors (Q j9 , Q j10 ) each of which is provided for each pair of divided bit lines to equalize the pair of divided bit lines. The equalizing transistors (Q j9 , Q j10 ) stop equalizing selectively and at different times among the blocks.

Description: The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM) in general. More particularly, but not exclusively, it relates to a CMOS-DRAM employing a (1/2) V CC precharge system, i.e. a system of precharging bit lines at (1/2) V CC by equalizing means. It also relates to a method of reading the same. A dynamic RAM generally comprises memory cell array blocks. Each of the blocks has a plurality of memory cells, and each of the memory cells is formed by a transistor and a capacitor. As the ratio of the capacitance of a bit line to that of the capacitor of the memory cell is decreased, potential variation of the bit line in data reading is increased so that input potential difference for a sense amplifier is increased, whereby a read operation is reliably performed. However, the memory cell size is reduced as a memory having a larger capacity is implemented with higher density of integration, whereby the memory cell capacitance is decreased while the number of memory cells connected to a bit line is increased. Therefore, the bit line is enlarged in length and the capacitance thereof is increased. Thus, the ratio of the bit line capacitance to the memory cell capacitance may be so increased that a read operation cannot be reliably performed. In order to solve such a problem, there is an attempt to divide a bit line into a plurality of blocks to reduce the ratio of the bit line capacitance to the memory cell capacitance. Fig. 1 shows the entire structure of a conventional basic DRAM. Referring to Fig. 1, the conventional DRAM comprises a memory part 1 including a memory cell array formed by a plurality of memory cells arrayed in the form of a matrix, a row decoder for selecting a row from the memory cell array and a column decoder for selecting a column from the memory cell array. Provided as peripheral circuits are a clock generation circuit 2 for generating various operation timing signals in response to an externally supplied clock signal RAS , an address buffer 3 for strobing externally supplied address signals A₀ to A n in response to a control signal (internal RAS ) from the clock generation circuit 2 to generate an internal address signal and supply the same to the row decoder and the column decoder of the memory part 1, a data input buffer 4 for receiving input data D IN in response to a control signal from the clock generation circuit 2 and transmitting the same to the memory part 1 and a data output buffer 5 for receiving data read from the memory part 1 in response to a control signal from the clock generation circuit 2 and transferring output data D OUT to the exterior. The clock signal RAS is supplied to a terminal 10. The external address signals A₀ to A n are supplied to terminals 11-0 to 11-n, respectively. The input data D IN is supplied to a terminal 12. The output data D OUT is transmitted from a terminal 13 to the exterior of the DRAM. A power terminal 14 for receiving supply voltage V CC and a ground terminal 15 connected to a ground potential V SS are further provided in order to supply operating voltage to the DRAM. The memory part 1 and the peripheral circuits are integrated on a semiconductor chip 16. Fig. 2 shows exemplary structure of the memory part 1 of the DRAM as shown in Fig. 1. Referring to Fig. 2, the memory cell array is divided into eight memory cell array blocks ML₁, ML₂, ML₃ and ML₄ and MR₁, MR₂, MR₃ and MR₄. A column decoder is provided for four memory cell array blocks. Namely, a column decoder CL is provided for the left memory cell array blocks ML₁ to ML₄ and another column decoder CR is provided for the right memory cell array blocks MR₁ to MR₄. A shared sense amplifier block NSL₁ is provided between the memory cell array blocks ML₁ and ML₂. Respective bit lines of the memory cell array blocks ML₁ and ML₂ are connected with each other through the shared sense amplifier block NSL₁, to form one bit line. A sense amplifier block PSL₁ is provided to detect and amplify information on each bit line of the memory cell array block ML₁, and a sense amplifier + I/O block PIL₁ is provided between the column decoder CL and the memory cell array block ML₂ in order to detect and amplify information on each bit line of the memory cell array block ML₂. The information on each bit line of the memory cell array block ML₁ is detected and amplified by respective amplifiers of the sense amplifier block PSL₁ and the shared sense amplifier block NSL₁. The information on each bit line of the memory cell array block ML₂ is detected and amplified by respective amplifiers of the shared sense amplifier block NSL₁ and the sense amplifier + I/O block PIL₁. One of the bit lines of the memory cell array blocks ML₁ and ML₂ is connected to a data input/output bus through an I/O gate in the sense amplifier + I/O block PIL₁ by output of the column decoder CL. The remaining memory cell array blocks ML₃ and ML₄ are arranged in a similar manner to the above. Namely, a sense amplifier + I/O block PIL₂ is provided between the column decoder CL and the memory cell array block ML₃ and a shared sense amplifier block NSL₂ is provided between the memory cell array blocks ML₃ and ML₄ while a sense amplifier block PSL₂ is provided on the right end of the memory cell array block ML₄. The right memory cell array blocks MR₁ to MR₄ are arranged symmetrically to the left memory cell array blocks ML₁ to ML₄. A sense amplifier block PSR₁ is provided for the memory cell array block MR₁, and a shared sense amplifier block NSR₁ is provided between the memory cell array blocks MR₁ and MR₂. A sense amplifier + I/O block PIR₁ is provided between the memory cell array block MR₂ and the column decoder CR. A sense amplifier + I/O block PIR₂ is provided between the column decoder CR and the memory cell array block MR₃. A shared sense amplifier block NSR₂ is provided between the memory cell array blocks MR₃ and MR₄, and a sense amplifier block PSR₂ is provided on the right end of the memory cell array block MR₄. Operation of each right block is functionally similar to that of the corresponding one of the left blocks. A row decoder RD is provided for selecting a word line (a row) from the memory cell array blocks ML₁ to ML₄ and MR₁ to MR₄. Description is now made on the structure of a bit line part selected by one of column decoder output, i.e., the structure of an adjacent pair of memory cell array blocks and a sense amplifier provided for the same. Fig. 3 illustrates the structure of a bit line pair and a CMOS sense amplifier part of a conventional DRAM as described in, e.g., ISSCC Digest of Technical Papers 1984, pp. 278 to 279. This DRAM employs the so-called shared sense amplifier structure in which each bit line is divided into a pair of divided bit lines to commonly share a sense amplifier with a divided bit line pair provided on both sides of the same. Although transistors of memory cells are formed by P-channel FETs and the shared sense amplifier is formed by P-channel FETs and sense amplifiers on both ends are formed by N-channel FETs in the structure described in the aforementioned literature, such FETs are reversed in conductivity type and the operation is slightly simplified in Fig. 3, for convenience of illustration and comparison. Referring to Fig. 3, symbols MCB j1 and MCB j2 indicate memory cell array blocks, each of which includes a plurality of word lines, a plurality of divided bit line pairs, memory cells, potential difference amplifying means and equalizing means. Bit lines forming folded bit lines are divided into bit line pairs BLL j , BLL j and BLR j , BLR j respectively. Cross-coupled FETs Q j1 and Q j2 form an N-channel sense amplifier (potential difference amplifying means) NSA j , which is shared with the memory cell array blocks MCB j1 and MCB j2 . Similarly cross-coupled FETs Q j5 , Q j6 and Q j7 , Q j8 are adapted to form P-channel sense amplifiers (potential difference amplifying means) PSA jL and PSA jR , respectively. The sources of the FETs Q j1 and Q j2 are commonly connected to the drain of an FET Q N , whose gate and source are connected to an N-channel sense amplifier driving signal S N and a ground potential V SS , respectively. The sources of the FETs Q j5 , Q j6 and Q j7 , Q j8 are commonly connected to the drains of FETs Q PL and Q PR respectively, while the gate and the source of the FET Q PL are connected to a P-channel sense amplifier driving signal S PL and a supply potential V CC respectively, and the gate and the source of the FET Q PR are connected to a P-channel sense amplifier driving signal S PR and a supply potential V CC , respectively. The P-channel sense amplifier PSA jL is connected to the divided bit lines BLL j and BLL j and the P-channel sense amplifier PSA jR is connected to the divided bit lines BLR j and BLR j . Transfer gate FETs Q j11 and Q j12 are provided between the divided bit lines BLL j and BLL j and the N-channel sense amplifier NSA j while transfer gate FETs Q j13 and Q j14 are provided between the divided bit lines BLR j and BLR j and the N-channel sense amplifier NSA j . The gates of the FETs Q j11 , Q j12 and Q j13 , Q j14 receive the transfer signals SL and SR, respectively. FETs Q j9 and Q j10 are provided for equalizing the divided bit line pairs BLL j , BLL j and BLR j , BLR j respectively, and the gates thereof receive equalizing signals EQ. The divided bit lines BLR j and BLR j are connected to bus lines BU and BU , respectively, through column gate FETs Q j15 and Q j16 , whose gates are connected to a column selecting signal Y j. Although a plurality of memory cells are generally connected to such divided bit lines in accordance with memory capacity, for simplicity is represented a memory cell MC ij connected to the divided bit line BLL j in Fig. 3. The memory cell MC ij is formed by a capacitor C ij and an FET Q ij , and the gate of the FET Q ij is connected to a word line WL i . An electrode of the capacitor C ij is connected to a memory cell plate potential V SG . Description is now made on an operation of the CMOS sense amplifier structure as shown in Fig. 3 in the case of reading data "1" stored in the capacitor C ij of the memory cell MC ij , with reference to Fig. 4 showing an operating waveform diagram. The DRAM enters an activated state on the falling edge of an external signal RAS (hereinafter referred to as Ext. R AS signal) as shown in Fig. 4. In this activated state, an external row address signal is latched in the interior of the chip on the falling edge of the Ext. RAS signal. Then the equalizing signal EQ and the transfer signal SR are turned to low levels to stop equalization of the divided bit lines BLL j , BLL j and BLR j , BLR j while separating the divided bit lines BLR j and BLR j from the N-channel sense amplifier NSA. At this time, the transfer signal SL is maintained at a high level. Then, a potential of a word line selected in response to the row address signal latched in the chip interior goes high. It is assumed here that the word line WL i of Fig. 3 is selected. When the potential of the word line WL i thus goes high, the FET Q ij enters an ON state so that the charge stored in the capacitor C ij is transferred to the divided bit line BLL j , whereby the potential of the divided bit line BLL j exceeds the level as is equalized, i.e., (V CC - V SS )/2. Then, the sense amplifier driving signals S N and S PL are turned to high and low levels, respectively, whereby the FETs Q N and Q PL are turned on so that the N-channel sense amplifier NSA j and the P-channel sense amplifier PSA jL operate to amplify the potential difference between the divided bit lines BLL j and BLL j . Then, the transfer signal SR again goes high so that the potentials of the divided bit lines BLL j and BLL j are transferred to the divided bit lines BLR j and BLR j . As the result, the potentials of the divided bit lines BLR j and BLR j go high and low, respectively. Then, the sense amplifier driving signal S PR goes low and the FET Q PR enters an ON state so that the P-channel sense amplifier PSA jR operates, whereby the potential of the divided bit line BLR j is raised to a higher level. Then, the column selecting signal Y j goes high so that the potentials of the divided bit lines BLR j and BLR j are transferred to the bus lines BU and BU , whereby the data "1" stored in the capacitor C ij of the memory cell MC ij is read out. When the Ext. RAS signal goes high so that the DRAM enters an inactivated state, the potential of the selected word line WL i goes low and the FET Q ij in the memory MC cj enters an OFF state. Then the sense amplifier driving signal S N is turned to a low level and the signals S PL and S PR are turned to high levels. Further, the equalizing signals EQ and the transfer signals SL and SR are turned to high levels, whereby the divided bit lines BLL j , BLL j and BLR j and BLR j are equalized so that the respective potentials thereof are averaged to the level of (V CC -V SS )/2, while the paired divided bit lines are connected with each other at the same time. The aforementioned various control signals are produced by circuits as shown in Fig. 5. Description is now made on the structure of each control signal producing circuit. The equalizing signal EQ is produced by a delay circuit 51 for delaying the clock signal RAS by a predetermined time t₂ and an equalizing signal generator 52 formed by a buffer for waveform-shaping output from the delay circuit 51 and outputting the same. A word line driving signal WL i is produced by a row decoder 53. The row decoder 53 decodes an internal row address from an address buffer 54 for receiving an external address and producing an internal address to select a word line WL i , thereby to make the potential of the selected word line rise in response to a signal from a delay circuit 55 for delaying the clock signal RAS by a time t₃. The NMOS sense amplifier driving signal S N is produced by a delay circuit 56 for delaying the word line driving signal WL i by a time t₄ and outputting the same and an NMOS sense amplifier driving signal generator 57 formed by a buffer for waveform-shaping output from the delay circuit 56 and outputting the same. The transfer signal SL is produced by a left transfer signal generator 60 activated in response to a block selecting address from the address buffer 54 for generating a signal which falls in response to a signal from a delay circuit 58 for delaying the clock signal RAS by a time t₁ while rising in response to output from a delay circuit 59 for delaying the NMOS sense amplifier driving signal S N by a time t₆. The transfer signal SR is produced by a right transfer signal generator 61 activated in response to a block selecting address from the address buffer 54 for generating a signal which falls in response to the output from the delay circuit 58 while rising in response to the output from the delay circuit 59. The PMOS sense amplifier driving signal S PL is produced by a left PMOS sense amplifier driving circuit 64 activated in response to a block selecting address from the address buffer 54 for generating a signal which goes low in response to either output from a delay circuit 62 for delaying the sense amplifier driving signal S N by a time t₅ or output from a delay circuit 63 for delaying the sense amplifier driving signal S N by a time t₇. The PMOS sense amplifier driving signal S PR is produced by a right PMOS sense amplifier activating circuit 65 activated by a block selecting address from the address buffer 54 for generating a signal which falls in response to either output from the delay circuit 62 or 63. The falling timing of the sense amplifier driving signals S PL and S PR is determined by the block selecting address. The column selecting signal Y j is produced by a column decoder 67. The column decoder 67 decodes a column address from the address buffer 54 to generate a signal Y j which rises in response to output of a delay circuit 66 for delaying the NMOS sense amplifier driving signal S N by a time t₈ to select a pair of bit lines and connect the same to the data input/output buses BU and BU . When the word line WL i in the left-side block is selected in the conventional dynamic random access memory as hereinabove described, the data stored in the memory cell is first read on the divided bit lines BLL j and BLL j , to be then transferred to the divided bit lines BLR j and BLR j . On the other hand, since the left and right divided bit line pairs BLL j , BLL j and BLR j , BLR j are equalized by the same signals EQ, equalization of these divided bit line pairs is simultaneously stopped. Consequently, when a word line in the left memory block is selected, the right-side divided bit lines BLR j and BLR j enter electrically floating states after the equalizing signal EQ goes low, to be maintained in such states until the transfer signal SR again goes high. Such an interval is about 5 to 15 nsec. in general. In this interval, the left-side divided bit lines BLL j and BLL j perform a sensing operation. During the sensing operation, one of the divided bit lines BLL j and BLL j , i.e., BLL j in this case, is discharged to the ground potential V SS while the other one, i.e., BLL j in this case, is charged to the power supply potential V CC . Such sensing operation is simultaneously performed in a number of divided bit line pairs coupled to memory cells which are connected to the selected word line WL i , whereby the levels of the ground potential V SS and the supply potential V CC are varied to cause noise. The right-side divided bit lines BLR j and BLR j are in floating states at the time when such noise is caused, to be subjected to potential deviation by such noise. When the divided bit lines BLR j and BLR j are affected by noise in a direction opposite to the potentials to be originally effected, it takes time to discharge and charge the divided bit lines BLR j and BLR j , respectively, whereby the sensing time is increased by Δ t as compared with the case in which no such noise is produced, to delay the access time. A method of equalizing a bit line pair is described in U.S. Patent No. 4397003 to Wilson et al., for example. However, this prior art takes no account of a divided bit line pair or noise applied to the divided bit line pair As relevant background prior art, mention is made of U.S. Patent Applications Serial Nos. 014837, 020192 and 027536 by the same applicant. Each of these disclose a DRAM having a divided line pair structure and the same equalising timing as just described. Other prior art dynamic random access memories having a multiple block structure and in which memory cells are accessed via a plurality of interconnectable divided bit line pairs are disclosed in: European Patent Application No. 0185572; European Patent Application No. 0165106; US Patent Specification No. 4122546; and IBM Technical Disclosure Bulletin, Volume 22 No. 8B, January 1980, pages 3738-3739, New York, US, L Arzubi et al, "Bit Line Cascading In Semiconductor Storage Chips". Dynamic random access memories in accordance with this invention, and memories as described above with reference to Figures 1 to 5, or as disclosed in other prior art and in particular as disclosed in European Patent Application No. 0185572, have the following features in common: a multiplicity of memory cells; a plurality of word lines each connected to a respective row of the memory cells; a plurality of paired bit-lines each connected to a respective column of the memory cells, each pair of bit-lines being divided into a plurality of sections each comprised of a pair of bit-line portions; amplifying means provided for each section for sensing and amplifying a difference in the potentials of the respective bit-line portions; equalising means provided for each section for equalising the potentials of the respective bit-line portions; switching means arranged for coupling together the plurality of sections of each pair of bit-lines and for connecting each pair of bit-lines to a read-out output of the memory; and timing control means for controlling the operations of said equalising means the amplifying means and the switching means. The present invention is intended to provide a dynamic random access memory capable of high speed operation and in which in particular read-out access is improved. Now it has been found that in dynamic random access memories having the common structure just described, the time that is required for the performance of sensing operation for each section of each pair of bit lines is unduly extended by reason that following inhibit of the equalisation of potentials the potentials become unbalanced prior to the respective start of sensing operation in each section. In the initial period of time during which a sensing and amplifying operation is performed in one section of a pair of bit-lines, a noise signal is ordinarily induced in the one or more other sections of the pair of bit-lines that are adjacent or near adjacent to that one section. It is during this initial period of time that charging currents flow and a cross-talk noise signal is induced in those adjacent or near adjacent sections that are at a floating potential. As follows, a solution is provided. In accordance with the present invention, there is provided a dynamic random access memory having the common structure just described, which dynamic random access memory is characterised in that the timing control means is operable to control operation of the amplifying means and the equalising means such that the amplifying means of one section of a bit-line pair is activated to sense and amplify the difference in the potentials of the respective bit-line portions thereof while the equalisation means of said other sections operates so that the potentials of the respective bit-line portions are maintained equal. In the aforesaid memory since the potentials are maintained equal in another of the sections, the effect of the charging currents flowing in the one section do not result in an unbalancing of the potentials in this another section. Accordingly when this another section is coupled in and sensing and amplification is performed, it can attain a stable state more rapidly with consequent reduction in the access time that is necessarily required for reading data stored in the memory. In the preferred embodiment described below potential equalisation in this another section is inhibited to immediately precede its coupling and the sensing and amplification operations that are performed therein. This effectively reduces the period of time during which this section is floating and this thus minimises the time interval during which it can respond to external noise. Mention is made here of European Patent Application No. 0071245. This also describes a memory in which equalisation operations are performed at different times during a read-out cycle. In the arrangement described, the equalisation circuits, one in each of a plurality of parallel pairs of bit-lines, are not all activated together but they are activated in a delayed time sequence. As a result the noise that is produced by the flow of charge/discharge currents in the pairs of bit-lines during equalisation is distributed in time and is substantially reduced in peak value. This is to be compared with the memory just defined which is provided to reduce that noise induced whilst a section of each pair of bit-lines is charged/discharged during sensing and amplification. In the embodiments described below the maintenance of potential equalisation is stopped at different times for each section of each pair of bit-lines, depending on when each section is coupled in and the sensing and amplifying operations are performed therein. The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically illustrates the entire structure of a conventional DRAM; Fig. 2 schematically illustrates the structure of a memory part of the conventional DRAM; Fig. 3 specifically illustrates the structure of a bit line part of a memory cell array of the conventional DRAM; Fig. 4 is a waveform diagram showing sensing operation of the conventional DRAM; Fig. 5 illustrates the structure of respective control signal producing circuits of the conventional DRAM; Fig. 6 illustrates the structure of a bit line part of a memory cell array of a DRAM according to an embodiment of the present invention; Fig. 7 is a waveform diagram showing sensing operation of the DRAM as shown in Fig. 6; Fig. 8 is a block diagram showing circuits for producing signals for controlling the operation of the DRAM as shown in Fig. 6; Fig. 9 illustrates the structure of a bit line part of a memory cell array of a DRAM according to another embodiment of the present invention; Fig. 10 is a waveform diagram showing sensing operation of the DRAM as shown in Fig. 9; Fig. 11 is a block diagram showing circuits for producing control signals for controlling the operation of the DRAM as shown in Fig. 9; and Fig. 12 illustrates the structure of a bit line part of a memory cell array of a DRAM according to still another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Description is now made of embodiments of the present invention with reference to the accompanying drawings. Fig. 6 illustrates the structure of a CMOS sense amplifier part and a paired bit line of a dynamic random access memory according to an embodiment of the present invention. Referring to Fig. 6, a bit line pair forming a folded bit line is divided into bit line pairs BLL j , BLL j and BLR j , BLR j by transfer gate FETs (switching means) Q j11 , Q j12 and Q j13 , Q j14 . Namely, the bit line pair is divided into two bit line pairs. An N-channel sense amplifier NSA j is formed by cross-coupled FETs Q j1 and Q j2 and P-channel sense amplifiers PSA jL and PSA jR are formed by cross-coupled FETs Q j5 , Q j6 and Q j7 , Q j8 , respectively. The sources of the FETs Q j1 and Q j2 are commonly connected to the drain of an FET Q N which in turn has a gate and a source connected to an N-channel sense amplifier driving signal S N and a ground potential V SS , respectively. The sources of the FETs Q j5 , Q j6 and Q j7 , Q j8 are commonly connected to the drains of FETs Q PL and Q PR , respectively, while the gate and the source of the FET Q PL are connected to receive a P-channel sense amplifier driving signal S PL and a supply potential V CC , respectively, and the gate and the source of the FET Q PR are connected to receive a P-channel sense amplifier driving signal S PR and a supply potential V CC . The P-channel sense amplifier PSA jL is provided for the divided bit line pair BLL j and BLL j while the P-channel sense amplifier PSA jR is provided for the divided bit line pair BLR j and BLR j . Transfer gate FETs Q j11 and Q j12 are provided between the divided bit lines BLL j and BLL j and the N-channel sense amplifier NSA j , while transfer gate FETs Q j13 and Q j14 are provided between the divided bit lines BLR j and BLR j and the N-channel sense amplifier NSA j . Transfer signals SL and SR are supplied to the gates of the FETs Q j11 , Q j12 and Q j13 , Q j14 , respectively. FETs Q j9 and Q j10 are adapted to equalize the divided bit line pairs BLL j , BLL j and BLR j , BLR j , respectively, and the gates thereof are connected with equalizing signals EQL and EQR, respectively. The divided bit lines BLR j and BLR j are connected to bus lines BU and BU through column gate FETs Q j15 and Q j16 , whose gates are connected with a column selecting signal Y j . Although a plurality of memory cells are connected to the divided bit lines in accordance with memory capacity, for simplicity is represented a memory cell MC ij connected to the divided bit line BLL j in Fig. 6. The memory cell MC ij is formed by a capacitor C ij and an FET Q ij , while the gate of the FET Q ij is connected to a word line WL i . An electrode of the capacitor C ij is connected to a memory cell plate potential V SG . Description is now made of operation of the CMOS sense amplifier part as shown in Fig. 6 in the case of reading data "1" stored in the capacitor C ij of the memory cell MC ij , with reference to Fig 7 showing an operating waveform diagram. The DRAM enters an activated state on the falling edge of an Ext. RAS signal as shown in Fig. 7. In this activated state, an external row address signal is latched in the chip interior on the falling edge of the Ext. RAS signal. Then the equalizing signal EQL and the transfer signal SR are turned to low levels to stop equalization of the divided bit lines BLL j and BLL j while separating the divided bit lines BLR j and BLR j from the N-channel sense amplifier NSA j . The transfer signal SL and the equalizing signal EQR are maintained at high levels at this time. Then, a potential of a word line selected in response to the row address signal latched in the chip interior is turned to a high level. It is assumed that the word line WL i is selected in Fig. 6. When the potential of the word line WL i thus goes high, the FET Q ij in the memory cell MC ij enters an ON state so that the charge stored in the capacitor C ij is transferred to the divided bit line BLL j , whereby the potential of the divided bit line BLL j exceeds the level as is equalized, i.e., (V CC - V SS )/2. Then the sense amplifier driving signals S N and S PL are turned to high and low levels, respectively, whereby the FETs Q N and Q PL enter ON states so that the N-channel sense amplifier NSA j and the P-channel sense amplifier PSA jL operate to amplify the potential difference between the paired divided bit lines BLL j and BLL j . Although noise is produced at this time as hereinabove described with reference to the prior art, no potential difference is introduced in the right-side divided bit line pair BLR j and BLR j , since the same are continuously equalized as shown in Fig. 7. Then the equalizing signal EQR goes low to stop equalization of the paired divided bit lines BLR j and BLR j . Further, the transfer signal SR again goes high so that the potentials of the divided bit lines BLL j and BLL j are transferred to the divided bit lines BLR j and BLR j , respectively. As a result, the potentials of the divided bit lines BLR j and BLR j go high and low, respectively. Then the sense amplifier driving signal S PR goes low and the FET Q PR enters an ON state so that the P-channel sense amplifier PSA jR operates to raise the potential of the divided bit line BLR j to a higher level. Then the column selecting signal Y j goes high and the potentials of the divided bit lines BLR j and BLR j are transferred to the bus lines BU and BU , whereby the data "1" stored in the capacitor C ij of the memory cell MC ij is read out. When the Ext. RAS signal goes high so that the DRAM enters an inactivated state, the potential of the selected word line WL i goes low and the FET Q ij enters an OFF state. Then the sense amplifier driving signal S N is turned to a low level and the signals S PL and S PR are turned to high levels. Further, the equalizing signals EQL and EQR and the transfer signals SL and SR are turned to high levels, whereby the divided bit lines BLL j , BLL j and BLR j , BLR j are equalized and the respective potentials thereof are averaged to the level of (V CC - V SS )/2, while the divided bit lines are connected with each other at the same time. Fig. 8 shows the structure of circuits for producing the control signals as shown in Figs. 6 and 7. Referring to Fig. 8, description is now made on the circuits for producing the control signals. A word line driving signal WL i is produced by a row decoder 53. This row decoder 53 decodes a row address from an address buffer 54 to make the potential of a selected word line rise in response to output from a delay circuit 71. The delay circuit 71 delays the clock signal R AS by a time t₃ and outputs the same. Thus, the word line driving signal WL i rises after a lapse of the time t₃ from falling of the clock signal RAS . The NMOS sense amplifier driving signal S N is produced by a sense amplifier activating circuit 72. The sense amplifier activating circuit 72 is formed by a buffer which receives output from a delay circuit 73 for delaying the word line driving signal WL i by a time t₄ to waveform-shape the same. Thus, the sense amplifier driving signal S N rises after a lapse of the time t₄ from rising of the word line driving signal WL i . The equalizing signal EQL is produced by a left bit line equalizing circuit 74. The left bit line equalizing circuit 74 is activated by a block selecting address (or row address) from an address buffer 54 to generate a signal which enters an inactivated state ("L" level) in response to either output from a delay circuit 75 or 76. The delay circuit 75 delays the clock signal RAS by a time t₂ to output the same. The delay circuit 76 delays the sense amplifier driving signal S N by a time t₉ to output the same. The left bit line equalizing circuit 74 generates a signal for stopping equalization (signal of "L" level) in response to the output of the delay circuit 75 when a row address designates a word line in a left memory block while otherwise generating a signal for stopping equalization in response to the output of the delay circuit 76. The equalizing signal EQR is produced by a right bit line equalizing circuit 77. The right bit line equalizing circuit 77 is similar in structure to the left bit line equalizing circuit 74, and generates a signal which enters an inactivated state ("L" level) in response to either output from the delay circuit 75 or 76 and to a row address (block selecting address). The transfer signal SL is generated by a left transfer signal generation circuit 78. The left transfer signal generation circuit 78 is activated on the basis of a row address signal to generate a signal which falls in response to output from a delay circuit 79 while rising in response to output from a delay circuit 80. The delay circuit 79 delays the clock signal RAS by a time t₁ to output the same. The delay circuit 80 delays the sense amplifier driving signal S N by a time t₆ to output the same. The left transfer signal generation circuit 78 is inactivated when a word line designated by the row address is included in a left memory block and is activated in other case. The transfer signal SR is generated by a right transfer signal generation circuit 81. The right transfer signal generation circuit 81 is similar in structure to the left transfer signal generation circuit 78, and generates, in response to a row address signal (block selecting address), a signal which falls in response to the output from the delay circuit 79 while rising in response to the output from the delay circuit 80. The left PMOS sense amplifier driving signal S PL is generated by a left PMOS sense amplifier activating circuit 82. The left PMOS sense amplifier activating circuit 82 generates, in response to a row address (or block selecting address), a signal which enters an activated state ("L" level) in response to either output from a delay circuit 83 or 84. The delay circuit 83 delays the sense amplifier driving signal S N by a time t₇ to output the same. The delay circuit 84 delays the sense amplifier driving signal S N by a time t₅ to output the same. The left PMOS sense amplifier activating circuit 82 generates a signal which enters an activated state in response to the output from the delay circuit 84 when the row address designates a word line in a left block while generating a signal which enters an activated state in response to the output from the delay circuit 83 in other case. The right PMOS sense amplifier driving signal S PR is generated by a right PMOS sense amplifier activating circuit 85. The right PMOS sense amplifier activating circuit 85 is similar in structure to the left PMOS sense amplifier activating circuit 85, and generates, on the basis of a row address (or block selecting address), a signal which enters an activated state ("L" level) in response to either output from the delay circuit 83 or 84. The column selecting signal Y j is generated by a column decoder 67. The column decoder 67 decodes a column address from the address buffer 54 to select a column decoder output line connected to a pair of bit lines and make the selected output line go high in response to output from a delay circuit 86. The delay circuit 86 delays the sense amplifier driving signal S N by a time t₈ to output the same. With the aforementioned structure, the control signals respectively having predetermined delay times are generated from falling of the clock signal RAS which in turn serves as a basic clock signal. Although the aforementioned embodiment is in the so-called shared sense amplifier structure of sharing an N-channel sense amplifier with left and right divided bit line pairs, N-channel sense amplifiers NSA jL and NSA jR and P-channel sense amplifiers PSA jL and PSA jR may be provided for respective memory cell array blocks MCB j3 and MCB j4 as shown in Fig. 9. In this case, switching means may be formed only by transfer gate FETs Q j17 and Q j18 . Description is briefly made of operation of the circuit as shown in Fig. 9 for reading data "1" stored in a memory cell MC ij with reference to Fig. 10 showing an operating waveform diagram thereof. When an Ext. RAS signal goes low, a transfer signal SR and an equalizing signal EQL for equalizing the left-side divided bit line pair are turned to low levels. Then, a word line WL i selected by a row address signal is turned to a high level. Then sense amplifier driving signals S NL and S PL sequentially go high and low, whereby the sense amplifiers NSA jL and PSA jL sequentially operate to amplify the potential difference between divided bit lines BLL j and BLL j . Then an equalizing signal EQR for equalizing the right-side divided bit line pair goes low to stop equalization. Then the transfer signal SR again goes high to transfer the potentials of the divided bit lines BLL j and BLL j to the divided bit lines BLR j and BLR j . Then the sense amplifier driving signals S NR and S PR sequentially go high and low, whereby the sense amplifiers NSA jR and PSA jR sequentially operate to amplify the potential difference between the divided bit lines BLR j and BLR j . Then a column selecting signal Y j goes high so that the potentials of the divided bit lines BLR j and BLR j are transferred to bus lines BU and BU , whereby the data is read out from the memory cell. Fig. 11 illustrates the structure of circuits for producing the control signals as shown in Figs. 9 and 10. A word line driving signal WL i is produced by a row decoder 100. The row decoder 100 decodes an internal row address from an address buffer 101 to select a single word line, thereby to make the potential of the selected word line rise in response to output from a delay circuit 102. The delay circuit 102 delays the clock signal RAS by a time t 3a to output the same. The sense amplifier driving signal S NL is produced by a left NMOS sense amplifier activating circuit 103. The left NMOS sense amplifier activating circuit 103 generates, on the basis of a row address (or block selecting address), a signal which rises in response to either output from a delay circuit 104 or 105. The delay circuit 104 delays the word line driving signal WL i by a time t₄ to output the same. The delay circuit 105 delays a previously rising one of the driving signals S NL and S NR by a time t₁₀ to output the same. The sense amplifier driving signal S NR is produced by a right NMOS sense amplifier activating circuit 106. The right sense amplifier activating circuit 106 is similar in structure to the left sense amplifier activating circuit 103. On the basis of a row address (or block selecting address), the right sense amplifier activating circuit 106 generates a signal which rises in response to either output from the delay circuit 104 or 105. Each of the activating circuits 103 and 106 makes its signal rise in response to the output of the delay circuit 104 when the row address (or block selecting address) designates a corresponding block, while making its signal rise in response to the output from the delay circuit 105 in other case. The transfer signal TR is produced by a transfer circuit 107. The transfer circuit 107 generates a signal which falls in response to output from a delay circuit 108 while rising in response to output from a delay circuit 109. The delay circuit 108 delays the clock signal RAS by a time t₁ to output the same. The delay circuit 109 delays a previously rising one of the output signals from the activating circuits 103 and 106 by a time t 6a to output the same. The equalizing signals EQL and EQR are produced by left and right bit line equalizing circuits 109 and 110, respectively. Each of the bit line equalizing circuits 109 and 110 generates a signal which falls in response to either output from a delay circuit 111 or 112. Namely, each of the bit line equalizing circuits 109 and 110 makes its signal fall in response to the output from the delay circuit 111 when the row address designates a corresponding block while making its signal fall in response to the output from the delay circuit 112 in other case. The delay circuit 111 delays the clock signal RAS by a time t 2a to output the same. The delay circuit 112 delays a previously rising one of the driving signals S NL and S NR by a time t₉ to output the same. The PMOS sense amplifier driving signals S PL and S PR are produced by left and right sense amplifier activating circuits 113 and 114, respectively. Each of the sense amplifier activating circuits 113 and 114 generates, on the basis of a row address (block selecting address), a signal which falls in response to either output from a delay circuit 115 or 116. Namely, each of the sense amplifier activating circuits 113 and 114 makes its signal fall in response to the output from the delay circuit 115 when the row address designates a corresponding block, while making its signal fall in response to the output from the delay circuit 116 in other case. The delay circuit 115 delays a previously rising one of the driving signals S NL and S NR by a time t₅ to output the same. The delay circuit 116 delays a subsequently rising one of the driving signals S NL and S NR by a time t₅ to output the same. The column selecting signal Y j is produced by a column decoder 117. The column decoder 117 decodes a column address from the address buffer 101 to make an output signal line connected to a pair of bit lines rise in response to output from a delay circuit 118 thereby to select a pair of bit lines. The delay circuit 118 delays a subsequently rising one of the sense amplifier driving signals S NL and S NR by a time t₁₁ to output the same. Although the bit line pair is divided into two bit line pairs in each of the aforementioned embodiments, the same may be divided into a larger number of bit line pairs while providing equalizing FETs for the respective divided bit line pairs so that timings for stopping equalization are made different for each of the divided bit line pairs, as shown in Fig. 12. As hereinabove described, the timings for inhibiting equalization of the divided bit line pairs are made different for each of the memory cell array blocks, thereby to prevent increase in sensing time by potential difference introduced in each divided bit line pair due to noise resulting from a sensing operation in another memory cell block. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A dynamic random access memory comprising: a multiplicity of memory cells (MC ij ); a plurality of word lines (WL i ) each connected to a respective row (i) of the memory cells (MC ij ); a plurality of paired bit-lines each connected to a respective column (j) of the memory cells (MC ij ), each pair of bit-lines being divided into a plurality of sections (BLL j , BLL j ; BLR j , BLR j ) each comprised of a pair of bit-line portions amplifying means (PSA jL & NSA j , NSA j & PSA jR ) provided for each section (BLL j , BLL j ; BLR j , BLR j ) for sensing and amplifying a difference in the potentials of the respective bit-line portions equalizing means (Q j9 , Q j10 ) provided for each section (BLL j , BLL j ; BLR j , BLR j ) for equalising the potentials of the respective bit-line portions switching means (Q j11 to Q j16 ) arranged for coupling together the plurality of sections (BLL j , BLL j ; BLR j , BLR j ) of each pair of bit-lines and for connecting each pair of bit-lines to a read-out output (BU, BU ) of the memory; and timing control means (fig. 8; fig.11) for controlling the operations of said equalising means (Q j9 , Q j10 ), said amplifying means (PSA jL & NSA j , NSA j & PSA jR ), and said switching means (Q j11 to Q j16 ); which memory is characterised in that: said timing control means (fig. 8; fig.11) is operable to control operation of said amplifying means (PSA jL & NSA j , NSA j & PSA jR ) and said equalising means (Q j9 , Q j10 ) such that the amplifying means (PSA jL & NSA j ) of one section (BLL j , BLL j ) of a bit-line pair is activated to sense and amplify the difference in the potentials of the respective bit-line portions thereof while the equalisation means (Q j10 ) of the other sections (BLR j , BLR j ) of the bit-line pair operates so that the potentials of the respective bit-line portions are maintained equal. A memory (fig.12) as claimed in claim 1 wherein: said plurality of sections exceeds two in number; and said timing control means is operable to control said equalising means (EQ₁, EQ₂, EQ₃) such that the potential equalisation of each section is inhibited in a controlled time sequence respectively to follow the sensing and amplifying commenced in another of the plurality of sections. A memory according to either preceding claim wherein: said timing control means is operable to control each equalising means (Q j9 , Q j10 ) so that each shall inhibit the potential equalisation of its respective section (BLL j , BLL j ; BLR j BLR j ) immediately preceding the operation of the respective switching means (Q j13 & Q j14 , Q j11 & Q j12 ) to couple in said respective section (BLL j , BLL j ; BLR j , BLR j ), and control the operation of the amplifying means (PSA jL & NSA j , NSA j & PSA jR ). A memory (fig.6) as claimed in any preceding claim wherein: the sections (BLL j , BLL j ; BLR j , BLR j ) of each pair of bit-lines are paired; said amplifying means (PSA jL & NSA j , NSA j & PSA jR ) provided for each section (BLL j , BLL j ; BLR j , BLR j ) includes a shared amplifier (NSA j ) in line between each respective pair of sections (BLL j , BLL j ; BLR j , BLR j ); and said switching means (Q j11 to Q j16 ) includes respective pairs of switches (Q j11 & Q j12 , Q j13 & Q j14 ) located each side of each shared amplifier (NSA j ). A memory (figs. 6 & 9) as claimed in any preceding claim wherein: the respective amplifying means (PSA jL & NSA j , NSA j & PSA jR ; PSA jL & NSA jL , NSA jR & PSA jR ) of each section (BLL j , BLL j ; BLR j , BLR j ) includes both an amplifier (NSA j ; NSA jL , NSA jR ) formed of N-channel FET's (Qj 1 , Q j2 ; Q j1 to Q j4 ) and an amplifier (PSA jL , PSA jR ) formed of P-channel FET's (Q j5 & Q j6 , Q j7 & Q j8 ). A memory as claimed in claim 5 wherein said equalising means (Q j9 , Q j10 ) provided for each section (BLL j , BLL j ; BLR j , BLR j ) comprises an N-channel FET. A memory as claimed in either of claims 5 or 6 wherein: said switching means (Q j11 to Q j16 ) comprises N-channel FETs. A memory as claimed in claim 1 wherein only one section (BLR j , BLR j ) of each pair of bit-lines is arranged adjacent to said read-out output (BU, BU ) of said memory. A memory as claimed in claim 1 wherein said timing control means (fig.8) includes means (53,71-73, & 78-81) for controlling said switching means (Q j11 to Q j14 ) to interrupt the connection of adjacent sections (BLL j , BLL j ; BLR j , BLR j ) of each pair of bit-lines for an interval of time (t₃+t₄+t₆) starting at a point in time following receipt of an external row address signal ( RAS ) and ending at a point in time following the commencement of sensing and amplifying in one (BLL j , BLL j ) of said adjacent sections (BLL j , BLL j ; BLR j , BLR j ). A memory as claimed in claim 1 wherein said one section (BLL j , BLL j ) is immediately adjacent to said another section (BLR j , BLR j ). A method of reading data stored in a memory cell (MC ij ) of a dynamic random access memory (fig.6), which memory comprises paired bit-lines each divided into sections (BLL j , BLL j ; BLR j , BLR j ), said method being performed by: addressing the memory cell (MC ij ) to create a potential difference across the section (BLL j , BLL j ) to which it is connected; sensing and amplifying said potential difference; coupling said section (BLL j , BLL j ) to the one or more other sections (BLR j , BLR j ) of the pair of bit-lines containing said section (BLL j , BLL j ) the potentials of said one or more other sections (BLR j , BLR j ) previously being equalised, and sensing and amplifying a potential difference across each of said one or more other sections (BLR j , BLR j ); and coupling said pair of bit-lines to a read-out output (BU, BU ) of the memory; this method being characterised in that: sensing and amplifying is commenced in one section (BLL j , BLL j ) of said pair of bit-lines while the potentials of said one or more other Sections (BLR j , BLR j ) of the pair of bit-lines are maintained equal. A method as claimed in claim 11 wherein the potential equalisation in said other sections (BLR j , BLR j ) is inhibited to immediately precede the commencement of sensing and amplifying in said other sections (BLR j & BLR j ). A method as claimed in either of claims 11 or 12 wherein sensing and amplifying is commenced in one section (BLL j , BLL j ) while the potentials of an adjacent section (BLR j , BLR j ) are maintained equal.

Inventors: MIYAMOTO, HIROSHI C/O MITSUBISI DENKI K.K. LSI, YAMADA, MICHIHIRO C/O MITSUBISHI DENKI K.K.LSI
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1987
Main classification: G11C11
IPC codes: G11C11