MEMORY CELL CIRCUIT

Abstract: A memory cell circuit has a pair of transistors (M1, M2) in which the gates are connected to the drains, a first and a second access transistor (M3, M4) whose gates are connected to a read line (WL) and which are located between gate-drain connections of said pair of transistors and a pair of bit lines (BL1, BL2). The memory cell circuit also includes a third access transistor (M5) whose gate is connected to the read line (WL) and is located in the circuit between said first access transistor (M3) and the gate of said pair of transistors corresponding to the first access transistor (M3), and a fourth access transistor (M6) whose gate is connected to the read line (WL) and is located in the circuit between said second access transistor (M4) and the gate of said pair of transistors corresponding to the second access transistor.

Description: The present invention relates generally to memory cell in a semiconductor integrated circuit. More specifically, the invention relates to a memory cell forming a semiconductor memory, such as a DRAM or the like. So called gain cells, such as DRAMs, which are composed of 4 transistors have been proposed, cf. eg. Hewlett-Packard Journal, Vol. 34, no. 8, August 1983, pages 20-24. In the known art, a memory cell circuit has a pair of memory transistors. The memory transistors are cross-coupled between their gates and drains. The memory transistors also have sources which are grounded in common. First and second access transistors are connected between gate-drain connections of the memory transistors and bit lines. The first and second access transistors have gates connected to a word line. In the above described memory cell circuit, the first access transistor and the second access transistor are responsive to a selection signal input to the gates via the word line to perform a switching operation. By this switching operation of the access transistors, ON/OFF control of the memory transistors is carried out. Also, by the switching operation of the access transistors, output of the memory transistors to the bit lines are controlled. However, in the above described memory cell circuit, there is a problem with channel leak between the transistors. That is, when channel leak occurs on the memory transistor and/or the access transistor, the charge level at the gate of the memory transistor tends to be lowered. The can cause a change in the stored data. On the other hand, a substantial level of noise can be superimposed on the signal on the bit lines. In this case, when the data is read from the above described memory cell circuit, the data stored in the gate of each memory transistor can be toggled (and thereby corrupted) by the substantial level of noise, which inverts the stored information. Moreover, nowadays, there is strong pressure to shorten the access time of integrated circuits, such as DRAMS and so forth. Therefore, it is an object of the present invention to provide an improved memory cell circuit which realizes improvements in data holding characteristics and enables quicker access operations. According to the present invention, there is provided a memory cell circuit characterised in that it comprises: first and second bit lines for transferring data therethrough; a word line through which, in use, a selection signal passes; first and second memory transistors having gates for storing data, drains, and sources which are grounded in common; first means for connecting said drain of said first memory transistor to said gate of second memory transistor; second means for connecting said drain of said second memory transistor to said gate of said first memory transistor; third means connecting said first means to said first bit line, said third means incorporating a first access transistor and being connected to said word line to receive said selection signal to be responsive to said selection signal to be switched into the conductive state; fourth means connecting said second means to said second bit line, said fourth means incorporating a second access transistor and being connected to said word line to receive said selection signal to be responsive to said selection signal to be switched into conductive state; a third access transistor connected to said word line to be switched into the conductive state in response to said selection signal, said third access transistor being connected in series between said first access transistor and the gate of the second memory transistor in such a manner as to suppress channel leak of the potential in said first means; a fourth access transistor connected to said word line to be switched into the conductive state in response to said selection signal, said fourth access transistor being connected in series between said second access transistor and the gate of the first memory transistor in such a manner as to suppress channel leak of the potential in said second means. In general, the value of the channel leak current I (leak) can be illustrated by: I (leak) ∝ exp (Vds) where Vds is the voltage between the drain and source. In a memory cell circuit of the invention, the third access transistor and the fourth access transistor as well as the first access transistor and the second access transistor are located between the gates of the pair of transistors and their bit lines, so that Vds can be divided; therefore, the channel leak is successfully reduced or eliminated. If respective drains in the pair of memory transistors are connected to connections, one of which is connected between the first and third access transistors and the other of which is connected between the second and fourth access transistors, the drains of the respective memory transistors are connected to respective bit lines via the respective first and second access transistors which are located near the bit lines when reading, amplification occurs. At that time, the gates of respective memory transistors holding information signals are connected to said connections via the respective ones of the third and fourth access transistors, so that the information signals which are held in the memory transistors cannot possibly be destroyed and can be correctly output. If the drain of one of the pair of memory transistors is connected to the connection between the first and third access transistor, and the drain of the other one is connected to the connection between the second and fourth access transistor, the data content can be held at a defined level at the connections and rapid read, etc can be obtained. Further, as has been described above, the channel leak can be reduced, so that the channel length can be shortened. If the channel length is shortened, speed of access can be increased. In the preferred construction, the third access transistor is disposed within the first means. It is also possible to dispose the fourth access transistor within the second means. In an alternative, the third access transistor is disposed within the third means. The fourth transistor may also be disposed with the fourth means. In order to form the aforementioned constructions of the memory cell circuit, the first and second memory transistors may comprise NMOS transistors. Further, the first, second, third and fourth access transistors may also comprise NMOS transistors. Alternatively, the first and second memory transistors may comprise PMOS transistors. Similarly, the first, second, third and fourth access transistors may comprise PMOS transistors. The present invention will be understood more fully from the detailed description given herebelow by way of non-limitative example with reference to the accompanying drawings of the preferred embodiment of the invention in which: Fig 1 is a circuit diagram which shows the structure of the memory cell circuit of the first illustrated embodiment of this invention; and Fig 2 is a circuit diagram which shows a second illustrated embodiment of the memory cell circuit structure of this invention. Referring now to the drawings, particularly to Fig 1, the first embodiment of a memory cell circuit, according to the present invention, has a pair of memory transistors M1 and M2, two pairs of access transistors M3, M4, M5 and M6. This embodiment of the memory cell circuit is intended to accomplish improved data holding characteristics and high speed read/write operation by connecting the drains of the memory transistors M1 and M2 to junctions between series of transistors M3, M5 and M4, M6. The first embodiment of the memory cell circuit according to the invention is formed as showed in Fig 1. The pair of memory transistors M1 and M2 respectively have sources connected in common to a ground. The memory transistor M1 also has a drain which is connected to a first bit line BL1 via a first access transistor M3. On the other hand, the memory transistor M2 has a drain connected to a second bit line BL2 via a second access transistor M4. The first and second access transistors M3 and M4 have their respective gates connected to a word line WL (read line). Furthermore, each of the first and second access transistors M3 and M4 has drain connected to the corresponding one of third access transistor M5 and fourth access transistor M6. The third and fourth access transistors M5 and M6 have gates connected to the word line WL. The drains of third and fourth access transistors M5 and M6 are connected to gates of respective diagonally opposing memory transistors M1 and M2. Hereinafter, the operation of the memory cell circuit is described. When holding data, all of the access transistors M3, M4, M5 and M6 are held OFF. By this means, the gates of the memory transistors M1 and M2 storing electric charge are disconnected from respectively associated bit lines BL₁ and BL₂. As a result, the electric charge represents a data component and can be held in the gates of the memory transistors M1 and M2. When a data bit "1" (HIGH level) is stored in the gate of the memory transistor M2, the electric charge at point D, to which the potential at the drain of the memory transistor M2 is applied is necessarily held at ground (GND) level. At the same time, the electric potential of a point C is also held at GND level. Since the input at the gate is held at GND level, the memory transistor M1 is maintained in the OFF state. In this state, the point B in the memory cell circuit of Fig 1 is held at floating state because of the electric charge stored in the gate of the memory transistor M2. In the conventional memory cell circuit, channel leak from the point B when in the floating condition has caused a problem. Whereas, according to the shown embodiment, the channel leak can be successfully suppressed by providing the third access transistor M5. In order to accomplish suppression of the channel leak, the third access transistor M5 is provided in such a position that it is disposed between the points B and A, at which point A, the drain of the memory transistor M1 is connected between the drain of the first access transistor and the source of the third access transistor M5. By this means, the third access transistor M5 divides the potential between the point B and point A. As set forth above, the magnitude of the channel leak is exponentially related to the voltage at the junction (A) between the drain and the source of the transistors. Therefore, by dividing the voltage, the voltage at the drain-source connection of the transistors can be substantially reduced so that the value of the current leak can be markedly reduced. When reading data, selection signal is applied to all of the gates of the access transistors M3, M4, M5 and M6 via the wordline WL. As a result, the first to fourth access transistors M3, M4, M5 and M6 are turned ON. In response to turning ON of the first to fourth access transistors M3, M4, M5 and M6, a latching operation takes place to turn off whichever one of the memory transistors M1 and M2 has lower charge in its gate and turn the other memory transistor ON. By this operation, data to be read out can be fixed. During the aforementioned read-out operation, the noise superimposed on the signal of bit lines BL₁ and BL₂ in the prior art tends to influence to the data read-out from the memory circuit. That is, when the noise is superimposed on the data of the bit lines BL1 and BL2, an error voltage can enter the memory cell circuit. The error voltage tends to be directly applied to the gate of the memory transistor to corrupt the data stored in the gate. However, in the illustrated embodiment, the gate of the memory transistor M2 is connected to the bit line BL₁ via the access transistors M3 and M5 and the gate of the memory transistor M1 is connected to the bit line BL₂ via the access transistors M4 and M6, so that the data content of the cell is sufficiently protected by their resistances when the access transistors M3, M4, M5 and M6 are held ON. Moreover, in the preferred embodiment of the memory cell circuit, the electric potentials at the points A and D which are connected to the drains of respective memory transistors M1 and M2, correspond to the data value stored in the memory transistors M1 and M2. Therefore, when accessing the content of the memory transistors M1 and M2, the data value can be transferred via first and second access transistors M3 and M4 via the points A and D. This is substantially equivalent to that in the memory cell circuits in the prior art. Therefore, the presence of the third and fourth access transistors M5 and M6 which suppress channel leak for better data holding ability, do not degrade the access speed of the memory cell circuit. In addition, because of the improved data holding ability, the size, ie channel length, of the access transistors can be reduced. As will be appreciated, a shorter channel length of the access transistors allows quicker access. Consequently, higher access speeds can be achieved when the channel length of the first and the second access transistors is shortened. Thus, the intervals between refresh cycles can be made longer and the power consumption can be reduced. As will be clear from the above, the illustrated embodiment of the memory cell circuit is constituted of six transistors, and has an increased number of circuit components. However, since all of the transistors constituting the memory cell circuit can be NMOS transistors which require a smaller chip area than CMOS transistors (which require a well region and so forth), the overall area occupied by the first embodiment of the memory cell circuit can be equivalent to or even smaller than that in the conventional ones. It should be appreciated that, although the illustrated embodiment of the memory cell circuit is described to be composed of the NMOS transistors, it would be possible to employ PMOS transistors to fabricate an equivalent circuit. Fig 2 shows a second embodiment of the memory cell circuit in accordance with the present invention. This second embodiment of the memory cell circuit is formed as a dual gate access transistor-type cell. This memory cell circuit has a pair of memory transistors M11 and M12; the drain of the memory transistor M11 is connected to the gate of the memory transistor M12 and the drain of the memory transistor M12 is connected to the gate of the memory transistor M11. The sources of transistors M11 and M12 are connected in common to a GND. A first and third access transistors M13 and M15 are disposed between a junction between the drain of the memory transistor M11 and the gate of the memory transistor M12, and the bit line BL₁. Likewise, second and fourth access transistors M14 and M15 are disposed between a junction between the drain of the memory transistor M12 and the gate of the memory transistor M11, and the bit line BL₂. Similarly to the foregoing first embodiment, the memory transistors M11 and M12 and the first, second, third and fourth transistors M3, M4, M5 and M6 comprise NMOS transistors. Even with the construction of the second embodiment set forth above, an equivalent effect in terms of suppressing channel leak and achieving high speed access can be achieved as compared with the first embodiment. Though the shown embodiment employs NMOS transistors, it would also be possible to employ PMOS transistors instead. As set forth above, the memory cell transistor of this invention is provided with the third and the fourth access transistors. Therefore, channel leak can be reduced exponentially and improvement of the data holding characteristics can be achieved. In a memory cell transistor, which comprises connections to the drains of a pair of transistors, one of the connections is connected between the first access transistor and the second access transistor and the other connection is connected between the third access transistor and the fourth access transistor, loss of data due to an error voltage can be prevented and a rapid access operation can be achieved with reduced power consumption in the refresh cycle of the memory cell circuit. While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding of the invention, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modifications to the shown embodiments within the scope of the invention set out in the appended claims.

Claims: A memory cell circuit comprising: first and second bit lines (BL1, BL2) for transferring data therethrough; a word line (WL) through which, in use, a selection signal passes; first and second memory transistors (M1, M2; M11, M12) having gates for storing data, drains, and sources which are grounded; first means for connecting said drain of said first memory transistor (M1; M11) to said gate of said second memory transistor (M2; M12); second means for connecting said drain of said second memory transistor to said gate of said first memory transistor; third means (M3; M13, M15) connecting said first means to said first bit line (BL1), said third means incorporating a first access transistor (M3; M13) and being connected to said word line (WL) to receive said selection signal to be responsive to said selection signal to be switched into the conductive state; fourth means (M4; M14, M16) connecting said second means to said second bit line (BL₂), said fourth means incorporating a second access transistor (M4; M14) and being connected to said word line (WL) to receive said selection signal to be responsive to said selection signal to be switched into conductive state; characterized by further comprising : a third access transistor (M5; M15) connected to said word line (WL) to be switched into the conductive state in response to said selection signal, said third access transistor (M5; M15) being connected in series between said first access transistor (M3; M13) and the gate of the second memory transistor (M2, M12) in such a manner as to suppress channel leak of the potential in said first means; a fourth access transistor (M6; M16) connected to said word line (WL) to be switched into the conductive state in response to said selection signal, said fourth access transistor (M6; M16) being connected in series between said second access transistor (M4; M14) and the gate of the first memory transistor (M1, M11) in such a manner as to suppress channel leak of the potential in said second means. A memory cell circuit as set forth in claim 1, wherein said third access transistor (M5) is disposed within said first means. A memory cell circuit as set forth in claim 1 or 2, wherein said fourth access transistor (M6) is disposed within said second means. A memory cell circuit as set forth in claim 1, wherein said third access transistor (M15) is disposed within said third means. A memory cell circuit as set forth in claim 1 or 2, wherein said fourth access transistor (M16) is disposed within said fourth means. A memory cell circuit as set forth in any one of claim 1 to 5, wherein said first and second memory transistors (M1, M2; M11, M12) each comprise an NMOS transistor. A memory cell circuit as set forth in any one of claims 1 to 6, wherein said first, second, third and fourth access transistors (M3-M6; M13-M16) each comprise an NMOS transistor. A memory cell circuit as set forth in any one of claims 1 to 5, wherein said first and second memory transistors (M1, M2; M11, M12) each comprise a PMOS transistor. A memory cell circuit as set forth in any one of claims 1 to 5 and 8, wherein said first, second, third and fourth access transistors (M3-M6; M13-M16) each comprise a PMOS transistor.

Inventors: SONEDA, MITSUO
Applicants: SONY CORPORATION
Application year: 1987
Main classification: G11C11
IPC codes: G11C11