Digital-to-analog conversion system

Abstract: A digital-to-analog conversion system including: a code conversion circuit for converting an input binary code to a three states code; the code conversion circuit designating each digit from one digit lower than a most significant digit to a least significant digit; when a designated digit and both lower and upper digits thereof are the same, a corresponding digit of the three states code is set to a first state, except for the above case, the designated digit is inverted, and when the upper digit of the designated digit is "0", the corresponding digit of the three states code is set to a second state, and when the digit lower than said designated digit is "l", the corresponding digit of the three states code is set to a third state, and a digital-to-analog conversion means connected to the code conversion and controlled by the three states code for outputting an analog value.

Description: The present invention relates to a digital-to-analog conversion apparatus and method. Conversion of a digital code to an analog value is usually performed in the field of measurements. In general, to meet the necessary requirements, the conversion circuit must be capable of a high conversion speed, high resolution, satisfactory differential linearity, and low power consumption. Digital-to-analog conversion circuits employing, for example, an R-2R ladder type conversion or a 2 n weighting resistance type conversion, both of which use a resistance circuit network, are known. In these conventional types of conversion, a binary code, for example, a 2's complement binary code, is usually used to convert a digital code to an analog value, but in this case, problems arise because a so-called "differential non-linearity error" becomes very large in some digits during the conversion, as explained in detail hereinafter. It is desirable to provide a digital-to-analog conversion system enabling a high speed and precise conversion by employing an improved three states code method in which it is possible to reduce the differential non-linearity error. GB-A-2 077 536 and GB-A-2 152 310 disclose digital to analog converters in which a binary input code is converted to a three-states (ternary) code so as to reduce the differential non-linearity error. According to a first aspect of the present invention, there is provided a digital-to-analog conversion circuit comprising:- a code conversion means arranged to convert an input binary code (d₀ to d n ) to a three states code (a₁ to a n ); and a digital-to-analog conversion means connected to said code conversion means and controlled by said three states code (a₁ to a n ), for outputting an analog value corresponding to the input binary code (d₀ to d n ); the input binary code consisting of digits d₀ to d n , the digit d₀ being the most significant digit, and the digit d n being the least significant digit; the three states code consisting of digits a₁ to a n , the digit a₁ being the most significant digit, and the digit a n being the least significant digit, the digits having a binary weighting and taking any of the values "-1", "0" and "1"; characterised in that said code conversion means is operable as follows:- when d₀ = 0:- (a) when digits d₁ to d i = "1" (1 ≦ i ≦ n), said code conversion means is arranged to set corresponding digits of the three states code a₁ to a i = "1"; (b) when digits d i to d j = "1" (2 ≦ i ≦ j ≦ n) and d i-1 = 0, d j+1 (if any) = 0, said code conversion means is arranged to set the three states code corresponding to these digits to a i-1 = 1, and a j = -1, and if j > i, a i to a j-1 = 0; (c) for other digits of the binary code, said code conversion means is arranged to set the corresponding three states code to a i = 0; when d₀ = 1:- (1) when digits d₁ to d i = 0 and d i+1 to d j = 1 (1 ≦ i < j ≦ n), said code conversion means is arranged to set corresponding digits of the three states code to a₁ to a i = -1, a j = -1, and if (j-i) > 2, a i+1 to a j-i = 0; (2) in the remaining digits, when d k to d L = 1 (1 ≦ k ≦ l ≦ n), said code conversion means is arranged to set corresponding digits of the three states code to a k-1 (if any) = 1, a L = -1, and if L > k, a k to a L-1 = 0; (3) for other digits of the binary code, said code conversion means is arranged to set the corresponding three states code to a i = 0. According to a second aspect of the present invention, there is provided a method for converting a binary code to an analog value, comprising the steps of :- code-converting said binary code to a three states code; and converting said three states code to said analog value based on a sequential output; the input binary code consisting of digits d₀ to d n , the digit d₀ being the most significant digit, and the digit d n being the least significant digit; the three states code consisting of digits a₁ to a n , the digit a₁ being the most significant digit, and the digit a n being the least significant digit, the digits having a binary weighting and taking any of the values "-1", "0" and "1"; characterised in that said code conversion step is performed as follows:- when d₀ = 0:- (a) when digits d₁ to d i = "1" (1 ≦ i ≦ n), corresponding digits of the three states code a₁ to a i are also set to "1"; (b) when digits d i to d j = "1" (2 ≦ i ≦ j ≦ n) and d i-1 = 0, d j+1 (if any) = 0, the three states code corresponding to these digits are determined as a i-1 = 1, and a j = -1, and if j > i, a i to a j-1 = 0; (c) for other digits of the binary code, the corresponding three states code is set to a i = 0; when d₀ = 1:- (1) when digits d₁ to d i = 0 and d i+1 to d j = 1 (1 ≦ i < j ≦ n), corresponding digits of the three states code are determined as a₁ to a i = -1, a j = -1, and if (j-i) > 2, a i+1 to a j-1 = 0; (2) in the remaining digits, when d k to d L = 1 (1 ≦ k ≦ l ≦ n), corresponding digits of the three states code are determined as a k-1 (if any) = 1, a L = -1, and if L > k, a k to a L-1 = 0; (3) for other digits of the binary code, the corresponding three states code is set to a i = 0. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a schematic block diagram of a conventional digital-to-analog converter; Fig. 2 shows one example of digital-to-analog conversion based on a conventional 2's complement binary code; Fig. 3 shows differential non-linearity errors based on a conventional method; Fig. 4 shows differential non-linearity errors based on a step graph; Fig. 5 is a schematic block diagram of a digital-to-analog conversion using the three states code; Fig. 6 shows one example of digital-to-analog conversion based on the three states code; Fig. 7 shows differential non-linearity errors based on the three states code; Fig. 8 shows the code conversion of the three states code according to the present invention; Fig. 9 is a flowchart of the process of a code conversion from the 2's complement binary code to the three states code embodying the present invention; Fig. 10 is a detailed block diagram of a code conversion circuit used to carry out the process shown in Fig. 9; Fig. 11 is a block diagram showing the connection of the code conversion circuit shown in Fig. 10; Fig. 12 shows the relationship between control commands and the three states code; Fig. 13 is a schematic block diagram of a digital-to-analog conversion system embodying the present invention; Fig. 14 is a timing chart of the basic operation of the system shown in Fig. 13; Figs. 15 and 16 are detailed circuit diagrams of the D/A conversion circuit shown in Fig. 13; Fig. 17 is a detailed block diagram of the control circuit shown in Fig. 13; and, Fig. 18 shows one example of a code conversion from the 2's complement binary code to the three states code. Before describing the preferred embodiments, an explanation will be given of a conventional digital-to-analog conversion method, with reference to Figs. 1 to 4. In Fig. 1, a digital-to-analog conversion circuit D/A is usually constituted by a R-2R ladder-type resistance circuit (not shown) or a 2 n weighting resistance-type circuit (not shown), and an operational amplifier (not shown). V ref is a reference voltage and is input to the resistance network, and D₀ to D₃ are digits of the digital code to be converted to the analog value and input to the resistance circuit through corresponding switches (not shown). Each digit is weighted by a predetermined weighed value, and the analog value V out can be obtained by calculating the sum of these weighted values multiplied by the reference voltage through the operational amplifier. The list in Fig. 2 shows one example of digital-to-analog conversion of four digits D₀ to D₃ , as expressed by the binary code, for example, the 2's complement binary code. For example, the digital code "1 0 1 0" is converted to the analog value "- 6 / 8·V ref " by the following calculations: = -V ref x 1 + 1 2 ·V ref x 0 + 1 4 ·V ref x 1 + 1 8 ·V ref x 0 = -V ref + 1 4 ·V ref = - 3 4 ·V ref = - 6 8 #CDT#V ref A problem arises, however, in a major carry portion, in which almost all digits are inverted to opposite digits, for example, "1 1 1 1" → "0 0 0 0", and "0 0 1 1" → "0 1 0 0". In the major carry portion, the difference between each of the digits is only 1 LSB (least significant bit) (that is, 1 / 8·V ref as an analog value) as shown in Fig. 3. However, each digit contains a voltage error (e₀ to e₃) caused by an electrical dispersion of each resistance value constituting the resistance circuit, and thus the weighted analog value also contains these errors at every digit when converted. Therefore, the converted analog value becomes 1 8 ·V ref - (e₀ + e₁ + e₂ + e₃) . The sum of these errors (e₀ + e₁ + e₂ + e₃) is called a "differential non-linearity error". As is obvious from Fig. 2, the major carry occurs in the two portions shown by dotted lines, and the differential non-linearity error has the largest value in these portions. In this case, each step between each digit is moved away from 1 LSB, as shown in Fig. 4. In Fig. 4, the ordinate shows the analog value and the abscissa a digital code value. These steps indicates the data when e₀ = e₁ = 0 and e₂ , e₃ < 0 (absolute value |e₂|, |e₃| > 0). As is obvious from these steps, when the digital code value "-4" is changed to "-5", the step of the analog output becomes small, and when the digital code value "0" is changed to "-1", the step of the analog output becomes large. Thus, it is obvious that the larger the deflection of the step, the larger the error in the differential linearity. In one proposed converter, the three states code is used for analog-to-digital conversion as a cyclic A/D conversion. However, in this method, when the three states code as above is merely employed at a D/A converter shown in Fig. 5, the following problem occurs upon a conversion. That is, in this method, the major carry occurs in the two portions shown by dotted lines in Fig. 6. Therefore, the same problem arises in this three states code as in the 2's complement binary code, as shown in Fig. 7. That is, the converted analog value contains large differential non-linearity errors (e₂ - e₁ - e₀), for the same reasons. In this case, the largest errors can be given by the sum of each absolute value |e₀| + |e₁| + |e₂|, as there are plus and minus values in each error. In Fig. 5, each of digits D₀ to D₃ can have three states; 1, 0, and -1. Therefore, two signal lines per each digit are necessary to handle the above three states. A digital-to-analog conversion system embodying the present invention will be explained in detail hereinafter. In Fig. 8, when the three states code is employed, it is possible to express the analog value by three kinds of digital codes so that the difference of the differential non-linearity error is shown under various expressions 1 ○ to 3 ○ of the digital code. In the three states code, for example, the digital code corresponding to the code value (decimal) "3" can be expressed in three forms, i.e., "0 1 1", "1 -1 1", and "1 0 -1". That is, three kinds of digital codes "0 1 1" (2² x 0 + 2¹ x 1 + 2⁰ x 1 = 3), "1 -1 1" (2² x 1 - 2¹ x 1 + 2⁰ x 1 = 3), and "1 0 -1" (2² x 1 + 2¹ x 0 - 2⁰ x 1 = 3) are equal to the code value "3". In the carry from the code value "3" to "4" (i.e., "1 0 0"), the sum of each error becomes "e₂ - e₁ - e₀" in the first form 1 ○ , e₁ - e₀" in the second form 2 ○ , and "e₀" in the third form 3 ○. This is because all digits are inverted to the opposite digits in the first form 1 ○, but only one digit is inverted to the opposite digit in the third form 3 ○. In this case, the largest value is given by each absolute value, that is, |e₂| + |e₁| + |e₀| in the first form 1 ○, |e₁| + |e₂| in the second form 2 ○, and |e₀| in the third form 3 ○. Accordingly, it is possible to reduce the differential non-linearity error if the digital code of the third form is employed as the three states code. The digital-to-analog conversion system embodying the present invention uses the three states code to obtain a digital code having the above third form, as explained in detail hereinafter. The flowchart in Fig. 9 shows the code conversion process from the 2's complement binary code to the three states code embodying the present invention. In the present invention, the digital code by the 2's complement binary code applied from an external stage is converted to another type of digital code by the three states code using a SRT division method by a divisor "1", or an equivalent method thereto. An SRT division method is a known method proposed by SWEENEY, ROBERTSON and TOCHER, but, in the present invention, the digital code is converted to the analog value through the another type digital code obtained by the SRT division by the divisor "1", or an equivalent method. That is, the code conversion is performed in such a way that each digit of the 2's complement binary code is divided by "1", and the resultant new digit is used in the three states binary code. In the flowchart, "d i " represents an optional digit. Therefore, d₀ is an MSB (most significant bit), d₁ is a next lower digit, and d n is an LSB (least significant bit). In the present invention, the process is started from i = 1, i.e., the next lower digit from the MSB (step 1) and is completed when i > n (step 9). In step 2, when d i-1 = "0", i.e., d₀ (MSB) = "0", it is determined whether or not the next lower digit d i or d i+1 is "1". When d i or d i+1 = "1", the MSB of the three states code a i becomes "1" (step 3). This signifies that the analog value converted from the digital code is larger or smaller than " 1 / 4" of the analog decision level. That is, when the result is "YES", this value is larger than " 1 / 4", and when the result is "NO", this value is smaller than " 1 / 4". In step 4, when d i-1 = "1", i.e., d₀ (MSB) = "1", it is determined whether or not the next lower digit d i or d i+1 is "0". When d i or d i+1 = "0", the MSB of the three states code a i becomes "-1" (step 5). This signifies that when the result is "YES", the analog value converted by the digital code is smaller than "- 1 / 4", and when the result is "NO", this value is larger than "- 1 / 4" These processes (steps 2 to 7) are based on the SRT division method by the divisor "1" or an equivalent method. When d i-1 = "1", and d i and d i+1 are not "0" in steps 2 and 4, the three states code a i becomes "0" at step 6. When a i = 1 and a i = -1 is obtained at steps 3 and 5, the d i is the remainder of the SRT division by the divisor "1". Note, d i is an inverted d i . Therefore, in step 7, addition or subtraction is performed between d i and d i to obtain the remainder value of the SRT division by the divisor "1" and a new three states code is obtained through the processes of steps 6 and 7. When the process "i = 1" is completed, the next process "i = i + 1" is started by the same steps 2 to 7 (step 8). This process is repeated until "i" becomes larger than "n" (step 9). As explained above, "n" is the LSB of the three states code. Figure 10 is a detailed block diagram of the circuit used for a code conversion from the 2's complement binary code to the three states code embodying the present invention. In the Figure, LI, MI, and HI represent input terminals, and digits d i+1 d i , and d i-1 of the 2's complement binary code are input from these terminals LI, MI, and HI. PO, NO and Q represent output terminals. Two kinds of control commands expressing the three states code a i are output from these terminals based on a predetermined set of PO and NO as shown in Fig. 12. The output Q is used for subtraction between d i and d i , i.e., the NAND gate 5 detects "1" at any of PO or NO. The inverted d i by the exclusive OR gate 9 is output from the terminal Q, and this output is input to the HI terminal of the next stage. As explained above, this conversion circuit comprises an OR gate 1, four NAND gates 2 to 5, three inverters 6 to 8, and an exclusive NOR gate 9. In this circuit, for example, when d i+1 = "1", d i = "0", and d i-1 = "0", an output of the OR gate 1 is "1" and the output of the NAND gate 2 is "0", thus, PO is "1", and the output of the NAND gate 3 is "1" and that of the NAND gate 4 is "1", and thus, NO is "0". As shown in Fig. 12, when PO is "1" and NO is "0", a i is "1". The block diagram in Fig. 11 shows the connection of a plurality of code conversion circuits shown in Fig. 10. Each of digits d₀ to d n denote the 2's complement binary code applied from an external stage by a user, and a₁ to a n denote three states codes inverted from digital codes. The D/A conversion system according to the present invention shown in Fig. 13 is one example applied to the cyclic D/A converter. Of course, the present invention can be applied to other types of D/A converter. In Fig. 13, CV is a digital-to-analog conversion circuit; this circuit is shown in partial detail in Figs. 15 and 16. S/H is a conventional sample and hold circuit, and CT is a control circuit constituted by a shift register and a timing generator; a partial detail diagram thereof being shown in Fig. 17. TS is a code conversion unit for converting the 2's complement binary code to the three states code; this circuit is shown in partial detail in Figs. 10 and 11, as previously explained. S4 is a switch, and G and L are terminals for the switch S4. In this case, the terminal G is connected to the ground and the terminal L is connected to the sample and hold circuit S/H. The switch S4 operates only when the initial value is set to "0". That is, when the switch S4 is connected to the terminal G, the initial value is set to "0" and thereafter, the switch S4 is always connected to the terminal L. A timing chart of the basic operation of the digital-to-analog conversion system is shown in Fig. 14. The D/A conversion circuit CV can have two states, i.e., a sampling state SMP and an outputting state OUT. The sample and hold circuit S/H also has two states, i.e., a sampling state S and a holding state H. a₁ to a n represent the three states code. In this case, the digit a₁ is the MSB and the digit a n is the LSB. A partially detailed diagram of the D/A conversion circuit D/A is shown in Figs. 15 and 16. Figure 15 shows the sampling state and Fig. 16 shows the outputting state. In Figs. 15 and 16, OP is an operational amplifier, C0 to C2 are capacitors each having an equivalent capacitance, SZ is a main switch, S1 is an input switch, S2 is a ground switch, S3 is a reference switch, IN is an input terminal, OUT is an output terminal, "ref" is an input terminal for a reference voltage V ref , VIN is an input voltage, VOT is an output voltage, and 1 to 4 and R, G are connection terminals of switches. In the sampling state as shown in Fig. 15, the switch SZ is ON, the switch S1 is connected to the terminal 2, and the switch S2 is connected to the terminal 4. In the outputting state as shown in Fig. 16, the switch SZ is OFF, the switch S1 is connected to the terminal 1, and the switch S2 is connected to the terminal 3. For sampling, the input voltage VIN is input from the input terminal IN, and for outputting, the output voltage VOT is output from the output terminal OT. In Figs. 15 and 16, the switch S3 is controlled by the control commands OP and NO from the control circuit CT. That is, the digits a i = 1, 0, -1 are used to control the switch S3. As shown in Fig. 12, the codes a i = -1, 0, -1 are determined by a set of PO and NO. As shown in the following table, in the sampling state shown in Fig. 15, when the digit a i = 1, the switch S3 is connected to the terminal R, and when the digit a i = 0 or a i = -1, the switch S3 is connected to the terminal G. In the outputting state shown in Fig. 16, when the digit a i = -1, the switch S3 is connected to the terminal R, and when the digit a i = 1 or a i = 0, the switch S3 is connected to the terminal G. In Fig. 15, when the switch S3 is connected to the terminal R, the sampling of the input voltage VIN is performed with respect to the conversion V ref as follows. switch SZ: ON switch S1: to VIN switch S2: to ground switch S3: to V ref capacitor C0: charged by V ref capacitor C1: to ground capacitor C2: charged by VIN When the switch S3 is connected to the terminal G, the sampling of the input voltage VIN is performed with respect to the conversion "0" as follows. switch SZ: ON switch S1: to VIN switch S2: to ground switch S3: to ground capacitor C0: to ground capacitor C1: to ground capacitor C2: charged by VIN With respect to the conversion "-V ref ", the sampling of the input voltage VIN is based on the same connections as the above. In Fig. 16, when the switch S3 is connected to the terminal G, the conversion of V ref is performed as follows. switch SZ: OFF switch S1: to terminal OT switch S2: to terminal OT switch S3: to ground capacitor C0: to ground capacitor C1: to terminal OT capacitor C2: charged by (VIN + V ref )/2 With respect to the conversion of "0", the procedure is based on the same connections as above. When the switch S3 is connected to the terminal R, the conversion of -V ref is performed as follows. switch SZ: OFF switch S1: to terminal OT switch S2: to terminal OT switch S3: to V ref capacitor C0: charged by V ref capacitor C1: to terminal OT capacitor C2: charged by (VIN - V ref )/2 As can be understood from the above description, three kinds of output voltages VIN/2, (VIN + V ref )/2, and (VIN - V ref )/2 are obtained from the output terminal OT. When a i = 1, 0, -1, the output voltage VOT is given as follows. VOT = (VIN + a i ·V ref )/2 For example, when the 2's complement binary code a i is "1 1 0 0 1 0 1 0" (= -54), the three states code a i becomes "-1 0 1 -1 1 -1 0" (= -54) by using the code conversion circuit shown in Figs. 10 and 11. The digital-to-analog conversion is performed as follows. Step 1; (LSB) VOT = (0 + 0·V ref )/2 = 0 a₇ Step 2; VOT = (0 + (-1)·V ref )/2 = -V ref /2 a₆ Step 3; VOT = (-V ref /2 + 1·V ref )/2 = V ref /4 a₅ Step 4; VOT = (V ref /4 + (-1)·V ref )/2 = -3/8·V ref a₄ Step 5; VOT = (-3/8·V ref + 1·V ref )/2 = 5/16·V ref a₃ Step 6; VOT = (5/16·V ref + 0·V ref )/2 = 5/32·V ref a₂ Step 7; (MSB) VOT = (5/32·V ref + (-1)·V ref )/2 = -27/64·V ref = -54/128·V ref a₁ The shift register SR shown in Fig. 17 comprises a plurality of units corresponding to digits a₁ (MSB) to a n (LSB). Each of these units is divided into NO and PO portions and "1" or "0" is stored in the NO and PO according to the list shown in Fig. 12. For example, when a i = 1, NO is "0" and PO is "1". Stored data is sequentially output from the digit a n (LSB) in response to a clock signal CLK. In this case, the control command PO is input to the switch S3 shown in Fig. 15 and the control command NO is input to the switch S3 shown in Fig. 16. That is, the control command PO is used for the sampling state and the control command NO is used for the outputting state. When the control commands PO and NO are "1", the terminal R is closed, and when the control commands PO and NO are "0", the terminal G is closed. These relationships are briefly shown in the following table. The timing generation TG generates a clock signal CLK for shifting the NO and PO in the shift register SR, and a switching signal SS for controlling the operations of the main switch SZ, the input switch S1, and the ground switch S2. The list in Fig. 18 shows one example of a code conversion from the 2's complement binary code to the three states code embodying the present invention. The major carry portions are shown by dotted lines in the 2's complement binary code, and the differential non-linearity error is large, as previously explained. That is, the major carry portions occur in "0", "+FS/2", and "-FS/2" (where; FS is full scale). Conventionally, the maximum errors occur in these portions, but these errors are eliminated in these portions in the present invention.

Claims: A digital-to-analog conversion circuit comprising:- a code conversion means (TS) arranged to convert an input binary code (d₀ to d n ) to a three states code (a₁ to a n ); and a digital-to-analog conversion means (CV) connected to said code conversion means (TS) and controlled by said three states code (a₁ to a n ), for outputting an analog value corresponding to the input binary code (d₀ to d n ); the input binary code consisting of digits d₀ to d n , the digit d₀ being the most significant digit (MSD), and the digit d n being the least significant digit (LSD); the three states code consisting of digits a₁ to a n , the digit a₁ being the most significant digit (MSD), and the digit a n being the least significant digit (LSD), the digits having a binary weighting and taking any of the values "-1", "0" and "1"; characterised in that said code conversion means (TS) is operable as follows:- when d₀ = 0:- (a) when digits d₁ to d i = "1" (1 ≦ i ≦ n), said code conversion means is arranged to set corresponding digits of the three states code a₁ to a i = "1"; (b) when digits d i to d j = "1" (2 ≦ i ≦ j ≦ n) and d i-1 = 0, d j+1 (if any) = 0, said code conversion means is arranged to set the three states code corresponding to these digits to a i-1 = 1, and a j = -1, and if j > i, a i to a j-1 = 0; (c) for other digits of the binary code, said code conversion means is arranged to set the corresponding three states code to a i = 0; when d₀ = 1:- (1) when digits d₁ to d i = 0 and d i+1 to d j = 1 (1 ≦ i < j ≦ n), said code conversion means is arranged to set corresponding digits of the three states code to a₁ to a i = -1, a j = -1, and if (j-i) > 2, a i+1 to a j-i = 0; (2) in the remaining digits, when d k to d L = 1 (1 ≦ k ≦ l ≦ n), said code conversion means is arranged to set corresponding digits of the three states code to a k-1 (if any) = 1, a L = -1, and if L > k, a k to a L-1 = 0; (3) for other digits of the binary code, said code conversion means is arranged to set the corresponding three states code to a i = 0. A digital-to-analog conversion circuit as claimed in claim 1, wherein said code conversion means (TS) comprises logic circuit units corresponding in number to the number of digits (n) in said three states code (a₁ to a n ); each of said logic circuit units having a first terminal (MI) for inputting a designated digit (d i ) of said input binary code, a second terminal (HI) for inputting a digit (d i-1 ) more significant than said designated digit, a third terminal (LI) for inputting a digit (d i+1 ) less significant than said designated digit, a fourth terminal (Q) for outputting said designated digit (d i ) or an inversion of said designated digit, a fifth terminal (NO, PO) for outputting one digit of said three states code, and a logic circuit (1 to 9); said logic circuit being constituted so as to output a first state signal to said fifth terminal (NO, PO) and output said designated digit (d i ) to said fourth terminal (Q) when values applied to said first, second and third terminals (MI, HI, LI) are the same, to output a second state signal to said fifth terminal (NO, PO) and output said inverted designated digit to said fourth terminal (Q) when said value applied to said second terminal (HI) is "0" and another value applied to said first or third terminal is "1", and to output a third state signal to said fifth terminal (NO, PO) and output said inverted designated digit when said value applied to said second terminal (HI) is "1" and another value applied to said first and second terminal is "0"; each of said logic circuit units being connected to each other in such a way that a second terminal (HI) of a next stage logic circuit unit is connected to said fourth terminal (Q) of a previous stage logic circuit unit, and a first terminal (MI) of said next stage is connected to said third terminal (LI) of said previous stage, and a value "0" being input to the third terminal (LI) of the logic circuit unit corresponding to the least significant digit (a n ); each digit (a₁ to a n ) of said three states code being output from the fifth terminal (NO, PO) of a respective one of the logic circuit units. A digital-to-analog conversion circuit as claimed in claim 2, wherein said logic circuit unit comprises:- an OR gate (1), one input being connected to said first terminal (MI) and the other input being connected to said third terminal (LI); a first NAND gate (3), one input being connected to said first terminal (MI) and the other input being connected to said third terminal (LI); a second NAND gate (2) receiving an output of said OR gate (1) and an inverted signal from said second terminal (HI); a third NAND gate (4), one input being connected to an output of said first NAND gate (3) and the other input being connected to said second terminal (HI); a fourth NAND gate (5), one input being connected to an output of said second NAND gate (2) and the other input being connected to an output of said third NAND gate (4); and an exclusive OR gate (9), one input being connected to said first terminal (MI) and the other being connected to an output of said fourth NAND gate (5); wherein outputs of said second and third NAND gates (2, 4) are connected to said fifth terminal (NO, PO) and an output of said exclusive OR gate (9) is connected to said fourth terminal (Q). A digital-to-analog conversion circuit as claimed in claim 1, 2 or 3, wherein said digital-to-analog conversion means comprises a cyclic-type digital-to-analog converter (CV). A digital-to-analog conversion circuit as claimed in any preceding claim, wherein each digit (d₀ to d n ) of said three states code is given by a binary signal having two bits. A method for converting a binary code to an analog value, comprising the steps of:- code-converting said binary code to a three states code; and converting said three states code to said analog value based on a sequential output; the input binary code consisting of digits d₀ to d n , the digit d₀ being the most significant digit (MSD), and the digit d n being the least significant digit (LSD); the three states code consisting of digits a₁ to a n , the digit a₁ being the most significant digit (MSD), and the digit a n being the least significant digit (LSD), the digits having a binary weighting and taking any of the values "-1", "0" and "1"; characterised in that said code conversion step is performed as follows:- when d₀ = 0:- (a) when digits d₁ to d i = "1" (1 ≦ i ≦ n), corresponding digits of the three states code a₁ to a i are also set to "1"; (b) when digits d i to d j = "1" (2 ≦ i ≦ j ≦ n) and d i-1 = 0, d j+1 (if any) = 0, the three states code corresponding to these digits are determined as a i-1 = 1, and a j = -1, and if j > i, a i to a j-1 = 0; (c) for other digits of the binary code, the corresponding three states code is set to a i = 0; when d₀ = 1:- (1) when digits d₁ to d i = 0 and d i+1 to d j = 1 (1 ≦ i < j ≦ n), corresponding digits of the three states code are determined as a₁ to a i = -1, a j = -1, and if (j-i) > 2, a i+1 to a j-1 = 0; (2) in the remaining digits, when d k to d L = 1 (1 ≦ k ≦ l ≦ n), corresponding digits of the three states code are determined as a k-1 (if any) = 1, a L = -1, and if L > k, a k to a L-1 = 0; (3) for other digits of the binary code, the corresponding three states code is set to a i = 0.

Inventors: KOBAYASHI OSAMU, KOBAYASHI, OSAMU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1987
Main classification: H03M1
IPC codes: H03M1, H03M5, H03M7