SPEED CONTROL SYSTEM FOR DC MOTOR

Abstract: A speed control system for a DC motor (10) is disclosed. This system includes a first transistor (6) connected between a first terminal (1) and a reference terminal (4), a second transistor (7) connected between a second terminal (2) and the reference terminal, an error amplifier (9) having first input terminal connected via a reference voltage circuit (8) to the first terminal, a second input terminal connected to a third terminal (3) and an output terminal connected to the bases of the first and second transistors, a first resistor (13) connected between a power terminal and the second terminal, a second resistor (12) connected between the first and third terminals, and a third resistor (11) connected between the second and third terminals, and the motor (10) is connected between the first terminal and the power terminal.

Description: BACKGROUND OF THE INVENTION The present invention relates to a motor control system, and more particularly to a circuit for controlling the rotational speed of a DC motor. The rotational speed of a DC motor is proportional to the counterelectromotive voltage. Accordingly, the principle for speed control of a motor is to change the motor driving current in accordance with variation of motor load and to counteract, by controlling a voltage between terminals of the motor, the variation of a voltage drop across the internal resistance of the motor caused by the change of the motor driving current. Thus,the counterelectromotive voltage of the motor becomes constant, and the rotational speed thereof is stabilized against load variation. A speed control circuit of a DC motor which is based upon the above-mentioned operating principle and which forms the preamble of claim 1 is known from EP-A-0 024 151. However, the control circuit according to prior art has a drawback that the variation of a bias current due to the changes of a power source voltage and/or an operating temperature causes the counterelectromotive voltage of the motor to vary with the result of change in a rotational speed. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an improved motor speed control circuit. Another object of one present invention is to provide a control circuit for stabilizing the speed of a motor against not only variation in a motor load but also variations in a power source voltage and an operating temperature. These objects are achieved by an integrated circuit as defined in claim 1; the dependent claims are related to further developments of the invention. The reference voltage circuit is provided on the side of the first terminal and is thus disconnected from the second terminal. Accordingly, the counterelectromotive voltage of the motor is stabilized against the variation in bias current flowing into the reference voltage generating means, so that the rotational speed of the motor is kept constant. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a circuit diagram showing a paior art control system; Fig. 2 is a circuit diagram showing a first embodiment of the present invention; Fig. 3 is a circuit diagram showing the circuit of Fig. 1 in detail; Fig. 4 is a circuit diagram showing another example of the construction of the reference voltage circuit and bias current source shown in Fig. 1; Fig. 5 is a circuit diagram showing a second embodiment of the present invention; Fig. 6 is a circuit diagram showing a third embodiment of the present invention; and Fig. 7 is a circuit diagram showing one application of the present invention. DETAILED DESCRIPTION OF THE PRIOR ART Before describing the embodiments of the present invention, a prior art motor speed control circuit will be described with reference to Fig. 1 to facilitate the understanding of the present invention. In Fig. 1, a first transistor 6 for motor driving has its collector-emitter path connected between a first terminal 1 and a reference terminal 4 which is grounded, and a second transistor 7 has its collector-emitter path connected between a second terminal 2 and the reference terminal 4. The second terminal 2 is connected to one input termihal of an error amplifier 9 through a reference voltage circuit 8, and the other input terminal of the error amplifier circuit 9 to a third terminal 3. An output from the error amplifier circuit 9 is applied in common to the bases of the transistors 6 and 7. A DC motor 10 is connected between a power source 15 and the first terminal 1, and a resistor 13 between the power source 15 and second terminal 2. A resistor 11 is connected between the second and third terminals 2 and 3, and a resistor 12 between the first and third terminals 1 and 3. These resistors 11 and 12 constitute a voltage divider. A bias current I B is applied from an current source 16 to the reference voltage circuit 8 which hence generates a reference voltage thereacross. In this arrangement, a voltage V M between terminals of the DC motor 10 is expressed by the following equation (1): V M = R M × I M + E a (1) wherein R M is the internal resistance of the DC motor 10; I M is a current flowing through the DC motor 10 (i.e., a motor driving current); and E a is a counterelectromotive voltage of the DC motor 10. Since the error amplifier circuit 9 operates to control the base voltages of the transistors 6 and 7 so as to equalize the voltages at the two input terminals thereof, the voltage between the terminals 2 and 3 becomes equal to the reference voltage VREF generated by the reference voltage circuit 8. Assuming that the resistance value of the resistor 11 is R₁, a current I₁ flowing through the resistor 11 is expressed by the following equation (2): Since an input current of the error amplifier circuit 9 is substantially zero, the current I₁ also flows through the resistor 12. Accordingly, the potential difference V 2-1 between the terminals 2 and 1 is expressed by the following equation (3): wherein R₂ represents the resistance value of the resistor 12. The current I₁ further flows through the resistor 13. A collector current I₇ of the transistor 7 and a bias current I B produced by the current source 16 also flow through the resistor 13. Therefore, the voltage drop V₁₃ across the resistor 13 is expressed by the following equation (4): V₁₃ = R₃ x (I₁ + I B + I₇) (4) wherein R₃ is the resistance value of the resistor 13. A collector current I₆ of the transistor 6 becomes equal to the sum of the motor driving current I M and the current I₁, and is expressed by the following equation (5): I₆ = I M + I₁ (5) Since the collector current I₇ of the transistor 7 is not supplied to the motor 10, the collector current I₇ is designed to be 1/K (K positive value) of the collector current I₆ of the transistor 6, as expressed by the following equation (6), for purpose of reducing power consumption. I₆ = K × I₇ (6) Conversely, the resistance value R₁₃ of the resistor 13 is designed to be K times as high as that of the internal resistance R M of the motor 10, as represented by the following equation (7): R₃ = K × R M (7) Thus, the following equation (8) is obtained from the above equations (2) - (7). Accordingly, as is clear from the results of comparison between the equations (1) and (8), the counterelectromotive voltage Ea of the motor 10 is expressed by the following equation: Thus, the counterelectromotive voltage Ea is made constant against the variation in the motor current I M . Namely, even when a load of the motor 10 varies, the rotation speed thereof is kept constant. However, a relatively large change occurs in the first member KI B R M of the right side of the equation (9) due to the variation in the voltage of the power source 15 and/or an operating temperature of the control system, so that the rotation speed of the motor varies. More specifically, the voltage of the power source 15 varies due to a ripple component when it is obtained by rectifying an AC voltage. When a battery is employed as the power source 15, its voltage decreases in accordance with power consumption. The operating temperature varies dependly upon the environmental conditions and further varies due to the heat generation of the transistors 6 and 7. Such variations of power source voltage and/or operating temperature cause the change in the bias current I B from the bias current source 16. The change in the bias current I B can be made small, but it is amplified with K times, as is apparent from the equation (9). Since the collector current I₇ of the transistor 7 is not used for driving the motor 10, the value of K is considerably increased to reduce the power consumption. Consequently, a large variation occurs in the counterelectromotive voltage Ea due to the change of the bias current I B , and the rotation speed of the motor cannot be kept constant. DETAILED DESCRIPTION OF THE EMBODIMENTS Referring to Fig. 2, there is shown a first embodiment of the present invention, in which the same constituents as those shown in Fig. 1 are denoted by the same reference numerals to omit their further description. In this embodiment, the reference voltage circuit 8 is connected between the first terminal 1 and the non-inverting input terminal (+) of the error or differential amplifier circuit 9, and a terminal 5 connected to the power source 15 is provided as a fifth terminal to disconnect the bias current source 16 from the second terminal 2. The bias current source 16 is connected between the terminal 5 and the reference voltage circuit 8. Accordingly, the bias current I B is supplied from the power source 15 without flowing through the resistor 13, and then flows into the transistor 6 through the reference voltage circuit 8. As a result, the equations (2) to (5) shown previously are rewritten to the following equations (10) to (13), respectively. From the equations (10) to (13), (6) and (7), a voltage V M between the terminals of the DC motor 10 is expressed by the following equation (14): Thus, the counterelectromotive voltage Ea is represented as follows: This voltage Ea is constant irrespective of the variation of the motor current I M . Namely, a stabilized rotational speed of the motor against the load variation is obtained. Moreover, the first member on the right side of the equation (15) does not contain the proportional constant K. Accordingly, even when the bias current I B varies slightly due to the variation of the voltage of the power source 15 and/or operating temperature, such slight variations are not amplified with K times. As a result, the rotation speed of the motor is also stabilized against the variations in the power source voltage and the operating temperature. Fig. 3 shows a detailed circuit construction of the embodiment of Fig. 1, wherein the transistors 6 and 7, the reference voltage circuit 8, the error amplifier 9 and the bias current source 16 are fabricated as a monolithic semiconductor integrated circuit device 100. In order to obtain the relation of the equation (6), the transistor 6 is formed of a plurality of unit transistors 6-1 to 6-N, and their collector-emitter paths are coupled in parallel, their bases being connected in common. The size of each of unit transistors is equal to the size of the transistor 7. The transistors 6-1 to 6-N and 7 have emitter resistors 6R-1 to 6R-N and 7R, respectively. The reference voltage circuit 8 consists of three NPN transistors Q₅ to Q₇ and three resistors 8R₁ to 8R₃ which are connected as shown in the drawing. This structure is known as a so-called "band gap regulator", which generates a reference voltage of about 1.2 V thereacross. This reference voltage does not change substantially irrespective of the variation in the voltage of the power source 15 and the operating temperature. The error amplifier 9 has two PNP transistors Q₁ and Q₂ connected in a differential form, the emitters of which are connected to a constant current source 9-1 through the respective emitter resistors 9R₁ and 9R₂. The base of the transistor Q₁ is connected to the terminal 3 as an inverting input terminal (-), and the base of the transistor Q₂ is connected as a non-inverting input terminal (+) to the node between the bias current source 16 and the reference voltage circuit 8. The collector of the transistor Q₂ is connected to the reference terminal 4 through a diode D₁ and a resistor 9R₃, and further to the base of an NPN transistor Q₃. The emitter of the transistor Q₃ is connected to the reference terminal 4 through a resistor 9R₄, and the collector thereof is connected to a constant current source 9-2 and the base of an NPN transistor Q₄. The collector of the transistor Q₄ is connected to the terminal 5, and the emitter thereof is connected to the reference terminal 4 through a resistor 9R₅. The emitter of the transistor Q₄ is led out as an output terminal of the error amplifier 9 and is connected in common to the bases of the transistors 7 and 6-1 to 6-N. Another circuit construction of the reference voltage circuit 8 and the bias current source 16 is shown in Fig. 4. In this circuit, the change in the bias current I B is made small against the variations of the power source voltage and operating temperature. More specifically, the bias current source 16 has a band gap regulator consisting of transistors Q₁₀ to Q₁₂ and resistors 16R₁ to 16R₃, and the regulator is connected in series between the terminals 5 and 4 via a diode-connected transistor Q₁₃ and a constant current source 16-1. A. transistor Q₁₄ and a resistor 16R₄ are further provided as shown in the drawing. Therefore, assuming that the voltage of the band gap regulator is represented by V B , the bias current I B takes a value of V B /R₁₆₄ (R₁₆₄ being a resistance value of the resistor 16R₄), so that the change of the bias current I B with respect to the variation in the power source voltage and the operating temperature is reduced to an extremely low level. The reference voltage circuit 8 consists of a single resistor 8R. Accordingly, the reference voltage V REF takes a value of (R₈ being a resistance value of the resistor 8R), and it is stabilized against the variation of the power source voltage and the operating temperature. If the resistance values R₈ and R₁₆₄ are designed to be R₈ = R₁₆₄, a band gap voltage V B appears across the resistor 8R. The transistor Q₁₃ may be omitted. In this case, a diode is provided to be connected in series to the resistor 8R in the reference voltage circuit 8. Fig. 5 shows a second embodiment of the present invention, in which the same constituents as those shown in Fig. 2 are denoted by the same reference numerals to omit their explanation. In this embodiment, an NPN transistor 17 is additionally provided. The collector-emitter path of this transistor 17 is inserted between the terminal 2 and the collector of the transistor 7, and the base of the transistor 17 is connected to the node between the reference voltage circuit 8 and the bias current source 14. Accordingly, the collector potential of the transistor 7 differs from the collector potential of the transistor 6 by a level that is equal to a voltage difference between the reference voltage V REF and a base-emitter forward voltage of the transistor 17. In other words, the collector-emitter voltage of the transistor 7 is rendered close to the collector-emitter voltage of the transistor 6, so that the transistor 7 is matched with the transistor 6 to obtain an accurate value of the proportional constant K. Fig. 6 shows a third embodiment of the present invention. The error amplifier 9 has a substantially identical construction as that shown in Fig. 3, and therefore includes the constant current source 9-1 between the terminal 5 and a node to which the emitters of the transistors Q₁ and Q₂ are connected in common through resistors 9R₁ and 9R₂. In order to expand the input dynamic range of the error amplifier 9, therefore, it is preferable to supply a lowered level of the voltage at the terminal 3 to the inverting input terminal (-) of the error amplifier 9. For this purpose, a transistor 60 and a constant current source 50 are provided as a level-shift circuit. The terminal 3 is connected via the base-emitter path of the transistor 60 to the inverting input terminal (-) of the error amplifier 9. Accordingly, the voltage at the terminal 3 is level-shifted by a base-emitter forward voltage of the transistor 60, and then applied to the inverting input terminal (-) of the error amplifier circuit 9. The constant current source 50 maintains the voltage between the base and emitter of the transistor 60 at a constant level. The bias current source 16 has a band gap regulator consisting of transistors Q₄₀ to Q₄₂ and resistors R₄₀ to R₄₂ and connected in series between the terminals 4 and 5 via a constant current source 40. The band gap voltage V B is supplied to a series circuit consisting of the base-emitter path of a transistor Q₄₃ and a resistor R₄₃. The transistors Q₄₄ and Q₄₅ constitute a current mirror circuit in which the ratio of input current to output current is set to 1, and a collector current of the transistor Q₄₃ is supplied as an input current for the current mirror circuit. Accordingly, the bias current I B from the bias current source 16 takes a value of (V B - V BE43 )/R₄₃, wherein V BE43 is the voltage between the base and emitter of the transistor Q₄₃. The reference voltage circuit 8 is formed of a single resistor R₅₀, the resistance value of which is set to the same level as that of the resistor R₄₃. Therefore, a voltage drop (V B - V BE43 ) occurs across the resistor R₅₀. Since the voltage between the base and emitter of the transistor Q₄₃ and that between the base and emitter of the transistor Q₆₀ are substantially equal, the voltage between the terminals 3 and 1 is maintained at the level of the band gap voltage V B . This voltage is stabilized against the variations of the power source voltage and operating temperature. Moreover, the change of the bias current I B become very small. Fig. 7 shows an application of the present invention, which can change the rotation speed of the motor 10. A control circuit 300 can employ any one of the structures shown in Figs. 1, 3, 5 and 6. It is understood from the equation (15) that the counterelectromotive voltage Ea of the motor 10, i.e. the rotational speed thereof, can be switched from one value to another value by changing the resistance value of at least one of the resistors 11 and 12. In the circuit shown in Fig. 7, the resistance value of the resistor 12 is changed. To this end, a series circuit of a resistor 201 and the collector-emitter path of a transistor 200 is connected in parallel to the resistor 12. The base of the transistor 200 is connected to the power source 15 through a resistor 202 and a switch 203. When the switch 203 is off, the transistor 200 is in a cut-off state, so that only the resistor 11 is connected between the terminals 1 and 3. When the switch 203 is turned on to energize the transistor 200, the resistor 201 is connected in parallel to the resistor 11, so that the resistance value between the terminals 1 and 3 becomes small. This causes the rotation speed of the motor to become low. The internal resistance R M of the motor 10 may become large as the rotational speed of the motor increases. If the resistance value of the resistor 13 as a torque control resistor is set constant nevertheless the internal resistance R M has become large, the variation of the rotational speed of the motor increases. Therefore, when the rotation speed of the motor is increased by changing the resistance value of at least one of the resistors 12 and 11, it is preferable to increase the resistance value of the resistor 13.

Claims: An integrated circuit device for a motor speed control, comprising first, second, third, fourth terminals (1, 2, 3, 4), first and second transistors (6, 7) each having a base, an emitter and a collector, first means (wiring between 1 and 6) for connecting the collector of said first transistor (6) to said first terminal (1), second means (wiring between 2 and 7; 17) for connecting the collector of said second transistor (7) to said second terminal (2), third means (wiring between 4 and 6, 7) for connecting the emitters of said first and second transistors (6, 7) to said fourth terminal (4), a differential amplifier (9) having first and second input terminals (-, +) and an output terminal, fourth means (wiring between 9 and 6, 7) for connecting said output terminal of said differential amplifier to the bases of said first and second transistors (6, 7), fifth means (wiring between 3 and 9; 60, 50) for connecting said first input terminal (-) of said differential amplifier (9) to said third terminal (3), a reference voltage circuit (8), and a bias current source (16), characterized in that said device further comprises a fifth terminal (5), that said reference voltage circuit (8) is coupled between said first terminal (1) and said second input terminal (+) of said differential amplifier (9), and that said bias current source (16) is coupled between said fifth terminal (5) and said second input terminal (+) of said differential amplifier (9), so that said bias current source (16) is disconnected from said second terminal (2). The integrated circuit device as claimed in claim 1 , characterized in that said integrated circuit device cooperates with externally provided elements to constitute a motor speed control system, said externally provided elements including a motor (10) coupled between said first and fifth terminals (1, 5), a first resistor (11) coupled between said second and third terminals (2, 3), a second resistor (12) coupled between said first and third terminals (1, 3) and a third resistor (13) coupled between said second and fifth terminals (2, 5), said fifth terminal (5) being supplied with a power voltage. The integrated circuit device as claimed in claim 1 or 2 , characterized in that said reference voltage circuit (8) comprises a band gap regulator (8R₁, 8R₂, 8R₃, Q₅, Q₆, Q₇) producing a band gap voltage. The integrated circuit device as claimed in claim 1 or 2 , characterized in that said bias current source (16) comprises a band gap regulator (16R₁, 16R₂, 16R₃, Q₁₀, Q₁₁, Q₁₂) producing a band gap voltage and transistor (Q14) biased by a voltage relative to said band gap voltage to produce a bias current. The integrated circuit device as claimed in claim 1, 2 or 4 , characterized in that said reference voltage circuit (8) comprises a resistor (8R, R50) supplied with the bias current from said bias current source (16) to produce a voltage drop thereacross. The integrated circuit device as claimed in claim 1, 2, 3, 4 or 5 , characterized in that said second means comprises a transistor (17) having a collector-emitter path inserted between said second terminal (2) and said collector of said second transistor (7), the base of said third transistor (17) being connected to said second input terminal (+) of said differential amplifier (9). The integrated circuit device as claimed in claim 1, 2, 4 and 5 , characterized in that said fifth means includes level-shifting means (60, 50) for level-shifting a potential at said third terminal (3) to supply a level-shifted potential to said first input terminal (-) of said differential amplifier (9). The integrated circuit device as claimed in claim 7 , characterized in that said level-shifting means comprises a transistor (60) having an emitter connected to said first input terminal (-) of said differential amplifier (9), a collector connected to said fifth terminal (5) and a base connected to said third terminal (3), and a current source (50) coupled between the emitter of said transistor (60) and said fourth terminal (4). The integrated circuit as claimed in claim 1, 2, 5, 7 or 8 , characterized in that said bias current source (16) comprises a band gap regulator producing a band gap voltage, means (Q43, R43) responsive to said a band gap voltage for producing a reference current, and a current mirror circuit (Q44, Q55) responding to said reference voltage to produce a bias current.

Inventors: ISHII, EIICHI C/O NEC CORPORATION, OSUGA. MASUO C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1987
Main classification: H02P5
IPC codes: H02P7, H02P27