TEMPERATURE COMPENSATED HYSTERESIS BUFFER

Abstract: A hysteresis circuit is disclosed in which a first signal path, including a hysteresis feedback loop, is separate from a second signal path that is used to carry data. When the signal input to the hysteresis circuit (also referred to hereinafter as the "input signal") crosses a first preselected hysteresis reference (of "threshold") level, the hysteresis feedback loop, which includes threshold adjustments means, will cause a change in the threshold from the first preselected level to a second preselected level. This adjustment of threshold level will take place in parallel with the data being propagated to the output over said separate second signal path. A subsequent crossing of the second preselected threshold level by said input signal will cause the first threshold level to be reset and so on. According to the preferred embodiment of the invention, the threshold adjustment means included in said first signal path further includes a temperature compensation string, current switching means and means which act as an anti-hysteresis killer to speed up the operation of the hysteresis circuit. This novel combination is operative to assure a preselected minimum hysteresis window over the 200°C temperature range between -55°C and 155°C, and renders the hysteresis circuit suitable for use in both military applications and other hostile environments. Furthermore, according to the preferred embodiment of the inven­ tion, the hysteresis circuit has a PNP input stage to reduce I IL and acordingly improve the input characteristics of the circuit, particularly fan-in. The circuit also features a low I CC and is designed to be self-compensating with respect to manufacturing disparities inherent in components used to fabricate the circuit itself.

Description: The invention relates to high-speed temperature compensated hysteresis circuits which guarantee a predetermined minimum hysteresis window over a wide temperature range so that the circuits are suitable for use in military applications and hostile environments. Hysteresis circuits are well known devices for accurately detecting a change in the value of an input signal voltage. These circuits operate by varying threshold voltage values so that when the input signal value is "low", a high threshold, V IH , is set and when the input signal is "high" a low threshold value V IL is set. By keeping the hysteresis window, i.e., the absolute value of the voltage difference of V IL and V IH , above some minimum value, reasonable assurance may be had that noise or transients do not inadvertently cause a threshold boundry to be crossed to yield a false signal that a swing in input signal voltage has occured. These circuits must operate to detect valid threshold crossings and adjust threshold levels accordingly, i.e., if the V IL threshold is set and crossed the circuit must operate to set the V IH threshold and vice versa. A hysteresis buffer according to the preamble portion of the independent claim 1 is known from EP-A-0 175 522. Some known hysteresis circuits are not output independent. Typically, signals output by a hysteresis circuit are also fed back to the circuit itself to set up the hysteresis reference levels (the threshold voltages V IL and V IH ). As a result, the hysteresis reference levels may be affected by variables in the output stage, for example, output current. It would therefore be desirable to have a hysteresis circuit which operates in parallel with data being propagated to the output stage, independent of the output itself, to eliminate such variables. Furthermore, it has been determined that it would be desirable to reduce I CC , the total current required by a hysteresis circuit, from the I CC levels required by known circuits in order to meet military application specifications. Still further, it has been determined that it would be desirable to be able to improve the input characteristics of known hysteresis circuits by minimizing I IL ("current when input is low") to, for example, achieve improved fan-in. Further yet, it would be desirable to insure that hysteresis circuits having all the features set forth hereinbefore assure a minimum preselected hysteresis window over wide temperature ranges. In particular, this feature is desirable over the 200°C operating range between -55°C and 155°C typically required for military applications. This assurance that a minimum preselected hysteresis window can be guaranteed over a wide temperature range would allow for the incorporation of these circuits in hostile environments generally. Known hysteresis circuits simply do not have this capability. Finally, it would be advantageous if hysteresis circuits having all the features set forth hereinbefore, were self-compensating with respect to the components used to fabricate the circuit itself. A self-compensating feature to account for manufacturing disparities in components would further improve the reliability and accuracy of such circuits. Accordingly, the present invention provides a temperature compensated hysteresis buffer having an upper and a lower threshold comprising (a) input means for receiving an input data signal; (b) output means for outputting an output data signal representative of said input signal; (c) a first signal path coupled to said input means for setting upper and lower hysteresis thresholds, as a function of said input signal; and, (d) a second signal path, coupled to said input means and to said output means, for propagating said input data to said output means; said second signal path being separate from said first signal path; whereby the first signal path includes threshold adjustment means comprising current switching means connected to be responsive to said input signal, said current switching means being controlled independently of said output signal; characterised in that said threshold adjustment means further comprises a temperature compensating means comprising a series connection of a Schottky diode and first resistance means of opposite temperature coefficient to that of said diode whereby the voltage drop across the temperature compensating means is substantially independent of temperature; and second resistance means; said current switching means and said temperature compensating means being connected in parallel and connected together at a node in series with said second resistance means, so that when said current switching means is on in response to said input signal being high it drains current flowing through said second resistance means from said node to set said lower threshold, and so that when said current switching means is off in response to said input signal being low, said temperature compensation means drains current flowing through said second resistance means from said node to set said upper threshold. The threshold adjustment means include means which act as an antihysteresis killer to speed up the operation of the hysteresis circuit. The arrangement is operative to assure a preselected minimum hysteresis window over the 200°C temperature range between -55°C and 155°C, and renders the hysteresis circuit suitable for use in both military applications and other hostile environments. The hysteresis circuit preferably has a PNP input stage to reduce I IL and accordingly improve the input characteristics of the circuit, particularly fan-in. The circuit may also feature a low I CC and is designed to be self-compensating with respect to manufacturing disparities inherent in components use to fabricate the circuit itself. We will describe a hysteresis circuit which is capable of adjusting its hysteresis reference level in parallel with data being propagated to the output of the circuit. We will describe a hysteresis circuit that guarantees a minimum preselected hysteresis window over a wide temperature range. In particular, it is an object of the invention to provide a circuit that guarantees a minimum 200 millivolt hysteresis window over the aforementioned 200°C temperature range to permit the use of said circuit in military applications and in hostile environments. We will describe a hysteresis circuit which requires a lower I CC and I IL compared with known hysteresis circuits, without reducing the operating speed of the circuit, and which provides for the automatic compensation for manufacturing disparities in components used to fabricate the circuit. These and other features of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description and the accompanying Drawing, in which like reference designations represent like features throughout the figures. BRIEF DESCRIPTION OF THE DRAWING FIGS. 1a - 1d depict, in block diagram form, various circuit arrangements incorporating hysteresis buffers. FIGS. 1a and 1b are prior art circuit arrangments which respectively perform inverter and noninverter functions. FIGS. 1c and 1d are block diagrams of the corresponding circuit arrangements suitable for incorporating the novel hysteresis buffer taught herein. FIG. 2 depicts the detailed circuit diagram for the temperature compensated, high performance hysteresis buffer taught herein. FIG. 3 depicts, in tabular form, the various states of the transistors depicted in FIG. 2 as a function of the state of the input signal. The circuit depicted in FIG. 2 and characterized by the table shown in FIG. 3. DETAILED DESCRIPTION Referring to FIG. 1a, a typical prior art hysteresis buffer, 101, is shown in combination with a 48 milliamp output buffer, 102, NPN input stage 103 and buffer 125. This circuit arrangement is operative to invert the signal input on line 120. An analagous circuit arrangement that does not invert the input is depicted in FIG. 1b. The only difference between the circuit depicted in FIG. 1a and FIG. 1b is the inclusion of inverter 104 in the FIG. 1b circuit. It should be observed that in these known circuit arrangements, the hysteresis feedback loop is not separate from the data path. As a result, the threshold values, V IL and V IH , may be affected by variables in the output stage such as output current. Thus, the hysteresis window, defined herein as the difference between V IL and V IH over the operating temperature range of the hysteresis circuit, is dependent on current delivered to the load via output buffer 102. In addition to being output dependent, the hysteresis window, as defined hereinbefore, is inherently a function of temperature. The hysteresis window of the known circuit arrangements varies considerably with temperature. This is because temperature sensitive components, such as Schotky diodes, are typically used to fabricate the circuits. As a result, not only the load, but swings in temperature as well, will have a significant impact on the degree to which the hysteresis window of known circuits will vary. In short, the known circuits are unreliable at best, if not altogether useless, in situations where widely varying loads and temperatures are present. Still further, the known circuit arrangements depicted in FIGS. 1a and 1b suffer a time delay before a threshold level can be changed. This is because the hysteresis feedback loop is output dependent. Any required switching follows the output serially. To solve the aforementioned problems, and by way of comparison, FIGS. 1c and 1d are presented, in block diagram form, to depict hysteresis buffer circuits suitable for incorporating the invention. In FIG. 1c it may be seen that a PNP input stage, 180, replaces the NPN input stage of the prior art circuit. This will reduce I IL and improve the circuits input characteristics. FIG. 1c also depicts hysteresis buffer circuitry 181 with a first signal path, 185, being fedback to the PNP input stage 180 and a second separate signal path, path 186, being used to couple data (via inverter 187) to output buffer 188. FIG. 1d is the same as FIG. 1c, except that a noninverter circuit arrangement is shown. The separate feedback and data paths shown in FIGS. 1c and 1d speed up switching the threshold levels in the novel circuits. Less time delay is suffered in switching hysteresis reference levels since the switching takes place in parallel with data being propagated to the output stage. In addition, the separate paths for data and for signals to control the hysteresis reference levels, climinates the problem of having the threshold levels being affected by variables in the output stage. It will be demonstrated, with reference to FIG. 2, that a minimum predetermined hysteresis window is guaranteed over wide termperature ranges using the temperature compensation and current switching techniques taught hereinafter. FIG. 2 depicts the circuit details of a hysteresis buffer that functions as an inverter. The circuitry depicted in FIG. 2 corresponds to the functional block 199 shown in dashed lines in FIG. 1c. The example set forth hereinafter, for constructing the FIG. 1c inverter circuit in accordance with the teachings of the invention, may easily be modified by one skilled in the art to realize the noninverter buffer shown in FIG. 1d. Referring now to FIG. 2, according to the preferred embodiment of the invention, the head of the feedback/threshold level adjustment path is PNP transistor Q1. The head of the signal path carrying data is PNP transistor Q2. These paths are hereinafter defined as the first signal path and second signal path respectively. The PNP input stage is clearly shown in FIG. 2 comprised of Q1 and Q2. The first signal path, including the loop which carries feedback to the PNP input stage, includes all the components shown in FIG. 2., except those components in the separate second signal path as it is hereinafter defined. The first signal path components taken together operate as the threshold adjustment means of the preferred embodiment. The threshold adjustment means of the preferred embodiment of the invention is more particularly defined to include temperature compensation string 201; anti-hysteresis killer means 202; and self-compensating resistors R4 and R7 comprised of multiple resistors each having the same resistance value; all depicted in FIG. 2. The second signal path, as depicted in FIG. 2, is comprised of PNP transistor Q2, Schotky diode D2A, and transistor Q4. This signal path couples the input, labled "in", to the circuit's output labeled "out". The input signal is propagated along the second signal path to the output stage (not shown in FIG. 2) which is coupled to "out". The inversion of the input signal may, for example, be performed by an inverter (like inverter 187 shown in FIG. 1c) being inserted between the hysteresis buffer and the output buffer. To appreciate the operation of the first signal path, reference should be made to FIGS. 2 and 3 together. This will enable one to see in tabular form (from FIG. 3) the state of the various circuit components depicted in FIG. 2 as a function of the input as being "low" or "high" as these terms are hereinafter defined. For the sake of illustration only, the circuit will be defined in accordance with TTL standards. Accordingly, the circuit depicted in FIG. 2 operates with V CC defined as +5.OV; with an input signal of greater then +2.OV defined as "high"; with an input signal of less then +0.8V defined as "low"; with the Schotky diodes defined as "on" at +0.5V; and with V BE at +0.8V and V CE at +0.3V when the transistors shown in FIG. 2 are characterized as "on" in the table depicted in FIG. 3. Further constraints and definitions to serve the purposes of the example and to meet the aforesaid specifications for military applications are that V IH cannot be greater than +2.0V; V IL cannot be less then +0.8V; and although V IH and V IL vary, their difference (i.e., the window between V IH minimum and V IL maximum) must always be greater then 200 millivolts over the temperature range of -55°C to 155°C. The key elements and functions performed by the circuit depicted in FIG. 2 are set forth in detail immediately hereinafter. According to the preferred embodiment of the invention, the aforesaid temperature compensation string 201, is comprised of Schotky diode D6 and resistor R7. The purpose of temperature compensation string 201 is to keep the voltage drop relatively constant between node "X" (shown in FIG. 2) and ground over the anticipated operating temperature range of the circuit. According to the instant example the range is 200°C. The temperature coefficients of Schotky diode D6 and of resistor R7 are opposite and therefore achieve the purpose of the string. The circuit depicted in FIG. 2 has the higher threshold, V IH , set when the input signal is low; i.e., V IH is set when transistor Q9 is off and current goes to ground via the temperature compensation string D6 and R7. The lower threshold, V IL , is set when Q9 is on and current goes to ground via Q9. This occurs when the input signal is high. It should be noted that a key feature of the invention is realized by the circuit depicted in FIG. 2 because current switching between the D6, R7 string and Q9 is triggered by swings in the input voltage signal; but is output independent. It should also be noted that the hysteresis window is set up by switching current between D6 and Q9. This hysteresis window is guaranteed to be at least 200 millivolts over the circuits operating range because of the temperature compensation string/current switching means (Q9) combination. The voltage drop across R7, D6 and Q9 is approximately one Schotky drop. The Q9 drop is approximately one Schotky drop since the V CE of Q9 is clamped by Q8 and D7 to be equal to the drop of D7; the D6 drop is one Schotky drop; and the voltage drop across R7 is also approximately one Schotky drop as will become obvious with reference to formula (2) set forth hereinafter where V R7 is calculated. As a result the difference between the voltage drop across Q9 and the voltage drop across R7 and D6 is approximately one Schotky drop which is always above 200 millivolts. FIG. 2 also depicts the threshold adjustment means as being further comprised of anit-hysteresis killer means 202. Means 202 is shown comprised, of transistor Q5, resistor R6 and Schotky diodes D4, D4A and D5. This string serves to sink current if the signal at the base of transistor Q3 exceeds two Schotky drops plus V BE . The anti-hysteresis string's purpose is to prevent node X from continuing to rise when switching from the V IH to V IL threshold, i.e., the circuit serves to stem the rising voltage at node X as the input voltage swings from low to high. Means 202 has the overall net effect of speeding up the hysteresis buffer, facilitating quick switching of threshold levels. Finally, with respect to the hysteresis buffer depicted by FIG. 2, it should be observed that V R7 is independent of both the process variation used to fabricate the resistors shown in FIG. 2 and is independent of the temperature coefficients of these resistors. In the preferred embodiment, as shown in FIG. 2, R7 is comprised of four 3.2K ohm resistors in parallel while R4 is comprised of three 3.2 ohm resistors in series. The algebraic calculation of V R7 , to be described in detail hereinafter, will show the temperature coefficients and process variables associated with the resistors used to fabricate R4 and R7, cancelling out, therefore achieving the aforesaid self-compensating feature. One of ordinary skill in the art will appreicate that the resistance values used herein are for the sake of illustration only. By way of further example, if it is desirable to widen the hysteresis window, this can be accomplished by choosing a greater value for R7 then the value used in the example of the preferred embodiment. The only condition is that the resistors have the same dimension. As indicated hereinbefore, an overview of the various states of the transistors used to fabricate the preferred embodiment of the invention is set forth in tabular form in FIG. 3. One of ordinary skill in the art will appreciate that when the input signal supplied to the hysteresis buffer circuit is "low", only Q1, Q2 and Q6 are "on". This is shown in the first line of the table set out in FIG. 3. In this case, V IH is set and Q9 is off forcing current to ground via D6 and R7. The output in this case is pulled high by the output buffer to achieve the inverter function. As shown in the second line of the table depicted in FIG. 3, when the input to the hysteresis buffer circuit is "high", Q3, Q4, Q7 Q8 and Q9 are "on". The output from the circuit depicted in FIG. 2 is now low, since transistor Q4 pulls the buffer output low when turned on. Further, V IL is set since Q9 is on forcing current to ground via Q9 instead of the D6, R7 string. Finally, it can be seen from FIG. 2 and FIG. 3 together that as the input swings from low to high, V IL is determined by Q3 turning on, Q6 turning off, Q7 turning on and Q8 and Q9 turning on. When the input voltage swings from high to low, the end result is that Q6 is left on, everything else (except Q1 and Q2) are turned off, and current is forced through D6 and R7 to ground to set V IH . The following analysis will prove that although V IH will vary with temperature over the 200°C range between -55°C and 155°C, it will not exceed +2.0V. That V IL does not fall below +0.8V will be demonstrated hereinafter. Obviously, if V IH were allowed to exceed +2.0V or if V IL were allowed to be less than +0.8V, the unacceptable prospect that the input signal could change states without crossing a threshold level would exist. Accordingly, these performance requirements are incorporated in the preferred embodiment of the invention. Furthermore, the hysteresis window will always exceed 200 millivolts as was demonstrated hereinbefore with reference to the voltage drops across the temperature compensation string/current switching means combination. To show V IH does not exceed +2.0V, consider the voltages developed across R7 at -55°C and 155°C (the extremes) and the formula: V IHMAX = 2V SCH + V R7 (1) One of ordinary skill in the art, using published tables, would determine that V SCH at -55°C is approximately +0.7 volts. V SCH at 155°C is approximately +0.4 volts. To calculate V R7 , one may start with the equations: and Since I R7 = I R3 + I R4 (the sum of the current at node X); therefore, and thus, To calculate the range of V IH at V CC = +5.0V, first at -55°C and then 155°C, begin by calculating V R7 using formula (2), and then substitute in formula (1), set forth hereinbefore, using the table values for V SAT , V BE and V SCH at the extreme temperatures of interest i.e., for -55°C and 155°C respectively. At 155°C: therefore, V IH155°C = 2 (V SCH ) + V R7 = 2(.4) + (.5013) = 1.3013V and at -55°C: therefore, V IK-55°C = 2(V SCH ) + V R7 = 2(.7) + .4365 = 1.8365V. Thus, the maximum value for V IH is less the +2.V over the 200°C operating temperature range of the hysteresis circuit used in the preferred embodiment of the invention. To appreciate that V IL always exceeds +0.8V, consider that V IL is equal to V CE of Q9 plus V BE of Q3 plus V SCH of D2 less V BE of Q1. Therefore, V IL is approximately 2 V SCH , which is always greater then +0.8V over the aforesaid temperature range. One of ordinary skill in the art will appreciate that the formulas set forth hereinbefore demonstrate that V R7 is independent of both process variation and the temperature coefficients of the various resistors (as stated hereinbefore) since the use of multiple resistors having the same value to fabricate R4 and R7 allows process variation dependent parameteres and temperature coefficients to cancel out. What has been set forth herein is a novel hysteresis buffer circuit which realizes all of the objectives set forth hereinbefore. In particular, the hysteresis circuit disclosed is output independent, meets the aforementioned minimum hysteresis requirements over temperature ranges suitable for military applications, operates with a relatively low I CC and I IL and is self-compensating.

Claims: A temperature compensated hysteresis buffer having an upper and a lower threshold comprising (a) input means (Q1,Q2) for receiving an input data signal; (b) output means (OUT) for outputting an output data signal representative of said input signal; (c) a first signal path (D2,Q3,Q6,Q7,Q8,Q9,Q5) coupled to said input means (Q1,Q2) for setting upper and lower hysteresis thresholds, as a function of said input signal; and, (d) a second signal path (D2A,Q4), coupled to said input means (Q1,Q2) and to said output means (OUT), for propagating said input data to said output means (OUT); said second signal path being separate from said first signal path; whereby the first signal path includes threshold adjustment means (R4,Q9,201) comprising current switching means (Q9) connected to be responsive to said input signal, said current switching means (Q9) being controlled independently of said output signal; characterised in that said threshold adjustment means (R4,Q9,201) further comprises a temperature compensating means (201) comprising a series connection of a Schottky diode (D6) and first resistance means (R7) of opposite temperature coefficient to that of said diode whereby the voltage drop across the temperature compensating means is substantially independent of temperature; and second resistance means (R4); said current switching means (Q9) and said temperature compensating means (201) being connected in parallel and connected together at a node (X) in series with said second resistance means (R4), so that when said current switching means is on in response to said input signal being high it drains current flowing through said second resistance means (R4) from said node (X) to set said lower threshold, and so that when said current switching means is off in response to said input signal being low, said temperature compensation means drains current flowing through said second resistance means (R4) from said node (X) to set said upper threshold. Buffer as claimed in Claim 1 characterised in that said input means comprises a PNP transistor input stage (D1,Q1,Q2) arranged to couple said input signal to said first signal path and separately to said second signal path. Buffer as claimed in Claims 1 or 2, characterised in that said current switching means comprises a transistor (Q9). Buffer as claimed in any of Claims 1 to 3, characterised in that the difference between the voltage drop across said temperature compensation means (201;R7,D6) when said switching means is off and the voltage drop across said switching means when it is on provides a minimum preselected hysteresis window over a predetermined operating temperature range for the hysteresis buffer. Buffer as claimed in any of Claims 1 to 4, characterised in that said first and second resistance means (R7,R4) are self compensating, whereby the temperature coefficients and process variables associated with the resistive components used to fabricate them are cancelled out. Buffer as claimed in Claim 5, characterised in that said first and second resistance means each comprises a plurality of resistors all of which have the same resistance value and physical dimensions, the resistors being coupled in parallel to form said first resistance means (R7), and coupled in series to form said second resistance means (R4). Buffer as claimed in any preceding claim, characterised in that said threshold adjustment means (R4,201,Q9) further comprises means (202) for speeding up the operation of said buffer to facilitate quick switching between said hysteresis reference levels, comprising a transistor (Q5) arranged to stem the rise in voltage at said node (X) when said input signal swings from a low to a high value. Buffer as claimed in any preceding claim, characterised in that said buffer has a temperature operating range of between -55°C and 155°C. Buffer as claimed in Claim 8, characterised in that the absolute value of the difference between the lower and upper thresholds exceeds 200 millivolts over said operating temperature range for the hysteresis buffer. Buffer as claimed in Claim 9, characterised in that said buffer is fabricated as a single semiconductor integrated circuit device.

Inventors: CHEN, MARTIN
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1987
Main classification: H03K3
IPC codes: H03K3