IMAGE PROCESSING APPARATUS

Abstract: The image processor includes a main processor, a controller and a frame memory to store image data. It also has a source counter, a convolution processor, an adder, a data latch circuit, a pipeline register, a bus buffer, a buffer RAM, an address counter, an address register and a destination counter. A frame memory stores the result. A convolution operation with coefficient matrix data on each pixel of the frame memory is carried out by storing the result of an intermediate operation in the buffer RAM. This result is then added to the result of the next intermediate operation successively.

Description: Technical Field This invention relates to a picture processing apparatus and, more particularly, to a picture processing apparatus for performing convolution processing with regard to plural items of pixel data, which are stored in a frame memory, on a time-sharing basis using a predetermined coefficient matrix comprising rows and columns. Background Art For such purposes as sharpening a picture, removing background noise from a picture, etc., conventional practice is to perform convolution processing with regard to pixel data in a frame memory using a predetermined weighted coefficient matrix comprising rows and columns. Fig. 4(a) illustrates a coefficient matrix of five rows and five columns, and Fig.4(b) illustrates 256 x 256 items of pixel data A₁₁, A₁₂, ..., A₂₅₆₂₅₆ in a frame memory. Weighted coefficients C₁₁, C₁₂, ..., C₅₅ in the coefficient matrix have weighted values for attaining the aforementioned purposes. In order to perform convolution processing with regard to the pixel data in a frame memory of the kind shown in Fig. 4(b) with a coefficient matrix of the kind shown in Fig. 4(a), a convolution processor is used. With a convolution processor, partial convolution processing is performed with regard to one predetermined row of pixel data in the frame memory, the results of this intermediate processing are stored in a buffer RAM, next the intermediate results just stored in the buffer RAM are read out, these intermediate results are added to the results of the next partial convolution processing obtained from the convolution processor, the resulting sum is repeatedly stored at the address in the buffer RAM where the preceding intermediate processing results were stored, and the sum is read out from this address. Thus, convolution processing is performed on a time-sharing basis. With the 5 x 5 coefficient matrix of the kind shown in Fig. 4(a), for example, this time-sharing convolution processing is executed by being split into five stages. When the convolution processing is performed with respect to the third row of pixel data in Fig. 4(b), partial convolution processing is carried out between the first row of the coefficient matrix and the 1 through 256 columns of pixel data in the first row in the first stage of processing. As shown in Fig. 6, is stored in third through 254th columns of the first row of the buffer RAM as the respective intermediate processing results of convolution processing. At this time, invalid data (indicated by the symbol "*" in the drawings) enter the first, second, 255th and 256th columns. Next, in the second stage of processing, these intermediate processing results stored in the buffer RAM are read out and, at the same time, the convolution processor performs partial convolution processing between the second row of the coefficient matrix and the first through 256th columns of pixel data in the second row. These partial results and the preceding intermediate processing results stored in a data latch circuit are added and the new intermediate processing results obtained from the addition are stored by rewriting the preceding intermediate processing results in the third through 254th columns of the buffer RAM, as shown in Fig. 6(b), at a write timing controlled by a bus buffer. Thus, are written in the third through 254th columns of the buffer RAM. The third, fourth and fifth stages of processing are executed through this procedure to store intermediate processing results of the kind shown in Figs. 6(c), (d) and (e) in the first row of the buffer RAM. When the fifth stage of processing is performed, 5 x 5 matrix convolution processing with respect to the third row of the frame memory will be completed, so that results of the kind shown in Fig. 6(e) can be obtained. In other words, However, when high-speed processing is attempted with this conventional apparatus for performing convolution processing on a time-sharing basis, a prescribed period of time is required for reading the intermediate processing results from the buffer RAM to the data latch circuit and for adding the intermediate processing results stored in the latch data circuit and the next convolution processing results from the convolution processor. Accordingly, a problem arises in that there is inadequate time for writing the intermediate processing results data in the buffer RAM. For example, as shown in the time chart of Fig. 5, if convolution processing is performed with regard to one row of pixel data in the frame memory of Fig. 5(a), a time T, or a processing frequency f, needed for one partial convolution processing performed by the convolution processor will be a video rate of 167 ns, as shown in Fig. 5(b). In other words, the processing will be executed at 6 MHz. Therefore, it is necessary that the contents of the buffer RAM be read R and written W at this rate. Though a buffer RAM capable of operating at high speed is used, the access time is 50 ns with C-MOS-type RAMs that are presently available. Fig. 5(b) illustrates the timing at which the first stage of convolution processing results are written (W) in the buffer RAM, and Fig. 5(c) shows the second stage of timing at which the intermediate processing results stored in the buffer RAM in the first stage of processing are read (R) and the sum obtained by adding these results to the next processing results are written (W) in the buffer RAM. It will be understood from Figs. 5(c) and (d) that after the intermediate processing results stored in the buffer RAM in accordance with the first stage of processing are read (R) and stored in the data latch circuit, the timing for outputting the results from the latch circuit to the adder is delayed a predetermined period of time. Fig. 5(e) illustrates the output of processing results at the next processing cycle of the convolution processor. Fig. 5(f) illustrates the timing for adding the results obtained in the next processing cycle of the convolution processor and the output from the data latch circuit shown in Fig. 5(d). The hatched portion indicates that the output of the adder is not valid. The timing at which the results of addition obtained from the adder are written in the buffer RAM is as shown in Fig. 5(g). This is done by bus buffer on/off control and a buffer RAM write-enable signal. It will be understood from Figs. 5(f) and (g) that since the results of addition obtained from the adder are considerably delayed with respect to the timing at which these results are written in the buffer RAM, the intermediate processing results cannot be stored in the buffer RAM with certainty. Thus, since the processor executes convolution processing at the video rate of 167 ns, there is a limitation with read/write control of a RAM having an access time of 50 ns. In order to avoid this read/write temporal limitation, the conventional apparatus is so adapted that the convolution processing is executed in twice the period, i.e., at a time equivalent to 2 x T. As a result, picture processing cannot be speeded up. The present invention has been devised in order to solve the aforementioned problems and its object is to provide a picture processing apparatus in which read/write control can be performed with certainty and it is possible to speed up convolution processing even if use is made of a RAM having an access time of 50 ns with respect to a video rate of e.g. 167 ns. Disclosure of the Invention In accordance with the present invention, there is provided a picture processing apparatus as claimed in claim 1. Brief Description of the Drawings Fig. 1 is a block diagram showing the inventive picture processing apparatus for performing time-sharing convolution processing, Fig. 2 is a time chart of time-sharing convolution processing according to the invention, Fig. 3 is a view showing the manner in which intermediate processing results are stored in a buffer RAM in accordance with the invention, Fig. 4 is an explanatory view illustrating a general example of picture processing, in which (a) is a view showing a coefficient matrix in a coefficient memory and (b) is a view showing pixel data in a frame memory that are to be subjected to convolution processing, Fig. 5 is a time chart of convolution processing in a conventional picture processing apparatus, and Fig. 6 is a view showing the manner in which intermediate processing results are stored in a buffer RAM in accordance with the conventional apparatus. Best Mode for Carrying Out the Invention An embodiment of the invention will now be described in detail with reference to the drawings. Fig. 1 is a block diagram showing the inventive picture processing apparatus for performing time-sharing convolution processing. A main processor 1 provides a controller 2 with a command for controlling convolution processing. On the basis of this command, the controller 2 outputs control signals for time-sharing convolution processing. Picture data composed of e.g. 256 x 256 pixels are stored beforehand in a frame memory 3, the read-out address of which is designated by a source counter 31. On the basis of a control signal from the controller 2, the source counter 31 designates the address of the frame memory 3, whereby pixel data of a predetermined row and column that is the object of processing is outputted from the frame memory 3 to a convolution processor 4. The convolution processor 4 performs convolution processing on a time-sharing basis, e.g. in five stages, with regard to the predetermined pixel data from the frame memory and e.g. a 5 x 5 coefficient matrix in a coefficient memory (not shown). The output of the convolution processor 4 is applied to one input of an adder 5. Applied to the other input of the adder 5 are output data from a data latch circuit 6. The adder 5 adds intermediate processing results from the convolution processor 4 and previous intermediate processing results from the latch circuit 6. The effective period of the output of adder 5 is determined by a control signal from the controller 2. The output of the adder 5 is applied to a delay circuit, e.g. a pipeline register 7. The pipeline register 7 is constituted by e.g. a D-type flip-flop and delays the output of the adder 5 until the start of the next convolution processing cycle. The output of the pipeline register 7 is applied to a bus buffer 8. The bus buffer 8 is on/off controlled by a control signal from the controller 2. It is possible for the output of the pipeline register 7 to be written into a buffer RAM 9 during the time that the bus buffer 8 is on. Since the output of the adder 5 is delayed by the pipeline register 7, the starting address for writing data in the RAM 9 is shifted by +1 whenever intermediate processing results are added. The buffer RAM 9 stores the intermediate processing results of time-shared convolution processing and is adapted to store the intermediate processing results of time-shared processing with regard to one row of pixel data in frame memory 3. In the prior art, it will suffice if the RAM is large enough to store 256 pixels. In accordance with the present invention, however, the address is incremented each time intermediate processing results are obtained owing to the provision of the pipeline register 7. With time-sharing processing performed in five stages, therefore, an additional area equivalent to four pixels is required. An address counter 10 applies a write/read address to the buffer RAM 9 under the control of the controller 2. When data are written in the buffer RAM 9, a starting address for writing in the intermediate processing results of the first stage and starting addresses for writing in subsequent intermediate processing results are successively incremented by +1 address. Also, when reading data out of the buffer RAM 9, it is required that starting addresses for reading out the intermediate processing results of the first, second, third, fourth and fifth stages be incremented by +1 address as set forth above. An address register 11 is provided for this purpose. By effecting operation in such a manner that an address value incremented by +1 over the starting address of each intermediate processing is preset from the address counter 10, "+1" will be stored in the address register 11. Whenever each partial convolution processing cycle ends, the value in the address register 11 is preset in the address counter 10 as the starting address value of the address counter 10 under the control of the controller 2, thereby incrementing the starting address by +1. With the first stage of intermediate processing, however, the counter 10 is cleared to start from address 1. When intermediate processing results are read out, the address counter 10 sends the intermediate processing results, the address whereof is designaged by the address counter 10, to the data latch circuit 6. When five stages of partial convolution processing of one row have been performed, the complete convolution results regarding pixels corresponding to the third row of frame memory 3, namely are outputted from the adder 5. Thus, the results of convolution processing regarding the fourth, fifth, ..., 254th rows of the frame memory 3 are successively outputted at every five stages of partial convolution. Therefore, these results can be transferred to a frame memory 13. A destination counter 12 is used for the transfer. The operation of the invention will now be described with reference to Figs. 2 and 3. Fig. 2 is a time chart illustrating write/read timing with respect to the buffer RAM 9, Figs. 3(a) through (d) illustrate the manner in which intermediate processing results are written in the buffer RAM 9 in first, second, third and fourth stages, respectively, and Fig. 3(e) illustrates the results of the fifth stage of processing, namely the complete convolution results. The results of the fifth stage of processing are stored in the frame memory 13 directly without being written in the buffer RAM 9. Fig. 2(a) illustrates one row of pixel data in the frame memory 3, and Fig. 2(b) illustrates a first cycle of write timing with respect to the buffer RAM 9. As for writing the first cycle of intermediate processing results, assume that the contents of the data latch circuit 6 are cleared without reading data out of the buffer RAM 9. The first stage of intermediate processing results from the convolution processor 4 are stored at the second through 257th addresses of the buffer RAM 9, as shown in Fig. 3(a). Here the data at the second, third, 256th and 257th addresses are invalid data. As for writing the second stage of intermediate processing results, first the data written in the buffer RAM 9 from the second to the 257th addresses are read out at the timing of reading R shown in Fig. 2(c), and these data are stored in the data latch circuit 6. Next, the first stage of intermediate processing results stored in the latch circuit 6 are read out at the timing shown in Fig. 2(d), these results are added to the next intermediate processing results from the convolution processor 4 by the adder 5 at the timing shown in Fig. 2(f), the results of the addition are delayed by the pipeline register 7, as shown in Fig. 2(h), this delayed second stage of intermediate processing results are written in the buffer RAM 9 at the timing shown in Fig. 2(g). The write timing shown in Fig. 2(g) is formed by controlling the bus buffer 8 by controller 2, as mentioned above. The starting address of buffer RAM 9 at which the second stage of intermediate processing results are stored is shifted by an address of "+1", as will be understood from Figs. 2(a), (h). Thus, the intermediate processing results of the second stage are written in the buffer RAM 9 from the third address to the 258th address, as shown in Fig. 3(b). Here the data at the third, fourth, 257th and 258th addresses, namely the two pixels of data at the left and the two pixels of data at the right, are invalid data. Next, as for writing the third stage of intermediate processing results, the intermediate processing results of the second stage stored in the buffer RAM 9 from the third to the 258th addresses must be read out and stored in the data latch circuit 6. However, the third address incremented by +1 from the second address, which is the starting address of the second cycle, is preset in the address counter 10 by the address register 11. As a result, it is possible to read from the third address of the buffer RAM 9. Here control is exercised by the controller 2 in such a manner that an address value incremented by +1 from the starting address of intermediate processing is preset in the address register 11 from the address counter 10 at all times. Thus, in the third stage of writing, the intermediate processing results of the third stage are written in the buffer RAM 9 from the fourth to the 259th addresses, as shown in Fig. 3(c). When the fourth stage of writing is performed, the initial value "1" now in the address counter 10 is preset to "4" by the address register 11 and the intermediate processing results of the third stage are read out from the fourth address of the buffer RAM 9 and stored in the data latch circuit 6. In the fourth stage of writing, the intermediate processing results of the fourth stage are written in the buffer RAM 9 from the fifth to the 260th addresses, as shown in Fig. 3(d). Thus, in the fifth stage, the complete convolution results shown in Fig. 3(e) are stored in the third row of the frame memory 13 directly without being written in the buffer RAM 9. Thus, as set forth above, the pipeline register 7 is provided behind the adder 5 and the timing at which the intermediate processing results are written is delayed by one address by the pipeline method, as illustrated in Fig. 2(h), as a result of which there is no drop in the high processing speed of the convolution processor 4. In other words, the intermediate processing results can be written in the buffer RAM 9 reliably without the predetermined processing cycle T of the convolution processor 4 being affected. Furthermore, with the one-address of the write timing, the intermediate processing results of the previous processing cycle written in synchronism with the immediately preceding write timing can be read out reliably by incrementing the starting address of the address counter 10 by "+1" whenever the intermediate processing results are to be read. Industrial Applicability In accordance with the picture processing apparatus of the present invention, a delay circuit such as a pipeline register is provided behind an adder and intermediate processing results from the adder are coordinated with the timing at which data are written into a buffer RAM. This makes it possible to write data in the buffer RAM with assurance and, at the same time, enables an increase in the convolution processing speed. Further, it is arranged so that an address counter and an address register are combined to designate the address of the buffer RAM, and the initial value in the address counter is revised and set to a value which takes a shift in the write address into account. Accordingly, predetermined intermediate processing results are read out of the buffer RAM reliably.

Claims: A picture processing apparatus for performing convolution processing with regard to plural items (A 1,1 to A 256,256 ) of pixel data organised in matrix form comprising rows and columns on a time-sharing basis i.e. in a plurality of successive stages with a predetermined coefficient matrix (C₁₁ to C₅₅) comprising rows and columns, the number of stages being identical to the number of rows of said latter matrix, comprising: a frame memory (3) storing said plural items of pixel data; processing means (4) for executing convolution processing with regard to each item of said pixel data on a time-sharing basis in said plurality of successive stages with coefficient matrix data; buffer means (9) for storing the intermediate processing results of one stage obtained by said convolution processing; adding means (5) for reading out the stored intermediate processing results of one stage and adding these results to intermediate processing results concerning the next stage and obtained from said processing means in the next processing cycle; and addressing means (10,11) for designating a write address of said buffer means and for designating an read address of said buffer means; characterised by delay means (7) for delaying the addition results for a predetermined time period and storing the same in said buffer means by rewriting the intermediate processing results in said buffer means; and said addressing means designating said read address of said buffer means upon revising said read address by an amount equivalent to a shift in the write address due to a delay time set by said delay means. A picture processing apparatus according to claim 1, characterized by having data latch means (6) for performing control in such a manner that intermediate processing results of a preceding cycle are read out to said adding means (5) in the next processing cycle of said processing means (4). A picture processing apparatus according to claim 1, characterized in that said delay means is constituted by a pipeline register 7. A picture processing apparatus according to claim 1, characterized in that a storage capacity of said buffer means (9) is modified and set in dependence upon coefficient matrix data used by said processing means (4).

Inventors: KURAKAKE, MITSUO, MURAOKA, YUTAKA, OTSUKA, SHOICHI
Applicants: FANUC LTD.
Application year: 1987
Main classification: G06F15
IPC codes: G06T7, G06F17, G06T13, G06T5