CORRELATOR CIRCUIT AND DEVICE FOR ULTRASOUND FLOW MAPPING COMPRISING SUCH A CIRCUIT

Abstract: A circuit for determining the cross-correlation function between two digitally sampled signals comprises a plurality of fractional step delay (FSD) digital interpolation filters (86, 87, 88) which estimate the value of one of said input signals at intervals between said samples and a plurality of correla­ tion circuits (89-97) each of which determined the correlation between the first signal and the output of one of said interpolation filters. A device for ultrasound flow mapping comprising such a circuit has an improved accuracy.

Description: The invention relates to a correlator circuit for determining the cross-correlation of a first input signal and a second input signal, said input signals each being represented as a series of discrete digital samples having a sample period τ. The invention further relates to a device for determining parameters of movement in a media by ultrasound pulse-echo measurements, comprising at least one ultrasound transducer, means for exciting emission of a pulsed echo sound signal from said transducer at a pulse repetition frequency F = 1/T, means for receiving ultrasound echoes which are reflected from said media back to said transducer and for processing such signals in a digital processing channel which acts on discrete samples of A-line signals received from said transducer and comprises, in cascade, means for suppressing signals in said A-lines which originate from fixed regions in said media, flow parameter estimation means, discriminator means, and means for displaying estimates of flow parameters. In pulse-echo ultrasound investigations, the velocity of ultrasound scatterers can be estimated from the relative time delay between signals in successive A-lines. This relative time delay can be determined from the value of a time lag which maximizes the cross-correlation of signals from two successive A-lines. The use of correlation functions makes it possible to measure time delays between signals as described, for example, in the article "The Generalized Correlation Method for Estimation of Time Delays", C.H. Knapp and G.C. Carter, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-24, No. 4, 1976. If the ultrasound scatterers have low velocity, the relative time delay between the signals in successive A-lines may be much shorter than the pulse repetition rate of the ultrasound transmitter (that is: the time interval between signal samples). Conventional discrete time correlators only generate correlation estimates for time lags which are multiples of the signal sample interval. Thus, when the scatterer velocity is low, it is difficult to accurately locate the maximum of the cross-correlation function from cross-correlation samples that are spaced at multiples of the sample interval. This problem is particularly severe if the cross-correlation estimates are computed with one-bit correlators. It is an object of the invention to provide a correlator circuit that overcomes the above-mentioned difficulty. The correlator circuit according to the invention is characterized in that it comprises a plurality of fractional step delay (FSD) digital interpolation filters, each of said filters functioning to interpolate the value of a filter input signal at a different predetermined time between discrete signal sample times, and a plurality of discrete time correlation estimator circuits connected in cascade with said interpolation filters. The implementation and use of fractional-step delay (FSD) digital filters is described in the article "State Space Realization of Fractional-Step Delay Digital Filters with Applications to Array Beam Forming", Shu-Hung Leung and Casper W. Barnes, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-32, No. 2, April 1984, pages 371-380. According to the invention a device for determining the parameters of movement in media of the kind set forth in the preamble is characterized in that the flow estimation means comprise a correlator circuit according to the invention. Fractional step delayed signal estimates are correlated, preferably using one-bit correlators, to locate the maximum of the cross-correlation function of the A-line signals. Fractional step correlators are relatively simple devices which are implementated with the full desired signal precision, that is 8, 12 of 16 data bits. Once fractional step delay estimates have been generated using the FSD filters, the cross-correlations of the full precision data can be efficiently computed with the data limited to one-bit. When using FSD digital filters, the complexity of hardware used to implement an ultrasound velocity measuring scanner can be reduced if the A-line signal is interpolated prior to correlation. The multiplications required for the FSD filters can be efficiently implemented by a table look-up using ROMs. A description of the prior art and a detailed description of an embodiment of the present invention is made with reference to the appended drawings in which: Figure 1 is an ultrasound, time domain flow imaging scanner of the prior art; Figure 2 is a fixed echo suppressor of the prior art; Figure 3 is a 1-bit correlator of the prior art; and Figure 4 is a discriminator of the prior art. Figure 5 represents a linear interpolation function; Figure 6 represents the application of the function of Figure 1 to interpolate a signal; Figure 7 represents a sinc interpolation function; Figure 8 represents the application of the function of Figure 3 to interpolate a signal; Figure 9 represents the truncated, delayed unit pulse response of a sinc (k (τ)) filter, Figure 10a and 10b are alternate block diagram representations of the interpolator; Figure 11 is a fractional step-delay digital filter using a transversal filter architecture; Figure 12 is a block diagram of a correlation estimator; Figure 13 is a fractional step correlation estimator; Figure 14a is a fractional step cross-correlator; Figure 14b illustrates the application of the correlator of Figure 10A to ultrasound flow imaging. European patent application (Publication Number EP-A-0225667) having priorities of 3.12.85 and 25.3.86 is a document in accordance with Article 54(3)EPC and describes an instrument as shown in Figure 1 for producing images of fluid flow within a body by ultrasound pulse-echo techniques (especially of blood-flow in organs such as the heart). It comprises at least one ultrasound transducer 10 associated with a pulse generator which generates a periodic pulses signal at a pulse repetition frequency F = 1 / T. The transducer 10 is connected to a transmitter stage 20, a reception and signal processing stage 30, and a device 40 that effects mechanical scanning of the transducer. The transmitter stage 20 comprises a generator of electrical excitation signals that are sent toward the transducer 10 which converts them into periodic pulse trains of ultrasound energy. This emission is commanded by clock signals at the predetermined frequency F - on the order of, for example 5 kHz - by a sequencer comprising, an oscillator having a frequency of, for example, 32 megahertz, and a frequency divider. The divider delivers clock signals as well as other command signals to connections 104 and 106 respectively, at 1 kilohertz and 16 megahertz in the example described here. A T-R switch prevents the blinding of the reception circuits by the emission signals. The reception and processing stage 30 comprises, at the output of the T-R switch, a high-frequency amplifier 300 (which includes means for compensation of gain as a function of the depth) followed by two parallel signal processing channels 301 and 302. Channel 301 is the conventional type, and comprises, in series, an envelope detector 310, a logarithmic compression amplifier 311, a storage and scanning conversion device 370 (which also includes a color coding function), and a display device 312. This channel 301 forms images of the media explored, in a gray scale, based on the principles of classic echography. Channel 302 comprises, in series, a fixed echo suppression circuit 320, a flow parameter estimation circuit 330, a discriminator circuit 360, the storage, scanning conversion and color coding device 370, and the display device 312. In Figure 2 the digital fixed-echo suppression circuit 320 comprises an analog-digital converter 321 whose output is connected directly to the negative input of a subtractor 322 and through a delay circuit 323 to the positive input of the same subtractor. The delay of circuit 323 can be equal to T. Circuit 320 eliminates all fixed echoes, especially those caused by the reflection of the ultrasound energy from the walls of the vessels which contain the flows under study. Fixed echoes are annoying due to their much higher amplitude (on the order of +40 dB in the case of blood flows) than the working signals which are back-scattered by moving targets. Circuit 320 is commanded, through connection 106, by the frequency divider of the sequencer that provides it with the sampling command signal at the 16 MHz frequency. Figure 3 shows the flow parameter estimation circuit 330. It comprises correlation circuits and an interpolation circuit. On the bases of the difference between two successive echographic A-lines of samples d i (t), d i+1 (t), etc ... (where i represents the index of this signal) successively furnished by the fixed echo suppression circuit 320, the correlation circuit delivers an odd number (2I + 1) of correlation function values. The interpolation circuit thus delivers parameters which characterize the various flows encountered along the axis of propagation of the ultrasonic wave on the basis of these values. These parameters are here the axial components of the average local speed V Z and the local variance σ2 of the latter, ("local" here being used in the sense of the localization in depth along the axis of propagation.) The correlation circuits comprise (2I + 1) correlators 342 which directly receive the output d i+1 (t) of feed echo suppression circuit 320 and, at a second input, receive this same output delayed by delays 341 and therefore corresponding to the preceding signal d i (t). Furthermore, each of delays 341 has a distinct delay which assumes (2I + 1) values from T - IΔt to T + IΔt, where Δt is the sampling interval to permit computing the (2I + 1) values of the correlation function. This parallel computation of the (2I + 1) values of the correlation function uses K successive samples of the two input signals of the correlators. The groups of K samples define successive time windows of length KΔt offset gradually at the cadence of the frequency imposed by connection 106. The correlation function is defined by an expression of the type: in which: J determines the start of the time window of length KΔt, P is the time delay introduced bwtween d i and d i+1 ranging from -I to +I, i is the rank of the difference between two successive echographic lines e i and e i+1 . The correlators 342, commanded through output connection 106 of the frequency divider of the sequencer, are preferably 1-bit correlators (for example type TDC 1023 made by TRW, La Jolla CA 92038). When the embodiment described comprises these 1-bit correlators, the interpolation circuit 350 is then, in general, a linear interpolation circuit. The interpolation circuit 350 can be a programmed microprocessor, or preferably a wired computer unit. This interpolation circuit works as follows: in a first stage there is a search for the maximum value among the (2I + 1) values of the correlation function, the two adjacent correlation function values are associated with it, and these three values permit the reconstitution of the principal correlation peak, in isoceles form. The abscissa τ(J) of the principal peak of correlation gives access to the local speed V Z at depth by multiplication according to the formula: and the amplitude f MAX of this peak gives access to the variance by operating according to the formula: where A is a factor of proportionality. Between each of the correlators 342 and the corresponding inputs of the interpolation circuit 350 there is an average computing circuit (which is in fact an accumulator), each comprising an adder 344 and a delay line 345 with a delay T. These average computing circuits permit the accumulation of the correlation function values on N successive A-lines, and to find their average. The adders 344 and the delay lines 345 are connected to the sequencer by connection 104 to be reset to zero at regular (N x T) intervals. The output signals from the flow parameter estimation circuit 330 are then validated by a discriminator circuit 360. The values thus confirmed are sent toward the display device 312 by means of color coding device 370. The presence of the discriminator circuit 360 (shown in Fig. 4) is essential. Outside of flow zones the output signal from fixed echo suppression circuit 320 is noise and the output of the flow parameter estimation circuit 330, which processes this noise, is not an indication of a zero speed. Circuit 360 therefore comprises, in series, a multiplier 361 which receives and squares the output signal d i from the feed echo suppression circuit 320; a summor 362 which computes the local energy of this difference signal according to the formula: a circuit (364, 365) which computes the average of the local energy on N shots, (as in the case of circuit 344 and 345 it is an accumulator comprising an adder 364 and a delay line 365 of delay T), that is to say (N-1) differences according to the expression: The average value computer is followed a validation circuit which comprises a comparator 461 which receives on a first input the output from the accumulator 364, 365 and on a second input 462a reference voltage forming a threshold. The output from the comparator 461 is the logic level 0 or 1 depending on whether the voltage from the accumulator is below or above the reference threshold. Two multipliers 463 and 464 receive, respectively, the output signals from circuit 330 at their first input, and transmit these two signals, hereinafter V' Z and σ'2 at their respective outputs or simply transmit zero values depending on whether the validation signal delivered at their second input by comparator 461 is respectively 1 or 0. Outside the true flow zones, the average energy computed at the output from circuit 364, 365 is that of noise alone, and can be measured in the absence of excitation, to determine the appropriate value of the threshold. In the presence of signals back-scattered by the moving targets, the average energy of the signal d i is higher than that of the noise alone; this validates signals delivered by flow parameter estimation circuit 330. The two outputs of the discriminator circuit 360 are sent towards the storage, scanning conversion and color coding device 370. In accordance with the invention the flow estimation circuit comprises a correlator circuit comprising FSD interpolation filters and discrete time correlators which will now be explained in detail. FSD Digital Interpolation Filter Let x (nτ) denote digital samples of a signal taken with a sample period τ. The signal values between sample times can be approximated by using an appropriate interpolating function in the following form: where g(t) is an interpolating function. Figure 5 illustrates a linear interpolating function g(t) which has values of 0 for a t = ± τand a value of 1 for t = 0. In this case the interpolated function comprises a series of straight line approximations as illustrated in Figure 6. The linear interpolating function of Figure 5 requires infinite bandwidth. For band limited interpolation let In this case the interpolating function g(t) has the form illustrated in Figure 7 and the interpolated signal will have the form illustrated in Figure 8. A time delay interpolator can be constructed by taking samples of x(t) with sample period τ and with sample times that are offset by a fraction of ξ from the original samples; that is y (mτ) = x(mτ-ξ) (9) where 0 < ξ < τ. (10) These samples can be obtained from the interpolated signal using equation 11: Let hξ(n) = g(nτ - ξ) (12) then Thus, the interpolated samples can be obtained from the original samples by a discrete convolution which represents a time-invariant filtering operation y(nτ) = x(nτ)·h(n) (14) where h(n) is the unit pulse response of the interpolating filter. To ensure that h(n) is finite and causal, it may be necessary to truncate the interpolating function and to introduce a delay Kτ; thus, in practice the interpolating filter should compute y(m τ) = x(mτ - Kτ - ξ) (15) where K is a positive integer chosen to be sufficiently large so that g(nτ - Kτ - ξ ) = 0 for n<0. (16) Thus the filtering operation for the time delay interpolator is where h ξ (n) = g (nτ- Kτ - ξ). (18) Figure 9 illustrates the truncated pulse response of a sinc (Kτ) interpolator for the case n = 6 and K = 2. Figure 10a and 10b are alternate representations of the transfer function of such an interpolator. Figure 11 illustrates the implementation of the FSD filter using a conventional transversal filter architecture with n = 5. The input signal passes through cascade delay elements 71, 72, 73, and 74 each having a delay period τ. The delay cascade is tapped and signals from the successive delays are multiplied by factors h ξ (0), h ξ (1), h ξ (2), h ξ (3), and h ξ (4) in multipliers 75, 76, 77, 78, and 79 respectively. The output signals from the multiplier 75 through 79 are summed in adding circuits 80a, 80b, 80c, and 80d to produce the filter output. The multiplying factors are calculated using equations 17 and 18 and standard digital filter design techniques as described in the above-mentioned background references. The FSDfilter is typically constructed to match the precision of the input signal, for example 8, 12, or 16-bit data. For 8 or 12-bit data the multipliers can be efficiently implemented by table look-up with ROMS. Discrete-Tome Correlators The cross-correlation between two discrete-time signals, a(nτ) and b(nτ), can be estimated from time averages of the form where the sum is taken over a finite number of terms and C is an appropriate normalizing constant. A discrete correlation estimator can be represented in block diagram form as shown in Figure 12. Figure 13 illustrates a fractional step correlation estimator. A first signal a(nτ + Kτ) is passed through a constant delay circuit 81 with delay time K. The second input signal b(nτ + Kτ) is passed through FSD interpolation filter 82 with transfer function h ξ (n). The outputs of circuits 81 and 82 are applied to inputs of a discrete time correlation estimator 83 the magnitude of whose output is an estimate of the cross-correlation between the signals a(nτ) and b(nτ - ξ). Figure 14a is an example of a fractional step cross-correlator 98. A first signal a(nτ + Kτ) is applied to a first input of a fixed delay circuit 84 having a delay time Kτ. The second input signal b(nτ + Kτ) is applied to the input of a second delay circuit 85 which is identical to the delay circuit 84. The second input signal is also applied to the inputs of a number of (in this example three) FSD interpolation filters 86, 87, and 88 having, for example, respective delay times of τ/4, τ/2, and 3τ/4. The output of delay circuit 84 is separately correlated with the output of delay circuit 85 and with the outputs of the fractional step interpolation filters 86, 87, and 88 in discrete time correlation estimator circuits 89, 90, 91 and 92 whose estimates respectively represent the cross-correlation of the input signals at times 0, τ/4, τ/2, 3τ/4. The same inputs are respectively applied to discrete time correlation estimators 93, 94, 95 and 96 which are constructed to cross-correlate signals spaced by sample interval - τ and whose outputs respectively represent estimates of the cross-correlation of the signals at period -τ, -3τ/4, - τ/2, and - τ/4. The outputs of delay circuits 84 and 85 are further applied to a single discrete time correlation estimator 97 having an integral delay of τ whose output is an estimate of the correlation of the input signals at time τ. The respective outputs of the correlation estimators 89-96 represent the cross-correlation function of the input signals. Although fractional step delays of τ/4, τ/2 and 3 τ/4 were used in this embodiment, FSD filters can be designed to produce fractional step delays with any value between zero and τ(where τ is the sample period). For example, one could use N FSD filters with any N different values of delay. Figure 14b illustrates the application of the fractional step correlator in a flow estimator 330 for use in the prior art ultrasonic pulse echo flow measuring device of Figure 1. The output of the fixed echo suppressor 320 is applied to the first input of a fractional step correlator 98 and to the input of a fixed delay 99 having a delay period T equal to the pulse repetition period of the ultrasound transmitter 20. The output of the delay 99 is applied to the second input of the fractional step correlator 98 so that the respective inputs of the fractional step correlator represents successive ultrasound echo A-lines with fixed echoes suppressed. The output signals from the correlation estimators in the fractional step correlator 98 are applied, through the discriminator 360 and the scan converter and color coder 370 to determine the color of regions in the display 312, as in the prior art scanner. Although the present invention has been described as a cascade fractional step delay interpolation filters followed by 1-bit correlation estimators, it is also possible to construct the fractional step correlator in a manner similar to that indicated in the prior art Figure 3 with fractional step interpolation filters acting on the output of correlation estimators.

Claims: A correlator (98) circuit for determining the cross-correlation of a first input signal (a) and a second input signal (b), said input signals each being represented as a series of discrete digital samples (nτ + kτ) having a sample period τ, characterized in that it comprises a plurality of fractional step delay FSD digital interpolation filters (86,87,88), each of said filters functioning to interpolate the value of input signal at a different predetermined time between said second discrete samples, and a plurality of discrete time correlation estimator circuits (89-93) connected in cascade with said interpolation fiters so that each of said circuits (85-93) determines the correlation between said first signal and an output of one of said interpolation filters. A correlator circuit as claimed in claim 1 characterized in that said first input signal is applied to a first input of each of said correlation estimators, said second input signal being applied to the input of each of said FSD interpolation filters, and the output of each said FSD filters being applied to second inputs of corresponding ones of said discrete time correlation estimators. A correlator circuit as claimed in claim 1, characterized in that it further comprises first fixed delay means, having a delay period Kτ, said first input signal being applied to the input of said first delay means and second fixed delay means having a delay period Kτ, said second input signal being connected to the input of said second delay means, each of said FSD interpolation filters being connected to receive samples of said second input signal and to generate an estimate of the value of said second signal at a different time between the discrete samples times of said signal, so that each of said FSD filters estimates the value of said second signal at a separate time between said discrete sample times and each of said discrete time correlation estimator circuits having a first input connected to receive delayed samples of the first signal from the output of said first fixed delay means and having a second input connected to receive one of the estimates of the value of said second signal from a corresponding output of either said second delay means or one of said interpolation filters, to generate therefrom an estimate of the cross-correlation between the inputs supplied to said first and second inputs. A correlator circuit as claimed in anyone of claims 1, 2 or 3, characterized in that said discrete time correlation estimator circuits are one-bit correlators. A correlator circuit as claimed in anyone of the preceding claims, characterized in that the said fractional step delay interpolation filters are constructed to interpolate the value of said second input signal at a set of intervals which are fractions of the sample period τ after said discrete sample times of said second signal. A correlator circuit as claimed in claim 5 characterized in that it comprises N-1 fractional step delay interpolation filters which are constructed to interpolate the value of said second input signal at intervals of Kτ / N after said discrete sample times of said second signal where N is an integer greater than 1 and k = 1, 2, 3, ... N-1. A device for determining parameters of movement in a media by ultrasound pulse-echo measurements, comprising at least one ultrasound transducer, means for exciting emission of a pulsed echo sound signal from said transducer at a pulse repetition frequency F = 1/T, means for receiving ultrasound echoes which are reflected from said media back to said transducer and for processing such signals in a digital processing channel which acts on discrete samples of A-line signals received from said transducer and comprises, in cascade, means for suppressing signals in said A-lines which originate from fixed regions in said media, flow parameter estimation means, discriminator means, and means for displaying estimates of flow parameters, characterized in that said flow estimation means comprise a correlator circuit as claimed in anyone of the preceding claims.

Inventors: BARNES, CASPER WILLIAM
Applicants: NORTH AMERICAN PHILIPS CORPORATION
Application year: 1987
Main classification: G06F15
IPC codes: G01S15, A61B8, G01S7, G06F17