PATTERN TRANSFER PROCESS FOR FABRICATING INTEGRATED-CIRCUIT DEVICES

Abstract: Available high resolution electron-beam-sensitive resists such as PBS are characterized by poor resistance to dry etching. Such resists are therefore not suitable for use in standard trilevel-resist processes that are essential for submicron lithography. As disclosed herein, a very thin layer (24) of a wet-etchable metal is substituted for silicon dioxide in the conventional trilevel structure. Since PBS exhibits good robustness to wet etching, patterns in PBS can be transferred into the very thin metal layer without significantly degrading line-edge quality. The metal layer then serves as a robust mask to dry etch the pattern into the underlying planarizing layer (22).

Description: PATTERN TRANSFER PROCESS FOR FABRICATING INTEGRATED-CIRCUIT DEVICES Backeround Qf# Invention This invention relates to the manufacture of integrated-circuit devices and, more particularly, to a method for transferring a pattern defined in resist into an underlying layer of a device structure. Increasing miniaturization of semiconductor integrated-circuit devices is the basis for reduced unit cost per function and for improved performance. Feature sizes in very-large-scale-integrated (VLSI) devices thus continue to get smaller. As feature sizes of VLSI devices decrease, processing requirements for fabricating the devices become more critical. These requirements include the availability of resists characterized by extremely high sensitivity and resolution. Moreover, for improved resolution and linewidth control, such resists must in many cases of be included in a so-called trilevel structure of the type described in U. S. Patent No. 4,244,799 and in "High Resolution, Steep Profile, Resist Patterns" by J. M. Moran and D. Maydan, Iht Bell Svstem Teclln;cal Vol. 58, No. 5, May. June 1979, pages 1027-1036. Such a structure typically includes a top resist layer, an iptermediate masking layer made, for example, of silicon dioxide and a bottom planarizing layer. In such a trilevel structure, pattern transfer from the resist must typically be done by anisotropic dry etching techniques. A number of negative and positive resists having the requisite sensitivity and resolution for VLSI device fabrication are known. One particularly attractive electron-sensitive positive resist is a material known as Poly(Butene.1 Sulfone) (PBS), which is described by M. J. Bowden and L. F. Thompson in "Electron Irradiation of Poly(olefin Sulfones) Application to Electron Beam Resists, Journal Qf Applied PolvmerScience, Vol. 17, pp. 3211-3221 (1973). Unfortunately, however, PBS and a number of other known resists otherwise suitable for VLSI device fabrication exhibit extremely poor resistance to dry etching. Thus, these resists have been generally regarded as not suitable for utilization in standard processes involving dry etching. In particular, these resists have therefore not been considered feasible for inclusion in trilevel structures. The present invention enables the utilization in a trilevel pattern transfer process of resists that exhibit poor dry etching characteristics. Summary Qf th e Invention A thin layer of a wet-etchable metal (such as chromium) is utilized as the intermediate layer directly underlying PBS in the modified structure. PBS exhibits good resistance to wet etching. Patterns defined in PBS can therefore be transferred into the metal layer in an isotropic wet-etching step. Since the metal layer is extremely thin, the isotropic nature of the wet-etching step does not in practice substantially degrade line-edge quality. The pattern thus formed in the metal layer is therefore a highly accurate replica of the resist pattern. The patterned metal layer then serves as a robust mask for dry etching the underlying planarizing layer of the trilevel structure. Brief Description Qf the Drawing FIG. 1 is a representative showing of a conventional trilevel structure of the type utilized to fabricate integrated-circuit devices; and FIG. 2 depcits a variation of the FIG. 1 structure as modified in accordance with the principles of the present invention. Detailed DescriDtion FIG. 1 represents a portion of a standard integrated-circuit device that comprises conductive elements 10 and 12 disposed on a substrate 14. Deposited on the top surface of the substrate 14 and covering the elements 10 and 12 is a layer 16 made of a conventional dielectric material such as p-doped glass. In accordance with standard steps of a known device fabrication sequence, openings or windows are to be formed in the layer 16 of FIG. 1 in aligned registry with the underlying conductive elements 10 and 12. A conductive material such as aluminum will then be deposited on the top surface of the device and in the aligned windows to establish electrical connections from an upper level of the device structure to the elements 10 and 12. A trilevel resist structure of the type described in the aforecited Fraser et al patent and Moran et al article is a particularly advantageous way of patterning the layer 16 As indicated in FIG. 1, such a known trilevel structure includes, from top to bottom, layers 18, 20, and 22. The layer 18 shown in FIG. 1 comprises a positive or negative resist material that can be selectively patterned by, for example, directing light, electrons, X-rays, or ions thereat. A wide variety of such materials are well known in the art. Many standard techniques are available for selectively exposing and developing these materials to form a specified high-resolution pattern in the layer 18. The intermediate layer 20 in the known structure of FIG. 1 comprises, for 0 example, a 120SAngstrom-unit (A)-thick layer of plasma-deposited silicon dioxide. In standard ways, the pattern in the resist layer 18 is transferred into the layer 20 by dry etching techniques. Illustratively, this is done by either plasma or reactive-ion etching the layer 20 with, for example, CHF3, utilizing the patterned layer 18 as a dry-etch-resistant mask therefor. The planarizing layer 22 shown in the standard structure of FIG. 1 comprises, for example, a relatively thick layer of an organic material. A number of available organic materials are suitable for forming the layer 22. Such materials include a variety of known resists and polyimides. Illustratively, the layer 22 comprises a 1.8-micrometer (pm)-thick layer of KPR-206 which, after deposition, is, for example, baked for about 20 minutes at approximately 210 degrees Celsius. HPR-206 is a standard positive photoresist commercially available from Philip A. Hunt Chemical Corporation, Palisades Park, New Jersey. The pattern in the layer 20 of FIG. 1 is transferred into the thick layer 22 in an anisotropic dry etching step. This is done, for example, in a reactive-ionetching or rf-sputter-etching step utilizing pure oxygen to form a plasma, with the patterned layer 20 acting as a mask. The openings thereby formed in the layer 22 exhibit substantially vertical walls, as indicated in FIG. 1. A conventional trilevel structure of the type shown in FIG. 1 and described above is an important factor in being able in practice to achieve sub micron lithography. Unfortunately, however, as specified earlier above, PBS and a number of other known resists exhibit such poor resistance to dry etching that they have been heretofore considered as not suitable for inclusion in trilevel structures. In accordance with the the present invention, the intermediate layer 20 of FIG. 1 is replaced with an extremely thin layer made of a wet-etchable metal. When such a material is utilized in conjunction with a resist that exhibits good resistance to wet etching (but poor resistance to dry etching), an effective basis is provided for including otherwise unsuitable resists in a trilevel structure. A specific illustrative trilevel structure modified in accordance with the principles of the present invention is shown in FIG. 2. Portions of the FIG. 2 structure that may be identical to corresponding portions of FIG. 1 are identified in FIG. 2 with the same reference numerals employed in FIG. 1. In FIG. 2, reference numeral 24 designates the aforementioned wetetchable layer. Illustratively, the layer 24 comprises a 300-to-50GA-thick layer of chromium. By way of example, the layer 24 is deposited on the entire top surface of the layer 22 in a standard sputtering step at a bias of approximately 400 volts dc. In practice, a chromium layer formed in this manner is substantially pin-hole free and exhibits low stress. Layer 26 overlying the chromium layer 24 of FIG. 2 comprises, for example, a layer of PBS resist. Illustratively, the layer 26 is formed by spincoating a 400GA-thick layer of PBS onto the layer 24 and then baking the coating for about 30 minutes at approximately 120 degrees Celsius. Subsequently, a prescribed pattern is formed in the resist layer 26 in standard ways known in the art. This is done, for example, by selectively irradiating the resist layer 26 with an electron beam in a direct-writing mode at a current density of about 2.5to3 microcoulombs per square centimeter. Standard wet development of the positive resist layer then results in removal of irradiated portions. Postbaking of the developed resist at about 120 degrees Celsius for approximately 30 minutes is then typically carried out. This leaves a patterned resist layer 26, as indicated in FIG. 2. The presence of a metallic (chromium) layer underlying the resist layer 25 during electron-beam exposure has been found to be advantageous. In practice, such a metallic layer causes the exposure of the resist layer to be more uniform than if the layer underlying the resist were made of, say, silicon dioxide as in a standard trilevel structure. In turn, more uniform exposure leads to better line-edge quality in the final pattern defined in the resist. Additionally, the presence of the metallic layer 24 in the trilevel structure of FIG. 2 is advantageous because it effectively prevents charge buildup during electron-beam exposure. Such buildup, if allowed to occur, can in practice lead to distortions in the patterned resist image by displacing the writing spot from its expected location. By connecting the metallic layer 24 to a point of reference potential such as ground on, for example, a workpiece holder, charge impinging on the trilevel structure during exposure is prevented from accumulating on the structure. Another advantageous property of the thin layer 24 described herein is that in practice it is relatively transparent to backscattered signals emanating from standard alignment marks (not shown) formed on the substrate 14. This facilitates conventional level-to-level registration during device fabrication. The pattern formed in the PBS resist layer 26 of the trilevel structure shown in FIG. 2 is then transferred into the chromium layer 24 in a wet-etching step. Illustratively, this is done by employing a standard solution of water and ceric ammonium nitrate in the approximate ratio of 2-to-1 by volume. This is the conventional chromium wet etch that is widely used in industrial clean rooms for production fabrication of photomasks. The aforespecified wet-etching step is isotropic in nature. But, since the chromium layer 24 is so thin (300-to-500 A), negligible undercutting occurs. In practice, line-edge quality in the pattern transfer process is therefore not substantially degraded. Subsequently, the patterned chromium layer 24 of FIG. 2 is utilized as a mask for conventional dry etching of the underlying thick layer 22. This is done, for example, in a standard reactive-ion-etching step utilizing an oxygen plasma, as is well known. In that way, substantially vertically walled features are transferred into the thick layer 22, as shown in FIG. 2. The patterned layer 22 of FIG. 2 is then utilized as a mask for processing of the underlying device structure. In practice, the overall transfer process described herein has been demonstrated to have a 0.25-#m-resolution capability with excellent image quality. Other resists that exhibit poor plasma erosion resistance but good resistance to wet etching and that may be used in a trilevel structure in conjunction with an underlying wet-etchable layer include PMPS, FB:vL-G, EBR-9, etc., as described by T. Tamamura, S. Imamura and S. Sugawara in "Resists for Electron Beam Lithography," Polvmers in Electronics, T. Davidson, editor (1984), ACS Symposium Series 242, pp. 103-118. Also, thin layers of wetetchable materials other than chromium may be employed to form the pattern transfer layer utilized to carry out applicants' inventive process. Examples of such materials are tungsten, aluminum, tantalum, and molybdenum. Additionally, the invention is not limited to pattern transfer processes that involve electron-beam exposure of resists, but is applicable to other exposure processes in which, for example, X-ray lithography is employed to selectively irradiate a wet-etch-resistant resist.

Claims: C1a#ims 1. A pattern-transfer method for fabricating integrated-circuit devices, said method characterized by the steps of: patterning a resist layer (26) that exhibits relatively poor resistance to dry etching but relatively good resistance to wet etching of specific substrate materials, utilizing said patterned resist layer as a mask, etching an underlying relatively thin layer (24), thereby transferring the pattern in said resist layer into said underlying layer, and utilizing the pattern thus formed in said relatively thin layer as a mask, etching a relatively thick underlying layer 22, thereby transferring the pattern in said first-mentioned underlying layer into said second-mentioned underlying layer, CHARACTERIZED BY wet etching said relatively thin layer, which layer is of a material that exhibits relatively poor resistance to wet etching but relatively good resistence to dry etching, and dry etching said relatively thick underlying layer, which layer is of a material that exhibits relatively poor resistance to dry etching. 2. A method as in claim 1 wherein said relatively thin layer comprises chromium. 3. A method as in claim 2 wherein said relatively thick layer comprises the planarizing layer of a trilevel structure. 4. A method as in claim 3 wherein said resist layer comprises PBS resist. 5. A method as in claim 4 wherein said chromium layer is formed in a bias-sputtering step. 6. Method as in claim 5 wherein said chromium layer is approximately 300-to-500 A thick. 7. A method as in claim 6 wherein said chromium layer is wet etched in a 2-to-1 solution of water and ceric ammonium nitrate. 8. A method as in claim 7 wherei#n said relatively thick layer is anisotropically dry etched in an oxygen plasma.

Inventors: MANSFIELD WILLIAM MICHAEL, VAIDYA SHEILA, MANSFIELD, WILLIAM, MICHAEL, VAIDYA, SHEILA
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1987
Main classification: G03F7
IPC codes: G03F7, H01L21