SENSE CIRCUIT FOR THE STATE OF MATRIX CELLS IN MOS EPROM MEMORIES

Abstract: The matrix cells have their drains connected to a first preset load, and an identical selection voltage is applied to the gate of a chosen matrix cell and to the gates of two virgin reference cells with a second conductance load equal to double that of the first load, and the respective currents which cross the two cells are compared in a differential amplifier. Respective current generators are connected to inject in said first and said second load respective identical currents, each approximately equal to the difference between the current in the virgin cell and the current in the written cell.

Description: The present invention relates to a sense circuit for the virgin or written state of matrix cells in MOS EPROM memories. The first types of sense circuits for the (programed or virgin) state of the cells of EPROM memories employed a current source (typically a depletion transistor) as load and the cell as switch to form a simple inverter. In normal operation, if the gate of a virgin cell was brought to the supply voltage, the output of the inverter was low. If instead the cell was programed, the output of the inverter was high. Such sense circuits according to the prior art were however affected by various disadvantages. First, the selection of the load current was critical, since it had to be small enough to allow the cell to lower the output of the inverter in the case of a virgin cell but also high enough to be able to rapidly raise the output of the inverter in the case of a programed cell, so that access time be brief. Moreover, with low supply voltages the cell conducted a very small current, and therefore the supply voltage operating interval was small, since the gate of the cell, which was brought to the supply voltage during a read operation, had to be distinctly higher than the threshold voltage, so that the conductance of the cell be greater than in the load transistor. The operating interval was also limited by the fact that with high supply voltages even the programed cells started to conduct, causing read errors. In order to eliminate the above described disadvantages, a differential sensing method was adopted, wherein the cells of the matrix were compared with a reference cell. In practice, the matrix cell and the reference cell derived current from two load transistors, and the voltages at the two outputs were compared by a differential amplifier. If both cells or both transistors variated in their characteristics, this caused a shift of the common-mode voltage but no variation of the differential voltage, and the dependence from the cell/load ratio was thus eliminated. With this method, the reference cell is crossed by a current which is greater than that of the programed cell, and is equal to that of the virgin cell. If a non-zero output voltage is desired from the readout of a virgin cell, the load transistor must therefore be greater than the matrix load, usually 2 to 5 times greater. However, this method, too, has limitations. In fact, in the linear operation region of the cells the difference between the currents in the matrix cell and in the virgin reference cell is constant, as will be described in greater detail hereinafter. As mentioned above, the state of the cell is determined by the ratio between the two currents, and since this ratio tends toward 1 as the gate voltage increases, read errors occur when this voltage exceeds a certain threshold. The operating interval is thereby limited. The aim of the invention is therefore to provide a sense circuit for the state of matrix cells in MOS EPROM memories, having a supply voltage operating interval which is greater than that of the sense circuits according to the prior art. The invention achieves the aim described above, as well as other objects and advantages which will become apparent hereinafter, with a sense circuit for the virgin or written state of matrix cells in MOS EPROM memories, wherein the matrix cells have their drains connected to a first preset load, and wherein an identical selection voltage is applied to the gate of a chosen matrix cell and to the gate of a virgin reference cell with a second preset load, and the respective currents which cross the two cells are compared in a differential amplifier, characterized in that the second load's conductance is double that of the first load, in that said virgin reference cell is connected in parallel to a second identical cell having its gate driven by the same selection voltage, and in that respective current generators are connected to inject in said first and said second load respective identical currents, each approximately equal to the difference between the current in the virgin cell and the current in the written cell. A preferred embodiment of the invention will now be described, given by way of non-limitative example, with reference to the accompanying drawings, wherein: Fig 1 is a diagram of a sense circuit according to the prior art; Fig. 2 is an exemplary circuit diagram including the concepts of the invention; and Fig. 3 is a diagram which is useful for understanding the operation of the invention. With reference to Fig. 1, the reference numerals 10 and 12 respectively indicate a virgin reference cell and a matrix cell of a MOS EPROM memory. The two cells 10 and 12 have their sources connected to the ground the gates driven in common by a control voltage V G , and the drains connected to loads 14, 16, consisting of respective transistors supplied by a supply voltage V CC and with their gates high. The transistor 14 which constitutes the load of the reference cell is 2 to 5 times greater than the transistor 16. The drains of the cells 10 and 12 are also connected to the respective inputs of a differential amplifier 18 for sensing, adapted to provide an output which is proportional to the difference between the voltages V R and V S of the drains of the two cells. If the supply voltage V CC is high enough, the cell operates in the linear region. The drain voltage is proximate to 1 volt, and the virgin threshold voltage is approximately 2.5 volt. Thus the cell will be in the linear range for gate voltages higher than 3.5 volts. The current I sdV in the virgin cell is: I dsV = K*(V g - V T )*V ds - (K/2)*V² ds where V g is the gate voltage, V T is the threshold voltage, and V ds is the voltage drop between the drain and the source. If the threshold shift is ΔV, the current I dsP in the programed cell is: I dsP = K*(V g - V T - ΔV)*V ds - (K/2)*V² ds Since the drain voltage is constant, by setting A = K*V ds and C = (K/2)*V² ds , the above described equations can be reduced to I dsV = A*(V g - V T ) - C (1) I dsP = A*(V g - V T - ΔV) - C, (2) which by subtraction yield the difference between the two currents: I dsV - I dsP = A*ΔV. (3) The difference current is thus constant for any gate voltage so long as one remains in the linear range. Moreover, by dividing I dsV obtained from (3) by I dsP , the ratio R between the two currents is obtained: R = (I dsP + A*ΔV)/I dsP . (4) Supposing the load transistor of the reference cell is 2 times that of the matrix cell, in order to have the sense circuit supply a logical "0" in output the ratio R must be smaller than 2. But from equation (4) it can be seen that as I dsP increases, that is to say, as the gate voltage V g increases, this ratio tends to 1, causing read errors if the gate voltage is too high. The invention starts from the idea of using loads which, instead of being different for the matrix cell and for the reference cell, in order to obtain difference and non-zero voltages on the sense circuit for the two states (virgin or programed) of the matrix cell, are instead identical on the two cells, while a displacement current is injected in the comparison between the current in the matrix cell and that in the reference cell. If the matrix cell is virgin, the difference in current between the same and the reference cell is zero. If the matrix cell is instead programed, the difference in current is a constant, that is to say A*ΔV . Thus the most desirable current value for the comparison of the matrix cell would be a current I S equal to the average between the current in the virgin cell and the current in the programed cell, that is to say I S = I dsP + A*ΔV/2 In this manner, and with reference to the graph of Fig. 3, the curve of the reference current assumes the same shape as the curve of the programed current, shifted by a constant amount ½A*ΔV , regardless of the value of the supply voltage. Thus the acceptable supply voltage interval for the safe discrimination between the virgin and programed states of the cell would extend in practice up to the cell's operational limits, since the curve is in every point parallel and substantially equidistant from the other two. In theory, it is possible to obtain the current I S using a programed reference cell, rather than a virgin one, but such a cell would be erased together with the matrix cells when the memory is erased. Though it is possible to protect a cell against erasure by means of a metallic covering, this would require excessively large structures. The invention overcomes this difficulty using a displacement current approximately equal to the difference between I dsP and I dsV , which is added both to the matrix cell and the reference cell. Moreover, in the invention a second reference cell is coupled in parallel to the first, and at the same time said two reference cells are provided with two load transistors in parallel, so that the reference current is double that of the virgin cell. It will become apparent hereinafter that such a circuital combination operates in a manner substantially equivalent to that of the circuit described above. The sense circuit according to the invention is illustrated in Fig. 2, wherein: 20 is a matrix cell; 22 is a transistor with its gate high acting as a load for the cell 20; 24 is a cell driven by a voltage generator 26 connected to inject a desired current into the load 22; 28, 30 are two identical virgin reference cells, arranged in parallel; 32 is a transistor with its gate high, and with its channel twice as wide as the transistor 22, so as to have double conductance with respect thereto; and finally 34 is another cell driven by the same voltage generator 26, and adapted to inject in 32 a current identical to that which crosses 24. The voltage generator 26 is designed, in a manner which is obvious for the expert in the field, so as to apply to the gates of the cells 24, 34 a voltage V diff such as to create in each cell an identical current I diff approximately equal to the difference between the currents I dsP and I dsV . The voltages V R and V S produced at the ends of the loads 22, 32 by the currents which cross them are applied to the inputs of a sense differential amplifier 36, adapted to provide an output voltage which is proportional to the difference between the inputs. Designating I ref as the reference current, I sense as the sense current in the load of the matrix cell, I cell as the current in the generic cell, I diff as the difference current between the current in the programed cell and the current in the virgin cell, the following thus occurs in the circuit branch comprising the elements 20, 22 and 24: I sense = I diff + I cell (5) and in the reference branch comprising the elements 28, 30, 32 and 34: I ref = I diff + 2*I cell ; (6) Since the conductance of the transistor 32 is double that of the transistor 22, the amplifier 36 compares voltages which are proportional to I ref and to I sense , respectively, and from (5) and (6) the following is derived: ½I ref = I sense = - ½I diff . Since the reference cell is always a virgin cell, the current I ref is equal to I dsV , while the current I sense in the matrix cell is either I dsV or I dsP , which are related by the relation: I dsP = I dsV - I diff . (7) Thus, if the matrix cell is virgin, the difference in currents sensed by the amplifier 36 is: ½I ref - I sense = I dsV + ½I diff - [I dsV + I diff ] = - ½I diff . If the matrix cell is instead programed, using (7) the following is obtained: ½I ref - I sense = I dsV + ½I diff - [I dsP + I diff ] = I dsV + ½I diff - [I dsV - I diff + I diff ] = ½I diff It can thus be observed that the comparison between I sense and I ref provides values for the two states of the matrix cell (virgin or programed) which are substantially identical in amplitude but have opposite sign. The condition of parallelism between I ref and I dsV and I dsP is still true, so that the operational interval of the supply voltage is increased. Though the Figures illustrate a single matrix cell, in the practical embodiment of the memory a plurality of cells divided in lines will be provided, and for each line there will be a sense circuit similar to the one described above It is obvious that the exemplary diagram illustrated in Fig 3 is susceptible to variations and refinements, within the scope of the illustrated operating principles, for example in perform compensations and stabilization, as is known in the field. It is therefore understood that the scope of the invention extends to all the modifications and variations equivalent to the preferred embodiment, according to the teachings given, without thereby abandoning the scope of the invention.

Claims: Sense circuit for the virgin or written state of matrix cells (20) in MOS EPROM memories, wherein the matrix cells have their drains connected to a first preset load (22), and wherein an identical selection voltage is applied to the gate of a chosen matrix cell (20) and to the gate of a virgin reference cell (28) with a second preset load (32), the respective currents which cross the two cells are compared in a differential amplifier, and the second load's conductance is double that of the first load, characterized in that said virgin reference cell (28) is connected in parallel to a second identical cell (30) having its gate driven by the same selection voltage, and in that respective current generators (24, 34) are connected to inject in said first and said second load respective identical currents, each approximately equal to the difference between the current in the virgin cell and the current in the written cell. Sense circuit according to claim 1 characterized in that said current generators comprise respective transistors connected in parallel respectively to said reference cell and to said matrix cell, and a fixed voltage generator (26) which drives the gates of said transistors. Sense circuit according to claim 2, characterized in that said transistors belonging to the current generators are virgin cells. Sense circuit according to one of the preceding claims, built into a solid-state EPROM memory.

Inventors: CAMPARDO, GIOVANNI, NOVOSEL, DAVID
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1987
Main classification: G11C7
IPC codes: G11C16, G11C7, G11C17