SENSE AMPLIFIER CIRCUIT FOR SEMICONDUCTOR MEMORY

Abstract: A sense amplifier circuit comprises a first am­ plifier circuit (Q₁, Q₂) for detecting the data from a memory cell and generating an output signal in accord­ ance with the detected data, a first load MOS transistor (Q₃) of one conductivity type connected between an out­ put terminal of the first amplifier circuit (Q₁, Q₂) and a power source terminal (VC), a second amplifier circuit (Q 1A , Q 2A ) for detecting the data from a dummy cell and generating an output signal in accordance with the de­ tected data, a second load MOS transistor (Q 3A ) of one conductivity type and a third load MOS transistor (Q₁₃) which are connected in parallel between an output ter­ minal of the second amplifier circuit (Q 1A , Q 2A ) and the power source terminal, and a comparator (3) for com­ paring the output signals from the first and second amplifier circuits (Q₁, Q₂, Q 1A , Q 2A ) and generating an output signal in accordance with the result of the com­ parison. The third load MOS transistor (Q₁₃) is a MOS transistor of an opposite conductivity type whose back gate is connected to a reference potential terminal.

Description: The present invention relates to a sense amplifier circuit which is used in an electrically programmable nonvolatile semiconductor memory or the like and, more particularly, to a sense amplifier circuit for comparing a bit line potential on the memory cell side and a reference potential on the dummy cell side. An electrically programmable nonvolatile memory, for example, an electrically programmable read only memory (EPROM) of the ultraviolet erasing type is constituted so as to have a memory cell array 1 and a sense amplifier 3, as shown in Fig. 1. In memory cell array 1, memory cells MC of, e.g., the floating gate type, are arranged in a matrix form, and word lines WL₁ to WL M and bit lines BL₁ to BL N are selectively coupled to those memory cells. One end of each of N-channel MOS transistors QB₁ to QB N for selecting the bit lines is commonly connected to a node NB. Bit lines BL₁ to BL N are respectively connected to the other ends of MOS transistors QB₁ to QB N . MOS transistors QB₁ to QB N are connected such that their conduction states are controlled by an output of a column decoder (not shown). Node NB is connected to an input terminal of a bit line potential amplifier circuit 2 whose output terminal is connected to an input node N₁ of a differential amplifier type comparator 3 such as a P-channel current mirror type comparator. Amplifier circuit 2 includes an enhancement type N-channel MOS transistor Q₁ connected between bit line node NB and a power source terminal VC; an enhancement type N-channel MOS transistor Q₂ whose one end is connected to bit line node NB; and an enhancement type P-channel MOS transistor Q₃ whose gate and drain are connected to the other end of MOS transistor W₂ and whose source is connected to power source terminal VC. A predetermined bias voltage VBA is applied from a bias voltage generator 4 to the gates of MOS transistors Q₁ and Q₂ through a bias line BSL. Bias voltage generator 4 comprises: a P-channel MOS transistor Q₄ which is connected between power source terminal VC and bias line BSL and whose gate is grounded; an N-channel MOS transistor Q₅ whose gate and drain are connected to bias line BSL; and an N-channel MOS transistor Q₆ whose gate and drain are connected to the source of MOS transistor Q₅ and whose source is grounded. Each of memory cells MC in memory cell array 1 is selectively set to either one of the states in which data was written, i.e., the state ("0" state) in which a threshold voltage V TH is high, and the erasing state in which no data is written, i.e., the state ("1" state) in which threshold voltage V TH is low. Therefore, in the reading mode, the data read out of the selected memory cell is amplified to bit line potential VB by bit line potential amplifier circuit 2 and thereafter, it is supplied to one input terminal N₁ of comparator 3. In this case, it is assumed that when the data read out of the memory cell in the "0" or "1" state is amplified by amplifier circuit 2, it is converted into bit line potential VB₀ or VB₁, respectively. A MOS transistor Q₇ for controlling the writing operation whose conduction state is controlled in accordance with inverted data D in of write data D in is connected between bit line node NB and a high voltage terminal VP to which a writing voltage is applied. Therefore, in the case of writing data into the selected memory cell, it is possible to effect control such that high voltage VP is applied to the drain of the selected memory cell in which a high voltage is also applied to the control gate. Comparator 3 is the current mirror circuit comprising two N-channel MOS transistors Q₈ and Q₉ for amplification and two P-channel MOS transistors Q₁₀ and Q₁₁ serving as loads. A reference voltage generator 5 is used to apply a reference voltage V ref to the other input terminal N₂ of comparator 3 and has a bit line potential amplifier circuit 6 which is constituted in a manner almost similar to bit line potential amplifier circuit 2. Amplifier circuit 6 includes: MOS transistors Q 1A to Q 3A which are constituted and connected in a manner similar to MOS transistors Q₁ to Q₃ in amplifier circuit 2; and a MOS transistor Q₁₂ connected between power source terminal VC and input terminal N₂. Reference potential generator 5 further has a floating gate type dummy cell DC in which one end is grounded and the other end is connected to amplifier circuit 6 through a bit line BLD and an N-channel MOS transistor QBD. Dummy cell DC is set into the erasing state or "1" state and power source voltage VC is applied to the control gates of dummy cell DC and MOS transistor QBD. It is required to set reference potential V ref which is generated from reference potential generator 5 so as to satisfy the relation of VB₀ > V ref > VB₁, i.e., in such a manner that V ref is lower than potential VB₀ at which the bit line is set when the data is read out of the memory cell in the "0" state and V ref is higher than potential VB₁ at which the bit line is set when the data is read out of the memory cell in the "1" state. For this reason, comparator 3 can certainly generate the output signal corresponding to the data read out of the selected memory cell. Thus, conventionally, in addition to MOS transistor Q 3A of the same size as MOS transistor Q₃, MOS transistor Q₁₂ is connected in parallel with MOS transistor Q 3A as the resistance load of the bit line in reference potential generator 5. Consequently, the synthesized ON resistance of MOS transistors Q 3A and Q₁₂ is smaller than the ON resistance of MOS transistor Q₃ and the relation of V ref > VB₁ is derived. In this manner, reference potential V ref is set to a value between potentials VB₀ and VB₁ for a standard power source voltage VCS of, e.g., 5 V. As shown in Fig. 2, reference potential V ref and bit line potentials VB₀ and VB₁ vary in accordance with a change in power source voltage VC. As will be obvious from Fig. 2, reference potential V ref changes at an increase rate larger than that of bit line potential VB₀ in association with an increase in power source voltage VC. When power source voltage VC rises to a VC₁ level of, e.g., 6 V, reference potential V ref becomes almost equal to bit line potential VB₀. When power source voltage VC further increases, V ref becomes larger than VB₀, causing a malfunction of the sense amplifier circuit. The difference of dependency on power source voltage VC between bit line potential VB₀ and reference potential V ref is caused by the difference between the size of load MOS transistor Q₃ in amplifier circuit 2 and the total size of load MOS transistors Q 3A and Q₁₂ in reference potential generator 5. In the sense amplifier circuit shown in Fig. 1, the allowable range between a standard power source voltage VCS and the maximum allowable power source voltage VC₁, namely, the power source voltage margin cannot be set to a sufficiently large value. Therefore, not only is it likely to cause a malfunction of comparator 3 by a variation in power source voltage VC, but also there is a possibility of causing a malfunction of comparator 3 by other factors, for example, by variations in circuit element parameters and in writing voltage into the memory cell as well. For example, even if reference potential generator 5 is designed to generate proper reference potential V ref when it is driven by standard power source voltage VCS (= 5 V), there is a case where the sense amplifier circuit in the memory IC actually manufactured cannot normally operate at a power source voltage VC = 5 V because of a variation in element parameters due to a fluctuation in manufacturing processes. It is an object of the present invention to provide a sense amplifier circuit which can always correctly operate without being largely influenced by a fluctuation in power source voltage. This object is accomplished by a sense amplifier circuit comprising: a first amplifier circuit for detecting data from a memory cell and generating an output signal in accordance with the detected data; a MOS transistor of one conductivity type connected between an output terminal of the first amplifier circuit and a power source terminal; a second amplifier circuit for detecting data from a dummy cell and generating an output signal in accordance with the detected data; a MOS transistor of one conductivity type and a MOS transistor of an opposite conductivity type which are connected in parallel between an output terminal of the second amplifier circuit and the power source terminal, a back gate of the MOS transistor of the opposite conductivity type being connected to a reference potential terminal; and a comparator for comparing the output signals of the first and second amplifier circuits and generating an output signal in accordance with the result of the comparison. In this invention, since the back gate of the MOS transistor of the opposite conductivity type is connected to the reference potential terminal, when the power source voltage rises, the ON resistance of the MOS transistor of the opposite conductivity type rises. Thus, the rate of the output signal of the second amplifier circuit which increases with an increase in power source voltage is reduced. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a memory circuit including a conventional sense amplifier circuit; Fig. 2 shows the relation between a power source voltage and each of a reference potential and a bit line potential in accordance with the data read out of the selected memory cell in the memory circuit shown in Fig. 1; Fig. 3 is a circuit diagram of a memory circuit including a sense amplifier circuit according to an embodiment of the present invention; and Fig. 4 shows the relation between a power source voltage and each of a reference potential and a bit line potential in accordance with the data read out of the selected memory cell in the memory circuit shown in Fig. 3. Fig. 3 shows an EPROM including a sense amplifier circuit according to an embodiment of the present invention. The sense amplifier circuit is constituted in a manner almost similar to the sense amplifier circuit shown in Fig. 1 except that a bit line potential amplifier circuit 6A in a reference potential generator 5A has an N-channel MOS transistor Q₁₃ whose substrate or back gate is grounded and whose drain and gate are connected to power source terminal VC in place of MOS transistor Q₁₂. In the circuit shown in Fig. 3, the same parts and components as those in the circuit shown in Fig. 1 are designated by the same reference numerals and their descriptions are omitted. In Fig. 3, the size and parameters of an N-channel MOS transistor Q₁₃ are set such that when power source voltage VC has standard value VCS, reference potential V ref is set to an intermediate potential between bit line potentials VB₀ and VB₁. In this manner, in this embodiment, the synthesized ON resistance of MOS transistors Q 3A and Q₁₃ in bit line potential amplifier circuit 6A is set to a value smaller than the ON resistance of MOS transistor Q₃ in bit line potential amplifier circuit 2. Therefore, in the reading mode, for example, when the data is read out of the memory cell in the "0" state, bit line potential VB₀, which is applied to input terminal N₁ of comparator 3, is higher than the bit line potential which is read out of dummy cell DC and is amplified by bit line amplifier circuit 6A. Thus, comparator 3 generates the output data in accordance with the data in the selected memory cell. In the sense amplifier circuit shown in Fig. 3, when power source voltage VC becomes higher than standard power source voltage VCS, the ON resistance of MOS transistor Q₁₃ increases due to the back gate bias effect, thereby suppressing an increase in reference potential V ref . Namely, the dependency of reference potential V ref on power source voltage VC decreases. For an increase in power source voltage VC, reference potential V ref rises more slowly, as compared with the reference potential in the sense amplifier circuit shown in Fig. 1. Therefore, as shown in Fig. 4, if power source voltage VC is lower than VC₂ level which is higher than the VC₁ level, the relation of VB₀ > V ref is satisfied. The maximum permissible voltage VC₂ is set to a value within a range of, e.g., 6.5 to 7 V. Consequently, the power source voltage margin is enlarged and a high operation margin is secured for a variation in power source voltage, variations in element parameters due to the fluctuation in manufacturing processes, and variations in writing conditions such as time and voltage required for writing data into the nonvolatile memory cell, and the like. The performance and yield of the memory products can be improved. Although the invention has been described above with respect to an embodiment, the invention is not limited to only this embodiment. For example, although the sense amplifier circuit used in the EPROM has been shown in Fig. 3, the sense amplifier circuit according to the invention can be also used in an electrically erasable programmable nonvolatile memory (EEPROM).

Claims: A sense amplifier circuit comprising: first amplifier means (Q₁, Q₂) for detecting data from a memory cell and generating an output signal in accordance with said detected data; a first load MOS transistor (Q₃) of one conductivity type connected between an output terminal of said first amplifier means (Q₁, Q₂) and a power source terminal (VC); second amplifier means (Q 1A , Q 2A ) for detecting data from a dummy cell and generating an output signal in accordance with said detected data; a second load MOS transistor (Q 3A ) of one conductivity type and a third load MOS transistor (Q₁₃) which are connected in parallel between an output terminal of said second amplifier means (Q 1A , Q 2A ) and said power source terminal; and comparing means (3) for comparing the output signals from said first and second amplifier means (Q₁, Q₂; Q 1A , Q 2A ) and generating an output signal in accordance with the result of the comparison, characterized in that said third load MOS transistor (Q₁₃) is the MOS transistor of an opposite conductivity type whose back gate is connected to a reference potential terminal. A sense amplifier circuit according to claim 1, characterized in that said third load MOS transistor is an enhancement type N-channel MOS transistor (Q₁₃) whose gate and drain are connected to said power source terminal (VC). A sense amplifier circuit according to claim 1 or 2, characterized in that said first load MOS transistor is an enhancement type P-channel MOS transistor (Q₃0 whose gate and drain are connected to the output terminal of said first amplifier means (Q₁, Q₂), and said second load MOS transistor is an enhancement type P-channel MOS transistor (Q 3A ) whose gate and drain are connected to the output terminal of said second amplifier means (Q 1A , Q 2A ) and which has substantially the same size as that of said first load MOS transistor (Q₃).

Inventors: SHIMAMUNE, YUJI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: G11C7
IPC codes: G11C7, G11C17, G11C16