INTERFACE, FOR EXAMPLE FOR A LIQUID CRYSTAL DISPLAY DEVICE

Abstract: An interface for converting separate video signals into a display data signal and a timing signal for operating a thin display panel comprises a timing circuit (101, 102, 103) for taking a timing so as to introduce effective display data into a data treating circuit (105) according to a synchronizing signal (Hsyc), a data treating circuit (105) for generating desired data for a thin display panel using the display data, and a timing signal generating circuit (104) for generating timing signals necessary for operating a driver of the thin display panel.

Description: This invention relates to interface circuits for example for thin displays, e.g. liquid crystal displays, EL displays, plasma displays or LED displays. More particularly, although not so restricted, the present invention relates to a thin display device having an interface circuit which can be used as a compact and lightweight display device by utilizing interface signals of CRT displays that have gained a wide application particularly in personal computers and the like. A liquid crystal display with a large-sized dot matrix panel has recently been employed as the display terminal of a personal computer or a word processor, because it is characterized by its thinness, low voltage and low power consumption. At present, a liquid crystal interface circuit capable of being connected directly with a CRT control circuit is being developed, so that such a panel may be used as the display terminal of a portable personal computer. However, the interface circuit of the thin display according to the prior art is designed so that the thin panel is driven even during the blanking period of the CRT display. Thus, the display data is read out sequentially after a frame buffer memory has been prepared by first writing the display data therein. Moreover, the original interface circuit of the prior art is especially for a monochromatic display, and so it lacks the capacity for the quantity of display information in the case of a graphic display or the like. Specifically, such a display is less attractive than the CRT display because one or two of the thin display data for red, green and blue are utilized and displayed simply in the ON-OFF manner on the simple matrix. On the other hand, however, an interface circuit for a multi-colored thin display is not yet practically developed, irrespective of both the establishment of the coloring filters on the surface of the transparent electrodes of a thin panel, and the development of a new liquid crystal panel having a storing function by having built therein an active element or a nonlinear element such as a TFT (i.e. Thin Film Transistor), metal-insulating film-metal (MIM) or metal-semi-insulator (MSI disclosed in our EP-A-202092A2) or a smectic liquid crystal. One interface circuit for use either with a CRT display or a liquid crystal display is disclosed in EP-A-0171 547. However, this circuit employs a frame buffer memory, which receives display data from a CPU, the interface circuit repeatedly reading out the data according to the CRT synchronization and scanning. Likewise, US-A-4275 421 discloses a control circuit for a liquid crystal display, in which a conventional television signal is read through a buffer. As has been described above, the interface circuit for the thin display according to the prior art is required to prepare the frame buffer memory as an external circuit to write in and read out the data under the administration of the interface circuit. This requirement raises the price of and complicates the circuitry so that the circuit is hard to be assembled into a small-sized display terminal. The present invention seeks to provide an interface circuit for a thin display, which has interface functions capable of giving display data to the thin display by using the real-time processing of input display data without storing them in a frame buffer memory (RAM) through the use of either a display data synchronizing signal of the CRT display or separate video signals having their composite signals separated. According to one aspect of the present invention there is provided an interface for converting separate video signals into a display data signal and a timing signal for operating a thin display panel characterised by a timing circuit arranged in response to at least one of a horizontal synchronizing signal (Hsyc) and a vertical synchronizing signal (Vsyc) to regulate the duration of a blanking period and arranged to generate a timing clock signal (P₁) at the end of the blanking period; a data treating circuit enabled by the timing clock signal to receive serial input display data and comprising means for converting the serial input display data into parallel display data, latch means for temporarily storing the parallel display data, and switching means for switching the output of the latch means in a time sharing manner for generating ouput display data; and a timing signal generator arranged to generate drive timing signals for operating driver circuits of the thin display panel. According to another aspect of the present invention there is provided a thin display device having a thin display panel, and an interface for converting separate video signals into a display data signal and a timing signal for operating the thin display panel, and characterised by a timing circuit arranged in response to at least one of a horizontal synchronizing signal (Hsyc) and a vertical synchronizing signal (Vsyc) to regulate the duration of a blanking period and arranged to generate a timing clock signal (P₁) at the end of the blanking period; a data treating circuit enabled by the timing clock signal to receive serial input display data and comprising means for converting the serial input display data into parallel display data, latch means for temporarily storing the parallel display data, and switching means for switching the output of the latch means in a time sharing manner for generating ouput display data; and a timing signal generator arranged to generate drive timing signals for operating driver circuits of the thin display panel. The thin display panel may have an X-Y dot matrix display electrode construction. In one embodiment the X-electrode comprises an uneven-numbered electrode group and an even-numbered electrode group, each of the groups being led out from opposite sides of the panel to each other. Preferably the data treating circuit gives 8 bits of desired data to the driver. The timing circuit may comprise an horizontal home position regulating circuit for controlling a timing so as to introduce horizontal effective display data into the data treating means, a vertical home position regulating circuit for controlling a timing so as to introduce vertical effective display data into the data treating means and a clock control circuit for generating a pulse when both of the horizontal and vertical display data are effective. In one embodiment at least one of the horizontal and vertical home position regulating circuit comprises a counter for counting a reference signal, external input means for arbitrarily setting the timing, and a coincidence detecting circuit for detecting a coincidence between the output of said counter and a set value of said external input means so that the display position is adjusted by said external input means. Additionally or alternatively at least one of the horizontal and vertical home position regulating circuit comprises delay time setting means for setting a desired delay time, synchronizing means for synchronizing the output of the delay time setting means to a clock signal, a counter for counting the clock signal according to the output of the synchronizing means, and initializing means for initializing the synchronizing means according to the output of the counter. The data treating circuit may comprise a data changing circuit for changing serial data of the display data into parallel data and storing the data temporarily, a first switching circuit for giving monochromatic data to the driver means, a second switching circuit for giving multicolor data to the driver, and a selecting circuit for selecting one of the switching circuits. In one embodiment, the data treating circuit comprises a color display data processing circuit, including an S/P converter circuit for converting R, G and B color display serial data into parallel form, color mixing and blending means for converting the output of said S/P converter circuit into mixed color data and a first group of switching circuits for switching said mixed color data, and a monochromatic display data processing circuit, including a second group of switching circuits for switching the output of said S/P converter circuit of at least one of said R, G and B display data. The data treating circuit may have display mode switching means for selectively switching ON and OFF the outputs of said color display data processing circuit and said monochromatic display data processing circuit. The data treating means may have display data reversing means for reversing said color display data. Preferably the data treating circuit has no RAMS. The invention is illustrated, merely by way of example, in the accompanying drawings, in which:- Figure 1 is a block diagram of one embodiment of an interface according to the present invention; Figure 2 is a block diagram of a second embodiment of an interface according to the present invention applicable to both the monochromatic and multicolor displays; Figure 3 is a block diagram of a third embodiment of an interface according to the present invention applicable to a color display; Figure 4 is a block diagram of a fourth embodiment of an interface according to the present invention applicable to a monochromatic liquid crystal display; Figure 5 is a circuit diagram of a fifth embodiment of an interface according to the present invention; Figure 6 is a timing chart explaining the operation of the interface of Figure 5; Figure 7 shows one embodiment of an electrode construction of a color liquid crystal display panel for use with an interface according to the present invention; Figure 8(A) shows an embodiment of a system for the monochromatic display, and Figure 8(B) shows an embodiment of a system for the color display; Figure 9 shows a sixth embodiment of an interface according to the present invention for a multicolor display; Figure 10 is a timing chart explaining the operation of the interface of Figure 9; Figure 11 is a circuit diagram showing a system of a color liquid crystal display with an interface according to the present invention; Figure 12 is a circuit diagram showing a sixth embodiment of an interface according to the present invention having a parallel bit selecting function to switch parallel display data into 4-bit or 8-bit data; Figure 13 is a timing chart explaining the operation of the interface of Figure 12; Figure 14 is a circuit diagram showing a seventh embodiment of an interface according to the present invention which can handle the various color dot arrangements (e.g. stripe, mosaic, inverse mosaic or triangle arrangements) of a color panel; Figure 15 shows various arrangement types of the color dots; Figure 16 shows one embodiment of a color arrangement selecting circuit of an interface according to the present invention; Figure 17 is a block diagram of an eighth embodiment of an interface according to the present invention for a multicolor flat type display; Figure 18 is a block diagram of a ninth embodiment of an interface according to the present invention where difficulty in connection is eliminated by separating an X-axis driver into two systems for upper and lower electrodes; Figure 19 is a timing chart explaining the operation of the interface of Figure 18; Figure 20 shows the construction of a color graphic liquid crystal display using an interface according to the present embodiment; Figure 21 is a block diagram showing a tenth embodiment of an interface according to the present invention for a color liquid crystal display; Figure 22 is a block diagram of an eleventh embodiment of an interface according to the present invention for monochromatic display. Figure 23 is a block diagram of a twelfth embodiment of an interface according to the present invention which can be admitted even at a low transfer speed by transferring data on a 8-bit parallel signal; Figure 24 is a timing chart explaining the operation of the interface of Figure 23; Figure 25 is a block diagram showing a system of a liquid crystal display according to a further embodiment of the present invention; Figure 26 is a diagram showing electrode construction of a liquid crystal panel using an interface according to the present embodiment; Figure 27 is a block diagram of a thirteenth embodiment of an interface according to the present invention; Figure 28 is a block diagram showing a fourteenth embodiment of an interface according to the present invention; Figure 29 is a block diagram showing the horizontal and vertical home position regulating circuits of an interface according to the present invention; Figure 30 is a block diagram of a fifteenth embodiment of an interface according to the present invention; Figure 31 is a timing chart explaining the operation of the interface of Figure 30; Figure 32 is a block diagram showing a sixteenth embodiment of an interface according to the present invention; Figure 33 is a timing chart explaining the operation of the interface of Figure 32; Figure 34 is a chart showing the timings of output signals of the interface of Figure 32; Figure 35 is a block diagram of a seventeenth embodiment of an interface according to the present invention; Figure 36 is a timing chart explaining the operation of the interface of Figure 35. Figure 1 is a block diagram of an interface according to the present invention. In Fig. 1, reference letters Hsyc denote a horizontal synchronizing signal; letters CK a dot clock signal; letters Vsyc a vertical synchronizing signal; letters DATA a display data signal. A horizontal home position regulating circuit 101 is used to regulate a stand-by time for regulating a blanking period continuing from the instant of reception of the horizontal synchronizing signal till reception of effective display data thereby to shift the horizontal home position to a left end. A vertical home position regulating circuit 102 is used to regulate a stand-by position for regulating a blanking period continuing from the instant of reception of the vertical synchronizing signal till reception of the effective display data thereby to shift the vertical home position to the highest one. Reference numeral 103 denotes a clock control circuit for regulating generation of a clock signal to allow a clock for generating a timing signal for change and display of the display data after the horizontal and vertical blanking periods thereby to control the number of effective display data per one line. Numeral 105 denotes a data treating circuit which is constructed of: a data changing circuit for either changing the serial data of the display data signal, Data, into a parallel signal or rearranging color display data of red, green and blue colors into mixed color display data of three primaries; a data regulating circuit that functions to regularly change the order of the color display data (i.e., red, green and blue color data) for each horizontal scanning into a mosaic pattern or a stripe pattern and to effect positive and negative displays; a monochromatic display data switching circuit for switching and outputting the output of the aforementioned data changing circuit in a time sharing manner; a switching circuit for switching the color display data in a time sharing manner; and a mono/multi color selecting circuit for selecting the switching circuits of mono/multi color display data and the display timing signals. Numeral 104 denotes a timing signal generator for outputting to a driver the timing signals such as a frame signal FRM, i.e., data for starting the scanning, a shift clock CP for shifting the display data or a latch signal LOAD for latching the display data shifted. As has been described above, the mono/multi color display data are inputted to the data treating circuit 105 and changed and treated so that they may be received by a driver and are then outputted to and displayed in the driver together with the timing signal of the timing signal generator 104. Fig. 2 is a block diagram showing the whole construction of one embodiment of an interface circuit applicable to both the mono and multi color displays. In Fig. 2, reference letters Hsyc denote the horizontal scanning signal; letters CK the dot clock signal; letters Vsyc the vertical scanning signal; and letters RD, GD and BD color video signals of red, green and blue colors. A horizontal home position regulating circuit 201 is used to regulate a stand-by time for regulating a blanking period continuing from reception of the horizontal synchronizing signal Hsyc till reception of effective display data so that the horizontal home position may be shifted to the left end. A vertical home position regulating circuit 202 is used to regulate a blanking period continuing from reception of the vertical synchronizing signal Vsyc till reception of effective display data so that the vertical home position may be shifted to the highest position. Numeral 203 denotes an AND circuit for regulating generation of the clock signal to allow a clock for generating timing signal for the data change and display in and after the horizontal and vertical blanking periods. Numeral 204 denotes a counter for dividing the frequency of the clock signal of the AND circuit 203 to monitor the number of the effective display data of one line and dot clock stopping means for counting the number of dot clocks to reset the horizontal home position regulating circuit 201. Numeral 205 denotes a data changing circuit for changing the serial data of the display data RD, GD and BD into parallel data or for rearranging the display data RD, GD and BD into mixed color display data. The data changing circuit 205 stores the data temporarily. Numeral 206 denotes a data regulating circuit which has functions to change the aforementioned display data RD, GD and BD into mosaic or stripe pattern for each horizontal scanning regularly in their order and to effect the positive and negative displays. Numeral 207 denotes a timing signal generator for outputting a timing signal such as the frame signal FRM, a control drive signal M, the shift clock CP or the latch signal LOAD to the driver so as to effect a liquid crystal display. Numerals 208 and 209 denote switching circuits for switching the output of the data changing circuit 205 in a time sharing manner. Especially the switching circuit 208 switches and outputs the color display data to the driver. The switching circuit 209 switches the monochromatic display data. Numeral 210 denotes a mono/multi color selecting circuit for selecting the time sharing timing of the aforementioned switching circuits 208 and 209, the timing of the shift clock CP and the mono/multi color display data in dependence whether the liquid crystal display is for color or monochromatic display. The aforementioned switching circuit 208 or 209 is switch in a time sharing manner to output display data UD₁ to UD₈ for upper electrodes and display data LD₁ to LD₈ for lower electrodes to the driver. Fig. 3 is a block diagram showing the construction of an interface which can be applied to the color display. Fig. 3 has a construction similar to the whole one of Fig. 2 excepting the mono/multi color selecting circuit 210 and the switching circuit 209. Moreover, the individual blocks have functions similar to those of Fig. 2, and the color video signals RD, GD and BD have their data changed by a data changing circuit 305 and subjected to a color mixing treatment and are switched in a time sharing manner by a switching circuit 308 to output the upper electrode display data UD₁ to UD₈ and the lower electrode display data LD₁ to LD₈ to the driver. Fig. 4 is a block diagram showing the construction of an interface which can be applied to the monochromatic liquid crystal display. Fig. 4 has a construction similar to the color interface construction of Fig. 3 excepting a data control circuit 306. Moreover, the individual blocks have functions similar to those of Fig. 3, but a data changing circuit 405 has no means for mixing the colors of the display data. The display data inputted in series are changed into parallel data by the data changing circuit 405. In the case of a 4-bit output, the parallel data are then switched in a time sharing manner to output the display data UD₁ to UD₄ and UD₅ to UD₈ in parallel. In the case of an 8-bit output, on the other hand, the time sharing is not conducted, but the display data UD₁ to UD₈ are outputted in parallel. The timing signal generator 407 likewise generates timing signals for feeding the driver with the frame signal FRM, the control drive signal M, the shift clock CP and the latch signal LOAD necessary for the liquid crystal display to output them together with the display data to the driver so that the liquid crystal display may be effected by the driver. The embodiment shown in FIG. 5 relates to an interface circuit which can select a display mode from monochromatic and multi colored displays. Fig. 5 is a circuit diagram showing one embodiment of the present invention, and Fig. 6 is a timing chart for supplementarily explaining the operations of the circuit of Fig. 5. In Fig. 5: reference letters Hsyc denote a horizontal synchronizing signal; letters Vsyc a vertical synchronizing signal; letters CK a dot clock signal; and letters RD, GD and BD the respective display data of red, green and blue colors. These signals Hsyc, Vsyc, CK, RD, GD and BD are equivalent to interface signals to be fed to a CRT display. Reference numeral 501 denotes an X-axis display position adjusting circuit for counting the number of the dot clocks CK to adjust the display position in the X-axis direction. Numeral 504 denotes a Y=axis display position adjusting circuit for counting the number of the horizontal synchronizing signals Hsyc to adjust the display position in the Y-axis direction. Numeral 503 denotes an AND circuit which is made receptive of both the outputs of the aforementioned X-axis and Y-axis display position adjusting circuits 501 and 504 and the dot clocks CK. Numeral 506 denotes a 1/8 frequency divider circuit for dividing the frequency of a clock signal P₁, i.e., the output of the aforementioned AND circuit 503 into one eighth. Numeral 507 denotes a frequency divider circuit for further dividing the frequency of the output P₂ of the 1/8 frequency divider circuit 506 to generate a reset signal P₃ for resetting the aforementioned X-axis display position adjusting circuit 501. Numerals 510, 511 and 512 denote shift register circuits for shifting the display data of red, green and blue colors. Numerals 513, 514 and 515 denote latch circuits for temporarily latching the display data of the shift registers 510, 511 and 512. Numerals 541 to 546 denote switching circuits for switching the display data of the latch circuits 513 to 515 in a time sharing manner to output the display data to the X-electrode driver circuit (which will be shortly referred to as the "X driver") of the liquid crystal display. Numeral 528 denotes a shift register for switching the aforementioned switching circuits 541 to 546 in a time sharing manner. Numerals 554, 555 and 556 denote Exclusive OR gates for inverting the display data of red, green and blue colors when a switch SW₁ is in ON state. Reference numerals 524 and 525 denote D-type flip-flop circuits (which will also be shortly referred to as the "D-type F/F circuit") which is made receptive of the aforementioned clock signal P₂ to generate a latch signal P₄. Numeral 521 denotes a set-reset flip-flop circuit for setting operations in response to the generation of the aforementioned latch signal P₄. Numerals 516 and 517 denote a D-type flip-flop circuit and a NOR circuit for generating a set pulse signal P₉ when the output T₂ of the aforementioned Y-axis display position adjusting circuit 504 rises to an "H" level. Numeral 518 denotes a flip-flop circuit for generating a set output in response to the aforementioned set pulse signal P₉. Numerals 547 and 548 denote D-type flip-flop circuits for delaying the output of the aforementioned flip-flop circuit 518. The output FRM of the aforementioned D-type flip-flop circuit 548 is a frame signal. Numeral 520 denotes a flip-flop circuit for dividing the frequency of the aforementioned frame signal into one half. The output of the flip-flop circuit 520 is an alternate drive signal M for alternately driving a liquid crystal. On the other hand, reference letters LK denote a latch signal which is latched from display data transferred to the X-axis driver circuit by a latch circuit built in the X-axis driver circuit. Numeral 531 notes a 1/4 frequency divider circuit for dividing the frequency of a clock signal P₁₀ into one quarter. Numeral 533 denotes a flip-flop circuit for dividing the frequency of the output P₁₃ of the aforementioned frequency divider circuit 531 into one half. Numerals 539 and 540 denote switching circuits for switching the display data of the aforementioned latch circuit 515. Numerals 535, 536 and 537 denote AND circuits and an OR circuit, which construct together a selecting gate circuit for selecting the shift clocks SK of a 4-bit parallel shift register built in the X-electrode driver circuit in the case of monochromatic or color display. Next, the operations of one embodiment of the present invention will be described in the following. The X-axis display position adjusting circuit 501 starts to count the number of the dot clocks CK when it receives the horizontal synchronizing signal Hsyc. When this counted value coincides with the set value of the blanking period of the display data, the output T₁ of the aforementioned X-axis display position adjusting circuit 501 rises to the "H" level. The setting of this blanking period can be adjusted at a unit of one dot by external setting means such as a digital switch. The Y-axis display position adjusting circuit 504 starts to count the number of the horizontal synchronizing signals Hsyc when it receives the vertical synchronizing signal Vsyc. When this counted value coincides with the set value of the blanking period of the display data in the Y-axis direction, the output T₂ of the aforementioned Y-axis display position adjusting circuit 504 rises to the "H" level. The setting of this blanking period can be similarly adjusted at a unit of one dot by external setting means such as a digital switch. When both the outputs T₁ and T₂ of the aforementioned X-axis and Y-axis position adjusting circuits rise to the "H" level, a display start (or home position) is taken so that the clock signal P₁ is outputted from the AND circuit 503. The clock signal P₁ is inputted to the 1/8 frequency divider circuit 506 and the shift registers 510, 511 and 512. The display data RD, GD and BD are shifted for each clock by the shift registers 510, 511 and 512 so that the aforementioned clock signal P₁ may be the shift clock. The output P₂ of the 1/8 frequency divider circuit 506 causes the D-type flip-flop circuit 524 and the NOR circuit 525 to generate the latch signal P₄, each time eight clock signals P₁ are inputted, and to latch the parallel display data of the aforementioned shift registers 510, 511 and 512 in the latch circuits 513, 514 and 515 thereby to conduct the S/P conversions. The latch signal P₄ is inverted by an inverter 526 to set the flip-flop circuit 521 so that an AND circuit 522 starts to output the clock signal P₁₀. This clock signal P₁₀ has its frequency divided by a 1/2 frequency divider circuit 527 and is inputted as the shift clock of the shift register 528. The shift register 528 uses the output of a NOR circuit 529 as the shift data so that it operates as a quaternary ring counter to generate switching control signals P₅, P₆ and P₇. As a result, the switching circuits 541, 542 and 543, and 544, 545 and 546 are turned on in a time sharing manner to output display data (UD₀ to UD₃) and (LD₀ to LD₃) in parallel. The clock signal P₁₀ has its frequency divided into one half by a flip-flop circuit 523 to output a clock signal P₈. Furthermore, the aforementioned flip-flop 523 is reset by the signal which was inverted from the shift data of the shift register 528 by an inverter 530 so that it outputs three clocks of the clock signal P₈ in response to eight clocks of the clock signal P₁₀ to generate the shift clocks SK through the AND circuit 536 and the OR circuit 537. The outputs of the latch circuits 515, 514 and 513 are inputted in the following manner to the switching circuits 541 to 546 to prepare the mixed R, G and B (i.e., red, green and blue) color display data. The switching circuits 541 to 546 are constructed of 4-bit parallel transmission gates and connected in the manner enumerated in the following table if their inputs are the 8th bits R₁, G₁ and B₁ to R₈, G₈ and B₈ from the 1st bits of the latch circuits 515, 514 and 513. As described above, the switching circuits 541, 543 and 545, and 542, 544 and 546 are grouped into the upper display data UD₀ to UD₃ and the lower display data LD₀ to LD₃, and the color display data RD, GD and BD are inputted alternately and separately from the 1st bits. As a result, the display data UD₀ to UD₃ generate the outputs (R₁, B₁, G₂ and R₃) (B₃, G₄ - - - and so on) whereas the display data LD₀ to LD₃ generate the outputs (G₁, R₂, B₂ and G₃) and (R₄, B₄ - - - and so on). Next, the timing signals to the liquid crystal display will be described in the following. The output T₂ of the Y-axis display position adjusting circuit 504 is inverted by an inverter 505, when it rises to the "H" level, so that the set pulse P₉ is generated by the D-type flip-flop circuit 516 and the NOR circuit 517 to set the flip-flop circuit 518. Then, the number of the clock signals P₂ the aforementioned 1/8 frequency divider circuit 506 is counted (up to 700, for example) by the frequency divider circuit 507 until the display data in the X-axis direction are inputted. After this, the reset signal P₃ is generated by a D-type flip-flop circuit 509 and a NOR circuit 508 to reset the X-axis display position adjusting circuit 501, the 1/8 frequency divider circuit 506, the frequency divider circuit 507 and the flip-flop circuit 518. This reset signal p₃ is used as both a latch signal LK for a latch circuit built in the aforementioned X-electrode driver circuit (i.e., the X driver) and a shift clock YSCL for a shift register built in the Y-electrode driver circuit (i.e., the Y driver). The output of the aforementioned flip-flop circuit 518 is delayed by the D-type flip-flop circuits 547 and 548 to output a frame signal FRM or data for starting the scanning of the Y-electrode driver circuit (i.e., the Y driver). The aforementioned frame signal FRM has its frequency divided by the 1/2 frequency divider circuit 520 to generate the AC drive signal M, which is outputted to the X-electrode and Y-electrode driver circuits, to reverse the polarity of the drive voltage. The description thus far made is directed to the case of the color display. Next, the case of the monochromatic display will be described in the following. The clock signal P₁₀ is inputted to the 1/4 frequency divider circuit 531 to output the 1/4 divided frequency output P₁₃, which further has its frequency divided into one half by the 1/2 frequency divider circuit 533 to output the switching control signals P₁₄ and P₁₅ of the switching circuits 539 and 540. The reversed output of the divided frequency output P₁₃ of the aforementioned 1/4 frequency divider circuit 531 is fed through the AND circuit 535 and the OR circuit 537 to output the monochromatic shift clocks SK of the aforementioned X-electrode driver circuit (i.e., the X driver). Exclusive OR circuits 554, 555 and 546 are polarity switching circuits for reversing or restoring the polarity of the aforementioned display data RD, GD and BD so that the polarity of these data RD, GD and BD can be reversed, when a switch SW₁ is turned on, and otherwise restored to switch the displays NEGA/Posi. On the other hand, a switch SW₂ is used to select the color and monochromatic dipslays. When this switch SW₂ is turned off, the reversed output of the output P₁₃ of the aforementioned 1/4 frequency divider circuit 531 is fed through the selecting gate circuit 535 and the OR circuit 537 to generate the shift clocks SK for the monochromatic display and at the same time to activate the outputs of the aforementioned switching circuits 539 and 540 thereby to raise the outputs of the switching circuits 541 to 546 to high impedances. When the switch SW₂ is turned on, on the contrary, the clock signal P₈ of the aforementioned flip-flop circuit 523 is fed through the AND circuit 536 and the OR circuit 537 to generate the shift clocks SK for the color display and at the same time to activate the outputs of the switching circuits 541 to 546 thereby to switch the outputs of the switching circuits 539 and 540 to high impedances. As has been described hereinbefore, the display modes can be switched between the color and monochromatic displays in accordance with the voltage level of a selecting terminal S₂. The displays NEGA/Posi can also be selected by setting the voltage level of a selecting terminal S₁. Fig. 6(A) is a timing chart showing the outputs T₁ and T₂ of the X-axis and Y-axis display position adjusting circuits. Fig. 6(B) shows the timing of the clock signals P₁ and P₃; Fig. 6(C) shows the timing of the switching control signals P₅, P₆ and P₇ and the display data UD₀ to UD₃ and LD₀ to LD₃; Fig. 6(D) shows the timing of the monochromatic display data LD₀ to LD₃; and Fig. 6(E) shows the timing the shift clocks CK, the latch clocks LK, the frame signal FRM and the AC drive signal M, i.e., the timing signals to be fed to the driver circuits of the liquid crystal display. Fig. 7 shows one embodiment of the electrode construction of a color liquid crystal panel in the case of the color display according to the present invention. The color array order of the electrodes should not be limited to that of the present invention. Fig. 8 shows system constructions of the embodiment of the present invention. Fig. 8(A) shows an example of the system construction for the monochromatic display, and Fig. 8(B) shows an example of the system construction for the color display. In view of Fig. 8, the present invention could be understood more deeply. As has been described hereinbefore, according to the present invention, conversions into the display data and timing signals of the liquid crystal display can be made on real time by using the interface signals of the CRT display. There can be attained the following outstanding effects. (1) Since no frame buffer memory is required, the small-sized inexpensive liquid crystal display terminal can be manufactured by integrating the gate array. (2) The interface circuit for the color display nonexisting in the prior art can be provided to increase the attraction of the liquid crystal display. (3) The display modes can be selected between the monochromatic and color displays by the single interface circuit. (4) Since the same driver circuit as that of the prior art can be used, it is unnecessary to develop the driver circuit especially for the color display. Moreover, the present invention is especially effective for a new liquid crystal panel of strong dielectricity making use of the storability of an element even for the blanking period, such as an active matrix having built therein a non-linear resistance element, e.g., MSI or MIM, an active matrix or a TFT panel having a switching transistor built therein, a smectic liquid crystal panel. FIG. 9 shows an embodiment of an interface circuit according to the invention which can be applied to a thin display capable of conducting the color display by making use the interface signal of the color CRT. Fig. 10 is a timing chart for supplementing the explanation of the operations of the circuit of Fig. 9. In Fig. 9: reference letters Hsyc denote a horizontal synchronizing signal; letters Vsyc a vertical synchronizing signal; letters CK dot clock signals; and letters RD, GD and BD display data in red, green and blue colors, respectively. These signals Hsyc, Vsyc, CK, RD, GD and BD are similar to interface signals to the CRT display. Reference numeral 901 denotes an X-axis display position adjusting circuit for counting the number of the dot clocks CK to adjust the display region (or position) in the X-axis direction. Numeral 907 denotes a Y-axis display position adjusting circuit for counting the number of the horizontal synchronizing signals Hsyc to adjust the display region (or position) in the Y-axis direction. Numerals 904 and 905 denote 1/8 and 1/80 counter circuits for counting effective dot clocks ₂. Numerals 911, 912 and 913 denote S/P converter circuits for converting the serial display data RD, GD and BD in the red, green and blue colors into parallel display data. Numerals 914, 915 and 916 denote latch circuits for temporarily storing the parallel display data outputs of the aforementioned S/P converter circuits 911, 912 and 913. Numerals 917 to 922 denote switching circuits for switching the parallel display data of the aforementioned latch circuits 914 to 916 in a time sharing manner to output parallel display data UD₁ to UD₄ and LD₁ to LD₄ to liquid crystal driver circuits. Numeral 923 denotes a 4-bit shift register circuit for switching the aforementioned switching circuits 917 to 922 in a time sharing manner. Letters SK denote a shift clock signal for shifting the parallel display data UD₁ to UD₄ and LD₁ to LD₄ of the shift register circuit built in the X-axis driver circuit. Letters LK denote a latch signal for latching the parallel display data UD₁ to UD₄ and LD₁ to LD₄ in the latch circuits built in the X-axis driver circuit. Letters FRM denote scanning start data for starting the scan in the Y-axis direction. Letter M denotes an alternating drive signal for driving the color liquid crystal panel by flowing an AC current. Next, the operations of the present invention will be described in the following. When the horizontal synchronizing signal Hsyc is inputted to the X-axis display position adjusting circuit 901, the output X T of this circuit 901 is reset at "L" to rise to "H" after a lapse of a predetermined time, as shown in the timing chart (A) in Fig. 10. This time width LW1 can change the display start position in the X-axis display direction by arbitrarily adjusting the counted value of the dot clocks CK of the built-in variable counter. Moreover, the horizontal synchronizing signal Hsyc sets an R-S flip-flop 906 so that the output T₁ of this flip-flop 906 rises to the value "H". As a result, the output ₁ of an AND circuit 902 generates the dot clocks for the X-axis effective display period at the timing shown in Fig. 10(A). The Y-axis display position adjusting circuit 907 is also made to have a similar construction and has its output Y T reset at the value "L", when it receives the vertical synchronizing signal Vsyc, and caused to rise to the value "H" after a lapse of predetermined time period, as shown in the timing chart (B) in Fig. 10. This time width LW2 can adjust the display start position in the Y-axis direction by arbitrarily adjusting the counted value of the horizontal synchronizing signals Hsyc of the built-in variable counter Moreover, the vertical synchronizing signal Vsyc sets an R-S flip-flop 909 so that the output T₂ of this flip-flop 909 takes the value "H". As a result, an AND circuit 908 outputs the horizontal synchronizing signals Hsyc of the Y-axis effective display period at the timing shown in Fig. 10(B). While the output T₂ of the R-S flip-flop 909 is at the value "H", the AND circuit 903 generates the dot clocks ₂ of the effective display period. These dot clocks ₂ are inputted as the shift clocks of the S/P converter circuits 911, 912 an 913 constructed of 8-bit shift registers. As a result, the serial data of the display data RD, GD and BD for the effective display periods of the red, green and blue colors are converted into parallel data and are outputted to the latch circuits 914, 915 and 916. The aforementioned dot clocks ₂ of the effective display period have their frequency divided by a factor of eight by the 1/8 counter to generate a carry signal ₃. This carry signal ₃ is a latch signal for the aforementioned latch circuits 914, 915 and 916. The carry signal ₃ is also inputted to the 1/80 counter 905 so that it is divided by a factor of eighty to generate a carry signal ₄ thereby to reset the aforementioned R-S flip-flop 906. As a result, the output T₁ of this flip-flop 906 is reset at the value "L" to interrupt the generation of the dot clocks ₁. During the aforementioned effective display period, the outputs of the latch circuits 914, 915 and 916 are inputted to the switching circuits 917 to 922. These switching circuits 917 to 922 are constructed into a 4-bit parallel transmission gate. If the input of this transmission gate falls at the eighth bit of R₁, G₁ and B₁ to R₈, G₈ and B₈ from the 1st bit of the latch circuits 914, 915 and 916, the input signals of the switching circuits 917 to 922 are rearranged in the following table: 1st bit 2nd bit 3rd bit 4th bit Switching Circuit 917 R₁ B₁ G₂ R₃ Switching Circuit 919 B₃ G₄ R₅ B₅ Switching Circuit 921 G₆ R₇ B₇ G₈ Switching Circuit 918 G₁ R₂ B₂ G₃ Switching Circuit 920 R₄ B₄ G₅ R₆ Switching Circuit 922 B₆ G₇ R₈ B₈ As seen from the above table, the switching circuits are grouped into the circuits 917, 919 and 921 and the circuits 918, 920 and 922, and the display data RD, GD and BD are inputted alternately and separately from the 1st bit. The switching signals of the aforementioned switching circuits 917 to 922 are generated by the 4-bit shift register 923. A 1/4 counter 924 is quarters the clock ₁₀, which is prepared by dividing the frequency of the dot clock ₂ into halves by a 1/2 counter 931, to generate a carry signal ₈, as shown in Fig.10(C). This carry signal ₈ is inputted to the shift register 923 to generate outputs Q₁ to Q₄. These outputs Q₁ to Q₄ generate the output "H" in a time sharing manner, but the outputs Q₂ to Q₄ are utilized as the switching signals of the switching circuits 917 to 922. The output Q₁ is reserved as an output data pause period. As a result, the switching circuits 917 to 922 are switched in a time sharing manner, i.e., 917 and 918, 919 and 920, and 921 and 922 to simultaneously output the parallel display data UD₁ to UD₄ and LD₁ to LD₄. The output SK of an AND circuit 927 between the inverted output of the output Q₁ of the shift register 923 and the shift clock ₇ of the shift register 923 outputs the 4-bit parallel data UD₁ to UD₄ and LD₁ to LD₄ as the shift clocks of the (4-bit parallel) shift registers built in the X-axis electrode driver circuit. The timing chart in Fig. 10(D) shows the timing of interface signals to the X-axis and Y-axis electrode driver circuits. The shift clocks SK are inputted to a 1/480 counter 928 so that the carry signal LK having a 1/480 frequency becomes a latch signal for latching the output of the 4-bit parallel shift register built in the aforementioned X-axis electrode driver circuit. An R-S flip-flop circuit 929 is set by the signal Vsyc and reset by the latch signal LK to output the Y-axis electrode scanning start signal FRM having the timing shown in Fig. 10(D). A 1/2 counter 930 generates the signal having one half frequency of the aforementioned signal FRM to invert for each frame the polarity of the drive voltage to be applied to the liquid crystal. Fig. 11 is a circuit diagram showing the system construction of the color liquid crystal display according to one embodiment of the present invention. Reference numeral 1160 denotes the aforementioned interface circuit; numeral 1150 a Y-axis electrode driver circuit; numeral 1140 an X-axis electrode driver circuit having the X-electrode of a color liquid crystal display panel 1144 led out upward; numeral 1149 an X-axis electrode driver circuit having the X-electrode led out downward. The X-axis electrode driver circuits 1140 and 1149 are constructed of 4-bit parallel shift registers 1141 and 1146, latch circuits 1142 and 1147, and liquid crystal driver units 11-3 and 1148. The parallel display data UD₁ to UD₄ and LD₁ to LD₄ are inputted simultaneously to the 4-bit parallel shift registers 1141 and 1146, shifted by the shift clocks SK and latched by the latch clocks LK. The outputs thus latched by the latch circuits 1142 and 1147 conduct the drives in accordance with the display data corresponding to the filter electrodes colored by the liquid crystal drivers 1143 and 1145, respectively. As has been described hereinbefore, according to the embodiment, the color displays of the liquid crystal or the else can be easily conducted in real time by using the interface signal of the CRT display but not the memory circuit such as the RAM. Thus, the present invention can provide an attractive display which can have its display information increased and be made light, thin and small so that it can be used as the flat display terminal. Since the IC of the driver circuit to be used can be similar to that of the monochromatic one of the prior art, another outstanding effect is that any driver circuit especially for the color display need not be developed. Fig. 12 is a circuit diagram showing one embodiment of an interface circuit having a parallel bit selecting function to switch parallel display data into 4-bit or 8-bit data. Fig. 13 is a timing chart for supplementing the description of the operations of Fig. 12. The circuit shown in Fig. 12 has a construction similar to that of Fig. 5 excepting a portion, and the common components conduct similar operations. Reference numerals 1210, 1211 and 1212 denote S/P changing circuits which are individually composed of shift registers for shifting red, green and blue display data and latch circuits for temporarily latching the outputs of the shift registers. Numeral 1221 denotes a set/reset flip-flop circuit for setting in response to the aforementioned first pulse signal P₂. Numerals 1257 and 1258 denote switching circuits for the display data of the upper and lower drivers, respectively, for outputting the display data in 4-bit parallel in a time sharing manner. Numerals 1260 and 1259 denote switching circuits for the display data of the upper and lower drivers, respectively, for outputting the display data in 8-bit parallel in a time sharing manner. Reference letters SW₂ denotes a selecting switch for selecting whether the aforementioned 4-bit or 8-bit parallel output is to be outputted to the driver. The first output P₂ of a 1/8 divider 1206 sets the flip-flop circuit 1221. As a result, an AND circuit 1222 starts the output of a clock signal P₁₀. When the selecting switch SW₂ is OFF, the gate is ON by the switching circuit 1251. As a result, the frequency is divided by a flip-flop circuit 1227 of the 1/2 divider and is inputted as the clock of a quaternary ring counter 1228. This quaternary ring counter 1228 uses the output of a NOR circuit 1229 as its data. The quaternary ring counter 1228 generates switching control signals P₅, P₆ and P₇ in a time sharing manner and switches on the switching circuits 1257, 1259 and 1260 in a time sharing manner to output the display data UD₁ to UD₄, LD₁ to LD₄, UD₅ to UD₈ and LD₅ to LD₈ in parallel. Moreover, the clock signal P₁₀ has its frequency divided into two halves by a flip-flop circuit 1223 so that a shift clock signal SK of the parallel data is outputted. The flip-flop circuit 1223 is reset by the signal, which is reversed data from the quaternary ring counter 1228 by an inverter 1230, to output three clocks of the shift clock signal SK of the parallel data in response to the input of eight clocks of the clock signal P₁₀. The output P₂ of the 1/8 divider 1206 is gated on by a switching circuit 1253 into the latch signals of latch circuits built in the S/P charging circuits 1210, 1211 and 1212 to latch the shifted data every eight shots of the clock signal P₁. The outputs of the aforementioned S/P changing circuits 1210, 1211 and 1212 are inputted alternately bit by bit into the switching circuits 1257 and 1258 so that they may be the mixed color display data of R, G and B (i.e., red, green and blue colors). The switching circuit 1257 outputs the upper display data UD₁ to UD₄ grouped, and the switching circuit 1258 outputs the lower display data LD₁ to LD₄ grouped. The color display data RD, GD and BD are inputted alternately from the individual first bits to the switching circuits 1257 and 1258. As a result, the display data are outputted in a time sharing manner in response to the outputs P₅, P₆ and P₇ of the aforementioned quaternary ring counter 1228 so that the switching circuit 1257 generates the outputs of (R₁, B₁, G₂ and R₃) and (B₃, G₄, ---, and so on) --- and so on. On the other hand, the switching circuit 1258 generates the outputs (G₁, R₂, B₂ and G₃) and (R₄, B₄ ---, and so on) to the display data LD₁ to LD₄ at the same timing as that of the switching circuit 1257. (Note: the numeral indicates what bit the data falls at.) In the system described above, the display data are transferred in the 4-bit parallel to the upper driver and the lower driver. Next, the following description is directed to the case in which the switch SW₂ is ON. In the 8-bit parallel output mode at this time, the switching circuits 1259 and 1260 are selected and activated to output the upper display data UD₁ to UD₈ and the lower display data LD₁ to LD₈ in a time sharing manner. The output P₂ of the 1/8 divider 1206 has its frequency divided into two halves by a flip-flop circuit 1252 and is inputted as a latch signal via the switching circuits 1253 to the S/P changing circuits 1210, 1211 and 1212. As a result, these S/P changing circuits 1210, 1211 and 1212 latch the display data of 16 bits. On the other hand, the output P₁₀ of the AND circuit 1222 has its frequency divided into two halves by the flip-flop circuit 1250 and further similarly divided through the switching circuit 1251 by the flip-flop circuit 1227 to operate the quaternary ring counter 1228 so that the shift clock SK of the display data is outputted from the flip-flop circuit 1223. The switching circuits 1259 and 1260 receive the 16-bit display data of the aforementioned S/P changing circuits 1210, 1211 and 1212 alternately for each one bit. The switching circuit 1260 outputs the upper display data UD₁ to UD₈ grouped, and the switching circuit 1259 outputs the lower display data LD₁ to LD₈ grouped. The color display data RD, GD and BD of the S/P changing circuits 1210, 1211 and 1212 are likewise inputted to the switching circuits 1260 and 1259 alternately from the first bit. As a result, the display data are outputted in a time sharing manner by the outputs P₅, P₆ and P₇ of the aforementioned quaternary ring counter 1228 so that the switching circuit 1260 generates outputs (R₁, B₁, G₂, R₃, B₃, G₄, R₅ and B₅), (G₆, R₇, B₇, G₈, ---, and so on), ---, and so on. On the other hand, the switching circuit 1259 generates the outputs (G₁, R₂, B₂, B₃, R₄, B₄, G₅ and R₆), (B₆, G₇, R₈, ---, and so on), ---, and so on to the display data at the same timing as that of the circuit 1260. (Note: the numeral indicates what bit the data falls at.) As has been described above, the 8-bit parallel mode can be selected by turning on the switch SW₂, and the 4-bit parallel mode can be selected by turning off the switch SW₂. The display data is inverted to effect an NEGA display by turning on a switch SW₁, and the Posi display can be effected by turning off the switch SW₁ In the timing chart of Fig. 13, (A) shows the timing of the outputs T₁ and T₂ of the horizontal and vertical home position regulating circuits. (B) shows the timing of clock signals P₁ and P₃; (C) the timing of the timing signals to the drivers of the liquid crystal display such as the switching signals P₅, P₆ and P₇ and the display data UD₀ to UD₃ and LD₀ to LD₃; and (D) the timing of the shift clock CP, the latch clock LK, the frame signal FRM and the control drive signal M. As has been described hereinbefore, according to the present embodiment, the parallel display data bits can be easily selected to the 4-bit or 8-bit so that the 4-bit or 8-bit parallel driver can be selected within the allowable range of the transfer speed to enhance the applicability remarkably. As a result, the 4-bit driver cannot be used in the prior art, but two of them can be used if they are in parallel to have an 8-bit construction. Since the driver having the same construction as that of the prior art can be used as it is, there is no necessity for developing a driver especially for color display. Although the present invention has been described only to the change from the 4-bit to 8-bit, it can be applied to another change from the 8-bit to 16-bit but should not be limited thereto. The present invention can naturally be applied to elements other than the liquid crystal ones. Fig. 14 is a circuit diagram showing one embodiment of the interface circuit which can handle the various color dot arrangements (e.g., stripe, mosaic, inverse mosaic or triangle arrangements) of a color panel. The circuit shown in FIG. 14 has a construction similar to that of FIG. 5 excepting a portion, and the common components have similar operations. Reference numeral 1450 denotes a color arrangement selecting circuit for causing the arrangements of the red, green and blue color dots to correspond to those of the color dots of the stripe (of Fig. 15(A)), the mosaic (Fig. 15(B)) and the inverse mosaic (Fig. 15(C)). In Fig. 15 showing the arrangement types of the color dots: (A) shows the stripe type (e.g., the parallel array of R, G and B); (B) shows the mosaic type (e.g., downward to the right of R , G and B); (C) shows the inverse mosaic type (e.g., downward to the left of R, G and B). Fig. 16 shows one embodiment of the color arrangement selecting circuit according to the present invention. Reference numerals 1664, 1665 and 1666 denote switching circuits which are switched in the order of connection to output the display data RD, GD and BD to display data output terminals D₁, D₂ and D₃. Numerals 1651, 1652 and 1653 denote D-type flip-flops (i.e., D-type F/F circuits) and a NOR circuit for generating a ternary ring counter. Numerals 1655 to 1658 denote transmission gate circuits for changing the outputs of the D-type flip-flop circuits of the aforementioned ternary ring counter by a selecting terminal S₄. A selecting terminal S₃ is used in case the arrangement is fixed at the stripe type. The selecting terminal S₄ is used to select the mosaic type or the inverse mosaic type. Next, the operations of Fig. 16 will be described in the following. In the case of the stripe type, i.e., in the case of the electrode construction of the color liquid crystal panel shown in Fig. 7 or 15(A), the selecting terminal S₃ is set at a voltage level "H". As a result, the D-type flip-flop circuits 1651 and 1652 of the ternary ring counter are reset. As a result, both the switching circuits 1665 and 1666 are turned off. The output of a NOR circuit 1654 takes an "L" level so that the switching circuit 1664 is turned on to output the display data RD, GD and BD to the D₁, D₂ and D₃. Next, the dot color arrangement of the mosaic type of Fig. 15(B) will be described in the following. The selecting terminal S₃ is set at the "L" level, and the selecting terminal S₄ is set at the "H" level. As a result, the ternary ring counter is reset by the vertical synchronising signal Vsyc and then performs its ternary ring counting operation when it receives the horizontal synchronizing signal Hsyc as its clock input. Then, the transmission gates 1655 and 1657 are turned on. As a result, the switching circuits 1664, 1665 and 1666 are turned on consecutively and cyclically each time they receive the horizontal synchronizing signal Hsyc, so that the output terminals D₁, D₂ and D₃ have their order changed, as follows, for each one line display to output the display data: BD, GD and BD - - - 1st Line; BD, RD and GD - - - 2nd Line; and GD, BD and RD - - - 3rd Line. Next, let the case of the inverse mosaic type shown in Fig. 15(C) be considered in the following. Both the selecting terminals S₃ and S₄ are set at the "L" level. Then, the transmission gates 1656 and 1658 are turned on. As a result, the output terminals D₁, D₂ and D₃ output the display data for each line display, as follows: RD, GD and BD - - - 1st Line; GD, BD and RD - - - 2nd Line; and BD, RD and GD - - - 3rd Line. These display data are inputted for S/P changing as the input data of the individual shift registers and are changed into parallel data, as has been described above. These parallel data are then switched in a time sharing manner by the grouped switching circuits and are driven by the X-axis drivers. As has been described hereinbefore, according to the present embodiment, an optimum system can be selected at any time by the selecting terminals even for the panel having the various color dot arrays such as the stripe type, the mosaic type and the inverse mosaic type of the color display panel so that the present embodiment can be applied to side purposes. Fig. 17 is a circuit diagram showing another embodiment of the interface for a color flat type display. In Fig. 17, a horizontal home position regulating circuit 1701 is made receptive of the horizontal synchronizing signal Hsyc and has a predetermined delay time for taking timing with the color display data. A vertical home position regulating circuit 1702 is made receptive of the vertical synchronizing signal Vsyc and has a predetermined delay time from the timing of the signal Vsyc to take timing with the display data. A variable counter 1703 counts the number of the clock signals CK and accordingly the number of the horizontal dot clocks. A flip-flop circuit 1704 divides the frequency of the output clock signal CK of an AND circuit 1717. Switching circuits 1732 and 1733 are switching circuits for selecting the color video signals DR, DG and DB in a time sharing manner to transfer data to a latch circuit 1734 or 1735. A latch circuit 1736 further latches the video data, which are latched in a time sharing manner, to output them in parallel. Next, the operations will be described in the following. When the horizontal synchronizing signal Hsyc is inputted to a monostable multivibrator 1709 of the horizontal home position regulating circuit 1701, the output of the monostable multivibrator 1709 falls to the "O" level with a delay time which is determined by the time constant of a capacitor 1714 and a variable resistor 1715. Since a flip-flop circuit 1710 is set by the signal Hsyc, the output of a NOR circuit 1712 rises to the "1" level. The vertical home position regulating circuit 1702 also has a similar construction and outputs the "1" level to the AND circuit 1717 with a delay time after the vertical synchronizing signal Vsyc. As a result, after the outputs of the horizontal home position regulating circuit 1701 and the vertical home position regulating circuit 1702 coincide to the "1" level, the AND circuit 1717 outputs the clock signals CK. The number of these clock signals CK is counted by the variable counter 1703. In case the counted value of the variable counter 1703 is set at 640, a carry signal CL₁ is generated in response to the 640th clock signal CK. Since the carry signal CL₁ sets the output of the flip-flop circuit 1710 at the "1" level, the AND circuit 1717 interrupts the output of the clock signals CK. On the other hand, the red, green and blue video signals DR, DG and DB are inputted to D-type flip-flop circuits 1729, 1730 and 1731 and are outputted with a delay of the half period of the aforementioned dot clock signals CK. The outputs of the flip-flop circuits 1729, 1730 and 1731 are inputted to the switching circuits 1732 and 1733 and are selectively switched until they are latched by the latch circuit 1734 or 1735. The control signals of these switching circuits 1732 and 1733 are switched alternately in response to each input of the clock signals by the output of the flip-flop circuit 1704 which is made receptive of the clock signals CK of the AND circuit 1717. The latch signals of the aforementioned latch circuits 1734 and 1735 are generated by AND circuits 1726 and 1725. The output CL₂ of the AND circuit 1725 is delayed by the delay circuit 1727 and is inputted as the latch pulse of the latch circuit 1736. The latch circuit 1736 latches the video signals of the aforementioned latch circuits 1734 and 1735 simultaneously to output the video signals R₁, G₁, B₁, R₂, G₂ and B₂ simultaneously to the driver of the color liquid crystal display. Moreover, the output CL₂ of the AND circuit 1725 is delayed by a delay circuit 1728 constructed of the D-type flip-flop and is outputted as a shift clock signal SC for the video signals R₁ to B₂ of the liquid crystal display driver. The carry signal CL₁ of the aforementioned variable counter 1703 is delayed by a delay circuit 1706 constructed of the D-type flip-flop circuit to generate the output LD as the data latch signal for one line to the liquid crystal driver. When the vertical synchronising signal Vsyc is inputted, this signal acting as the data for starting the drive of the first scanning line is inputted to a NOR circuit 1722 so that the output of a NOR circuit 1721 is set at "1". And, the latch signal LD of the aforementioned liquid crystal driver is delayed a half period of the clock signal CK by a delay circuit 1707 constructed of the D-type flip-flop circuit and is inputted to the NOR circuit 1721 so that it resets the output of the NOR circuit 1721 at "0". The output signal FRM of this NOR circuit 1721 is outputted as the data (i.e, the frame signal) for starting the scanning at the common side of the liquid crystal driver to the liquid crystal driver. Moreover, the output FRM of the aforementioned NOR circuit 1721 has its frequency divided by a flip-flop circuit 1711 to invert the polarity of the liquid crystal drive voltage for each frame thereby to output the drive control signal M for the control drive. According to the present invention, it is possible to construct a novel color interface circuit which can have its circuitry simplified at a low cost by the use of the interface signal of a CRT display and which is compatible with the CRT display. Figs. 18 to 20 show another example in which the difficulty in connection is to be eliminated by separating an X-axis driver into two systems for upper and lower electrodes. A D-type flip-flop (which will be shortly referred to as a "D-type FF") 1806 and a NOR circuit 1812 are circuits for generating a data hold signal HP for holding the data to a segment driver. A D-type FF circuit 1801, a NOR circuit 1813 and an FF circuit 1814 are circuits for generating the frame signal FRM. An FF circuit 1815 is a circuit for generating a drive signal polarity inversion control signal DF for alternately driving a liquid crystal. An FF circuit 1807 is a circuit for dividing the frequency of an effective horizontal dot signal ₂. A D-type FF circuits 1808 and a NOR circuit 1810 are circuits for generating a shift clock USK for transferring data UST to the shift register of the upper segment driver. A D-type FF circuit 1809 and a NOR circuit 1811 are circuits for generating a shift clock LSK for transferring data LST to the shift register of the lower segment driver. A D-type FF circuit 1923 and a NOR circuit 1824 are circuits for generating a set signal ₅ to the set/reset circuits of FF circuits 1825 and 1826. Delay circuits 1927 and 1828 are circuits for delaying the aforementioned data shift clocks USK and LSK to generate a reset signal to the FF circuits 1925 and 1826. Transmission gates 1816 and 1819, 1817 and 1820, and 1818 and 1821 are switching circuits for sharing the red, green and blue video signals between the red, green and blue UR, UG and UB of the upper segment driver and the red, green and blue LR, LG and LB of the lower segment driver. The present embodiment has the components recited above. Next, the operations of Fig. 18 will be described in the following. Fig. 19 is a timing chart of Fig. 18. In Fig. 18, a vertical home position regulating circuit 1802 is a circuit for setting the effective display period in the Y-axis direction and has built therein a counter circuit for counting the vertical flyback period after it receives the vertical synchronising signal Vsyc and a counter circuit for counting the number of the horizontal synchronizing signals for the effective display region period. The horizontal synchronizing signal Hsyc is inputted as the clock input to the vertical home position regulating circuit 1802. The output T₁ of this vertical home position regulating circuit 1802 is an output signal at the "H" level for the period of the effective display region in the Y-axis direction, as shown in Fig. 19. As a result, the output ₁ of an AND circuit 1803 inputs the horizontal synchronizing signal Hsyc for the period of the effective display period in the Y-axis direction to a horizontal home position regulating circuit 1804. This horizontal home position regulating circuit 1804 has the same construction as that of the vertical home position regulating circuit 1802 and has built therein a counter circuit for counting the horizontal flyback period after it receives the horizontal synchronizing signal Hsyc and a counter circuit for counting the number of the dot clocks CK. These dot clocks CK are inputted as the clock input. The output T₂ of the horizontal home position regulating circuit 1804 is an output signal at the "H" level for the period of the effective display region in the X-axis direction, as shown in Fig. 19. As a result, an AND circuit 1805 outputs the dot clock signal ₂ in the effective display region. The red, green and blue video signals RD, GD and BD are shared selectively between upper video signals UR, UG and UB and lower video signal data LR, LG and LB by switch circuits, which are constructed of transmission gates 1816 and 1819, 1817 and 1820, and 1818 and 1821, and are outputted to the upper and lower segment drivers. The selected controls of the aforementioned transmission gates 1816 to 1821 are shared by an output signal ₆ which has its frequency divided into one half by the dot clock signal ₂. The D-type FF circuit 1808 and the NOR circuit 1810 generate a shift clock USR, which is to be used as the shift clock of the shift register built in the upper segment driver, in response to the fall of the Q output of the FF circuit 1807. In response to the fall of the Q output of the D-type FF circuit 1807, a shift clock LSK is generated to provide a shift clock for the shift register built in the lower segment driver. A D-type FF circuit 1823 and a NOR circuit 1824 generate a set pulse ₅ for setting the shift data in response to the fall of ₁ to set FF circuits 1825 and 1826 at the "H" level. Since these FF circuits 1825 and 1826 are reset by the first shots of the shift clock USK of the upper segment driver and the shift clock LSK of the lower segment driver, the outputs LSK and LST of the aforementioned FF circuits 1825 and 1826 provide the data of the shift registers of the upper and lower segment drivers. The D-type FF circuit 1801 and the NOR circuit 1813 generate a set pulse signal ₃ at the fall of the output T₁ of the aforementioned horizontal home position regulating circuit 1802 to set the FF circuit 1814. The D-type FF circuit 1806 and the NOR circuit 1812 generate the data hold pulse HP at the fall of the aforementioned horizontal home position regulating circuit T₂ to hold the data of the upper and lower segment drivers. Moreover, the data is also delayed by a delay circuit 1830 and is applied as the reset signal of the FF circuit 1814 to reset the FF circuit 1814. Therefore, the output FRM of the FF circuit 1814 provides the scan starting data for the shift registers of the common driver as the frame signal for starting the scanning. The FF circuit 1815 divides the frequency of the aforementioned FRM signal to input the polarity inversion signal DF for inverting the polarity of the drive voltage to the upper and lower segment drivers and the common driver for each frame thereby to switch the polarity. Fig. 20 shows the whole construction of a color graphic liquid crystal display using the interface of the present embodiment. In Fig. 20: reference 2042 denotes an upper segment driver; numeral 2043 a lower segment driver; numeral 2041 a common driver; and numeral 2060 a color liquid crystal display panel. The upper and lower segment drivers 1042 and 2043 are constructed of shift registers 2044 and 2052, switching circuits 2045, 2046, 2050 and 2051, waveform polarity converting circuits 2048 and 2053, and data hold circuits 2047 and 2049. The horizontal electrodes R₁, G₁ and B₁ to R₄, G₄ and B₄ of the color liquid crystal panel 2060 are connected with the upper and lower segment drivers and are driven vertically. The shift data UST and LST of the shift registers 2044 and 2052 are shifted by the shift clocks USK and LSK. The outputs Q₁ to Q₄ of the shift registers 2044 and 2052 are controlled sequentially by the switching circuits 2045 and 2050 to sample and hold the data. After this, in response to the data hold signal HP, the data hold circuit 2047 holds the analog voltage of one horizontal scanning line to drive the S electrodes R₁, G₁ and B₁ to R₄, G₄ and B₄. The common driver 2041 is fed with the frame signal FRM as the frame starting data to conduct the linear sequential scannings in response to the aforementioned hold panel signal HP. The waveform polarity converting circuits 2048 and 2053 controls to convert the polarity of the analog voltage in accordance with the polarity of the polarity converting signal DF to effect the control drive. According to the present embodiment, the color video signals are shared and transferred to the upper and lower sides so that the pitch interval between the color panel X-axis electrodes and the driver can be enlarged to facilitate the connection therebetween. Moreover, the transfer clock frequency of the data can be reduced to one half so that the IC price can be dropped. Still moreover, the driver is laid out at the upper and lower sides so that the pattern design and mounting of the periphery of the driver can be facilitated. Fig. 21 is a block diagram showing a further embodiment of the interface for the color liquid crystal display. In Fig. 21, shift registers 2112, 2113 and 2114 are circuits for shifting the output signals of latch circuits 2109, 2110 and 2111 for each one bit in response to shift clock signals ₄, ₅ and ₆. AND circuits 2115, 2116 and 2117 are selecting gate circuits for selectively extracting the output signals of the aforementioned shift registers 2112, 2113 and 2114. A shift register 2119 is a circuit for-shifting the output signals of the aforementioned selecting gate circuits. A latch circuit 2120 is a circuit for temporarily storing the output of the aforementioned shift register 2119 to output the mixed color display data in parallel. A frame signal generator 2123 is a circuit for generating a frame signal. A shift clock generator 2124 is a circuit for generating shift clocks for sequentially transferring the mixed color display data inputted to an X-axis driver 2127. A latch clock generator 2125 is a circuit for generating a latch signal for latching the data inputted to the X-axis driver 2127 and a Y-axis driver 2129. A control signal generator 2126 is a circuit for switching the polarity of the drive signals of the X-axis driver 2127 and the Y-axis driver 2129 so as to drive a color liquid crystal panel 2128 in a controlled manner. The color liquid crystal panel 2128 is a panel having red, green and blue filters attached to its transparent electrodes. The X-axis driver 2127 and the Y-axis driver 2129 are circuits for driving the X-electrodes and Y-electrodes of the color liquid crystal panel 2128, respectively. A frequency multiplier 2130 is a circuit which uses a PSL circuit for oscillating at a frequency three times as high as that of the clock signal ₂. Next, the operation of the present embodiment will be described in the following. The latch signal ₁ is a carry signal which is prepared by dividing the aforementioned clock signal ₂ by the 1/8 divider 2105. The output signals of the latch circuits 2109, 2110 and 2111 are the signals ₃ which are inverted from the latch signal ₁ by the inverter 2121, and are transferred in parallel to the shift registers 2112, 2113 and 2114. The individual color display data transferred to the aforementioned shift registers 2112, 2113 and 2114 are shifted for each one bit in response to the shift clocks ₄, ₅ and ₆ and are inputted to the AND circuits 2115, 2116 and 2117, respectively. A ring counter 2122 is made receptive of the output of the frequency multiplier 2130, which uses the PLL circuit oscillating with a frequency three times as high as that of the aforementioned clock signal ₂, to output the clock signals ₄, ₅ and ₆ in time series to provide the shift clock signals for the aforementioned shift registers 2112, 2113 and 2114. As a result, the OR circuit 2118 outputs the color display data of the red, green, blue, red, - - -, and so on sequentially and selectively from the shift registers 2112, 2113 and 2114. The output signal of the aforementioned OR circuit 2118 is inputted to the shift register 2119 and is shifted and stored for each one clock signal because the clock signal ₂ is used as the shift clock signal. The latch circuit 2120 latches the output signal of the aforementioned shift register 2119 in parallel in response to the aforementioned latch signal ₁ to output the mixed color display data to the X-axis driver 2127. The shift clock generator 2124 generates the shift clock signal by the counter, which is operative to divide the frequency of the clock signal ₆ into 1/8, because the color display data of the aforementioned latch circuit 2120 is shifted to the 8-bit mixed color display data parallel to the shift register of the X-axis driver 2127. The latch clock generator 125 is constructed of a counter for dividing the frequency of the carry signal of the aforementioned shift clock generator 124 into 1/80 and outputs the latch signal to the latch circuit built in the X-axis driver 2127 when the mixed color display data shifted to the shift register of the X-axis driver 2127 takes 640 x 3 dots. On the other hand, the frame signal generator 2123 feeds the frame signal to the shift register of the Y-axis driver 2129 when it receives the vertical synchronizing signal Vsyc. That frame signal generator 2123 is constructed of a one-shot multivibrator, and its frame signal is a data signal for the Y-axis driver 2129. Moreover, the latch signal of the aforementioned latch clock generator 2125 is inputted as the shift clock signal of the data to the Y-axis driver 2127 to shift the data. The X-axis driver 2127 and the Y-axis driver 2129 have built therein the drivers for driving the X- and Y-electrodes of the color liquid crystal panel 2128 so that they generate selection signals, when the data are at "1", and non-selection signals, when the data are at "0", for their driving operations. Fig. 23 is a circuit diagram showing a further embodiment of the interface which can be admitted even at a low transfer speed by transferring data on a 8-bit parallel signal, and Fig. 24 is a timing chart for supplementarily explaining the operations of the circuit of Fig. 23. In Fig. 23: reference numeral 2310 denotes a variable counter for setting the counted value of the output ₅ of an AND circuit 2308 at 200 or 400; numerals 2317 and 2318 buffers for classifying the 8-bit output data of a latch circuit 2314 into odd and even bits to amplify the display data UD₁ to UD₄ and LD₁ to LD₄ in the upper and lower extraction electrode drivers of the X-electrodes of the liquid crystal display; and letters shift clock signals for shifting the parallel display data UD₁ to UD₄ and LD₁ to LD₄ to the 4-bit parallel shift register circuits built in the X-axis driver. Letters LK denote a latch signal for latching the parallel display data UD₁ to UD₄ and LD₁ to LD₄ in the latch circuit built in the X-axis driver. Letters FRM denote scanning starting data for starting the scanning of the Y-axis FIG. 22 shows an embodiment of an interface for monochromatic display. In FIG. 22, a 4-bit shift register 2205 is a circuit for converting a video signal VD coming in series into a parallel signal. A quartering counter 2204 is a circuit for generating a latch circuit for latching the display data of said 4-bit shift register 2205. A video signal VD is inputted to the 4-bit shift register 2205 for shiftclocking the output of the AND circuit 2217. As a result, the data is shifted and fetched each time a clock signal is inputted. On the other hand, the quartering counter 2204 is a frequency divider circuit made receptive of the clock signals of the AND circuit 2217 for generating a carry signal CL₂ in response to the fourth clock signal. This carry signal CL₂ latches the data of the aforementioned 4-bit shift register 2205. The 4-bit video data D₀ to D₃ thus latched are outputted from the 4-bit shift register 2205. The carry signal CL₂ of the aforementioned quartering counter 2204 is delayed by a D-type flip-flop circuit 2208 and is outputted as a shift clock signal SC for a data shift register of a liquid crystal driver circuit. The circuit shown in FIG. 22 has a construction similar to that of FIG. 17 except a portion. Fig. 23 is a circuit diagram showing a further embodiment of the interface which can be admitted even at a low transfer speed by transferring data on a 8-bit parallel signal, and Fig. 24 is a timing chart for supplementarily explaining the operations of the circuit of Fig. 23. In Fig. 23: reference numeral 2310 denotes a variable counter for setting the counted value of the output ₅ of an AND circuit 2308 at 200 or 400; numerals 2317 and 2318 buffers for classifying the 8-bit output data of a latch circuit 2314 into odd and even bits to amplify the display data UD₁ to UD₄ and LD₁ to LD₄ in the upper and lower extraction electrode drivers of the X-electrodes of the liquid crystal display; and letters shift clock signals for shifting the parallel display data UD₁ to UD₄ and LD₁ to LD₄ to the 4-bit parallel shift register circuits built in the X-axis driver. Letters LK denote a latch signal for latching the parallel display data UD₁ to UD₄ and LD₁ to LD₄ in the latch circuit built in the X-axis driver. Letters FRM denote scanning staring data for starting the scanning of the Y-axis electrodes of the liquid crystal display panel. Letter M denotes a control drive signal for driving the liquid crystal panel in a controlled manner. Next, the operations of the embodiment of the present invention will be described in the following. The horizontal synchronizing signal Hsyc sets an R-S flip-flop 2306 so that the output T₁ of this flip-flop takes the "H" level. As a result, the output ₁ of an AND circuit 2302 generates dot clocks for an X-axis effective display period at the timing shown in Fig. 24(A). A vertical home position regulating circuit 2307 also has a similar construction and has its output Y T reset at "L", as shown in Fig. 24(B), when the vertical synchronizing signal Vsyc is inputted, to rise to the "H" level after lapse of a predetermined time period. This period Lw₂ is enabled to regulate the display starting position in the Y-axis direction by arbitrarily regulating the value of the built-in variable counter. Moreover, the vertical synchronizing signal Vsyc sets an R-S flip-flop 2309 so that the output T₂ of this flip-flop 2309 takes the "H" level. As a result, the AND circuit 2308 generates the output ₅ of the Y-axis effective display period at the timing shown in Fig. 24(B). The variable counter 2310 outputs the carry signal ₆ at the counted value 200, when a switch 2334 is ON, and at the counted value 400 when the switch is OFF. While the output T₂ of the R-S flip-flop 2309 is at the "H" level, an AND circuit 2303 generates the dot clock ₂ of the effective display period. This dot clock ₂ is inputted as the shift clock of an S/P changing circuit 2311 constructed of an 8-bit shift register. As a result, the serial data of the display data D are changed to parallel data, which are outputted to the latch circuit 2314. The dot clock of the aforementioned effective display period has its frequency divided into 1/8 by the 1/8 counter to generate the carry signal ₃. This carry signal ₃ becomes the latch signal of the aforementioned latch circuit 2314. The carry signal ₃ is further inputted to a 1/80 counter 2305 to have its frequency divided into 1/80 so that the carry signal ₄ is generated to reset the aforementioned R-S flip-flop 2306. As a result, the output T₁ is reset at the "L" level to interrupt the generation of the dot clock ₁. For the aforementioned effective display period, the output of the latch circuit 2314 is fed to the X-axis driver from the buffers 2317 and 2318. The odd bit output of the latch circuit 2314 is inputted to the buffer 2317 to output the display data UD₁ to UD₄, whereas the even bit output is inputted to the buffer 2318 to output the display data LD₁ to LD₄. The timing chart (D) of Fig. 24 shows the timing of the interface signals to the X-axis and Y-axis drivers. The shift clock SK is inputted to a 1/80 counter 2328 so that the carry singal LK having its frequency divided into 1/80 becomes a latch signal for latching the output of the 4-bit parallel shift register built in the aforementioned X-axis driver. An R-S flip-flop 2329 is a circuit to be set by the signal Vsyc and reset by the latch signal LK to output the signal FRM for starting the scanning of the Y-axis electrodes at timing shown in Fig. 24(D). A 1/2 divider 2330 generates the signal M, which is prepared by dividing the frequency of the aforementioned FRM signal into 1/2, to invert for each frame the polarity of the drive voltage to be impressed upon the liquid crystal. Fig. 25 is a block diagram showing the system construction of the liquid crystal display according to a further embodiment of the present invention. X-axis drivers 2540 and 2545 are constructed of 4-bit parallel shift registers 2541 and 2546, latch circuits 2542 and 2547, and liquid crystal drivers 2543 and 2548. The parallel display data UD₁ to UD₄ and LD₁ to LD₄ are inputted simultaneously to the 4-bit parallel shift registers 2541 and 2546, shifted in response to the shift clocks SK and latched by the latch circuits 2542 and 2547 in response to the latch clocks LK. The outputs thus latched by the latch circuits 2542 and 2547 effect the drives in accordance with the display data corresponding to the filter electrodes colored by the liquid crystal drivers 2548 and 2545, respectively. Fig. 26 is a diagram showing the electrode construction of the liquid crystal panel using the present embodiment. In Fig. 26, the odd number X-axis electrodes X₁, X₃, X₅, - - -, and so on are used as the upper lead electrodes, and the even number electrodes X₂, X₄, - - -, and so on are used as the lower lead electrodes, and these upper and lower lead electrodes are driven by different X-axis drivers. As has been described above, according to the present embodiment, the display data can be transferred in 8-bit parallel to the upper and lower electrodes so that the speed of the transfer shift clock signal can be retarded two times. Since, moreover, the pitch interval of the X-axis electrodes of the liquid crystal panel can be enlarged two times, the connection between the liquid crystal panel and the X-axis drive output can be facilitated. Fig. 27 is a circuit diagram showing one embodiment of the present invention. In Fig. 27, reference numeral 2701 denotes an X-axis display position adjusting circuit, and numeral 2702 denotes a Y-axis display position adjusting circuit. The X-axis display position adjusting circuit 2701 is constructed of external setting means 2721 such as a digital switch, a counter circuit 2722 for counting the number of clock signals CK, a group of exclusive OR circuits constructing together a coincidence detecting circuit; a group of NOR circuits 2724, a group of NAND circuits 2725, and a NOR circuit 2729. The Y-axis display position adjusting circuit 2702 is constructed, like the aforementioned X-axis display position adjusting circuit, of a counter circuit for counting the number of reference signals, external input means, and a coincidence detecting circuit for detecting a coincidence. Next, the operations of Fig. 27 of the present invention will be described in the following. When a horizontal synchronizing signal Hsyc is inputted to the X-axis display position adjusting circuit 2701, a flip-flop circuit (or an F/F circuit) 2720 has its output set at an "H" level so that a clock signal CK is outputted from an AND circuit 2750 and inputted to the counter circuit 2722. The output of the counter circuit 2722 and the output of the external setting means 2721 are inputted to the grouped exclusive OR circuits 2723, the outputs of which are outputted through the grouped NOR circuits 2724 and the grouped NAND circuits 2725 to the NOR circuit 2729. As a result, the set value of the aforementioned external setting means 2721 such as the digital switch and the counted value of the aforementioned counter circuit 2722 coincide with each other, the output R₁ of the NOR circuit 2729 rises to the "H" level to reset the aforementioned flip-flop circuit 2720. As a result, the output Q of the flip-flop circuit 2720 is dropped to an "L" level. Since a flip-flop circuit 2730 is reset, the output of a NOR circuit 2731 takes the "H" level. Then, this "H" signal is inputted to the data input of a D-type flip-flop circuit 2732 to output a signal T₁ from the output terminal Q to an AND circuit 2703. On the other hand, the Y-axis display position adjusting circuit 2702 has a construction similar to that of the X-axis display adjusting circuit 2701 to count the number of the horizontal synchronizing signals Hsyc in response to the input of a vertical synchronizing signal Vsyc. When the counted value coincides with the set value of the external input means, the counter circuit is reset in response to the coincidence detection signal to generate an output T₂ thereby to input the "H" signal to the AND circuit 2703. Just at this time, the display start (or the home position) is taken to output the shift clock SP and a clock signal P₂. This clock signal P₂ has its frequency divided into one eighth by a 1/8 frequency divider circuit 2734 to generate latch pulses LP by a D-type flip-flop circuit 2739 and a NOR circuit 2740 so that the output of a shift register 3205 (which should be referred to in Fig.32) is latched in a latch circuit 3209 (which should also be referred to in Fig.32) to execute the serial/parallel conversions of the display data. The output of the 1/8 frequency divider circuit 2734 is further inputted to a frequency divider circuit 2735 to count the number (e.g., 672) of effective display dots in the X-axis direction. In response to the output of the frequency divider circuit 2735, reset pulses P₁ are generated by a D-type flip-flop circuit 2736 and a NOR circuit 2737 to reset the flip-flop circuit 2730, the 1/8 frequency divider cirucit 2734 and the frequency divider circuit 2735. On the other hand, the shift clock SP is inputted as a shift clock to the aforementioned shift register (which should also be referred to in Fig.32). Moreover, the shift clock SP has its frequency divided into one sixteenth by a 1/16 frequency divider circuit 2742 to generate a set signal for a flip-flop circuit 2745 by a D-type flip-flop circuit 2741 and a NOR circuit 2743. When the flip-flop circuit 2745 is set, an AND circuit 2746 generates the clock signal P₅ to input it to a 1/4 frequency divider circuit 2747. The output CP of this 1/4 frequency divider circuit 2747 is turned as the shift clock signals of display data D₀ to D₃ (which should also be referred to in Fig.32) into the shift clock of a 4-bit parallel shift register built in a liquid crystal driver circuit IC. The output of the 1/4 frequency divider circuit 2747 further has its frequency divided by a flip-flop circuit 2748 to generate switching signals GP₁ and GP₂ so that the 8-bit output of the aforementioned latch circuit 3209 (which should also be referred to in Fig.32) is switched for each 4 bits in parallel to output the 4-bit parallel display data D₀ to D₃. Fig. 33 is a timing chart showing the timings of the individual parts of the circuit according to the embodiment of the present invention shown in Fig.27. In Fig.33, the output Q₁ is set at the "H" level in response to the horizontal synchronizing signal Hsyc by the flip-flop circuit 2720 (which should be referred to in Fig.27) and is reset by the output R₁ of the NOR circuit 2729 of the coincidence detecting circuit so that the output Q of the D-type flip-flop circuit 2732 then generates the signal T₁. As a result, the clock signal P₂ can have its frequency divided by the frequency divider circuit 2735 to set and reset the flip-flip circuit 2730 and the frequency divider circuit 2735 in response to the reset signal P₁. As will also be understood, moreover, after the latch signal LP has been generated, the shift clock CP of the 4-bit parallel data and the switching signals GP₁ and GP₂ of the 4-bit parallel data D₀ to D₃ are generated. Fig.32 is a diagram showing the overall construction of the interface of the present embodiment. In Fig.32: the letters Hsyc denote the horizontal synchronizing signals; the letters Vsyc the vertical synchronizing signals; the letters CK the dot clock signals; and the letter D the display data. These signals Hsyc, Vsyc, CK and D are similar to the interface signals of the CRT display. Reference numeral 3201 denotes an X-axis display position adjusting circuit for counting the number of the dot clock signals CK to adjusting the display start (or the home position) in the X-axis direction. Numeral 3202 denotes a Y-axis display position adjusting circuit for counting the number of the horizontal synchronizing signals Hsyc to adjust the display start (or the home position) in the Y-axis direction. Numeral 3203 denotes an AND circuit for generating the dot clocks CK when the outputs of the X-axis and Y-axis display position adjusting circuits coincide with each other. Numeral 3204 denotes means constructed of a frequency divider circuit or the like for counting the number of horizontal dots to reset the aforementioned X-axis display position adjusting circuit. Numeral 3205 denotes a shift register for shifting the serial data D. Numeral 3209 denotes a latch circuit for latching the output of the shift register 3205. Numeral 3206 denotes a frequency divider circuit for dividing the frequency of the shift clock SP to generate in the latch circuit 3209 the latch signal, the GP₁ and GP₂ for switching circuits 3207 and 3208, and the data shift clock CP. Numeral 3210 denotes a timing signal generator circuit for generating the interface signal for a liquid crystal driver circuit such as a LOAD for latching the AC drive signal M, the frame starting signal FRM and the display data transferred to the driver. The numerals 3207 and 3208 denote switching circuits for alternately turning on and off every 4 bits of the 8th bits of the latch output of the latch circuit 3209 to output the display data in 4 bits. Next, the operations of Fig.32 will be described in the following. When the horizontal synchronizing signal Hsyc is inputted to the X-axis display position adjusting circuit 3201, the number of the clock signals CK is counted by the counter circuit built therein. When the counted number coincides with the set count value, moreover, the X-axis display position adjusting circuit 3201 outputs the signal T₁. When the vertical synchronizing signal Vsyc is likewise inputted to the Y-axis display position adjusting circuit, the number of the horizontal synchronizing signals Hsyc is counted by the counter circuit built therein. When the counted number coincides with the set count value, moreover, the Y-axis display position adjusting circuit 3202 outputs the signal T₂. Since the AND circuit 3203 has received the aforementioned signals T₁ and T₂ and clocks CK, it generates the clock signal P₂ and the shift clock signal SP when both the signals T₁ and T₂ take the "H" level. The first clock signal when both the two signals T₁ and T₂ rise to the "H" level provides the display start (or the home position). When the clock signal P₂ is inputted to the frequency divider circuit 3204 so that the data of one line in the X-axis display direction are transferred, the reset signal P₁ is generated to reset the X-axis display position adjusting circuit 3201 to interrupt the input of the clock signal P₂. On the other hand, the aforementioned shift clock signal SP is inputted as the shift clock of the shift register 3205 to shift the display data D. Moreover, the shift clock signal SP is inputted to the frequency divider circuit 3206 to generate the 1/8 frequency dividing signal so that the output of the aforementioned shift register 3205 is latched in the latch circuit 3209. The 8th bit data of the latch circuit 3209 are inputted at the unit of 4 bits to the switching circuit 3207 and the switching circuit 3208 to generate the parallel display data D₀ to D₃ of 4 bits which were switched by the switching signals GP₁ and GP₂ (i.e., the inverted signal of the signal GP₁) of the aforementioned frequency divider circuit 3206. Moreover, this frequency divider circuit 3206 generates the shift clock signal CP so as to shift the aforementioned display data D₀ to D₃ to the shift register built in the driver. The timing signal generator circuit 3210 generates the driver latch signal LOAD, the frame signal FRM and the AC drive signal M to cause the liquid crystal driver circuit (or the driver) to generate those interface signals. Incidentally, the embodiment thus far described is limited to the case in which the outputs of the display data are the 4 bits D₀ to D₃. The present invention should not be limited thereto but can be applied to the cases of 8 bits and 16 bits. Moreover, the reset means 3204 should not be limited to the frequency divider circuit but may reset the X-axis display position adjusting circuit 3201, when the data of one line in the X-axis direction are transferred, to interrupt the input of the signal P₂. Fig.34 is a chart showing the timings of the output signals of the overall construction of Fig. 32. Incidentally, in the foregoing embodiment, the display data D are subjected to the serial/parallel conversions to drop the transfer speed to the driver so as to divide the frequency of the shift clock CP into one quarter. However, the serial data themselves can be transferred to the driver. The interface circuit of the present invention can be used in a variety of plane displays such as a liquid crystal panel (which should be referred to in Japanese Patent Laid-Open Nos. 94086/1986 and 174509/1986, for example) using a nonlinear resistive film such as silicon oxide or nitride film, a liquid crystal panel using a nonlinear element such as MIM or TFT, a smectic liquid crystal panel, a simple matrix TN plasma display, or an EL display. If the interface circuit is used in an unstorable display panel such as the simple matrix TN liquid crystal panel, the display element is not driven during the blanking period to reduce the substantial duty ratio, thus raising a problem that the contrast will drop. This problem is suitably eliminated in case the interface circuit is used in the storable display panel such as the aforementioned MSI, TFT and smectic liquid crystal panel. FIG. 28 shows another embodiment of the invention. In response to a 1/8 divider 2834 of Fig. 28, as has been described above, a latch signal LP is generated by a D-type flip-flop circuit 2839 and a NOR circuit 2840. On the other hand, the output of the 1/8 divider 34 has its frequency divided by a divider 2835. The first output P₆ of this divider 2835 is the 1/16 signal of the clock signal P₂. That divided signal P₆ is used to generate a set pulse P₄ by a D-type flip-flop 2845. As a result, an AND circuit 2846 generates the clock signal P₅. And, a 1/4 divider 2847 divides the frequency of the clock signal P₅ into 1/4 to generate the shift clock signal CP. As has been described above, the shift clock signal CP becomes the shift clock of the 4-bit parallel shift register, which is built in a liquid crystal driver IC, as the shift clock signal of the 4-bit display data D₀ to D₃. A flip-flop circuit 2848 divides the frequency of the shift clock signal CP to generate switching signals GP₁ and GP₂. Fig. 29 is a circuit diagram showing a further embodiment of the horizontal and vertical home position regulating circuits. In Fig. 29, the horizontal home position regulating circuit is constructed of: delay time setting means composed of a monostable multi-vibrator 2940 so as to determine the delay time by the time constant of a capacitor 2956 and a variable resistor 2957; synchronizing means using a D-type flip-flop 2944 for synchronization with the clock signal CK in response to the output of an AND circuit 2942; counting means using a variable counter 2946 enabled to count the number of the clock signal outputs of an AND circuit 2945 to set the counted number in a variable manner; and initializing means using a flip-flop circuit 2947 for initialization in response to the carry signal of the aforementioned variable counter. Likewise, the vertical home position regulating circuit is constructed of: delay time setting means using a monostable multivibrator 2948; synchronizing means using a D-type flip-flop 2952; counting means using a scanning number counter 2954 enabled to set the counted value in a variable manner; and initializing means using a D-type flip-flop for initialization with the carry output of the aforementioned scanning number counter. Next, the operations of the horizontal home position regulating circuit will be described in the following. In response to the horizontal synchronizing signal Hsyc, the flip-flop 2947 is reset so that the output Q₁ takes the "0" level. The output P of the monostable multivibrator is raised to the "1" level and fell to the "0" level after lapse of a predetermined time period. This holding time period of the "1" level is determined by the time constant C x R of the capacitor 2956 and the variable resistor 2957. As a result, after the predetermined time period, the output of a NOR circuit 2941 takes the "1" level and is inputted via the AND circuit 2942 to the D-type flip-flop 2944. As a result, the output Q₂ of the D-type flip-flop circuit 2944 is synchronized by the clock CK and outputted to the AND circuit 2945. As a result, the fine changes of the predetermined time period due to the fluctuations of the time constant CR and the voltage are always times to a constant value by that synchronizing means. The clock signal CK having passed through the AND circuit 2945 is inputted to the variable counter 2946. In the case of the display horizontal dot number 640, the carry signal is generated by the 640th clock signal CK, if the counted value is set at 640, and is inputted to the clock signal of the flip-flop circuit 2947. As a result, the output Q₁ of the flip-flop circuit 2947 takes the "1" level to fell the output of the NOR circuit 2941 to the "0" level. As a result, the output Q₂ of the D-type flip-flop takes the "0" level so that the generation of the clock CK is interrupted by the AND circuit 2945. As described above, the predetermined time period can be made arbitrarily variable by using the output P of the monostable multivibrator 2940 so that the display position in the horizontal (or X-axis) direction can be easily regulated. The vertical home position regulating circuit can likewise be regulated easily. If the vertical synchronizing signal Vsyc is inputted, a flip-flop circuit 2955 is reset so that the output Q₃ takes the "0" level. The output R of the monostable multi-vibrator is made to rise to the "1" level and is made to fall to the "0" level after lapse of a predetermined time period. The hold time of this "1" level can likewise be varied by adjusting a variable resistor 2959. After the predetermined time, the output of a NOR circuit 2949 takes the "1" level and is inputted through an AND circuit 2950 to a D-type flip-flop 2952. As a result, the output Q₄ of the D-type flip-flop circuit 2952 is synchronized with the horizontal synchronizing signal Hsyc and outputted to an AND circuit 2953. The horizontal synchronizing signal Hsyc having passed through the AND circuit 2953 is inputted to the variable counter 2954. In case the number of the vertical scanning lines for the display is 400, the carry signal is generated in response to the 400th horizontal synchronizing signal Hsyc, if the counted value is set at 400, and is inputted to the clock signal of the flip-flop circuit 2955. As a result, the output Q₃ of the flip-flop circuit 55 takes the "1" level to drop the output of the NOR circuit 2949 to the "0" level. As a result, the output Q₄ of the D-type flip-flop takes the "0" level so that the generation of the horizontal synchronizing signal Hsync is interrupted by the AND circuit 2953. Like the horizontal home position regulating circuit, moreover, the display position in the vertical (or Y-axis) direction can be easily regulated by regulating the variable resistor 2948 of the monostable multivibrator 2948. And, the output H DC of an AND circuit 2960 is a horizontal dot clock in the effective display area so that an image can be displayed in the liquid crystal display by making use of the clock H DC and the display data. Fig. 30 is a circuit diagram showing a further embodiment of the present invention. Fig. 31 is a timing chart of Fig. 30. Reference numeral 3013 denotes a 1/8 a divider for dividing the frequency of the dot clock P₁ to feed a latch signal to a latch circuit 3008. Numeral 3018 denotes a 1/4 divider for generating a latch signal and then counting the number of the dot clocks P₁ to feed the shift clock CP to a 4-bit parallel shift register built in the driver. Numeral 3019 denotes a flip-flop circuit for dividing the frequency of the output of the 1/4 divider into 1/2. Numerals 3009 and 3010 denote switching circuits for switching the 8-bit parallel signal of the aforementioned latch circuit 3008 for every four bits to output the display data D₀ to D₃. A D-type flip-flop circuit 3012 and a NOR circuit 3014 are set pulse generators for generating the set signal P₂ when the output of the vertical home position regulating circuit 3002 takes the "H" level. A flip-flop circuit 3015 is a circuit for setting in response to the set signal P₂ and resetting in response to the reset signal R₁ to generate the frame data P₃. Numeral 3016 denotes a D-type flip-flop circuit for clocking the reset signal R₁ by using the frame data P₃ as its data. A flip-flop circuit 3017 divides the frequency of the output of the D-type flip-flop circuit 3016. The present embodiment has the construction thus far described. Here, the output M of the flip-flop circuit 3017 is a control signal for inverting the polarity of the waveform of the drive signal for each frame. The output FRM of the D-type flip-flop circuit 3016 is both a frame signal for starting to scan the first common electrode of the Y-axis driver. The LOAD signal is a latch circuit for latching the display data D₀ to D₃ in the built-in latch circuit, after those of the display data, which correspond to the X-axis electrodes, are shifted by the shift clock CP to the 4-bit parallel shift register built in the X-axis driver, and a shift clock of the shift register, which is built in the Y-axis driver, to scan a next Y-electrode. Next, the operations of the present embodiment will be described in the following. A flip-flop circuit 3005 and a NOR circuit 3006 generate the reset signal R₁ and reset a horizontal home position regulating circuit 3001 to drop the output signal T₁ to the "L" level. The display data D are transferred to a shift register 3007 by using the dot clock P₁ as the shift clock input. In response to the latch signal having its frequency divided by the 1/8 divider 3013, the latch circuit 3008 converts the display data of the shift register 3007 to 8-bit parallel data. After the latch signal is outputted, the 1/4 divider 3018 divides the dot clock P₁ into 1/4 to output the shift clock CP for shifting the 4-bit parallel data D₀ to D₃ to the 4-bit parallel shift register built in the liquid crystal driver. When the vertical home position regulating circuit 3002 generates the output signal T₂, the D-type flip-flop circuit 3012 and the NOR circuit 3014 generate the set pulse P₂ for setting the flip-flop circuit 3015. This set signal P₂ sets the flip-flop circuit 3015 to raise the frame data signal P₃ to the "H" level. This frame data signal P₃ is fed as the data input of the D-type flip-flop circuit 3016. Next, when the aforementioned reset signal R₁ is generated, the flip-flop circuit 3015 is reset. Simultaneously with this, the D-type flip-flop circuit 3016 has its data shifted to raise the frame signal FRM to the "H" level. This frame signal FRM is dropped to the "L" level in response to the subsequent reset signal R₁. As a result, the aforementioned frame signal FRM has just the same pulse width as the period of the reset signal R₁ (i.e., the LOAD signal) and is fed as the data of the shift register built in the Y-axis driver. Moreover, absolutely the same reset signal (i.e., the LOAD signal) is inputted as the shift clock of that shift register so that the liquid crystal can be driven by the scanning signals timed all over the common electrodes. Incidentally, the aforementioned vertical fly-back period can be arbitrarily set by the vertical home position regulating circuit 3002. As has been described hereinbefore, according to the present embodiment, the frame signal is fed to the shift register of the Y-axis driver through the D-type flip-flop (or the shift register). As a result, the scanning time is common for the common electrodes from the first one to the last one. As a result, it is possible to solve the problem of the display quality of the prior art, in which the displays of the first and last common electrode lines are abnormally dense or thin, so that the displays cannot be misread by the observer. FIG. 35 is a circuit diagram showing another embodiment of the invention. In FIG. 35, Hsyc inputted into a D-type flip-flop 3551 is synchronized by clock signal CK and outputted to a D-type flip-flop 3552. A NOR circuit 3555 generates a first pulse by the rise edge of Hsyc. The first pulse resets a D-type flip-flop 3557 of a horizontal home position regulating circuit 3501, so that a NOR circuit 3560 puts out clock CK. A counter 3561 counts up the clock CK. When counted value of the counter 3561 becomes equal to the setting value of an external setting means 3562, a coincidence circuit 3563 which comprises an exclusive OR and a NAND generates a coincidence signal. The signal reverses the output of the flip-flop 3557 and stops supply of the clock CK to the counter 3561. Therefore it is possible to regulate the horizontal blanking period. The vertical blanking period may be regulated by counting the pulse signal P15 of the first pulse generating means through a counter 3567 and using the output of a coincidence circuit 3569 similarly. The setting of the horizontal or vertical blanking period may be regulated by the dot in X or Y axis direction. When both of the outputs Q of the flip-flops 3557 and 3565 become "L", a display start (home position) is taken so that a NOR circuit 3559 generates clock signal P1. The clock P1 is inputted into a 1/8 divider 3506 and S/P changing circuits 3510, 3511 and 3512. When the display data for 1 line are transferred, Hsyc fall down,Consequently, a second pulse generating means which comprises a D-type flip-flop 3553 and a NOR circuit 3554 generates pulse signal P16. The pulse P16 reverses the output Q of a flip-flop circuit 3558, so that the NOR circuit 3559 stops the generation of clock signal P1.

Claims: An interface for converting separate video signals into a display data signal and a timing signal for operating a thin display panel characterised by a timing circuit (101, 102, 103) arranged in response to at least one of a horizontal synchronizing signal (Hsyc) and a vertical synchronizing signal (Vsyc) to regulate the duration of a blanking period and arranged to generate a timing clock signal (P₁) at the end of the blanking period; a data treating circuit (105) enabled by the timing clock signal to receive serial input display data and comprising means (510, 511, 512) for converting the serial input display data into parallel display data, latch means (513, 514, 515) for temporarily storing the parallel display data, and switching means (540 to 546) for switching the output of the latch means in a time sharing manner for generating ouput display data; and a timing signal generator (104) arranged to generate drive timing signals for operating driver circuits of the thin display panel. An interface as claimed in claim 1 characterised in that the timing circuit comprises a horizontal home position regulating circuit (101) for controlling a timing for introducing horizontal effective display data into the data treating circuit (105), a vertical home position regulating circuit (102) for controlling a timing for introducing vertical effective display data into the data treating circuit and a clock control circuit (103) for generating the timing clock signal when both of the horizontal and vertical display data are effective. An interface as claimed in claim 2 characterized in that at least one of the horizontal and vertical home position regulating circuit (figure 27) comprises a counter (2722) for counting a reference signal (CK), external input means (2721) for arbitrarily setting said timing, and a coincidence detecting circuit (2723-5) for detecting a coincidence between the output of said counter and a set value of said external input means so that the display position is adjusted by said external input means. An interface as claimed in claim 2 or 3 characterized in that at least one of the horizontal and vertical home position regulating circuit (figure 29) comprises delay time setting means (2940,2956-7) for setting a desired delay time, synchronizing means (2944) for synchronizing the output of the delay time setting means with a clock signal (CK), a counter (2946) for counting the clock signal according to the output of the synchronizing means, and initializing means (2947) for initializing the synchronizing means according to the output of the counter (2946). An interface as claimed in any preceding claim characterised in that the data treating circuit comprises first switching means (208) for switching the output of the latch means for generating monochromatic output display data, second switching means (209) for switching the output of the latch means for generating multi-color output display data, and selecting means (210) for selecting a respective one of said output display data. An interface as claimed in any preceding claim characterised in that the data treating circuit (figure 5) comprises a color display data processing circuit, the converting means (510, 511, 512) being arranged to convert R, G and B color display serial data into parallel form, and the latch means and the switching means being arranged to co-operate so as to provide color mixing and blending means for generating mixed color output display data. An interface as claimed in claim 6 characterised in that the data treating circuit comprises display data reversing means (SW1) for reversing said color output display data. An interface as claimed in any preceding claim characterised in that the data treating circuit comprises first S/P converter means (2106-8) for converting R, G and B color display serial data into parallel form, shift registers (2112-4) for shifting the parallel R, G and B color display data, selecting gate circuits (2115-7) for selectively extracting the output of the shift registers, and second S/P converter means (2119) for converting serial data from the selecting gate circuits into parallel form. A thin display device having a thin display panel, and an interface for converting separate video signals into a display data signal and a timing signal for operating the thin display panel, and characterised by a timing circuit (101, 102, 103) arranged in response to at least one of a horizontal synchronizing signal (Hsyc) and a vertical synchronizing signal (Vsyc) to regulate the duration of a blanking period and arranged to generate a timing clock signal (P₁) at the end of the blanking period; a data treating circuit (105) enabled by the timing clock signal to receive serial input display data and comprising means (510, 511, 512) for converting the serial input display data into parallel display data, latch means (513, 514, 515) for temporarily storing the parallel display data, and switching means (540 to 546) for switching the output of the latch means in a time sharing manner for generating ouput display data; and a timing signal generator (104) arranged to generate drive timing signals for operating driver circuits of the thin display panel. A display device as claimed in claim 9 characterised in that the thin display panel has an X-Y dot matrix display electrode construction, and in that the X-electrodes comprise an uneven-numbered electrode group and an even-numbered electrode group, with the groups being led out respectively from opposite sides of the panel to each other. A display device as claimed in claim 9 or 10 characterised in that the thin display panel is a multi-color display panel, and in that the data treating circuit comprises a color arrangement selecting circuit for changing said output display data according to a type of arrangement of color dots of the thin display panel.

Inventors: KONDO, KENICHI SEIKO INSTRUMENTS INC.
Applicants: SEIKO INSTRUMENTS INC.
Application year: 1987
Main classification: G09G3
IPC codes: G09G3