QAM DEMODULATOR WITH RAPID RESYNCHRONIZATION FUNCTION

Abstract: In order to rapidly resynchronize a QAM demodulator by effectively operating a transversal equalizer, a message point of an incoming quadrature-modulated signal is checked as to its location within a signal space diagram. In the event that the message point is deviated within a predetermined region of the signal space diagram, a transversal filter functions normally irrespective of whether or not a demodulating section is synchronized, while in the event that the message point is deviated outside the predetermined region, the transversal filter is allowed to perform the normal operation thereof only if the demodulating section is in synchronism.

Description: This invention relates generally to a QAM (Quadrature Amplitude Modulation) demodulator and more specifically to such a demodulator featuring an improved function by which resynchronization can be achieved in a shorter time duration as compared with known QAM demodulators. This invention is highly suited for use in a digital radio transmission system. A digital radio transmission system is susceptible to multipath fading or the like and invites waveform distortion of the transmitted signal, which degrades signal reception. In order to minimize these problems, it is the current practice to employ a transversal equalizer using a tranversal filter. The transversal equilizer in a digital radio transmission system, however, has encountered the difficulty that distortion of the transmitted signal is apt to exceed the equalizing capability thereof. More specifically, upon the distortion reaching a level at which the equalizer is unable to deal with same, asynchronism of clock and carrier signals in a demodulator is induced and results in asynchronism of the control loop of the transversal filter. These conditions induce signal distortion within the equalizer itself. Therefore, even if the distortion of the transmitted signal again falls within the capability of the equalizer, the synchronized state is not automatically restored in the equalizer. A known approach to solving this problem is to reset the tap gain control signals to their initial values upon the occurrence of asynchronism in the demodulator. This prior art maintains the equalizer at reset until resynchronism of the clock and carrier in the demodulator occurs. Accordingly, as the equalizer remains inoperative during this time period, the control loop of the equalizer is not brought into synchronization unless the waveform distortion of the transmitted signal is lowered to a considerable extent. The problem of the prior art will further be discussed with reference to Figs. 1 through 3. Fig. 1 is a block diagram showing a known 16-QAM demodulator, which generally comprises a transversal equalizer 1 and a demodulator or demodulating section 2 interconnected thereto. The transversal equalizer 1 includes a tap gain control signal generator 3, four adders 5 to 8, four subtracters 9 to 12, a switch 85 and a transversal filter 4. On the other hand, the demodulator 2 includes a coherent detector 13, two 3-bit type of AD (Analog-to-Digital) converters 14 and 15, and a carrier recovery circuit 16. The transversal filter 1 includes a delay circuit with 5 taps and a tap gain controller (both not shown). The transversal filter 1 receives an incoming quadrature-modulated IF (Intermediate Frequency) signal, and reduces or eliminates intersymbol interference involved in the applied signal using tap gain control signals R+1, R-1, R+2, R-2, I+1, I-1, I+2 and I-2. These tap gain control signals are applied to the transversal filter 1 through the switch 85 from the adders 5-8 and subtracters 9-12. The coherent detector 13 receives the output of the transversal filter 1 and coherently or synchronously demodulates same using a recovered carrier applied thereto from the carrier recovery circuit 16. The reproduced baseband signals (analog) P and Q are applied to the AD converters 14 and 15. The AD converter 14 outputs two data signals D1p, D2p, and an error signal Ep, while the other AD converter 14 outputs two data signals D1q, D2q, an error signal Eq, and a clock signal CLK. The carrier recovery circuit 16 is supplied with D1p, D1q, Ep, Eq, and recovers the carrier which is applied to the coherent detector 13 as above mentioned. On the other hand, the tap gain control signal generator 3 receives all of the outputs of the AD converters 14 and 15, and produces control signals Rp+1, Rp-1, Rp+2, Rp-2, Rq+1, Rq-1, Rq+2, Rq-2, Ip+1, Ip-1, Ip+2, Ip-2, Iq+1, Iq-1, Iq+2 and Iq-2, which undergo addition and subtraction at the next stage and then are applied, as the tap gain control signals R+1 through I+2, to the transversal filter 1 via the switch 85. The carrier recovery circuit 16 produces a rest signal R which assumes a logic 0 as long as the demodulator 2 is synchronized and which assumes a logic 1 upon the demodulator 2 going out of synchronism. The switch 85 is reset in response to the reset signal R assuming a logic 1. More specifically, the switch 85 prohibits the tap gain control signals R+1 through I-2 to be applied to the transversal filter 1, and begins applying a previously determined constant levels to the transversal filter 1. This means that the transversal equalizer 1 is maintained inoperative while the reset signal R assumes a logic 1. The principle operation of a transversal equalizer has been described in an article entitled "4/5 GHz 16-QAM 200Mb/s demodulator with transversal equalizer" in the 1984 plenary meeting of The Institute of Electronics Communications Engineers of Japan. Further, the carrier recovery circuit has been disclosed in detail in Japanese Patent Application No. 56-15775. Figs. 2A and 2B are block diagrams showing in detail the arrangement of the conventional tap gain control signal generator 3. As shown in Fig. 2A, tapped delay means 17L, 20L, 23L, 26L, 29L and 32L are provided in parallel, each of which includes three one-bit delay lines (17-34). The one-bit delay lines 17, 20, 26 and 29 respectively receives the data signals D1p, D2p, D1q and D2q, while the other one-bit delay lines 23 and 32 receives respectively the error signals Ep and Eq. Each of the delay means 17L, 20L, 23L, 26L, 29L and 32L outputs delayed signals (D1p0, D1p1, D1p2, etc., as shown in the drawing), some of which are applied to exclusive OR gate 37-52 of Fig. 2B and are utilized to generate the above-mentioned tap gain control signals Rp+1 through Ip-2. The operations of the arrangements shown in Figs. 2A and 2B will be well known to those skilled in the art, so that the further description thereof will be omitted for clarity. In order to explain in more detail the problem of the prior art, reference is now made to Fig. 3 in which a space diagram of the incoming modulated IF signal is illustrated concurrently with the outputs of the AD converters 14 and 15. In Fig. 3, 16 black circles are arranged in parallel with the orthogonal axes P and Q, and represent respectively normal or standard positions of the incoming message points A1 to A16. It is assumed that the message points A1, A5 and A13 respectively depart from their normal positions to A1′, A5′ and A13′ due to intersymbol interference (viz., the standard message points are deviated in-phase with same polarity). In accordance with this assumption if the demodulator 2 is in synchronism, the deviated message points A1′, A5′ and A13′ remains at their positions, and hence appropriate error signals are generated by which the undesirably deviated message points are able to restor their standard positions. On the other hand, if the demodulator 2 is not synchronized, the deviated message point A5′ moves along circle M1 and is located at a message point A5″ (for example). As a result, this message point A5″ is erroneously determined as a message point which is deviated from the nearest message point A1. For this reason the transversal equalizer 1 is reset or rendered inoperative if the demodulator 2 is not synchronized. This control pause of the equalizer continues until the demodulator 2 restores synchronism. In order to overcome this problem, intermittent resetting of a transversal filter has been proposed in the United States Patent 4,567,599 assigned to the same entity as the instant invention. According to this prior art, when asynchronism is detected in a demodulator, a reset signal is intermittently generated to render the transversal filter operative at intervals during a period in which the transversal filter is paused. This prior art strives to shorten the inoperative duration of the equalizer by discontinuously checking quality recovery of an incoming IF signal through intermittent resetting of the equalizer. However, such a negative approach has proven insufficient to effectively shorten the inoperative period of the equalizer. It is an object of this invention to provide a QAM demodulator equipped with a transversal equalizer, which features an improved function by which resynchronization can be achieved in a shorter time duration. In general terms the present invention provides a QAM demodulator whose normal operation can rapidly be restored by effectively operating a transversal equalizer. According to the present invention, a message point of an incoming quadrature-modulated signal is checked as to its location within a signal space diagram. In the event that the message point is deviated into a predetermined region of the signal space diagram, a transversal filter functions normally irrespective of whether or not a demodulating section is synchronized, while in the event that the message point is deviated to a portion outside the predetermined region, the transversal filter is allowed to perform its normal operation only if the demodulating section is in synchronism. More specifically, the present invention takes the form of a QAM demodulator including a transversal equalizer and a demodulating section. The transversal equalizer includes a transversal filter which compensates for intersymbol interference involved in an incoming quadrature-amplitude modulated signal applied thereto. The demodulating section is supplied with the output of the transversal filter and produces data and error signals. According to the present invention the transversal equalizer comprises: first means for receiving the data and error signals and for determining whether or not a message point of the incoming signal is deviated from the normal position thereof into a predetermined region of a signal space diagram, the first means outputting a logic signal indicating whether the message point is deviated into the predetermined region; and second means for controlling the operation of the transversal filter in response to the logic signal such that (a) in the event that the message point is deviated within the predetermined region, the transversal filter functions normally irrespective of whether or not the demodulating section is synchronized, and (b) in the event that the message point is deviated outside the predetermined region, the transversal filter is allowed to perform the normal operation thereof only if the demodulating section is in synchronism. The features and advantages of the present invention will become more clearly appreciated from the following description taken in conjunction with the accompanying drawings in which like blocks or signals are denoted by like reference numerals and in which: Fig. 1 is a block diagram showing a conventional 16-QAM demodulator; Figs. 2A and 2B are block diagrams illustrating one example of a portion of the Fig. 1 arrangement; Fig. 3 is a signal space diagram of an incoming quadrature-modulated signal and also shows tables of the outputs of some blocks included in the Fig. 1 arrangement; Fig. 4 is a block diagram showing a 16-QAM demodulator according to this invention; Figs. 5A through 6 are block diagrams illustrating in detail a block of the Fig. 4 arrangement; Fig. 7 is a signal space diagram of an incoming quadrature-modulated signal and also shows tables of the outputs of some blocks included in the Fig. 4 arrangemnt; Figs. 8 through 10 are block diagrams showing a second embodiment according to this invention; and Fig. 11 is a signal space diagram of an incoming quadrature-modulated signal and also shows tables of the outputs of some of the blocks of the second embodiment. Reference is now made to Fig. 4, wherein a first embodiment of this invention is shown in block diagram form. The system shown in Fig. 4 is a 16-QAM demodulator and is identical to that shown in Fig. 1 except that (a) a tap gain control signal generator 3′ of Fig. 4 is configured somwhat differently as compared with its counterpart 3 and (b) the reset signal R is applied to the generator 3′. The above-mentioned differences will be described later in detail, but the remaining portions of Fig. 4 will not be described since already referred to with reference to Fig. 1. The details of the tap gain control signal generator 3′ are illustrated in Figs. 5A to 5C and Fig. 6. Fig. 5A is identical to Fig. 2A but presented again only for the convenience of explaining the first embodiment. Fig. 5B is a block diagram showing circuitry coupled to the Fig. 5A arrangement. Fig. 5C is a block diagram showing circuitry which is coupled to the Fig. 5B arrangement and which generates the control signals Rp+1 through Iq-2. The Fig. 5B arrangement comprises a region determining circuit 69, three AND gates 70, 71 and 72, and two D flip-flops 35, 36. The region determining circuit 69 has inputs coupled to the delay means 17L, 20L, 23L, 26L, 29L and 32L of Fig. 5A and coupled to the carrier recovery circuit 16, and is supplied with the signals D2p0, Ep0, D2q0, Eq0, and the reset signal R. The region determining circuit 69 produces an output C, while the OR gates 70, 71 and 72 produce outputs C0, C1 and C2, respectively. The circuit 69 will be explained in detail with reference to Fig. 6 which shows the detailed arrangement of the circuit 69 and which comprises three inverters 73, 74 and 75, two exclusive OR gates 76, 77, and two OR gates 78, 79. The arrangement shown in Fig. 5C is identical to that of Fig. 2B except that the former arrangement further includes D flip-flops 53 to 68, whose data inputs D are respectively coupled to the outputs of the exclusive OR gates 37 to 52 and whose clock inputs receive the control signals C, C2 from the circuit shown in Fig. 5B. Fig. 7 is a space diagram showing the 16 normal positions of the incoming IF message points A1 to A16, which corresponds to those shown in Fig. 3. In Fig. 7, the hatched portion (region A) is defined as a controllable region, while the non-hatched portions (regions B) are defined as uncontrollable regions. More specifically, any signal deviated into the region A is apt to restore its normal position with high probability as compared with the case where a deviated signal is located with the region B. Such a probability increases in the case of a multivalue QAM demodulator more than 16 (such as 64- and 256-QAM demodulators). According to the present invention, in the event that the demodulator 2 remains in synchronism, the transversal equalizer 1 is allowed to operate normally. On the other hand, if the demodulator 2 falls into asynchronism, the equalizer 1 functions normally only if a deviated message point is detected within the region A. In other words, the equalizer 1 is rendered inoperative only if the demodulator 2 is not synchronized and the deviated signal is within a B region. The operation of the tap gain control signal generator 3′ will further be described with reference to Figs. 4 through 7. The AD converters 14, 15 (Fig. 4) apply the signals D1p, D2p, Ep, D1q, D2q and Eq to the delay means 17L, 20L, 23L, 26L, 29L and 32 L (Fig. 5A), respectively. The region determining circuit 69 receives the delayed outputs D2p0, Ep0, D2q0 and Eq0 from the delay means 20L, 23L, 29L and 32L, respectively, and also receives the reset signal R from the carrier recovery circuit 16. Further, the various delayed outputs obtained at the delay means in Fig. 5A, are applied to the exclusive OR gates 37 to 52 of Fig. 5C in the same manner as in Figs. 2A and 2B. The outputs of the exclusive OR gates 37 to 52 of Fig. 5C are respectively applied to the data inputs D of the corresponding D flip-flops 53-68. The flip-flops 53-68 of Fig. 5C apply the control signals Rp+1 through Iq-2 to the adders 5-8 and the subtracters 9-12 (Fig. 4). It should be noted that it depends on the clock signals C0, C2 if the control signals Rp+1 through Iq-2 have been renewed or not. In Fig. 6, the OR gate 79 outputs a logic 1, if the signals D2p0 and Ep0 assume the same logic state or if the signals D2q0 and Eq0 assume the same logic state. In other words, if a deviated message point is located within the controllable region A (Fig. 7), the OR gate 79 outputs a logic 1. Therefore, the output C of the OR gate 78 assumes a logic 1 regardless of whether or not the demodulator 2 is synchronized. The output C (a logic 1) causes the outputs C0, C1 and C2 of the AND gates 70, 71 and 72 (Fig. 5B) to assume a logic 1 in synchronism with the clock CLK. (It should be noted that the output C1 is not applied to the D flip-flops shown in Fig. 5C in this embodiment). Therefore, the D flip-flops 53 to 68 respond to the outputs C0 and C2 and relay the outputs of the corresponding exclusive OR gates 37-52 to the adders 5-8 and the subtracters 9-12, whereby the equalizer 1 functions normally. In the event that a deviated message point resides within the uncontrollable region B, none of the exclusive OR gates 76, 77 assumes a logic 1. This means that the equalizer 1 is allowed to normally perform its function only if the demodulator 2 stays in synchronism (viz., if the reset signal assumes a logic 0). In the case that the output of the OR gate 78 is a logic 0, each D flip-flop of Fig. 5C holds its output and continues outputting same. Therefore, the transversal filter 1 is controlled by the tap control signals which are stored in the D flip-flops 53-68 just before the filter control becomes impossible. This is one of the important features of this invention. Viz., transversal filter 1 is effectively controlled by the control signal which is considered as the most appropriate control signal while the transversal filter 4 is rendered inoperative. It should be noted that according to the prior art, the transversal filter 4 is controlled by a predetermined initial value when it stops automatic control. Reference is now made to Figs. 8 through 11, wherein a second embodiment according to this invention is illustrated. Figs. 8, 9, 10 and 11 correspond to Figs. 5A, 5B, 6 and 7, respectively, and Figs. 4 and 5C of the first embodiment are used in the second embodiment without being unchanged or slightly modified. As clearly seen from Fig. 11, this embodiment is directed to a 64-QAM demodulator and the underlying principle thereof is essentially equal to that of the first embodiment. As previously mentioned, this invention is more useful when applied to higher multilevel QAM type demodulators than the lower multilevel type (such as 16-QAM demodulators). The arrangement of Fig. 8 is identical to that of Fig. 5A except that the former arrangement further includes two delay means 120L and 129L adapted to receive data signals D3p and D3q, respectively. It is understood that the AD converters 14, 15 of Fig. 4 should be modified in a manner to ouput the data signals D3p and D3q. The arrangement of Fig. 9 is identical to that of Fig. 5B except that a region determining circuit 69′ of Fig. 9 is further supplied with the data signals D3p0 and D3q0. In Fig. 9, the outputs C0 and C2 are fed to the arrangement shown in Fig. 5C. Fig. 10 is a block diagram showing in detail the region determining circuit 69′, which includes an inverter 80, four AND gates 81 to 84, four OR gates 85 to 88. Fig. 11 corresponds to Fig. 7, and It is understood that A and B regions of Fig. 11 are defined by the output C of Fig. 10. Operation of the second embodiment is essentially identical to that of the first embodiment, and hence further descriptions of the second one will be omitted for clarity. This invention demonstrates a remarkable effect when a message point deviates in an in-phase direction as above mentioned. However, even if a message point deviates in an orthogonal or phase direction, the demodulator according to this invention is brought into synchronism quicker than the known demodulators. In the above, the transversal equalizer according to the present invention has been described as a type which is interposed in a IF stage. However, this invention is applicable to a transversal equalizer provided in a base band stage with simple modifications. Further, this invention can be applied to 256-QAM demodulator or even more higher multilevel type QAM demodulators.

Claims: A QAM demodulator including a transversal equalizer (1) and a demodulating section (2), said transversal equalizer (1) including a transversal filter (4) which compensates for intersymbol interference involved in an incoming quadrature-amplitude modulated signal applied thereto, said demodulating section (2) receiving the output of said transversal filter (1) and producing data and error signals, characterized in that said transversal equalizer comprises: first mean (3') for receiving the data and error signals and for determining whether or not a message point of the incoming signal is deviated from the normal position thereof into a predetermined region of a signal space diagram, said first means (3') outputting a logic signal indicating whether the message point is deviated into said predetermined region; and second means (85) for controlling the operation of said transversal filter (4) in response to said logic signal such that (a) in the event that the message point is deviated within said predetermined region, said transversal filter (4) functions normally irrespective of whether or not said demodulating section (2) is synchronized, and (b) in the event that the message point is deviated outside said predetermined region, said transversal filter (4) is allowed to perform the normal operation thereof only if said demodulating section (2) is in synchronism. A QAM demodulator as claimed in claim 1, wherein said predetermined region is defined, within each quadrant of the signal space diagram, as a region surrounding the area enclosed by the plurality of normal message points in that quadrant.

Inventors: MATSUURA, TORU
Applicants: NEC CORPORATION
Application year: 1987
Main classification: H04L27
IPC codes: H04B3, H03H15, H04L27, H04B7