Data processor capable of immediately calculating branch address in relative address branch

Abstract: A data processor includes a data bus of N bits, an address bus of 2N bits, a memory coupled to the address bus so that a necessary information can be read from a location indicated by the address transmitted through the address bus, and first and second instruction address registers coupled to the address bus for respectively storing a less significant portion and a more significant portion of the address of an instruction to be read from the memory. An arithmetic and logic unit is coupled to the data bus and capable of adding the content of the first instruction address register and the offset contained in a relative address branch instruction so as to output the result of addition to the address bus as the lower N bits of the branch destination address. A control circuit is coupled to the arithmetic and logic unit so as to generate an increment/decrement signal on the basis of the result of addition by the arithmetic and logic unit. An increment/decrement is coupled through the data bus to the second instruction address register and controlled by the increment/decrement signal so as to increment the content of the second instruction address register when the increment signal is generated and to decrement the content of the second instruction address register when the decrement signal is generated, whereby the incrementer/decrementer outputs the incremented/decremented data to the address bus as the higher N bits of the branch destination address.

Description: Background of the Invention Field of the Invention The present invention relates to a stored program type digital computer, and more specifically, to a data processor for use in small sized digital computers such as microcomputers. Description of related art In general, the stored program digital computers have been adapted to fetch necessary instructions and data from an associated memory so as to execute necessary operation. At present, a program counter is widely used as means for designating the address of instructions to be read out of the memory. Namely each time one instruction is executed, the program counter is incremented to designate the address of an instruction to be executed next, so that a sequence of instructions are read in accordance with the address indicated by the program counter. In this method, however, in order to change a flow of sequential operations, a so-called branch instruction is required. The branch instruction is divided into an absolute address branch instruction and a relative address branch instruction. Most of small scaled microcomputers of an initial stage had been operated with only the absolute address branch instructions. A first reason for this is that the microcomputers of the initial stage can handle only jobs of several kilobytes or less in the amount of programs, and therefore, use of the absolute address branch had not so given a trouble in development of programs. A second reason in that a complicated control for hardware is required in order to execute the relative address branch. However, appearance of microcomputers, which have a memory space of 64 kilobytes or more, has required as one necessary minimum condition that a program is relocatable in the course of development from the viewpoint of facility of edition and modification of program. For complying with this demand, the branch instruction should be the relative address branch instruction. Heretofore, the relative address branch instruction has been executed by calculating the branch address by use of an arithmetic and logic unit for data processing, and then by setting the calculated branch address to the program counter. In general microcomputers, however, the address information for memory access has a bit length larger than that of the data processed in the microcomputer. Therefore, the arithmetic and logic unit cannot calculate the destination address of the relative address branch at only one operation. Therefore, a plurality of operations must be executed. This is one hindrance in a high speed operation of the computer. Reviewing the relative address branch instructions in actual computer programs from a statistical viewpoint, the branch destination addresses distribute in a limited range near to the current address, and it is a rare case that the branch destination addresses distribute in a wide range accessible by the microcomputer. This means that it is sufficient if the microcomputer has a function of branching to an address contained in a limited range in the case of the relative address branch instruction. In any case, even if the relative address branch has the feature as mentioned above, a plurality of operations are still required for calculation of the branch destination address. Therefore, in order to speed up the calculation of the branch destination address in the prior art, it was necessary to provide an independent operating unit only for the branch destination address calculation so that the arithmetic and logic unit for data processing is not used for address calculation. A technique for high speed processing of relative jump instructions is disclosed in IBM technical disclosure bulletin, vol. 20, No. 4, September 1977, pages 1284-1285. In this technique the assembler calculates the lowest four bits of the destination address and inserts them into the instruction instead of the actual displacement, and depending from the jump direction and a comparison of the said lowest four bits of the destination address with the lowest four bits of the programm counter the remaining twelve bits are either incremented or decremented. Increment is conducted by a ordinary 16-bit increment logic, and decrement is conducted by using a 8-bit ALU and an additional four bit decrementer. Accordingly, it is an object of the present invention to provide a microcomputer which has overcome the above mentioned disadvantage of the conventional ones. Another object of the present invention is to provide a data processor capable of calculating a branch destination address of a relative address branch at a high speed and with a simple additional circuit. These objects are achieved by a data processor as defined in claim 1; the dependent claims are related to further developments of the invention. The above and other objects, features and advantages of the present invention will be apparent from the following description of the preferred embodiment of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram of one embodiment of the data processor in accordance with the present invention; Figure 2 is a circuit diagram of the control circuit shown in Figure 1; and Figure 3 illustrates the structure of the machine language of the relative address branch instruction used in the embodiment shown in Figure 2. Description of the Preferred Embodiment Referring to Figure 1, a data processor in accordance with the present invention comprises an address bus 10 used for transmitting an address information for access to a memory 12 coupled to the address bus 10. In this embodiment, the address bus 10 is of a parallel type having a width of 16 bits. The memory 12 is also coupled to a data bus 20 used for transferring various items of data within the computer. In this embodiment, the data bus 20 is of a parallel type having a width of 8 bits. A pair of instruction address registers 30 and 31 of 8 bits are coupled at their outputs to the data bus 20. Further, a pair of incrementer/decrementers 40 and 41 of 8 bits are coupled at their one inputs to the data bus 20 and at their other inputs to the outputs of the instruction address registers 30 and 31, respectively. Outputs of the incrementer/decrementers 40 and 41 are coupled to respective inputs of a pair of address latches 50 and 51 of 8 bits, respectively. These address latches 50 and 51 are coupled at their outputs to the less significant 8 bits and the more significant 8 bits of the address bus 10, respectively, and also to inputs of the instruction address registers 30 and 31, respectively. Furthermore, the shown data processor includes an arithmetic and logic unit (ALU) 60 having a pair of 8-bit inputs coupled to outputs of a pair of input temporary registers 61 and 62 of 8 bits, which are in turn coupled at their inputs to the data bus 20. The ALU 60 has an 8-bit output coupled to an input of an output temporary register 63 of 8 bits, whose output is coupled to the data bus 20. The most significant bit (MSB) 64 of the temporary register 61 is supplied to a control circuit 70, which also receive a carry signal 65 from the ALU 60, another carry signal 66 from the incrementer/decrementer 40, and a control signal 67 indicative of a relative address branch instruction. The control circuit 70 is adapted to respond to the above four signals to generate an increment signal 71 or a decrement signal 72 to the incrementer/decrementer 41. Specifically, the instruction address registers 30 and 31 store the address of an instruction stored in the memory 12 and to be read from the memory 12, in such a manner that the register 30 stores less significant 8 bits of the address and the register 31 stores more significant 8 bits of the same address. On the other hand, the input temporary registers 61 and 62 respectively receive through the data but 20 the data to be inputted to the ALU 60, and then, output the temporarily held data to the ALU 60. At the same time, the most significant bit (MSB) signal 64 is supplied to the control circuit 70 from the input temporary register 61. For example, the ALU 60 adds the pair of data supplied from the temporary registers 61 and 62, and outputs a data signal representative of the result of addition through the output temporary register 63 to the data bus 20. Concurrently with this operation of addition, the ALU 60 generates the carry signal 65 to the control circuit 70 if a carry has occurred. The incrementer/decrementers 40 and 41 respectively receive the data outputted on the data bus 20, and then, output the data to the address latches 50 and 51, respectively. Furthermore, when the increment signal 71 is generated by the control circuit 70, the incrementer/decrementer 41 receiving the more significant half of the data will increment the content of the more significant instruction address register 31 to output an incremented address information to the address latch 51. When the decrement signal 72 is generated by the control circuit 70, the incrementer/decrementer 41 will decrement the content of the register 31 so as to output the decremented address information to the address latch 51. These address latches 50 and 51 respectively latch the inputted address information of 8 bits, and then, output the latched address to the address bus 10 in the form of 16 bits. Referring to Figure 2, there is shown a circuit diagram of the control circuit 70. The shown control circuit 70 includes a three-input AND circuit 74 connected to receive at its first input the control signal 67 indicative of the relative address branch instruction, at its second input the carry signal 65 outputted from the ALU 60 and at its third input through an inverter 76 the MSB signal 64 supplied from the input temporary register 61. An output of the AND circuit 74 is connected to one input of an OR circuit 73, whose other input is connected to receive the carry signal 66 outputted from the incrementer/decrementer 40. The OR circuit 73 generates the increment signal 71 which is supplied to the incrementer/decrementer 41. The control circuit 70 also includes another three-input AND circuit 75 receiving the control signal 67 and the MSB signal 64 and also the carry signal 65 through another inverter 77. This AND circuit 75 generates the decrement signal 72 to the incrementer/decrementer 41. Turning to Figure 3, there is shown one example of a machine language of the relative address branch instruction. The branch instruction includes two bytes, a first byte of which is composed of an operation code (OPC). The second byte indicates a branch relative address, which is divided into a most significant bit (MSB) and other seven bits and defined as follows: When the MSB is of "0", it is instructed to branch to the address obtained by adding the current address with the lower seven bits of the second byte. When the MSB is of "1", it is instructed to branch to the address obtained by adding the data in a complement form of the lower seven bits of the second byte to the current address (i.e., by subtracting the data of the lower seven bits of the second byte from the current address). This operation for the branch instruction is executed under control of a sequence controller (not shown) as the result of the decoding of the operation code included in the first byte. Now, operation will be explained. When the relative address branch instruction is detected, the control signal 67 is brought into a high level "1". Further, the data of the second byte of the relative address branch instruction as shown in Figure 3 is stored in the input temporary register 61, and the less significant byte of the instruction address contained in the instruction address register 30 is stored through the data bus 20 to the input temporary register 62. The pair of data stored in the temporary register 61 and 62 are supplied to the ALU 60 where the pair of data are added. The result of addition is outputted to and held in the output temporary register 63, and then, transferred through the data bus 20 to the less significant incrementer/decrementer 40. At this time, the incrementer/decrementer 40 carries out neither the increment operation nor the decrement operation, so that the result of addition is inputted to the address latch 50 as it is. Concurrently with this operation, the control circuit 70 receiving the signals 64 and 65 will generate the increment signal 71 or the decrement signal 72 to the more significant incrementer/decrementer 41. Specifically, if the MSB signal 64 of the input temporary register 61 is of "0", when the carry signal 65 is generated by the ALU 60, the increment signal 71 is generated since the control signal 67 is at a high level "1". On the other hand, if the MSB signal 64 of the input temporary register 61 is of "1", when the carry signal 65 is not generated by the ALU 60, the decrement signal 72 is generated. If the increment signal 71 is inputted to the more significant incrementer/decrementer 41, the content of the more significant instruction address register 31 is incremented by the more significant incrementer/decrementer 41, so that the incremented data is outputted to the address latch 51. On the other hand, when the decrement signal 72 is inputted to the more significant incrementer/decrementer 41, the content of the more significant instruction address register 31 is decremented by the incrementer/decrementer 41, and the decremented data is outputted to the address latch 51. In the other cases than the two cases mentioned above, since the result of the address calculation executed by the ALU 60 for the lower 8 bits of the address does not influence the upper 8 bits of the address, neither the increment signal 71 nor the decrement signal 72 is generated. Namely, the content of the more significant instruction address register 31 is inputted to the address latch 51 without modification. Thus, when the MSB signal 64 is of "0", the branch destination absolute address of 16 bits is obtained by adding the total 16-bit content of the instruction address registers 30 and 31 with the lower 7 bits of the second byte of the relative address branch instruction, and then latched in the address latches 50 and 51 in a divided form. The address of 16 bits in total latched in the address latches 50 and 51 is outputted to the address but 10 and hence to the memory 12. In addition, if the MSB signal 64 is of "1", the branch destination absolute address of 16 bits is calculated by subtracting the lower 7 bits of the second byte of the relative address branch instruction from the 16 bit content of the instruction address registers 30 and 31, and then, is latched in the address latches 50 and 51 so that it is transferred to the address bus 10. When the control signal 67 is at a lower level "0" representative of non-branch operation, the AND gates 74 and 75 are closed so that neither the increment signal nor the decrement signal is generated by the AND gates 74 and 75. In this case, each time one operation is executed by the ALU 60, the less significant incrementer/decrementer 40 increments the content of the less significant instruction address register 30 and outputs the incremented data to the address latch 50. As the result of the increment, if the carry signal 66 is generated by the less significant incrementer/decrementer 40, the carry signal 66 is supplied through the OR circuit 73 as the increment signal 71 to the more significant incrementer/decrementer 41. At this time, this incrementer/decrementer 41 increments the content of the more significant instruction address register 31 and outputs the incremented data to the address latch 51. Unless the increment signal 71 is inputted, the incrementer/decrementer 41 supplies the content of the register 31 to the address latch 51 without modification. Accordingly, the circuits 30, 31, 40, 41, 50 and 51 function as a program counter of 16 bits in a normal sequential program operation.

Claims: A data processor in which a memory access address information has a bit length larger than that of data processed in the processor, which comprises an address bus (10), a data bus (20), first and second instruction address registers (31, 30) coupled to the address bus (10) and the data bus (20) and used for respectively storing a more significant portion and a less significant portion of the address of an instruction to be read, an arithmetic and logic unit (60) coupled to the data bus (20) and capable of executing a calculation on the basis of the content of the second instruction address register (30) and the offset contained in a relative address branch instruction, a control circuit (70) coupled to the arithmetic and logic unit so as to generate an increment signal (71) or a decrement signal (72) on the basis of the result of the calculation by the arithmetic and logic unit, an incrementer/decrementer (41) coupled through the data bus to the first instruction address register (31) and controlled by the increment signal (71) and the decrement signal (72) so as to increment the content of the first instruction address register (31) when the increment signal is received and to decrement the content of the first instruction address (31) register when the decrement signal is received. A data processor as claimed in claim 1, further comprising a memory (12) coupled to the address bus so that a necessary information can be read from a location indicated by the address transmitted through the address bus. A data processor as claimed in claims 1 or 2, characterized in that the data bus (20) and each of the first and second instruction address registers (30, 31) are of N bits. A data processor as claimed in Claim 3 further comprising a second incrementer/decrementer (40) coupled to the second instruction address register (30), wherein the first and second incrementer/decrementers (41, 40) are coupled at their outputs to first and second address latches (51, 50) of N bits, which are in turn coupled at their outputs to the more significant N bits and the less significant N bits of the address bus (10), respectively, and also coupled to the first and second instruction address registers (31, 30), respectively. A data processor as claimed in Claim 3 wherein the arithmetic and logic unit (60) has a first N-bit input coupled through a first input temporary register (61) to the data bus so as to receive a N-bit portion of the relative address branch instruction including the offset, and a second N-bit input coupled through a second input temporary register (62) to the data bus so as to receive the content of the second instruction address register (30). A data processor as claimed in Claim 5 wherein the N-bit portion held in the first input temporary register (61) includes the most significant bit (MSB) indicative of whether addition or substraction should be executed to obtain the branch destination address from the relative branch address, and the other (N-1) bits representative of the relative branch address, and the control circuit (70) receives a carry signal (65) generated by the arithmetic and logic unit (60) and the most significant bit signal (64) of the first input temporary register, the control circuit operating to selectively generate the increment signal (71) or the decrement signal (72) in response to a logical combination of the two input signals. A data processor as claimed in Claim 6 wherein the control circuit (70) includes a first AND circuit (74) receiving at its first input the carry signal (65) from the arithmetic and logic unit (60) and at its second input through an inverter (76) the most significant bit signal (64) of the first input temporary register (61) for the purpose of generating the increment signal (71), and a second AND circuit (75) receiving at its first input through another inverter (77) the carry signal (65) from the arithmetic and logic unit (60) and at its second input the most significant bit signal (64) of the first input temporary register (61) for the purpose of generating the decrement signal (72). A data processor as claimed in claim 7, wherein each of the first and second AND circuits (74, 75) has a third input receiving a control signal (67) indicative of the relative address branch instruction. A data processor as claimed in claim 3, wherein the arithmetic and logic unit (60) is capable of adding the content of the second instruction address register (30) and the offset contained in a relative address branch instruction so as to output the result of addition to the address bus (10) as the lower N bits of the branch destination address and wherein the incrementer/decrementer (41) outputs the incremented/decremented data to the address bus as the higher N bits of the branch destination address.

Inventors: KIMOTO MANABU C O NEC CORPORAT, KIMOTO, MANABU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1987
Main classification: G06F9
IPC codes: G06F9, G06F12