Clock recovering device

Abstract: A device for recovering a clock from received data which has a different duty ratio is disclosed. The optimum timing of a recovered clock is determined based on the pulse width of received data. A clock is accurately recovered so long as the duty ratio of received data is not greater than ±50 %.

Description: The present invention relates to a clock recovering device and, more particularly, to a device for accurately recovering a clock from received data which has a different duty ratio of logical ONEs and logical ZEROs. For the recovery of a clock from received data, it has been customary to detect a transition of the incoming data and, if the recovered clock is low level (or high level) at the instant of detection of a transition, retard (or advance) the phase of the recovered clock deciding that the phase is advanced (or retarded). In this manner, a prior art clock recovering device corrects the phase of a recovered clock timed to transitions of received data. However, a problem with such a device is that when the duty ratio of ONEs and ZEROs of received data is different, even if the phase of a recovered clock is greatly deviated, the phase is decided as being advanced and retarded alternately every time a transition is detected. This indefinitely prevents a clock from being correctly recovered. A clock recovering device according to the preamble of claim 1 is disclosed in FR-A-2 336 833. It is, therefore, an object of the present invention to provide a clock recovering device capable of accurately recovering a clock from received data despite a difference of duty ratio. This object is solved with the features of the claims. In accordance with the present invention, a device for recovering a clock from received data which has a different duty ratio determines the optimum timing of a recovered clock based on the pulse width of received data. A clock is accurately recovered so long as the duty ratio of received data is not greater than ±50 %. Figs. 1 and 2 are timing charts demonstrating the operation of a prior art clock recovering device; Fig. 3 is a block diagram showing a clock recovering device embodying the present invention; Fig. 4 is a timing chart representative of the operation of the clock recovering device in accordance with the present invention; Fig. 5 is a block diagram showing another embodiment of the present invention; and Fig. 6 is a chart showing data stored in a ROM (Read Only Memory) which is included in the device of Fig. 5. To better understand the present invention, the operation of a prior art clock recovering device will be outlined with reference to Figs. 1 and 2. As shown in Fig. 1, it is a common practice to correct the phase of recovered clock by detecting a transition of received data and, if the recovered clock is low level at the instant of detection of a transition, retarding the phase deciding that the phase is advanced and, if it is high level, advancing the phase deciding that the phase is retarded. As previously stated, such a prior art implementation indefinitely fails to correctly recover a clock if the duty ratio is not greater than ±50 %, because, as shown in Fig. 2, the phase is decided as being advanced and retarded alternately timed to the transitions of received data even if the phase of the recovered clock is greatly deviated. Referring to Fig. 3, a clock recovering device embodying the present invention and which is free from the drawback discussed above is shown. The clock recovering device, generally 10, comprises an edge detector 12 to which received data 13 is applied, a first n-bit binary counter 14 which is supplied with an output 12a of the edge detector 12, a second n-bit binary counter 16 which is also supplied with the output 12a of the edge detector 12, an inverter 18 connected to the first n-bit binary counter 14, a phase comparator 20 to which an output 16a of the second n-bit binary counter 16 is coupled, and a variable frequency divider 22 which received an output 20a of the phase comparator 20 and, in turn, feeds its output 22a to the phase comparator 20. The operation of the clock recovering device 10 will be described with reference to Fig. 4. In the figure, "n" is assumed to be 3. Assume that the width of a logical high or a logical low pulse of the received data 13 is T P , the period of the received data 13 is T O , and the deviation of duty is greater than -50 % and smaller than +50 %. Then, if the data length is 1, the timing of recovered clock is 0.5T P before because T P is equal to or greater than 0.5T O and smaller than 1.5 T O ; if the data length is 2, the timing of recovered clock is 0.5 (T P - T O ) before because T P is equal to or greater than 1.5T O and smaller than 2.5 T O ; if the data length is 3, the timing of recovered clock is 0.5 (T P -2T O ) before because T P is equal to or greater than 2.5T O and smaller than 3. 5T O ; and if the data length is m, the timing of recovered clock is 0. 5 [T P - (m - 1) T O ] before because T P is equal to or greater than (m - 0. 5)T O and smaller than (m + 0.5)T O. Upon transition of the received data 13 from high to or low or vice versa, the edge detector 12 produces a pulse 12a. The first n-bit binary counter 14 counts a high-speed clock 24 which is 2 n times higher than the transmission rate of received data. The counter 14 is reset by each pulse 12a to reach the same count at every period T, so that the count l immediately before resetting is produced by: Since a relation 2 n-1 ≦ l < 2 n - 1 holds under a condition of (m - 0. 5)T O < T P < mT O and a relation 0 ≦ l < 2 n-1 holds under a condition of mT O ≦ T P < (m + 0. 5) T O , the timing of recovered clock is expressed as: As shown in Fig. 3, the "n-1" to "1" bit outputs of the first n-bit binary counter 14 are connected to, respectively, the "n-2" to "0" bit inputs of the second binary counter 16. Further, the "n-1" bits output of the first counter 14 is connected to the "n-1" bit input of the second counter 16 by way of the inverter 18. Assuming that the value read in response to the pulse 12a is K, there holds an equation: Hence, what is stored in the second n-bit binary counter 16 is a time interval between the optimum timing of recovered clock and a transition of received data. Since the second n-bit binary counter 16 continuously counts the high-speed clock 24, its carry 16a coincides in timing with the optimum timing of recovered clock. The carry 16a and the recovered clock 22a are fed to the phase comparator 20 which then decides the phase of the recovered clock 22a and produces a phase correct signal 20a. In response, the variable frequency divider 22 changes the frequency division number to thereby correct the phase of the recovered clock 22a. Referring to Fig. 5, another embodiment of the present invention is shown. This embodiment is essentially the same in construction as the embodiment of Fig. 3 except for the provision of a first and a second N-bit counter 26 and 28 and a ROM 30 which serves as a decoder. By the operation which will be described, the clock recovering device of Fig. 5 recovers a clock in the same manner as the device of Fig. 3, when N is 8. The ROM 30 computes L = 0.5N + 0.5M (where M < 0.5N) and L = 0.5M (where M > 0.5N) based on a count m of the first N-bit counter 26. Turning back to Fig. 4, as the received data 13 changes from high to low or vice-versa, the edge detector 12 produces a pulse 12a. Counting the high-speed clock 24 which is N times higher than the received data transmission rate, the first N-bit counter 26 is reset by each pulse 12a to reach the same count at each period T. Hence, the count M immediately before resetting is produced by: Since M is the count of the N-bit counter, relations M≧ 0.5N and M < 0.5N hold under conditions of (m - 0.5)T O < T P < mT O and mT O < T P (m + 0.5)T O , respectively. Further, there holds an equation: Therefore, the timing of recovered clock is produced by: The "0", "1", ..., "n - 1" bit outputs of the first N-bit counter 26 are fed to, respectively, the "A₀", "A₀", ..., "A n-1 " bits of the ROM 30. The ROM 30 computes L = 0.5M (M≧ 0.5N) and L = 0.5N + 0.5M (M < 0.5N) (data stored in the ROM 30 when N is 8 are shown in Fig. 6), the results appearing on the "O₀", "O₁", ..., "O n-1 " bits. The second N-bit counter 28, therefore, is loaded with a time interval between the optimum timing of recovered clock and a transition of received data. Since the second N-bit counter 28, too, has a period of T O , its carry 28a coincides in timing with the optimum timing of recovered clock. Subsequently, as in the first embodiment, the carry 28a and the recovered clock 22a are applied to the phase comparator 20. In response, the phase comparator 20 decides the phase of the recovered clock 22a and, then, produces a phase correct signal 20a. The variable frequency divider 22 changes the frequency division number by using the phase correct signal 20a, thereby correcting the phase of the recovered clock 22a. In summary, it will be seen that the present invention provides a clock recovering device which accurately recovers a clock if the duty ratio of received data is not greater than ±50 %, because it determines the optimum timing of recovered clock based on the pulse width of received data.

Claims: A clock recovering device comprising: an edge detector means (12) for producing a pulse when received data changes; a first counter means (14,26); a logic means (18,30) for processing an output of said first counter means (14,26); a second counter means (16,28) for receiving an output of said logic means (18,30); characterized in that said first counter means (14,26) counts a high-speed clock which is an integral multiple times higher than a transmission rate of the received data, and is reset by the pulse output by said edge detector means (12); said second counter means (16,28) is reset by the pulse for counting the high-speed clock and by providing a phase comparator means (20) for deciding a phase of recovered clock timed to a carry which is output by said second counter means (16,28); and a variable frequency divider means (22) controlled in frequency division number by an output of said phase comparator means (20) for producing the recovered clock from the high-speed clock. A clock recovering device as claimed in claim 1, wherein said first counter means comprises a first n-bit binary counter (14) for counting a high-speed clock which is 2 n times higher than the transmission rate of the received data, and reset by the pulse. A clock recovering device as claimed in claim 2, wherein said logic means comprises an inverter (18) for inverting an "n - 1" bit output of said first n-bit binary counter (14). A clock recovering device as claimed in claim 3, wherein said second counter means comprises a second n-bit binary counter (16) having an "n - 1" a bit input to which an output of said inverter (18) is connected and an "n - 2" to a "0" bit input to which an "n -1" to a "1 " bit output of said first n-bit binary counter (14) are respectively connected, so as to read data in response to the pulse, and counting the high-speed clock. A clock recovering device as claimed in claim 1, wherein said first counter means comprises a first N-bit counter (26) for counting a high-speed clock which is N times higher than the transmission rate of the received data, and reset by the pulse. A clock recovering device as claimed in claim 5, wherein said logic means comprises a decoder (30) for computing L = 0. 5N + 0.5M (M < 0. 5N) and L = 0. 5M (M > 0. 5N) by using a count M of said first N-bit counter (26). A clock recovering device as claimed in claim 6, wherein said second counter means comprises a second N-bit counter (28) for counting the high-speed clock and set to an initial value L by the pulse.

Inventors: SAEGUSA NOBORU C O NEC CORPORA, SAEGUSA, NOBORU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1987
Main classification: H04L7
IPC codes: H03L7, H03K5, H04L7, G11B20