A FAULT DETECTION SIGNAL TRANSMISSION SYSTEM

Abstract: The fault detection signal transmission system has a trans­ mit terminal and a receive terminal. The transmit terminal comprises a fault detector (14), a multiplex conversion circuit (13) for producing a multiplex signal by multi­ plexing at least a parity check signal with an output signal of the transmit interface circuit to produce a multiplexed signal, a transmit parity check circuit (16) for checking parity of the multiplexed signal, and a parity check signal output circuit (15) responsive to the fault detection signal and an output signal of the trans­ mit parity check circuit for, when the fault detection signal is representative of a fault, producing the parity check signal by inverting a logical state of the output signal of the transmit parity check circuit. The receive terminal comprises a demultiplex conversion circuit (21) for extracting from a received signal the parity check signal, a receive parity check circuit (25) for checking parity of the received signal, and a parity check signal comparison decision circuit (26) for deciding whether or not an apparatus fault exists by comparing the parity check signal extracted by the demultiplex conversion circuit and an output signal of the receive parity check circuit. This system transmits an apparatus fault detection signal without resorting to a particular time slot and, thus, improves the transmission efficiency.

Description: BACKGROUND OF THE INVENTION The present invention relates to a radio digital signal transmission system and, more particularly, to a fault detection signal transmission system in which a transmit terminal sends to a receive terminal a fault detection signal which is representative of a fault in an input stage circuit of the transmit terminal. A conventional fault detection signal transmission system of this kind comprises a transmit terminal and a receive terminal. In a digital signal processing circuit of the transmit terminal, a signal to be transmitted is digitally processed and then multiplexed with a parity check signal and other various kinds of signals including a fault detection signal. The fault detection signal is associated with an input stage circuit of the transmit terminal, i.e., a transmit interface circuit and any circuitry preceding the circuit as will be described hereinafter. The processed and multiplexed signal is modulated and frequency converted by a transmitter and sent to the receive terminal. In the receive terminal, a received signal including the parity check signal and the fault detection signal is frequency converted and demodulated by a receiver, parity checked and demultiplexed by a digital signal processing circuit. Also, an alarm signal is provided based on the demultiplexed fault detection signal. In such a transmission system, some time slots must be assigned to multiplex the fault detection signal as well as the parity check signal. This complicates the transmit terminal and lowers the transmission efficiency as will be more obvious hereinafter. SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a fault detection signal transmission system capable of transmitting an apparatus fault detection signal without resorting to a particular time slot otherwise defined in a transmission frame. This object is solved with the features of the claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which: FIGS. 1A and 1B are schematic block diagrams showing, respectively, a transmit terminal and receive terminal of a fault detection signal transmission system of the present invention. DETAILED DESCRIPTION OF THE INVENTION Referring to FIGS. 1A and 1B, there are shown, respectively, a transmit and a receive terminal of a fault detection signal transmission system of the present invention. A transmit terminal shown in FIG. 1A comprises a transmit (TX) interface circuit 11, a TX synchronous conversion circuit 12, a multiplex circuit 13, a fault detector circuit 14, a parity check signal output circuit 15, a TX parity check circuit 16, a transmitter 17 and an antenna 18. In the transmit terminal, an input signal or interface signal a from an exchange via a multiplexer (not shown) is applied to the TX interface circuit 11 as a signal which is to be transmitted. Having a self-diagnosis function, the TX interface circuit 11 applies its output signal b representative of the result of diagnosis to the fault detector circuit 14. Simultaneously, the TX interface circuit 11 converts the signal a (e.g. bipolar signal) into an NRZ (Non-Return to Zero) signal c which the TX synchronous conversion circuit 12 and multiplex conversion circuit 13 can process. Upon reception of the NRZ signal c , the TX synchronous conversion circuit 12 applies to the NRZ signal synchronous conversion which is necessary for the multiplex conversion circuit 13 to perform multiplexing. Specifically, the major role played by the circuit 12 is to form a time slot which is needed to multiplex a parity signal h and a supplementary signal (channel monitoring signal or order signal) q with the output signal c of the TX interface circuit 11. The synchronous conversion may be implemented with a pulse stuffing system, a rate conversion system and other various techniques which per se are well known in the art. The output signal e of the TX synchronous conversion circuit 12 is routed to the multiplex conversion circuit 3. In response, the circuit 13 inserts the parity check signal h , supplementary signal q and other various kinds of signals in predetermined time slots of the signal e , respectively, to thereby multiplex them while, at the same time, adding a frame synchronizing signal to the signal e . The resulting multiplexed signal f is fed to the transmitter 17 as well as to a TX transmit parity check circuit 16. The TX parity check circuit 16 counts those bits of the multiplexed signal f in which the logical state is a ONE, during a predetermined time interval. Then, the circuit 16 produces a ONE if the number of those bits is even, for example, and a ZERO if it is odd, the output signal g of the circuit 16 being applied to one input terminal of a parity check signal output circuit 15. This circuit 15 may be implemented with an Exclusive-OR (EX-OR) gate by way of example. Applied to the other input terminal of the parity check signal output circuit 15 is a fault detection signal d which is output by the fault detector circuit 14. The fault detection signal d is a ONE when a fault is detected. Specifically, the signal d is set to, for example, a ONE when the output signal a from the exchange and the output signal c of the TX interface circuit 11 are absent or when the output signal b from the TX interface circuit 11 as a result of self-diagnosis is representative of the occurrence of a fault in the circuit 11. Hence, when the fault detection signal d is a ONE due to the occurrence of a fault, the output signal h of the parity check signal output circuit 15 becomes a parity check signal as produced by inverting the logical state of the output signal g of the TX parity check circuit 16. Specifically, while the signal d is a ONE, the signal h becomes a ONE if the signal g is a ZERO (even number) and a ZERO if it is a ONE (odd number). The output signal f is applied to the transmitter 17 which includes a digital modulator (for example, PSK modulator, QAM modulator), a frequency converter and a power amplifier (not shown). The output of the transmitter 17 is sent to the receive terminal shown in FIG. 1B via the antenna 18. The receive terminal of FIG. 1B comprises a demultiplex circuit 21, a receive (RX) synchronous conversion circuit 22, an RX interface circuit 23, a frame synchronization circuit 24, an RX parity check circuit 25, a parity check signal comparison decision circuit 26, an antenna 27 and a receiver 28. In the receive terminal, the signal from the transmit terminal is picked up by the antenna 27 and fed to the receiver 28 including a amplifier, a frequency converter and a demodulator (not shown). The output signal f ′ of the receiver 28 is applied to the demultiplex conversion circuit 21, the frame synchronization circuit 24, and the RX parity check circuit 25. First, the demultiplex conversion circuit 21 separates from the multiplexed signal f ′ an output signal j as well as the parity check signal h , supplementary signal q and others which have been inserted at the transmit terminal, in response to a control signal i which is generated by the frame synchronization circuit 24. The parity check signal h , the output signal or received information signal j , and the supplementary signal q are routed to the parity check signal comparison decision circuit 26, the RX synchronous conversion circuit 22, and a supplementary signal interface circuit (not shown) respectively. The input signal j to the RX synchronous conversion circuit 22 is vacant at the locations which the various signals have occupied due to the operation of the demultiplexer conversion circuit 21, i.e., a signal having a so-called phase gap. The circuit 22, therefore, removes the phase gap from the signal j to apply a smoothed signal n to the RX interface circuit 23. In response, the RX interface circuit 23 produces an output signal p after applying various kinds of processing to the input signal n such as the conversion of the signal format to a one which is feasible for the following devices. Upon reception of the multiplexed signal f ′, the frame synchronization circuit 24 establishes frame synchronization for allowing the receive terminal to detect the signal positions which are necessary for demultiplexing and, based on the result of frame synchronization, delivers the previously mentioned control signal i to the demultiplex conversion circuit 21 and RX parity check circuit 25. In response to the control signal i , the RX parity check circuit 25 performs parity check on the input multiplexed signal f ′ in the manner known in the art and delivers a signal k representative of the result of parity check to the parity check signal comparison decision circuit 26. So long as transmission bit errors are absent, the signal k is identical on content with the output signal g of the TX parity check circuit 16. Implemented with an EX-OR gate, for example, the parity check signal comparison decision circuit 26 compares the parity check signal h from the demultiplex conversion circuit 21 and the above-mentioned parity check signal k with respect to their logical states. If the logical states of the signal h and k are opposite to each other, the circuit 26 turns its output signal m into, for example, a ONE indicating that a fault has occurred. If the two logical states are identical with each other, the circuit 26 turns its output signal m to, in this case, a ZERO indicating that no faults have occurred. The output signal p from the RX interface circuit 23 is applied to an exchange via a demultiplexer (not shown). In summary, paying attention to the parity checking function which is originally assigned to the above-described type of digital signal processing circuit, the present invention causes a transmit terminal to send the signal indicating the presence/absence of an apparatus fault to a receive terminal while relating it to the logical states of a parity check signal, thereby allowing the receive terminal to detect the fault as represented by a parity check error. Specifically, at the transmit terminal, the TX synchronous conversion circuit 12 sends a fault detection signal by inverting the logical state of the parity check signal g , so that a particular time slot heretofore used to transmit a fault detection signal is needless. In addition, the multiplex conversion circuit 13 need not multiplex a fault detection signal as an independent signal. On the other hand, at the receive terminal, the demultiplex conversion circuit 21 does not have to perform the extraction of a fault detection signal particular to a prior art circuit. The RX synchronous conversion circuit 22, too, is freed from the operation of eliminating the phase gap of a particular time slot which would otherwise be assigned to a fault detection signal. Consequently, the amount of signal processing and, therefore, the circuit scale in reduced at both of the transmit and receive terminals.

Claims: A fault detection signal transmission system having a) a transmit terminal (Fig 1A) comprising a fault detector circuit (14) for generating a fault detecting signal by detecting an apparatus fault based on at least an input state of a transmit interface circuit (11); and b) a receive terminal (Fig. 1B) comprising means for detecting said fault detecting signal; characterized in that c) said transmit terminal comprises: c1) a multiplex conversion circuit (13) for producing a multiplex signal by multiplexing at least a parity check signal with an output signal of said transmit interface circuit; c2) a transmit parity check circuit (16) for checking parity of said multiplexed signal; and c3) a parity check signal output circuit (15) responsive to said fault detection signal and an output signal of said transmit parity check circuit (16) for, when said fault detection signal is representative of a fault, producing said parity check signal by inverting a logical state of the output signal of said transmit parity check circuit (16); and d) said receive terminal comprises: d1) a demultiplex conversion circuit (21) for extracting from a received signal said parity check signal which is inserted at said transmit terminal; d2) a receive parity check circuit (25) for checking parity of said received signal; and d3) a parity check signal comparison decision circuit (26) for deciding whether or not an apparatus fault exists by comparing said parity check signal extracted by said demultiplex conversion circuit (21) and an output signal of said receive parity check circuit (25). A system as claimed in claim 1, wherein said parity check signal output circuit (15) comprises an Exclusive-OR gate. A system as claimed in claim 1 or 2, wherein said parity check signal comparison decision circuit (26) comprises an Exclusive-OR gate.

Inventors: FUKUDA, SEIJI C/O NEC CORPORATION, SASAKI, KATSUHIRO C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1987
Main classification: H04J3
IPC codes: H04J3, H04L1