LOGIC CIRCUIT

Abstract: A logic circuit comprises an input section for inputting a signal and outputting an output signal through a CMOS inverter circuit (I₁, I₂); an output section having first darlington-connected bipolar transistors (Q₁₁, Q₁₂) and a bipolar transistor (Q₁₃) to the first bipolar transistors (Q₁₁, Q₁₂) in the shape of a totem pole, and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistors (Q₁₁, Q₁₂); and a control section having CMOS transistors (P₁₃, P₁₄, P₁₅, N₁₃, N₁₄) operated on the basis of the output signal of the input section, and controlling the operations of the first and second bipolar transistors (Q₁₁, Q₁₂) of the output section through the CMOS transistors (P₁₃, P₁₄, P₁₅, N₁₃, N₁₄) in accordance with the output signal of the input section.

Description: The present invention relates to a logic circuit using bipolar transistors and CMOS transistors to reduce cost in electric power and provide drive ability for high load and perform their operations at a high speed. BACKGROUND OF THE INVENTION In a conventional logic circuit, there are various kinds of circuit systems such as the one constituted by bipolar transistors and CMOS transistors. Fig. 1 is a diagram of a NAND gate circuit constituted by bipolar transistors. With respect to a NAND gate shown in Fig. 1, an input stage having two input terminals A and B is constituted by a diode transistor logic having diodes D₁ and D₂ and schottky transistors (call them S transistors in the following description) Q₁ and Q₂ of NPN type, and an output stage has an S transistor Q₃ and a bipolar transistor Q₄ (call it a B transistor in the following description) of NPN type which are darlington-connected to each other, and the output stage also has an S transistor Q₅ connected to the transistors Q₃ and Q₄ in the shape of a totem pole. An output terminal OUT is connected to the connecting point between the B transistor Q₄ and the S transistor Q₅. When the logic gate is constituted by the B transistor, a logic gate having drive ability for high load and operated at a high speed can be provided by a large transfer conductance of the B transistor which is one of the characteristics thereof. In Fig. 1, when both the input terminals A and B are in a high level state in voltage, the S transistor Q₁ is turned on so that an electric path is formed from a voltage source V cc through a resistor R₁, S transistor Q₁ and a resistor R₂ to ground. Further, the S transistor Q₂ is turned on so that an electric current flows along a path from the voltage source V cc through a resistor R₃, S transistor Q₂ to the base terminal of S transistor Q₅. When either one of the input terminals A and B is in a low level state in voltage, e.g., the input terminal A is in the low level state, an electric current flows along a path from the voltage source V cc through a resistor R₄ to a diode D₁. Accordingly, even when the circuit is in the stationary state, the electric current path mentioned above is formed in the circuit so that the power consumption is increased. When the electric current is reduced to decrease the power consumption, the circuit is not operated at a high speed. Therefore, the circuit has been constructed by CMOS transistors to operate the circuit at a high speed and reduce the power consumption. Fig. 2 is a diagram of a NAND gate circuit constituted by CMOS transistors. In the NAND gate circuit, an input stage having two input terminals C and D is constructed by a P channel MOS transistor P₁ (call it PMOS in the following description) and N channel MOS transistors (call it NMOS in the following description) N₁ and N₂ connected in series to each other, and a PMOS transistor P₂, an NMOS transistor N₃ and an NMOS transistor N₄ which are connected in series to each other and connected in parallel to PMOS transistor P₁, NMOS transistor N₁ and NMOS transistor N₂. An output stage of the NAND gate circuit is constructed by an inverter circuit composed of a PMOS transistor P₃ and an NMOS transistor N₅, and an inverter circuit composed of a PMOS transistor P₄ and an NMOS transistor N₆ and cascade-connected to the former inverter circuit. An input protecting circuit constituted by diodes D₃ and D₄ of PN junction and a resistor R₅, and diodes D₅ and D₆ of PN junction and a resistor R₆ is connected to the respective input terminals C and D. When the logic circuit is constructed by the CMOS transistors as mentioned above, the current drive ability is reduced and it is difficult to operate the circuit at a high speed since the transfer conductance of MOS transistor is smaller than that of bipolar transistor. Accordingly, the output stage of the logic circuit is constructed by inverter circuits having the increased sizes of transistors and cascade-connected to each other. However, in such a logic circuit constructed as above, an output signal is delayed by a transfer delay time t pd of the inverter circuits cascade-connected to each other. Further, when the sizes of the transistors at the output stage are increased, the circuit is increased in size, which is disadvantageous to especially provide a compact circuit by integration. Further, when the sizes of the transistors at the output stage are increased, the ON resistances of the transistors are reduced. Accordingly, when an output signal is overshot or undershot, the ON resistances of the transistors cannot absorb the overshoot or undershoot of the output signal in a resonant circuit formed by an inductance component of a wiring connected to an output terminal OUT and a capacity component of a load, thereby generating ringing and causing an error in operation in the worst case. Therefore, the input protecting circuit by diodes of PN junction and resistor is connected to the input terminals C and D, and is efficient with respect to surge noise. However, it is difficult to sufficiently restrict the ringing since the voltage drop V F in the forward direction of the diodes of PN junction is about 0.7 volt. As mentioned above, when the logic gate is constructed by bipolar transistors, the load-drive ability and the speed in operation are improved, but the power consumption is increased, and the speed in operation is reduced when the power consumption is reduced. When the logic gate is constructed by only CMOS transistors, the power consumption can be reduced but the load-drive ability is reduced and it is difficult to operate the circuit at a high speed. When the sizes of the transistors at the output stage are increased to improve the load-drive ability, the structure of the circuit is increased in size and it is difficult to sufficiently restrict the ringing. Therefore, in such constructions, it is difficult to reduce power consumption and improve load-drive ability and speed in operation and restrict ringing. EP-A-0 23 97 62, published on 07.10.87 and having the date of priority of 31.03.86, describes a buffer circuit comprising first to third CMOS inverters whose input terminals are mutually connected, first and second npn transistors whose bases are commonly connected to an output terminal of the first CMOS inverter and whose emitters are respectively connected to output terminals of the second and third CMOS inverters fourth and fifth CMOS inverters for inverting the output signals of the first and third CMOS inverters, a third npn transistor whose base and emitter are respectively connected to output terminals of the fourth and fifth CMOS inverters, fourth and fifth npn transistors whose conduction states are controlled by the output signals of the first and fourth CMOS inverters, first and second n-channel MOS transistors which are serially connected to the fourth and fifth npn transistors respectively and whose gates are respectively connected to the third and fifth CMOS inverters and third and fourth n-channel MOS transistors which are respectively connected between the gates of the first and second n-channel MOS transistors and a reference voltage terminal and whose gates are respectively connected to the fourth and first CMOS inverters. JP-A-60-21 77 26 describes a logic circuit with an inverter circuit as input and a darlington pair as output. A phase split circuit is connected between the output of the inverter and the inputs of the darlington pair. The darlington pair is connected to a further bipolar transistor in totem pole form. The phase split circuit consists of a single bipolar transistor. A logic circuit is also described having a plurality of inputs each connected to an individual inverter, the outputs of these inverters being supplied to a single inverter. The phase split circuit and output circuit are identical to that described above. SUMMARY OF THE INVENTION To solve the problems mentioned above, an object of the present invention is to provide a logic circuit for reducing power consumption and improving load-drive ability and speed in operation and restricting ringing. With the above object in view, the present invention resides in a logic circuit comprising: first input means including a first CMOS inverter circuit connected between a high voltage source and a low voltage source for inputting a first signal and outputting a first output signal through said first CMOS inverter circuit; second input means including a second CMOS inverter connected between the high voltage source and the low voltage source for inputting a second signal and outputting a second output signal through said second CMOS inverter circuit; and output means connected between the high and low voltage sources and having a first darlington-connected bipolar transistor means and a second bipolar transistor in the shape of a totem pole and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistor means, the base terminal of the second bipolar transistor means being connected to the low voltage source through a third bipolar transistor; characterized by control means having two pairs of complementary first and second MOS transistors of first and second conductivity types operated on the basis of the first and second output signal of the first and second CMOS inverter circuits, the first and second transistors of the first conductivity type being connected in series between the high voltage source and the base terminal of the third bipolar transistor, the first and second transistors of the second conductivity type being connected in parallel between the base terminal of the second bipolar transistor and the gate terminal of the third MOS transistor and connected to the high voltage source through a resistance means, the gate terminal of the third MOS transistor being connected to the input terminal of the first darlington-connected bipolar transistor means. The object of the invention is also solved by a buffer circuit comprising: input means including a CMOS inverter circuit connected between a high voltage source and a low voltage source for inputting a signal and outputting an output signal through said CMOS inverter circuit; output means connected between said high and low voltage sources and having a first darlington-connected bipolar transistor means and a second bipolar transistor means in the shape of a totem pole and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistor means and a third bipolar transistor means connected between the low voltage source and the base terminal of the second bipolar transistor means; characterized by control means having complementary first and second MOS transistor means operated on the basis of the output signal of said CMOS inverter circuit, one of the source and drain terminals of the first MOS transistor means being connected to the base terminal of the second bipolar transistor means, the base terminal of the third bipolar transistor means being connected to one of the source and drain terminals of the second MOS transistor means, a third MOS transistor means connected between the high voltage source and the other of the source and drain terminals of the second MOS transistor means, the gate terminal of the third MOS transistor being connected to the input terminal of the first darlington-connected bipolar transistor means and the other of the source and drain terminals of the first MOS transistor means. The object of the invention is also solved by a buffer circuit comprising: first input means including a first CMOS inverter connected between a high voltage source and a low voltage source for inputting a first signal and outputting a first output signal through said first CMOS inverter circuit; second input means including a second CMOS inverter connected between the high voltage source and the low voltage source for inputting a second signal and outputting a second output signal through said second CMOS inverter circuit; output means connected between the high and low voltage sources and having a first darlington-connected bipolar transistor means and a second bipolar transistor means in the shape of a totem pole and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistor means, the base terminal of the second bipolar transistor means being connected to the low voltage source through a third bipolar transistor; characterized by control means comprising a series connection of first MOS transistor means of a first conductivity type and a parallel connection of second MOS transistor means of a second conductivity type opposite to the first conductivity type operated on the basis of the first and second output signal of the first and second CMOS inverter circuits, one terminal of the parallel connection being connected to the high voltage source through a third MOS transistor means, the other terminal of the parallel connection being connected to the base terminal of the third bipolar transistor means, one terminal of the series connection being connected to the input terminal of the darlington-connected bipolar transistor means and the gate terminal of the third MOS transistor means, the other terminal of the series connection being connected to the base terminal of the second bipolar transistor means. In the logic circuit of the present invention, the operations of the bipolar transistors connected to each other in the shape of the totem pole and constituting the output section are controlled by the control section having the CMOS transistors. The base charge of one of the bipolar transistors is discharged through the transistors constituting the control section, thereby reducing a through electric current flowing through the output section and reducing power consumption and performing logic operation with respect to the input signal. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more apparent from the following preferred embodiments thereof in conjunction with the accompanying drawings in which: Fig. 1 is a diagram of a conventional logic circuit constituted by bipolar transistors; Fig. 2 is a diagram of another conventional logic circuit constituted by CMOS transistors; Fig. 3 is a diagram showing the construction of a logic circuit according to a first embodiment of the present invention; Fig. 4 is a view showing waveforms of signals in operation of the logic circuit of Fig. 3; Fig. 5 is a diagram showing the construction of a logic circuit according to a second embodiment of the present invention; Fig. 6 is a diagram showing the construction of a logic circuit according to a third embodiment of the present invention; and Fig. 7 is a diagram showing the construction of a logic circuit according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Fig. 3 is a diagram showing the construction of a logic circuit in according with a first embodiment of the present invention. In Fig. 3, the logic circuit is constituted by a mixture of bipolar transistors and CMOS transistors, and comprises an input section I, a control section II having CMOS transistors, and an output section III composed of bipolar transistors, constituting an AND gate or NOR gate having two input terminals A and B. In Fig. 3, the input section I has inverter circuits I₁ and I₂ composed of PMOS and NMOS transistors. The input terminal A is connected to an input of the inverter circuit I₁ through an input protecting circuit composed of a schottky diode (call it an S diode in the following description) D₁₁ and a resistor R₁₁. The input terminal B is connected to an input of the inverter circuit I₂ through an input protecting circuit composed of an S diode D₁₂ and a resistor R₁₂. The control section II controls the operation of the output section described later, and comprises a switching circuit 1 for operating the logic gate shown in Fig. 3 as an AND gate or NOR gate, PMOS transistors P₁₃, P₁₄ and P₁₅ connected in series to each other, NMOS transistors N₁₄ and N₁₅ connected in parallel to each other, and an S transistor Q₁₄ and a resistor R₁₄. When the logic gate is operated by the switching circuit 1 as AND gate, an input terminal a and an output terminal b, and an input terminal c and an output terminal d are respectively short-circuited therebetween. When the logic gate is operated by the switching circuit 2 as NOR gate, inverter circuits are respectively inserted between the input and output terminals a and b, and the input and output terminals c and d. The gate terminals of the PMOS transistor P₁₅ and the NMOS transistor N₁₃ are connected to an output of the inverter circuit I₂ through the switching circuit 1. The gate terminals of the PMOS transistor P₁₄ and the NMOS transistor N₁₄ are connected to an output of the inverter circuit I₁ through the switching circuit 1. The gate terminal of the PMOS transistor P₁₃ is connected to the drain terminals of the NMOS transistors N₁₃ and N₁₄. The S transistor Q₁₄ is disposed to discharge the base charge of the S transistor Q₁₃ constituting the output section III described later, and is inserted between ground and the source terminals of the NMOS transistors N₁₃ and N₁₄. The base terminal of the S transistor Q₁₄ is connected to the drain terminal of the PMOS transistor P₁₅ and is connected to ground through a resistor R₁₄. The output section III has an S transistor Q₁₁ and a B transistor Q₁₂ darlington-connected to each other, and an S transistor Q₁₃ connected to the transistors Q₁₁ and Q₁₂ in the shape of a totem pole. An output terminal OUT is connected to the connection point between the B transistor Q₁₂ and the S transistor Q₁₃. The base terminal of the S transistor Q₁₁ is connected to a voltage source V cc through a resistor R₁₃, and is connected to the drain terminals of the NMOS transistors N₁₃ and N₁₄. The base terminal of the S transistor Q₁₂ is connected to the base terminal of the S transistor Q₁₁ through an S diode D₁₃. The base terminal of the S transistor Q₁₃ is connected to the source terminals of the NMOS transistors N₁₃ and N₁₄. The operation of the logic circuit in the first embodiment of the present invention mentioned above will now be described with reference to Fig. 4 showing waveforms of signals in Fig. 3. In the following description, the input and output terminals a and b, and the input and output terminals c and d are respectively short-circuited in the switching circuit 1, and the logic gate in Fig. 3 is operated as AND gate. When the input terminal A is in a high level state in voltage, an output of the inverter circuit I₁ becomes in a low level state in voltage, and the PMOS transistor P₁₄ is turned on, and the NMOS transistor N₁₄ is turned off, and the potential of the output terminal OUT in this state is changed as follows. Namely, in such a state, when the input terminal B is in the low level state, an input of the inverter circuit I₂, i.e., the potential at point D is in the high level state, and the NMOS transistor N₁₃ is turned on. Accordingly, the S transistor Q₁₁ and the B transistor Q₁₂ are turned off, and the S transistor Q₁₃ is turned on and its output is in the low level state. When the input terminal B is changed from the low level to the high level, the potential at point D begins to be decreased from the high level to the low level. The PMOS transistor P₁₅ is turned on when the potential at point D becomes less than a potential which is the source potential V S15 of the PMOS transistor P₁₅ minus a threshold voltage V T15 of the PMOS transistor P₁₅. Thus, an electric current is supplied from a voltage source V cc to the base terminal of the S transistor Q₁₄ through the PMOS transistors P₁₃, P₁₄ and P₁₅ so that the S transistor Q₁₄ is turned on. Accordingly, the base charge of the S transistor Q₁₃ is discharged to ground through the S transistor Q₁₄ so that the S transistor Q₁₃ is rapidly turned off. When the S transistor Q₁₄ is turned on, an electric current flows along a path from the resistor R₁₃ through the NMOS transistor N₁₃ to the S transistor Q₁₄. The time at which the S transistor Q₁₄ is turned on is delayed by making the electric current, which begins to be supplied to the base terminal of the S transistor Q₁₄, to flow through the resistor R₁₄, thereby reducing a through electric current flowing through the transistors Q₁₂ and Q₁₃. The NMOS transistor N₁₃ is turned on until the potential at point D is further reduced and has become a voltage which is a voltage V BE13 between the base and emitter of the S transistor Q₁₃ plus a threshold voltage V T13 of the NMOS transistor N₁₃, but the drain current of the NMOS transistor N₁₃ begins to be gradually reduced since the voltage between the gate and source thereof is reduced. When the potential at point D has reached the voltage (V BE13 + V T13 ), the NMOS transistor N₁₃ is turned off. The potential at point C is increased in accordance with a time constant between the resistor R₁₃, the drains of the NMOS transistors N₁₃ and N₁₄, and the parasitic capacities in the S diodes D₁₃ and D₁₄. When the potential at point C is increased, the S transistor Q₁₁ is turned on so that the B transistor Q₁₂ is turned on and the output terminal OUT is changed from the low level state to the high level state. When the potential at point C is further increased and has become greater than voltage V cc - V T13 which is the threshold voltage of the PMOS transistor P₁₃, the PMOS transistor P₁₃ is turned off. Thus, the electric current is not supplied to the base terminal of the S transistor Q₁₄, and the charge accumulated in this base terminal is discharged to ground through the resistor R₁₄ so that the S transistor Q₁₄ is turned off. Accordingly, when the output terminal OUT is changed from the low level state to the high level state, the base charge of the S transistor Q₁₃ is discharged to ground through the S transistor Q₁₄, thereby reducing the through electric current flowing from the voltage source V cc through the B transistor Q₁₂ and the S transistor Q₁₃ to ground. In such a state, when the input terminal B is changed to the low level state, the potential at point D begins to be increased from the low level to the high level so that the NMOS transistor N₁₃ is turned on and an electric current begins to flow through the NMOS transistor N₁₃. Thus, when the potential at point C begins to be decreased and has become less than the threshold voltage V cc - V T13 of the PMOS transistor P₁₃, the PMOS transistor P₁₃ is turned on, and all of the PMOS transistors P₁₃, P₁₄ and P₁₅ are temporarily turned on. However, the potential at point D is increased and the PMOS transistor P₁₅ is immediately thereafter turned off so that all of the PMOS transistors P₁₃, P₁₄ and P₁₅ are turned on for a very short time. The electric current, which is the voltage V BE between the base and emitter of the S transistor Q₁₄ divided by the resistance R of the resistor R₁₄, in the electric current flowing through the base terminal of the S transistor Q₁₄ is absorbed by the resistor R₁₄. Accordingly, the S transistor Q₁₄ is held to be turned off. Accordingly, an electric current is supplied to the base terminal of the S transistor Q₁₃ from the voltage source V cc through the resistor R₁₃ and the NMOS transistor N₁₃. Further, the base charge of the B transistor Q₁₂ is supplied through the S diode D₁₃ and the charge of the output terminal OUT is supplied through the S diode D₁₄. Thus, the S transistor Q₁₃ is turned on and the S transistor Q₁₁ and the B transistor Q₁₂ are turned off, and the output terminal OUT is changed from the high level state to the low level state. The same results as above can be provided even when the input terminal B is in the high level state and the state of the input terminal A is changed, and can be provided even when inverter circuits are inserted between the input and output terminals a and b, and between the input and output terminals c and d of the switching circuit 1. Although the bipolar transistors are used in the above logic circuit, the electric current in the active and normal states in the circuit is greatly reduced, and the power consumption can be approximately reduced to the one in a circuit constructed by only CMOS transistors. Further, since the output stage is constructed by the bipolar transistors, the high load drive ability can be obtained and the speed in operation can become high. Further, the ON resistance of the bipolar transistors at the output stage can restrict the ringing since the electric current-voltage characteristics thereof are not linear ones and the ON resistance is greater than that of CMOS transistor having a similar drive ability. Further, the input protecting circuit in the logic circuit of the present invention is constituted by the S diode which is fast in response and which has a small voltage drop in the forward direction in comparison with diode of PN junction. Therefore, the ringing, which tends to be generated when the wiring connected to the input terminal is long, can be restricted in comparison with an input protecting circuit using diode of PN junction. In the construction of the logic circuit shown in Fig. 3, both the PMOS transistors P₁₄ and P₁₅ are changed to be turned on in accordance with input change in the following two cases. (1) When the output terminal d of the switching circuit 1 is in the low level state and the PMOS transistor P₁₄ is turned on, the output terminal b of the switching circuit 1 is changed from the high level state to the low level state and the PMOS transistor P₁₅ is changed from the turning-off state to the turning-on state. (2) When the output terminal b of the switching circuit 1 is in the low level state and the PMOS transistor P₁₅ is turned on, the output terminal d of the switching circuit 1 is changed from the high level state to the low level state and the PMOS transistor P₁₄ is changed from the turning-off state to the turning-on state. In item (1), since the PMOS transistor P₁₄ is turned on, the voltage V DS between the source and drain of the PMOS transistor P₁₄ is 0 volt. Further, since the NMOS transistor N₁₃ is turned on and the PMOS transistor P₁₃ is turned on, the potential of the source of the PMOS transistor P₁₅ is equal to the potential of the voltage source V cc . Accordingly, when the potential of the gate of the PMOS transistor P₁₅ is changed from the high level state to the low level state, the PMOS transistor P₁₅ is rapidly turned on, thereby rapidly performing the switching operation from the turning-off state to the turning-on state. In item (2), since the PMOS transistor P₁₄ is turned off, the potential of the source of the PMOS transistor P₁₅ is equal to the threshold potential of the PMOS transistor P₁₅ so that the PMOS transistor P₁₅ is in the cutoff state. Accordingly, when the potential of the gate of the PMOS transistor P₁₄ is changed from the high level state to the low level state, the potential of the source of the PMOS transistor P₁₅ is increased and the voltage V GS between the gate and source of the PMOS transistor P₁₅ is increased after the PMOS transistor P₁₄ has been turned on. Accordingly, with respect to the input change in item (2), the PMOS transistor P₁₅ is turned on after the PMOS transistor P₁₄ has been turned on, and the switching operation from the turning-off state to the turning-on state is slightly delayed in comparison with the case of item (1), thereby generating differences with respect to the response characteristics of the logic circuit at the time of the high level output. Fig. 5 shows a second embodiment of the present invention constructed such that the response characteristics mentioned above become the same. Fig. 5 is a diagram showing the construction of a logic circuit in accordance with the second embodiment of the present invention in which the PMOS transistors P₁₄ and P₁₅ shown in Fig. 3 are replaced by a same threshold circuit 3 enclosed by a dotted line of Fig. 5 in which the threshold values are same. The other construction of Fig. 5 is similar to the construction of the logic circuit shown in Fig. 3, and therefore the same reference numerals in Fig. 5 are the same or corresponding portions in Fig. 3. In Fig. 5, the same threshold circuit 3 is constituted by four PMOS transistors P₁₆, P₁₇, P₁₈ and P₁₉. The PMOS transistors P₁₆ and P₁₇ are connected in series to each other between the drain terminal of the PMOS transistor P₁₃ and the base terminal of the S transistor Q₁₄. The gate terminal of the PMOS transistor P₁₆ is connected to the output terminal b of the switching circuit 1, and the gate terminal of the PMOS transistor P₁₇ is connected to the output terminal d of the switching circuit 1. The PMOS transistors P₁₈ and P₁₉ are connected in parallel to the PMOS transistors P₁₆ and P₁₇ connected in series to each other, and are connected in series to each other between the drain terminal of the PMOS transistor P₁₃ and the base terminal of the S transistor Q₁₄. The gate terminal of the PMOS transistor P₁₈ is connected to the output terminal d of the switching circuit 1, and the gate terminal of the PMOS transistor P₁₉ is connected to the output terminal b of the switching circuit 1. The operation of the same threshold circuit 3 constructed as above will now be described when the PMOS transistors P₁₆ and P₁₇, and the PMOS transistors P₁₈ and P₁₉ connected in series to each other are respectively turned on. In this case, in the switching circuit 1, the input and output terminals a and b, and the input and output terminals c and d are respectively short-circuited to operate the logic circuit as AND gate. First, the input terminal A is in the high level state, and the input terminal B is in the low level state. The operation of the logic circuit will be described in these states when the input terminal B is changed from the low level state to the high level state. When the input terminal A is in the high level state and the input terminal B is in the low level state, the output terminal b of the switching circuit 1 is in the high level state and the output terminal d thereof is in the low level state, and the PMOS transistors P₁₆ and P₁₉ are turned off, and the PMOS transistors P₁₇ and P₁₈ are turned on. Accordingly, the potential of the source of the PMOS transistor P₁₇ is equal to the threshold voltage of the PMOS transistor P₁₇, and the potential of the source of the PMOS transistor P₁₉ is equal to the potential of the voltage source. In such a state, when the input terminal B becomes in the high level state, the output terminal b of the switching circuit 1 is changed from the high level state to the low level state, and the PMOS transistors P₁₆ and P₁₉ are changed from the turning-off state to the turning-on state. At this time, since the potential of the source of the PMOS transistor P₁₉ is equal to the potential of the voltage source, the PMOS transistors P₁₈ and P₁₉ are turned on before the PMOS transistor P₁₆ is changed from the turning-off state to the turning-on state and both the PMOS transistors P₁₆ and P₁₇ are turned on. Therefore, the electric current flowing out of the voltage source V cc through the PMOS transistor P₁₃ is supplied to the base terminal of the S transistor Q₁₄ through the PMOS transistors P₁₈ and P₁₉ immediately after the output terminal b of the switching circuit 1 is changed from the high level state to the low level state. Next, the input terminal A is in the low level state, and the input terminal B is in the high level state, and the operation of the logic circuit will be described in these states when the input terminal A is changed from the low level state to the high level state. When the input terminal A is in the low level state and the input terminal B is in the high level state, the output terminal b of the switching circuit 1 is in the low level state and the output terminal d thereof is in the high level state, and the PMOS transistors P₁₆ and P₁₉ are turned on, and the PMOS transistors P₁₇ and P₁₈ are turned off. Accordingly, the potential of the source of the PMOS transistor P₁₉ is equal to the threshold potential of the PMOS transistor P₁₉. In such a state, when the input terminal A is changed from the low level state to the high level state, the output terminal d of the switching circuit 1 is changed from the high level state to the low level state, and the PMOS transistors P₁₇ and P₁₈ are changed from the turning-off state to the turning-on state. At this time, since the potential of the source of the PMOS transistor P₁₇ is equal to the potential of the voltage source, the PMOS transistors P₁₆ and P₁₇ are turned on before the PMOS transistor P₁₈ is changed from the turning-off state to the turning-on state, and both the PMOS transistors P₁₈ and P₁₉ are turned on. Therefore, the electric current flowing out of the voltage source V cc through the PMOS transistor P₁₃ is supplied to the base terminal of the S transistor Q₁₄ through the PMOS transistors P₁₆ and P₁₇ immediately after the output terminal d of the switching circuit 1 is changed from the high level state to the low level state. As mentioned above, there are the first case in which both the input terminals A and B are changed to the high level state by changing the input terminal A from the low level state to the high level state, and the second case in which both the input terminals A and B are changed to the high level state by changing the input terminal B from the low level state to the high level state. The PMOS transistors changing from the turning-off state to the turning-on state in the same threshold circuit 3 are different from each other with respect to the first and second cases, but the same threshold circuit 3 is symmetrically constructed with respect to the output terminals b and d of the switching circuit 1. Accordingly, the same threshold circuit 3 is similarly operated in the first and second cases in that the electric current is supplied to the base terminal of the S transistor Q₁₄ from the voltage source V cc . Accordingly, the logic circuit in the second embodiment has the effects similar to the ones of the first embodiment, and the responsive speed of the same threshold circuit 3 can be same irrespective of change of the input level, and the responsive characteristics of the logic circuit at the time of the high level output can be same. The similar effects can be obtained even when inverter circuits are respectively connected between the input and output terminals a and b, and between the input and output terminals c and c of the switching circuit 1, and the logic circuit is operated as NOR gate. Fig. 6 is a diagram showing the construction of a logic circuit in accordance with a third embodiment of the present invention. In Fig. 3, the drain terminal of the PMOS transistor P₁₃ and the base terminal of the S transistor Q₁₄ are connected to each other through the PMOS transistors P₁₄ and P₁₅ connected in series to each other. In contrast to Fig. 3, in the logic circuit of Fig. 6, the drain terminal of the PMOS transistor P₁₃ and the base terminal of the S transistor Q₁₄ are connected to each other through PMOS transistors P₂₁ and P₂₂ connected in parallel to each other. The gate terminal of the PMOS transistor P₂₁ is connected to the output terminal b of the switching circuit 1, and the gate terminal of the PMOS transistor P₂₂ is connected to the output terminal d of the switching circuit 1. Accordingly, the logic circuit is operated as OR gate by the switching circuit 1 in which the input and output terminals a and b, and the input and output terminals c and d are respectively short-circuited, and the logic circuit is operated as NAND gate by the switching circuit 1 in which inverter circuits are respectively inserted between the input and output terminals a and b, and between the input and output terminals c and d of the switching circuit 1. Further, in Fig. 3, the base terminals of the respective S transistors Q₁₁ and Q₁₃ are connected to each other through the NMOS transistors N₁₃ and N₁₄ connected in parallel to each other. In contrast to Fig. 3, in the logic circuit of Fig. 6, NMOS transistors N₂₁ and N₂₂ connected in series to each other, and NMOS transistors N₂₃ and N₂₄ connected in series to each other are connected in parallel to each other between the base terminals of the respective S transistors Q₁₁ and Q₁₃. The gate terminals of the NMOS transistors N₂₁ and N₂₄ are connected to the output terminal b of the switching circuit 1, and the gate terminals of the NMOS transistors N₂₂ and N₂₃ are connected to the output terminal d of the switching circuit 1. According to such a construction, the switching operation of the S transistor Q₁₃ is not changed irrespective of the output change of the switching circuit 1. In the construction of the logic circuit constructed above, the same effects as the ones in the first embodiment can be obtained even when the logic circuit of Fig. 6 is operated as OR gate or NAND gate, and the responsive characteristics of the logic circuit can be the same with respect to the output change of the switch circuit 1. Fig. 7 is a diagram showing the construction of a logic circuit in accordance with a fourth embodiment of the present invention. In contrast to Fig. 3, the logic circuit of Fig. 7 is operated as buffer circuit by constituting the input section I by one inverter circuit I₃, and by short-circuiting input and output terminals a and b of a switching circuit 2 therebetween, and is operated as inverter circuit by inserting an inverter circuit between the input and output terminals a and b. The switching operation of an output signal is similar to the one in Fig. 3. According to the construction of the logic circuit mentioned above, the effects similar to the ones in the first embodiment of Fig. 3 can be obtained even in a buffer circuit or an inverter circuit. In the logic circuits in the first to fourth embodiments of the present invention, the inverter circuits I₁, I₂ and I₃ receiving an input signal are constituted by CMOS transistors, and the level of the input signal is equal to the levels of the CMOS transistors. However, the input signal at transistor-transistor logic level can be also used by setting the threshold voltage of PMOS transistors constituting the inverter circuits I₁, I₂ and I₃ higher than the normal voltage such as about 0.8 volt. As mentioned above, according to the present invention, the operation of bipolar transistors constituting an output section and connected to each other in the shape of a totem pole is controlled by a control section having CMOS transistors, and the base charge of one of the bipolar transistors is discharged through a transistor constituting the control section when the bipolar transistors are switched, thereby reducing a through electric current flowing through the output section. Accordingly, in the logic circuit of the present invention, power consumption can be reduced, and high load drive ability can be obtained, and the operation can be performed at a high speed. Further, since the output section is constituted by using the bipolar transistors, the ringing generated in an output terminal can be sufficiently restricted.

Claims: A buffer circuit comprising: input means including a CMOS inverter circuit (I₃) connected between a high voltage source and a low voltage source for inputting a signal and outputting an output signal through said CMOS inverter circuit (I₃); output means connected between said high and low voltage sources and having a first darlington-connected bipolar transistor means and a second bipolar transistor means in the shape of a totem pole and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistor means and a third bipolar transistor means connected between the low voltage source and the base terminal of the second bipolar transistor means; characterized by control means having complementary first and second MOS transistor means operated on the basis of the output signal of said CMOS inverter circuit (I₃), one of the source and drain terminals of the first MOS transistor means being connected to the base terminal of the second bipolar transistor means, the base terminal of the third bipolar transistor means being connected to one of the source and drain terminals of the second MOS transistor means, a third MOS transistor means connected between the high voltage source and the other of the source and drain terminals of the second MOS transistor means, the gate terminal of the third MOS transistor being connected to the input terminal of the first darlington-connected bipolar transistor means and the other of the source and drain terminals of the first MOS transistor means. A buffer circuit as claimed in claim 1, wherein said CMOS inverter circuit (I₃) of the input means is connected to an input protecting circuit using a schottky diode. A logic circuit comprising: first input means including a first CMOS inverter circuit (I₁) connected between a high voltage source and a low voltage source for inputting a first signal and outputting a first output signal through said first CMOS inverter circuit (I₁); second input means including a second CMOS inverter (I₂) connected between the high voltage source and the low voltage source for inputting a second signal and outputting a second output signal through said second CMOS inverter circuit (I₂); and output means connected between the high and low voltage sources and having a first darlington-connected bipolar transistor means (Q₁₁,Q₁₂) and a second bipolar transistor (Q₁₃) in the shape of a totem pole and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistor means (Q₁₁,Q₁₂;Q₁₃), the base terminal of the second bipolar transistor means (Q₁₃) being connected to the low voltage source through a third bipolar transistor (Q₁₄); characterized by control means having two pairs of complementary first and second MOS transistors of first and second conductivity types (P₁₄, P₁₅, N₁₃, N₁₄) operated on the basis of the first and second output signal of the first and second CMOS inverter circuits (I₁ and I₂), the first and second MOS transistors and a third MOS transistor of the first conductivity type (P₁₄ and P₁₅, P₁₃) being connected in series between the high voltage source and the base terminal of the third bipolar transistor (Q14), the first and second transistors of the second conductivity type (N₁₃ and N₁₄) being connected in parallel between the base terminal of the second bipolar transistor (Q₁₃)and the gate terminal of the third MOS transistor (P₁₃) and connected to the high voltage source through a resistance means (R₁₃), the gate terminal of the third MOS transistor (P₁₃) being connected to the input terminal of the first darlington-connected bipolar transistor means (Q₁₁,Q₁₂). A logic circuit as claimed in claim 3, wherein said CMOS inverter circuit (I₁;I₂) of the first and second input means is connected to an input protecting circuit using a schottky diode (D₁₁;D₁₂). A logic circuit as claimed in claim 4, wherein the first and second MOS transistors (P₁₄,P₁₅) of the first conductivity type are replaced by fourth and fifth transistor means connected in parallel to each other, each transistor means being respectively composed of two transistors (P₁₆,P₁₇; P₁₈,P₁₉) of the first conductivity type connected in series to each other. A buffer circuit comprising: first input means including a first CMOS inverter connected between a high voltage source and a low voltage source for inputting a first signal and outputting a first output signal through said first CMOS inverter circuit; second input means including a second CMOS inverter connected between the high voltage source and the low voltage source for inputting a second signal and outputting a second output signal through said second CMOS inverter circuit; output means connected between the high and low voltage sources and having a first darlington-connected bipolar transistor means (Q₁₁,Q₁₂) and a second bipolar transistor means (Q₁₃) in the shape of a totem pole and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistor means, the base terminal of the second bipolar transistor means (Q₁₃) being connected to the low voltage source through a third bipolar transistor (Q₁₄); characterized by control means comprising a series connection of first MOS transistor means of a first conductivity type (N₂₁ and N₂₂) and a parallel connection of second MOS transistor means of a second conductivity type opposite to the first conductivity type (P₂₁ and P₂₂) operated on the basis of the first and second output signal of the first and second CMOS inverter circuits, one terminal of the parallel connection being connected to the high voltage source through a third MOS transistor means (P₁₃), the other terminal of the parallel connection being connected to the base terminal of the third bipolar transistor means (Q₁₄), one terminal of the series connection being connected to the input terminal of the darlington-connected bipolar transistor means (Q₁₁ and Q₁₂) and the gate terminal of the third MOS transistor means (P₁₃), the other terminal of the series connection being connected to the base terminal of the second bipolar transistor means (Q₁₃).

Inventors: UENO, MASAJI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: H03K19
IPC codes: H03K19