METHOD AND APPARATUS FOR MULTI-GRADATION DISPLAY

Abstract: In a multi-gradation display method and apparatus by which a display signal formed by a picture element signal of any one of the levels of N gradations (where N is an integer equal to or greater than 3) is displayed on a display panel (54) in which each picture element produces a two-gradation display, one frame is composed of (N - l) fields, and accordingly each picture element is supplied with a binary signal (N - l) times for each frame, and the binary signal is given one of its values by a number of times corresponding to the level value of the input picture element signal and the other value by the remaining number of times.

Description: The present invention relates to a method and an apparatus which enable a multi-gradation display with three or more gradations through use of, for example, a liquid crystal display panel in which each picture element is capable of producing a display with only two gradations. For providing a multi-gradation display on a liquid crystal display, it is customary in the prior art to employ an arrangement in which an analog picture element signal is supplied from the source side of a thin film transistor to each picture element electrode (a drain electrode) for driving it. The liquid crystal display is usually what is called a row scan type in which picture element electrodes are arranged in a matrix form and are driven row by row for display. In order to display an analog display signal such as a TV signal on the row scan type display, it is necessary to hold each picture element signal in an analog sample hold circuit for each horizontal scanning line of the input TV signal. On the other hand, a binary (two-gradation) image signal can be displayed on the row scan type display by the employment of a simple arrangement in which the binary image signals of one horizontal scanning line are applied in serial to a shift register and the contents of respective stages of the shift register are provided in parallel for simultaneously driving respective column drive lines of the display (source buses in the case of the liquid crystal display). Accordingly, the signal processing is digital, and hence is very simple. In the past, however, there have not been provided any method and apparatus by which multi-gradation image signals are displayed with three or more gradations on the two-gradation display panel through digital processing. US-A-4559535 describes a display panel plurality of memory sections is provided each storing binary data to be employed for refreshing picture elements of a thin-film EL matrix display panel on successive frame time periods constituting an integration time period. The number of frame time periods in an integration time period corresponds to the number of different shades to be displayed on the panel. Each of the memory sections is binarily weighted and, during an integration time period, each memory section is read out a number of frame time periods corresponding to its binary weight in order to obtain different brightness levels or shades on the panel. Thus, some of the picture elements on the panel are refreshed more than others during the integration time period. Accordingly, the eye of the viewer receives more light from some picture elements than others during each integration time period which results in the relative brightness levels and, therefore, the shades of the picture elements to vary. It is, therefore, an object of the present invention to provide a method and an apparatus which permit a multi-gradation display through digital processing i.e., through binary display driving. The object of the present invention is solved by a multi-gradation display method in which display signals formed by picture element signals, each indicating any one of the levels of N gradations (where N is an integer equal to or greater than 3), are displayed on a display panel in which each picture element provides a two-gradation display, wherein a binary signal is supplied to each picture element (N - 1) times for displaying one frame, and the binary signal is given one of two values a number of times corresponding to the value of the input picture element signal, out of (N - 1) times, thereby providing a multi-gradation display in one frame, characterized in that, the binary signal is produced by comparing the level P of the input picture element signal and the number CN of applications of each binary signal, and the binary signal is given one of the two values when P> CN and the other when P≦ CN. The object of the invention is also solved by a multi-gradation display apparatus which is provided with a first dot clock generator for generating a first dot clock; a row clock generator; a dot shift register of n shift stages supplied with the first dot clock as a shift clock from the first dot generator, a column latch/drive circuit for latching the contents of the dot shift register by the row clock; a row shift register/drive circuit and a display panel in which picture elements are arranged in the form of a matrix with ℓ rows and n columns, the picture elements on the n columns being connected to n column drive lines respectively corresponding thereto, the picture elements on the ℓ rows being connected to ℓ row drive lines respectively corresponding thereto, the picture elements being each driven by inputs to the column and row drive lines connected thereto to provide a display accordingly, the n column drive lines are respectively connected to n outputs of the column latch/drive circuit (26), and the ℓ row drive lines being respectively connected to ℓ outputs of the row shifts register/drive circuit (28), a frame memory in which ℓ x n picture element signals of one frame are stored as display signals each of the picture element signals having M bits (where 2 M is greater than or equal to N which is an integer greater than or equal to 3) indicating any one of the levels of N gradations; a readout address counter a field counter characterized by, a picture element counter for frequency dividing the first dot clock down to 1/n to obtain said row clock, a row counter for frequency dividing the row clock down to 1/ℓ to obtain a field clock, said row shift register/drive circuit being supplied with the field clock as a data input from the row counter and the row clock as a shift clock from the picture element counter, said readout address counter counting the first dot clock from the first dot clock generator and supplying the count value as an address to the frame memory to read it out and being reset by the field clock from the row counter, said field counter counting the field clock from the row counter; and an M-bit comparator which compares the count value CN of the field counter and the level value P of each picture element signal read out of the frame memory and outputs a binary signal of one of its two values when CN > p and a binary signal of the other value when CN≦ p, the binary signal output being applied as a data input to the dot shift register. Thus, each frame signal is supplied, as (N - 1) fields of binary display signals, to the display panel. At this time, each picture element is activated with one of the two logic values from the M-bit comparator for a number of fields, out of (N - 1) fields, corresponding to the level value of the picture element signal. Thus, an N-gradation display is produced apparently. Fig. 1 is a diagram showing, by way of example, the relationship between the level of a picture element signal and its converted binary signal; Fig. 2 is a block diagram showing an example of the basic arrangement for performing the conversion depicted in Fig. 1; Fig. 3 is a block diagram illustrating an example of the multi-gradation display apparatus of the present invention; Fig. 4 is a timing chart for explaining the operation of the apparatus shown in Fig. 3; Fig. 5 is a block diagram illustrating an example of color multi-gradation display apparatus embodying the present invention; and Fig. 6 is a diagram showing, by way of example, the relationships between colors which can be displayed by the apparatus of Fig. 5 and color signals. Referring first to Fig. 1, the principles of the present invention will be described as being applied to a four-gradation display (N = 4) through use of a binary signal. The picture element signal can assume any of levels 0, 1, 2 and 3, and the corresponding picture element of the display panel is driven by the binary signal three times (N - 1 = 3). When the picture element signal has the level 0, the binary signal is a "0" all three times; when the picture element signal is at the level 1, the binary signal is a "1" only once; when the picture element signal is at the level 2, the binary signal is a "1" only twice; and when the picture element signal is at the level 3, the binary signal is a "1" all three times. By repeating such driving at a high speed as compared with the time of visual persistance, a four-gradation display in black, dark gray, light gray and white can be provided. Such a binary signal is obtained through use of such an arrangement as shown in Fig. 2. The level value of the picture element signal is set in a memory 11, clock pulses from a terminal 13 are counted by a modulo-4 counter 12, and its count value and the level value stored in the memory 11 are compared by a comparator 14, which provides an output "1" or "0" to an output terminal 15 depending upon whether the count value is greater than or equal to or smaller than the level value. In this way, the binary signal is obtained at the output terminal 15. Next, a description will be given, with reference to Fig. 3, of a specific example of the method for providing a multi-gradation display according to the present invention. In this example, a frame memory 21 comprises M memory planes, each composed of ℓ by n bits (where ℓ and n are integers greater than one), and each frame consists of ℓ by n picture elements. Each picture element signal assumes any one of the values of N gradations (where 2 M ≧ N and N is an integer equal to or greater than 3), and each picture element signal is stored in the frame memory 21, with each of its M bits assigned to one of the M memory planes. A dot clock DCK from a dot clock generator 22 is counted by an address counter 23, the count value of which is used as an address for reading out a picture element signal of M bits simultaneously from the M memory planes of the frame memory 21, and the read-out picture element signal P is supplied to an M-bit comparator 24. The dot clock DCK is frequency divided by a picture element counter 25 down to 1/n, and the row clock HCK, which is the frequency-divided output, is provided as a latch command to a column latch/drive circuit 26. At the same time, the row clock HCK is frequency divided by a row counter 27 down to 1/ℓ, producing a field clock VCK. The field clock VCK is fed into a serial data input terminal of a row shift register/drive circuit 28 having ℓ shift stages, and then shifted stage to stage in synchronization with the row clock HCK upon each occurrence of n dot clocks. The address counter 23 is reset by the field clock VCK. The field clock VCK is counted and frequency divided by a field counter 29 down to 1/(N - 1), yielding a frame clock FCK. The frame clock FCK is used to update the frame, and when the display panel is a liquid crystal display panel, it is used to reverse the polarity of a drive voltage for activating the liquid crystal. The level P of each picture element signal read out of the frame memory 21 and the count value CN of the field counter 29 are compared by the M-bit comparator 24, which outputs a "1" for P > CN and a "0" for P ≦ CN, respectively. The binary signals from the comparator 24 are fed in serial to a data terminal D of a dot shift register 31 and shifted into the respective n stages of the shift register 31 under control of the dot clock DCK. Then, the contents of the shift register 31 are latched in parallel in the column latch/drive circuit 26 upon each occurrence of the row clock HCK. By n outputs from the column latch/drive circuit 26 n column drive lines of a display panel 32 with ℓ rows and n columns are respectively driven, and one of its ℓ row drive lines is selectively driven in accordance with the contents of the row shift register drive circuit 28. In other words, n picture elements connected to the selected one of row drive lines are driven in parallel by the n outputs from the column latch/drive circuit 26. With such an arrangement, all the counters 23, 25, 27 and 29, the column latch/drive circuit 26, and the dot shift register 31 are initially reset, and a "1" is initially set in the initial stage of the row shift register/drive circuit 28. Then picture element signals on a first row of the frame are read out of the frame memory 21 in succession. Where the read-out values are, for example, "3", "2", "0", "1", ..., as shown in Fig. 4A, these values are successively compared with the count value CN of the field counter 29, first with a "0" as depicted in Fig. 4B, in the comparator 24, which provides outputs "1", "1", "0", "1", ... corresponding to the above-noted values 3, 2, 0, 1, ..., as shown in Fig. 4C. These outputs are sequentially loaded in the dot shift register 31. Upon completion of the readout for the first row, the row clock HCK is generated by the picture element counter 25, by which the contents of the dot shift register 31 are latched in the column latch/drive circuit 26, and at the same time the "1" shifts to the first stage of the row shift register/drive circuit 28, with the result that n picture elements on the first row of the display panel 32 are respectively driven by binary signals. In this way, each time picture element signals of one row are read out of the frame memory 21, the activation of the picture elements on the display panel 32 is shifted by one row. When the frame memory 21 has been read out for one frame, that is, when the display for the first field has been completed, the row counter 27 yields the field clock VCK, as depicted in Fig. 4D, by which the address counter 23 is reset, and the same contents of the frame memory 21 is read out again, starting at picture element signals corresponding to those on the first row. Thus the display for the second field is initiated. At this time, the count value of the field counter 29 is a "1", with which are compared the picture element signals "3", "2", "0", "1", ... read out of the frame memory 21. In consequence, the comparator 24 outputs binary signals "1", "1", "0", "0", ..., as depicted in Fig. 4C, and they are displayed on the display panel 32. Thereafter the frame memory 21 is repeatedly read out in the same manner as described above, and the display panel 32 is scanned row by row, providing a display. In the display of an (N - 1)th field the count value of the field counter 29 is N - 2, with which are compared the outputs P from the frame memory 21. At the end of the display of the (N - 1)th field the display of one frame is completed, and the frame clock FCK is generated by the field counter 29, as shown in Fig. 4E, starting the display of the next frame with renewed picture element signal values 4, 1, 0, 2, ..., for example. As described above, each picture element is driven by binary signals (N - 1) times. When the picture element signal value is P, the same picture element is driven by the binary signal "1" P times and by the binary signal "0" (N - 1 - P) times, thereby producing an N-gradation display. In order to prevent the display from flickering, the frequency of the frame clock FCK is selected to be 60 Hz, for instance. For updating the display of one frame, it is necessary only to employ two sets of frame memories and write in one of them display signals to be displayed next while the other is being read out. For displaying a color display signal as a color image, a color display panel is employed in which every three picture elements constitute three color pixels having red, green and blue color filters, respectively. In the case of producing a color display in, for example, 3³ = 27 colors based on the three primary colors, it is necessary only to take such steps as described below. For instance, as illustrated in Fig. 5, the dot clock generator 22 is placed under synchronous control of a vertical synchronizing signal of a TV signal which is supplied from a terminal 47. Let it be assumed that red, green and blue color pixel signals constituting a color signal of the color TV signal are each given any one of the levels 0, 1 and 2, that is, N = 3. Accordingly, the field counter 29 frequency divides the field clock VCK down to 1/(N - 1) (i.e., 1/2), producing the frame clock FCK. The respective picture element signals are written in one of frame memories 21a and 21b in the cyclical sequence red - green - blue. That is, the red, green and blue color pixel signals are applied simultaneously to input terminals 42R, 42G and 42B of a selector 43 which is formed by an analog switch, and they are repeatedly selected in succession and applied to an AD converter 44. A write dot clock DCK₁ is generated by a write dot clock generator 56 at a rate three times higher than the rate of the color signals in the TV signal, in synchronism with the TV horizontal and vertical synchronizing signals HSYN and VSYN from terminals 41 and 47 and supplied to a color select control circuit 45, from which a control signal is applied to the selector 43 to successively and repeatedly select the inputs from the terminals 42R, 42G and 42B. In a blanking control circuit 46 the write dot clock DCK₁ is processed by the vertical synchronizing signal in the TV signal from the terminal 47 so that during the blanking period the dot clock DCK₁ is inhibited, thereby stopping the increment of address generation at a write address counter 48 during the blanking period. The output dot clock from the blanking control circuit 46 is counted by the write address counter 48 to produce the write addresses. A write address created by the write address counter 48 is provided via an address selector 49 to either one of the frame memories 21a and 21b. In the AD converter 44 the input color pixel signals are converted into 2-bit digital values in accordance with their levels 0, 1 and 2 in this example, and then applied as write data to either one of the frame memories 21a and 21b via a data selector 51. The outputs read out of the frame memories 21a and 21b are selected by a data selector 52 for input into the 2-bit comparator 24. The display dot clock DCK₂ from the dot clock generator 22 is frequency divided by the picture element counter 25 down to 1/n. The frequency-divided output is further frequency-divided by the row counter 27 down to 1/ℓ and is then provided to the field counter 29, as in the case of Fig. 3. The readout address from the readout address counter 23 is supplied via the address selector 49 to that one of the frame memories 21a and 21b which is not being supplied with the write address. Upon each toggle of a flip-flop 55 on the vertical synchronizing signal, the address selector 49 and the data selectors 51 and 52 are switched between their operational states for selecting the frame memories 21a and 21b. When the data selector 51 is applying the AD converted output to the frame memory 21a, the address selector 49 supplies the write addresses to the frame memory 21a to put it in the write mode and at the same time provides the readout addresses to the frame memory 21b to put it in the read mode, and the data selector 52 supplies the comparator 24 with the output read out from the frame memory 21b. Accordingly, the input TV signals are written in the frame memory 21a in the order red - green - blue for every three picture elements, starting at the left-hand end of the first row on the picture frame. At the same time, the frame memory 21b is read out and the red, green and blue color pixel signals are converted into binary signals for every three picture elements, starting at the left-hand end of the first row, and they are sequentially written in the dot shift register 31. When the picture element signals of one row have been read out from the frame memory 21b, the data in the dot shift register 31 is latched in the column latch/drive circuit 26. A color display panel 54 has an ℓ by n matrix structure of picture elements every three of which are formed by color pixels with red, green and blue filters in a row. The red, green and blue color pixel signal outputs from the column latch/drive circuit 26 are provided to the color pixels on the row drive line selected by the row shift register/drive circuit 28. In this example, when the frame memory 21b has been read out twice, the frame clock FCK is yielded. In this example the display is produced in 27 colors, as depicted in Fig. 6. The frame clock FCK has a frequency of, for instance, 60 Hz, as mentioned previously. Since the frame memories 21a, 21b are each read out two times during each frame period, the display dot clock DCK₂ has a frequency about two times higher than that of the write dot clock DCK₁. As has been described above, according to the present invention, a multi-gradation display can be provided through use of a display panel which is driven by binary signals. This enables simple digital processing of display signals, and hence allows ease in the processing for display on the row scan type display panel. In the case of employing the digital comparator 24, as described previously, the frame memory needs only to have M bits (where 2 M greater than or equal to N) for each picture element in the case of an N-gradation display, and accordingly the memory capacity needed is small.

Claims: A multi-gradation display method by which display signals formed by picture element signals, each indicating any one of the levels of N gradations (where N is an integer equal to or greater than 3), are displayed on a display panel in which each picture element provides a two-gradation display, wherein a binary signal is supplied to each picture element (N - 1) times for displaying one frame, and the binary signal is given one of two values a number of times corresponding to the value of the input picture element signal, out of (N - 1) times, thereby providing a multi-gradation display in one frame, characterized in that, the binary signal is produced by comparing the level P of the input picture element signal and the number CN of applications of each binary signal, and the binary signal is given one of the two values when P> CN and the other when P≦CN. The method of claim 1, wherein the respective (N - 1) applications of the binary signal to each picture element are performed in corresponding (N - 1) fields constituting each frame. A multi-gradation display apparatus which is provided with a first dot clock generator (22) for generating a first dot clock (DCK, DCK₂); a row clock generator (HCK); a dot shift register (31) of n shift stages supplied with the first dot clock (DCK, DCK₂) as a shift clock from the first dot generator (22), a column latch/drive circuit (26) for latching the contents of the dot shift register (31) by the row clock (HCK); a row shift register/drive circuit (28) and a display panel (32, 54) in which picture elements are arranged in the form of a matrix with ℓ rows and n columns, the picture elements on the n columns being connected to n column drive lines respectively corresponding thereto, the picture elements on the ℓ rows being connected to ℓ row drive lines respectively corresponding thereto, the picture elements being each driven by inputs to the column and row drive lines connected thereto to provide a display accordingly, the n column drive lines being respectively connected to n outputs of the column latch/drive circuit (26), and the ℓ row drive lines being respectively connected to ℓ outputs of the row shifts register/drive circuit (28), a frame memory (21) in which ℓ x n picture element signals of one frame are stored as display signals each of the picture element signals having M bits (where 2 M is greater than or equal to N which is an integer greater than or equal to 3) indicating any one of the levels of N gradations; a readout address counter (23), and a field counter (29); characterized by, a picture element counter (25) for frequency dividing the first dot clock (DCK, DCK₂) down to 1/n to obtain said row clock (HCK), a row counter (27) for frequency dividing the row clock (HCK) down to 1/ℓ to obtain a field clock (VCK), said row shift register/drive circuit being supplied with the field clock (VCK) as a data input from the row counter (27) and the row clock (HCK) as a shift clock from the picture element counter (25), said readout address counter (23) counting the first dot clock (DCK, DCK₂) from the first dot clock generator (22) and supplying the count value as an address to the frame memory (21) to read it out and being reset by the field clock (FCK) from the row counter (27), said field counter (29) counting the field clock (FCK) from the row counter; and an M-bit comparator (24) which compares the count value CN of the field counter (29) and the level value p of each picture element signal read out of the frame memory (21) and outputs a binary signal of one of its two values when CN > p and a binary signal of the other value when CN ≦ P, the binary signal output being applied as a data input to the dot shift register (31). The apparatus of claim 3, wherein the frame memory (21) comprises first and second frame memories (21a, 21b), each display signal is a TV signal, a second dot clock (DCK₁) generated by a second dot clock generator (56) in synchronism with the picture element signals is counted by a write address counter (48), the count value of the write address counter (48) is applied as a write address to one of the first and second frame memories (21a, 21b) via an address selector (49), the count value of the readout address counter (23) is applied as a readout address to the other of the first and second frame memories (21b, 21a) via the address selector (49), the TV signal is converted by an AD converter (44) into an M-bit digital value for each picture element signal, the converted digital value is applied as a write data via a first selector (51) to one of the first and second frame memories (21a, 21b) which is being supplied with the write address; the output read out of one of the first and second frame memories (21a, 21b) which is being supplied with the readout address is provided via a second selector (52) to the M-bit comparator (24); the second dot clock generator (56) and the write address counter (48) are synchronously controlled by a vertical synchronizing signal of the TV signal; the vertical synchronizing signal is frequency divided by a flip-flop (55) down to 1/2, the first and second selectors (51, 52) and the address selector (49) are switched under control of the frequency-divided output of the flip-flop (55); and the frequency of the second dot clock (DCK₁) of the second dot clock generator (56) is selected about (N - 1) times higher than the frequency of the first dot clock (DCK₂, DCK) of the first dot clock generator (22). The apparatus of claim 4, wherein the TV signal is a color TV signal; a third selector (43) is controlled by a color select control circuit (45) which operates on a clock of a frequency three times higher than that of the color signals each composed of red, green and blue color pixel signals; the red, green and blue color pixel signals in the color TV signal are selectively applied via the third selector (43) to the AD converter (44); every three of the n outputs of the column latch drive circuit (26) correspond to the red, green and blue color pixel signals; and every three picture elements in the display panel (54) are formed by red, green and blue color pixels. The apparatus of claim 3, wherein the display panel (32, 54) is a liquid crystal display panel.

Inventors: YASUI, MASARU
Applicants: HOSIDEN CORPORATION
Application year: 1987
Main classification: G09G3
IPC codes: G09G3, H04N3