PROCESS AND APPARATUS TO CONTROL SYNCHRONOUS MOTORS, SERVOMOTORS IN PARTICULAR

Abstract: The proposed process forsees the following phases: a) measuring, with the RC method, the mechanical angle between the polar axes of the rotor and the stator of a resolver, one of which is integral with the rotor of the motor; b) opening and subsequent closing of a counting window that gives the ''enable'' to ''count'' to a counter that is fed by a clock, in such a way that the number of counted impulses univocally corresponds to the measured angle; during this phase a count adjustment is possible, by modifying its contents according to other external factors; c) transmitting this count as an address to a memory where for each numerical data received, the wave-form required to control the synchronous motor are stored; d) transmitting the storage outputs to a multiplying digital to analogic converter having a multiplication coefficient established by the factor that has to be externally adjusted. e) acting on the contents of the counter, modifying them according to other external factors such as speed, voltage, current or the like.

Description: " ■ PROCESS AND APPARATUS TO CONTROL SYNCHRCMOϋS MOTORS, SERVOMOTORS IN PARTICULAR" This invention is concerned with a circuit generating two- or three phase signal that can be utilized as current reference for a servo-amplifier that controls synchronous motors and in particular synchronous- servo-motors. 5. Till now known circuits are neither simple nor economical. 1) A system for example requires the use of cams and/or variable reluctance detectors. These systems are closely dependent on the motor shape for which they were designed, their mechanical form being tied to the polar form, of the motor. Their output is therefore strictly dependent on the mechanical shape of the cams and/or the reluctance of the 5. magnetic masses. As a result, these systems must have the same polar and/or magnetic configuration as that of the motor. The signals produced can only be varied in amplitude, there can be no phase correction, and therefore no automatic optimization of the system's efficiency, as no processing of phases and their 10. contents is possible. 2) Another system involves the use of a resolver installed on the motor axis. Theis resolver must have the same polar configuration as the motor. "This system therefore does not permit the use of any resolver with any motor. Furthermore, it does not allow any 15. simple continuous and automatic phase processing, which is however necessary for optimization of the servo-system efficiency. The only possible motor phase process must be achieved by means of a microcomputer, which makes the whole operation complicated and expensive. 20. 3) Another approach involves the use of a resolver followed by a high precision (resolver to digital) converter (a R/D converter is an electronic system that transforms the angular signal of a resolver into a digital number resulting from the measured angle) . This system permits the subsequent data processing both 25. in amplitude and phase, but is very expensive. In practice, the need is felt for an apparatus that can be used for simple processing and/or automatic correction of phases, depending on or correlating to various external factors, such as, for example: - "SPEED" to correct the delay inherent in all conversion systems (conversion time) ; for example, a delay of 200 microseconds results from the use of a frequency of 5 KHz as sampling time; 5. - "CURRENT" to correct, where necessary, possible shifts of the motors' magnetic axes depending on the motor's current; - "VOLTAGE" to correct the phase according to the mains voltage. The main purpose of this invention is therefore to embody a simple and economical circuit allowing the elimination of any dependence 10. between the number of poles of the resolver and of the motor. Another purpose, no less important than the preceding one, is to be able to utilize the same circuit used for the generation of motor control "phases" to carry out phase shifts depending on other variables, such as, for example, speed, current or voltage. This is 15. extremely important for the servo-system's performance in its entire operational range, but especially at high speed and/or in presence of high currents. The above-mentioned aims have been achieved as specified in the attached claims. 20. The invention will now be more precisely described by some exemplary embodiments shown in the enclosed drawings, wherein: Fig. 1 is an overall circuit diagram of the apparatus; Fig. 2 is a detailed diagram of a first embodiment ' that does not include phase correction; Fig. 3a up to 3i show voltage wave forms at various points shown on the diagram of fig. 2; 5. Fig. 4 and 5 are schematic views of further embodiments, that show double cycler (a) half time for counting (b) half time for service; Figs. 6a, 6b and 6c are further embodiments of the circuit allowing 10. the "AUTOMATIC PHASE CORRECTION"; Figs. 7a and 7b show, as a diagram, the wave-forms at various points of the circuit in fig. 6b. - 7a shows the circuit 6b without phase correction that means V 12 = 0 V. - 15. - 7b shows the same circuit with phase correction that means V 12 different from 0 V. Figs. 8 and 9 are diagrams of further embodiments of the circuit allowing phase correction; Fig. 10 is a detail of the circuit in Fig. 6b, to which an improve- 20. ment has been made, for a better linearization; Fig. 11a to 11f show the voltage at various points of the circuit illustrated in Fig. 10 before and after correction; Fig. 12a shows a circuit where the correction is made adding one short delay in serial between V5 and the output V6 25. (see also Fig. 6b) ; Fig. 12b, 12c and 12d show the voltage at various points of the circuit in fig. 12a. Here, it must be stated that when a positive or a negative polarity leading or (rising) edges are mentioned, these are to be taken as purely indicative values, being it possible, in each case, to invert these rising values, placing positive in the place of negative and leading instead of trailing or vice-versa, set or reset, these values depending entirely on the components used. 5. Fig. 1 shows the fundamental flow chart of a servo-mechanism according to this invention. It involves a syncrhonous servomotor M which can be three-phase, a resolver RES, assembled coaxial to the motor M for the detection of polar position and a tachymetric generator "G" for the detection of angular speed. 10. The servomotor M is controlled by a current generator for example three-phase (current loop) which, taking data from the resolver, generates the three control currents through one processing step, one memory, Digital to Analogic (D/A) converters and multipliers. The "phase" of the three currents is controlled by the current 15. loop; the "amplitude" of the three currents is instead dependent on the speed loop. The "speed loop" compares the requested "angular" speed, (voltage V1), with the "actual speed" detected by G generator (voltage V2) . The difference between the two voltages, suitably amplified and 20.corrected, represents the amplitude multiplication coefficient of the three vector current signals feeding the servomotor M. In Fig. 2 it can be noted that the proposed apparatus includes the well known "angle measurement system", starting from a resolver (RES) , fed by a sine wave on the primary winding, and having two 25.secondary outputs V4/1=V sin w t. sin < mech and V4/2=V sin w t. cos ^ mech applied to a "RC circuit" satisfying the wRO=1 function. A voltage V5 (fig. 3g) can be obtained at the common point on the RC circuit, its phase can differ from the resolver primary- input V3. This phase is strictly proportional to the mechanical 5. angle between the rotor and the stator axis of the resolver. This variation is shown in fig. 3g as "arrow movement"*. In Fig. 2 we also have: a) the high frequency oscillating circuit "A" (2.56 MHz in this case) generates the V1 voltage high frequency. 10. b) the M1/M2 frequency divider "B" divides the 2.56 MHz frequency by 256 to obtain 10 KHz. (in this case) . c) the low-pass filter "C" eliminating the harmonic of the square wave V2, so transforming it into a pure sine wave V3 (fig. 3a) having the same fundamental frequency of "V2" (10 KHz. in this 15. case). At this point, once the two sinusoidal signals V5 (fig. 3g) and V3 (fig. 3a) have been obtained, having a phase difference proportional to the mechanical angle, an output digital number has to be obtained, after various processing phases. This digital number 20. serves as a "storage address" to extract the data from the memory concerning the wave forms used to control the motor. For this purpose, at first the two sine waves must be squared. Wave V3 (fig. 3a) is transformed into square wave V7 (fig. 3b) . Wave V5 (fig. 3g) is transformed into square wave V6 (fig. 3h) . 25.Eig. 3h shows four waves, V6, marked 1, 2, 3 and 4. Each one of these detects a specific phase difference to V3 (corresponding to the rotation) . The two resulting voltages, V6 and V7, control the state of a bistable circuit ( ) , with set S and reset R input. 5. For convenience bistable commutation occurs during positive transition edge of input signal (can be reversed) . As a result, the signal V8 (fig. 3i) is obtained, that remains positive (or, vice-versa, negative) for a period directly propor¬ tional to the value of the mechanical angle, between rotor and 10. stator of the resolver, or rather, to the value of the phase difference angle between the two waves V3 and V5. Fig. 3i shows the "V8" signal corresponding to the four different angular phase difference values "V6" the four waves V6 showed in Fig. 3h as 1, 2, 3 and 4. 15. The signal "V8" is thus utilized as "enable" for a COUNTER (binary type in this case) . The counting clock is given by V1 signal. It is clear that the counter must have a maximum capacity equal to the number of clock (V1 pulses) , which can transit during one cycle of signal V3 or V5, corresponding to the divider ratio (b) as in 20. F g- 2. A logic circuit generates a signal allowing to reset' synchronously the counter at the beginning of each counting cycle. Then the counter process is activated by the signal "V8 enable" and clock "V1". The new content is dependent on the value of the mechanical angle and is then transferred as address to the memory through a latch 5. logic. Control voltage (V10) applied to the latch (fig. 3f) (negative logic in this case) activates this transfer function. Considering that the counting cycle is related to frequency "V3", in order to prevent coincidences and as a consequence, false condition among the signals of: 10. - enable - reset and preset - memory reading - memory addressing (latch) - analogic switching (commutation) 15. it has been adopted as processing cycle time a period equal to two cycles of frequency V3 (fig. 3c - and 4) . Signal V7 (here 10 KHz) is applied to a (bistable) flip-flop utilized as a by two frequency divider to generate the signal at 5 KHz (V10) (fig. 3c and 4) . 20. As a result the process cycle will depend and is synchronized with the V8 frequency equal to 5 KHz. (repetition rate) . Fig. 3a to 3i show all the wave forms of the utilized signals, in particular: Fig. 3a, shows the voltage wave form of the (V3) 10 KHz. frequency feeding the resolver rotor. Fig. 3b shows the square wave signal V7, as result of signal V3 squaring. Fig 3c shows the square wave signal V10 resulting from the frequency 5. division of signal V7 (see fig. 4 as well) . Fig. 3d shows the control voltage that allows the successive switching commutation of selectors S1, S2 and S3, synchronized with the three memory cells read in each single cycle. Fig. 3e shows the counter "RESET" signal V11 (see fig. 4 as well) 10. positive edge action in this case. Fig. 3f shows the latch signal "V10" (negative edge) used to transfer and store in memory (address latch) the value contained in the counter. Fig. 3g shows the V5 signal. The signal is shifted with respect to 15. the reference signal V3. The phase displacement depends on the phase difference existing between the rotor polar axis and the stator polar axis of the resolver. Fig. 3h shows the V6 signal, corresponding to the squaring of four different V5 signals (time depending) . 20. Fig. 3i shows four "enable" signals (V8) obtained on the flip-flop fig. 4 from the combination of "set" positive edge (V10) and "reset" (signal positive edge V6) . With reference to fig. 4 the positive edge of signal V10 is used as a SET for a flip-flop or bistable circuit while the ' positive edge of signal "V6" is used as a "RESET" (it is possible to invert functions and polarities) . The output "V8" of flip-flop " " remains positive for a cycle equal 5. to the electric phase displacement between the voltages V5 and V3, depending on the mechanical angle difference between rotor and stator. Signal V8 is now utilized as enable control signal for the counter, so the counter will count and increment only during the positive 10. cycle of signal V8 (see fig. 3 and 4) . As can also be seέn in fig. 4, signal V8 can only be positive during phase A of signal V10 (fig. 3c) that means the "counting phase" of the cycle in phase A only, because the start "SET" (CORRESPONDING TO THE POSITIVE EDGE OF V10) takes place only in phase A. 15. The "enable" to "count" can be also obtained by the use of an "exclusive OR" between signals V7 and V6, as shown in fig. 5. The output "V8" of the "exclusive OR" between "V6" and "V7" is used as a GATE controlling the clock input pulse. In particular: 20. - if the two voltages V7 and V6 are in phase, a complete conductance occurs, producing the counter's m«vtτnvtτn load; - if the voltages are in phase opposition, the-conductance is zero, producing the zero increment on the counter. Of course, depending on the design, the opposite condition can also occur; - the "negative edge" of voltage V10 transfers the contents of the counter to the memory as "Address". The RESET of the counter (fig. 4) is obtained by signal V11, being # positive if V7 and V10 are negative (NAND V7:V10) . After the reset counter is ready to start a new cycle. The contents of the counter at the end of the next cycle will depend on the value of the mechanical angle and will serve as an address to the memory on which two (bi-phase) or three (three-phase) numbers that contain the 10. current vector information correspond for each address. These numbers are converted into analogic signals by DAC (digital to analogic converter) . Unlike what is shown in fig. 1, in order to simplify the circuit a single DAC (fig. 2) can be used. 15. The DAC will receive the digital input information sequentially in two (in case of bi-phase) sequential time, the output of the DAC through the switch SI S2 S3 synchronized with the sequentially digital input will be applied to the three sampling hold output amplifier. The output of the three sampling hold represents the 20. requested vector signal of the two or three phase current reference. So far a system has been described where the angular position of the rotor of a resolver is detected and quantified into a digital number. This digital number used as address to a memory, generates three analogic data, in output, required to control the current loop of the synchronous motor. The AUTOMATIC CORRECTION or automatic processing of the phase can be obtained as weel, by this system, in accordance with other factors such as: speed, current, system's power supply or anything else. 5. In practical working, the entire conversion system often shows a delay due to the repetition rate of the operating cycle. In our case it is 5 KHz. and the resulting delay is 200 microseconds. At high angular speed of the motor this delay can cause considerable problems as the analogic voltages Vu, Vv and Vw, generated by the 10. system, can be delayed of 200 microseconds when compared with theoretical time. This delay causes a phase displacement which prevents the optimal operation of the servosystem. In order to compensate this unrequested phase delay, or even to correct it in advance, or in any case, to carry out advisable 15. correction, the following methods can be adopted: 1) The use of an analogic adder on signal V5 or V3, before the trigger. Fig. 6a shows a block diagram with the "adder" (20) connected in series to V3 - V7 line. 20.Fig. 6b shows a block diagram including the "adder" (20) connected in series to V5-V6 line. Fig. 6c shows a particular embodiment of the adder connected in series with V5 - V6 line where an additional adder (21) can be seen receiving the weight resistances corresponding to the desired corrections (this solution is suggested where more then one correction is needed) . 5> Fig. 7a shows signals V5 and V6 referred to the circuit in fig. 6b without any correction (V12 - OV) . It has been noted that no phase difference exists. Furthermore, the leading edge of signal V6 is clear, being it used to reset the bistable circuit controlling the counter. 10 • Fig. 7b shows the effect of the correction of signal V6 caused by a positive voltage V12 added to the voltage V5. The leading edge of wave V6 is shiftefd on an additional angle fø in relation to the preceding state where V12 was zero. The shift of both wave edges of signal "V6" can be observed. 15. For relatively small shifts, up to 30°, these phase displacements can be considered linear referred to the V12 correction voltage, even if the V5 signal is sinusoidal. By following this procedure and by carefully choosing the correction phase, (the displacement can be either leading or lagging) the servo-mechanism can be automatically 20. corrected and optimized. The signal Vu, Vv and Vw will therefore depend not only on the phase between the rotor and stator of the resolver but also on external correction factors. 2) Should larger phase displacements be necessary a triangular wave instead of a sinusoid wave can be generated (fig. 10) , so 25. allowing a greater phase displacement, linearized along the entire cycle, by connecting a circuit (fig. 10) to line V5 - V6 or to line V3 - V7 as described below. Fig. 10 shows the circuit connected to line V5 - V6. At the trigger output (23) generating the voltage V15 is connected 5. an integrator that transforms the square wave voltage V15 in a triangular wave form V13 with linear sloop. In fig..11a is shown the input sinusoidal wave form of V5. In fig. 11b is shown the square wave form of the signal V15. In fig. 11c is shown the triangular wave form V13. 10. At this point, by adding the triangular wave V13 to the correction voltage V12 by the adder 20, the signal V1 is obtained (fig. 11e), which represents the V13 displaced vertically. The signal V14 so obtained is applied to a squarer generating the signal V6 (fig. 11f). 15. Fig. 11d shows the wave V6 without phase correction (V12=0) while in fig. 11f the same wave-form is shown in the presence of a correction, (V12) Note the phase correction . 3) Another solution provides to connect a delay circuit in series to line V5 - V6 or V3 - V7. This delay circuit is made up of "one 20. shot" or something similar, having its delay value controlled by voltage V12 (fig. 12a). Considering that only the leading edge of the V6 reset signal is used, a "one shot" can be introduced in series to the line V6 so that the wave form at the output of one shot is that shown in fig. 12e. Here it can easily been observed that most of the time the one 5. shot stays positive and becomes negative when it is activated. In presence of a positive edge of V15 (fig. 12c) , the one shot becomes negative (fig. 12d) and becomes positive again (fig. 12e) after a period of time that varies according to the correction voltage V12. 10. 4) In order to correct the phase angle or the contents of the counter (representing the phase angle) in another way, the correction voltage V12 (see fig. 8) can be taken and converted by an "analogic to digital" converter; then the digital data is applied as a "preset value" to the counter. In practice, 15. numerical values to or from the counter are simply added or subtracted (set or preset) . 5) The correction data could be easily available in digital form (fig. 9) . In this case, as shown in fig. 9, the system is even simpler. The digital data can be directly used, as preset values. 20. it is however clear that the digital correction data must have previously been processed. For storage reading, two addresses can be used (fig. 2: address B1 and address B2) . Address B1 establishes the choice of a group of cells (in this case three cells) . Address B2 establishes a reading sequence in the group of cells chosen by address B1. Because of each group is made up of three, they are read sequen- 5. tially by a logic combination of signals V7 and V10 (see fig. 3d, 4 and 5) . Data output from the memory is consequently sequential. Decoding is automatically obtained inside the memory. These same signals, V7 and V10, when decoded (fig. 2 and 3d) control 10. selectors S1 , S2 and S3 in order to synchronize the output of the data from the memory with the analogic outputs Vu, Vv and Vw.

Claims: C A I M S 1. A process for producing two or three-phase signals that are made to correspond to a given angle and utilized to control syncrhonous motors and in particular synchronous servomotors, characterized in that the following phases are involved: 5. a) measuring, with the RC method, the mechanical angle existing between the polar axes of the rotor and the stator of a resolver, one of which is integral with the rotor of the motor; b) opening and subsequent closing of a counting window that gives the "enable" to "count" to a counter fed by a clock so that the 10. amount of counted pulses univocally corresponds to the angle measured; c) transmitting this count as an address to a memory in which, for each numerical data received, the wave-forms required to control the synchronous motor are stored (numerical form) ; 15. d) transmitting the storage outputs to a multiplying digital to analogic converter with a multiplication coefficient controlled by other factors; e) acting on the contents of the counter, modifying them according to other external factors such as speed, voltage, current or the like (fig. 7a, b; 11d, f; 12c, d) . 2. Process as in claim 1, characterized in that the wave controlling the opening or closing of the window is linearized (fig. 5. 11b, c, e) . 3. Apparatus providing two or three phase signals to control synchronous motors, synchronous servomotors in particular, characterized in that the following items are'involved: a) resolver with an RC detector unit to detect the mechanical angle, 10. b) a means designed to carry out opening and closing of a counting window according to the data detected by the resolver, c) a counter, d) a memory receiving -the count, carried out by the counter as an address and containing two or three numerical references 15. depending on the required wave form, e) at least one D/A Converter, f) at least one multiplier, having a multiplying coefficient given by the torque control. g) modifying means capable of varying the contents of the counter 20. according to other measurable external factors (fig. 6a, b, c, fig 8, fig. 9, fig. 10 and fig. 12a) . 4. Apparatus as in claim 3, characterized in that the means for varying the contents is an adder (20) (fig. 6a, b, c, and fig. 10) connected in series to one of the two lines with voltages V6 and 25. V7, calculating the sum of the original signal and the correction signal, thus obtaining the shifting of window opening and/or closing. 5. Apparatus as in claim 4, characterized in that a linearizing circuit is also included (22, 23, fig. 10) so that a large correction remains linear. 6. Apparatus as in claim 3, characterized in that the means 5. for varying the counter contents (fig. 8 and 9) consists of a preset counter value, a value that varies depending on the measured external factors according to which the correction is made. 7. Apparatus as in claim 3, characterized in that the means for varying the counter contents according to external factors is a 10. delaying or t anticipating device (one shot) connected to the line with voltage V5 or V7 (fig. 12a) .

Inventors: FRANZOLINI LUCIANO, FRANZOLINI, LUCIANO
Applicants: APPARECCHI ELETT IND SRL
Application year: 1987
Main classification: H02P5
IPC codes: H02P25