OUTPUT DRIVER CIRCUIT

Abstract: An output driver circuit comprises an output NPN transistor (T r1 ), a control NPN transistor (T r2 ), and a protection circuit (14) for protecting the output tran­ sistor (T r1 ) from being destroyed. The protection circuit (14) detects a collector current of said output NPN tran­ sistor (T r1 ) and changes a base current of said control NPN transistor (T r2 ).

Description: The present invention relates to an output driver semiconductor circuit according to the precharacterizing portion of claim 1. In general, a single NPN transistor is employed as an output driver circuit used as an interface driver and the like. However, the use of a single NPN transistor entails the risk that if the collector and a power source is short-circuited, a large current exceeding the maximum value in the safe operating range begins to flow between the collector and emitter, with the result that the transistor breaks down. In such an abnormal condition, there is also the danger that the transistor will generate increased heat and that its temperature will exceed the safe junction temperature, again resulting in the transistor breaking down. Accordingly, an output driver circuit using a single NPN transistor possesses the drawback wherein it is easily rendered inoperative by an excessive output current or by excessive temperature. From document DE-A-2 351 732, a protection circuit for an output transistor in a monolithic integrated circuit is known, in which the output transistor is protected with regard to over-temperature and excessive output current e.g. in case of shortcircuit. The over-temperature is detected by an excessive temperature detector including a diode exhibiting a positive temperature coefficient. A resistor is connected between an output terminal and the emitter of the output transistor. The voltage drop across said resistor is utilized to drive overcurrent protection means limiting the maximum current flowing through the output transistor operating in emitter mode and thereby preventing a destruction of that transistor. From document US-A-4,555,742, a shortcircuit detection circuit and method for operatively controlling current in an electrical load such as an alternator field coil is known. The circuit includes a driving device such as a Darlington transistor for driving the electrical load. Detection means selectively withhold and provide operating current to the driving means when a shorted and a not-shorted condition of the electrical load is respectively detected at the driven terminal of the driving device. The output transistor is operated in an open-collector mode. Both circuits disclosed with the above-mentioned documents DE-A-2 351 723 and US-A-4,555,742 do not exhibit dedicated means to protect the circuit against influences cause by electrical noise and the like. It is therefore object of the present invention to provide an improved output driver circuit of three terminals, which can be prevented from breaking down due to an excessive output current and excessive temperature. This object is solved according to the present invention by an output driver semiconductor circuit according to the precharacterizing portion of the main claim, exhibiting the features specified within the characterizing portion of the main claim. The dependent claims 2, 3, and 4 exhibit further non-trivial improvement on the subject-matter of the main claim. An output driver circuit according to the present invention comprises: an output NPN transistor whose collector and emitter are respectively connected to first and second terminals; a control NPN transistor whose emitter is connected to the base of the output NPN transistor, and whose base and collector are connected to a third terminal; and a protection circuit for detecting a collector current to the output NPN transistor and controlling a base current to the control NPN transistor. The operation of the present invention will now be explained briefly. When the collector current to the output NPN transistor becomes an excessive value, supply of the base current to the control NPN transistor is shut off by the protection circuit, so that the output NPN transistor is protected. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a diagram showing the basic structure of an output driver circuit according to an embodiment of the present invention; Fig. 2 is a circuit diagram of the driver circuit shown in Fig. 1 and, in particular, shows a protection circuit, as a block diagram; Fig. 3 is a circuit diagram of the driver circuit shown in Fig. 1 and shows the protection circuit in further detail; Fig. 4 is a circuit diagram of a driver circuit alternative which is not claimed. Fig. 5 is a circuit diagram of another alternative driver circuit which is not claimed; and Fig. 6 is a circuit diagram of another alternative driver circuit which is not claimed. An embodiment of the present invention will now be described hereinbelow, with reference to the drawings. The collector and emitter of an output NPN transistor Tr₁ are respectively connected to first and second terminals 11 and 12 shown in Fig. 1. The emitter and collector of an NPN transistor Tr₂ are respectively connected to the base and collector of output transistor Tr₁. A resistor R₁, for absorbing a leakage current and increasing the operation speed, is connected between the base and emitter of transistor Tr₁, in order to prevent a malfunction. The emitter of a control NPN transistor Tr₃ is connected to the base of transistor Tr₂. A resistor R₂, for absorbing a leakage current and increasing the operation speed, is connected between the base and emitter of transistor Tr₂, in order to prevent a malfunction. A third terminal 13 is connected to the collector of control NPN transistor Tr₃, via a resistor R₃ for limiting a bias current to transistor Tr₁. Third terminal 13 is connected to the base of transistor Tr₃, via a bias resistor R₄. A protection circuit 14 is also connected to the base of transistor Tr₃. The base and emitter of output NPN transistor Tr₁ and third terminal 13 are all connected to protection circuit 14. In the foregoing construction, when an input current I i is supplied to third terminal (input terminal) 13, control NPN transistor Tr₃ is turned on, and darlington-connected transistors Tr₂ and Tr₁ are sequentially turned on. Now, assuming that current-amplification factors of transistors Tr₂ and Tr₁ are h FE2 and h FE1 , respectively, and that a bias current of protection circuit 14 is I BIAS , an output current I out will become I out ≃ (I i - I BIAS )h FE2 · h FE1 (1) Further, a current-amplification factor h FE (= h FE2 x h FE1 ) of the transistor circuit composed of transistors T r2 and T r1 is expressed as follows. Fig. 2 shows the circuit of Fig. 1 and illustrates a structure of protection circuit 14, as a block diagram. In Fig. 2, the same parts and elements as those shown in Fig. 1 are designated by the same reference numerals, and thus, their detailed descriptions are omitted. The structure of protection circuit 14 will be first described. One end of a resistor R₅ is connected to third terminal 13. A constant-voltage circuit 15 of band-gap type is arranged between the other end of resistor R₅ and the ground. An inverting input terminal (-) of a comparator 16 is connected to an output terminal of constant-voltage circuit 15, i.e., to a node between resistor R₅ and constant voltage circuit 15. A node of resistors R₆ and R₇ is connected to a non-inverting input terminal (+) of comparator 16. Resistors R₆ and R₇ are serially connected between third terminal 13 and the ground. Resistor R₆ is arranged on the side of third terminal 13. Resistor R₇ is arranged on the ground side. An output terminal of comparator 16 is connected to one input terminal of a two-input AND gate 17. An input terminal of an excessive current-detection circuit 18 is connected to the base of output NPN transistor Tr₁. An output terminal of detection circuit 18 is connected to one input terminal of a two-input OR gate 20. The other input terminal of OR gate 20 is connected to an output terminal of an excessive temperature-detection circuit 19. An output terminal of OR gate 20 is connected to an input terminal of a delay circuit 21. The output signal of OR gate 20 is delayed by delay circuit 21. An output terminal of delay circuit 21 is connected to a set input terminal S of a latch circuit 22. The output signal of delay circuit 21 is latched by latch circuit 22. An output terminal Q of latch circuit 22 is connected to the other input terminal of two-input AND gate 17. An output terminal of AND gate 17 is connected to the base of control NPN transistor Tr₃. The AND (logical product) output signal of AND gate 17 is supplied to the base of control NPN transistor Tr₃. An excessive current-limitter 23 is arranged between the base of control NPN transistor Tr₃ and the base of output NPN transistor Tr₁. The limitter 23 limits the base current of control NPN transistor Tr₃, thereby suppressing a base current, flowing through transistor Tr₁, to a value below a desired value. The operation as a driver circuit in the foregoing constitution will now be described. When an input voltage V in is applied to third terminal 13, an output terminal voltage V s of constant-voltage circuit 15 is applied to the inverting input terminal (-) of comparator 16, and a voltage of which is derived by dividing input voltage V in by resistors R₆ and R₇, is applied to the non-inverting input terminal (+). When the output of comparator 16 becomes "L" level and the output of AND gate 17 also becomes "L" level. Therefore, no bias current flows through the base of control NPN transistor Tr₃, and each of transistors Tr₃, Tr₂, and Tr₁ is turned off. On the other hand, when the output of comparator 16 becomes "H" level. The output of latch circuit 22 becomes "H" level, in the normal operation of output transistor Tr₁, and becomes "L" level in the abnormal condition thereof. In normal operation, both of two inputs of AND gate 17 become "H" level, and the output of AND gate 17 becomes "H" level. Therefore, the base of control NPN transistor Tr₃ is biased via resistor R₄, by input voltage V in , so that transistor Tr₃ is turned on. Thus, transistors Tr₂ and Tr₁ are sequentially turned on. A threshold voltage V TH of this integrated circuit becomes as follows from expressions (3) and (4): However, when comparator 16, and resistors R₆ and R₇ are not provided (the circuit also operates even if they are not provided), threshold voltage V TH of the circuit becomes the sum of each voltage V BE of transistors Tr₃ to Tr₁, i.e., 3V BE . Therefore, threshold voltage V TH of expression (5) needs to be set to a value higher than 3V BE . Since constant voltage circuit 15 is of the bandgap type, threshold voltage V TH does not depend on the ambient temperature. The protecting operation performing in the event that output NPN transistor Tr₁ experiences an abnormal condition, will now be described. It is now assumed that the load (not shown) connected to first terminal 11 of transistor Tr₁, for example, was short-circuited, so that a collector current to NPN transistor Tr₁ has increased. In this case, the abnormal state (excessive current) is detected by excessive current-detector 18, and the output signal of detector 18 becomes "H" level. Alternatively, assuming that the temperature of the chip has greatly increased due to the abnormal operation of transistor Tr₁, this abnormal state (excessive temperature) is detected by excessive temperature-detector 19, and the output of detector 19 becomes "H" level. When at least one of the output signals of excessive current-detector 18 and excessive temperature-detector 19 becomes "H" level, the output signal of OR gate 20 becomes "H" level. The output signal of OR gate 20 is supplied to delay circuit 21. After the output of an "H" level signal from OR gate 20, when a predetermined time has elapsed, the output signal of delay circuit 21 becomes "H" level and latch circuit 22 is set. Thus, the Q output signal of latch circuit 22 becomes "L" level, so that the output signal of AND gate 17 becomes "L" level, irrespective of the level of the output signal of comparator 16. Transistors Tr₃, Tr₂, and Tr₁ are sequentially turned off and the abnormal state brought about by the excessive current or excessive voltage is eliminated. Therefore, no current flows through transistors Tr₃ to Tr₁, so that transistors Tr₃ to Tr₁ do not break down. The reason why control NPN transistor Tr₃ is turned off, after the elapse of a predetermined time period, by using delay circuit 21, following output of the "H" level signal was from OR gate 20, is to prevent protection circuit 14 from responding to the instantaneous increase in the base current of output NPN transistor Tr₁, which is caused by external noise and the like. In order to set output NPN transistor Tr₁ into the safe operating range, within the delay time, by means of delay circuit 21, excessive current-limitter 23 operates to restrict the base current of control NPN transistor Tr₃. Namely, limitter 23 limits the base current of control NPN transistor Tr₃, thereby suppressing the base current of output NPN transistor Tr₁. When the abnormal state is eliminated and the normal state is restored, latch circuit 22, is reset by the following high level pulse of input voltage V in . As the result, the output signal of AND gate 17 becomes "H" level and transistors Tr₃ to Tr₁ are again turned on, so that the current starts flowing again. According to the foregoing structure, abnormal conditions such as excessive output current excessive temperature, and the like, of the output transistor, can be eliminated, so that the breaking down of the output transistor can be prevented. Moreover, since the entire circuit has three terminals, it can be used as an output driver circuit composed of a single NPN transistor, without being modified. Fig. 3 shows the circuit of Fig. 1 and, in particular, illustrates a structure of protection circuit 14 in greater detail than in Fig. 2. Since constant-voltage circuit 15 and comparator 16 are well-known circuits, they are represented simply by a block and a symbol, and thus, the detailed structures thereof are omitted here. In Fig. 3, the same parts and elements as shown in Figs. 1 and 2 are designated by the same reference numerals, and will be explained in detail hereinafter. Excessive current-detector 18 is comprised of an NPN transistor Tr₄ and a resistor R₈. A detection current I c4 is set by a voltage V BE1 across the base and emitter of output NPN transistor Tr₁. Detection current I c4 is represented by expression (6). Excessive temperature-detector 19 is composed of an NPN transistor Tr₅ and resistors R₉ and R₁₀, and is made operative by an output voltage V s of constant-voltage circuit 15. A voltage VBE5 across the base and emitter of transistor Tr₅ is expressed as follows: An increase in ambient temperature is detected by use of a temperature coefficient (nearly -2 mV/°C) of voltage V BE5 . Delay circuit 21 comprises: a PNP transistor Tr6 of multicollectors; NPN transistors Tr₇, Tr₁₀, Tr₁₂, and Tr₁₃; PNP transistors Tr₈, Tr₉, and Tr₁₁; resistors R₁₁ to R₁₅; and a capacitor C. The operation of delay circuit 21 will now be explained. A collector current I c7 of transistor Tr₇ becomes a reference current for the excessive output current and excessive temperature detection current. Collector current I c7 is expressed by the following expression (8). A current having a value substantially the same as that of current I c7 flows to a junction of the base of transistor Tr₈ and the collectors of transistors Tr₄ and Tr₅, from PNP transistor Tr₆. Now, assuming that collector currents of NPN transistors Tr₄ and Tr₅ are I c4 and I c5 , respectively. Transistor Tr₈ is turned off under the condition where I c7 is larger than I c4 , or where I c7 is larger than I c5 , so that delay circuit 21 does not operate. Transistor Tr₈ is turned on under the condition where I c7 < I c4 + I c5 so that capacitor C is charged by a small current I determined by transistors Tr₉ to Tr₁₁ and resistors R₁₂ and R₁₃. When the charged potential in capacitor C reaches a predetermined level, transistors Tr₁₂ and Tr₁₃ are sequentially turned on. Thus, latch circuit 22 operates. Small current I to capacitor C is obtained in the following manner: A collector current I c10 to transistor Tr₁₀ is In addition, assuming that the voltage across the base and emitter of transistor Tr₁₁ is V BE11 , and that resistance value of resistor R₁₂ is R₁₂, a voltage VBE9 across the base and emitter of transistor Tr9 will be V BE9 = I c10 x R₁₂ + V BE11 (10) Therefore, small current I can be obtained by q denotes the charge of electron, k denotes the Boltzman constant and T denotes an absolute temperature. In addition, delay time T is expressed by Latch circuit 22 comprises NPN transistors Tr₁₄, Tr₁₅, Tr₁₆ and Tr₁₇ and resistors R₁₆ to R₁₉. Resistors R₁₈ and R₁₉ serve to reset the latch circuit, by means of a high level pulse of an input signal voltage V in . When input signal voltage V in is input, transistor Tr₁₅ is turned on and transistor Tr₁₄ is turned off. NPN transistor Tr₁₆ is emitter-follower connected, and drives NPN transistor Tr₁₇. In the reset state of latch circuit 22, transistors Tr₁₆ and Tr₁₇ are turned off. On the other hand, when transistors Tr₁₁ and Tr₁₂ in delay circuit 21 are ON, transistor Tr₁₅ is turned off. Thus, since transistors Tr₁₆ and Tr₁₇ are turned on, the output signal of AND gate 17 becomes "L" level, and transistors Tr₃, Tr₂, and Tr₁ are sequentially turned off. Excessive current-limitter 23 composed of an NPN transistor Tr₁₈ and a resistor R₁ (R 1a , R 1b ). Transistor Tr₁₈ is made operative by the voltage obtained by dividing voltage V BE1 across the base and emitter of output NPN transistor Tr₁, by resistors R 1a and R 1b . Assuming that resistance values of resistors R 1a and R 1b are respectively R 1a and R 1b , operating voltage V BE18 is expressed by the following expression (13): According to such a structure, excessive current-detector 18, excessive temperature-detector 19, delay circuit 21, latch circuit 22, and excessive current-limitter 23 can be realized by a relatively small number of elements. As has been described above, according to the present invention, it is possible to obtain an output driver circuit of three terminals, which can eliminate abnormal conditions such as excessive output current and excessive temperature and the like, of the output transistor, and can prevent the breaking down of the output transistor, due to such abnormal conditions. Fig. 4 shows an example in which excessive temperature-detector 19 has been removed. In this case, the output transistor cannot be protected from breaking down due to excessive temperature, but can be protected from a breakdown caused by excessive current. However, OR gate 20 can be omitted. Fig. 5 shows an example in which the excessive current-detector has been removed. In this case, although the output transistor cannot be protected from breaking down due to excessive current, but can be protected from a breakdown caused by excessive temperature, OR gate 20 can be omitted. Fig. 6 shows an example in which the excessive current-limitter has been removed. In this case, even if an excessive current flows, it cannot be reduced, for the constant delay time period, by delay circuit 21. However, if the excessive current is generally not so large, excessive current-limitter 23 is not always necessary.

Claims: An output driver semiconductor circuit comprising: (a) an output NPN transistor (TR1) whose collector and emitter are connected to first and second terminals (11, 12), respectively, an output current (I out ) flowing through said first terminal (11); (b) a control NPN transistor (TR3) whose emitter is connected to the base of said output NPN transistor, and whose base and collector are operatively connected to a third terminal (13); and (c) a protection circuit (14), connected between the base of said output NPN transistor (TR1) and the base of said control NPN transistor (TR3) for detecting a collector current of said output NPN transistor (TR1) based on a base-emitter voltage thereof and for controlling a base current of said control NPN transistor (TR3) to turn the control transistor (TR3) on or off, the protection circuit (14) comprising a first detection circuit (18) for detecting an excessive collector current of said output NPN tranistor (TR1), and a second detection circuit (19) for detecting an excessive temperature of said output NPN transistor (TR1), characterized in that (d) said protection circuit (14) further comprises: a logic circuit (20) for providing a logical sum of output signals of said first and second detection circuits (18, 19), a delay circuit (21) including a capacitor (C) for delaying the output of the logical sum for a predetermined time period, a latch circuit (22) for latching an output signal of said logic circuit (20) which is used to control the base current of said control NPN transistor (TR3) to turn it on and off, and a limit circuit (23) for controlling the base current of said control NPN transistor (TR3), so that a base current of said output NPN transistor (TR1) is limited to a predetermined value. An output driver circuit according to claim 1, characterized in that said protection circuit (24) further comprises: a constant-voltage circuit (15) for generating a constant voltage; a comparator (16) for comparing a constant voltage of said constant-voltage circuit (15) and a voltage corresponding to an input voltage of said third terminal (13); and a logic gate (17) for providing a logical product of an output signal of said comparator (16) and an output signal of said latch circuit (22), the logic product being used to control the base current of said control NPN transistor (TR3). An output driver circuit according to claim 2, characterized in that said constant-voltage circuit (15) is of band gap type. An output driver circuit according to claim 1, characterized in that said second detection circuit (19) detects an excessive temperature of said output NPN transistor (TR1), based on a temperature coefficient of the base-emitter voltage of an NPN transistor (TR5).

Inventors: MATSUMURA, KEN C/O PATENT DIVISION, TEZUKA, HIDEHARU C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: H03K19
IPC codes: H03K19, H03F3, H03K17