Memory cartridge

Abstract: A memory cartridge is loaded in a main unit of a personal computer when used. The memory cartridge comprises a case, and a printed circuit board which is installed therein and on which a large-capacity, one-chip ROM is mounted. Stor­ age area of the one-chip ROM is divided into a plurality of banks respectively having memory addresses of a number accessible by a central processing unit of the main unit, and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with pro­ gress of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits. An arbitrary bank of the one-chip ROM is changed over at an arbitrary timing by the bank selecting data outputted from the other banks of the one-chip ROM.

Description: The present invention relates to a memory cartridge. More specifically, the present invention relates to a memory cartridge which is attachable to and detachable from a main unit of a personal computer such as a home video gaming machine and is loaded in the main unit when used. The invention also relates to a video game machine including such a cartridge. Home personal computers include the gaming machine called the "Nintendo Entertainment System" (trade mark) manufactured and sold by the applicant of the present invention and the one called the "MSX" (commodity name). In these personal computers, an external memory cartridge in which a program of game, education or the like is written in advance is used, and the personal computer is enabled by loading such external memory cartridge in the main unit. The memory cartridge includes a non-volatile memory (for example, ROM) for storing program data and/or character data for display. When a central processing unit (CPU) comprised in the main unit of the personal computer accesses to the ROM of the memory cartridge, the maximum number of accessible addresses, that is, address space is limited by the performance (number of bits) of the central processing unit, and therefore the usable memory capacity of the ROM comprised in the memory cartridge is also limited naturally. For example, in the above-described "Nintendo Entertainment System", only a 256K-bit ROM can be used for program and a 64K-bit ROM for characters at a maximum. Thus, the maximum number of program steps is limited to a maximum address space accessible by the central processing unit, and therefore when such a personal computer is used as a gaming machine, for example, the length of story of the game, the extension of variation in the game, the number of display scenes and the number of characters capable of being displayed are limited. One prior art document proposes to eliminate such an inconvenience. (Japanese Patent Laid-Open No. 112352/1984, laid open on June 28, 1984, which corresponds to EP-A-64,801). In the above-described prior art, an address from the central processing unit installed in the main unit of the gaming machine is given to a plurality of memory chips as a common address input, while that address is decoded by an address decoder. When a specific address is outputted by the central processing unit, the address decode outputs a signal, and in response to the signal, a flip-flop or a latching circuit is operated. From the flip-flop or the latching circuit, a chip select (CS) signal for selecting one corresponding to that specific address is outputted, and the chip select signal enables the corresponding memory chip. Accordingly, the memory area designated by the address of the selected memory chip can be accessed by the central processing unit. The above-described prior art has an advantage that the memory capacity can be expanded without increasing the address ports from the central processing unit. Electronics Engineering 58 No. 711, 1986 pp 131-134 K. Robinson "Overcoming addressing limitations with page - addressed EPROMS" discloses a page - addressed 512K EPROM whose memory area is organised as four pages of 16K bytes each. This EPROM is stated to be suitable for use with an 8-bit processor, which needs only 14 of its 16 address bits to access the full 64K bytes of code in the EPROM. In addition, various other methods of changing over the memory banks have been proposed, but none of them are related to the present invention. US 4,485,457 discloses a memory cartridge for loading in a main unit of a video game machine including a central processing unit, said memory cartridge comprising a case housing a circuit board and a first memory which is mounted on said circuit board and is divided into a plurality of banks (BKO-BK7), each of said banks having a plurality of address locations and at least one of said banks (BK7) including stored bank-selecting data for selecting another of said banks; conductive patterns being formed on said circuit board which include address lines which lead address terminals and data lines which lead data terminals of said first memory to an edge of said circuit board to enable said terminals to be connected to such a central processing unit of the video game machine; data holding means mounted on said circuit board, said data holding means being arranged to hold bank-selecting data. In one aspect the present invention provides a memory cartridge as disclosed in US 4,485,457, characterised in that said data holding means has at least one data input terminal coupled to at least one of the data lines of said first memory, and has at least one data output terminal coupled to a predetermined address terminal of said first memory, said data holding means having at least one control terminal which is led by a control line to an edge of said circuit board and is connected to a control terminal (CE) of said first memory; said data holding means being responsive to a control signal (ROMSEL) and a read/write signal (R/W) on said control line to read out and hold said stored bank-selecting data from said first memory and said first memory being arranged to read out data from another bank, different from that containing bank-selecting data, in accordance with bank-selecting data held by said data-holding means. In accordance with the present invention, even if the address space accessible by the central processing unit is limited, by properly changing-over banks of the first memory, a memory having capacity larger than the maximum address space of the central processing unit can be utilized. This means that, in accordance with the present invention, the memory capacity accessible by the central processing unit can be expanded. Preferably a predetermined one of said banks (BK7) of said first memory is always addressable by predetermined address lines of said first memory said predetermined bank contains bank-selecting data which determines which other of said banks can be addressed at any given time. Preferably said first memory contains a stored program, said stored program includes bank-selecting data relating to each other of said banks and each of said banks includes bank-selecting data which determines which bank (apart from said predetermined bank) can be addressed next. Preferably said first memory contains stored character data and is arranged to transfer said character data to a second memory in response to a write signal on a control line, said first memory having a relatively large memory capacity and said second memory having a relatively small memory capacity. In one embodiment, a large-capacity, one-chip ROM is used as the first memory. A specific bank of the one-chip ROM is kept accessible all the time by the central processing unit. When the specific bank is accessed and a bank selecting data for selecting another bank is read therefrom, the bank selecting data is given to a counter as an active device. Output of the counter is given to the most significant three bits of the address of the one-chip ROM, and thereby another bank in the one-chip ROM is enabled. The bank thus enabled can be addressed by the output from the address port of the central processing unit. Selecting data for still another bank is stored in the previously enabled bank, and when the same is read out, the counter outputs an address which is to enable that still another bank to the most significant three bits of the address of the one-chip ROM in a similar manner. Thus, in accordance with the above embodiment of the present invention, change-over to an arbitrary bank can be made at an arbitrary timing with the progress of a program. Accordingly, by utilizing the memory cartridge as described above in a gaming machine, a more versatile game can be realized. In this case, the character data stored in the bank of the one-chip ROM can be utilized in common in each scene of displaying performed by each bank of the one-chip ROM, and therefore a series of games having long stories can also be produced easily. Also, in accordance with the present invention, unauthorised copying or dubbing of the memory cartridge can be prevented by arbitrarily setting the bank selecting data at an arbitrary program step. In another aspect, the invention provides a video game machine comprising an external memory cartridge connected to a central processing unit and having an address bus which enables the central processing unit to address a predetermined number of address locations; said external memory cartridge comprising a ROM which has a larger number of address locations than are addressable by said central processing unit and whose address ports are connected to said address bus; said central processing unit and said ROM being connected by a data bus; the memory area of said ROM being divided into a plurality of banks (BKO to BK7) each of said banks having a smaller number of address locations than are addressable by said central processing unit; said external memory cartridge comprising data-holding means having an input connected to predetermined bits of said data bus and having an output connected to specific bits of said ROM, and at least one of said banks (BK7) including stored bank-selecting data for selecting another of said banks, said data holding means being responsive to a control signal (ROMSEL) and a signal (R/W) from said central processing unit to read out and hold said stored bank-selecting data from said ROM and said ROM being arranged to read out data from said another bank in accordance with the bank-selecting data held by said data-holding means. A preferred embodiment of the invention is described below by way of example only with reference to Figures 1 to 4 of the accompanying drawings, wherein: Fig. 1 is an exploded perspective view showing one embodiment in accordance with the present invention; Fig. 2 is a schematic block diagram showing one example of a home TV gaming machine capable of utilizing a cartridge as shown in Fig. 1; Fig. 3 is a detailed circuit diagram showing a relationship between a memory for program and a memory for characters as shown in Fig. 1 and Fig. 2, and Fig. 4 is an illustrative view showing a relationship between banks of the memory for program and a memory map of microprocessor. Fig. 1 is an exploded perspective view showing one embodiment in accordance with the present invention. A memory cartridge for gaming machine (hereinafter referred to simply as cartridge) 10 comprises a case 12 formed by an upper case 12a and a lower case 12b. The case 12 is flat and nearly rectangular, and a protrudent portion 14 is formed at one side thereof. Then, an opening 16 is formed by this protrudent portion 14 and the other sides of the case 12 are sealed by side walls. A printed circuit board 18 is housed in the case 12, and a protrudent portion 20 is formed at a portion of the printed circuit board 18 corresponding to the protrudent portion 14 of the above-described case 12. Accordingly, the protrudent portion 20 of the printed circuit board 18 is exposed through the opening 16 of the case 12. Then, conductive patterns or contacts 22, 22, ... constituting means for connecting the cartridge 10 to a main unit of a gaming machine are formed on the protrudent portion 20 in a manner of distributing in the extending direction of the side of the protrudent portion 20. A program memory 24 as a first memory, a character memory 26 as a second memory and a semiconductor device 28 as an active device are mounted on the printed circuit board 18. As detailed later, the semiconductor device 28 may be a counter or a latching circuit. Then, these devices 24, 26 and 28 are connected to proper conductive patterns on the printed circuit board 18, being connected to predetermined contacts 22 formed on the protrudent portion 20 as required. Fig. 2 is a schematic block diagram showing one example of a home TV gaming machine capable of utilizing the cartridge as shown in Fig. 1. A configuration in this Fig. 2 shows the above-described "Nintendo Entertainment System" manufactured and sold by the applicant of the present invention. However, it is pointed out in advance that the present invention can be utilized for every apparatus such as the gaming apparatus or the microcomputer using an external memory cartridge. As described above, the cartridge 10 comprises the program memory 24, the character memory 26 and the semiconductor device 28 which are mounted on the printed circuit board 18, and the protrudent portion 20 of the printed circuit board 18 is attached to an edge connector 32 of a gaming machine main unit 30, and thereby the cartridge 10 and the gaming machine main unit 30 are connected electrically so as to constitute one gaming system. The gaming machine main unit 30 comprises a microprocessor 34 which may be, for example, the integrated circuit "2A03" manufactured by Nintendo, and controllers 38a and 38b are connected to the microprocessor 34 through an I/O interface 36. The gaming machine main unit 30 is further provided with a PPU (picture processing unit) 40, a video RAM 42 and an RF modulator 44. For the PPU 40, for example, the integrated circuit "2C02" manufactured by Nintendo is used, and the PPU 40 reads video data under the control of the microprocessor 34, and gives the same to the RF modulator 44 as a video signal. The RF modulator 44 outputs a video signal being given as a television signal for a TV receiver, for example, of the NTSC system. Here, detailed description is made on correlation among the program memory 24, the character memory 26 and the semiconductor device 28 in reference to Fig. 3. For example, the program memory 24 is composed of a lM-bit masked ROM, and the character memory 26 is composed of a 64K-bit static RAM. Ground terminals G of the program memory 24 and the character memory 26 are connected to the ground, and a predetermined power supply voltage Vcc is applied to these memories 24 and 26 through power supply terminals. A chip enable terminal CE of the program memory 24 is connected to the gaming machine main unit 30 (Fig. 2) through a predetermined terminal (for example, No. 44 terminal) of the edge connector 32. A memory select signal ROMSEL from the gaming machine main unit 30 is given to the chip enable terminal CE. Furthermore, the program memory 24 has address terminals A0-A16 of 17 bits, and has data terminals D0-D7 of 8 bits. These address terminals and data terminals are connected to the gaming machine main unit 30 through the edge connector 32, and data from predetermined terminals, that is, data from the terminals D0-D2 of the least significant three bits in this embodiment, is given as bank selecting data and as three-bit input of the semiconductor device, that is, the counter 28. A chip select terminal CS, the chip enable terminal CE and a write enable terminal WE of the character memory 26 are all connected to the gaming matching main unit 30 through the terminals of the edge connector 32 (for example, No. 56 terminal, No. 17 terminal and No. 47 terminal). A read signal RD from the gaming machine main unit 30 is given to the chip enable terminal CE through the edge connector 32, and the write signal WE is given to the write enable terminal WE. Also, the character memory 26 comprises address terminals A0-A12 of 13 bits and data terminals D0-D7 of 8 bits. The address terminals A0-A12 are connected to the gaming machine main unit 30 through the edge connector 32. The data terminals D0-D7 are connected likewise to the gaming machine main unit 30. Note that one digit of address is indicated by the hexadecimal notation. In this embodiment, as shown in Fig. 4, the program memory 24 is constituted, for example, as a set of memory banks on a 128K-bit basis. This means that the first memory or the program memory 24 comprises eight 128K-bit banks BK0-BK7. These banks BK0-BK7 are defined by addresses "00000-1FFFF". Also, the second memory or the character memory 26 is constituted as a 64K-bit static RAM. Furthermore, in this embodiment, for the semiconductor device 28, for example, the integrated circuit "74LS161" manufactured by Texas Instruments is used, and accordingly the semiconductor device 28 is constituted as a three-bit counter. A read/write signal R/W from the gaming machine main unit 30 is given to a load terminal LOAD of the counter 28, and as described above, the data terminals D0-D2 of the least significant three bits of the program memory 24 are connected to the load terminal LOAD as a preset input. Furthermore, the memory select signal ROMSEL from the gaming machine main unit 30 to the program memory 24 is given to a clock terminal CK through the edge connector 32. Accordingly, count input is given to the counter 28 every time when the program memory 24 is selected by the gaming machine main unit 30, and the counter 28 is incremented (or decremented) by that count input. Output terminals of the counter 28 is of three bits, and the three-bit output is given to the address terminals of the most significant three bits A16, A15 and A14 of the program memory 24 through respective OR gates 46a, 46b and 46c. More specifically, the address terminal (No. 35 terminal) of the gaming machine main unit 30 is connected to one input of each of these OR gates 46a, 46b and 46c, and each output of the corresponding bit of the counter 28 is given to the other input of each OR gate. Accordingly, for the program memory 24, the bank thereof is selected according to the bank selecting data (Fig. 4) in the output of the counter 28. For example, as shown in Fig. 4, if the output of the counter 28 is "000", the bank BK0 is selected, if "001" the bank BK1 is selected, if "010" the bank BK2 is selected, if "011" the bank BK3 is selected, if "100" the bank BK4 is selected, if "101" the bank BK5 is selected, if "110" the bank BK6 is selected, and if "111" the bank BK7 is selected, respectively. The microprocessor 34 of the gaming machine main unit 30 is accessible only to two-bank area of the program memory 24 as the first memory. This means that the microprocessor 34 has address spaces for two banks, "8000-FFFF". Among them, a first address space "C000-FFFF" is allocates so as to access in a fixed fashion always to the bank BK7 of the program memory 24. Then, when an arbitrary bank of the banks BK0-BK7 of the program memory 24 is selected, a second address space of 64K bits defined by addresses "8000-C000" is allocated to the address space corresponding to the selected bank. Accordingly, in the banks BK0-BK7 of the first memory 24, the bank selecting data for the bank to be selected next is required to be stored in the last of or halfway that data. To be detailed, in the bank BK7 as a standing area, the data of the bank to be accessed next by the central processing unit or the microprocessor 34 is stored, and in the bank to be read next in such a manner, the selecting data for the still next bank is stored. Then, all the banks of the program memory 24 can be utilized at an arbitrary timing by the second address space of the microprocessor 34. In the operation, the power supply is first turned on in the state that the cartridge 10 is loaded in the gaming machine main unit 30, and immediately after that or after a reset switch has been depressed, a read command is outputted from the microprocessor 34 of the gaming machine main unit 30 through the address terminal A14 thereof (No. 35 terminal of the edge connector 32). When the address terminal A14 goes high, all outputs of the OR gates 46a-46c become high, and "1" is inputted to all of the address terminals A16-A14 of the most significant three bits of the program memory 24, and accordingly, at this point the microprocessor 34 is accessible to the standing area, that is, the bank BK7 of the program memory 24. Then, the program data of the bank BK7 of the program memory 24 is read and the microprocessor 34 is operated based on that program data. This means that, at this time, the microprocessor 34 can address the bank BK7 using the first address space of the addresses "C000-FFFF". The microprocessor 34 executes a program according to a program data of the bank BK7 of the program memory 24, and the bank selecting data for designating a bank of the program memory 24 is set in the first of (or in the last of or halfway) that program data. As described previously, the bank selecting data selects any one of the banks BK0-BK7 of the program memory 24 by three bits of "000"-"111". Then, the bank selecting data from the data terminals D0-D2 of the least significant three bits of the program memory 24 is given as a preset input of the counter 28. On the other hand, the read/write signal R/W is given to the counter 28 as a load command of the counter 28 from the microprocessor 34, and at this time, the signal R/W is given as the high level, and accordingly in the counter 28, the preset input thereof is not loaded. When the read/write signal R/W goes low level during execution of the program, that is, when the load command is given, the bank selecting data outputted from the data terminals D0-D2 of the least significant three bits of the program memory 24 is written to the counter 28. Thereafter, the microprocessor 34 gives a read signal, that is, changes the signal R/W to the high level, and accesses to the bank (for example, BK6) selected by the counter 28 using the second address space as described above. When the memory select signal ROMSEL from the microprocessor 34 of the gaming machine main unit 30 is low level, the counter 28 and the program memory 24 are enabled. Then, if the data of the selected bank (for example, BK6) is character data, a command of transferring the character data to the second memory, that is, the character memory 26 is outputted. Then, according to that transfer command, the write enable signal WE from the microprocessor 34 is changed to the low level, and write of the character memory 26 is made possible. Then, the data of the selected bank (for example, BK6) of the program memory 24 are all read in the address sequence, and the read character data are given to the microprocessor 34. The microprocessor 34 gives the character data to the PPU 40, and the PPU 40 writes the character data to the character memory 26 in synchronism with address designating of the character memory 26. Thereafter, similarly, according to the bank selecting data contained in the program data from the program memory 24, any of the banks BK0-BK7 of this program memory 24 is addressed as "8000-C000" of the second address space of the microprocessor 34, and the game progresses based on the program data of the bank selected at that time and the character data of the character memory 26. Accordingly, the character data has only to be written in advance to an arbitrary bank of the program memory 24 to be required. This means that the bank selecting data is set in advance in a program data contained in any of the banks of the program memory 24, and the data of the bank selected by the bank selecting data is written into the character memory for characters 26, and thereby the bank of that character data has only to be accessed only when required. In order words, processing has only to jump to the required bank during execution of the program to read the character data at that time. Then, such a bank selecting data can be set arbitrarily by the program, and therefore copying or dubbing of the cartridge 10 can be prevented effectively. As in the case with this embodiment, even if the maximum address space of the microprocessor 34 is relatively small, all of the banks of the program memory 24 can be selected arbitrarily, and therefore the memory capacity which can be utilized by the microprocessor 34 can be expanded apparently. In addition, the present invention can be utilized not only for the gaming system but also for the educational system, being able to have universality. In addition, in the above-described embodiment, the case is described where among a plurality of banks BK0-BK7 comprised in the program memory 24, in the bank BK7, data for transfer-controlling the character data (that is, bank selecting data, latch command of bank selecting data, write command to the character memory 26 and the like) are program-set in advance, and a return command is set in advance in the last address of the bank storing the character data, and with the progress of the game, based on the program of the bank BK7, a character data of another bank is controlled to be transferred to the character memory 26. However, the transfer-controlling data may be stored in several bites close to the last address of each bank storing the character data. Also, in the above-described embodiment, a masked ROM is used for the program memory 24. However, for the program memory 24, for example, an EPROM or the like can be utilized, and further any type of memory can be utilized if it is not volatile. Furthermore, in the embodiment, the character data is written into the character memory 26, but for such data, besides, video data and the like can be written, and in this case, the character memory 26 can be utilized also as a so-called video RAM.

Claims: A memory cartridge (10) for loading in a main unit of a video game machine including a central processing unit (34), said memory cartridge comprising a case (12) housing a circuit board (18) and a first memory (24) which is mounted on said circuit board and is divided into a plurality of banks (BK0-BK7), each of said banks having a plurality of address locations and at least one of said banks (BK7) including stored bank-selecting data for selecting another of said banks; conductive patterns being formed on said circuit board which include address lines which lead address terminals and data lines which lead data terminals of said first memory to an edge of said circuit board to enable said terminals to be connected to such a central processing unit of the video game machine; data holding means (28) mounted on said circuit board, said data holding means being arranged to hold bank-selecting data, said data holding means having at least one data input terminal coupled to at least one of the data lines of said first memory, and has at least one data output terminal coupled to a predetermined address terminal of said first memory, characterised in that said data holding means has at least one control terminal which is led by a control line (44) to an edge of said circuit board and is connected to a control terminal (CE) of said first memory; said data holding means being responsive to a control signal (ROMSEL) and a read/write signal (R/W) to read out and hold said stored bank-selecting data from said first memory and said first memory being arranged to read out data from another bank, different from that containing bank-selecting data, in accordance with bank-selecting data held by said data-holding means, said control signal (ROMSEL), given on said control line (44) by the microprocessor (34), enabling said holding means (28) and said program memory (24); said read/write signal (R/W) being given to said holding means (28) either as a load command (W) of said holding means (28) from the microprocessor (34), said bank selecting data (D0-D2) in which case on the data lines of the program memory (24) are written to said data holding means (28) when said load command (W) is given; or said read/write signal (R/W) being given as a read command (R) to access the bank selected by said holding means (28). A memory cartridge according to claim 1, wherein a predetermined one of said banks (BK7) of said first memory is always addressable by predetermined address lines of said first memory (24) said predetermined bank contains bank-selecting data which determines which other of said banks can be addressed at any given time. A memory cartridge according to claim 2 wherein said first memory (24) contains a stored program, said stored program includes bank-selecting data relating to each other of said banks and each of said banks includes bank-selecting data which determines which bank (apart from said predetermined bank) can be addressed next. A memory cartridge as claimed in any preceding claim wherein said first memory (24) contains stored character data and is arranged to transfer said character data to a second memory (26) in response to a write signal on a control line (14), said first memory having a relatively large memory capacity and said second memory having a relatively small memory capacity. A memory cartridge as claimed in any preceding claim wherein said data holding means comprises a counter (28) and has a LOAD terminal connected to a first control line (14) which is led to an edge of said circuit board and has a CLOCK terminal connected to a second control line (44) which is led to an edge of said circuit board (18) and is connected to an ENABLE terminal of said first memory (24) said counter having a plurality of input terminals which are coupled to respective data terminals (D0,D1,D2) of said first memory (24) and a plurality of output terminals which are coupled to respective predetermined address terminals (A14,A15,A16) of said first memory. A memory cartridge as claimed in claim 5 wherein said counter (28) is provided with gating means (4,6a,b,c) which is responsive to a control signal on a further control line (35) leading to an edge of said circuit board (18) to send said control signal to said predetermined address terminals (A14,A15,A26) of said first memory (24) and which in the absence of said control signal couples said output terminals of said counter to said predetermined input terminals. A video game machine (10,30,38a,b) having loaded therein a memory cartridge (10) as claimed in any preceding claim, said memory cartridge thereby being connected to a central processing (34) unit of said video game machine. A video game machine (10,30,38a,b) comprising an external memory cartridge (10) connected to a central processing unit (34) and having an address bus which enables the central processing unit to address a predetermined number of address locations; said external memory cartridge comprising a ROM (24) which has a larger number of address locations than are addressable by said central processing unit and whose address ports are connected to said address bus; said central processing unit and said ROM being connected by a data bus; and said memory cartridge being characterized by the features as claimed in claim 1. A video game machine as claimed in claim 8, wherein a predetermined one (BK7) of said banks of said ROM (24) is always addressable by said central processing unit and said predetermined bank contains bank-selecting data which determines which other of said banks can be addressed at any given time. A video game machine according to claim 9 wherein said ROM (24) contains a stored program, said stored program includes bank-selecting data relating to each other of said banks and each of said banks includes bank-selecting data which determines which bank (apart from said predetermined bank) can be addressed next. A video game machine as claimed in any of claims 8 to 10 wherein said ROM (24) contains stored character data and is arranged to transfer said character data to a separate memory (26) in response to a control signal (R/W) from said central processing unit (34), said separate memory having a smaller memory capacity than said one-chip ROM. A video game machine as claimed in any of claims 8 to 11 wherein said data-holding means comprises a counter (28) and has a LOAD terminal connected to a first control line (14) of said central processing unit (34) and has a clock terminal connected to both a second control line (44) of said central processing unit and an ENABLE terminal of said ROM (24), said counter having a plurality of input terminals which are coupled to respective data terminals (D0,D1,D2) of said ROM and a plurality of output terminals which are coupled to respective predetermined address terminals (A14,A15,A16) of said ROM. A video game machine as claimed in claim 12 wherein said counter (28) is provided with gating means (46,a,b,c) which is responsive to said control signal (ROMSEL) on a further control line (44) from said central processing unit (34) to send said control signal to said predetermined address terminals (A14,A15,A16) of said ROM (24) and which in the absence of said control signal couples said output terminals of said counter to said predetermined input terminals.

Inventors: NAKAGAWA KATSUYA, NAKAGAWA, KATSUYA
Applicants: NINTENDO CO LTD, NINTENDO CO. LIMITED
Application year: 1987
Main classification: G06F12
IPC codes: G11C8, G11C11, G11C5, G06F12, G06T13