Method and apparatus for PCM recording and reproducing audio signal

Abstract: In a method and apparatus for recording and reproducing a PCM audio signal together with a video signal or singly using a rotary-head type scanner, an analog audio signal is converted into a digital signal of a predetermined number of quantization bits at a prede­ termined sampling period, the digital signal is recorded on a recording medium such as a magnetic tape and an analog audio signal is reproduced from the digital signal reproduced from the recording medium. In a reproducing mode, a signal reproduced from the tape is written into a memory where error detection correction and deinter­ leaving are carried out, and the signal is then read from the memory and applied to a D/A converter. A write rate to the memory depends on the video field period, and a read rate depends on the sampling period. Accordingly, a difference between a write address and a read address of the memory depends on the difference between the field period and the sampling period. Accordingly, by changing a master clock which defines the sampling period con­ trolled by the read address in accordance with the address difference, the difference between the video signal field period and the audio signal sampling period can be controlled and compensated.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to recording and reproducing of a PCM audio signal, and more particularly to method and apparatus for recording and reproducing a coded audio signal together with a video signal or singly to and from a magnetic tape by a rotary magnetic head type scanner, and still more particularly to method and apparatus for recording and reproducing a PCM audio signal which are suitable when a sampling frequency for the PCM audio signal and a rotation frequency of the scanner are asynchronous. The recording and reproducing of the PCM audio signal have been adopted in order to improve the quality of the audio signal accompanied with a video. For example, an 8 mm video recorder adopts an audio PCM system. A sampling frequency of the audio PCM signal is two times as high as a repetition frequency of a horizontal synchronization signal. It is different from an internationally common sampling frequency (32 kHz, 44.1 kHz or 48 kHz). For example, a sampling frequency of an audio PCM signal in a satellite broadcast is 32 kHz or 48 kHz. On the other hand, in a MUSE system which is one of transmission systems for a high grade television system, the sampling frequency of the audio PCM signal is 32 kHz or 48 kHz. Thus, if data sampled at the above sampling frequency are to be recorded field by field, the number of data per field includes a fraction. In order to resolve this problem, a packet transmission system having a leap field to absorb the excess has been adopted as disclosed in NHK Technical Journal 27-7, page 282. In a video disk, the PCM audio signal is recorded at the sampling frequency of 44.1 kHz with the same format as that of a compact disk. However, when the PCM signal is to be recorded by an apparatus such as a video tape recorder which records or transmits the signal discontinuously in time, a following problems arise. First, when a field frequency of a video signal is not an integer multiple of the sampling frequency of the audio signal, the problem described above is encountered in coding. While a solution such as MUSE system described above has been proposed, there must be a synchronous relationship between the field frequency fv of the video signal or a rotation frequency f D of a head scanner which rotates synchronously with the field frequency, and the sampling frequency f s of the video signal. This imposes a limitation to a system application range. As an apparatus for PCM recording and reproducing only the audio signal by a rotary head type VTR, a consumer PCM encoder/decoder (registered in September 1983) of the Japanese Electronic Industries Association Technical Standard CPZ-105 has been known. A recording and reproducing apparatus in accordance with the above Technical Standard is disclosed in an article "Digital Audio/Video Combination Recorder Using Custom Made LSI's, IC's" presented at the 69th Convention, 1981 May 12 - 15, Los Angles AES 1791 (B-6), particularly Figs. 1 and 14. In this article, in the NTSC system, the field frequency f v and the sampling frequency f s are divided from the same master clock and they have a relationship of f s = 735 f v . Accordingly, the number of samples per field is constant at 735. Fig. 1 of the above article shows a block diagram of a configuration of an apparatus for recording and reprodicing sampled PCM signals. An address of a RAM which serves as an interleaving memory is controlled by an address control circuit. However, when the PCM audio signal is to be recorded together with a video signal by a rotary head helical scan type VTR, and if the video signal is of 525 lines/60 fields Television system, the field frequency (f v = 59.94 Hz) is not an integer multiple of the sampling frequency (f s = 32 kHz, 48 kHz), and the number of blocks per field includes a fraction. As a result, a block set which is an aggregation of a predetermined number of blocks for processing the signal such as interleaving and deinterleaving is separated between the fields, inconveniently. A rotary head type digital audio type recorder (R-DAT) for recording only the audio signal has been known and a portion of its specification has been published by "Technical Standard of Rotary Head System (R-DAT)", Dempa Shimbun, October 7, 1985, page 48. In each of the above cases, it is assumed that the field frequency f v and the sampling frequency f s have a certain relationship and there is no discussion for a case where f v and f s are not correlated. In the prior art techniques described above, the sampling frequency of the video signal is not the internationally common sampling frequency the number of quantized bits is small, and the sampling frequency of the audio signal and the field frequency have a synchronized relationship. Thus, when a video signal from a camera and a digital signal from a compact disk are to be recorded together, it is very difficult to simultaneously record them because the sampling frequencies are different and there is no synchronous relationship between the sampling frequency and the field frequency. A solution to the above problem has been proposed in British Patent Application No. 423452 field on September 17, 1984 (JP-A-61-73207). Since it has not been published before the present invention, it is not cited herein as prior art. The European Patent Application EU-A-0 178 075 describes a method for recording and reproducing audio signals, comprising the steps of assembling incoming audio data words, which correspond to successive samples of an audio signal, into groups nominally of N audio data words, where N is the number of audio samples corresponding to the digital video signal to be recorded in one oblique track, allowing the number of audio data words in each group to vary preferably over the range N-1 to N+1 to maintain synchronism of the audio signal with the rotational frequency of the rotary head, coding the audio data words into error-correction blocks for recording by the rotary head, and associating with each error-correction block a status code for use on reproduction and which indicates whether the number of audio data words in the corresponding group is N-1, N or N+1. With the system of this reference the reproducing mode is dependent from the recording mode. The non-prepublished European Patent Application EU-A-0 222 386 discloses a method and apparatus for PCM recording and reproducing of audio signals. The essential features of the reproducing mode of the present invention are not disclosed in this prior art document. In other words, this prior art document does not disclose the detection of a difference between a write-in data rate and a read-out-data rate. Furthermore corrected data is not read out after deinterleaving from the memory at a controlled read-out-data-rate while controlling the write-in data rate in accordance with said detected difference. The prior art the document GB-A-2 107 496 provides an error flag processor intended for saving the storage capacity of a flag RAM. It further provides a RAM control device for simplifying the controlling of a write address for writing error flags into a RAM unit of one frame. It shows the relationship between data and error detection/correction codes, the number of data and the data rate being set a fixed values. SUMMARY OF THE INVENTION It is an object of the present invention to provide a video tape recorder and digital/audio signal processing method and apparatus for recording and a method and apparatus for reproducing a digital audio signal of an internationally common sampling frequency under a video field frequency which is not synchronous with the sampling frequency. The above object is achieved by recording a signal while controlling the number of audio signal samples to be recorded in each field in accordance with a ratio of a video signal field period and an audio signal sampling period. A signal is reproduced while controlling an output rate in accordance with a difference between the field period and the sampling period. In a reproducing system, a signal reproduced from a tape is written into a memory where error correction and deinterleaving are carried out, and the signal is then read from the memory and applied to a D/A converter. A write rate to the memory depends on the video field period, and a read rate depends on to sampling period. Accordingly, a difference between a write address and a read address of the memory depends on the difference between the field period and the sampling period. Accordingly, by changing a master clock which defines the sampling period controlled by the read address in accordance with the address difference, the difference between the video signal field period and the audio signal sampling period can be controlled and compensated. The object of the present invention is reached with the apparatus and methods as defined in the enclosed claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a circuit diagram of one embodiment of the present invention. Fig. 2 shows a partial circuit diagram of Fig. 1, Fig. 3 shows a circuit diagram of another embodiment, Fig. 4 shows a partial circuit diagram of Fig. 3, Figs. 5 and 6 show specific circuits of the partial circuit shown in Fig. 4 and Fig. 7 shows a circuit diagram of a multi-recording system. DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention is now explained with reference to Fig. 1. In a recording mode, a 2-channel (L, R) analog signal is supplied through an input terminal 1. The input signal is amplified to a predetermined level by an amplifier 2, band-limited by a filter 3, and sampled by a sample/hold circuit 4. The sampled input signals are alternately supplied to an A/D converter 6 through a switching circuit 5, and converted to a PCM signal. The signal converted by the A/D converter 6 is written into a RAM 15 through a bus line 14. The PCM signal is arranged and an error correction code is added in accordance with a predetermined format. The error correction code is added by an error correction circuit 20. After the arrangement of the PCM code and the addition of the error correction code, the data is read from the RAM. The writing, arrangement and reading of the PCM signal and the addition of the error correction code are carried out by controlling the RAM addresses by address generation circuits 17 - 19 and an address switching circuit 16. The read address generation circuit 19 is controlled such that the member of audio signal samples in one field counted by a field sample counter 36 is equal to the number of samples set by a field sample count setting circuit 15 in accordance with a signal of a difference detection circuit 34 which detects a difference between the write address and the read address extracted by an address difference extract circuit 33. The signal read from the RAM is converted to a serial signal by a parallel/serial converter 23. Signals other than the audio signal, and control signals such as a synchronization signal are added by the control signal circuit 24 and the switching circuit 25, and they are modulated by a modulation circuit 37. It is amplified to a predetermined level by a recording amplifier 26 and recorded on a magnetic tape 32 by an audio rotary head 31. A switching circuit 30 switches recording and reproducing. A timing generation circuit 21 generates a timing signal to control the entire system by a clock generated by an oscillation circuit 22 and a head switching signal determined by a scanner phase. In a reproducing mode, the switching circuit 30 selects the reproduction, and a signal reproduced by the audio rotary head 31 is amplified to a predetermined level by a reproducing amplifier 29, and shaped by a waveform equalizer. The wave-equalized signal is demodulated by a demodulator 38 and converted to a digital signal. The demodulated digital signal is detected for a synchronization signal by a synchronization detection circuit 28 and converted to a parallel signal by a parallel/serial converter 27. The detected synchronization signal is used as a reference to reproduce data. A signal discriminator 44 discriminates the parallel-converted data to determine whether it is an audio signal or other signal. Only the audio signal is stored in the RAM 15 where data are arranged and error correction is made by the error correction circuit 20. The error-corrected data is read from the RAM 15 and supplied to the D/A converter 12 through the bus line 14. The writing to the RAM 15, error correction and reading from the RAM 15 are carried out by controlling the addresses of the RAM 15 by the address generation circuits 17 - 19 and the address switching circuit 16. The difference between the write address and the read address is extracted by the address difference extract circuit 33, and a control signal for the clock generated by the oscillation circuit 22 is generated by an oscillation control circuit 46 based on the output signal of the address difference extract circuit 33. The analog data converted by the D/A converter 12 is resampled for each channel by the sample/hold circuit 11. The resampled analog signals are supplied from an output terminal 8 through a filter 10 and an amplifier 9. In the record mode, the video signal is supplied from an input terminal 40, converted to a predetermined signal by a video circuit 42 and recorded on the tape 32 by a video rotary head 43. In the reproducing mode, the signal reproduced by the video rotary head 43 is converted to a predetermined signal by the video circuit 42 and outputted from an output terminal 41. With this arrangement, the number of audio signal samples recorded in one field in the record mode and the output rate of the audio PCM signal in the reproducing mode are controlled in accordance with the difference between the write address and the read address of the memory so that asynchronization between the sampling period and the field period is absorbed. Fig. 2 shows a block diagram of one embodiment for synchronizing a video signal system and an audio PCM signal system in the reproducing mode. In the present embodiment, a frequency of the oscillator 22 which generates a sampling frequency of the audio PCM signal is controlled by the difference between the sampling period and the video signal period. The write address at which the reproduced signal is recorded into the RAM 15 is generated by the write address circuit 17 based on the signal generated by the input signal processing circuit, from the reproduced signal, and it depends on the video signal period. The read address at which the audio signal is read from the RAM 15 is generated by the read address circuit 19 based on the signal generated by the timing generation circuit 21 from the clock generated by the oscillator 22, and it depends on the sampling period. Accordingly, the input rate of the audio PCM signal in the reproduced signal and the output rate of the audio PCM signal are not constant. Thus, the difference between the write address and the read address is extracted by the address difference extract circuit 33, and the signal to control the change of frequency of the clock generated by the oscillator 22 is generated by the oscillation control circuit 46 in accordance with the extracted signal. Namely, when the input rate of the audio PCM signal in the reproduced signal is higher than the output rate of the audio PCM signal and the difference between the write address and the read address increases, the oscillation control circuit 46 functions to increase the clock frequency generated by the oscillator 22 so that the output rate of the audio PCM signal increases. If the input rate of the audio PCM signal in the reproduced signal is lower than the output rate of the audio PCM signal and the difference between the write address and the read address decreases, the oscillation control circuit 46 functions to decrease the clock frequency generated by the oscillator 22 so that the output rate of the audio PCM signal decreases. Such a circuit may be constructed by a D/A converter and an amplifier for the oscillation control circuit 46 and by a voltage controlled oscillator for the oscillator 22. With this arrangement, the input rate of the audio PCM signal in the reproduced signal and the input rate of the audio PCM signal in the reproduced signal can be equalized. Fig. 3 shows a block diagram of another embodiment for synchronizing the video signal system and the audio PCM signal system in the reproducing mode. In the present embodiment, the sampling frequency of the audio PCM signal is generated by the crystal oscillator 22 and the difference between the sampling frequency and the video signal period is controlled by changing the rotation speed of the cylinder. When the signals having their own master clocks for the video signal system and the audio signal system recorded in the recording mode are reproduced, the output rate of the audio PCM signal and the input rate of the audio PCM signal in the reproduced signal may not be constant if the master clocks for both systems are independent from each other. A similar problem may arise even if a master clock of one of the systems is shared. In the present embodiment, the difference between the write address from the write address generator 17 at which the reproduced signal is to be recorded in the memory and the read address from the read address generation circuit 19 at which the signal is read from the memory 15 to produce the audio signal stored in the memory is extracted by the address difference extract circuit 33 and a cylinder servo control signal is generated by a control signal generation circuit 47 in accordance with the output signal of the address difference detection circuit 33. A cylinder servo circuit 48 generates a rotation speed control signal for a cylinder motor 51 based on the cylinder servo control signal, an output signal of a pulse generator (PG) 49 of a cylinder 52 and an output signal of a frequency generator (FG) 50 of the cylinder motor 51. A specific embodiment of the cylinder servo circuit 48 is explained. Fig. 4 shows a block diagram of the cylinder servo circuit 48. In a normal video reproducing mode, an output of a crystal oscillator 54 is selected by a switching circuit 55 and supplied to a frequency divider 56. The output signal from the frequency divider 56 may be at 3.58 MHz from which a signal of approximately 29.97 Hz is generated. A phase comparator 57 compares phases of the output of the frequency divider 56 and an output of a PG head 49 shaped by a waveform shaper 59, and a phase compare output by the phase comparator 57 is pulse-width modulated by a pulse width modulator 58. The output of the pulse width modulator 58, and an output signal of an FG head 50 amplified by a pre-amplifier 63 and frequency/voltage-converted by a discrimination control circuit 62 are summed by an adder 60, and the sum output is amplified by a motor drive amplifier 61 to produce a cylinder motor drive signal. In order to equalize the input and output rates of the audio PCM signal, the switching circuit 55 selects a variable frequency oscillator 53. An oscillation frequency of the variable frequency oscillator 53 is controlled by the output of the control signal generation circuit 47. With the circuits shown in Figs. 3 and 4, if the input rate of the reproduced audio PCM signal is higher than the output rate of the audio PCM signal, the difference between the write address and the read address is large. As a result, the variable frequency oscillator 53 is controlled to lower its oscillation frequency so that the rotation speed of the cylinder is lowered. Thus, the input rate of the audio PCM signal is lowered. If the input rate of the audio PCM signal is lower than the output rate of the audio PCM signal, a difference between the write address and the read address is small. The control signal generator 47 thus produces a signal to raise the oscillation frequency of the variable frequency oscillator 53. As a result, the oscillation frequency rises, the rotation speed of the cylinder rises and the input rate of the audio PCM signal rises. In this manner, the input and output rates of the audio PCM signal are equalized without regard to the operation in the record mode. In the record and reproducing modes, an error of a ratio of a vertical synchronization signal repetition frequency fv and the sampling frequency fs of the audio PCM signal due to the difference between the master clock pulse of the video signal system and the master clock pulse of the PCM signal system, is very small when the oscillation sources of those clock pulses are crystal oscillators. However, if the error is neglected, the error is accumulated. In the digital signal processor, since the memories for time-basis expansion/compression and interleaving/deinterleaving are cyclically used, overflow or underflow takes place between the address signal. In order to eliminate such an overflow or underflow the frequencies f v and f s are measured in the record mode, and the same frequencies as those f v and f s in the record mode are generated in the reproducing mode. In the present invention, the frequency difference between f v and f s is not detected but the difference between the read address and the write address of the memory is detected so that the error of the ratio of f v and f s is extracted and compensated. Fig. 5 shows a specific circuit diagram of a 525/60 (NTSC) system of the frequency divider. A signal at a frequency 3.58 MHz selected by the switching circuit 55 is frequency-divided by a frequency divider 64 by a factor of 161, and the divided signal is supplied to a phase comparator 66. An output at 4.090908 MHz of a voltage controlled oscillator 68 is frequency-divided by a frequency divider 65 by a factor of 184, and the divided signal is supplied to another input of the phase comparator 66. The phase comparator compares the phases of the input signals. The output signal of the phase comparator 66 is supplied to a low pass filter 67. The output of the low pass filter controls the oscillation frequency of the voltage controlled oscillator 68. The output of the frequency divider 65 is frequency-divided by a frequency divider 69 by a factor of 136,500, and the divided output is supplied to the phase comparator 57. Fig. 6 shows a circuit diagram of other embodiment in which the output of the crystal oscillator 54 and the output signal of the control signal generator 47 are received to generate compare input signals to the phase comparator 57. A frequency divider 74 selectively receives an output of the crystal oscillator 54 or an output of a variable frequency oscillator 70 through a switching circuit 71, and frequency-divides the input signal by a predetermined factor. A variable frequency oscillator 72 selects the output signal of the control signal generator 47 or an output of a low pass filter, through a switching circuit 73, as a frequency control signal. The output signal of the variable frequency oscillator 72 is supplied to a frequency divider 75 which frequency-divides it by a predetermined factor. The outputs from the frequency dividers 74 and 75 are supplied to a phase comparator 76 as phase compare signals. The output of the phase comparator is filtered by a low pass filter 77. The output of the low pass filter is supplied to the variable frequency oscillator 70 as the frequency control signal and to one input of the switching circuit 73. The output of the frequency divider 75 is supplied to a frequency divider 78 which frequency-divides it by a predetermined factor. The output of the frequency divider 78 is supplied to the phase comparator 57. In the switching circuits 71 and 73, a position V represents a normal video mode and a position P represents an audio PCM signal reproducing mode. The numerals in the parentheses show example for the 525/60 (NTSC) system. Fig. 7 shows an embodiment which records an audio signal in multiplication with a video signal. The audio signal is multiplexed with the video signal by an adder 79, and the multiplexed signal is supplied to a record amplifier 26. Thus, the audio signal is recorded in multiplication with the video signal. The reproduced signal is amplified by the amplifier 29, and the output of the amplifier 29 is supplied to the waveform equalizer 37 and the video circuit 42. In this manner, the multiplex recording and reproducing are attained. In accordance with the present invention, when the PCM audio signal is recorded and reproduced together with the video signal by the rotary magnetic head type scanner, it is not necessary that the rotation frequency of the head scanner and the sampling frequency of the PCM audio signal are synchronized. Accordingly, any video signal and any PCM audio signal may be recorded or reproduced in combination.

Claims: Method for recording and reproducing a PCM audio signal by converting an analog audio signal to a digital signal of a predetermined number of quantization bits at a predetermined sampling frequency and using a rotary head locked to a vertical synchronization signal of an analog video signal, said sampling frequency being asynchronous with said vertical synchronization signal, comprising the steps of: in reproducing (a) storing a signal containing interleaved digital audio data and an error detection/correction code, reproduced from said recording medium within a predetermined period of time synchronous with said vertical synchronization signal, in a memory for deinterleaving; (b) correcting errors in said data stored in said memory in accordance with said error detection/correction code; (c) detecting a difference between a write-in data rate of digital audio data to be stored in said memory for deinterleaving, after being reproduced from said magnetic tape, and a read-out data rate of the data after error detection/correction to control said read-out data rate or said write-in data rate; and (d) reading out said corrected data, after deinterleaving, from said memory at said controlled read-out data rate or while controlling said write-in data rate in accordance with the difference detected in step (c). Method for recording and reproducing according to claim 1 further comprising the steps of: in recording, (e) storing a sequence of data of said digital audio signal in a memory for interleaving on a recording medium; (f) adding an error detection/correction code to the digital audio signal data stored in said memory; (g) determining the number of digital audio signal samples to be recorded on said recording medium from said memory in accordance with a difference between the number of samples stored in said memory and the number of samples recorded on said recording medium within a predetermined period of time synchronous with said vertical synchronization signal; and (h) reading out data and an error detection/correction code in said determined number of samples from said memory, after interleaving, and recording the same on said recording medium. Apparatus for recording and reproducing a PCM audio signal by converting an analog audio signal to a digital signal of a predetermined number of quantization bits at a predetermined sampling frequency and using a rotary head locked to a vertical synchronization signal of an analog video signal, said sampling frequency being asynchronous with said vertical synchronization signal, comprising: for reproducing, (a) reproduction means (29, 39, 38, 27, 28, 44) for reproducing a signal recorded by a recording means on a recording medium; (b) memory means (15, 17) for storing said signal, which is reproduced within a predetermined period of time synchronous with said vertical synchronization signal and contains interleaved digital audio signal data and error detection/correction code, for deinterleaving; (c) correction means (18, 20) for correcting errors in said digital audio signal data stored in said memory by using said error detection/correction code; (d) address generating means (16 - 19) for deinterleaving said corrected data in said memory means; (e) detection means (17, 19, 33, 34) for detecting a difference between a write-in data rate of audio signal data to be stored in said memory, after being reproduced from said recording medium, and a read-out data rate of audio signal data to be read-out from said memory; (f) control means (46, 22, 21, 19) for controlling said read-out data rate or said write-in data rate using the difference detected by said detection means; and (g) means (19, 12, 11, 10, 9) for reading out said corrected deinterleaved data from said memory means at said controlled read-out data rate or while controlling said write-in data rate. Apparatus for recording and reproducing according to claim 3 further comprising, for recording, (h) memory means (15, 17) for storing a sequence of data of said sampled digital audio signal for interleaving on a recording medium; (i) means (18, 20) for adding an error detection/correction code to the data stored in said memory means; (j) address generating means (16 - 19) for interleaving said data stored in said memory means; (k) detecting means (17, 19, 33 - 36) for determining the number of digital audio signal samples to be recorded on said recording medium from said memory in accordance with a difference between the number of samples stored in said memory and the number of samples recorded on said recording medium within a predetermined period of time synchronous with said vertical synchronization signal; and (l) means for recording on said recording medium the digital audio interleaved data and the error detection/correction code in said determined number of samples read out from said memory means.

Inventors: ARAI TAKAO, KOBAYASHI MASAHARU, ARAI, TAKAO, KOBAYASHI, MASAHARU
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1987
Main classification: G11B20
IPC codes: H04N9, H04N5, G11B20