SEMICONDUCTOR NONVOLATILE MEMORY DEVICE

Abstract: In a nonvolatile memory device which is integrated by combining SRAM cells (ST) and nonvolatile memory cells (T MM ) at a ratio of l : l; a control circuit is provided which, at a recall time, selects all word lines (WL) and supplies a predetermined electric potential to bit lines (BL) so that a recall is carried out simply and accurately.

Description: The present invention is related to a nonvolatile memory device which is integrated by combining Static RAM (SRAM) cells and nonvolatile memory cells. A nonvolatile random access memory known as a nonvolatile RAM (NVRAM) may be formed by integrating an Electrically Erasable PROM (EEPROM) and an SRAM on a basis of a ratio of l : l in the memory cell unit. In the NVRAM, the information stored in the SRAM can be stored in the EEPROM when the power source is turned off, and the information stored in the EEPROM can be recalled to the SRAM when the power source is turned on. Conventionally, SRAM cells are formed by a flip-flop having depletion type transistors as the loads, and a nonvolatile memory cell is formed by a transistor having a gate in a floating state, for example, a transistor having a floating-gate tunnel oxide (FLOTOX) structure, described later. In a previous nonvolatile RAM, as explained in detail hereinafter, the pair of transistors is formed in such a manner that the state of the flip-flop becomes unbalanced. This unbalanced state is formed by the load transistor or by adding capacitors. However, because the pair of transistors or the pair of capacitors are made in an unbalanced state, the relationship between a low level and a high level in flip-flop becomes unsymmetrical and the access speed is reduced. Further, a problem arises in that, as the unbalance between the transistors requires a corre­ sponding unbalance of the cell current, then an increase of dissipation current occurs. Further, because a depletion type MOS transistor is used as a flip-flop load in the static memory portion, the drawback of an in­ crease in the electric power dissipation arises. Further, the unbalanced store as mentioned above requires considerable cell area, so the integration density is decreased. An embodiment of the present invention may provide a semiconductor nonvolatile memory device which can operate symmetrically. An embodiment of the present invention may provide a semiconductor nonvolatile memory device which can be operated with a low electric power dissipation. An embodiment of the present invention may also provide a semiconductor nonvolatile memory device having reduced dimensions. The present invention addresses the problem wherein, when the SRAM cell is formed by CMOS inverters to decrease the power dissipation of the NVRAM, it is difficult to reset the balance state of 0 V, 0 V of nodes of the flip-flops at the time of a recall. According to the present invention, the semiconduc­ tor nonvolatile memory device comprises a pair of bit lines; a plurality of memory cells, each including a static memory cell connected between the pair of bit lines and a nonvolatile memory cell connected to the static memory cell; a plurality of word lines connected to the memory cells; and a control circuit, operatively connected to the word lines and at least one of the bit lines, for supplying a predetermined potential to the bit line to put the static memory cell into a predetermined state and for selecting all of the word lines when infor­ mation stored in the nonvolatile memory cell is recalled to the static memory cell. An embodiment of the invention can simply and accurately perform a recall from a nonvolatile memory cell to a static RAM cell. Reference is made, by way of example, to the accompanying drawings in which: Figures lA and lB show a circuit diagram and waveforms for explaining one example of a previous circuit, respectively; Figs. 2A and 2B show another circuit diagram and waveforms for explaining another example of a previous circuit, respectively; Figs. 3A and 3B show a circuit diagram of a main portion of the circuit of one embodiment of the present invention and waveforms thereof, respectively; Fig. 4 is a circuit diagram showing the contruction for a reset operation at a recall time in the embodiment of the present invention; Fig. 5 shows waveforms for explaining the operation of the embodiment of the present invention; Figs. 6A and 6B show a circuit for generating a timing necessary for the embodiment of the present invention, and timing waveforms thereof respectively; Figs. 7A and 7B show a circuit diagram of an essential portion of the circuit of another embodiment of the present invention and waveforms thereof, respectively; Figs. 8A and 8B show a circuit diagram of an essential portion of the circuit of further embodiment of the present invention and waveforms thereof; and, Figs. 9A and 9B show a circuit diagram of an essential portion of the circuit of one embodiment of the present invention and waveforms thereof. Figure lA and Fig. 2A are circuit diagrams of one example of a previous NVRAM. Figure lB and Fig. 2B are timing charts respectively showing an electric power source V CC at a recall time, a recall signal RCL, and a control signal. The circuit shown in Fig. lA is described in detail in Japanese Patent Application No. 58-l9l039, and the circuit shown in Fig. lB is described in detail in Japanese Patent Application No. 58-45697. In Fig. lA and Fig. lB, depletion transistors T₁ , T₂ and N channel enhancement transistors T₃ , T₄ form a SRAM cell. Further, a nonvolatile memory cell is formed, as shown in Fig. lA, by a transistor T₆ in which a gate FG is in a floating state, and, as shown in Fig. 2A, by a transistor having a FLOTOX construction. Data is written to the nonvolatile memory cell by injecting electrons into the floating gates of the transistors T₆ , T₇ , or releasing of electrons from those floating gates. Therefore, the threshold voltage at the transistors T₆ , T₇ changes and T₆ , T₇ are made ON or OFF state in accordance with the data in the SRAM. On the other hand, the recall operation is carried out as follows. Namely, in Fig. lA, and as shown in Fig. lB, the power source V CC rises when the recall transistor T₅ is made ON. At this time, if the T₆ is ON, because a node N₂ is at a low level, only an electric potential of N₁ rises, and thus T₄ becomes ON and T₃ becomes OFF, so that N₁ becomes high level and N₂ becomes low level. On the other hand, if T₆ is OFF state, since N₂ is in a floating state, the state of flip-flop formed by T₁ ∿ T₄ is not unique. Then, when T₆ is OFF, the state of the flip-flop must be determined to be in the opposite state of that when T₆ is ON state. Therefore, the circuit is normally formed in such a manner that the flip-flop is unbalanced. This unbalanced state is determined by load transistors T₁ , T₂, or capacitors C₁ , C₂ For example, the unbalance of the load transistors T₁ , T₂ is determined by the relationship W/L, where W is the channel width and L is the channel length, and the unbalance of the value of the capacitances C₁ , C₂ is determined by the shape of the pattern. For example, if the values of the capacitance have the relationship C₁ > C₂ , the recall operation when T₆ is OFF is carried out as follows. Namely, when the power source voltage V CC rises, if the relationship of the capacitors is C₁ > C₂ , the electric potential at the node N₁ rises more slowly than that of the node N₂ , and thus the node N₁ becomes low level and the node N₂ becomes high level. On the other hand, as N₂ is forcibly made to a low level when T₆ is ON, as already mentioned, the node N₁ becomes high level, and the node N₂ becomes low level. The relationship between the channel width W and the channel length L of the depletion type load transistors T₁ , T₂ is as follows. That is, usually a current becomes larger when W is larger, and the current becomes larger when L is smaller, and accordingly, the value of W/L is equivalent to the value of the resistors. Therefore, the recall operation as mentioned above can be carried out due to the load, i.e., the relationship W/L, instead of the value of C₁ , C₂ In the case shown in Fig. 2A, VR rises at the recall, and therefore, the relationship between T₇ is ON or OFF state and the levels of N₁ , N₂ becomes the reverse of those shown in Fig. lA. The other fundamental operation is the same as that shown in Fig. lA. That is, when T₇ is ON, N₂ becomes high level and N₁ becomes low level, and when T₇ is OFF, N₂ becomes low level and N₁ becomes high level. However, the relationship of the values of capacitance is C₁ < C₂. In the construction of the NVRAM as mentioned above, ideally the capacitances C₁ , C₂ are naturally determined by the pattern obtained when a layout of the integrated circuit is designed. However, in practice, the capacitance C₁ generated at the node N₁ depends on the transistors T₁ , T₃ and the capacitance C₂ generated at the node N₂ depends on the transistors T₂ , T₄ , T₅ , T₆ , etc., and therefore, to satisfy the condition C₁ > C₂ , the capacitance C₁ must be made intentionally large, which causes a corresponding increase in the cell area. On the other hand, to differentiate the load transistors T₁ , T₂ , for example, T₁ > T₂ , the dimensions of the channel width or the channel length must be different, and thus the cell area is again increased. Further, because T₁ and T₂ or C₁ and C₂ are made in an unbalanced state, as the SRAM characteristic, the relationship between the low level in the node N₁ and low level at the node N₂ or high level in the node N₂ (level itself and charging speed) becomes nonsymmetrical, and thus the problem of a reduced access speed arises. Further, a problem arises in that, as the unbalance between T₁ and T₂ requires a corresponding unbalance in the cell current, and this causes an increase in dissipation current. Further, because a depletion type MOS transistor is used as a flip-flop load in the static memory portion, a drawback of an increased electric power dissipation occurs. Accordingly, an attempt is made to lower the electric power by using a CMOS circuit. However, in this case, if the nodes N₁ , N₂ of the flip-flop are intended to be 0 volt, by making the electric power source 0 volts, these are only decreased to the threshold value V th of the p-channel (P-ch) enhancement transistor, i.e., about -l V, and this l volt voltage remains. Therefore, the nodes N₁ , N₂ of the flip-flop stop at, for example, 0 V, l V, and do not reach the balanced state of 0 V, 0 V. Therefore, if the flip-flop can not be completely reset, there is a danger that the recall operation will malfunction. Figure 3A is a circuit diagram showing a main portion of one embodiment of the present invention. In Fig. 3A, ST is a static RAM, T MM is a transistor of an EEPROM cell, BL is a bit line, WL is a word line, V CC is a high power source, and V SS is a low power source(in this case, ground). N channel enhancement transistors forming a flip-flop of the static RAM cell are designated as T S1 , T S2 , T LR1 , T LR2 , an enhancement type p-ch load transistor at a node N₂ side of the flip-flop transistor of SRAM connected to the recall transistor T AR is T LR2 , and an enhancement type p-ch transistor of the other load is T LR1 . These transistors are connected to corresponding n-channel enhancement transistors T S1 , T S2 to form a complementary type MOS inverter, and the pair of inverters are cross-connected to form a flip-flop circuit. A recall control signal RCL is applied to a gate of the recall transistor T AR . S is a store circuit, but as the present invention is concerned with the recall operation, the construction thereof is similar to the above circuit, and it is not necessary to make a special explanation thereof. In the above-mentioned construction, the operation (store) for storing the data from a static RAM side to an EEPROM side is exactly the same as that described above. On the other hand, the operation for recalling the data from the static RAM side to the EEPROM side is as explained below. The bit line (BL) voltage V BL is made 0 V (V BL = 0 V) and the bit line () voltage V is made V CC (V = V CC ). The word line WL voltage V WL is risen to turn T₁ and T₂ on. (V WL = V CC ). As a result, the node N₁ voltage V N1 is reset to 0 V (V N1 = 0 V) and the node N₂ voltage V N2 is reset to V CC (V N2 = V CC ). When the recall signal RCL is at a high level (V ARC = V CC ), V N1 and V N2 change in accordance with whether the transistor T MM , which forms the EEPROM cell, is ON or OFF. That is, as shown in Fig. 3A, (a) When the transistor T MM is ON → V N1 = V CC and V N2 = 0 V, (b) When the transistor T MM is OFF → V N1 = 0 V and V N2 = V CC Figure 3B shows waveforms in the circuit of this embodiment of the present invention. In the Figure, hatched portions show that the potential of N₁ or N₂ is unstable whether it is high level or low level, and further, RCL may be applied before the falling of the word line voltage V WL as shown by the dotted line. As clear from Fig. 3B, when the transistor T MM is ON, as in item (a) mentioned above (it is assumed that information "l" exists), a plus charge is injected to the floating gate FG of the transistor T MM , and thus the T MM is made ON. When the signal RCL becomes H level at the time of the recall, and the recall transistor T AR becomes ON, the node N₂ is connected via T AR and T MM to the ground (GND). Therefore, when the nodes N₁ and N₂ of the SRAM are high level and low level, respectively, the SRAM is reset to the original state by the recall operation. On the other hand, when the nodes N₁ and, N₂ of the SRAM are low level and high level, respectively, the current flows from the node N₂ to the ground, the state of the flip-flop is inverted, and N₁ and N₂ become high level and low level, respectively. Namely, the "l" of the EEPROM cell is recalled to the SRAM cell by the recall operation. Further, when the transistor T MM is OFF, as in item (b) above (it is assumed that information "0" is held), a minus charge is injected to the floating gate FG of the transistor T MM , the T MM becomes OFF, and even if the recall transistor T AR becomes ON, the node N₂ is disconnected from the ground GND. Therefore, even if the signal RCL becomes high level at the time of the recall and T AR becomes ON, the SRAM cell is held in the original state, that is, V N1 = 0 V and V N2 = V CC . Namely, the "0" of the EEPROM cell is recalled to the SRAM cell by the recall operation. However, to assure the operation of the embodiment mentioned above, it is necessary to maintain the ratio between the load transistor T LR2 of the flip-flop and (T AR + T MM ). Unless the ratio of the current value which can flow in T AR + T MM to that which can flow in T LR2 is sufficient, and the data in the node N₂ is rapidly taken out to remove the electric level in the node N₂ , the p-ch load transistor may be turned ON and thus the flip-flop is inversely set. Usually, the following condition should be satisfied. In the above expression, W denotes a channel width and L denotes a channel length of each transistor. Here, since T LR2 is a p-ch enhancement transistor, the mobility of the carriers is lower than that of an n-ch enhancement transistor, and thus the ratio may be comparatively small, as shown in expression (l). Next, the circuit construction for carrying out the reset in the recall operation mentioned in item of the above embodiment will be explained with reference to Fig. 4. In Fig. 4, l designates a row decoder (ROW), 2 designates a column decoder (Column), 3 and 4 designate bit line load transistors, 5 designates a bit line level control transistor, 6, 7, and 8 designate NAND gates, and 9 designates a sense amplifier and write circuit. Further, (the bar denotes a active low signal as shown hereinafter) , RC, and are control signals. Elements the same as shown in Fig. 3A are denoted by the same symbols. Further, in Fig. 4, a plurality of SRAM cells (ST) are connected between bit lines BL and , also a plurality of word lines WL are connected to SRAM cells and gates 6, 7 are provided in the same number as the word lines respectively, however, these are not shown. Figure 5 is a diagram showing waveforms of the operation of the circuit shown in Fig. 4. The circuit of Fig. 4 will be explained with reference to Fig. 5. First, a recall mode signal RC is made to rise at a recall time as shown in (a) of Fig. 5. Accordingly, the output of the gate 8 becomes high level, and an low level is given via the inverter l0 to the output gate COL. The COL is then cut off so that the sense amplifier and write circuit 9 and a bit line are separated. Next, the signal AR2 is made to rise as shown in (b) of Fig. 5, the bit line load transistor 3 is turned OFF and the transistor 5 is turned ON, so that the bit line BL is connected via the transistor 5 to ground, that is, to 0 V. On the other hand, is made to rise via the bit line load transistor 4 to a high potential of power source V CC . Next, when the signal ARl has risen as shown in (c) of Fig. 5, the output of gate 7 becomes high level, all word lines WL are at a selected level (high level), and the transistors TW₁ and TW₂ of the word transfer gate become ON, so that the nodes Nl , N₂ of the flip-flops of the SRAM cell ST are reset to 0 V, V CC respectively, in accordance with 0 V, V CC of BL, . In this state, the recall control signal RCL is made low level, all word lines WL become low level, and the word transfer gates TW₁ and TW₂ are turned OFF, so that the flip-flops of the SRAM cell ST are separated from the bit lines. In this state, when the recall control signal RCL becomes H level, the recall transistor T AR is turned ON, the T MM is made ON when information l is stored in the EEPROM (the plus charges are stored in the floating gate FG), and the node N₂ is then grounded. Therefore, when the nodes N₁ and N₂ of the SRAM cell are high level and high level, respectively, these nodes N₁ and N₂ are reset to the original state by the recall operation, and when the nodes N₁ and N₂ of the SRAM are low level and high level respectively, the flip-flops are inverted so that the nodes N₁ and N₂ become high level and low level respectively, as shown in (j) and (k) of Fig. 5. Further, when the EEPROM cell maintains information "0" (floating gate FG has a minus charge), the T MM is made OFF, and thus even if the recall transistor T AR is made ON, the node N₂ is separated from V SS . Therefore, the state of the SRAM cell is set as it is, and accordingly, the electric potentials of the nodes N₁ and N₂ are V N1 = 0 V and V N2 = V CC as shown in (h) and (i) of Fig. 5. Figure 6A shows a circuit construction for generating the timing signal required for the recall operation in this embodiment of the present invention, and Fig. 6B shows waveforms for the operation thereof. The circuit shown in Fig. 6A is provided with flip-flops at the input thereof and timing generating circuits (which are formed by an inverter, a depletion type MOS transistor formed as a diode and a capacitor and which are actuated as a delay circuit) for generating a timing signal from to . The recall pulse shown in (a) of Fig. 6B is applied to the input of the flip-flop, and the output of the timing generating circuit at the last stage is fed back to the flip-flop to reset the same. In Fig. 6B, (b) to (i) are waveforms at each point ∿ in Fig. 6A. A signal AR2 is obtained as an inverted signal of the output of the NAND gate by inputting the output signals and of the timing generating circuit as shown in (k) of Fig. 6B, a signal ARl is obtained as the output of NOR gate by inputting and as shown in (l) of Fig. 6B, a signal RCL is obtained as the output of NOR gate by inputting and as shown in (m) of Fig. 6B, and a signal RC is obtained from the output of the flip-flop, as shown in (j) of Fig. 6B. Figure 7A is a circuit diagram showing another embodiment of the NVRAM according to the present invention. Elements the same as those shown in Fig. 3A are designated by the same symbols. Fig. 7B shows waveforms for explaining the operation of the circuit shown in Fig. 7A. In the construction of Fig. 3A, at the recall time, the current is allowed to flow to the ground (GND), but in the case of Fig. 7A, the current is made to flow from an external source at the recall time. In this case, at the recall time, the voltage V ST /RCL is supplied from the external source to cause a current flow, and at the store time, two voltages such as 0 V and 22 V are used. A nonvolatile transistor T₇ has a construction in which the transistor T MM and a part of the store circuit S, as shown in Fig. 3A, are formed as one body, and this corresponds to T₇ in Fig. 2A. At the recall time, the control gate is made high level by PRG/RCL, and becomes ON and OFF in accordance with the plus or minus of the charge in the floating gate. In this case, when the nonvolatile memory transistor T₇ has information "l", contrary to the first embodiment, minus charges are stored in the floating gate so that T₇ is made OFF, and when T₇ has information "0", plus charges are stored in the floating gate so that T₇ is made ON. Therefore, if at the reset time of the flip-flop, the node N₁ is reset to the H level and the node N₂ is reset to 0 volt, contrary to the case of Fig. 3A (all word lines are selected as in the above mentioned embodiment and BL is supplied by high level and is supplied by low level, contrary to the first embodiment), and at the recall time, V ST /RCL is made V CC so that the current is made to flow to the node of the flip-flop when T₇ is ON, the information in the EEPROM cell can be restored in the SRAM cell. A further embodiment of the invention is shown in Fig. 8A. Figure 8B shows waveforms for explaining the operation of the circuit shown in Fig. 8A. The symbols in each Figure denote the same elements as those of Fig. 3A. In this embodiment, the construction by which all word lines are selected at the recall time, and a predetermined electric potential is supplied to the bit lines to reset the flip-flop, is common for each embodiment as already mentioned. However, in this embodiment, by resetting the SRAM cell at the recall time, both nodes N₁ and N₂ of the flip-flop are made 0 V. To this end, in this embodiment, all word lines WL are selected during the time the flip-flop of the SRAM cell is reset at the time of the recall mode, i.e., a 0 V reset voltage is supplied from bit lines BL, to the flip-flop. Hereinafter, the recall operation is carried out in the usual manner. For example, when the flip-flop has an unbalanced construction, and the electric potential of the node N₂ is made to rise earlier than that of the node N₁ at a rise time of the power source, the transistor TRCL of the transfer gate is made ON by the recall mode signal RC, the flip-flop is set in accordance with whether the transistor T MM of EEPROM is ON or OFF, and therefore, the information can be restored. Or, instead of forming the flip-flop with an unbalanced construction as shown in Fig. 8A, as in the circuit construction shown in Fig. 9A as another embodiment, an unbalanced operation may be introduced to the operation of the flip-flop by shifting the timing for applying the source voltage VCl and VC2 of the flip-flop. That is, when the transistor T₆ in EEPROM cell is made ON, the timing for applying the power sources VCl and VC2 for the p-ch transistors TLRl and TLR2 of the flip-flop may shifted so that the flip-flop is set in a reverse state when the transistors of the EEPROM cell are ON. Further, the embodiments of Figs. 8A and 9A show the case in which the current flows to ground at the recall time, however, it will be clear that a construction by which the current may be allowed to flow from an external source at the recall time (corresponding to Fig. 7A) is also possible. In embodiments of the invention, the SRAM cell of the NVRAM has a CMOS construction, so that the power dissipation can be considerably decreased compared to when a depletion type load transistor is used, and any mulfunction of the recall operation can be avoided. Further, the construction thereof is comparatively simple, compared with previous circuits, and the recall operation is always available. As explained above, in embodiments of the invention a control circuit is provided which, at a recall time, selects all word lines and supplies a predetermined electric potential to bit lines, so that a recall is carried out simply and accurately.

Claims: 1. A semiconductor nonvolatile memory device comprising: a pair of bit lines; a plurality of memory cells, each including a static memory cell connected between said pair of bit lines, and a nonvolatile memory cell connected to the static memory cell; a plurality of word lines connected to said memory cells; and a control circuit, operatively connected to said word lines and at least one of said bit lines, for supplying a predetermined potential to the or each bit line to put said static memory cell into a predetermined state and for selecting all of said word lines when information stored in the nonvolatile memory cell is recalled to said static memory cell. 2. A semiconductor nonvolatile memory device according to claim l, wherein the static memory cell includes a flip-flop, composed of cross-coupled complementary type inverters, having first and second terminals, a first transfer gate transistor connected between one of said bit lines and the first terminal, and a second transfer gate transistor connected between another of said bit lines and the second terminal, and the nonvolatile memory cell includes a nonvolatile memory transistor, and a third transfer gate transistor connected between the nonvolatile memory transistor and one of the first and second terminal. 3. A semiconductor nonvolatile memory device according to claim 2, wherein the complementary type inverters include a load transistor connected to the third transfer gate transistor, and a relationship between the load transistor, the third transfer gate transistor, and the nonvolatile memory transistor is as shown by the following expression: (wherein W denotes a channel width and L denotes a channel length). 4. A semiconductor nonvolatile memory device according to claim l, 2, or 3, said device further comprising: a row decoder for selecting one of said word lines; and an output gate circuit connected to said bit lines; a column decoder for controlling the output gate; wherein said control circuit includes a bit line level control circuit, connected to one of said bit lines, for supplying the predetermined potential to one of said bit lines in response to a first control signal; a first gate circuit, connected between the row decoder and said word lines, for inhibiting an output of the row decoder in response to a second control signal and outputting a selection signal to all of said word lines in response to a third control signal; a second gate circuit, connected between the column decoder and the output gate, for inhibiting transfer of an output of the column decoder and turning the output gate circuit off in response to the second control signal; and timing generator circuit, connected to the first and second gate circuits and the bit line level control circuit, for generating the first, second, and third control signals. 5. A semiconductor nonvolatile memory device according to claim 4, wherein the first gate circuit includes a first NAND circuit having a first input connected to the row decoder and a second input for receiving the second control signal, a second NAND circuit having a first input connected to an output of said first NAND circuit, a second input for receiving the third control signal and an output connected to said word line, and the second gate circuit includes a third NAND circuit having a first input connected to the column decoder and a second input for receiving said second control signal, and inverters connected between said third NAND circuit and the output gate. 6. A semiconductor, nonvolatile memory device according to claim 4, or 5, wherein the bit line level control circuit includes a first transistor, connected between said bit line and a higher power source, for separating said bit line from the higher power source while the first control signal is applied, and second transistor, connected to said bit line, for supplying the prede­ termined potential while the first control signal is applied. 7. A semiconductor nonvolatile memory device according to claim 4, 5, or 6, wherein the timing generator circuit comprises a flip-flop circuit connected to an input terminal, a first to a seventh delay circuits connected in series, each of which are formed by an inverter, a depletion type MOS transistor connected as a diode to said inverter, and a capacitor connected between an output of said depletion type MOS transistor and a low power source, each of which has a first to a seventh outputs respectively, the first control signal is obtained as a reversed output of a NAND circuit which inputs the second and the fifth output signals of delay circuits, the third control signal is obtained from the output of a NOR gate which inputs the third and fourth outputs of said timing generator circuit, the second control signal is obtained from the output of said flip-flop circuit, and a recall control signal for controlling the third transfer gate transistor is obtained from another NOR circuit which inputs the fifth and sixth outputs of delay circuits. 8. A semiconductor nonvolatile memory device according to claim 4, 5, 6, or 7, wherein the first control signal is generated while the second control signal is generated, and the third control signal is generated while the first control signal is generated. 9. A semicondcuctor nonvolatile memory device according to any one of claims 2 to 8, wherein the third transfer gate transistor is turned on after the static memory cell reaches the predetermined state.

Inventors: ARAKAWA, HIDEKI
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C17
IPC codes: G11C7, G11C14