SAMPLING CLOCK PULSE GENERATOR FOR IMAGE DISPLAY UNITS

Abstract: A sampling clock Pulse generator comprises a basic clock pulse generator 1 which prepares a basic clock pulse 12 having an oscillation frequency of an interger multiple of a dot frequency of a display data signal. The generator also comprises a horizontal synchronous signal detector 2 which converts a horizontal synchronous signal 11 to a pulse synchronous with the basic clock, and a dot clock pulse generator 3 which divides the basic clock pulse 12 into clock pulses 14, each having a dot frequency of the display data signal, by establishing an output 13 of the horizontal synchronous signal detector 2 as a synchronous reset signal, so that the display data signal is sampled by the output of the dot clock pulse generator 3.

Description: The present invention relates to a sampling clock pulse generator for image display units which is connected to a device of preparing image informations through digital processing by a personal computer or the like, and more particularly to a sampling clock pulse generator which is suitable for an image display unit having function of sampling a display data signal from a device of preparing image informations and storing the sampled signal once in a memory. It is a recent trend that a display unit having a flat display screen of liquid crystal panel, EL (electroluminescent) panel, etc. is used in connection with a personal computer or the like. In the flat display unit of this kind, it is necessary to increase duty factor in view of sufficient contrast, and a scanning period of a signal sent from the personal computer is not always coincident with a scanning period of the display unit. For example, to increase duty factor, a display unit is driven so as to scan a signal by dividing its display screen into two areas, i.g., upper and lower areas. Accordingly, when the display unit receives display data for one picture to be displayed which are outputted from the personal computer, the display data are divided into two parts, i.e., upper area data and lower area data to be scanned respectively in the upper and lower areas. As a result, the scanning period of the signal from the personal computer is not coincident with the scanning period of the display unit. Thus, it is necessary to carry out conversion of scanning period by some appropriate means, and conversion of scanning period is usually carried out by a buffer memory. To be more specific, in the display unit, a display data signal is sampled, then once stored in the buffer memory, and read out being adjusted to the control timing of the display unit. Concerning dot clock pulse generating means which generates a sampling clock pulse for sampling display data signal, it is conventional to use such means as shown in Fig. 1, which is disclosed in a literature titled "Digital Technology in Broadcasting" (published by Japan Broadcasting Publishing Co., Ltd. on December 20, 1982; pages 164 - 165). In Fig. 1, a reference numeral 31 denotes a phase comparator, 32 denotes a voltage control oscillator (VCO), 33 denotes a divider, 11 denotes a synchronous signal and 14 denotes a dot clock pulse for sampling a display data signal. Establishing that a horizontal scanning period of the display unit is 800 times the dot period of the display data signal, the dot clock pulse 14 which is an output of the VCO 32 is divided into 1/800 by the divider 32, then is inputted to the phase comparator 31, and a phase difference between it and the horizontal synchronous signal is detected. The VCO 32 is so controlled as to reduce the phase difference by the output of the phase comparator 31 and, as a result, a sampling clock pulse (dot clock pulse) 14 synchronous with the horizontal synchronous signal 11 is generated. This method is so-called a PLL (phase-locked-loop) method. The PLL method is widely used to obtain a signal synchronous with an external signal, but this method is very sensitive to variation in external factors such as ambient temperature, ambient noise, etc. Accordingly, a problem exists in that dislocation of oscillating frequency, jitter or the like due to unlocking is easy to occur, which results in dislocation of dots on the display screen of the display unit. Fig. 2 is a view explaning how to occur the problem. Under the normal operation of the dot clock pulse generator, the "N"th display data 15 are supposed to be sampled by rising the "N"th dot clock pulse 14 as shown in the drawing, and the "N+1"th display data 15 are sampled by rising the "N+1"th dot clock pulse 14, but in the event that the rise of the "N"th dot clock pulse is dislocated to a position shown by the broken line due to aforesaid variation in external factors, the "N+1"th display data 15 are sampled despite that the "N"th display data 15 are to be sampled. As a result, such problem as omission of data, dislocation of dots, comes out on the display screen of the display unit. Accordingly, an object of the present invention is to provide a sampling pulse generator for image display units in which regardless of variation in the external factors such as ambient temperature, ambient noise, a stable sampling clock pulse for sampling a display data signal is obtained in view of securing display quality and reliability of the image display unit. In order to accomplish the foregoing object, a sampling clock pulse generator according to the invention comprises a basic clock pulse generator which prepares a basic clock pulse having an oscillating frequency of an integer multiple of a dot frequency of the display data signal, a horizontal synchronous signal detector which converts a horizontal synchronous signal to a pulse synchronous with the basic clock, and a dot clock pulse generator which divides the basic clock pulse by establishing an output of the horizontal synchronous signal detector as a synchronous reset signal, so that the display data signal is sampled by the output of the dot clock pulse generator. Fig. 1 is a block diagram showing a dot clock pulse generator according to the prior art; Fig. 2 is a time chart to explain the problem of the prior art shown in Fig. 1; Fig. 3 is a block diagram showing an essential part of an embodiment of an image display unit to which the present invention is applied; Fig. 4 is a block diagram showing an embodiment of a sampling clock pulse generator according to the invention; Fig. 5 is a circuit diagram of a horizontal synchronous signal detector according to the embodiment shown in Fig. 4; Fig. 6 is a circuit diagram of a dot clock pulse generator according to the embodiment shown in Fig. 4; and Fig. 7 and Fig. 8 are time charts of waveforms to explain the operation according to the embodiment shown in Fig. 4. Referring now to the accompanying drawings, a preferred embodiment of a sampling clock pulse generator according to the present invention is described in detail hereunder. Fig. 3 shows an example of the image display unit to which a sampling clock pulse generator according to the invention is applied, and in which a personal computer 100 which prepares image informations and a liquid crystal display unit 200 (hereinafter simply referred to as "display unit") which serves as an image display unit are shown. Construction of each of these two components is the same as known one. Various signals such as display data dignal, horizontal synchronous signal, etc. necessary for image display are sent from the personal computer 100 to the display unit 200. The display unit 200 has its essential part as shown in Fig. 3. That is to say, in Fig. 3, a liquid crystal panel 201 serving as a display screen is driven by the output from a segment driver section 202 and a common driver section 203. The segment driver section 202 and the common driver section 203 both generate a driving voltage of a waveform necessary for driving the liquid crystal. A driving voltage control section 204 generates driving voltages of 5 potentials necessary for driving the liquid crystal. A signal processing section 205 samples a display data signal received from the personal computer 100, writes the data in a memory, reads out the data from the memory according to scanning conditions of the liquid crystal 201, sends the data to the segment driver section 202, and further sends control signals to the segment driver section 202 and the common driver section 203. The essential part of the signal processing unit 205 comprises a display data sampling section 211 which samples the display data signal sent from the personal computer 100 by the output from the sampling clock pulse generating section 212, a sampling clock pulse generating section 212 which generates a clock pulse for sampling according to the horizontal synchronous signal from the personal computer 100, a memory 213 in which the display data sampled by the display data sampling section 211 are stored, a control signal generating section 214 which supplies drive control signals to the segment driver section 202 and the common driver section 203, and an address preparing section 215 which prepares address signals for the memory 213 and the control signal generating section 214. A backlight 206 comprising a fluorescent discharge tube, for example, is controlled by the output of a backlight control section 207. Fig. 4 shows an embodiment of a device according to the invention which can be used in the sampling clock pulse generating section 212 in Fig. 3. In Fig. 4, a basic clock pulse generator 1 prepares a basic clock pulse having an oscillating frequency of an integer multiple of a dot frequency of the display data signal. The basic clock pulse generator 1 includes a crystal oscillator, for example, and performs stable oscillation regardless of the variation in external factors such as ambient temtperature. A horizontal synchronous signal detector 2 converts a horizontal synchronous signal 11 sent from the personal computer 100 shown in Fig. 3 to a pulse which is synchronous with the basic clock pulse 12 sent from the basic clock pulse generator 1. A dot clock pulse generator 3 prepares a dot clock pulse 14 by dividing the basic clock pulse 12 sent from the basic clock pulse generator 1 synchronously with a detecting output 13 of the horizontal synchronous signal detector 2. The horizontal synchronous signal detector 2 shown in Fig. 4 is formed by a circuit shown in Fig. 5, for example. In a first D-flip-flop 21 shown in Fig. 5, the horizontal synchronous signal 11 is inputted to a D-terminal, and the basic clock pulse 12 is inputted to a T-terminal. In a second D-flip-flop 22, an output Q of the D-flip-flop 21 enters is inputted to a D-terminal, and the basic clock pulse 12 is inputted to a T-terminal. An output Q of the D-flip-flop 22 and an output Q of the D-flip-flop 21 are inputted to a NAND gate 23. The dot clock pulse generator 3 shown in Fig. 4 comprises a counter 24 with synchronous reset function as shown in Fig. 6, for example. In the counter 24, the basic clock pulse 12 is inputted to a clock input terminal CK, and a detection output 13 of the horizontal synchronous signal detector 2 is inputted to a synchronous reset input terminal R . The dot clock pulse 14 obtained by dividing the basic clock pulse 12 is sent from an output terminal QC. A semiconductor IC such as fully synchronous presettable 4-bit binary counter (Model: M74LS163 manufactured by Mitsubishi Electric Corporation) is used as the counter 24, for example. Described hereunder is operation of the device of the above composition. The basic clock pulse generator 1 prepares the basic clock pulse 12 having the frequency of an integer multiple K (in this embodiment 8 times) of the dot frequency of the display data signal 15. The horizontal synchronous signal detector 2 receives the basic clock pulse 12 and differentiates the horizontal synchronous signal 11. That is to say, as shown in Fig. 7, the output of the Q-terminal of the D-flip-flop 21 is changed to "L" while the output of the Q -terminal is changed to "H" by the rise of the basic clock pulse 12 after the change of the horizontal synchronous signal 11 to "L". Further, as the output of the Q-terminal of the D-flip-flop 22 is "H", the output 13 of the NAND gate 23 is changed to "L". When the next basic clock pulse 12 is inputted to the T-terminal thereafter, the output of the Q-terminal of the D-flip-flop 22 is changed to "L", and the output 13 of the NAND gate 23 is changed to "H". In this manner, the horizontal synchronous signal 11 synchronizes with the basic clock pulse 12, and is converted to the pulse output 13 corresponding to one period of the basic clock pulse 12. In addition, numerals shown in the display data signal 15 in Fig. 7 mean dot numbers of the liquid crystal cell 201. As the basic clock pulse 12 from the basic clock pulse generator 1 is inputted to the clock input terminal CK of the counter 24 and the pulse output 13 from the horizontal synchronous signal detector 2 is inputted to the synchronous reset input terminal R , the dot clock pulse generator 3 divides the basic clock pulse into 1/K (1/8 in this embodiment) synchronously with the pulse output 13 and sends the dot clock pulse 14 having a frequency equal to the dot frequency as shown in Fig. 7 from the output terminal QC. It is usual that the display data dignal 15 and the horizontal synchronous signal 11 are synchronously sent by the personal computer 100. Accordingly, the dot clock pulse 14, rising several clocks (5 clocks in this embodiment) after the basic clock pulse 12 which detected the horizontal synchronous signal 11, is supposed to rise almost in the middle of the dot period of the display data signal 15. In this connection, the dot clock pulse varies principally due to phase difference between the basic clock pulse 12 and the horizontal synchronous signal 11. Such variation, however, is not more than one period of the basic clock pulse 12 at the most, and therefore even when such phase difference takes place, the display data signal 15 is exactly sampled by the dot clock pulse 14 without omission as is comparatively shown in Fig. 8. In the display data sampling section 211 of the display unit 200, the display data signal 15 is sampled by the dot clock pulse 14 generated in the sampling clock pulse generator 212 as described above. Description with regard to the manner of control in displaying the display data sampled by the display data sampling section on the display screen is omitted herein, since the manner of control is well known in the art and the invention is not directly designated thereto. As has been described so far, according to the invention, since the sampling clock pulse is prepared by dividing the basic clock pulse supplied from a stable oscillation source synchronously with the horizontal synchronous signal, it becomes possible to perform stable oscillation at all times without affection by the variation of external factors, improving thereby display quality and reliability of the display unit as compared with the prior art. The circuitry of the horizontal synchronous signal detector 2 and the dot clock pulse generator 3 both forming the device according to the invention is not limited to that shown in Fig. 5 and Fig. 6. Further, the frequency of the basic clock pulse 12 is illustratively 8 times the dot frequency of the display data signal 15 in the foregoing embodiment, but the multiple is not limited thereto, either. Furthermore, a personal computer is used as a device for preparing image informations and a liquid crystal display unit is used as an image display unit in the foregoing embodiment, but the device and unit according to the invention is not limited to them.

Claims: A sampling clock pulse generator for image display units (200) which generates a clock pulse for sampling a display data signal received from a device (100) for preparing image information so as to be used in an image display unit, comprising: a basic clock pulse generator (1) for preparing a basic clock pulse (12) having an oscillating frequency of an integer multiple of a dot frequency of the display data signal received by said image display unit, a horizontal synchronous signal detector (2) for converting a horizontal synchronous signal received from said device for preparing image information to a pulse synchronous with the basic clock pulse output of said basic clock pulse generator, and a dot clock pulse generator (3) for dividing said basic clock pulse oscillating frequency in synchronism by the output of said horizontal synchronous signal detector, and for supplying a clock pulse (14) for sampling said display data. A sampling clock pulse generator according to Claim 1, wherein said horizontal synchronous signal detector (2) detects said horizontal synchronous signal (11) by the clock pulse from said basic clock pulse generator. A sampling clock pulse generator according to Claim 2, wherein said horizontal synchronous signal is converted to a pulse which is synchronous with said basic clock pulse and corresponding to one period of said basic clock pulse. A sampling clock pulse generator according to Claim 1, wherein said horizontal synchronous signal (11) detector comprises a first D-flip-flop (21) having an input (D) terminal to which said horizontal synchronous signal is inputted and a trigger terminal (T) to which said basic clock pulse is inputted, a second D-flip-flop (22) having an input terminal to which an output of said first D-flip-flop is inputted and a trigger terminal to which said basic clock pulse is inputted, and a NAND gate to which an output of said second D-flip-flop and a negative output of said first D-flip-flop are inputted. A sampling clock pulse generator according to Claim 1, wherein said dot clock pulse generator includes a counter having synchronous reset function, so that said basic clock pulse is inputted to a clock input terminal of the counter, an output of said horizontal synchronous signal detector is inputted to a reset input terminal, and a dot clock pulse having a frequency equal to said dot frequency is sent from an output terminal. A sampling clock pulse generator according to Claim 1, wherein said basic clock pulse generator includes a crystal oscillator. A sampling clock pulse generator according to Claim 1, wherein said device of preparing image informations digitally processes display data, a display screen of said image display unit is flat, the sampling clock pulse generator is provided in a signal processing section of said image display unit, so that the clock pulse for sampling is sent to a display data sampling section provided in said signal processing section.

Inventors: YOSHIOKA, KAZUO C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1987
Main classification: G09G3
IPC codes: G09G3, H04N1, G09G5