Semiconductor memory device

Abstract: A semiconductor memory device having a memory cell array constituted by a plurality of memory cell blocks (11, 12) includes a clock generator unit constituted by a plurality of clock generator sections (61, 62), respective clock generator sections corresponding to respective ones of the memory cell blocks, and a block selector unit (53) for selecting one of the clock generator sections in correspondence with the row address of a designated address. Accordingly, only a clock generator section corresponding to the selected memory cell block is operated by the designated address, thereby enabling power consumption in the device to be reduced.

Description: The present invention relates to a semiconductor memory device which may be used, for example, in a dynamic random access memory. In previously-proposed semiconductor memory devices, a memory cell array is sometimes constituted by a plurality of memory cell blocks. In such devices, it is possible to keep the memory cell blocks which do not include the selected word line in the inactive state so that the consumption of electric power of the device is reduced. However, in some such previously-proposed devices, only some of the memory cell blocks are kept in the inactive state due to a non-selection thereof, and the clock generator which is provided in common for the plurality of memory cell blocks is always in operation to supply clock signals such as word line activation clock signals to all of the plurality of memory cell blocks. Hence, the reduction of the electric power consumption may not be satisfactorily attained in such devices. With a view to overcoming this disadvantage of the prior art, the applicants previously proposed in EP-A-0068893 that an independently-operable clock generating circuit be provided for each memory cell block. In particular, EP-A-0068893 discloses a semiconductor memory device comprising: an array of memory cells divided into a plurality of memory cell blocks; a plurality of row selection circuits operatively connected to respective memory cell blocks and arranged to receive an address signal indicative of a memory cell to be accessed during an accessing operation; column decoder circuitry operatively connected to said plurality of memory cell blocks and arranged to receive the said address signal; the row selection circuit which is associated with the memory cell block containing the memory cell to be accessed and said column decoder circuitry being operable, upon receipt respectively of a row selection circuit activation signal and a column decoder activation signal, to select respectively, in accordance with said address signal, a row and a column within said memory cell block; clock signal generating means connected to said row selection circuits and said column decoder circuitry and operable to generate said row selection circuit activation signal and said column decoder activation signal, which means include a plurality of clock signal generating circuits connected to respective row selection circuits and selectively operable individually to produce said row selection circuit activation signal and to supply that signal to the row selection circuit associated therewith; and block selection means connected to each of said clock signal generating circuits and arranged to receive said address signal, said means being operable at the commencement of an accessing operation to select, in dependence upon that address signal, that one of the clock signal generating circuits which serves the row selection circuit associated with the memory cell block to which the memory cell to be accessed belongs, which clock signal generating circuit is thereby caused to deliver said row selection circuit activation signal to the row selection circuit associated therewith, so activating during said accessing operation only that one of the row selection circuits which is associated with the memory cell block containing the memory cell to be accessed. However, it is desirable to reduce the power consumption of such of a device still further. An additional difficulty, in a large capacity semiconductor memory device, having a chip size of the order of 10 mm² or more, is that the length of the wiring for transmitting clock signals becomes large and accordingly, the parasitic capacitance of the wiring becomes large, so that a high speed operation of the device may be difficult to attain. Also the consumption of electric power can become large, and an IR drop caused by the resistance of the wiring can become significant. According to the present invention there is provided a semiconductor memory device comprising: an array of memory cells divided into a plurality of memory cell blocks; a plurality of row selection circuits operatively connected to respective memory cell blocks and arranged to receive an address signal indicative of a memory cell to be accessed during an accessing operation; column decoder circuitry operatively connected to said plurality of memory cell blocks and arranged to receive the said address signal; the row selection circuit which is associated with the memory cell block containing the memory cell to be accessed and said column decoder circuitry being operable, upon receipt respectively of a row selection circuit activation signal and a column decoder activation signal, to select respectively, in accordance with said address signal, a row and a column within said memory cell block; clock signal generating means connected to said row selection circuits and said column decoder circuitry and operable to generate said row selection circuit activation signal and said column decoder activation signal, which means include a plurality of clock signal generating circuits connected to respective row selection circuits and selectively operable individually to produce said row selection circuit activation signal and to supply that signal to the row selection circuit associated therewith; and block selection means connected to each of said clock signal generating circuits and arranged to receive said address signal, said means being operable at the commencement of an accessing operation to select, in dependence upon that address signal that one of the clock signal generating circuits which serves the row selection circuit associated with the memory cell block to which the memory cell to be accessed belongs, which clock signal generating circuit is thereby caused to deliver said row selection circuit activation signal to the row selection circuit associated therewith, so activating during said accessing operation only that one of the row selection circuits which is associated with the memory cell block containing the memory cell to be accessed; characterised in that said column decoder circuitry comprises a plurality of column decoders connected to respective memory cell blocks, and in that said clock signal generating circuits are also connected respectively to the column decoders such that each such circuit is connected to the column decoder and row selection circuit associated with the same memory cell block, and are operable individually, when selected by said block selection means, to produce said column decoder activation signal and to supply that signal to the column decoder associated therewith. In the device of EP-A-0068893, a pair of memory cell blocks sharing a common column decoder are provided, the clock signal circuitry serving the column decoder being separate from that serving the row selection circuits. In contrast, in a device embodying the present invention, each memory cell block has its own column decoder which is controlled by the clock signal generating circuit associated with the row selection circuit for that block. Since only the column decoder for the memory cell block containing the memory cell to be accessed is activated, power consumption in the device is reduced as compared to that in the device of EP-A-0068893. Reference will now be made, by way of an example, to the accompanying drawings, in which: Fig. 1 shows a previously-proposed semiconductor memory device; Fig. 2 shows a structure of a clock generator in the device of Fig. 1; Fig. 3 shows a semiconductor memory device embodying the present invention; Fig. 4 shows the structure of a clock generator in the device of Fig. 3; Fig. 5 shows the structure of a block selector in the device of Fig. 3; Fig. 6 shows the structures of a row decoder and word driver in the device of Fig. 3; and Fig. 7 shows a modified device embodying the present invention. Before describing a typical embodiment of the present invention, a previously-proposed semiconductor memory device will be explained with reference to Figs. 1 and 2. The structure of the clock generator in the device of Fig. 1 is shown in Fig. 2. The device of Fig. 1 is constructed by a No. 1 memory cell block 11, No. 2 memory cell block 12, word drivers 411, 412, row decoders 421, 422, sense amplifier and input/output circuits 21, 22, column decoders 31, 32, clock generation portion 6 having an address drive generator 6A, block selector 6B and clock generator 6C, write clock generator 7, data input buffer 81, and data output buffer 82. The clock generation portion 6 receives a chip activation signal S( CE ), and a clock signal S(AD) from the clock generation portion 6 is supplied to the address buffer 52. The external address bits A₀ , A₁ , A₂ , ... A n are latched in the address buffer 52. In the address buffer 52, the MOS level address bits a₀ , a₁ , a₂ , ... a n and the inverted MOS level address bits a₀ , a ₁ , a₂ ... a n are produced from the external address bits A₀ , A₁ , A₂ ... A n , and the produced signals are supplied to the column decoders 31, 32 and the row decoders 421, 422. A clock signal S(WD) for activating word lines from the clock generation portion 6 is supplied to the word drivers 411 and 412. A clock signal S(LE) for resetting bit lines from the clock generation portion 6 is supplied to the sense amplifier and input/output circuits 21 and 22, to precharge the bit lines. A clock signal S(CD) for activating bit lines from the clock generation portion 6 is supplied to the column decoders 31 and 32. The write clock generator 7 supplies the write clock signal S(7) to the data input buffer 81 in response to a write enable signal S(WE). The input data D(IN) in the data input buffer 81 is supplied to the sense amplifier and input/output circuits 21 and 22 in accordance with the write clock signal S(7). The clock generator 6C includes a sequence of buffers: BUFFER-1, BUFFER-2, BUFFER-3, ... BUFFER-X. Each of the buffers produces a predetermined clock signal such as S(AD), S(WD), S(LE), S(OB) or the like with a predetermined delay time. A semiconductor memory device embodying the present invention is shown in Fig. 3. The structures of the clock selector and the block selector in the device of Fig. 3 are shown in Figs. 4 and 5, respectively. The semiconductor memory device of Fig. 3 is constructed from a No. 1 memory cell block 11, No. 2 memory cell block 12, word drivers 411, 412, row decoders 421, 422, sense amplifier and input/output circuits 21, 22, column decoders 31, 32, address drive generator 51, address buffer 52, block selector 53, No. 1 clock generator 61, No. 2 clock generator 62, write clock generator 7, data input buffer 81, and data output buffer 82. The address drive generator 51 receives the chip activation signal S( CE ), and supplies the clock signal S(AD) to the address buffer 52. The external address bits A₀ , A₁ , A₂ ... A n are latched in the address buffer 52. In the address buffer 52, the MOS level address bits a₀ , a₁ , a₂ , ... a n and the inverted MOS level address bits a₀ , a₁ , a₂ , ... a n are produced from the external address bits A₀ , A₁ , A₂ , ... A n , and the produced signals are supplied to the column decoders 31, 32, and the row decoders 421, 422. The clock generators 61, 62 are associated with respective ones of the memory cell blocks 11, 12. Clock signals S(WD) for activating word lines are supplied to the word drivers 411 and 412 by the No. 1 clock generator 61 and the No. 2 clock generator 62 respectively. Clock signals S(LE) for resetting bit lines are supplied by the clock generators 61 and 62 to the sense amplifier and input/output circuits 21 and 22 respectively to precharge the bit lines. Clock signals S(CD) for activating bit lines are supplied to the column decoders 31 and 32 from the clock generators 61 and 62 respectively. The write clock generator 7 supplies the write clock signal S(7) to the data input buffer 81 in response to a write enable signal S(WE). The input data D(IN) in the data input buffer 81 is supplied to the sense amplifier and input/output circuits 21 and 22 in accordance with the write clock signal S(7). The block selector 53 receives from the address buffer 52 a signal S() representing a portion of the row address, for example, the uppermost bit of the row address, and selects either the No. 1 clock generator 61 by supplying a signal S(₁) thereto or the No. 2 clock generator 62 by supplying a signal S(₂) thereto in accordance with the information of the portion of the row address. In the operation of the device of Fig. 3, both the row decoders 412 and 422 are activated. However, only one of the word drivers 411 and 412 is activated in accordance with the selection between the No. 1 clock generator 61 and the No. 2 clock generator 62. The structure of the No. 1 and No. 2 clock generators is shown in Fig. 4, and the structure of the block selector 53 is shown in Fig. 5. As shown in Fig. 4, the No. 1 clock generator 61 includes the series connected buffers: BUFFER-2, BUFFER-3, BUFFER-4, and so on. Each of these buffers operates with a predetermined delay time. The No. 2 clock generator 62 includes similar series connected buffers. As shown in Fig. 5, the block selector 53 is constructed from a series connection of a NAND gate and an inverter. One input terminal of the NAND gate receives the signal S() from the address drive generator, while the other input terminal receives address bits a n and a n from the address buffer 52. The address bits a n and a n are the MOS level address bits converted from the external address A n . When A n is at a HIGH level, a n is at a HIGH level, and a n is at a LOW level. The selection signal S(₁) or S(₂) is delivered from one of the inverters of the block selector 53. The characteristic of the capacitance distribution in the word driver 411 in the device of Fig. 3 will be explained with reference to Fig. 6, which shows the structures of the row decoder 421 and the word driver 411 in the device of Fig. 3. The word driver 411 is constructed from flip-flop circuits. The signal S(WD1) and the signal S(WD2) are supplied as a power source voltage to one branch of the flip-flop circuits. The outputs of the row decoder 421 are supplied to the gates of the transistors in the one branch of the flip-flop circuits. The reset clock signals S(R1) and S(R2) are supplied to the gates of the transistors in the other branch of the flip-flop circuits. In the word driver 411 of the device of Fig. 3, the portions ℓ(1a) and ℓ(2a) of the wirings ℓ(1) and ℓ(2) do not exist. Since there are no wirings of the portions ℓ(1a) and ℓ(2a), the parasitic capacitance of the entire wiring is reduced accordingly. Therefore, the entire parasitic capacitance of the wirings is reduced in the device of Fig. 3. Accordingly, the operation speed of the device is enhanced and the consumption of electric power is reduced in the device of Fig. 3. Contrary to this, if the portions ℓ(1a) and ℓ(2a) exist as in the case of the prior art device, a considerably large parasitic capacitance of the wiring is formed, and this formed parasitic capacitance is added to the drain capacitances of the transistors of the flip-flop circuits in the word driver. This large capacitance requires a considerably large capacity of the power source, and constitutes a disadvantage of the prior art. In the device of Fig. 3, the parasitic capacitances of the wirings for transmitting the signals S(WD), S(LE), and the like from the clock generators 61 and 62 (Fig. 4) are reduced, and thus the charge/discharge current is reduced, and the time of charge/discharge is reduced. Also, the capacity requirement for the buffers: BUFFER-2, BUFFER-3, etc., is reduced. Only one of the clock generators is required to operate so that the consumption of electric power is reduced. Although a typical embodiment of the present invention is explained with reference to Figs. 3 to 6 in which the division by 2 of the cell blocks is realized, other embodiments of the present invention are possible in which the division by 4, 8, 16, or the like of the cell blocks is realized. Also, although in the device of Fig. 3 the division is realized only in the row decoder side, it is also possible to realize the division not only in the row decoder side but also in the column decoder and input-output side. The clock generator should be divided in correspondence with such division in the column decoder and input-output circuit side. A semiconductor memory device according to a modified embodiment of the present invention is shown in Fig. 7. In the device of Fig. 7, the memory cell block is divided into m divisions along the row direction and n divisions along the column direction, to consequently attain m x n divisions. The block selector 53 delivers the clock signals S(₁₁), S(₂₁), ... S( m1 ; S(₁₂), S(₂₂), ... S( m2 ); ... S( 1n ), S( 2n ), ... S( mn ) which are supplied to the clock generators No. 11, No. 21, ... No. m1; No. 12, No. 22, ... No. m2; ...; No. 1n, No. 2n, ... No. mn. For example, the No. 11 clock generator delivers the signals for the No. 11 cell block, and the No. mn clock generator delivers the signal for the No. mn cell block.

Claims: A semiconductor memory device comprising: an array of memory cells divided into a plurality of memory cell blocks (11; 12); a plurality of row selection circuits (411,421; 412,422) operatively connected to respective memory cell blocks (11; 12) and arranged to receive an address signal (a₀,...,a n ) indicative of a memory cell to be accessed during an accessing operation; column decoder circuitry (31,32) operatively connected to said plurality of memory cell blocks (11; 12) and arranged to receive the said address signal (a₀,...,a n ); the row selection circuit (411,421; 412,422) which is associated with the memory cell block (11; 12) containing the memory cell to be accessed and said column decoder circuitry (31,32) being operable, upon receipt respectively of a row selection circuit activation signal (S(WD)) and a column decoder activation signal (S(CD)), to select respectively, in accordance with said address signal (a₀,...,a n ), a row and a column within said memory cell block (11; 12); clock signal generating means (61,62) connected to said row selection circuits (411,421; 412,422) and said column decoder circuitry (31,32) and operable to generate said row selection circuit activation signal (S(WD)) and said column decoder activation signal (S(CD)), which means (61,62) include a plurality of clock signal generating circuits (61; 62) connected to respective row selection circuits (411,421; 412,422) and selectively operable individually to produce said row selection circuit activation signal (S(WD)) and to supply that signal (S(WD)) to the row selection circuit (411,421; 412,422) associated therewith; and block selection means (53) connected to each of said clock signal generating circuits (61; 62) and arranged to receive said address signal (a₀,...,a n ), said means being operable at the commencement of an accessing operation to select, in dependence upon that address signal (a₀,...,a n ), that one of the clock signal generating circuits (61; 62) which serves the row selection circuit (411,421; 412,422) associated with the memory cell block (11; 12) to which the memory cell to be accessed belongs, which clock signal generating circuit (61; 62) is thereby caused to deliver said row selection circuit activation signal (S(WD)) to the row selection circuit (411,421; 412,422) associated therewith, so activating during said accessing operation only that one of the row selection circuits (411,421; 412,422) which is associated with the memory cell block (11; 12) containing the memory cell to be accessed; characterised in that said column decoder circuitry (31,32) comprises a plurality of column decoders (31; 32) connected to respective memory cell blocks ((11; 12), and in that said clock signal generating circuits (61; 62) are also connected respectively to the column decoders (31; 32), such that each such circuit (61; 62) is connected to the column decoder (31; 32) and row selection circuit (411,421; 412,422) associated with the same memory cell block (11; 12), and are operable individually, when selected by said block selection means (53), to produce said column decoder activation signal (S(CD)) and to supply that signal (S(CD)) to the column decoder (31; 32) associated therewith. A device as claimed in claim 1, wherein said block selection means (53) are operable to produce a plurality of selection signals (S(₁); S(₂)) for delivery respectively to said clock signal generating circuits (61; 62), which selection signals (S(₁); S(₂)) are such that only the clock signal generating circuit (61; 62) to be selected is activated. A device as claimed in claim 2, wherein said block selection means (53) comprise a plurality of selection signal generating circuits for respectively providing the said selection signals (S(₁); S(₂)), each selection signal generating circuit being constituted by a NAND gate connected in series with an inverter. A device as claimed in claim 3, wherein in each of the selection signal generating circuits said NAND gate has a first input terminal connected to receive an operating signal (S()) from an address drive generator (51) of the device, and a second input terminal connected to receive address bits (a₀,...,a n ) from an address buffer (52) of the device. A device as claimed in any preceding claim, wherein each of said clock signal generating circuits (61; 62) comprises at least two buffers (BUFFER-2, BUFFER-3,...) connected together in series such said row selection circuit activation signal (S(WD)) and column decoder activation signal (S(CD)) are provided at preset times at respective output nodes of the said buffers (BUFFER-2, BUFFER-3,...). A device as claimed in any preceding claim, wherein each of said clock signal generating circuits (61; 62) is also operable to produce clock signals for use in input/output circuitry (81/82) and sense amplifier circuitry (21; 22) of the device.

Inventors: NAKANO TOMIO, OHIRA TSUYOSHI, NAKANO, TOMIO, OHIRA, TSUYOSHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1987
Main classification: G11C8
IPC codes: G11C11, G11C7, G11C8