A PROCESS FOR FORMING VIAS ON INTEGRATED CIRCUITS

Abstract: In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a predetermined via pattern with a second etchant which reacts with the second metal and which is substantially unreactive with the first metal. The first metal layer is then etched with a first etchant which reacts with the first metal and which is substantially unreactive with the second metal or with the semiconductor substrate in order to form a pre-­ determined contacting relationship with the predetermined via pattern. This process may be used to generate second and subsequent levels of vias and interconnects which can be used to contact metal layers at any level directly to the substrate by building via posts from the substrate to any desired metal layer.

Description: This application is a continuation-in-part of co-pending United States patent application Serial Number 644,028, filed August 23, 1984. This invention is related to the fabrication of multilevel interconnects for integrated circuits and more particularly to the formation of vias for selectively providing electrical interconnections between selected levels of the multilevel structure. Integrated circuits include a multiplicity of semiconductor devices which are disposed substantially co-planar with respect to one another on a silicon wafer. In order to have a functioning circuit, it is necessary to electrically interconnect the electrical contact regions of these devices. Electrical interconnections, depending on the complexity of the circuit, may require duplication of devices, extensive or complex routing of the interconnects, or both. Such requirements adversely affect circuit densification by utilizing more area than would be necessary if the interconnects were able to be routed without consideration of overlapping metal lines. It is of course possible to route interconnects over one another without making contact by constructing multilevel integrated circuit devices comprising two or more levels of interconnects separated by a dielectric layer. When constructing such devices, vertical interconnects, sometimes known as vias, are required in order to route signals and signal returns from one level of planar interconnects to another. As device densification on the integrated circuits becomes greater, alignment of metal to contacts and vias becomes more and more critical. This is due to the fact that greater device density necessarily causes a concomitant increase in contact and interconnect density. Consequently, when it is required to electrically connect a particular contact or interconnect disposed on the substrate to a particular interconnect on the next higher level or to electrically connect two particular interconnects between levels, precise alignment of the vias is mandatory. Misalignment could cause unwanted short circuits between interconnects or between a contact and an interconnect. In addition to short circuits, a misalignment may also create a marginal electrical contact between the via and the interconnect thereby creating a region of increased current density, a defect which can be potentially fatal to the operation of the circuit. Furthermore, utilizing the prior art technique of via formation which entails deposition of the via material into an aperture etched through the dielectric material separating the interconnect levels, misalignment of the via apertures may cause over etching of the dielectric down to the proximity of the surface of the semiconductor substrate, if not actually into the substrate. Subsequent deposition of the via metal into the aperture could then create defects due to punch through or contamination of the substrate material. One method of compensating for via misalignment consists of forming pads or nests which are enlargements of the width of the planar interconnects at the approximate via locations. Consequently, the larger the pad or nest, the greater the via misalignment which can be tolerated. Creation of such pads or nests itself has an adverse affect on densification since these enlarged portions of the interconnect preclude closer spacing between interconnects. Furthermore, placing a metal interconnect line across a contact hole exposing a device contact region, allowance must be made for possible misalignment of the metal line position with respect to the hole, so that the hole will not be uncovered and partially, or even fully in extreme misalignments, exposed to the etches that are used to create the metal interconnect line pattern. This has required in the past that the the metal line width in the vicinity of the hole include a certain fraction of width beyond the electrical requirements of the interconnect line, this fraction being at least equal to the expected maximum misalignment of the line. This additional width increases the minimum line center to line center spacing that is possible in laying out geometries of the metal interconnection lines. This may be shown by referring to Figure 13 which depicts metal structures that schematically represent present requirements. As shown in Figure 13, a "dog bone" structure 702, which is an enlargement of the interconnect line 704, is designed to completely surround the contact region 706 by overlying metal in order to ensure that the contact region 706 is not exposed to etchant used to form the interconnect lines 704. Consequently, the line center to line center distance is equal to w 2 +a+d+ w 2 ; where w is the required width of a metal interconnect line, a is the misalignment allowance, and d is the required separation of the metal lines. Consequently, it can be seen that the misalignment allowance, a, increases the necessary line to line spacing. Accordingly, it is an object of the present invention to provide a method for forming vertical interconnects in multilevel metallization for integrated circuits which are substantially self aligning. The process defined by patent claim 1 addresses this problem. It is to be noted that EP-A-0 175 604 which discloses steps (a) through (d) forms prior art under the provisions of Art. 54(3) and (4) EPC. The process of the present invention distinguishes over this prior art by the steps (c1) and (c2). The process of the present invention aims at the formation of posts in an integrated circuit which includes a semiconductor substrate having an insulating layer formed thereover. The insulating layer has at least one device contact region defined therein. A layer of a first metal which is reactive to a first etchant but substantially unreactive with a second etchant is formed on the insulating layer and into the device contact regions. A layer of a second metal which is reactive with the second etchant but substantially unreactive with the first etchant is formed on the first metal layer. The second metal layer is then masked as required to form a predetermined post pattern with at least one defined post having an area which is at least equal to the area of the underlying device contact region and which is substantially aligned therewith in covering spacial relationship thereto. The posts are then formed by etching the unmasked portions of the second metal layer. Since the first metal layer is not reactive to the second etchant, etching will stop at the surface of the first metal layer. The first metal layer is then masked to form the desired interconnect pattern. The first metal layer is then etched using the first etchant. Since the second metal layer is non-reactive to the first etchant, the posts which were formed in the second metal layer are unaffected by the first etchant and furthermore serve as masks on the first metal layer thereby creating precise alignment between the posts constructed of the second metal with the interconnects constructed of the first metal and with the underlying device contact regions. Patent claims 2 and 3 define respectively two possible alternatives to implement the process as defined in patent claim 1. Figures 1 through 5A illustrate sequential cross-sectional views of yet a fabrication scheme for an integrated circuit employing an alternate preferred embodiment of the method of the present invention. Figure 6 is a top plan view of a segment of an integrated circuit as depicted in cross-section in Figure 5A. Figure 7 is a top plan view of a segment of an integrated circuit as depicted in cross-section in Figure 5B. Figure 8 is a top plan view of a segment of an integrated circuit as depicted in cross-section in Figure 5C. Figure 9 is a top plan view of a segment of an integrated circuit as depicted in cross-section in Figure 5D. Figure 10 is a top plan view of a segment of an integrated circuit as depicted in cross-section in Figure 5E. Figures 11A through 11D illustrate sequential cross-sectional view of still another fabrication scheme for an integrated circuit employing another alternate preferred embodiment of the present invention. Figure 12 is a top plan view of a segment of an integrated circuit as depicted in cross-section in Figure 11D. Figure 13 is a top plan view of a segment of an integrated circuit depicting misalignment tolerance in a prior art fabrication scheme. Figure 14 is a top plan view of a segment of an integrated circuit depicting the illumination of metal to contact misalignment tolerance in accordance with the present invention. Referring now to Figures 1 through 5A there is shown yet a fabrication scheme for multilevel interconnects for integrated circuits employing a preferred embodiment of the method of the present invention. Figure 1 shows a semiconductor substrate 102 having devices formed therein. A dielectric layer 104 is formed on the surface of the semiconductor substrate 102. It is preferred that the dielectric layer 104 comprise a silicon dioxide material which is formed to a thickness of approximately 7,000 Å (10 Å = 1 nm) preferably by the technique of chemical vapor deposition. A plurality of apertures 106 are formed in the dielectric layer 104 in predetermined spaced relation to the devices which have been formed in the silicon substrate 102 using any compatible masking technique; for example, optical imaging of a pattern into photoresist. A first metal layer 108 is formed over the dielectric layer 104 and into the apertures 106, preferably using a sputter deposition technique. However, physical vapor deposition or chemical vapor deposition can also be used. It is preferred that the first metal layer 108 comprise aluminum or aluminum alloys and is formed to a thickness substantially equal to 7,500 Å. A second metal layer 110 is formed over the first metal layer 108 preferably using a sputter deposition technique. However, physical vapor deposition or chemical vapor deposition (CVD) can also be used. It is preferred that the second metal layer 110 comprise tungsten which is formed to a thickness substantially equal to 7,500 Å. A layer of photoresist material 112 is then formed on the second metal layer 110 and is masked and patterned using conventional photoresist techniques to form a pattern of substantially parallel stripes 114 as shown in Figure 6 The stripe patterns 114 are segmented and disposed on the substrate in predetermined spacial relationship with the apertures 106 because they are used to form a portion of via posts as will be explained in detail later in this specification. The unpatterned photoresist is then developed to expose the second metal layer 110 which is etched down to the top surface of the first metal layer 108 in order to form a plurality of second metal stripes 116 as depicted in Figures 2 and 7, using reactive ion etching of tungsten with a fluorine based plasma, which will etch through the second metal 110 but will stop at the first metal 108. Next, as shown in Figure 3, a layer of photoresist material 118 is formed over the stripes 116 and first metal layer 108, then is masked and patterned using conventional photoresist techniques to form a pattern of interconnects 120, which pattern intersects the stripe segments 116 in plan view as shown in Figure 8. These intersections will form posted vias as will be subsequently described. The unpatterned photoresist material is developed and the exposed second metal areas are etched away down to the surface of the first metal layer 108 using reactive ion etching of tungsten with a fluorine based plasma, which will etch away the second metal but will stop at the first metal. The exposed areas of the first metal layer 108 are then etched using a second etchant which attacks the first metal but does not attack the second metal nor the material comprising the insulating layer 104. Since, in this embodiment, the first metal layer is aluminum or an aluminum alloy, the exposed areas of the first metal layer are etched using a reactive ion etching technique with a chlorine based plasma. As a result of this etching step, an interconnect pattern 122 having posted vias 124 disposed thereon is formed over the insulating layer 104 as depicted in Figures 4 and 9. As seen in Figure 9, the posted vias 124 are formed at the intersection of the interconnects 122 with the stripe segments 116. As a result, the posted vias 124 are automatically aligned with the interconnects 122. A layer of an insulating material, preferably S i O₂ is formed over the interconnects 122 and posted vias 124 using low pressure CVD, to a thickness of preferably 20,000 Å. The insulating layer 126 is then planarized as shown in Figure 5 using an etchback planarization process which exposes the top surfaces of the posted vias 124 (see also Figure 10). In order to construct a second level of interconnects, a third metal layer 128, preferably aluminum, is formed over the planarized surface of the second insulating layer 126 and the tops of the posted vias 124, using either sputtering, physical vapor deposition or CVD, to a thickness which is preferably 7,500-12,000 Å. The third metal layer will form electrical contact with the exposed top surfaces of the posted vies 124. If no additional levels are required, the third metal layer is etched into a predetermined interconnect pattern exposed in a layer of photoresist as is known in the art. This final level then can be coated with a dielectric for scratch protection in the conventional manner in order to complete the multilevel structure. If additional interconnect levels are desired, a fourth metal layer 130 is formed over the third metal layer and a layer of photoresist 132 is formed over the fourth metal layer 130 as set forth above in connection with Figure 5A. The second level of interconnects as well as a second set of posted vias, for electrically connecting the second level of interconnects to a third level of interconnects, are formed in accordance with the process described above. This process can be repeated until the desired number of interconnect levels has been achieved. As can be seen from the above description of the preferred embodiment of the process of the present invention, the via posts 124 are automatically aligned with the underlying interconnect pattern 122 even if the first mask is not precisely aligned with the second mask since the second metal itself acts as a mask to first metal etching because the posts occur at intersections between the first and second metals. Referring now to Figures 11A through 11D, there is shown yet another fabrication scheme for multilevel interconnects for integrated circuits employing yet another alternate preferred embodiment of the method of the present invention. Figure 11A shows a semiconductor substrate 502 having devices formed therein. A dielectric layer 504 is formed on the surface of the semiconductor substrate. It is preferred that the dielectric layer 504 comprise a silicon dioxide material which is formed to a thickness of approximately 7,000 Å preferably by the technique of chemical vapor deposition. A plurality of apertures 506 are formed in the dielectric layer 504 exposing contact regions of the devices which have been formed on the silicon substrate 502. The apertures 506 are formed in the dielectric layer 504 using any compatible masking technique; for example, optical imaging of a pattern into photoresist. A first metal layer 508 is formed over the dielectric layer 504 and into apertures 506, thereby making contact with the device contact regions exposed by the apertures 506. It is also preferred that the first metal layer 508 be formed by using a sputter deposition technique. However, physical vapor or chemical vapor deposition can also be used. It is preferred that the first metal layer 508 comprise aluminum or aluminum alloys and be formed to a thickness to 7,500 Å. A second metal layer 510 is formed over the first metal layer 508 preferably using a sputter deposition technique. However, physical vapor deposition or chemical vapor deposition (CVD) can also be used. It is preferred that the second metal layer 510 comprise tungsten which is formed to a thickness substantially equal to 7,500 Å. A layer of photoresist material 512 is then formed on the second metal layer 510 and is masked and patterned using conventional photoresist techniques to form a pattern of posts. Those posts which are defined above underlying contact regions, see for example 514 in Figure 11A, are dimensioned completely and encompass, including misalignment tolerance, the underlying aperture 506 and device contact region. The unpatterned photoresist is then developed to expose the second metal layer 510 which is etched down to the top surface of the first metal layer 508 in order to form a plurality of posts 516 as depicted in Figures 11B and 12, preferably using reactive ion etching of the tungsten with a fluorine based plasma, which will etch through the second tungsten metal layer 510 but will stop it the first aluminum metal layer 508. Next, as shown in Figure 11C, a layer of photoresist material 518 is formed over the posts 516 and the first metal layer 508, then is masked and patterned using conventional photoresist techniques to form a pattern 520, as indicated by the dotted lines in Figure 11C, of interconnects. The unpatterned photoresist material is developed and the exposed first metal areas are etched away down to the surface of the insulating layer 504 using a second etchant which attacks the first metal but does not attack the second metal or the material comprising the insulating layer 504. Since, in this embodiment, the first metal layer is aluminum or an aluminum alloy, the exposed areas of the first metal layer 508 are preferably etched using a reactive ion etching technique with a chlorine based plasma. As a result of this etching step, an interconnect pattern 522 having posts 516 disposed thereon is formed over the insulating layer 504, as depicted in Figures 11D and 12. The posts 516 function as masks during the second etching process. Since they completely encompass, including misalignment tolerance, the underlying apertures 506 in the insulating layer 504, and since they do not react with the second etchant, they prevent the second etchant from entering the apertures 506 and possibly exposing or otherwise damaging the device contact regions. The final interconnect level can be constructed by forming a single layer of the first metal over the exposed top surfaces of the underlying posts which layer is then etched in accordance with a predetermined pattern exposed in a layer of photoresist as is known in the art. This final level can then be coated with a dielectric for scratch protection in the conventional manner in order to complete the multilevel structure. As shown in Figure 14, when compared with the prior art depicted in Figure 13, the present invention continues to afford protection of the underlying contact regions while eliminating the need to include the misalignment allowance (a) between the line center to line center spacing thereby enabling the lines to be placed closer together by that amount. At the present time, a typical dimension for intermetal spacing (d) is approximately 2 microns while the misalignment allowance (a) typically equals one-half micron. In a large scale or very large scale integrated device, elimination of the half micron tolerance allowance between each adjacent interconnect line can add up to a significant saving in surface area thereby enabling the incorporation of more devices into the substrate. In addition to permitting closer spacing of the metal lines, use of this method protects the underlying structures from undesired metal etch in the event of misalignment. Furthermore, the posts which are formed to protect underlying contact regions are also useable as via posts and therefore do not add any process complexity. Another method of protecting against inadvertent etching of underlying contact regions is to provide a thin etch stop layer. For example, a thin layer of titanium, having a thickness of approximately 400 Å, is deposited over the exposed underlying contact regions. Next, a second thin layer, for example tungsten having a thickness of approximately 800 Å is formed over the titanium layer. Then, a first metal layer of aluminum is formed over the thin titanium/tungsten layers. This is followed by the formation of a second metal layer, for example, tungsten, over the aluminum layer. Etching of the tungsten and aluminum layers into their predetermined patterns would be performed as previously described. However, the thin titanium/tungsten layers would act as a etch stop against the etchant used to etch the aluminum layer. Similarly, when using tungsten as the first metal layer and aluminum as the second metal layer, a thin layer of aluminum, for example approximately 300 Å thick, could be utilized between the tungsten layer and the underlying exposed contact regions, as a etch stop layer. In this way, when etching the aluminum and tungsten layers into their predetermined patterns as previously described, the thin aluminum layer will act as in etch stop against the etchant used to etch the overlying tungsten layer. The final step in both of the above examples is to etch the thin etch stop layers. Although the etchant used to etch the etch stop layers would also etch the posts formed in the second metal layer, the amount of post material lost would be minimal due to the relative thinness of the etch stop layer. Although some post material would be lost, utilizing the thin barrier layer described above significantly reduces the adverse effects of misalignment to underlying contact regions. While the principles of the present invention have now been made clear in an illustrative embodiment according to claim 1, there will be immediately obvious to those skilled in the art many modifications of structure, arrangement, the elements, material and components used in the practice of the invention and otherwise, which are particularly adapted for specific environments and operating requirements without departing from those principles. The appended claims are, therefore, intended to cover and embrace any such modifications within the limits only of claim 1.

Claims: A process for forming vias in an integrated circuit, comprising the steps: (a) forming a layer of a first metal on a semiconductor substrate, (b) forming a layer of a second metal on said first metal layer, (c) etching said second metal layer with a second etchant which reacts with said second metal but is substantially unreactive with said first metal so as to form a predetermined via pattern, (d) etching said first metal layer with a first etchant which reacts with said first metal but is substantially unreactive with said second metal so as to form a predetermined interconnect pattern, characterised in that said step (c) comprises (c1) a preparatory etching step with said second etchant so as to form a preliminary pattern including via areas, and (c2) a final etching step with said second etchant so as to remove all portions of said second metal except said via pattern. The process of claim 1 wherein said preliminary pattern is the interconnect pattern and said etching steps are executed in the order (c1), (d), (c2). The process of claim 1 wherein said preliminary pattern is different from the interconnect pattern and step (c2) is executed with the interconnect pattern, the etching steps being executed in the order (c1), (c2), (d). The process of claim 1 additionally comprising the steps of: (e) forming a first dielectric layer over said interconnect and via patterns; and (f) forming a substantially planar surface on said first dielectric layer, which surface is substantially co-planar with the upper surfaces of said via pattern, by etching back said dielectric layer until at least the upper surface of said via pattern is exposed, using an etchant which reacts with said dielectric material but is substantially unreactive with said second metal, said exposed upper surfaces forming via contact regions. The process of claim 4 additionally comprising the steps of: (g) forming a third layer of said first metal on said planar surface in contact with said via contact regions; (h) etching said third layer in a second predetermined interconnect pattern; and (i) forming a layer of dielectric material over said second predetermined interconnect pattern and said first dielectric layer. The process of claim 4 additionally comprising the steps of: (g) forming a third layer of said first metal on said planar surface in contact with said via contact region; (h) forming a fourth layer of said second metal on said third layer; (i) etching said fourth layer, with said second etchant, in a second predetermined via pattern with at least one via having an area which is at least substantially equal to the area of an underlying via contact region and which is substantially aligned therewith in covering spacial relationship thereto; and (j) forming a second set of vias in predetermined spacial relationship with a second predetermined interconnect pattern by etching said third layer, in said second predetermined interconnect pattern, with said first etchant. The process of claim 6 additionally comprising the steps of: (k) repeating step (e) with respect to said second pattern; and (l) repeating step (f). The process of claim 7 wherein steps (g) through (l) are repeated at least once to form at least a third set of vias and at least a third predetermined interconnect pattern and additionally comprising the steps of: (m) forming a top layer of said first metal on the uppermost planar surface; (n) etching said top layer in a final predetermined interconnect pattern; and (o) forming a top layer of dielectric material over said final predetermined interconnect pattern and the uppermost dielectric layer.

Inventors: BROWN, ROBERT L., THOMAS, MICHAEL E.
Applicants: FAIRCHILD SEMICONDUCTOR CORPORATION
Application year: 1987
Main classification: H01L21
IPC codes: H01L21