SEMICONDUCTOR STRUCTURE WITH A MULTILAYER CONTACT

Abstract: A multilayer contact is shown having two superimposed conductive layers (14, 16) separated by a barrier layer (15) a first contact (11) extends through the upper conductive layer (14) to the lower conductive layer (16). A second contact (21, 30) separated from the first contact (11) extends to the upper conductive layer (14). A Schottky contact (18, 19) arranged between both contacts (11; 21, 30) on the surface of the upper conductive layer (14) establishes a depletion region (19) within the upper conductive layer (14). Said depletion region (19) electrically controls the current flow path between both contacts (11; 21, 30).

Description: This invention relates to semiconductor devices and, in particular, to a semiconductor device with a multilayer contact. Semiconductor devices, such as transistors, can consist of multiple layers of semiconducting or insulating materials. In a vertical transistor there are at least three layers including an emitter, base and collector. Charge carriers, either holes or electrons or both, pass from the emitter, through the base, to the collector. A metallic contact is deposited on each of the layers for operating the transistor. Horizontal or field effect transistor are also multilayer devices. The source, gate and drain each have a metallic contact on a common, upper surface. The gate may include a Schottky barrier that creates a depletion layer to control the transfer of charges that flow underneath the gate from the source to the drain. Recent developments in semiconductor have produced multilayer heterojunction devices. These devices, either vertical or horizontal transistors, are typically fashioned from alternate layers of gallium arsenide (Ga As) and aluminum gallium arsenide (Al Ga As). Under voltages suitably applied to such a device, a thin, high mobility region is formed at the junction of such materials. This region, in a horizontal transistor, is termed a two dimensional electron gas or 2 DEG. Electrons that enter a 2 DEG can move very quickly. Such quick motion gives such transistors a switching speed almost four-times as fast as other transistors. In horizontal high mobility devices, such as field effect transistors, it is known to place a source and a drain contact on a common upper surface. A Schottky barrier, as a gate, is positioned between source and drain and on the upper surface. The gate controls the flow of charges in the 2 DEG between source and drain by depleting the 2 DEG beneath the gate electrode. See, for example, U.S. Patent Nos. 4,558,337; 4,471,367 and 4,455,564. The source and drain contacts are both on the upper layer and do not extend to other layers. Vertical high mobility devices are more difficult to fabricate. They comprise very thin layers that have to be precisely deposited or etched to expose lower layers for forming ohmic contacts. A thickness of 20 nm is typical to some layers. Molecular beam epitaxial deposition equipment can deposit such thin layers. However, it is difficult to fix metal contacts on devices with such thin layers. Moreover, it is desirable in some applications e.g. oscillators, to switch the conduction path between different layers. As such, it would be desirable to have a device with a metallic contact selectively connectable to two or more layers, i.e. a multilayer contact. Such a contact could extend from an upper surface through to a desired lower layer. Such a contact would reduce the need for precise etching of intermediate, thin layers to expose the contact layer for receiving the metal contact. EP-A-0 193 842 discloses an integrated semiconductor circuit comprising an inner layer of semiconductor material of one conductivity type contiguous with a substrate layer of semiconductor material of the opposite conductivity type and an outer layer of semiconductor material of the opposite conductivity type contiguous with the inner layer. There are a first ohmic contact to a first region of the outer layer, a second ohmic contact to a first region of the inner layer, and a third common ohmic contact to both a second region of the outer layer and a second region of the inner layer. Control means varies conduction between the first and second regions of the outer layer. Thus this structure forms an inverter circuit consisting of a FET serially connected with a load. The FET is formed in the outer layer whereas the load is formed by the inner layer. The invention as claimed in claim 1 provides an apparatus for independently contacting various layers of a device with a single contact. A first high conductivity region or contact extends through the surface of the device to a lower layer of the device. A second high conductivity region or contact is separated form the first region or contact and extends from the surface of the device to another layer adjacent the surface. A carrier depletion control means, such as a Schottky barrier is deposited on the surface of the device between the first and second high conductivity regions or contacts. The control means operates to deplete carriers from a region between the two contacts and thereby control the conductivity of part of one layer so that two layers may be contacted independently. Hence, separate contacts are provided for two vertically separate layers without the need for providing a separate insulating material on the surface layer between the contacts or for physically removing material form the upper layer to expose the lower layer for receiving a metallic contact. As such, the invention is especially useful in vertical, heterojunction, single carrier devices such as ballistic or tunneling hot electron transfer amplifier (THETA) devices. Electrical contact to various layers is maintained even though the layers are as thin as 20 nm. Such a technique could be used to further reduce the overall dimension of a device since thin layers of 20 nm or less can be used to separate conductors. The invention could further the development of a three-dimensional or stacked microprocessor since interlayer metallic contact is feasible. One way of carrying out the invention is described in detail below with reference to the drawings in which: Fig. 1 is a cross-sectional view of one preferred embodiment of the invention; Fig. 2 is a graph of the voltage and current characteristics of a structure of the invention. A structure 10 in Fig. 1 generally shows the features of the invention. A first region of high conductivity or a metallic alloy contact 11 extends through an electrode 12 and conductive layer 14 through a barrier layer 15, and into conducting layers 16 and 17. A second region of high conductivity or metallic alloy contact 30 extends into an upper electrode 21 deposited on conductive layer 14. Electrodes 12 and 21 are formed of n⁺ doped Ga As. Each electrode 12, 21 is approximately 200 nm thick and its doping is 5 × 10¹⁸/cm³. Electrodes 12, 21 extend from a common upper surface 25 to conductive layer 14. Layer 14 lies underneath electrodes 12, 21 and comprises approximately 100 nm of Ga As doped n⁻ in the order of 1 × 10¹⁷/cm³. Beneath layer 14 is layer 15, a barrier layer separating conducting layers 14 and 17. It is shown as a 200 nm layer of Al Ga As. Conducting layer 17 is formed of Ga As. The lower conducting layer, layer 16 is a 200 nm layer of modulation doped Al Ga As. Due to the alignment of the conduction bands of Ga As and Al Ga As at the heterojunction between layers 17 and 16 a high mobility 2 DEG 17 is formed in layer 17. However, if a 2 DEG is not required, layer 17 could be a heavily doped layer of Ga As and layer 16 could be omitted or replaced by undoped Al Ga As. A depletion control means comprising a Schottky barrier electrode 18 is deposited on upper surface 28 of layer 14 between electrodes 12 and 21. When suitably biased, the depletion control electrode 18 generates a depletion region 19 in layer 14. The boundary of depletion region 19 is shown by dashed line 20. By adjusting the bias voltage applied to electrode 18, the boundary 20 can be extended to layer 15, thereby effectively electrically isolating the portion of layer 14 that underlies electrode 12 from the rest of layer 14. In this manner, contact 11 is isolated electrically from contact 21. The device 10, thus has a two-layer contact 11 that is in contact with a lower layer 17 and selectively connectable to electrode 21 through layer 14 or 17. Hence, a bias of one voltage can be applied to electrode 21 and a bias of another voltage can be applied to layer 16. Electrode 21 and the underlying portion of layer 14 can be kept electrically isolated from layer 16 by a suitable control voltage imposed on control electrode 18. Alternatively, the electrode 21 and layer 16 can be electrically connected by altering the voltage on control electrode 18 to reduce the depletion region 19. Thus, a lower layer 16 can be connected independently from the contacting of upper layer 14 without precision etching of upper layer 14 and layer 15 to expose layer 16. The structure of Fig. 1, in operation, can be used to provide an output of ohmic characteristic or the characteristic determined by layers 15, 16 and 17. For zero bias voltage on electrode 18, current will flow between contacts 11 and 30 in accordance with the simple formula of V=IR. The resistance, R, can be effectively increased by applying a bias voltage to electrode 18. However, when the depletion region expands to layer 15, normal ohmic current will be cut off. Thereafter, the I/V characteristic of the device will be different. It may have a negative resistive characteristic. That characteristic will depend upon the materials comprising layers 15, 16 and 17 and the effects of the 2 DEG layer. Such a dual characteristic device is especially useful to fabricate oscillators. Such a dual characteristic is shown in Fig. 2, where I is current between contacts 11, 30 and V is the voltage between those contacts. Two curves, or characteristics, 40, 42 are shown. When the bias voltage on electrode 18 is below a threshold value, the device of structure 10 will demonstrate an ohmic characteristic, 40. Past the threshold value, the depletion region 19 electrically isolates layer 14 from 17, and a second characteristic 42 is demonstrated. Such a dual characteristic device is useful as an amplifier or an oscillator since it has two discrete valves (I₁, I₂) as a function of the bias on electrode for a given voltage (V₀). Those skilled in the art will appreciate that the invention makes possible the separation of active layers with a common electrical contact. Such a feature could be used to further reduce the size of a semiconductor device since separation may be made by means of a thin molecular epitaxially deposited layer.

Claims: A semiconductor structure having a plurality of superimposed layers essentially parallel to an exposed surface and providing a separate ohmic contact to layers containing charge carriers, comprising in combination: an AlGaAs modulation doped substrate (16), a layer of undoped GaAs (17) epitaxially deposited on said substrate for generating a two dimensional electron gas (2 DEG) layer in said undoped epitaxial layer (17), a layer of undoped AlGaAs (15) provided on said undoped GaAs layer (17), a layer of doped GaAs (14) epitaxially deposited on said undoped AlGaAs layer (15); a first high conductivity region (11) extending through the surface of said doped GaAs layer (14) to said substrate (16) and in electrical contact with the doped GaAs layer (14) and the substrate layer (16); a second high conductivity region (21, 30), laterally spaced from the first high conductivity region (11) and in electrical contact with said doped GaAs layer (14); an electrode (18) on the surface of said doped GaAs layer (14), said electrode being positioned between the two high conductivity regions (11; 21, 30) for depleting charge carriers beneath the electrode (18) when a voltage is applied to said electrode whereby independent contact is made to the substrate (16) and the doped GaAs layer (14). The semiconductor structure of claim 1 wherein said first and second high conductivity regions comprise first and second metallic alloy contacts (11, 21). The semiconductor structure of claim 1 or 2 wherein said electrode (18, 20) comprises a Schottky barrier. The semiconductor structure of claims 1 to 3 wherein said doped GaAs is n-doped. The semiconductor structure of claims 1 to 3 wherein said doped GaAs is p-doped.

Inventors: SMITH III, THEOREN P.
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: H01L29
IPC codes: H01L29, H01L21, H01L23