VIDEO MEMORY

Abstract: A video memory, for use with a video tape recorder, a television receiver of the like to process a picture, is simplified and can achieve the functions of a time base corrector, a noise reduced and a comb filter, so as to considerably improve the quality of a video picture. A frequency converting circuit for use with the video memory includes a comparator (30) for comparing first and second address signals and an address correction circuit (38) connected to receive an output signal from the com­ parator (30). When a crossing occurs between the first and second address signals, the sequential order in which an address signal is supplied to the memory (12) is switched by the address correcting circuit (38), to thereby derive a continuous output signal from the memory (12).

Description: This invention relates to a video memory apparatus for use with a video tape recorder, a television receiver or the like to process a video signal. A prior art video memory apparatus for processing a video signal is shown in Fig. 1. Referring to Fig. 1, a video signal is applied to an input terminal 1 and this video signal is then supplied to a multiplier 2 in which it is multiplied by a coefficient K (K < 1). The output signal from the multiplier 2 is supplied through an adder 3 to a frame delay circuit 4 in which it is delayed by a delay time of one frame period. The output signal from the frame delay circuit 4 is supplied to a multiplier 5 in which it is multiplied by a coefficient 1 - K. The output signal from the multiplier 5 is supplied to the adder 3 in which it is added with the output signal from the multiplier 2. The output signal from the frame delay circuit 4 is supplied through a first-in-first-out memory (hereinafter simply referred to as FIFO) circuit 6 to an output terminal 7. The multiplier 2, the adder 3, the frame delay circuit 4 and the multiplier 5 constitute a kind of low pass filter having a time constant K and which constitutes a noise reducer circuit for reducing a noise component contained in the video signal. The frame delay circuit 4 may be formed of a generally available dynamic random access memory (hereinafter simply referred to as a DRAM). Since the frame delay circuit 4 operates at low speed, a serial-parallel converter and a parallel-serial converter are connected to the input and output sides of this frame delay circuit 4 though not shown. The FIFO circuit 6 is used as a time base corrector. According to this FIFO circuit 6, the data supplied thereto is written in its memory by a write clock synchronized with an incoming video signal and in which the written data is read out from the memory by a reference read clock asynchronous to the write clock and which is developed externally. Also, since this FIFO circuit 6 operates at low speed, a serial-parallel converter and a parallel-serial converter are connected to the input and output sides thereof though not shown. When the known video memory is constructed as shown in Fig. 1, a plurality of memories are used to reduce the noise component and to correct the time base error thereby to improve the quality of a picture. In other words, since the frame memory is used to reduce the noise component and the FIFO memory is used to correct the time base error, the known video memory is complicated in circuit arrangement. Further, these memories require control circuits for their operation. This makes the peripheral circuit complicated, the system large in size and causes several defects from a cost standpoint and from a design standpoint. A frequency converter circuit is used in the above mentioned video memory apparatus. This frequency converter is suitable for a video memory apparatus. The known frequency converter circuit (frame synchronizer) for converting a frequency is constructed, as for example, shown in Fig. 2. Referring to Fig. 2, there are shown a plurality of frame memories (or field memories) 1 and 2. These frame memories 1 and 2 are supplied with data of the upper 4 bits and data of the lower 4 bits of a composite color video signal of 8 bits. That is, the frame memories 1 and 2 are each adapted to write data of 4 bits supplied thereto in turn in response to a write clock signal CKW and to read the same in response to a read clock signal CKR. At that time, the write clock signal CKW and the read clock signal CKR are not synchronized with each other so that the frame memories 1 and 2 generate output signals of frequencies different from those of the input signals, or output signals which are frequency-converted. When "crossing" occurs between a write address signal and a read address signal used in the frame memories 1 and 2 as will be described later, this crossing is detected by a crossing detecting circuit 3. Then, on the basis of the detected results from the crossing detecting circuit 3, a chroma inverter 4, to which the data read out from the memories 1 and 2 are supplied, shifts the phase of a subcarrier by 180° and supplies a video signal with correct color reproduction to an output terminal 5. The frame memories 1 and 2 may be each constructed, for example as shown in Fig. 3. As shown in Fig. 3, a video signal applied to an input terminal 10 is sequentially written in a serial access memory (hereinafter referred to as SAM) 11 of a line unit in response to the write clock CKW. The data written in the SAM 11 is transferred to a DRAM (dynamic random access memory) 12 and written in the DRAM 12 at its predetermined position designated by an address signal from a write address circuit 13 formed of a counter and which is supplied with a clock signal CLK. The data written in the predetermined position of the DRAM 12 is designated by an address signal from a read address circuit 14, which is formed of a counter and supplied with the clock signal CLK, read out therefrom and transferred to and written in a SAM 16. The data transferred to the SAM 16 is shifted bit by bit each time the read clock signal CKR is supplied to the SAM 16 and then supplied to an output terminal 17. The SAMs 11 and 16 are of the same storage capacity and the clock signals CKW and CKR are not synchronized with each other. With the circuit arrangement shown in Fig. 2, since the input and the output of each of the frame memories 1 and 2 are not synchronized with each other, the write address signal from the address circuit 13 and the read address signal from the address circuit 14 cross each other at times. When they cross each other, data is exchanged from the present field to the immediately-preceding field. This will be explained more fully with reference to Fig. 4. In Fig. 4, a solid line assumes a transition of the write address signal with respect to time and a dashed line assumes a transition of the read address signal with respect to time. Also, let it be assumed that the read address signal is higher than the write address signal in frequency (with a shorter cycle). Then, if the write address signal and the read address signal do not cross, the field information of an n-th field would be read out from t₁ to t₂; the field information of an (n + 1)-th field would be read out from the time t₂ to t₄; the field information of an (n + 2)-th field would be read out from t₄ to t₅; and the field information of an (n + 3)-th field would be read out from time t₅ to t₆. However, when the read address signal crosses the write address signal at time t₃, the field information of the (n + 1)-th field, namely, the field information at the present field is read out from time t₂ to t₃ but the field information of the n-th field, or field information before the preceding field information is read out from time point t₃ to t₄ as shown in Fig. 4. Similarly, the field information of one field before such as the field information of the (n + 1)-th field is read out out from the time t₄ to t₅ and the field information of the (n + 2)-th field is read out from time t₅ to t₆ and so on. In the circuit arrangement in which the frame memory 1 for the higher 4 bits and the frame memory 2 for the lower 4 bits are used as shown in Fig. 2, the above mentioned crossing does not cause any trouble, if it occurs both in the frame memories 1 and 2 simultaneously. However, it causes a serious trouble if the crossing does not occur at the same time between the frame memories 1 and 2 due to the scattering of delay in the memories 1 and 2. That is, at that time the field information and the field information of one field before are mixed between the upper 4 bits and the lower 4 bits. As a result, this exerts a fatal bad influence upon the picture. The prior art video memory apparatus as described above comprises the features a, b, c, d, e, h, i, and j of claim 1 as enclosed. Also an address generating means is provided, however this means differs from the means g of claim 1 in that it does not provide a second read clock. The part of the prior art video memory apparatus which comprises the just mentioned features performs the noise reduction. A time base correction is provided by the "FIFO-memory 6". A video memory apparatus having the features a - h of claim 1, i. e. the features of the preamble of claim 1, is described in US-A-4,339,803. In this apparatus, a write address signal and the two read address signals are all asynchronously with each other. The output terminal receives its signal from the signal processing means. A video apparatus for correcting time base errors and for compensation dropouts is described in EP-A-0 163 504. Said apparatus comprises the features a, b, c, e, f, g, h, i, and k of claim 1 as enclosed. It also comprises a memory means, similar to the frame memory means according to feature d of claim 1, however, this memory means has a storage capacity less than one frame. The apparatus further comprises a signal processing means for compensating dropouts. The signal from said signal processing means is only switched to the input buffer means in case that a dropout detector detects a dropout. It is an object of the present invention to provide a video memory apparatus of simple construction, for providing noise reduction and time base correction. This object is achieved by the video memory apparatus defined by the features of claim 1. This apparatus has very simple construction by combining the features as known from EP-A-0 163 504 into the apparatus as described in US-A-4,339,803. Further, the apparatus of the present invention is provided with means for handling the write address and the second read address when crossings occur due to the fact that these addresses are clocked asynchronously. Such means are similarly known from US-A-4,249,198, however, in the apparatus according to this US-patent, coincidence is not detected by comparing the address signals by using input and output signals, and addition or subtraction of a fixed value is not provided on the output side but on the input side of a memory means. These and other objects, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments that are to be read in conjunction with the accompanying drawings, in which like reference numerals designate like elements and parts. Fig. 1 is a block diagram schematically showing a prior art video memory apparatus; Fig. 2 is a block diagram schematically showing a known frequency converting circuit; Fig. 3 is a block diagram showing a known arrangement of a frame memory; Fig. 4 is a diagram used to explain the occurrence of the crossing between write and read address signals; Fig. 5 is a block diagram schematically showing a main portion of a frame memory which is used in the present invention; Fig. 6 is a block diagram schematically showing an embodiment of a video memory apparatus according to the present invention; Fig. 7 is a block diagram schematically showing another embodidment of the video memory apparatus according to the present invention; Fig. 8 is a block diagram schematically showing an embodiment of a frequency converting circuit according to the present invention; Figs. 9A to 9F are respectively diagrams used to explain the generation of flags in the embodiment shown in Fig. 8; Figs. 10A to 10C and Figs 11A to 11C are respectively diagrams used to explain the operation of the embodiment shown in Fig. 8; and Fig. 12 is a diagram showing a relationship between a video signal and the position of an address signal. Now, an embodiment of the video memory apparatus according to the present invention will hereinafter be described in detail with reference to Figs. 5 to 7. A frame memory (or field memory) used in the video memory apparatus of this invention will be described first with reference to Fig. 5 which shows a main portion of this frame memory. Referring to Fig. 5, a video signal is supplied to an input terminal 10 as serial data. The serial data applied to the input terminal 10 is supplied to and sequentially written in a SAM 11 unit which functions as an input buffer means in response to a write clock signal CKW. Data written in the SAM 11 is transferred to a DRAM 12 in parallel over a data bus, and then written in the DRAM 12 at a predetermined address designated by an address signal from a write address circuit 13. Data written in the DRAM 12 at a predetermined address is read out therefrom in parallel by the address signal from a first read address circuit 14, transferred to and written in a SAM 16 used as a first output buffer means. Information transferred to the SAM 16 is shifted by one bit each time the SAM 16 is supplied with a read clock signal CKR₁ and then supplied to an output terminal 17 as a first output OUT1. Data written into the DRAM 12 at another predetermined address is read out therefrom in parallel by an address signal from a second read address circuit 14A, transferred to and written in a SAM 18 used as a second output buffer means. Information transferred to the SAM 18 is shifted by one bit each each time the SAM 18 is supplied with a read clock signal CKR₂ and then supplied to an output terminal 19 as a second output OUT2. The SAMs 11, 16 and 18 are selected to have the same storage capacity. Fig. 6 schematically illustrates an embodiment of a video memory apparatus according to the present invention which employs the frame memory as shown in Fig. 5. This embodiment can achieve the function of a time base corrector and the function of a noise reducer by using the same frame memory. In Fig. 6, like parts corresponding to those of Fig. 1 are marked with the same references and will not be described in detail. Referring to Fig. 6, there is shown a frame memory 20 constructed as shown in Fig. 5. Referring to Figs. 5 and 6, the input terminal 10 of the frame memory 20 is connected to the output side of the adder 3 and the output terminal 17 thereof is connected to the input side of the multiplier 5. The output terminal 19 of the frame memory 20 is connected to an output terminal 21. Then, the read clock signal CKR₁ applied to the SAM 16 within the frame memory 20 is synchronized with the write clock signal CKW applied to the SAM 11. The read clock signal CKR₂ applied to the SAM 18 is made asynchronous to the read clock signal CKR₁ and to the write clock signal CKW, and constitutes a reference signal which is developed externally. Since the read clock signal CKR₁ and the write clock signal CKW are asynchronous to the read clock signal CKR₂, it is necessary to prevent transfer pulses from respective ports from being transferred simultaneously during a period of one horizontal line (corresponding to the duration of 1H where H is one horizontal scanning period). The data applied to the input terminal 10 is written in the SAM 11 in response to the clock signal CKW and then transferred through the DRAM 12 to the SAM 16. When the data transferred to the SAM 16 is read out therefrom in response to the read clock signal CKR₁ synchronized with the clock signal CKW, the input data and the output data are delayed by a delay time of substantially one frame period. Then, the output data is supplied through the multiplier 5 to the adder 3 thereby to form a kind of cyclic-type filter, to achieve the noise reducer function. When the data is written in the SAM 11 on the basis of the clock signal CKW containing a jitter component and the data is read out from the SAM 18 on the basis of the fixed reference clock signal CKR₂ containing no jitter component, the function of a time base corrector can be achieved. Fig. 7 schematically illustrates another embodiment of the video memory apparatus according to the present invention which employs the frame memory shown in Fig. 5. According to this embodiment, the same frame memory is used to achieve the function of the time base corrector and the function of a comb filter. Referring to Fig. 7, the output terminals 17 and 19 of the frame memory 20 are connected to respective input terminals of an adder 22, and a 1/2 attenuator 23 is connected to receive the output of the adder 22. Then, the write clock signal CKW applied to the SAM 11 and the read clock signals CKR₁ and CKR₂ applied to the SAMs 16 and 18 of the frame memory 20 (Fig. 5) are made asynchronous to one another and the read clock signals CKR₁ and CKR₂ are synchronized with each other, and are used as reference signals developed externally. Since the write clock signal CKW is made asynchronous to the read clock signals CKR₁ and CKR₂, also in this case, it is necessary to prevent transfer pulses of the respective ports from being overlapped simultaneously during a period of one horizontal line (1H). According to this embodiment, data is written in the SAM 11 in response to the clock signal CKW containing the jitter component and data are read out from the SAMs 16 and 18 in response to the fixed reference clock signals CKR₁ and CKR₂ containing no jitter component, whereby the function of the time base corrector can be achieved. The video signal consists of a luminance signal Y and a chrominance signal C and the chrominance signal C is inverted at every line so that if the video signal of the present line is taken as Y + C, a video signal of a next line is expressed as Y - C. Accordingly, when both of the video signals Y + C and Y - C are added and then the sum is divided by 2, can be established. Thus, the luminance signal Y can be separated from the video signal. Therefore, according to this embodiment, when the respective output signals from the SAMs 16 and 18 are added by the adder 22 and the added output therefrom is divided by 2 by the 1/2 attenuator 23, the separated luminance signal can be obtained at the output terminal 21. That is, the same function as that of the comb filter can be achieved. As set forth above, according to the video memory apparatus of the present invention, the input buffer means is connected to the input side of the memory means, the first and second output buffer means are connected to the output side of the memory means and the input buffer means is made asynchronous to at least either the first or second output buffer means. Thus, the function of the time base corrector, the function of the noise reducer and the function of the comb filter can be achieved by the single memory without making the peripheral control circuit complicated, the quality of picture can be improved and the circuit arrangement can be simplified. An embodiment of the frequency converting circuit according to the present invention will be described with reference to Fig. 8 which is a block diagram showing a circuit arrangement of this embodiment. In this embodiment, the frame memory shown in Fig. 3 is employed so that in Fig. 8, like parts corresponding to those of Fig. 3 are marked with the same references and will not be described in detail. Referring to Fig. 8, there is shown a comparator 30 which compares the address signal from the write address circuit 13 and the address signal from the read address signal circuit 14. The comparator 30 generates a flag signal when one address signal crosses the other. The flag signal from the comparator 30 is supplied to the input terminals D of a pair of flip-flop circuits 31 and 32. The clock signal CLK applied to the read address circuit 14 is supplied to the clock terminal of the flip-flop circuit 31 and also supplied through an inverter 33 to the clock terminal of the flip-flop circuit 32. When the state in which the writing is ahead of the reading is changed to the state in which the reading is ahead of the writing, or when the read address signal crosses the write address signal, the output of the flip-flop circuit 32 becomes "1" (high level) and the output of the flip-flop circuit 31 becomes "0" (low level). Further, when the state in which the reading is ahead of the writing is changed to the state in which the writing is ahead of the reading, or when the write address signal crosses the read address signal, the output of the flip-flop circuit 31 becomes "1" and the output of the flip-flop circuit 32 becomes "0". The output of the flip-flop circuit 31 is supplied to a set terminal SET2 of a switching control circuit 34, while the output of the flip-flop circuit 32 is supplied to a set terminal SET1 of the switching control circuit 34. The switching control circuit 34 controls a switch 35 so as to connect its movable contact c to one fixed contact a during a vertical blanking period of the reading. When the control circuit 34 is supplied at either its set terminal SET1 or SET2 with the signal "1", the switching control circuit 34 controls the switch 35 so as to connect its movable contact c to the fixed contact a after a predetermined period of time, for example, 2H following the signal "1" being supplied thereto. The other fixed contact b of the switch 35 is connected through a 2H delay circuit 36 to the output side of the SAM 16 and the fixed contact a of the switch 35 is directly connected to the output side of the SAM 16. The common terminal c of the switch 35 is connected to an output terminal 37. The output signals from the flip-flop circuits 31 and 32 are supplied to an address correcting circuit 38, responsive to the output signals from the flip-flop circuits 31 and 32, the address correcting circuit 38 controls the write address circuit 13 or the read address circuit 14. Specifically, when the flip-flop circuit 32 generates an output "1" and the flip-flop circuit 31 generates an output "0", the address correcting circuit 38 controls the read address circuit 14 so as to make the sequential order of its address signal as -2, while when the flip-flop circuit 31 generates the output "1" and the flip-flop circuit 32 generates the output "0", the address correcting circuit 38 controls the write address circuit 13 so as to make the sequential order of its address signal by +2. In other words, the state of the applicable address circuit is increased or decreased by 2. The operation of the frequency converting circuit shown in Fig. 8 will be described with reference to Figs. 9 to 12. Figs 9A to 9F are respectively diagrams used to explain flag signals generated at the output side of the comparator 30. A clock signal CLK shown in Fig. 9A is supplied to the read address circuit 14 and to the clock terminal of the flip-flop circuit 31. This clock signal CLK is further supplied through the inverter 33 to the clock terminal of the flip-flop circuit 32. When the state of the read address signal, shown in Fig. 9B, from the read address circuit 14 is higher than that of the write address signal, shown in Fig. 9C, from the write address circuit 13, as will be clear from Figs. 9B and 9C, the read address signal crosses the write address signal. When the read address signal coincides with the write address signal in part, or the read address signal crosses the write address signal, the comparator 30 generates a flag signal shown in Fig. 9D. For example, when (n - 1)-th, n-th and (n + 1)-th read and write address signals coincide with one another in part, the comparator 30 generates flag signals as shown in Figs. 9B to 9D. If the state of the write address signal is higher than that of the read address signal, as will be clear from Figs. 9B and 9E, the write address signal crosses the read address signal. When the write address signal coincides with the read address signal in part, or the write address signal crosses the read address signal, the comparator 30 generates a flag signal shown in Fig. 9F. For example, the comparator 30 generates the flag signals when the (n - 2)-th, (n - 1)-th and n-th read and write address signals coincide with one another in part as shown in Figs. 9B, 9E and 9F. The flag signal generated at the output side of the comparator 30 is supplied to the D input terminals of the flip-flop circuits 31 and 32, so that when the clock signal CLK applied to the read address circuit 14 is supplied to the clock terminals of the flip-flop circuits 31 and 32, the flag signal is manifested by the flip-flop circuits 31 and 32 at their output terminals Q. In other words, when the read address signal (Fig. 9B) crosses the write address signal (Fig. 9C), the flag signal shown in Fig. 9D is generated, and the flip-flop circuit 32, at the time of the trailing edge of the clock signal CLK shown in Fig. 9A. generates the output "1" (while the flip-flop circuit 31 generates the output "0"); and when the write address signal (Fig. 9E) crosses the read address signal (Fig. 9B), the flag signal shown in Fig. 9F is generated, and the flip-flop circuit 31, at the time of the leading edge of the clock signal CLK shown in Fig. 9A generates the output "1" (while the flip-flop circuit 32 generates the output "0". Upon normal operation, in which the read and write address signals do not cross with each other, the switch control circuit 34 allows the movable contact c of the switch 35 to be connected to its fixed contact b , so that the frame memory, or the SAM 16 generates the video signals corresponding to the (n - 2)-th, (n - 1)-th, n-th, (n + 1)-th, ..., (n + 5)-th address signals, in turn as shown in Fig. 10A. As the result, at the output terminal 37, connected to the movable contact c , are generated in turn the video signals corresponding to the (n - 4)-th, (n - 3)-th (n - 2)-th, (n - 1)-th, n-th, ..., (n + 3)-th address signals, which all result from delaying the outputs of the SAM 16 by the 2H in the 2H delay circuit 36 as shown in Fig. 10C. However, when the read address signal crosses the write address signal as described above, the flip-flop circuit 32 generates the output "1" and the flip-flop circuit 31 generates the output "0", with the result that the address correcting circuit 38 controls the read address circuit 14 so as to shift the timing at which the crossing occurs, for example, n-th address by - 2 as shown in Fig. 10A. Thus, the (n - 2)-th address signal is generated from the read address circuit 14 and supplied to the DRAM 12. In like manner, the read address circuit 14 sequentially generates the address signals in the shifted form, such as (n - 1)-th address signal for (n + 1)-th address signal, (n + 3)-th address signal for (n + 1)-th address signal, ..., by -2 each. Then, after 2H periods from the time when the crossing occurs, the output of the flip-flop circuit 32 becomes "1" and the output of the flip-flop circuit 31 becomes "0", and the switching control circuit 34 controls the switch 35 so as to allow its movable contact c to be connected to the contact a . While the video signals corresponding to the (n - 4)-th, (n - 3)-th, (n - 2)-th and (n - 1)-th address signals shown in Fig. 10C are generated at the output terminal 37, after the switch 35 connects its movable contact c to the fixed contact a , video signals corresponding to those at n-th, (n + 1)-th, (n + 2)-th and (n + 3)-th shown in the right-hand and lower side of Fig. 10A are generated at the output terminal 37. In other words, the video signals are generated at the output terminal 37 in the order encircled by the hatched areas in Fig. 10A. When the write address signal crosses the read address signal, the output of the flip-flop circuit 31 becomes "1" and the output of the flip-flop circuit 32 becomes "0", so that the address correcting circuit 38 controls the write address circuit 13 so as to shift an address signal at a crossing time point, for example, an n-th address signal by +2 as shown in Fig. 11A and to supply and (n +2)-th address signal to the DRAM 12. Then, a video signal corresponding to the n-th address signal is written in the DRAM 12 at its predetermined position corresponding to the (n + 2)-th address signal. In other words, in the normal mode where no crossing occurs, video signals V₁, V₂, V₃, ..., V n are written in and read out in turn in response to the respective addresses 1, 2, 3, ... n as shown in Fig. 12. When the write address signal crosses the read address signal, the video signal is not written at the positions of the crossing address signal and the next address signal, but is sequentially written from the position corresponding to the address signal shifted by +2. Accordingly, as shown in Fig. 11A, no video signal is written in the positions corresponding to the n-th address signal of a crossing time point and the next (n + 1)-th address signal, but a video signal V n corresponding to the n-th address signal is written in the position corresponding to the (n + 2)-th address signal; and a video signal V n + 1 corresponding to the (n + 1)-th address signal is written in the position corresponding to the (n + 3)-th address signal. This is also true for the succeeding video signals. After 24 periods from a time point where the crossing occurs, or when the output of the flip-flop circuit 31 becomes "1" and the output of the flip-flop circuit 32 becomes "0", the switch control circuit 34 supplies the control signal to the switch 35, so that the switch 35 connects its movable contact c to the fixed contact a . Then, while video signals V n - 4 , V n - 3 , V n - 2 and V n - 1 corresponding to the (n - 4)-th, (n - 3)-th, (n - 2)-th and (n - 1)-th address signals (Fig. 11C) were previously sequentially delivered through the 2H delay circuit 36 to the output terminal 37, after the movable contact c of the switch 35 is connected to the fixed contact a , video signals V n , V n + 1 , V n + 2 , V n + 3 corresponding to the (n + 2)-th, (n + 3)-th, (n + 4)-th and (n + 5)-th address signals as shown in Fig. 10A are delivered to the output terminal 37. That is, the video signal corresponding to the respective address signals in the sequential order encircled by the hatched areas in Fig. 11 are sequentially developed at the output terminal 37. According to the frequency converting circuit of the present invention, as set forth above, when it is found that the crossing occurs between the first and second address signals as the result of the comparison of them, the sequential order in which the address signal is supplied to the memory is switched and the continuous output signal is derived from the memory, so that the occurrence of the crossing between the address signals can be avoided. Accordingly, when input data is processed in the data form of upper and lower bits, no trouble occurs and it becomes possible to prevent a serious bad influence from being exerted upon the picture which was a disadvantage of the prior art. Furthermore, according to the present invention, the crossing itself between the address signals can be avoided, so that unlike the prior art, the crossing detection circuit, the chroma inverter or the like can be removed, with the circuit arrangement being simplified accordingly.

Claims: A video memory apparatus for providing noise reduction and time base correction, said apparatus comprising: a) an input terminal (1) for inputting video signals; b) a signal processing means (2, 3, 5) for processing said inputted video signals as well as video signals read out from a frame memory means (12) by a first output buffer means (16) and a second output buffer means (18); c) an input buffer means (11) for receiving the signals outputted from said signal processing means and for supplying its output signals to said frame memory means with a write clock (CKW); d) said frame memory means (12); e) said first output buffer means (16) reading signals from said frame memory means with a first read clock (CKR1); f) said second output buffer means (18) reading signals from said frame memory means with a second read clock (CKR2); g) address generating means (13, 14, 14A) for addressing said frame memory means in dependence of said write clock and said first and second read clocks; and h) an output terminal (19) receiving the output signals from said second output buffer means; characterized in that i) said input buffer means and said first output buffer means are clocked synchronously, thereby said first output buffer means receiving signals which are shifted against the input signals by essentially one frame; j) said signal processing means (2, 3, 5) is arranged, for providing noise reduction, to multiply the input signals with a factor K; multiply the signals output from said first output buffer means with a factor 1-K; add the two multiplication results; and output said addition signal to said input buffer means; k) said second output buffer means is clocked, for providing time base correction, with a second read clock asynchronously to said write clock and said first read clock; l) a comparison means (30) is provided, for comparing the write address signal and the second asynchronous read address signal with each other and for producing a coincidence signal; m) an address correcting circuit (38) is provided, for increasing said second read address by a fixed value as soon as said coincidence signal announces that said write address overtakes said second read address, and for decreasing said second read address by said fixed value as soon as said coincidence signal announces that said second read address overtakes said write address; n) a delay circuit (36) is provided, for delaying the signal read from said second read address by a delay time periode corresponding to integer multiples of the horizontal synchronizing period, said integer being said fixed value; and o) a switch means (31, 32, 34, 35) is provided, for switching said delayed signal to the output terminal when said coincidence signal is provided, and for switching the undelayed signal to the output terminal a predetermined time period thereafter, whereby said switching to the delayed signal is provided after said delay time period has elapsed since provision of said coincidence signal. An apparatus according to claim 1, characterized in that said fixed value is "2".

Inventors: EBIHARA, NORIO, KITA, HIROYUKI, OHSAWA, YOSHIHITO, SASAKI, TAKAYUKI
Applicants: SONY CORPORATION
Application year: 1987
Main classification: H04N5
IPC codes: G11C7, H04N5, H04N9