Process for manufacturing a semiconductor device using a mask, and resist material therefor

Abstract: In the manufacture of a semiconductor device, the dry etching of a resist layer of an organic material can be utilized without decreasing the yield of the semi-conductor layer, by using a resist layer of an organic material containing heavy metals in an amount of less than 20 ppb for each heavy metal.

Description: The present invention relates to a process for manufacturing a semiconductor device, more particularly for etching an organic resist layer on a substrate on which another layer is subsequently formed, and a resist material therefor. The processing of a semiconductor substrate using a resist layer of an organic material including a photoresist as a mask is widely used in the manufacture of semiconductor devices. In this processing, a resist layer is locally formed on a part of a semiconductor substrate, for example, an epitaxial layer, and subsequently, selective etching, ion implantation, etc., are carried out on the semiconductor substrate using the resist layer as a mask. The resist layer is then removed. To remove the resist layer, wet etching, for example, chemical etching, has been used, but dry etching such as plasma etching is now increasingly used since the disposal of waste matter is easier in dry etching than in wet etching. Therefore, there is a desire to use dry etching in the removal of a resist layer used as a mask in the processing of a semiconductor substrate. However, although a resist layer of an organic material can be removed by wet etching without problems, the removal of a resist layer of an organic material on a substrate by dry etching causes the formation of particles on the surface of the substrate, and as a result, a layer deposited thereon becomes rough-surfaced For example, if a polycrystalline silicon layer is deposited on a substrate containing the particles as mentioned above, bright points (particles which can be observed as bright points in the dark field of a microscope) appear in the polycrystalline silicon layer, which are nuclei of crystal defects, and the thickness of the resulting polycrystalline silicon layer is non-uniform and/or the top surface of the polycrystalline silicon layer is uneven. These defects, rough surface, etc., may cause a deterioration of the characteristics of semiconductor devices having such a polycrystalline silicon layer or of another layer superimposed on the polycrystalline polysilicon layer, which may have reflected defects or rough surface. Accordingly, it has been considered that dry etching should not be used for the removal of a resist layer, and the reasons therefor have not been investigated. An embodiment of the present invention may enable the utilization of dry etching of a resist layer of an organic material in the manufacture of a semiconductor device. According to a first aspect of the present invention, there is provided a process for manufacturing a semiconductor device, comprising the steps of:- providing a substrate; locally forming a resist layer of an organic material on a first area of the substrate, the organic material containing a total of less than 20 ppb of heavy metals; carrying out a required process on the substrate with the resist layer thereon; removing the resist layer by dry etching; and depositing a further layer on the substrate in a second area including at least a part of said first area. According to a second aspect of the present invention, there is provided an organic resist material for use in such a process containing a total of less than 20 ppb of heavy metals. The term heavy metals as used herein denotes particularly, but not necessarily exclusively, metals having an atomic number of 21 or more, including iron (Fe), nickel (Ni), chromium (Cr), etc. Generally, the amount of iron in an organic resist material tends to be large such as more than about 150 ppb to about 1000 ppb because a reactor for producing resist materials is made of stainless steel, etc., but decreasing the contents of other heavy metals in resist materials is relatively easy. Therefore, preferably an organic resist material having contents of the other heavy metals apart from iron of less than 5 ppb is used. Reference is made, by way of example, to the accompanying drawings, in which:- Fig. 1 shows a relationship between the number of bright points and the content of iron in an organic resist material; and Figs. 2A, 2B and 2C are sectional views of an EPROM in main steps of manufacturing same. In the prior art, it has been known that the existence of heavy metals in a semiconductor crystal has a disadvantageous effect on the characteristics of semiconductor devices. However, it has not been known that the heavy metal content of an organic resist material causes a deterioration of a semiconductor device when a resist layer is removed by dry etching. Conventional organic resist materials including organic photoresist materials contain heavy metals in an amount of about 100 ppb to about 1000 ppb and this content of heavy metals has been considered as not causing a problem. Further, it has not been known that a deterioration of the characteristics of a semiconductor device comes from defects, rough surface, etc., of a layer formed on a substrate on which a resist layer of an organic material has been formed and then removed by dry etching. The inventors coated a novolak-system positive type resist layer having an iron content of 150 ppb, 230 ppb, 360 ppb, or 540 ppb and content of other heavy metals such as copper and nickel of less than 5 ppb, to a thickness of about 1 µm on a silicon dioxide layer and carried out patterning thereon. Here, the content of heavy metals was measured by atomic absorption spectroscopy. Boron ions were then locally implanted through the silicon dioxide layer into a silicon substrate at a dose of about 1 x 10¹³ cm⁻², using the resist layer as a mask. The resist layer was then removed by oxygen plasma etching. The conditions for the plasma etching were as follows: Oxygen flow rate: 50 cc/min Oxygen pressure: 1 Torr (133.3 Pa) Power source frequency: 13.56 Hz High frequency power: 300 W After the resist layer was removed, a polycrystalline silicon layer having a thickness of about 400 nm was deposited on the silicon dioxide layer by chemical vapor deposition (CVD). Bright points appeared in the polycrystalline silicon layer and the number of bright points was counted for each case. The results are shown in Fig. 1, in which the abscissa indicates the iron content and the ordinate indicates the relative number of bright points in comparison with the number of bright points when wet etching is used for removing a resist layer of an organic material. From Fig. 1, it can be seen that, when the iron content in the organic material of the resist layer is less than 20 ppb, the number of bright points is equal to or less than that when a resist layer is removed by wet etching, and does not cause problems in a semiconductor device. Next, an EPROM (erasable and programmable read only memory), a type of MIS (metal-insulator-semiconductor) FET (field effect transistor), was manufactured using an organic resist material as a mask to form source and drain doped regions, and a polycrystalline silicon layer to form a floating gate. Referring to Fig. 2A, the surface of an p-type silicon substrate 1 was oxidized to form a silicon dioxide layer 2 having a thickness of 40 nm as a gate insulating layer on which a photoresist layer 3 having a thickness of 1.1 µm was formed and patterned to remove portions at which the source and drain are to be formed. Arsenic ions were locally implanted into the silicon substrate 1 through the silicon dioxide layer 2 using the photoresist layer 3 as a mask, to form n-type doped source and drain regions 4 and 5. Referring to Fig. 2B, the photoresist layer 3 was removed by oxygen plasma etching under the conditions described above. After removal of the photoresist layer 3, an n-doped polycrystalline silicon layer 6 having a thickness of about 400 nm was deposited by CVD. The surface of the polycrystalline silicon layer 6 was oxidized to form a silicon dioxide layer 7 having a thickness of 10 to 40 nm. An n-type polycrystalline silicon layer 8 having a thickness of 400 nm was again deposited on the silicon dioxide layer 7. Referring to Fig. 2C, the polycrystalline silicon layer 8, the silicon dioxide layer 7, and the polycrystalline silicon layer 6 were patterned to form a gate comprising a floating gate 6', an insulating layer 7', and a polycrystalline silicon gate 8'. Then, an insulating layer 9 and source and drain electrodes 10 and 11 were formed. Thus, an EPROM, (EPROM Cell) was created. In this process of manufacturing an EPROM, when the photoresist layer 3 used was made of an organic material having an iron content of 150 ppb or more, particles were left on the surface of the silicon dioxide layer 2 after the photoresist layer 3 was removed by plasma etching. As a result, the top surface of the polycrystalline layer 6 deposited on the silicon dioxide layer 2 with the particles thereon became rough and the thickness of the silicon dioxide layer 7 formed by oxidizing the rough top surface of the polycrystalline layer 6 was non-uniform. Further, the silicon dioxide layer 7 sandwiched by the two polycrystalline layers 6 and 8 had a non-uniform thickness, and very thin portions were easily broken when a voltage was applied thereto. Thus, EPROM devices manufactured by the above process or under the above conditions had a low yield. In contrast, when the photoresist layer 3 used was made of an organic material containing an iron content of less than 20 ppb and a content of other heavy metals of less than 5 ppb, the particles did not appear, or at least the number thereof decreased, and the thickness of the silicon dioxide layer 7 was uniform, giving the same yield of the EPROM devices as when a photoresist layer was removed by wet etching. Thus, by means of the present invention, dry etching such as plasma etching can be utilized for removing a resist layer of an organic material without leaving particles, without forming bright points in a crystalline layer formed thereafter, and without deteriorating the characteristics of a semiconductor device. Such etching can be applied, for example, to local etching of a semiconductor substrate using the resist layer as a mask. In the above example, the polycrystalline silicon layer 6 was deposited by CVD; however, it is also possible to use physical vapor deposition for this process step.

Claims: A process for manufacturing a semiconductor device, comprising the steps of:- providing a substrate; locally forming a resist layer of an organic material on a first area of the substrate, the organic material containing a total of less than 20 ppb of heavy metals; carrying out a required process on the substrate with the resist layer thereon; removing the resist layer by dry etching; and depositing a further layer on the substrate in a second area including at least a part of said first area. A process according to claim 1, wherein said heavy metals are defined as metals having an atomic number of 21 or more. A process according to claim 1 or 2, wherein said deposition of the further layer is carried out by chemical vapor deposition. A process according to claim 1 or 2, wherein said deposition of the further layer is carried out by physical vapor deposition. A process according to any preceding claim, wherein said process carried out on the substrate with the resist layer thereon is a local etching of the substrate using the resist layer as a mask. A process according to any of claims 1 to 4, wherein said process carried out on the substrate with the resist layer thereon is a local ion implantation into the substrate using the resist layer as a mask. A process according to any preceding claim, wherein said substrate is a semiconductor substrate. A process according to claim 7, wherein said substrate has an insulating layer formed on the surface thereof, the resist layer being formed on said insulating layer. A process according to any preceding claim, wherein said further layer is of a semiconductor material or an insulator material. An organic resist material for use in a process according to any preceding claim, said material containing a total of less than 20 ppb of heavy metals.

Inventors: FUJIMURA SHUZO, YANO HIROSHI, FUJIMURA, SHUZO, YANO, HIROSHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1987
Main classification: H01L21
IPC codes: H01L21, G03F7