COLOUR GRAPHICS CONTROL SYSTEM

Abstract: A colour graphics control system for generating red, blue and green analog signals (15, 16, 17) to a raster scan display (21) at a pixel frequency comprises a RAM (22) storing a plurality of digital colour values, digital to analog converters (26, 27, 28) with decoding means (29) for converting the digital colour values into analog signals, an interface (24) to permit an external controller (23) to write digital colour values into the RAM locations, timing means (25) including a pixel clock (14) and RAM accessing means controlled by the timer to pipeline RAM accessing with a cycle time of more than one pixel period.

Description: The invention relates to a colour graphics control system for generating electrical signal values for respective colour inputs to a raster scan colour display unit under the control of a microprocessor screen controller or computer. Commonly computers or microcomputers are required to control a colour display on a raster scan colour display unit such as a colour cathode ray tube. In such a raster scan display unit each scanning line comprises a succession of pixels and it is necessary to supply analog input signals to the red, blue and green colour inputs of the cathode ray tube at the pixel frequency in order to establish the correct colour composition for each pixel. The colour composition required for each pixel may be indicated by a numerical value stored in a pixel memory or bit map. Values from this pixel memory are read at the pixel frequency and must then be converted into appropriate analog signal values to each of the different colour inputs for the cathode ray tube. Colour look-up tables are known for this purpose. In this case a combination of red, blue and green colour values is derived from a look-up table for each pixel value. Due to the high pixel frequencies normally used in a raster scan display problems arise in deriving red, blue and green colour values from a colour look-up table embodied in an integrated circuit memory device. Previous devices capable of operating at high pixel frequencies have involved many separate components at relatively high cost and with substantial power comsumption. It is an object of the present invention to provide an improved colour graphics control system in which stored pixel values may be used to generate a succession of electrical signals representing respective colour inputs for a raster scan colour display unit at high pixel frequencies with low cost and low power consumption, and with improved digital to analog signal conversion. It is a further object of the invention to provide an improved colour graphics control system which may be incorporated in a single integrated circuit chip. A colour lookup table system for a raster scan display is described in IEEE International Solid State Circuits Conference, Volume 28, February 1985, pages 76, 77, 310 and 311. That system provides a colour graphics control system using a RAM storing a plurality of digital colour values together with digital to analog converter circuits to generate respective analog signals for each colour in response to colour values from the RAM. Timing control is used to provide pipelined memory access extending over a plurality of pixel periods. An interface for connection to a microprocessor is provided for writing values to loctions in the RAM. Pages 175 to 181 of Computer Design, Volume 23, No 13, November 1984, describe in an article called "High Speed DA-Converters Yield Precision Graphics" a digital to analog converter system in which to reduce unwanted glitch phenomena current sources are arranged in groups for switching together, the group representing the largest current value representing less than the maximum digital value to be converted. In this way the switching is carried out on smaller current values reducing the glitch problem. The present invention is specifically concerned with the problem of providing a colour graphics control system which may be incorporated on a single integrated circuit chip operating at high pixel frequencies with low cost and low power consumption and with digital to analog signal conversion which minimises the risk of unwanted signals occurring from the digital to analog conversion. This requires maximum elimination of glitch energy in switching current sources as well as stabilising the analog signals which are generated by switching in of current sources. The present invention provides a colour graphics control system for generating electrical signal values for respective colour inputs to a raster scan colour display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for a scanning sequence, said control system comprising: memory means in the form of RAM having a plurality of addressable locations each storing a digital colour value, digital to analog converter means for receiving a multi-bit digital signal from said RAM and in response to each different colour value generating a different combination of analog electrical signals representing respectively red, blue and green colour values for each pixel in a raster scan display, said converter means including a plurality of selectively operable current sources with switch means for operating a selected number of current sources corresponding to the value of said multi-bit signal, timing means for indicating a pixel frequency corresponding to that of the raster scan and generating timing control signals for synchronising the generation of said analog signals at said pixel frequency, RAM accessing means for receiving a succession of pixel values from said pixel memory device at the pixel frequency and in response to each pixel value effecting a multi-stage accessing operating including addressing a corresponding location of the RAM and reading from the location a digital colour value for supplying to said digital to analog converter means, and an interface connected to said RAM and arranged for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital colour values into one or more locations in said RAM, said timing means being arranged to control each successive stage of RAM accessing wherein a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a RAM location and reading the digital colour value for each pixel value, characterised in that the current sources are grouped into a plurality of groups having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group having a number of current sources which is less than the digital value of the bit of maximum significance in said multi-bit signal, decoding means are provided for decoding said multi-bit signal and providing a number of switch actuating signals greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group of current sources, thereby reducing the number of current sources in any group of current sources necessary to be switched at any time, and current stabilising circuitry is provided for each current source to render the current of each source independent of the number of parallel current sources that are switched on or off, said switch means for each group of current sources being arranged to switch together each current source and each stabilising circuit of the group in response to a common switch actuating signal. By use of groups of current sources as set out above a significant reduction in glitch phenomenon can be achieved on switching the current sources to effect the digital to analog conversion. Furthermore the current stabilising circuitry enables the current rendered by each current source in a group to be independent of the number of parallel current sources that are switched on or off. The simultaneous switching of all current sources in a group together with simultaneous operation of each current stabilising circuit in response to a common switch actuating signal for each group minimises the risk of unwanted current signals being provided in the output. An embodiment of the invention will now be described by way of example and with reference to the accompanying drawings. Figure 1 is a block diagram of a colour graphics control system in accordance with the present invention, Figure 2 is a more detailed block diagram of the memory shown in Figure 1, Figure 3 is a more detailed block diagram of the microprocessor interface shown in Figure 1, Figure 4 is a more detailed diagram of the digital to analog converters of Figure 1, Figure 5 shows a group of current sources used in the digital to analog converters of Figure 4, Figure 6 illustrates a pixel frequency pulse train, and Figure 7 illustrates two timing signals derived from the pixel frequency for use in the arrangement of Figure 1. This example provides a colour graphics control system for generating electrical signal values for respective colour inputs to a raster scan colour display unit in response to a succession of digital pixel values derived from a pixel memory device in the form of a bit map store 11 storing pixel values for a scanning sequence. The colour graphics control system includes a colour look-up table chip 12 which is arranged to receive pixel values on a bus 13 from the store 11 at a pixel frequency determined by a pixel clock 14. The chip 12 converts the pixel values into analog electrical signals on output lines 15, 16 and 17 which are connected respectively to the red, blue and green guns 18, 19 and 20 of a colour cathode ray tube 21. The chip 12 has a RAM memory 22 which is used to look up a colour value for each of the pixel values received from the store 11 and a controlling microprocessor 23 is provided to allow control of the colour values stored in the memory 22 for each of the possible pixel values. In this example the chip 12 comprises a single integrated circuit device produced on a twin tub P-well in an N-substrate CMOS process with a composite silicide/doped polycrystalline transistor gate and interconnect material. The single integrated circuit chip includes in addition to the RAM 22, a microprocessor interface 24, a timing generator 25 and three digital to analog converters 26, 27 and 28 with decoding means 29. The RAM 22 has 256 addressable locations each holding an 18 bit word representing a colour value. Pixel values are supplied on the bus 13 at the pixel frequency determined by the pixel clock 14. Each pixel value is an 8 bit pixel word which is used as an address into the 256 location RAM 22. Each pixel value causes an 18 bit wide data value to be supplied on a bus 30 from the memory 22 to the decoder 29. The 18 bit data value is composed of three groups of 6 bits each representing an intensity value for red, blue or green respectively and is fed to the corresponding digital to analog converter 26 to 28. In this way, each pixel value can choose any one of 256 colour values which are held in the memory 22. The timing generator 25 controls the timing operation of the memory 22, decoder 29 and digital to analog converters so that the analog output signals are supplied on lines 15, 16 and 17 at the same pixel frequency. The microprocessor 23 can write different colour values into one or more memory locations 22 by use of the interface 24. In this way, the 256 locations in the memory 22 can be used to form a colour palette which by use of the microprocessor 23 and interface 24 can provide up to 262,144 different colours. In some applications it is necessary to operate with a high pixel frequency and frequencies of up to 50 MHz or higher may be required. This involves carrying out look up operations at time intervals of 20 ns or less. In this example a fast cycle time is achieved by using a pipelined RAM access so that address decoding for the RAM and reading of data from the memory cells in the RAM is completed as a multi-stage operation over two pixel clock cycles. This will be further described with reference to Figure 2. The microprocessor interface 24 simplifies communication between the chip 12 and the microprocessor 23 and is totally asynchronous to the pipeline pixel clock. The RAM 22 and memory accessing procedure will be further described with reference to Figure 2. The RAM is a static RAM having two arrays of memory cells each consisting of 36 columns and 64 rows. The arrays are marked 33 and 34. Each column is connected by a pair of bit lines 35 to a column multiplexor 36. The column multiplexor is connected by a two-way bus 37 to sense amplifiers 38 having a two-way bus 39 for the input and output of data. Each row is connected to a row decoder 40. Bus 13 supplying pixel values from the store 11 is also connected to a bus 40 connected to the microprocessor interface 24 for providing 8 bit write address values. The buses 13 and 40 provide an 8 bit signal which is split to supply two bits to each of four predecoders 41, 42, 43 and 44. Three predecoders decode the two bits received so that they each provide signals on four output lines 45 to the row decoder 40. One predecoder 41 provides signals on four lines 46 to the column multiplexor 36. The row decoder 40 therefore receives signals on 12 lines 45 and decodes these signals to select one of the 64 row lines. The column multiplexor effects a column select in response to the signals on the four lines 46. This selects which in a group of four columns are to be accessed so that 18 bits are accessed for each addressing operation. The sense amplifiers 38 determine the storage state of the accessed memory cells in the memory array in response to a pixel value on bus 13 or alternatively allow writing of data from the microprocessor interface 24 in response to an address from the microprocessor interface on bus 40. The RAM accessing is carried out in a time controlled sequence under the control of the timing generator 25. The pixel frequency required for the raster scan in the CRT tube 21 is indicated by the pixel clock 14 which supplies to the timing generator 25 a pulse train indicated in Figure 6. The timing generator 25 provides necessary systems clock pulses and these are indicated in Figure 7 wherein the upper pulse sequence is denoted PHI I and the lower pulse sequence by PHI II. The clock pulses PHI I and PHI II marked 48 and 49 respectively form two-phase non-overlapping clocks generated by using an internal edge triggered monostable circuit via a two-phase clock generator to vary the monostable pulse width. In this way the clock signals 48 and 49 are determined by the rising edge of each pulse in the pixel clock train 50 but are not dependent on the duration of each pulse in the pixel clock train. These system clock pulses are supplied to the memory array as illustrated in Figure 2. The memory accessing operation is the multi-stage operation extending over two pixel pulses and with reference to the letters marked in Figure 7, the address is latched into the predecode circuitry 41 to 44 at the point marked (a) where signal PHI I goes to a low value and the predecode is carried out. When signal PHI II goes low at the point marked (b) the predecoded row lines are latched and the row decode is performed as well as the column select. When signal PHI I goes to a low value again at the point marked (c) the accessed row is latched and the word lines in the memory array are driven. When signal PHI II goes low again at the point marked (d) the sense amplifiers 49 sense the signal values on the bit lines 35 and drive data out through the bus 39. It will therefore be seen that the RAM accessing is carried out as a pipelined operation in which successive stages are carried out in a pipeline extending over two pixel periods. The bus 39 leading from the sense amplifiers 38 is connected to both buses 30 leading to the decoder 29 and a further data bus 51 from the microprocessor interface 24. The bus 30 supplies in parallel 18 bits from the RAM 22 representing the colour intensity value corresponding to the pixel value from the bit map store 11. The digital to analog conversion will be described in more detail with reference to Figure 4. As illustrated, the 18 parallel bits from the bus 30 consist of 6 bits representing a red signal which are fed to a decoder 54, a further six bits representing the blue signal which are fed to a decoder 55 and the remaining six bits representing the green value are fed to a decoder 56. The three decoder units 54, 55 and 56 illustrated in Figure 4 form the decoder unit 29 illustrated in Figure 1. Each decoder 54, 55, 56 decodes the incoming signal to produce outputs on seven binary signal lines 59, 60 and 61 leading to respective digital to analog converters 62, 63 and 64. Each of the digital to analog converters is similar and only unit 62 handling the red signal will be described in detail. The DAC 62 consists of a plurality of current sources which may be selectively switched to generate an analog voltage corresponding to the digital input. The current sources each provide a standard unit of current. The current sources are however grouped into a variety of different size groups all current sources within any one group being switched as a unit. The first group 65 has only a single current source providing one unit of current when switched on. Group 66 provides two units of current. Similarly group 67 has four current sources and provides four units of current, group 68 has eight current sources and provides eight units of current, and group 69 has sixteen current sources providing sixteen units of current. Groups 70 and 71 each contain a further sixteen current sources and each provide sixteen units of current. Each group of current sources has an associated switch control connected to a respective one of the seven output lines 59 from the decoder 54. The switch controls have been marked 72 to 77 respectively and it can be seen that switch 72 corresponds to the bit of least significance in the output of the decoder 54 and switch 77 corresponds to the output line of greatest significance. It will therefore be seen that the groups of current sources 65, 66, 67, 68 and 69 have progressively increasing current values corresponding to the digital value on the output lines 59 controlling their switches. However, groups 70 and 71 do not follow this pattern in that they repeat sixteen current sources which is less than the digital value of the most significant bit in the output of decoder 54. This is in order to limit the maximum number of current sources which may be switched at any time in order to change the analog output to represent a change in digital input. This will be further described after reference to Figure 5. Figure 5 illustrates further details of some current sources used in the digital to analog converter of Figure 4. A specified reference current IREF is supplied on line 79 from an external source. This is applied to the gate of a plurality of parallel transistors 80 to 81 arranged to provide a suitable reference voltage on line 82. This reference voltage is then applied to the gate of a transistor 65 forming the first current source. Further current sources such as transistors 83 and 84 forming the second current source 66 are connected in parallel and each has its gate connected to the reference voltage 82. It will be appreciated that further transistors similar to those marked 83 and 84 are also connected in similar fashion and grouped together to form the other groups of current sources described with reference to Figure 4. In order to provide high quality colour displays, it is important to provide linear digital to analog conversion and due to the finite conductance of the transistors used as the current sources, stabilising circuitry 85 is provided for each current source. This consists of a further transistor 86 connected in series with the transistor 65. Its gate is connected to a transistor switch 87 under control of the switch signal 72. This may connect the gate of transistor 86 to a five volt supply line 88 when the current source is switched off or alternatively to the output of a differential operational amplifier 89 when the current source is switched on. The differential amplifier 89 has one input connected to the reference voltage line 82 and the other input connected to a point 90 intermediate the transistors 65 and 86. In the event of further current sources being switched on or off in such a manner as to vary the potential at the junction 90, the differential amplifier 89 varies the gate potential on transistor 86 so as to restore the potential at junction 90 to the required value. In this way the single unit of current which is output on line 91 from the current source 65 is stabilised and substantially independent of the number of current sources which are switched on. Each of the subsequent current sources such as transistors 83 and 84 has a similar stabilising circuit 85 but in this case the switches 87 are linked together so that they are switched together in dependence on the switch signal on line 73. When there are changes in the digital signals supplied to the digital to analog converters, unwanted spikes representing glitch energy may occur in the analog outputs. This can result from irregular loading on the data inputs to the digital to analog converter causing data skews and it may also be caused by asymetrical turn-on and off characteristics of the transistors forming the current sources. The above described arrangement reduces unwanted glitch phenomenon by arranging for the decoding by units 54, 55 and 56 as well as the limited size of current source groups in the digital to analog converters. In the arrangement shown in Figure 4, the decoding is time controlled in response to the waveform PHI I in Figure 7. Decoded outputs are supplied on lines 59, 60 and 61 in response to a fall in value in waveform 48 as indicated at point (e) in Figure 7. The operation of the current sources within the digital to analog converters is however controlled by signal PHI II so that the analog outputs are generated when signal PHI II falls to a lower level as indicated at point (f) in Figure 7. It will therefore be seen that the digital to analog conversion extends the pipeline operation commenced at memory accessing so that the entire pipeline operation of accessing the memory and producing analog output signals is a pipeline operation carried out in synchronism with the pixel frequency with the pipeline period extending over three pixel periods. By carrying out the decoding prior to supplying signals on lines 59, 60 and 61 to the digital to analog converters, the data input to the switches of the digital to analog converters is realigned in relation to the systems clock on application to the input of every current source. Furthermore, any glitch phenomenon due to asymmetrical switch on and off characteristics of the transistors is reduced by avoiding the necessity to switch any single group of current sources corresponding to the bit of greatest significance which in this example would be 32. In the example shown in Figure 4, the decoder 54 has output lines marked 0 to 6. An output on line 0 activates one current source. An output on line 1 activates two current sources. An output on line 2 activates four current sources. An output on line 3 activates eight current sources. An output on line 4 activates sixteen current sources and is caused by the logical OR of an input on either lines 4 or 5 of the decoder 54. An output on line 5 is caused by an input on line 5 and activates sixteen current sources. An output on line 6 is generated by the logical AND of inputs on lines 4 or 5 of the decoder 54 and activates sixteen current sources. In this way it is possible to select analog values representing any of 64 different digital inputs without switching a single block of current units greater than 16 so that any asymmetric transistor characteristics have a reduced effect in producing glitch phenomena. Although the RAM 22 holds data for 256 colours at any one time, these can be varied by writing in different colour values from the microprocessor 23 through the interface 24. The microprocessor may communicate with the interface at a much slower speed than the pixel frequency and this example enables the microprocessor to load data into the interface asynchronously with the pixel frequency. The microprocessor is connected to the interface by a data bus 93 leading to a data buffer 96. It is also connected by a register select line 94 and a WRITE control line 95. The WRITE control line 95 is connected to a WRITE BUFFER 97 which controls the periods in which the microprocessor is permitted to write data into the interface. The WRITE buffer 97 supplies a signal to a register select decoder 98 which is controlled by the register select line 94 to select whether data fed into the data buffer 96 from the microprocessor 23 is supplied to an address register 99 or a data register 100. When it is required to write new colour values into the RAM 22, the address register 99 is loaded with the first address in the RAM 22 into which a new colour value is to be written. The new colour value is then supplied through the data buffer 96 into the data register 100. Three successive bytes are supplied so as to fill the three registers 100, 101 and 102. The least significant six bits of each byte in the registers 100, 101 and 102 are fed into an 18 bit buffer 103. This 18 bit word consists of three groups of six bits representing the red, blue and green colour values. When the byte counters 104, 105 and 106 indicate that three bytes have been loaded, a signal is fed to a synchroniser 107 which also receives a system clock signal 108 from the timing generator 25. The synchroniser provides a WRITE signal on line 109 to the sense amplifiers 38 and the WRITE address is supplied from the address register 99 on the bus 40 so that at the beginning of the next synchronous pixel period, a writing operation is carried out at the address indicated by the contents of the register 99. The data written into the RAM 22 is supplied from the buffer 103 on the data bus 110 which is connected to the input data bus 39 connected to the sense amplifiers 38. The synchroniser 107 has one signal line 111 to control the supply of address data from the register 99 onto the bus 40. It has a further line 112 which may be used to increment the address after each writing operation. Three further colour values may thus be supplied by the controlling microprocessor without the need to supply a new address, the address used for this following update of the RAM being the newly incremented value. This sequence may be repeated indefinitely. By use of the interface shown in Figure 3, the microprocessor may communicate with the interface asychronously without reference to the pixel clock signal but the synchroniser 107 arranges for the writing operation from the interface to be carried out in synchronism with the pixel clock controlled pipeline operation. By use of the pipelining operation the required analog signals are supplied to the input of the cathode ray tube at the required pixel frequency although the generation of the analog signal from the original pixel value in the bit map store 11 has extended over three whole pixel periods. The delay between the store 11 and the input to the cathode ray tube 21 is not important provided new values are supplied at the required pixel frequency. This enables the use of a colour look-up table chip 12 of simplified form and does not require a memory which is capable of being accessed in a single operation within one pixel period. The above embodiment also has a low power consumption in that it may dissipate less than 600 mW.

Claims: A colour graphics control system for generating electrical signal values for respective colour inputs to a raster scan colour display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for a scanning sequence, said control system comprising: memory means in the form of RAM (22) having a plurality of addressable locations each storing a digital colour value, digital to analog converter means (26,27,28) for receiving a multi-bit digital signal from said RAM and in response to each different colour value generating a different combination of analog electrical signals representing respectively red, blue and green colour values for each pixel in a raster scan display, said converter means including a plurality of selectively operable current sources (62,63,64) with switch means (72-78) for operating a selected number of current sources corresponding to the value of said multi-bit signal, timing means (25) for indicating a pixel frequency corresponding to that of the raster scan and generating timing control signals for synchronising the generation of said analog signals at said pixel frequency, RAM accessing means (36,38,40) for receiving a succession of pixel values from said pixel memory device at the pixel frequency and in response to each pixel value effecting a multi-stage accessing operating including addressing a corresponding location of the RAM and reading from the location a digital colour value for supplying to said digital to analog converter means, and an interface (24) connected to said RAM and arranged for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital colour values into one or more locations in said RAM, said timing means being arranged to control each successive stage of RAM accessing wherein a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a RAM location and reading the digital colour value for each pixel value, characterised in that the current sources (62-64) are grouped into a plurality of groups (65-71) having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group (71) having a number of currant sources which is less than the the digital value of the bit of maximum significance in said multi-bit signal, decoding means (54,55,56) are provided for decoding said multi-bit signal and providing a number of switch actuating signals (59,60,61) greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group (65-71) of current sources, thereby reducing the number of current sources in any group of current sources necessary to be switched at any time, and current stabilising circuitry (86,89) is provided for each current source to render the current of each source independent of the number of parallel current sources that are switched on or off, said switch means (72-78) for each group of current sources being arranged to switch together each current source and each stabilising circuit of the group in response to a common switch actuating signal. A colour graphics control system according to claim 1 wherein said timing means is arranged to control RAM accessing so that each accessing operation extends over two successive pixel periods. A colour graphics control system according to claim 1 in which said interface includes temporary store means for receiving data from a microprocessor or other controller for use in writing into said RAM and access means for controlling loading of data into said temporary store means, said access means being operable independently of the pixel frequency to permit asynchronous loading of data into said interface from a microprocessor or other controller. A colour graphics control system according to claim 3 in which said temporary store means includes means for holding a RAM address and means for holding a digital colour value to be written into said RAM address. A colour graphics control system according to claim 4 in which means is provided for incrementing the RAM address in said temporary store means after each writing operation. A colour graphics control system according to any one of claims 1 to 5 in which the timing means includes a pixel clock providing signals at the pixel frequency and said interface includes synchronising means arranged to receive timing signals from said timing means whereby a writing operation from the interface into said RAM is synchronised with the pixel clock. A colour graphics control system according to claim 6 in which the writing operating is a multi-stage operation having a cycle time of more than one pixel period, each stage being controlled by said timing means so that a pipeline effect is achieved in writing in synchronism with the pixel clock over more than one period of the pixel frequency. A colour graphics control system according to any one of claims 1 to 7 in which each current source comprises a first transistor with said reference voltage forming a gate voltage for the transistor, the stabilising means comprising differential amplifier circuit means responsive to current fluctuations through said first transistor and arranged to provide a compensating voltage to the gate of a further transistor in series with said first transistor. A colour graphics control system according to any one of claims 1 to 8 wherein said RAM, interface and digital to analog converter means are formed on a single integrated circuit device. A colour graphics control system according to any one of claims 1 to 9 wherein each addressable location in said RAM is arranged to store an 18-bit word, said word having three groups of six bits representing respectively the colour values for red, blue and green. A colour graphics control system according to claim 10 wherein said RAM provides 256 addressable word locations.

Inventors: TALBOT, GERALD ROBERT, WORK, GORDON STIRLING
Applicants: INMOS LIMITED
Application year: 1987
Main classification: G09G1
IPC codes: G09G5, G09G1, H03M1