A RECORDING/REPRODUCING SYSTEM FOR A MAGNETIC RECORDING MEDIUM

Abstract: A data separator system has a PLL circuit (25) for outputting data pulses (DP) and clock pulses (CP) on the basis of the read data (RD) from a magnetic recording medium. The system also includes an external synchroni­ zation detection circuit (2l) which detects the synchro­ nization data (predetermined zero pattern data) recorded in the synchronization area of the magnetic recording medium (l3) on the basis of the read data (RD). When detecting the synchronization data, the synchronization detection circuit (2l) enables the PLL circuit (25) to oscillate in synchronism with the read data (RD). The data pulses (DP) and clock pulses (CP) output from the PLL circuit (25) are also supplied to an internal synchronization detection circuit (3l). On the basis of the data pulses (DP) and the clock pulse (CP), the internal synchronization detection circuit (3l) detects the synchronization data and upon detection thereof, a floppy disk controller (29) performs the data readout operation. The system further comprises a preventing circuit (25, 33 to 39) which prevents the PLL circuit (27) from performing the synchronizing operation to the read data, which is read out from the overwritten area in the magnetic recording medium (l3) by the preceding-­ erase type magnetic head.

Description: The present invention relates to a recording/reproducing system for a magnetic recording medium. In the field of floppy disk apparatuses, a preceding-erase type magnetic head has recently been devised, which is suitable for use with a high-density magnetic recording medium (disk). In the preceding-erase type magnetic head, an erase head is located in front of a read/write head in the rotational direction of the medium. Before new data are recorded in the medium by the read/write head, previously recorded data are first erased by the erase head. When this type of magnetic head is employed, the erase head should preferably be turned on at a predetermined time before the recording of data on the medium by the read/write head begins, and turned off at a predetermined time before the recording of data end. However, to be able to perform such a control procedure requires a controller, for turning the heads on and off, which is complicated in its construction. The conventional controller is in capable of performing such a control procedure, and for this reason, the erase head and the read/write head are turned on or off simultaneously. Normally, a track of a magnetic recording medium has a format shown in Fig. 1A, i.e. in which one sector comprises an ID field and a data field. The ID field comprises a synchronization area SYNC, address mark area AM, identification area ID, and cyclic redundancy check area CRC. Information representative of the starting position and address of a sector are recorded in the ID field. The data field records data, and comprises synchronization area SYNC, address mark area AM, data area DATA, and cyclic redundancy check area CRC. Synchronization areas SYNC store synchronization data for a PLL circuit; address mark AM areas store address mark data indicative of the starting position of the ID field or the data field; ID area ID stores data such as the cylinder number, the side number, the sector number, and the length of the data field; data areas DATA store data read out or written in by a user; and cyclic redundancy check areas CRC store data for checking whether or not the data read out from the ID field or the data field contains an error. Gaps 1, 2, 3, and 4 are areas for absorbing a fluctuation of rotation and an error in a mechanical alignment. Fig. 1D shows a configuration of a preceding-erase type magnetic head. The magnetic head has an erase head, a read/write head and a separator. The separator magnetically separates the erase head from the read/write head. The erase head is located in front of the read/write head with respect to the rotational direction Z of a recording medium. Data read out from the recording medium by the magnetic head are fed to a data separator which includes a PLL circuit and an external synchronization detecting circuit. The external synchronization detector detects the synchronization data in the read data, and upon detection of the synchronization data, the PLL circuit begins oscillating in synchronism with the read data and outputs data pulses and clock pulses. When the PLL circuit operates in synchronism with the read data, an internal synchronization detector detects the synchronization data on the bases of the data pulses and the clock pulses, and a floppy disk controller checks whether or not the following data are address mark data. When the address mark data are detected, the floppy disk controller reads out the data stored in the ID area ID or in data area DATA, on the basis of the data pulses and clock pulses. When data other than the address mark data are detected, the floppy disk controller stops operating for a predetermined time period, and then repeats the above-mentioned operation. Figs. 1B and 1C show the positions where the erase head and read/write head of the preceding-erase type magnetic head are turned on and off during data are written in the medium. As is shown in Figs. 1A to 1C, over-written areas are formed in Gap 2, where data are not erased by the erase head and new data are overlapped by recorded on the previously recorded data. In such a system, when data identical to the synchronization data are recorded in the over-written areas, a problem arise in that an address detection error of the floppy disk controller may occur at the boundary between the over-written areas and the data fields. In other words, when data identical to the synchronization data are recorded in the over-written areas, the floppy disk controller detects the synchronization data at the over-written area, and waits for an address mark data. When the floppy disk controller read out the confused data, it examines whether or not the read-out data is an address mark. When the floppy disk controller judges that the read-out data is not the address mark data, it stops functioning for a predetermined time period. If the floppy disk controller performs the above operation, it cannot read out the data of the data field which follows the boundary. Prior art document EP-A-0 146 636 discloses a synchronizing circuit in which data signals are divided into groups of a predetermined number of bits, each having a synchronizing signal, any desired address signal and an error detection signal for detecting an error of the address signal. The groups of data signals are adapted to be written in a memory device in accordance with the address signals. The synchronizing circuit has means for detecting any error in the address signal, means for detecting the synchronizing signal, an internal synchronizing signal generating circuit and an internal address signal generating circuit. The internal synchronizing signal generating circuit is driven, when the error detecting means judges that the address signal is correct so that an internal synchronizing signal drives the internal address signal generating circuit. The address signal or the internal address signal is selectively supplied by the memory device depending on whether the address signal is correct or wrong. In this way, data blocks synchs are suppressed if a following block address cannot be detected, i.e. if data is misinterpreted as a sync. pattern. It is an object of the present invention to provide a high reliability recording/reproducing system which uses a preceding-erase type magnetic head. To solve this object the present invention provides a recording/reproducing system as stated in claim 1. With such an arrangement, the data pulses (DP) and the clock pulses (CP) are prevented from being output from the PLL circuit means (27), during the time period that the digital signal (RD) reproduced from the overwritten area (GAP2) of the magnetic recording medium (13) is supplied to the PLL circuit means (27). Therefore, there never occurs the situation that the reading means (29) detects the data recorded in the overwritten area (GAP2) as the synchronization data, and that consequently the address mark detect error will occur. The recording/reproducing system with high reliability can be realized. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1C show timing charts illustrating the track, the on/off timings of the read/write head when the data field is recorded, in connection with the on/off timing of the erase head; Fig. 1D shows a configuration of a preceding-erase type magnetic head; Fig. 2 shows a block diagram illustrating a circuit configuration of a data separator system which is a first embodiment of this invention; Figs. 3A to 3F show timing charts illustrating the operation of the circuit configuration of Fig. 1; and Fig. 4 shows a block diagram illustrating the configuration of a second embodiment of the data separator system according to this invention. A recording/reproducing system according to a first embodiment of this invention will be described, referring to the accompanying drawings. Its configuration will first be described. Magnetic head 11 of floppy disk apparatus (FDP) 10 has an erase head and a read/write head same as Fig. 1D. FDC 29 receives write data WD from a host computer (not shown), and supplies write data WD to write circuit 53. FDC 29 also supplies gate signal GS to write circuit 53 and selector 51. Gate signal GS functions as a write gate signal, an erase gate signal and a select signal. The write gate signal and the erase gate signal are supplied to write circuit 53. The select signal is supplied to selector 51. Selector 51 supplies write signal to the read/write head when the select signal is ON level. Selector 51 supplies output signal of the read/write head to prestage circuit 15 when the select signal is OFF level. Prestage circuit 15 is made up of an amplifier circuit, a time domain filter, and the like. Prestage circuit 15 amplifies the input signal, converts the output of magnetic head 11 into digital data, and outputs the data. The output data of prestage circuit 15 is supplied to external synchronization detect circuit 21 of data separator circuit 20 as read data RD. External synchronization detect circuit 21 detects the synchronization area of recording medium 13 on the basis of read data RD. In other words, external synchronization detect circuit 21 detects the synchronization data (fixed zero pattern data) recorded in the synchronization area on the basis of read data RD. External synchronization detect circuit 21 outputs an H-level pulse when it detects the synchronization data. The output signal S of external synchronization detect circuit 21 is supplied to the clock terminal CK of first D-type flip-flop (first D FF) 23. The D terminal of first D FF 23 is connected to an H level. Read gate signal RG to be described later is supplied to the low active CLR terminal of first D FF 23. First D FF 23 latches the H level signal at the leading edge of the output signal S of external synchronization detect circuit 21. The Q output Q1 of first D FF 23 is supplied to the the other input terminal of AND gate 25. Output signal PG of AND gate 25 is supplied to the control terminal C of phase locked loop (PLL) circuit 27. The read data RD is also supplied to the input terminal I of PLL circuit 27. PLL circuit 27 is provided with a voltage controlled oscillator in it, and operates so that the phase of the output pulses is equal to that of the input pulses. When the signal supplied to the control terminal C is at H level, PLL circuit 27 oscillates in synchronism with the read data RD, and separates the read data RD into data pulses DP and clock pulses CP (read operation). Data pulses DP are a pulse signal representing the data as written into the data areas on the tracks of the recording medium 13. Clock pulses CP are a pulse signal representing the timing for reading out data. PLL circuit 27, when the signal supplied to control terminal C is low in level, oscillates in synchronism with the clock signal (at the write center frequency), which is contained in the PLL circuit per se. Data pulses DP and clock pulses CP, which are output from PLL circuit 27, are supplied to floppy disk controller (FDC) 29. FDC 29 is connected to a host computer (not shown), and the like. FDC 29, as well known, receives a read command from the host computer, and controls read gate signal RG, thereby to control read operation. The data pulses DP and the clock pulses CP are also supplied to internal synchronization detect circuit 31. Upon detect of the synchronization data, internal synchronization detect circuit 31 outputs H level signal SYNC on the basis of the data pulses DP and the clock pulses CP, which come from PLL circuit 27. The output signal from internal synchronization detect circuit 31 is supplied to FDC 29. FDC 29, when the signal SYNC is high, executes the read/write operation of data. The data pulse DP and the clock pulse DP, which come from PLL circuit 27, are also supplied to address mark detect circuit 33. This circuit 33 detects address mark data (predetermined pattern data) as stored in the address mark areas in the tracks on recording medium 13, on the basis of the data pulses DP and the clock pulses CP. It then outputs H-level signal SAD. Output signal PG of AND gate 25 is supplied to the low active clear terminal CLR of address mark detect circuit 33. The signal SAD is supplied to clock terminal CK of second D FF 35. Read gate signal RG (to be described later) is supplied to the D terminal of second D FF 35. The signal PG of AND gate 25 is supplied to the low active clear terminal CLR of second D FF 35. At the leading edge of signal SAD, second D FF 35 outputs an H-level signal. The Q output Q2 of second D FF 35 is supplied to the input terminal of AND gate 37. Read gate signal RG is supplied to the low active, other input terminal of AND gate 37. The output signal of AND gate 37 is supplied to the clock terminal CK of monostable multi-vibrator (one-shot) (MMV) 39. At the leading edge of the output signal of AND gate 37, MMV 39 outputs a pulse signal to the other input terminal of AND gate 25. The pulse signal is kept at low level during time period Tg. Each track of magnetic recording medium 13 of this embodiment also has a format shown in Fig. 1A. And, when the data is recorded, the on/off of the erase head, and the on/off of the read/write head are timed as shown in Figs. 1B and 1C. An operation of the first embodiment will be described, referring to Figs. 2 to 3F. First, the recording operation will be described. The host computer supplies a write command to FDC 29. In response to this command, FDC 29 causes the gate signal GS to rise to H level. Gate signal GS functions as write gate signal, erase gate signal and select signal. Write circuit 53 receivers the write gate signal and the erase gate signal. When the write gate signal and the erase gate signal is H level, write circuit 53 generates a write signal and erase signal on the bases of write data WD supplied from the host computer via FDC 29 to write circuit 53. Write circuit 53 supplies the write signal to selector 51, and the erase signal to the erase head. When the select signal rises to H level, selector 51 supplies the write signal, which has been supplied from write circuit 53, to the read/write head. By the above-mentioned operation, the data previously recorded on medium 13 is erased by the erase head, and new data is recorded on medium 13 by the read/write head. Reproducing operation will now be described. When a host computer (not shown) sends a read command to FDC 29, FDC 29 causes gate signal GS fall to L level. When gate signal GS falls to L level, write circuit 53 stops generating the erase signal and the write signal. When the write signal is not supplied to the read/write head, read/write head reads the data recorded on medium 13, and outputs a signal corresponding to this data. When gate signal GS falls to L level, selector 51 supplies the output signal of the read/write head to prestage circuit 15. Prestage circuit 15 outputs read data RD. When external synchronization detect circuit 21 detects the synchronization data (predetermined zero pattern data) from read data RD, it outputs an H-level pulse to clock terminal CK of first D FF 23. At the leading edge of the pulse, first D FF 23 latches the H-level signal, and outputs H-level signal Q1 to AND gate 25. In the stationary state, Q output M of MMV 39 is at high level, as shown in Fig. 3F. At the detection of the data by external synchronization detect circuit 21, AND gate 25 outputs H-level signal PG to PLL circuit 27, as shown in Fig. 3C. Upon receipt of the H-level signal, PLL circuit 27 starts the synchronizing operation for read data RD. PLL circuit 27 oscillates in synchronism with read data RD, and separates data pulses DP and clock pulses CP from read pulse RD, and outputs the pulses. On the basis of data pulses DP and clock pulses CP, internal synchronization detect circuit 31 detects the synchronization data. Upon detection, circuit 31 outputs H-level signal SYNC. When supplied with H-level signal SYNC, FDC 29 starts the data read operation. Data pulses DP and clock pulses CP from PLL circuit 27 are supplied to address mark detect circuit 33. On the basis of data pulses DP and clock pulses CP, address mark detect circuit 33 detects the address mark data recorded in address mark area AM in the ID field. It then outputs pulse signal SAD, as shown in Fig. 3D. At the leading edge of signal SAD, second D FF 35 latches read gate signal RG. At this time, because read gate signal RG is at high level, as shown in Fig. 3B, second D FF 35 outputs H-level signal Q2, as shown in Fig. 3E. AND gate 37 keeps the outputting of the L-level signal, because read gate signal RG is high. MMV 39 keeps the outputting of H-level signal M, because no trigger is input to MMV 39. AND gate 25 also keeps the outputting of H-level signal PG. PLL circuit 27, supplied with H-level signal PG, continues the synchronizing operation for read data RD. FDC 29 reads out the data recorded in the ID field. After completing the read operation for the ID field, FDC 29 resets read gate signal RG to the low level (Fig. 3B). Upon receipt of L-level read gate signal RG, AND gate 37 outputs an H-level signal to MMV 39. With the trigger of the leading edge of the output signal of AND gate 37, MMV 39 outputs negative pulse M. The pulse M keeps its L-level during fixed period of time Tg, as shown in Fig. 3F. The pulse width Tg is substantially equal to the time required for magnetic head 11 to read areas GAP 2 in the tracks. In other words, the pulse width Tg is substantially equal to the required for read data RD reproduced from the data overwritten area in the tracks to be supplied to PLL circuit 27. Upon receipt of negative pulse M, AND gate 25 renders control signal PG low in level, as shown in Fig. 3C. Upon receipt of L-level control signal PG, PLL circuit 27 stops the synchronizing operation for read data RD, and stops the operation for separating data pulses DP and clock pulses CP from read data RD. PLL circuit 27 synchronizes with the clock in the PLL circuit 27. When supplied with L-level read gate signal RG, first D FF 23 is cleared. When supplied with L-level signal PG, address mark detect circuit 33 and second FF 35 are also cleared. To read the data field, FDC 29 again renders read gate signal RG high. Afterwards, when external synchronization detect circuit 21 detects the synchronization data, the same operation as the read operation for ID field is started. PLL circuit 27 then performs the synchronizing operation for read data RD. FDC 29 performs the data readout. When the data field has been read, FDC 29 renders read gate signal RG low. Upon receipt of negative pulse M, PLL circuit 27 stops the synchronizing operation for read data RD during fixed time period Tg. This stoppage prevents PLL circuit 27 from synchronizing with the read data RD at varying frequency that is reproduced from the DC erased area of the tracks. As described above, during time period Tg after the data readout from the ID field or the data field completes, PLL circuit 27 does not perform the synchronizing operation for read data RD. In other words, when read data RD reproduced from the overwritten areas (GAP2) and DC erased areas (GAP3) is supplied to PLL circuit 27, PLL circuit 27 does not perform the synchronizing operation for read data RD. Even if the same data as the synchronization data is recorded in the overwritten area (GAP2), there never occurs the situation in which detect error of the address mark data occurs at the boundary between the overwritten area (GAP2) and the synchronization area (SYNC). Further, there never occurs the situation where PLL circuit 27 synchronizes with the read data at varying frequency from DC erased area (GAP3),and that the PLL circuit 27 oscillates at a frequency greatly shifted from the original oscillating frequency. A second embodiment of the invention will now be described, referring to Fig. 4. Fig. 4 is a block diagram illustrating the second embodiment. The main portions of the 5 circuit are the same as those of the Fig. 2 circuit. Therefore, only the features of the second embodiment will be given. The structural features of the second embodiment, when comparing with those of the first embodiment are: (1) Signal Q1 is directly supplied to control terminal C of PLL circuit 27, with omission of AND gate 25; (2) AND gates 41 and 43 are additionally used, and clock pulses CP are supplied to one input terminal of AND gate 43, while signal M is supplied to the other input terminal of each AND gate 51 and 43; (3) The outputs of AND gates 41 and 43 are supplied to internal synchronization detect circuit 31. According to the Fig. 4 configuration, PLL circuit 27 continuously performs the synchronizing operation for data RD even when negative pulse M is output. However, the supply of data pulses DP and clock pulses CP from PLL circuit 27 to internal circuit is inhibited during the pulse time TG of negative pulse M. In other words, at least after the readout for ID field or data field, for the duration of negative pulse M, data pulses DP and clock pulses CP are not supplied to internal synchronization detect circuit 31. This prevents internal synchronization detect circuit 31 from detecting synchronization data from overwritten area GAP2. Therefore, FDC never outputs a detect error for the address mark data at the boundary between areas (GAP2) and synchronization area (SYNC). As seen from the foregoing, according to this invention, when read data RD reproduced from GAP areas (GAP2 and GAP3 in Fig. 1A) of the tracks of the magnetic recording medium is supplied to PLL circuit 27, the PLL circuit 27 stops the synchronizing operation and the signal out putting. Accordingly, with the data separator system of this invention, the synchronization data can be accurately detected from the synchronization area of the magnetic recording medium, and normal data can be reproduced from the data area. It is not essential that the pulse width Tg of pulse M is set to to be equal to the width corresponding to the length of gap areas GAP2 and GAP3. If the detection error of the address mark data from FDC 29 can be prevented, it is only needed that the operation of PLL circuit 27 can be stopped during at least part of the time period that the read data is supplied to circuit 27. The width Tg is appropriately selected allowing for the system characteristics. The PLL circuit, address mark detect circuit, and synchronization detect circuits may be those known circuits. For the address mark detect circuit, for example, any circuit may be used, if it can detect the predetermined address mark data (for example, the missing cross) recorded in the address mark in the track. As a one-chip controller containing a floppy disk controller (FDC) and internal synchronization detect circuit, µDP7260 manufactured by NEC is known. Any IC with the performance comparable with that of this IC may be used. In the embodiments, FDC29 is provided outside FDP10 and data separator circuit in Fig. 2. In practice, FDC 29 may be incorporated into FDP10 and/or circuit 20.

Claims: A recording/reproducing system comprising: a magnetic head (11) in contact with a flexible magnetic recording medium (13), for recording data on said magnetic recording medium 13 and reading out data stored in said recording medium (13), said magnetic head (11) having a read/write head for writing data on, and reading data from, said magnetic recording medium (13), and an erase head arranged for erasing data recorded on said magnetic recording medium (13); write means (53) for turning said magnetic head (11) on, thereby to erase data recorded on said magnetic recording medium (13), and to write data on said magnetic recording medium (13); digital signal-outputting means for outputting a digital signal corresponding to the data read out by the read/write head from said magnetic recording medium; PLL (Phase Locked Loop) circuit means (27) for receiving the digital signal, and for oscillating in synchronism with the digital signal, thereby to output data pulses (DP) and clock pulses (CP); readout means for receiving the data pulses (DP) and the clock pulses (CP) and reading out data from said magnetic recording medium (13) in accordance with the data pulses (DP) and the clock pulses (CP); external synchronization detecting means (21) for detection synchronization data formed of predetermined pattern data, in accordance with the digital signal, and for enabling said PLL circuit means (27) to oscillate in synchronism with the digital signal after the synchronization data has been detected; and internal synchronization detecting means (31) for detecting the synchronization data in accordance with the data pulses and the clock pulses output from said PLL circuit means (27); wherein: said magnetic head (11) is a preceding-erase type magnetic head, said erase head being arranged in front of said read/write head; said write means (53) turns said-read/write head and said erase head on substantially simultaneously and supplies a specified signal to said read/write head, thereby to erase data recorded on said magnetic recording medium (13), and to write data on said magnetic recording medium (13); and said system further comprises preventing means (25, 33-39) for preventing said PLL circuit means (27) from outputting pulses in synchronism with said digital signal when said digital signal (RD) is reproduced from overwritten areas (GAP2), existing on the tracks of said magnetic recording medium (13), which have not been erased and in which new data has been written over the previously written data, said preventing means working by inhibiting said PLL circuit means (27) when a predetermined signal has been detected. A system according to claim 1, characterized in that said preventing means (25, 33 to 39) prevents said PLL circuit means (27) from outputting said data pulses (DP) and said clock pulses (CP) for a fixed period of time after the completion of the read operation of each ID field in tracks of said recording medium (13). A system according to claim 1, characterized in that said PLL circuit means includes a PLL circuit (27), and said preventing means (25, 33 to 39) prevents said PLL circuit (27) from performing the synchronizing operation for said digital signal. A system according to claim 3, characterized in that said PLL circuit (27) performs the synchronizing operation for a predetermined reference clock when said preventing means (25, 33 to 39) prevents said PLL circuit (27) from performing the synchronizing operation for said digital signal. A system according to claim 1, characterized in that said PLL circuit means includes a PLL circuit (27), and said preventing means (25, 33 to 39, 41, 43) prevents the data pulses (DP) and clock pulses (CP) output from said PLL circuit (27) from being output to outside of said PLL circuit means. A system according to claim 1, said system further comprising a floppy disk controller (29) for reading out the data recorded on the magnetic recording medium (13) on the basis of said data pulses (DP) and clock pulses (CP) and the operation of the internal synchronization detect circuit (31), and wherein said preventing means (25, 33 to 39) prevents the outputting operation of the PLL circuit means (27) for a fixed period of time following the outputting of a signal, representing the completion of the readout of data recorded in each field in tracks of said recording medium (13), which is output from said floppy disk controller (29). A system according to claim 1, characterized in that said preventing means (25, 33 to 39) includes a means (29) for outputting a signal (RG) for indicating that the readout of each field in tracks of said recording medium (13) is completed, and a circuit (25, 39) for outputting an operation-preventing signal of predetermined pulse width to said PLL circuit means (27), in response to said signal (RG) indicating the end of the readout operation.

Inventors: SUZUKI, HIROSHI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: G11B5
IPC codes: G11B20, G11B27, G11B19, G11B5