Image processing system

Abstract: An image processing system comprising a first and second video signal sources (1, 2) providing a main-field video signal and sub-field video signal, respectively, means for compressing the sub-field video signal on the time axis, and a signal merging unit (26) which merges the compressed sub-field video signal into the main-field video signal and delivers the resulting signal to a television receiver set, wherein the signal compressing means comprising a dual-port memory (12) having a first and second ports (60, 62) and operating to compress the sub-field video signal on the time axis and store the compressed signal, and control means (13, 14) for controlling the reading and writing of the memory for the sub-field video signal, the control means comprising a first control section for writing the sub-field video signal into the first port of said memory, a second control section for trasferring a signal from the first port to the second port, and a third control section for reading out a signal from the second port, said memory implementing the reading operation and writing operation in asynchronous manner.

Description: The present invention relates to an image processing system. The image processing system of the present invention is especially suitable for use in an apparatus which receives two different video signals (for example, video signals from a magnetic recording/reproducing apparatus such as a video tape recorder and from a signal source such as a television tuner) compresses one of the two video signals on the time axis, merges the compressed video signal into the other video signal, and supplies the resultant signal to a Braun tube in a television set so that two-field images are displayed simultaneously on the Braun tube. Such a system which simultaneously displays two different video signals on one Braun tube, is well known and is called a "picture-in-picture system". A conventional apparatus using the above-described system is provided with two memories for storing one of the two different video signals to be displayed in a sub-field (small area) of the Braun tube. In another known embodiment the sub-field is stored in a one-field memory and buffered in an additional buffer memory (EP 175 590). A multiplexer feeds the luminance signal Y and the color difference signals R-Y and B-Y alternatively to an A/D converter (IEEE Transactions on Consumer Electronics, vol. CE-25, Feb/1979, pages 152-158; M. Masuda et al.: "Fully digitalized color picture in picture television system"). The video signal is sequentially written into the memories and at the same time the signal is read out from the memories in a compressed form. The retrieved signal is merged into the other video signal to be displayed in a main-field (large area) on the Braun tube. Writing and reading of the two memories are switched at the input and output stages of the memories in synchronism with the two video signals. Namely, writing into the memories is in synchronism with the sub-field video signal, while reading from the memories is in synchronism with the main-field video signal. However, in the above-mentioned systems with the ability of simultaneous reading and writing of the memories, the main-field and sub-field video-signals are usually out of phase with each other, and therefore the memory contents is often replaced with the next field information in the course of monitoring the sub-field, with the result that different images are displayed on the upper and lower portions of the sub-field. In this way, when pictures of different fields in its upper and lower portions are connected, it is indistinct in a high speed picture and unpleasant since brightness changes at a joint. Furthermore, if the memory has only one field, the resolution of the picture is less than that of a picture in which two odd/even pictures are employed. An object of the present invention is to provide an image processing system which is simple in structure and is capable of satisfactory sub-field display. To achieve the above objective, discriminating means for discriminating odd/even fields of each main-field and sub-field picture, memory means for storing information of the sub-field picture, and address control means for controlling read/write timing of the sub-field picture information are employed. The sub-field coincides with the result of the field discrimination of the main-field picture to/from the memory means at an appropriate timing. In this invention, a high resolution picture is realized compared to systems having only one field picture information, and no jolt in the vertical direction appears since the memory means includes both odd/even information, and the memory address control means supplies information which coincides with the result of the discrimination of the main-fields picture. Furthermore in this invention, a joint of two field appearing in the sub-field picture results in that rewriting new information during reading is prevented since the memory address control means controls so that the reading phase is always proceeding in a memory area corresponding to one field. Fig. 1 is a block diagram showing one embodiment of the inventive image processing system; Figs. 2 and 3 are block diagrams showing part of the video signal processing unit; Fig. 4 is a block diagram showing an example of the outrun inhibit circuit; Figs. 5, 6 and 7 are diagrams of displays on the screen and waveform diagrams of signals, all pertinent to the explanation with Fig. 4; Fig. 8 is a block diagram showing an example of the field discrimination circuit and false operation preventing circuit; and Figs. 9 and 10 are waveform diagrams used for the explanation with Fig. 8. Embodiments of the present invention will be described with reference to the drawings. Fig. 1 shows in block diagram the image processing system representing one embodiment of this invention. This embodiment is capable of accomplishing "picture-in-picture" for the sub-field with high picture equality using only one memory. According to this embodiment, the disturbance in sub-field which is caused by the outrun of the memory read phase over the memory write phase, i.e., the misalignment of sub-field video signals (2-field display) read out of the memory, can be prevented. The embodiment will be described in detail with reference to the drawing. Shown by 301 and 302 are sync separation circuits connected to the first and second video signal sources for separating the vertical and horizontal sync signals from the video signal, 303 and 304 are field discriminating circuits for discriminating the field of the main-field video signal by receiving the sync signals, 305 is a false operation preventing circuit, 3' and 4' are switches operated in unison and connected to the outputs of the field discriminating circuits 303 and 304; 306 is a field information read/write outrun inhibit circuit which receives the sigal passing the switches and produces a control signal for controlling the switching control circuit 5 and a control signal for controlling the dual-port memory 12 in the time-axis compressing circuit in the video signal processing unit 220, and a television receiver set 16. In the above arrangement, the video signals including the main-field video signal and sub-field video signal originating from the video signal sources 1 and 2 are fed to the sync separating circuits 301 and 302, respectively, by which the vertical sync signal and horizontal sync signal are separated. The video signals are further fed through the field discriminating circuits 303 and 304 and switches 3' and 4', and supplied to the outrun inhibit circuit 306. At the same time, the main-field video signal from the video signal source 2 is fed through the switch 3 to one input terminal of an adder 26. The sub-field video signal from the video signal source 1 is fed through the switch 4 to the memory 12, and after it is compressed on the time-axis by the memory it is delivered to another input terminal of the adder 26. The main and sub-field video signals merged by the adder 26 are delivered to the television receiver set 16, on which two fields are displayed to accomplish the "picture-in-picture" function. In this operation, the false operation preventing circuit 305 and switching control circuit 5 play a protective role for coping with the field discrimination for the sync signals disturbed by noises and the transitional operation at exchange of two fields, and these circuits may be simplified or eliminated in some cases. Next, the arrangement and operation of the individual functional blocks will be described in more detail using waveform diagrams. Figs. 2 and 3 are block diagrams for explaining the read/write operations of the memory 12. Shown in Fig. 2 by 10a is an analog-to-digital (A/D) converter, 10b is a sampling circuit, 10c is an automatic phase controller, 10d is a clock signal generator, 11a and 15a are switches, 60a-60d are areas of a memory 12, and 19 is a digital-to-analog (D/A) converter. In operation, the sub-field video signal S1 in a digital form at the end of the A/D converter 10a is sampled by the sampling circuit 10b in response to the clock signal provided by the clock signal generator 10d. The clock signal is controlled by the automatic phase controller 10c to be in-phase with the burst signal of the sub-field video signal S1, and it has a frequency twice or more of the burst signal. The sampled signal is written into any of the areas 60a-60d in the memory 12. The memory readout operation takes place in asynchronous manner with the write operation. The memory read and write operations are carried out by switching the switches 11a and 15a by the control signal C (C1 and C2) from the outrun inhibit circuit 306 based on the result of field discrimination by the field discriminating circuits 303 and 304. Transforming the signal read out of the memory areas 60a-60d into an analog signal by the D/A converter 19 results in a signal S1' which is a time-axis compressed version of the sub-field video signal S1. Shown in Fig. 3 by 6 is a luminance signal extractor, 8 is a color-difference separator, 8' is an automatic phase synchronization control circuit, 9 and 19d are switches, 10e is a color-difference and luminance switching circuit, 19a and 19b are D/A converters, and 19c is an adder. The difference between Fig. 2 and Fig. 3 is whether or not the sub-field video signal S1 is decomposed into the luminance signal and color-difference signal. The former can be called "composite system", and the latter "component system". The following describes the operation of the component system. The NTSC signal forming the video signal S1 in Fig. 3 is known to be the quadrature modulation of the color-difference signal in which two kinds of color information are modulated in the phase difference relative to the burst signal, and therefore demodulation of this signal necessitates the clock signal which is in-phase with the burst signal. As an example of the arrangement for the clock generation, the automatic phase synchronization control circuit 42 is used for the control. The circuit is known in the art and its detailed explanation will be omitted. The color signal separator 8 is merely required to demodulate the color-difference signal from the NTSC signal, and a commonly used demodulator suffices for this purpose. The luminance signal is extracted by the luminance signal extractor 6, and also in this case a usual low-pass filter suffices for the purpose. The input signal which has been decomposed into the luminance signal and color-difference signal is fed through the switch 9 to the A/D converter 10a, by which it is transformed into digital data in a time slicing manner. After that the data is stored in the memory areas 60a-60d by way of the sampling circuit 10b and switch 11a. This management of the signal is due to the use of a single A/D converter, and in exchange for the provision of a plurality of A/D converters the switch circuits 9 and 19d and the color-difference and luminance switching circuit 10e can be eliminated. In synchronism with the clock signal produced by the clock signal generator 10d, the switch 19d is operated by the signal C4 and at the same time sampling is implemented by the sampling circuit 10b. Accordingly, when the switch 19d is positioned to a ○-terminal, the luminance signal is A/D converted and sampled by the samping circuit 10b and then written in the memory areas 60a-60d. With the switch 19d positioned to b ○-terminal, the color-difference signal is sampled and written in the memory areas 60a-60d. For reading, the switch 19d is operated in synchronism with the reading of the memory areas 60a-60d. Namely, the read clock is controlled by the color-difference and luminance switching circuit 10e so that the luminance and color-difference signals are read out in a prescribed order, and the switch 19d is operated at this timing. In consequence, the switch 19d is positioned to a ○-terminal at reading of the luminance signal out of the memory areas, while the switch is positioned to b ○-terminal at reading of the color-difference signal, and after being transformed into analog signals by the D/A converters 19a and 19b both signals are merged by the adder 19c. This summing operation implies modulation to the NTSC signal, and a usual NTSC modulator suffices for the purpose. Next, a specific arrangement and operation of the outrun inhibit circuit 306 will be described. Fig. 4 shows in block diagram the arrangement of the outrun inhibit circuit 306, Fig. 15 explains the circuit, and Fig. 17 is a waveform diagram used to explain the operation of the circuit. In Fig. 4, shown by 306a is an AND gate, 306b is a sub-field trigger generator, 306c and 306d are flip-flops, and 306e and 306f are decoders. In Fig. 5, shown by 16a and 16b are screens on the Braun tube of the television receiver set. In Figs. 6 and 7, shown by T1 through T17 are time bands on the signal waveforms. The main-field and sub-field discrimination signals f1 and f2 are the input signals to the outrun inhibit circuit 306. The operation of the outrun inhibit circuit 306 will be described. The field discrimination signal f2 for the sub-field is divided in frequency by two by the flip-flop 306d, which produces a signal 60 on its Q-output. The field discrimination signal (information) f1 for the main-field is taken AND by the AND gate 306a with the sub-field trigger signal 61 produced by the sub-field trigger generator 306b. The sub-field trigger signal 61 is a pulse which rises when the scanning spot has reached a point al on the screen 16a (see Fig. 5), and it indicates the starting time point for the sub-field display (the falling time point is arbitrary). The resulting signal 62 is used as a data input trigger for the flip-flop 306c. The flip-flop 306c has its input terminal D receiving a signal 60 which is the result of frequency division for the signal f2 by the flip-flop 306d, and therefore the flip-flop 306c produces a signal 63 on its Q -output. The following Table 1 lists the states of the signal f2 and signal 60 in the time bands T1 and T4 and the signal f1 and signal 63 in the time bands T5-T9. (pertinent to Fig. 6) Time band T1 T2 T3 T4 Signal f2 H L H L Signal 60 H H L L Time band T₅ T₆ T₇ T₈ T₉ Signal f1 H L H L H Signal 63 H H L L H (H: high, L: low) In case the phase relationship between the main and sub-field video signals has varied, resulting in another waveform diagram shown in Fig. 7, the states of the signal f2 and signal 60 in the time bands T10-T13 and the signal f1 and signal 63 in the time bands T14-T17 are as shown in Table 2. (pertinent to Fig. 7) Time band T10 T11 T12 T13 Signal f2 H L H L Signal 60 H H L L Time band T₁₄ T₁₅ T₁₆ T₁₇ Signal f1 H L H L Signal 63 L L H H (H: high, L: low) The operation of the decoders 306e and 306f for operating the switches 11a and 15a in Fig. 2 or Fig. 3 in response to the control signals C1 and C2 produced following the reception of the signals f2 and 60 or signals f1 and 63 is stated as shown in the following Table 3. According to the outputs f1 and f2 of the field discrimination circuits 303 and 304, writing to any of memory areas 60a-60d and reading from any of memory areas 60a-60d in the memory area 60 are controlled. In the preceding example, with the phase relationship between the main and sub-field video signals shown in Fig. 7, the time difference between reading and writing of a memory area is greater than 1-field scanning length. In the phase relationship shown in Fig. 6, the time difference between reading and writing is short, but in this case reading always precedes writing for a memory area. For example, at time t1 in Fig. 6, the signal f2 and signal 60 are both low, causing the write switch 11a to position to c ○-terminal, as indicated in Table 3, while the signal f1 and signal 63 are both high, causing the switch 11a to turn to b ○-terminal. At the time point when the scanning has reached the sub-field al as shown in the screen 16a of Fig. 5, the bl information for the screen 18b is written in the memory, but in this case reading takes place for the memory area 60d are writing takes place for the memory area 60c. At time t2 in Fig. 6, the signals f2 and 60 go high, causing the switch 11a to turn to b ○-terminal. Reading and writing take place for the same memory area 60c, but in the time band T5 reading for the memory area 60c always precedes, and therefore the writing phase never outruns the reading phase. Reading of the memory area 60c completes at time t3, and a short while later following the end of the time band T1, writing of the memory area 60c completes. For the same memory area, the reading phase and writing phase becomes closest when the signals f2, 60 and 63 rise coincidently (at this time the signal f1 is fixed to high), but even under this condition reading always precedes writing except for a coincident moment at the beginning of reading and writing for a memory area. Accordingly, the outrun phenomenon can be prevented by the present invention. Next, a specific arrangement and operation of the field discrimination circuit 303 and false operation preventing circuit 305 shown in Fig. 8 will be described. In the figure, shown by 303a is a horizontal sync separator, 303b is a vertical sync separator, 303c is a pulse generating circuit, 303d is a reversible counter, 303e is a logic circuit, 303f is a flip-flop, 305a is a frequency division counter, and 305b is a discrimination circuit. Shown by 134 is a preset pulse applied to the reversible counter 303d, and 135 is a latching pulse for the output of the reversible counter 303d. The operation of the above arrangement will be described with reference to the principal signal waveforms shown in Figs. 9 and 10. The sync-separated signal 130 is fed to the horizontal sync separator 303a and vertical sync separator 303b, by which a horizontal sync signal 131 and vertical sync signal 132 are extracted. The number of pulses of the horizontal sync signal 131 in the outside of the period of the vertical sync signal 132 varies in each field, and the number of pulses of the horizontal sync signal within the vertical sync signal period (a, b, c) also varies in each field. It is a matter of choice to count the number of pulses of the horizontal sync signal 131 inside or outside of the vertical sync period, but in this embodiment to save the bits count, the number of pulse of the horizontal sync signal 131 within the vertical sync period (a, b, c) is counted. For this purpose, the pulse generating circuit 303c extracts horizontal sync pulses 133 within the vertical sync periods a, b and c, and supplies them as a clock to the reversible counter 303d. The reversible counter 303d reveals the difference of horizontal sync pulses 133 among the consecutive vertical sync periods a, b and c. Namely, the circuit bases the field discrimination on the difference of horizontal sync pulses 133 in consecutive vertical sync periods. The field discrimination operation will be described in more detail in the following. The flip-flop 303f doubles the period of the vertical sync signal 132, and the first horizontal sync pulse (e) during the high period of that vertical sync signal and following the falling of the original vertical sync signal is used to make a latching pulse 134, and the subsequent horizontal sync pulse (d) is used to make a presetting pulse 135. In this embodiment, the reversible counter 303d is made up of three bits having bit outputs Q1, Q2 and Q3, and the counter is preset to have '111' on the Q1, Q2 and Q3, i.e., a preset value of '7'. The reversible counter 303d is designed to up-count in response to a high output signal (f1) from the flip-flop 303f and down-count in response to a low output signal f1. Under these operating conditions, the reversible counter 303d which has been preset to value '7' in response to the preset pulse 135 at time point d operates to down-count (because of the low signal 136) the horizontal sync pulses 133 within the period of the next vertical sync signal 132. Accordingly, the counter 303d down-counts from '7' to '6' to '5' and to '4' as shown by 137 in Fig. 9, and in the next vertical sync period c up-counts the pulses 133 from '5' to '6' to '7' and to '0'. The count value is latched in response to the latch pulse 134 at e. When the signal 136 goes high in periods (a and c) including a larger number of horizontal sync pulses among the vertical sync periods a, b and c, as in the above case, the latched count value is rendered zero. In another case shown in Fig. 10, where the vertical sync periods a, b and c include horizontal sync pulses 133 in '3', '4' and '3' in number, respectively, the latched count value when the signal 136 goes low in the period (b) including a larger number of horizontal sync pulses is '7'. The above latching operation and discrimination of the count value are the role of the logic circuit 303e, and it suffices to determine whether the latched value of Q3 is high or low. If the signal 136 in Figs. 9 and 10 is used as the field discrimination signal f1, one of the cases of Figs. 19 and 20 is a false judgement, and therefore the phase of the flip-flop 303f is unchanged or unchanged or inverted depending on this judgement result. In this case, single judgement result can be erroneous due to a noise component on the sync signals, and therefore it is desirable to make a final decision using several judgement results. The false operation preventing circuit 305 is provided for this purpose, and it includes a decision circuit 305b which makes a final decision upon consistent results of count for the vertical sync signal 132 (or signal 136) by the counter 305a. The flip-flop 303f is controlled to reverse upon successive false decisions in several count operations, and the noise immunity of the operation can be enhanced significantly. As for the switching control circuit 5 in Figs. 1 and 2, it serves to exchange the main-field and sub-field in 2-field display. The circuit is operated in synchronism with the vertical sync signal to gain the smoothness. Since the circuit can be arranged using known means, and its detailed explanation will be omitted. According to the foregoing embodiments of this invention, 2-field patches at the top and bottom of the screen, which has occurred in the conventional 2-field display system in displaying a sub-field due to outrun of read/write phases, can be eliminated, and a sub-field display can be a complete 1-field picture even in the case of fast motion, whereby the performance can effectively be improved.

Claims: An image processing system for compressing a sub-field picture signal by using a memory (12) for storing picture information of the sub-field picture signal and for outputting the compressed sub-field picture signal synthesized - in a signal merging unit (26) - with a main-field picture signal, wherein the memory (12) is a dual-port memory having a first port and a second port and implementing its reading operation and its writing operation in asynchronous manner, characterized by, field discriminating means (303, 304) which discriminates odd-numbered and even-numbered fields of the main-field video signal and the sub-field video signal, memory address control means (306) for controlling the writing of said sub-field picture information into a certain area of said memory means (12) according to the result of said field discrimination of the sub-field picture and for controlling the read-out of stored information from a selected one of said areas in response to the result of said field discrimination of both the main-field and sub-field picture. An image processing system according to claim 1, wherein said memory (12) is capable of storing four fields of sub-field video signals, and the system further comprises, divider means for dividing the discriminating sub-field video signals; displaying period control means (306b) which outputs a displaying period signal of the sub-field video signals; merging means with merges main-field video signals and sub-field video signals for output in accordance with the controlled displaying period signal; said memory address control means (306) comprising write address control means for deciding an address area in said memory to write information in accordance with the discriminated sub-field video signals and the divided sub-field video signals and; read address control means for deciding the read address area in the memory according to said discriminating main field video signals, the displaying period signal and said divided sub-field video signals. An image processing system according to claim 1, wherein each of said field discriminating means for main-field and sub-field video signals comprises; a reversible counter which counts the number of horizontal sync signals inside or outside a vertical sync signal period of the image and sub-field video signals, means for presetting said reversible counter once in N periods (where N is a positive integer) of the vertical sync signal, sample-holding means which samples and holds the contents of said reversible counter immediately before presetting, second frequency-division means which implements frequency division for the vertical sync signal, and frequency division phase control means which varies the frequency-division phase of said second frequency-division means in accordance with the output of said sample holding means. An image processing system according to claim 3, further comprising a counter for counting the vertical sync signal or the output of said second frequency-division means, variation detection means which detects whether or not the output of an sample-holding means varies during a certain count period of said counter, and means for operating on said frequency-division phase only at the detection of variation by said variation detecting means.

Inventors: MASUDA MICHIO, NISHIJIMA HIDEO, OHTSUBO HIROYASU, OKAMOTO KANEYUKI, ONO KOICHI, MASUDA, MICHIO, NISHIJIMA, HIDEO, OHTSUBO, HIROYASU, OKAMOTO, KANEYUKI, ONO, KOICHI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1987
Main classification: H04N5
IPC codes: H04N5