CERAMIC COMBINED COVER FOR A SEMICONDUCTOR PACKAGE

Abstract: A combination ceramic sealing cover for a semiconductor package has a flat ceramic lid member with metallization applied as a foundation for a seal ring or frame portion. On the metallized layer is a gold-tin solder layer, in the form of either a solder ring that is tack welded on, or solder paste that is screened onto the base metallization and furnace reflowed.

Description: This invention relates to hermetic sealing covers for enclosures or containers, and is more particularly directed to combination sealing covers or lids with incorporated sealing rings for packages for semiconductor devices. Previous sealing covers and lids have been proposed to produce a package that is resistant to corrosion, especially in salt atmospheres. This is required to satisfy specifications of finished packages, such as Mil-Std-883C, Method 1009, Test Condition A, Salt Atmosphere (corrosion). In the packaging of high reliability micro-circuits, a semiconductor chip is typically housed with a cavity formed in a ceramic housing and a lid is sealed to the housing to close the package. This lid is generally formed of an iron based metal called Kovar (Registered US Trade Mark of Carpenter Technology Corporation) and the seal is formed by a pre-formed solder frame that is placed between the lid and package housing. A lid is described in US-A-4 601 958. This lid is formed of a Kovar substrate (Kovar is an alloy of nickel iron and cobalt), covered with alternate layers of nickel and gold electroplate. The lid is affixed, using an 80/20 Au/Sn solder ring preform, to the semiconductor package. These lids are quite resistant to corrosion. However, because the Kovar base is corrosible, the entire lid must be completely covered with the Ni and Au plated layers. The nickel electroplate process is rather slow, which leads to long process times and hence high cost. Also, the two gold layers increase the expense of the lid considerably. Moreover, if a lid is defective and it is necessary to scrap the lid, the buried gold layer is not salvageable, so its gold value is lost. The semiconductor industry has long sought a cover which would be extremely corrosion resistant, but could be easily manufactured with a minimum use of precious metals. Objects and Summary of the Invention According to one aspect of this invention, a semiconductor device package has a lid that is formed as a flat ceramic sheet substrate. One side of the substrate faces the package, and a plural-layer sealing ring is formed on the perimeter of that side. The sealing ring includes a precious-metal layer formed directly on the ceramic substrate, and a solder layer on the precious metal layer on the side away from the substrate. The metal layer can be Mo-W refractory metallization, covered with nickel deposition and gold electroplate, the latter providing a surface for wetting the solder layer. The solder layer can be a solder paste that is screened on, or can be a gold-tin solder frame that is tack-welded on. In alternative embodiments the base metal layer can be a gold thick-film or a Pd-Ag thick-film. In another embodiment, the base-layer metallization can be an active-metal process, such as titanium alloy, which is covered with nickel followed by gold. The above and many other objects, features, and advantages of this invention will become more fully apparent from the ensuing detailed description of several preferred embodiments of this invention, which is to be read in connection with the accompanying drawing. Brief Description of the Drawing Fig. 1 is a perspective view of a semiconductor package with a combination cover formed of a ceramic lid and a thick-film metallized sealing ring, according to an embodiment of this invention. Figs. 2, 3, 4 and 5 are partial perspective views of ceramic combination covers according to respective embodiments of this invention. Detailed Description of the Preferred Embodiments With reference to the drawings, Fig. 1 shows a semiconductor package assembly (10) for encapsulating a semiconductor device (12), such as an integrated circuit. The package has a main body (14) with a cavity (16) therein for receiving the semiconductor device (12). The body (14) has a conductive ring or frame (18) for receiving a hermetically sealing combination cover (20). Here, the cover (20) has as the lid a ceramic sheet substrate (22) of a nominal thickness of about 635 micrometers (0.025 inches). The substrate (22) can be of any suitable ceramic material, such as black alumina, white alumina, or sapphire. The latter material is useful for encapsulating programmable read only memories (PROM'S) as it permits reprogramming using ultraviolet light. The ceramic cover (20) has, on the periphery of the surface of the substrate (22) that faces the body (14), a sealing ring formed by either refractory or active metallisation either cofired with the ceramic ("green tape" process) or fired after the ceramic and then electroplated with a solderable metal or covered using a thick-film metallisation technique. The base metallisation layer (24) is of a material that is capable of being wetted by gold-tin solder of the layer (26), or else is plated with a metal that is so capable. The solder layer is an 80/20 Au/Sn ring tack welded on, or an Au/Sn solder paste, which is screened on over the base metallisation layer (24), and then reflowed. A first embodiment of the lid of this invention is shown in Fig.2. Here the ceramic substrate (22) carries a selectively applied base metallisation (24) which can be of a refractory molybdenum-tungsten material. This layer, which is either cofired with the ceramic material, or is laid down and fired on a previously fired ceramic substrate, has a minimum thichness of five micrometers. The metal layer (24) is covered with a layer of nickel electroplate (28), with a thickness of approximately 2.5 micrometer (one hundred micro inches), and this layer (28) is followed by a gold electroplate layer (30) of approximately 1,25 micrometer (fifty micro inches). The solder layer (26) is here in the form of a pre-cut gold-tin solder frame, which is tack welded onto the gold layer (30). The gold layer (30) is readily wettable by the solder layer (26), and is also extremely corrosion resistant. A cover (120) according to a second embodiment of this invention is shown in Fig.3, and comprises a flat ceramic substrate (122) to which is selectively applied a precious metal thick-film ring layer (124), with a minimum thickness of ten micrometers. The preferred material for this embodiment is Dupont 9110. After this layer (124) is fired, a layer (126) of gold-tin solder paste is screened on, and is furnace reflowed. A cover (220) according to a third embodiment of this invention is shown in Fig.4, and comprises a flat ceramic substrate (222) which carries a titanium-alloy active metallisation layer (224). This layer (224) is preferably at least five micrometers in thickness. After firing the metallisation layer (224), a nickel electroplate layer (228) of approximately 2,54 micrometers (one hundred micro inches) thickness, and a gold electroplate layer (230) of approximately 1,25 micrometer (fifty micro inches) thickness, are deposited in that order atop the thick-film layer (224). Then, a gold-tin solder paste layer (226) is screened on and reflowed. A cover of layer (320) according to a fourth embodiment of this invention is shown in Fig. 5. Here, a ceramic substrate (322) has a palladium-silver thick-film layer (324) with a thickness of ten micrometers laid down on the substrate (322) and subsequently fired. The palladium-silver thick-film material is preferably Dupont 6120 or Dupont 6124. In this embodiment, a gold-tin solder ring (326) is tack-welded directly onto the palladium-silver thick-film layer (334). The layer (24) our (224) can be co-fired with the ceramic substrate (22) or (220), or can be fired separately on previously kilned ceramic material. The furnace reflow of the solder layer (26,126,226,326) takes place typically with a dwell time of two minutes at 350°C, in a dry nitrogen atmosphere. The details of the process of forming these covers is described in US-A-4,746,583. The technique for tack welding of the solder ring (26) or (326) is well known, and the details need not be described here. Of course, the solder layer (26) can be another precious metal based solder, and another noble metal could be substituted for gold in the electroplated layer (30) or (230).

Claims: A ceramic sealing cover for a semiconductor package in which a flat ceramic sealing member has one side that faces the package and at the perimeter of the one side there is a plural layer sealing ring adhered onto the perimeter, said sealing ring comprising a base metallisation layer (24) and a solder layer (26) over said base metallisation layer (24) on the side away from said ceramic sealing member (22), characterized in that said base metallisation layer (24) is made of Mo-W. A ceramic sealing cover according to claim 1 further characterized in that atop said base metallisation layer there is a noble metal electroplated layer (30). A ceramic sealing cover according to claim 2 further characterized in that a layer (28) of nickel electroplate is interposed between said base metallisation layer (24) and said noble metal layer (30). A ceramic sealing cover for a semiconductor package in which a flat ceramic sealing member has one side facing said package and at the perimeter of said one side there is a plural layer sealing ring, comprising a metallisation layer (224) deposited on said ceramic sealing member (222) and a solder layer (226) over said metallisation layer (224) on the side away from said ceramic sealing member (222), characterized in that said metallisation layer (224) is formed of a titanium alloy at least five micrometers thick. A ceramic sealing cover according to claim 4 further characterized in that atop said titanium alloy layer (224) there is an electroplated noble metal layer (230). A ceramic sealing cover according to claim 4 further characterized in that atop said titanium alloy layer (224) there is an electroplated nickel layer (228) followed by an eletroplated gold layer (230), with said solder layer (226) being affixed onto said gold layer (230).

Inventors: FALANGA, RICHARD J.
Applicants: INDIUM CORPORATION OF AMERICA
Application year: 1987
Main classification: H01L23
IPC codes: H01L23, B65D85