REAL LOAD UNBALANCE PROTECTION CIRCUIT AND METHOD

Abstract: A method for sensing real load unbalance in an electrical power system having at least two clock based power sources (10, 12) which are connected for parallel operation combines a real load difference current signal, proportional to the difference in real load currents in corresponding phases of the power sources, with a phase angle signal which is, proportional to the phase difference between an external clock signal and an internal clock signal of one of the power sources, to produce an error signal. When this error signal exceeds a predetermined threshold level, a trip signal is produced to indicate that an excessive real load unbalance situation exists.

Description: This invention relates to DC link variable speed constant frequency (VSCF) power systems having two parallel connected channels, and more particularly, to a method and circuit for protecting such systems by sensing unbalanced real current flow and producing a selective trip signal when the unbalanced real current flow reaches a predetermined level. AC electric power systems are usually connected in parallel to increase total system rating or, in certain cases such as airborne power systems, to increase reliability. In order to further improve reliability and to maximize efficiency, it is generally desired that the total system load be divided equally among the paralleled generators. Parallel connected DC link variable speed constant frequency power sources constitute a clock based system in which a single digital clock signal is delivered to all channels whether or not they are connected to the parallel load bus. The clock signal is generally a 400 hertz squarewave. The angle between each channel Thevenin voltage and the clock signal represents an angle error. The angle error closes the feedback loop to control the channel's Thevenin angle. US Patent Application Serial No 06/938,661, corresponding to European Patent Application No 87310545.6, published as EP-A-0273598, discloses a control system for such a power system. That application discloses a system having a real load division loop which adds an input to a phase-locked loop clock circuit in a manner such that the phase angle is controlled to offset any real load unbalance. Although the frequency reference signal is used as the vehicle for obtaining the desired phase angle change, the control system does not alter the steady state frequency of the output. Unlike parallel connected constant speed generators, the VSCF system does not have a frequency droop with real load errors. It has an angle droop with real load errors. VSCF systems do not exhibit frequency droop with any load conditions because the system frequency is determined totally independent of the generator speed and torque. Thus, it is impossible to bias the VSCF over frequency/under frequency (OF/UF) protection circuits with the real load division error to get selecting tripping of the parallel channels as disclosed in GB-A-1216928. An object of this invention is to provide a protection circuit and method which can selectively trip parallel connected DC link VSCF channels in the event of excessive real current unbalance. According to the invention this object is achieved by the features specified in claims 1 and 4 respectively. The trip signal can be used in well known existing circuitry to either provide isolated operation of the channels or to disconnect a particular channel. The invention will become more readily apparent from the following description of the preferred embodiment thereof, shown by way of example only, in the accompanying drawings wherein: Figured 1A and 1B are block diagrams of a parallel connected DC link VSCF power system which includes the protection circuit of the present invention; Figures 2A, 2B, 2C and 2D show a series of voltage vectors which are used to describe the operation of the system of Figures 1A and 1B; Fig. 3 is a schematic diagram of a portion of the unbalanced current sensing circuitry used in the system of Figures 1A and 1B; and Fig. 4 is a schematic diagram of the window detector circuitry of the system of Fig. 1. Referring to the drawings, Figures 1A and 1B are block diagrams of portions of a parallel connected DC link variable speed constant frequency power system having two channels 10 and 12 each including a DC link variable speed constant frequency power source 14 and 16 having output phases 18 and 20. These phases are corresponding phases of the multiple phase output of each channel. Since the control and protection circuits for each channel are identical, similar numbers will be used to identify similar components in each of the channels. A master clock signal is supplied on terminal 22 and transmitted to a phase detector 24 in each channel. That phase detector serves as the input to a phase-locked loop which includes integrator 26 and voltage controlled oscillator 28. The output of the voltage controlled oscillator is fed to a microprocessor 30 which is located in the waveform pattern generator of the existing DC link system and produces a plurality of output pulses on lines 32 which serve to control a plurality of switching transistors in an output bridge circuit as is commonly found in existing DC link VSCF systems. That microprocessor also produces an internal clock signal on line 34 which is used to achieve phase-lock with the master clock signal. Control current transformers 36 are inductively coupled to corresponding output phases of the power sources and are electrically connected in a series loop with each other to produce a signal on line 38 which is representative of the difference or unbalanced current flowing in the output phases. A real load demodulator 40 is used to produce a voltage signal V rc on line 42 which is proportional to the difference in real load currents flowing in corresponding phases of the power sources. This signal is combined with a phase angle signal V pd in summation point 44 to minimize real current unbalances by controlling the phase relation of the Thevenin voltage of each channel with respect to the parallel bus voltage as defined by the master clock. It should be understood that although only a single output phase is illustrated for each channel in Fig. 1, the total unbalanced real load current would be sensed by sensing at least N-1 of N output phases as illustrated in the above noted US Patent Application Serial No 06/938,661 (EP-A-0273598). Therefore, V rc represents the total unbalanced real load current. Protection circuitry constructed in accordance with the present invention uses protection current transformers 46 which are inductively coupled to corresponding output phases of the DC link VSCF power sources and are electrically connected in series with each other to produce a current unbalance signal on lines 48. Here again, total unbalanced real current would be sensed. Real load demodulators 50 demodulate the signal on line 48 to produce a real load current difference signal V rp on line 52. Phase detectors 54 receive both the master clock signal and the appropriate internal clock signal to produce a phase angle signal V pd which is proportional to the phase difference between the external clock signal and the internal clock signal of each power source. Each real load current difference signal V rp is combined with a phase angle signal V pd in summation point 56 to produce an error signal on line 58. Window detecting circuitry 60 determines when the error signal exceeds a preselected threshold level and then produces a trip signal on terminal 62. This trip signal can be used by well known conventional circuitry to open the contacts of a bus tie breaker 64 and thereby provide for isolated operation of the system channels. Alternatively, other switching arrangements can be used to disconnect a particular channel from the loads. U.S. Patent No. 4,510,399, issued April 9, 1985 to Baker, discloses a demodulator circuit which is suitable for use in blocks 40 and 50 in the circuit of Figures 1A and 1B and is hereby incorporated by reference. The voltage vectors of Figures 2A, 2B, 2C and 2D can now be used to describe the operation of the control circuit of the power system of Figures 1A and 1B. Consider two normally operating channels having no error associated with their real load control circuits. The preparallel condition with no phase error between the Thevenin and master voltage is shown by the vectors of Fig. 2A. In this case, the Thevenin and master voltages, V th and V m , are in phase and the phase angle signals V pd1 and V pd2 are equal to zero. Now assume that an unbalance in the system exists, such as different feeder impedances or different tolerances in the control circuits of the two channels. This will result in an unbalanced load division when the two channels are initially connected in parallel. The resulting real load unbalance signal will retard the Thevenin voltage of the channel supplying more real power and advance the Thevenin voltage of the channel supplying less real power. The system will stabilize itself with some real load unbalance proportional to the gain of the real load control loop and the amount of unbalance due to feeders, etc. This situation is illustrated by the vectors of Fig. 2B. In this case, channel 1 is shown as supplying slightly more than its fair share of real load. Since there was no initial (preparallel) error in the real load control loop, each real load control loop difference current signal V rc is equal to each real load difference current protection loop signal V rp . That is: V rc1 = V pd1 (1) V rc2 = V pd2 (2) Then the protection circuit window detector does not detect any error in the real control loop at line 58, thereby indicating that the real load division loop is functioning properly. Next consider a problem in the real loop of one of the channels, say channel number 1. The preparallel condition is shown by the vectors of Fig. 2C. The problem in the real load control loop of channel number 1 as represented by phase angle signal is in a direction which causes the Thevenin voltage V th to lead the master voltage V m . Initially a large unbalanced real load division will result when the channels are paralleled. This unbalanced real load will be sensed by the control circuit which will attempt to retard the Thevenin voltage of channel 1 and advance the Thevenin voltage of channel 2. The system will finally stabilize itself with some real load unbalance proportional to the gain of the real load control loop and the unbalance due to the problem. This is illustrated by the vectors of Fig. 2D. Under these conditions: where is the preparallel error. The relative magnitudes of V rc1 and V pd1 are related to the gains of the real load control loop and the phase-locked loop. From the vectors of Fig. 2D, it is apparent that: V rc1 = V rp1 (4) V rc2 = V rp2 (5) V pd1 - V rc1 = 0 (6) V pd2 - V rc2 = 0 (7) Note that for channel number 1, V pd and V rp are in the same direction. The protection circuit window detector will detect the problem in channel 1 on line 58 and will isolate it from the parallel bus if the error detected exceeds the allowable level. Note that only the failed channel is detected and isolated from the parallel bus. Fig. 3 is a schematic diagram of a portion of the difference current sensing circuitry used in the system of Fig. 1. Current transformers 46 are shown to be connected in series with each other, with each current transformer being connected in parallel with a burden resistor 66. Isolation transformers 68 are used to supply the difference current signals to the protection circuitry 70 which includes demodulator 50, phase detector 54, summation point 56 and window detector 60 as illustrated in Fig. 1. Lines 72, 74 and 76 are shown to be connectable to additional power system channels if present. This sensing circuitry is used on at least N-1 phases of an N phase system so that total real error current will be sensed. Fig. 4 is a schematic diagram which provides a detailed schematic of the window detector 60 in Fig. 1. To provide a more complete description of this embodiment, Table 1 includes a list of components used to construct the circuit of Fig. 4. Figure 4 Components U1 HA5160 U2, U3 3140 R1 45K R2 3.16K R3 4.76K R4 255K R5 3.01K R6, R8 1.82K R7 4.67K R9 10M R10 200K R11 4.99K R12 10K C1 2µf C2 30 pf CR1, CR2, CR3 1N647 Although the present invention has been described in terms of what is at present believed to be its preferred embodiment, it will be apparent to those skilled in the art that various changes may be made without departing from the scope of the invention as defined in the appended claims.

Claims: A real load unbalance protection circuit for a DC link variable speed constant frequency (VSCF) power system in which two clock based power sources (10,12) are connected for parallel operation, each of said power sources producing an output load current having a frequency determined by an internal clock signal of the respective power source, which internal clock signal is phase locked to an external master clock signal supplied to both power sources, said circuit comprising, for each of the power sources (10,12): means (46,50) for producing a real load difference current signal (Vrp1, Vrp2) proportional to the difference in the real load output currents of the power sources; means (54) for producing a phase angle signal (Vpd1, Vpd2) proportional to the phase difference between the external clock signal and the internal clock signal of the respective power source; means (56) for combining said real load difference current signal and said phase angle signal to produce an error signal; and means (60) for producing a trip signal when said error signal exceeds a preselected threshold level. A circuit as recited in claim 1, wherein said means for producing a real load difference current signal comprises means (46) for monitoring the difference in the output load currents flowing in electrically connected output phases of each of said power sources, to produce a difference current signal; and means (50) for demodulating said difference current signal to produce said real load difference current signal. A circuit as recited in claim 2, wherein said means for monitoring the difference current comprises a plurality of current transformers (46), each of said transformers being inductively coupled to an output phase of one of said power sources; said transformers which are coupled to connected ones of said output phases (18,20) being electrically connected in series with each other; and each of said transformers being electrically connected in parallel with a resistor (66). A real load unbalance protection method for a DC link variable speed constant frequency (VSCF) power system in which two clock based power sources (10,12) are connected for parallel operation, each of said power sources producing an output load current having a frequency determined by an internal clock signal of the respective power source, which internal clock signal is phase locked to an external master clock signal supplied to both power sources, said method comprising, for each of the power sources (10,12), the steps of: producing a real load difference current signal (Vrp1, Vrp2) proportional to the difference in the real load output currents of the power sources; producing a phase angle signal (Vpd1, Vpd2) proportional to the phase difference between the external clock signal and the internal clock signal of the respective power source; combining said real load difference current signal and said phase angle signal to produce an error signal; and producing a trip signal when said error signal exceeds a preselected threshold level. The method of claim 4, wherein the step of producing a real load difference current signal comprises the steps of: monitoring the difference in the output load currents flowing in electrically connected output phases of each of said power sources, to produce a difference current signal; and demodulating said difference current signal to produce said real load difference current signal.

Inventors: BAKER, DONAL  EUGENE, BEG, MIRZA AKMAL, BAKER, DONAL EUGENE
Applicants: SUNDSTRAND CORPORATION
Application year: 1987
Main classification: H02H7
IPC codes: H02J3, H02H7