Photoelectric converting apparatus

Abstract: A photoelectric converting cell has a control electrode region of a semiconductor transistor (S₁). The carriers generated in the control electrode region by the light excitation are accumulated, and the accumulation voltage generated by this accumulation is read out from one of the main electrode regions of the semiconductor transistor. The control electrode region is connected to an excess carrier eliminating circuit (D₁, Lrh, Ve) to perform the switching operation in dependence on the potential difference across the control electrode region.

Description: FIELD OF THE INVENTION The present invention relates to a photoelectric converting apparatus of the system in which the carriers generated in the control electrode region of a transistor by the light excitation are accumulated and, more particularly, to a photoelectric converting apparatus to prevent the outflow of the excess carriers. Related Background Art Fig. 1A shows a schematic cross sectional view of a photoelectric converting apparatus and Fig. 1B is a diagram showing an equivalent circuit of one of the photoelectric converting cells in this apparatus. In Fig. 1A, an n - epitaxial layer 4 is formed on an n silicon substrate 1. Photoelectric converting cells which are electrically insulated from one another by a device separating region 6 are arranged in the layer 4. First, a p base region 9 of a bipolar transistor is formed on the n - epitaxial layer 4. An n + emitter region 15 is formed in the p base region 9. Further, a capacitor electrode 14 to control the potential of the p base region 9 and an emitter electrode 19 connected to the n + emitter region 15 are formed through an oxide film 12, respectively. An electrode 17 connected to the capacitor electrode 14 is formed. An n + region 2 for ohmic contact is formed on the back side of the substrate 1. A collector electrode 21 of the bipolar transistor is formed under the n + region 2. In this manner, a photoelectric converting cell is constructed. The fundamental operation of the photoelectric converting cell will now be described. First, the p base region 9 which is biased to the negative potential is set into the floating state. The holes in the electron/hole pairs generated by the light excitation are accumulated into the p base region 9 (accumulation operation). Subsequently, the positive voltage is applied to the capacitor electrode 14, thereby forwardly biasing the circuit between the emitter and the base. The accumulated voltages generated by the holes accumulated are read out to the emitter side in the floating state (readout operation). Then, the emitter side is grounded and pulses of the positive voltage are applied to the capacitor electrode 14, thereby extinguishing the holes accumulated in the p base region 9. Thus, when the positive voltage pulse for refreshing falls, the p base region 9 is reset to the initial state (refresh operation). In such a photoelectric converting apparatus, after the accumulated charges were amplified by the amplifying function of each cell, they are read out, so that the high output, high sensitivity, and low noise can be accomplished. On the other hand, since the structure is simple, this apparatus is also advantageous to realize the high resolution in future. However, when a long sensor is formed using the photoelectric converting cells, in the case of the constitution of the conventional photoelectric converting apparatus, there are problems such that the refresh operation conditions differ every cell, and this results in causes of the occurrence of the fixed pattern noise, variation in sensitivity, and the like. Additionally, when a photoelectric converting apparatus is constructed by arranging a plurality of photoelectric converting cells mentioned above, there is a problem such that in the case where the light of a saturation light amount or more was irradiated onto a certain pixel, smear occurs. Namely, when strong light enters, a large quantity of holes are accumulated in the p base region 9, so that the base potential increases. When the base potential increases to a value in excess of the collector potential, a depletion layer 22 between the base and the collector is extinguished and the accumulated carriers in the base flow into the adjacent cells (as indicated by arrows 23). Thus, the p base region 9 of the adjacent cells enters the accumulation state in which the inflow holes were added. When an image of the readout signal is reproduced, the smear occurs. EP-A-0132076 discloses a photoelectric converting cell substantially as shown in Figures 1A and 1B of the present application. In EP-A-0132076 there is described, with reference to Figure 21 thereof, an arrangement in which refreshing is carried out by applying a voltage to the base region via an MOS transistor provided in the cell for this purpose. A modification of this arrangement is described with reference to Figure 22 of EP-A-0132076 in which the control electrodes of the MOS transistors of the cells in one row of an array are connected to the same control line as the capacitor electrode for the cells in an adjacent row of the array, and the system is operated so that the MOS transistors in one row are turned on, to apply a predetermined voltage to the base regions to refresh them, while readout from the cells of the adjacent row is carried out. SUMMARY OF THE INVENTION According to the present invention there is provided a photoelectric converting apparatus as set out in claim 1 and a method of operating a photoelectric converting apparatus as set out in claim 11. The remaining claims set out optional features. In an embodiment of the apparatus of claim 1, since the control region of the later cell is clamped to a constant potential at the refresh operation timing of the preceding cell, the time intervals from the clamping operation until the refresh operation regarding all of the photoelectric converting cells are the same. Therefore, the refresh operation conditions are the same. The generation of the fixed pattern noise, variation in sensitivity, and the like are prevented. Preferably, an excess carrier eliminating means is provided for limiting the potential generated in the control region, so that smear can be prevented. Embodiments of the present invention, given by way of non-limiting example, will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic cross sectional view of a photoelectric converting cell disclosed in Japanese Laid-Open Patent Gazette Nos. JP-A-60-012759 to JP-A-60-012765; Fig. 1B is an equivalent circuit diagram of this cell; Fig. 2A is a schematic circuit diagram in the first embodiment of a photoelectric converting apparatus according to the invention; Fig. 2B is a schematic cross sectional view of a photoelectric converting apparatus having a transistor for refreshing; Fig. 2C is an equivalent circuit diagram of one photoelectric converting cell in the apparatus shown in Fig. 2B; Fig. 2D is a voltage waveform diagram for explaining the refresh operation; Fig. 3 is a timing chart for explaining the operation in the embodiment; Fig. 4A is a schematic cross sectional view of a photoelectric converting cell having an n channel transistor for refreshing; Fig. 4B is an equivalent circuit diagram of the cell in Fig. 4A; and Fig. 5 is a schematic circuit diagram in the second embodiment of the invention using the above photoelectric converting cell. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 2A is a schematic circuit diagram in the first embodiment of a photoelectric converting apparatus according to the invention. In the diagram, the photoelectric converting cells S l to S n shown in Fig. 2B are arranged in line. Fig. 2B is a schematic cross sectional view of the photoelectric converting apparatus in the first embodiment having a transistor for refreshing. Fig. 2C is an equivalent circuit diagram of one photoelectric converting cell in the apparatus shown in Fig. 2B. Fig. 2D is a voltage waveform diagram for explaining the refresh operation. In Figs. 2A and 2B, photoelectric converting cells are arranged on an n silicon substrate 401. Each cell is electrically isolated from the adjacent cells by a device separating region 402. Each cell has the following constitution. By doping p type impurities (e.g., boron or the like), a p base region 404 and a p region 405 are formed on an n - region 403 having a low impurity concentration which is formed by an epitaxial technique or the like. An n + emitter region 406 is formed in the p base region 404. The p base region 404 and p region 405 serve as a source and a drain of a p channel MOS transistor, which will be explained hereinlater. An oxide film 407 is formed over the n - region 403 in which the foregoing regions are formed. A gate electrode 408 of the MOS transistor and a capacitor electrode 409 are formed on the oxide film 407. The capacitor electrode 409 faces the p base region 404 through the oxide film 407 and constitutes a capacitor to control the base potential. An emitter electrode 410 connected to the n + emitter region 406 is formed. An electrode 411 connected to the p region 405 is formed. A collector electrode 412 is formed on the back surface of the substrate 401 through an ohmic contact layer. The operation of the foregoing photoelectric converting cell will now be explained. The light enters from the side of the p base region 404. The carriers (in this case, the holes) corresponding to the light quantity are accumulated into the p base region 404. The base potential changes by the accumulated carriers (accumulation operation). Next, a positive voltage pulse for readout is applied to the capacitor electrode 409, thereby increasing the base potential. The potential change by the accumulation of the carriers is read out of the emitter electrode 410. Thus, the electric signal corresponding to the incident light quantity can be obtained (readout operation). The refresh operation to eliminate the holes accumulated in the p base region 404 will now be described. As shown in Fig. 2D, since the MOS transistor is of the p channel transistor type, it is turned on only when a negative voltage in excess of the threshold value is applied to the gate electrode 408. To perform the refresh operation, the emitter electrode 410 is grounded and a constant voltage is applied to the electrode 411. Then, the negative voltage is applied to the gate electrode 408 to turn on the p channel MOS transistor. Thus, the potential of the p base region 404 is set to a constant value irrespective of the accumulated potential level. Subsequently, by applying a voltage pulse for refreshing to the capacitor electrode 409, the p base region 404 is forwardly biased to the n + emitter region 406. The accumulated holes are eliminated through the grounded emitter electrode 410. When the refresh pulse falls, the p base region 404 is reset to the initial state of the negative potential (refresh operation). After the potential of the p base region 404 was set to the constant potential by the MOS transistor, the residual charges are erased by applying the refresh pulse as explained above. Therefore, the new accumulation operation can be executed irrespective of the preceding accumulated potential. The linearity of the photoelectric converting characteristic can be improved. The problem of the occurrence of an after image can be solved. Further, since the residual charges can be promptly extinguished, the high speed operation can be performed. The accumulation, readout, and refresh operations are repeated in a manner similar to the above. Returning to Fig. 2A, the constant positive voltage V cc is applied to the collector electrode 412 of each photoelectric converting cell. The capacitor electrodes 409 are connected to the parallel output terminals of the scan circuit 102, respectively. The photoelectric converting cells perform the readout operation or refresh operation by the signals  h1 to  hn from the parallel output terminals, respectively. A constant voltage V bg is applied to the electrode 411 of the refreshing transistor of each cell. The output pulses  h0 to  hn-1 of the scan circuit 102 are applied to the gate electrodes 408 through transistors Q f1 to Q fn and inverters IV 1 to IV n , respectively. A pulse  f is commonly supplied to the gate electrodes of the transistors Q f1 to Q fn . Therefore, by turning on the transistors Q f1 to Q fn by the pulse  f , the base clamping operation of each cell can be sequentially executed at the refresh timing of the one-preceding cell in response to the pulses  h0 to  hn-1 from the scan circuit 102. The foregoing refresh operation can be sequentially executed by the subsequent pulses  h1 to  hn . On the other hand, the emitter electrodes 410 are commonly connected to the output line 103 through transistors Q 1 to Q n . The gate electrodes of the transistors Q 1 to Q n are connected to the output terminals of the scan circuit 102 in a manner similar to the capacitor electrodes 409. Further, the emitter electrodes 410 are connected to a constant voltage line L rh through transistors Q e1 to Q en , respectively. A constant voltage V e lower than the voltage V cc is applied to the line L rh . A pulse  hrs is applied to the gate electrodes of the transistors Q e1 to Q en . These transistors execute the ON/OFF operations at the timing of the pulse  hrs . The output line 103 is grounded through a transistor 104 and connected to an amplifier 105. The readout signal is serially output to the outside from the output terminal 106 of the amplifier 105. The signal  hrs is applied to the gate electrode of the transistor 104, thereby refreshing the output line 103. The operation in this embodiment having such a constitution will now be explained with reference to Fig. 3. Fig. 3 is a timing chart for explaining the operation in this embodiment. First, the transistor 104 is turned on by the signal  hrs and the output line 103 is grounded. Further, the transistors Q f1 to Q fn are turned on by the pulse  f . The pulses  h0 to  hn are sequentially output from the output terminals of the scan circuit. The pulse  h0 at the high level is set to the low level by the inverter IV 1 . This low level pulse is input to the gate electrode 408 of the refreshing transistor of the cell S 1 through the transistor Q f1 . Thus, the transistor is turned on. The base potential of the cell S 1 is clamped to the constant voltage V bg irrespective of the accumulated voltage level. When the high level pulse  h1 is subsequently output, the transistor Q 1 is turned on and the emitter electrode 410 is grounded through the output line 103 and transistor 104. Moreover, when the pulse  h1 is input to the capacitor electrode 409 of the cell S 1 , the foregoing refresh operation is executed. At the same time, the high level pulse  h1 is set to the low level by the inverter IV 2 . This low level pulse is input to the gate electrode 408 of the refreshing transistor of the cell S 2 through the transistor Q f2 , so that this transistor is turned on. When the pulse  h1 falls, the cell S 1 finishes the refresh operation and starts the accumulation operation. The base potential of the cell S 2 is clamped to the constant potential V bg irrespective of the accumulated voltage level. In a manner similar to the above, the base clamping operation is executed at the pulse timing of the preceding cell by the pulses  h2 to  hn and the refresh operation is executed at the pulse timing of the relevant cell. Upon completion of the refresh operation, the accumulation operation is sequentially started. In this manner, since the base clamping operation and refresh operation are sequentially executed at the timings of the pulses  h0 to  hn' the time intervals of the base clamping operation and refresh operation in each cell are equalized. The occurrence of the fixed pattern noise and the like as in the conventional apparatus can be prevented. When the pulse  hn falls and the refresh operation of the cell S n is finished, the pulse  f also falls to thereby turn off the transistors Q f1 to Q fn . Therefore, after that, the refreshing transistors of the cells are held in the off state irrespective of the pulses  h0 to  hn . The carriers of the amount corresponding to the illuminance of the incident light are accumulated in the p base region 404 of the cell which has started the accumulation operation. At this time, if strong light enters, excess carriers (in this case, the holes) are accumulated and the base potential rises. When the base potential rises to a value which is higher than the constant voltage V e by about 1.4 V, the PN junction with the line L rh of the constant voltage V e is set into the forward bias state. The excess carriers flow out to the line L rh through the PN junction between the base and the emitter. As explained above, even if strong light entered, the excess carriers in the p base region 404 are eliminated to the line L rh and do not flow out to the adjacent cells, so that the occurrence of the smear can be prevented. After the accumulation operation was executed for a constant period of time, the scan circuit 102 sequentially outputs the pulses  h0 to  hn . However, since the transistors Q f1 to Q fn are in the off state, the pulse  h0 is meaningless. Before the next pulse  h1 is output, the pulse  hrs is set to the low level to turn off the transistor 104, thereby setting the output line 103 into the floating state. Subsequently, by outputting the pulse  h1 from the scan circuit 102, the readout pulse is applied to the capacitor electrode 409 of the cell S 1 and the transistor Q 1 is turned on. The signal of the cell S 1 is read out to the output line 103 through the transistor Q 1 and is output as an output signal V 1 from the output terminal 106 through the amplifier 105. Therefore, the accumulation period of time of the cell S 1 is equal to the time interval from the time point when the pulse  h1 falls upon refresh operation until the time point when the pulse  h1 rises upon readout operation. When the output signal V 1 is output, the transistor 104 is turned on by the pulse  hrs and the residual carriers in the output line 103 are eliminated. In a manner similar to the above, the readout pulses are applied to the capacitor electrodes 409 of the cells S 2 to S n from the scan circuit 102 at the timings of the pulses  h2 to  hn . The output signals V 2 , V 3 , ... are output from the output terminal 106. At the same time, the transistor 104 is turned on at the timing of the pulse  hrs and the output line 103 is refreshed. The output timings of the pulses  h0 to  hn of the scan circuit 102 upon refresh operation and readout operation are uniform. Thus, the accumulation period of time of each cell is the same as that of the cell S 1 as will be obvious from a timing chart of Fig. 3. In this manner, since the signals of the photoelectric converting cells S 1 to S n are directly read out to the output line 103 through the transistors Q 1 to Q n , the outputs of the cells appear on the output line 103 without being attenuated. Therefore, the high output signal V out can be derived. On the other hand, as shown in the diagram, since the voltage which is applied to the capacitor electrode 409 and the gate voltages of the transistors Q 1 to Q n are supplied in response to the output pulses  h1 to  hn from the scan circuit, the circuit constitution is simple. In the above embodiment, the case where the refreshing transistor is the p channel MOS transistor has been shown. However, the invention is not limited to this case. An n channel transistor may be also formed as will be explained hereinafter. In this case, the inverters IV 1 to IV n in the above embodiment are unnecessary. Fig. 4A is a schematic cross sectional view of a photoelectric converting cell having an n channel refreshing transistor. Fig. 4B is an equivalent circuit diagram of this cell. The parts and components having the same functions as those shown in Fig. 2B are designated by the same reference numerals and their descriptions are omitted. In the diagrams, a bipolar transistor for performing the photoelectric conversion which has already been explained is formed in the n - region 403. Further, a p well 413 is formed through the device separating region 402. n + regions 414 and 415 serving as source and drain regions are formed in the p well 413. A gate electrode 418 is formed over the surface of the p well 413 through the oxide film 407. An n channel MOS transistor for refreshing is constructed. A p + region 416 is formed in the p base region 404 and electrically connected to the n + region 415 of the refreshing transistor by a wiring 417. An electrode 419 connected to the n + region 414 is also formed. Fig. 5 is a schematic circuit diagram in the second embodiment of the invention using the foregoing photoelectric converting cell. This embodiment is constituted in a manner similar to the first embodiment except that an n channel MOS transistor is used as a refreshing transistor of each cell. The second embodiment operates in a manner similar to the above by the various kinds of pulses shown in the timing chart of Fig. 3. As described in detail above, in the photoelectric converting apparatus embodying the invention, at the timing for the refresh operation of the preceding cell, the control electrode region of the later cell is clamped to the constant potential. Therefore, the time intervals from the clamping operation until the refresh operation regarding all of the photoelectric converting cells are the same. Thus, the refresh operation conditions are equalized. The occurrence of the fixed pattern noise, the variation in sensitivity, and the like are prevented.

Claims: A photoelectric converting apparatus comprising: a plurality of photoelectric converting cells (S) each including a semiconductor transistor; switching means for clamping the potential of a control region of said semiconductor transistor to a constant value (Vbg); and control means (102) for performing (a) an accumulation operation to accumulate carriers generated in said control region by a light excitation by controlling the potential of said control region, (b) a readout operation to read out an accumulated voltage generated by said carrier accumulation, (c) a clamping operation to clamp the potential of said control region to a constant potential (Vbg) by said switching means, and (d) a refresh operation for applying a signal to said control region to extinguish the carriers in said control region after completion of said clamping operation, characterised in that said control means (102) controls the switching means of a predetermined one of said plurality of photoelectric converting cells, thereby clamping the potential of said control region of said predetermined cell to said constant value, synchronously with a refresh operation timing of another cell different from said predetermined cell. An apparatus according to claim 1 wherein said semiconductor transistor is a bipolar transistor. An apparatus according to claim 1 wherein said switching means includes an MOS transistor. An apparatus according to claim 1 wherein said control means extinguishes the carriers by applying predetermined pulses to said control region. An apparatus according to claim 1 wherein said control means executes the readout operation by sequentially reading out the accumulated voltages from said plurality of photoelectric converting cells in accordance with a predetermined order. An apparatus according to claim 5 wherein said control means executes the refresh operation by sequentially refreshing said plurality of photoelectric converting cells in accordance with said predetermined order. An apparatus according to claim 1 wherein said semiconductor transistor has a first main electrode region connected to a predetermined potential and a second main electrode region connected to a load. An apparatus according to claim 1 further having limiter means (Qe) operable during said accumulation operation to limit the potential generated in the control region with reference to a reference potential. An apparatus according to claim 8 wherein said limiter means (Qe) includes a transistor. An apparatus according to claim 9 further having means for selectively making said transistor operative so as to selectively make said limiter means (Qe) operative. A method of operating a photoelectric converting apparatus in which the photoelectric converting apparatus comprises: a plurality of photoelectric converting cells (S) each including a semiconductor transistor; switching means for clamping the potential of a control region of said semiconductor transistor to a constant value (Vbg); and control means (102) for performing (a) an accumulation operation to accumulate carriers generated in said control region by a light excitation by controlling the potential of said control region, (b) a readout operation to read out an accumulated voltage generated by said carrier accumulation, (c) a clamping operation to clamp the potential of said control region to a constant potential (Vbg) by said switching means, and (d) a refresh operation for applying a signal to said control region to extinguish the carriers in said control region after completion of said clamping operation, characterised in that the method comprises controlling the switching means of a predetermined one of said plurality of photoelectric converting cells, thereby clamping the potential of said control region of said predetermined cell to said constant value, synchronously with a refresh operation timing of another cell different from said predetermined cell.

Inventors: NAKAMURA YOSHIO, SUGAWA SHIGETOSHI, NAKAMURA, YOSHIO, SUGAWA, SHIGETOSHI, NAKAMURA, YOSHIO, C/O CANON KABUSHIKI KAISHA, SUGAWA, SHIGETOSHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1987
Main classification: H04N3
IPC codes: H01L27, H04N3