VERTICAL DEFLECTION CIRCUIT

Abstract: A vertical deflection amplifier (20) of a video display ap­ paratus includes first (Q1) and second (Q2) transistor amplifier output stages arranged in a totem-pole, push-pull configura­ tion. A vertical deflection winding (L v ) is coupled to the output stages at a deflection amplifier output terminal (22). An S-­ capacitor (C1) is coupled to the deflection winding (L v ) at a second terminal (21) remote from the output terminal (22). A source (23) of deflection rate signals is coupled to the deflec­ tion amplifier (20) for generating a deflection current (i v ) in the deflection winding (L v ). A base current generating circuit (40) is coupled to one (Q1) of the transistor amplifier output stages for providing base current (i1) thereto. The S-capacitor voltage (V1) is applied to the base current generating circuit (40) for enabling conduction of base current (i1) in the one amplifier output stage (Q1). When the video display apparatus is first turned on, the initially discharged S-capacitor (C1) is slowly charged from a DC voltage supply (+30V) to delay genera­ tion of vertical deflection past completion of picture tube de­ gaussing.

Description: This invention relates to deflection amplifier circuitry. In a typical linearly operated vertical deflection circuit for example as described in US-A-4238713, first and second output transistors are coupled together in a push-pull configuration at a deflection amplifier output terminal. A vertical deflection winding, in series with an S-shaping capacitor, is coupled to the output terminal. A vertical rate, sawtooth input signal is coupled to the deflection amplifier to generate a sawtooth vertical deflection current in the deflection winding. During the first half of vertical trace, the top output transistor is conducting to generate the first half of the vertical deflection current and to charge the S-shaping capacitor from a DC voltage source. During the second half of vertical trace, the bottom output transistor is conducting to apply the S-capacitor voltage to the deflection winding for generating the second half of the vertical deflection current. The S-shaping capacitor is discharged by the vertical deflection current through the bottom transistor. Except for a small overlap interval at the center of trace, the top output transistor is nonconductive when the bottom transistor is conductive. DC negative feedback of the amplifier output voltage or of the S-capacitor voltage establishes correct DC biasing of the deflection amplifier. Thus, for example, should the S-capacitor voltage tend to decrease, the DC feedback increases conduction of the top output transistor to increase the charging current to the S-capacitor from the DC voltage source, thereby maintaining the proper DC operating point. A fault operating condition may arise if the S-capacitor becomes short-circuited, decreasing the DC voltage at the amplifier output terminal to a very low value. The DC negative feedback loop tries to restore the DC output voltage by turning on the top output transistor to full or near full conduction in an attempt to recharge the S-capacitor from the DC voltage source via the vertical deflection winding. Such fault mode operation may be undesirable in that excessive power dissipation may result in the top output device and in any current limiting resistor in series with the DC voltage source. Furthermore, the large unidirectional current flowing in the deflection winding during fault mode operation, may deflect the electron beams to such an extreme angle that they strike the picture tube neck, causing neck heating and possible tube breakage. According to the present invention, there is provided a deflection circuit, comprising: a deflection amplifier including first and second transistor amplifier output stages; a deflection winding coupled to said first and second transistor amplifier output stages at a deflection amplifier output terminal; an S-shaping capacitance coupled to said deflection winding at a second terminal remote from said amplifier output terminal for developing an S-capacitance voltage; a source of a deflection rate signal coupled to said deflection amplifier for generating a deflection current in said deflection winding; means coupled to said deflection amplifier and responsive to a voltage representative of said S-capacitance voltage for forming a DC negative feedback loop to stabilize the DC voltage at said output terminal; and characterized by a base current generating circuit coupled to one of said transistor amplifier output stages for providing base current thereto, said base current generating circuit being coupled to said second terminal and having said S-capacitance voltage applied thereto independently of said DC negative feedback loop for enabling the conduction of said base current. In an embodiment of the invention, a main charging path of the S-capacitance is provided via the top output stage of a deflection amplifier arranged in a push-pull configuration. A second, slower charging path for the S-capacitance is also provided which bypasses the top output stage. Conduction.of base current to the top output stage is enabled only when the S-capacitance voltage is greater than a predetermined magnitude. During start-up, when the S-capacitance is initially discharged, the main charging path is disabled. The second charging path charges the S-capacitor to the voltage level needed to enable operation of the top output device. By proper selection of the charging rate in the second charging path, a start-up delay is provided to operation of the vertical deflection circuit. The start-up delay enables picture tube degaussing to be completed before vertical deflection current is generated. This prevents the vertical deflection magnetic field from undesirably affecting the degaussing process. In the Drawing: FIGURES 1 and 2 illustrate two different inventive embodiments of a vertical deflection circuit; and FIGURE 3 illustrates a video display apparatus, embodying the invention, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing. In vertical deflection circuit 20 of FIGURE 1, a vertical deflection amplifier 30 comprises output transistor stages Q1 and Q2 coupled together in a push-pull configuration at an amplifier output terminal 22. A vertical deflection winding L V is coupled to terminal 22. An S-capacitor C1 is coupled to deflection winding L V at a second terminal 21 remote from output terminal 22. A current sampling resistor R12 is coupled between the lower terminal of capacitor C1 and ground. The collector of bottom output transistor Q2 is coupled to the base of top output transistor Q1 via a resistor R4 and a diode D4 to form a totem-pole configuration, wherein base drive for top transistor Q1 is shunted through bottom transistor Q2. A resistor R8 is coupled between output terminal 22 and the collector of transistor Q2 to reduce crossover distortion. A diode D3 parallels resistor R8 and becomes conductive during the second half of vertical trace to shunt current away from resistor R8 at large deflection current amplitudes during the second half of trace. This reduces overall power dissipation during the second half of vertical trace and enables a lower DC operating point to be selected for output terminal 22. A +24V supply source is coupled to the collector of transistor Q1 via a small current limiting resistor R6 and a diode D5. The control circuitry for deflection amplifier 30 includes a vertical sawtooth generator 23 that develops a vertical rate sawtooth voltage V3 that is AC coupled to the noninverting input terminal of a driver amplifier U1 via a capacitor C4 and a resistor R13. A reference voltage V REF is coupled to the inverting input terminal. The output of driver U1 is coupled to the base of bottom transistor Q2 via resistor R9 of biasing resistors R9 and R14. A base current generating circuit 40, embodying an aspect of the invention, generates a base current i1 for top output transistor Q1. Base current generating circuit 40 includes a bootstrap capacitor C2 having a lower terminal coupled to amplifier output terminal 22 at the emitter of transistor Q1 and an upper terminal coupled to the junction of a diode D1 and a resistor R3. Resistor R3 is coupled to the base of transistor Q1. Bootstrap capacitor C2 is charged by a current i c ₂ flowing from terminal 21 via a relatively small valued resistor R2 and diode D1. The value of current i c2 is established in accordance with the S-capacitor voltage V1 established at terminal 21. During normal steady-state deflection circuit operation, voltage V1 is a vertical rate parabola voltage, skewed downwardly by the superimposed sawtooth voltage V s developed across sampling resistor R12. At the beginning portion of the vertical trace interval T t , output transistor Q1 is conducting a positive vertical deflection current i V to charge S-capacitor C1 from the +24V supply via resistor R6 and diode D5. Bootstrap capacitor C2 provides the forward base current for transistor Q1 during the early portions of vertical trace. Near the beginning of vertical trace, deflection amplifier output voltage V2 developed at terminal 22 is sufficiently greater than S-capacitance voltage V1 to reverse bias diode D1 and prevent the recharging of bootstrap capacitor C2. The decreasing, positive sawtooth portion of vertical deflection current i V during the first half of vertical trace is produced as a result of the decreasing conduction of top output transistor Q1. In the totem-pole deflection amplifier arrangement, the upwardly ramping sawtooth input voltage V3 is amplified by driver U1 to increase the conduction of bottom output transistor Q2, thereby increasing the amount of current shunted away from the base of transistor Q1 via resistor R4 and diode D4. At some point near the center of vertical trace, transistor Q2 shunts enough base current i1 to cut off conduction in output transistor Q1. During the second half of vertical trace, with transistor Q2 conductive, S-capacitor voltage V1 drives vertical deflection current i V in the negative direction via transistor Q2. Amplifier U1 increases the conduction of transistor Q2 as the second half of vertical trace progresses, to generate the negative portion of the downwardly ramping vertical deflection current. During the vertical trace interval T t , output voltage V2 is a downwardly ramping voltage. At some instant after the center of trace, S-capacitor voltage V1 has increased and output voltage V2 has decreased to values which enable diode D1 to become forward biased. At this time, bootstrap capacitor C2 is recharged by current i c2 to the S-capacitor voltage V1. With diode D1 conducting, S-capacitor terminal 21 sources currents i c2 and i1. When diode D1 first begins conducting after the center of vertical trace, deflection current i V flows into terminal 21 from S-capacitor C1, and is large enough to be the main source for current i c2 . Near the center of trace and during the second half of trace, S-capacitor C1 becomes the main source for current i c2 . To maintain scan linearity, the AC sawtooth sampling voltage V s , developed across current sampling resistor R12, is summed via a resistor R11 with the 180° out-of-phase sawtooth input voltage V3 at the noninverting input terminal of amplifier U1. To stabilize the DC operating point of output terminal 22 at a predetermined average value, S-capacitor voltage V1, developed at terminal 21, is DC coupled to the noninverting input terminal of driver U1 via a resistor R10. A negative feedback loop is formed from output terminal 22, that includes deflection winding L v , terminal 21, driver amplifier U1 and bottom output transistor Q2. Should, for example, S-capacitor voltage V1 tend to decrease, this decrease in voltage is applied to driver U1 to decrease conduction of transistor Q2. Conduction in transistor Q1 is increased to recharge capacitor C1 to its stabilized average value. To initiate the vertical retrace interval T r , sawtooth input voltage V3 abruptly decreases, producing the cutoff of bottom output transistor Q2 at the end of trace. A resonant retrace interval is initiated that charges a retrace capacitor C3 coupled across diode D5. When transistor Q2 becomes cut off, output voltage V2 begins to increase due to the inductive kick provided by deflection winding L V . Voltage V2 forward biases a retrace diode D2 coupled between the base and emitter electrodes of transistor Q1, and forward biases the base-collector path of transistor Q1. Deflection current i V flows via retrace diode D2 and reverse base-collector conduction into retrace capacitor C3 and the +24 volt supply. Deflection current i V begins to rapidly ramp up during retrace. During retrace, when deflection current i V is negative, bootstrap capacitor C2 is discharged by deflection current i V via reverse collector conduction of transistor Q1. When deflection current i V ramps up during retrace through its zero current value, the inductive action of deflection winding L V decreases output voltage V2 at the emitter of transistor Q1 by an amount that enables diode D2 to become reverse biased. Bootstrap capacitor C2 begins to discharge into the base of top output transistor Q1, maintaining the transistor in saturated conduction throughout the remainder of the retrace interval. At the end of vertical retrace, the positive retrace deflection current i V has increased to a value that enables sawtooth sampling voltage V s to reestablish drive to bottom output transistor Q2, thereby initiating the subsequent vertical trace interval. With bottom device Q2 conducting, a shunt path is established for current i1 that bypasses the base of transistor Q1, bringing the transistor out of saturation into the linear mode of operation. At the end of vertical retrace, some voltage remains in retrace capacitor C3. Capacitor C3 becomes discharged very early within trace by conduction of transistor Q1, after which time diode D5 becomes forward biased. One terminal of a resistor R7 is coupled to a +131V DC voltage supply of value greater than the +24V supply. The other terminal of resistor R7 is coupled to the junction of the collector of transistor Q1 and retrace capacitor C3. A resistor R5 is coupled across retrace capacitor C3. During the second half of vertical trace, when transistor Q1 is cut off, capacitor C3 is precharged to a voltage level that is established by voltage dividing resistors R7 and R5, coupled between the +131V voltage source and the +24V voltage source, in accordance with the RC time constant associated with the resistors and capacitor C3. The precharged voltage on retrace capacitor C3 at the end of trace provides a more rapid retrace of vertical deflection current i V , thereby shortening the duration of retrace interval T r . Embodying an aspect of the invention, S-capacitor voltage V1 is applied to base current generating circuit 40 independently of the DC stabilizing negative feedback loop, to enable the generation of current i1 when the S-capacitor voltage V1 exceeds a predetermined magnitude. Base current generating circuit 40 is dependent on S-capacitance voltage V1 as a DC voltage supply source. Should the magnitude of S-capacitance voltage V1 decrease below the predetermined magnitude, base current generating circuit 40 will be unable to generate adequate current i1 to maintain top output transistor Q1 in conduction. The main charging path for S-capacitor C1 is via top output transistor Q1. When base current generating circuit 40 is unable to supply base current to maintain transistor Q1 conductive, this main charging path will be disabled. Under certain fault operating situations, it may be desirable for the fault to trigger the disabling of base current generating circuit 40 and of the main charging path to capacitor C1. Such a situation may arise, for example, if S-capacitor C1 becomes short-circuited. When S-capacitor C1 becomes short-circuited, voltage V1 will tend to decrease to zero. The DC negative feedback loop via resistor R10 tries to maintain voltage V1 at its stabilized value by turning bottom output transistor Q2 off, in an attempt to maintain transistor Q1 conducting heavily. If base current generating circuit 40 were not disabled in such a situation, large current would flow in the main charging path to the now short-circuited S-capacitor via deflection winding L V , transistor Q1, diode D5 and resistor R6. Excessive dissipation and possible component failure would result. Furthermore, the large unidirectional current flowing in deflection winding L V would deflect the electron beams of the picture tube by a large angle, permitting the electron beams to strike and possibly damage the neck of the picture tube. Embodying an aspect of the invention, when the S-capacitor voltage decreases below a predetermined magnitude, such as may occur when the S-capacitor becomes short-circuited, voltage V1 becomes too low to provide forward bias to diode D1. Bootstrap capacitor C2 becomes disconnected from its source of charging current, disabling the generation of current i1 into the base of top output transistor Q1. Without base current, transistor Q1 becomes nonconductive, disabling the main charging path into the short-circuit of capacitor C1, thereby avoiding undesirable short-circuit fault operation of vertical deflection circuit 20. Embodying another aspect of the invention, an auxiliary or second charging path for capacitor C1 is provided directly to a DC voltage supply, bypassing the main charging path of top output transistor Q1 and the vertical deflection winding L V . A relatively large valued resistor R1 is coupled from a +30V supply to S-capacitor terminal 21. An auxiliary charging current i₀ flows from the +30V supply via resistor R1 to S-capacitor terminal 21. When the television receiver is first turned on, S-capacitor C1 is initially in a discharged state. When the power supply for the television receiver generates the DC supply voltages such as the +24V, +30V and +131V voltages, S-capacitor C1 begins to charge with current i₀ from the +30V supply via resistor R1. Due to the relatively large value of S-capacitor C1, voltage V1 remains below the predetermined magnitude required during start-up for enabling base current generating circuit 40. During this substantial start-up delay interval, transistor Q1 remains essentially cutoff, disabling the main charging path for capacitor C1 via deflection winding L V . When the television receiver is first turned on, the discharged S-capacitor C1 slowly begins to charge with current i₀ from the +30V supply. Voltage V1 begins to increase as C1 charges. As long as voltage V1 is below its normal steady-state value, the DC negative feedback loop maintains transistor Q2 cutoff. No significant current path to ground exists by which bootstrap capacitor C2 may charge. When S-capacitor C1 has charged sufficiently to permit voltage V1 to increase to approximately or slightly greater than its normal, steady-state value, the DC negative feedback loop turns on transistor Q2, enabling bootstrap capacitor C2 to charge to a value which is capable of forward biasing transistor Q1. Soon afterwards, normal steady-state deflection circuit operation commences. During steady-state operation, the value of auxiliary charging current i₀ is determined by the difference in voltage between the +30V supply and the steady-state value of S-capacitor voltage V1. The DC component of current i₀ flows into terminal 21 from the +30V supply. By proper selection of component values, such as the value of resistor R3, the DC component of the current flowing in the current path (R2, D1, R3) equals the DC component of current i₀. In this situation, no net DC current flows in deflection winding L V from resistor R1. If the DC component of current i1 differs from the DC component of current i₀, the difference current will flow as a DC component in vertical deflection current i V . This difference current is of relatively small value and may be eliminated, if so desired, by proper adjustment of a DC centering control circuit for deflection winding L V , not illustrated in FIGURE 1. For the values given in the circuit of FIGURE 1, the start-up delay time for the generation of vertical deflection current is approximately one to two seconds. The start-up delay advantageously permits completion of picture tube degaussing before the generation of vertical deflection current, thereby avoiding any undesirable interaction between the vertical deflection magnetic field and the degaussing process. FIGURE 3 illustrates a portion of a video display apparatus 60, embodying an aspect of the invention, that includes a picture tube degaussing circuit 10 and vertical deflection circuit 20 of FIGURE 1, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing. Vertical deflection circuit 20 of FIGURE 1 is shown in FIGURE 3 in partial detail only. In FIGURE 1, an AC mains supply, developing a voltage V AC , energizes a DC power supply 16 when an on-off switch 15 is conductive, or switched to the on-position. DC power supply 16 develops various DC supply voltages for the circuitry of video display apparatus 60 including a +DC1, a +DC2, a +DC3 and a +DC4 voltage. Voltage +DC4, for example, energizes a horizontal deflection circuit 17 to generate horizontal deflection current in a horizontal deflection winding L H . Degaussing circuit 10 includes a degaussing coil DG located adjacent a picture tube 50 of video display apparatus 60. Degaussing coil DG is coupled in series with a positive temperature coefficient thermistor 13, AC mains supply 14 and the mechanical switch portion of an electro-mechanical degaussing relay 11. The mechanical switch portion of relay 11 is normally non-conductive when the relay coil is deengerized. To initiate a degaussing interval, when degaussing action takes place, on-off switch 15 is made conductive to permit DC power supply 16 to develop the DC supply voltages, including the +DC1 supply voltage. The +DC1 supply voltage is coupled via a charging capacitor 12 to the coil of relay 11. Current flows in the relay coil from the +DC1 supply, energizing the relay coil and closing the mechanical switch portion of degaussing relay 11. With the mechanical switch portion of relay 11 conductive, AC degaussing current flows from AC mains supply 14 in degaussing coil DG and thermistor 13 at the frequency of AC mains voltage V AC . As thermistor 13 self-heats by the degaussing current, its resistance increases producing a decaying alternating degaussing current that reaches a very low residual amplitude, bringing the degaussing interval to a conclusion. The decaying alternating degaussing current produces a decaying alternating degaussing magnetic field that degausses the shadow mask, magnetic shield and other magnetizable material associated with picture tube 50, but not illustrated in FIGURE 3. After conclusion of the degaussing interval, series capacitor 12 charges to the +DC1 supply level, preventing current from flowing in the coil of relay 11. The mechanical switch portion of relay 11 returns to its normally non-conductive position to eliminate the flow of even a residual current in degaussing coil DG after conclusion of the degaussing interval. The DC supply voltages developed by power supply 16 are rapidly developed from a zero voltage level after on-off switch 15 is made conductive. In particular, the DC supply voltages developed for vertical deflection circuit 20 attain levels adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval. Advantageously, however, capacitor C1, whose voltage V1 controls operation of vertical deflection circuit 20, disables base current generator 40 to prevent the generation of vertical deflection current in vertical deflection winding L V immediately after on-off switch 15 is closed. Capacitor C1 is slowly charged from the +DC3 supply via resistor R1 to delay the enablement of base current generating circuit 40 and thus to delay the generation of vertical deflection current until after conclusion of the degaussing interval. This delay avoids any undesirable interaction between the vertical deflection magnetic field and the degaussing process. FIGURE 2 illustrates a vertical deflection circuit 120, embodying the invention, similar to the vertical deflection circuit of FIGURE 1, but modified to reduce any net DC current that may flow through deflection winding L V from auxiliary charging current i₀. Items in FIGURES 1 and 2 similarly identified represent similar elements or quantities. In FIGURE 2, a controllable impedance, a transistor Q3, is interposed between base current generating circuit 40 and the +30V supply, with the collector of the transistor coupled to the +30V supply and the emitter coupled to resistor R2. The base of transistor Q3 is coupled to S-capacitor second terminal 21 at the junction of charging resistor R1 and S-capacitor C1. The S-capacitor voltage V1 controls the conductivity of transistor Q3 and the amount of current flowing in the collector circuit of transistor Q3 to base current generating circuit 40. Should capacitor C1 become short-circuited and voltage V1 decrease to near zero, transistor Q3 becomes cut off, disconnecting the +30V supply from base current generating circuit 40, and disabling the generation of current i1 into the base of top output transistor Q1. Similarly during start-up, because capacitor C1 is initially discharged, transistor Q3 is cut off to disable top output transistor Q1. The auxiliary charging current i 0 charges capacitor C1 after a start-up delay to the value needed to turn on transistor Q3 for enabling base current generating circuit 40. Because of the gain provided by transistor Q3, charging current i 0 may be relatively small, and the net DC current component introduced into deflection winding L V by current i₀ is negligible.

Claims: 1. A deflection circuit, comprising: a deflection amplifier including first and second transistor amplifier output stages; a deflection winding coupled to said first and second transistor amplifier output stages at a deflection amplifier output terminal; an S-shaping capacitance coupled to said deflection winding at a second terminal remote from said amplifier output terminal for developing an S-capacitance Voltage; a source of a deflection rate signal coupled to said deflection amplifier for generating a deflection current in said deflection winding; means (R10) coupled to said deflection amplifier (30) and responsive to a voltage representative of said S-capacitance voltage (V1) for forming a DC negative feedback loop to stabilize the DC voltage at said output terminal (22); and characterized by a base current generating circuit (40) coupled to one (Q1) of said transistor amplifier output stages (Q1,Q2) for providing base current (i1) thereto, said base current generating circuit being coupled to said second terminal (21) and having said S-capacitance voltage (V1) applied thereto independently of said DC negative feedback loop for enabling the conduction of said base current (i1). 2. A deflection circuit according to Claim 1, characterized by a DC voltage supply (+30V) and means (R1) for charging said S-capacitance (C1) from said DC voltage supply above a predetermined magnitude. 3. A deflection circuit according to Claim 2, characterized in that the conduction of said base current becomes disabled when said S-capacitance voltage (V1) is lower than said predetermined magnitude. 4. A deflection circuit according to Claim 3, characterized in that the charging rate of said S-capacitance (C1) from said DC voltage supply (+30V) is sufficiently low to provide a delay to the attainment of said predetermined magnitude for delaying the generation of said scanning current (i V ) during a start-up interval. 5. A deflection circuit according to any one of the preceding Claims characterized in that said charging means (R1) generates a charging current (i O ) that bypasses said deflection winding (L V ). 6. A deflection circuit according to Claim 5, characterized in that said charging means (R1) generates said charging current (i O ) that bypasses a main current path of said one transistor amplifier output stage (Q1). 7. A deflection circuit according to any of Claims 1 to 4, characterized in that said base current generating means (40) includes a controllable semiconductor impedance (Q3) responsive to said S-capacitance voltage (V1) for controlling the conduction of said base current (i1) in accordance with said S-capacitance voltage (V1). 8. A deflection circuit according to any one of the preceding Claims, characterized in that said deflection current (i V ) charges said S-capacitance (C1) each deflection cycle via said one transistor amplifier output stage (Q1) and discharges said S-capacitance via the other stage (Q2). 9. A deflection circuit according to Claim 8, characterized in that the two transistor amplifier output stages (Q1,Q2) form a totem-pole configuration. 10. A deflection circuit according to Claim 9, characterized in that said base current generating circuit (40) includes a bootstrap capacitor (C2) coupled to said tne transistor amplifier output stage (Q1) and means (D1) responsive to said S-capacitance voltage (V1) for charging said bootstrap capacitor (C2) from said S-capacitance (C1) during a latter portion within a trace interval of each deflection cycle. 11. A circuit according to Claim 10 characterized in that said bootstrap capacitor charging means includes means (R2) for applying said S-capacitance voltage (LV) to said bootstrap capacitor (C2) via a rectifier (D1).

Inventors: SUTHERLAND, HUGH FERRAR II
Applicants: RCA LICENSING CORPORATION
Application year: 1987
Main classification: H04N3
IPC codes: H04N9, H04N3, H03K4