RASTER DISPLAY CONTROLLER WITH VARIABLE SPATIAL RESOLUTION AND PIXEL DATA DEPTH

Abstract: A display controller provides multiple different resolutions by selectively enabling different combinations of shift registers (SHR0-SHR7) between the frame buffer and video look-up tables (VLTs). The VLTs are partitioned, with different partitions being programmed identically in accordance with the values of only the number of address bits which will be active from the shift registers at any one time. For example, reading out any of the 512 lines of the frame buffer twice in succession, before incrementing the line counter to access the next line, allows for using one half of the stored bits each time such line is read, to simulate a horizontal resolution having the double number of pixels. Alternatively, making two consecutive passes through the buffer and using each time a different half of the stored bits, allows for simulating a vertical resolution comprising the double number of display lines.

Description: The present invention relates to the control of data to a two-dimensional display screen, e.g., on a computer monitor. More particularly, the present invention is directed to a technique for providing a variable resolution display. Computers commonly operate in different display modes with different display characteristics, in accordance with the requirements of the data being displayed. For example, a typical computer may operate its display in either a text or graphics mode, and may be capable of several different types of graphics modes. Bit plane graphics provides the least expensive way of displaying information on the screen, simply storing one bit for each pixel. However, the versatility of the display is not very good, since the allocation of only one bit per pixel means that no shading can be shown. Gray scale level displays require more memory to store an image of the same resolution. E.g., by allocating four bits per pixel, each pixel can be shown in sixteen different levels of shading, thus increasing the versatility in what kinds of displays can be provided. For the same resolution, however, a gray level display with four bits per pixel will require a frame buffer which is four times as large as that required for a bit plane graphics display. Finally, colour displays typically allocate between four and eight bits per pixel to allow any given pixel to be represented in a large number of different colour shades. To provide the same level of resolution as above, the frame buffer for a colour display would necessarily be four to eight times larger than for a bit plane graphics system. It would be desirable to provide a universal display controller capable of operating in each of the three different modes, but a number of problems are encountered. If the same spatial resolution is required for each different mode, the only approach would be to provide a frame buffer of maximum size which could provide high resolution images even in a colour display having a "depth" of eight bits per pixel. Such an arrangement, however, would be expensive not only due to the cost and size of the frame buffer, but also as a result of the very high cost of high resolution colour monitors as compared with gray level or black-and-white (B&W) monitors of the same resolution. As a practical matter, there is not often a requirement for equal resolution in both B&W and colour modes. Moderately priced systems may include a high resolution B&W monitor and lower resolution colour monitor. Higher priced systems may also utilize monitors with different resolutions, since B&W monitors in general provide higher resolution than the best colour monitors. It is therefore desirable to provide a means for operating at different display resolutions. Examples of display controllers adaptable to different resolutions are disclosed in Patents US-A-4,500,875 to Schmitz and US-A-4,236,228 to Nagashima et al. The latter discloses a technique whereby a slow addressing method is used to assist the microprocessor in appropriately addressing a memory location, but this is not practical for providing fast video refresh. The former reference discloses a technique wherein a plurality of gates are provided in the video data path between the frame buffer and colour map memory. This is disadvantageous not only due to the complexity of the gate array but also in that the different propagation paths through the gate array must be very short and of equal propagation delay, requiring further complex hardware to ensure satisfaction of the timing requirements. From EP-A-0 166 054 a graphics display terminal and method of storing alphanumeric data therein is known. The graphics display terminal comprises a raster-scan display device and a refresh buffer including a plurality of bit planes each having a respective bit storage location corresponding to each addressable pel position on the screen of the display device. In the method, a first bit plane stores high resolution luminescence data defining alphanumeric characters each as a selection of "on" bits and at least one further bit plane stores low resolution color data for the characters. However, this method does not provide for variable spatial resolution. Thus, a display controller with a permanent frame buffer configuration requires a very large frame buffer size to handle both requirements of high resolution and of maximum pixel depth. It is possible to provide additional hardware to reconfigure the frame buffer structure for particular applications, but such additional hardware would be quite expensive. It is, therefore, an object of the present invention to provide a display controller capable of variable spatial resolution and variable pixel data depth. It is a further object of this invention to provide such a system which avoids the use of costly additional frame buffer reconfiguration hardware. It is a feature of the present invention, as claimed, that the frame buffer is software-reconfigurable using a Video Look-up Table (VLT). Briefly, the present invention employs a frame buffer configured for the maximum pixel data depth data mode at a limited spatial resolution, and a VLT for receiving the frame buffer output data and providing appropriate pixel data through a digital-to-analog (D/A) converter to the monitor. If a colour monitor is used, separate VLTs may be used for each colour. All VLTs are divided into partitions which are programmed identically. A plurality of shift registers are used to pass the data from the frame buffer to the VLTs. The shift registers are arranged such that their collective outputs at any given time will represent a multi-bit address word to the VLT. The shift registers are provided with separately controllable Clear inputs so that the effective depth of the pixel data can be varied in accordance with the display mode, allowing a concomitant increase of the spatial resolution, if desired. For example, with a maximum pixel depth of eight bits per pixel, all eight shift registers may be used to provide data to the VLTs. In a higher resolution mode, the pixel depth may be four bits per pixel. This can be accomplished by reading through a column or row of the frame buffer twice, the first time utilizing half of the shift registers to provide half of the data to the VLTs, and the second time using the other half of the shift registers to provide the other half of the frame buffer data to the VLTs. For a frame buffer configured for a pixel depth of eight bits, it is possible to increase the display resolution by a factor of eight by reading out only one bit per pixel. The invention will be more clearly understood from the following description in conjunction with the accompanying drawings, wherein: FIG. 1 is a block diagram of a display controller in accordance with a first embodiment of the present invention; FIG. 2 is a block diagram of a display controller in accordance with a second embodiment of the present invention; and FIG. 3 is a block diagram of a display controller in accordance with a third embodiment of the present invention. A relatively simple implementation of the present invention is represented by the embodiment of FIG. 1. In this embodiment, the frame buffer having an organization of 1024 (horizontal) x 512 (vertical) by 8 (depth) can be also used to provide a resolution of 1024 x 1024 with a depth of 4 bits per pixel. The system of FIG. 1 is a conventional display controller with three VLTs (red, green and blue), a frame buffer, eight N-bit shift registers SHRO-SHR7, D/A converters for the outputs of each of the VLTs, and a line counter. The frame buffer may be a µpD 41264 video RAM made by NEC Corporation. The line counter provides nine bits (0-8) of its output as the vertical video-refresh address to the frame buffer, so the line or row address range is 0 ... 511. Each successive address from the bits 0-8 of the line counter addresses one of the 512 lines, or rows, of the frame buffer, with each row including 1024 8-bit pixel data values. In a known manner, the 8 bits of each pixel data value can be read out in parallel, with each bit going to a respective one of the shift registers SHR0-SHR7. These N-bit shift registers are loaded in response to a signal (VCLK/N) applied to their load terminal LD, so that N pixel values are taken from the frame buffer at each load signal (VCLK/N), where N is a ratio between the video clock (VCLK) frequency and the frame buffer video refresh read-out period. Next to each load signal, N pulses of the video clock VCLK occur, shifting out in parallel the contents of all registers SHR0-SHR7, with the collective outputs of the shift registers at any given time representing one of the 8-bit pixel data values provided in common to all of the VLTs. In addition to the conventional structure, the device includes a one-bit Mode Register, two NAND gates and one inverter INV. In addition, the line counter includes an extra bit position LC<9>. The "clear" inputs CLR of the shift registers SHR0-SHR3 are connected in common to the output of the gate NAND1, and the "clear" inputs of the registers SHR4-SHR7 are connected in common to the output of gate NAND2. For 512 x 1024 resolution, the mode register is set to a value of "0". This will cause the outputs of each of the gates NAND1 and NAND2 to be continually high, so that none of the shift registers SHR0-SHR7 are cleared. Once each count of the line counter, a new line in the frame buffer is accessed. Once each cycle of the load signal (VCLK/N), N 8-bit pixel data values are loaded in parallel into the registers SHR0-SHR7. The register contents are then shifted out in response to the video clock signal VCLK, with the collective outputs of the shift registers SHR0-SHR7 at any time representing one 8-bit pixel value. These 8-bit values are provided in common to all three VLTs. With each pixel value having a depth of 8-bits, the VLTs can cooperate to provide 256 different shades of colour for each pixel. Alternatively, a B&W monitor may be used, e.g., operated in accordance with a gray scale. If higher resolution is desired, this can be easily accomplished by effectively dividing the frame buffer into halves. More particularly, instead of operating the frame buffer as though each line includes 1024 columns which are 8-bits deep, the frame buffer is operated as two different 512 x 1024 x 4 buffers. To operate in the 1024 x 1024 mode, the mode register is set to a value of "1". During a first pass through the frame buffer, the output bits 0-8 from the line counter sequentially step through all 512 lines of the frame buffer. At this time, the additional bit LC<9> is low, so that the output of NAND1 is high and the output of NAND2 is low. As a consequence, registers SHR4-SHR7 are kept cleared. Thus, when the 8-bit words are loaded in parallel across the 8 registers SHR0-SHR7, the bits 4-7 are effectively ignored, with the 8-bit word subsequently provided to the VLTs comprising the output bits from SHR0-SHR3 as its four least significant bits and a value of "0" as its four most significant bits. During the next pass through the 512 lines of the frame buffer, the additional bit LC<9> has a value of "1", so that the output of NAND1 is low and the output of NAND2 is high. This time through, the registers SHR0-SHR3 are maintained cleared, while the bits 4-7 from each column of the frame buffer are provided through the registers SHR4-SHR7 as the four most significant bits of the address word to be provided to the VLTs. Thus, in this higher resolution mode, the four upper bits of the pixel data are equal to 0 during the first half of the frame period, and the four lower bits are equal to 0 during the second half. If VLT R is loaded in accordance with Table 1, set forth below, the data value provided at the output of the VLT will be determined in accordance with only those four bits from the shift registers SHR which are not cleared. The frame buffer data stored in bits 0-3 corresponds to the pixel values for the raster lines 0-511, while the data stored in the bits 4-7 corresponds to the pixel values for the raster lines 512-1023. In this way, the output of VLT R is exactly the same as if the frame buffer would have been organized as a 1024 x 1024 x 4 memory. The A(0)...A(F) data provided at the output of VLT R may represent image transformation data (e.g., gamma correction data), or in the simplest case may simply be equal to the VLT location address (proportional output). As a result, the output of the D/A converter connected to VLT R can be used for a B&W monitor with double resolution. Of course, the vertical sync parameters should be mode-dependent as well, and this can be accomplished in a straightforward manner which need not be described in detail here. No additional hardware is required for communication with the host processor. When the desired resolution is 512 x 1024, data can be written in complete 8-bit bytes. If the resolution is changed to 1024 x 1024, a read-modify-write mode can be used (i.e. stored data are read, then modified and re-stored) in order to write either the upper or lower four bits as required. As can be seen from the above description, a value of "0" in the mode register allows the frame buffer to perform as a 512 x 1024 x 8 buffer, thus giving a resolution of 512 x 1024 with 8 bits of depth per pixel. A mode register value of "1" permits the buffer to operate as a 1024 x 1024 x 4 buffer for a resolution of 1024 x 1024 and four bits of "depth" per pixel. The embodiment of FIG. 1 is thus easily implemented without excessive frame buffer storage requirements and without costly additional hardware, while providing a simple and effective technique for alternately operating at different resolutions. Fig. 2 illustrates a second embodiment of the invention which is useful if there exists a speed limitation which will not permit the use of a read-modify-write mode to separately maintain the upper and lower halves of the frame buffer during 1024 x 1024 operation. In FIG. 2, the frame buffer address register FBADREG serves a similar function as the line counter in FIG. 1, with the first 9 bits (0-8) providing the line address to the frame buffer. The mode signal is provided from a mode register (not shown) as in the embodiment of FIG. 1. In this embodiment, the read signal FBRD is high during a frame buffer read operation, and the write signal FBWR is high during a frame buffer write operation. In addition, transceivers T1, T2 and T3 are provided between the frame buffer data I/O ports and the host data bus, with the direction of data transmission through the transceivers being controlled in accordance with the signal at the direction terminal D. (In some cases where it is unnecessary to change the width of the host data path to the frame buffer from 8 bits to 4 bits, these additional transceivers may be unnecessary.) For MODE = 0 operation, i.e. for 512 x 1024 resolution with 8 bits of depth per pixel, the outputs of NAND1 and NAND2 are always high, and the transceiver T3 is disabled through the inverter INV2. During a read operation, the outputs of gates NAND3 and NAND4 are low so that each of transceivers T1 and T2 will pass data in the direction from the frame buffer to the host data bus. For a write operation, the outputs of gates NAND5 and NAND6 are both low, enabling the writing of data into all 8 bits of the frame buffer depth. The outputs of gates NAND3 and NAND4 are high, so that transceivers T1 and T2 pass all 8 bits of data in the direction from the host data bus to the frame buffer. For 1024 x 1024 resolution with a depth of 4 bits per pixel, the MODE signal is set to a value of "1", thus disabling transceiver T2 and enabling transceiver T3. For a read operation, the signals FBRD and FBWR are high and low, respectively. During the first 512-count cycle of the frame buffer address register bits 0-8, the additional bit FBADREG<9> will have a value of "0", so that the outputs of NAND1 and NAND2 will be high and low, respectively. As a consequence, the outputs of gates NAND3 and NAND4 will be low and high, respectively. Transceiver T1 will pass the frame buffer bits 0-3 to the host data bus. Transceiver T3 will pass the same bits back to the I/O ports for bits 4-7, but this will be of no consequence since the writing of data into the frame buffer will be disabled. During a second pass through the frame buffer, the additional bit in the frame buffer address register will be high, so that the outputs of gates NAND1 and NAND2 will be low and high, respectively, and the outputs of gates NAND3 and NAND4 will be high and low, respectively. During this half of the frame period, the frame buffer output bits 4-7 are provided to the host data bus through the transceiver T3. Thus, the bits 0-3 on the host data bus will always represent the pixel data, and the frame buffer will appear to the host processor to operate as a 1024 x 1024 x 4 structure. For a write operation in the high resolution mode, the signals FBRD and FBWR are low and high, respectively, so that the outputs of both of gates NAND3 and NAND4 will be high and the transceivers T1 and T3 will both pass data in the direction from the host data bus bits 0-3 to the frame buffer data I/O ports. During a first pass through the 512 lines of the frame buffer, the additional bit in the frame buffer address register will have a low value, so that the outputs of gates NAND1 and NAND2 will be high and low, respectively, and the outputs of gates NAND5 and NAND6 will consequently be low and high, respectively. Thus, the four bits 0-3 of pixel data provided from the host data bus in common through the transceivers T1 and T3 can only be written into the bits 0-3 of the frame buffer. During the second half of the frame period, the additional bit in the frame buffer address register will have a high value, so that the outputs of gates NAND5 and NAND6 will be high and low, respectively, thereby permitting the four bits of data provided from the host data bus to be written only into the bits 4-7 of the frame buffer. The embodiment of FIG. 2 is supplementary to that of FIG. 1. It is relatively easily implemented and helps to provide an effective technique for operating in either a 512 x 1024 x 8 mode or 1024 x 1024 x 4 mode, without requiring either an excessive frame buffer storage capacity or complicated hardware for switching between different modes of operation. It should also be noted that the displayable image could be selected between these lower and higher resolution modes, e.g., 1024 x 800 x 4. This could be achieved by simply changing sync parameters and through corresponding adjustment of the sequence of the video refresh addresses. Turning now to FIG. 3, a third embodiment of the invention is illustrated for controlling spatial resolution in either direction. In the example of FIG. 3, the frame buffer structure is 512 x 512 x 8 bits, and again the buffer may be the NEC µpD 41264 video RAM. As before, the frame buffer output is provided in parallel across 8 shift registers SHR0-SHR7 each having a separately controllable clear terminal CLR . The embodiment of FIG. 3 further includes an 8-bit clear data register CLR, and a combinational shifter SHIFT, the shift amount of which is controlled by a 3-bit shift signal SH. In this embodiment, the mode register MODR is a three-bit register. As before, the line counter LCNT includes 9 bits (0-8) which provide the line count portion of the video refresh address to the frame buffer. The scan generator multiplexer SGMUX provides any one of the bits 8-10 of the 11-bit pixel counter PCNT to the count input of the 11-bit line counter LCNT, and the shift multiplexer SHMUX provides an appropriate 3-bit control signal SH to the shifter SHIFT. Both of the multiplexers SGMUX and SHMUX are controlled by the three-bit output from the mode register MODR. Next to each of the multiplexer inputs, the controlling 3-bit combination which selects that input is shown, in FIG. 3. When LCNT is stepped, PCNT is reset to zero. The following Table 2 shows the various resolutions which are available, the data depth at each resolution, the corresponding mode register value and CLR data value. For 512 x 512 x 8 operation, the data in the clear data register CLR is FF (hex), i.e., all ones. Thus, regardless of the value of the shift signal SH, all outputs of the shifter SHIFT will be 1, and none of the registers SHR0-SHR7 will be cleared. Under control of the line counter, now clocked by PCNT<8> since MODR = 000, byte-wide data will be read out of the frame buffer into the registers SHR0-SHR7 and will be provided from there to the VLTs. The line counter is stepped when the pixel counter reaches a value of 512, i.e. when PCNT<8> makes a negative transition, from 1 to 0 value. For 1024 x 512 x 4 operation, the mode register is set to a value of 1 and the register CLR is set to a value of OF (hex), i.e., 00001111. Each line is read out once due to clocking of the line counter by PCNT<8>, but two passes are made through the buffer lines to simulate 1024-line vertical resolution. To read a different four bits during each pass through the 512 lines, the shift control signal SH for MODR = 001 is controlled by LCNT<9>. In particular, when the first 512 lines are being displayed, LCNT <9> = 0 so that the shift control signal SH is zero and the shifter SHIFT passes the CLR output value of OF (hex) unchanged, so that the four higher-order control bits are zero and SHR4-SHR7 are cleared. When the next 512 lines are being displayed, LCNT <9> = 1 so that the shift control signal SH is 4 (hex) whereby the CLR value of OF (hex) is shifted four steps, resulting in FO (hex), and SHR0-SHR3 are cleared. For 512 x 1024 x 4 operation, the mode register is set to a value of 2 (i.e., "010"), and the register CLR is again set to a value of OF (hex). With the mode register MODR having a value of "010", the shift control signal SH will be determined by PCNT<9>, i.e. it will be 0 during the first 512 pixels and 4 (hex) during the second 512 pixels of each displayed line. The scan generator multiplexer SGMUX will pass PCNT<9> to the count input of the line counter LCNT so that each line will be read twice in succession during a single pass of the line counter through the 512 lines of the buffer. This will simulate a buffer line length of 1024 pixel values. For 1024 x 1024 resolution, the pixel data depth is reduced to two bits, and the mode register MODR is set to a value of 3 (i.e., "011"), with the clear data register CLR being set to a value of 03 (hex), i.e., 00000011. Two passes must be made through the 512 lines of the frame buffer, to simulate 1024 display lines and, during each pass, every buffer line must be read twice to simulate 1024 pixels per line. The line counter LCNT is again clocked by PCNT<9> so that a line is read twice in succession for each LCNT output, and the SH signal to the shift register SHIFT will be represented by (LCNT9, PCNT9, 0). A timing sequence of the CLR signals (0 = clear, 1 = do not clear) and video refresh addresses corresponding to the 1024 x 1024 x 2 reorganization of the frame buffer is shown in the following Table 3. The row address RA is represented by the lower 9 bits (0-8) of the line counter LCNT, with the column address CA being internally generated by the frame buffer, and of course also being represented by the lower 9 bits of the pixel counter PCNT. As can be seen from Table 3, a first pass through the 512 lines of the frame buffer is made, with each line being read out twice. During the first reading of each line, only SHR0 and SHR1 are used, with the remainder of the registers SHR2-SHR7 being kept cleared. During the second reading of each line, only registers SHR2 and SHR3 are used i.e. not cleared. Next, a second pass through the 512 lines of the frame buffer is made, with each line again being read out twice. During the first reading of each line, only the registers SHR4 and SHR5 are not cleared, and during the second reading of each line only the registers SHR6 and SHR7 are not cleared. Thus, with two readings of each line, and two passes through the 512 lines, the 512 x 512 x 8 frame buffer is effectively operated as a 1024 x 1024 x 2 structure. For 2048 x 1024 x 1 operation, the mode register MODR is set to a value of "100" with the clear data register CLR set to a value of 00000001, as shown in the previous Table 2. In this mode, each line is read twice to simulate a horizontal resolution of 1024, and four passes are made through the 512 lines of the frame buffer to simulate a vertical resolution of 2048. The shift signal SH is controlled by LCNT<10>, LCNT<9> and PCNT<9>. Finally, for 1024 x 2048 x 1 operation, the mode register MODR is set to a value of "101" with the clear data register CLR having a value of 00000001. The line counter LCNT is stepped by PCNT <10> so that a line is read four times in succession for each LCNT output. The SH signal to the shift register SHIFT is represented by (LCNT9, PCNT10, PCNT9). During a first pass through the 512 lines of the frame buffer, each line is read four times, passing a single different bit each of those four times. During a second pass through the 512 lines of the frame buffer, each line is again read four times, each time passing a single one of the remaining four bits of the buffer depth. This effectively goes through the 512 lines of memory twice to simulate a vertical resolution of 1024, while reading each line four separate times to simulate a horizontal resolution of 2048. As can be seen from the above description, the present invention provides a frame buffer architecture that can be used with a wide variety of monitors with different resolutions. The solution is most suitable for systems already using a video look-up table (VLT) for conventional purposes, e.g., gamma correction, colour transformations, 2.5D graphics, etc. In such cases, the implementation requires very little additional hardware.

Claims: A display control apparatus for storing image data representing an image to be displayed and for providing a stream of display control data to a display means for displaying said image, wherein said image has a resolution of l · m · n pixels, where l is the number of lines, m is the number of pixels in a line and n is the number of bits per pixel, said display control apparatus comprising: storage means (FRAME BUFFER) for storing said image data, said storage means being organized in I lines and J columns of storage locations each for storing a pixel data value and each storage location having K bits, where I · J · K ≧ l · m · n; translation means for translating said image data into said display control data; a set of K shift register means (SHR0-SHR7) for receiving the image data from said storage means and for providing said image data to said translation means; line counter means (LCNT) having at least ldl digit positions, said line counter means providing at least a portion of its output as a line count address to said storage means (FRAME BUFFER); pixel counter means (PCNT) having at least ldm digit positions, said pixel counter means providing at least a portion of its output as a pixel count address to said storage and/or said display means; characterized in that in the case that the number l of lines is chosen to be greater than I, a first control signal (LCNT<10>, LCNT<9>) is generated based on a transition of one of the ldl - ldI most significant digit positions (9, 10) of said line counter means, and in the case that the number m of pixels in a line is chosen to be greater than J, a second control signal (PCNT<9>, PCNT<10>) is generated based on a transition of one of the ldm - ldJ most significant digit positions (9, 10) of said pixel counter means, so that a subset of said set of shift register means is enabled in response to said first and/or second control signal. The display control apparatus as defined in claim 1, wherein said display control apparatus is capable of operating in a first resolution mode wherein all of said shift registers are enabled at one time, and at least one second resolution mode wherein at most L of said shift registers are enabled at one time, where L<K and preferably L divides K. The display control apparatus as defined in any previous claim, wherein said display control apparatus is capable of operating in a plurality of second resolution modes. The display control apparatus as defined in claim 3, wherein said plurality of second resolution modes include different horizontal resolutions. The display control apparatus as defined in claim 3 or 4, wherein said plurality of second resolution modes include different vertical resolutions. The display control apparatus as defined in any previous claim, wherein said line counter means comprises address means (LCNT) for generating a multi-bit cyclical signal, with M bits being provided to said storage means as an address signal for reading out said image data and at least one additional bit (LC<9>) designating shift registers to be enabled during operation in said second resolution mode. The display control apparatus as defined in claim 6, further comprising mode designation means (MODR) for providing a mode signal indicating the desired resolution mode, and logic means (NAND1, NAND2, SG MUX, SH MUX) responsive to said mode signal and to the value of said at least one additional bit for selectively enabling and disabling said shift registers. The display control apparatus as defined in any previous claim wherein said translation means comprises at least one memory (VLT) addressed by the collective outputs of said plurality of shift registers, said at least one memory, in said second resolution mode, storing display control values corresponding to the address values represented by the L shift registers which are enabled at one time, whereby identical display control values are stored at different locations (Table 1) in said at least one memory. The display control apparatus as defined in any previous claim, wherein: said storage means comprises a buffer memory having I lines and J columns of storage locations each for storing a pixel data value, with each storage location having K bits, said buffer memory having separately controllable write enable terminals ( WE ) corresponding to each of said K bits for enabling the writing of data into a respective bit position in accordance with write enable signals, and data Input/Output (I/O) ports for providing data to and from said buffer; said display control apparatus is capable of operating in a first resolution mode in which all shift registers are enabled at one time and a second resolution mode in which less than all of said shift registers are enabled at one time, said line counter means comprises address means for generating a multi-bit cyclical signal, with M bits being provided to said storage means as an address signal for reading out said image data and at least one additional bit for designating shift registers to be enabled during operation in said second resolution mode, and means for providing a read signal (FB RD) designating a read operation; said display control device further includes means for providing a mode signal (MODE) designating a desired resolution mode, means for providing a writ signal (FB WR) designating a write operations, transceiver means (T1-T3) coupled between said data I/O ports and a host processor data bus for passing data in a direction in accordance with a direction control signal at their control (D) terminals; logic means (NAND5-NAND6) responsive to said mode signal, said write signal and the value of said additional bit for providing said write enable signals, and logic means (NAND3-NAND4) responsive to said mode signal, said read signal and the value of said additional bit for providing said direction control signals. The display control apparatus as defined in claim 9, wherein said transceiver means comprises a first transceiver (T1) coupled to a first plurality of said data I/O ports and to a first plurality of bit positions of said host processor data bus and receiving a first direction control (NAND3) signal, a second transceiver (T3) coupled between a second plurality of said data I/O ports and said first plurality of bit positions of said host processor data bus and receiving a second direction control (NAND4) signal, a third transceiver (T2) coupled between said second plurality of data I/O ports and a second plurality of bit positions of said host processor data bus and receiving said second direction control signal, and further logic means (INV2) responsive to said mode signal for selectively enabling only one of said second and third transceivers. The display control apparatus as defined in any previous claim, wherein: said display control apparatus further comprises a first multiplex means (SG MUX) for selectively providing any one of a plurality of pixel counter means outputs as line count increment signals to said line counter means in accordance with a mode (MODR) signal; and a first register (CLR) for storing clear data representing shift registers to be enabled, a control shift register (SHIFT) for receiving said clear data and serially shifting said clear data in accordance with a shift signal (SH), the contents of said control shift register then being provided in parallel as enabling signals to said plurality of shift registers, and second multiplexer means (SH MUX) responsive to said mode signal for providing selected outputs from said pixel and line counter means to said control shift register as said shift signal.

Inventors: LUMELSKY, LEON
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: G09G1
IPC codes: G09G5