LASER INCLUDING MONOLITHICALLY INTEGRATED PLANAR DEVICES AND PROCESSES FOR THEIR PREPARATION

Abstract: Monolithically integrated devices are dis­ closed in which a laser having a capping layer with a relatively high conductivity imparting ion concentra­ tion is laterally offset along a planar surface from a surface layer having a lower conductivity imparting ion concentration. The monolithically integrated layer and sur­ face layer are formed by providing laterally offset channels in a planar substrate surface and selec­ tively epitaxially growing the required laser layers and the surface layer in separate channels.

Description: This invention is directed to semiconductor lasers, specifically monolithically integrated lasers, and to processes for their manufacture. In preparing monolithically integrated semiconductor components (also referred to as chips) distinct advantages have been recognized to result from employing monocrystalline semiconductive substrates presenting planar surfaces-i.e., surfaces having the low levels of relief common to semiconductor devices fabricated using planar processing. Planar surfaces exhibit a relief variance of a micrometer (µm) or less. When monocrystalline semiconductive substrates exhibit surface relief in excess of about 1 µm, particularly when these relief differences are exhibited by next adjacent chip components, manufacturing difficulties arise leading to reduced yields. As the relief differences between adjacent chip elements increases, the slope of connecting surfaces of the substrate increases, shifting from a horizontal orientation toward a vertical orientation. As surface orientations become increasingly sloped, the choice of techniques by which overlying layers, such as insulative or conductive layers, can be deposited reliably is reduced. Additionally, increased relief differences impose localized reduced radii of curvature on overlying layers. It is at these sites in overlying layers that coating non-uniformities are most common. Further, it is at the low radius of curvature layer locations that stress defects, such as those attributable to differences in thermal expansion characteristics, are most likely to occur. Botez, "Laser Diodes are Power-Packed", IEEE Spectrum, June 1985, pp. 43-53, provides a state of the art survey of laser diodes as discrete elements. Positivie index lasers are disclosed and schematically illustrated. Although it is a simple matter for Botez to show schematically planar surfaces for discrete lasers, it has been a problem of long standing in the laser art to find ways of monolithically integrating lasers with other circuit components while achieving workable chip topographies. It is known in the art that a laser can be formed by planar processing. Such lasers are formed by introducing along a substrate surface N and P conductivity type ions in laterally spaced regions so that an active region is created therebetween. While such lasers are ideal in terms of achieving an overall planar surface for a chip, emission efficiency of such lasers is relatively low. For this reason Botez limits discussion to lasers which consist of a plurality of superimposed semiconductive layers. Lasers can be formed with only three superimposed layers, superimposed N and P conductivity type layers with an active layer intervening. Efficient lasers are typically formed with five or more superimposed layers. Perhaps the most common approach for preparing a monolithic circuit including a laser is to grow the required laser layers over the entire upper surface of the semiconductive substrate and then to remove these layers by etching from all but the desired laser areas. This produces lasers of the mesa type, with several layers protruding above the lowest common substrate surface. Attempts to overcome the high relief of mesa construction have included subsequently regrowing the substrate epitaxially in etched substrate regions. Unfortunately, this also results in additional deposits on the laser mesa so that ultimately achieving a surface that approaches a planar surface is a laborious undertaking and not readily achieved. As a result of these difficulties one approach to which the art has resorted in monolithically integrating lasers and other semiconductive circuit components is to increase the lateral distance between the laser and next adjacent component spacing. While this does not reduce the relief difference between the laser surface and the adjacent component surface, it does reduce the slope of the intervening surfaces. Typical integrated circuit arrangements of this type are illustrated by Sanada et al, "Monolithic Integration of a Low Threshold Current Quantum Well Laser and a Driver Circuit on a GaAs Substrate," App. Phys. Lett. 46 (3), February 1, 1985, pp. 226-228, and Cohen, "Optoelectronic Chip Integrates Laser and Pair of FETs", Electronics, June 30, 1983, pp. 89 and 90. The inherent disadvantage of increased spacing to achieve reduced slope is that it is incompatible with the higher packing densities of chip components desired for efficient substrate utilization and therefore limits the number of elements which can be accommodated within a given chip area. Recognizing the difficulties of integrating wave guides such as lasers in multicomponent chips, the art has continued to investigate the properties of waveguide semiconductive materials and the manner in which such materials can be deposited. Ghosh et al, "Selective Area Growth of Gallium Arsenide by Metalorganic Vapor Phase Epitaxy," App. Phys. Lett. 45 (11), December 1, 1984, pp. 1229-1231, discloses the selective growth of gallium arsenide by organometallic vapor phase epitaxy on a gallium arsenide substrate partially masked by a silica layer. Tokumitsu et al, "Molecular Beam Epitaxial Growth of GaAs Using Trimethylgallium as a Ga Source," J. Appl. Phys. 55 (8), April 15, 1984, pp. 3163-3165, reports similar selective deposition employing molecular beam epitaxy. Kamon et al, "Selective Epitaxial Growth of GaAs by Low Pressure MOVPE," Journal of Crystal Growth 73 (1985), pp. 73-76, discloses the selective growth of gallium arsenide on gallium arsenide in areas not covered by silica and in "Selective Embedded Growth of AlGaAs by Low-Pressure Organometallic Vapor Phase Epitaxy", Japanese Journal of Applied Physics, 25 (1), January 1, 1986, pp. L10-L12, extend their previous disclosure to growing selective gallium aluminum arsenide on an etched substrate. In one aspect this invention is directed to a process comprising (i) providing a monocrystalline substrate, (ii) epitaxially growing on the substrate a laterally restricted lasing region comprising superimposed P and N conductivity type cladding layers, an active layer therebetween, and a capping layer adjacent the major surface having greater than 10¹⁹ conductivity imparting ions per cm³, laterally offset from the lasing region providing on the substrate a semiconductive surface layer having a conductivity imparting ion concentration less than that of the capping layer, for the integration of another circuit component, the substrate and the layers together forming a monocrystalline III-V compound structure, wherein the group V ions are arsenic and the group III ions are at least one of gallium and aluminum, and (iii) providing conductive means at the compound structure surface for providing a conduction path between the surface layer and the capping layer; such process being capable of offering the advantage of selective deposition of the waveguiding III-V compound at desited sites. Additional advantages which can be realized include forming waveguides with planar surfaces, avoiding etching of large areas of the device or epitaxial deposition onto other areas after the waveguide is formed in order to achieve the desired planar surface structure. The above advantages can be realized while at the same time choosing the initial composition of the substrate to achieve desired positive index waveguide and electrical isolation characteristics. Finally, it is an object to provide a process compatible with achieving layers overlying the semiconductor substrate which are more readily and more reliably produced. The process is characterized in that (a) the substrate adjacent one major surface intended to separate the lasing region and the surface layer is formed of monocrystalline gallium aluminum arsenide having a resistivity greater than 10⁵ ohm-cm and (b) the capping layer, the surface layer, and the separating substrate surface are formed to present a planar surface by the steps including (c) providing on the one major surface a protective layer defining an opening, (d) through the opening creating a channel in the substrate to expose an unprotected portion of the substrate beneath the one major surface, (e) epitaxially depositing the laser region layers on only the unprotected substrate portion, at least the active layer being comprised of gallium arsenide or gallium aluminum arsenide of a higher refractive index than the substrate monocrystalline gallium aluminum arsenide, (f) terminating epitaxial deposition when the lasing region forms with the one major surface an overall planar surface, (g) forming the surface layer to present a planar surface with the substrate at a location laterally offset from the lasing region, and (h) depositing on the planar surface at least one conductive means providing a conduction path between the surface layer and the capping layer. It is another object of this invention to provide a semiconductor device comprised of a substrate having a major surface, a laterally restricted lasing region comprising superimposed P and N conductivity type cladding layers, and active layer therebetween, and a capping layer adjacent the major surface having greater than 10¹⁹ conductivity imparting ions per cm³, a semiconductive surface layer laterally offset from the lasing region having a conductivity imparting ion concentration less than that of the capping layer, for the integration of another circuit component, the substrate and the layers together forming a monocrystalline III-V compound structure, wherein the group V ions are arsenic and the group III ions are at least one of gallium and aluminum, and conductive means at the compound structure surface for providing a conduction path between the surface layer and the capping layer; such device offering the advantage of presenting a planar surface, which facilitates the formation of overlying layers, such as conductive and insulative layers, and allows these layers to be more reproducibly formed. A further advantage is that the substrate portion separating the lasing region and the laterally offset surface layer along the planar surface requires no special modification to isolate adjacent layers and provide positive waveguiding. Another advantage is that the substrate adjacent the planar surface is better suited for electrical isolation and for the integration of additional circuit components. The device is characterized in that the substrate forms with the capping layer and the surface layer a planar surface of the monocrystalline III-V compound structure, the conductiv means is located on the planar surface, and the substrate comprises monocrystalline gallium aluminum arsenide of a single conductivity type having a resistivity of greater than 10⁵ ohm-cm isolating the surface layer from the lasing region and providing positive index wave guiding at its interface with the active layer. Brief Description of the Drawings These and other advantages of this invention can be better appreciated by reference to the following detailed description of the invention considered in conjunction with the drawings, in which Figure 1 is a sectional detail of a semiconductor element according to the invention; Figure 2 is a sectional detail at one stage of element fabrication; Figures 3A and 3B are sectional details of alternative channel configurations; Figure 4 is an isometric view showing alternative channel orientations; and Figure 5 is a sectional detail at a fabrication step following formation of one laser and before formation of a second laser. In Figure 1 is shown a detail of an exemplary preferred semiconductor device 100 according to the present invention containing a laser monolithically integrated with a field effect transistor. The device in the detail shown is comprised of a monocrystalline III-V compound structure consisting of a substrate 102, a lasing region 108, and a surface layer 222. As shown, the lasing region and the surface layer are epitaxially grown in channels 110 and 210, respectively, of the substrate. A first major surface 124 of the substrate and the upper surfaces of the lasing region and the surface layer together form an overall planar surface of the device while the substrate alone forms a second major surface 126 of the device. A first electrode 128 serves as an ohmic contact to the second major surface. An insulative layer 130 overlies the planar surface provided by the lasing region, surface layer, and substrate. The insulative layer contains first and second apertures 132 and 232 overlying the lasing region and the surface layer, respectively. A second electrode 134 contacts the upper surface of the lasing region through the first aperture and extends over the intervening portion of the insulative layer to contact one extremity of the surface layer through the second aperture, thereby conductively joining the lasing region with the surface layer. A third electrode 224 overlies the insulative layer and contacts the opposite extremity of the surface layer through the second electrode. A gate electrode 226 contacts the surface layer at a location mediate its extremities within the second aperture. The surface layer and the electrodes therefor together form a field effect transistor in the preferred embodiment shown. The second and third electrodes form ohmic contact with the surface layer and act as source and drain electrodes for the field effect transistor. The gate electrodes forms a Schottky barrier interface with the surface layer. The substrate 102 in one preferred form is comprised of a more conductive portion 104 typically formed of gallium arsenide containing at least 5 X 10¹⁷ and preferably from 1 to 3 X 10¹⁸ N conductivity type ions per cm³. An isolating portion 106 of the substrate is comprised of an aluminum gallium arsenide layer epitaxially grown on the more conductive portion of the substrate. The isolating portion contains sufficient aluminum to reduce its refractive index below that of the active layers of the lasing regions, which it laterally confines, so that it forms with the lasing region a positive index waveguide. The isolating portion preferably contains about 30 to 60 mole percent aluminum, mole percentages being based on the total group III ions present, except as otherwise indicated. To isolate the lasing region electrically from the field effect transistor and any other integrated circuit components, not shown, at least the portion of the substrate adjacent the first major surface exhibits a resistivity of greater than 10⁵ ohm-cm, preferably greater than 10⁷ ohm-cm. Suitable resistivity levels can be achieved by known gallium arsenide deposition techniques, such as by gallium arsenide deposition at temperatures of 550 to 650°C and/or in an atmosphere containing from 2 to 10 ppm of oxygen. Since the insulating portion need not be relied upon for current conduction, the majority charge carriers can be of either N or P conductivity type or the insulating portion can be substantially intrinsic. The surface layer is of either N or P conductivity type and is preferably of a conductivity type opposite that of said substrate so that the surface layer and substrate form a junction at their interface. The surface layer preferably contains a dopant impurity concentration of from about 10¹⁴ to 10¹⁷ ions per cm³. Overlying the second, third, and gate electrodes is an electrically insulative barrier layer 136. It should be noted that though neither the second and third electrodes nor the barrier layer are shown deposited on a zero relief surface, each are presented with planar surfaces, since the relief variance introduced by providing a apertures through the insulative layer is well within the relief range of a planar surface. The electrodes and the insulative and barrier layers can be of any convenient conventional composition. Both gold-zinc alloys and titanium nitride are typical electrode materials for forming ohmic contacts to III-V compound monocrystalline structures. Schottky barrier contacts are typically formed using gold or aluminum at the interface with a III-V compound monocrystalline structure. In one alternative form, instead of forming a Schottky barrier interface with the surface layer the gate electrode can be separated from the surface layer by an interposed portion of the insulative layer. In this instance the gate electrode materials can be chosen from among the same materials used to form the source and drain electrodes. The insulative barrier layer is entirely optional, since the device can be mounted in a hermetically sealed housing, if desired. When present, the barrier layer can take the form of a passivating layer, such as a borosilicate glass. The insulative layer can take the form of a chemically vapor deposited insulative material, such as silica or silicon nitride. Additional conductive and/or insulative layers, not shown, can overlie the barrier layer, depending upon the requirements of other, optional device components, not shown. While no elements other than those formed by the lasing region and the surface layer are required to be present in the device 100 and therefore are not shown, it is appreciated that the substrate portion adjacent the first major surface is particularly suited to the placement of additional, optional circuit components, if desired. The lasing region, lying entirely within the channel 110 formed by the substrate, has its lateral extent defined by the isolating portion of the substrate and its lower wall 112 defined by the more conductive portion of the substrate. Adjacent the lower channel wall the lasing region is shown comprised of a gallium arsenide lower capping layer 114, typically having an N type conductivity ion concentration of from 10¹⁷ to 5 X 10¹⁸ ions per cm³. Lying immediately above the lower capping layer is lower cladding layer 116 of N conductivity type. Lying above the lower cladding type is upper cladding layer 118 of P conductivity type. Each cladding layer can be comprised of aluminum arsenide or gallium aluminum arsenide containing up to 90 mole percent gallium. The cladding layers each typically have a conductivity imparting ion concentration of from 10¹⁶ to 10¹⁸ ions per cm³, but typically each contain somewhat lower conductivity imparting ion concentration than the capping layer with which it is in contact. Interposed between the upper and lower cladding layers is an active layer 120. The active layer normally contains a lower conductivity imparting ion concentration than either of the cladding layers it contacts. That is, the cladding layer normally contains less than 10¹⁸ conductivity imparting ions per cm³ and can be as nearly intrinsic as can be conveniently realized. Addtionally, the active layer contains less aluminum than either of the cladding layers and less aluminum that the isolating portion of the substrate. Capping layer 122 is in contact with the upper cladding layer. The upper capping layer is preferably comprised of gallium arsenide having a P type conductivity imparting ion concentration of greater than 10¹⁹ ions per cm³. Instead of being of N conductivity type as described the lower capping and cladding layers can alternatively be of P conductivity type with the upper capping and cladding layers in this instance being of N conductivity type. The upper surfaces of the upper capping and surface layers lie along the planar surface of the semiconductor device within a µm and typically within about 300 nm (3000 Å) of the plane of the first major surface of the substrate. As shown the first major surface of the substrate and the upper surfaces of the capping and surface layers are in their ideal coplanar relationship. To form the semiconductor device 100 acording to the process of the present invention a monocrystalline gallium arsenide wafer is provided having properties corresponding to those of the conductive portion 104 of the substrate. The wafer thickness is chosen to make efficient use of material while permitting manipulation during processing without damage. While in practice a plurality of identical semiconductive devices are formed in laterally offset relation on a single wafer, the description which follows is in terms of forming a single device, since the process steps are the same. Onto the wafer forming the more conductive portion 104 of the device substrate a monocrystalline layer is epitaxially grown forming the isolating portion 106 of the substrate. The isolating portion is typically grown to a thickness of from about 3 to 10 µm, optimally from about 4 to 8 µm. Formation of the substrate can be achieved by any convenient conventional means. Referring to Figure 2, to begin construction of the device a protective layer 140 is formed on the first major surface 124 of the isolating portion 106 of the substrate 102. The protective layer forming material can be selected from among a variety of known materials which are stable at required processing temperatures and which can be readily removed in at least selected areas. Examples of such materials are silica (SiO₂), silicon nitride (Si₃N₄), and refractory metals as well as their oxides and silicides-e.g., tungsten, tungsten oxide, and tungsten silicide. The layer need be no thicker than is required to assure pin hole free coverage of the first major surface and in any event is less than about 300 nm (3000 Å) in thickness, preferably from about 50-200 nm (500 to 2000 Å) in thickness. Initially the protective layer overlies the entire first major surface. To locate the lasing region in the substrate an opening 142 is first formed in the protective layer, and the substrate is then etched through the opening to form the channel 110. The opeining in the protective layer can be formed by conventional photomasking and etching steps. For example, the protective layer can be overcoated with a layer of a conventional photoresist, imagewise exposed, and developed to define an opening in the photoresist layer corresponding to the location of the opening in the protective layer desired. The protective layer can then be etched through the openings in the photomask to define the desired openings. A variety of suitable conventional etching techniques are known, as illustrated by the various etching techniques outlined in Sugishima et al U.S. Patent 4,352,724. After every material removal step, regardless of whether the material being removed is from the substrate itself or an associated conductive or insulative layer, it is conventional practice to follow up immediately with a washing step to assure maintenance of the high levels of cleanliness required for successful semiconductor device yields. Typically deionized water is used for washing. To avoid repetitive references to washing, it is to be understood that a washing step, though not specifically described, preferably follows each step calling for removal of any material, particularly any step calling for material removal by etching. Since the protective layer is comparatively thin, it is normally immaterial whether isotropic or anisotropic etching conditions are employed to form the opening. The same comment does not apply to forming the channel. The side walls of the channel are shown to be perpendicular to the first major surface of the substrate. However, alternative orientations are possible and can be employed to advantage. To appreciate the alternatives some appreciation of the substrate crystal structure is required. The Group III-V compounds which form the substrate and lasing regions all form essentially similar cubic crystal lattices of the zinc blende type, and their lattice constants are essentially similar-e.g., 5.63 Å for gallium arsenide and 5.66 Å for aluminum arsenide. The common crystalline class and the close similarity in lattice spacings facilitates epitaxial deposition of materials differing in the selection of aluminum or gallium as the Group III ions. As normally prepared the major surfaces of the substrate lie in {100} crystallographic planes. By employing known etching conditions the substrate can be etched essentially isotropically through the opening in the protective layer, with a certain amount of undercutting of the protective layer occurring. Alternatively, anisotropic etching can be achieved which reduces undercutting of the protective layer. Under anisotropic etching conditions the lateral walls of the channel are defined by the more thermodynamically stable crystallographic planes of the crystal structure. The {111} crystallographic planes are the most stable and can be revealed selectively by anisotropic etching to form the side walls of the channel. Any conventional anisotropic etchant can be employed. One preferred anisotropic etchant capable of efficiently revealing {111} channel side walls is a 5:1:1 volume ratio mixture of H₂O:H₂SO₄:H₂O₂. Another suitable anisotropic etchant is a 2 percent by weight bromine dissolved in methanol. The {111} crystallographic planes intersect {100} crystallographic planes at a 55° angle. Two entirely different {111} crystallographic plane channel side wall orientations are possible, as can be appreciated by reference to Figures 3A, 3B, and 4. Figure 4 is an isometric detail showing two possible alternative, mutually perpendicular channel orientations. Each of the channels 110a and 110b to be formed by etching is aligned with one of two mutually perpendicular sets of <110> vectors lying in the {100} first major surface of the substrate. Figure 3A illustrates the channel side walls which result when the channel longitudinal axis is oriented parallel to one set of <110> vectors on the {100} crystallographic plane forming the first major surface while Figure 3B illustrates the channel side walls which result when the channel longitudinal axis is oriented parallel to a second set of <110> vectors on the {100} crystallographic plane forming the first major surface, where the two sets of <110> vectors are mutually perpendicular. The direction of <110> vectors on a {100} crystal surface can be determined by light diffraction patterns on the crystal surface, as is well understood. However, discrimination between the two sets of <110> vectors for purposes of choosing the side wall orientation of the channel created by etching requires a trial etching step in an expendable area of the substrate wafer being processed. In Figure 3A a structure is shown similar to the right hand portion of Figure 2, with like elements assigned like reference numbers. The difference in the Figure 3A structure is the configuration of the channel 110a. In this structure the channel is formed by two opposed side walls 144a and 144b and a bottom wall 144c. The bottom wall is shown lying along the interface of the substrate portions 104 and 106-i.e., in a {100} crystallographic plane. The side walls diverge linearly from the protective layer opening toward the substrate portion 104 and then curve back to join the bottom wall. The linear portion of each side wall lies in a different {111} crystallographic plane. Dashed line 146 shows the lower boundary of the channel at an intermediate stage of etching. From observing channel boundaries at intermediate stages of etching the manner in which the more thermodynamically stable {111} crystallographic planes define the channel side walls can be appreciated. The regions 148a and 148b, each defined by extrapolations of the laterial wall limiting {111} crystallographic plane and bottom wall defining {100} crystallographic plane, are not normally removed by etching, but should be removable if the rate of etching along the bottom wall is slowed, as by introducing an etch resistant layer in the substrate during its formation. However, the rounding of the channel side walls at their intersection with the bottom wall is advantageous in that the necessity of epitaxy at the areally constricted oblique intersections of the {111} and {100} planes is avoided, thereby facilitating epitaxy on all channel walls. In Figure 3B a somewhat broader opening 142a is shown, since the side walls 150a and 150b of the channel 110b converge toward the channel bottom wall 152. Dashed line 154 represents the bottom wall at an intermediate stage of etching. It is to be noted that in this instance side walls entirely conform to {111} crystallographic planes and that the angles of intersection of the side walls and the bottom wall are obtuse, which facilitates epitaxial deposition at the intersections of the {100} and {111} crystallographic planes. Since by definition a <110> crystallographic vector is oriented perpendicular to {110} planes, it follows that there are two sets of mutually perpendicular {110} crystallographic planes each intersecting the first major surface of the substrate at right angles. For example, in Figure 4, two near edges of substrate are visible. Each near edge lies in a {110} crystallographic plane. Referring back to Figures 1 and 2 it is therefore apparent that the side walls of the channel 110 can be oriented to lie in {110} crystallographic planes. By a suitable etchant choice it should be possible to form a channel with side walls lying in {110} crystallographic planes and a bottom wall lying in a {100} crystallographic plane. In this regard it is to be noted that the substrate surfaces formed by {110} crystallographic planes are more thermodynamically stable during etching than the surfaces formed by {100} crystallographic planes. Thus, etching would be expected to proceed anisotropically, deepening the channel bottom wall while exhibiting little undercutting of the protective layer. Once a channel has been formed in the substrate of the desired configuration and depth, the next step is to deposit epitaxially III-V compound selectively in the channel formed so that deposition occurs only in the channel and not on the protective layer. To achieve this goal of selective site deposition of the III-V compound care must be undertaken in the choice of deposition conditions. A preferred procedure for depositing III-V compound only on the unprotected or exposed surfaces of the substrate lying in the channel employs selected conditions of organometallic vapor phase epitaxy. The substrate in any one of the forms shown in Figures 2, 3A, or 3B is placed in a vacuum chamber where it is heated to a temperature in the range of from 500 to 800°C, preferably in the range of from 650 to 750°C. The pressure in the vacuum chamber is reduced to less than 6666 Pascal (50 torr), preferably less than 1333 Pascal (10 torr). At the same time an atmosphere is provided in the vacuum chamber comprised of arsine (AsH₃) and one or a mixture of organo-aluminum and organo-gallium gases-e.g., trimethyl or triethyl aluminum or gallium. The alluminum and gallium ratio are dictated by the ratio of these metals desired in the epitaxy being deposited on the substrate. A molar excess of the arsine gas is maintained. A molar ratio of vapor phase arsine to total vapor phase aluminum and gallium of from about 2:1 to 100:1 is maintained. Deposition is continued until the epitaxy deposited in the channel forms with the first major surface of the substrate an overall planar surface-e.g., until the surface of the eiptaxy in the lasing region lies within about a µm of the first major surface of the substrate, preferably within about 300 nm (3000 Å) of the first major surface. To provide the III-V compound being deposited in the waveguide region with the desired concentration of N or P conductivity type ions one or more N or P dopant materials are introduced along with the other gases. N type dopants, such as silicon, selenium, sulfur, tellurium, tin, and germanium, can be introduced as vapor phase compounds, such as silane, hydrogen selenide, germanium hydride, dialkyl telluride, or tetraalkyl tin while P type dopants, such zinc, cadmium, beryllium, and magnesium, can be introduced as the corresponding dialkyl compounds, where alkyl in each instance is independently methyl or ethyl. Except for the particular vacuum chamber conditions noted, doping procedures can generally follow the conventional practices of the art. In depositing III-V compounds in the channel to form the various lasing region layers different crystal faces bounding the channel can affect the relative rates of epitaxial deposition. There appears to be a preference for deposition onto {111}, {100}. and {110} in that order of preference. Thus, exposed {111} crystal faces appear to accept epitaxy at a somewhat higher rate than the remaining crystal faces. In epitaxially depositing into channels bounded by {111} side walls, as shown in Figures 3A and 3B, this can result in some bonding of the layers at their edges. Edge contouring of the various epitaxial layers can be employed to advantage, if desired. Even where edge contouring of the successive epitaxially deposited layers is observed, the contouring effect is not incompatible with obtaining the desired final planar surface configuration. Since contouring results from interaction with the substrate channel walls, once epitaxy covers these walls, the successive deposition favors restoring planarity to the upper surface of the epitaxy. Edge contours of lasing region layers can be minimized by maintaining the channel depth small in relation to its width. Where the channel is initially bounded by side walls lying in {110} crystallographic planes, the slower deposition onto walls of this crystallographic orientation favors the deposition of flat layers essentially free of edge contours, as shown in Figure 1. According to the preferred practice of the invention the lasing region epitaxy is grown just to or slightly below the first major surface of the substrate to form a planar surface extension of the first major surface-i.e., a surface that lies within about a µm and preferably within about 300 nm (3000 Å) of the first major surface. Continued growth of the epitaxy within the ordinary relief tolerances of planar surfaces can be preformed, but is preferably avoided. Epitaxial deposition in the lasing region above the channel results in edge bounding of the epitaxy by {111} crystallographic planes. Since such planes are canted at 55° with respect to the first major surface of the substrate, this produces an overhang that creates disadvantages in further processing to produce a completed device. The surface layer 222 can be formed by selective site epitaxial deposition employing a variation of the process described above for forming the lasing region. In one illustrative form, once the III-V compound layers of the lasing region have been deposited, the next objective is to prevent further III-V compound epitaxy at this location while forming the surface layer. This can be achieved merely by closing the opening 142 with additional material of the type used to form the protective layer 140. This can be done locally over the first lasing region or uniformly over the entire upper surface of the device. It is preferred first to remove the entire protective layer 140 and then, as shown in Figure 5, to form a second protective layer 156 over the entire first major surface 124 of the substrate and the capping layer of the lasing regionl. Thereafter opening 158 and channel 210 are formed similarly as described above with reference to opening 142 and channel 110, with the notable difference that the channel 210 will normally be much shallower than the channel 110. The channel 210 typically has a depth no greater than the thickness of cladding layer 118 and capping layer 122. The surface layer 222 can then be epitaxially grown selectively in the channel 210. Once the lasing region and surface layers have been completed, subsequent processing to produce a completed device can be undertaken by well known conventional techniques. The protective layer or layers used for directing epitaxy, if both are still present, can remain as permanent layers of the completed device or can be removed and replaced by an insulative layer, such as layer 130 in Figure 1. Alternatively, the insulative and protective layers can be used together. It is to be noted that the insulative layer 130 as shown in Figure 1 covers portions of the lasing region to limit the lateral contact of the second electrode with the lasing region. This arrangement can be used to advantage to combine gain guiding with positive index guiding. The substrate containing the lasing region intended to form the semiconductor device is typically cleaved from a wafer of which it forms a part during fabrication so that two parallel smooth mirror edges intersect the channels containing the lasing regions. These mirror edges interact with the lasing regions to increase the emission efficiency of the completed device. While the invention has been described with reference to certain preferred embodiments, it is appreciated that numerous modifications can be undertaken, the relative merits of which will depend upon the specific user application being addressed. For example, it is not necessary that the lasing region contains five separate layers as shown in Figure 1. The capping layer 114, for example, can be omitted. It is also possible to form laser regions with superimposed active layers separated by one or more intervening cladding layers. Although only one lasing region has been described, it is appreciated that a single substrate can contain any number of separate lasing regions, since the process of the present invention by offering the capability of selective site epitaxy allows each lasing region to be fabricated independently of other lasing regions which have been or may subsequently be formed. Semiconductive devices with from 2 to 10 different lasing regions are specifically contemplated. The substrate 102 has been shown to be comprised of both conductive portion 104 and isolating portion 106; however, only the isolating portion is essential. Thus, a unitary substrate can be formed in which a wafer having the composition of the isolating portion is provided and etched to form channels therein without any intervening step of epitaxially deposition of additional III-V compound thereon. While a field effect transistor has been described as a specific illustration of a device which can be formed with the surface layer, it is appreciated that the surface layer can be used to form other useful integrated circuit components, if desired. For example, the surface layer can be used to introduce a controlled resistance connecting the second and third electrodes. By bringing the second and third electrodes into close lateral spacing on the surface layer a capacitor can be formed. In another variant form both the gate and third electrodes can be eliminated and the second electrode extended over the entire width of the surface layer. In this arrangement the surface layer can form a storage stage of charge coupled device. It is also possible to omit the third and gate electrodes and to terminate the second electrode short of the surface layer and in contact with the surface layer. In this instance the surface layer can function to complete a photodiode. Thus other useful integrated components can be completed by the surface, if desired.

Claims: A process comprising (i) providing a monocrystalline substrate (102) having a major surface (124), epitaxially growing on said substrate a laterally restricted lasing region (108) comprising superimposed P and N conductivity type cladding layers (116, 118), an active layer (120) therebetween, and a capping layer (122) adjacent said major surface having greater than 10¹⁹ conductivity imparting ions per cm³, (ii) laterally offset from said lasing region providing on said substrate a semiconductive surface layer (222) having a conductivity imparting ion concentration less that that of said capping layer, for the intergration of another circuit component, said substrate and said layers together forming a monocrystalline III-V compound structure, wherein the group V ions are arsenic and the group III ions are at least one of gallium and aluminum, and (iii) providing conductive means (134) at said compound structure surface for providing a conduction path between said surface layer and said capping layer, characterized in that (a) said substrate adjacent said major surface (124) intended to separate said lasing region (108) and said surface layer (222) is formed of monocrystalline gallium aluminum arsenide (106) having a resistivity greater than 10⁵ ohm-cm and (b) said capping layer (122), said surface layer, and said separating substrate surface are formed to present a planar surface by the steps including (c) providing on said major surface a protective layer (140) defining an opening (142), (d) through the opening creating a channel (110) in said substrate to expose an unprotected portion of said substrate beneath said major surface, (e) epitaxially depositing said laser region layers on only said unprotected substrate portion, at least said active layer being comprised of gallium arsenide or gallium aluminum arsenide of a higher refractive index than said substrate monocrystalline gallium aluminum arsenide (106), (f) terminating epitaxial deposition when said lasing region forms with said major surface an overall planar surface, (g) forming said surface layer to present a planar surface with said substrate at a location laterally offset from said lasing region, and (h) depositing on said planar surface at least one conductive means (134) providing a conduction path between said surface layer and said capping layer. A process according to claim 1 wherein said substrate (102) includes a more conductive portion (104) spaced from said major surface (124) and said channel (110) extending into said substrate to said more conductive portion. A process according to claim 1 or 2 in which said substrate presents a {100} crystal face and a longitudinal axis of said channel is formed along a <110> vector. A process according to claim 3 in which at least one of the channels is formed with side walls lying in {111} crystal planes. A process according to claim 4 in which said {111} side walls diverge in a direction away from said substrate surface. A process according to claim 4 in which said {111} side walls converge in a direction away from said substrate surface. A process according to any one of claims 1 through 6 in which gallium arsenide or gallium aluminum arsenide is selectively deposited in each of the channels by a vapor phase double decomposition reaction of arsenic, gallium, and, optionally, aluminum compounds at a temperature of from 500 to 800°C from an atmosphere of less than 6666 Pascal (50 torr). A process according to claim 7 in which epitaxial deposition is undertaken at a pressure of less than 1333 Pascal (10 torr). A process according to claim 7 in which epitaxial deposition is undertaken at a temperature of from 650 to 750°C. A process according to any one of claims 1 through 9 in which gallium arsenide or gallium aluminum arsenide is selectively deposited epitaxially in said channel by a vapor phase double decomposition reaction of arsenine and at least one of trialkyl gallium and trialkyl aluminum, where alkyl is independently methyl or ethyl. A process according to any one of claims 1 through 10 in which said substrate adjacent said one major surface exhibits a resistivity of greater than 10⁷ ohm-cm. A process according to any one of claims 1 through 11 in which said lasing region is comprised of N and P conductivity type cladding regions of aluminum arsenide or gallium aluminum arsenide containing from 10¹⁶ to 10¹⁸ conductivity imparting ions per cm³ and an intervening active layer of gallium arsenide or gallium aluminum arsenide containing less aluminum than either of said cladding regions and less aluminum than at least that portion of said substrate contiguous therewith. A process according to any one of claims 1 through 12 in which at least one protective layer is formed of silica or silicon nitride. A process according to any one of claims 1 through 13 in which epitaxial deposition of said lasing region is terminated within less than a micrometer of said major surface of the substrate. A process according to claim 14 in which epitaxial deposition of said lasing regions is terminated within less than 300 nm (3000 Å) of said major surface of said substrate. A process according to any one of claims 1 through 15 in which said surface layer is formed of a conductivity type opposite that of said substrate, thereby forming a junction therewith. a process according to claim 16 in which a Schottky barrier layer is deposited on said surface layer. A process according to any one claims 1 through 16 in which said surface layer is provided with source, drain, and gate electrode to form a field effect transistor. A semiconductor device comprised of a substrate (102) having a major surface (124), a laterally restricted lasing region (108) comprising superimposed P and N conductivity type cladding layers (116, 118), an active layer (120) therebetween, and a capping layer (122) adjacent said major surface having greater than 10¹⁹ conductivity imparting ions per cm³, a semiconductor surface layer (222) laterally offset from said lasing region having a conductivity imparting ion concentation less than that of said capping layer, for the intergration of another circuit component, said substrate and said layers together forming a monocrystalline III-V compound structure, wherein the group V ions are arsenic and the group III ions are at least one of gallium and aluminum, and conductive means (134) at said compound structure surface for providing a conduction path between said surface layer and said capping layer, characterized in that said substrate (102) forms with said capping layer (122) and said surface layer (222) a planar surface of said monocrystalline III-V compound structure, said conductive means (134) is located on said planar surface, and said substrate comprises monocrystalline gallium aluminum arsenide (106) of a single conductivity type having a resistivity of greater than 10⁵ ohm-cm isolating said surface layer (222) from said lasing region (108) and providing positive index wave guiding at its interface with said active layer (120). A semiconductor device according to claim 19 wherein said substrate (102) includes a more conductive portion (104) spaced from said major surface (124) and said lasing region (108) extends into said substrate to said more conductive portion. A semiconductor device according to claim 19 or 20 in which said substrate presents a {100} crystal face and a longitudinal axis of each channel is formed along a <110> vector. A semiconductor device according to claim 21 in which said lasing region has side walls which intersect said {100} crystal face at a 55° angle. A semiconductor device according to claim 22 in which said side walls diverge in a direction away from said {100} crystal face. A semiconductor device according to claim 22 in which said side walls converge in a direction away from said {100} crystal face. A semiconductor device according to any one of claims 19 through 24 in which a portion of said substrate separating said lasing region and said surface layer exhibits a resistivity of greater than 10⁷ ohm-cm. A semiconductor device according to any one of claims 19 through 25 in which said lasing region is comprised of N and P conductivity type cladding regions of aluminum arsenide or gallium aluminum arsenide containing from 10¹⁶ to 10¹⁸ conductivity imparting ions per cm³ and an intervening active layer of gallium arsenide or gallium aluminum arsenide containing less aluminum than either of said cladding regions and less aluminum than contiguous portions of said substrate. A semiconductor device according to any one of claims 19 through 16 in said III-V compound structure exhibits surface relief of less than 1 µm. A semiconductor device according to any one of laims 19 through 26 in which said III-V compound structure exhibits surface relief of less than 300 nm (3000 Å). A semiconductor device according to claim 19 wherein said substrate includes a first portion having a conductivity imparting ion concentration of from 1 to 3 X 10¹⁸ ions per cm³ and a second, epitaxially grown isolating portion comprised of gallium aluminum arsenide containing from 30 to 60 mole percent aluminum having a resistivity of greater than 10⁷ ohm-cm, said isolating substrate portion forming one major surface of the substrate, and said lasing region includes in sequence a first gallium arsenide layer having a first conductive type ion concentration of from 10¹⁷ to 5 X 10¹⁸ ions per cm³, a first cladding layer comprised of aluminum arsenide or gallium aluminum arsenide containing at least 90 mole percent aluminum having a first conductivity type ion concentration of from 10¹⁶ to 10¹⁸ ions per cm³, an active layer comprised of gallium arsenide having a substantially lower conductivity imparting ion concentration than the first cladding layer, a second cladding layer comprised of aluminum arsenide or gallium aluminum arsenide containing at least 90 mole percent aluminum having a second conductivity type ion concentration of from 10¹⁶ to 10¹⁸ ions per cm³, and a surface gallium arsenide layer having a second conductivity type ion concentration of greater than 10¹⁹ ions per cm³, said surface gallium arsenide layer lying at or beneath said major surface by a distance of less than 300 nm (3000 Å) to form a planar surface therewith. A semiconductor according to claim 29 in which said surface layer has a dopant concentration in the range of from from 10¹⁴ to 10¹⁷ ions per cm³.

Inventors: SMITH, FRANK THOMAS JOHN EASTMAN KODAK COMPANY
Applicants: EASTMAN KODAK COMPANY (A NEW JERSEY CORPORATION)
Application year: 1987
Main classification: H01S3
IPC codes: H01L27, H01S5