Method of and apparatus for processing data

Abstract: A data processor of this invention specifies (16, 17) either of a predetermined maximum length of an address (a bits) and the length of an address less than the former length and at least one register (7) having the number or length of bits of the maximum address length or greater (r bits). The data pro­ cessor reads out lower-order d bits of said at least one regi­ ster (7) specified by a first instruction to perform arithmetic operations, and writes the arithmetic result into a register element contained in said at least one register (7). Moreover, the processor reads out bits from a register element con­ tained in said at least one register (7) specified in a second instruction to generate an a-bit address, and reads out d bits from a storage device (5) in response to the thus-generated address to write the d bits into either the storage device (5) or said register element. Accordingly, since the data length is consistently d bits irrespective of specified effective length of an address, direct data transfer is enabled between programs each having a different effective length of an address. Facilitating extension of the length of a storage address and assuring compatibility with conventional data processor.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates generally to data processing which is performed using a large-capacity main storage device and, more particularly, to a method of and an apparatus for effecting data processing both of which are suitable for the extension of the length of a storage address with assuring compatibility with a conventional type of data processor. DESCRIPTION OF THE PRIOR ART A typical technique of extending the length of main storage addresses used in a data processor is discussed in a manual provided by IBM, "IBM System/ 370, Extended Architecture Principles of Operation (1983), pp. 5-4 to 5-10 and pp. 7-1 to 7-8". This prior art adopts a so-called virtual storage system which includes two kinds of mode of address length, i.e., 24-bit and 31-bit modes and in which fixed point data and logic data have a data length of 32 bits. Each of general registers employed has a length of 32 bits, and data arithmetic or logic instructions such as addition and subtraction are prepared for the entire 32 bits of each of the general registers. However, since no arithmetic instruction dedicated to the handling of addresses is prepared, arithmetic operations on the addresses are performed by means of the data arithmetic or logic instructions. During the execution of the data arithmetic or logic instructions, the entire 32 bits of any of the general registers is read out, and arithmetic or logic operations are performed on 32-bit data. The 32-bit result of the arithmetic operations is written into the general registers. An instruction for accessing a main storage containing an operand specifies two general- registers serving as a base register and an index register, respectively, both of which are used in generating the address of an operand in accordance with a corresponding instruction code. A virtual address for main-storage access is generated by adding the contents of the base register and the index register to displacement in the instruction code concerned. In this case, if the length of the result of addition exceeds the length of the virtual address, the excessive higher-order portion of the result is ignored. Therefore, such addition is commonly performed by reading out only the number of bits equivalent to the length of the virtual address from the base and index registers in accordance with the mode of the virtual address length. More specifically, higher-order 24 bits upward from the least significant bit of the general register is read out in a 24-bit mode, and, in a 31-bit mode, the read out of higher-order 31 upward from the least significant bit is effected. A load instruction serving as one of the main-storage access instructions specifies the action of reading 32-bit data out of the main storage specified by the thus-generated address irrespective of the mode of the virtual address length, such read out data being written into the entire 32-bit general register. The virtual address length mode is specified by a 1-bit mode in a register holding a program status word indicating the status of various conditions in the processor. The mode bit can be changed by a mode change/branch instruction. The virtual address length mode is changed by changing the mode bit. As described above, however, the prior art takes no account of the case where the length of an address is extended so greatly that the extended length of the address exceeds the length of data which is not extended, that is, the number of bits or length of a bit string of the general register. In such a case, if the prior art is used, it is required to extend the data length to a size equal to or greater than the extended length of the address so as to use data arithmetic or logic instructions for the purpose of executing arithmetic or logic operations on the extended data length. However, extension of the data length would make it difficult to perform data transfer between an old program formulated before the data extension and a new program formulated after the same. For instance, if the non-extended length of data is 32 bits in the old program and the extended length of data in the new program is 64 bits, the 32-bit data must be converted to the 64-bit data so as to enable data transfer from the old program to the new program. This leads to a problem in that the extension of data length makes is difficult to assure compatibility between various data processors. Another technique of extending length of main storage addresses is shown in Japanese published laid-open patent application (Kokai tokkyo koho) 54-95129, wherein a data processor includes a circuit for generating an extended length address of 32 bits by use of general purpose registers of 32 bits so as to enable execution of instructions prepared for a main storage which is accessible by 24 bits addresses. In this prior art it is controlled that an extended-length address includes significant 24 bits at its lower bit portion and 8 bits of all zero at its upper bit portion, when the extended-length address is to be used to fetch an instruction from a main storage. Thus, this prior art enables the data processor to use already made control programs (operating system program) with less change. In this prior art, however, length of data fetched from or stored into the main storage is presumed to be 32 bits. That is, the extended address does not still exceed the data length. Therefore, this prior art has the same problem as mentioned above regarding the previously mentioned prior art. A data processor with the features included in the first part of claim 1 is known from "Introduction To The 80386", INTEL, April 1986, pages 4-1, 4-2, 7, 8, 14, 15, 17 to 19, 31, 32 and 55. The known processor is capable of operating in different modes of operation with different bit lengths. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processor and a data processing method which enable efficient extension of main storage addresses while assuring compatability with conventional types of data processors. This object is achieved by the processor defined in claim 1 and the processing method defined in claim 14. The present processor comprises means for specifying either a predetermined maximum address length ( a bits) or an address length less than the maximum, and at least one register having maximum address length ( r bits), in which lower-order d bits in the at least one register specified by a first instruction is read out to perform arithmetic or logic instructions, the result of such arithmetic or logic instructions being written into a register element contained in the at least one register and in which the number of bits equivalent to a specified effective length is read out of a register element contained in the at least one register specified by a second instruction to generate an a -bit address, d bits being thus read out in response to the thus-generated address to be written into either of a register element contained in the at least one register thus specified and the storage device. In this arrangement, data is loaded and stored by d -bit access means, and this enables direct transfer of data between a plurality of programs each having a different effective length of the address of an operand. It is therefore easy to assure compatibility with conventional types of data processor. Also, the number or length of bits equivalent to the effective length of an address is read out of the r -bit general register in accordance with the effective length of the address, thereby enabling extension of the length of the address of the main storage in excess of the d bits. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the construction of a preferred embodiment of the present invention; Fig. 2 is a block diagram showing the construction of a 64-bit address arithmetic circuit incorporated in the embodiment; Fig. 3 is a block diagram showing the construction of a 32-bit address arithmetic circuit incorporated in the embodiment; Fig. 4 is a block diagram showing the construction of an address generating circuit incorporated in the embodiment; Fig. 5 is an illustration of the arrangement of an RX instruction format used in the embodiment; Fig. 6 is an illustration of the arrangement of an R instruction format used in the embodiment; Fig. 7 is a table showing the operations of a selector associated with an address generating circuit; Fig. 8 is a table showing the operations of a selector associated with the result of arithmetic or logic operations; and Fig. 9 illustrates a virtual storage region used in the address mode of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment and its modified forms of the present invention will be described below with reference to Figs. 1 to 9. The presently preferred embodiment adopts a virtual storage system and has three kinds of mode such as 24 bit-, 31 bit- and 48 bit-modes as the modes of a virtual address length (hereinafter referred to as "address mode"). Therefore, the effective length of an operand address are changed to 24 bits, 31 bits or 48 bits in accordance with the respective modes. Fig. 9 shows virtual address regions which are accessible in the respective modes. When the 24-bit mode is selected, a region 201 corresponding to virtual addresses 0 to 2²⁴-1 is accessible. Similarly, the 31-bit mode allows for access to a region 202 corresponding to virtual addresses 0 to 2³¹-1 and the 48-bit mode allows for access to a region 203 corresponding to virtual addresses 0 to 2⁴⁸-1. The data length is consistently 32 bits irrespective of any of the address modes. Fig. 1 shows the construction of the preferred embodiment in block form. The illustrated embodiment is formed including an instruction register 1 for holding therein an instruction code to be executed, an instruction decoder 2, a program status word (PSW) 3, a flip-flop V18 for controlling the number or length of bits to be handled by arithmetic operations upon an address, an address generating circuit 4 for generating the real address of an operand in response to an instruction code, a main storage device 5, a fetch data register 6, sixteen 64-bit general registers 7, 64-bit address arithmetic circuit 8, a 32-bit data arithmetic circuit 9, a register 10, selectors 11, 20, 21, an AND gate 14 and an OR gate 13. Fig. 2 is a block diagram of the construction of the 64-bit address arithmetic circuit 8. The 64-bit address arithmetic circuit 8 includes a 64-bit binary fixed point arithmetic circuit 51, a 64-bit logic arithmetic circuit 52 and selectors 53, 54. Fig. 3 is a block diagram of the construction of the 32-bit data arithmetic circuit 9. The 32-bit data arithmetic circuit 9 includes a 32-bit binary fixed point arithmetic circuit 61, a 32-bit logic arithmetic circuit 62, a 32-bit decimal arithmetic circuit 63 and selectors 64, 65. Fig. 4 is a block diagram of the construction of the address generating circuit 4. The address generating circuit 4 includes a 48-bit three-input adder 71, a 31-bit three-input adders 72, a 24-bit three-input adder 73, registers 74, 75 and 76 for holding therein the results of addition, a selector 77, an address converter circuit 78 for converting a virtual address to a real address and a real address register 79 for holding therein the thus-obtained real address. Fig. 5 shows an RX instruction format 96 which is a main storage access instruction format used in the data processor constituting the preferred embodiment. The RX instruction format 96 is formed having an operation code ( OP ) 97, an R field 98 for the register number of a first operand, an X field 99 for the index register number of a second operand, a B field 100 for the base register number of the second operand and a D field 101 for the displacement of the second operand. Fig. 6 shows an RR instruction format 102 which is the format of arithmetic or logic instructions. The RR instruction format 102 is formed including an operation code ( OP ) 103, an R1 field 104 for the register number of the first operand and an R2 field 105 for the register number of the second operand. The program status word 3 includes bits A1 16 and A2 17 assigned to the control of the address modes. When the bits Al 16 and A2 17 are set to "0, 0", the 24-bit mode is selected. Similarly, "1, 0" corresponds to the 31-bit mode and "0, 1" or "1, 1" corresponds to the 48-bit mode. When the filp-flop V18 is set to "0", the number of bits of the address arithmetic instruction and the main storage access instruction the access target of which is an address is consistently 64 bits irrespective of the address modes. When the flip-flop V18 is set to "1", the length of a target bit is 32 bits in either the 24-bit mode or the 31-bit mode and 64 bits in the 48-bit mode. The operation of the preferred embodiment will be described below. First, reference is made to various instructions used in the data processor constituting the preferred embodiment. The presently preferred embodiment utilizes address arithmetic instructions used in performing arithmetic or logic operations as between the general registers, data arithmetic instrutions used in performing arithmetic or logic operations as between the general registers and the main storage access instructions used in performing data transfer between the main storage device and the general registers. The address arithmetic instructions have the RR instruction format 102, and an example of such instruction is an unsigned binary fixed point adding instruction (ADDA instruction). The data arithmetic instructions have the RR instruction format 102 and an example of such instructions is a signed binary fixed point adding instruction (ADD instruction). The main storage access instructions have the RX instruction format 96 and examples of such instructions are a data load instruction (L instructions) the access target of which is data, a data store instruction (ST instruction), an address load instruction (LA instruction) the access target of which is an address and an address store instruction (STA instruction). The following description refers to the operation of the embodiment during the execution of the main storage access instructions. When execution of the main storage access instructions is commenced, corresponding instruction codes are stored in the instruction register 1. The instruction decoder 2 decodes the operation code 97 of the main storage access instruction having the RX instruction format 96 from the instruction register 1, and provides the decoded operation code 97 to a signal line OC36. Simultaneously, in order to indicate the main storage access instructions, a signal line MA 45 is set to "1", and, in the case of instructions such as the L instruction and the ST instruction the access target of which is data, a signal line AI 39 is set to "0" while, in the case of instructions such as the LA instruction and the STA instruction the access target of which is an address, the signal line AI 39 is set to "1". The address generating circuit 4 adds the value of the D field 101 to two register elements (hereinafter referred to as "index register" and "base register", respectively) specified by the X field 99 and the B field 100 based on the RX instruction format 96 in the instruction register 1, thereby generating the address of an operand. In such addition, any one of the results of addition performed in the adders 71, 72 and 73 each having a different number of bits is selected via a signal line AM 37 as shown in Fig. 7. More specifically, when the signal line AM 37 is "0, 0" to indicate the 24-bit mode, lower-order 24 bits are read out of the two registers 7 assigned to the index and base registers, and the 24 bits are added to the value of the 12-bit D field 101 by the 24-bit adder 73. The result of such addition is supplemented with higher-order "0"s, stored in the 48-bit register 76, selected by the selector 77, and then supplied to the address converter circuit 78. When the signal line AM 37 is "1, 0" to indicate the 31-bit mode, lower-order 31 bits are read out of the general register 7, and are then subjected to similar addition by the 31-bit adder 72. The result of such addition is likewise selected by the selector 77. When the signal line AM 37 is "0, 1" or "1, 1" to indicate the 48-bit mode, lower-order 48 bits are read out of the general register 7 and are then subjected to similar addition by the 48-bit adder 71. The result of such addition is likewise selected by the selector 77. The result of such addition selected by the selector 77, that is, an operand address which is a virtual address is converted to a real address by the address converter circuit 78, which delivers the real address to the real address register 79. Subsequently, in the case of load instructions such as an L instruction and an LA instruction, the main storage device delivers to the fetch data register 6 the contents of the main storage corresponding to the real address in the real adddress register 79. When the signal line LS 46 is "1", the length of fetch data is 64 bits and higher 32 bits and lower 32 bits of fetched data are selected by the selector 21 and are written into the fetch data register 6 via the lines 83 and 84 respectively, when it is "0", the length is 32 bits and 32 bit fetched data are selected by the selector 21 and are written into the fetch data register 6 via the line 84. The contents of the fetch data register 6 is passed through either the 64-bit address arithmetic circuit 8 of or the 32-bit data arithmetic circuit 9, and is written into the general register 7 specified by the R field 98 based on the RX instruction format 96. In this case, 32-bit data is combined with "0"s equivalent to higher-order 32 bits in the register 10, and the thus-obtained 64-bit data is written into the general register 7. Similarly, in the case of the ST and STA instructions, data and addresses are written from the general register 7 to the main storage device 7 through the selectors 11 and 21. The selector 21 selects both the higher 32 bits and lower 32 bits of the data on line 80 when the signal LS is "1", selects only the lower 32 bits of the data on line 80 when the signal LS is "0" and provides the selected data to the main storage device 5. The main storage device 5 is constructed so as to perform a read or write operation with respect to 64 bit data when the signal LS is "1" and with respect to 32 bit data when the signal LS is "0". The signal line LS 46 is a line indicating whether a target to be handled is 32-bit data or a 64-bit address. As shown in Fig. 8, the value of the signal line LS 46 is determined via gates 13 and 14 in accordance with the state of the bits of the program status word 3. The following description refers to the operation of the presently preferred embodiment during execution of the data arithmetic instructions and the address arithmetic instructions. When the execution of any of these instructions is commenced, corresponding instruction codes are read into the instruction register 1. The instruction decoder 2 decodes the operation code 103 based on the RR instruction format 102 which code is delivered from the instruction register 1, and provides the thus-decoded operation code 103 to the signal line OC 36. Also, in order to indicate that such instructions are not the main storage access instructions, the signal line MA 45 is set to "0", and the signal line AI is set to "1" in the case of the address arithmetic instructions and to "0" in the case of the data arithmetic instructions. The 32-bit data arithmetic circuit 9 reads out lower-order 32 bits from the two general registers 7 specified by the R1 field 104 and the R2 field 105, respectively, and performs arithmetic operations specified via the signal line OC 36. The result of such arithmetic operations is combined with "0"s as high-order 32 bits by the register 10. The 64-bit address arithmetic circuit 8 reads out the entire 64 bits of the two registers specified by the R1 field 104 and the R2 field 105 both of which are based on the RR instruction format 102, and performs arithmetic operations specified via the signal line CC 36. If the signal line LS 46 is "1", the selector 11 writes the output of the 64-bit address arithmetic circuit 8 to the general registers 7. If the signal line LS 46 is "0", the selector 11 writes the output of the register 10 to the general registers 7. The state of the mode bits 16 and 17 of the program status word 3 is changed by executing branch instructions used in saving an old mode bit and setting a new mode bit. Also, the state of the flip-flop VI8 is changed using a dedicated read out instruction and a write operation. These instructions are not essential to the present invention, and thus the detailed description is omitted. In the above-described embodiment, when data is to be written to the general registers, the higher-order bits of the general registers upward from the length of the data are set to "0"s. Therefore, when address transfer is needed between an old program in which the length of an address is not extended and a new program in which the length of an address is extended, the result of data arithmetic operations performed in the old program can be used as an address in th new program. This facilitates assurance of compatibility with a conventional type of data processor. In addition, arithmetic operations can be performed upon an address having the number or length of bits exceeding the data length. This enables high-speed arithmetic operations on an address as compared with a conventional method in which an address is divided into higher-order and lower-order portions to perform data arithmetic operations two times. Moreover, the length of a bit string of the general registers greater than data length can be loaded and stored between the main storage device and the general registers. This enables high-speed loading and storing of address data as compared with a conventional method in which address data is divided into higher-order and lower-order portions to execute data load and data store two times. Furthermore, if the length of an address upon which arithmetic operations should be performed and the length of address data which should be loaded and stored are fixed irrespectively of the address modes, it is possible to perform arithmetic operations upon, loading and storing of an address of length greater than the length of data in a program running in an address mode handling address length less than data length. This enables transfer of an address of length greater than data length between different address modes, one handling address length equal to or less than data length and the other handling address length less than data length. Therefore, compatibility between different modes can be easily assured. In addition, if the length of an address upon which arithmetic operations should be performed and the length of an address which should be loaded and stored are changed in accordance with the address mode, it is not necessary to perform airthmetic operations upon an address of length less than data length by means of address arithmetic means having the number of bits exceeding the data length. It is unnecessary to store nor load such address by main storage access means having the number of bits exceeding the data length. This enables high-speed arithmetic operations upon an address and high-speed loading and storage thereof. In another form of the embodiment of the present invention, the address generating circuit 4 in the above-described embodiment may be constituted by a single 48-bit adder, and lower-order 24 and 31 bits of the result of addition may be used in 24-bit and 31-bit modes, respectively. Also, a 64-bit data arithmetic circuit may be provided in place of the 64-bit address arithmetic circuit 8 and the 32-bit arithmetic circuit 9 and lower-order 32 bits of the result of the 64-bit arithmetic operations could be used to perform operations on 32-bit data. In the above-described embodiment, by way of example, a plurality of adders are separately provided in order to achieve the high speed of arithmetic operations on 32-bit data. In a second modified form of the above-described embodiment, the 64-bit address arithmetic circuit 8 may be constituted in 48-bit form, and thus arithmetic operations on an address could be performed on the basis of the length of 48 bits. However, in the above-described embodiment, the length of 64 bits is illustratively adopted in order to enable simultaneous arithmetic operations on data which is not an address but stored in higher-order 16 bits exceeding the most significant bit of 48 bits of the general register. In a third modified form of the present invention, except for the flip-flop V18, arithmetic operations upon an address and the main storage access instructions the access target of which is consistently an address arithmetic operation. In this case, although the speed of address arithmetic operations in 24-bit and 32-bit modes may be reduced, this exerts no influence over the principal effects of the present invention. The preferred embodiment and its modified forms have been described in detail. As described above, any of the embodiment and the modified forms is achieved by a control mechanism for controlling the general registers. However, the present invention is not confined solely to the aforesaid example. Such control may be achieved by control exerted by micro-programming in an operating system (OS) of a computer. The above description refers to the use of the general registers. While an address processing similar to that of such registers may be achieved by a dedicated address register or registers. In accordance with the present invention, since the length of an address can be extended with the length of data being the same, it is easy to transfer data between a program in which the length of an address is not extended and a program in which the length of an address is extended. This assures compatibility with conventional types of data processor.

Claims: A data processor comprising a main storage (5), means (3) for specifying a virtual address length selected from a first bit length ( a bits) greater than the length of a data word and at least one second bit length smaller than the first bit length ( a bits), a plurality of registers (7) each having a third bit length ( r bits) not smaller than the first bit length ( a bits), each for handling a signal indicative of a virtual address or data, operation means (8, 9) connected to said registers (7) and said main storage (5) for performing an arithmetic or logical operation designated by an instruction, the designated operation being performed on a portion of a first signal held by a first one of the registers (7) designated by the instruction so as to provide a second signal corresponding to a result of the designated operation to a second one of the registers (7) designated by the instruction, wherein both the bit portion operated upon by the designated operation within the first signal and the bit length of the second signal are not smaller than the first bit length ( a bits) in a first mode of operation of the operation means, and are equal to a fourth bit length ( d bits) smaller than the first bit length ( a bits) in a second mode of operation of the operation means, and access means (4) connected to said main storage (5), said registers (7) and said specifying means (3) for generating a virtual address having the first bit length (a bits) in response to a bit portion within a third one of the registers (7), with the address length specified by said specifying means, said third register being designated by an instruction and accessing said main storage (5) with the generated address (AD 43), the access means (4) including means for accessing said main storage (5) for a signal having at least the first bit length ( a bits) in the first mode of operation and having the fourth bit length ( d bits) in the second mode of operation, so that signals having significant bit portions of different lengths are transferred between said main storage (5) and said registers (7), characterised in that control means is connected to said operation means (8, 9) and said access means (4) for causing said operation means to adopt said first mode of operation, in which the bit length corresponds to that required for addressing, in response to an instruction requiring access to said main storage (5) by said access means (4), and the adopt said second mode of operation, in which the bit length is equal to said fourth bit length and thus independent of that adopted in said first mode of operation, in response to an instruction requiring execution of an operation other than accessing the main storage by said operation means. The data processor of claim 1, wherein said control means includes means responsive to an instruction requiring execution of an operation by said operation means (8, 9) for controlling said operation means so as to perform the first or the second mode of operation, depending upon whether the instruction belongs to a first or a second group of instructions, at least when the address length specified by said specifying means (3) is the first bit length ( a bits), and for controlling said operation means (8, 9) so as to perform the second mode of operation at least when the specified address length is the second bit length and at the same time the instruction belongs to the second group of instructions, and responsive to an instruction requiring access to said main storage (5) by said access means (4) for controlling the access means so as to perform the first or second mode of operation thereof, depending upon whether the instruction belongs to the first or second group of instructions, at least when the specified address length is the first bit length ( a bits), and for controlling said access means (4) so as to perform the second mode of operation at least when the specified address length is the second bit length and at the same time the instruction belongs to the second group of instructions. The data processor of claim 2, wherein said means included in said control means includes means responsive to an instruction (102) requiring execution of an operation by said operation means (8, 9) for controlling the operation means so as to perform the first or the second mode of operation, depending upon whether the instruction belongs to the first or second group of instructions, irrespective of the specified address length, and responsive to an instruction (96) requiring access to said main storage (5) by said access means (4) for controlling the access means so as to perform the first or second mode of operation, depending upon whether the instruction belongs to the first or second group of instructions, irrespective of the specified address length. The data processor of claim 2, wherein said means included in said control means includes means connected to said specifying means (3) and responsive to an instruction (102) requiring execution of an operation by said operation means (8, 9) for controlling the operation means so as to perform the first or the second mode of operation, when the specified address length is the first bit length ( a bits) and the instruction belongs to the first group of instructions or when the specified address length is the second bit length or the instruction belongs to the second group of instructions, and responsive to an instruction (96) requiring access to said main storage (5) for controlling said access means (4) so as to perform the first or second mode of operation, when the specified address length is the first bit length ( a bits) or when the specified address length is the second bit length or the instruction belongs to the second group of instructions. The data processor of claim 1, wherein said operation means includes first operation means (8) for performing one of a first group of arithmetic or logical operations on a bit portion (r bits) not smaller than the first bit length ( a bits) within a signal held by one of said registers (7) and providing a signal which corresponds to the result of the one operation and is not shorter than the first bit length (a bits), and second operation means (9) for performing one of a second group of arithmetic or logical operations on a bit portion with the fourth bit length (d bits) within a signal held by one of said registers (7) and providing a signal which corresponds to the result of the one operation and has the second bit length. The data processor of claim 5, wherein said operation means (8, 9) further includes means (10) connected to said second operation means (9) for generating a signal having bit length not smaller than the first bit length (a bits) and including the signal provided by said second operation means (9) at a lower bit portion and "0"s at an upper bit portion, for storing the generated signal into one of said registers (7). The data processor of claim 6, wherein said operation means (8, 9) further includes select means (11) connected to said first operation means (8) and said generating means (10) for selectively transferring one of the signals provided by said first operation means (8) and said generating means (10). The data processor of claim 6, wherein the third bit length ( r bits) is greater than the first bit length ( a bits), wherein the bit length of a signal operated upon by said first operation means (8) is equal to the third bit length ( r bits), the bit length of a signal provided by said first operation means (8) is equal to the third bit length ( r bits), and the bit length of a data signal generated by said generating means (10) is equal to the third bit length ( r bits). The data processor of claim 5, wherein the total number of arithmetic or logical operations of the first group is smaller than the total number of arithmetic or logical operations of the second group. The data processor of claim 1, wherein said operation means (8, 9) includes means for providing, as the second signal corresponding to the result of the operation by said operation means, a data signal having a predetermined bit length not smaller than the first bit length ( a bits), irrespective of whether the mode of operation of said operation means is the first or the second mode of operation. The data processor of claim 10, wherein the bit length of a bit portion operated upon by said operation means (8, 9) in the first mode of operation and the predetermined bit length are equal to the third bit length ( r bits). The data processor of claim 11, wherein the third bit length ( r bits) is greater than the first bit length ( a bits). The data processor of claim 11, wherein said main storage (5) includes means for performing a write or a read operation on a signal having the third bit length ( r bits) in the first mode of operation, and on a signal having the fourth bit length ( d bits) in the second mode of operation, wherein said operation means (8, 9) includes means for receiving, from said main storage (5), a signal of the fourth bit length ( d bits) to be provided to one of the registers and for generating a signal of the third bit length ( r bits) including the received signal as a significant bit portion, so as to provide the generated signal to said one register in the second mode of operation of said operation means (8, 9), and wherein said access means (4) includes means for receiving a signal having the third bit length ( r bits) from said operation means (8, 9) and for providing a signal comprised of a significant bit portion having the fourth bit length ( d bits) to said main storage (5) to be stored therein in the second mode of operation. A data processing method using a processor which has a main storage (5), a memory access means (1, 2) for accessing said main storage under a virtual storage system, registers (7), and data and address arithmetic and logic operation means (8, 9) connected to said main storage and said registers, comprising a step of specifying either a predetermined maximum length of an address ( a bits) or the length of an address less than said predetermined maximum length, a first arithmetic step for reading out the lower-order d bits from a first one of said registers (7) specified by a first instruction, which is one of a first group of instructions, to perform arithmetic operations on said d bits, and writing the result of said arithmetic operations into a second one of said registers, an address generating step for reading a bit string of a specified effective length out of a third one of said registers (7) specified by a second instruction, which is one of a second group of instructions, to generate an a -bit address, and a step of reading d bits out of said main storage (5) in response to said address generated in said address generating step and writing said d bits into either said main storage (5) or a specified one said registers (7), characterised by a control step for performing said ad+ dress generating step in a first mode of operation, in which the bit length corresponds to that required for addressing, in response to an instruction of said second group of instructions, and for performing said arithmetic step in a second mode of operation, in which the bit length is equal to said fourth bit length and thus independent of that adopted in said first mode of operation, in response to an instruction of said first group of instructions. The method of claim 14, wherein said first group of instructions includes a first group of arithmetic or logic instructions and a first group of storage access instructions, wherein said arithmetic step is activated in response to said first group of storage access instructions. The method of claim 14, wherein said first arithmetic step comprises a step of writing the d -bit result of arithmetic operations into lower-order d bits and "0"s into all other bits of one of said registers (7), and a step of writing data read from said main storage (5) into the lower-order d bits and "0"s into all bits other bits of one of said registers (7). The method of claim 14, wherein said registers include general register elements only, the method further comprising a second arithmetic step of reading lower-order n bits upward from a bits of a first general register element or first general register elements specified by an arithmetic instruction, to perform arithmetic operations on said n bits, and writing the result of arithmetic operations on said n bits into the lower-order n bits of a second register element specified by said arithmetic instruction, and a step included in said control step for performing said arithmetic step in response to the second arithmetic instruction. The method of claim 17, wherein, if an effective length equal to or less than the d bits of the address is specified for an operand in response to said second group of arithmetic operations, said control step performs said first arithmetic step while, if said effective length specified exceeds d bits, said control step performs said second arithmetic step. The method of claim 18 further comprising a second storage access step for either reading of r bits out of said main storage (5) in response to an address generated by said address generating step and writing said r bits to said first general register element specified by a storage access instruction, or reading r bits out of said first register element and writing said r bits into said storage (5), wherein said storage access control step includes the step of performing a second main storage access step in response to a second group of main storage access instructions indicative of an address transfer. The method of claim 19, wherein, if an effective length equal to or less than d bits of the address is specified for an operand in response to said second group of arithmetic operations, said storage access control step performs said first storage access step while, if said effective length specified exceeds d bits, said storage access control step activates said second storage access step.

Inventors: KAGIMASA TOYOHIKO, MATSUDA YOSHIKI, TAKAHASHI KIKUO, YOSHIZUMI SEIICHI, KAGIMASA, TOYOHIKO, MATSUDA, YOSHIKI, TAKAHASHI, KIKUO, YOSHIZUMI, SEIICHI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1987
Main classification: G06F9
IPC codes: G06F9