SEMICONDUCTOR INTEGRATED CIRCUIT WITH DETECTION CIRCUIT FOR ADDRESS SIGNAL CHANGE

Abstract: A semiconductor integrated circuit with a detection circuit for detecting an address signal change comprises a plurality of gate circuits (21, 22, 23), and a plurality of resettable delay circuits (24, 25). Each delay circuit (24, 25) is reset when an address signal (A) or an inverted address signal ( ) is at a predetermined polarity and level. Thus the circuit generates a pulse having a pulse width no shorter than a predetermined time interval upon each address change even if that change is only caused by noise.

Description: The present invention relates to a semiconductor integrated circuit with a detection circuit for detecting changes in an input signal, for example, an address signal, and particularly, to a semiconductor integrated circuit generating a pulse always having a pulse no shorter than a predetermined (normal) time interval upon detection of a change of an address signal. Certain semiconductor memory devices contain a pulse generating circuit for generating a pulse when an address signal is changed, to promote discharge of word lines, short circuit a pair of bit lines, and charging of the pair of bit lines. This pulse desirably has a constant pulse width, and for the memory device to operate effectively the pulse width must not be shorter than a normal pulse width. If a signal change caused, for example, by noise equivalent to an address change occurs after only a short interval the pulse width of the pulse generated by the circuit is narrower than the normal pulse width, and the application of such a narrow width pulse will not ensure normal operation of the memory device. A conventional semiconductor integrated circuit with a detection circuit for detecting a change in an input signal comprises a first gate circuit for receiving an input signal at one of its inputs; a second gate circuit for receiving an inverted input signal at one of its inputs; a third gate circuit for receiving outputs of the first gate circuit and second gate circuit; a first delay circuit receiving an output of the second gate circuit, and delaying the output of the second gate circuit for a predetermined time interval, an output of the second delay circuit being connected to another input of the second gate circuit. According to this invention in such a circuit the first and second delay circuits are both resettable delay circuits; the first resettable delay circuit being reset in response to a change of the input signal; and, the second resettable delay circuit being reset in response to a change of the inverted input signal. The circuit in accordance with the present invention provides a circuit which generates a pulse the length of which is never shorter than a predetermined value irrespective of the timing of a signal change. In the circuit in accordance with this invention if, for example, the first, second, and third gate circuits are NAND gates, when the address input is low level the first delay circuit is reset and outputs a low level signal, and if the first, second, and third gate circuits are NOR gates, when the address input is high level the first delay circuit is reset and outputs a high level signal. On the other hand if, for example, the first, second, and third gate circuits are NAND gates, when the inverted address input is low level the second delay circuit is reset and outputs a low level signal, and if the first, second and third gate circuits are NOR gates, when the inverted address input is high level the second delay circuit is reset and outputs a high level signal. As a result, the semiconductor integrated circuit according to the present invention generates a pulse always having a pulse width no shorter than a predetermined value when a change occurs in the address signal. Particular embodiments of circuits in accordance with this invention will now be described and contrasted with the prior art with reference to the accompanying drawings, in which:- Figure 1 is a circuit diagram of a conventional circuit generating a pulse upon detection of an address change; Fgiure 2 is a waveform diagram of the conventional circuit; Figure 3 is a circuit diagram of a semiconductor integrated circuit with a detection circuit for detecting an address signal change according to a first embodiment of the present invention; Figure 4 is a waveform diagram of the circuit shown in Figure 3; Figure 5 is a circuit diagram of an example of delay circuit shown in Figure 3; Figure 6 is a graph showing the voltage change across the capacitor in the circuit shown in Figure 5; Figure 7 is a circuit diagram of a second embodiment of the present invention; and, Figure 8 is a waveform diagram showing an output voltage of the circuit shown in Figure 7. Prior to the description of the preferred embodiments, a conventional circuit is explained for comparison with reference to Figure 1. Figure 2 shows a waveform diagram in the circuit in Figure 1. As shown in Figure 1, this circuit comprises NAND gates 11, 12, and 13, and delay circuits (DELAY) 14 and 15. The reference character A represents an address signal, represents an inverted address signal, and P represents an output pulse. Referring to the reference characters c to f in the figure, the waveforms thereof are shown in Figure 2, wherein DV₁ and DV₂ are charge voltages in the delay circuits 14 and 15, respectively, having polarities opposite to those of the voltages of e and f. In Figure 2, as shown at time t₁, when the address signal A is high level (H) and the inverted address signal is low level (L), the output c of the NAND gate 12 is H, the output d of the NAND gate 11 is L, and the output P of the NAND gate 13 is H. At time t₂, when the address signal A becomes L and the inverted address signal becomes H, the output d of the NAND gate 11 is H, the output c of the NAND gate 12 is still H, and the output P of the NAND gate 13 is L. After the delay time ND by the delay circuit 15, the output f of the delay circuit 15 is H, the output c of the NAND gate 12 is L, and the output P of the NAND gate 13 is H. Thus, when the address signal A goes from H to L and the inverted address signal goes from L to H, the output P which is L during the interval ND, which is equal to the delay time by the delay circuit 15, is obtained. Conversely, when the address signal A goes from L to H and the inverted address signal goes from H to L, the output P which is L during the delay time by the delay circuit 14, is obtained. If the delay times of the delay circuits 14 and 15 are the same, the pulse width of the output P is the same in both cases. As mentioned above, in the circuit of Fig. 1, a pulse P having a predetermined pulse width is output when the address signal changes. The above cases are the normal case, but if the address signal change occurs within the delay time ND then, as shown at times t₃ to t₅ in Fig. 2, the pulse width of the output P becomes narrower than the predetermined value ND. Namely, at the time t₃ , if the address signal A is H, the inverted address signal is L, and the output P is H, and at the time t₄ , if the address signal A is L and the inverted address signal is H, then the output P is L. Up to this point, the changes in level are the same as described case. However, if during the delay time ND, i.e., before the output f of the delay circuit 15 becomes H, the address signal A becomes H and the inverted address signal becomes L, as shown at the time t₅ , since the output e of the delay circuit 14 is still H, the output d of the NAND gate 11 immediately becomes L, and thus the output P becomes H. Usually, a change of the address signal does not occur at an interval shorter than the delay time ND, and the change as shown in the time t₃ to t₅ in Fig. 2 is an abnormal condition such as a noise insertion. When an abnormal condition occurs in the semiconductor memory device, the pulse width of the output P must not be shorter than the predetermined value ND. If the pulse width is narrower than the value ND, a failure can occur during the memory operation. In Fig. 2, AB shows the abnormal pulse widths; that on the right having a zero width. Figure 3 shows a first embodiment of the present invention. The circuit in Fig. 3 comprises NAND gates 21, 22, and 23, and delay circuits 24 and 25. As can be seen in comparison with the circuit in Fig. 1, the circuit in Fig. 3 is provided with a delay circuit 24 including a NAND gate 26, a resettable delay circuit 28, and an inverter 30, instead of the delay circuit 14, and a delay circuit 25 including a NAND gate 27, a resettable delay circuit 29, and an inverter 31, instead of the delay circuit 15. In Fig. 4, a prime is added to the reference characters corresponding to c, d, e, f and DV₁ , DV₂ in Fig. 2. As shown in Fig. 4, in this circuit the output pulse P is initiated from the start of the address signal change and is ended after the delay time ND from the last address signal change, when the address signal change occurs at a short interval. Thus the output P having a short pulse width is not generated. Namely, when the address signal A is H and the inverted address signal is L, at the time t₃ , the output c′ of the NAND gate 22 is H, the output of the NAND gate 26 is L, the output e′ of the inverter 30 is H, the output d′ of the NAND gate 21 is L, and the output P of the NAND gate 23 is H. At the time t₄ , when the address signal A is L and the inverted address signal is H, the output d′ of the NAND gate 21 is H and the output P of the NAND gate 23 is L. When the output d′ of the NAND gate 21 is H, the output of the NAND gate 27 is L. After the lapse of the delay time of the resettable delay circuit 29, the output f′ of the inverter 31 is H, the output c′ of the NAND gate 22 is L, and the output P of the NAND gate 23 is H. If before the lapse of the delay time (t₅) the address signal A becomes H, and the inverted address signal becomes L, the output c′ of the NAND gate 22 is H. At this time, in the circuit in Fig. 1 the output e of the delay circuit 14 is H, the output d of the NAND gate 11 is L, and therefore, the output P of the NAND gate 13 is H. But, in the circuit in Fig. 3, when the address signal A is L the resettable delay circuit 28 is reset by the H level output of the NAND gate 26, and thus the output of the resettable delay circuit 28 is H. Therefore, the output e′ of the inverter 30 is L, the output d′ of the NAND gate 21 is H, and the output P of the NAND gate 23 remains L. Successively, even when the address signal A is L and the inverted address signal is H, the output d′ of the NAND gate 21 is H, the resettable delay circuit 29 is reset by the H output of the NAND gate 27, because the inverted address signal is L, the output of the resettable delay circuit 29 is H, the output f′ of the inverter 31 is L, the output c′ of the NAND gate 22 is H, and the output P of the NAND gate 23 remains at L. If, at this time, the change of the address stops and the address signal A remains L and the inverted address signal remains H, the circuit operates normally. In this state, since the output d′ of the NAND gate 21 is H, the output of the NAND gate 27 is L, and the resettable delay circuit 29 starts to count a time. After the lapse of a prede­ termined delay time ND, the output of the resettable delay circuit 29 becomes L, the output f′ of the inverter 31 becomes H, the output c′ of the NAND gate 22 becomes L, and the output P of the NAND gate 23 becomes H. In Fig. 1, when the delay circuit 15 determines the pulse width of the output P, the delay circuit 14 is not used. Moreover, the delay circuit 14 generates the H output, and when the address signal A is H, the output d of the NAND gate 11 is made L and the output P of the NAND gate 13 is made H. These are disadvantageous incurred by the generation of the pulse having the narrower pulse width. Assuming that the change of the address is generated within the delay time ND, the address signal A is H, and the inverted address signal is L, then at this time, the output e of the delay circuit 14 is still H, the output d of the NAND gate 11 is made L, and the output P of the NAND gate 13 is made H. At this time (A is L), the output e of the delay circuit 14 has no relation to the determination of the pulse width of the output P, and therefore, it does not matter if the output e is L when the address signal A is L. Using the above-mentioned circuit, when the address signal A is H, the output d does not become L. In the present invention, when the address signal A is L, the resettable delay circuit 28 is reset, and the output thereof is made H and then made L through the inverter 30. The resettable delay circuit 29 is reset when the inverted address signal is L and the output f′ is made L. Thus, if the address signal A is H, the output d′ of the NAND gate 21 is H, and the generation of the output pulse P having a narrow pulse width can be prevented. A concrete example of the delay circuit 24, which is as same as the delay circuit 25, is shown in Fig. 5. The delay circuit 24 comprises p channel MOS transistors Q₁ , Q₂ , and Q₃ , n channel MOS transistors Q₄ , Q₅ , and Q₆ , a capacitor C₁ , and a resistance R₁. In the delay circuit 24, the NAND gate 26 or 27 is composed of the p channel transistors Q₁ and Q₂ , and n channel transistors Q₄ and Q₅; the resettable delay circuit 28 or 29 is composed of the capacitor C₁ and the resistance R₁; and the inverter 30 or 31 is composed of the p channel MOS transistor Q₃ and the n channel MOS transistor Q₆. Preferably, the MOS transistors Q₁ and Q₂ have a large W/L (channel width/channel length), and the MOS transistors Q₄ and Q₅ have a small W/L. In Fig. 5, V CC is a positive terminal and V EE is a negative terminal, of the power source. Figure 6 shows the voltage change across the capacitor C₁ in the circuit of Fig. 5. As shown in the figure, the charge of the charged capacitor C₁ is gradually discharged through the resistance R₁, transistors Q₄ and Q₅ following the time constant R₁ x C₁ by applying a high level at the gate thereof, and thus the voltage across the capacitor C₁ is decreased. When the voltage has decreased to a value V th , the output level is inverted by the inverter. The operating voltage of the inverter is determined by the W/L of the transistors Q₃ and Q₆. In the figure, the reset (RS) is shown by the steep slant at the right. When the capacitor C₁ is reset, the capacitor is abruptly charged, following the slant, and the voltage across the capacitor is returned to a high level through the transistor Q₁ or Q₂ by applying a low level at the gate thereof. The output levels of the resettable delay circuits 28 and 29 in the circuit in Fig. 3 are shown as DV₁′ and DV₂′ in Fig. 4, respectively. Figure 7 shows a circuit according to a second embodiment of the present invention. In this circuit, compared with the first embodiment, NOR gates 41, 42, and 43 are used instead of the NAND gates 21, 22, and 23, OR gates 46 and 47 are used instead of the NAND gates 26 and 27, amplifiers 50 and 51 are used instead of the inverters 30 and 31, and the resettable delay circuits 48 and 49 are reset so that when the address signal A or the inverted address signal is H, the output of the resettable delay circuit 48 or 49 is H, respectively. The operation of this circuit is substantially the same as that of the circuit of the first embodiment, except that the polarity of the output P is H as shown in Fig. 8. The circuits of the present invention can be advantageously used in a semiconductor memory device because the circuits can generate a pulse always having a pulse width no shorter than a predetermined value even if an abnormal change of an address signal occurs.

Claims: 1. A semiconductor integrated circuit including a detection circuit for detecting a change of an input signal comprising: a first gate circuit (21, 41) for receiving an input signal (A) at one of its inputs; a second gate circuit (22, 42) for receiving an inverted input signal () at one of its inputs; a third gate circuit (23, 43) for receiving outputs of the first gate circuit (21, 41) and second gate circuit (22, 42); a first delay circuit (24, 44) receiving an output of the second gate circuit (22, 42), and delaying the output of the second gate circuit (22, 42) for a predetermined time interval, an output of the second delay circuit (25, 45) being connected to another input of the second gate circuit (22, 42); characterised in that the first and second delay circuits (24, 44 and 25, 45) are both resettable delay circuits; the first resettable delay circuit (24, 44) being reset in response to a change of the input signal (A); and, the second resettable delay circuit (25,45) being reset in response to a change of the inverted input signal. 2. A semiconductor integrated circuit according to claim 1, wherein the first (21), second (22), and third (23) gate circuits are NAND gates. 3. A semiconductor integrated circuit according to claim 1, wherein the first (41), second (42), and third (43) gate circuits are NOR gates. 4. A semiconductor integrated circuit according to any one of the preceding claims, wherein each resettable delay circuit (24, 25, 44, 45) comprises a capacitor (C1), a resistance (R1), first (Q1), second (Q2), third (Q4), and fourth (Q5) transistors, and an inverter (Q3, Q6); the capacitor (C1) being charged to a high level through the first transistor (Q1) when the first transistor receives at its gate a low level signal from the input signal (A) or the inverted input signal (); the capacitor (C1) being charged to a high level through the second transistor (Q2) when the second transistor (Q2) receives at its gate a low level signal (C′, d′) from an output of a gate circuit (22, 21) connected to an output of the other resettable delay circuit (25, 24); an electric charge in the capacitor (C1) being discharged through the third transistor (Q4), the fourth transistor (Q5), and the resistance (R1) when the third transistor (Q4) receives at its gate a high level signal from the input signal (A) or the inverted input signal (), and when the fourth transistor (Q5) receives at its gate a high level signal (c′, d′) from the output of the said gate circuit (22,21); and, a voltage across the capacitor (C1) being amplified and inverted by a predetermined threshold through the inverter (Q3, Q6) and supplied as an output (e′, f′).

Inventors: TAKEUCHI, ATSUSHI
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: H03K5
IPC codes: H03K5, G11C11