SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device enabling a two or more direction data access with a high speed, a simple circuit construction and an easy selection. A semiconductor memory device including: a plu­ rality of word lines; a plurality of bit lines; a plurality of momory cells (l0) connected to the bit lines and the word lines; a first selection unit operatively connected to the word lines, for selecting one of the word lines in response to a first address signal; and a second selection unit, operatively connected to the bit lines, for receiving a plurality of bit data from the bit lines and selecting at least two bit data from the received plurality of bit data in response to a second address signal. A relationship between the at least two bit data and the second address signal is changed in response to an access direction signal which designates one of the access directions.

Description: The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device enabling a multidirection data selection, especially a two or more direction data read and/or write in a logical bit map space. In an image data processing system, for example, in a computer tomography (CT) scanning system, three dimensional bit map data are used and each data has a color and gradation indicating density. In the CT scanning system or the like, a high-speed reading of a plurality of data in a X-, Y- or plane-direction of a three dimension bit map space is required. Conventional memory devices are essentially accessed in only one direction, for example, by a word line and bit lines. However, the conventional memory devices cannot achieve a multidirection access, in other words, a high dimension access, because, for example, in a two dimension logical bit map space, a plurality of bit data in a X direction can be read by one access, but a plurality of accesses for reading a plurality of bit data in a Y direction is required. EP-A-0 179 605 discloses a semiconductor memory device having the features of the preamble of the accompanying claim 1. According to the present invention there is provided a semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells connected to said bit lines and said word lines; first selection means, connected to said word lines, for selecting one of said word lines in response to a first address signal; and second selection means, connected to said bit lines for selecting data from the selected word line in response to a second address signal, characterised in that: data of said memory cells connected to one of said word lines forms a global word divided into a plurality of normal words, each of said normal words forming a multi-dimensional data array with bit data therein arranged along predetermined directions, whereby said first selection means is operative to select one global word; and in that said second selection means comprises: a first means for selecting a plurality of bit data from the selected word line so as to select one directional data belonging to the same predetermined direction from each of the normal words of the selected global word; and a second means for selecting at least two bit data from said plurality of bit data so as to select said two bit data from one normal word of the selected global word; a relationship, between the position of said at least two bit data along said predetermined directions and said second address signal, being changed in response to an access direction signal which designates one access direction of said multidimensional data array. An embodiment of the present invention may provide a semiconductor memory device enabling a multidirection data read and/or write with a high speed. An embodiment of the present invention may provide a semiconductor memory device enabling a multidirection data read and/or write with a simple circuit construction which results in a low power consumption and a high integration. For example, in a two dimension logical bit map space, a plurality of bit data in a X-, Y- or plane direction can be read or written by a single access, and in a three dimension logical bit map space, a plurality of bit data in any direction can be read or written by a single access, and so on. The selection circuit may further include a circuit for inputting a plurality of bit data of at least two bits to be stored from an external circuit and sending the input data to the bit lines. In one embodiment of the invention, the semiconductor memory device includes: a plurality of memory blocks, each having a plurality of word lines, a plurality of bit lines, a plurality of memory cells connected to the bit lines and the word lines, a first selection unit, operatively connected to the word lines, for selecting one of the word lines in response to a first address signal, and a second selection unit, operatively connected to the bit lines, for receiving a plurality of bit data from the bit lines and selecting at least two bit data from the received plurality of bit data in response to a second address signal. A relationship between the at least two bit data and the second address signal is changed in response to an access direction signal which designates one of access directions. Each memory block further has a third selection unit, operatively connected to the second selection unit of each memory block, for selecting a plurality of bit data from the data selected by the second selection unit in response to a third address signal. Another relationship between the third address signal and the plurality of bit data selected by the third address signal is changed by the access direction signal. In another embodiment, the semiconductor memory device includes : a plurality of memory units; a plurality of first selection units each operatively connected to the corresponding memory unit; a plurality of first data bus units each operatively connected to the corresponding first selection unit; a second selection unit operatively connected to the first selection units through the first data bus units; and a second data bus unit operatively connected to the plurality of second selection unit. Each memory unit for storing and reading a plurality of bit data arranged in a multidimensional form, has a plurality of word lines, a plurality of bit lines and a plurality of memory cells operatively connected between the word lines and the bit lines to read or write a plurality of bit data therefrom or therein connected to a selected word line. Each of the first data bus units has a plurality of bus lines equal to at least two bit data to be selected. Each of the first selection units includes a plurality of selection circuits connected therebetween and connected to the bus lines of the corresponding first data bus unit, in a relationship for receiving a plurality of data on the bit lines and outputting the bit data selected from the received data in response to a first selection signal supplied to the first selection units and the connection of the relationship. The second selection unit outputs bit data selected from the data on the first data bus units in response to a second selection signal to the second data bus unit. In a further embodiment of the invention the semiconductor memory device includes : a memory unit for storing and reading a plurality of bit data arranged in a multidimensional form; a plurality of selection units each operatively connected to the memory unit; and a data bus unit operatively connected to the selection units. The memory unit has a plurality of word lines, a plurality of bit lines and a plurality of memory cells, operatively connected between the word lines and the bit lines to read or write a plurality of bit data therefrom or therein connected to a selected word line. The data bus unit has a plurality of bus lines equal to at least two bit data to be selected. Each of the selection units includes a plurality of selection circuits connected therebetween and connected to the bus lines, in a relationship for receiving a plurality of data on the bit lines and outputting the bit data selected from the received data in response to a first selection signal supplied to the selection units and the connection of the relationship. The plurality of selection units are consecutively operated to receive data from the memory unit continuously accessed prior to the operation of the selection unit. In a still further embodiment of the invention, the semiconductor memory device includes: a plurality of memory units; a plurality sets of first selection units each set including a plurality of selection units operatively connected to the corresponding memory unit; a plurality of first data bus units each operatively connected to the corresponding first selection unit; a second selection unit operatively connected to the first selection units through the first data bus units; and a second data bus unit operatively connected to the plurality of second selection units. Each memory unit for storing and reading a plurality of bit data arranged in a multidimensional form, has a plurality of word lines, a plurality of bit lines and a plurality of memory cells operatively connected between the word lines and the bit lines to read or write a plurality of bit data therefrom or therein connected to a selected word line. Each of the first data bus units has a plurality of bus lines equal to at least two bit data to be selected. Each of the first selection units includes a plurality of selection circuits connected therebetween and connected to the bus lines of the corresponding first data bus unit, in a relationship for receiving a plurality of bit data on the bit lines and outputting the bit data selected from received data in response to a first selection signal supplied to the first selection units and the connection of the relationship. The plurality of selection units are consecutively operated to receive data from the memory units continuously accessed prior to the operation of the selection units. The selection unit outputs data selected from the bit data on the first data bus unit in response to a second selection signal to the second data bus unit. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a view of a logical bit map space of a conventional memory system for an image data processing; Fig. 2 is a block diagram of an embodiment of a semiconductor memory device in accordance with the present invention; Figs. 3a to 3c are view illustrating data output from the memory device shown in Fig. 2; Fig. 4 is a view illustrating a three dimensional data arrangement of a global word shown in Fig. 2; Figs. 5a to 5g are views illustrating data selection of the memory device shown in Fig. 2; Figs. 6a and 6b are a circuit diagrams of the memory device shown in Fig. 2; Figs. 7a to 7d are views illustrating another three dimensional data arrangement; Figs. 8a to 8d are views illustrating still another three dimensional data arrangement; Fig. 9 is a circuit diagram of another selection circuit of the memory device shown in Fig. 2; Fig. l0 is a circuit diagram of a decoder shown in Fig. 9; Fig. ll is a circuit diagram of still another selection circuit of the memory device shown in Fig. 2; Figs. l2a to l2d are views representing the relationships between the segments in the X, Y, and S directions and the sense amplifiers; Fig. l3 is a block diagram of the memory device shown in Fig. ll; Figs. l4a and l4b are a circuit diagrams of a selection circuit of the memory device shown in Fig. l3; Fig. l5 is a circuit diagram of another selection a circuit of the memory device shown in Fig. l3; Fig. l6 is a block diagram of still another embodiment of a semiconductor memory device according to the present invention; Fig. l7 is a circuit diagram of a part of the memory device shown in Fig. l6; Fig. l8 is a circuit diagram of a latch circuit shown in Fig. l7; Fig. l9 is a circuit diagram illustrating the connection between a multidirection selection circuit and a latch circuit shown in Fig. l6; Fig. 20 is a view illustrating a data access arrangement applied to the circuit shown in Fig. l6; Figs. 2la to 2lg are views of a detailed arrangement selected from the memory device shown in Fig. l6; Fig. 22 is a circuit diagram of yet another embodiment of a selection circuit shown in Fig. l6; Fig. 23 is a block diagram of yet another embodiment of a semiconductor memory device according to the present invention; Figs. 24a to 24g are timing charts illustrating the operation of the memory device shown in Fig. 23; Fig. 25 is a circuit connection diagram of selectors, latch circuits and a data bus shown in Fig. 23; Fig. 26 is a circuit diagram of a selector shown in Fig. 25; Figs. 27a to 27f are timing charts of the circuits shown in Fig. 25; Fig. 28 is a block diagram of another embodiment of a semiconductor memory device according to the present invention; Fig. 29 is a circuit diagram of a selection circuit shown in Fig. 28; Figs. 30a to 30e are timing charts of a selection circuit shown in Fig. 28; and Fig. 3l is a block diagram of still another embodiment of a semiconductor memory device according to the present invention. Before describing the preferred embodiments of the present invention, an example of a prior art semiconductor memory system for an image display is described with reference to the drawings, comparison. As shown in Fig. l, the memory system has a logical bit map space therein, i.e., each bit in the memory system corresponds to each picture element (PIXEL) in an image display unit, such as a CRT unit. The memory system includes three memory planes Ml to M3 storing image data for the colors red (R), green (G), and blue (B), respectively. In this example, each memory plane consists of l6 × l6 bits, but in practice, each memory plane has a large capacity of, for example, 52l × 5l2 bits or l024 × l024 bits. In Fig. l, a word consists of eight bits, as shown by shading. Numberals 0 to l5 correspond to bit lines and symbols A to P correspond to word lines. If one memory device consists of 8 bits (one word) × 8 bits (one word) = 64 bits, each memory plane is formed by four memory devices, and thus three memory planes Ml to M3 are formed by twelve memory devices. Eight bits in a word, along the word lines, can be simultaneously read from or written into the memory device. However, the reading or the writing of eight bits marked with crosses along the bit lines requires eight consecutive accesses, resulting in a long access time. To avoid this disadvantage, another approach which assigns the image data in a word line direction to other memories has been attempted. However, this approach still has a low performance when applied to a bulky memory device. In addition, the external circuits become complex, and since a plurality of memory devices must operate simultaneously, the power consumed thereat is increased. Furthermore, peripheral circuits of the memory planes for handling color, etc., become complex. Referring to Figs. 2 to 5g, a first embodiment of a semiconductor memory device in accordance with the present invention will be described. In Fig. 2, the memory device includes a memory cell array l0, a column register l2, and a selection circuit l4. Each global word in the memory cell array l0, as shown by shaded lines, consists of 64 bits, and each normal word consists of eight bits. Accordingly, each global word consists of eight normal words WRD A to WRD H . The 64 bits in each global word can be simultaneously read or written. The eight normal words WRD A to WRD H are stored in a line form in the memory cell array l0 as shown in Fig. 2, but correspond to three dimensional image data as shown in Fig. 4. Further, each word, for example, the word WRD A , consisting of eight bits, also consists of three dimensional image data assigned by directions (000), (00l), (0l0), (0ll), (l00), (l0l), (ll0), and (lll), and each image data consists of one bit. The eight words are virtually arranged in three dimensions, i.e., the X, Y, and Z directions. First, the conceptual operation will be described. When a certain row is selected, a corresponding global word, as shown by hatching in Fig. 2, consisting of eight words WRD A to WRD H , and thus formed by 64 bits, is output from the memory cell array l0 and once stored in the column register l2 of 64 bits. By designating the direction with the direction signal SDIR to the selection circuit l4, data in one direction of the X, Y, or Z directions can be output from the column register l2 as shown in Figs. 3a to 3c. The direction signal SDIR consists of two bits able to designate the three directions. Figures 5a, 5b, 5d, and 5f show the above selection. In the drawings, solid lines indicate a selected data combination in each direction. Further, by designating an address ADR in the drawings with an address signal SADR of two bits, a pair of image data can be selected as shown in Figs. 5c, 5e and 5g. Furthermore, by designating a bit BIT with a bit signal SBIT, a desired image data can be selected. The above selections can be simultaneously effected. Table l is a summary of the above image data selection. In Table l, the direction, the address, and the bit are binary-coded. DIRECTION ADDRESS BIT X = 00 00 000, 100 10 010, 110 01 001, 101 11 011, 111 Y = 01 00 000, 010 10 100, 110 01 001, 011 11 101, 111 Z = 10 00 000, 001 10 100, 101 01 010, 011 11 110, 111 Referring to Figs. 6a and 6b, a specific embodiment of the semiconductor memory device shown in Fig. 2 will be described. The memory device includes the memory cell array l0, a row decoder ll, and a sense amplifier circuit l3 including 64 sense amplifiers SA₀ to SA₆₃ . The memory device may further include the static column register l2 including 64 latch circuits and the selection circuit l4. The selection circuit l4 includes a direction decoder l4a, first and second X decoders l4b and l4c, first and second Y decoders l4d and l4e, and first and second Z decoders l4f and l4g. The selection circuit l4 further includes first to eight X selection gate circuits l4X₁ to l4X₈ , first to eighth Y selection gate circuits l4Y₁ to l4Y₈ , and first to eighth Z selection gate circuits l4Z₁ to l4Z₈ . The memory device also includes a data bus 20. The X selection gate circuits l4X₁ to l4X₈ include 64 transfer gates TG₀ to TG₆₃ . The arrangement of eight transfer gates in each X selection gate circuit is the same, and is formed to output a pair of data as shown in Fig. 5b and Table l. Each X selection gate circuit, for example, l4X₁ also includes a multiplex gate circuit MG₁ formed by two parallel-connected transistors. The Y selection gate circuits l4Y₁ to l4Y₈ and the Z selection gate circuits l4Z₁ to l4Z₈ are similarly formed to meet the relationship shown in Figs. 5d and 5f. The row decoder ll receives a row address of RA₀ to RA₇ and selects a corresponding word line in the memory cell array l0, outputting 64 bits of data on the bit lines. The 64 bits of data on the bit lines are amplified at the sense amplifiers SA₀ to SA₆₃ and stored in the latch circuits SC₀ to SC₆₃ of the column register l4. The direction decoder l4a receives a direction address of DA₁ and DA₀ as the direction signal SDIR in Fig. 2 and outputs an enable signal. When the direction address DA₁ and DA₀ is "00", the enable signal for energizing the X decoders l4b and l4c is output. Similarly, when the direction address DA₁ and DA₀ is "0l", the enable signal for energizing the Y decoders l4d and l4e is output. When the direction address DA₁ and DA₀ is "ll", the enable signal for energizing the Z decoders l4f and l4g is output. A lower column address CA₁ and CA₀ is supplied to the first X, Y, and Z decoders l4b, l4d, and l4f. One of these decoders l4b, l4d, and l4f, energized by the enable signal from the direction decoder l4a, outputs a gate control signal to one of lines ℓ₁ to ℓ₄ . Namely, for example, when the lower column address CA₁ and CA₀ is "00" the gate control signal is output to the line ℓ₁ . An upper column address CA₄ to CA₂ is supplied to the second X, Y and Z decoders l4c, l4e, and l4g. One of these decoders l4c, l4e, and l4g, energized by the enable signal, outputs a multiplex control signal to one of lines L₁ to L₈ . When the direction address DA₁ and DA₀ is "00", the lower column address CA₁ and CA₀ is "00", and the upper column address CA₄ to CA₂ is "000", the image data stored in the latch circuits SC₀ and SC₁ are output to the data bus 20 through the transfer gates TG₀ and TG₁ and the multiplex gate circuit MG₁ in the X selection gate circuit l4X₁ , as shown in Fig. 5c. Similarly, a pair of image data in an arbitrary direction, defined by the three dimensional relationship as shown in Figs. 5a to 5g, can be arbitrarily read from the semiconductor memory device. The above principle can be applied not only to the DRAM as shown but also to a static RAM and a ROM. Another embodiment will be described with reference to Figs. 7a to 7d. In Fig. 7a, a single global word consists of a cubic- arranged three dimensional data of 8 × 8 × 8 bits = 5l2 bits. When the memory device shown in Fig. 2 is applied to handle the data shown in Fig. 7a, the global word of 5l2 bits can be read from the memory cell array l0 and stored in the column register l2 having 5l2 latch circuits through 5l2 sense amplifiers (not shown in Fig. 2). Eight image data in an arbitrary direction of the X, Y, and Z directions can be simultaneously output from the selection circuit l4, as shown in Figs. 7b to 7d. Figure 7b shows a data arrangement of eight image data in the X direction, and Figs. 7c and 7d show data arrangements in the Y and Z directions. Still another embodiment will be described with reference to Figs. 8a to 8d. In Fig. 8a, a single global word consists of l6 × l6 plane-arranged data, each data consisting of ℓ bits. The data of l6 × l6 × ℓ bits is read from the memory cell array l0 and stored in the column register l2. By selecting the direction, either l6 data in the X direction as shown in Fig. 8b, l6 data in the Y direction as shown in Fig. 8c, or 4 × 4 data in a plane form as shown in Fig. 8d, can be read from the selection circuit l4. In this case the plane data array of 4 × 4 bits can be read simultaneously. The above embodiments may be summarized as follows: a) The provision of a memory cell means which enables a simultaneous read or write of a plurality of data bits forming multidimensional data in response to an access request, and b) The provision of a data selection means in, for example, a DRAM device, between bit lines and a data bus. Upon a selection of a word line, all data in memory cells connected to the word line are output on the bit lines. The selection means receives the output data on the bit lines and outputs desired data therein in response to a selection signal designating one or more dimensions. One or more of the data busses can be provided in response to a request for simultaneous data selection. Yet another embodiment of a semiconductor memory device of the present invention will be described with reference to Fig. 9. The memory device is formed to select the data arrangement shown in Figs. 8a to 8d. In Fig. 9, reference WLi denotes the i-th word line connected to 256 memory cells (MC S ), BL72 and BL72 denote a pair of 72-th bit lines, SA₇₂ denotes a 72-th sense amplifier, a detailed circuit construction of which is shown for a 73-th sense amplifier SA₇₃ , l6 denotes a selection circuit l6, and 20 denotes a data bus for outputting two bites i.e., l6 bits. The selection circuit l6 consists of 256 decoder for selecting directions, but only the 72-th and 73-th direction decoders l6D₇₂ and l6D₇₃ , and direction control lines l6a are shown. Each direction decoder, for example l6D₇₂ , consists of an X decoder XD₇₂ , a Y decoder YD₇₂, and an S decoder SD₇₂ . Each direction decoder commonly receives a segment address of B₀ and B₀ to B₃ and B₃ . One of the direction control lines 16a brings the corresponding direction decoder XD₀ to XD₂₅₅ , YD₀ to YD₂₅₅ , or SD₀ to SD₂₅₅ to an active state. As shown in Fig. 8a, the 72-th sense amplifier SA₇₂ outputs a data bit of the ninth bit in the X direction (X = 8) on the fifth row in the Y direction (Y = 4). The 73-th sense amplifier SA₇₃ outputs the tenth bit in the X direction (X = 9) on Y = 4. When the segment address of B₃ and B₃ to B₀ and B₀ indicates Y = 4 and the X decoder SD₇₂ is energized, the data of the sense amplifier SA₇₂ is output to a pair of data busses DB8 and DB8 through the X direction decoder XD₇₂. Similarly, the data of the sense amplifier SA₇₃ is output to a pair of data busses DB9 and DB9 through the X direction decoder XD₇₃ . As a result, the 64-th to 79-th data bits are simultaneously output to the data bus 20, as shown in Fig. 8b. Alternatively, the 72-th sense amplifier SA₇₂ outputs a data of the fifth bit in the Y direction (Y = 4) on the ninth row in the X direction (X = 8). When the segment address of B₃ and B₃ to B₀ and B₀ is eight (X = 8) and the Y decoder YD₇₂ is energized, the data of the sense amplifier SA₇₂ is output to a pair of data busses DB4 and DB4 through the Y decoder YD₇₂ . On the other hand, when the segment address of B₃ and B₃ to B₀ and B₀ is nine (X = 9) and the Y decoder YD₇₃ is energized, the data of the sense amplifier SA₇₃ is output to the pair of data busses DB4 and DB4 through the Y decoder YD₇₃ . Similarly, l6 bit data in the Y direction can be simultaneously output, as shown in Fig. 8c. The above data selection can be applied to the selection on the S plane (direction) of 4 × 4 bits as shown in Fig. 8d. In other words, the direction decoder, for example, l6D₇₂ consisting of the X, Y, and S decoders XD₇₂ , YD₇₂ and SD₇₂ , the direction control lines l6a, and the data bus 20 are connected to output l6 bit data in any direction, i.e., X direction, Y direction, or S plane. Figure l0 is a circuit diagram of the X decoder SD₇₂ . References Q₁ to Q₆ and Q₁₆ denote p-channel MOS transistors, and Q₇ to Q₁₅ denote n-channel MOS transistors. When the X line of the direction control lines l6a is high level, the transistor Q₁₆ is turned ON but the transistor Q₁₅ is turned OFF, and thus a node Nl is low level. The transistor Q₁₂ is turned OFF but the transistor Q₆ is turned ON. When the segment address of B₃ and B₃ to B₀ and B₀ is "0l00" and selects the X decoder XD₇₂ , a decoding portion formed by the parallel-connected transistors Q₁ to Q₄ and the series-connected transistors Q₇ to Q₁₀ becomes effective, making a node N3 low level. The transistor Q₅ is turned ON and the transistor Q₁₁ is turned OFF making a node N2 high level. As a result, the transfer gate transistors Q₁₃ and Q₁₄ are turned ON, outputting the data from the sense simplifier SA₇₂ to the data busses DB8 and DB8 . In Fig. 9, the direction decoder, for example, l6D₇₂ , consisting of three decoders XD₇₂ , YD₇₂ , and SD₇₂ must be provided for each sense amplifier. Generally, N a is the number of memory cells connected to a word line, where N is the number of simultaneous selection bits data and a is the number of directions of the logical bit map space, and the simultaneous selection for N bits in k dimensions (or directions) is required, the direction decoders of kN a and selection signal lines, connecting between the decoders and the data busses, of (2·log₂N a-1 + k) must be provided. These cause a complex circuit construction. In addition, since a distance between the adjacent bit lines in the cell array is narrow, the provision of the decoders of k in the distance is actually impossible. As a result, the distance must expanded, resulting in a low integration of the semiconductor memory device. A circuit shown in Fig. 11 is intended to solve the above defects. In Fig. ll, a predecoder circuit l8 consisting of an X predecoder l8 x , a Y predecoder l8 y , and an S predecoder l8 s , X selection lines 30 x , Y selection lines 30 y , S selection lines 30 s , and transfer gates 72 x , 72 y , 72 s , 73 x , 73 y and 73 s , are provided between the sense amplifiers SA₇₂ and SA₇₃ and the data bus 20. The transfer gate 72 x corresponds to the transistors Q₁₃ and Q₁₄ in Fig. l0. One of the predecoders l8 x , l8 y , and l8 s is energized by one of the direction control signals SX, SY, and SS in an active state. The energized predecoder outputs a high level signal to a line in the selection lines 30 x , 30 y or 30 s in response to the segment address of B₃ and B₃ to B₀ and B₀ and energizes the transfer gate connected to the line, outputting the data of the sense amplifier to the data bus 20. An output "0" of the X predecoder l8 x selects a 0-th segment. The data of the 0-th segment in the X direction are output from the sense amplifiers SA₀ to SA₁₅ (not shown). Transfer gates 00 x to l5 x (not shown) pass the data from the sense amplifiers SA₀ to SA₁₅ to pairs of the data busses DBO and DBO to DBF and DBF . In more detail, as shown in Fig. ll, when the X predecoder l8 x is energized by the direction control signal SX and the segment address B₃ and B₃ to B₀ and B₀ is four ("0l00"), the X predecoder l8 x makes a fifth output ("4") high level. The transfer gate 72 x is turned ON, passing the data of the sense amplifier SA₇₂ to the pair of data busses DB8 and DB8 . Alternatively, the Y predecoder 18 y is energized and the segment address of B₃ and B₃ to B₀ and B₀ is eight ("1000"), the Y predecoder 18 y outputs the data of the sense amplifier SA₇₂ to a pair of data busses DB4 and DB₄ through the transfer gate 72 y . The relationship between the X selection lines 30 x of hexadecimal numbered "0" to "F" (sixteen) lines, the data bus 20 consisting of 16 pairs of data busses also hexadecimal numbered "0" and " 0 " to "F" and " F ", and the sense amplifiers SA₀ to SA₂₅₅ , is defined as shown in Table 2. In Table 2, the segment corresponds to the X selection lines 30 x , because each line designates a segment of 16 bits. The above relationship is also represented in Figs. 12a and 12d. In Fig. 12a, reference B indicates the segment address of B₃ and B₃ to B₀ and B₀ . The relationship between the Y selection lines 30 y , the data bus 20, and the sense amplifiers is also defined as shown in Table 3 and Figs. 12b and 12d. Similarly, the relationship between the S selection lines 30 s , the data bus 20, and the sense amplifiers is defined as shown in Tables 4-1 to 4-4, as typical examples, and Figs. 12c and 12d. Figure 13 is a block diagram of the memory device shown in Fig. 11. The memory device includes the memory cell array 10 of 256 pairs of bit lines x 256 word lines, the row decoder 11, the sense amplifier circuit 13 consisting of 256 sense amplifiers, the predecoder circuit 18 consisting of the X predecoder 18 x , the Y predecoder 18 y , and the S predecoder 18 s , a multidirection selection circuit 19 including the transfer gates and the X selection lines 30 x , the Y selection lines 30 y and the S selection lines 30 S , and the data bus 20. The memory device also includes a latch circuit 22 holding a selected 16 bits of data. Compared with the memory device shown in Fig. 9, the number of decoders in the memory device shown in Fig. 11 can be reduced to k. However, kN a-1 of selection lines still must be provided. Referring to Figs. l4a and l4b, another embodiment of a semiconductor memory device of the present invention, which enables a further simplification of the circuit construction, will be described. In Figs. l4a and l4b, the memory device enables the selection of three directions of X, Y, and S and the simultaneously output of sixteen bits of data. The data bus 20 includes 16 pairs of data busses of DB0 and DB0 to DBF and DBF . A predecoder 40 is provided for commonly using all selection directions. An exclusive selection circuit 38 includes l6 lines. In order to select the direction, a direction selection gate circuit 34 consisting of 256 selection gate groups, each group including X, Y, and S selection gates, for example, 72S x , 72S y and 72S s , and the transfer gate circuit 36 consisting of 256 transfer gate groups, each group including X, Y, and S transfer gates, for example, 72 x , 72 y and 72 s similar to those in Figs. 9 and 11, are provided. Each selection gate, for example, 72S x , is formed by an NOR gate. The 256 × 4 = 1024 bit lines are provided, discretely arranged in fours and connected to the sense amplifier circuit 13. The 0-th segment of 16 bits includes data for the 0-th, fourth, eighth, ..., 66-th bit lines. The 1-st (first) segment includes data on the 64-th, 68-th, 72-th, ..., 124-th bit lines. Four groups of 16 × 16 bits of data as shown in Fig. 8d are connected to one word line. The sense amplifier circuit 13 includes 1024 sense amplifiers SA0 A , SA0 B , SA0 C , SA0 D , ..., SA72 A , SA72 B , SA72 C , SA72 D , ..., SA255 A , SA255 B , SA255 C , SA255 D . A bit selection decoder 32 and bit selection gates, for example, 72B A to 72B D , select data from the sense amplifiers, for example, SA72 A to SA72 D , and output the data to a pair of lines L72. When a bit selection signal C₁ and C₀ is "00" the bit selection gates 72B A , 73B A and 74B A are turned ON, outputting the data from the sense amplifiers SA72 A , SA73 A , SA74 A to the lines L72, L73, and L74. The data to the sense amplifier SA72 A is the data of fourth segment and eighth bit. When the segment address of B₃ and B₃ to B₀ and B₀ is four ("0100"), the predecoder 40 outputs a low level signal on an output of 4 . When the X direction selection signal SX is low level, the data on the lines L72 is output to the pair of data busses DB8 and DB8 through the transfer gate 72 x . By constructing the circuit as shown in Figs. 14a and 14b, the selection circuits, for example, 72B A , 72S x , and 72 x , can be provided in a pitch between the adjacent bit lines without expanding the pitch. On the other hand, by increasing the bit lines, a space in the memory cell array is obtained, and circuits for other groups can be provided in that space, and data from the circuits can be selected by the bit selection decoder 32. As a result, integration of the memory device as a whole can be greatly improved. In addition, compared with the decoder shown in Fig. 10, since the selection gate, for example, 72S x is a NOR gate, the space required by the circuit is reduced to approximately one-thirds. The selection lines between the sense amplifier circuit 13 and the data bus 20 are also greatly reduced. Instead of the bit selection gates, for example, 72B A to 72B D , latch circuits can be provided. The bit decoder 32 selects the data from the latch circuits. The arrangement shown in Figs. 14a and 14b is optimized for the selection in the X direction, but the arrangement can be modified to optimize the selection in the Y direction, or the S plane. In the circuit shown in Figs. 14a and 14b, the circuits are operated at a low enable level, but can be modified to operate at a high enable level. Figure 15 is a circuit diagram of a semiconductor memory device modified from the memory device shown in Figs. 14a and 14b. The selection gates in the bit selection gate circuit 34 have same inputs. For example, in Figs. l4a and l4b, the gates 72S x and 73S x have the same inputs. Also, the gates 72S s and 73S s have the same inputs. The circuit shown in Fig. 15 eliminates these redundancies and simplifies the circuit construction. When 16 bits of data in the X direction are sequentially arranged on the word line, inputs of a NOR gate from the sense amplifiers SA₀ to SA₁₅ become the same upon an output of "0" from the predecoder 40. As a result, the above operation can be achieved by a single gate. In Fig. 15, the circuits operate at a high enable level. Accordingly, the NOR gate in Figs. 14a and 14b can be replaced by an AND gate, such as OX in Fig. 15. The AND gate OX can be commonly used for one segment of 16 bits. Since the plane selection gates have the same four inputs, a single AND gate, such as OS, can achieve the selection for one segment. However, Y selection gates do not have the same inputs, and thus must be provided independently as shown by OY, lY, ... FY. The sense amplifier SA₀ represents the sense amplifiers SA0 A to SA0 D . Lines LO correspond to the lines, for example, L72, operatively connected to the sense amplifiers SA72 A to SA72 D . The transfer gates, for example, 72 x , 72 y and 72 s , can be connected to the lines LO and triggered by outputs from the AND gates OX, OY, and OS. In Fig. 15, only an O-segment is shown. When the bits of data in the Y direction are sequentially arranged at the word line, the number of gates for the Y direction can be reduced, but the gates for the X direction must be provided independently. In the above embodiments, if the directions are increased and/or the bit length of one segment is expanded, the areas of the selection circuit 16, the decoder 18, etc., are greatly increased. Also, a drive current may be increased. In addition, an access time may become long. Furthermore, the total cost of the semiconductor memory device may be increased. The following embodiments are intended to overcome the above defects when a high direction : a of the logical bit map space and a large bit length N of the segment and/or a large number of the access directions : k are required. Referring to Fig. l6, a semiconductor memory device includes l6 memory cell arrays l0a to l0p, l6 sense amplifier circuit sets l3a to l3p each set consisting of 256 sense amplifiers, l6 first multidirection selection circuit sets l6a to l6p each set consisting of 256 selection circuits, l6 latch circuits 22a to 22p, a second multidirection selection circuit incorporated with circuits l6A to l6P, first data busses 20a to 20p (not shown), a second (common) data bus 20A, and an output buffer 24A. Each memory cell array is formed by a folded type DRAM and has a capacity of 256 × 256 bits. Accordingly, in each memory cell array, 256 pairs of bit lines BL₀ and BL₀ to BL₂₅₅ and BL₂₅₅ and 256 word lines WL₀ to W₂₅₅ are provided, and 256 memory cells (16 × 16) are connected to each word line. Each sense amplifier circuit, for example, 13a, consists of 256 sense amplifiers. One segment consists of 16 bits of data. A same row address RA₀ to RA₇ (not shown) is commonly applied to all memory cell arrays 10a to 10p. A first segment address of B₀ and B₀ to B₃ and B₃ (not shown) is commonly applied to the first multidirection selection circuits l6a to 16p. A second segment address of B₄ and B₄ to B₇ to B₇ (not shown) is commonly applied to the second multidirection selection circuit of l6A to l6P. Each first data bus, for example, 20a consists of l6 pairs of data busses DB0 and DB0 to DBF and DBF , but is illustrated only in outline. The second multidirection selection circuit, for example, l6A, receives l6 bits of data. The second multidirection selection circuit incorporated with the circuits 16A to 16P hold 16 × 16 = 256 bits. Accordingly, the second multidirection selection circuit of 16A to 16P can be selected in the same way as the selection of the first multidirection selection circuits 16a to 16p. Thus, 16 bits of data from a selected second multidirection selection circuit are output to the second data bus 20A. The data on the second data bus 20A is output to an external circuit (not shown) through the output buffer 24A. First, in the first multidirection selection circuits, 16 bits of data within 16 × 16 bits in a logical bit map plane in any one of the X, Y, and S dimensions can be selected. Next, in the second multidirection selection circuits, 16 bits of three dimensional data within 16 × 16 × 16 bits in a logical cubic bit map space can be selected. That is, a three direction data selection can be achieved. Figure 17 shows the detailed connections between the first data bus 20a and the latch circuit 22a between the latch circuit and the second multidirection selection circuit 16A, and between the second multidirection selection circuit 16A and the second data bus 20A. In Fig. 18, a detailed latch circuit DLO comprises p-channel MOS transistors Q′₄ , Q′₅ , Q′₁₂ , and Q′₁₃ and n-channel MOS transistors Q′₁ to Q′₃ , Q′₆ to Q′₁₁ , and Q′₁₄ and Q′₁₅. Reference BSR denotes a bus reset signal for resetting the data busses DB0 and DB0 ; reference SBE denotes an enable signal for enabling the data latch; and reference R/W denotes a read/write signal for generating a read enable signal RE and a write enable signal WE through an inverter INV₃. When the bus reset signal BSR becomes high level, the transistors Q′₁ to Q′₃ are turned ON, shorting the data busses DB0 and DB0 , and accordingly, resetting the latch circuit. When the data latch enable signal SBE becomes high level after the signal BSR becomes low level, a p-channel MOS transistor Q′₁₆ is turned ON by an inverted signal of the enable signal SBE through an inverter INV₁. As an n-channel MOS transistor Q′₁₇ is turned OFF, a voltage at a node NAl becomes a power supply voltage V CC . On the other hand, an inverted bus reset signal BSR inverted at an inverter INV₂ is supplied to a gate of a p-channel MOS transistor Q′₁₈ , turning the MOS transistor Q′₁₈ OFF. An n-channel MOS transistor Q′₁₉ is turned ON, and as a result, a voltage at a node NA2 becomes ground level. Accordingly, a latch circuit consisting of the transistors Q′₄ to Q′₇ is made active. When the data bus DB0 is high level and the data bus DB0 is low level, the transistors Q′₄ and Q′₇ are turned ON and the transistors Q′₅ and Q′₆ are turned OFF, maintaining the above high level on the data bus DB0 and the low level on the data bus DB0 . Furthermore, when the read/write signal R/W is high level indicating the read operation, the transistors Q′₁₂ to Q′₁₅ are turned ON, outputting a high level on the data bus DB0 and low level on the data bus DB0 to the second multidirection selection circuit l6A through a switching circuit consisting of the transistors Q′₁₂ to Q′₁₅ and a pair of busses BSO and BSO . At this time, the transistors Q′₈ and Q′₉ are kept OFF. A circuit consisting of the transistors Q′₈ to Q′₁₁ does not effect the above operation. The circuit on the left in Fig. l8 and enclosed by a one-dotted line is commonly used for the latch circuits, as shown in Fig. l7. Figure l9 shows the detailed connections between the latch circuit 22a and the second multidirection selection circuit l6A and between the second multidirection selection circuit l6A and the second data bus 20A. One group of l6 groups in each second multidirection selection circuit l6A consists of three second X, Y, and S decoders, for example, X2D₇ , Y2D₇ , and S2D₇. These second decoders commonly receive data from the latch circuit DL7. These second decoders also commonly receive second segment address of B₄ and B₄ to B₇ and B₇ . One of these second decoders, for example, X2D₇ , Y2D₇ , and S2D₇ , is energized by one of the second direction signals SX2, SY2, and SS2. A combination of the first and second multidirection selection circuits, can provide any one data selection within three dimensional data arrangements, i.e., the XY plane and the Z direction, the YZ plane and the X direction, and the ZX plane and the Y direction, as shown in Fig. 20. Figure 2la is a specific example of the three dimensional data arrangements shown in Fig. 20. The three dimensional data arrangement in Fig. 2la is l6 × l6 × l6 bits. According to all combinations of the first and second multidirection selection, nine data selections can be achieved as shown in Table 5. However, the same data selections exist (marked with a star) and thus, in practice, the data selection is six. 1st SEL 2nd SEL SELECTED DATA X1 X2 X DIRECTION Fig. 21b Y2 Z DIRECTION Fig. 21e S2 ZX PLANE Fig. 21g Y1 X2 Y DIRECTION Fig. 21c Y2 * Z DIRECTION Fig. 21e S2 YZ PLANE Fig. 21f S1 X2 XY PLANE Fig. 21d Y2 * Z DIRECTION Fig. 21e S2 * ZX PLANE Fig. 21g Each direction data consists of serial l6 bits of data. Each plane data consists of 4 × 4 square bits of data. When the first multidirection selection in the X direction is carried out, all data in the second multidirection selection circuit of l6A to l6P is data in the ZX plane. These data are called intermediate segment data. Further, when the second multidirection selection in the X direction is carried out, the X direction data as shown in Fig. 2lb are obtained. Alternatively, when the second multidirection selection in the Y direction is carried out, the Z direction data as shown in Fig. 2le are obtained. When the second multidirection selection in the S plane is carried out, the ZX plane data as shown in Fig. 2lg are obtained. To ensure a connection between the first segment address of B₀ and B₀ to B₃ and B₃ and the second segment address of B₄ and B₄ to B₇ and B₇ , the first multidirection selection circuits and the second multidirection selection circuit must be subjected to a predetermined limitation. If the arrangement between the first multidirection selection circuits and the sense amplifiers is freely set, the arrangement between the second multidirection selection circuit and the latch circuits must be set to a predetermined pattern, or vice versa. Referring to Table 5, when Xl and Y2, Yl and Y2, and Sl and Y2 are given, the Z direction data are obtained. However, the actual data obtained depends on the segment addresses B₀ and B₀ to B₃ and B₃ , and, B₄ and B₄ to B₇ and B₇ . In order to avoid a complex addressing, the redundant selection marked with the stars in Table 5 should be omitted. This can be achieved by predecoding. Table 6 shows an example of such a combination. In Table 6, V₃, V₂ and V₁ are direction designation bits obtained from an external circuit. The selection in Table 6 can be realized by, for example, a three-input and six-output ROM. That is, the ROM reads three inputs for the direction designation of V₃, V₂, and V₁ and outputs six outputs of SX₁ , SY₁ , SS₁ , SX₂ , SY₂ , and SS₂. If the data access for the YZ plane and the ZX plane is not necessary, the S decoder in the second multidirection selection circuit can be omitted. Alternatively, if the data access for the XY plane is not necessary, the S decoder in the first multidirection selection circuit can be omitted. Therefore, the first and second multidirection selection circuits do not always have the same circuit construction. These selection circuits depend on the selection requirement. Referring back to Fig. l6, adjacent memory cell arrays, for example, l0a and l0b, are simultaneously and multidirectionally selected by a same row address. Accordingly, two adjacent first multidirection selection circuits can be commonly used. Figure 22 is a circuit diagram of a common selection circuit. An exclusive X direction selection line 30′ x connected to a X predecoder l8′ x , an exclusive Y direction selection line 30′ y connected to a Y predecoder l8′ y , and an exclusive S plane selection line 30′ s connected to an S predecoder l8′ s are commonly used. A data bus 20 ℓ is connected to the sense amplifier circuit l3ℓ through a gate circuit 50 ℓ . A data bus 20 r is connected to the sense amplifier circuit l3 r through a gate circuit 50 r . To reduce the number of circuit elements, a time division operation may be applied. Figure 23 is a block diagram of a semiconductor memory device which operates in a time sharing mode. Each memory cell array, for example, l0′a, consists of 5l2 word lines × 256 bit lines. That is, the capacity of each memory cell array in Fig. 23 is twice that of Fig. l6. On the other hand, the number of the memory cell arrays is reduced by a half. The second data bus 20A is used by time sharing. The operation of the memory device shown in Fig. 23 will be described in detail with reference to Figs. 24a to 24g. In the read mode, an inverted row address strobe signal RAS becomes low level (Fig. 24a). The word line WL i in the memory cell array l0′a is selected, outputting 256 data on the bit lines (Fig. 24d). Thereafter, the first data latch enable signal SBE having a high level is output to the selection circuit of l6A and 22a, (Fig. 24e), holding the data on the bit lines in the selection circuit of l6A and 22a. Next, the word line WL i+l in the memory cell array l0′a is selected, also outputting other 256 data on the bit lines (Fig. 24d). The second data latch enable signal SBE′ having a high level is output to the selection circuit l6B (Fig. 24f), holding the data on the bit lines in the selection circuit l6B. The data in the selection circuits l6A and l6B are consecutively output to the data bus 20A and to the external circuit (not shown) through the input/output buffer 24A. The latch circuits in the selection circuit can be reduced by a half. Figure 25 is a circuit diagram of this type of circuit. A selector 5l₀ , a detailed circuit of which is shown in Fig. 26, receives two bit data from the data busses DB0 and DB0 , and DB1 and DB1 and outputs either one of the data in response to either one of selection signals SA and SB. The latch circuit l6a₁ in the first multidirection selection circuit l6a receives the output data. Either one of the latch circuits 52₀ and 53₀ in the second multidirection selection circuit l6A′ receives the data from the latch circuit l6a₁ , and outputs the data to the data bus 20A. The above operation is shown in Figs. 27a to 27f. The above common use and time sharing can be combined. Figure 28 is a block diagram of a combined semiconductor memory device. The memory device includes memory cell arrays l0″a and l0″b, data busses 20a and 20b, the first multidirection selection circuit l6, the latch circuit l6a, the second multidirection selection circuit l6A′, and the second data bus 20A. Figure 29 is a circuit diagram of a combination of the common data bus and the common multidirection selection circuit. The circuit shown in Fig. 29 differs in the following points from the circuit shown in Fig. 22: the provision of a left block selection gate circuit 54 energized by the selection signal SA, the provision of a right block selection gate circuit 55 energized by the selection signal SB, the provision of the X, Y and S direction decoders for each sense amplifier, and the provision of the common data bus. Figures 30a to 30e are timing charts illustrating the operation of the circuit shown in Fig. 29. Figure 3l is a block diagram of another semiconductor memory device. The data bus 20A′ has eight bit lines. Eight bits of data on the data bus 20A′ are alternatively inserted into two latch circuits 22Al and 22A2 each having an eight bit length through a selector 5l. The data in the latch circuits 22Al and 22A2 are output to the external circuit through the I/O buffer 24A. In the above embodiments, folded DRAM devices were discussed, but the concept of the present invention can be easily applied to other type of memory devices, such as a static RAM device, and a ROM device for a read only operation. In addition, in the above embodiments, mainly a read operation was discussed, but a write operation obviously can be achieved by providing an input buffer or an input and output buffer as shown in Figs. 23 and 3l. Many widely different embodiments of the present invention may be constructed without departing from the scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims: A semiconductor memory device comprising: a plurality of word lines (WL); a plurality of bit lines (BL); a plurality of memory cells (MC) connected to said bit lines and said word lines; first selection means (11), connected to said word lines, for selecting one of said word lines in response to a first address signal (RA₀...RA₇); and second selection means (14,16), connected to said bit lines for selecting data from the selected word line in response to a second address signal (CA₀...CA₄); characterised in that: data of said memory cells connected to one of said word lines forms a global word divided into a plurality of normal words (WRD A ...WRD H ), each of said normal words forming a multi-dimensional data array with bit data therein arranged along predetermined directions, whereby said first selection means is operative to select one global word; and in that said second selection means (14,16) comprises: a first means (14a, 14b, 14d, 14f) for selecting a plurality of bit data from the selected global word so as to select one directional data belonging to the same predetermined direction from each of the normal words of the selected global word; and a second means (14b, 14d, 14f, 14c, 14e, 14g) for selecting at least two bit data (D0, D1) from said plurality of bit data so as to select said two bit data from one normal word of the selected global word; a relationship (14X1, 14Y1, 14Z1, MG1), between the position of said at least two bit data (D0, D1) along said predetermined directions and said second address signal (CA₀...CA₄), being changed in response to an access direction signal (SDIR;DA₀,DA₁;SX,SY,SS) which designates one access direction (X,Y,Z;X,Y,S;X,Y,Z,ZY,YZ,ZX) of said multidimensional data array. A device according to claim 1, wherein said second selection means further comprises: at least two data buses (20), and transfer gate means (14X,14Y,14Z) connected between said bit lines and said data buses, for transferring said at least two bit data to said data buses; wherein said second means comprises a plurality of decoders (14b,14c;14d,14e;14f,14g) each commonly receiving said second address signal (CA₀...CA₄) and controlling said transfer gate means (14X,14Y,14Z) for selecting said at least two bit data from said plurality of bit data, wherein one of said decoders is activated in response to said access direction signal (SD1R;DA₀,DA₁). A device according to claim 2, wherein the number of said decoders (14b,14c;14d,14e;14f,14g) is equal to a number of access directions (e.g.X,Y,Z) of said multidimensional data array. A device according to claim 2, wherein said transfer gate means comprises a plurality of groups of transfer gates (14X₁...14X₈;14Y₁...14Y₈;14Z₁...14Z₈) each of said groups corresponding to a respective access direction (X,Y,Z) of said multidimensional data array. A device according to claim 1, wherein said second selection means comprises: at least two data buses (20); transfer gate means (14X,14Y,14Z), operatively connected between said bit lines and said data buses, for transferring said at least two bit data to said data buses; a decoder providing said second means, receiving said second address signal (CA₀...CA₄) and providing an output signal, and logical gate means for receiving the output signal from said decoder and said access direction signal (DA₀,DA₁) and providing a control signal based on a logical operation between said output signal from said decoder and said access direction signal, for controlling said transfer gate means. A device according to claim 1, wherein said memory cells are provided as a plurality of memory blocks (10'a...10'p), each memory block comprising third selection means (51), operatively connected to said second selection means (16), for selecting data from said at least two bit data selected by said second selection means (16) in response to a third address signal (SA,SB), and wherein the relationship between said third address signal (SA,SB) and the plurality of bit data selected by said third address signal is changed by said access direction signal. A device according to claim 1, wherein said second selection means (14) comprises a plurality of decode means (14b,14c;14d,14e;14f,14g) equal to a number of access directions (X,Y,Z) of said multidimensional data and a plurality of gate circuit rows (14X,14Y,14Z) equal to the number of said decode means, each gate circuit row (14X,14Y,14Z) including a plurality of gate groups (14X₁...14X₈,14Y₁...14Y₈,14Z₁...14Z₈) equal to a number of segments, each group having a plurality of transfer gates (TG₀...TG₂₅₅) equal to the number of data output from said second selection means (14), said plurality of transfer gates in each group in the gate circuit row being operatively connected to said bit lines (BL) in a predetermined relationship, one of said decode means (14b,14c;14d,14e;14f,14g) being activated in response to the access direction signal (DA₀,DA₁), and said activated decode means activating one of said gate groups corresponding to said activated decode means in response to the second address signal (CA₀...CA₄), so that said bit data in the access direction defined by the second address signal (CA₀...CA₄) and the access direction signal (DA₀,DA₁) are selected. A device according to claim 7, wherein said second selection means (14) further comprises a plurality of data bus means (20) equal to the number of the groups in each gate circuit row, each including a plurality of bus lines connected to output terminals of said transfer gates in corresponding groups of the different gate circuit rows. A device according to claim 7, wherein each of said decode means includes a first decoder (14b,14d,14f) and a second decoder (14c,14e,14g) and each group of each gate circuit row further includes a multiplexing gate (MG₁...MG₈) having a control terminal connected to one of a plurality of output terminals of said second decoder (14c,14e,14g) and an input terminal connected to output terminals of said gates (TG₀...TG₂₅₅), said first decoder (14b,14d,14f) activating one of said gates (TG₀...TG₂₅₅) in each group of a corresponding gate circuit row (14X₁...14X₈;14Y₁...14Y₈;14Z₁...14Z₈) in response to a part (CA₀,CA₁) of said second address signal, and said second decoder (14c,14e,14g) activating one of said multiplexing gates (MG₁...MG₈) in a corresponding gate circuit row in response to another part (CA₂...CA₄) of said second address signal. A device according to claim 1, wherein said second selection means comprises data bus means (20) including a plurality of bus lines equal to the number of said bit data to be output therefrom, and a plurality of decoder sets (16Dn) equal in number to said bit lines, each including a plurality of decoders (XDn,YDn,SDn) equal in number to said access directions (X,Y,S), each decoder in each decoder set (16Dn) having an input terminal operatively connected to the corresponding bit line and an output terminal connected to the bus line of said data bus means (20) in a predetermined relationship for outputting said bit data therefrom, one of said decoders (XDn,YDn,SDn) in each decoder set being commonly activated in response to the access direction signal (SX,SY,SS), and said activated decoders passing said data on said bit lines to said bus lines in response to the second address signal (B₀... B₃ ). A device according to claim 1, wherein said second selection means comprises data bus means (20) including a plurality of bus lines equal to the number of bits of data to be output therefrom, a plurality of decoders (18x,18y,18s), and a plurality of gate circuits (72x,72y,72s;73x,73y,73s) equal in number to said bit lines, each including a plurality of gates equal in number to said decoders, said gates in each gate circuit having input terminals commonly and operatively connected to the corresponding bit line, each gate in each gate circuit having a control terminal connected to a corresponding output terminal (O-F) of the corresponding decoder (18x,18y,18s), and an output terminal connected to the corresponding bus line of said data bus means, one of said decoders (18x,18y,18s) being activated in response to the access direction signal (SX,SY,SS), and said gates connected to said output terminal activating in response to said second address signal (B₀... B₃ ). A device according to claim 1, wherein each bit line has a plurality of subbit lines corresponding to the number k of access directions (X,Y,S) of said multidimensional data array, and wherein said second selection means comprises a first decoder (32), a second decoder (40), a plurality of bit selection gate circuit groups (72B,73B,74B) each having a plurality k of bit selection gates (72B A ,72B B ,...), a plurality of direction decoder groups (34) each having up to k decoders (72Sx,72Sy,72Ss), a plurality of transfer gate circuit groups (36) each having k transfer gates (72x,72y,72s), and a data bus means (20) including a plurality of bus lines equal to the number of bits (N) of said bit data to be selected, said bit selection gates (72B A ,72B B ,...) in each bit selection gate circuit group (72B,73B,74B) having input terminals operatively connected to said subbit lines discretely by k steps, output terminals commonly connected therebetween, and control terminals connected to output terminals of said first decoder (32), said transfer gates (72x,72y,72s) in each transfer gate circuit group (36) having input terminals commonly connected therebetween and connected to said common-connected output terminals of said corresponding bit selection gates (72B A ,72B B ,...), and output terminals connected to said bus lines in a predetermined relationship; said first decoder (32) outputting a first activating signal (A...D) at the output terminal thereof connected to said control terminals of said same bit selection gates (72B A ,72B B ,...) of the different groups to pass the data from each bit selection gate circuit group in response to a first selection signal (C₀,C₁); said second decoder (40) outputting a second energising signal to a corresponding one of said decoders (72Sx,72Sy,72Ss) in each direction decoder group (34) in response to a second selection signal (B₀...B₃); wherein one of said decoders (72Sx,72Sy,72Ss) in each direction decoder group (34) can be activated by a combination of said second activating signal (B₀...B₃) and the access direction signal (SX,SY,SS) and activating the corresponding one of said transfer gates (72x,72y,72s). A device according to claim 12, wherein said common decoders of said decoders (72Sx,72Sy,72Ss) in said direction decoder group (34), determined by said access directions (X,Y,S), are reduced to one, respectively. A device according to claim 1, wherein said second selection means further comprises a circuit for inputting a plurality of bit data to be stored from an external circuit and sending said input data to said bit lines. A device according to claim 1, further comprising a plurality of latch circuits (22a...22p;DLO...DLF) operatively connected between said bit lines (BL) and said second selection means (16'A). A device according to claim 1, further comprising a plurality of sense amplifiers connected between said bit lines and said second selection means. A device according to claim 1, wherein said memory cells comprise dynamic RAM cells. A device according to claim 1, wherein said memory cells comprise static RAM cells. A device according to claim 1, wherein said memory cells comprise ROM cells. A device according to claim 1, having a plurality of memory blocks, each memory block comprising: a memory cell array (10'a...10'p) containing some of said plurality of memory cells; said second selection means comprising a said first means (16A...16P) operatively connected to the memory cell array, a first data bus means (DBO... DBF ) operatively connected to the corresponding first means, and a said second means operatively connected to said first means through said first data bus means; and wherein the device further comprises a second data bus means (20A) operatively connected in common to the second means of said second selection means of each block, each of said first data bus means having at least two bus lines, equal in number to a number of bits of data to be selected, each of said first means including a plurality of selection circuits (51) connected therebetween and connected to said bus lines of the corresponding first data bus means, in a relationship for receiving a plurality of data on said bit lines and outputting said bit data selected from said received data in response to a first selection signal supplied to said first means and in accordance with said connection relationship, and said second means outputting bit data selected from the bit data on said first data bus means in response to a second selection signal (SA,SB) to said second data bus means (20A). A device according to claim 20, wherein adjacent two (e.g.16A,16B) of said first means (16A,16P) are reduced to one for commonly using two adjacent ones of said memory cell arrays (10'a...10'p). A device according to claim 20, wherein said first means (16A...16P) further comprises a circuit (94A) for inputting a plurality of bit data to be stored from an external circuit and sending said input data to said bit lines. A device according to claim 20, wherein said first means (16A...16P) further comprises a plurality of latch circuits operatively connected to said bit lines. A device according to claim 20, wherein each memory block comprises a plurality of sense amplifiers connected to said bit lines (BL) and outputting amplified data signals to said first means. A device according to claim 1, having a plurality of memory blocks each comprising a memory cell array (10"a,10"b) containing some of said plurality of memory cells (MC); the device further comprising: data bus means (20a,20b) operatively connected to said first means (16) of said second selection means and having at least two bus lines, equal in number to a number of bits of data to be selected, said first means (16) including a plurality of selection circuits connected therebetween and connected to said bus lines, in a relationship for receiving a plurality of data on said bit lines and outputting said bit data selected from said received data in response to a first selection signal supplied to said first means and in accordance with said connection relationship, said plurality of selection circuits being consecutively operated to receive data from the memory cell array (10"a,10"b)continuously accessed prior to said operation of said first means. A device according to claim 25, wherein said first means (16) further comprises a circuit for inputting a plurality of bit data to be stored from an external circuit and sending said input data to said bit lines. A device according to claim 25, wherein said first means (16) further comprises a plurality of latch circuits (16a) operatively connected to said bit lines. A device according to claim 25, wherein each memory block comprises a plurality of sense amplifiers connected to said bit lines and outputting amplified data signals to said first means. A device according to claim 1, wherein said memory cells (MC) are organised in a plurality of memory means; said first means of said second selection means comprises a plurality of sets of first selectors, the first selectors in each set being operatively connected to a corresponding one of the memory means; a plurality of said first data bus means are provided, each operatively connected to the corresponding first means; said second means of said second selection means comprises a plurality of second selectors operatively connected to said first means through a first data bus means; a second data bus means (20A') is provided, operatively connected to said plurality of second means, each of said first data bus means having a plurality of bus lines equal in number to said at least two bit data to be selected, each of said first means including a plurality of selection circuits connected therebetween and connected to said bus lines of the corresponding first data bus means, in a relationship for receiving a plurality of bit data on said bit lines and outputting said bit data selected from received data in response to a first selection signal supplied to said first means and in accordance with said connection relationship, said selectors of said first means being consecutively operated to receive data from said memory means continuously accessed prior to said operation of said first means, and said selectors outputting bit data selected from said bit data on said first data bus means in response to a second selection signal (SA,SB) to said second data bus means (20A'). A device according to claim 29, wherein said first means further comprises a circuit (24A) for inputting a plurality of bit data to be stored from an external circuit and sending said input data to said bit lines (BL). A device according to claim 29, wherein said first means further comprises a plurality of latch circuits operatively connected to said bit lines (BL). A device according to claim 29, wherein each memory means comprises a plurality of sense amplifiers connected to said bit lines (BL) and outputting amplified data signals to said first means.

Inventors: KOBAYASHI, KAZUYA, MIYASAKA, KIYOSHI, OGAWA, JUNJI BERUMEZON ICHIGAO 102
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C7
IPC codes: G11C8, G11C7