A TIME DELAY CIRCUIT FOR A SEMICONDUCTOR DEVICE

Abstract: A plurality of time delay circuits (1-1, 1-2,...), usually a dummy word line made similarly to a word line having a delay characteristics for charging and discharging, are provided in a memory device in place of a single delay circuit of prior art. A selection circuit (11) selectively drives one of the delay circuits (1-1, 1-2,...) and enables a gate connected to the driven delay circuit (1-1, 1-2,...) in a circulating sequence each time an input pulse is received. A gate circuit 12 detects a moment at which the output voltage of the dummy word line reaches a threshold level and then outputs an enabling signal to the readout sense amplifier. A noise coming-in closely before a normal signal is led to a delay circuit (1-1, 1-2,...) but disabled by the normal signal, thus having no effect on the signal. So, the invention is effective when the input signal is from an address transition detector (10) which, used in an asynchronous memory device, is apt to produce the above-described type of noise. And further, immediately after an enabling signal is outputted, a next address change is acceptable, because the next delay circuit is ready to function without being disturbed by the remaining voltage in the previously used delay circuit. Thus, both the increased speed of memory cycling and the increasedscale of integration can be achieved at the same time.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a time delay circuit used in a semiconductor device, and particularly to reducing malfunction caused by noise as well as to speeding up the semiconductor device. Description of the Related Art A time delay circuit, which produces an output signal S o at a predetermined delay time t₁ measured after an application of an input signal S i on its input terminal, has been used in semiconductor devices. Among some types of time delay circuits, there is a CR (Capacitance, Resistance) type, in which the input signal S i is applied via a resistor R to a capacitor C and a voltage V c slowly produced on the capacitor C is detected by a logical gate circuit G at a predetermined threshold level V th for outputting delayed signal S o , as shown in FIG. 1 and FIGs. 2A-2D using positive pulses. In this type, if a noise pulse, N₁ etc., which is usually short, is inputted to the time delay circuit 1, the noise pulse charges the time delay circuit 1. And before the charge is completely discharged, if an input signal pulse S i is inputted, the voltage V c on the capacitor C rises to the threshold level V th after a period T₂ which is shorter than the normal delay period T₁, resulting in malfunction of the time delay circuit, as shown in FIGs. 3A-3C. This kind of noise pulses are very possible for the delay circuit 1 in a semiconductor device. On the other hand, this type of delay circuit can not accept a next input signal until the charge in the delay circuit is completely discharged, because of the same reason that the voltage V c of the capacitor rises and reaches the threshold level V th earlier than the normal delay period T₁, thus a malfunction is caused. In order to solve this problem, there may be provided with a circuit which compulsively discharge the residual charge in the capacitor as soon as the delayed signal is outputted. However, this measure is not effective for some type of CR delay circuit, such as distributed CR delay circuit, i.e. a dummy word line which is made similarly to a word line of a semiconductor memory device. The word line of a semiconductor IC memory is generally made of relatively high electrically resistive material, such as polycrystalline silicon. And further, the word line has relatively large stray capacitance along each line. Thus, the word line, i.e., the dummy word line, forms a distributed CR delay circuit. The distributed delay circuit takes some time not only for charging up the capacitances but also for discharging the capacitances, so the compulsive discharging is not effective for the distributed CR delay circuit. And the larger the scale of integration is attempted, the finer, i.e., the more resistive, the word line is becoming thus requiring more time to charge and discharge. And also, the higher cycle speed is required in a memory device, the more serious becomes this problem. Therefore, an improved delay circuit which is less susceptive to noise inputs and is quicker to be ready to accept next input signal after completion of a delaying operation has been requested. US-A-3,675,049 discloses a device for delaying the bits of a serial data stream particularly suitable for producing a variable delay for a large number of bit times. The bits of the incoming data stream are sequentially applied to the inputs of a number of parallel delay channels by a bit distributor. The outputs of all delay channels are logically "OR"ed. together to reform the data stream. The distributor advances only after a "one" has been applied to a delay channel. EP-A-0 167 275 discloses a semiconductor memory device comprising an address change detection circuit and a pulse witdh control circuit. The pulse width control circuit inhibits the passage of write enable signals having a short pulse width predetermined time period after a change of address has occurred. SUMMARY OF THE INVENTION It is a general object of the invention to provide a time delay circuit which can reduce the malfunction caused by an input noise signal as well as can reduce memory cycling time in an increased scale of integration. This object is solved by the features of claim 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a time delay circuit. FIG. 2 is a circuit diagram of a CR type delay circuit. FIGs. 2B-2C are timing diagrams for explaining delay function of the CR type delay circuit. FIG. 3A-3C are timing diagrams for explaining malfunction of the CR type delay circuit. FIG. 4 is a bolck diagram of an embodiment of the present invention. FIG. 5 is a block diagram of a semiconductor memory device having a time delay circuit of the present invention. FIGs 6A-6Q are timing diagrams for explaining the operation of the semiconductor memory device shown in FIG. 5. FIG. 7 is a circuit diagram of AND gates associated with a dummy word line shown in FIG. 5. FIG. 8 is a circuit diagram of a counter in a selector circuit. FIGs. 9 is a circuit diagram of the decoder circuit shown in FIG. 5. FIGs. 10A-10F are timing diagrams for explaingng the influence of noise signal. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiment of the present invention referring to FIG. 4 and an application to a semiconductor memory device in FIG. 5 shall be described hereinafter in detail. FIG. 4 is shown using a positive input signal pulse, but FIG. 5 is shown using negative input signal pulses. The timing diagrams for FIG. 5 are shown in FIGs. 6A-6Q. In these embodiments, four delay circuits 1-1 through 1-4 are provided. EAch of delay circuits 1-1' through 1-4' of FIG. 4 includes each of the delay circuits 1-1 through 1-4 of FIG. 5 and each of AND gates 17-1 through 17-4 respectively at each input terminal of the delay lines 1-1 through 1-4. Therefore, description shall be made for the circuit of FIG. 5, which can explain the operation of the circuit in FIG. 4. Each time an input signal S i as well as a noise signal is inputted to the selection circuit 11, one of the outputs g₁-g₄ of a decoder 16 therein is selectively activated. Each output of the decoder 16 is operatively connected to one of the delay circuits 1-1 - 1-4. Thus, one of the delay circuits 1-1 - 1-4, for example the delay circuit 1-1, is selectively activated by the decoder 16. At this time, an AND gate 13-1, in a gate circuit 12, connected to the output terminal of the selected delay circuit 1-1 is enabled by the activated decoder's output g ₁. When a delayed signal i ₁ is outputted from the delay circuit 1-1, the AND gate 13-1 outputs the signal j ₁ to an OR gate 14 in the gate circuit 12, which outputs a delayed signal S o . In this state, a next input signal b ₂ comes in to the selection circuit 11 as shown in FIG. 6B. Then, the selection circuit 11 selectively activates the second delay circuit 1-2 as well as discontinues to drive the previous delay circuit 1-1 by lowering the driving voltage of the output g ₁ down to L. The output circuit of the selection circuit 11 is made up to be able to sink a current from its load, as a widely used common technique, so the charge in the delay circuit 1-1 begins to be discharged through the output circuit of the selection circuit 11 when this delay circuit is switched to "not-driven". At the same time, the AND gate 13-1 connected to the output terminal of previous delay circuit 1-1 is disabled, so that the previously used delay circuit 1-1 does not disturb other output signals i ₂ etc. from other delay circuits 1-2 etc.. The selectively driven delay circuit 1-2 operates in the same way as the first delay circuit 1-1. The third and fourth input signals are respectively processed in the same way as above-described first and second inputs. However, the fifth input signal (not shown in the figure) is led to drive the first delay circuit 1-1 again, which is already discharged completely. This is because, in these embodiments where four delay circuits are provided, the counter 15 is chosen to be a divide-by-four counter to select four different outputs, so after counting a value four, the count returns back to value one. Thus, one of four outputs g₁-g₄ of the decoder 16, each output terminal of which is connected to each of the delay circuits 1 and each AND gate 13, is selected in circulating sequence, each time a signal or a noise is inputted to the counter 15. Description of the timing chart FIGs. 6A-6Q shall be made later in detail. Further more in detail, main practical circuits of the embodiment of the delay circuit 1-1, the selection circuit 11 and the gate circuit 12 are described and referred to FIG. 7 through FIG. 9, though the circuit techniques employed are all well known. The circuit figures are all described with MOS (Metal Oxide Semiconductor) and CMOS (Complementary MOS) transistors. Description of details of each MOS and CMOS transistor is omitted because they all are well known. R and C in FIG. 7 denote respectively a resistance and a capacitance per unit length of the dummy word line, composing a distributed CR delay line. A basic binary counter used in the counter circuit 15 is shown in FIG. 8. Firstly, the negative signal pulse b from the ATD is converted to C₀ and its complement C ₀, which are applied to the terminals denoted by C₀ and C ₀ respectively. Each time the negative input signal pulse b is applied twice, the output Q₁ and its complement Q ₁ are outputted. Therefore, a same basic binary counter, additionally connected in cascade to the first one, receiving Q₁ and Q ₁ as its inputs, can produce output signals Q₂ and its complement Q ₂, each time the input signal pulse b is inputted four times to the first basic binary counter. The decoder circuit 16 is composed of four decoder units 16-1 - 16-4 shown by the boxes in FIG. 9. For example, the decoder unit 16-1 in FIG. 9 is a NOR gate, whose inputs are Q₁ and Q₂ and the output terminal g₁ is connected to an input terminal of an AND gate 17-1 connected to the delay circuit 1-1. When both of Q₁ and Q₂ are L (low level), the output g₁ becomes H (high level), thus selects the delay circuit 1-1. The blank units of 16-2 to 16-4 contain the same circuit as in the box of 16-1, but the inputs to each unit are of different combinations of two L level signals out of the four output signals, Q₁ through Q ₂, of the counter so that each unit activates different delay circuit respectively. Thus, the decoder 16 selectively drives one of the delay circuits 1-1 - 1-4 in sequence depending on the counted value of the counter 15. In FIG. 7 are shown practical circuits of AND gates 17-1, optionally included in the selection circuit 11. Inputs to the AND gate 17-1 are the input signal b and the output from the decoder 16-1. The output of the AND gate 17-1 is connected to the input terminal of the delay circuit 1-1 as described above. The AND gate 17-1 is composed of a NAND gate and an inverter, and is provided for initiating input signal to the delay circuit 1-1 by a rising edge of the negative input signal b ₁. The driver stage of the AND gate 17-1 is composed of a single-ended push-pull configuration, therefore, the output terminal can sink the charge in the delay line when the output level is L. The AND gates 13-2 - 13-4 and the NOR gate 14 in the gate circuit 12 are also composed similarly in a very general way. An application of the present invention to an asynchronous semiconductor memory device, is shown in FIG. 5, where the delay circuits 1-1 through 1-4 are made similarly to the word lines. The input signal b is output of an address transition detector 10 (referred to hereinafter as ATD). The ATD 10 outputs a pulse signal b each time it detects a transition of X-address signals. The output k of the gate circuit 12 is an enabling signal to enable a sense amplifier which reads out datum scored in the addressed word line via bit lines. The timing of enabling the sense amplifier is at the time just after one of the word lines is charged high enough to be readed out, because the delay circuit 1 has essentially similar delay time to that of the word line. The names of the graphs in the diagram FIGs. 6A-6Q are corresponding to the names of signals in the figures. A negative pulse is used for the input signal b ₁ as shown in FIG. 6B. When AND gates 17-1 and 13-1 are enabled by the output g₁ of the decoder 16, signal i ₁ rises gradually after the application of the input signal h₁ as shown in FIGs. 6E, 6F and 6G, because this graph shows the case where the delay circuit is of CR type. And, when the signal i ₁ reaches the threshold level V th of the AND gate 13-1, the AND gate 13-1 outputs the signal j ₁. Operation of the circuits for the inputs coming later than the third input b ₄ are not shown in FIGs. 6A-6Q, however, the fifth signal b ₅ is processed in the same way as those of the first input signal b ₁. The ATD is apt to output a short noise pulse closely before a normal input signal, when the address signals change in some particular condition. However, according to the present invention, this noise does not effect operation of the delay circuit for the following normal signal, as is described below, referring to FIG. 10. When a noise pulse n , usually short and closely before a normal input signal b ₁, is inputted to the selection circuit 11, the noise n is processed by the selection circuit 11 in the same way as that of a normal signal from the ATD, thus the noise signal n is led to select and drive one of the delay circuits, for example 1-1, in the circulating sequence. However, this noise pulse n can not produce its output signal from the selected delay circuit 1-1, because the next input signal b ₁ coming-in just after the noise pulse n is processed by the selection circuit to switch off the delay circuit 1-1 before the delayed output voltage i ₁ of the delay circuit 1-1 reaches the threshold level V th , and to selectively drive the next delay circuit 1-2. Thus the signal b ₁ is correctly outputted from the gate circuit 12 without being disturbed by a remaining charge of the noise in the previously used delay circuit 1-1. In order to ensure to process the short noise, a wave-form shaping circuit, such as a one-shot multi-vibrator, (not shown in the figure) may be provided at the input of the selector circuit 11. Thus, a malfunction caused by noise is removed by the circuit configuration according to the present invention. Another advantage of the present invention is speeding up the cycle time of memory access, as below-described. Even immediately after completing one cycle of delaying operation of an input signal b ₃ for example, the circuits can be ready to accept the next incoming input signal b ₄. It is because the next incoming signal b ₄ is processed by the selection circuit 11 to drive the next delay circuit 1-4 without being disturbed by the remaining charge in the previously used delay circuit 1-3 whose output is already disabled by its AND gate 13-3. Thus, the memory cycling time can be reduced down to as short as the memory access time. Although, four of the delay circuits are referred to in the above-described embodiments, other quantity, such as two, may be chosen as long as the circuit is properly designed so that the remaining charge in the delay circuit is substantially zero when the delay circuit is selected again by a new input signal. The timing for initiating driving, i.e. charging, a selected delay circuit, and the threshold level V th of the gate circuit 12, i.e. the voltage level at which the enabling signal for the sense amplifier is to be outputted, are both in relation to the timing in the circuits associated with the word lines and bit lines. Therefore, the method to obtain the timing described in the above-described embodiment is only an example, so other timing may be chosen depending on the used circuit. If the driving of the selected delay circuit is not initiated directly by the input signal pulse b , the AND gates 17 are not necessary. Although in the above-described embodiment the delay circuit is made of distributed CR line similar to a word line, a digital delay circuit, such as a mono-stable multi-vibrator, or a series connection of inverters is also applicable to the delay circuit. In the above-described embodiment for the asynchronous memory device, the input signal is an output from the ATD, however, if the memory device is of synchronous type, the input signal can be replaced by clock pulse. Although the time delay circuit in the above-described embodiment is for obtaining a timing of charging word line, it is apparent that the time delay circuit according to the present invention can be employed for obtaining a timing of charging bit line, too, if needed. Embodying the present invention, a 1 M bit CMOS EPROM (Erasable Programmable Read Only Memory) having an access time 100 ns, and cycle time 100 ns is materialized. The percentage of area occupied by the added circuit according to the invention is order of 0.1%, which is quite negligible and requiring little cost increase. The many features and advantages of the invention are apparent from the detailed specification and thus, it is intended by the dependent claims to cover such features and advantages of the system which fall within the scope of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation shown and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

Claims: A semiconductor device comprising a plurality of delay circuits (1-1, 1-2...) connected in parallel with their first inputs to an input signal (Si) for delaying said input signal having a first level and a second level; a selection circuit (11) connected to said input signal (Si) and having outputs each operatively connected to a second input of one of said delay circuits (1-1, 1-2...) for selecting one of said delay circuits (1-1, 1-2...), in sequence, in response to a transition from the first level to the second level of the input signal; and a gate circuit (12), whose first input terminals are operatively connected to the outputs of said delay circuits (1-1, 1-2...), characterized in that the outputs of said selection circuit (11) are connected to second input terminals of said gate circuit (12) for outputting a delayed input signal (Si) from said selected one of said delay circuits and that the delay circuits (1-1,1-2,...) output signals having the same signal width as said input signal (Si). A semiconductor device according to claim 1, characterized in that said selection circuit (11) includes: a counter (15) for receiving said input signal (Si); a decoder (16) connected to said counter (15) for decoding outputs from said counter (15); a gate means (17-1, 17-2,...) having a first input connected to said input signal and a second input connected to the output of said decoder (16); and that each of said delay circuits (1-1, 1-2,...) has only one input which is connected to the output of said gate means (17-1,...). A semiconductor device according to claim 1 or 2, characterized in that said gate circuit (12) includes AND gates (13-1, 13-2,...) and OR gate (14). A semiconductor device according to any one of claims 1 to 3, characterized in that said semiconductor device further includes a memory circuit having an address transition circuit (10) for detecting a transition of address signals, said address transition circuit outputting said input signal (Si) upon detecting said transition of address signals; and said gate circuit (12) has its output operatively connected to said memory circuit and supplies said delayed input signal as a control signal to said memory circuit. A semiconductor device according to claim 4, characterized in that said memory circuit further comprises word lines; and a plurality of dummy word lines, as said delay circuits, having a similar delay characteristics to said word lines.

Inventors: TAKEUCHI, ATSUSHI
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C7
IPC codes: G11C7, H03K5, G06F1, G11C11, G11C5, G11C8, H03K17