STATIC SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED PULL-UP OPERATION FOR BIT LINES

Abstract: In a semiconductor memory device in which static memory cells are provided at each of the intersections between word lines (WL₀, WL₁,...) and bit line pairs (BL₀, BL₀, ...), a pull-up operation for non-selected bit lines is the same during a read mode as during a write mode, thus stabilizing the state of the cells.

Description: The present invention relates to a static semiconductor memory device, and more particularly, to an improvement of a pull-up operation for bit line pairs. In general, in a metal-oxide-semiconductor (MOS) static memory device, static memory cells are provided at each intersection of word lines, and bit line pairs. All the bit lines are connected via load transistors to a power supply, and in this case, the load transistors serve as pull-up means for the bit line pairs. When a word line and a bit line pair are selected to read data from a memory cell at the intersection thereof, a load current flows through the memory cell. In this case, also in the non-selected memory cells (hereinafter, referred to as half-selected cells) connected to the selected word line, similar load currents flow therethrough. However, no load currents flow through the non-selected cells connected to the non-selected word lines. Further, when writing data into the selected memory cell, one bit line of the selected bit line pair is pulled down to a level such as the ground level, so that a large load current flows through a path including the one bit line, thus increasing the power consumption during a write-mode. In order to reduce the above-mentioned power consumption during a write mode, a static semiconductor memory device is known from Yamamoto et al. "A 256KCMOS SPRAM with Variable Impedance Loads", ISSCC DIGEST OF TECHNICAL PAPERS, P. 58, 59, Feb. 1985. In this static memory device, however, there is a possibility that the contents of the next half-selected memory cells will be reversed, which will be later explained in detail. In GB-A-2163616 a memory device according to the preamble of claim 1 is disclosed. In this device each bit line pair may be selectively short-circuited to reduce the potential between the lines to increase the speed of the memory device. An object of the present invention is to provide a static semiconductor memory device which carries out a pull-up operation while stabilizing the state of the memory cells. According to the present invention, a semiconductor memory device comprises: static memory cells, provided at each intersection between a plurality of word lines and a plurality of bit line pairs; suppressing means provided at each of said bit line pairs, for suppressing the reduction of the potential of the lower level bit line of each bit line pair; word line selection means for selecting one of the word lines; bit line pair selection means for selection one bit line pair and prohibiting the suppressing operation of the reduction of the potential of the lower level bit line of that pair by the suppressing means, characterised in that the suppressing means includes: a connection line provided at the bit line pairs; and, a plurality of transistors, connected between the bit line pairs and the connection line, the transistors being turned ON when the corresponding bit line pairs are not selected by the bit line pair selection means, wherein said connection line is in a floating state when all of said transistors are turned OFF. The present invention will be more clearly understood from the description as set forth below, and in contrast with the prior art, with reference to the accompanying drawings, in which:- Figures 1 and 3 are circuit diagrams illustrating prior art static semiconductor memory devices; Figure 2 is a partial detailed diagram of Figure 1; and, Figures 4, 5 and 6 are circuit diagrams illustrating embodiments of the static semiconductor memory device according to the present invention. First, the prior art static semiconductor memory devices will be explained with reference to Figures 1 to 3. In Figure 1, which illustrates a prior art static semiconductor memory device, static memory cells, C₀₀, C₀₁ , ..., C n-1,n-1 are provided at each intersection of word lines WL₀ , WL₁ , ..., and WL n-1 and bit line pairs BL₀ , BL ₀ ; BL₁ , BL ₁ ; ...; and BL n-1 , BL n-1 . One word line and one bit line pair are selected by row selection signals X₀ , X₁ , ..., and X n-1 of a row address decoder RD and column selection signals Y₀ , Y₁ , ..., and Y n-1 of a column address decoder CD, i.e., one memory cell is selected. In Fig. 1, column selection gates Q B0 , Q B0 ′; Q B1 , Q B1 ′; ...; and Q B,n-1 , Q B,n-1 ′ are controlled by the column selection signals Y₀, Y₁ , ..., and Y n-1 . All the bit lines BL₀ , BL ₀ , BL₁ , BL ₁, ..., BL n-1 , BL n-1 are connected via load transistors Q L0 , Q L0 ′, Q L1 , Q L1 ′, ..., and Q L,n-1 , Q L,n-1 ′ to a power supply V CC , and are also connected via column selection gates Q B0 , Q B0 ′, Q B1 , Q B1 ′, ..., Q B,n-1 , Q B,n-1 ′ to a sense amplifier SA (output buffer OB) and a write amplifier WA. DB and DB designate data buses, D out an output data, and D in an input data. As illustrated in Fig. 2, the memory cells C₀₀, C₀₁ , ... of Fig. 1 comprise loads R₁ and R₂ (resistors, drain-gate connected enhancement type N-channel transistors, or source-gate connected depletion type N-channel transistors), and a pair of cross-coupled transistors Q₁ and Q₂. In Fig. 2, when the memory cell C₀₀ is selected in order to read data therefrom, the row selection signal X₀ is made high and the column selection signal Y₀ is made high. As a result, in the selected cell C₀₀ , if the transistors Q₁ and Q₂ are turned ON and OFF, respectively, a load current I L0 flows. In this case, also in the non-selected cells (hereinafter, referred to as half-selected cells) connected to the selected word line WL₀ , similar load currents I L1 flow therethrough. However, no load currents flow through the non-selected cells C₁₀ and C₁₁. Further, when writing data into the memory cell C₀₀ , one of the selected bit lines BL₀ and BL ₀, such as the bit line BL₀ is pulled down to a V SS level, so that a large load current flows through a path V CC → Q L0 → BL₀ → DB. Therefore, a problem arises in that the power consumption during a write mode is increased. In order to reduce the above-mentioned power consumption during a write mode, a static semiconductor memory device as illustrated in Fig. 3 is known (see Yamamoto et al. "A 256KCMOS SRAM with Variable Impedance Loads", ISSCC DIGEST OF TECHNICAL PAPERS, P. 58, 59 Feb. 1985). That is, in Fig. 3, load transistors Q L0 ″, Q L0 ‴, Q L1 ″, Q L1 ‴, ..., Q L,n-1 ″, Q L,n-1 ‴ controlled by a write enable signal WE are added to the load transistors Q L0 , Q L0 ′, Q L1 , Q L1 ′, ..., and Q L,n-1 , Q L,n-1 ′ which serve as steady pull-up means. Therefore, during a read mode ( WE = "1"), load currents from the transistors Q L0 ″, Q L0 ‴, Q L1 ″, Q L1 ‴, ..., Q L,n-1 ″, Q L,n-1 ‴ in addition to load currents from the transistors Q L0 , Q L0 ′, Q L1 , Q L1 ′, ..., And Q L,n-1 , Q L,n-1 ′ are supplied to the bit lines BL₀ , BL ₀ , BL₁ , BL ₁ , ..., and BL n-1 , BL n-1 . During a write mode ( WE = "0"), only load currents from the transistors Q L0 , Q L0 ′, Q L1 , Q L1 ′, ..., Q L,n-1 , Q L,n-1 ′ are supplied to the bit lines BL₀ , BL ₀ , BL₁ , BL ₁ , ..., BL n-1 , BL n-1 . Note that the size of the transistors Q L0 , Q L0 ′, Q L1 , Q L1 ′, ..., and Q L,n-1 , Q L,n-1 ′ can be reduced compared with those of Fig. 1. Therefore, during a write mode, the load current supplied to one of the selected bit lines such as BL₀ and BL ₀ can be reduced, compared with the device of Fig. 1. In the circuit of Fig. 3, however, since the load current supplied to the non-selected bit lines BL₁ , BL ₁ , ..., and BL n-1 , BL n-1 is smaller during a write mode than during a read mode, a problem arises in that the contents of the non-selected cells may be reversed. For example, it is assumed that a write operation is performed upon the memory cell C₀₀. Then, the row selection signal X₀ and the column selection signal Y₀ are made high, and in addition, one of the selected bit lines such as BL₀ is made low and the other BL ₀ is made high, thus performing a write operation upon the memory cell C₀₀. At this time, the half-selected cells C₀₁, C₀₂, ..., and C 0,n-1 are also connected to the respective bit lines BL₁, BL ₁, BL₂, BL ₂, ..., and BL n-1 , BL n-1 . Therefore, for example, in the memory cell C₀₁, if the left-side transistor Q₁ is turned ON and the right-side transistor Q₂ is turned OFF, a pull-up operation for the bit lines BL₁ and BL ₁ is carried out by only the transistors Q L1 and Q L1 '. Therefore, the potential at the bit line BL₁ may be excessively reduced. As a result, when the selected word line is transferred from WL₀ to WL₁, the transistor Q₁ of the half-selected cell C₁₁ is forcibly turned OFF, regardless of the state thereof, thereby turning ON the transistor Q₂. That is, there is a possibility that the contents of the next half-selected memory cells will be reversed. Figure 4 illustrates a first example of the present invention in which the load transistors Q L0 , Q L0 ', Q L1 , Q L1 ', ..., Q L,n-1 , Q L,n-1 ' act as the pull-up means of Figure 1. In Fig. 4, a connection line L and transistors Q L0 ", Q L0 "', Q L1 ", Q L1 "', ..., Q L,n-1 ", Q L,n-1 "' (in this case, P-channel transistors) between the line L and the bit lines BL₀, BL ₀, BL₁, BL ₁, ..., and BL n-1 , BL n-1 are provided. Further, these transistors Q L0 ", Q L0 "', Q L1 ", Q L1 "', ..., and Q L,n-1 ", Q L,n-1 "' are controlled by the column selection signals Y₀, Y₁, ..., and Y n-1 . That is, in this case, the common connection line L holds the mean potential of all the bit lines (precisely, the non-selected bit lines), and equalizes the potentials of all the non-selected bit lines. Note that the size of the load transistors Q L0 , Q L0 ', Q L1 , Q L1 ', ..., Q L,n-1 , Q L,n-1 ', can be reduced compared with those of Fig. 1. In Fig. 4, when the bit lines BL₀ and BL ₀ are selected, the column selection signal Y₀ is high and the other column selection signals Y₁ to Y n-1 are low. Therefore, the transistors Q L0 " and Q L0 "' are turned OFF and the transistors Q B0 and Q B0 ' are turned ON, so that the bit lines BL₀ and BL ₀ are connected to the data buses DB and DB , respectively. In a write mode, when the data bus DB is caused to be low by the write amplifier WA, a current flows through a path: Q LO → BL₀ → Q B0 → DB. Even in this case, however, the power consumption can be reduced due to the reduced size of the load transistors Q LO and Q LO ′ as compared with the prior art. On the other hand, all the transistors Q B1 , Q B1 ′, ... , and Q B,n-1 , Q B,n-1 ′ are turned OFF and all the transistors Q L1 ″, Q L1 ‴, ..., and Q L,n-1 ″, Q L,n-1 ‴are turned ON. As a result, the non-selected bit lines BL₁ , BL ₁ , ..., BL n-1 , BL n-1 are commonly connected by the connection line L, and therefore, the potentials of these non-selected bit lines are equalized. The advantage of provision of the connection line L will be explained. In Fig. 4, if the size of the load transistors Q LO , Q LO ′, ..., and Q L,n-1 , Q L,n-1 ′ is reduced, the pull-up power for the bit lines is small. Therefore, when the bit lines BL₀ and BL ₀ are changed from a selected state to a non-selected state after one of the bit lines such as BL₀ is caused to be low by the write amplifier WA, the bit line BL₀ is not rapidly pulled up by the load transistors Q LO and Q LO ′. In Fig. 4, however, the lower potential at the bit line BL₀ is pulled up by the potential at the connection line L due to the change of the transistors Q LO ″ and Q LO ‴ from an OFF state to an ON State. Note that the potential at the connection line L is always relatively high, since a mean value of the potentials at the non-selected bit lines are higher than a mean value of the potentials at the selected bit lines. In this case, the total load currents in the non-selected bit lines are the same during a read mode as during a write mode. Thus, also in the circuit of Fig. 4, during a write mode, the load currents in the selected bit lines are reduced, thus improving the power consumption, and the load currents in the non-selected bit lines are the same during a read mode as during a write mode. As a result, in the non-selected bit lines, even when the half-selected cells are changed, there is little possibility that the data of the previous half-selected cells will rewrite the data of the next half-selected cells. In a second example of a semiconductor memory device according to this invention, as shown in Figure 5, in addition to the connecting line of the first example, the semiconductor memory also includes load transistors Q L0 , Q L0 ', Q L1 , Q L1 ', ..., Q L,n-1 , Q L,n-1 ' as the pull-up means of Fig. 1 which are controlled by the column selection signals Y ₀, Y ₁, ..., and Y n-1 . That is, no load current is supplied to the bit lines such as BL₀ and BL ₀ when the level of the inverted column selection signal Y ₀ is low. In this case, during a read mode, the selected Bl₀ and BL ₀ are connected by the column selection gates Q B0 and Q B0 ' to the data buses DB and DB , and accordingly, the selected bit lines BL₀ and BL ₀ are pulled up by the pull-up means incorporated into the sense amplifier SA. Also, during a write mode, one of the data buses DB and DB is made low and the other is made high by the write amplifier WA, and accordingly, a write operation is performed upon the selected cell such as C₀₀ by the data buses DB and DB , the column selection gates Q B0 and Q B0 ', and the bit lines BL₀ and BL ₀. On the other hand, since the transistors Q L1 , Q L1 ', ..., and Q L,n-1 , Q L,n-1 ' are turned ON when the inverted column selection signals Y ₁, ..., and Y n-1 are high. Therefore, load currents are supplied to the non-selected bit lines such as BL₁, BL ₁, ..., and BL n-1 , BL n-1 . Also, in this case, the load currents are the same during a write mode as during a read mode. Thus, in the circuit of Fig. 5, during a write mode, the load currents in the selected bit lines are reduced, thus reducing the power consumption, and the load currents in the non-selected bit lines are the same during a read mode as during a write mode. As a result, in the non-selected bit lines, even when the half-selected cells are changed, there is little possibility that the data of the previous half-selected cells will rewrite the data of the next half-selected cells. Figure 6 illustrates a third example of the present invention. In addition to the connecting line L of the first embodiment, the semiconductor memory also includes bit line short-circuiting transistors Q S0 , Q S1 , ..., Q S,n-1 (in this case, P-channel transistors) which are provided for each pair of the bit line pairs BL₀, BL ₀, BL₁, BL ₁; ...; and BL n-1 , BL n-1 , and these transistors Q S0 , Q S1 , ..., and Q S,n-1 are controlled by the column selection signals Y₀, Y₁, ..., and Y n-1 . In Fig. 6, both in the selected and non-selected bit lines, load currents are supplied from the transistors Q L0 , Q L0 ', Q L1 , Q L1 ', ..., and Q L,n-1 , Q l,n-1 '. In the selected bit lines BL₀ and BL ₀, the transistor Q S0 is turned OFF, and in the non-selected bit lines BL₁, BL ₁, ..., and BL n-1 , BL n-1 , the transistors Q S1 , ..., and Q S,n-1 are turned ON, thus equalizing the potential between each pair of the non-selected bit line pairs. Thus, also in the circuit of Fig. 6, in the non-selected bit lines, even when the half-selected cells are changed, there is little possibility that the data of the previous half-selected cells will rewrite the data of the next half-selected cells. In Fig. 6, the potential at the lower bit lines of the non-selected bit line pairs are further increased, to avoid the reversion of the contents of the next half-selected cells. Note that, in the above-mentioned embodiments, the type of transistors is not limited, and of course, P-channel type transistors and N-channel type transistors can be used as occasion demands. As explained above, according to the present invention, the power consumption can be reduced, and in addition, since the load currents in the non-selected bit lines, i.e., the pull-up power, is the same, during a read mode as during a write mode, even when the half-selected cells are changed in the non-selected bit lines, there is little possibility that the data of the previous half-selected cells will rewrite the data of the next half-selected cells, thus avoiding the reversion of the contents of memory cells.

Claims: A semiconductor memory device comprising: static memory cells (C₀₀, C₀₁, ...), provided at each intersection between a plurality of word lines (WL₀, WL₁, ...) and a plurality of bit line pairs (BL₀, BL ₀, ...); suppressing means provided at each of said bit line pairs, for suppressing the reduction of the potential of the lower level bit line of each bit line pair; word line selection means (RD) for selecting one of the word lines; bit line pair selection means for selection one bit line pair and prohibiting the suppressing operation of the reduction of the potential of the lower level bit line of that pair by the suppressing means, characterised in that the suppressing means includes: a connection line (L) provided at the bit line pairs; and, a plurality of transistors (Q L0 ", Q L0 "', ..., Q L,n-1 ", Q L,n-1 "'), connected between the bit line pairs and the connection line, the transistors being turned ON when the corresponding bit line pairs are not selected by the bit line pair selection means, wherein said connection line (L) is in a floating state when all of said transistors (Q L0 ", Q L0 "', ..., Q L,n-1 ", Q L,n-1 "') are turned OFF. A device according to claim 1, wherein the suppressing means includes load transistors (Q L0 , Q L0 ', ..., Q L,n-1 , Q L,n-1 '), connected between the bit line pairs and a power supply, the load transistors being turned ON when the corresponding bit line pairs are not selected by the bit line pair selection means. A device according to claim 1 or 2, wherein the suppressing means includes bit line short-circuiting means (Q S0 , Q S1 , ...), provided for each of the bit line pairs, for suppressing the reduction of the potential of the lower level bit lines of the bit line pairs, the bit line short-circuiting means being turned ON when the corresponding bit line pairs are not selected by the bit line selection means.

Inventors: KAWASHIMA, SHOICHIRO
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C11
IPC codes: G11C11