WIRING LAYOUT FOR BIPOLAR AND UNIPOLAR INSULATED GATE TRANSISTORS

Abstract: A semiconductor device comprises a drain region (11, 12), base regions (14), gate electrodes (17) formed over the drain region between two adjacent base regions through an insulating layer (16) such that each bridges the surface of the drain region to partially cover the two adjacent base regions (14), source regions provided in the base regions, a source electrode provided on the source regions, and a metal gate electrode wiring contacting the gate electrodes. The metal gate electrode wiring includes closed loop portions (19b) and the source electrode is divided into branch sections (18a), each corresponding to the closed loop portion.

Description: This invention relates to a semiconductor device comprising: a semiconductor substrate of a first conductivity type forming a drain region; a plurality of base regions of a second conductivity type, formed in a first main surface portion of said semiconductor substrate; insulating layers, each formed on the surface of said drain region between two adjacent base regions so as to partially cover the two adjacent base regions; gate electrodes, each formed on said insulating layer; source regions of the first conductivity type formed in said base region; and a source electrode formed on said source regions. Such a device is known from GB-A-2 082 385. The invention is applicable to a DMOS FET or a conductive modulation type MOS FET. DMOS FET (double diffusion insulating gate longitudinal FET) or a conductive modulation type MOS FET has a high-speed switching characteristic and has been used primarily as a high-power type semiconductor device due to its small input loss and high input impedance. For example, DMOS FET contains an n-type drain region, a plurality of p-type base regions formed in the drain region, source regions formed in the base region, a source electrode formed on the source region and a gate electrode formed over the drain region between two adjacent base regions through an insulating layer. In the conductive modulation type MOS FET, a p-type anode region is formed under the aforementioned n-type drain region. For ease in understanding this invention a semiconductor device containing a conventional conductive modulation type MOS FET will be explained below with reference to Fig. 1. Fig. 1 shows a plan view showing semiconductor device 10 having metal (aluminium) gate electrode wiring 2, aluminium source electrode 1 and gate electrode 3. The metal gate electrode wiring 2 electrically contacts gate electrode 3, formed of polysilicon. Aluminium source electrode 1 is patterned by aluminium gate electrode wiring 2 to provide a predetermined pattern, but is not divided into a plurality of aluminum source electrode branch sections. Gate electrodes 3, formed of polysilicon, are located under aluminum source electrode 1. In semiconductor device 10, including metal gate electrode wiring 2 shown in Fig. 1, if the dimension of the semiconductor chip or a drain region formation region is increased to about 8.0 x 8.0 mm, gate electrode 3 of polysilicon becomes extremely long and, as a result, its resistance becomes too great to be disregarded and, at the same time, its input capacity becomes greater. This causes a reduction in switching speed, an increase in input loss and a transient degeneration in drain current distribution. That is, when a MOS FET which is now in an on state is rendered off, the drain current distribution in the chip becomes nonuniform. In other words, the drain current is concentrated into that portion of the semiconductor device where the OFF-time delayed MOS FET is located, thus resulting in a breakdown of the aforementioned device portion. This causes a decrease in latching-up current, in the case of the conductive modulation type MOS FET, and a lowering in the V DSX(SUS) capability (i.e., a surge voltage absorption capability when the MOS FET is switched OFF) in the case of DMOS FET, with the result that the breakdown load current of the MOS FET at the switching-off time is lowered under such an inductive load as when a motor is driven. One object of this invention is to provide a semiconductor device which can eliminate drawbacks as encountered in a conventional semiconductor device. Another object of this invention is to provide a semiconductor device which can reduce a delay time from the OFF time of the gate voltage to that of the drain current, to allow the uniform distribution of a drain current, and hence can improve the breakdown load current of a MOS FET at a switching-off time. According to the invention, the device initially defined is characterized in that: a metal gate electrode wiring is provided which includes a plurality of closed loop wiring portions electrically contacting said gate electrodes at contact positions situated along said closed loop wiring portions, and said source electrode is divided into a plurality of branch sections, each corresponding to a respective closed loop wiring portion. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a plan view showing a conventional semiconductor device containing a conductive modulation type MOS FET; Fig. 2 is a plan view showing a semiconductor device according to one embodiment of this invention, including a conductive modulation type MOS FET; Fig. 3 is a cross-sectional view showing a conductive modulation type MOS FET for explaining the arrangement shown in Fig. 2; Fig. 4 is a perspective view showing an external connection relation of the semiconductor device of Fig. 2; Fig. 5 shows characteristic curves showing a gate voltage-versus-drain current relation of the semiconductor device of Fig. 2; and Fig. 6 is a characteristic graph showing a relation of a drain current of the semiconductor device of Fig. 2 to a breakdown probability. Fig. 2 is a plan view showing semiconductor device 20 according to one embodiment of this invention, which includes conductive modulation type MOS FETs. Fig. 3 is a cross-sectional view showing the conductive modulation type MOS FET in which a semiconductor substrate D constitutes a drain region and contains N type region 11 having a main surface and N⁺ type region 12 contacting P type anode region 13. A plurality of P⁺ type base regions 14 are formed in the main surface portion of N type region 11. N⁺ type source regions 15, 15 are formed in the respective base region. Gate insulating layer 16 is formed on N type region 11 between two adjacent base regions 14 in a manner so as to partially cover the adjacent base regions 14. Gate electrode 17, formed of polysilicon, is formed on gate insulating layer 16. Source electrode 18, formed of aluminum, is formed such that it bridges that surface portion of p⁺ base region 14 defined between two adjacent N⁺ type source regions 15 and 15. Semiconductor device 20 of this invention thus contains P anode region 13, drain region D, base regions 14 and source regions 15. Fig. 2 shows a pattern, illustrating a number of gate electrodes 17, source electrode 18 and metal gate electrode wiring 19 electrically contacting gate electrodes 17. Metal gate electrode wiring 19, formed of aluminum, comprises a plurality of closed loop portions 19b (8 in this embodiment) and a center portion 19a, located substantially at the center of semiconductor device 20. Source electrode 18 is electrically divided into 8 source electrode branch sections 18a to correspond to 8 closed loop portions. Respective closed loop portions 19b contact gate electrodes 17, formed of polysilicon, along the closed loop portion. Gate electrodes 17, formed of polysilicon, are located, in a stripe-like fashion, under source electrode branch section 18a which is formed as an integral structure. The metal gate electrode wiring 19 is formed in a symmetric pattern with respect to its center portion. Semiconductor device 20, shown in Fig. 2, is mounted on a mounting metal plate 22 provided on ceramic base plate 21, with anode region 13 contacting the mounting metal plate 22 (Fig. 4). First and second metal plates 23 and 24 are formed on ceramic base plate 21. External connection lead 25, for gate electrode 17, is connected to first metal plate 23, and external lead 26, for source electrode branch sections 18a, is connected to second metal plate 24. Center portion 19a of metal gate electrode wiring 19 is connected to first metal plate 23 through bonding wire 28, and source electrode branch sections 18a are connected through corresponding bonding wires 29 to second metal plate 24. Semiconductor device 20 of this invention, as shown in Fig. 2, has the following advantages. First, when a chip of the same size is used for the formation of the structure where metal gate electrode wiring 19 and source gate branch sections 18a are connected respectively through bonding wires 28 and 29 to the corresponding external connection leads, it is possible to extend the active region on the chip. Second, metal gate electrode wiring 19 has closed loop portions 19b, gate electrodes 17 are connected to the respective closed loop portion and the source electrode 18 is divided into the plurality of source electrode branch sections 18a, whereby gate electrodes 17 of a shorter length can be realized to permit the charging and discharging of the gate electrodes to occur substantially uniformly in the chip to prevent a local concentration of drain current in the chip. It is, therefore, possible to increase the breakdown load current of the semiconductor device thus fabricated. The internal resistance of gate electrodes 17 in semiconductor device 20 of this embodiment was measured under the condition of f = 1 MHz and found to be about 2.0 Ω. In semiconductor device 10, shown in Fig. 1, the internal resistance of the gate electrodes was about 4.0 Ω. Semiconductor device 20 of this embodiment was operated with an R (resistance) load connected thereto and then the drain current was cut off, in which case a waveform as shown in Fig. 5 was obtained. In Fig. 5, the ordinate denotes gate voltage V G and drain current I D and the abscissa denotes a time base, i.e., a delay time td (off) taken for the drain current to reach a zero level after the gate voltage has been started to reach a zero level. In Fig. 5, characteristic lines I and II correspond to semiconductor devices 20 (Fig. 2) and 10 (Fig. 1), respectively. As evident from the graph of Fig. 2, it is possible for the embodiment of Fig. 2 to markedly improve the delay time td (off). Semiconductor devices 20 and 10 were tested, in a V DSX(SUS) mode (in a surge absorption mode of the semiconductor device at the switching-off time), for the breakdown load current, the result of which is as shown in Fig. 6. In Fig. 6 the abscissa denotes the drain current and the ordinate denotes the breakdown probability, noting that the lines III and IV correspond to semiconductor devices 20 and 10, respectively. As evident from the graph as shown in Fig. 6, the line III, upon comparison with the line IV, shows a prominently greater allowable drain current for the same breakdown probability. Conversely, if the drain current is the same, then it will be seen that the breakdown probability is very small for line III. Although in the aforementioned embodiment, the semiconductor device containing the aforementioned conductive modulation type MOS FET has been explained, this invention can also be applied to the semiconductor device containing a DMOS FET. Needless to say, this invention can equally be applied to a semiconductor device containing a DMOS FET and a conductive modulation type MOS FET fabricated from the same chip.

Claims: A semiconductor device comprising: a semiconductor substrate of a first conductivity type forming a drain region (D); a plurality of base regions (14) of a second conductivity type, formed in a first main surface portion of said semiconductor substrate; insulating layers (16), each formed on the surface of said drain region between two adjacent base regions so as to partially cover the two adjacent base regions; gate electrodes (17), each formed on said insulating layer; source regions of the first conductivity type formed in said base region; and a source electrode (18) formed on said source regions; characterized in that: a metal gate electrode wiring (19) is provided which includes a plurality of closed loop wiring portions (19b) electrically contacting said gate electrodes (17) at contact positions situated along said closed loop wiring portions, and said source electrode (18) is divided into a plurality of branch sections (18a), each corresponding to a respective closed loop wiring portion. A semiconductor device according to claim 1, characterized in that an anode semiconductor region (13) of said second conductivity type is formed on a second main surface of said semiconductor substrate. A semiconductor device according to claim 1, characterized in that at least some of said branch sections (18a) are connected to one another by bonding wire means (29). A semiconductor device according to claim 1, characterized in that said metal gate electrode wiring (19) is formed in a symmetric pattern with respect to its centre portion. A semiconductor device according to claim 1, characterized in that said gate electrode (17) is formed of polysilicon and said metal gate electrode wiring (19) is formed of aluminium.

Inventors: KUWAHARA, MASASHI C/O PATENT DIVISION,
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: H01L29
IPC codes: H01L29, H01L23