Self-aligned ultra high-frequency field-effect transistor, and method for manufacturing the same

Abstract: Disclosed is a semiconductor device with its gate electrode and source/drain extraction electrodes (24a, 24b) being made of the same material on a GaAs substrate (20), and with its source/drain heavily doped regions (22a, 22b), which are formed by doping Se in a lightly doped semiconductor layer (2l) on the GaAs substrate (20), self-aligned with both gate electrode (23) and source/drain extraction electrodes (22a, 22b).

Description: This invention relates to a semiconductor device constituted by an ultra high frequency GaAs field effect transistor. Previously known semiconductor devices including an ultra high frequency GaAs field effect transistor (hereinafter referred to as GaAs FET) have the device structure as shown in Fig. 1, for example. More specifically, a lightly doped semiconductor layer 2 of an N conduction type is formed on a semi-insulating undoped GaAs substrate 1 (hereinafter referred to as GaAs substrate). Heavily doped regions 3a and 3b constituting a source and drain, respectively are formed in the predetermined region of the lightly doped (low impurity concentration) layer 2 with a predetermined interval therebetween. A gate electrode 4 is formed on the lightly doped semiconductor layer 2 between the heavily doped regions 3a and 3b, and is made of metal such as Aℓ, Au, etc. or is made of stacking metal layers such as Ti, Aℓ. Source/drain extraction electrodes 5a and 5b of Au Ge/Pt, etc. are formed on the heavily doped regions 3a and 3b, respectively. This conventional semiconductor device 10 is manufactured as follows. First, as shown in Fig. 2A, the N conduction type lightly doped semiconductor layer 2 which acts as an active layer is selectively formed on the GaAs substrate 1. An SiO 2 film is formed on the lightly doped semiconductor layer 2, and the SiO 2 film thus formed is selectively etched to form a dummy gate 11 having a predetermined pattern. A side wall film constituting member 12 of a Si 3 N 4 film is deposited so as to cover the dummy gate 11. As shown in Fig. 2B, a resist film (not shown) is formed on the side wall constituting member 12. The resist film is etched-back to be flattened through a reactive ion etching technique (hereinafter referred to as RIE), thus removing the side wall film constituting member 12 portion on the dummy gate 11. Using, as a mask, the dummy gate 11 and the portion of the side wall film constituting member 12 at the side thereof, impurities of Si are ion-implanted in the lightly doped semiconductor layer 2 through the side wall film constituting member 12 portions on the lightly doped semiconductor layer 2. The implanted impurities are activated to form the heavily doped regions 3a and 3b. As shown in Fig. 2C, the dummy gate 11 is removed through wet etching using NH 4 F, for example. As shown in Fig. 2D, an electrode constituting member 13 of metal such as Aℓ, Au or stacking metal layers such as Ti, Aℓ thereof is formed on the exposed surface of the lightly doped layer 2 using the remaining side wall film constituting member 12 as a mask. As shown in Fig. 2E, both the side wall film constituting member 12 and the electrode constituting member 13 thereon are simultaneously removed through a chemical dry etching technique (CDE) so as to form a gate electrode 14 having a predetermined pattern on the lightly doped semiconductor layer 2. Finally, as shown in Fig. 2F, an ohmic contact is patterned on the heavily doped regions 3a and 3b to form a resist pattern and an ohmic metal contact of AuGe/Pt, etc. is deposited by, e.g., evaporation, etc. After that, the source/drain extraction electrodes 5a and 5b are formed by means of a tape lift-off technique, thus completing the semiconductor device 10 by alloying the ohmic metal contact. The conventional semiconductor device as shown in Fig. 1 has the following problems. (1) The heavily doped regions 3a and 3b and the source/drain extraction electrodes 5a and 5b are not self-aligned with each other so that the interval between the gate electrode 4 and the extraction electrode 5a is larger than that between the gate electrode 4 and the heavily doped region 3a. This leads to insufficient reduction of a so-called source resistance Rs and large variations therein. As a result, the semiconductor device 10 cannot have a good high frequency performance. (2) The intervals between the gate electrode 4 and the source/drain extraction electrodes 5a and 5b cannot be sufficiently reduced. Thus, the device cannot be sufficiently miniaturized and so its integration degree cannot also be sufficiently enhanced. (3) The gate electrode 4 and the source/drain extraction electrodes 5a, 5b are made of different materials so that manufacturing process of the device is complicated. (4) The ohmic property of the source/drain extraction electrodes is improved through the alloying of AuGe. However, if it is intended to further improve the ohmic property by increasing the concentration of Ge, a so-called ball-up phenomenon that the extraction electrodes 5a and 5b are peeled off will occur. If the extraction electrodes 5a and 5b are made of stacking metal layers such as AuGe, Pt, etc. as a holding member in order to prevent the aforesaid phenomenon, the electrode structure becomes complicated still more. Further, the aforesaid method for manufacturing the semiconductor device, as shown in Figs. 2A to 2F has the following problems. (1) The heavily doped regions 3a and 3b, which act as a source and a drain, respectively, cannot have a sufficiently high impurity concentration and also the gate is in a Schottky gate structure so that in order to improve the ohmic property of the source/drain extraction electrodes 5a and 5b, the gate electrode 14 and the electrodes 5a, 5b must be made of different materials, thus making the manufacturing process complicated. (2) The ohmic property of the source/drain extraction electrodes 5a and 5b can be improved by increasing the Ge concentration in the AuGe alloy constituting an ohmic metal contact. If the Ge concentration is increased, however, a so-called ball-up phenomenon that the extraction electrodes are peel off will occur. The provision of the extraction electrodes 5a and 5b in order to prevent such a phenomenon as a holding member of stacking metal layers such as Pt, Ni, Au, etc. makes the manufacturing process complicated. (3) The heavily doped regions 3a and 3b are not self-aligned with the extraction electrodes 5a, 5b. This makes the so-called mask alignment process, etc. complicated and makes the completion of the miniaturized semiconductor device difficult. (4) In order to improve the ohmic property of the source/drain extraction electrodes 5a and 5b, the alloyed process of forming the ohmic metal contact of AuGe is required. (5) The ohmic metal contact formed by the alloying process is liable to be influenced by physical and chemical conditions. Therefore, the selection of the kind of chemicals which are required for the succeeding treatment processes, and of time and temperature conditions in the processes is difficult. US-A-4 455 738 describes a MESFET and the method of manufacturing thereof. In a p-type silicon substrate a lightly doped n-type surface layer is formed. A dummy gate is formed from silicon dioxide. Side walls are formed on the dummy gate from silicon nitride using an anisotropic etching technique. The source and drain regions are then formed by heavily doping the silicon substrate using the dummy gate and the side walls as a mask. The dummy gate is selectively etched to leave the side walls and a platinum layer is deposited and heat treated to form a silicide wherever it is in contact with the silicon substrate. The unreacted platinum on the top of the side walls is removed. The platinum silicide forms a Schottky barrier with the gate region and ohmic contact with the source and drain regions. The disclosure in IBM Technical Disclosure Bulletin, Vol. 24, No. 7A, December 1981, by H.S. Bhatia and J. Riseman, entitled "High Performance MESFET Structure", describes a silicon MESFET and a manufacturing method therefor. The method is considered as adaptable to other substrates such as gallium arsenide. The method involves forming a dummy gate from a layer of silicon dioxide and a layer of silicon nitride. Silicon dioxide side walls are then formed by reactive ion etching. The source and drain regions are then formed by implanting impurities using the dummy gate and the side walls as a mask. The dummy gate is then etched (this is not selective as a part of the dummy gate and the side walls are both made from silicon dioxide) and contact metallurgy then deposited and defined. The book by R.E. Williams "Gallium Arsenide Processing Techniques", 1984, Dedham, MA, USA, pages 232 to 235, 270 to 273 and 292 and 293 describes the general requirement and known techniques for forming a Schottky barrier and ohmic contacts using metal layers on gallium arsenide. For forming ohmic contacts a doping level of greater than 1 x 10 19 is recommended but no method is described which is considered to be reliable. The general recommendation is to alloy the metal into the gallium arsenide. Experimental methods are briefly described for doping gallium arsenide to high enough levels using electron beam or laser annealing to form ohmic contacts to Ti Pt Au without allyoing but it is considered that many difficulties remain and that it is unlikely that the procedure will mature in the foreseeable future. The article in Applied Physics Letters, Vol. 40, No. 9, 1 May 1982, pages 805 to 807, New York, USA, by R.L. Chapman et al entitled "Transient Annealing of Selenium-Implanted Gallium Arsenide Using a Graphite Strip Heater" discusses the difficulties of producing highly doped gallium arsenide using selenium as an impurity. The article confirms that laser and electron beam annealing may be used to produce high electron cencentrations but with the disadvantage of low mobilities. The disadvantages of such methods are considered sufficiently serious that an alternative method of gallium arsenide annealing is required to increase the carrier concentration without producing deleterious side effects. The proposed method is to encapsulate the doped gallium arsenide in a layer of silicon nitride and of silicon dioxide and then to place the doped substrate on a graphite heater. Concentration levels as high as 3 x 10 19 cm -3 are reportet. It is suggested that higher concentration levels can be obtained either with a better encapsulant or in an atmosphere with controlled arsenic vapour pressure. An object of this invention is to provide a semiconductor device with its gate electrode and source/drain extraction electrodes made of the same material, and with its source/drain heavily doped regions self-aligned with both the gate electrode and source/drain extraction electrodes, thereby providing its excellent device performance and implementing its miniaturization. Another object of this invention is to provide a method for manufacturing a semiconductor device, which is capable of providing its device performance and implementing its miniaturization. The objects of the invention are solved by a semiconductor device having source/drain electrodes and a gate electrode formed on a semiconductor substrate, comprising: a one-conduction type lightly doped semiconductor layer formed on said semiconductor substrate; a gate electrode formed on a predetermined region on said lightly doped semiconductor layer; heavily doped source/drain regions formed in said lightly doped semiconductor layer with prescribed intervals from both sides of said gate electrode, and source/drain extraction electrodes of the same material as the gate electrode, formed on said heavily doped source/drain regions and with said prescribed intervals from both sides of said gate electrode; characterized in that the semiconductor - substrate is a GaAs semi-insulating substrate; said heavily doped source/drain regions are doped with impurities of Se at an impurity concentration of 3 to 5 x 10 19 cm -3 , and said gate electrode and said extraction electrodes are formed in a single layer structure of Au without alloying between said extraction electrodes and said heavily doped source/drain regions. The objects of the invention are also solved by a method for manufacturing a semiconductor device having source/drain electrodes and a gate electrode formed on a Gas semiconductor substrate comprising the steps of: forming said one-conduction type lightly doped semiconductor layer on a semiconductor substrate; forming a dummy gate from a first material on a predetermined region on said lightly doped semiconductor layer; forming a side wall film constituting member from a second material on the exposed surface of said lightly doped semiconductor layer, the side wall film constituting member covering said dummy gate; performing an anisotropic etching for said side wall film constituting member to form a side wall film on each side of said dummy gate and to expose the surface of said lightly doped semiconductor layer; hot-ion implanting of Se impurity into said lightly doped semiconductor layer, by using as a mask said side wall films and said dummy gate, and followed by lamp annealing so as to form heavily doped source/drain regions with an impurity concentration of 3 to 5 x 10 19 cm -3 ; selectively removing said dummy gate so as to expose said lightly doped semiconductor layer therebelow; depositing an electrode constituting member on said exposed lightly doped semiconductor layer and said heavily doped source/drain regions using the remaining side wall films as a mask, to form ohmic contact between said electrode constituting member and said heavily doped source/drain regions without an alloying step, said electrode constitutina member being made in a sinqle layer structure of Au and removing said side wall films and said electrode constituting member deposited thereon so as to form a gate electrode and source/drain extraction electrodes on said lightly doped semiconductor layer and said heavily doped source/drain regions, respectively. The semiconductor device in accordance with this invention provides the following meritorious effects. (1) Since the heavily doped regions are self-aligned with both the gate electrode and the source/drain electrodes, the intervals between the gate electrode and the source/drain extraction electrodes can be sufficiently reduced, thereby implementing the miniaturization of the device and so the high integration degree thereof. (2) Since the intervals between the gate electrode and the source/drain extraction electrodes are set to a constant and small value, the source resistance (Rs) can be reduced and its variations can be made small, thereby providing the improved high frequency characteristic of the device. (3) Since the source/drain extraction electrodes are made of metal such as Aℓ, Au, Ti/Aℓ, etc. without through their alloying action, and also provide good ohmic contacts without holding members, the electrode structure can be simplified and also the manufacturing process can be simplified. Further, the method for manufacturing a semiconductor device in accordance with this invention provides the following meritorious effects. (1) Since the heavily doped regions are made so as to have a sufficiently high impurity concentration by the addition of Se, the source/drain extraction electrodes capable of providing good ohmic contacts can be easily made of metal such as Aℓ, Au, Ti/Aℓ, etc. without through their alloying action. Moreover, the gate electrode and the source/drain electrode can be simultaneously formed of the same material through a so-called dummy gate technique. Thus, the electrode forming step can be very simplified. (2) Since the heavily doped regions, the gate electrode and the source/drain extraction electrodes can be formed using the same side wall film as a mask, the heavily doped regions can be self-aligned with both the gate electrode and the source/drain extraction electrode. Thus, the intervals between the gate electrode and the source/drain extraction electrode can be held at a small and constant value so that the source resistance and its variations can be reduced, thereby providing the improved high frequency characteristic of the device. The device can also be small-sized and miniaturized. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a sectional view showing the schematic structure of the prior art semiconductor device; Fig. 2A to Fig. 2F are sectional views showing a metal for manufacturing the prior art semiconductor device; Fig. 3 is a sectional view showing the schematic structure of a semiconductor device according to this invention; Fig. 4A is a sectional view after the state when after a lightly doped layer had been formed on a GaAs substrate, an SiO 2 film has been formed on the lightly doped layer, the SiO 2 film has been selectively etched to form a dummy gate and a side wall film constituting member has been deposited; Fig. 4B is a sectional view showing the state when the side wall film has been etched back to form a side wall film covering both sides of the dummy gate, and impurities have been ion-implanted in the lightly doped semiconductor layer and activated to form heavily doped regions; Fig. 4C is a sectional view showing the state when the dummy gate has been removed; Fig. 4D is a sectional view showing the state when an electrode constituting member has been deposited; and Fig. 4E is a sectional view showing the state when the side wall film and the electrode constituting member portion located thereon have been removed to form a gate electrode and source/drain electrodes. Fig. 3 is a sectional view showing the schematic structure of a semiconductor device according to this invention. In the figure, 20 is a semi-insulating undoped GaAs semiconductor substrate (hereinafter referred to as GaAs substrate). An N-conduction type lightly doped semiconductor layer 21 is deposited on the GaAs substrate 20. Heavily doped regions 22a and 22b which act as a source and a drain, respectively are formed in predetermined regions of the lightly doped semiconductor layer 21 by diffusing impurities of Se so that they extend into the GaAs substrate 20; the impurity concentration of those heavily doped regions 22a and 22b are set to 3 to 5 × 10 19 cm -3 . A gate electrode 23 is formed on the lightly doped semiconductor layer 21 located between the heavily doped regions 22a and 22b. Extraction electrodes 24a and 24b of the same material as the gate electrode are provided on the heavily doped regions 22a and 22b, respectively. The gate electrode 23 and the extraction electrodes 24a, 24b are made in a single layer structure of Au. The heavily doped regions 22a and 22b are self-aligned with both the gate electrode 23 and the extraction electrodes 24a and 24b. In the semiconductor device 30 constructed as mentioned above, the heavily doped regions 22a and 22b are self-aligned with both the gate electrode 23 and the extraction electrodes 24a and 24b so that the intervals between the gate electrode 23 and the extraction electrodes 24a, 24b are properly set to a predetermined value which is sufficiently small. Thus, the so-called source resistance (Rs) can be very reduced and its variations can also be made small, thereby providing the improved high frequency characteristic of the device. Further, since the intervals between the gate electrode 23 and the extraction electrodes 24a, 24b can be reduced, the miniaturization of the device and the high integration degree thereof can be implemented. Since the gate electrode 23 and the extraction electrodes 24a and 24b are made of the same material, the electrode structure of the device can be simplified and the device performance can be improved. A method for manufacturing a semiconductor device in accordance with this invention will be explained with reference to Figs. 4A to 4E. First, as shown in Fig. 4A, the N-conduction type lightly doped semiconductor layer 21 which acts as an active layer is formed on the GaAs substrate 20 through an ion implantation technique. An SiO 2 film is formed on the lightly doped semiconductor layer 21. The SiO 2 film thus formed is selectively etched to form a dummy gate 31 having a width of 0.25 to 0.5 µ and a height of approx. 1 µ. A side wall film constituting member 32 of an Si 3 N 4 film having a thickness of 0.5 to 1.0 µ, which covers the dummy gate 31, is deposited on the lightly doped semiconductor layer 21. The Si 3 N 4 film may be a CVDSi 3 N 4 film which is created by the reaction between SiCℓ 4 , SiH 4 , etc. and ammonia. As shown in Fig. 4B, the side wall constituting member 32 is etched back through a RIE technique to form a side wall film covering both sides of the dummy gate 31 and expose the surface of the lightly doped semiconductor layer 21. Impurities of Se are hot-ion-implanted in the lightly doped semiconductor layer 21 using as a mask the dummy gate 3l and the side wall film 33; this ion-implantation is performed with a dose of 1 × 10 15 cm -2 of Se and at a depth reaching the GaAs substrate. The implanted impurities of Se are activated by a lamp annealing technique, for example, to form the heavily doped regions 22a and 22b having an impurity concentration of 3 to 5 × 10 19 cm -3 . As shown in Fig. 4C, the dummy gate 31 is removed through a wet etching technique using NH 4 , etc. As shown in Fig. 4D, an electrode constituting member 34 of Au is vacuum-deposited on the exposed surface of the lightly doped semiconductor layer 21 and the heavily doped regions 22a and 22b using the side wall film as a mask. Finally, as shown in Fig. 4E, the side wall film 33 and the electrode constituting member 34 thereon are removed by the use of both a tape lift-off technique or ion-milling technique and a CDE technique, thus forming the gate electrode 23 and the source/ drain extraction electrodes which have predetermined patterns. In this way, the semiconductor device 30 is completed. In the process mentioned above, the intervals between the gate electrode 23 and the extraction electrodes 24a, 24b are decided in accordance with the thickness of the side wall film 31 and the heavily doped regions 22a and 22b are self-aligned with both the gate electrode 23 and the extraction electrodes 24a and 24b. In accordance with the semiconductor device manufacturing method of this invention, the gate electrode 23 and the extraction electrodes 24a and 24b are made of the same material so that the device performance can be improved. Further, the heavily doped regions 22a and 22b are formed by ion-implanting impurities of Se so that they are allowed to have a higher impurity concentration. Thus, the source/drain extraction electrodes 24a and 24b can make good ohmic contacts with the heavily doped regions 22a and 22b without through the alloying action. Further, in accordance with the method of this invention, there can be easily provided the semiconductor device 30 which has a very small and uniform source resistance (Rs) and is small-sized and highly integrated.

Claims: A semiconductor device having source/drain electrodes and a gate electrode formed on a semiconductor substrate, comprising: a one-conduction type lightly doped semiconductor layer (21) formed on said semiconductor substrate (20); a gate electrode (23) formed on a predetermined region on said lightly doped semiconductor layer (21); heavily doped source/drain regions (22a, 22b) formed in said lightly doped semiconductor layer (21) with prescribed intervals from both sides of said gate electrode (23), and source/drain extraction electrodes (24a,24b) of the same material as the gate electrode, formed on said heavily doped source/drain regions (22a, 22b) and with said prescribed intervals from both sides of said gate electrode; characterized in that the semiconductor substrate (20) is a GaAs semi-insulating substrate; said heavily doped source/drain regions (22a, 22b) are doped with impurities of Se at an impurity concentration of 3 to 5 x 10 19 cm -3 , and said gate electrode and said extraction electrodes (24a, 24b) are formed in a single layer structure of Au, without alloying between said extraction electrodes (24a, 24b) and said heavily doped source/drain regions (22a, 22b). A method of manufacturing a semiconductor device having source/drain electrodes and a gate electrode formed on a GaAs semiconductor substrate comprising the steps of: forming a one-conduction type lightly doped semiconductor layer (21) on said semiconductor substrate (20); forming a dummy gate (31) from a first material on a predetermined region on said lightly doped semiconductor layer (21); forming a side wall film constituting member (32) from a second material on the exposed surface of said lightly doped semiconductor layer (21), the side wall film constituting member (32) covering said dummy gate (31); performing an anisotropic etching for said side wall film constituting member (32) to form a side wall film (33) on each side of said dummy gate (31) and to expose the surface of said lightly doped semiconductor layer (21); hot ion implanting of Se impurity into said lightly doped semiconductor layer (21), by using as a mask said side wall films (33) and said dummy gate (31), and followed by lamp annealing so as to form heavily doped source/drain regions (22a, 22b) with an impurity concentration of 3 to 5 x 10 19 cm -3 ; selectively removing said dummy gate (31) so as to expose said lightly doped semiconductor layer (21) therebelow; depositing an electrode constituting member (34) on said exposed lightly doped semiconductor layer (21) and said heavily doped source/drain regions (22a, 22b) using the remaining side wall films (33) as a mask, to form ohmic contact between said electrode constituting member (34) and said heavily doped source/drain regions (22a, 22b) without an alloying step, said electrode constituting member (34) being made in a single layer structure of Au; and removing said side wall films (33) and said electrode constituting member (34) deposited thereon so as to form a gate electrode (23) and source/drain extraction electrodes (24a, 24b) on said lightly doped semiconductor layer (21) and said heavily doped source/drain regions (22a, 22b), respectively. A method for manufacturing a semiconductor device according to claim 2, characterized in that said first material is SiO 2 . A method for manufacturing a semiconductor device according to claim 2, characterized in that said second material is Si 3 N 4 . A method for manufacturing a semiconductor device according to claim 2, characterized in that said anisotropic etching is a reactive ion etching.

Inventors: FUKUDA TOSHIKAZU, MITANI TATSURO, FUKUDA, TOSHIKAZU, MITANI, TATSURO, FUKUDA, TOSHIKAZU C/O PATENT DIVISION, MITANI, TATSURO C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: H01L21
IPC codes: H01L21, H01L29