Gated tunnel diode

Abstract: A semiconductor device comprising a p⁺ region (2) and an n⁺ region (3) forming a p⁺/n⁺ homojunction in a semiconductor layer (2, 3) formed between a semiconductor substrate (1) and a cap semiconductor layer (4) both of a wider band gap material than that of the semiconductor layer (2, 3). The p⁺ region (2) and the n⁺ region (3) are respectively provided with contact regions (6, 5), and a gate electrode (7) is formed on the cap layer (4). A tunneling current can flow between a two-dimensional electron gas (10) and a two-dimensional hole gas (11) induced at the heterojunction boundaries of the double heterojunction structure owing to an electric field applied to the semiconductor layer (2, 3). A buffer layer (71) of wide band gap semiconductor material can be further provided between the semiconductor substrate (1) and the semiconductor layer (2, 3) for reducing the leakage currents.

Description: BACKGROUND OF THE INVENTION: I. FIELD OF THE INVENTION: The present invention relates to an ultrahigh speed transistor which utilizes tunneling. More particularly, it relates to a three-terminal tunnel FET in which a tunneling current is induced by applying an external gate field to a semiconductor layer held in a double heterojunction. II. DESCRIPTION OF THE RELATED ART: As a device exhibiting a switching time on the order of picoseconds at room temperatures, there has heretofore been an Esaki diode constructed of a p⁺/n⁺ junction as shown in Fig. 6(a). As is well known, this diode is based on the fact that, since the depletion layer of the heavily doped p⁺/n⁺ junction becomes as thin as about 10 nm, an electron tunneling current flows between the conduction band of the n⁺-layer and the valence band of the p⁺-layer (refer to S. M. Sze: "Physics of Semiconductor Devices," John Wiley & Sons, Inc., NY. (1981), p. 513). Since, however, the Esaki diode is a two-terminal device, it has limits to applications as practical logic switching devices and is not used nowadays. FR-A-1 533 811 discloses a three-terminal device of the FET type in which the electrical isolation between an input and an output is favorable, while the high speed of the tunneling is exploited. Fig. 6(c) is a conceptual diagram of the current - voltage characteristic of the tunnel diode, in which V p and I p denote the values of a voltage and a current that produce the peak current with a forward bias, and V v and I v denote the values of a voltage and a current that produce a valley current, respectively. The figure of merit of the tunnel diode in the application to microwaves etc. is expressed by I p /C j where C j indicates a junction capacitance. Decrease in C j necessitates to make the area of the junction as small as several µ m² or below. Assuming I p ≧ 5 mA, however, a certain degree of junction area is required in order to avoid an excessively high current density. SUMMARY OF THE INVENTION: It is an object of the present invention to provide an improved semiconductor device which operates at high speed and is very little affected by thermal noise. This object is accomplished by a tunnel effect semiconductor device comprising a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, having free electrons and holes therein, said third semiconductor layer being disposed between, and having a narrower band gap than, the first and second semiconductor layers, so that the resulting band discontinuities form at a first boundary between the third semiconductor layer and the first semiconductor layer a first barrier to said holes in the valence band, and form at a second boundary between the third semiconductor layer and the second semiconductor layer a second barrier to said electrons in the conduction band, said holes and electrons forming respectively a two-dimensional hole gas at said first boundary and a two-dimensional electron gas at said second boundary and being separated by a distance small enough for enabling tunneling of carriers, a first contact region contacting said electrons, a second contact region contacting said holes, first and second electrodes formed on said first and second contact regions respectively, and a gate electrode controlling the internal electric field of the third semiconductor layer thereby controlling the tunneling of carriers which are permitted to flow between said boundaries. In a preferred embodiment, said third semiconductor layer comprises a p⁺ -layer and a n⁺ -layer forming a p⁺/n⁺ junction therebetween, said junction producing the internal electric field of the third semiconductor layer. In another preferred embodiment, said first semiconductor layer is doped with p-type impurities, said second semiconductor layer is doped with n-type impurities and said third semiconductor layer is undoped, said impurities producing the internal electric field of the third semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1(a) is a structural diagram of a tunnel FET according to the present invention, while Fig. 1(b) is an energy band diagram thereof; Figs. 2(a) and 2(b) are current - voltage characteristic diagrams and band diagrams of tunnel FET's according to the present invention; Fig. 3 is a diagram showing the crystal structure of an embodiment of the present invention; Fig. 4 is a diagram showing the crystal structure of another embodiment of the present invention; Figs. 5(a) and 5(b) are structural diagrams of a tunnel FET in still another embodiment of the present invention; Figs. 6(a) - 6(c) are structural and characteristic diagrams of a conventional tunnel diode; and Fig. 7 is a structural diagram of a tunnel FET in an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS: A semiconductor device according to the present invention will be described in detail in conjunction with an embodiment. Fig. 1(a) shows the structure of an FET which exploits the tunnel effect. This transistor basically has such a structure that, on a semi-insulating substrate crystal 1, a very thin layer having a p⁺/n⁺ homo-junction (2, 3) which has a band gap smaller than that of the substrate and whose whole thickness is equal to the width of a depletion layer or so is formed, and that it is held in a double heterojunction defined by the substrate crystal 1 and a cap layer 4 which has a band gap greater than that of this layer having the p⁺/n⁺ junction (2, 3). The p⁺-layer 2 and n⁺-layer 3 are respectively formed with contact regions 6 and 5 by diffusion, ion implantation or the like, and a drain electrode 9 and a source electrode 8 are formed on the respective contact regions. In addition, a gate electrode 7 is formed on the cap layer 4. Numerals 12 and 13 in the figure indicate a source - drain bias (V sd ) and a gate bias (V g ), respectively. The band structure of that part of the structure of Fig. 1(a) which underlies the gate electrode 7 is shown in Fig. 1(b) with respect to the thermal equilibrium at a gate voltage = 0. A two-dimensional electron gas layer 10 or 14 and a two-dimensional hole gas layer 11 or 15 are induced at the heterojunction boundaries of the double heterojunction structure, and the charges of these layers balance with the total quantities of the charges of ionized donors 16 and ionized acceptors 17 within the depletion layer of the p⁺/n⁺ junction, whereby an electrical neutral condition is held. The two-dimensional electron gas 10 or 14 and the two-dimensional hole gas 11 or 15 join with the source electrode 8 in Fig. 1(a) and with the drain electrode 9 under very low series resistances, respectively. In contrast, the potential barrier of the depletion layer intervenes between the two-dimensional electrons and the two-dimensional holes, and the source - drain current of the FET is very low at the gate voltage = 0. Under this state, the source - drain bias V sd and the gate bias V g are respectively applied to the source electrode 8 and the gate electrode 7 with reference to the drain electrode 9 as illustrated in Fig. 1(a). Several combinations of the signs of the bias voltages V sd and V g afford different current - voltage characteristics, and simple combinations consist of the voltages V sd and V g of identical signs. Fig. 2(a) illustrates a situation in which a reverse tunneling current flows under a reverse bias, while Fig. 2(b) illustrates a situation in which a forward tunneling current flows. With the reverse bias, when the gate voltage is enlarged, the current increases monotonically, but with a forward bias, when the gate voltage is enlarged, decrease in the tunneling current occurs on the basis of the same principle as in the Esaki diode. Such currents I sd do not depend very intensely upon the source - drain voltages V sd . Anyway, the speed at which the tunneling arises is on the order of picoseconds, so that a switching time of about 100 picoseconds can be achieved by optimizing the capacity and current value of the device. Meanwhile, in the construction of Fig. 1(a), leakage currents can develop through the p-n junctions between the n⁺-layer 3 and p⁺-contact layer 4 and between the p⁺-layer 2 and the n⁺-contact layer 5. The influences of the leakage currents, however, are negligibly small. In case of Ge, with a doping concentration of about 1 x 10¹⁹ cm⁻³ for the p⁺- and n⁺-layers, the width of the depletion layer is approximately 10 nm, and the internal electric field is approximately 1 x 10⁶ V/cm. Accordingly, the sum of the thicknesses of the p⁺-layer and the n⁺-layer may be 10 to 15 nm. In addition, the peak current density J p corresponding to the peak current I p of the tunnel diode stated before is approximately 10² A/cm². Fig. 7 shows another embodiment of the present invention. This embodiment is an improvement on the embodiment of Fig. 1(a). Although the leakage current between the source and drain is negligible in the embodiment of Fig. 1(a), it is more reduced to enhance characteristics in the present embodiment. It is as in the foregoing embodiment of Fig. 1(a) that a buffer layer 71 is formed on a substrate crystal 82, and that a layer having a p⁺/n⁺ homo-junction (72, 73) which has a band gap smaller than that of the buffer layer 71 and which has a total thickness nearly equal to the width of a depletion layer is so formed as to be held in a double heterojunction defined by the buffer layer 71 and a cap layer 74 which has a band gap greater than that of the layer having the p⁺/n⁺ junction (72, 73). Regarding contact regions to be formed by diffusion, ion implantation or the like, an ion-implanted layer (n⁺⁺) 75 is formed on the side of a source electrode 78 by, for example, the ion implantation of Si so shallowly that the n⁺/p⁺ boundary is not reached, while the cap layer 74 and the n⁺-layer 73 on the side of a drain electrode 79 are etched and removed down to the n⁺/p⁺ boundary by dry etching, and a p⁺⁺-layer 76 is formed in the corresponding part of the p⁺-layer 72 by the diffusion of Zn or the ion implantation of Be. Thereafter, ohmic electrodes are respectively formed on the n⁺⁺-layer 75, p⁺⁺-layer 76 and cap layer 74 as the source electrode 78, the drain electrode 79 and a gate electrode 77 by evaporation. According to the present embodiment, the leakage current elucidated in Figs. 1(a) and 1(b) is almost null, and hence, a semiconductor device of still better characteristics can be realized. In the embodiment of Fig. 7, the first semiconductor layer defined in the present invention is the buffer layer 71 formed on the crystal substrate 82. Such a construction may of course be employed. By way of example, in case of using a GaAs substrate, it is possible to use Ga 1-x Al x As for the buffer layer, a GaAs-based material for the third semiconductor layer, and Ga 1-u Al u As ( u ∼0.3) for the second semiconductor layer. Likewise, in case of using an InP substrate, it is possible to use InP, InAlAs or InGaAsP for the buffer layer, InGaAs or InGaAsP for the third semiconductor layer, and InAlAs, InGaAsP or InGaAlAs for the second semiconductor layer. Besides, a semi-insulating material is suitable as the substrate 82. Fig. 3 shows another example of a crystal structure which the semiconductor device according to the present invention possesses. A substrate 31 was semi-insulating GaAs, on which a p⁺/n⁺ junction layer made up of p⁺-Ge (p ≃ 1 x 10¹⁸ - 10¹⁹ cm⁻³, thickness ∼ 10 nm) 32 and n⁺-Ge (n ≃ 1 x 10¹⁸ - 10¹⁹ cm⁻³, thickness ∼ 10 nm) 33, and a hetero-cap layer 34 (undoped GaAs or Al x Ga 1-x As ( x ∼ 0.5 - 0.7), thickness: 50 to 200 nm) were grown by molecular-beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). Fig. 4 shows still another example. A substrate 41 was semi-insulating InP, a layer 42 was made of p⁺-In 0.53 Ga 0.47 As, a layer 43 was made of n⁺-In 0.53 Ga 0.47 As (the total thickness of the layers 42 and 43 was approximately 10 nm), and a hetero-cap layer 44 was made of undoped InP or In 0.52 Al 0.48 As (50 to 200 nm thick). A contact for the n⁺-layer was formed in such a way that a contact layer having an impurity concentration of or above 2 x 10¹⁸ cm⁻³ was formed by a method of ion-implanting and then annealing Si, whereupon AnGe, Ni and An were evaporated and then alloyed as an ohmic electrode. The alloy layer was so deep as to penetrate the cap layer and to extend down to a level within the n⁺-layer. On the other hand, a contact for the p⁺-layer was formed in such a way that a contact layer was formed by diffusing Zn or ion-implating Be deep enough to reach the p⁺-layer, whereupon Cr-Au was or Ti, Pt and An were evaporated as an ohmic electrode. The parts of the layers other than device portions were mesa-etched and removed down to the substrate. Al/Ti, or the like was used as a gate metal. FET's as shown in Fig. 1(a) were manufactured for trial by the use of these crystal structures illustrated in Figs. 3 and 4. When the current - voltage characterisitcs of the FET's under forward and reverse biases were measured, characteristics as illustrated in Figs. 2(a) and 2(b) were obtained. In addition, switching times responsive to gate voltage pulses became several picoseconds, and the possibility of an ultrahigh speed switching device could be verified. It has been revealed that, as the heterojunction cap layer under the gate electrode exhibits a greater conduction-band-discontinuity ΔE c with respect to the p/n junction portion, the gate leakage current becomes less advantageously. Besides, similar characteristics were obtained as to crystal structures in which the p⁺- and n⁺-layers 32 and 33 in Fig. 3 and 42 and 43 in Fig. 4 were replaced with each other. Further, as another embodiment, there was fabricated a structure shown in Fig. 5(a) in which the barrier layer of a heterojunction was doped as in a HEMT, thereby to form a two-dimensional electron gas layer 60 and a two-dimensional hole gas layer 61 on both the sides of an undoped layer 53, and the tunneling between the layers 60 and 61 was controlled by a gate electrode 57. Since, in this case, the layer 53 was of high resistivity, the isolation between a source and a drain under the null gate voltage was improved. However, ohmic contacts for the two-dimensional electron and hole gas layers were more difficult than in the case of Fig. 1(a), and the parasitic resistance of an FET became high. On a semi-insulating InP substrate 51, there were grown a p⁺-In 0.52 Al 0.48 As layer 52 (1 x 10¹⁸ - 10¹⁹ cm⁻³, 50 to 200 nm thick), the undoped In 0.53 Ga 0.47 As layer 53 (about 20 nm thick), and an n⁺-In 0.52 Al 0.48 As layer 54 (1 x 10¹⁸ - 10¹⁹ cm⁻³, 50 to 200 nm thick). With this crystal structure, characteristics similar to those of the structures in Figs. 3 and 4 were obtained. In Fig. 5(a), numerals 55 and 56 designate n-type and p-type contact layers, numerals 58 and 59 source and drain electrodes, and numerals 62 and 63 ionized donors and acceptors, respectively. In Fig. 5(b), numeral 64 indicates the two-dimensional electron gas layer, numeral 65 the two-dimensional hole gas layer, numeral 66 the ionized donors, and numeral 67 the ionized acceptors. In the above, the hetero-cap layer epitaxially grown on the p⁺/n⁺ junction layer was used. FET's in each of which the hetero-cap layer was replaced with an insulator gate such as of SiO₂ or SiN x were fabricated for trial, and similar high-speed switching characteristics were attained. Among these tunnel FET's, the FET in Fig. 1(a) had a very low series resistance, so that the thermal noise was of low level, and characteristics favorable for a high-frequency and low-noise transistor could be achieved.

Claims: A tunnel effect semiconductor device comprising a first semiconductor layer (1; 31; 41; 52; 71), a second semiconductor layer (4; 34; 44; 54; 74), a third semiconductor layer (2, 3; 32, 33; 42, 43; 53; 72, 73) having free electrons and holes therein, said third semiconductor layer being disposed between, and having a narrower band gap than, the first and second semiconductor layers, so that the resulting band discontinuities form at a first boundary between the third semiconductor layer and the first semiconductor layer a first barrier to said holes (11; 15; 61; 65; 81) in the valence band, and form at a second boundary between the third semiconductor layer and the second semiconductor layer a second barrier to said electrons (10; 14; 60; 64; 80) in the conduction band, said holes and electrons forming respectively a two-dimensional hole gas at said first boundary and a two-dimensional electron gas at said second boundary and being separated by a distance small enough for enabling tunneling of carriers, a first contact region (5, 55, 75) contacting said electrons, a second contact region (6, 56, 76) contacting said holes, first and second electrodes (8, 9; 58, 59; 78, 79) formed on said first and second contact regions respectively, and a gate electrode (7; 57; 77) controlling the internal electric field of the third semiconductor layer thereby controlling the tunneling of carriers which are permitted to flow between said boundaries. The semiconductor device of claim 1, wherein said third semiconductor layer comprises a p⁺ -layer (2, 32, 42, 72) and a n⁺ -layer (3, 33, 43, 73) forming a p⁺/n⁺ junction therebetween, said junction producing the internal electric field of the third semiconductor layer. The semiconductor device of claim 1, wherein said first semiconductor layer (52) is doped with p-type impurities, said second semiconductor layer (54) is doped with n-type impurities and said third semiconductor layer (53) is undoped, said impurities producing the internal electric field of the third semiconductor layer. The semiconductor device of claim 1, wherein said first semiconductor layer (31) is made of a semiconductor material composed of GaAs, said second semiconductor layer (34) is made of a semiconductor material composed of Al x Ga 1-x As, and said third semiconductor layer (32, 33) is made of a semiconductor material composed of Ge. The semiconductor device of claim 1, wherein said first semiconductor layer (41) is made of a semiconductor material composed of InP, said second semiconductor layer (44) is made of a semiconductor material composed of In 0.52 Al 0.48 As and said third semiconductor layer (42, 43) is made of a semiconductor material composed of In 0.53 Ga 0.47 As. A method of making the tunnel effect semiconductor device of claim 1, including the steps of: forming said third semiconductor layer (2, 3; 53; 72, 73) on said first semiconductor layer (1; 52; 71) and said second semiconductor layer (4; 54; 74) on said third semiconductor layer, forming said first and second contact regions (5, 6; 55, 56; 75, 76) into at least said third semiconductor layer (2, 3; 53; 72, 73) by diffusion or ion implantation whereby a first contact region (5; 55; 75) of a first conductivity type and a second contact region (6; 56; 76) of a second conductivity type are formed, forming said first and second electrodes (8, 9; 58, 59; 78, 79) on said first and second contact regions (5, 6; 55, 56; 75, 76), respectively and, forming said gate electrode (7; 57; 77) on said second semiconductor layer (4; 54; 74).

Inventors: KURODA TAKAO HITACHI KOGANEI-R, MATSUMURA HIROYOSHI, MIYAZAKI TAKAO, WATANABE AKIYOSHI HITACHI SHOB, KURODA, TAKAO HITACHI KOGANEI-RYO, MATSUMURA, HIROYOSHI, MIYAZAKI, TAKAO, WATANABE, AKIYOSHI HITACHI SHOBU-RYO
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1987
Main classification: H01L29
IPC codes: H01L29, H01L21