POWER TRANSISTOR WITH SELF-PROTECTION AGAINST DIRECT SECONDARY BREAKDOWN

Abstract: A power transistor with self-protection against direct secondary breakdown, comprises a plurality (1,2) of elementary transistors (3) having their emitter terminals mutually connected and forming a common emitter terminal (E), collector terminals also mutually connected and forming a common collector terminal (C), and base terminals connected to at least one current source (5). Switches (6,7) are furthermore provided selectively associated with some (2) of the elementary transistors, preferably with one elementary transistor every two, and allowing operation of the associated elementary transistors in the saturation operating region and switching off the associated elementary transistors during high-voltage operation.

Description: The present invention relates to a power transistor with self-protection against direct secondary breakdown. As is known, direct secondary breakdown is the main cause of malfunction in power transistors and occurs due to a concentration of current in a specific region so that the local temperature increase has a regenerative effect on the accumulation of current in said region and represents a positive feedback phenomenon. It is furthermore known that the main impediment to the obtainment of an improved direct secondary breakdown phenomena withstanding ability of power transistors is due to the electrothermic interaction among the different power dissipating regions of the transistor. In order to improve the ability of transistors to withstand such stresses, several solutions have already been proposed. In particular, one solution entails the use of resistors, so-called ballast resistors, in series to the emitter of each elementary transistor constituting the complete power transistor. Another solution is proposed in the U.K. patent No. 1,467,612, disclosing replacing each elementary transistor with a pair of transistors geometrically arranged so as to obtain a compensation of the thermal imbalances. Yet another solution is the one known from the Italian patent application No. 21028 A/84 and German patent application DE-A-3 518 077, according to which each elementary transistor is controlled by means of its own current source so as to reduce electrothermic regeneration phenomena. Such known solutions allow to reduce only partly the phenomenon of direct secondary breakdown and are not always free from disadvantages. A substantial improvement in the problem is instead achieved according to the solution indicated in the U.S. patent 4,682,197. According to the solution described in the abovementioned patent, it is possible to obtain an integrated semiconductor device capable of delivering a power which is equal to the sum of the powers supplied by each elementary transistor (formed by a plurality of cells and indicated also as a "finger", the latter including a group of cells) if a bipolar power transistor is produced. In detail, the device consists of a plurality of elementary transistors electrically connected by physically spaced apart by an amount equal to 0.4 mm (17 mils) (i.e. approximately the width of a single finger). Since however in most cases the maximum number of fingers constituting the power transistor is set by the saturation voltage, the solution indicated in the last-mentioned patent does not constitute a fully optimum solution as to the bulk of said power transistor. Moreover, the solutions indicated in order to minimize the bulk of the device, such as the insertion, between two adjacent elementary transistors, of the drive transistors operating as current sources or of the elementary transistors of the complementary stage, if the device constitutes a class-B output stage the two output transistors whereof operate alternately, are limited in their usefulness, in particular when the double metal level cannot be used. Given this situation, the aim of the present invention is to provide a bipolar power transistor which eliminates the disadvantages of the prior art solutions and in particular provides a behavior which is improved and self-protecting against direct secondary breakdown phenomena. Within this aim, a particular object of the present invention is to provide a bipolar power device the elementary transistors whereof are adjacent to one another, without interspacing, and which is nonetheless capable of ensuring the same power levels obtainable with the spaced structure indicated in the last-mentioned patent. Still another object of the present invention is to provide a bipolar power transistor which has low saturation values by virtue of the fact that during its operation in saturation all the elementary transistors, or fingers, are active. Another object of the present invention is to provide a bipolar power transistor having a bulk practically equal to the one of a standard structure. Not the least object of the present invention is to provide a power transistor which can be easily integrated using technology and machinery which is common in the electronics industry, so as to have production costs which are comparable with known devices. The aim described, the objects mentioned and others which will become apparent hereinafter, are achieved by a power transistor self-protecting against direct secondary breakdown, as defined in the appended claim 1. According to the invention, during operation in low-current saturation, in which there is no risk of direct secondary breakdown, all the elementary transistors work together so as to exploit to the utmost the silicon area, while instead, proximate to the region in which direct secondary breakdown may occur, some transistors, preferably arranged alternated with the remaining elementary transistors, are suddenly or gradually switched off so that the elementary transistors not controlled by the switches, when they operate in the high-voltage operation region, are mutually spaced like in the solution indicated in the U.S. patent 4,682,197. In this manner, in the dangerous operation region, the power deliverable by an individual elementary transistor is multiplicated by the number of elementary transistors not switched off by the related switch. Further features and advantages of the invention will become apparent from the description of two preferred, but not exclusive, embodiments, illustrated only by way of non-limitative example in the accompanying drawings, wherein: Figure 1 is the equivalent circuit diagram of a first embodiment of a power transistor according to the invention; Figure 2 is an equivalent circuit diagram of a second embodiment of a power transistor according to the invention; and Figure 3 illustrates the behavior of the currents flowing in the individual elementary transistors of the embodiment according to figure 2 versus the collector to emitter voltage. With reference to figure 1, a first embodiment of the power transistor is illustrated in which some individual elementary transistors which form the complete power transistor are switched off suddenly when a specific threshold voltage is exceeded. In figure 1 the power transistor comprises a plurality of transistor structures, separated from one another by broken lines and respectively indicated by the reference numeral 1 if they are not provided with switch means, and by the reference numeral 2 when they comprise a control switch for turning off the associated elementary transistor when a threshold voltage is exceeded. In detail, each transistor structure 1, 2 comprises an elementary transistor 3, here of the NPN type, said elementary transistors 3 having mutually connected emitter terminals which form the common emitter terminal of the device, indicated at E, collector terminals also all mutually connected and forming the common collector terminal C of the power transistor, and base terminals each connected to a respective resistor 4. In the illustrated embodiment, the elementary transistors are driven by a common current source, formed here by a transistor 5 of the PNP type having its base terminal forming the base terminal B of the complete power transistor, its collector terminal connected to the resistors 4 and its emitter terminal connected to the common collector terminal C of the device. As is apparent, the structure consists of the alternation of transistor structures 1 and 2 having the basic structure described above and being differentiated in that the transistor structures indicated at 2 have switch means adapted to cause their switching off when a preset threshold voltage is reached. In particular, here, the switch means consist of the combination of a transistor 6 connected to the base of the transistor 3 and of a Zener diode 7 appropriately connected between the base of the transistor 6 and the common collector terminal C. In detail, the transistor 6 is an NPN transistor having its collector terminal connected to the base of the transistor 3, its emitter terminal connected to the common emitter terminal E, and its base terminal connected to the anode of the Zener diode 7, having its cathode connected to the common collector C. As is clear to the expert in the field, during low-voltage operation all the elementary transistors 3 are operating, since across the Zener diodes 7 there is a reverse voltage having a value insufficient to cause them to conduct. On the contrary, when the breakdown voltage of the Zener diodes 7 is exceeded, said diodes start to conduct, switching on the respective transistors 6 which therefore, shorting the emitter and base terminals of the transistors 3 associated therewith, cause their switching off. Accordingly, if the power transistor operates in the danger zone in which direct secondary breakdown phenomena may occur, the power transistor according to figure 1 has alternately on and off elementary transistors, i.e. in this danger zone the operating elementary transistors are spaced from one another by the space occupied by the off transistors of the structures 2. In this manner it is possible to operate in this region with a structure similar to that proposed in the aforesaid US patent, which allowed an increase in the power which can be dissipated by said power transistor by a factor equal to the number of operating elementary transistors. The solution illustrated in figure 1 is particularly simple and allows the immediate switching off of the transistors having the switching-off system when the voltage threshold preset by the zener 7 is reached. However, if the power transistor operates in a linear manner, such a sudden switching off is undesirable since it would entail distortions in the output signal which may be disadvantageous, for example, if the power device is used in audio devices or in other systems in which a switching operation is desired. In this case it is possible to use instead the solution illustrated in figure 2, wherein the switch means no longer operate so as to suddenly switch off the associated elementary transistors, but, upon exceeding the preset threshold voltage, switch off said transistors gradually. In detail, the power transistor according to figure 2 also consists of the alternation of transistor structures, here indicated at 10 and 11 depending respectively on whether the associated elementary transistor is active in high-voltage operation or is switched off in said region. Each transistor structure 10, 11 substantially consists of an elementary transistor 16, here of the NPN type, and of a related drive transistor 15, here of the PNP type. In detail, the transistors 16 have mutually connected collector terminals forming the common collector terminal C of the device, first mutually connected power emitter terminals 17 forming the common emitter terminal E of the device, and base terminals connected to the collector terminals of the drive transistors 15. In turn, the drive transistors 15 have emitter terminals which are connected to one another and to the common collector terminal C of the device and base terminals connected to one another and forming the common base terminal B of the device. According to the illustrated embodiment, each elementary transistor is provided with a current control system which comprises a second emitter 18 having an appropriate area and being insulated from power emitter 17 and a further transistor respectively indicated at 19 and 19′ depending on whether it belongs to the transistor structure 10 or 11. As can be seen in the figure, the transistors 19, 19′ are connected with their collector terminal to the base of the transistors 16 and with their base terminal to the second emitter 18 of the transistor 16.The emitter terminal of the transistors 19 and the main emitter terminal 21 of the transistors 19′are connected, to the common emitter terminal of the complete power transistor, while the transistors 19′ of the transistor structures 11, provided with the switching-off system, have a second emitter 22 connected to the common collector terminal C through a related resistor 23. The current limiting structure is completed by a resistor 20 arranged between the second emitter 18 of the transistor 16 and the common emitter terminal E, with an anti-leakage function so as to better define the existing current levels. By virtue of the structure illustrated in figure 2 the currents supplied by the individual transistors 16 are as illustrated in figure 3, wherein 30 indicates the current supplied by transistor structures 10, while 31 indicates the current supplied by the transistor structures 11. In practice, by virtue of the provision of the second emitter 18, having an appropriate area, smaller than that of the main or power emitter 17 and being insulated from the latter, preferably arranged at the center thereof, but even laterally thereto, a system is obtained which detects the base-emitter voltage drop and the temperature of the power transistor and is capable, together with the transistor 19, to limit said drop to the sum of the base-emitter drop of the transistor 19 and the base-emitter 18 of transistor 16 in the forward active region. Moreover, by virtue of the second emitter 18 and of the transistor 19 it is also possible to limit the overall current flowing in the power transistor. In fact the emitters 18 and 22 are dimensioned as to obtain desired current ratios, achieving limitation of the total current of the transistor structure, and therefore the output characteristic indicated by 30 in figure 3. Instead, as to the transistor structure indicated at 11, since the second emitter 22 of the transistor 19′ acts like a Zener diode, in the low-voltage operating region with the Zener in the OFF state, the structure 11 operates exactly like the one of figure 10 and the current output characteristic 31 coincides with the first part of the curve 30 in figure 3. However, when the voltage between the collector and the emitter of the power transistor increases so much as to cause the breakdown of the Zener diode formed by the junction base-second emitter 22, the Zener starts to conduct, drawing current through the resistor 23. The beginning of the conduction of the transistor comprising the second emitter region 22 causes a removal of current from the base of the transistor 16 which gradually begins to switch off. As the voltage between the common collector C and the emitter E increases, a progressive switching off of the transistor 16 therefore occurs along the descending line indicated by 31 in figure 3. In particular, the point at which the curve 31 reaches zero depends on the ratio between the resistors 20 and 23. In practice, with the structure according to figure 2 a device is provided which, besides achieving the illustrated current limiting by virtue of the second emitter 18 and the transistor 19, has a system for switching-off the elementary transistors which operates in a gradual manner and is therefore adapted for linear operation. As in the preceding embodiment, the transistor structures 11 with associated switching-off system are preferably arranged alternately to the transistor structures 10 which remain active even in the high-voltage region, so that after the switching off of the transistor structures 11 a system is obtained having active elementary transistors which are mutually spaced apart by an amount equal to the width of one elementary transistor, thus obtaining an improvement in the direct secondary breakdown withstanding ability by virtue of the improvement in the I s/b (i.e., the collector current for which, at a specific collector-emitter voltage, the elementary transistor fails) by a factor equal to the number of active elementary transistors. As is apparent from the previous description, the invention fully achieves the intended aim and objects. In fact a power transistor has been provided in which an optimum area occupation occurs with low saturation values since in said operating region all the elementary transistors are active, obtaining however an improvement in the direct secondary breakdown withstanding ability by switching off some elementary transistors in case of operation in the danger zone due to the possibility of the occurrence of direct secondary breakdown phenomena. Moreover, the described solution does not require a high circuital complexity and the layout is particularly simple in case of the use of a double metallization level. However, the invention may be implemented also with a single metal layer level. Furthermore, in the case of the use of the structure illustrated in figure 2, limitation of the maximum current is achieved also for the elementary transistors which are not provided with the automatic switching-off system, thus improving the characteristics of the device. The invention is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. In particular the fact is stressed that though the illustrated embodiments alternate always-active elementary transistors and elementary transistors provided with the switching-off system, so that between two always-active transistors there is always a transistor adapted to switch off in high-voltage operation, said alternation can also be different, for example providing a single elementary transistor having a switching-off device every three elementary transistors or vice versa. Furthermore, though it is advantageous to produce power transistors with an odd number of fingers (elementary transistors), beginning and ending with always active elementary transistors, the invention is nonetheless not restricted to this solution. Moreover, the sudden or gradual switching-off systems are not limited to the illustrated solutions and the invention comprises any solution which allows switching off of some elementary transistors when the power transistor reaches the region of danger as to direct secondary breakdown. Furthermore, all the details may be replaced by other technically equivalent ones.

Claims: A power transistor with self-protection against direct secondary breakdown, comprising a first and a second plurality (2,11;1,10) of elementary transistors (3,16) having their emitter terminals mutually connected and forming a common emitter terminal (E), collector terminals mutually connected and forming a common collector terminal (C), and base terminals connected to at least one current source (5,15), characterized in that it comprises switch means (6,7;18,19′,22,23) selectively connected to said first plurality (2;11) of elementary transistors (3,16) for allowing operation of said first plurality of elementary transistors in a saturation operating region and switching off said first plurality of elementary transistors (3,16) in a high-voltage operating region, while said second plurality (1,10) of elementary transistors (3,16) are active in both said saturation and high voltage operation regions. A power transistor according to claim 1, characterized in that said switch means (6,7) are of the type switching off said first plurality (2) of elementary transistors (3) suddenly when a preset threshold voltage is reached. A power transistor according to claim 2, characterized in that said switch means comprise switching-off transistors (6) having emitter and collector terminals connected respectively to said base and emitter terminals of said first plurality (2) of elementary transistors (3) and base terminals connected to said common collector terminal (C) by means of respective Zener diodes (7). A power transistor according to claim 1, characterized in that said switch means (18,19′,22,23) are of the type gradually switching off said first plurality (11) of elementary transistors when a preset threshold voltage is reached. A power transistor according to claim 1 or 4, characterized in that said switch means comprise secondary emitter regions (18) formed in said first plurality (11) of elementary transistors (16) and switching-off transistors (19′)having base terminals connected to said secondary emitter regions (18), and collector and emitter terminals respectively connected to said base and emitter terminals of said first plurality of elementary transistors, said switching-off transistors (19′) further comprising secondary emitter regions (22) connected to said common collector terminal (C) through respective resistors (23). A power transistor according to claim 5, characterized in that resistors (20) are provided between said secondary emitter regions (18) of said first plurality (11) of elementary transistors (16) and said common emitter terminal (E). A power transistor according to claim 5 or 6, characterized in that it comprises current limiting means for said elementary transistors including said secondary emitter regions (18) and said switching-off transistors (19′) in said first plurality (11) of elementary transistors (16), and similar secondary emitter regions (18) formed in said second plurality (10) of elementary transistors (16) as well as further control transistors (19) having base terminals connected to said similar secondary emitter regions (18), and collector and emitter terminals respectively connected to the base and emitter terminals of said second plurality of elementary transistors. A power transistor according to any of the preceding claims, characterized in that said switch means (6,7;18,19′,22,23) are provided every two elementary transistors (3;16). A power transistor according to any of the preceding claims, characterized in that it comprises an odd number of elementary transistors (3;16) arranged in sequence side-by-side, and in that said first plurality (2,11) of elementary transistors (3;16) with said switch means (6,7;18,19′,22,23) are provided at even-numbered positions in said sequence of said elementary transistors.

Inventors: MURARI, BRUNO, VILLA, FLAVIO
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1987
Main classification: H02H9
IPC codes: H01L29, H03F1, H02H7, H02H9, H01L21, H03K17