FABRICATION PROCESS FOR EPROM CELLS WITH OXIDE-NITRIDE-OXIDE DIELECTRIC

Abstract: The process calls for covering of the dielectric (6) with a thin additional layer of polysilicon (10) which has the function of protecting the dielectric from any defects which would otherwise be introduced from the subsequent masking.

Description: The present invention relates to a fabrication process for EPROM cells with oxide-nitride-oxide intermediate dielectric. A relatively recent development in integrated circuit fabrication techniques has indicated the use of a dielectric with a triple oxide-nitride-oxide layer (ONO, as will be often indicated below) in place of the more usual single silicon oxide layer as being profitable. Specifically the ONO dielectric proved to be profitable concerning electrical properties such as low leakage currents, the high voltage of dielectric breakage, but especially reduced defects with low electrical fields. It was natural to think of using a triple ONO layer as the intermediate dielectric between two layers of polysilicon in EPROM memories which utilize particularly said properties. Attempts made heretofore in this direction have however shown a certain criticality of essential cleaning of the surface of the ONO dielectric after removal of the masking required for forming its contours. Said cleaning is usually performed by hydrofluoric acid etching and introduces a substantial indetermination of the thickness of the top layer of oxide and has a negative influence on the reproduceability of the cell. It also necessitates the use of a top oxide layer of greater thickness than necessary with the resulting lengthening of the heat treatment required, which worsens the electrical characteristics of the triple ONO layer. Finally, in spite of all possible care in the cleaning phase, small residues from the masking tend to remain while the still uncovered dielectric tends to pick up small traces of dirt, causing defects in the dielectric. US-A-4426764 discloses a manufacturing process for a memory cell, which provides for successive formation of a gate oxide layer, a first polysilicon layer and a dielectric layer. A first mask is then arranged on the dielectric layer to protect a selected portion of said layers during a subsequent etching operation which removes uncovered portions of the layers. A second polysilicon layer is then deposited on the resulting structure and a further etching operation is carried out to remove unselected portions of the layers. US-A-4577390 in turn discloses a process for manufacturing polysilicon to polysilicon capacitors, which provides for deposition of two polysilicon layers with an interposed ONO dielectric. The object of the present invention is to solve the problem of contamination of the dielectric from masking material and the resulting need for cleaning in the construction of EPROM cells with an ONO dielectric, so as to grant good quality and reproducibility. In accordance with the invention said object is achieved by a process as defined in claim 1 In this manner the mask does not introduce defects in the dielectric, which need not be subjected to cleaning operations with chemical etching and consequently has good quality, definite thickness and perfect reproducibility. The thickness of the top oxide layer of the dielectric can be made dependent only on required electrical performance and can be appropriately decreased together with the duration of the necessary heat treatment. Good quality and reproducibility of the dielectric are also assured by the fact that the dielectric does not remain uncoverd while awaiting the second layer of polysilicon but is always protected by the additional polysilicon layer. Moreover, the additional polysilicon layer is unaffected by large defects introduced from the mask. The process in accordance with the invention thus makes it possible to construct EPROM cells with oxide-nitride-oxide dielectric which are unaffected by problems connected with defects and imprecision of the thickness of the dielectric. The process in accordance with the invention used as an example in the fabrication of an EPROM memory cell with associated transistor is illustrated in detail in the annexed drawings wherein:- FIGS. 1-6 show schematically the successive steps of the above process. FIG. 1 shows a substrate of monocrystalline silicon on which in the areas 2 and 3 designed to form an EPROM memory cell and an associated transistor have been deposited by known techniques gate oxide 4 and a first layer of polycrystalline silicon or polysilicon 5 appropriately doped. As shown in FIG. 2 over the entire structure is then formed by known techniques a dielectric 6 consisting of a triple layer (ONO) of silicon oxide 7, silicon nitride 8 and silicon oxide 9 totalling on the order of 20-100nm (200-1000 Å). More precisely, a first phase of oxidation causes formation of the lower layer of oxide 7, then the intermediate layer of nitride 8 is deposited and lastly nitride oxidation is performed to form the top layer of oxide 9 preferably on the order of 2-10nm (20-100 Å). On the dielectric ONO 6 is deposited immediately afterward a thin additional or 'ficticious' layer of polysilicon 10 preferably on the order of 30-200nm (300-2000 Å). To the structure is then applied a mask 11 preferably of photolithographic resist which covers only the area of the EPROM cell 2 (FIG. 2). In the areas not protected by the mask 11 are then performed in succession etching of the additional layer of polysilicon 10 and ONO dielectric 6, obtaining after removal of the mask 11 the structure shown in FIG. 3. Thanks to the presence of the superimposed additional layer of polysilicon 10 the dielectric 6 has not been contaminated by the mask 11 so that it has no defects and its thickness is well established and, especially in the top layer of oxide 9 made thin enough to not require long heat treatment which would damage the underlying nitride. At the same time the defects introduced by cleaning of the polysilicon layer 10 have far less effect on electrical performance. 0n the structure thus obtained is then deposited a second layer of polysilicon 12 which by appropriate heat treatment can be made into a single piece in the cell area 2 with the underlying additional layer 10. 0n the aforesaid second layer 12 after appropriate doping there is formed a layer of oxide 13. The structure now appears as shown in FIG. 4. A mask 14 is then laid over the structure to cover appropriate portions of the cell area 2 and the transistor area 3 corresponding to the desired layout for the second layer of polysilicon 12. The uncovered zones undergo in succession etching of the oxide 13, etching of the second layer of polysilicon 12 and of the additional layer 10, and lastly etching of the three layers 9, 8 and 7 of the ONO dielectric 6. Thus is obtained the structure shown in FIG. 5 and then, by a similar masking and selfaligned etching of the layer of polysilicon 5 and the underlying gate oxide 4 at the sides of the ONO dielectric of the cell area 2, the final structure shown in FIG. 6.

Claims: Fabrication process for an EPROM cell, comprising the following succession of steps: deposition of a dielectric (6) formed by a triple oxide-nitride-oxide layer (7, 8, 9) on a first polysilicon layer (5) laid over a semiconductor substrate (1) provided with a gate oxide (4); deposition of an additional intermediate polysilicon layer (10) on the dielectric (6); application of a first protective mask (11) for covering a selected portion of the dielectric (6) and of the additional intermediate polysilicon layer (10); removal of the unmasked portions of the dielectric (6) and the intermediate polysilicon layer (10) to separate the EPROM cell from any other semiconductor device on the same substrate (1); removal of said first mask (11); deposition of a second polysilicon layer (12); application of a second protective mask (14) for covering a further selected portion of the dielectric (6) and of the intermediate and second polysilicon layers (10, 12); and removal of the unmasked portions of the second and intermediate polysilicon layers (10, 12) and the dielectric (6). Process in accordance with claim 1, characterized in that said additional polysilicon layer (10) has a total thickness of the order of 30-200 nm (300-2000 Angstrom). Process in accordance with claim 1, characterized in that said dielectric (6) has a total thickness of the order of 20-100 nm (200-1000 Angstrom). Process in accordance with claim 3, characterized in that said dielectric (6) has an oxide top layer (9) with a thickness of the order of 2-10 nm (20-100 Angstrom).

Inventors: CRISENZA, GIUSEPPE, GHIDINI, GABRIELLA
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1987
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29