OVERCURRENT DETECTOR AND CIRCUIT BREAKER

Abstract: Solid state overcurrent detector is provided with a current sensor means (200) having an OR circuit (130) connected by its input terminals to output terminals of burden circuits (41,42,43) and phase selecting circuit (400) for selecting largest phase connected by its input terminals to the output terminals of the burden circuits, the output terminal of the phase selecting circuit (400) is connected through a signal converting circuit (90) and an A/D converter (100) to a microcomputer (110) having a first level-discrimination means (110) and a first time-­ current operation means (150) with inverse time-current characteristics for various time interruptions responding to amount of overcurrent, and the output terminals of the OR circuit (130) is connected through a second level-­ discrimination circuit (140) to a sacond time-current operation circuit (150) for instant interruption.

Description: FIELD OF THE INVENTION The present invention relates generally to an overcurrent detector and a circuit breaker including such an overcurrent detector. DESCRIPTION OF THE RELATED ART FIG. 1 shows a prior art circuit breaker disclosed in published unexamined Japanese patent application SHO 60-32211 and in EP-A-0 133 968. In FIG. 1, on a set of power lines, namely R, S and T of three phase power lines 10, current transformers 21,22 and 23 of a current sensor means 200 are provided, respectively. Full-wave rectifiers 31, 32 and 33 are connected with their two input lines across both output lines of the current transformers 21, 22 and 23, respectively. Burden circuits 41, 42 and 43 are connected with their input lines to output lines of the full-wave rectifiers 31, 32 and 33, respectively, and one of the input lines of each of the burden circuits 41, 42 and 43 are connected in common to the ground. Output terminals of the burden circuits 41, 42 and 43 are connected to the input terminals of an OR circuit 130, which consists of three diodes 131, 132 and 133, the output terminals of which are connected in common as an output terminal of the OR circuit 130. Adjustable output terminals of the burden circuits 41, 42 and 43, wherefrom output signals can be obtained in desirably adjusted levels, are connected to input terminals of mean/effective value circuits 91, 92 and 93 of mean/effective value means 90, for producing mean values or effective values of the signals from the burden circuits 41, 42 and 43. The output terminals of the mean/effective value circuits 91, 92 and 93 are connected to the input terminals of OR circuit 160 which consists of three diodes 161, 162 and 163 and issues an output signal to an A/D converter 100. A microcomputer 110 is connected to the output terminal of the A/D converter 100. The output terminal of the OR circuit 130, as a second output terminal of the sensor means 200, is connected to the A/D converter 100 and the microcomputer 110 through a power source circuit 300, which is generally a constant voltage circuit. Furthermore, the second output terminal of the current sensor means 200 is connected to a second level discrimination circuit 140 which, for instance, comprises at least one zener diode. The second level discrimination circuit 140 is connected to a second time-current operating circuit 150. Output terminals of the microcomputer 110 and the second time-current operating circuit 150 are connected to an output circuit 120 through an OR gate 121. The output circuit 120, for instance comprising a thyristor, actuates a releasing device 80 for carrying out disconnection of line switches 201, 202 and 203. An indicator 180 is provided for indicating that the releasing device 80 has operated. The microcomputer 110 comprises a first level discrimination means and a first time-current operating means as is described later herein. The current sensor means 200 issues from the mean/effective value circuit 90 signals corresponding to means values or effective values of the currents in the power lines R, S and T, and also issues from the OR circuit 130 the second output signal corresponding to the largest value of the current in the power line R, S and T. The second output signal of the current sensor means is given through the second level discrimination circuit 140 to the second time-current operating circuit 150. The A/D converter 100 and the microcomputer 110 are fed with a constant voltage D/C current from the power source circuit 300. When overcurrent(s) flow in the AC power lines 10, output currents of the current transformers 21, 22 and 23, which are coupled to the AC power lines R, S and T of the AC power lines 10, correspondingly produce output currents at predetermined transforming ratio. The output currents are rectified by the full-wave rectifiers 31, 32 and 33, respectively. The rectified output currents of the full-wave rectifiers 31, 32 and 33 are fed to respective burden circuits 41, 42 and 43. The output signals of the burden circuits 41, 42 and 43 are transformed into mean values or effective values thereof by the mean/effective value circuits 91, 92 and 93 of the mean/effective value means 90. The largest signal among the output signals of the mean/effective value circuits 91, 92 and 93 is given to the A/D converter 100. This digital signal is fed to the microcomputer 110. The microcomputer 110 carries out level discrimination of this digital input signal in accordance with a predetermined program stored in a read-only memory 114. Furthermore, basing on the results of the level discrimination, a predetermined time-current operation is carried out, thereby to issue an output signal. That is, the microcomputer 110 functions as the first level discrimination means and the first time-current operation means. The above-mentioned time-current operation is carried out, for instance, along the inverse long time-current characteristic of part A of FIG. 2. The output signal issued from the microcomputer 110 is fed to the gate of the thyristor 120, which is then turned on to drive the output device 80. Accordingly, the overcurrent indicator 180 indicates the occurrence of an overcurrent and at the same time the releasing device 80 actuates the interrupting connectors 201, 202 and 203. The above-mentioned time-current characteristic of the curves A, B and C are designed taking into account the capacity of fuses in the upper stream part of the power line 10. On the other hand, the outputs of the full-wave rectifiers 31, 32 and 33 are given to the OR circuit 130 comprising diodes 131, 132 and 133. Since the output terminal of the OR circuit 130 is connected to the second level discrimination circuit 140 which, for instance, comprises at least one zener diode, when one input signal to the OR circuit 130 exceeds the second level, the discrimination circuit 140 gives an output signal to the second time-current operating circuit 150, which accordingly carries out necessary time-current operation, and thereby triggers the gate of the thyristor 120. The time-current operation in this case is, for instance, as shown by the part B of the short time current inverse characteristic or the part C of instantaneous time-current characteristic. By the above-mentioned turn-on of the thyristor 120, the output device 80 is actuated, thereby the indicator 180 indicates the kind of the overcurrent and also drives the interruption connectors 201, 202 and 203. In this prior art circuit breaker, one mean/effective value circuit is necessary for each respective phase. Therefore, the circuit becomes complex and expensive. Further adjusting operation is necessary for averaging the outputs of the mean/effective value circuits. Therefore, the production process becomes complex, too. OBJECT AND SUMMARY OF THE INVENTION It is an object of the invention to provide an overcurrent detector having a simpler circuit not requiring the above-mentioned adjusting operation. According to the invention, this object is achieved by the overcurrent detector specified in claim 1. While the novel features of the invention are set forth particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is the circuit block diagram of the overcurrent detector of the prior art. FIG. 2 is the current vs. time characteristic graph of the prior art overcurrent detector. FIG. 3 is a circuit block diagram of a first embodiment in accordance with the present invention. FIG. 4 is a detailed circuit diagram of the microcomputer 110 of the circuit of FIG. 3. FIG. 5 is a flow chart showing the operation of the microcomputer shown in FIG. 4. FIG. 6 is a circuit block diagram of a second embodiment in accordance with the present invention. FIG. 7 is a current vs. time characteristic graph of the overcurrent detector of FIG. 6. FIG. 8 is a circuit block diagram of still another embodiment in accordance with the present invention DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, details of the invention are described with reference to the drawings. In FIG. 3, on a set of power lines R, S and T of three phase power lines 10, current transformers 21, 22 and 23 of a current sensor means 200 are provided, respectively. Full-wave rectifiers 31, 32 and 33 are connected with their two input lines across both output lines of the current transformers 21, 22 and 23, respectively. Burden circuits 41, 42 and 43 are connected with their input lines to output lines of the full-wave rectifiers 31, 32 and 33, respectively, and the output lines of the burden circuit 41, 42 and 43 are connected to the input terminals of an OR circuit 130, which consists of three diodes 131, 132 and 133, the output terminals of which are connected in common as an output terminal of the OR circuit 130. Adjustable output terminals of the burden circuits 41, 42 and 43, wherefrom output signals can be obtained in desirably adjusted levels, are connected to input terminals of a phase selecting circuit 400. The phase selecting circuit 400 selects, as largest phase, a phase which consists of largest value in inputted values. The largest phase selected by the phase selecting circuit 400 is connected to a signal conversion circuit 90 for obtaining a geometric mean of inputted value. The converted output signal of the signal conversion circuit 90 is converted from analog signal into digital signal by an A/D converter 100. The digital output of the A/D converter 100 is inputted to a microcomputer 110. The output of the microcomputer 110 is connected to a gate of a thyristor 120 for operating a releasing device 80. The releasing device 80 actuates the disconnectable contacts 201, 202, 203 to disconnect. The output of an OR circuit 130 is connected to a second time-current operation circuit 150 through zener diodes 140. An output of the second time-current operation circuit 150 is connected to the gate of thyristor 120 for operating the releasing device 80. The releasing device 80 disconnects the disconnectable contacts 201, 202 and 203 in response to on state of the thyristor 120. The constitution and processing of the microcomputer 110 are described with reference to FIGs. 4 and 5 hereafter. FIG. 4 is a circuit block diagram of the microcomputer 110. As shown in FIG. 4, the microcomputer 110 comprises a central processor unit 111, a read-only memory 114, a random-access memory 115, and I/O port 116, a data bus 112 and an address bus 113. Parts of the data bus 112 and the address bus 113 are also connected to the A/D converter 100. The read-only memory 114 stores a program for executing necessary signal processing, and also data for a long time characteristic, a short time characteristic and an instant time characteristic of the first time-current operating means. The central processor unit 111 contains clock signal means necessary therefor. The random-access memory 115 functions as a register which is necessary for the signal processing. FIG. 5 is a flow chart of the computer program for the microcomputer 110. The flow chart contains a first level-discrimination step (step 1001) and a first time-current operating step (step 1002) for performing a first time-current operation in response to the output of the first level discrimination means. The flow chart also contains decrement means (step 1003) for decreasing the register in response to radiation characteristics. When overcurrent(s) flows in the AC power lines 10, the current transformers 21, 22 and 23, coupled to the AC power lines R, S and T of the AC power lines 10, correspondingly produce output currents at predetermined transforming ratios. The output currents are rectified by the full-wave rectifiers 31, 32 and 33, respectively. The rectified output currents of the full-wave rectifiers 31, 32 and 33 are fed to respective burden circuits 41, 42 and 43. The outputs of burden circuits 41, 42 and 43 are inputted to a phase selecting circuit 400 which selects, as largest value phase, a phase which consists of largest value from inputted phases. The selected largest value phase is inputted to the signal conversion circuit 90 and converted into a signal which is the geometric mean thereof. The geometric mean output is fed to the A/D converter 100 which converts the analog signal into a digital signal. This digital signal is fed to the microcomputer 110, which carries out level discrimination with respect to the digital signal. Further, the microcomputer carries out first time-current operation and issues an output signal from the output port 116. The output signal is fed to the gate of thyristor 120 for driving the releasing device 80 which disconnects the disconnectable contacts 201, 202 and 203. On the other hand, outputs of the burden circuits 41, 42 and 43 are inputted to OR circuit 130 which consists of the diodes 130, 131 and 132. The output of the OR circuit 130 is connected to the second time-current operating circuit 150 through the zener diodes 140 as second level-discrimination. Therefore, when the output of OR circuit 130 is over a zener voltage of the zener diode 140, the output of OR circuit 130 is fed to the second time current operating circuit 150. The second time-current operating circuit 150 carries out the predetermined second time-current operation for triggering the thyristor 120 for driving the releasing device 80. The microcomputer 110 rises up, and then the computer program shown in flow chart of FIG. 5 starts. The system is initiallized (i.e. setting of I/O port, and setting/resetting of flags are made,) at a step F2. Then, the microcomputer 110 controls the A/D converter 100 to convert the output signal of signal conversion circuit 90 into a digital signal (step F3). This digital data is stored in the RAM 115. Next, it is determined whether this digital data indicates overcurrent or not (step 1001). When the digital data does not show an overcurrent, the operation jumps from the heat charging routine to the heat discharging routine and then returns to the A/D conversion (step F3). When the digital data shows an overcurrent, a heat charging flag H is set in the step F4, and bits for heat charging is added for every predetermined unit times by utilizing the random access memory 115 or a register in the central processor unit 111, so as to count time responding to amount of input signal level. The heat charging bits are selected in order to realize time-current operation along the characteristic curves of FIG. 2. Then, the added bits number is examined whether the time is up for the selected time-current operation of the predetermined characteristic. And as a result, when the added bits number does not yet reach the predetermined number, in other words, when the time is up, an output is issued through the I/O port 116 to drive the thyristor 120, and thereby to actuate the first indicator 180 and the output device 80. Nextly, operation of heat discharging routine, namely, the routine for resetting the time-current operation is described. The steps F5, 1003, F8 and F9 together form a heat discharging routine. It is discriminated whether the heat charging flag H has been set or not (step F5). When the heat charging flag H has been set, the heat charging flag H is decreased at the step 1003 for every predetermined unit times. When the counted number of the bits becomes 0 as a result of the subtractions in the step F9, the heat discharging routine goes back from the step F9 to the A/D conversion step F3. When the counted number of the bits is not entirely reset, the heat charging flag H is not reset and the heat discharging routine goes back from the step F8 to the A/D conversion step F3. As above-mentioned, the microcomputer gives most appropriate time-current operating characteristic, taking account of heat charging and heat discharging in the electric power lines and loads. Incidentally, addition or subtraction of the heat charging and heat discharging can be executed in the inverse order to the above-mentioned embodiment. The calculation for effective value in the microcomputer 110 is described. The A/D converted value stored in the register is which corresponds to the current Im, where is defined as the mean square of On the other hand, the effective value Im rms is defined as follows: where T = 2π/ω and ω = angular frequency of Im. The formula (1) is equivalent with following: To obtain the time-current operating characteristic in accordance with the effective value, the microcomputer 110 calculates the root of the A/D converted value. In another embodiment, the roots of the A/D converted values are preliminarily stored in ROM by utilizing a look-up table method. FIG. 6 shows another embodiment in accordance with the present invention. An output of the signal conversion circuit is fed to a current conversion circuit 910. The current conversion circuit 910 has a function of level discrimination which is provided for carrying out the conversion operation only when the inputted signal is over a predetermined level. The current conversion circuit 910 examines whether the output of the signal conversion circuit is over the predetermined level or not. When the output of the signal conversion circuit is over the predetermined level, the current conversion circuit 910 outputs a current corresponding to An integration circuit and timing circuit which forms a third time current operating circuit 920, can be realized by combination of capacitance charge circuit comprising known charge circuit and level discrimination element by PUT etc. By charging the current corresponding to the integration value corresponding to square mean can be obtained. Further, the effective value can be obtained at longer integration time than a time period caused by an overcurrent. Therefore, back-up time-current characteristic of the curve G is easily obtained. When the time is up, the time-current operating circuit 920 issues the output for driving the releasing device 80. As described above, in this embodiment, as a result of introducing the current conversion circuit 910 and the third time-current operating circuit 920, the protection operation can be carried out even in case of trouble of microcomputer 110. Because the signal converting circuit 900 is provided, the current converting circuit 910 and time-current operating circuit 920 as back-up circuit becomes simple. In another modified embodiment, the current converting circuit 910 does not have the above-mentioned level discrimination function. In this case, wider range back-up can be achieved. FIG. 8 shows still another embodiment in accordance with the present invention. In FIG. 8, an output of the microcomputer 110 is converted into an analog signal by a D/A converting circuit 141 and then is impressed to an input terminal of the operational amplifier 143. To another input terminal of the operational amplifier 143, a reference voltage Vref is impressed. Where the output of D/A converting circuit 141 is Vt, the output Vs of the operational amplifier 143 is as follows: Vs = 2Vref - Vt. The output Vs is inputted to one input of a comparator 142 as threshold value. To another input of the comparator 142, the output from the OR circuit 130 is inputted. Second level-discrimination means 140 comprises the comparator 142, D/A converting circuit 141 and operational amplifier 143. An output of the comparator 142 is inputted to a second time-current operating circuit 150 as second time-current operating means. The rectified output currents of the full-wave rectifiers 31, 32 and 33 are fed to the OR circuit 130 which comprises diodes 131, 132 and 133. The output of the OR circuit 130 is inputted to an input terminal of the comparator 142. When this inputted signal is over a threshold value Vs which is inputted to the other input terminal of the comparator 142, an output of the comparator 142 is reversed and an operating signal is inputted to the time-current operating circuit 150. The threshold value is defined by the difference between the reference voltage Vref and the analog voltage which is converted from the digital output having a predetermined value of output port 117 of the microcomputer 110 by D/A converting circuit 141. The time-current operating circuit 150 carries out the time-current operation in accordance with the output signal from the comparator 142, and triggers the gate of thyristor 120. The above-mentioned time-current operation is carried out along the instantaneous characteristic (curve C of FIG. 7). The threshold value can be easily changed by changing the output of microcomputer 110 and can be accurately determined. Even when the D/A converted output is not produced before rising the microcomputer, a predetermined value is given as the threshold value for the second level-discrimination means. Therefore, the protection can be realized even in rising or troubling of the microcomputer. In other modified embodiment, a multiplexer is used instead of OR circuit 130 for selecting the signal with time division.

Claims: An overcurrent detector, comprising: first means (21-23, 31-33, 41-43) for sensing the currents in the respective phases (R, S, T) of an AC power line (10); second means (400, 90, 100, 110) for providing the mean/effective value of the largest current of said phases (R, S, T); third means (110) for processing said mean/effective value provided by said second means (400, 90, 100, 110) and for issuing a first releasing signal; and fourth means (130, 140, 150) for providing the largest instantaneous value of the currents in said phases and for issuing a second releasing signal; characterized in that said second means comprises a phase selection circuit (400) for selecting the largest current value of said phases (R, S or T), a signal conversion circuit (90) for providing an analog signal representing the mean square value of the current selected by said phase selection circuit (400), an A/D converter (100) for converting this analog signal into a digital signal and digital processing means (110) for providing the square root of the digital signal from said A/D converter (100) to obtain said mean/effective value. An overcurrent detector according to claim 1, characterized in that said processing means (110) includes a microprocessor (110) for discriminating the level of said mean/effective value; and for performing a time-current operation when said mean/effective value is above a predetermined threshold value. An overcurrent detector according to claim 1 or 2, characterized by fifth means (910, 920) for discriminating the level of the output signal of said signal conversion circuit (90) and for performing a time-current operation when the output signal of said signal conversion circuit (90) is above a predetermined value discriminated by said fifth means (910, 920). An overcurrent detector according to one of claims 1 to 3, characterized in that said processing means (110) outputs a controllable reference value and in that said fourth means (130, 140, 150) issues said second releasing signal when said largest instantaneous value exceeds a difference between said reference value and a predetermined value (Vref). An overcurrent detector according to claim 4, characterized in that it comprises a D/A-converter (141) for converting said controllable reference value outputted by the processing means (110) into an analog form. An overcurrent detector according to claim 4 or 5, characterized in that said fourth means (130, 140, 150) comprises a comparator (142) for issuing said second releasing signal. An overcurrent detector according to one of claims 1 to 6, characterized in that it comprises an OR-gate (121) for combining the releasing signals from the third and fourth means to form a single releasing signal. A circuit breaker comprising an overcurrent detector according to one of claims 1 to 7, wherein a disconnectable contact (201, 202, 203) provided in said AC power line (10) is controlled by any of said releasing signals.

Inventors: ARINOBU, ICHIROU
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1987
Main classification: H02H3
IPC codes: H02H3