FREQUENCY RESPONSE COMPENSATION CIRCUIT

Abstract: A frequency response compensation circuit includes a first forward gain stage (J1, T1, T1′, R1, R1′, R3, R3′) and a second reverse gain stage (J2, T2, T2′, RE, RE′, R2, R2′) coupled to the first stage in negative feedback mode. The reverse gain stage depresses the gain of the first stage at low frequencies. When the frequency response of the reverse gain stage begins degrading, which corresponds to the frequency of the real zero of the compensation circuit, the gain of the compensation circuit begins increasing and increases until the gain of the reverse stage is zero. The circuit consists of only transistors and resistors and so can be formed as an integrated circuit. By proper selection of the resistors in the circuit, the zero of the compensation circuit can be chosen to correspond to the frequency of the pole of the uncompensated input, so as to increase the bandwidth. Multiple reverse gain stages can be included, with a selected reverse gain stage switched into connection with the first stage, so as to provide a constant frequency response for different frequency response inputs.

Description: This invention relates to a circuit for compensating the frequency response of an electronic system. In specific circuit applications it is often necessary to correct the frequency response of a particular system. Circuits for accomplishing such frequency response compensation are well known, and typically involve the use of capacitors and inductors. For example, phase lead and lag networks employing operational amplifiers with passive element negative feedback configurations are known, as described in Handbook of Operational Amplifier Applications , Burr-Brown Research Corp., First Edition, 1963. However, because such circuits require the use of capacitors and inductors, they cannot be used in applications where it is necessary or desirable to implement the entire circuit into integrated technology. US-A-3 427 560 describes a direct current amplifier circuit comprising a first stage having an input signal amplifier configured as a forward path stage. A second stage configured as a feedback, or reverse, path stage is coupled to the first stage in a negative feedback mode for depressing the gain of the first stage. The circuit elements of the first and second stages consist only of transistors and resistors. However, the second stage does not comprise frequency compensation means for depressing the gain of the first stage at low frequencies only. In certain applications the electronic system may in fact comprise several different systems, each having a different frequency response. For example, in magnetic recording disk files, the read/write channel may be connected to a multiple number of separate preamplifiers, each of which amplifies the signal from an associated read/write transducer. Because of the variations in the individual transducers, as well as variations in the length of the electrical leads from the transducer to the read/write channel, the output of each preamplifier will typically have a frequency response to different from that of the other preamplifiers. The invention seeks to provide a frequency response compensator which can be readily formed as an integrated circuit. In accordance with the present invention, there is now provided a frequency response compensation circuit comprising: a first stage having an input signal amplifier configured as a forward path, or gain, stage; a second stage configured as a feedback, or reverse, path and coupled to the first stage in a negative feedback mode; the elements of the first and second stages consisting only of transistors and resistors; characterised in that the second stage comprises frequency compensation means defining a real zero and a real pole at respectively first and second frequencies in the frequency response of the circuit, the first frequency being lower than the second frequency to depress the gain of the first stage for input signals below the second frequency. Because the first and second stages consist only of transistors and resistors, the circuit may be conveniently implemented as a semi-conductor integrated circuit. Preferably, the forward gain stage includes a current source, resistors and NPN transistors, and the reverse gain stage includes a current source, PNP transistors. The reverse gain stage decreases the gain of the forward gain stage at low frequencies. The reverse gain stage has a degenerated high frequency response and can be designed such that the gain of the compensator begins increasing at approximately that frequency at which the gain of the uncompensated electronic system begins decreasing. The frequencies of the zero and pole of the compensator are functions of, among other things, the transition frequency of the PNP transistors in the reverse gain stage. By proper selection of the values of the resistors in the compensator, the frequency of the zero of the compensator may be selected to occur at approximately the same frequency as the pole of the uncompensated electronic system, so as to extend the frequency response of the resultant system. As the compensator can be fabricated in integrated circuit format, it is possible to form multiple reverse gain stages on the same semiconductor chip. Thus, different uncompensated systems, each with its own frequency response, can be compensated by switching in different current sources for the reverse gain stages. The resistance values of emitter resistors in the different reverse gain stages can be selected such that the gain of the compensator remains the same when the different reverse gain stages are switched in to compensate these different systems. How the invention can be carried out will now be described by way of example, with reference to the accompanying drawings, in which:- Fig. 1 is a circuit diagram of a frequency response compensator embodying the invention, Fig. 2 is an asymptotic Bode diagram illustrating the frequency response of the compensator, and the first stage of the compensator in the absence of the second stage; Fig. 3A is an asymptotic Bode diagram illustrating the resultant frequency response when the frequency of the compensator zero is at the same frequency as the pole of the uncompensated system; Fig. 3B is an asymptotic Bode diagram illustrating a peaking of the gain of the resultant signal if the frequency of the compensator zero occurs before the frequency of the pole of the uncompensated system; and Fig. 3C is an asymptotic Bode diagram illustrating the resultant frequency response if the compensator zero occurs after the pole of the uncompensated system. An electronic system whose frequency response is to be compensated is represented as the input V₁ (Fig. 1) to a frequency response compensation circuit embodying the invention, and V o is the output of the compensator. The first stage of the compensator is a forward gain stage and includes NPN transistors T1, T1′; NPN collector resistors R1, R1′; NPN emitter resistors R3, R3′; and current source J1. The second stage, which is a reverse gain stage, is connected to the first (forward) gain stage at nodes N1, N1′, N2, N3, and N3′. The reverse gain stage includes PNP transistors T2, T2′; resistors R2 and R2′; PNP emitter resistors RE and RE′ and current source J2. Because no capacitors or inductors are used in the compensator of Fig. 1, it can be formed in an integrated circuit. The asymptotic Bode diagram of the frequency response compensator is illustrated as solid line 10 in Fig. 2. The reverse gain stage is used to decrease the gain of the forward gain stage at low frequencies. Because of the presence of the two PNP transistors, the series base resistors R2 and R2′ and emitter resistors RE and RE′, the reverse gain stage has a degenerated high frequency response. The result of the combination of the forward gain stage and reverse gain stage is that the real zero of the compensator (Z c ) occurs at a lower frequency than the real pole of the compensator (P c ). The low frequency gain is A l and the high frequency gain A h . That portion of the compensator frequency response where the gain is A l is the frequency range over which the negative feedback from the second stage depresses the gain of the first stage. At Z c the frequency response of the second stage begins degrading and thus the effect of the feedback on the first stage begins to lessen. The frequency P c is determined by the product of the zero, Z c , and the d.c. loop gain A h /A l . That portion of the compensator frequency response where the gain is A h is where the gain is due mainly to the first stage. Dashed line 20 in Fig. 2 represents the frequency response the compensator would exhibit if the reverse gain stage were not present in the circuit of Fig. 1. The following equations (1) through (4) express the frequencies of the compensator pole and zero and the gain at low and high frequencies as functions of the parameters of the circuit elements shown in Fig. 1, where RE = RE′, R1 = R1′, R2 = R2′ and R3 = R3′, and it is assumed that the d.c. loop gain is much greater than 1. The following definitions apply to equations (1) through (4): rE = differential emitter resistances of the NPN transistors = (k T / q Ic1) = (J1 - J2)/2, Ic1 = collector current of the NPN transistors, re = differential emitter resistances of the PNP transistors = (k T / q Ic2) = J2/2, Ic2 = collector current of the PNP transistors, k = Boltzmann's constant, T = absolute temperature, q = electron charge, Bp = forward current gain of the PNP transistors, and Ft PNP = transition frequency of the PNP transistors. Equations (1) through (4) have been simplified by assuming that Ft PNP is much less than the transition frequency of the NPN transistors, and that re is much less than RE. In addition, the base spreading resistance of the PNP transistors T2 and T2′ has been included in the values for R2 and R2′. By referring to equations (1) through (4), it will be noted that A l , Z c and P c can be selected by proper selection of resistance values and Ft PNP . The selection of A l results in the setting of A h . Referring now to Fig. 3A, the frequency response of an uncompensated system, represented as line 30 with low frequency gain A u , is desired to be corrected to increase its bandwidth so as to give a resultant frequency response, represented as line 32. As shown in Fig. 3A, if the frequency of the compensator zero (Z c ) is at the same frequency as the pole of the uncompensated electronic system (P u ), the bandwidth of the electronic system is extended, with a flat frequency response A r , to the pole of the compensator (P c ). The frequency response of the compensator is designated as line 34. If it is desired to provide a peak gain over a particular frequency range, then the resistor values in the circuit of Fig. 1 can be selected such that Z c occurs before P u . Thus, as shown in Fig. 3B, the frequency response 44 of the compensator causes the uncompensated frequency response 30 to be modified to generate a peak gain in the resultant frequency response 42 at a frequency beyond Z c . The amount of peaking is limited to the difference between A l and A h (Fig. 2), which is defined by the selection of resistor values in the compensator. Referring to Fig. 3C, the resultant frequency response will be as shown by line 52 if Z c of the compensator's frequency response 54 is greater than P u . Assuming that Z c is not too much greater than P u , the resultant bandwidth will be greater than the uncompensated bandwidth. Referring again to Fig. 1, nodes N1, N1′, N2, N3 and N3′ are common nodes separating the forward gain stage from a number of selectable reverse gain stages, only one of which is shown in Fig. 1. Thus, it is possible to vary the bandwidth of the resultant system by selecting the proper reverse gain stage. The reverse gain stages can be selected by switching in the appropriate current from the current source J2 associated with each reverse gain stage. Thus, if the compensator of Fig. 1 having multiple reverse gain stages is connected to several input systems having different frequency response characteristics, then an identical compensated frequency response for each input can be achieved by selecting the appropriate reverse gain stage. Thus such a compensator can be connected to different input preamplifiers, each having its own unique frequency response, for creating a resultant frequency response which is the same for each input. In addition, if the compensator having multiple reverse gain stages connected to the common nodes is connected to an electronic system with a single frequency response, then different frequency response outputs can be achieved by selecting an appropriate reverse gain stage. In the embodiment having multiple reverse gain stages, each pair of PNP transistors will have associated with it a unique emitter current and base resistances. Thus, when different reverse gain stages are selected the compensator may have different gains. However, by proper selection of RE and RE′ (Fig. 1) the difference in compensator gain when different reverse gain stages are selected can be eliminated so that the compensator has the same gain, regardless of which reverse gain stage is selected.

Claims: A frequency response compensation circuit comprising: a first stage (J1, T1, T1', R1, R1', R3, R3') having an input signal amplifier configured as a forward path stage; a second stage (J2, T2, T2', RE, RE', R2, R2') configured as a feedback path stage and coupled to the first stage in a negative feedback mode; the elements of the first and second stages consisting only of transistors and resistors; characterised in that the second stage defines a real zero (Zc) and a real pole (Pc) at respectively first and second frequencies in the frequency response of the circuit, the first frequency being lower than the second frequency to depress the gain of the first stage for input signals below the second frequency. A circuit as claimed in claim 1, which has a real zero occurring approximately at the frequency of the real pole of the frequency response to be compensated. A circuit as claimed in claim 1, wherein the real zero of the compensating circuit occurs at a frequency lower than the frequency of the real pole of the frequency response to be compensated, whereby the resultant compensated frequency response has a peak gain over a predetermined frequency range. A circuit as claimed in any preceding claim, wherein the transistors in the first stage are NPN transistors and wherein the transistors in the second stage are PNP transistors. A circuit as claimed in claim 4, wherein the first (forward gain) stage consists of a pair of NPN transistors, a pair of collector resistors, a pair of emitter resistors and a first current source connected between the emitter resistors; and the second (reverse gain) stage consists of a pair of PNP transistors, a pair of emitter resistors, a pair of base resistors and a second current source connected between the reverse gain stage emitter resistors. A circuit as claimed in claim 5 when appendant to claim 2, wherein the resistors of the first and second stages have resistance values such that the real zero of the circuit occurs at approximately the same frequency as the real pole of the frequency response to be compensated. A circuit as claimed in any preceding claim, further comprising a plurality of second stages and means for switching any selected one of said second stages into connection with the first stage.

Inventors: JOVE, STEPHEN ALAN, KLAASSEN, KLAAS BEREND, VANPEPPEN, JACOBUS CORNELIS LEONARDUS, VO, CHON NGOC
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: H03F1
IPC codes: G11B5, H03F1, H03G7