Raster correction circuit

Abstract: In a deflection circuit such as for a CRT display device, modulated current that is generated in a raster control circuit especially for East-West pincushion distortion correction, is coupled to a deflection circuit output stage (100) via a Class A operated amplifier (Q2) serving as a current source having a high output impedance during retrace. The current source prevents coupling of a signal at a retrace frequency during retrace between a high voltage winding (W1) of the flyback transformer (T1) and a retrace resonant circuit (27) that includes the deflection winding (L H ). The high output impedance of the amplifier current source during retrace maintains the average value of the modulated current during retrace unaffected by an amplitude of a retrace voltage that is developed in the retrace resonant circuit (27). In this way, ultor voltage loading variation is prevented from causing "mouseteeth" distortions.

Description: This invention relates to a deflection circuit in which the amplitude of the deflection current may be varied or modulated over a relatively wide range by supplying a modulation current from a terminal of a semiconductor having a high output impedance. Modulation of the deflection current amplitude is desired for such purposes as correction of outside and of inside east-west pincushion distortion. Typically, a horizontal deflection circuit such as provided in association with a CRT display device comprises an output stage that includes a horizontal deflection winding and a trace capacitance that supplies deflection current to the deflection winding during each trace interval. A retrace capacitance is coupled across the deflection winding during the retrace interval to form a retrace resonant circuit. Energy is replenished during retrace via a flyback transformer. The heavy loading, or high beam current in a secondary winding of the flyback transformer, that occurs in the course of displaying, for example, each white horizontal strip of a crosshatch pattern represents a heavy load to the flyback transformer during retrace. In some prior art circuits in which the retrace resonant circuit is coupled via a relatively small modulation inductance of an east-west control circuit to the primary winding of the flyback transformer, the retrace capacitance may be slightly discharged during retrace due to the aforementioned loading. This may result in a discharge current from the trace capacitance into the retrace capacitance through the deflection winding and a slight drop of the voltage across the trace capacitance during the white horizontal strips of the crosshatch pattern. The charge of the trace capacitance is replenished during the retrace intervals associated with the scan lines that display the black picture portion underneath the white crosshatch stripes. This causes a small current in the opposite direction through the deflection winding. The charge and discharge current of the trace capacitance produces a small raster displacement and results in low frequency oscillations modulating the deflection winding trace current. This low frequency modulation may cause each vertical strip of the crosshatch pattern to appear as being of a zig-zag shape, instead of a straight line shape. The zig-zag shape appears in a given vertical strip immediately below the intersection point with a horizontal strip. Such distortions are sometimes referred to by the name "mouseteeth" distortions. They appear, during and just after the times in which high beam current transients occur, because the deflection circuit that represents a low impedance energy flywheel, supplies the transient increase in energy requirement of the ultor circuits. Thus, energy transferred from the deflection circuit to the ultor circuits may tend to cause variations in the deflection winding trace current. "Mouseteeth" distortions may be reduced in an arrangement such as described in UK Published Application 2150796A, published 3 July 1985, corresponding to U.S. Patent No. 4,634,937, entitled EAST-WEST CORRECTION CIRCUIT, issued to P.E. Haferl on 6 January 1987, that is referred to herein as the Haferl patent, by supplying an E-W modulation current generated by an east-west control circuit via a choke having a high impedance. This choke integrates the horizontal frequency components resulting in a sink current that is substantially a D.C. current that flows from the deflection circuit to the E-W control circuit. Deflection disturbances referred to as "mouseteeth" are avoided because of the loose coupling between the flyback transformer and the deflection winding during the retrace interval. The loose coupling is provided by the choke that provides high frequency isolation of the deflection circuit output stage from the E-W control circuit. Since a suitable choke may be expensive, it may be desirable to reduce the "mouseteeth" distortion without using such choke. The present invention provides a deflection apparatus with raster distortion correction, comprising: a source of input signal at a frequency that is integrally related to a first deflection frequency; a deflection winding; switching means coupled to said deflection winding, said switching means operating, in accordance with said input signal, at said first deflection frequency for generating scanning current in said deflection winding during a trace interval of each deflection cycle; a deflection retrace capacitance coupled to said deflection winding to form a deflection retrace resonant circuit that produces a first retrace pulse voltage at a retrace frequency during a retrace interval of each deflection cycle; a source of supply voltage; a supply inductance connected to receive said supply voltage and coupled to said switching means for generating a second retrace pulse voltage in said supply inductance said supply inductance being effective to supply to said retrace resonant circuit during said retrace interval a supply current from said source of supply voltage that replenishes energy losses in said retrace resonant circuit; a load circuit at energized by said second retrace pulse voltage in said supply inductance; and a source of a modulation signal; characterized by controllable means, including semiconductor means, responsive to said modulation signal for generating a resonant circuit that is applied to said retrace resonant circuit to modulate said scanning current for providing raster distortion correction, said semiconductor means forming an output impedance for said modulation current that during said retrace interval is sufficiently large to prevent a high frequency coupling between said supply inductance and said retrace resonant circuit during said retrace interval. In accordance with an aspect of the invention, a deflection circuit output stage, responsive to an input signal at a frequency that is related to a deflection frequency, includes a retrace capacitance that is coupled to a deflection winding to form a retrace resonant circuit during retrace. A supply inductance generates, in accordance with the input signal, a pulse voltage during retrace that is coupled to a load circuit. A control circuit, responsive to a second signal, generates a modulation current at a second frequency that is coupled to the retrace resonant circuit via a semiconductor arrangement having a high output impedance. The high output impedance of the semiconductor arrangement isolates the supply inductance from the retrace resonant circuit to prevent load variation in the load circuit from affecting the retrace resonant circuit. Color television picture tubes with a large faceplate radius, such as, for example, Philips 45AX picture tube, may require a significantly high amount of inside pincushion correction. The deflection circuit typically includes a deflection transistor switch operating at a deflection rate coupled in parallel with a damper diode arrangement. An inside pincushion correction current generated by an inside pincushion correction circuit that is coupled to a trace capacitor, may, disadvantageously, back-bias the damper diode arrangement during trace. When the damper diode arrangement includes, for example, a pair of series coupled diodes, it may be desirable to couple the junction terminal between the series coupled diodes to ground via a conductive switch throughout the first half trace so as to clamp, via one of the diodes, the collector voltage of the deflection transistor switch to ground potential. In accordance with another aspect of the invention, the transistor, mentioned before, that has the high output impedance and that supplies the modulated current during retrace to provide outside distortion correction, is coupled at the junction terminal between the diodes. Such transistor that supplies the modulated current during retrace, operates as a switch that is conductive during trace. Thus, advantageously, it clamps the collector voltage of the deflection transistor switch to a potential that is close to ground potential. In the accompanying drawings: FIGURE 1 illustrates a deflection circuit, embodying an aspect of the invention, that includes inside pincushion correction arrangement; FIGURES 2a-2f illustrate waveforms useful in explaining the circuit of FIGURE 1; FIGURES 3a-3e illustrate additional waveforms useful in explaining the circuit of FIGURE 1; FIGURES 4a-4b illustrates waveforms, that occur during retrace, and that are useful in explaining the circuit of FIGURE 1; FIGURE 5 illustrates a second embodiment of the invention; FIGURES 6a-6e illustrate waveforms associated with the circuit of FIGURE 5; FIGURE 7 illustrates a crosshatch pattern in which "mouseteeth" distortion is uncorrected; and FIGURE 8 illustrates a portion of a deflection circuit, forming a third embodiment of the invention. A deflection circuit 100 of FIGURE 1, embodying an aspect of the invention, may provide horizontal deflection of the electron beams in, for example, a Philips 110° 45AX FS color picture tube type A66-EAK00X01. In FIGURE 1, a source of regulated direct current voltage B+, developed between a terminal 22 and ground, is coupled through a small-valued resistor R1 to a terminal 22a of a primary winding W1 of a horizontal flyback transformer T1. The other terminal of winding W1 is coupled to a junction terminal 23. A filtering capacitance C1 is coupled from terminal 22a to ground. Regulated voltage B+ is generated, for example, by a switched mode power supply 90. A secondary winding W3 of transformer T1, supplies an ultor voltage U through a rectifying diode D40. A horizontal output transistor Q1, operating at a deflection rate f H and having its base coupled to a conventional driver and oscillator circuit 50, has its collector-to-emitter path coupled between junction terminal 23 and ground. Circuit 50 is synchronized by a sync signal H s and by a retrace pulse representative signal H r , in a well known manner. Paralleling transistor Q1 is the series arrangement of two rectifiers, diodes D 1 and D 2 operating as a damper diode arrangement. Coupled in parallel with the anode and cathode electrodes of diode D 1 is an arrangement of a horizontal deflection winding L H that is coupled to an S-shaping, or trace, capacitance C s . A deflection retrace capacitance CRD, coupled also in parallel with the anode and cathode electrodes of diode D 1 , forms with deflection winding L H , a parallel retrace resonant circuit 27. A second retrace capacitance C RT iscoupled between a junction terminal 28 and ground. A small-valued capacitance C P is coupled between terminal 23 and ground. Capacitance C P provides fine tuning of the resonance frequency of retrace resonance circuit 27. Coupled between terminal 28 of deflection winding L H , at the junction between capacitance C RT and capacitance C RD , and ground, is a series arrangement of a diode D 3 and a controllable East-West current source 25 that includes a current sink transistor Q 2 having, at the collector electrode, a high output impedance during retrace. The collector electrode of transistor Q 2 is coupled via a diode D 3 to terminal 28 to provide a modulated sink current i 3 that varies in a vertical rate parabolic manner. Diode D 3 decouples the collector of transistor Q 2 from ground, toward the end of trace, when diode D 2 conducts, to prevent the flow of saturation collector current in transistor Q 2 , prior to retrace. An inside pincushion distortion correction circuit 60 includes an inductance L1 that is coupled to a terminal 60a at the junction of capacitance C s and inductor L H . A capacitor C 6 of circuit 60 is coupled between a terminal 60b and ground. During the first half of trace, deflection current i 1 flows, in a direction opposing the arrow, in deflection winding L H and in diode D 1 . During the second half of trace, deflection current i 1 flows in deflection winding L H , in the direction of the arrow, and in diode D2 and transistor Q1 that is conductive. At the end of trace, transistor Q1 becomes nonconductive and a retrace voltage V 1 is developed between terminal 23 and ground. During the retrace interval, charge is taken away from retrace capacitance C RT by East-West modulated sink current i 3 that flows via diode D 3 . The higher the integral ∫i 3 dt, over the entire retrace interval, for example, the larger becomes a retrace voltage V41 across capacitance C RD and the smaller becomes a modulated voltage V 3 across capacitance C RT . The peak of deflection current i 1 through deflection winding L H , during the trace interval, is directly related to the peak of retrace voltage V41 across capacitance C RD at the center of the retrace interval. By modulating current i 3 of transistor Q 2 at a vertical rate, switched current source 25 provides outside pincushion correction to horizontal scanning current i 1 . As described later on, the average value of modulation current i 3 during each retrace interval is controlled in such a way that it remains unaffected by retrace voltage V 3 . Thus, transistor Q 2 forms, with respect to the average value of current i 3 , a high output impedance. In accordance with an aspect of the invention, the above mentioned high output impedance of transistor Q 2 that is interposed between winding W1 and retrace resonant circuit 27 prevents, during horizontal retrace, an undesirable high frequency coupling through current source 25 between winding W1 of flyback transformer T1 and retrace resonant circuit 27 that, otherwise, could have caused "mouseteeth" distortion. Moreover, the high output impedance of transistor Q 2 prevents any retrace voltage from affecting the collector current in transistor Q 2 that provides East-West modulation. In contrast, in some prior art circuits, "mouseteeth" distortion is prevented by supplying the East-West modulated current, instead of through the high output impedance of the transistor of the present invention, via a choke having a high impedance. The choke, however, disadvantageously, may be expensive. An example of such prior art is described in the Haferl patent that was mentioned before. Capacitor C RT is coupled to winding W1 via ground and capacitor C 1 to form a second retrace resonant circuit that is coupled to retrace resonant circuit 27 so as to form a combined retrace resonant circuit that includes winding W1, capacitor C RT and retrace resonant circuit 27. The combined retrace resonant circuit is tuned to, for example, the retrace frequency. In order to tune the combined resonant circuit to the retrace frequency, each of retrace resonant circuit 27 and the second retrace resonant circuit that includes winding W1 and capacitor C RT is tuned to a frequency that may be lower than the retrace frequency. Capacitor C RT causes the retrace voltage across winding W1 and that across deflection winding L H to occur simultaneously. Therefore, retrace voltage H r across winding W4 that provides synchronization information to Driver and oscillator 50, advantageously, contains the same synchronization information as of the retrace voltage across deflection winding L H or as of voltage V 41 across capacitor C RD . The purpose of capacitor C RT is described in detail in the Haferl Patent. The values of the capacitors C P , C RD and C RT are selected to obtain the correct retrace time and to avoid retrace time modulation of voltage V 1 . Capacitor C RT determines the lowest deflection current amplitude that corresponds with current i 3 that is zero. Except for a short interval that occurs immediately at the beginning of retrace when transistor Q 2 is still in saturation, transistor Q 2 of E-W control circuit 25 of FIGURE 1 operates, during the rest of horizontal retrace interval, as a Class A sink current amplifier. Sink current i 3 in transistor Q 2 develops a proportional feedback voltage V R4 across a resistor R 4 that is coupled between the emitter of transistor Q 2 and ground. Voltage V R4 is fed back to the base of a transistor Q 3 via a resistor R 5 . The collector of transistor Q 3 is coupled to the base of transistor Q 2 at a terminal 25a. The average value of sink current i 3 during retrace, is kept independent from variations of the shape and amplitude of voltage V 3 by, for example, the negative feedback arrangement of resistors R 4 and R 5 . Therefore, a high output impedance to the average value of current i 3 at the retrace frequency and above is established at the collector of transistor Q 2 . The average value of sink current i 3 is adjusted by a width control resistor R 11 , which determines the emitter voltage of transistor Q 3 , in accordance with a vertical parabola voltage V 10 , that is described below. Thus, the average value of current i 3 is modulated at a vertical rate in a parabolic manner in accordance with voltage V 10 . FIGURES 2a-2f, 3a-3e, and 4a-4b illustrate waveforms useful in explaining the operation of the arrangement of FIGURE 1. Similar numbers and symbols in Figures 1, 2a-2f, 3a-3h and 4a-4b indicate similar items or functions. Parabola voltage V 10 of FIGURE 1 is generated across a capacitor C c of, for example, a conventional vertical deflection circuit 300. Parabola voltage V 10 of FIGURE 3d is AC coupled to the emitter of transistor Q 3 of FIGURE 1 via a DC blocking capacitor C 4 , a resistor R 14 and an adjustable E-W control resistor R 12 . Retrace voltage V 3 is coupled via diode D 3 and a time-integrating network, or lowpass filter that includes a resistor R 2 and a capacitor C 2 that filters out frequencies above the vertical frequency. The lowpass filtered voltage is coupled, via a resistor R 3 , to the emitter of transistor Q 3 . The low frequency negative feedback voltage that develops across capacitor C 2 causes the average value of voltage V 3 to vary in a vertical rate parabolic manner in accordance with vertical parabola voltage V 10 . Because of the negative feedback, the peak, for example, of the vertical rate envelope of voltage V 3 is inversely related to the vertical parabola voltage applied across emitter-base junction of transistor Q 3 that is obtained from voltage V 10 . Such low frequency feedback arrangement of resistors R 2 and R 3 provides DC stabilization and improves linearity. Also applied to the base of transistor Q 3 is an adjustable portion of a vertical sawtooth voltage V 11 , that provides trapeze correction, shown in FIGURE 3e, that is obtained across a resistor R s of FIGURE 1. Resistor R s is coupled in series with a vertical deflection winding L v and capacitor C c of circuit 300. The downramping slope of current i 3 , during retrace, having a waveform that is included in FIGURE 1, is obtained by a low pass filter formed by capacitor C 3 in parallel with a resistor R 6 that are, each, coupled between the base of transistor Q 2 and ground. Negative feedback voltage V R4 across resistor R 4 causes the voltage across capacitor C 3 to be higher and to cause a higher level of current i 3 at the beginning of retrace than at the end of retrace. Thus, voltage V R4 tends to reduce, gradually, current i 3 via the discharge of capacitor C 3 , by action of the negative feedback. Advantageously, the power dissipation of transistor Q 2 is maintained at a low level, such as 2 watts, because at the beginning of retrace, when current i 3 is larger than at the end of retrace, voltage V 3 in the corresponding waveform of FIGURE 1 is still low. Thus, advantageously, the modulation dynamic range of control circuit 25 that is determined by, for example, the average value of current i 3 during retrace, is increased. High beam load current that flows in a winding W3 of transformer T1 causes a downramping slope of voltage V 3 during the second half of retrace and may add harmonic oscillations to voltage V 3 as shown in FIGURE 2f. The width of retrace pulse voltage V 3 that is determined by the instant when voltage V 3 is clamped by diode D 2 of FIGURE 1 to ground potential also limits the modulation dynamic range. Because sink current i 3 of FIGURE 2e is downramping, during the second half of retrace, the downramping slope of voltage V 3 is, advantageously, less steep, during the second half of retrace, than if current i 3 would have been, for example, at a constant level, during retrace. Thereby, the dynamic range is, advantageously, further increased. Correction of inside pincushion distortion is accomplished by the "S"-shaping of deflection current i 1 , in accordance with an inside pincushion correction modulation current i 2 that flows in capacitance C 6 and in inductor L1 of inside pincushion distortion correction circuit 60. Current i 2 that flows in a current path that includes trace capacitance C s , varies a voltage V cs across trace capacitance C s , during trace, at a frequency that is higher than the trace resonance frequency of the trace resonant circuit that includes deflection winding L H andtrace capacitance C s . The amplitude of current i 2 is modulated by voltage V 3 of FIGURE 2f at terminal 28 of FIGURE 1 to provide inside pincushion correction. The higher the amplitude of current i 2 , the higher is the peak-to-peak amplitude of trace voltage V cs that is produced and the more significant is the amount of "S"-shaping of deflection current i 1 that is provided, and vice versa. Operation of circuit 60 is described in more detail in European Published Patent Application No. 0236064, entitled PINCUSHION CORRECTION IN DEFLECTION CIRCUIT, in the name of RCA Corporation, published 9 September 1987. Capacitance C 6 and inductor L1 of circuit 60 form, with trace capacitance C s and deflection winding L H , a resonance circuit portion of correction circuit 60 during trace. The resonance circuit portion of circuit 60 is tuned by inductor L1 to a frequency that is lower than frequency f H so that current i 2 will not reach zero value prior to the end of horizontal trace; yet, it is tuned to a frequency that is substantially higher than the resonance frequency of the trace resonant circuit of deflection winding L H and trace capacitance C s . Inside pin modulation inductor L1 may be of a variable type if an adjustable amount of correction is required. For the circuit values shown in FIGURE 1, inductor L1 may tune the resonance circuit portion of circuit 60 to a frequency of, for example, 14 KHz. The portion of voltage V cs that is caused by deflection current i 1 is generally a parabola shaped waveform that, in each horizontal period H, is composed of trace and retrace sinewave portions, respectively. During trace, the corresponding sinewave portion of voltage V cs is at a frequency that is approximately equal to the trace resonance frequency of winding L H and capacitor C s . Such resonance frequency is for example, equal to approximately 7 KHz. During retrace, the corresponding sinewave portion is at approximately 44 KHz. Inductor L1 and capacitance C 6 are included in a circuit branch that, during trace, is coupled in parallel with trace capacitance C s . During the first half of trace, resonance current i 2 flows, in a direction opposite to the arrow, from ground, through capacitance C 6 , inductor L1, capacitance C s , diode D 1 , deflection transistor Q1 that is conductive and back to ground. During the second half of trace, current i 2 circulates in the direction of the arrow from ground through diode D 2 , capacitance C s , inductor L1 and capacitance C 6 and back to ground. Deflection current i 1 flows, during retrace, in a current path that includes retrace capacitor CRD, deflection winding L H and trace capacitor C s . Trace capacitor C s , that provides low impedance during retrace, prevents current i 1 from flowing, throughout retrace, in the branch of circuit 60 that includes capacitance C 6 and inductor L1. Because inductor L1 is bypassed by capacitor C s , the deflection inductance during retrace and retrace voltage V 1 are, advantageously, not substantially affected by inductor L1. Therefore, deflection circuit 100 of FIGURE 1 may, advantageously, require a relatively low level of voltage B+ when operating at higher deflection frequencies such as, for example, 2×f H . During horizontal trace, voltage V 3 of FIGURE 1 is maintained zero as shown in FIGURE 2f. At the center of vertical trace, when current i 3 is at a maximum level, horizontal retrace voltage V 3 is at minimum that may be for example, at zero volts. Consequently, in this case, it is trace voltage V cs across capacitor C s that generates resonant current i 2 . Current i 2 of FIGURE 2c, that flows in capacitor C s in the same phase as current i 1 of FIGURE 2a, adds in capacitor C s to current i 1 to provide maximum "S" shaping of voltage V cs when current i 3 is at the maximum. As current i 3 becomes smaller, during vertical trace, horizontal retrace voltage V 3 becomes increasingly larger as shown in the corresponding waveforms in FIGURE 1. The phase of voltage V 3 is shifted by approximately 180° from that of voltage V cs , because the positive peak of voltage V cs or V 2 of FIGURE 2d occurs at the center of horizontal trace; whereas the peak of modulated voltage V 3 of FIGURE 2f occurs during horizontal retrace. Therefore, voltage V 3 of FIGURE 1, which is added to voltage V cs across capacitor Cs to form voltage V 2 , has an opposite effect on current i 2 than that of trace voltage V cs . When retrace voltage V 3 increases, current i 2 decreases, causing less modulation of trace voltage V cs or V 2 and less "S" shaping. A further increase of retrace voltage V 3 causes the amplitude of current i 2 to be zero. An even further increase of retrace voltage V 3 causes current i 2 to flow in the opposite direction. Thus, current i 2 of FIGURE 2c that modulates voltage V 2 of FIGURE 2d is modulated by voltage V 3 of FIGURE 2f. Since voltage V 3 is modulated by current i 3 of FIGURE 2e, the parabolic waveform of voltage V 2 of FIGURE 2d is modulated in the vertical rate by current i 3 of FIGURE 2e to provide inside pincushion distortion correction. The correction of outside pincushion distortion requires, at the top and bottom of the raster, a lower amplitude of deflection current i 1 of FIGURE 2a than at the center. The correction of inside pincushion distortion requires a lower amount of "S" shaping at the top and bottom than at the center. At the top and bottom sink current i 3 that is lower, causes a higher amplitude of retrace voltage V 3 . The higher amplitude of voltage V 3 causes a lower amplitude of current i 2 . At the center of the vertical trace, sink current i 3 , that is at a maximum, causes the amplitude of retrace voltage V 3 to be at a minimum. Accordingly, at the center of vertical trace, the amplitude of each of deflection current i 1 and inside pincushion correction current i 2 is at a maximum, resulting in more "S" shaping of voltage V cs . Advantageously, by selecting the values of the circuit components of circuit 60, a required amount of inside pincushion correction can be obtained for a given amount of outside pincushion correction. Circuit 60 is coupled in parallel with capacitor C RT during the retrace interval. Therefore, the value of capacitor C RT has to be larger than if circuit 60 was not used, so as to account for the effect of circuit 60 on the total retrace capacitance that is required. Increasing the value of capacitor C RT has a tendency to increase the coupling between flyback transformer T1 and resonant circuit 27 that may, if not accounted for, disadvantageously, increase "mouseteeth" distortions. A resistor R18 is coupled between terminal 22a and an intermediate terminal, or tap, 112 of inductor L1. Resistor R18 supplies a DC current i 4 that bypasses deflection winding L H and winding W1. Current i 4 that flows through resistor R18 and inductance L1, advantageously, stabilizes the DC voltage in capacitor C s by providing an additional DC current path between supply voltage V 6 and capacitor C s . The average DC value of voltage V 2 at junction terminal 60a of winding L H and capacitance C s is equal to voltage V 6 that is at terminal 22a between capacitor C1 and resistor R18. Thus, advantageously, by supplying a portion of the DC current that is required for maintaining average voltage V cs, constant through resistor R18, in addition to the portion that is supplied through winding W1, transient discharge of capacitor C s due to varying ultor load is, advantageously, reduced; hence, "mouseteeth" distortion is reduced. The AC portions of voltages V 2 of FIGURE 2d and V 5 of FIGURE 3c at the end terminals of inductor L1 have opposite phases. The location of tap 112 of FIGURE 1 is selected in such a way that, advantageously, causes voltage V 4 at tap 112 of inductor L1 of FIGURE 1, that is approximately equal to the average of voltages V 2 and V 5 , to have a minimal AC component, during trace, as shown in FIGURE 3b. Consequently, resistor R18 of FIGURE 1, that is coupled to tap 112 does not load significantly any of deflection circuit 100 and inside pincushion correction circuit 60 and, therefore, advantageously, does not increase AC losses in circuits 100 and 60. Current i 4 of FIGURE 3a that flows in resistor R18 of FIGURE 1 is sawtooth shaped because of the ripple voltage of voltage V 6 . Advantageously, current i 4 may correct some of the asymmetrical horizontal linearity errors. Linearity errors occur because of power losses in winding L H and in inductor L1 during trace that might have caused a slight decrease in voltage V 4 at tap 112. The decrease in voltage V 4 might have resulted in currents i 1 and i 2 having smaller amplitudes near the end of horizontal trace. To correct, at least some of such asymmetrical linearity error, current i 4 , that is sawtooth shaped, advantageously, reduces the amount of decrease in voltage V 4 that might have, otherwise, occurred. During the first half of trace, current i 2 flows, in a direction that is opposite to that of the arrow, from ground, through capacitor C 6 , inductance L1, and capacitor C s to junction terminal 28 between diodes D 1 and D 2 . An energy recovery current i w1 flowing through winding W1 of flyback transformer T 1 in a direction of the arrow, keeps diode D 2 conducting as long as current i 2 is smaller than energy recovery current i w1 and provides a ground return for current i 2 . However, diode D 2 may become nonconductive when the increasing amplitude of current i 2 is equal to the decreasing amplitude of energy recovery current i w1 in winding W1. Such situation is undesirable because it may cause the trace voltage at terminal 23 of transistor Q1 to rise significantly above ground potential. In accordance with a further aspect of the invention, sink current transistor Q 2 is switched into saturation at the beginning of the horizontal trace interval. Advantageously, this provides a current path for inside pincushion modulation current i 2 during the first half of the trace interval. Current i 2 causes voltage V 3 , during trace, to increase so as to bias diode D 3 in the forward direction. Because transistor Q 2 is saturated, diode D 3 , advantageously, provides a ground return for current i 2 via saturated transistor Q 2 and clamps voltage V 3 to approximately zero volts. In carrying out a yet further aspect of the invention, transistor Q 2 is switched into saturation by retrace pulse H, across winding W4 that is applied to the base of transistor Q 3 through a capacitor C 5 . A waveform shaping network that includes capacitor C 5 and resistors R 15 and R 16 generates from pulse H r an upramping voltage V 7 , during trace that is shown in the corresponding waveform in FIGURE 1. The negative portion of voltage V 7 is applied to the base of transistor Q 3 via a diode D 4 and a resistor R 17 to form a voltage V 9 that causes transistors Q 3 and Q 2 to saturate. The waveform, that is included within FIGURE 1, of voltage V 9 shows the base voltage of transistor Q 3 . At a time t a in the waveform of voltage V 9 in FIGURE 1, that occurs at the end of retrace, transistors Q 3 and Q 2 are driven into saturation by negative going voltage V 9 . Both transistors Q 3 and Q 2 remain in saturation until a time tb, when diode D 4 is reverse biased by upramping voltage V 7 . During the interval t b -t a ', transistor Q 2 is biased for Class A operation so as to provide high output impedance. FIGURE 2b illustrates the waveform of retrace voltage V 1 at terminal 23 of FIGURE 1. Retrace voltage V 1 of FIGURE 2b is, advantageously, unaffected by modulation of E-W modulation current i 3 . FIGURE 5 illustrates a second embodiment of the invention, referred to as deflection circuit 100', that may provide East-West corrected deflection current i 1 ' to a Videocolor 110° PIL-FS 10 picture tube type A66EAS00X01. Alternatively, with some changes that are shown in dashed lines, it may be used in conjunction with a picture tube of the 110° COTY SP type. FIGURES 6a-6e illustrate waveforms associated with the circuit of FIGURE 5. Similar numbers and symbols in FIGURES 1, 5 and 6a-6e illustrate similar items or functions. Note that inside pincushion correction circuit 60 of FIGURE 1 is not incorporated in the circuit of FIGURE 5. Transistor Q 2 ' of FIGURE 5 does not operate as a switch during trace; whereas, transistor Q 2 of FIGURE 1 operates as a switch during trace. In many other respects, deflection circuits 100 of FIGURE 1 and 100' of FIGURE 5 are similar and operate similarly. FIGURE 6a illustrates voltage V 1 ' across transistor Q 1 ' of FIGURE 5. Note that the amplitude and width of voltage V 1 ' of FIGURE 6a are not affected by the modulation caused by E-W control circuit 25' of FIGURE 5. FIGURE 6b illustrates voltage V 3 ' modulated by E-W control circuit 25' of FIGURE 5 for obtaining outside pincushion raster correction. The peak retrace voltage across capacitance C RD ' is amplitude modulated by the same amount as voltage V 3 ' of FIGURE 6b. Retrace resonant circuit 27' of FIGURE 5 resonates at the fundamental retrace frequency. The trailing edge of the pulse of voltage V 3 ' of FIGURE 6b is modulated by sink current i 3 ' of FIGURE 5. Thus, pulse of voltage V 3 ' of FIGURE 6b, such as shown between time t 2 and t 3 , is narrower at the center of vertical trace than at the top or bottom. Voltage V 3 ' of FIGURE 5 is zero during horizontal trace due to conduction of damper diode D 2 '. The result is that diode D 3 ' is reverse biased during this interval. The amplitude modulation of deflection current i 1 ' of FIGURE 6d is 7%. Power dissipation of transistor Q 2 ' of FIGURE 5 is about 2 Watts. In television applications with picture tubes having nonspherical faceplates, such as, for example, the RCA 110° COTY SP tube, additional vertical parabola shaping may be required so as to flatten the slope of the parabola at the edges. Such parabola shaping arrangement, an arrangement 70, is drawn in FIGURE 5 by dashed lines. The purpose of such arrangement 70 is described in detail in U.S. Patent No. 4,687,972, entitled, RASTER DISTORTION CORRECTION CIRCUITRY FOR A VIDEO DISPLAY APPARATUS, in the name of P.E. Haferl. A capacitor C 500 ' of arrangement 70 that is coupled to voltage V 11 ', having a sawtooth waveform at the vertical rate, is charged by a current that flows in a resistor R 155 '. Capacitor C 500 ' discharges via a resistor R 166 ', a diode D8' and a resistor R 14 ', during the low voltage portion of the vertical parabola voltage. The voltage drop across resistor R 14 ' provides the parabola shaping. The amount of parabola shaping is controlled by the charging current through resistor R 155 '. Capacitor C 500 ' operates as an ideal voltage source and, advantageously, provides suppression of the sawtooth voltage. FIGURE 8 illustrates an E-W control circuit 25" that may be used in the arrangement of FIGURE 5, for example, instead of control circuit 25'. Similar numbers and symbols in FIGURES 5 and 8 illustrate similar items or functions. Neither transistor Q 2 " of FIGURE 8 nor, as described before, transistor Q 2 ' of FIGURE 5, operates as a switch during trace. In control circuit 25' of FIGURE 8, during retrace, a vertical rate parabolic signal V 10 " is coupled through a resistor R 77 " to a base electrode of a transistor Q 4 " of a temperature compensated differential amplifier 77". The base electrode of transistor Q 4 " is also coupled through a resistor R 78 " and a diode D 78 " to a terminal of a flyback transformer winding such as, for example, winding W 4 ' of FIGURE 5. Consequently, throughout trace, the base voltage of transistor Q 4 " of FIGURE 8 is clamped to approximately 2.5 volts. A collector electrode of a transistor Q 5 " of amplifier 77" is coupled to the base electrode of a transistor Q 2 " to provide a pulse V Q5 ", during each retrace interval. Pulse V Q5 " has a peak voltage that varies in a vertical rate parabolic manner in accordance with signal V 10 ". The emitter electrode of transistor Q 2 " is coupled through a resistor R 4 " to a parallel arrangement of a resistor R 44 " and a capacitor C 44 ". An emitter voltage V Q2 of transistor Q 2 " is representative of a collector current i 3 " that flows in transistor Q 2 ". Voltage V Q2 is fed back to the base electrode of transistor Q 5 " through a resistor R 45 " that determines the close-loop gain of amplifier 77". Current i 3 " is coupled through a diode D 3 " to a terminal 28" of a retrace resonant circuit, not shown in FIGURE 8, to provide East-West modulation current. The operation of transistor Q 2 " and of diode D 3 " is similar to the operation of transistor Q 2 ' and of diode D 3 ' of FIGURE 5, respectively. The negative feedback through resistor R 45 " of FIGURE 8, establishes the average value of current i 3 " during each retrace interval, in accordance with parabolic signal V 10 ". In this way, the average value of current i 3 ", advantageously, is maintained unaffected by the amplitude of retrace voltage V 3 " at terminal 28". Therefore, mouseteeth distortions are, advantageously, reduced.

Claims: A deflection apparatus with raster distortion correction, comprising: a source of input signal (Hs) at a frequency, that is integrally related to a first deflection frequency; a deflection winding (L H ); switching means (Q1) coupled to said deflection winding, said switching means operating, in accordance with said input signal, at said first deflection frequency for generating scanning current (i 1 ) in said deflection winding during a trace interval of each deflection cycle; a deflection retrace capacitance (C RD ) coupled to said deflection windind (L H ) to form a deflection retrace resonant circuit (27) that produces a first retrace pulse voltage at a retrace frequency during a trace interval of each deflection cycle; a source (90) of supply voltage; a supply inductance (W1) connected to receive said supply voltage and coupled to said switching means (Q1) for generating a second retrace pulse voltage in said supply inductance (W1), said supply inductance being effective to supply, to said retrace resonant circuit (27) ) during said retrace interval, a supply current from said source (90) of supply voltage that replenishes energy losses in said retrace resonant circuit (27); a load circuit (at U) energized by said second retrace pulse voltage in said supply inductance (W1); a source (300) of a modulation signal ; and controllable means including semi-conductor means (Q2) responsive to said modulation signal for generating a modulation current (i 3 ) that is applied to said retrace resonant circuit (27) to modulate said scanning current (i 1 ) for providing raster distcrticn correction; characterised in that said semi-conductor means (Q2) also forms an output impedance for said modulation current that, during said retrace interval, is sufficiently large to prevent a high frequency coupling between said supply inductance (W1) and said retrace resonant circuit (27) during said retrace interval. An apparatus according to Claim 1 characterized in that said first deflection frequency is a horizontal deflection frequency and wherein said output impedance has a value that is substantially higher at said horizontal deflection frequency, than the value of the impedance of at least one of said deflection winding and said supply inductance. An apparatus according to Claim 1 characterized in that said controllable means (Q2,Q3) comprises an amplifier that maintains an average value of said modulation current (i 3 ) during said retrace interval unaffected by said first retrace pulse voltage. An apparatus according to Claim 3 characterized in that said amplifier (Q2,Q3) operates as a Class A amplifier. An apparatus according to Claim 1 characterized in that said controllable means (Q2,Q3) forms said output impedance that is high at a collector electrode of a transistor (Q2) for preventing a variation of a load current in said load circuit from affecting said modulation current (i 3 ). An apparatus according to Claim 1 characterized in that said supply inductance comprises a winding (W1) of a flyback transformer (T1). An apparatus according to Claim 6 characterized in that said load circuit is coupled to a second winding (W3) of said flyback transformer (T1) to produce an ultor voltage (U). An apparatus according to claim 1 characterized by a second retrace capacitance (C RT ), coupled between said retrace resonant circuit (27) and a common supply terminal (ground), said second retrace capacitance being effective together with said supply inductance (W1) and said retrace resonant circuit (27) for causing said second retrace pulse voltage to contain the same synchronization information as said first retrace pulse voltage. An apparatus according to claim 1 characterized by a second retrace capacitance (C RT ), coupled between said retrace resonant circuit (27) and a common supply terminal (ground), said second retrace capacitance being effective together with said supply inductance (W1) and said retrace resonant circuit (27) to form a second retrace resonant circuit that is tuned to said retrace frequency and that includes said first retrace resonant circuit (27), said supply inductance (W1) and said second retrace capacitance (C RT ). An apparatus according to Claim 1 characterized by means (C 4 ) responsive to said modulation signal and coupled to said controllable means (Q2,Q3) for generating said modulation current having a downramping slope during said retrace interval. An apparatus according to Claim 1 characterized in that said supply inductance comprises a flyback transformer (T1) having a first winding (W1) coupled to said source (90) of supply energy and a high voltage winding (W3) across which is developed said second pulse voltage, wherein said load circuit comprises a high voltage circuit (U) for deriving from said second pulse voltage that is developed across said high voltage winding (W3) an ultor voltage at an ultor terminal and wherein said controllable means (Q2,Q3) includes a transistor (Q2) that prevents variations of beam current loading at said ultor terminal from substantially affecting said retrace resonant circuit (27). An apparatus according to claim 1 characterized in that the signal from said source (300) of modulation signal is at a vertical rate, and said first deflection frequency is at a horizontal rate. An apparatus according to Claim 1 characterized in that said controllable means (Q2,Q3) comprises a transistor (Q2) that is responsive to a signal at a horizontal frequency, said transistor operating as a conductive switch during said trace interval, having a low output impedance relative to the impedance of the deflection and supply windings. An apparatus according to Claim 13 characterised in that said transistor (Q2) operates as a Class A amplifier having said large output impedance relative to the impedance of the deflection and supply windings during said retrace interval, such that said modulation current is supplied via a collector electrode thereof. An apparatus according to Claim 1 characterized by a trace capacitance (C s ) coupled to said deflection winding (L H ) to form with said deflection winding a first trace resonant circuit during said trace interval such that said scanning current that flows in said trace capacitance develops, during said trace interval, a parabolic voltage in said trace capacitance (C s ), and a circuit branch (60) for generating in said circuit branch a second modulation current (i 2 ) at an amplitude that is modulated in accordance with said modulation current, said second modulation current (i 2 ) being coupled to said trace capacitance (C s ) to vary said parabolic voltage in said trace capacitance in a manner to reduce inside pincushion distortion. An apparatus according to Claim 15 characterized in that said trace capacitance (C s ) acts as a low impedance bypass capacitance for said scanning current (i 1 ) around said circuit branch (60) substantially throughout said retrace interval. An apparatus according to Claim 15 characterized in that said circuit branch (60) comprises a second capacitance (C 6 ) and a modulation inductance (L 1 ) that form a second trace resonant circuit with said first trace capacitance (C s ) and with said deflection winding (L H ) such that said second trace resonant circuit is tuned to a frequency that is higher than the resonance frequency of said first trace resonant circuit. An apparatus according to Claim 15 characterized in that said controllable means (Q2,Q3) comprises a transistor (Q2) that is responsive to a horizontal rate signal that causes said transistor to operate, during said trace interval, as a switch that is conductive. An apparatus according to Claim 1 characterized in that said switching means (Q1) is conductive during at least a first portion of said trace interval to maintain a voltage at a terminal of said switching means at a predetermined substantially constant level during said trace interval and wherein said controllable means (Q2,Q3) comprises a transistor (Q2) that operates as a switch that is conductive during at least a second portion of said trace interval when said switching means (Q1) is nonconductive for maintaining said voltage at said terminal of said switching means at substantially said predetermined constant level throughout said trace interval. An apparatus according to Claim 19 characterized in that said switching means comprises a second transistor (Q1) and an arrangement of a pair of series coupled diodes (D1,D2) that is coupled across the main current carrying terminals of said second transistor (Q1) and wherein said first transistor (Q2) that is conductive during said second portion of said trace interval is coupled at a junction terminal (28) between said diodes (D1,D2) to maintain a low impedance across one of said diodes (D2) when said one of said diodes is nonconductive.

Inventors: HAFERL PETER EDUARD, HAFERL, PETER EDUARD
Applicants: RCA THOMSON LICENSING CORP, RCA THOMSON LICENSING CORPORATION
Application year: 1987
Main classification: H04N3
IPC codes: H04N3, G09G1