Step-cut insulated gate static induction transistors and method of manufacturing the same

Abstract: A step-cut insulated gate static induction transistor can accurately make a channel length and a gate length and is excellent as a high speed transistor but is greatly affected by a deviation in mask alignment in the manufacturing process. This invention utilizes the fact that a gate portion formed in a previous processes is used as a mask in a post portion to thereby self-adjustably form the post portion, thus eliminating the influence of the deveation in mask alignment. In addition, a construction has been invented in which a current flowing through a protion apart from a gate between a drain and a source can be restricted. The aforesaid manufacturing method is also used for this improved construction.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a step-cut insulated gate static induction transistor capable of carrying out high-speed switching, a high-speed and low power step-cut insulated gate static induction transistor integrated circuit, and method of manufacturing the same. Description of the Prior Art Insulated gate transistors for high frequency amplification and integrated circuits have been heretofore used but have a disadvantage that the drivability is small. For example, a complementary metal-oxide-semiconductor transistor integrated circuit (C-MOS) has been known as an application of an insulated gate transistor. However, this circuit (C-MOS) operates at low dissipation power but operates at low switching speed, because of small drivability. To overcome such disadvantages as noted above, one of the present inventors has previously proposed an insulated gate static induction transistor (for example, see Japanese Patent Application No. 1756/1977) and a step-cut insulated gate static induction transistor (for example, see Japanese Patent Application No. 13,707/1977). The insulated gate static induction transistor is designed so that the depletion layer spread from the drain region reaches the source region. So, a current flowing from source to drain is controlled not only by the gate voltage but also by the drain voltage and the current flows into not only an interface between a semiconductor and an insulator but a substrate. Therefore, the insulated gate static induction transistor has non-saturating current-voltage characteristics and has large drivability. Particularly, the step-cut insulated gate static induction transistor has a channel formed depthwise of a semiconductor substrate, thus providing a good controllability for a channel length and a gate length, and said transistor is well suited for shortening a channel to improve its drivability. Thus, the step-cut insulated gate static induction transistor is able to increase its drivability and decrease a parastic capacitance and therefore exhibits an excellent performance as a high speed switching transistor and a high-speed and low power integrated circuit. Prior art will be described hereinafter with reference to FIG.1. FIG.1(a) shows an example of a construction in section of a conventional step-cut insulated gate static induction transistor. In FIG. 1(a) 10 designates a semiconductor substrate, a main surface of which is partly provided with a U-shaped groove. A drain region 11, a channel region 13 and a source region 12 are provided in said order depthwise from the main surface along the side wall of the U-shaped groove, and a drain electrode 11' is connected to the drain region 11. A source electrode, which is not shown, is provided vertically as viewed from the paper surface. The drain region 11 and the source region 12 have the impurity concentration of the order of 10 18 to 10 21 cm -3 , the conductivity type of which is shown as P type but N type can be used. In addition, the region 11 can be used as a source region and the region 12 used as a drain region. The channel region 13 has the impurity concentration of the order of 10 12 to 10 16 cm -3 , the conductivity type of which can be of the same as or opposite to that of the drain region 11 and the source region 12, and a multi-layered construction can be also employed. The impurity concentration as well as the depth of the aforesaid U-shaped groove are determined so that a depletion layer spread from the drain region 11 reaches the source region 12 at least a part of the operating condition thereof. A gate insulator 14 such as an oxide film is provided in contact with the channel region 13 and has a thickness of the order of 100 to 1,000 Å (10Å = 1nm). On the side opposite the gate insulator 14 is provided a gate electrode 14' formed of metal, polycrystalline silicon or the like. 15 designates a field oxide film. Since a conventional step-cut insulated gate static conduction transistor as shown in FIG. 1(a) is formed depthwise with respect to a semiconductor substrate. dimensions of a transistor can be controlled with precision of deposition and etching providing a good controllability for the channel length and gate length and being well suited for shortening the channel to improve drivability. Accordingly, such a transistor as noted above has a large drivability and can decrease a parastic capactance and therefore exhibits an excellent performance as a high speed switching transistor and a high speed low power integrated circuit. One example of a well known fabrication process for manufacturing the aforesaid step-cut insulated gate static conduction transistor will be described with reference to FIG. 2. FIG. 2(a) An epitaxial layer 22 constituting a channel is grown on a semiconductor substrate 21 used as a drain, a channel impurity is introduced by thermal diffusion or ion implantation and thereafter a U-shaped groove is formed in a part of a main surface of the semiconductor substrate by anisotropic plasma etching or the like. FIG. 2(b) A conventional photolithography and a selective oxidation are used to form a field oxide film 23 and windows, which are provided in a part of a main surface of a semiconductor substrate and are including at a part of the side wall of a U-shaped groove to form a gate oxide film 24. FIG. 2(c) A polycrystalline silicon 25 constituting a gate electrode is deposited, which is subjected to etching by a conventional photolithography so as to have it remained on a gate oxide film of the side wall of a U-shaped groove, and thereafter a source region 26 is formed by thermal diffusion or ion implantation. FIG. 2(d) A passivation film 27 is deposited and contact hole is opened to form a drain electrode 21', a gate electrode 25' and a source electrode 26'. The impurity concentration of the aforesaid drain region 21 and source region 26 is of the order of 10 18 to 10 21 cm -3 . It is noted of course that the conductive type can be of either P type or N type, and the 21 can be used as a source region and the 26 as a drain region conversely to the former. The impurity concentration of the channel region 22 is of the order of 10 12 to 10 16 cm -3 , and the conductive type thereof can be the same as or opposite to that of the aforementioned drain region and source region, a multi-layered construction being possibly used. However, at least in a part of the operating condition a depletion layer spread from the drain region must reach the source region, and to meet this requirement, the impurity concentration thereof as well as the depth of the U-shaped groove are determined. The thickness of the gate oxide film 24 is set to be of the order of 100 to 1,000 Å, and the gate electrode is ordinarily formed of polycrystalline silicon or the like, the thickness being of the order of 1000 Å to 1 µm. In the above-described conventional process of manufacturing an step-cut insulated gate static induction transistor, a conventional photolithography is used and therefore a margin for mask alignment is required. Consequently, this margin make it difficult to form the gate electrode 25 only on the side wall of the U-shaped groove. For example, FIG. 3 shows an example of a plan construction of a conventional step-cut insulated gate static induction transistor, which corresponds to the fabrication process shown in FIG. 2. In FIG. 3. 31 designates a side wall of a U-shaped groove, 32 a window provided by selective oxidation, 33 a gate electrode of a polycrystalline silicon, 34 and 35 a drain contact hole and a gate contact hole, respectively, and 36 and 37 a drain electrode and a gate electrode, respectively. In FIG. 3, the section of B-B' is shown in FIG. 2(d). ℓ b and ℓ c denote mask alignment margins with respect to the photolithography of the FIG. 2 processes (b) and (c), the margin being normally designed approximately 0.1 to 2 µm. An example of the drain current-drain voltage characteristics of a transistor different in mask alignment margin ℓ c is shown in FIGS. 4 (a) to (c). In this case, it is designed so that the channel length is approximately 0.5 µm; the dosage of the channel impurity is approximately 1.5 x 10 13 cm -2 ; and the thickness of the gate oxide film is approximately 250 Å, the mask alignment margin ℓ c being 0 µm in the (a), and 1 µm and 2 µm in the (b) and (c), respectively. In the case of the (a), there exhibits the unsaturated type current-voltage characteristic, the drivability is large and the characteristic of the step-cut insulated gate static induction transistor is conspicuous but there gives rise to a disadvantage that yield is poor. On the other hand, in the case of the (b) and (c), since a portion corresponding to the mask alignment margin works similarly to a planar type transistor, the effective channel length becomes extended, deteriorating the drivability. In the conventional step-cut insulated gate static induction transistor, the drain region 11 is opposed to the source region 12 with the channel region 13 sandwiched therebetween, and therefore if the channel is shortenned to attain higher speed, a current flows between drain and source even at a point away from the gate surface by being affected by the drain field. This current component cannot be controlled by a gate voltage. This results in disadvantages that a leak current is large at the off state, etc. For example, FIG. 1 (b) shows an example of the drain current-drain voltage characteristics of a conventional step-cut insulated gate static induction transistor so designed that the channel length is approximately 0.5 µm, the dosage of channel impurity is approximately 2 x 10 13 cm -2 , and the thickness of the gate oxide film is approximately 250 Å. Even when the gate voltage is 0 Volt, the drain current flows as the drain voltage increases. It is noted of course that such a current flowing on the bulk side can be suppressed to some extent by selecting the impurity concentration of the channel region 3. FIG. 1 (c) shows an example of the drain current - drain voltage characteristics of a conventional step-cut insulated gate static induction transistor so designed that the channel length is approximately 0.5 µm, the dosage of channel impurity is approximately 6x 10 13 cm -2 , and the thickness of the gate oxide film is approximately 250 Å. A leak current at the off state was improved but drivability is sacrificed to some extent because the static induction effect on the drain side became hard to extend to the source side, and the threshold voltage is increased. It is an object of the present invention as claimed is claim 1 to provide a method of manufacturing a step-cut insulated gate static induction transistor which self-adjustably forms a gate electrode and using the gate electrode as a mask in the formation of drain and source regions. This overcomes the above-described problem of mask alignment during formation of the gate oxide film and the gate electrode, whilst increasing reproducibility and reliability. An improved method of manufacturing a step-cut insulated gate static induction transistor according to the present invention is characterised by the following sequence of steps: anisotropic etching of a main surface of a semiconductor substrate to form a U-shaped groove; deposition of mask material for selective oxidation on said main surface; anisotropic etching of said mask material to leave said mask material on an area of said main surface intended for eventual formation of said transistor; selective oxidation to form a field oxide film over said main surface and to remove said mask material to create a window in said field oxide film; formation of a thin gate oxide film in said window; deposition of material to form a gate electrode and anisotropic etching to leave said gate electrode material in a self-aligned manner on a side wall of said groove; and formation of a drain region and a source region using said gate electrode as a mask. It is a further object of the invention to provide an insulated gate static induction transistor, as claimed in claim 4, wherein both drain and source region are arranged so as to be free from the provision of a portion wherein the drain region is opposed to the source region with a channel region sandwiched in between, said channel having a low impurity concentration provided only in the vicinity of a surface of a side wall, whereby in normal operating conditions a leakage current does not flow between the drain and the source under the influence of a drain electric field. British Patent Application No. 2 103 879 relates to an MOS type of field effect transistor in which one of the stated objects is to solve a problem arising in the positional adjustment of a deposition source which occurs when a gate electrode is formed on the side wall of a mesa by oblique deposition. In order to achieve this object, a thick oxide film is formed over the entire surface of a semiconductor substrate. A mesa is formed and an undercut is made therein resulting in an overhang of the oxide film which is, in turn, used to form a gate electrode on the side wall. An embodiment of the present invention will now be described, by way of example only, with reference to the drawings, in which: FIG. 1 shows one example of a conventional step-cut insulated gate static induction transistor, FIG. 1 (a) showing a sectional structural view, FIG. 1 (b) showing one example of the drain current - drain voltage characteristics, and FIG. 1 (c) showing another example of the drain current drain voltage characteristics; FIG. 2 is an explanatory view of the fabrication process showing one example of a conventional method of manufacturing a step-cut insulated gate static induction transistor; FIG. 3 is a plan view showing a plane construction of a conventional step-cut insulated gate static induction transistor; FIG. 4 is a characteristic view showing one example of the drain current - drain voltage characteristics caused by a difference of mask alignment margin of a conventional step-cut insulated gate static induction transistor; and FIG. 5 shows one example of an improved step-cut insulated gate static induction transistor not forming part of the claimed invention, FIG. 5 (a) being a sectional structural view, and FIG. 5 (b) showing one example of the drain current - drain voltage characteristics; FIG. 6 is a sectional structural view of an improved step-cut insulated gate static induction transistor; FIG. 7 is a sectional view showing one example of an integrated circuit of an improved step-cut insulated gate static induction transistor, not forming part of the claimed invention FIG. 8 is an explanatory view of the fabrication process of an improved step-cut insulated gate static induction transistor according to a method of manufacturing an step-cut insulated gate static induction transistor of this invention; FIG. 9 is a plan view showing a plane construction thereof; FIG. 10 is a sectional view showing one example of an integrated circuit manufactured by this method; Referring now to FIG. 5 (a), this shows one example of a sectional construction of an improved step-cut insulated gate static induction transistor. In the figure, 90 designates a semiconductor substrate, the main surface of which is partly provided with a U-shaped groove. In this U-shaped groove, a drain region 91 and a channel region 93 are provided depthwise in order from the main surface along the side wall, a drain electrode 91' being connected to the drain region 91. A source region 92 is provided in contact with the lower end of the side wall of the U-shaped groove and along the bottom of said groove so as not to provide a portion opposed to the drain region. The source electrode though not shown is provided, for example, vertically as viewed from the paper surface. The drain region 91 and the source region 92 have the impurity concentration which is of the order of 10 18 to 10 21 cm -3 , and the conductivity type shown is the P type, but the N type can be used. Also, the region 91 can be used as a source region, and the region 92 as a drain region. The channel-region 93 has the impurity concentration which is of the order of 10 12 to 10 16 cm -3 . The conductivity type can be of the same as or opposite to the drain region 91 and the source region 92, and a multi-layer construction can be used. And, it may have the imupurity distribution which decreases toward the drain region, but at least in a part of the operating condition, the impurity concentration as well as the depth of the U-shaped groove are determined so that, a depletion layer spread from the drain region 91 reaches the source region 92. A gate insulator 94 such as an oxide film is provided in contact with the channel region 93 and has a thickness of the order of 100 to 1,000 Å. A gate electrode 94' formed of metal or polycrystalline silicon or the like is provided opposite to the gate insulator film 94. 95 designates a field oxide film. In this construction, the drain region 91 and the source region 92 have no portion opposed with the channel region 93 sandwiched therebetween, unlike prior art. Accordingly, the drain field on the bulk side is alleviated as compared with prior art type to increase the breakdown voltage between the drain and the source and decrease a leak current. FIG. 5 (b) shows the drain voltage - drain current characteristics of the step-cut insulated gate static induction transistor according to the present construction. In this case, it is designed so that the channel length is approximately 0.5 µm, the dosage of the channel impurity is approximately 5 x 10 12 cm -2 , and the thickness of the gate oxide film is approximately 250 Å. It is understood from FIG. 5 (b) that even in the impurity concentration of the channel lower than the prior art, a leak current between the drain and the cource is reduced. FIG. 6 shows an example of a sectional construction of a step-cut insulated static induction transistor according to the present invention. A semiconductor substrate 100, a drain region 101, a source region 102, a channel region 103, a drain electrode 101', a gate insulated film 104, a gate electrode 104', and a field oxide film 105 are arranged similarly to those shown in FIG. 5 (a). It is designed so that a leak current between the drain and the source is further suppressed by the semiconductor substrate 100. This embodiment is characterized in that a high impurity concentivation region 106 having the conductivity type opposite to that of the drain 101 is embedded in the vicinity of the cource region 102. FIG. 7 shows a sectional construction of a inner to gate in which a step-cut insulated gate static induction transistor is applied to a complementary metal-oxice-semiconductor transistor integrated circuit. An N channel transistor in a semiconductor substrate 110 has an n + drain region 111, an n + source region 113, a p channel region 115, a drain electrode 111', a gate insulater 117 and a gate electrode 117' while a p channel transistor has a p + drain region 112, a p + source region 114, an n channel region 116, a drain electrode 112', a gate insulator 117 and a gate electrode 117'. The n + drain region 111, p + drain region 112, n + source region 113, p + source region 114 have the impurity concentration of the order of 10 18 to 10 21 cm -3 . The p channel region 115 and the n channel region 116 have the impurity concentration of the order of 10 12 yo 10 16 cm -3 , and the impurity concentration as well as the depth of the U-shaped groove are determined so that at least in a part of the operating condition a depletion layer spread from the drain regions 111 and 112 reaches the source regions 113 and 114. The gate insulator 117 such as an oxide film has the thickness of the order of 100 to 1,000 Å. In the figure, 118 denotes a field oxide film. A p well 119 is provided to separate the p channel transistor from the N channel transistor. The gate electrode 117' comprises a logical input while the drain electrodes 111' and 112' comprise a logical output, a power supplied voltage is applied to source electrodes connected to the source regions 113 and 114, respectively. When the logical input is in a high level the N channel transistor assumes the on state while the P channel transistor assumes the off state, and therefore the logical output becomes a low level. The same is true for the reverse case. Even if, the shorter channel is attained to easily extand the static induction effect of the drain voltage to the source region to increase the drivability of the device, since the step-cut insulated gate static induction transistor is designed so that the drain region and the source region are not superposed with the channel region sandwiched therebetween, a leak current at the off state can be decreased and a standby power can be reduced. Accordingly, it is possible to provide a high speed and low power complementary metal-oxide-semiconductor transistor integrated circuit. For example, A propagation delay time of 63 psec is obtained at a dissipation power of 3.9 mW, by a ring oscillator of the complementary metal-oxide-semiconductor transistor integrated circuit shown in FIG. 7. As described above, in this construction, the disadvantages encountered in the conventional step-cut insulated gate static induction transistor are overcome whereby even in the case where the shorter channel is attained and the static induction effect of the drain voltage is sufficiently obtained, unnecessary current between the drain and the source may be decreased. Accordingly, an step-cut insulated gate static induction transistor which can perform high speed switching and is less consuming power can be provided, and this transistor can be used to provide a high speed and low power-consumed insulated gate transistor integrated circuit thus providing a great industrial value. (Manufacturing method) FIG. 8 shows one example of a process of manufacturing the aforesaid step-cut insulated gate static induction transistor. FIG. 8 (a) An epetaxial layer 122 constituting a channel is grown on a semiconductor substrate 121, a channel impurity is introduced therein by thermal diffusion or ion implantation, and thereafter a U-shaped groove is formed in a part of the main surface of the semiconductor substrate by anisotropic plasma etching or the like. FIG. 8 (b) The selective oxidation is used to form a field oxide film 123, and at the same time a window is formed in an active area of the main surface of the semiconductor substrate to form a gate oxide film 124. FIG. 8 (c) A polychrystalline silicon 125 constituting a gate electrode is deposited, a gate electrode is self-adjustably formed only on the side wall of a U-shaped groove by anisotropic plasma etching or the like, and thereafter this gate electrode 125 is used as a mask to form a drain region 126 and a source region 127 by thermal diffusion and ion implantation. FIG. 8 (d) A passivation film 128 is deposited and a contact hole is openned to form a drain electrode 126' and a source electrode 127'. In this case, the impurity concentration of the drain region 126 and source region 127 is of the order of 10 18 to 10 21 cm -3 . Of course, the conductivity type can be either P type or N type, and the 126 can be employed as a source region, and the 127 as a drain region. The impurity concentration of the channel region 122 is of the order of 10 12 to 10 16 cm -3 , and the conductivity type thereof can be the same as or opposite to that of the drain region 126 and source region 127, and a multilayer construction can be also employed. However, at least in a part of the operating condition, the impurity concentration and the depth of the U-shaped groove are determined so that a depletion layer spread from the drain region reaches the source region. The thickness of the gate oxide film 124 is set to 100 to 1,000 Å or so, and the thickness of the gate electrode set to approximately 1,000Å to 1 um. For example, it is very advantabeous that a polychrystalline silicon is used for a gate electrode. Anisotropic etching may be conducted by PCl 3 plasma etching whose pressure is of the order of 0.03 Torr [1 Torr = 133.3 Pa] to 0.2 Torr. According to the aforesaid manufacturing process, a gate oxide film which greatly influences upon the characteristic of the device and a gate electrode can be self-adjustably formed only on the side wall of the U-shaped groove, thus providing step-cut insulated gate static induction transistor which has good reproducibility and reliability and has the drain current - drain voltage characteristic as shown in FIG. 4 (a). FIG. 9 shows one example of a plane construction of a step-cut insulated gate static induction transistor corresponding to the manufacturing process shown in FIG. 8. In this figure, 131 designates a U-shaped groove side wall, 132 a window obtained by selective oxidation constituting an active area, 133 a gate electrode formed from a polychrystalline silicon 134, 135 and 136 a drain contact hole, a source contact hole and a gate contact hole, respectively, 134', 135' and 136' a drain electrode, a source electrode and a gate electrode, respectively. In the figure, the section taken on A-A' is shown in FIG. 8 (d). Since the active area is all self-adjustably formed with respect to the side wall of the U-shaped groove, a step-cut insulated gate static induction transistor which has a good reproducibility can be manufactured. FIG. 10 shows one example of a sectional construction of 1 gate in which the aforesaid step-cut insulated gate static induction transistor is applied to a complementay metal-oxide-semiconductor transistor integrated circuit. In the figure, 140 designates a semiconductor substrate, the main surface of which is partly provided with a U-shaped groove. 141 designates an N + drain region, 142 a P + drain region, 143 an N + source region, and 144 a P + source region, and these regions have the impurity concentration of the order of 10 18 to 10 21 cm -3 . 145 designates a P channel region and 146 an N channel region, and these regions have the impurity concentration of the order of 10 12 to 10 16 cm -3 . At least in a part of the operating condition the impurity concentration and the depth of the U-shaped groove are determined so that a depletion layer spread from the drain region reaches the source region. 147 designates a gate insulator such as an oxide film and has a thickness of approximately 100 to 1,000 Å, 147' a gate electrode, and 148 a field oxide film. 149 designates an N type a berried layer for spaarating P channel transistor from N channel transistor. The gate electrode 147' comprises a logical input and the drain electrode 141' comprises a logical output, a power supplied voltage is applied between the source electrodes 143' and 144'. When the logical input is in a high level, the N channel transistor assumes a on state while the P channel transistor assume a off state, and therefore the logical output becomes a low level. The same is ture for the reversal case. Even such an integrated circuit can be manujactured nearly similarly to the manufacturing process shown in FIG. 8 except the construction of the substrate, and a high speed and low power complementary metal-oxide-semiconductor transistor integrated circuit may be provided with high reproducibility and reliability. For example, propagation delay time of 63 psec is obtained at a dissipation power of 3.9 mW, by a ring osciallator of the complementary metal-oxide-semiconductor transistor integrated circuit shown in FIG. 10.

Claims: A method of manufacturing a step-cut insulated gate static induction transistor, characterised by the following sequence of steps: anisotropic etching of a main surface of a semiconductor substrate (121) to form a U-shaped groove; deposition of mask material for selective oxidation on said main surface; anisotropic etching of said mask material to leave said mask material on an area of said main surface intended for eventual formation of said transistor; selective oxidation to form a field oxide film (123) over said main surface and removal said mask material to create a window (132) in said field oxide film (123); formation of a thin gate oxide film (124) in said window; deposition of material to form a gate electrode (125) and anisotropic etching to leave said gate electrode material in a self-aligned manner on a side wall of said groove; and formation of a drain region and a source region using said gate electrode (125) as a mask. A method according to claim 1 characterised in that said deposition of material for said gate electrode comprises deposition of a polycrystalline silicon film, and said anisotropic etching thereof comprises reactive ion etching using PCl 3 . A method according to claim 1 or claim 2 characterised in that a plurality of said transistors is integrated and formed on said substrate by said method. A step-cut insulated gate static induction transistor comprising: a U-shaped groove in a main surface of a semi conductor substrate (100); a drain or source region (101) having a high impurity concentration provided at the top of one side of said groove; a source or drain region respectively (102) having a high impurity concentration provided along the bottom of said groove in a position offset from said drain or source region, such that there is no overlap in their vertical alignments; a thin gate oxide film (104) on a side wall of said groove between said source and drain regions; a gate electrode (104') on said thin gate oxide film; a channel region (103) having a low impurity concentration provided between said source and drain regions, and a thick field oxide film (105) extending over said substrate (100) apart from contact areas to electrodes for said gate, drain and source regions; characterised in that a high impurity concentration region (106) having a conductivity type different from said drain or source region (101) and said source or drain region (102) is provided in the vicinity of said source region thereby to restrict a region through which current flows. A transistor according to claim 4 characterised in that said transistor comprises at least one of the constituent elements of a semi conductor integrated circuit.

Inventors: NISHIZAWA JUNICHI, SUZUKI SOUBEI, TAKEDA NOBUO, NISHIZAWA, JUNICHI, SUZUKI, SOUBEI, TAKEDA, NOBUO
Applicants: JAPAN RES DEV CORP, NISHIZAWA JUNICHI, SUZUKI SOUBEI, TAKEDA NOBUO, NISHIZAWA, JUN-ICHI, RESEARCH DEVELOPMENT CORPORATION OF JAPAN, SUZUKI, SOUBEI, TAKEDA, NOBUO
Application year: 1987
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27