Bi-level image display signal processing apparatus

Abstract: An image signal processing apparatus for converting step-gradation density values (I xy ) of successive picture elements to bi-level values (P xy ) for display by a bi-level display device, in which a bi-level error (E xy ) between a bi-level value determined for a picture element and an appropriate density value for the element is apportioned among a set of peripherally adjacent picture elements (A to D) by computing a corresponding set of error apportionment values (G A to G D ), and in which a difference between the sum total of these apportionment values and the bi-level error is derived, and error apportionment is modified such as to eliminate the effects of this difference. Improved reproduction is thereby attained of image regions which are of uniformly high density or low density.

Description: A requirement has arisen in recent years for high-quality reproduction of both printed images and step gradation images (for example an image representing a continuous-tone image as a plurality of step gradation density values) by utilizing a bi-level type of display device such as a gas plasma dot-matrix display which is inherently capable of generating only two levels of display density. This is achieved by generating a spatial gray scale display image. However, problems are presented by the prior art methods proposed for implementing such reproduction. With such a bi-level display device, each picture element generated by the display can be set (e.g. as an element of a dot matrix) in either a light or a dark state. There have been various proposals for implementing pseudo-continuous tone reproduction by such display devices by employing a spatial gray scale, which are based on setting a relatively high proportion of picture elements of the display in the light state within a display region which is to represent a light (i.e. low-density) region of the original image, and a high proportion in the dark state in the case of a dark (i.e. high-density) region of the original image. The most well-known method of providing such pseudo-continuous tone reproduction is the dither technique, whereby a step gradation representation of a continuous tone image is reproduced on the basis of numbers of dots within each of predetermined areas of the continuous tone image, by utilizing a dither matrix. Threshold values of the dither matrix are compared with the level of an input signal, one picture element at a time, to thereby execute bi-level image conversion processing. However this method has the disadvantage that the step gradation reproduction characteristic and the resolution of the image that is obtained will both depend directly upon the size of the dither matrix, and have a mutually incompatible relationship. Moreover with the dither technique, it is difficult to avoid the generation of moire patterns, particularly when printed images are reproduced. A method has been proposed in the prior art which is highly effective in overcoming these problems of the dither method. This is the "error diffusion" method, which has been proposed by R. Floyd and L. Steinberg under the title "An Adaptive Algorithm for Spatial Gray Scale", published in the SID 75 Digest, pp 36-37. The basic principles of the proposed method are as follows. To determine whether a picture element of the input signal is to be displayed at the dark or at the light level in the image generated by the bi-level display device, the corresponding level of the input image signal is compared with a threshold value, and a light/dark decision thereby made. The density value (i.e. completely dark or completely light) which is thereby determined for that picture element will in general be in error with respect to the desired density of that element, i.e. with respect to the density of the corresponding picture element in the original image. This error is referred to in the following as the bi-level conversion error. However with the error diffusion method, the effect of this error are substantially reduced by modifying (in accordance with the value of the error) the respective values of desired density to be subsequently used in processing respective ones of a specific set of picture elements which are positioned peripherally adjacent to the object picture element, and have not yet been processed. This modification is performed by apportioning the value of error obtained for that object picture element among these peripheral picture elements, with the error being apportioned in accordance with predetermined fixed factors. Such factors are referred to in the following as apportionment factors. The term "object picture element" as used herein has the significance of a picture element which is currently being processed, to determine a corresponding bi-level display image value, with data being utilized in that processing which have been obtained beforehand during processing of preceding picture elements. The error diffusion method is superior to the dither method with regard to image resolution and the reproduction characteristic for a step gradation source image, and enables the degree of generation of moire patterns to be made very small even when a printed image is being reproduced. However in the case of reproduction of an image which has only small amounts of changes in density, such as a computer-generated image having areas of extremely uniform density, the error diffusion method produces regions of texture in the reproduced image. This texture is inherent to the error diffusion method, and for this reason the error diffusion method has not been widely adopted. The reason for generation of this texture is that a fixed relationship is continuously maintained between an object picture element and the aforementioned set of picture elements which are disposed peripherally adjacent to the object picture element, and fixed values are also maintained for the respective proportions by which the bi-level conversion error of the object picture element is apportioned among these peripheral picture elements. Furthermore, if it is attempted to produce a practical type of digital computation processing circuit for implementing this prior art error diffusion method, it is found that the sum of the aformentioned error apportionment values which are generated during processing of each picture element is not equal to the corresponding bi-level error which is computed for that picture element. This is due to invevitable inaccuracies which arise in the process of computing these error apportionment values, due to discarding of low-significance bits of certain computation results. As a result, the entire bi-level error is not correctly apportioned among the picture elements which are peripherally adjacent to the object picture element, so that all of the possible step gradation density levels of the input signal cannot be properly reproduced in the final image. This is especially true when the input signal level represents a high value or a low value of image density, and hence the range of step gradation image density values which can be reproduced by the prior art error diffusion method is made narrow. It is a further disadvantage of the prior art is that a plurality of respectively different computations must be executed consecutively in order to process each picture element, so that it is difficult to achieve a high speed of image processing. It is an aim of the present invention to provide an image signal processing apparatus which overcomes the disadvantages of the prior art error diffusion method described above, and which provides a display image having high resolution and an excellent step gradation reproduction characteristic, with only very small amounts of moire pattern being produced even when the source image is a printed image, and with no texture being generated even in image regions which are of highly uniform density. The present invention provides an image signal processing apparatus for receiving an input signal comprising successive digital level values each representing a step gradation density level of a corresponding picture element of a source image, to produce a bi-level image signal by sequentially converting these level values to corresponding bi-level values in respective processing steps, with an error between the bi-level value derived for each of the picture elements and a required density level for that picture element being apportioned among a set of peripherally adjacent picture elements which have not yet been processed. According to the present invention there is provided an image signal processing apparatus for sequentially processing input level values which are supplied to an input terminal in successive processing periods and which represent respective density levels of a rectangular array of picture elements representing an image, to produce corresponding bi-level values, said apparatus comprising: error memory means for storing a bi-level error of an object picture element in a set of memory locations respectively corresponding to said object picture element and to a set of adjacent picture elements which have not yet been processed and which extend peripherally from the object picture element in said rectangular array; input correction means including means for adding an input level value, which is received at said input terminal two processing periods prior to a processing period in which said input level of said object picture element is received and corresponds to a first one of said set of peripherally adjacent picture elements, to an accumulated error which is stored at a location in said error memory means corresponding to said first adjacent picture element, to thereby derive a first corrected input level value, and first register means for holding and outputting said corrected input level value after one processing period; difference computing means coupled to said first register means to receive a second corrected input level value corresponding to a second one of said set of adjacent picture elements, and including means for obtaining a first difference level value as said difference between a first possible value of said bi-level output values and said second corrected input level value, and a second difference level value as said difference between a second possible value of said bi-level output values and said second corrected input level, and second and third register means for respectively holding said first and second difference level values and outputting said first and second difference level values after one processing period; bi-level conversion means coupled to receive said first and second difference level values produced from said register means of said difference computing means, and including means for adding to each of said first and second difference level values a first error apportionment value, to obtain a first error value and second error value respectively, comparator means for comparing said first error value with a predetermined threshold value to thereby obtain a bi-level value for said object picture element, selector means for selecting one of said first and second error values in accordance with said state of said bi-level value for said object picture element, to be outputted as a bi-level error for said object picture element, and fourth register means for holding and outputting said bi-level error after one processing period; apportionment factor generating means for generating a set of apportionment factors for use in apportioning said bi-level error of said object picture element among elements which have not yet been processed; and error apportionment and updating means for computing respective error apportionment values including said first error apportionment value and respectively corresponding to a set of picture elements which are immediately peripherally adjacent to said object picture element and have not yet been processed, based on said bi-level error read out from said bi-level error register and said set of apportionment factors, adding said error apportionment values to respective values of accumulated error which are stored at locations in said error memory means respectively corresponding to said set of immediately peripherally adjacent picture elements, and storing said respective addition results in said error memory means as updated accumulated error values. With the above apparatus according to the invention, processing operations which must be performed sequentially to process each picture element in the case of the other apparatus are performed concurrently, for respectively different picture elements, so that a substantially increased processing speed can be attained. The present invention will be further described hereinafter with reference to the following description of an exemplary embodiment and the accompanying drawings, in which: Fig. 1 is a conceptual block circuit diagram of a first image signal processing apparatus described for use in explaining the advantages of the present invention; Figs. 2(a) and 2(b) are block circuit diagrams to respectively show details of essential blocks in two different implementations of the apparatus of Figure 1; Fig. 3 is a conceptual block circuit diagram of a second image signal processing apparatus described for reference; Figs. 4(a) and 4(b) are block circuit diagrams respectively showing details of essential blocks shown in Fig. 3; Fig. 5 is a conceptual block circuit diagram of a third image signal processing apparatus described for reference; Fig. 6 is a block circuit diagram showing details of essential blocks shown in Fig. 5; Fig. 7 is a conceptual block circuit diagram of a fourth image signal processing apparatus described for reference; Fig. 8 is a block circuit diagram showing details of essential blocks shown in Fig. 7; Fig. 9 is a conceptual block circuit diagram of a fifth image signal processing apparatus described for reference; Fig. 10 is a diagram to illustrate an arrangement of sequentially positioned image regions for assistance in describing the apparatus of Fig. 9; Fig. 11 is a conceptual block circuit diagram of an example of a density modulation section in the apparatus of Fig. 9; Fig. 12 is a conceptual block circuit diagram of an embodiment of the present invention; and Fig. 13 is a block circuit diagram showing details of an error apportionment and updating section in the embodiment of Fig. 12. Fig. 1 is a general block diagram showing the essential components of a first image signal processing apparatus which is described for reference purposes. Numeral 104 denotes an input terminal to which is applied to input image signal I xy consisting of successive digital values constituting respective level values, each representing a step gradation density level of a corresponding picture element of a source image. The input image signal is derived by successively sampling the source image in units of picture elements, i.e. by successively sampling picture elements along each of a successively selected lines of picture elements, each line being aligned in a direction referred to in the following as the x-direction, the lines being successively arranged along a direction perpendicular thereto (referred to in the following as the y-direction), so that each picture element can be defined by x and y-coordinates. The apparatus functions to produce a a bi-level output value P xy in response to each input level value I xy , from an output terminal 106 by sequentially converting the input level values in respective processing steps. The bi-level output values that are thus produced can each represent either of two values, designated as 0 and R in the following, corresponding to a low and a high density (i.e. light and dark state) respectively of a bi-level display image produced on the basis of these bi-level values. An error between the bi-level value derived for a picture element and the density level which is actually appropriate for that picture element (defined as described hereinafter) is apportioned among a set of peripherally adjacent picture elements which have not yet been processed. In Fig. 1, the display coordinates of an object picture element (i.e. a picture element for which image processing is currently being executed to generate a corresponding bi-level output value) are designated as (x,y). Reference numeral 101 denotes an error memory section, used to store values of accumulated error as described hereinafter. Numeral 103 denotes a location in the error memory section 101 in which is stored the accumulated error value for the object picture element, the object picture element position being indicated by the * symbol, and numeral 102 denotes a storage region of error memory 101 containing a set of memory locations respectively corresponding to positions of a set of picture elements (designated as A, B, C and D) that have not yet been processed and are positioned adjacent to the periphery of the object picture element. Each picture element is processed during an interval of fixed duration, synchronized with a sync signal. The picture element at position A is processed to generate a corresponding bi-level value immediately following processing of the object picture element, i.e. processing of successive picture elements takes place (in the x-direction) from left to right as seen in Fig. 1, and picture element positions D, C and B will be successively processed during scanning of the next line of picture elements, i.e. after one line shift in the y-direction has occurred. Numeral 105 denotes an adder which amends the input signal level I xy by adding thereto an accumulated error S xy (whose value is determined by a combination of accumulated error values as described hereinafter) to produce a corrected input level I' xy for the object picture element, i.e. I' xy = I xy + S xy . Numeral 107 denotes a terminal to which is applied a threshold level which in this embodiment is equal to R/2, and 108 denotes a device such as a comparator, for executing bi-level conversion of the input level I' xy , by comparing the level I' xy with the fixed threshold value R/2, to produce as output a bi-level value P xy at the R level if I' xy > R/2, and otherwise producing P xy at the 0 level. Numeral 109 denotes a subtractor, for computing a difference between the corrected input level I' xy and the output bi-level value P xy to thereby derive a bi-level conversion error E xy (i.e. E xy = I' xy - P xy ) for the object picture element. The components described above, and their functions, might be envisaged on the basis of the published matter concerning the error diffusion method described hereinabove. The novel features of this apparatus reside in an error apportionment value computation section 110, an apportionment factor generating section 111, an error updating section 112, a residual error computation section 113 and an apportionment value computation section 114, which are described in detail in the following. The apportionment factor generating section 111 has stored therein beforehand a set of apportionment factors K A to K D , and supplies these apportionment factors to the error apportionment value computation section 110, for apportioning the bi-level error E xy of the object picture element among the picture element positions A to D of the peripheral picture element region 102. The error apportionment value computation section 110 operates in synchronism with a sync signal which is synchronized with the intervals of processing successive picture elements, and utilizes the bi-level error E xy for the object picture element (produced from the difference computation section 109) and the apportionment factors K A to K D to derive a set of error apportionment values G A to G D for the picture element positions A, B, C and D within the peripheral picture element region 102, employing equations (1) below. The error apportionment value computation section 110 supplies these error apportionment values G A to G B to the error updating section 112 and the residual error computation section 113. The residual error computation section 113 functions to derive, using equation (2) below, a residual error J B which is the difference between the bi-level error E xy and the sum total of the error apportionment values G A to G D . In addition, the residual error J xy is multiplied by each of the factors A A to A D , as shown in equations (5) below, to derive respective residual apportionment values RZ A to RZ D . The residual apportionment values RZ A to RZ D thus obtained are output to the apportionment value computation section 114 (described hereinafter), which functions to add the error apportionment values G A to G D from the error apportionment value computation section 110 to the residual apportionment values RZ A to RZ D respectively, and to output the results as respective apportionment values H A to H D , to the error updating section 112. The error updating section 112 operates in synchronism with the aforementioned sync signal, and receives the apportionment values H A to H D from the apportionment value computation section 114, reads out a set of accumulated errors S A ', S B ', S C ', S D ' which had been derived and stored in the memory device 101 during previously executed picture element processing operations at locations respectivly corresponding to the picture elements of positions A, B, C and D in the peripheral picture element region 102 of error memory section 101, and derives new values of accumulated error S A to S D by utilizing equations (4) below. In addition, the error updating section 112 performs updating processing by writing into the error memory section 101 the new values of accumulated error S A to S D , at locations respectively corresponding to the picture element positions A to D. Fig. 2(a) shows specific configurations for the error apportionment value computation section 110, the apportionment factor generating section 111, the error updating section 112, the residual error computation section 113 and the apportionment value computation section 114 respectively shown in Fig. 1. In Fig. 2(a), the apportionment factor generating section 111 incorporates a memory section 201 having stored therein beforehand (prior to the commencement of image processing) a set of apportionment factors K A to K D . The memory section 201 can consist for example of a ROM (read-only memory) into which the apportionment values K A to K D have been written beforehand. The error apportionment value computation section 110 includes a set of multipliers 202a to 202d, for deriving the respective products of the bi-level error E xy and each of the apportionment factors K A to K D , as the error apportionment values G A to G D . These error apportionment values are supplied to the apportionment value computation section 114 and the residual error computation section 113. The residual error computation section 113 computes a value of residual error J xy , which is the difference (derived by a subtractor 204) between the bi-level error E xy and the sum total of the error apportionment values G A to G D from the error apportionment value computation section 110 (this sum being derived by adders 203a to 203c). The residual error J xy is supplied to a residual apportionment value computation section 205, which includes a memory having a table of values stored therein, which contains the set of residual factors A A to A D of equation (3) above, and multipliers for multiplying the residual error J xy by each of these residual factors obtained from the table of values. The residual apportionment value generating section 205 thereby produces a set of residual apportionment values RZ A to RZ D in accordance with the residual error J xy , which are used by the apportionment value computation section 114 for apportioning the residual error J xy amaong the peripheral picture element positions A to D respectively. The apportionment value computation section 114 adds the error apportionment values G A to G D from the error apportionment value computation section 110 to the residual apportionment values RZ A to RZ D respectively, in a set of adders 206a to 206d, and thereby produces respective apportionment values H A to H D as outputs, which are applied to the error updating section 112. The error updating section 112 operates in synchronism with a sync signal 215 which is applied to a sync input terminal 107 and constitutes the sync signal described hereinabove which is synchronized with successive picture element processing intervals. The error updating section 112 functions to add (in an adder 208a) the apportionment value H A to the accumulated error S' A corresponding to the picture element position A, which has been derived in a previously executed picture element processing operation and stored in the error memory section 101, and stores the result of the addition temporarily in an internal register 209a (R A ) to be used as the accumulated error S xy in the next picture element processing operation (i.e. the operation in which the picture element of position A in region 102 becomes the object picture element, and is processed). The apportionment value H B which is produced in the current picture element processing step, during processing of the object picture element, is temporarily stored (i.e. to be read out in the succeeding picture element processing interval) in an internal register 209b (R B ) as the accumulated error S B for the picture element position B. The apportionment value H C is added (in an adder 208b) to the data S B ' which had been temporarily stored in the internal register 209b during the preceding picture element processing operation, and the result is stored in an internal register 209c (R C ) as the accumulated error S C for the picture element position C. The apportionment value H D is added to data S C ' which had been temporarily stored in an internal register 209c (R C ) during processing of the preceding picture element, and the result is stored in a memory unit of the error memory section 101 at a location corresponding to the picture element position D, as the accumulated error S D for that picture element position. It can be seen that with the configuration for the error updating section 112 described above, the only accessing of the memory unit in the memory section 101 consists of read-out access corresponding to the picture element position A and write-in access corresponding to the picture element position D. Each of the internal registers 209a etc. can be configured as simple latch circuits, for example. Thus, the memory section 101 can be easily implemented. Fig. 2(b) shows another specific configuration for the apportionment factor generating section 111, the error apportionment value computation section 110, residual error computation section 113 and memory section 205, which can be utilized if the following values are adopted for the apportionment factors which apportion the bi-level error E xy among the the set of unprocessed picture elements positioned at the periphery of the object picture element: In the above, i and j denote respective coordinates along the horizonal and vertical directions, considering the set of positions in region 102 and the object picture element position, as a matrix array. In Fig. 2(b), the only blocks which differ from those of Fig. 2(a) are the residual error computation section 113 and error updating section 112 which are described in the following, while the apportionment value computation section 114 of the arrangement shown in Fig. 2(a) is eliminated. In the embodiment of Fig. 2(b), the bi-level error E xy is a digital value consisting of more than three bits. The residual error computation section 113 contains a line selector 210 which extracts the three least significant bits of the data representing E xy , and reapportions these bits as residual apportionment values RV A , RV C and RV D . The error updating section 112 is substantially identical to that of Fig. 2(a), however the adders 208a, 208b and 208c which compute the new accumulated errors S A to S D , are different in that a "carry" input terminal (designated as C) of each of these adders is utilized. The new accumulated errors S A to S D are obtained by adding the error apportionment values G A to G D to respective ones of the accumulated errors S A ', S C ' and S D ' which were derived during previous picture element processing operations, and to the residual apportionment values RV A , RV C and RV D respectively from the residual error computation section 113. Each of the residual apportionment values RV A , RV C and RV D consists of a single data bit, these being respectively applied to the "carry" input terminals C of the adders 208a, 208b and 208c. This enables the apportionment value computation section 114 shown in Fig. 2(a) to be eliminated. In this way, a practical circuit can be implemented, by utilizing the apportionment factor values set out in equation (6) above, whereby the computation operations and circuits can be substantially simplified by comparison with the system of Fig. 2(a). With the first apparatus, as described above, a bi-level error of an object picture element is apportioned as error apportionment values among a set of picture elements which are peripherally adjacent to that object picture element, with a residual error (which is the difference between the bi-level error and the sum total of the error apportionment values) being derived and reapportioned as a set of residual apportionment values. As a result, a problem which arises with a digital computation type of processing circuit for practical implementation of the error diffusion method, i.e. the problem of deterioration of the continuous tone reproduction characteristic when the input signal level represents a low image density or a high image density, is substantiall overcome. Fig. 3 is a general block diagram of a second image signal processing apparatus. The essential feature of this apparatus, as for the first apparatus, is that of elimination of the effects of an error resulting from digital computation of the error apportionment values by which the bi-level error E xy of the object picture element is apportioned among a set of peripherally adjacent picture element positions, i.e. a residual error whereby the sum total of these error apportionment values is not equal to the value of the bi-level error. In Fig. 3, each of blocks 101 to 111 is essentially identical to the correspondingly numbered block in Fig. 1, described hereinabve, so that further description of these will be omitted. The features of the second embodiment which are different from those of the first embodiment reside in an error updating section 112 and a residual error computation section 113, described in the following. The residual error computation section 113 functions to derive, using equation (6) below, the residual error J B which is the difference between the sum total of the error apportionment values G A to G D and the bi-level error E xy . The residual error J B is supplied to the error updating section 112. The error updating section 112 functions in synchronism with a sync signal (synchronized with successive picture element processing operations, as described for the first embodiment) to receive the error apportionment values G A to G D from the error apportionment value computation section 110 and the residual error J B from the residual error computation section 113 and to read out accumulated errors S A ', S C ', S D ' which were obtained in previously executed picture element processing operations and stored in a memory unit at locations corresponding to the picture element positions A, C, D in the error memory section 101, and derives new values of accumulated errors S A to S D by using equations (7) below. In addition, the error updating section 112 performs updating processing by writing into the error memory section 101 the new accumulated errors S A to S D ' at locations respectively corresponding to the picture element positions A to D. In the above description the residual error J B is obtained by using equations (7) on the basis of picture element position B within the peripheral picture element region 102. However it would be equally possible to use any of the other picture element positions A, B, C or D within that region for this purpose. In the following, it will be assumed that the picture element position B is used in equations (7). It should also be noted that it would be equally possible to temporarily store the residual error J B within an internal register, and to read out this residual error at the time of processing the next picture element and add the residual error to the error apportionment value for any one of the picture element positions A', B', C' or D'. Fig. 4(a) shows a specific configuration for the error apportionment value computation section 110, the apportionment factor generating section 111, the error updating section 112 and the residual error computation section 113. With this configuration, the residual error J B is temporarily stored in an internal register, to be used in computing a value of accumulated error for the peripheral picture element position B, as described in the following. The apportionment factor generating section 111 includes a memory section 201 having stored therein beforehand (i.e. prior to the commencement of image processing) a set of apportionment factors K A to K D . The memory section 201 can consist for example of a ROM (read-only memory). The error apportionment value computation section 110 derives the respective products of the bi-level error E xy and each of the apportionment factors K A to K D (by a set of multipliers 201a to 201d) as the error apportionment values G A to G D , and outputs these error apportionment values to the error updating section 112 and the residual error computation section 113. The residual error computation section 113 computes the residual error J B ' which is the difference (computed by a subtractor 204) between the bi-level error E xy and the sum total of the error apportionment values G A to G D from the error apportionment value computation section 110 (computed by a set of adders 203a to 203c) and temporarily stores the result in an internal register 401 (R J ), until the succeeding picture element processing operation. A residual error J B ' which had been derived and stored in the internal register 401 at the time of processing the preceding picture element is output at this time to the error updating section 112. The error updating section 112 operates in synchronism with a sync signal 214, applied to a sync input terminal 207, which is synchronized with successive picture element processing operations, and adds (by an adder 402a) the error apportionment value G A to the accumulated error S A ' for the picture element position A, read out from the error memory section 101, and temporarily stores the result in an internal register 403a (R A ) to be used as the accumulated error S xy during processing of the succeeding picture element. In addition, the accumulated error for picture element position B is added (by an adder 402b) to the residual error J B ' which was temporarily stored in the residual error computation section 113 during processing of the preceding picture element, and stores the result as an accumulated error S B in the internal register 403b (R B ). The error apportionment value G C is added (by an adder 402c) to the data which had similarly been stored in the internal register 403b (R B ), and the result is temporarily stored in the internal register 403c (R C ) as the accumulated error S C for the picture element position C. The error apportionment value G D is added (by an adder 402d) to the data which had been temporarily stored in the internal register 403c (R C ), and the result is stored at a location in a memory unit of the error memory section 101 corresponding to the picture element position D, as the accumulated error S D for the picture element position D. Thus, as for the first apparatus, the only accessing of the memory unit of the memory section 101 consists of read-out access corresponding to the picture element position A and write-in access corresponding to the picture element position D, so that a practical apparatus can be readily configured. Fig. 4(b) shows a specific configuration for the residual error computing section 113, for the case in which the apportionment factors K ij for apportioning the bi-level error E xy among the picture elements which are peripherally adjacent to the object picture element are respectively determined to be as follows: In Fig. 4(b) a bi-level error E xy ' consists of the least significant three bits of the bi-level error E xy , and is inputted to a decoder 411 which thereby produces as output the residual error J B as a 2-bit data value. The relationships between the values of E xy ' and J B established by this decoder 411 are as shown in the following table. E xy ' J B 111 3 110 2 101 2 100 1 011 2 010 1 001 1 000 0 The residual error J B is temporarily stored in a register 412 and is read out during processing of the next picture element, as the residual error J B '. In this way, by using a set of apportionment factors as specified in equation (8), a practical circuit configuration can be realized without the need for complex computations. With the second apparatus, as described in the above, a bi-level error of an object picture element is apportioned as error apportionment values among a set of picture elements which are peripherally adjacent to that object picture element, with the difference between the bi-level error and the sum total of the error apportionment values being derived during each picture element processing operation and used for correction to compensate for that error during a succeeding picture element processing operation. As a result, the problem which arises with a processing circuit having a digital computation type of processing circuit for practical implementation of the error diffusion method, i.e. the problem which arises with respect to the continuous tone reproduction characteristic for input signal levels representing low values of image density or high values of density due to the effects of the error, is substantially eliminated. Fig. 5 is a conceptual block diagram of a third image signal processing apparatus. In Fig. 5, numerals 101 to 109 denote blocks which are similar to the correspondingly numbered blocks in the apparatus shown in Fig. 1, so that further description of these will be omitted. The circuit of Fig. 5 differs from that of Fig. 1 with respect to the respective configurations of the apportionment value computation section 114, apportionment factor generating section 111, error updating section 112 and bi-level error apportioning section, which will be described in detail in the following. The bi-level error E xy is obtained as a digital value composed of more than n bits, where n is a fixed integer. The bi-level error apportionment section 115 functions to extract the n least significant bits of E xy and output these n bits as a bi-level error E xyl to the error updating section 112, and also sets each of the n least significant bits of the bi-level error E xy to zero and outputs the resultant converted value of E xy as a bi-level error E xyu to the apportionment value computation section 114. The apportionment factor generating section 111 has stored therein beforehand a set of apportionment factors for a set of unprocessed picture elements positioned at the periphery of the object picture element, and outputs these apportionment factors K A to K D to the apportionment value computation section 114, for apportioning the bi-level error E xyu among these picture elements A to D within the peripheral picture element region 102. The apportionment value computation section 114 operates in synchronism with a sync signal which is synchronized with successive picture element processing intervals, and utilizes the bi-level error E xyu for the object picture element (produced from the bit apportioning section 109) and the apportionment factors K A to K D to derive a set of error apportionment values G A to G D for the picture element positions A, B, C and D within the peripheral picture element region 102 of the error memory section 101, employing equations (9) given below. The apportionment value computation section 114 thereby produces the error apportionment values G A to G D as outputs, and supplies these to the error updating section 112. The error updating section 112 operates in synchronism with the aforementioned sync signal, and functions to derive new values of accumulated error S A to S D respectively corresponding to the picture element positions A, B, C, D within the peripheral picture element region 102 of the error memory section 101, based on the error apportionment values G A to G D , accumulated error values S A ', S C ' and S D ' which were derived and stored in previously executed processing operations, and the bi-level error E xyl produced from the bi-level error apportioning section 115, by employing equations (10) below: In this apparatus, the bi-level error E xyl is added to the error apportionment value for picture element position B of the peripheral picture element region 102. However it would be equally possible to add E xyl to any one of error apportionment values for the respective picture element positions A, B, C or D. In the following it will be assumed that picture element position B is utilized. Fig. 6 shows specific configurations for the apportionment value computation section 114, the apportionment factor generating section 111, the error updating section 112 and the bi-level error apportioning section 115. In this apparatus, the bi-level error E xyl is applied to the picture element position B, as described in the following. The apportionment factor generating section 111 includes a memory section 201 having stored therein beforehand (i.e. prior to the commencement of image processing) a set of apportionment factors K A to K D . The memory section 201 can consist for example of a ROM (read-only memory) having the apportionment factors written therein. The bi-level error apportioning section 115 includes a bit apportioning section 601 which functions to reset the n least significant bits of the bi-level error E xy to logic "0", with the resultant converted value of E xy being output as the bi-level error E xyu to the error apportionment value computation section 114, and a bit apportioning section 602 which functions to extract the n least significant bits of the bi-level error E xy and to output these as the bi-level error E xyl to the error updating section 112. The apportionment value computation section 114 multiplies each of the apportionment factors K A to K D by the bi-level error E xyu in a set of multipliers 603a to 603c, to thereby derive the error apportionment values G A to G D , and outputs these to the error updating section 112. The error updating section 112 operates in synchronism with a sync signal 214 applied to a sync input terminal 207 which is synchronized with successive picture element processing intervals, and adds the error apportionment value G A to the accumulated error S A ' for the picture element position A, read out from the error memory section 101 (this addition being executed by an adder 604a), and temporarily stores the result in an internal register 605a (R A ) to be used as the accumulated error S xy during processing of the succeeding picture element. The accumulated error for picture element position B is obtained by adding the bi-level error E xyl from the bi-level error computation section 115 to the error apportionment value G B for picture element position B (by an adder 604b), and storing the result as an accumulated error S B in the internal register 605b (R B ), until the next processing interval. The error apportionment value G C is added by an adder 604c to the data which had been temporarily stored in the internal register 605b (R B ) at the time of processing the preceding picture element, and the result is stored in the internal register 605c (R C ) as the accumulated error S C for the picture element position C, until the next procesing interval. The error apportionment value G D is added by an adder 604d to the data which had similarly been temporarily stored in the internal register 605c (R C ), and the result is stored at a memory location in the error memory section 101 corresponding to the picture element position D, as the accumulated error S D for that picture element position. Due to the configuration for the error updating section 112 described above, the only accessing of the memory in the memory section 101 consists of read-out access corresponding to the picture element position A and write-in access corresponding to the picture element position B, so that a practical apparatus can be easily implemented. With the third apparatus, as described in the above, the n least significant bits of the bi-level error E xy are extracted and apportioned to one of the picture element positions which is peripherally adjacent to the object picture element position, while in addition these n least significant bits of the bi-level error E xy are reset to logic "0" and the resultant value is apportioned among each of the remaining peripheral picture element positions in accordance with the respective apportionment factors for these positions. As a result, this apparatus effectively eliminates the effects of an error which arises due to the effects of discarding low-significance bits of the bi-level error E xy during computation of the error apportionment values G A to G D . Thus, the effective sum total of the error apportionment values used for apportioning the bi-level error E xy of the object picture element among the picture element positions peripherally adjacent thereto is made identical to that bi-level error. The apparatus thereby enables a practical integer computation type of processing circuit for implementing the error diffusion method to be realized, by considerably improving the step gradation reproduction characteristic for input signal levels which represent image regions of low density or high density. Fig. 7 is a conceptual block diagram of a fourth image signal processing apparatus. In Fig. 7, numerals 101 to 109 denote blocks which are similar to the correspondingly numbered blocks in the prior art apparatus for the error diffusion method shown in Fig. 1, so that description of these will be omitted. The apparatus of Fig. 7 differs from that of Fig. 1 with respect to an error computation section 700, an error apportionment and updating section 710, and an apportionment factor generating section 720, which will be described in detail in the following. The error computation section 700 serves to derive a compensated error H XY by utilizing a factor Kt which is a function a threshold level TH (produced as described hereinafter,) and the bi-level error E xy which is produced from the difference computation section 109, by using equation (11) below: H XY = E xy x Kt(TH) The apportionment factor generating section 720 has two sets of apportionment factors stored therein prior to the commencement of processing, corresponding to a set of picture elements peripherally adjacent to the object picture element,and operates in synchronism with successive picture element processing intervals to select from these sets of apportionment factors a set of apportionment factors KA to KD for apportioning the compensated error H XY among a plurality of picture element positions A to D within the peripheral picture element region 102, and supplies the selected apportionment factors to the error apportionment and updating section 710. Numeral 718 denotes a threshold level adjustment section, which produces the threshold level value TH and which is operable (e.g. by the action of a user of the apparatus) to vary the value TH. Such variation of the threshold level applied the the bi-level conversion section 108 results in corresponding variations the overall density (i.e. overall darkness or lightness) of a bi-level display image which is produced utilizing the bi-level values from output terminal 106. The user can thereby the adjust the overall image density as required. The error apportioning and updating section 710 receives the apportionment factors KA to KD and the compensated error H XY of the object picture element, and apportions this error in acccordance with the apportionment factors among the set of peripheral picture element positions of region 102 described above, as respective error apportionment values. The error apportioning and updating section 710 also reads out accumulated errors sa', sc' and sd' (which have been obtained in the processing operation executed for the preceding picture element) corresponding to the picture element positions A, C and B in the region 102, and derives new values of accumulated error S A to S D by using the following equations (12): Updating processing is then executed by the error apportionment and updating section 710, by writing the new values of the accumulated errors S A to S D into the error memory section 101 at locations which respectively correspond to the picture element positions A to D. It would be equally possible to derive the compensated error H XY from the following equation (13): H XY = E xy + (TH - R/2) In the above, R is the maximum value of density level of the bi-level output, i.e. of P xy . Fig. 8 shows specific configurations for the error computation section 700, the error apportionment and updating section 710 and the apportionment factor generating section 720. In Fig. 8, it is assumed that the error computation section 700 functions to derive the compensated error H XY by utilizing equation (13) above. The error computation section 700 performs this computation by utilizing the bi-level error E xy and the difference between the density level R/2 (which is applied to a density level input terminal 213) and the threshold level TH, and outputs the value of H XY thus computed to the error apportionment and updating section 710. The apportionment value computation section 720 includes a memory 1 (721) and memory 2 (722) having respectively stored therein prior to the commencement of image processing two sets of apportionment factors K1A to K1D and K2A to K2D. Apportionment factors are selected from among the contents of memories 721 and 722, to be produced as the set of apportionment factors K A to K D , by a set of four selectors 724 to 727, with the selection thus executed being determined by a selection signal 723a applied from a selection signal generator 723. The selection signal generator 723 is configured such that the selection signal is a random signal, and can for example be implemented as a maximum length counter. Each of the selectors 724 to 727 has two input terminals and one output terminal, and each is controlled by the selection signal 723a for randomly selecting a set of apportionment factors KA to KD from the two sets of apportionment factors K1A to K1D and K2A to K2D in the first and second memories 721 and 204. The apportionment value computation section 720 multiplies each of the apportionment factors KA to KD by the compensated error H XY supplied from the error computation section 760, to thereby produce error apportionment values 711a to 714a. The error apportionment value 711a is then added to the accumulated error S A ' that corresponds to the picture element position A, (the accumulated error S A ' being read out from a location of error memory section 101 corresponding to position A in the peripheral region 102) and the result of this is temporarily stored in an internal register 716a (RA) to be utilized as the accumulated error S xy for the next picture element to be processed in the succeeding processing step. Then, since the accumulated error for the picture element B is first produced during processing of the object picture element, the error apportionment value 712a is temporarily stored (without being altered) as the accumulated error (SB) for the picture element position B, in an internal register 716b (RB). The error apportionment value 713a and the data which were derived during the immediately preceding picture element processing operation and temporarily stored in the internal register 716b (RB) are added together, and the result of the addition is then temporarily stored in the internal register 716c (RC), as the accumulated error value (SC) for the picture element position C. The error apportionment value 217 is added to the data which were derived during the immediately preceding picture element processing operation and temporarily stored in the internal register 716c(RC), and the result of this addition is stored as the accumulated error (SD) for the picture element position D, in a memory location in the error memory section 101 which corresponds to the picture element position D. As a result of this operation of the error apportionment and updating section 710 the only memory accessing which is required for the error memory section 101consists of read-out access corresponding to the picture element A, and write-in access corresponding to the picture element D. Thus, a practical configuration for this embodiment can be easily implemented. With the fourth apparatus, as described in the above, the ratios by which the bi-level error of the object picture element is compensated by a factor which is a function of the threshold level, prior to apportionment of the bi-level error. As a result, density adjustment of the reproduced image by variation of the threshold level can be performed to adjust the overall image density of a bi-level display image produced from the output signal of the apparatus, while maintaining satisfactory error apportionment operation. It is an inherent disadvantage of the prior art error diffusion method that any regions in the source image which have extremely uniform density will result in corresponding regions of the displayed bi-level image containing a texture pattern. A fifth image signal processing apparatus will be described whereby such a texture pattern can be substantially completely eliminated. Fig. 9 is a block diagram of the essential components of this apparatus. The blocks numbered 101 to 109 in Fig. 9 are respectively identical to the correspondingly numbered blocks in Fig. 1, described hereinabove. This embodiment differs from the example of Fig. 1 with respect to error apportionment and updating section 900, apportionment factor generating section 910, and density modulation section 928, which are described in detail in the following. The density modulation section 928 functions to modulate the input image signal, i.e. the input level I xy , such as to superimpose periodically positioned regions of modulated density upon the density levels of the source image, to produce an input level I' xy . Each of these modulation regions can for example consist of an array of 8 x 8 picture elements, as illustrated in Fig. 10. The function of this modulation of the source image density levels is to impart variations in density to any portions of the source image which are of highly uniform density, prior to bi-level conversion processing, and to thereby eliminate the generation of texture patterns in the resultant bi-level displayed image, which is an inherent feature of the prior art error diffusion method as described hereinabove. However the modulation within each of these regions is both positive and negative-directed, i.e. density is added to and subtracted from respective picture elements within each region, with this density addition and subtraction being executed such that the total resultant change in density within each region is zero. Thus, since each of the modulation regions is of extremely small size by comparison with the overall display image area, there will be no visibly perceptible effect upon the display image produced by utilizing the output bi-level signal from by the apparatus. Fig. 10 illustrates an arrangement of such modulation regions, for the case in which each region consists of a rectangular array of 8 x 8 picture elements. Numeral 940 denotes the set of picture elements of the source image (only part of which are shown), numeral 941 a first modulation region, numeral 951 a modulation region positioned immediately below region 941, and numeral 961 a modulation region positioned immediately to the right of region 941. As shown, each modulation region consists of a rectangular array of picture elements which are respectively numbered from I x0,y0 to I x7,y7 (i.e. by coordinates which define position within each modulation region). Numeral 942 denotes the first picture element I x0,y0 of modulation region 941, numeral 943 denotes picture element I x0,y0 of region 951, and numeral 944 denotes picture element I x0,y0 of modulation region 961. Fig. 11 shows an example of a configuration for the density modulation section 920, in which an address signal generating circuit 962 is coupled to receive an x-direction sync signal (i.e. a signal which is synchronized with successive picture element processing intervals along the x-direction) and a y-direction sync signal (i.e. a signal which is synchronized with selection of successive lines of picture elements, along the y-direction), and produces address signals which are supplied to a memory 963. The memory 963 can be configured as a RAM (random access memory) or a ROM (read-only memory), and has a predetermined set of density values stored therein, for thereby producing output signals representing successive values which respectively vary in amplitude and polarity in response to successive address signals supplied from the address signal generating circuit 962. The values produced from the memory 963 are predetermined such that the sum total of these values within each of the modulation regions is zero. Each of these values is added to an input density level signal I xy in an adder 964, which produces an output density-modulated value I xy ' to be supplied to the adder 105 in Fig. 9. Thus, during processing of the first line of picture elements of the source image, a set of 8 values varying respectively in amplitude and polarity are successively produced from memory 963 and added to successive input level values in the adder 964 corresponding to picture elements I x0,y0 to I x7,y0 of the first modulation region 941, the same set of 8 values are then once more read out from memory 963 for the second modulation region 961, and so on. The same process thereafter occurs, with a different set of 8 values being repetitively read out from memory 963, during processing of the second line of picture elements. When the 9th line of picture elements is reached, the second row of modulation regions begins to be modulated, by the same sequences of output values from the memory 963 as were produced for the first row. It should be noted that it would also be possible to achieve the effects of the address signal generating circuit 962 and the memory 963 by utilizing a shift register circuit. Referring again to Fig. 9, the apportionment factor generating section 910 has stored beforehand therein one set of apportionment factors (i.e. corresponding in number to a set of unprocessed picture elements positioned at the periphery of the object picture element ) as shown for example in Figs. 2(a), (b), Fig. 4(a) or Fig. 6 described hereinabove, and functions to randomly select from that set of apportionment factors a set of apportionment factors K A to K D for respectively apportioning the bi-level error E xy among a plurality of picture element positions A to D within the peripheral picture element region 102, and supplies the selected apportionment factors to the error apportionment and updating section 900. The error apportionment and updating section 900 operates in synchronism with the sync signal 931a (i.e. the x-direction sync signal as described hereinabove) to store in the error memory section 103 the bi-level error E xy of an object picture element (produced from difference computation section 109) in accordance with the apportionment factors K A to K D , at memory locations corresponding to the picture element positions A, C and D respectively within the peripheral picture element region 102. The error apportionment and updating section 900 also reads out accumulated errors S A ', S C ' and S D ' (which have been obtained in previously executed picture element processing operations) corresponding to the picture element positions A, C and B in the peripheral picture element region 102, and derives new accumulated errors S A to S D by using the following equation (14): Updating processing is then executed by the error apportionment and updating section 900, by writing the new values of the accumulated errors S A to S D into the error memory section 101 at locations which respectively correspond to the picture element positions A to D. With this apparatus, due to the fact that level values varying in amplitude and polarity in a manner which is independent of the source image are added to the density levels of respective picture elements of the source image, a texture pattern which is produced in the processed output image when using prior art error diffusion method in the case of a source image containing regions of highly uniform density is effectively suppressed. Since computer-generated images frequently contain regions of extremely uniform image density, this embodiment of the invention provides a practical apparatus for display of computer-generated images by a bi-level display device. In each of the apparatus described above, it is necessary to conscutively execute three basic operations within each picture element processing period (i.e. within each period of the x-direction sync signal). These operations are: (1) Read out the stored accumulated error S xy for the object picture element, and apply this to compensate the input level value I xy for the object picture element, to produce a corrected level value I xy '. (2) Compare this corrected level value with a threshold level, to determine a bi-level output value P xy for the object picture element, and subtract that output value from the corrected level value I xy ' to obtain a bi-level error value E xy for the object picture element. (3) Utilize this error value E xy to derive respective values of accumulated error for the set of peripherally adjacent picture elements to the object picture element (A, B, C and D). The above three basic operations must be performed consecutively, since a result obtained in each of the basic operations (1) and (2) is required for the succeeding operation. The total time required to successively execute all of these basic operations during each picture element processing period determines the speed at which image processing can be performed by such an apparatus. Fig. 12 is a general block diagram showing the essential elements of an embodiment of an image signal processing apparatus according to the present invention, which has the objective of providing a high speed of image processing by eliminating the necessity to consecutively execute all of the above basic operations for each picture element during a single processing period. In Fig. 12, components 101 to 103, 106 and 931 respectively correspond to the identically numbered components in Fig. 9 above. Numeral 1000 denotes an input computation section, numeral 1100 denotes a difference computation section, numeral 1200 denotes a bi-level conversion section, numeral 920 denotes an error apportionment and updating section, and numeral 910 denotes an apportionment factor generating section. In the input computation section 1000, during the processing period in which the object picture element having coordinates (x, y) is being processed to obtain a corresponding output bi-level value P xy , an input level value I x+2,y for the picture element having coordinates (x+2,y), i.e. corresponding to picture element position A' of the error memory section 101, is applied from input terminal 104 to be added to the corresponding accumulated error S x+2,y which is read out from the error memory section 101, in an adder 1001. These operations are synchronized by an x-direction sync signal 931a applied to terminal 931. A corrected level value I' x+2,y corresponding to the picture element position A' (i.e. the picture element position to be processed after position A) is thereby derived during one processing interval, and is temporarily stored in a register 1002 to be read out during the next processing interval. During the processing interval in which level value I' x+2,y is derived as described above, a level value I , x+1,y (i.e. corresponding to the picture element position A of the error memory section 101) which was temporarily stored in the register 1002 during the immediately preceding picture element processing period, is read out from the input computation section 1000 to be temporarily stored in a register 1102 of the difference computation section 1100 and at the same time is applied to one input of a subtractor 1101 of the difference computation section 1100. A level value R (i.e. one of the two possible values R or 0 of the bi-level output signal produced by the apparatus) is applied to the other input of subtractor 1101, and the resultant subtraction value is temporarily stored in a register 1103 of the difference computation section 1100. As a result, the registers 1102 and 1103 now respectively contain values representing the level value I' x+1,y having each of the two possible values 0 and R of the bi-level output signal subtracted therefrom. These respective register contents are designated as error difference levels D 1 and D 2 . During the processing interval in which the input level I x+2,y is derived as described above, the error difference levels D 1 and D 2 corresponding to the object picture element (which had been stored during the preceding processing interval) are read out from registers 1102 and 1104 respectively. Also during this processing interval, a bi-level error E xy which was stored in a register 1204 during the preceding processing period (as described hereinafter) is read out from register 1204, and is utilized by the error apportionment and updating section 920 to generate a set of error apportionment values corresponding to picture element positions A, B, C and D in a similar manner to that described for previous apparatus, e.g. as shown in Fig. 8. An error apportionment value 921a corresponding to the picture element position A is thereby produced from the error apportionment and updating section 920 and is added to each of the difference levels D 1 and D 2 to thereby obtain respective errors E 1 and E 2 respectively. The error E 1 is compared in a comparator 26 with a predetermined threshold value to thereby derive a bi-level value P xy for the object picture element, which is produced from output terminal 106. At the same time, either error E 1 or E 2 is selected by the selector 1203, in accordance with the level of the bi-level value P xy which has been determined (i.e. R or 0) and the selected error is temporarily stored as an updated value of bi-level error in a register 1204, to be used in the succeeding processing period. The apportionment factor generating section 910 contains a plurality of sets of apportionment factors, and periodically selects (i.e. once in each picture element processing period) a set of apportionment factors from these. The selected apportionment factors K A , K B , K C and K D are supplied to the error apportionment and updating section 920 as in the previously described embodiments. The apportionment factor generating section 910 operates in synchronism with the x-direction sync signal 931a, applied from input terminal 931. The error apportionment and updating section 920 utilizes the apportionment factors K A to K D for apportioning the bi-level error E xy among the picture element positions A to D respectively within the peripheral picture element region 102 of the error memory section 101, and operates in synchronism with the sync signal 931a to generate updated values of accumulated error for the picture element positions A to D and store these at corresponding memory locations. The error apportionment and updating section 920 reads out accumulated errors S C ' and S D ' (which have been obtained in the preceding processing period) and derives new accumulated errors S A to S D by using the following equations (15): Updating processing is then executed by the error apportionment and updating section 920, by writing the new values of the accumulated errors S A to S D into the error memory section 101 at locations which respectively correspond to the picture element positions A to D. Fig. 13 illustrates the configuration of the error apportionment and updating section 920 of this embodiment, for executing the computations set out in equations (15) above. As shown, a set of multipliers 1206 to 1209 serve to generate the error apportionment values K A x E xy to K D x E xy respectively, with the error apportionment value K A x E xy being supplied as value 921a to the adders 1201 and 1202 in Fig. 12, to produce the error values E 1 and E 2 described above. It can be understood from the above that with the embodiment of the present invention, all of the aforementioned basic operations (1), (2) and (3) are performed concurrently for three different picture elements, within a single processing interval, rather than consecutively as in the case of the preceding apparatus. That is to say, the difference computation section 1100 computes the two possible values for difference level D 1 and D 2 for a picture element position (x,y) during the processing period immediately previous to that in which the bi-level output value for that picture element is derived by the bi-level conversion section 1200. In addition, the input computation section 1000 computes the corrected input level I xy ' for the picture element position (x,y) during the processing period immediately preceding that in which these difference levels D 1 and D 2 are derived. These difference levels are then each added to the appropriate error apportionment value, to derive values which can be considered as respective provisional values of bi-level error for the object picture element, and the apparatus functions by selecting one of these two provisional values on the basis of the bi-level value determined for the object picture element. Due to the concurrent form of processing executed by this invention, a substantially higher processing speed can be attained than is possible with the preceding apparatus.

Claims: An image signal processing apparatus for sequentially processing input level values which are supplied to an input terminal (104) in successive processing periods and which represent respective density levels of a rectangular array of picture elements representing an image, to produce corresponding bi-level values, said apparatus comprising: error memory means (101) for storing a bi-level error of an object picture element in a set of memory locations respectively corresponding to said object picture element and to a set of adjacent picture elements (A, A', B', B, C, D) which have not yet been processed and which extend peripherally from the object picture element in said rectangular array; input correction means (1000) including means (1001) for adding an input level value (I X+2,Y ), which is received at said input terminal two processing periods prior to a processing period in which said input level of said object picture element is received and corresponds to a first one (A') of said set of peripherally adjacent picture elements, to an accumulated error which is stored at a location in said error memory means corresponding to said first adjacent picture element, to thereby derive a first corrected input level value (I' X+2,y ) value, and first register means (1002) for holding and outputting said corrected input level value after one processing period; difference computing means (1100) coupled to said first register means (1002) to receive a second corrected input level value (I' x+1,y ) corresponding to a second one (A) of said set of adjacent picture elements, and including means for obtaining a first difference level value as said difference between a first possible value of said bi-level output values and said second corrected input level value, and a second difference level value as said difference between a second possible value of said bi-level output values and said second corrected input level, and second and third register means (1102, 1103) for respectively holding said first and second difference level values and outputting said first and second difference level values after one processing period; bi-level conversion means (1200) coupled to receive said first and second difference level values (D 1 , D 2 ) produced from said register means of said difference computing means, and including means (1201, 1202) for adding to each of said first and second difference level values a first error apportionment value (921a), to obtain a first error value (E 1 ) and second error value (E 2 ) respectively, comparator means (26) for comparing said first error value (E 1 ) with a predetermined threshold value to thereby obtain a bi-level value (P xy ) for said object picture element, selector means (1203) for selecting one of said first and second error values in accordance with said state of said bi-level value for said object picture element, to be outputted as a bi-level error (E xy ) for said object picture element, and fourth register means (1204) for holding and outputting said bi-level error (E xy ) after one processing period; apportionment factor generating means (910) for generating a set of apportionment factors for use in apportioning said bi-level error (E xy ) of said object picture element among elements which have not yet been processed; and error apportionment and updating means (920) for computing respective error apportionment values (K A ,...K B ) including said first error apportionment value and respectively corresponding to a set of picture elements (A, B, C, D) which are immediately peripherally adjacent to said object picture element and have not yet been processed, based on said bi-level error (P XY ) read out from said bi-level error register and said set of apportionment factors, adding said error apportionment values to respective values of accumulated error which are stored at locations in said error memory means respectively corresponding to said set of immediately peripherally adjacent picture elements, and storing said respective addition results in said error memory means as updated accumulated error values.

Inventors: KUROSAWA TOSHIHARU, MARUYAMA YUJI, NAKAZATO KATSUO, TAKAHASHI KIYOSHI, TSUCHIYA HIROYOSHI, KUROSAWA, TOSHIHARU, MARUYAMA, YUJI, NAKAZATO, KATSUO, TAKAHASHI, KIYOSHI, TSUCHIYA, HIROYOSHI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1987
Main classification: H04N1
IPC codes: H04N1