BURST LOCKED OSCILLATOR WITH SIDE-LOCK PROTECTION

Abstract: A burst locked phase locked loop (PLL) includes a relatively wide-band voltage controlled oscillator (18). This PLL may erroneously lock at a frequency which differs from the frequency of burst by an amount equal to the horizontal line frequency. To prevent this side-locking condition, the PLL includes circuitry (22-32) which changes the frequency of the signal produced by the VCO when it detects a side-lock condition e.g. when the number of cycles of the signal provided by the PLL during one horizontal line interval corresponds to the number which would be obtained in a side-lock condition.

Description: This invention relates to a phase-locked loop system which generates a signal that is locked in frequency and phase to the color synchronizing burst signal component of a composite video signal and which is prevented from locking at an erroneous frequency. Color television signals under the PAL and NTSC signal standards include color information signals which are phase modulated onto a suppressed color subcarrier signal having a frequency within the band of frequencies occupied by the baseband luminance signals. In a conventional PAL or NTSC television receiver, the modulated subcarrier signal is separated from the luminance signals and then synchronously demodulated to recover the color information signals. As a step in the synchronous demodulation process, it is desirable to regenerate the suppressed color subcarrier signal. This is generally done by a phase-locked-loop (PLL) which generates a continuous oscillatory signal that is locked in frequency and phase to the color synchronizing burst signal component of the composite video signal. The burst signal component includes eight to ten cycles of a signal having the same frequency as the suppressed subcarrier signal. This burst signal occupies a small portion, the burst interval, of each horizontal line of the video signal. One potential problem which exists in these PLL systems is side-locking. Side-locking occurs when the PLL erroneously locks at a frequency which differs from the frequency, f c , of the color subcarrier signal by an amount equal to the frequency, f H , of the horizontal line scanning signal. Side-locking occurs because the PLL uses only a relatively small portion of each horizontal line to regenerate the subcarrier signal. One method of guarding against side-lock conditions is to use a resonant crystal oscillator in the PLL. Using this type of oscillator, the range of frequencies which may be produced by the PLL is restricted to exclude any of the side-locked frequencies. This method is undesirable, however, since the resonant crystal is relatively expensive and since resonant crystal oscillators generally need to be trimmed manually, a relatively expensive step in the assembly of a consumer television receiver or video tape recorder. One method which does not require a resonant crystal and which does not need a manual trimming operation is set forth in U.S. Patent US-A-4,255,759. In this system, coarse frequency control circuitry is used to hold the signal produced by automatic phase control circuitry (a PLL) within a range that excludes the side-lock frequencies. This system is in effect a double PLL. An inner PLL, the automatic phase control circuitry, locks to the color reference burst signal component of the composite video signal while an outer PLL, the coarse frequency control circuitry, locks to the horizontal line synchronization signal components of the composite video signal. This system depends on the ratio of f c to f H remaining constant. In the NTSC system, for example, the color subcarrier signal is the 455th harmonic of one-half of the line scanning frequency (i.e. f c = 227.5 f H ). For broadcast and other "standard" signals this ratio holds. However, for signals produced by "nonstandard" sources such as video tape recorders, video disc players and home computers the ratio of f c to f H may vary over a range of values centered about the nominal value. Only a relatively small portion of this range of values corresponds to undesirable side-lock conditions. The system set forth in the referenced patent may not perform well when these nonstandard sources are used because the combined effect of the two loops may change the frequency of the regenerated subcarrier signal when no change is desired. GB-A-1272447 discloses a burst-responsive oscillator synchronizing system in which burst synchronization of the oscillator (achieved via an injection locking technique) is supplemented with an additional control system comprising a frequency control loop including a phase error detector responsive to a horizontal line synchronizing signal and to a frequency divided version of the oscillator output. The supplemental control loop forces the oscillator frequency to be a selected multiple of the line frequency. Aspects of the invention are specified in the claims. The present invention is embodied in circuitry which includes a wide-band phase-locked loop that is synchronized to the color synchronizing burst signal component of a composite video signal. The signal produced by this phase-locked loop is applied to circuitry which is responsive to the horizontal line synchronizing signal component of the composite video signal for detecting a side-lock condition. When a potential side-lock condition is detected, this circuitry applies a signal to the phase-locked loop to correct the side-lock condition. When no potential side-lock condition is detected, this circuitry has no effect on the operation of the phase locked loop. The sole figure of the drawing is a block diagram, partially in schematic diagram form, of a phase locked loop system embodying the present invention. In the drawing, broad arrows represent busses for conveying multiple-bit parallel digital signals and line arrows represent connections for conveying analog signals or single-bit digital signals. Depending on the processing speed of the devices, compensating delays may be required in certain of the signal paths. One skilled in the art of designing phase locked loop systems would know where such delays would be needed in a particular system. In the PLL system shown in the figure, a source of color burst signal 10, which may, for example, include the tuner, IF amplifier, video detector, and burst gate circuitry of a conventional television receiver provides separated color burst signals to one input terminal of a phase detector 12. The phase detector 12, which may be of conventional design, compares the color burst signal to an oscillatory signal, FC, produced by a frequency divider 20. The signal FC has substantially the same frequency as the color burst signal. The output signals provided by the phase detector 12 are proportional to the difference in phase between the burst signal and the signal provided by the frequency divider 20. The output signal of the phase detector 12 is applied to a low-pass filter, the system loop filter of the PLL, which includes a resistor 14 and a capacitor 16. This low-pass filter integrates the phase error signal over several horizontal line intervals to develop a frequency control signal which is applied to the input terminal of a voltage controlled oscillator (VCO) 18. The VCO 18 may be, for example, a relatively inexpensive, wide-band circuit which includes a resistor-capacitor (RC) resonant circuit. The free-running frequency of this VCO is approximately 4f c , four times the frequency f c of the color subcarrier signal. The output signal provided by the VCO 18 is a signal, CK, which may be used in a television receiver as shown, for example, in the referenced U.S. Patent No. 4,255,759. The signal CK is applied to the frequency divider 20 which divides its frequency, by four to produce the signal FC that is applied at the phase detector 12. The circuit described above is a conventional burst-locked PLL. However, as set forth above, because this PLL uses a relatively wide-band VCO, it may be susceptible to side-locking. Side-locking occurs when the frequency of the signal FC differs from f c by an amount substantially equal to f H or a multiple of f H . Since the burst signal is applied to the phase detector 12 only during the burst interval of each horizontal line, the output signal provided by the phase detector 12 exhibits local minima when the frequency of FC is substantially equal to f c -f H , f c , and f c +f H . These three frequencies represent stable operating points for the PLL. To prevent the PLL from stabilizing at one of the side-lock frequencies f c -f H or f c +f H , the remainder of the circuitry in the figure detects a side-lock condition, and upon detection, destabilizes the PLL in a sense which causes the PLL to re-lock at a frequency substantially equal to f c . The 4f c signal CK provided by the VCO 18 is one of the input signals to the detecting circuitry. This signal is applied to the input terminal of a ten-bit counter 22. A horizontal synchronization signal, HS, provided by a source of horizontal sync signals 28 is applied to a second input terminal of the detecting circuitry. The signal HS is applied, via the delay element 26, to the reset input terminal of the counter 22. The counter 22 increments its value for each pulse of the signal CK. When standard signals are received and the PLL is not side-locked, the value produced by the counter 22 is reset to zero by a pulse of the signal HS, increments to 909, and is then reset to zero by the next subsequent pulse of the signal HS. The ten-bit output value produced by the counter 22 is applied to a latch 24 which is controlled by the undelayed signal HS to load the counter value during each horizontal line interval. The delay element 26 provides a delay that is a fraction of a period of the signal CK. Consequently, the value loaded into the latch 24 is substantially equal to the value produced by the counter 22 immediately before it is reset. The value stored into latch 24 is applied to the address input port of a read only memory (ROM) 30. The ROM 30 is programmed to produce output signals SC, SE and, in an alternative embodiment, an output signal SI, responsive to different values applied to its address input port. The following Table I illustrates the values of the signals SC and SE that are produced responsive to the different values of the count value signal CV. In the table, a value of 'x' indicates a "don't care" state. The signals SC and SE are applied to the signal input terminal and control input terminal, respectively, of a three-state gate 32. The gate 32 provides an output signal which is applied, through a resistor 34, to the interconnection of the resistor 14 and capacitor 16. The signal SE is an error signal, indicating that the PLL may be in a side-lock condition. The signal SC indicates the type of side-lock, either greater than or less than the desired frequency. When the signal SE is a logic zero, the three-state gate 32 is enabled to apply a signal to the resistor 34 which is substantially equal to the signal SC. However, when the signal SE is a logic one, the three-state gate 32 exhibits a high impedance at its output terminal effectively removing the side-lock protection circuit from the PLL. In this embodiment of the invention, the signal SE conditions the gate 32 to exhibit a high impedance state for count values ranging from 906 to 912. Count values in this range correspond to variations in the ratio of f c to f H which do not correspond to a side-lock condition. These variations may occur, for example, when the video signals applied to the PLL system are from a VTR, video disc player or home computer. Count values less than or equal to 905 may indicate that the PLL has locked at a frequency f c -f H . In this instance, the ROM 30, via the signals SC and SE, conditions the gate 32 to apply a logic one to the resistor 34 to cause the VCO 18 to increase the frequency of its output signal. The amount by which the frequency is increased is sufficient to destabilize the PLL and cause it to relock at a frequency of f c . Conversely, count values greater than or equal to 913 may indicate that the PLL has locked at a frequency f c +f H . In this instance, the signals provided by the ROM 30 condition the gate 32 to apply a logic zero value to the resistor 34. This causes the VCO 18 to decrease the frequency of its output signal by an amount sufficient to condition the PLL to lock at f c . The flip-flop 36, shown in phantom, is included in an alternative embodiment of the invention to compensate for errors in the input video signal which may, for example, cause one horizontal sync pulse to be missing, or which may result in a sudden phase shift in the horizontal synchronization signal without any change in the ratio of f c to f H . The first of these errors may be caused by a defect in the tape of a VTR which prevents one pulse of the horizontal synchronization signal from being recorded. The second error may occur during head switching in a multiple-head VTR when the video signal is obtained from at least two of the heads. Each of these errors results in a change in the ratio of f c to f H during one horizontal line interval which does not occur during subsequent line intervals. The flip-flop 36 is included in the PLL system to ignore single errors of this type. The flip-flop 36 may be, for example, a conventional set-reset flip-flop. In the illustrative embodiment, the flip-flop 36 is of the type wherein the set input takes precedence if a value of logic one is applied to both the set and reset input terminals. A signal, SI, provided by the ROM 30 is applied to the set input terminal, S, of the flip-flop 36 and the signal SE is applied to the reset input terminal, R. the output terminal Q is coupled to the address input port of the ROM 30 as, for example, the least significant bit of the address value. Table 2 illustrates the operation of the ROM 30 and flip-flop 36. Since the output signal, Q, of the flip-flop 36 is changed by the ROM 30 and since the signal Q is an address input signal to the ROM 30, separate from the signal CV, it is listed both as an input (Q i ) and an output (Q i+1 ) in the Table II. As illustrated by Table II, if the flip-flop 36 is reset when a possible side-lock condition is detected, the flip-flop 36 is set but the signals SC and SE are not changed. A side-lock indication during the next successive line interval activates the side-lock protection circuitry to correct the condition. However, if the flip-flop 36 is set during one horizontal line interval and the output of the ROM 30 during the next horizontal line interval does not indicate a possible side-lock condition the flip-flop 36 is reset.

Claims: A phase locked loop system for use in a system for processing television signals which include a colour synchronising burst signal component and a horizontal line synchronising signal component, the phase locked loop system comprising: a source (10) of said colour synchronising burst signal; phase locked loop circuitry (12-20), coupled to said source, for providing an oscillatory signal (CK) that is substantially locked in phase to said colour synchronising burst signal, said phase locked loop circuitry being susceptible to undesirable side-lock conditions; characterised by counting means (22), responsive to said oscillatory signal and to said horizontal line synchronising signal component, for counting the number of periods of said oscillatory signal occurring in each period of said horizontal line synchronising signal; error signal generating means (30), responsive to the output of said counting means, for generating an error signal (SE) which is in a first state when the output of said counting means has a value outside of a predetermined range of values, and which is in a second state otherwise; correcting means (32), coupled to said error signal generating means and responsive to said error signal being in said first state, for changing the frequency of the signal produced by said phase locked loop in a sense to return said counting means output value to said predetermined range of values, said correcting means having substantially no effect on the frequency of the signal produced by said phase locked loop circuitry when said error signal is in said second state. The phase locked loop system set forth in claim 1 wherein: said phase locked loop circuitry is susceptible to first and second side-lock conditions for which the frequency of said oscillatory signal is respectively greater than and less than a desired range of frequencies; and further characterised in that: said system further includes circuitry, responsive to the output of said counting means, for providing an error type signal (SC) which is in first and second states when said counting means output value indicates that the frequency of said oscillatory signal is greater than and less than said desired range, respectively; and said correcting means is responsive to said error signal and to said error type signal for generating a correction potential for application to said phase locked loop circuitry, said correction potential having a first polarity with respect to a reference value when said error signal is in its first state and said error type signal is in its first state, having a second polarity with respect to a reference value when said error signal is in its first state and said error type signal is in its second state, and having a null value when said error signal is in its second state. The phase locked loop system set forth in claim 2 wherein: said phase locked loop circuitry includes: phase detecting means (12), responsive to said oscillatory signal and to the colour synchronising burst signal provided by said source, for generating a phase difference signal that is proportional to the instantaneous difference in phase therebetween; integrating means (14,16), coupled to said phase detecting means for integrating the phase difference signal to produce a frequency control signal; and a variable oscillator (18) coupled to said integrating means for producing said oscillatory signal, the frequency of said oscillatory signal being determined by said frequency control signal; and further characterised in that: said correcting means includes means for applying said correction potential to said integrating means. The phase locked loop system set forth in claim 2 or 3 wherein said correcting means further includes means (36) permitting a departure of said correction potential from said null value only after values provided by said counting means are outside of said predetermined range of values for two successive periods of said horizontal line synchronising signal.

Inventors: DISCHERT, ROBERT ADAMS
Applicants: RCA THOMSON LICENSING CORPORATION
Application year: 1987
Main classification: H04N9
IPC codes: H03L7, H04N9