Arithmetic coding encoding and decoding method

Abstract: Apparatus and method for compressing and de-compressing binary decision data by arithmetic coding and decoding wherein the estimated probability Qe of the less probable of the two decision events, or outcomes, adapts as decisions are successively encoded. To facilitate coding computations, an augend value A for the current number line interval is held to approximate one by renormalizing A whenever it becomes less than a prescribed minimum AMIN. When A is renormalized, the value of Qe is up-dated. The renormalization of A and up-dating of Qe are preferably based on a single-bit test. Also, each Qe value is preferably specified as a 12-bit value having the least significant bit set to 1 and having no more than four other bits set to 1. The number of Qe values in the 1/4 to 1/2 probability range is enhanced to improve coding efficiency. A decision coding parameter of preferably six bits indicates the sense of the more probable symbol (MPS) in one bit and identifies a corresponding Qe value with the remaining five bits. In addition to probability adaptation, the present invention discloses an allocation of bits in a code stream register in which preferably two spacer bits are inserted between a next byte portion (which contains a byte of data en route to a buffer) and a fractional portion which may be involved in further computation. With the two spacer bits, any code greater than or equal to Hex 'C0' which follows a Hex 'FF' byte is illegal for data and therefore provides for an escape from the code stream. The two spacer bits also reduce the number of stuff bits inserted to account for carry or borrow propagation. Encoding and decoding can be performed interchangeably by hardware or software which feature differing coding conventions.

Description: BACKGROUND OF THE INVENTION I. Field of the Invention The present invention relates to compressing incoming data by arithmetic coding encoding and retrieving the original data by arithmetic coding decoding. II. Description of the Problem In order to achieve a desired rate of data transfer or to store data in a limited memory space, it is often necessary or desirable to compress data into fewer bits. Some time after the data is compressed, the original data is to be retrieved --the latter step being referred to as de-compressing the data. One application of data compression/de-compression involves optical imaging. In optical imaging, there are typically numerous pieces of information --such as darkness or shade of picture elements (pels)-- which must be transferred at high rates or which must be stored for future use. Arithmetic coding is one technique for achieving data compression and de-compression. In arithmetic coding, one decision after another is encoded to define successively smaller, lesser-included intervals along a number line. Arithmetic coding is described in various articles written by the present inventors: "An Introduction to Arithmetic Coding", by G.G. Langdon, Jr. IBM Journal of Research and Development,; vol. 28, n. 2, March 1984, 135-149; and "Arithmetic Compression Code Control Parameters Approximation" (by D.R. Helman, G.G. Langdon, Jr., and J.J. Rissanen), in IBM Technical Disclosure Bulletin, volume 23, No. 11, April 1981, pp. 5112-5114. The cited references are incorporated herein by reference to provide background. As noted in the above articles, arithmetic coding provides that each decision has a plurality of possible exclusive outcomes (or events). Each outcome or event is represented in data by a symbol. In the optical imaging environment, for example, each decision may correspond to whether or not a given pel is black --the decision outcome being represented by a Y (or YES) symbol if the pel is black or an N (or NO) symbol if the pel is not black. A plurality of decisions may then be represented by a sequence of symbols, e.g. YNYYN ... In accordance with prior arithmetic coding teachings, a probability line has a current interval defined therealong. The first current interval is 0 to 1. The current interval is divided into segments in which each segment corresponds to one possible outcome for the next decision. Where there are only two possible outcomes for each decision, the current interval is divided into two segments. The length of each segment is based on its respective associated probability. The respective probabilities may remain fixed or may adapt as decision data is entered. It is the correlating of larger segments to symbols which occur with greater frequency which leads to the compression effect. In the former cited article ("An Introduction to Arithmetic Encoding"), a 4-symbol arithmetic coding example is set forth in which each decision can result in an "a" event (having a 50% probability), a "b" event (having a 25% probability), a "c" event (having a 12.5% probability), or a "d" event (having a 12.5% probability). Representing the four events in binary form would require two bits for each decision where the events would be represented respectively by 00, 01, 10, and 11. For three decisions, such as aab which is highly likely, the straightforward uncoded data would be 00 00 01; requiring six bits. However, as observed in the article at page 137, the arithmetic coding approach permits the sequence aab to be represented by the value .001. Instead of six bits, the information can be represented in three bits. This conservation of bits results as successive events having relatively high associated probabilities occur. The conservation deteriorates if numerous events occur for which there are low probabilities and relatively short line segments. With the above-noted probabilities, a sequence of events dd would be represented with uncoded data as 11 11 whereas, by arithmetic coding, the dd events would be represented by 111111. Provided that the larger segments in fact correspond to events which occur with correspondingly greater frequency, the additional bits needed for less probable symbols are outweighed by the conservation achieved when more probable symbols occur. Hence, it is important to ensure that the associated probability (and segment length corresponding thereto) reasonably track the actual probabilities of the respective events. Various techniques have been proposed for estimating event probabilities as more decision data history is gathered. In an article entitled "Method for Converting Counts to Coding Parameters" (by G.G. Langdon, Jr. and J.J. Rissanen), IBM Technical Disclosure Bulletin in volume 22, No. 7, December 1979, pp. 2880-2882, counters are used to detect changes in the symbol probabilities from observed symbol occurrences, and to modify the probability q of a less probable symbol (LPS). In particular, q is changed to reflect the number of counts of one symbol divided by the total number of symbols counted during a symbol string. That is, if k is the counts for one symbol and n is the number of counts for both symbols, symbol probability is changed based on k/n. Another article by Langdon and Rissanen, "Compression of Black-White Images with Arithmetic Coding", IEEE Transactions on Communications, volume COM-29, No. 6, pp. 858-867, June 1981, also discusses adapting probabilities in an arithmetic coding environment. In discussing adaptation to nonstationary statistics, the IEEE article proceeds on page 865 as follows: "Suppose that we have received r [consecutive] 0's at state z, and our current estimate of the probability of [symbol] s(i) being 0 is p=c0/c [where c0 is a count defined as c(0|z,s(0)...s(t)) and c is a count defined as c(z,s(0)...s(t)) . We receive the symbol s(i). If s(i) is 0, we test: Is p′(r+1)≧0.2? If yes, we regard the observation as being ... consistent with our estimate of p, and we update c0 and c by 1 to form a new estimate. ... If, however, p′(r+1)<0.2, the observation is likely an indication of changed statistics, and we ought to be prepared to change our estimates to a larger value of p. We do this by halving the counts c0 and c before updating them by 1. If the received symbol s(i) is 1, we do the same confidence test using the probability p(r).... In reality, for the sake of easier implementation, we put suitable upper and lower bounds on the count of the less probable symbol for each skew value Q (s) to indicate when to halve or not the counts." In describing the Q(s) value, it is noted that the IEEE article discusses the approximating of the less probable symbol probability to the nearest value of 2 -Q(s) where Q(s) is an integer referred to as the "skew number". A particular approach to probability adaptation is included in a co-pending European patent application EP-A-0 224 753 entitled "Probability Adaptation for Arithmetic Coders", invented by W.B. Pennebaker and J.L. Mitchell, priority December 4, 1985 which is incorporated herein by reference. This document represents state of the art according to Article 54(3). According to this patent application the probability symbol is readjusted from time to time. For this purpose the occurrences k of the one probability symbol LBS and all n probability events are counted. The values of LBS are set to new values when n exceeds a selected maximum n max and k exceeds threshold values k min and k max . Another probability estimator is also set forth in EP-A-0 154 860 of F. Goertzel and J.L. Mitchell entitled "Model driven adaptive Data Compression/Decompression System for Data Transfer". A general novel approach to adapting a probability estimator is set forth in a co-pending European application EP-A-0260 460 of W.B. Pennebaker and J.L. Mitchell with the same priority date as this application and entitled "Probability Estimation based on Decision History" which is incorporated herein by reference to the extent required to set forth the environment of the present invention. In the co-pending application, a plurality of possible probability values Q e for an event are prescribed --as in a table. Based on the invention disclosed in the co-pending application, an augend value A is defined and, with each decision, the augend value is reduced. The amount by which the augend value is reduced is event dependent. That is, in a binary application in which each decision may result in a less probable symbol (LPS) having a current estimated probability Qe being entered or a more probable symbol (MPS) being entered, the entering of an LPS results in the augend value being reduced to the current Qe value; whereas the entering of an MPS results in the augend value A being computed as A-Qe. If the up-dated value of A is less than a pre-defined minimum AMIN (which is greater than highest value of Qe), the up-dated value is renormalized (preferably by doubling) until A again is at least AMIN. A fundamental concept of the invention in the co-pending application is that the value of Qe is up-dated each time A is renormalized. If renormalization follows an LPS event, the Qe value (representing the estimated probability of the LPS event) is increased. If renormalization follows an MPS event, the Qe value diminishes. By linking Qe changes to augend value renormalization, the time for Qe change is readily determined without the need for counters and, contrary to prior techniques, provides close tracking of actual Qe probability over the range of Qe values. In addition, the novel approach in the co-pending application has recognized that, at certain values of Qe, the up-dating procedure could be trapped at certain "bad" values. By way of example, values which --when doubled one or more times-- are equal or nearly equal to AMIN can result in the following troublesome sequence. A is set equal to Qe(bad) after an LPS event; the up-dated A is doubled (and redoubled as required) until A is no longer less than AMIN and a higher Qe value is selected; because the up-dated A is equal or nearly equal to AMIN, a single MPS event results in A falling below AMIN thereby requiring a renormalization and a reduction in the Qe value to Qe(bad); if the LPS probability is actually much greater than the estimated Qe value, an LPS event may likely occur again thereby returning Qe to the higher value; again a single MPS event will cause a renormalization and a movement of the Qe value back to the Qe(bad) value; and so on. According to the teachings of the co-pending application, the "trapping" problem is addressed by disallowing the "bad" values, however, certain values which are "bad" from a "trapping" standpoint are good values from an overall efficiency standpoint. In addition to adapting probabilities based on an up-dated decision history, the implementation of arithmetic coding involves other problematic issues --such as "carry propagation" and "borrow propagation". The "carry propagation" problem is noted with reference to a first type of arithmetic coding encoder which up-dates a code stream C with successive decision inputs in accordance with the following conventions: (1) if the symbol being encoded is an LPS, C remains the same in value and the current interval becomes A(new)=Qe, and (2) if the symbol being encoded is an MPS, C is up-dated to C+Qe and the current interval becomes A(new)=A(previous)-Qe. As the interval A becomes smaller and such smaller intervals are added to C, the precision of C (i.e., the length of the code stream) increases. The precision may extend without any fixed limit as long as decision data is entered for encoding. Because C can be of indeterminate length (and precision) but only limited memory is available for containing code stream information, there may be a problem if a carry occurs. In particular, if the code stream value is a sequence of several hundred l's but only the most recent bits of C are contained in a shift register, a problem results if some A is to be added to C. The carry will not be able to propagate through the several hundred 1 bits because only the most recent bits are accessible. One solution to carry propagation is referred to as bit-stuffing and has been outlined in the literature. The bit-stuffing of the prior technology suggests the insertion of at least one carry-receiving bit after a prescribed number of 1 bits in a row. In an arithmetic coding encoder set forth in a co-pending European patent application EP-A-0 260 462 filed on even date herewith, entitled "Arithmetic Coding for Data Compression/De-compression By Selectively Employed, Diverse Arithmetic Coding Encoders and Decoders," invented by J.L. Mitchell and W.B. Pennebaker, an "optimum" software encoder is described in which the code point remains fixed in value or decrements with each encoded decision. Accordingly, when the code stream C s includes a string of 0 bits and a subtraction is required, a borrow may propagate beyond the length of a shift register which contains the most recent portion of the code stream. Such "borrow propagation" is accounted for in the above-identified co-pending application by converting some or all Hex '00' bytes in the encoded code stream to Hex 'FF' with a carry bit. In this way, the borrow propagation becomes a carry propagation situation. Accounting for carry and borrow without sacrificing coding efficiency and requiring numerous additional bits is a desired end. As a further aspect of arithmetic encoding, it is desirable to enter control words in the code stream. That is, it is desirable to enable an external controller to break into the code stream and insert a control word. At the decoder end, another controller should be able to detect and strip the control word from the received string of data. With regard to control word insertion, it is desirable to (a) provide for a large number of possible control words and (b) identify the presence of a control word without substantially reducing coding efficiency. In the aforementioned EP-A-0 260 462 relating to arithmetic coding data compression/de-compression, a thirty-two bit register is provided for containing portions of the code stream en route to a buffer. The least significant twelve bits (0 through 11) represents a "fractional" portion of the code stream which is aligned with the current value of A. Bit 12 corresponds to a spacer bit. Bits 13 through 20 represent an 8-bit byte of code stream data that is next to be shipped to the buffer. Bit 21 is a carry receiver bit. Of the two bits which precede bit 21, bit 22 is used for identifying whether a control word is inserted. Bits 31 through 24 provide a flag bit which shifts left as data bits enter at bit 0. (After eight shifts, the flag bit is at a bit position which indicates that a byte of data is ready to be shipped to the buffer.) With the single spacer bit, two stuffed bits may be required under certain conditions. SUMMARY OF THE INVENTION In accordance with the present invention, an arithmetic coding encoder and decoder features probability adaptation as set forth in the aforementioned co-pending patent application EP-A-0 260 460 "Probability Estimation Based on Decision History", especially where the probability adaptation is enhanced by selecting possible Qe values which improve encoder and decoder performance. In this regard, it is noted that the present invention relates to a binary arithmetic coder which has a probability estimator integrated into the arithmetic coding process. That is, the augend value in the present invention corresponds to the current interval along the number line and the value of Qe is up-dated in response to a renormalization of A, i.e. the value of the current interval. In determining when the augend value (i.e., current interval value) A has fallen below a minimum AMIN and hence an up-date of Qe is required, the present invention represents AMIN by a value which includes a first set bit followed by unset bits. For example, AMIN may be represented by Hex '1000', or 1 0000 0000 0000 (in binary). In this way, renormalization and Qe up-dating are indicated when the leading bit changes to 0 --the renormalization test thus being a single-bit test. The invention thus achieves the object of providing a simple test for determining when Qe should be changed as well as when renormalization is required. It is noted that U.S. Patent 4467317 suggests a one-bit test for augend renormalization; however the integration of probability adaptation and a single-bit test for renormalization results in notable benefits over the earlier teachings. Moreover, the present invention enhances the probability adaptation approach disclosed in the above-cited co-pending patent application in several ways. First, the Qe values are included in a table wherein the table has the following characteristics: 1. each entry in the Qe table has a 6-bit coding parameter in which one bit indicates the sense of the MPS value and 5 bits Q-index which identifies a corresponding Qe value; and 2. for each entry, the Qe value is preferably 12 bits in length with no more than 5 bits of any Qe value being set, the least significant bit of each Qe value always being set (which facilitates hardware implementation). The selection of which bits are set for the various Qe values is, in part, determined to limit the number of gates that must be traversed as one derives a Qe value from the Q-index thereof. The use of a six-bit coding parameter is significant in that it conforms to existing macros and predefined hardware cells. Moreover, if less bits were used for the coding parameter, table granularity would become too coarse and results for stationary statistics would degrade. With more than six bits, additional chip area would be required and expense would increase. By properly selecting Qe values, the number of Qe entries required is held to a relatively low number (e.g., thirty) while achieving coding efficiency and fairly simple implementation. Furthermore, in order to avoid the problem of "trapping" the Qe value, the present invention provides the following enhancement. As in the aforementioned co-pending patent application relating to probability estimation, some "bad" Qe values of the form AMIN/2 n are disallowed. However, for "bad" Qe values which --except for promoting "trapping"-- contribute to performance, the invention permits inclusion in the table. To avoid the "trapping" effect for such retained "bad" values, the invention provides that --in response to an LPS renormalization at a "bad" Qe value-- the Qe value is incremented to a prescribed table value which requires more than one MPS renormalization to return to the bad Qe value. The present invention thus achieves the object of retaining Qe values which would otherwise result in "trapping", by a method according to Claim 1. Furthermore, to facilitate the software implementation of an encoder and decoder according to the present invention, a negative Qe representation indicates when the sense of MPS is 1; a positive Qe representation indicating when MPS=0. In particular, with this approach, a sign bit need not be masked and processing cycles are saved. A further object of the invention is to improve the allocation of bits in a shift register which contains code stream data en route to a buffer memory. In this regard, more than one spacer bit is provided to separate the fractional portion of the code stream from the "byte" to be shipped. By including more than one spacer bit, the possibility of a Hex 'FF' sequence following another Hex 'FF' sequence is obviated. Moreover, with multiple spacer bits, a single stuffed bit can serve to either receive a carry or to provide escape codes for control words. According to one embodiment of the invention, an X shift register containing code stream data initially allocates its bits as follows: X = 0000000f 00000000 ss.xxxxxx xxxxxx00 When a byte is ready to be shipped to the buffer, the X register is configured as follows: X = f ← 0000000c bbbbbbbb ss.xxxxxx xxxxxx00 By using two spacer bits (illustrated as "ss") rather than one, any possible need for more than one stuffed bit is eliminated. Accordingly, the use of two spacer bits enhances coding efficiency by eliminating the possible need for an extra bit to be transmitted. Moreover, the present invention achieves the additional object of providing an efficient escape in which a control word may be inserted, by an external controller, into the code stream before encoding and transmission, and may be withdrawn from the transmitted stream before decoding. The present invention further provides that the first two bits of a code stream are 00. This achieves the object of facilitating decoding. Finally, the present invention features the above objects in an arithmetic coding system in which encoding and/or decoding may be performed interchangeably with either hardware or software which follow differing conventions. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a block diagram showing a general arithmetic coding system including a Q-Coder and Q-Decoder of the present invention. Fig.2 is an illustration of a probability number line with an interval divided into two segments, according to a preferable hardware encoding and decoding embodiment. Fig.3 is an illustration of a probability number line with an interval divided into two segments, according to a preferable software encoding and decoding embodiment. Fig.4 is a diagram illustrating a plurality of diverse encoders any of which which can be used interchangeably with any of a plurality of decoders. Fig.5 is an illustration depicting the allocation of bit positions in a 32-bit code Register (X Register) used in encoding a compressed data stream. Fig.6 is an illustration depicting the allocation of bit positions in a 32-bit Register used in decoding a compressed data stream. Fig.7 is an illustration showing how the up-dating of the probability Qe is integrated with augend renormalization. Fig.8 is a graph depicting coding inefficiency. Fig.9 is an illustration of a gating circuit used in deriving a Qe value output from a q-index which is input. Fig.10 is a table showing a plurality of contexts each having a respective current estimated probability. Fig.11 is an illustration showing how a string of bits are interpreted based on context. Fig.12 is an illustration of a finite state machine representation of a single rate arithmetic coding system. Fig.13 through Fig.49 are flowcharts showing the respective operations of the Q-Coder and Q-Decoder. Fig.50 is a general block diagram showing the major components of a hardware Q-Coder in accordance with the invention. Fig.51 through Fig.53 are illustrations showing elements of the Q-Coder in detail. Fig.54 is a general block diagram showing the major components of a hardware Q-Decoder in accordance with the invention. Fig.55 and Fig.56 are illustrations showing elements of the Q-Decoder in detail. DESCRIPTION OF THE INVENTION I. Generating Identical and Compatible Code Streams with Encoders Having Differing Encoding Conventions Referring to Fig.1, a general apparatus 100 for compressing and de-compressing data is shown including an arithmetic encoder 102 and a corresponding arithmetic decoder 104. In compressing data, the apparatus 100 takes incoming data (DATAIN) which may be expressed as a series of binary decisions BITIN (YN) --wherein each outcome or event has a respective probability-- and characterizes the series by an encoded sequence of bits. By encoding the series of decisions with probability information imbedded therein, the compressed sequence of bits may be transferred more quickly than the original incoming data. Moreover, the compressed data may be stored in less space than the original information being transferred. In applications where large portions of data are to be transferred by some transfer device or medium (e.g., element 105) at high rates or where large portions of data are to be stored in limited memory (or where large portions of data are to be stored and thereafter transferred at a low baud rate), the use of compressed data is of tremendous value. One particular environment in which such compression is of notable value is in the field of video data processing and, more particularly, in teleconferencing. In teleconferencing, vast amounts of information must be rapidly communicated from one location to another to convey picture and other information. After encoded data is transferred to its desired destination, it is de-compressed. That is, the original data or some related representation thereof is retrieved by means of the decoder 104. The decoder 104, in effect, undoes the procedure of the encoder 102 by examining an encoded code stream one byte at a time. In Fig.1, the incoming data DATAIN is initially processed by a model 106. Various types of models are discussed in the prior technology. The model generates a context state S and a binary decision BITIN for the Q-Coder 102 to encode. From past BITIN decisions for the particular context state S, the Q-Coder has already generated an estimate of the probability of the BITIN decision being 1 or 0; that estimate is used in coding BITIN. For example, in facsimile, pieces of incoming data may correspond to whether a given pixel is black or not-black. An estimate of whether a given pixel is expected to be black or white can generally be obtained from the neighboring pixel values which have already been encoded. These neighboring pixel values are used to construct the state S. The Q-Coder and Q-Decoder make estimates of the probability of the given pixel being black or not-black, based on prior pixel values for the same neighborhood pixel values. As successive pieces of data are processed, the relative probabilities between the more probable condition (labelled the "MPS" or non-Qe event) and the less likely condition (labelled the "LPS" or Qe event) may change in value or even switch for any given context state. That is, if the more probable condition is black and numerous instances of not-black occur, the not-black condition may become more probable. The MPS would then change from the black condition to the not-black condition. The Q-coder 102 converts the state S and BITIN information from the model 106 into compressed data by means of arithmetic coding. In the arithmetic coding an estimate of the probability is used that the Q-Coder has already generated and stored in a suitable form following past BITIN decisions for the state S. Fig.2 and Fig.3 each represent an encoding scheme. Fig.2 represents an optional hardware encoder. Fig.3 represents an optional software encoder. In Fig.2, the code point is initially positioned at the "lower" (in value) boundary of a given interval. The Q segment associated with the occurrence of an LPS event is also at the lower end of the interval. The P segment associated with an MPS event is at the upper end of the interval. C(n) corresponds to a code stream value at a time n. A(n) corresponds to the value of the current interval at time n. For each decision, an optimal hardware encoder --illustrated in Fig.2--follows the conventions: When the decision event (illustrated in the figures as YN) is an MPS event-- (a)C(n) ← C(n-1)+Q (b)A(n) ← A(n-1)-Q When the event is an LPS event-- (a)C(n) ← C(n-1) (b)A(n) ← Q In these and the following formulas the sign "←" means that the left term (new values, e.g. C(n), A (n), or in the claims A new , C new ) results from the right term (previous values, e.g. A(n-1), C(n-1), or in the claims A previous , C previous ). Whether there is an MPS event or an LPS event, the hardware spends a processing cycle re-specifying the value of A, the interval (or range). Moreover, when there is an MPS, the code point is incremented (i.e., moved) by the value of Q. Because the hardware can process the up-dating of A and C in parallel, such hardware need expend only one processing cycle for any decision. On the other hand, if the hardware were configured to move the code point on each LPS event, two processing cycles --in determining C ← C + (A-Q)--would be required each time the code point was to be moved. In that limiting the number of processing cycles is critical in hardware operation and in that code point movement on LPS events results in the use of more cycle times, code point movement on MPS events has been found optimal for hardware. The encoding process of Fig.3 represents a preferred "software" scheme with the same ordering of the P and Q segments as in Fig.2. The code point, however, moves downward (i.e., to a lesser value) in response to an LPS event. The code stream is represented by in this scheme. C(n) + A(n) is the same as (n) ; A single decoder can decode C(n) or (n) or to retrieve the same set of input decision events, provided that some portion of the final interval is subtracted from Ci. That is, given a first input to a decoder (see decoder 104 of Fig.1) indicating which condition corresponds to an MPS event and a second input indicating the current value of Q for the piece of the code stream being decoded, the decoder can process C(n) or (n) minus some portion of the final interval to produce a sequence of YN outputs which correspond to the sequence of YN inputs to the encoder 102. The YN decisions enter a model 110 --which matches the model 106-- and provides the original data or a replica thereof as a DATAOUT output. In that the scheme of Fig.3 provides for code point movement on an LPS event, the number of cycles required for software processing is kept low. Referring to Fig.4, four encoders 200 through 206 are shown. Encoders 200 and 204 encode according to the optimal hardware rule that the code point moves on each MPS event, the former being implemented with P/Q symbol ordering and the latter being implemented with Q/P (inverted) symbol ordering. Encoders 202 and 206 encode according to the optimal software rule that the code point moves on each LPS event, the former being implemented with P/Q symbol ordering and the latter being implemented with Q/P (inverted) symbol ordering. The code streams generated by the encoders 200 and 202 can be made the same (or at least compatible) and are represented as C. The code streams generated by the encoders 204 and 206 can be made the same (or at least compatible) and are represented as Z. Z and C can be derived from each other in accordance with the expression: C = A(0) - Z, which calculation is illustrated in inverter 208 with A(0) having a value of one. Code stream C is directly decodable by a decoder 210 which is based on optimal hardware considerations (e.g., unawkward calculations). Code stream Z is directly decodable by a decoder 216 which is based on optimal software considerations. It is observed that either decoder 210 or 216 may be used in decoding a code stream generated by any of the four encoders 200 through 206, some of the code streams being processed en route to the decoder by the inverter 208. For completeness, it is noted that two other decoders --a Q/P hardware decoder and a P/Q software decoder can also be implemented. These various embodiments are discussed in the co-pending patent application relating to arithmetic coding with diverse encoders and decoders. II. Encoding and Decoding Successive Events with Finite Precision To facilitate the description in this section, the following definitions are provided. Variable names, for the most part, have the same meaning. Definitions C = code stream; the pointer (i.e., code point) to the current interval. C d = decoder code stream with base line adjusted. X = the part of the code stream in the register and not shipped out. Qe(i) = estimated probability for an LPS event for the ith symbol coded. Pe(i) = estimated probability for an MPS event for the ith symbol coded. A(i) = augend (or interval) for ith symbol. S i = ith symbol n(i) = cumulative renormalization count up to the coding of symbol S i . R(i) = renormalization factor for ith symbol. δ condition = equivalent of Kronecker delta function. (1 if condition true, 0 if false) ε = smallest change possible for the current value of Q Given the above definitions, the following relationships apply: Pe(i) = 1 - Qe(i) R(i) = 1 2 n(i) ε = R(i)2⁻¹² for 12 bit precision. A. P/Q Hardware Encoder and Decoder For P/Q symbol ordering, an optimal hardware encoder points to the bottom of the current interval and the code stream C is represented by the equation: In words, the value of C is determined by examining each successive decision event (or symbol). If a subject symbol corresponds to an LPS event, the Qe value at the time of the subject symbol is multiplied by a renormalization factor. The renormalization factor relates to the fact that the interval size is maintained between prescribed limits, for example 0.75 and 1.5. That is, the interval size is represented by an "augend" (referred to as "A") which is adjusted in value to remain between the pre-defined limits. When the augend value at an ith symbol --i.e., A(i)-- falls below 0.75, it is doubled (or altered in some other way) as often as necessary to bring it back into the prescribed limits. By keeping A at or near one in value, the computations for A and C simplify --where multiplicative factors A*Q are approximated as Q. Each time a symbol is encoded, a renormalization is possible. To be sure, each time the interval size is set equal to A*Qe≅Qe (which by definition is less than or equal to A*Pe and hence less than or equal to 0.75), the value of A(i) is renormalized (e.g., multiplied by 2 at least once) to bring it within the limits. In response to an MPS event, the size for the current interval A(i) is approximated as [A(i-1)-Qe] which may or may not be less than 0.75; thus renormalization may or may not be required in the event of an MPS. The total number of times the current interval is renormalized is tallied and represented as R(i), or as noted above R(i) = 1/2 n(i) . The renormalization factor ensures that C is changed in value (e.g., is doubled the same number of times) as is the interval. The value of C when symbol S i is coded is thus incremented for the P/Q hardware in the event of an MPS event, and the increment is determined by Qe values and the renormalization factors for all previous symbols. The P/Q hardware decoder undoes the above process according to the equation: C d is the code stream value after the effect of an event is removed. The P/Q hardware decoder decodes an LPS if C d < A(i)Qe(i). B. P/Q Software Encoder and Decoder The P/Q software encoder points to the top of each current interval. The software code stream is determined by the equation: The evaluation of starts with an A(0) value from which a sum is subtracted. Each addend of the sum corresponds to the product of A times the current P value times a renormalization factor for a previous LPS event. Subtracting the final interval value A(f) from results in the value C derived as the P/Q hardware code stream. A P/Q software decoder would follow the equation: However, the comparison needed to decode the LPS symbol is awkward: C d < A(O)-A(i)+A(i)xQe(i) Or, subtracting A(0) from both sides of the relationship C d -A(O)<-A(i)+A(i)xQe(i) Letting C′ d = C d -A(O), it is observed that: C′ d < [-A(i)x(1-Qe(i))] Both C′ d and -A(i)x(1-Qe(i)) are negative, but are always within A(i) of 0. Therefore, the arithmetic for the decoder is fixed precision arithmetic. The software decoder is thus: T ← AxQe A ← A-T If C′ d H<A (LPS decoded) C′ d ← C′ d -A A ← T renormalize A and C′ d else (MPS decoded) renormalize A and C' d if needed. endif The above computations are simplified as appropriate by setting the A(i) values to approximate one. III. Encoder and Decoder Registers Referring to Fig.5, a preferred X memory register 300 for storing code stream information is shown. The register 300 includes 32 bits which are allocated as follows. Bits 31-24 represent 8 flag bits, the 31st bit representing a "sign" bit. Bit 24 also receives a "carry" if one is generated in the process of preparing the next byte to be shipped. Normally every 8 shifts, bits 23 through 16 (identified as bbbbbbbb) represent the byte that is to be shipped to a buffer memory. In the event of the previous byte being an 'FF', only seven shifts are required and bits 24 through 17 are shipped out. In bit positions 14 and 15 are spacer bits which provide a delay between the bit positions for the byte to be shipped and the bit positions of data which is involved in further computations with the augend. Bits 13 through 2 represent the most recent portion of code stream data to which may be added (or subtracted) the value in a register containing the current interval (augend) value. Bits 13 through 2 are referred to as the "fractional portion" of the code stream and bits 24 through 14 correspond to the "integer portion" of the code stream. The register 300 is referred to as the X register, and contains the latest coded portion of the code stream. Before the bits in the X register were encoded, thousands of bits may have previously been encoded. Those earlier bits moved through the fractional portion of the X register into the integer portion of the register, and from there into a buffer memory which stores up to a finite number of previous bytes. As desired, bytes from the buffer memory may be transferred to storage or may be transferred to another location at which decoding is performed. As suggested above, data is structured as bytes and is shipped as bytes. This is achieved by means of the flag bits. By initializing the 8 flag bits to 00000001 it is noted that the 1 bit shifts left as successive b bits shift into the integer portion of the register 300. When the leftmost flag bit becomes 1, the contents of the X register are considered "negative". On the next shift, the integer portion of the X register 300 is entered into buffer memory. Preferably, buffer memory (not shown) is a memory which stores, for example, 256 bytes. A buffer pointer BP identifies the byte most recently entered into the buffer memory. In addition to the X register, there is also an A register for storing the value of the current interval. As noted hereinabove, the current interval is maintained between prescribed limits, for example 0.75 and 1.5. The A register includes a twelve-bit "fractional" portion (with two 0 bits tagged thereon) which is aligned with the fractional portion of the X register (with two 0 bits tagged thereon) and also includes an integer portion. The alignment of the fractional portions of the X register and the A register facilitates the various computations performed in up-dating the code stream. It is also again noted that each time the interval is renormalized to bring it back into limits, the code stream is similarly renormalized to retain the relative values thereof. The renormalization, it is recalled, simply involves some left shifts (i.e., multiplies by 2) if the interval size limits are set at 0.75 and 1.5. After a code byte is set (and absent a CARRY), the contents of the X register 300 are ANDed with an appropriate Hex value to remove code byte bits. Also, the X register is set to X OR′ 1 00 00 00′ (Hexadecimal notation), ensuring that bit 24 (of the flag bits) is set to 1. In Fig.6, a 32-bit decoder register 400 used with a P/Q hardware implementation is shown. The bit allocations include: two leading zero bits followed by 12 "fraction" bits which are in turn followed by two mm bit positions and 8 new data bit positions. The least significant 8 bits correspond to flag bits. The register 400 may be segmented in various ways as a least significant 8 bits correspond to flag bits. The register 400 may be segmented in various ways as a full word, half words, and bytes. The 12 bits of the fractional portion are aligned with the fractional bits of the augend stored in a decoder A register. After a new data byte has been shifted into XC (bits 31 through 16), the new data is entered into the higher bits of XNEW (bit 15 through bit 8) and XFLAG is reset to 1 unless a carry has occurred. That is, XNEW = SLL B 8 XFLAG = 1 When XFLAG the low order byte, becomes zero, a new compressed data byte is needed. D. CARRY and BORROW In the above review of encoders and decoders, it is observed that the only place where the code streams might differ is where a CARRY or BORROW occurs for a given P,Q convention. At this point it is noted that CARRY's and BORROW's are provided for by stuffing one or more bits (but less than a byte) as appropriate at byte boundaries. The effect of any CARRY or BORROW thus does not propagate beyond the last shipped byte. Hence, the buffer pointer need never back up to earlier bytes, but may instead advance to point at successive bytes as each enters the buffer memory. The problem of CARRY propagation arises when the code stream is up-dated by incrementing the value thereof and when one or more successive bytes of encoded data each comprise a sequence of 1 bits. In this event, an addition will result in a CARRY propagation. To avoid this situation, the present invention provides that a bit be stuffed in a byte to receive a CARRY that might be generated. For example, let there be a sequence of bytes β n-1 , β n , β n+1 where β n-1 is in buffer memory, with the buffer pointer identifying byte β n-1 . Byte β n is in the integer portion of the X register and β n+1 is in the fractional portion of the X register. If the value of byte β n is 'FF' (in Hexadecimal notation), the next byte β n+1 gets a stuffed bit at its leading (most significant bit) position. If β n and β n+1 resulted respectively in 11111111 ('FF') and 11111111 ('FF'), the present invention would stuff a bit at the most significant bit of β n+1 so that the new sequence of encoded data would be 11111111, 01111111, 1... wherein the 0 bit is a stuffed bit for receiving a carry if required. When the decoder detects a byte of all 1 bits, it recognizes the next less significant bit as a stuffed bit and processes it accordingly to produce the proper code stream value. The problem of BORROW propagation arises when the code stream which can be decremented includes a byte of all 0 bits. For example, suppose that there are three sequential bytes β n-1 , β n , β n+1 wherein the middle byte is all 0's. One would be pre-borrowed from the B n-1 byte, converting the B n byte to eight 1 bits. A stuffed bit would be inserted as the new leading bit of byte B n+1 . That new leading bit serves as a set carry bit. The data stream as transferred by the encoder is then: (B n-1 -1) 111111111 (leading 7 bits of B n+1 ) Any bit dropped off the B n+1 byte segment is picked up in the next byte segment of data. The BORROW in effect has been changed to a CARRY by means of a (set) stuffed bit. The decoder, in any event, detects the stuffed bit as such and processes the stuffed bit as a CARRY. Since the goal is to create a P/Q software code stream which is compatible with a P/Q hardware code stream that includes bit stuffing, the code stream must be generated subject to two constraints. First, any hexadecimal 'FF' must be followed by a stuffed bit. Otherwise, byte patterns which are illegal for the hardware decoder will be generated. Second, the code stream must be constructed such that whenever a borrow is needed from the present byte, it can --by definition--be taken. (The present byte is the byte which was transferred from the code register to the code buffer on the previous code byte cycle.) Since only one unit is borrowed, the only byte value which cannot be borrowed from is zero. In general, the need for a borrow from the present byte is detected by setting a high order "preborrow" bit in the code register at the start of a new byte. For convenience, it is set in a bit position, P, which will become the sign bit when the next byte is ready to be written. For example, with a 32-bit Code (X) register, suppose the register contents are: X register: 00000000,P0000000,xxxxxxxx,xxxxxxxx A register: 000aaaaa,aaaaaaaa When the next byte is complete, the contents become: X register: P0000000,nnnnnnnn, xxxxxxxx,xxxxxxxx A register: 000aaaaa,aaaaaaaa If the code register is positive (P = 0), the preborrow has been used and a borrow is needed from the present byte. The borrow is therefore taken from the present byte before the new byte, nnnnnnnn, is transferred from the code register to the buffer. When the preborrow is used, the value in the code register is always larger than the A register and future borrows can be taken from the code register contents. If the code register is negative (P = 1), no borrow is needed from the current byte and the unused preborrow, P, is removed. The code (X) register is compared to the A register. If the code register is smaller, two things have been detected. First, the next byte to be shipped (nnnnnnnn) is zero. Second, a borrow from the current byte might be needed. A borrow is therefore taken from the current byte and propagated through the zero byte in the register. This converts the zero byte to 'FF'. After shipping this 'FF' to the code buffer and shifting the contents of the code register, two preborrows are set - one in the position which will become the sign bit, and the other in the bit position which will become the 'carry' bit position for the next byte. Thus, if the code register is smaller than the A register, X register: 00000000,P0000000,00Px,xxxx,xxxxxxxx A register: 000aaaaa,aaaaaaaa and when the next byte is complete, X register: P0000000,Pnnnnnnn,xxxxxxxx,xxxxxxxx A register: 000aaaaa,aaaaaaaa The Hex 'FF' in the buffer triggers bit stuffing, so the preborrow bit is written into the stuff bit (carry receiver) position. An unused preborrow is thus equivalent to a hardware code stream carry. If the code register is not smaller than the A register, the current contents of the code register are large enough to satisfy any borrow requirements. The current byte is checked, and if it is 'FF', bit stuffing is triggered. In this case, since no preborrow was required, the stuffed carry bit is always clear. The sequence above satisfies all requirements; it creates a code stream which blocks borrow propagation, and which is compatible with hardware. If all zero bytes were simply converted to 'FF', a hardware decoder could decode the resulting code stream. However, the look-ahead to see if a borrow might be needed when the byte to be shipped is zero makes the resulting code stream identical ot the hardware code stream. In effect, this look-ahead detects the existence of the 'FF' in the hardware code stream. IV. PROBABILITY ADAPTATION A. Probability Adaptation Integrated with Arithmetic Coding The above-cited prior art articles by Langdon and by Langdon and Rissanen discuss arithmetic coding in detail and are incorporated herein by reference for such teachings. Arithmetic coding has been found to be a powerful technique for encoding strings of data symbols into compressed form, transferring the compressed (encoded) data, and retrieving the original data symbol string by means of a decoder which undoes the encoding. Arithmetic coding derives its power from two basic attributes: (1) the ability to approach the entropy limit in coding efficiency and (2) the ability to dynamically change the probabilities of the symbols being encoded. As suggested hereinabove, a plurality of decisions are to be encoded to represent a point on a number line. The point is associated with a number line interval which uniquely represents a particular sequence of decisions. Such encoding is accomplished by initially defining a current interval bounded by two points on a number line. The current interval is then partitioned into segments, each segment corresponding to one of the possible events that may result from a decision. The possible events should be exclusive; no segments overlap. In a multiple symbol environment, each decision can result in one of m events (where 2≦m). The length of each segment is determined by the relative probability of the decision event corresponding thereto. That is, the larger the decision event probability, the larger the segment corresponding thereto. This is significant, in that larger segments can be represented by fewer bits; hence, the events which should be encoded more frequently are represented by relatively few bits. For binary arithmetic coding in which m=2, a less probable symbol LPS event may correspond to either a YES or a NO symbol (or event) for a given YES/NO (Y/N) decision; the other event then corresponding to a more probable symbol MPS event. The segments are conveniently referred to as the Q segment (which corresponds to the less probable event) and the P segment (which corresponds to the more probable event). The length of the Q segment corresponds to the estimated probability Qe for the LPS event and the P segment corresponds to the probability (1-Qe). By maintaining A within the limits 0.75 to 1.5, the value of A may be approximated as 1.0. It is then noted that the above computations for determining C and A for an optimal hardware scheme simplify to: If an MPS is encoded-- C ← C + Qe A ← A - Qe If an LPS is encoded-- A ← Qe In the event that A < 0.75 after a decision event is encoded, there is a renormalization of A and C. By renormalizing C as well as A, the code point value remains in the same proportions as the interval. For decoding the encoded data generated according to the P/Q hardware scheme, the following operations are performed: if C ≧ Qe an MPS is decoded and the following computations are made: C ← C - Qe A ← A - Qe If the above condition does not hold, an LPS is decoded and A ← Qe The simplified encoder (and decoder) described above are ideal for hardware implementation because the range subtraction (addition) and the code stream addition (subtraction) can be done in parallel. However, a software implementation employing the same conventions for defining and changing the code stream is not as efficient because two arithmetic operations are required on the most frequently taken path. Therefore, a more efficient software implementation of the encoder is realized by pointing the code stream, C, at the top of the current interval rather than the bottom. For software, the encoding process is as follows: if there is an MPS event-- A ← A-Qe if there is an LPS event-- C ← C-(A-Qe) A ← Qe In either the optimal hardware scheme or software scheme, if A < 0.75 renormalize A and C; update Qe. In examining the above conventions, it is noted that A and C are renormalized in each embodiment when A < 0.75, and Qe is correspondingly up-dated. The manner in which Qe is up-dated according to the invention is now described. B. Up-dating the Probability Estimator 1. Up-dating Qe with Each Augend Renormalization Fig.7 illustrates the up-dating of an estimated probability value Qe as succeeding events are encoded and renormalizations occur. In Fig.7, the ordinate represents values of the augend A and the abscissa represents allowed values of Qe as generated by, for example, a Qe table (discussed hereinbelow). Starting at the allowed Qe value of 0.42208, an LPS event is encoded resulting in an augend value of 0.42208. The LPS event, which drives the augend to a value less than 0.75, results in an LPS renormalization (or "LPS renorm") which results in an incrementing of the Qe value to 0.46896 and a renormalization of A to a value of 0.84416. It is noted that renormalizing A and C in the present embodiment involves a multiplication by two. This operation is not only simple --being performed with simply a register shift-- but also makes it easy to keep count of the number of renormalizations performed. A subsequent MPS event results in A taking on the value 0.37520 according to the simplified expression: A ← A - Qe That is, A = (0.84416-0.46896) = 0.37520 Because A is less than 0.75, an MPS renormalization (or "MPS renorm") takes place. Qe takes on the lower value of 0.42208 and A is renormalized to a value of 0.75040. (A further renormalization is not required because the value of A is no longer less than 0.75.) On the next MPS event, A decreases to 0.32833 which is less than 0.75. A lower Qe value is chosen at 0.32833. The value of A is doubled to equal 0.65666 which is still less than 0.75. The value of A is doubled again so that A becomes 1.31332. A subsequent MPS event reduces the augend to 0.98499 which exceeds 0.75 so that no renormalization occurs. Another MPS event causes A to drop to 0.65666 which results in an MPS renorm. A lower value of Qe is chosen, namely 0.30489, and the augend A is multiplied by two to become 1.3133. On the second MPS event thereafter, an MPS renorm is required. 2. The Qe Table(s) In accordance with the invention, Qe values such as those shown in Fig.7 are stored in table form. In Table 1, a plurality of allowed Qe values are shown in hexadecimal notation in the left column. Each Qe value in the table is preferably a 12-bit value and is defined to occupy two bytes. The Qe values are divided by 5461 (hexadecimal 1555) to convert to N-decimal fractional representation. A 5 bit index is sufficient to uniquely identify each Qe value. To move to an adjacent entry in the table, a shift of two bytes is required. In Table 1, the second column indicates how many bytes are to be shifted for each listed probability value following an LPS renorm. It is observed that, in some instances, an LPS renorm results in the probability value incrementing by one, two, or three index positions in the table. In examining Table 1, it is observed that entries therein correspond to the Qe values set forth in Fig.7. That is, 0.46896 in decimal corresponds within the decimal precision used to the 0a81 hexadecimal value in Table 1. The three entries listed thereafter --namely 0a01, 0901, and 0701-- correspond respectively to the 0.42208, 0.32833, and 0.30489 values of Fig.7. The negative of Qe is used where MPS is 1. An alternative to Table 1 is shown in Table 2. Table 2 shows qi0 values for allowed Qe values which are associated with LPS renormalization. The qi0 values are derived from Table 1 by multiplying the Qe values in Table 1 by 4. In addition, if the MPS is 1, the q0 value is negated. The qi0 term in Table 2 is referred to as qilps(i0) indicating that the index contains information relating to the next Qe value (q0) for both MPS of 0 ,i.e., positive Qe, and MPS of 1 ,i.e., negative Qe, and the index (i0) therefor which apply when an LPS renorm occurs. In Table 2, both the next Qe value and its associated i0 value are found at the previous index. In Table 1, however, a next index is first determined and then the next Qe value is determined therefrom. Table 2 provides a simpler look-up procedure. Table 3 is similar to Table 2, except that it is intended for use with MPS renorms. In particular, in the event of an MPS renorm, Table 3 shows the next probability value q0 and next index i0 for each Qe value in the table. In Table 2, higher values are chosen whereas in Table 3 lower values are chosen. It should be recognized that the tables only include Qe values in the range from 0 to 0.5. At 0.5, the binary event representing the LPS becomes the MPS and vice versa. The event which corresponds to Qe thus changes. For example, if a white pel event represents an LPS event, Qe values represent the probability estimated for the white pel event; however, when the Qe value reaches and exceeds 0.5, the black pel event now becomes the LPS event identified by Qe. The Qe table may be viewed as symmetric about the exchange point where the definitions of the LPS and MPS change. The selection of allowed Qe values is determined based on a number of factors. First, certain values are recognized as "bad" values. In particular, those values which can result in "trapping" the Qe value are not permitted. Probability values that are at or near the values AMIN/2, AMIN/4,... AMIN/2 n --where n is some positive integer-- are considered "bad" values. At such values, a cycle of (1) LPS renormalization, (2) movement to a first Qe value, (3) MPS renorm after a single likely MPS, with a corresponding movement to a second (lower) Qe value, (4) another LPS and LPS renorm, and (5) a return to the first Qe value could trap the estimation process. Accordingly, the values of Qe are preferably selected to exceed AMIN/2 n by a prescribed value δ, so that the probability of an MPS renorm after an LPS renorm is not excessively high. One method of accomplishing this end is to space all smaller Qe values far enough away from a renormalized hex value '1000' to require a plurality of MPS events to invoke an MPS renorm following an LPS renorm. For Qe values near 0.5 this condition is relaxed. For very small Qe the interval between the renormalized Qe and AMIN must be large enough that the MPS renorm probability is of the same order of magnitude as the LPS probability. In addition to the above approach of avoiding Qe values which, when renormalized, are near or equal to AMIN, the present invention teaches the inclusion of a "bad" Qe values provided that the jump of index positions in response to an LPS renorm is relatively greater than the drop of index positions in response to an MPS renorm. For example, the smallest value of Qe in Table 1 is a "bad" value. However, the index to the Qe value is shifted by 2 entries (4 bytes) when an LPS renorm occurs. Therefore, two MPS renorms must occur in sequence to return to the smallest value, and the estimator is not trapped by the high probability of the first MPS renorm. A second consideration in selecting table values involves coding inefficiency. In this regard, it is desirable that minimum coding inefficiency be achieved over the range of allowed Qe values. Referring to Fig.8, a graph of coding inefficiency vs. Qe value is shown for Qe values included in Table 1. The circles represent experimental results and the solid line represents theoretical results for a single context coding embodiment (see section 3). Coding inefficiency is based on entropy, on the bit rate/symbol for a particular state (or specific entry in the Qe table), and on the occupation probability for the particular state. Entropy, it is noted, is defined as: H= - (ΣPr(i)logPr(i)) where each Pr(i) represents the probability of an ith decision event, the sum being taken over all decision events for a given decision. Preferably, but not necessarily, the most uniform curve --given table granularity and arithmetic approximations used in the coding-- is desired. In accordance with the invention, the density of index positions is enhanced at high entropy Qe value portions of the table compared to a power-of-2 set of probabilities. In a power-of-2 set, the range 1/4 to 1/2 corresponds to a Qe value of 0.1; 1/8 to 1/4 corresponds to 0.01; 1/16 to 1/8 corresponds to 0.001; and so on for successive index positions. Near the 1/4 to 1/2 range, there is a relatively large number of entries compared, for example, to the aforementioned skew coder. At lower entropy Qe values, density is relatively sparse. Third, system responsiveness is a consideration; namely, how long it takes to reach the proper Qe value from a value far from the mark. In furtherance of this end, larger increments and decrements are selected between adjacent Qe values, provided that such large differentials do not adversely impact stationary results. Stationary results are generated based on data provided according to a fixed probability --for example, by a pseudorandom number generator producing outputs based on a fixed probability. Nonstationary results are based on actual data wherein the probability may fluctuate over time. Table 1 was determined in accordance with the above considerations and represents a compromise between simplicity, minimum storage requirements for each context (e.g., six bits which include one bit for the sense of the MPS symbol and five bits for the Qe value), reasonable coding efficiency for fixed (i.e., stationary) statistics, and good performance on multiple context data obtained from different data compression models (for example, a facsimile compression model and a continuous tone image compression model). In the above description, a compromise between coding efficiency and rapid estimation of changing probabilities is noted. Referring to Fig.9, a gating circuit is shown. A plurality of input lines and a plurality of output lines are provided. By setting the input lines to a prescribed pattern of 0 and 1 signals, a corresponding q-index is input to the gating circuit. For each q-index the gating circuit provides a pattern of signals on the output lines which represent a corresponding Qe value. In accordance with the invention, Qe values have been selected so as to limit the number of gates and required gating in providing Qe value output for q-index input. The Qe values have been selected so that (a) the least significant bit of each Qe value is always set (to 1) and (b) no more than five of the twelve Qe value bits are set for any Qe value. Accordingly, the above-noted objectives as well as facilitated hardware are achieved. 3. Single Context and Multiple Context Adaptation Referring to Fig.10, a context table is shown. In particular, three contexts C0, C1, and C2 are listed. Each context corresponds to a different setting in which decisions are being made. For example, the differing contexts could represent different areas in a frame of optical data. One area of the frame may be predominately black, another may be predominately white, and a third area may be fairly evenly represented by each type of event. Accordingly, for each context, there is a respective MPS identifier; that is, an indicator as to whether the black (or YES) decision is the MPS or whether the white (or NO) decision is the MPS. In binary notation this is represented in the Fig.10 table by the MPS column in which the 0 event represents the MPS event for the C0 and C2 contexts, while the 1 event represents the MPS event for the C1 context. The next column in the Fig.10 table is a Qe index table which indicates the Qe entry currently being pointed to for the respective context. In context C0, the 0th entry is being pointed to; in the C1 context, the 12th entry is being pointed to; and in the C2 context the 29th entry is being pointed to. The respective current Qe values are shown in the last column to be 0.5, 0.10, and 0.001, respectively. The MPS identifier and Qe index are preferably represented by 6 bits, the Qe index preferably being represented by 5 bits in this embodiment --it being recognized that the number of bits may vary. In accordance with one embodiment the invention, a single augend value is stored and used regardless of which context is being considered. As decisions are entered in each context and as renormalizations are provided for each context, a common augend is processed. By way of example, a string of 0 and 1 bits are shown, each being associated with a corresponding context. The string 01100 represents bits in the C0-C1-C0-C0-C2 contexts, respectively. From the table of Fig.10, it is observed that the bit sequence represents an MPS (for C0), an MPS (for C1), an LPS (for C0), an MPS (for C0), and an MPS (for C2). Let the initial value of A before the first bit is encoded be 1.0 for purposes of this example. In response to the bit string 01100, then, the following operations take place given a P/Q encoding scheme as described hereinabove: i. For the first bit, A ← A - Qe(C0) = 1.0 - 0.5 = 0.5; Because A is now less than 0.75, A is renormalized to 1.0 and the value Qe (C0) is decremented to 0.48. ii. The second bit represents an MPS in context C1, causing the value of the augend A to drop according to the expression A ← A - Qe (C1); which is equal to (1.0 - 0.1) = 0.90. No renormalization is performed. iii. The third bit is an LPS in context C0, resulting in an LPS renorm. The augend value changes from 0.90 to Qe (C0), or 0.48. The value for A must be renormalized (doubled) to the value of 0.96 and the Qe value for the C0 context is incremented. For this example, it is assumed that the value Qe (C0) increments by one entry back to the 0th entry. As discussed hereinbelow, the invention also contemplates the Qe value being moved upward to a single value which is more than one entry away. Alternatively, the invention contemplates the possibility of moving the Qe value upward to a chosen one of several possible next Qe values depending on how far the Qe value appears to be from the actual probability. The latter methodology is discussed as a multiple rate embodiment in the co-pending probability adaptation patent application. iv. At the fourth bit, there is an MPS for context C0. A is altered to (0.96 - 0.5) = 0.46 which requires an MPS renorm. The value for A is doubled to 0.92 and Qe (C0) drops to 0.48. v. The fifth bit corresponds to an MPS in context C2. The value of the augend A becomes (0.92 - Qe (C2)) = 0.92 - 0.001 = 0.919; which is greater than 0.75. No renormalization takes place. After the five bits, the table has the following entries. For context C0, MPS=0, the Qe (C0) index is 1, and the Qe (C0) value is 0.48. For context C1, all data remains unchanged. For context C2, all data remains unchanged. The current augend A for the next encoded decision event is 0.919 regardless of the context of the decision. The multiple context embodiment, compared to a single context embodiment, permits a plurality of decision contexts to be processed together. 4. Single Rate Adaptation A single rate estimator provides that, for a given Qe value, there is only one specified greater value which is to be chosen as the next probability for an LPS renorm and one specified lesser value to be chosen for an MPS renorm. An embodiment of a single rate estimator is set forth hereinbelow in section 5 as a finite state machine. 5. Finite State Machine Representation of the Qe Table Fig.12 shows a finite state machine implementation of a single rate, single context estimator. The value k ex represents a state at which an event which MPS and LPS event definitions are exchanged. In Fig.12, each state has one outgoing path for an MPS renorm and one outgoing path for an LPS renorm. For k max the MPS renorm results in an up-dating which returns to the same state. Each state may thought of as a table entry, representing a particular Qe value. Each entry is linked to two possible succeeding entries. Preferably, MPS renorms result in movement to the next state closer to k max . On an LPS renorm, it is noted that the state may change by one, two, or more state positions on its path to a single possible next state. V. Description of Q-Coder System Flowcharts In the following flowcharts, the "hardware" and "software" embodiments set forth hereinabove are described in terms of flowcharts. The encoder and decoder embodiments are labeled with -H or -S where they differ. Fig.13 is a flowchart showing a coder and decoder according to the present arithmetic coding compression/decompression system. (Compare Fig.1) In Fig.1 BITIN is the binary event encoded, and BITOUT is the binary event decoded. In the flowcharts the binary decisions are called YN in both encoder and decoder. By way of general description, INITENC in Fig.14 and in Fig.15 each initializes the compression system --one in a hardware scheme, the other in a software scheme. The model process is represented by the statement "get S, YN". INITSTATE (Fig.16) sets the initial q-index value and Q e value for all context states S. ENCODE block (Fig.17) uses the context state S and the YN values to generate the compressed data stream. The decision as to when all symbols have been encoded is provided by some external means. For example, for grayscale TV images there is a fixed format such as 512 pels/line by 480 lines. If there is no agreed upon convention, the encoder must supply the decoder with that information either externally or as part of the compressed data stream. When all symbols have been encoded, the block FLUSH (Fig.33 and Fig.34) outputs the final bytes so that the decoder is guaranteed to have enough data to completely decode all of the symbols. The block "transmit" could represent either storage or transmission. This figure suggests that the complete compressed data stream is generated before transmission or storage. However, each byte of compressed data can be transmitted as soon as the next byte has been created. The INITDEC block (Fig.39 and Fig.40) is called once to initialize the decoder. In the decoder, the model supplies the context state S value. The DECODE block (Fig.41) returns the YN decision. The decision as to when the decoding is done is supplied externally or as part of the compressed data stream. A. Detailed Description of the Encoder Operation The following definitions apply to the flowcharts and description thereof. Definitions In the programs and flowcharts Q0(S) is defined as a fixed point fraction with 16 bits. It can either a positive or negative quantity. I0(S) is the index to the QIMPS or QILPS table for updating the Qe probability value. It is stored in the two bytes immediately following Q0(S). The 4 bytes from the QIMPS or QILPS tables will be the next Q0,I0 pair. A is a 16 bit integer, but can be considered a binary fraction with the binary point positioned to provide 12 fractional bits followed by two zeros and 2 leading integer bits. X is a 32-bit number which has a structure as shown in Fig.5 for the encoder and Fig.6 for the decoder. XC is the 16 most significant bits of X in the decoder. XNEW is the 16 least significant bits of X in the decoder. XFLAG is the 8 least significant bits of X in the decoder. LEN is the length of the buffer for the code stream. It is set to 256 bytes (an arbitrary but convenient choice). LEN could be set to 1. BPST points to the start of the compressed data buffer. BE points to the first byte beyond the compressed data buffer. BP is the pointer to the current byte of compressed data. B is the byte of compressed data pointed to by BP. AMIN determines when renormalization is needed. AMIN is set to Hex '4000' (which is equivalent to 0.75) for everything except the software decoder for which it is set to minus Hex '4000' (which is still equivalent to 0.75). INITENC (Fig.14 and Fig.15) does the initialization for the encoder. Two versions of INITENC have been implemented according to whether the hardware version (-H) shown in Fig.2 or the software version (-S) shown in Fig.3 is implemented. After the tables have been set up, INITSTATE (Fig.16) initializes the context storage area. Both versions initialize LEN to 256 bytes, point BE to the end of the compressed data buffer, and point BP to 1 byte before BPST, the actual start of the buffer to be sent. The pointer is updated before a byte is written; hence an offset of 1 is necessary. The byte B (addressed by BP) is initialized to '80' to guarantee that the special cases of B=0 or B='FF' will not be triggered for the first byte in the compressed data stream. The range A is initialized to '4000' and AMIN is initialized to the same value. The differences between the versions appear in the initialization of X. All versions have the 8th msb set to 1 to flag when 8 compressed bits are ready. In the software version a borrow bit is inserted just after the flag bit in X and A is ORed into the low order bits. This borrow bit blocks prevents borrow propagation to the flag bit. ENCODE (Fig.17) shows the two paths taken according to whether YN is 1 or 0. CODEYN1 (Fig.18 and Fig.19) encodes YN=1. If Q0(S) < 0, then MPS=1 and an MPS symbol must be coded. A is decreased by adding the negative Q0. The hardware version moves X up by subtracting negative Q0. On the MPS path if A is less than AMIN, then Q0 can be decreased by UPDATEMPS (Fig.22) The RENORME block (Fig.24) renormalizes both A and X. If Q0 is positive (zero is not allowed), then MPS=0 and an LPS symbol must be coded. For the software version the MPS range must be calculated and X moved down by the new A. In both cases, A is set to Q0 and the update of the probability for an LPS case is then done in UPDATELPS (Fig.23). Since Q0 is always less than AMIN, renormalization is required. CODEYN0 (Fig.20 and Fig.21) shows the same operations as Fig.18 and Fig.19 for the YN=0 path. In this case, Q0 is positive for the MPS path and negative for the LPS path. UPDATEMPS (Fig.22) does the probability update on the MPS path. The new Qe and index (4 bytes total) are found in the QIMPS table at the old I0(S) location. Table 3 gives an example of a QIMPS table. UPDATELPS (Fig.23) does the probability update on the LPS path. The new Qe and index (4 bytes total) are found in the QILPS table at the old I0(S) location. Table 2 gives an example of a QILPS table. RENORME (Fig.24) normalizes the A and X values one bit at a time. A is shifted first and then X is tested to see if the most significant bit is set. If so, the next shift of X removes that flag bit and a byte is output by BYTEOUT (Fig.25 and Fig.26). Otherwise X is just shifted one bit. This process is continued as long as A is less than AMIN. In accordance with BYTEOUT (Fig.25 and Fig.26), the decoder expects every 'FF' byte to be followed immediately by one leading stuffed bit in the next byte. The leading bit will be the carry bit. In Fig.25, the hardware version of BYTEOUT first looks at the last byte B and immediately outputs only 7 data bits in SHIP7-H (Fig.27) if B is 'FF'. Any carry will appear in the most significant bit of the new byte. If B is less than Hex 'FF', X is tested for a carry and if there is none, 8 bits can be output in SHIP8-H (Fig.29). If there is a carry, the last byte needs to be incremented by 1 and the result tested to see if it is now Hex 'FF'. If so, then the carry in X which has already been added to B must be cleared before outputting the next 7 bits. Otherwise, 8 bits may be output into the new byte. The software version BYTEOUT-S (Fig.26) tests whether X is positive. If X is positive, the borrow bit was used and B must be decremented by 1 before outputting 8 bits. If the borrow bit was not used, it is cleared from X before A is compared to X. If X is smaller than A, a borrow could be needed in the future that would not be available if the new byte were output as zero. (A is at most '7FFC' so X has only zeros in the 8 output bits). SHIP8FF-S (Fig.31) does the pre-borrow, converts the new byte to 'FF', and saves the borrowed bit into X. If B is 'FF', then only 7 bits are shipped by SHIP7-S (Fig.28) instead of the 8 bits by SHIP8-S (Fig.30). SHIP7-H (Fig.27) increments the output byte pointer in NEXTBYTE (Fig.32) and stores in the new B bits 24 to 17 from X. The leading bit contains any carry. Only the trailing 17 bits are left in X before the flag is inserted at the 7th most significant bit. This causes the next byte to be output when 7 new bits are ready because one has been left in X. SHIP7-S (Fig.26) is the same as SHIP7-H except that the borrow bit is set to immediately follow the flag bit. SHIP8 (Fig.29 and Fig.30) is similar for both versions. After incrementing the pointer to the next output byte B, the 8 bits in X at bits 23 - 16 are stored at B. All but the 16 least significant bits are cleared in X and the flag is inserted at the 8th most significant bit. The software version also inserts a borrow bit after the flag. The software encoder has to guarantee that B can be decremented if necessary. SHIP8FF-S (Fig.31) is executed when the next byte to be written is zero and a borrow might be required from it. A borrow is therefore taken immediately, decreasing B by 1 and converting the next byte to Hex 'FF'. The borrow taken from these two bytes is inserted into X where it will be output in the next byte as a carry if it is not needed. NEXTBYTE (Fig.32) moves BP to address the next byte in the compressed data buffer. If, after it is incremented, BP is not less than the end of the buffer, the buffer must be transferred and BP reset to the start of the buffer. It is assumed that BPST and BE will be appropriately changed if necessary. After the final symbol has been coded, the 22 compressed data bits still in X need to be flushed out. In FLUSH-H (Fig.33) CT is initialized to 22 and decremented for each shift in X until the flag is in the most significant bit. One more shift puts the output bits on a byte boundary. Then FINALBYTES-H (Fig.35) can output these last bytes. FLUSH-S (Fig.34) moves X to the bottom of the interval which then positions it precisely to the value generated by the hardware version. After byte aligning the bits, if the borrow has been used, the last byte must be decremented before outputting the final bytes in FINALBYTES-S (Fig.36). FINALBYTES-H (Fig.35) goes through the same type of operations as BYTEOUT-H (Fig.25) within a loop until all bits have been flushed out. The blocks FLUSH7 (Fig.37) and FLUSH8 (Fig.38) include an appropriate decrement of CT by 7 or 8 bits. When completed, BP is incremented past the last byte stored and the final buffer can be sent out. The software version of FINALBYTES-S (Fig.36) only has to worry about shipping 7 or 8 bits according to whether the preceding byte is 'FF'. The preborrow was already handled in FLUSH-S. Since X was moved to the bottom of the interval, the test with A in BYTEOUT-S is irrelevant. In FLUSH7 (Fig.37) 7 bits are output for both the hardware and software versions by pointing to the new byte, storing bits 24-17, saving only the 17 least significant bits of X and decrementing CT by 7. In FLUSH8 (Fig.38) 8 bits are output for both the hardware and software versions by pointing to the new byte, storing bits 23-16, saving only the 16 least significant bits of X and decrementing CT by 8. B. Detailed Description of the Decoder Operation INITDEC (Fig.39 and Fig.40) does the initialization for the decoder. Two versions of INITDEC have been implemented according to whether the hardware (-H) movement of the code point for the MPS and LPS symbols shown in Fig.2 or the software version (-S) shown in Fig.3 is desired. After the tables are set up, all states are initialized as in the encoder. The initialization of X is from the buffer of compressed data. It is noted, however, that the magnitude of A is initialized to match to the encoder. Both versions start by getting a new buffer of compressed data. This is assumed to initialize BPST and LEN. BE is pointed to the end of the compressed buffer and BP is initialized to the start of the buffer. The differences between the versions appear in the initialization of X, A, and AMIN. For the hardware version the range A is initialized to '4000' and AMIN is initialized to '4000'. For the software version these numbers are negated. For INITDEC-H the first two bytes are positioned in bits 31-16. For convenience in initialization, the two leading bits of the compressed data stream are defined to be 0. This provides a simple byte alignment between the code bytes and the bytes of the X register during initialization. The first byte is shifted into positions 31-24, the pointer BP is incremented in GETBYTE (Fig.49) and then the second byte added into bits 23-16. The leading byte is guaranteed not to be 'FF' so no testing is needed. The decoding process only looks at the bits in XC, the high two bytes of X (bits 31-16). BYTEIN is used to position a third byte in bits 15-8 (unless the second byte was 'FF' in which case it is added into bits 16-7). BYTEIN sets the flag indicating when a new byte will be needed. The software version INITDEC-S (FIG. 40) starts at 0 minus A which is 'C000' in XC. The first two bytes are added to this starting point. BYTEIN is used to add in the third byte and set the flag. DECODE (Fig.41) shows the two paths taken according to whether MPS is 1 or 0. DECODEMPS1 (Fig.42 and Fig.43) shows two implementations for decoding when MPS=1. In the hardware version, the negative Q0(S) is added to XC. If the result is greater than or equal to 0 the MPS path is followed. YN is set to one and A is decreased by adding the negative Q0(S). If a renormalization of A is necessary on the MPS path because A is less than AMIN, then the magnitude of Q0(S) will be decreased in UPDATEMPS as well. On the LPS path YN is set to 0, XC restored by subtracting the negative Q0(S), and A set to the negation of Q0(S). Renormalization is always required on the LPS path, and the magnitude of Q0(S) is increased in UPDATELPS. The software version in FIG.43 decreases A in magnitude by subtracting the negative Q0(S) before comparing XC to A. A then contains the negative MPS range. If XC is at least as large as A, the LPS is decoded; otherwise the MPS is decoded. If the LPS is decoded, the software version increases XC by subtracting the negative MPS range A. On the MPS path since both A and AMIN are negative, A greater than AMIN indicates that the magnitude of A is less than the magnitude of AMIN and renormalization is needed. DECODEMPS0 (Fig.44 and Fig.45) shows the same operations as Fig.42 and Fig.43 for the MPS=0 path. In this case, Q0 is positive. RENORMD (Fig.46 and Fig.47) each normalize the A and X values one bit at a time. Both A and X are shifted and then XFLAG, the least significant byte of X is tested to see if any bits are set. If not, it is time to get a new byte. This process is continued as long as A is less than AMIN (for hardware) or is more than AMIN (for software). During the process of moving a new byte into X as shown in BYTEIN (Fig.48) the last byte B is tested to see if it was an 'FF' byte before GETBYTE (Fig.49) moves to the next byte. The leading bit in every byte following an 'FF' was inserted during encoding and must be appropriately accounted for during decoding. Following an 'FF', BYTEIN sets XNEW, the two least significant bytes of X, to 2 to shift the flag bit in XFLAG by 1. Then the next byte which would normally be placed in the second least significant byte is shifted up an extra bit and added to X. If the last byte B is not 'FF' the least significant bit of XNEW is set and the new byte B is added to the high order byte of XNEW. GETBYTE (Fig.49) moves BP to address the next byte in the compressed data buffer. If, after it is incremented, BP is not less than the end of the buffer, a new buffer must be obtained and BP reset to the start of the buffer. It is assumed that BPST and BE will be appropriately changed if necessary. The above-described procedures for a software encoder are implementable on a conventional mainframe computer, for example an IBM 3370, or in personal computers such as the IBM PC-XT or PC-AT. The procedures can be implemented in high level languages such as PASCAL. VI. Description of a Hardware Embodiment As shown in Fig.50 the Q-Coder 500 is supplied an appropriate N bit state S by an encoder state generator model (see Fig.1) for each binary event BITIN encoded. The output of the Q-Coder 500 is bytes of compressed data which are transmitted and/or stored before becoming input to a Q-Decoder (see Fig.54). The Q-Decoder determines the boolean value of the binary event BITOUT based on the N bit input state S from the decoder state generator model. This decoded BITOUT value is fed-back to the decoder state generator (not shown). The Q-Coder/Q-Decoder system performs one major cycle per binary event to be encoded. Timing is determined by edge-triggered flip-flops and a single phase clocked system. The time between clock edges is sufficiently long that worst-case propagation delays and set-up time requirements have been met. This description discusses what occurs on each major cycle. Fig.50 gives a block diagram of the Q-Coder 500. For each new cycle, the primary inputs to the Q-Coder 500 are the binary event value BITIN and the state S which specifies where the information about the probability has been stored. At the end of the cycle the OUTPUT CONTROL from a C/OVER outbuffer 508 specifies whether zero, one, or two bytes of compressed data are ready in the 16 bits of the CODESTRING. One input to the statistics unit 502 is the N bit state S which is used to address the conditioning context storage in order to obtain the most probable symbol value MPSVAL and the QINDEX for the current binary decision BITIN. QINDEX is a sequence of integers and is the index to one of a set of probability estimates for the less probable symbol. In the embodiment, QINDEX ranges from 0 to 29. The statistics unit 502 outputs MPSVAL and QINDEX early in the cycle so that these parameters are available for input to both the encoder unit 504 (Fig.41) and an adaptor unit 506. Late in the cycle the statistics unit 502 stores the NEWMPSVAL and NEWQINDEX at the location specified by the state S, provided that the input A-BUS<0> (the most significant bit of the A-BUS) was zero for some interval during the cycle. The operation of the statistics unit 502 is the same for both the encoder and the decoder. The adaptor unit 506 is also the same for the encoder and decoder. The operations in this unit are given in Table 4. The same function can be achieved with discrete logic. The binary event BITIN is input to the encoder unit 504 along with MPSVAL and QINDEX. One output from the encoder unit 504 is the binary (Boolean) signal A-BUS<0>, the most significant bit of the A-BUS. This signals to the statistics unit 502 that it is time to change QINDEX or MPSVAL. The adaptor unit 506 receives the "MPSOP" Boolean signal from the encoder unit 504 which indicates whether the current decision is an MPS operation or not. The output of the adaptor unit 506 is the new values for the two inputs from the statistics unit 502. The statistics unit 502 will only store the new values if A-BUS<0> has been zero. The C/OVER-outbuffer 508 performs bit stuffing for carries on the same cycle as the encoder unit 504 and adaptor unit 506, or it can operate in a pipelined fashion. As a unit of a pipeline, flip-flops store the encoder output each cycle such that on cycle "n" the system would have the C/OVER-outbuffer 508 functioning on the encoder unit 504 output of cycle "n-1". There are two types of major cycles: MPS operation and LPS operation, respectively denoted by MPSOP equal 1 and MPSOP equal 0. If the BITIN value and MPSVAL value are the same, the operation is an MPS operation, otherwise it is an LPS operation. The Exclusive-OR gate in Fig.51 acting on BITIN and MPSVAL determines the type of operation for the Major Cycle. During a cycle, the encoder unit 504 outputs to the C/OVER-outbuffer 508 the binary carry out value C/OUT, the 13-bit unnormalized code stream C-UNNORM, and the 4-bit control signal SHIFTAMT which indicates how much to shift the code stream. The C/OVER-outbuffer 508 outputs one or two 8-bit byte quantities, and a control signal indicating whether 0, 1, or 2 bytes are to be shipped. The statistics unit 502 and adaptor unit 506 are identical in both the Q-Coder and Q-Decoder. A more detailed block diagram of the encoder unit 504 is given in FIG.51. Arithmetic coding of the type discussed here forms the code string by adding and shifting. The quantities that are added are "augends". Input QINDEX is related to the augend. The QVALUE values are in one-to-one correspondence with the QINDEX values, where QVALUE is the augend of the arithmetic coding process for the hardware embodiment of the Q-coder. The encoder unit 504 only requires QVALUE and not QINDEX. In the present embodiment, since QINDEX is a 5-bit quantity and QVALUE is 12 significant bits plus a leading 0, it is less expensive to store QINDEX. Also, it is convenient for the adaptor unit 506 to manipulate QINDEX. The conversion of QINDEX to QVALUE is performed by Q-LOGIC 510 for both the encoder and decoder. The conversion can be done by Table 5 or by a combinational circuit using the truth table methods appearing in current textbooks. Note that the most significant bit of QVALUE is always zero and the least significant bit is always 1. The Q-coder uses two registers called the A-Register 528 and the C-Register 534. The C-Register is functionally equivalent to the X-Register used in the software flowcharts. The logic which modifies the contents of the A-Register 528 is shown in the more detailed diagram of the block A-Logic 520 in FIG.52. Based on the input MPSOP, the A-MUX 522 selects QVALUE for an LPS operation (0) or QVALUE subtracted from A-Register 528 for an MPS operation (1). The Priority Encoder 524 counts the number of leading zeros on the A-BUS and generates the amount of shift SHIFTAMT needed to restore a 1 to the most significant bit of A-BUS. This shift is done in the A-Shifter 526. The least significant bits are filled with zeros as needed. Table 6 shows the values of SHIFTAMT as a function of A-BUS. Dashes indicate "don't care" bits. The A-Register 528 is clocked late in the cycle after all values have stabilized. Its contents are supplied to A-Subtractor 529. The shifting out of the code stream, specifically via the C-Register 534, is controlled by the A-Register 528 in the following way. When the A-Register 528 must shift left a given number of bit positions, then the C-Register 534 is left-shifted by the same number of bits. At the beginning of each major cycle, the A register must be normalized, i.e. the value in the A register must equal or exceed a lower bound value. If this condition --as discussed above-- is not satisfied, A is renormalized (by left shifts). (A is initialized to the lower bound LB.) The A-Register 528 shifts occur during major cycles for which the operation on the A-Register 528 causes it to fall below the lower bound. Falling below the lower bound is detected by the most significant bit of the A-BUS; A-BUS<0> becomes zero. For an MPS operation, QVALUE is subtracted from the A-Register 528, with the difference renormalized if necessary and returned to the A-Register 528. On an LPS operation, the normalized value of QVALUE is placed in the A-Register 528. In Fig.52, the subtraction of QVALUE from the A-Register 528 for MPSOP is performed in the unit A-Subtractor, whose output passes through a 2-by-1 data selector called A-MUX. For an LPSOP, QVALUE passes through the data selector A-MUX 522, whose output bus is called ABUS. The subtraction can cause the result ABUS to fall below value LB. In the instant embodiment, the value of LB is chosen such that if ABUS<0> is 0, then at least one renormalization shift must occur. In fact, the number of renormalization shifts that ABUS must undergo is the number of leading 0s in the result on ABUS. ABUS is renormalized in unit A-Shifter 526, which is a barrel left-shifter with zero-fill. The number of bit positions shifted out of ABUS depends on the number of leading zeros on ABUS. The A-Shifter control, SHIFTAMT, is a 4-bit number between 0 and 12. When the ABUS needs no renormalization, SHIFTAMT is 0 and ABUS passes straight through. The control signal SHIFTAMT feeding the shifter is determined via Priority Encoder 524 which encodes the number of leading 0s on the ABUS bus. During an MPSOP, A-MUX 522 feeds the A-Register minus QVALUE to the ABUS, and during an LPSOP, data selector A-MUX 522 feeds QVALUE. The value SHIFTAMT also controls the C-Register 534 portion of the encoder, and is a control signal to the C/OVER-outbuffer 508 unit. For a MPSOP, the C-Register 534 and QVALUE are summed in C-Adder 536 giving the MPS result for the C-BUS. For an LPSOP, the C-MUX 532 feeds the C-Register 534 to the C-BUS. The C/OUT is fed to the C/OVER-outbuffer 508 unit. The summation of QVALUE to C-Register 534 may be performed concurrently (as in this embodiment) with the subtraction of QVALUE from the A-Register 528. The C-BUS must be shifted by the same SHIFTAMT as the ABUS, hence the output of unit Priority Encoder 524, SHIFTAMT, is also fed to the C-Shifter. On MPSOP cycles, the 2-by-1 data selector C-MUX passes C-BUS to the C-Shifter left-shifting barrel shifter unit which is a twin to the A-Shifter unit. The output of the C-Shifter, is sent back to the C-Register 534. The output of C-MUX (unshifted), named C-UNNORM, is sent to the C/OVER-outbuffer 508 unit, as is SHIFTAMT. SHIFTAMT tells the C/OVER-outbuffer 508 unit how many of the leading bits of C-UNNORM to take. For an LPSOP, the C-Register 534 is not added to, only shifted. On LPSOP cycles, the C-MUX control signal selects the C-Register 534 itself to feed the C-Shifter, where it is left-shifted by SHIFTAMT bits, and then returned to the C-Register 534. As before, SHIFTAMT and C-UNNORM (the output of C-MUX) feeds the C/OVER-outbuffer 508 unit. C/OUT must be 0 at this point in time, because nothing is being added to C. The purpose of the adaptor unit 506 is to adjust the coding parameters employed for a particular context, based on the relative frequency of the incoming 0s and 1s. In the code described, the A-Register 528 and C-Register 534 are both 13 bits in length, and we denote the bit positions 0, 1, ..., 12, where position 0 is the most significant and 12 the least significant. It is convenient to view a radix point between positions 0 and 1 of the A-Register 528, so that with bit A<0> a "1", the A-Register value is between 1.0 and less than 2.0. Value LB is 1.0. The QVALUES are all less than 1.0, but some are close to .5, so the range of values for QVALUE has 12 significant bits. Bit position C<0> is never directly added into, since the corresponding bit position in QVALUE is known to be 0. Thus, C<0> can only be changed during an MPSOP cycle by being carried into. By the nature of arithmetic coding, the value of the codestring after any major cycle can never exceed the sum of the current A-Register 528 value and the codestring to include the current C-Register 534 value. Thus, once a carry-out from C<0> occurs, there will never again be another carry to that bit position of the codestring. The encoder C-Logic 530 block is shown in Fig.53. The input MPSOP with the C-MUX 532 selects the contents of C-Register 534 for an LPS operation (0) or QVALUE added to the content of C-Register 534 for an MPS operation (1) by adder 536. The thirteen bits of output from the C-MUX 532 are output (before renormalization) as the C/UNNORM signal. The same data on the C-BUS is input to a C-Shifter 538 so that it can be shifted by SHIFTAMT before being clocked into the C-Register 534 late in the cycle. Zeroes are filled into the least significant bits during the shifting process as needed. The Q-Decoder 600 of Fig.54 includes a statistics unit 602, adaptor unit 604, decoder unit 606, and C/IN Inbuffer 608 which accounts carries in the code stream. Elements 602 and 604 are identical to the similarly named units in the Q-Coder 500. The decoder unit 606 is shown in detail in Fig.55. The decoder unit 606 includes CD-logic 608, Q-logic 610, and A-logic 612. The decoder CD-Logic 608 is shown in FIG.56. The least significant bit of QVALUE (which is always 1) minus the carry-in C/IN will be 1 if C/IN is 0 and 0 if C/IN is 1. Therefore, QVALUE minus C/IN is obtained by substituting the inverse of C/IN for the least significant bit of QVALUE. If the result of subtracting QVALUE minus C/IN from the contents of the CD-Register 624 in the CD-Subtractor 620 is positive, then an MPS has been decoded and that result will be fed to the CD-Shifter 622 on the CD-BUS. The MPSOP signal is 1. Otherwise an LPS occurred and the contents of the CD-Register 624 plus C/IN output of Adder 626 will be selected by the MPSOP of 0 at CD-MUX 628. The BITOUT value is obtained by Exclusive OR-ing the MPSOP signal with the MPSVAL. The shift amount SHIFTAMT determines how much the CD-BUS value must be shifted before it will be ready to be stored in the CD-Register 624. The least significant bits are filled with the most significant bits of INSTRING during shifting. The CD-Register 624 in effect contains the current code value relative to the bottom of the current interval. The high order 12 bits of the 13 bit QVALUE (the most significant bit is zero) are fed to the CD-Subtractor 620. The least significant bit of QVALUE is replaced with a bit derived from C/IN. Since the least significant bit of the QVALUE is always 1, when C/IN is zero (no carry) the value is inverted to become the least significant bit of QVALUE for the CD-Subtractor 620, and is also fed directly without inversion to the C/IN-Adder. The carry is thus in parallel added to the code stream and removed from QVALUE before QVALUE is subtracted from the code value. The BORROW from the CD-Subtractor 620 is the decoded MPS/LPS decision, MPSOP. The value of BITOUT is then obtained by exclusive or of MPSOP and MPSVAL. Fig.56 also shows the CD-Register 624 data path. Although bit CD-BUS<0> is not directly subtracted from, it must be present because a shifting operation may shift a '1' value into CD-BUS<0>. SHIFTAMT, obtained from the A-Logic circuit, is the control input to the left-shifting CD-Shifter 622. The low-order "fill" bits for the shifter come from bus INSTRING that emanates from the C/IN-Inbuffer unit. The Decoder Unit 606 (Fig.55) uses up to 12 bits from INSTRING plus the carry input C/IN signal to decompress the data. The MPSVAL and QINDEX values are also needed as input to decode the output bit BITOUT. The Decoder Unit 606 supplies the statistics unit 602 with the A-BUS<0> signal as in the encoder. VII. Escaping from the arithmetic code stream In many coding environments, it is desirable to provide an escape from the code stream that can be detected independent of the arithmetic decoder. Hereinbelow is a discussion of escape based on the allocation of spacer bit positions in the encoder code stream register X. The inclusion of spacer bits, in effect, delays the time at which xxxx&ellipsis. bits are shifted into a next byte portion of the X register identified by bit positions bbb&ellipsis.. By including the spacer bits, certain bit patterns after a Hex 'FF' byte are illegal and hence suggest an escape from the code stream and the insertion of a control word. (The control word is typically withdrawn by a controller device prior to decoding.) In addition, the use of spacer bits obviates the possibility of getting more than one carry beyond the byte in next byte portion of the code stream register. The bit pattern of the X register holding the partially completed next byte of the code stream is bit aligned with the (augend) register A which contains the value of the current interval. For a 12-bit integer representation of the probabilities, one possible bit assignment in the encoder registers would be: X = 00000000 0cbbbbbb bbss.xxxx xxxxxxxx A = 00000000 00000000 000a.aaaa aaaaaaaa where '0' indicates zero bits, c is a carry receiver bit, 'b' labels bits in the positions where the next code byte is generated, 's' indicates spacer bits needed to limit carry propagation, and x represents the binary fraction still being developed in the X register. The 'a' bits represent the single integer bit and the fractional bits in the A register. If the preceding code byte is Hex 'FF', the bit positioning is shifted by 1 bit, such that the carry bit occupies the stuff bit position of the next byte. For that special case, X = 00000000 00cbbbbb bbss.xxxx xxxxxxxx Note that only seven 'b' bits are defined for this special case. Following the removal of a fully developed code byte, the rules for bit positioning and renormalizaton dictate an upper bound on the values in the two registers: X = 00000000 00000000 0011.1111 11111111 A = 00000000 00000000 0001.1111 11111110 Note that as future events are coded the value in the X register can never reach the sum of the current X value and the A value, multiplied by any renormalization factor. Therefore, an upper bound on the code register is X = SLL (00000000 00000000 0101.1111 11111101) N where N is the renormalization shift count and SLL stands for a 'shift left logical' operation. When the byte is complete, N will be 8 when the previous byte is not 'FF' and 7 when it is 'FF'. Therefore, following the 'FF', the upper bound on the X register is: X = 00000000 00101111 1111.1110 10000000 X = 00000000 00cbbbbb bbss.xxxx xxxxxxxx Therefore, the maximum value of a data byte following a Hex 'FF' is Hex 'BF' if two spacer bits are included. Further it is noted that if only one spacer bit is allowed, the maximum value for the byte after a 'FF' will be 'FF' and if three spacer bits are allowed, it will be '9F'. Thus, with two or more spacer bits, illegal codes following the 'FF' byte provide an escape from the arithmetic code stream. A two bit shift in the alignment of the A and X registers (as is shown in the flowcharts and Tables 2 and 3) shifts the byte which is to be removed from the code register to a byte boundary of the X registers. This shift does not change the escape code structure. Test Sequence for a small data set A test file was generated using a random number generator such that the probability of 0's in the binary sequence was 0.1875. The actual number of zeros in the file was 48, as expected. The Qe value was initalized to '0AC1' which when shifted left by 2 appears as '2b04'. The positive Qe indicates MPS value of 0. In the following tests, the event counter ec is followed by the Qe value at the end of the cycle and then by the YN symbol. The A, X, and I0 values are given at the end of each cycle after renormalizations. The total number of renormalizations is listed under 'bits'. The "codebytes" are listed as they are output. More than one byte in that column list both a changed preceding byte along with the new byte(s). Test data (in hexadecimal form): EBB7FAFEBFEFD6C7F7FFFDFE7FFBDFF3FDFFFF97F6F5F7FEB97BDF76EDD7E7FF For this file the coded bit count is 208, including the overhead to flush the final data. The actual compressed data stream for both encoders is (in hexadecimal form): 23CA08826F7E20151C267BA0AB606CD63AA26E71C197A80A07C0

Claims: Method for arithmetic coding, whereby portions C of the code are calculated step by step as code points C new ← C previous + A * Q e on a number line, wherein C new is the code point of the new step, Cprevious the code point of the previous step, Q e the estimated probability and A the augend, an interval on the number line which is reduced in each step in dependence to the decision event inputs to A new ← A previous - Q e or A new ← Q e and whereby the reduced augend values A are compared to a prescribed minimum value AMIN and renormalized, preferably doubled, to a value > AMIN and also Q e up-dated when A < AMIN, this method comprising the further steps of: representing AMIN by a 1 bit (n th bit) followed by n-1 0 Bits; and renormalizing A and up-dating a current scaled Q e value to another scaled Qe value when it is detected that the nth bit of A is changing from 1 to 0. The method of Claim 1 wherein said AMIN selecting step includes the step of representing AMIN as Hex '1000'. The method of Claim 1 wherein said Qe value selecting step includes: choosing Qe values which are twelve bits in length wherein the least significant bit of each Qe value is set. The method of Claim 1 wherein said Qe value selecting step further includes: choosing Qe values in which, for each Qe value, no more than five of the twelve bits are set. The method of Claim 1 wherein said Qe up-dating includes the steps of: revising Qe to a higher scaled value when A is renormalized after a Qe event; revising Qe to a lower scaled value when A is renormalized after a non-Qe event; wherein each Qe value approximately equal to AMIN/(2 m ) (where m is a positive integer) is characterized as a bad Qe value and wherein revising a given bad Qe value after a Qe event renormalization includes the step of augmenting the given bad value to a higher value which, after a non-Qe event renormalization, takes on a value other than the given bad Qe value. The method of Claim 1 wherein the Qe probability corresponds to the probability of the less probable binary event and wherein the selecting of Qe values includes the step of: representing Qe as a positive value when the more probable binary event corresponds to a first type of binary decision outcome; and representing Qe as a negative value when the more probable binary event corresponds to the other type of binary decision outcome. The method of Claim 1 comprising the further step of: forming a six-bit coding parameter for a decision to be encoded in which one bit indicates which decision event is the more probable decision event and in which the five remaining bits identify a corresponding Qe value. Encoder using one of the methods of Claims 1 to 7, the encoder further comprising: means (buffer memory) for storing encoded data bytes; a code stream register (X register 300, C-register 534) having (a) a binary fraction (xx..x) for containing code stream data which is adjusted by a current interval value (A) when a first type of binary decision is encoded and remains unadjusted by the current interval value (A) when the other binary event is encoded, (b) a next byte portion (xnew) for containing code stream data which is to be shipped next to said storing means (buffer memory), and (c) at least one spacer bit (s) interposed between said binary fraction portion (xx..x) and said next byte portion (xnew); means for shifting (C-SHIFTER) code stream data through the shift register (C-REGISTER) in response to the encoding of decision events; and means for shipping out one byte of data (C/OUT) at a time into the storing means (buffer memory). An encoder as in Claim 8 further comprising: means for stuffing at least one bit in the code stream in the code stream register following the shipping of a Hex 'FF' byte to said storing means. An encoder as in Claim 8 wherein said at least one spacer bit includes two or more spacer bits and wherein the encoder further comprises bit stuffing means for inserting a single stuff bit after a Hex 'FF' byte. An encoder as in Claim 10 further comprising: means for setting the first two bits in the encoded code stream to zero. An encoder as in Claim 8 further comprising: means for setting at least the first bit in the encoded code stream to zero. An encoder as in Claim 8 wherein said code stream register has at least two spacer bits and in which bytes comprises eight bits, the encoder further comprising: means for escaping from the code stream when a Hex 'FF' byte is followed by a byte having a value which is greater than the largest possible value for the byte which can be generated in the code register following a Hex 'FF'. An encoder as in Claim 13 which includes: means for identifying a current number line interval with a first code stream value that points to a first bound of the interval, wherein said identifying means excludes the other bound from the current interval; and where another encoder identifies said current number line interval with a second code stream value which points as close to said other bound of the current number line interval as possible without including said other bound. An encoder as in Claim 14 wherein said other encoder (A) decrements the value of the code stream therefor when a non-Qe event is encoded and (B) maintains the code stream value when a Qe event is encoded, the encoder further comprising: means for maintaining the first code stream value when a Qe event is encoded and for incrementing the first code stream value when a Qe event is encoded. An encoder as in Claim 8 wherein said code stream register has at least one spacer bit and in which bytes comprises eight bits, the encoder further comprising: means for escaping from the code stream when a Hex 'FF' byte is followed by a byte having a value which is greater than or equal to Hex 'C0'. Apparatus using one of the methods of Claims 1 to 7 for adapting a decision event probability Q e based on successive decision event inputs, the apparatus (Table 1) further comprising: a plurality of selectable Q e value outputs; a distinct q-index (I(dQ)) corresponding to each Qe value output; means having a q-index (I(dQ)) as input, for generating a Q e value output in response to the q-index (I(dQ)) input; wherein the density of q-indexes (I(dQ)) is proportionately greater at higher Q e value outputs and less at lower Qe value outputs relative to the distribution of Q e values in a power-of-two set of estimated probability values. Apparatus as in Claim 17 wherein said generating means includes a gating circuit (Fig.9); and wherein each q-index (QIN) includes input wires to that gating circuit having a distinct pattern of binary signals thereon; and wherein each Q e value output includes output wires from that gating circuit having a corresponding pattern of binary signals generated by the gating circuit in response to the q-index (QIN) corresponding thereto being input.

Inventors: LANGDON GLEN G JR, MITCHELL JOAN L, PENNEBAKER WILLIAM B, RISSANEN JORMA J, LANGDON, GLEN G., JR., MITCHELL, JOAN L., PENNEBAKER, WILLIAM B., RISSANEN, JORMA J.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: H03M7
IPC codes: H03M7, G06T9