Switching device with dynamic hysteresis

Abstract: A switching device (22) responsive to an input voltage V A is powered by low and high internal supply voltage V L and V H . The switching device (22) changes state as V A -V L passes a threshold voltage V T . After the switching device (22) makes a desired change of state in response to rising V A , a hysteresis circuit (24) temporarily decreases V T below that which would otherwise be present. Likewise, after the switching device (22) makes a desired change of state in the opposite direction when V A is falling, the dynamic hysteresis circuit (24) temporarily decreases V T . In both cases, V T later automatically returns to its original value. This dynamic hysteresis prevents spikes in V L and V H from causing undesired changes in state.

Description: The invention relates to an integrated circuit with a switching device comprising, connected between two supply lines, a series arrangement of conduction channels of a first and second transistor respectively, said transistors being of mutually opposite conductivity type, receiving the same input voltage at their respective control terminals and generating an output voltage at the common node between said transistors, the device comprising at least one additional conduction channel, in parallel to one of the conduction channels of the first and second transistor, the device comprising control means responsive to the output voltage, for causing the additional conduction channel to conduct when the device switches to make the transistor conductive in parallel to which the additional transition channel is placed. Such an integrated circuit is known from US Patent No. 4,498,021. According to this publication, the additional current path serves to boost the speed with which the output voltage of the device switches state, by providing additional current to charge any load capacitance of the device. Another such circuit, which also serves to boost the speed is known from US patent No. 4,532,436. In both circuits the additional conduction channels is turned off as soon as the output voltage of the series arrangement has switch. Various problems arise when a fast semiconductor integrated circuit (IC) interacts with the outside world. One problem is that the voltages on the internal supply lines often "bounce" up and down. The bounce can cause the IC to operate improperly when it responds to an input signal having a slowly changing voltage. The problem normally becomes more serious as the IC speed increases. In explanation of supply line bounce, Fig. 1 illustrates a portion of a digital IC 10 that receives largely constant external supply voltages V HH and V LL at respective externally accessible supply terminal (or pads) T H and T L . V HH is greater than V LL . IC 10 produces a circuit output voltage V O at an externally accessible output terminal T O in response to a circuit input voltage V I received at an externally accessible input terminal T I . A capacitor C O , which may be real or parasitic, is connected between terminal T O and the V LL supply. The illustrated portion of IC 10 is a conventional inverting driver powered by high and low internal supply voltages V H and V L provided on lines connected respectively to terminals T H and T L . Responsive to an internal input voltage V A supplied on a line connected to terminal T I , the driver produces an internal output voltage V D on a line connected to terminal T O . Parasitic inductances L L , L H , L I and L O are respectively associated with the lines carrying voltages V L , V H , V A and V D . The driver consists of an input inverter 12, an intermediate inverter 14, and an output inverter 16, each of which is progressively larger so as to provide progressively more current. Inverter 12 is formed with complementary input field-effect transistors (FET's) Q1 N and Q1 P whose gates receive voltage V A and whose interconnected drains provide an inverter output voltage V B logically inverse to voltage V A . Inverter 14, which is typically configured the same as inverter 12, generates a voltage V C inverse to voltage V B . Inverter 16 consists of complementary output FET's Q2 N and Q2 P whose gates receive voltage V C and whose interconnected drains provide voltage V D as the inverse of voltage V C . FET's Q1 N and Q2 N are N-channel devices whose sources are connected to the V L supply line. FET's Q1 P and Q2 P are P-channel transistors having their sources tied to the V H supply line. Returning to inverter 12, it changes state as the voltage difference V A -V L passes an inverter threshold voltage V T . Threshold V T is at a nominal value V S when internal supply voltages V L and V H are respectively at (or very close to) V LL and V HH . Accordingly, inverter 12 switches from a high logic state to a low logic state as voltage V A rises above V LL + V S . This is manifested in voltage V B which goes from a high voltage level close to V HH to a low voltage level close to V LL . When V A later drops below V LL +V S , inverter 12 switches from its low logic state to its high logic state. V B then rises from V LL back up to V HH . Consider what happens if input V I changes very slowly. With reference to Fig. 2 which roughly shows how certain voltages vary with time for IC 10, assume that V I is initially low. Also assume that V L and V H are respectively at V LL and V HH . V A is then low, causing V B to be at V HH . V C is low so that FET Q2 N is turned off and FET Q2 P is turned on. V D and V O are both at V HH . Capacitor C O is charged to a high level. As V I rises slowly, V A tracks V I closely. Inductance L I does not have any significant effect on V A . At the time t₁, V A starts to go above V LL +V S . This causes V B to drop rapidly to V LL . V C goes high to turn FET Q2 N on and FET Q2 P off. V D drops rapidly to V LL . At a time t₂ depending on the transmission delays through inverters 14 and 16, capacitor C₀ starts discharging to the V LL supply by way of a path through elements L₀, Q2 N and L L to pull V₀ rapidly down to V LL . The current flowing through this path varies with time in a non-linear manner. Since the voltage across an inductor is the inductance times the time rate of change of current flowing through the inductor, a positive voltage builds up across inductance L L , reaching a maximum, at a time t₃. A positive (or upward going) spike in V L thereby occurs at t₃ as shown in Fig. 2. The V L spike at t₃ is the "first" spike in a set of timewise contiguous pairs of alternating spikes that die out quickly, of which only the first pair of alternating spikes are actually shown in Fig. 2. The same applies to the further supply line spikes discussed below for Fig. 2 and to the supply line spikes illustrated in the other time diagrams herein. The V L spike at t₃ is often so high that V A -V L temporarily drops below threshold V T . This is true even though the attendant reduction of the difference between V H and V L during the positive V L spike reduces V T somewhat. See shaded area 18 in Fig. 2. (Note that the comparison of V L to V A -V T shown in the various time diagrams herein is equivalent to the comparison of V A -V L to V T which is more difficult to illustrate graphically). Inverter 12 then makes a pair of rapid changes in logic state at approximately a time t₄, causing V B to spike upwards. In turn, the V B spike causes a positive V₀ spike to occur at a time t₅. Even if the C₀ discharge current flowing through FET Q2 N in output inverter 16 were not sufficient in itself to cause the V₀ spike, it could be produced as the result of several such output inverters acting in unison in IC 10. The rapid charging and discharging of capacitor C₀ that occur with the V₀ spike produce a negative (or downward going) V H spike followed by another positive V L spike. In the example shown in Fig. 2, neither of the further spikes is sufficient to cause V A -V L to fall below V T . However, if V I were rising slower than indicated, the further supply line bounce could cause inverter 12 to make additional undesired transitions, thereby resulting in further V₀ spiking. The same situation arises if V I drops slowly, except that the polarities and supply lines are reversed. The first spike is a negative V H spike that results from the rapid charging of capacitor C₀ by way of a path through elements L H , Q2 P and L₀. The V₀ spikes and the corresponding spikes in V B , V C and V D can be disastrous. They can cause a circuit (such as a flip-flop) responsive to V₀, V B , V C or V D to be set in a wrong state. To overcome the bounce problem, one might consider replacing inverter 12 with a device (such as a Schmitt trigger) having a pair of separate static voltage thresholds. While static hysteresis might be useful in certain applications, it is not effective if the two thresholds must lie within a narrow voltage range. A solution that entails a single static threshold is desirable. A better solution is to utilize dynamic hysteresis to prevent internal supply line voltage bounce from causing unwanted changes in state. The present hysteresis is termined "dynamic" because a change in device threshold voltage triggered by a change in logic state occurs only for a prescribed period of time. When that period expires, the threshold voltage automatically returns to its original value. The device therefore has only one static threshold. This is especially useful in a high-speed IC having a narrow threshold range in which the input voltage must switch. This also avoids the additional propagation delays that normally occur with static hysteresis. A circuit with dynamic hysteresis is known from U.S. Patent 3,718,864 (Kelly). This prior art circuit functions as a cross-over detector. The known circuit includes a comparator for comparing an input voltage at an input terminal with a reference voltage at a reference terminal. The comparator is biased at the reference terminal through a resistance connected to a supply voltage terminal. The comparator's output is coupled to the reference terminal via a capacitance, thus establishing an a.c. feedback-path. Consequently, in response to an output voltage change the reference voltage experiences an associated pulse-like change. However, this prior art circuit does not mention the bounce problem in digital circuits and it does not teach how dynamic hysteresis can be realized in digital circuits which use inverter circuits built of complementarily controlled transistors whose conduction paths are in series arrangement. It is an object of the invention to provide an integrated digital circuit which overcomes the bounce problem. The integrated circuit according to the invention is characterized in that the control terminals of the first and second transistor are interconnected with an externally accessible terminal of the integrated circuit, and in that the control means are arranged for causing the additional conduction channel to conduct only for a prescribed period of time after the output voltage of the device has changed logic state. An embodiment of the invention is characterized in that the at least one additional current conduction channel is part of a further transistor having the same conductivity type as the transistor in parallel to which its conduction channel is placed, the further transistor receiving on its control terminal a control voltage generated by said control means. The first and second transistor are typically an N-channel and a P-channel FET respectively, having their gates responsive to voltage V A , sources respectively coupled to the lines carrying voltage V L and V H and drains coupled together to provide an output voltage V B inverse to voltage V A . The further transistor is typically an N-channel FET having its gate responsive to signals from the control circuit, its source coupled to V L line and drain coupled to the drain of the first transistor. A further P-channel FET may also be provided having its gate responsive to signals from the control circuit, its source coupled to the V H line and drain coupled to the drain of the second transistor. More particularly, the present device is incorporated in an electronic circuit in which a low supply voltage V L and a high supply voltage V H are provided to power the device. In response to an input voltage V A , the device changes state as V A -V L passes a threshold voltage V T . With threshold V T substantially at a value V S and with voltages V L and V H substantially at respective values V LL and V HH , the device switches from a first state to a second state as V A rises above V LL +V S and from the second state to the first state as V A drops below V LL +V S . The device includes a dynamic hysteresis circuit that, after V A rises above V LL +V S , temporarily decreases V T below that which would otherwise be present and/or, after V A drops below V LL +V S , temporarily increases V T above what would otherwise be present. V T normally returns to V S before V A starts moving in the direction opposite to that in which it was moving when V T changed. An embodiment of the invention is characterized in that the first and second current conduction paths comprise a conduction channel of a first and second transistor, respectively, said transistors being of a mutually complementary conductivity type, and receiving the same input voltage at their respective control terminals, whereby the at least one additional current conduction path comprises a conduction channel of a further transistor having the same conductivity type as the transistor in parallel to which its conduction channel is placed, the further transistor receiving on its control terminal a control voltage generated by said control means. The first and second transistor are typically an N-channel and a P-channel FET respectively, having their gates responsive to voltage V A , sources respectively coupled to the lines carrying voltages V L and V H and drains coupled together to provide an output voltage V B inverse to voltage V A . The further transistor is typically an N-channel FET having its gate responsive to signals from the control circuit, its source coupled to the V L line and drain coupled to the drain of the first transistor. A further P-channel FET may also be provided having its gate to signals from the control circuit, its source coupled to the V H line and drain coupled to the drain of the second transistor. The control circuit causes the further N-channel FET to turn on temporarily in response to voltage V B going from a high level to a low level. This temporarily increases the width of the pertinent conducting N-channel area in the device so as to reduce V T until the further N-channel FET turns off. Likewise, the control circuit causes the further P-channel FET to turn on temporarily in response to voltage V B going from its low level to its high level. The width of the pertinent conducting P-channel area in the device thereby increases to raise V T briefly. The temporary change in V T provides a clearance that prevents the present device from making a pair of rapid changes of state as a result of internal supply line bounce when V A is changing slowly. This avoids output voltage spikes. BRIEF DESCRIPTION OF THE DRAWINGS. Fig.1 is a circuit diagram for a portion of a digital IC utilizing a conventional input inverter. Fig. 2 is a pair of graphs for various voltages as a function of time for the IC of Fig. 1. Fig. 3 is a circuit diagram for a portion of a digital IC that utilizes an input inverting device having dynamic hysteresis according to the invention. Figs. 4a and 4b are two pairs of graphs for various voltages as a function of time for the IC of Fig. 3. Figs. 5 and 6 are circuit diagrams for specific embodiments of the control circuit 26 in Fig. 3. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. In the drawings, each N-channel FET has an arrow pointing towards its channel. Each P-channel FET has an arrow pointing away from its channel. All of the FET's shown in the drawings are enhancement-mode insulated-gate devices. DESCRIPTION OF THE PREFERRED EMBODIMENTS. Referring to the drawings, Fig. 3 illustrates a portion of a digital IC 20 in which a very fast logic circuit powered by high and low internal supply voltages V H and V L operates on input voltage V A and possibly on other input voltages (not shown) to produce output voltage V D . The logic circuit contains an input inverting device 22 that produces voltage V B as the logical inverse of voltage V A . Device 22 is formed with input inverter 12 consisting of FET's Q1 N and Q1 P arranged as described above and a circuit 24 that provides dynamic hysteresis for the threshold voltage V T of device 22. Dynamic hysteresis circuit 24 consists of a control circuit 26 powered by supply voltages V H and V L , an N-channel FET Q3 N , and a P-channel FET Q3 P . In response to voltage V B , control circuit 26 supplies threshold-control voltages V N and V P to the respective gates of FET's Q3 N and Q3 P . Their sources are respectively connected to the V L and V H supply lines, while their drains are connected to the drains of FET's Q1 N and Q1 P to produce voltage V B . FET Q3 N is therefore "in parallel" with FET Q1 N . Likewise FET's Q3 P and Q1 P are in parallel. The threshold voltage for an inverter formed with complementary FET's depends on the ratio R P/N of the P-channel width to the N-channel width (at constant channel length). This means the widths of the channel areas that are conducting at the threshold point. The threshold voltage increases when R P/N increases and vice versa. FET's Q3 N and Q3 P are normally off or at so low conductive levels as to be effectively off. Accordingly, the quiescent value of R P/N for device 22 is simply the Q1 P channel width divided by the Q1 N channel width since FET's Q1 N and Q1 P are both conducting at the threshold point, one in the midst of turning on and the other in the midst of turning off. If FET Q3 N is on but FET Q3 P is off, the N-channel width for device 22 increases since FET's Q3 N and Q1 N are in parallel. R P/N for device 22 is therefor less than its quiescent value. In like manner, R P/N for device 22 is greater than the quiescent value when FET Q3 P is on but FET Q3 N is off. With the foregoing in mind, device 22 operates as follows. FET's Q3 N and Q3 P are initially off. Supply voltages V L and V H are initially at (or very near) respective substantially constant levels V LL and V HH . Under these conditions, threshold V T is at quiescent value V S determined by the quiescent R P/N of device 22. When V A -V L passes V T , device 22 changes state. If V A rises above V LL +V S , FET Q1 N turns on and FET Q1 P turns off. Device 22 as manifested by the conductive conditions of FET's Q1 N and Q1 P switches from a high logic state to a low logic state, causing voltage V B to go from a high level near V HH to a low level near V LL . Responsive to this change in voltage V B , control circuit 26 temporarily raises V N enough to turn FET Q3 N on for a brief period. FET Q3 P remains off. R P/N drops below its quiescent level. This reduces V T until circuit 26 reduces V N sufficiently to turn FET Q3 N back off. Largely the reverse occurs when V A drops below V LL +V S . FET Q1 N turns off and FET Q1 P turns on, causing device 22 to switch from its low logic state to its high logic state. V B goes from V LL up to V HH . In response to this V B change, circuit 26 temporarily provides V P at a sufficiently low voltage to turn FET Q3 P on for a short time. FET Q3 N stays off. Consequently, R P/N rises above its quiescent value so as to increase V T . When circuit 26 subsequently raises V P to turn off FET Q3 P , V T drops back down. The logic circuit in IC 20 also contains an intermediate logic section 28 and output inverter 16. Logic section 28 may perform any of a number of logical functions such as inversion, ANDing, and ORing. Section 28 might also be a non-inverting buffer or simply a direct connection. Depending on how section 28 is configured, it operates on voltage V B and possibly on other input voltages (not shown) to produce voltage V C at a value that is logically the same as or inverse to voltage V B . Inverter 16 consists of FET's Q2 N and Q2 P arranged as described above to produce voltage V D as the inverse of voltage V C . Circuit input voltage V I and external supply voltages V LL and V HH are supplied respectively to externally accessible terminals T I , T L and T H which are interconnected with the logic circuit via parasitic inductances L I , L L and L H in IC 20 in the same way that these elements are interconnected with the inverting driver in IC 10. The same comments apply to parasitic inductance L O , capacitance C O and externally accessible output terminal T O at which circuit output voltage V O is provided in IC 20. Now, look at what happens if voltage V I is changing slowly when internal supply line voltage bounce arises in the manner described above. Assume (for example) that section 28 provides a voltage inversion so that V C is the inverse of V B . Fig. 4a is a pair of simplified diagrams illustrating voltage variation as a function of time for IC 20 for the case in which V I rises slowly. Fig. 4b is a corresponding pair of simplified time diagrams for the situation in which V I falls slowly. In both Figs. 4a and 4b, V L is initially at V LL while V H is initially at V HH . Threshold V T thus starts at V S . First consider Fig, 4a which is analogous to Fig. 2. V I , V A , V B and V O are initially at the values given above for Fig. 2. Capacitor C O is charged to a high level. As V I rises, V A follows closely. Inductance L I again has no significant effect. When V A passes V LL +V S at time t₁, V B drops rapidly to V LL . In response, hysteresis circuit 24 reduces V T starting at a time t 1.5 . The difference between dotted line 30 and the solid line representing V A -V T in Fig. 4a indicates the amount of reduction in V T . Capacitor C O starts discharging at time t₂. This produces a positive V L spike at time t₃ according to the mechanism described above for IC 10. The attendant reduction of the difference between V H and V L at t₃ does result in a further V T reduction beyond that already caused by circuit 24. However, due solely to the V T reduction produced by circuit 24, V A -V L stays above V T during the positive V L spike. Capacitor C O thereby remains discharged so as to substantially inhibit any further internal supply line voltage bounce. Accordingly, no spikes occur in V B , V C , V D and V O . At a later time t 3.5 , V T automatically returns to V S . The circuit timing parameters and device values are preferably chosen in such a manner that V T goes back to V S before V I and V A start to drop in subsequent switching operation. The falling V I situation of Fig. 4b is essentially the complement of that of Fig. 4a. In Fig, 4b, hysteresis circuit 24 increases V T between t 1.5 and t 3.5 . The amount of V T increase is indicated by the difference between dotted line 32 and the solid line labeled V A -V T . As the result of the V T increase, V A -V L remains below V T during the negative V H spike to prevent further spiking. Alternatively, section 28 might generate V C at the same logical value as V B . If V I rises slowly, the first supply line spiking occurs on the V H line as a negative spike followed immediately by a positive spike. Circuit 24 decreases V T to prevent V A -V L from dropping below V T during the positive V H spike -- i.e., the second spike in the pair of alternating V H spikes. The same applies when V I drops slowly except that the polarities and supply lines are reversed. Since the magnitude of the second spike in each pair of alternating internal supply line spikes is normally slightly less than the magnitude of the first spike, the situation in which V C and V B are logically the same is not as critical as when V C is the inverse of V B . Turning to Fig. 5, it depicts a specific embodiment for control circuit 26 in device 22. Circuit 26 here consists of complementary charge-supply FET's Q4 N and Q4 P , capacitors C1 and C2, and complementary discharge FET's Q5 N and Q5 P connected as shown in Fig. 5. FET's Q4 N and Q4 P are arranged as an inverter 34 with their drains connected together to provide a voltage V E inverse to voltage V B supplied to their gates. Circuit 26 in Fig. 5 operates in the following way. When V B drops from V HH to V LL , FET Q4 N turns off and FET Q4 P turns on. Current from the V H line flows through FET Q4 P to capacitors C1 and C2. Capacitor C1 provides positive charge to the Q3 N gate for a short period of time. During this period, charge also flows to the V L line by way of a path through FET Q5 N which turns on. A competition thus exists between the charging of the Q3 N gate by capacitor C1 and the discharging of the Q3 N gate through FET Q5 N . With appropriate selection for the transistor/capacitor sizes, the average charge rate during the charging period exceeds the average discharge rate by an amount sufficiently great so that voltage V N rises enough to turn FET Q3 N on. Shortly afterwards, the charge on the Q3 N gate dissipates sufficiently through FET Q5 N to cause FET Q3 N to turn back off. When V B returns to V HH at a later time, elements Q4 N , C2 and Q5 P function in a complementary manner to enable FET Q3 P to turn on briefly. Fig. 6 shows a preferred embodiment for control circuit 26. In this case, circuit 26 consists of inverter 34, an inverter 36 that inverts voltage V E to produce a voltage V F , an inverter 38 that inverts voltage V F to produce a voltage V G , transmission gates 40 and 42, and discharge FET's Q5 N and Q5 P whose gates receive voltage V G here. FET Q5 N is source-drain connected between the V L line and the Q3 N gate. FET Q5 P is similarly source-drain connected between the V H line and the Q3 P gate. Inverter 36 consists of complementary FET's Q6 N and Q6 P arranged in the conventional manner shown. Similarly, inverter 38 consists of FET's Q7 N and·Q7 P connected conventionally. Gate 40 is formed with complementary FET's Q8 N and Q8 P whose gates respectively receive voltages V F and V G . FET's Q8 N and Q8 P have interconnected first source/drain elements connected to the Q4 N and Q4 P drains and interconnected second source/drain elements connected to the Q3 N gate. Gate 42 consists of complementary FET's Q9 N and Q9 P arranged with regard to the Q3 P gate in a manner that is complementary to the arrangement of gate 40 with respect to the Q3 N gate. Circuit 26 in Fig. 6 operates as follows. Assume that V B is initially at V HH so that FET Q4 N is on and FET Q4 P is off. V F is likewise at V HH . V E and V G are both at V LL . FET Q8 N is on, thereby setting V N at V LL . FET's Q3 N , Q5 N and Q8 P are all off. When V B drops to V LL , FET Q4 N turns off and FET Q4 P turns on. V E rises to V HH . During an initial part of the time needed for inverter 36 to drop V F down to V LL , positive charge form the V H line flows through FET's Q4 P and Q8 N to the Q3 N gate. V N increases, enabling FET Q8 P to turn on. Although FET Q8 N gradually turns off, positive charge from the V H line now flows through FET's Q4 P and Q8 P to the Q3 N gate to raise V N further. This continues for the entire time needed for inverter 36 to raise V G up to V HH . At some point during the charging of the Q3 N gate, FET Q3 N turns on. When inverter 38 finally switches, FET Q8 P turns off to stop the charging of the Q3 N gate. At this point, FET Q5 N turns on. It opens a path to the V L line for discharging the Q3 N gate, causing FET Q3 N to turn off. Inverters 36 and 38 and FET's Q4 N , Q9 N , Q9 P and Q5 P operate in a similar, complementary manner to enable FET Q3 P to turn on briefly when V B later returns to V HH . If the transmission delay of inverter 36 or 38 is too small to allow enough time to charge the Q3 N gate and/or the Q3 P gate, a delay element can be placed in series with inverter 36 or 38. The delay element might, for example, consist of a pair of inverters in series. For the embodiment of Fig. 6, V LL and V HH preferably are 0 volt (ground) and 5 volts. FET's Q1 N , Q1 P , Q3 N , Q3 P , Q4 N , Q4 P , Q5 N , Q5 P , Q6 N /Q7 N , Q6 P /Q7 P , Q8 N /Q9 N , and Q8 P /Q9 P have respective channel widths of 100, 270, 50, 100, 20, 50, 1, 5, 5, 10, 10 and 25 microns. The channel length for all of these FET's is preferably 1 micron except for FET Q5 N whose channel length is 5 microns. In some situations, the values at which V A is provided from an IC preceding IC 20 may not be appropriate for driving FET's Q1 N and Q1 P directly with V A so as to achieve a desired quiescent (V S ) value for V T . Such cases can be handled by inserting a non-inverting buffer in the line leading to the gate of one of FET's Q1 N and Q1 P . The buffer might, for example consist of a pair of inverters in series. Nonetheless, the gates of FET's Q1 N and Q1 P are still responsive to V A . Such an arrangement does not have any particularly significant effect on the dynamic hysteresis. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and various mofifications could be made. For example, junction FET's could be used instead of insulated-gate FET's. Certain of the enhancement-mode FET's could be replaced with depletion-mode FET's. If dynamic hysteresis is needed only when input V I rises, FET Q3 P and the portions of circuit 26 not used with FET Q3 N (for example, FET's Q5 P , Q9 N and Q9 P in Fig. 6) could be deleted. The converse applies if dynamic hysteresis is needed only when V I falls. Furthermore, threshold V T was defined with respect to low supply voltage V L merely because this is the normal convention. V T could as well have been defined with reference to high supply voltage V H without changing the design, physical operation, or effect of the invention. The only difference is that the polarities relating to V T would generally have to be reversed in the operational explanation.

Claims: An integrated circuit with a switching device comprising, connected between two supply lines (V HH , V LL ), a series arrangement (22) of conduction channels of a first (Q1 n ) and second (Q1 p ) transistor respectively, said transistors being of mutually opposite conductivity type, receiving the same input voltage (V A ) at their respective control terminals and generating an output voltage at the common node between said transistors, the device comprising at least one additional conduction channel (Q3 n , Q3 p ), in parallel to one of the conduction channels of the first and second transistor (Q1 n , Q1 p ), the device comprising control means (26) responsive to the output voltage, for causing the additional conduction channel (Q3 n , Q3 p ) to conduct when the device switches to make the transistor (Q1 n , Q1 p ) conductive in parallel to which the additional transition channel is placed, characterized in that the control terminals of the first and second transistor (Q1 n , Q1 p ) are interconnected with an externally accessible terminal of the integrated circuit, and in that the control means (26) are arranged for causing the additional conduction channel (Q3 n , Q3 p ) to conduct only for a prescribed period of time after the output voltage of the device has changed logic state. An integrated circuit as claimed in Claim 1, characterized, in that the at least one additional current conduction channel is part of a further transistor (Q3 n , Q3 p ) having the same conductivity type as the transistor (Q1 n ,Q1 p ) in parallel to which its conduction channel is placed, the further transistor (Q3 n , Q3 p )receiving on its control terminal a control voltage generated by said control means (26). An integrated circuit according to Claim 2, wherein the further transistor is referred to as the first further transistor (Q3 n ) and is in parallel to the conduction channel of the first transistor (Q1 n ), characterized in that it comprises a second further transistor (Q3 p ) in parallel to the conduction channel of the second transistor (Q1 p ) and of the same conductivity type as the second transistor (Q1 p ), the control means are arranged for causing the conduction channel of the second further transistor (Q3 p ) to conduct for the prescribed period of time after the output voltage of the device has switched to make the transistor (Q1 n , Q1 p ) conductive in parallel to which the second further transistor (Q3 p ) is placed. An integrated circuit as claimed in Claim 2 or 3, characterized in that the control means (26) comprises an inverter (34) for charging via an inverter output thereof the control terminal of the further transistor (Q3 n , Q3 p ) via a charging path (C1,C2, Q9 n , Q9 p , Q8 n , Q8 p ), said inverter (34) being fed via a junction of the first and second current conduction path, the control means (26) also comprising a discharging element (Q5 n , Q5 p ), connected between the control terminal of the further transistor (Q3 n , Q3 p ) and the relevant supply line (V H , V L ). An integrated circuit as claimed in Claim 2 or 3, characterized in that the control means (26) comprises a charging path (C1, C2) between on the one hand a terminal providing a voltage (V E ) inverse to the output voltage (V B ) and on the other hand the control terminal of the further transistor (Q3 n , Q3 p ), and a discharging element (Q5 n , Q5 p ) connected between the control terminal of the further transistor (Q3 n , Q3 p ) and the relevant supply line (V H , V L ). An integrated circuit as claimed in Claim 4 or 5, characterized in that the charging path comprises a capacitive coupling (C1, C2) to the control terminal of said further transistor (Q3 n , Q3 p ), whereby said discharging element is one of the following elements: a resistive element, a diode (Q5 n , Q5 p ). An integrated circuit as claimed in Claim 4, wherein said transistors (Q1 n , Q1 p , Q3 n , Q3 p ) are of the field effect type, characterized in that said charging path comprises a transmission gate comprising a parallel arrangement of conduction channels of a pair of transistors (Q8 n , Q8 p , Q9 n , Q9 p ) which are of a mutually complementary conductivity type, whereby said discharging element comprises a third transistor (Q5 n , Q5 p ) of the same conductivity type as that of the further transistor (Q3 n , Q3 p ), which third transistor (Q5 n , Q5 p ) has its conduction channel connected between the control terminal of the further transistor (Q3 n , Q3 p ) and the relevant supply line (V H , V L ), the control terminal of said third transistor (Q5 n , Q5 p ) and the control terminal of the transistor in the transmission gate (Q8 n , Q8 p , Q9 n , Q9 p ) of the conductivity type opposite to that of the third transistor (Q5 n , Q5 p ) receiving a first control signal of a polarity that is the same as that of the input voltage, the other transistor in the transmission gate (Q8 n , Q8 p , Q9 n , Q9 p ) receiving on its control terminal a second control signal of a polarity opposite to that of the input voltage. An integrated circuit as claimed in Claim 7, characterized in that the control means (26) further comprises in addition to said inverter (34), now referred to as the first inverter, a second and a third inverter (36,38), the second inverter (36) being fed by the first inverter (34) and feeding the third inverter (38), the first control signal being generated on an output terminal of the third inverter (38), the second control signal being generated on the output terminal of the second inverter (36).

Inventors: FLETCHER THOMAS DALE, SHIN YONG-IN, FLETCHER, THOMAS DALE, SHIN, YONG-IN
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: H03K19
IPC codes: H03K17, H03K3, H03K19