Demodulator for a color composite video signal

Abstract: This invention provides a digital color demodulator having: a first phase locked loop circuit (14) which generates an analog subcarrier signal phase locked to the color burst signal; a second phase locked loop circuit (15) which generates an internal system clock signal phase locked to a horizontal period; a Y/C color separation circuit (13) operating under the internal system clock signal; a pair of multiplying circuits (20,21) one of which multiplies a digital subcarrier signal, converted from the analog subcarrier signal, with the color signal, and the other of which multiplies the digital subcarrier signal, phase delayed by substantially 90°, with the color signal, thereby performing orthogonal demodulation of the signal. The digital processing circuits are all driven by the internal system clock signal generated by the second phase locked loop circuit (15).

Description: The present invention relates to a demodulator for a color composite video signal and a method for demodulating a color composite video signal. The invention is in the field of digital signal processing in a television receiver, and particularly relates to the improvement of a color demodulation system. In conventional color demodulation systems, the clock signal which is used for A/D conversion has a quadruple subcarrier frequency (4F SC ) phase locked to a color burst signal. Data of 4F SC in frequency are phase-shifted to be related to each other as (R-Y), (B-Y), -(R-Y) and -(B-Y). Every other piece of the data is extracted to perform color demodulation. In conventional color demodulation systems, color demodulation can be performed even if the system receives an analog composite signal which is sent out from a video tape recorder, for example, and in which a color burst signal and a horizontal synchronizing signal are not synchronized with each other. However, since the video signal is subjected to A/D conversion through the use of the clock signal of the quadruple subcarrier frequency 4F sc in the system, the number of the samples of one line may not be 910. When signal processing is performed, such as scanning line interpolation and double writing into a memory to double a scanning line, the number of the samples of one line is not a fixed value locked to a horizontal period but fluctuates. This engenders problems such as manufacturing 1H delay lines. Also, system circuitry becomes complex. Various color decoding schemes have been proposed. For example, Fernseh & Kinotechnik, vol. 40, no. 4, April 1986, pages 141-146 discloses a digital color decoding scheme in which the horizontal component of the input signal is used to provide a reference for signal processing portions of the circuit. In operation, the circuit processes a composite video signal by first digitizing the entire signal, then deriving a horizontal period from the digitized signal, locking this derived signal to a crystal controlled phase-locked loop, processing the resulting signal, converting the processed signal to an analog signal, and then using the resulting signal as a reference signal and thus assure signal stability. This invention is to solve many problems inherent in prior art apparatus. This is achieved by a demodulator for a color composite video signal as described in independent claim 1 and the method as described in claim 5. This invention provides a digital color demodulator having: a timing means for generating, from an analog color composite video signal, H pulses synchronized with horizontal synchronizing signals of the video signal and which have a horizontal period; clamp pulses depending on the back porch of the horizontal synchronizing signal, and burst gate pulses from the color burst signal included in the analog composite video signal; a first phase-locked loop circuit which generates an analog subcarrier signal phase-locked to the color burst signal; a second phase-locked loop circuit which generates, from the H pulses, an internal system clock signal phase-locked to the horizontal period; first conversion means. that convert the analog color composite video signal into a digital composite video signal, the first conversion means including a clamp means responsive to the clamp pulses, the first conversion means performing sampling according to the internal system clock signal; second conversion means that convert the analog subcarrier signal into a digital subcarrier signal, the second conversion means sampling the analog subcarrier using the internal system clock signal; a Y/C color separation circuit, operating under the internal system clock signal for separating the digital composite video signal into a luminance signal (Y) and a color signal (C) modulated by the color subcarrier signal, and receiving the composite video signal from the first conversion means; first delaying means that delay the digital subcarrier signal by an amount equal to the amount by which the separation means delayed the luminance and color signals relative to the digital composite video signal, the first delay means being driven by the internal system clock signal; second delaying means that delay the phase of the once delayed digital subcarrier signal by substantially 90°, the second delay means being driven by the internal system clock signal; a pair of multiplying circuits, one of which multiplies a digital subcarrier signal with the color signal, and the other of which multiplies the twice delayed digital subcarrier signal, with the color signal. The digital processing circuits of this invention are all driven by the internal system clock signal generated by the second phase-locked loop circuit. For that reason, signals can be digitally processed in the circuits, since the number of samples per horizontal line remains a fixed value locked to the horizontal period, even if an analog composite video signal does not have a prescribed correlation between the subcarrier frequency and frequency of horizontal synchronizing signal. FIG. 1 shows a block diagram of a first embodiment of the present invention. FIG. 2 shows a block diagram of a Y/C separation circuit in the first embodiment. FIG. 3 shows a block diagram of a second embodiment of the present invention. FIG. 4 shows the constitution and characteristic of a band pass filter in the second embodiment. Two preferred embodiments of the present invention are described below. FIG. 1 shows a block diagram of a first embodiment of the invention. An input terminal 11 provides an analog composite video signal to a first A/D converter 12, a first phase locked loop circuit 14, and a timing circuit 16. The first A/D converter 12 operates under an internal system clock signal of 910F H (F H denotes a frequency of horizontal synchronizing frequency). Clamp pulses described below are supplied from the timing circuit 16 to the first A/D converter 12 so that the converter provides a digital composite video signal to a Y/C separation circuit 13. The Y/C separation circuit 13 separates the digital composite video signal from the first A/D converter 12 into a luminance signal Y and a color signal C modulated by a color subcarrier signal. The luminance signal Y is outputted to an output terminal 24. The color signal C is outputted to a first and a second multiplier 20 and 21 described below. The timing circuit 16 separates a horizontal and a vertical synchronizing signal from the analog composite video signal supplied through the input terminal 11. The timing circuit 16 generates: H pulses, synchronized with the horizontal synchronizing signal and having a horizontal period; clamp pulses, which are generated depending on the back porch of the horizontal synchronizing signal; and burst gate pulses, which are generated at the time for extracting a color burst signal included in the analog composite video signal. Fig. 1 shows a second phase locked loop circuit 15 which generates the internal system clock signal of 910F H in frequency, phase-locked to the H pulses sent out from the timing circuit 16. The first phase locked loop circuit 14 operates under both the analog composite video signal supplied through the input terminal 11 and the burst gate pulses supplied from the timing circuit 16, and outputs an analog subcarrier signal. A second A/D converter 17 converts the analog subcarrier signal from the first phase locked loop circuit 14 into a digital subcarrier signal, which is inputted into a delay circuit 18 next to the second A/D converter. The delay circuit 18 delays the digital subcarrier signal by the equivalent of a delay in the Y/C separation circuit 13 and outputs the delayed digital subcarrier signal to a 90° phase shifter 19 and to the first multiplier 20 next to the delay circuit. The 90° phase shifter 19 is a one-sample delay (one-sample delay denotes a 1/910F H delay). The first and the second multipliers 20 and 21 are conventional digital multipliers and multiply the color signal C (modulated by a color subcarrier signal) by above-mentioned digital subcarrier signals. Both first and second multipliers 20 and 21 outputs a demodulated color signal including harmonic components. The output signals of the first and second multipliers 20 and 21 pass through a first and a second low pass filters 22 and 23, respectively, so that color difference signals C₁ and C₂ are outputted to output terminals 25 and 26, respectively. The first and second low pass filters 22 and 23 are conventional digital filters which remove harmonic components included in the output signals of the first and the second multipliers 20 and 21, respectively. The signals C₁ and C₂ correspond to R-Y(I) and B-Y(Q) signals, respectively. The digital color demodulator will now be described in detail. The analog composite video signal is applied to the input terminal 11 with an exemplary property of 75 Ω and 1 Vp-p. The first A/D converter 12 converts the analog composite video signal into the 8-bit digital composite video signal. The first A/D converter 12 includes a low pass filter and a pedestal clamp circuit, which operates under the clamp pulses supplied from the timing circuit 16. The first A/D converter 12 performs sampling by internal system clock signal generated by the second phase locked loop circuit 15 and having a frequency of 910F H . The Y/C separation circuit 13, which is supplied with the digital composite video signal from the first A/D converter 12, is made of a digital filter, for example, shown in FIG.2. The Y/C separation circuit 13 separates the luminance signal Y and the color signal C modulated by the color subcarrier signal, and outputs the luminance signal and the color signal. FIG. 2 shows a terminal 131 to which the digital composite video signal is supplied from the first A/D converter 12, a terminal 132 from which the luminance signal Y is generated, and a terminal 133 from which the color signal C modulated by the color subcarrier signal is generated. FIG. 2 also shows delay lines Z⁻¹ 134 to 137 for (1/910F H ) adders 138, 139, 141, and a positive and a negative half weighting circuits 142 and 140. The delay lines Z⁻¹ and the weighting circuits 140 and 142 are conventional ones. The first phase locked loop circuit 14 operates with both the analog composite video signal supplied from the input terminal 11 and the burst gate pulses supplied from the timing circuit 16, so that the first phase locked loop circuit outputs the analog subcarrier signal phase-locked to the color burst signal. The second A/D converter 17 is supplied with the analog subcarrier signal from the first phase locked loop circuit 14 and outputs the 8-bit digital subcarrier signal. The second A/D converter 17 includes a low pass filter for removing harmonics included in the analog subcarrier signal, an amplifier for amplifying the signal to the dynamic range of the second A/D converter, and a bias circuit for biasing the signal to the center of the dynamic range of the A/D converter. The second A/D converter 17 samples the analog subcarrier signal by using the internal system clock signal outputted by the second phase locked loop circuit 15 and having the frequency of 910F H . The delay circuit 18 delays the digital subcarrier signal to compensate for the delay caused by the signal processing in the Y/C separation circuit 13. The digital subcarrier signal generated by the delay circuit 18 and the color signal C generated by the Y/C separation circuit 13 are multiplied together by the first multiplier 20. The digital subcarrier signal generated by the delay circuit 18 is also supplied to the 90° phase shifter 19 which serves as a one-sample delay to delay the digital subcarrier signal by substantially 90° and then supply the signal to the second multiplier 21. The color signal C separated by the Y/C separation circuit 13 is supplied to the second multiplier 21 as well as the first multiplier 20. Each of the first and the second multipliers 20 and 21 is an 8-bit/8-bit multiplier in the exemplary embodiment. The first and the second multipliers perform orthogonal demodulation with the once delayed digital subcarrier signal from the delay circuit 18, the twice delayed digital subcarrier signal from the 90° phase shifter 19, and the color signal C. The low pass filters 22 and 23, which are conventional digital filters, are connected to the output sides of the first and the second multipliers 20 and 21, respectively, so that the harmonic components included in the output signals of the multipliers and centering about a frequency of 2F SC are removed from the output signals to thereby obtain the color difference signals C₁ and C₂. Thus, the color difference signals C₁ and C₂ are outputted to the output terminals 25 and 26. The outputs from the first and second multipliers 20 and 21 can be changed from the color difference signals R-Y and B-Y into signals I and Q by altering the demodulation axes. The second phase locked loop circuit 15 outputs the internal system clock signal having the frequency of 910F H and phase-locked to the H pulses generated by the timing circuit 16. The internal system clock signal are supplied as drive pulses to the circuits of the digital color demodulator except to the first and the second multipliers 20 and 21 and the first phase locked loop circuit 14. FIG. 3 shows a block diagram of a second embodiment of the present invention. In FIG. 3, like parts and components are designated by the same reference numerals as that in FIG. 1. According to the second embodiment in FIG. 3, the band pass filter 27 of linear phase and symmetric gain characteristic is connected as a digital filter to extract the subcarrier. The set DC bias level of the A/D converter 17 is likely to fluctuate due to the temperature characteristic thereof and a DC component comes into the output 17a from the A/D converter due to the nonlinearity thereof. Besides, a high-frequency noise inevitably comes into the output 17a. The band pass filter is so provided as to prevent the high-frequency noise from coming into the output 17a. FIG. 4(a) shows the constitution of the band pass filter 27 which is a transversal filter comprising four delay elements 71, 72 73 and 74 in series and adders 75 and 76. The clock signal of 910F H in frequency is used in filter 27. The adder 76 is a coefficient adder in which a signal 75a is multiplied by -1/4, a signal 72a is multiplied by +1/2 and the signals added together. An impulse response is (-0.25,0,0.5,0,-0.25). As shown in FIG. 4(b), the band pass filter 27 has the symmetric gain characteristic having a peak at substantially the subcarrier frequency F SC and acts to remove the DC component and the high-frequency noise. The delay circuit 18 connected to the band pass filter 27 functions so that the phase of the C signal separated by the Y/C separation circuit 13 and that of an input signal 18a to the orthogonal demodulation section 120 are matched with each other. According to the present invention, a digital color demodulation system operates with a clock signal having a frequency of 910F H phase-locked to H pulses even if the analog composite video signal does not have a prescribed correlation between the subcarrier frequency and frequency of the horizontal synchronizing signal. For that reason, the number of the samples of one line is 910, so that a correlation perpendicular to picture data can be taken. Since a color difference signal is demodulated by multiplying an A/D-converted digital subcarrier signal and a color signal modulated by the subcarrier signal together in the system, color demodulation can be performed even if a sampling clock is not phase-locked to a color burst signal. Further, a DC component generated in an analog section and an unexpected noise component are removed from the system owing to the band pass filter. The reliability of the digital color demodulator is thus enhanced.

Claims: A demodulator for an analog color composite video signal comprising: timing means (16) for generating, from the analog color composite video signal, H pulses in synchronization with horizontal synchronizing signals of the analog color composite video signal and having a horizontal period, clamp pulses depending on the back porch of the horizontal synchronizing signal, and burst gate pulses from the color burst signal included in the analog color composite video signal; a first phase-locked loop circuit (14) for generating, from the analog color composite video signal and the burst gate pulses, an analog color subcarrier signal in synchronization with the color burst signal; a second phase-locked loop circuit (15) for generating, from the H pulses, an internal system clock signal in synchronization with the horizontal synchronizing signals; first conversion means (12) for converting the analog color composite video signal into a digital composite video signal, the first conversion means including a clamp means responsive to the clamp pulses, the first conversion means performing sampling according to the internal system clock signal; second conversion means (17) for converting the analog subcarrier signal into a digital subcarrier signal, the second conversion means sampling the analog subcarrier using the internal system clock signal; means (13) for separating the digital composite video signal into a luminance signal (Y) and a color signal (C) modulated by a color subcarrier signal, the separation means receiving the composite video signal from the first conversion means (12); first delaying means (18) for delaying the digital subcarrier signal by an amount equal to the amount by which the separation means delayed the luminance and color signals relative to the digital composite video signal, the first delay means (18) being driven by the internal system clock signal; second delaying means (19) for delaying the phase of the once delayed digital subcarrier signal by substantially 90°, the second delay means being driven by the internal system clock signal; first multiplying means (20) for multiplying the color signal by the once delayed digital subcarrier signal; and second multiplying means (21) for multiplying the color signal by the twice delayed digital subcarrier signal. A demodulator as in Claim 1, further comprising: first filtering means (22) for low-pass filtering the output of the first multiply means to produce a first color difference signal; and second filtering means (23) for low-pass filtering the output of the second multiply means to produce a second color difference signal. A demodulator as in Claim 1, further comprising: a band pass filter (27) having a linear phase and a gain characteristic symmetric with regard to substantially the subcarrier frequency, the band pass filter being electrically positioned between the second conversion means (17) and the first delay means (18). A demodulator as in Claim 1, wherein the internal system clock is of 910F H in frequency. A method for demodulating an analog color composite video signal comprising: generating from the analog color composite video signal, H pulses in synchronization with horizontal synchronizing signals of the video signal and having a horizontal period, clamp pulses depending on the back porch of the horizontal synchronizing signal and generating burst gate pulses during the color burst signal included in the analog color composite video signal; generating, from the analog composite color video signal and the burst gate pulses, an analog color subcarrier signal which is phaselocked to the color burst signal; generating, from the H pulses, an internal system clock signal which is phaselocked to the H pulses; converting the analog color composite video signal into a digital composite video signal under control of the internal system clock signal and the clamp pulses, the analog color composite signal being sampled according to the internal system clock signal; converting the analog subcarrier signal into a digital subcarrier signal, the analog subcarrier being sampled according to the internal system clock signal; separating the digital composite video signal into a luminance signal and a color signal modulated by a color subcarrier signal; delaying the digital subcarrier signal by an amount equal to the amount by which separating the luminance and color signals delayed those signals relative to the original digital composite video signal, the delaying being performed in response to the internal system clock signal; delaying the phase of the delayed digital subcarrier signal by substantially 90°, the delaying being performed in response to the internal system clock signal; multiplying the color signal by the once-delayed digital subcarrier signal to produce a first demodulated signal; and multiplying the color signal by the twice-delayed digital subcarrier signal to produce a second demodulated signal. A method as in Claim 5, further comprising: low-pass filtering the first demodulated signal to produce a first color difference signal; and low-pass filtering the second demodulated signal to produce a second color difference signal. A method as in Claim 5, further comprising band pass filtering the digital subcarrier signal prior to delaying the signal, the band pass filter transfer function having a linear phase and a gain characteristic symmetric with regard to substantially the subcarrier frequency. A method as in Claim 5, wherein the internal system clock signal is of 910F H in frequency.

Inventors: KOBAYASHI REIICHI, KOBAYASHI, REIICHI
Applicants: NIPPON DENKI HOME ELECTRONICS, NEC HOME ELECTRONICS LTD.
Application year: 1987
Main classification: H04N9
IPC codes: H04N9