Micro processor capable of being connected with coprocessor

Abstract: A micro processor capable of being connected with a coprocessor is disclosed. The micro processor including an execution unit and a bus control unit coupled to the execution unit. When the execution unit receives an instruction to be executed by the coprocessor, the bus control unit supplies to the coprocessor a command code responsive to the instruction. The micro processor further includes a terminal connected to the execution unit and supplied with a busy signal representing that the coprocessor is in an arithmetic operating state. The execution unit controls the bus control unit to read status information of the coprocessor after the busy signal disappears. The presence or absence of the coprocessor is thus detected from the content of the read status information.

Description: The present invention relates to a microprocessor capable of being coupled to a coprocessor, comprising an execution unit executing instructions from a program, a bus control unit, coupled to said execution unit and controlling an address bus and a data bus to initiate a bus cycle for reading or writing data, and a terminal connected to said execution unit, said terminal being supplied with a busy signal which takes a first or a second logic level under control of said coprocessor, when said coprocessor is coupled to said microprocessor, said first logic level representing that said coprocessor is in an arithmetic operable state and said second logic level representing that said coprocessor is not in the arithmetic operating state. The US patent US-A- 4 547 849 shows a microprocessor with a MATCH-PRESENT FLAG, which tells the microprocessor whether or not a coprocessor is present in the system. If no coprocessor is present a EMULATION FLAG tells the microprocessor whether or not software emulation of ESC-instructions has to take place. The ESC-instructions have to be executed by the coprocessor. That is, when this microprocessor encounters the ESC-instructions, first the content of the MP-flag is checked for detecting whether the coprocessor is present in the system or not, then the content of the MP-flag is checked. This procedure is called EMULATION TEST and is always performed each time the microprocessor encounters the ESC-instructions. The microprocessor treats the ESC-instructions as one of eight different categories, each of which defines the sequence of operations to be performed by the microprocessor. In every category the emulation test is listed as the first operation. Therefore, whenever the microprocessor encounters an ESC-instruction, it always performs at first the emulation test, irrespective of the category thereof. In the emulation test, the MP-flag is checked to detect the presence or absence of the coprocessor and then the EM-flag is checked, if the MP-flag indicates the absence of the coprocessor. When the MP-flag tells the presence of the coprocessor on the other hand, a busy signal and an error signal are checked and a command code representative of the ESC-instruction is sent to the coprocessor, if necessary. According to this prior art the microprocessor has to execute the emulation test with checking the content of the MP-flag irrespective of presence of the coprocessor. For this reason the executing time of the high level instruction is prolonged to lower the arithmetic speed. Moreover, in a case where a plurality of coprocessors are required, a plurality of flags corresponding to the respective coprocessors are necessitated to enlarge a hardware of the microprocessor. In the IEEE-MICRO, vol. 6, no. 2, April 1986, pages 29-46, IEEE, New York, there is disclosed a microprocessor which is allowed to monitor the condition of the coprocessor. Therefore an object of the present invention is to provide an improved microprocessor capable of being connected with a coprocessor. Another object of the present invention is to provide a microprocessor which can detect presence or absence of coprocessor without employing a flag. A further object of the present invention is to produce a new control system between a microprocessor and a coprocessor. A microprocessor according the present invention as mentioned above is characterized in that, said terminal is fixed at said second logic level when said coprocessor is absent, that said bus control unit initiates, whether or not said coprocessor is absent, a first bus cycle for supplying said coprocessor with a command code representative of an instruction to be executed by said coprocessor, and that said execution unit detects the level at said terminal after said bus cycle for supplying said command code is initiated, commands said bus control unit to initate a second bus cycle for reading status information of said coprocessor therefrom when said terminal is detected to be at said second level and thereafter checks information obtained by said second bus cycle. Other aspects and features of the microprocessor according the present invention are specified in the enclosed subclaims 2 to 4. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be more apparatus from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a block diagram representative of an embodiment of the present invention; Fig. 2 is a flow chart representative of an operation of a master processor shown in Fig. 1; Fig. 3 is a timing chart representative of the operation shown in Fig. 2; Fig. 4 is a block diagram representative of a modified example of the embodiment shown in Fig. 1; Fig. 5 is block diagram representative of another embodiment of the present invention; Fig. 6 is a flow chart representative of an operation of a master processor shown in Fig. 5; Fig. 7A and 7B are timing charts representative of the operation shown in Fig. 6; and Fig. 8 is a block diagram representative of a modified example of the embodiment shown in Fig. 5. DETAILED DESCRIPTION OF THE EMBODIMENTS Referring to Fig. 1, there are shown a master processor 10 as a CPU, a slave processor 30 as a coprocessor, and a memory 20. The slave processor 30 operates under the control of the master processor 10 and executes at a high speed high level instructions such as a floating-point arithmetic operation, a function arithmetic operation, etc., in place of the master processor 10. The memory 20 is accessed by the master processor 10 and stores data and a program including low level instructions and high level instructions. The master processor 10, the memory 20 and the slave processor 30 are interconnected via an address bus 40 and a data bus 50. The master processor 10 includes an instruction decoder unit 11 decoding instructions which are executed by the master processor 10 and the slave processor 30, an execution unit 12 controlling the whole operation of the master processor 10 and executing instructions under the micro program control, an effective address calculation unit 13 calculating an effective address of each operand of the respective instructions, and a bus control unit 14 controlling the address bus 40 and the data bus 50 to access the memory 20 and the slave processor 30, these units 11 to 14 being coupled as shown via internal bus lines. The bus control unit 14 supplies a bus cycle signal BC of a high level to the execution unit 12 via a line 16 when it transfers command information of the instruction to be executed by the slave processor 30 to the data bus 50. The master processor 10 further includes a terminal 15 connected to the execution unit 12 and supplied with a busy signal BS which will be described later. The slave processor 30 includes an arithmetic unit 31 performing an arithmetic operation of the high level instructions, a command port 32 receiving via the data bus 50 command codes of the instructions executed by the slave processor 30, a status port 33 receiving the status of the arithmetic unit 31 and outputting them to the data bus 50, an operand port 34 receiving via the data bus 50 data necessary to the arithmetic operation of the unit 31 and outputting the arithmetic result to the data bus 50, and an address decoder 15 receiving address information via the address bus 40 and selecting one of the ports 32, 33 and 34 in response thereto, these units 31 to 35 being coupled as shown via internal bus lines. The slave processor 30 further includes an output terminal 37 and an N-channel MOS transistor 36 of an open-drain type. The source-drain path of the transistor 36 is connected between the terminal 37 and a ground and the gate thereof is connected to the arithmetic unit 31. The terminal 37 of the slave processor 30 is connected via a line 61 to the terminal 35 of the master processor 10. The line 61 is pulled up to a power voltage Vcc via a resistor 60. The arithmetic unit 31 of the slave processor 30 supplies a high level to the MOS transistor 36 during a time period when the unit 31 is in the arithmetic operating state to turn the transistor 36 ON. Thus, the slave processor 30 produces the busy signal BS of a low level which is in turn supplied to the execution unit 12 of the master processor 10 via the terminal 15. The transistor 36 is in a non-conductive state except an arithmetic operating period of the unit 31, so that the busy signal BS takes the high level. In other words, the slave processor 30 does not produce the busy signal BS. Referring to Fig. 2, there is shown a flow chart representative of an operation of the execution unit 12 in a case where the instruction decoder unit 11 decodes the instruction to be executed by the slave processor 30. This flow chart indicates a dyadic operation of "A+B → B". When the data of first and second operands A and B are stored in the memory 20, the execution unit 12 prompts the bus control unit 14 to read out the data of the first and second operands A and B from the memory 20 and to store them into the operand port 34 of the slave processor 30 (steps 201 and 202). Thus, the bus control unit 14 controls the address and data buses 40 and 50 and writes the data of the first and second operands A and B into the operand port 34. If the operands A and B are registers (not shown) in the slave processor 34, the steps 201 and 202 is not carried out. Thereafter, the execution unit 12 supplies to the bus control unit 14 a command code inputted from the instruction decoder unit 11 and prompts the unit 14 to supply it to the command port 32 (step 203). In response to this prompt, the bus control unit 14 transfers the command code on the data bus 50 and the address information of the command port 32 on the address bus 40, as shown in Fig. 3. The command code on the data bus 50 is thus written into the command port 32. During this bus cycle period, the bus control unit 14 supplies the bus cycle signal BS of the high level shown in Fig. 3 to the execution unit 12 via the signal line 16. As a result, the execution unit 12 is brought into a standby condition until the bus cycle signal BS changes to the low level, i.e. until the write operation of the command code into the command port 32 is completed (step 204). In response to the change of the bus cycle signal BC from the high level to the low level, the execution unit 12 checks the level of the busy signal BS supplied via the terminal 15 to detect whether or not the arithmetic operation by the unit 31 is completed (step 205). If the slave processor 30 is absent, the terminal 15 is pulled up to the high level by the resistor 60. That is, the busy signal BS takes the high level. Therefore, the execution unit 12 regards the arithmetic operation by the unit 31 as being completed and prompts the bus control unit 14 to read status information of the status port 33 (step 206). The bus control unit 14 transfers the address information of the status port 33 to the slave processor 30 via the address bus 40 and reads the status information stored therein which is in turn supplied to the execution unit 12 via the data bus. The execution unit 12 judges the content of the read-out status information (step 207). Since the slave processor 30 is absent and since each bit line of the data bus is pulled up or pulled down, all of the bits of the read-out status information are "1" or "0". Namely, the content of the status information takes an abnormal value. As a result, the execution unit 12 detects the absence of the slave processor 30 and executes the instruction to be executed by the slave processor 30 by itself, as represented as a slave processor absence operation (step 208). The execution unit 12 is not equipped with a function similar to the arithmetic unit 31, and therefore various low level instructions should be combined to execute the high level instruction, so that a processing time is prolonged. When the slave processor 30 is coupled to the master processor 10, as shown in Fig. 1, the unit 31 executes the arithmetic operation of the data between the first and second operands A and B stored in the operand port 34 in response to the command code supplied from the command port 32 and further supplies the high level to the transistor 36, which is thereby turned ON to change the busy signal BS to the low level, as shown in Fig. 3. Accordingly, the execution unit 12 receives the low level busy signal BS in response to the change of the bus cycle signal BS from the high level to the low level and thus regards the arithmetic unit 31 as being arithmetic operating state to inhibit the slave processor 30 from being accessed. The address and data buses 40 and 50 are thus brought into a free state. Although the execution unit 12 takes a standby condition in the flow chart shown in Fig. 2, since the buses 40 and 50 are free, the execution unit 12 may prefetch instructions from the memory by make use of buses 40 and 50 or peripheral units (not shown) may use the buses 40 and 50. The execution unit 12 cyclically checks the level of the busy signal BS. When the arithmetic operation by the unit 31 is completed, the unit 31 stores the status information and the arithmetic result into the status port 33 and operand port 34, respectively. The arithmetic unit 31 further supplies the low level to the transistor 36 to turn it OFF. The busy signal BS is thus changed to the high level by the pull-up resistor 60, as shown in Fig. 3. As a result of detecting the high level busy signal BS, the execution unit 12 regards the arithmetic unit 31 as completing its arithmetic operation and prompts the bus control unit 14 to read the status information (step 206). Thus, the bus control unit 14 supplies the address information of the status port 33 to the slave processor 30 via the address bus 40 and reads out the status information from the status port 33 via the data bus 50, as shown in Fig. 3. The read-out status information is judged by the execution unit 12 (step 207). If the status information includes arithmetic exception data representative of overflow or zero-divisor, the execution unit 12 performs an error representation as a slave processor arithmetic exception operation 210. When the status information does not include the abnormal value and the arithmetic exception, the execution unit 12 prompts the bus control unit 14 to read out the arithmetic result (step 209). As a result, the bus control unit 14 supplies the address information of the operand port 34 to the slave processor 30 via the address bus 40 and the arithmetic result stored in the operand port 34 is read out and then transferred to the data bus 50. Since the absence of the slave processor 30 is detected by reading and judging the content of the status information of the status port, the master processor 10 does not require a flag representative of presence or absence of the slave processor 30. Moreover, the reading of the status information is carried out only when the busy signal takes information representative of completion of an arithmetic operation of the unit 31, and therefore the buses 40 and 50 are not occupied with reading the status information. Referring to Fig. 4, a plurality of slave processors (three processors in the drawing) 30-1, 30-2 and 30-3 are coupled to the master processor 10 via the address and data buses 40 and 50. Each of the slave processors 30-1 to 30-3 has the same construction as that shown in Fig. 1, and busy signal output terminals 37-1 to 37-3 thereof are connected in common to the terminal 15 of the master processor 10 via the line 61. Since each port of the respective slave processors 30-1 to 30-3 is assigned to an individual address space, only one of the ports among the slave processors 30-1 to 30-3 is accessed by the address information produced by the master processor 10. Since each of the slave processors 30-1 to 30-3 includes a transistor of an open-drain type (transistor 36 in Fig. 1), the busy signal BS is controlled by one of the slave processors 30-1 to 30-3 which is in an arithmetic operating state. Thus, the master processor 10 can control a plurality of slave processors 30-1 to 30-3 in the same manner as described hereinbefore. In the above-mentioned embodiment, the status information of the slave processor 30 is always read out. However, when the status information does not include the abnormal information and the arithmetic exception information, the reading of the status information is not necessary. That is, the arithmetic result can be read from the slave processor without reading the status information. The processing time of the high level instruction is thereby further shortened. For this purpose, as shown in Fig. 5 as another embodiment of the present invention, a master processor 70 is provided with a second input terminal 17 coupled to the execution unit 12 and a slave processor 80 is provided with a second N-channel MOS transistor 38 of an open-drain type and a second output terminal 39. The terminals 17 and 39 are connected to each other via a signal line 63 which is in turn pulled up to the power voltage Vcc via a resistor 62. The drain-source path of the transistor 38 is connected between the terminal 39 and the ground and the gate thereof is connected to the arithmetic unit 31. The unit 31 supplies the high level to the transistor 38 at the end of the arithmetic operation when the necessity of reading the status information does not occur, i.e. when the arithmetic exception and flag updating do not occur as a result of the arithmetic operation. The transistor 38 is thereby turned ON to change the line 63 to the low level. The level of the line 63 is supplied via the terminal 17 to the execution unit 12 as a status read request signal STRD. A detailed description of a circuit operation will be made below with reference to a flow chart shown in Fig. 2 and timing charts shown in Figs. 7A and 7B. The flow chart of Fig. 2 also indicates a dyadic operation of "A+B → B". Steps 601 to 605 correspond respectively to the steps 201 to 205, and therefore the description thereof is omitted. When the execution unit 12 detects the high level of the busy signal BS, it catches the status read request signal STRD supplied from the terminal 17 to detect the level thereof. Assuming that both of the arithmetic exception and flag updating do not occur, the arithmetic unit 31 supplies the high level to the transistor 38 at the end of the arithmetic operation. The transistor 38 is thereby turned ON to change the status read request signal STRD to the low level, as shown in Fig. 7A. Therefore, the execution unit 12 receives the low level signal STRD. As a result, the execution unit 12 prompts to the bus control unit 14 to read the arithmetic result without reading the status information of the slave processor 80 (step 612). Thus, the bus control unit 14 supplies the address information of the operand port 34 to the slave processor 80 via the address bus 40 and reads out the arithmetic result stored in the port 34 via the data bus 50, as shown in Fig. 7A. The processing time of the high level instruction is thereby made short. In contrast, when the arithmetic exception or flag updating occurs, the arithmetic unit 31 does not turn the transistor 38 ON. The status read request signal STRD is thereby maintained at the high level, as shown in Fig. 7B. Since the execution unit 12 receives the high level signal STRD, it prompts the bus control unit 14 to read the status information (step 607). Thus, the bus control unit 14 supplied the address information of the status port 33 to the slave processor 80 via the address bus 40 and reads out the status information stored therein via the data bus 50, as shown in Fig. 7B. The execution unit 12 judges the content of the read-out status information (step 608). When the status information contains the arithmetic exception data, the execution unit 12 carries out a slave processor arithmetic exception operation which has been described hereinbefore (step 610). In a case where the status information contains flag updating data, the execution unit 12 updates the content of the associated one of flags 18 (step 609). The updated flag is used for a branch operation or a subroutine procedure, for example. Thereafter, the execution unit 12 prompts the bus control unit 14 to read the arithmetic result (step 612). If the slave processor 80 is absent, both of the busy signal BS and the status read request signal STRD are maintained at the high level. All of the bits of the read-out status information take "1" or "0". As a result, the execution unit 12 executes a slave processor absence operation (step 611) which has been mentioned above. Since the bus cycle for reading the content of the status port 33 can be omitted by use of the status read request signal STRD, the execution time of the high level instruction is further shortened. Referring to Fig. 8, the master processor 70 is connected with a plurality of slave processors (three processors in the drawing) 80-1, 80-2 and 80-3 each having the same construction as that shown in Fig. 5. The busy signal output terminals 37-1, 37-2 and 37-3 of the slave processors 80-1 to 80-3 are connected in common to the terminal 15 of the master processor 70 via the line 61, and the status read request signal output terminals 39-1 to 39-3 are connected in common to the terminal 17 via the line 62. Since the respective ports of the slave processors 80-1 to 80-3are assigned to respective address spaces, the master processor 70 can control individually these slave processors 80-1 to 80-3.

Claims: A microprocessor (10, 70) capable of being coupled to a coprocessor (30, 80), the microprocessor comprising an execution unit (12) executing instructions of a program, a bus control unit (14) coupled to said execution unit and controlling an address bus (40) and a data bus (50) to initiate a bus cycle for reading or writing data, and a terminal (15) connected to said execution unit, said terminal (15) being supplied with a busy signal (BS) which takes a first or a second logic level under control of said coprocessor (30, 80) when said coprocessor is coupled to said microprocessor, said first logic level representing that said coprocessor is in an arithmetic operating state and said second logic level representing that said coprocessor is not in the arithmetic operating state, characterized in that said terminal (15) is fixed at said second logic level when said coprocessor is absent, in that said bus control unit (14) initiates, whether or not said coprocessor (30, 80) is absent, a first bus cycle for supplying said coprocessor (30, 80) with a command code representative of an instruction to be executed by said coprocessor (30, 80) and in that said execution unit (12) detects the level at said terminal (15) after said bus cycle for supplying said command code is initiated, commands said bus control unit (14) to iniate a second bus cycle for reading status information of said coprocessor (30, 80) therefrom when said terminal (15) is detected to be at said second level and thereafter checks information obtained by said second bus cycle. The microprocessor as claimed in claim 1, characterized in that said bus control unit (14) supplies said execution unit (12) with a bus cycle signal (BC) representing that said first bus cycle is being performed, and that said execution unit (12) detects the level at said terminal (15) when said bus cycle signal (BC) disappears. The microprocessor as claimed in claim 1 or 2, characterized in that said microprocessor further comprises an additional terminal (17) connected to said execution unit (12), said additional terminal (17) being supplied with a status read request signal (STRD) which takes an active or an inactive level under control of said coprocessor (30, 80) when said coprocessor is coupled to said microprocessor and being fixed at said active level when said coprocessor is absent, said active level representing that the status information of said coprocessor is needed to be checked by said microprocessor and said inactive level representing that the status information of coprocessor is not needed to be checked by said microprocessor, and that said execution unit (12) commands said bus control unit (14) to initiate said second bus cycle when said additional terminal (17) is detected to be at said active level after said terminal (15) is detected to be at said second logic level. The microprocessor as claimed in claim 3, characterized in that said execution unit (12) commands said bus control unit (14) to initiate a third bus cycle for reading arithmetic result data from said coprocessor (30, 80) when said additional terminal (17) is detected to be at said inactive level after said terminal (15) is detected to be at said second logic level.

Inventors: NAKAYAMA TAKASHI C O NEC CORPO, NAKAYAMA, TAKASHI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1987
Main classification: G06F9
IPC codes: G06F9