PROCESS FOR FORMING MOS INTEGRATED CIRCUIT DEVICES

Abstract: A process for forming LDD (lightly doped drain) MOS structures includes the steps of forming a thin (150-200 nm) amorphous silicon or polysilicon layer (13) over the device active areas, forming a mask (14) over the silicon layer (13), subjecting the structure to a high energy implant dose, etching the silicon layer (13) to a predetermined distance beneath the mask (14) to form a gate electrode (19), removing the mask (14), subjecting the structure to a low energy implant dose, and applying a thermal drive-in cycle to form source and drain regions (25) and associated LDD regions (22). A tungsten shunt layer (29) is selectively deposited over the silicon gate electrode. The process is simple and amendable to the formation of guard band structures (24) and gate sidewall oxide spacers (27, 31).

Description: PROCESS FOR FORMING MOS INTEGRATED CIRCUIT DEVICES Technical Field This invention relates to processes for forming MOS integrated circuits on a substrate having device active regions. Background Art With the increasing implementation of small geometry, highly dense MOS monolithic integrated circuit components, various structural and operational problems have combined to limit device performance and manufacturing yields and, thus, the achievable minimum features sizes and maximum densities. Among the most difficult of the problems are those collectively termed short-channel effects, which include hot carrier injection into the gate oxide and/or substrate, source- drain punch-through, reduced breakdown voltage and impact ionization. In hot carrier injection, for example, electrons are permanently injected into the gate oxide by the strong electric field which is created by the narrow channel region adjacent ~ tfϊe ~" drain and, as a consequence, alter the threshold voltage of. the device. In addition to the short-channel effects, overlap between the gate electrode and the source and drain results in parasitic capacitance known as Miller capacitance, which decreases high frequency response and operational speeds. As channel lengths and other device dimensions are reduced in VLSI monolithic integrated circuits, new device structures such as LDD structures have been implemented to reduce the shoft-channel effects and to optimize transistor characteristics such as high transconductance, high breakdown voltage, fast operating speeds and device densities. The LDD structure is a shallow, preferably self-aligned n~ or p ~ region formed between the MOSFET channel and the n + or p+ source and drai diffusions. Except when bidirectional current is used, the LDD structure is needed only for the drain, not the source, but LDD structures are typically formed for both the source and the drain diffusions to avoid the use of an additional masking step. The LDD structure increases breakdown voltage and reduces impact ionization and hot electron emission by spreading the high electric field at the drain pinch-off region into the associated n- or p " region. Ogura et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field Effect Transistor", IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, pp. 1359-1367, August 1980, describes LDD device design and characteristics and, in pertinent part, describes a conventional planar silicon gate processing technique for LDDFETS. After forming the field oxide and gate oxide, an oversized gate stack comprising the poly gate and an overlying oxide-nitride mask is formed and used as a mask during implanting of the n+ source and drain through- the gate oxide layer. A wet etch or plasma etch is then applied--to undercut the gate to its final dimension, then the oxide-nitride mask is stripped and an n- implant is applied to form the LDD regions self-aligned with the channel and the n+ source/drain diffussions. U.S. Patent No, 4,198,250 discloses a process wherein a silicon dioxide gate overhang mask is formed and an n+ implant step is used to implant the n- LDD structure through the gate oxide layer. The oxide overhang mask is defined by wet chemical undercutting of the supporting doped polysilicon gate to the desired gate dimensions beneath the mask, then the n+ source/ drain implant is applied. During the n+ implantation, the overhang mask partially blocks the ions so that the implant also forms shallow, lightly doped n- LDD regions self- aligned with the channel and the n+ source and drain regions. Disclosure of the Invention It is an object of the present invention to provide a process for forming MOS integrated circuits, whereby a self-aligned LDD (lightly doped drain) structure can be provided in a simple manner. Therefore, according to the present invention, there is provided a process for forming a MOS integrated circuit on a substrate having device active regions, characterized by the steps of: forming a silicon layer which is approximately 150 - 200 nanometers thick over the device active regions, forming a mask over said silicon layer having edge boundaries defining edge boundaries of source and drain regions, subjecting the structure to a relatively high energy implant dose adapted to penetrate said silicon layer to form relatively highly doped implants in the surface-adjacent substrate regions of said source and drain regions; etching said silicon layer in the presence of said mask to pattern the silicon to a gate electrode of selected lateral dimensions recessed a predetermined distance beneath said edge boundaries of. said mask; removing said mask; subjecting the structure to a relatively low energy implant of the same conductivity type as said energy implant to form lightly doped implants self-aligned with said source and drain regions and said gate electrode; and applying a thermal cycle to activate the implanted species and drive-in the implanted species to form said source and drain regions and lightly doped regions associated therewith. Brief Description of the Drawings Embodiments of the present invention will now be described by way of example, with reference to the accompanying drawings, in which: Figs. 1-7 are schematic cross-sectional representation of an n-LDD MOSFET taken sequentially during the major processing steps illustrating the sequence for forming LDD structures (and optional guard band structures, sidewall oxide spacers and self- aligned contacts); and Fig. 8 depicts a pertinent process step of a different process sequence. Best Mode for Carrying Out the Invention Fig. 1 is a schematic cross-sectional representation of the front-end processing stage of an NMOS integrated circuit, taken at the point of implementing the critical steps of the present invention. For simplicity, each of the four figures shows a single MOS active region 15 of a monolithic integrated circuit. The starting structure typically comprises <100>, p-type or n-type (for n-channel or p-channel devices, respectively} single crystal silicon substrate 10 having a resistivity of about 1 to 20 ohm centimeters. Epitaxial material could also be used. At this stage in the front end processing, an isolation structure such as field oxide 11 has been formed in substrate 10, preferably partially or entirely recessed within the- substrate, followed by the formation of a gate oxide 12 and field and channel implants (not shown). Typically, the field oxide 11 is about 600 - 850 nanometers thick and is formed by thermal oxidation of the silicon substrate. The gate oxide 12 can be about 25 - 75 nanometers thick and is also formed by oxidation of the silicon substrate. Those of skill in the art will readily implement the steps necessary to provide the structure of Fig. 1 and will understand that these process parameters and dimensions, as well as those described below, are given by way of example only and can be varied to achieve the desired structure as well as modifications which are within the scope of the invention. Next, and referring further to Fig. 1, a thin layer of typically phosphorus doped polycrystalline silicon or, possibly, doped amorphous silicon, 13 is deposited over the gate and field oxide structure to a nominal thickness of about 150 - 200 nanometers using an LPCVD process (low pressure chemical vapor deposition) and an SiH4 gas system. Use of an amorphous silicon layer reduces occurrence of channeling of implanted ions and will result in a shallower distribution of deposit along in the source/drain areas, most importantly in the case of boron. An etchant- and implant- mask 14 is then formed above the gate electrode location. Specifically, the lateral dimensions of the mask are selected so that sides 16-16 thereof define the boundaries of the subsequently formed n+ or p+ source and drain regions. The mask 14 can be a photoresist layer which is deposited and delineated using conventional photolithographic techniques. The desired thickness of the subsequently- patterned gate electrodes/conductors determines the as- deposited thickness of polysilicon layer 13. If the n + or p + source/drain implant through the silicon requires a different, smaller thickness, the poly is etched to the desired thickness outside the confines of mask 14. Preferably, a directional dry etch technique is used. One suitable process is reactive ion etching using a C2CIF5/SF5 gas system. The resulting thickness, shown in phantom as layer 9, is determined by the particular implantation process and the desired source/drain doping profile. Normally, it is unnecessary. Next, referring still further to Fig. 1, the structure is subjected to an n + or p + implant in the presence of the oversized photoresist mask 14 to deposit the source and drain regions. The chosen implant energy is sufficiently high so that the arsenic or phosphorus (or boron) ions penetrate the thin silicon layer 13 (or 9) and the gate oxide 12, and are embedded in substrate 10 at a shallow depth generally designated as surface-adjacent region 17. The implant beam current is selected to provide a heavy doping level in the surface adjacent region 17. The inside boundaries of the n + or p + source/drain regions 17-17 are precisely aligned by the edges 16-16 of the photoresist mask 14. For example, for a silicon layer 13 which is 200 nanometers thick, a boron implant energy of 80 keV and dose of 5E15-1E16 cm "2 provides a p + layer 17 of about 2 x 10^^ cm "3 concentration at an initial junction depth of 40-60 nanometers. Similarly, for a 200 nanometers silicon layer 13, a phosphorus implant of 190 keV, and 5E15-1E16 cm -2 provides approximately a 2 x 10 19 cm "3 n + layer 17 at an initial XJ of about 50 nanometers. Next, referring to Fig. 2, the silicon layer 13 is etched in the presence of the oversized mask 14 to remove the layer 13 outside the boundaries of the mask and continued to undercut the silicon a predetermined distance beneath the mask. An isotropic etch or a combination of anisotropic and isotropic processes may be used. One suitable process is a wet chemical etch using a diluted concentration of nitric acid, hydrofluoric acid and acetic acid in water. One suitable dry etch is reactive ion etching using an SF5 gas system. Using these etching techniques, the photoresist 14 is preserved and provides"precise pattern definition of the silicon, while the underlying oxide 12 serves as an etch barrier to protect the silicon substrate 10. As one example of dimensions, the oversized photoresist mask 14 is 1.5 micrometers wide and the plasma etch process is used to overetch/undercut the silicon layer 0.2 - 0.3 micrometers from each side to align each gate edge 21 with the inner edge of LDD regions 18. Alternatively, the silicon layer is overetched/undercut about 0.4 micrometers on each side of the mask 14 to provide a gate electrode 19 which is 0.7 micrometers wide, and which has resulting sides 21-21 which precisely locate the subsequent LDD implant relative to the channel between the n + source/drain regions. Referring to Fig. 3, the next step is to remove the photoresist mask 14, using any of several techniques such as an oxygen plasma ashing, a wet chemical resist strip using concentrated sulfuric acid and hydrogen peroxide, or an ultrasonic acetone bath. The gate oxide layer 12 may then be lightly etched, as by applying buffered hydrofluoric wet acid etchant, for the purpose of controlling the thickness of the oxide layer, in the event the LDD implantation requires a lesser level of partial masking by the gate oxide layer. Referring further to Fig. 3, the structure is then subjected to a low energy blanket implant (phosphorus 30 keV, or arsenic at 70 keV and 5Ξ13 cm -2 ; or boron at 20 keV and 5E13 cm -2 ) to complete the formation of the n~ or p ~ LDD impurity concentrations regions 18 self-aligned with the respective n + or p + source and drain impurity concentration regions 17, and a medial channel region 23 defined by the gate electrode boundaries 21-21. As an option, a 5E13 cm -2 dose, low energy (typically 50 keV for boron, 75 keV for phosphorus), opposite conductivity implant can be implemented to form p- or n- guard band structures 24 (see Fig. 4) about the respective n- or p- LDD regions 22 self- aligned with the respective n + or p + source/drain regions 25 and the gate electrodes 19, and to a deeper junction depth (following the anneal/drive-in) than the corresponding LDD regions 22. Referring to Fig. 4, the structure in Fig. 3 is shown following an anneal cycle (for example, at 900 degrees C for 0.5 hours in nitrogen) to anneal implant damage, activate the implanted species, drive-in all implants to a desired junction depth, and form silicon crystals in the gate electrode 19 layer if amorphous silicon was initially utilized. For the above- described exemplary conditions and parameters, the resulting n + and p + source/drain junction depths are in the range of 0.2 - 0.3 micrometers. As shown schematically in the figure, the resulting guard band layers 24 extend to a slightly greater depth than the LDD structures 22. As a result, the guard band structures keep the electric field lines from extending into the channels and thereby allow the use of higher electric fields and/or smaller device dimensions. In short, the guard bands enhance the action of the LDD structures in suppressing short channel effects, with little or no increase in gate overlap and the associated Miller capacitance. It will be appreciated that during the anneal cycle, the initial aligned LDD regions do not diffuse to the extent that the highly doped ' regions do, so that initial lightly doped drain alignment is preserved during the anneal and/or other high temperature processing. Those of skill in the art will appreciate that the use of subsequent high temperature process steps can be used to supplement or replace the anneal step in providing the desired anneal, activation and drive-in functions. The process can also include the formation of sidewall dielectric structures. Referring to Fig. 5, in a preferred sequence of forming sidewall oxidation, a layer 26 of CVD silicon dioxide is conformally deposited on the structure of Fig. 4 (after the removal of mask 14, and after the LDD and guard band implants and the annealing step) * A suitable CVD gas system is silane/oxygen at atmospheric or reduced pressure with or without RF plasma excitation. A typical thickness of layer 26 is about 80 - 100 nanometers. As shown in Fig. 6, the oxide layer 26 is then etched using directional techniques such as reactive ion etching and an etchant gas mixture of equal parts C2F5 (Freon 116) and CHF3, to remove the oxide from horizontal surfaces and leave intact the 80-100 nanometer thick sidewall spacers 27-27. If the surfaces of areas defined by source/drain and LDD regions 22 and 25 are to remain masked by residuals of gate oxide 12, the end point of the etch will have to be responsive to the exposure of silicon gate electrode 19 surface, designated 28. The next steps of the present embodiment are completed by selective deposition of a shunt layer 29, such as selectively deposited tungsten on surface 28 of the silicon electrode 19. See Fig. 7. Standard processing can then be employed to complete the monolithic FET integrated circuit, including forming contacts in the interlayer dielectric to the underlying conductors, and forming metallization contacting the conductors via the contact cuts, followed by passivation. If gate electrode or interconnect silicon resistance is not a serious concern, it may be possible to overlook the use of a metal or silicide shunting layer over the thin silicon layer. The process is also readily varied to incorporate sidewall thermal oxide spacers 31 rather chan CVD spacers 27. Here, and as shown in phantom in Fig. 1, a silicon nitride masking layer 30 is formed on the polysilicon 13 beneath and congruent with the resist mask 14. Typically, the nitride mask is formed to a thickness of about 40 nanometers on the polysilicon by chemical vapor deposition, then is etched using the resist mask 14 as the etch mask. The process then proceeds the same as before through the Fig. 3 removal of the photoresist mask 14, the LDD implant and the optional guard band implant in Fig. 3. Referring to Fig. 8, prior to the implant anneal and activation, the structure is heated at a relatively low temperature (typically 850 degrees C) in an oxidizing steam ambient. This selectively forms sidewall oxide spacers 31 approximately 200 nanometers thick on the sidewalls of gate electrode 19. In addition, the thermal oxidation step partially performs the implant anneal, that is, partially drives-in and activates the implanted n + and/or p + regions. The structure after the thermal oxidation and subsequent anneal is shown in Fig. 8. The steps of the present invention are then completed as described previously by selective deposition of a shunt layer 29 of tungsten on the silicon conductor 19. See generally Fig. 7. Standard processing can then be employed to complete the monolithic FET integrated circuit. Any high temperature processing steps subsequent to the sidewall thermal oxidation step and the anneal are used in combination with these two steps to establish the n + or p + junction depths. As described, the present process normally eliminates an initial silicon etch step, provides controlled, shallow implantation through a thin silicon layer, and permits reduced device size due to the use- of lightly doped drain structures which are formed by blanket implant of light dose. Both Miller capacitance and short-channel effects are reduced. In addition, the controlled implantation of boron or boron-bearing species using a thin silicon layer eliminates the need for very expensive high dose silicon amorphizing implant sequences, which use a high energy silicon ion pre-amorphizing step in conjunction with boron implantation and an anneal to provide high dose boron implants without channeling. As described, the present process is applicable to NMOS, PMOS, and with nominal extension to CMOS structures.

Claims: CLAIMS 1. A process for forming a MOS integrated circuit on a substrate having device active regions, characterized by the steps of: forming a silicon layer (13) which is approximately 150 - 200 nanometers thick over the device active regions; forming a mask (14) over said silicon layer (13) having edge boundaries (16) defining edge boundaries of source and drain regions (25); subjecting the structure to a relatively high energy implant dose adapted to penetrate said silicon layer to form relatively highly doped implants in the surface-adjacent substrate regions of said source and drain regions (25); etching said silicon layer (13) in the presence of said mask (14) to pattern the silicon to a gate electrode (19) of selected lateral dimensions recessed a predetermined distance beneath said edge boundaries (16) of said mask (14), removing said mask (14); subjecting the structure to a relatively low energy implant of the same conductivity type as said high energy implant to form lightly doped implants self-aligned with said source and drain regions and said gate electrode (19); and applying a thermal cycle to activate the implanted species and drive-in the implanted species to form said source and drain regions (25) and lightly doped regions (22) associated therewith. 2. A process according to claim 1, characterized by the additional step of forming a conductive shunt layer (29) on the silicon. 3. A process according to claim 2, characterized in that, following said low energy implant, the structure is subjected to a second low energy opposite conductivity implant adapted to form guard band doped regions (24) about the lightly doped regions (22) . 4. " A process according to claim 3, characterized in that, after said thermal cycle, a conformal layer of silicon dioxide (26) is deposited on the structure and subjected to an anisotropic etch to remove horizontal sections of the layer and thereby provide gate sidewall oxide spacers (27). 5. A process according to claim 1, characterized by the step of forming a silicon nitride layer (30) on said silicon layer (13) congruent with said mask, and in that, after said step of subjecting the structure to a relatively low energy implant, there is effected a thermal oxidation step adapted to thermally oxidize the unmasked sidewalls of said gate electrode (19) but not the nitride-protected upper surface thereof.

Inventors: MAHERAS GEORGE, METZ WERNER ADAM JR, MILLER GAYLE WILBURN, SZLUK NICHOLAS JOHN, MAHERAS, GEORGE, METZ, WERNER, ADAM, JR., MILLER, GAYLE, WILBURN, SZLUK, NICHOLAS, JOHN
Applicants: NCR CO, NCR CORPORATION
Application year: 1987
Main classification: H01L29
IPC codes: H01L21, H01L29