Method of sensing data at high speed, and dynamic semiconductor memory apparatus for realizing the method

Abstract: A dynamic semiconductor memory apparatus which can sense data at high speed includes first and second bit line pairs (BL, BL; α, ), memory cells (C1, C2) connected to the first bit line pair (BL, BL), barrier transistors (T1, T2), connected between the first and second bit line pairs (BL, BL; α, ), its impedance being varied in accordance with a level of an input first control signal, and a control unit (15) for out­ putting the first control signal to the barrier tran­ sistors (T1, T2) and for controlling transmission of a potential difference generated in the first bit line pair (BL, BL) due to data read out from the memory cells (C1, C2) to the second bit line pair (α, ) in accor­ dance with an input read control signal. The first control signal is at a first level for a first prede­ termined time interval after the read control signal is input, at a second level for a second predetermined time interval after the first predetermined time inter­ val has passed, and at the first level after the second predetermined time interval has passed, and an impedance of the barrier transistors (T1, T2) obtained when the first control signal is at the first level is smaller than that obtained when the control signal is at the second level.

Description: The present invention relates to a dynamic semiconductor memory apparatus which can sense data at high speed, and to a method of sensing data at high speed in a dynamic semiconductor apparatus. As shown in Fig. 1, in a dynamic random access memory (DRAM), n-channel MOS transistors T1 and T2 are inserted in series with ends of bit lines BL and BL , respectively, of each column to be connected to memory cells (not shown). Restore circuit 51 and synctype sense amplifier 52 for receiving sync signal 1 to perform a sense-amplifying/latching operation are connected between bit line portions α and α at the side opposite to that of the memory cells with reference to barrier transistors T1 and T2. Note that a precharge equalizer (not shown) is connected to the other ends of bit lines BL and BL . As shown in Fig. 2A, memory cell data is read out when read control signal RAS is input to the DRAM at timing S1. That is, as shown in Fig. 2C, control signal T is activated to turn on barrier transistors T1 and T2. Thereafter, as shown in Fig. 2E, at timing S3, amplifier 52 amplifies a small potential difference generated between bit lines BL and BL connected to memory cells selected at timing S2 in accordance with control signal 1 shown in Fig. 2B. Therefore, read data "1" or "0" is determined. At this time, since a charge stored in the bit lines is discharged at once as shown in Fig. 2F, a large current flows to generate noise. In addition, as a DRAM is highly integrated, a load capacitance of bit lines BL and BL is increased to increase a sensing time. Therefore, resistance RV of barrier transistors T1 and T2 is inserted between bit lines BL and BL and amplifier 52 so that a potential difference between bit line portions α and α with a small capacitance at the side of amplifier 52 can be rapidly sensed. Control signal T is supplied to the gate of each of barrier transistors T1 and T2, and potentials as shown in the following Table are used. Bit Line Precharging Voltage Sensing Operation Restoring Operation Precharging Operation Vcc (Power Source Potential) > Vcc + VT > Vcc + VT > Vcc + VT Vcc (Ground Vcc Potential) Vcc > Vcc + VT Vcc 1/2 Vcc Vcc > Vcc + VT Vcc In the above Table, VT represents a threshold voltage of barrier transistors T1 and T2, and a constant potential (Vcc + VT or Vcc) is used as signal T during the sensing operation in any of the above cases. As resistance RV of barrier transistors T1 and T2 is increased, a time required for transmitting the small potential difference generated between bit lines BL and BL to bit line portions α and α through barrier transistors T1 and T2 is increased. Therefore, a start timing of the sensing operation is delayed. On the contrary, when resistance RV is reduced, the smaller a difference between resistance RV and resistance RS of transistors of amplifier 52 becomes, the longer the time required for completing the sensing operation with respect to the potential difference between bit line portions α and α becomes. That is, since a relationship between a load capacitance of bit lines BL and BL , resistance RV of barrier transistors T1 and T2, and resistance RS of the transistors of amplifier 52 is complex, it is difficult to design a DRAM which can perform the sensing operation at high speed as a capacity of the DRAM is increased. Moreover, when resistance RS of the transistors of amplifier 52 is reduced, i.e., a current drive capability is improved, change over time di/dt of a bit line charging/discharging current during the sensing operation is increased, thereby generating a large noise signal on a power source line of a memory chip. "IEEE Journal of Solid-State Circuits", Vol. SC-13, No. 5, 1978, pages 708-711, discloses a memory device comprising a first bit line pair, a second bit line pair, transmission transistors, a sense amplifier, and data output lines. This document teaches that the sensing operation should commence after the sense amplifier nodes have been isolated from the large capacitances of the bit lines, i.e. after the transmission control means have been turned off. It is an object of the present invention to provide a dynamic semiconductor memory apparatus and a method which can easily perform a sensing operation at high speed and and by saving time. A peak current value during a sensing/restoring operation. may be reduced.. The object of the present invention is attained by the dynamic semiconductor memory apparatus according to claim 1 and by the method of sensing data in said dynamic semiconductor memory apparatus according to claim 7, respectively. Further improvements of the present invention are specified in the sub-claims to said claims 1 and 7, respectively. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing part of an arrangement of a conventional dynamic random access memory (DRAM); Figs. 2A to 2F are timing charts for explaining a sensing operation of the conventional DRAM of Fig. 1; Fig. 3 is a circuit diagram showing part of an arrangement of a 1/2 Vcc precharging type DRAM according to an embodiment of the present invention; Figs. 4A to 4H are timing charts for explaining a sensing operation of the DRAM of Fig. 3; Fig. 5 is a circuit diagram showing part of an arrangement of a DRAM according to another embodiment of the present invention; and Figs. 6A to 6H are timing charts for explaining a sensing operation of the DRAM of Fig. 5. Preferred embodiments of a random access memory (DRAM) according to the present invention will be described in detail with reference to the accompanying drawings. Referring to Figs. 3 and 4A to 4H, a DRAM according to a first embodiment will be described below. First, an arrangement of the first embodiment of the present invention will be described with reference to Fig. 3. Fig. 3 shows a necessary portion of an arrangement corresponding to one column of memory cells in a 1/2 Vcc precharging type CMOS DRAM. Precharge equalizer 21 is connected to ends of bit lines BL and BL and precharges the bit lines to 1/2 Vcc to read out data from cell C1 or C2. Barrier transistors T1 and T2 each constituted by an n-channel MOS transistor are connected in series with the other ends of bit lines BL and BL , respectively. Operations of barrier transistors T1 and T2 are controlled by control signal T from controller 15. Restore circuit 11 and sense amplifier 12 are connected between bit line portions α and α at the side opposite to memory cells with reference to barrier transistors T1 and T2. Circuit 11 includes a flip-flop circuit obtained by connecting two p-channel transistors P1 and P2, and its ON and OFF states are controlled by restore control signal RS from controller 15. Amplifier 12 includes a flip-flop circuit obtained by connecting two n-channel transistors Nl and N2, and its ON and OFF states are controlled through n-channel transistor N3 which is turned on/off by sense amplifier control signal 1 from controller 15. Transfer gates 13 and 14 are connected in series with the other ends of bit line portions α and α and are turned on/off by column selection signal CSL from controller 16. Data on bit line portions α and α are supplied to data lines DL and DL through transfer gates 13 and 14, respectively. In accordance with input read control signal RAS, controller 15 generates control signals 1, T, and RS respectively for controlling precharging, restoring, and sensing operations of the bit lines. A read operation of the DRAM according to the first embodiment of the present invention will be described below with reference to Figs. 4A to 4H. A period until signal RAS is input at timing T1 is for a precharge operation of bit lines. Bit lines BL and BL are supplied with 1/2 Vcc by equalizer 21. Signal T for transistors T1 and T2 is set to a potential higher than 1/2 Vcc + VT by controller 15 for the precharge operation. Therefore, barrier transistors T1 and T2 are turned on, and bit lines BL and BL and bit lines α and α are precharged by equalizer 21 to 1/2 Vcc. Equalizer 21 becomes inactive when signal RAS is input and the precharge operation of the bit lines is completed. Then, when word lines W and W connected to memory cells C1 and C2 are selected at timing T2 (see Fig. 4B), transistors CT1 and CT2 are turned on. Therefore, a small potential difference is generated between bit lines BL and BL due to memory cell data as shown in Fig. 4F. This potential difference between bit lines BL and BL is small at first but is gradually increased as time passes. In this case, assuming that cell C2 is a dummy cell and data "1" is stored in cell C1, a potential of bit line BL becomes higher than that of bit line BL. At this time, since barrier transistors T1 and T2 have been turned on, voltages generated on bit lines BL and BL in accordance with the memory cell data, i.e., a memory cell voltage are transferred to bit line portions α and α through barrier transistors T1 and T2, respectively, as shown in Fig. 4G. When the potential difference is so increased as to be detected by amplifier 12, signal T is switched to a low potential at timing T4 as shown in Fig. 4C. Therefore, barrier transistors T1 and T2 are substantially turned off. As shown in Fig. 4D, signal 1 is output from controller 15 to circuit 11 and amplifier 12, respectively, at timing T3. The sense amplifier 12 and restore circuit 11 initiate the sensing/restoring operation at timing T3 earlier than timing T4 when transistors T1 and T2 are turned off Thus, bit lines α and α can be sensed and restored speedily if barrier transistors T1 and T2 are turned off while bit lines BL and BL and bit lines α and α are sensed and restored even though sense amplifier 12 and restore circuit 11 initiate the sensing/ restoring operations at timing T3. In this case, the potential of bit line BL is higher than that of bit line BL . Therefore, when signal RS is input, transistor P1 is turned on, and transistor P2 is turned off. In amplifier 12, transistors N2 and N3 are turned on, and transistor N1 is kept off. Since the load capacitances of bit line portions α and α are very small, the potential difference between bit line portions α and α is rapidly increased as shown in Fig. 4G and hence can be sensed by amplifier 12 earlier than in a conventional DRAM. At this time, a discharging current flows as shown in Fig. 4H. When data of the memory cell is sensed by amplifier 12, controller 16 outputs signal CSL to transfer gates 13 and 14 at timing T5. Therefore, transfer gates 13 and 14 are turned on, and data between bit line portions α and α are read out to data lines DL and DL . Then, as shown in Fig. 4C, signal T is switched to a high potential again at timing T6, and barrier transistors T1 and T2 are turned on. For this reason, although the potential difference between bit line portions α and α slightly varies as shown in Fig. 4G, it is restored by circuit 11 and amplifier 12. At this time, a large discharging current flows as shown in Fig. 4H. Bit lines BL and BL are sensed/restored by amplifier 12 and circuit 11. Therefore, as shown in Fig. 4F, the potential difference between bit lines BL and BL is rapidly increased. As a result, bit line BL goes to potential Vcc, and bit line BL goes to potential Vss. Thereafter, when signal RAS is inactivated at timing T7, signals 1 and CSL are reset, and the data reading, sensing, and restoring operations are completed. Signal CSL is controlled in accordance with signals RAS and CAS . As described above, during the reading operation, bit line portions α and α are sensed/restored when barrier transistors T1 and T2 are temporarily turned off, and bit lines BL and BL are sensed/restored when barrier transistors T1 and T2 are turned on again. Since the load capacitances of bit line portions α and α are smaller than those obtained when bit lines BL and BL are connected to bit line portions α and α , respectively, data can be sensed at speed higher than that of a conventional DRAM. In addition, since bit lines BL and BL are sensed/restored after bit line portions α and α are sensed/restored, bit line charging/ discharging current i becomes smaller than that in a conventional DRAM wherein entire bit lines BL and BL are sensed/restored at the same time during data reading. Therefore, a noise signal is rarely generated in the memory power source voltage. In the first embodiment, barrier transistors T1 and T2 are substantially turned off for a period from timing T4 to timing T6. However, even if barrier transistors T1 and T2 are not completely turned off but only set at impedances higher than those in ON states, data can be sensed at speed higher than that in a conventional DRAM. More specifically, if bit lines α and α are sensed when transistors T1 and T2 are in the higher impedance states, bit lines BL and BL can be also sensed. However, the sensing/restoring operation for bit lines BL and BL is very slowly performed comparing to that for bit lines α and α . This is because charge/discharge current flowing between bit lines BL and α or between bit lines BL and α when transistors T1 and T2 are in the higher impedance states is less than that when transistors T1 and T2 are in ON state. Therefore, the sensing/restoring operation for bit lines α and α can be performed at high speed regardless of that for bit lines BL and BL . A second embodiment of the present invention will be described below with reference to Figs. 5 and 6A to 6H. First, referring to Fig. 5, an arrangement of the second embodiment will be described. In Fig. 5, the same parts as in Fig. 3 will be denoted by the same reference numerals. In Fig. 5, restore circuit 11 is connected between bit lines BL and BL . Similar to the first embodiment shown in Fig. 3, in accordance with input read control signal RAS controller 15 outputs control signals 1, RS, and T to sense amplifier 12, circuit 11, and barrier transistors T1 and T2, respectively. An operation of the second embodiment will be described below with reference to Figs. 6A to 6H. When signal RAS is input, precharge equalizer 21 becomes inactive, and a precharge operation for bit lines BL and BL and bit lines α and α is completed. A word line is designated at timing P2, and transistors CT1 and CT2 are turned on. Therefore, as shown in Fig. 6F, a small potential difference is generated between bit lines BL and BL and bit line portions α and α . The generated potential difference is increased as time passes and transmitted to amplifier 12. When a potential difference large enough to be detected by amplifier 12 is transmitted between bit line portions α and α , signal T is switched to level L at timing P4 as shown in Fig. 6C, thereby separating bit lines BL and BL from bit line portions α and α . Before, at timing P3, controller 15 outputs signals 1 and RS to amplifier 12 and circuit 11. Therefore, the potential difference between bit line portions α and α or bit lines BL and BL is increased. In this case, a potential difference of bit lines BL and BL having large load capacitances is slowly determined by only circuit 11, and that of bit line portions α and α having small load capacitances is determined faster. However, in either case, the potential is determined by only circuit 11 or amplifier 12. Therefore, only a potential difference up to about 1/2 Vcc is generated. In order to read out data when this potential difference may be generated, data lines DL and DL , for example, are precharged to Vcc potential. In this case, by turning on transfer gates 13 and 14, the data can be sufficiently read out. Then, when barrier transistors T1 and T2 are turned on again at timing P6, the restoring operation is performed by amplifier 12 and circuit 11 until the potential difference between bit line portions α and α and that between bit lines BL and BL become Vcc, respectively, as shown in Figs. 6F and 6G. In this case, Fig. 6F shows a case wherein the potential difference of Vcc is generated also between bit line portions α and α by completely turning on barrier transistors T1 and T2 under the condition of T ≧ Vcc + V. However, if the potential difference of Vcc is required between only bit lines BL and BL , the condition of T ≧ VT is sufficient. According to the second embodiment, during the sensing operation, the potential difference of bit lines BL and BL having large load capacitances is determined twice, i.e., in a time interval between timings P3 and P6 wherein barrier transistors T1 and T2 are turned off and in a time interval between timings P6 and P7 wherein barrier transistors T1 and T2 are turned on. Therefore, the bit line charging/discharging current can be divided into two parts, thereby further reducing its peak current as compared with that in the first embodiment. Note that in the circuit shown in Fig. 5, if circuit 11 and amplifier 12 are replaced with each other, the same effect as that described above can be obtained. Also, in the second embodiment, similarly to the first embodiment, barrier transistors T1 and T2 can be used not in off state but in higher impedance state and the sensing/restoring operation is initiated before transistors T1 and T2 are turned off, as being shown in Figs. 6A to 6H. Thus, the sensing/restoring operation can be performed at higher speed. Further the present invention is not limited to the above embodiments. For example, the sense amplifier may be constituted by p-channel transistors, and p-channel transistors may be used as the barrier transistors so that the Vss potential is supplied to their gates. In addition, the restore circuit can perform the restoring operation regardless of whether p- or n-channel transistors are used and hence can be applied to any of NMOS, PMOS, and CMOS memories.

Claims: A dynamic semiconductor memory apparatus which can sense data at high speed, comprising (a) a first bit line pair (BL, BL ) and a second bit line pair (α, α ); (b) memory cells (C1, C2) connected to said first bit line pair (BL, BL ); (c) transmission control means including n-channel MOS transistors (T1, T2), connected between said first and second bit line pairs (BL, BL ; α, α ) its impedance being varied in accordance with a level of a first control signal (ΦT); (d) sensing means (12) incuding an activation n-channel MOS transistor (N3), connected between the lines of said second bit line pair (α, α ); (e) control means (15) for outputting said first control signal (ΦT) to said MOS transistors (T1, T2) of said transmission control means to control transmission of a potential difference on said first bit line pair (BL, BL ) generated due to data read out from said memory cells (C1, C2) to said second bit line pair (α, α ) in accordance with a read control signal ( RAS ), and outputting a second control signal (Φ1) to said MOS transistor (N3) of said sensing means (12); and (f) data output line means (DL, DL ) connected to said sensing means (12); wherein (g) the first control signal (ΦT) is at a high level for a first predetermined time interval at least after the read control signal ( RAS ) changes from the high level to a low level, to turn said MOS transistors (T1, T2) of said transmission control means on so that said first bit line pair (BL, BL ) is connected to said second bit line pair (α, α ) via said MOS transistors (T1, T2) of said transmission control means during said first predetermined time interval; (h) the first control signal (ΦT) is at a low level for a second predetermined time interval after the first predetermined time interval has elapsed from when the read control signal ( RAS ) has changed from the high level to the low level, to turn said MOS transistors (T1, T2) of said transmission control means off so that said first bit line pair (BL, BL ) is disconnected from said second bit line pair (α, α ) to disconnect a load on said first bit line pair (BL, BL ) from said second bit line pair (α, α ) during said second predetermined time interval; (i) the first control signal (ΦT) is again at the high level after said second predetermined time interval has elapsed; (j) the impedance of said transmission control means obtained when the first control signal (ΦT) is at the high level is lower than that obtained when the first control signal (ΦT) is at the low level; (k) the second control signal (Φ1) is at the low level when the read control signal (RAS) changes from the high level to the low level, and changes from the low level to the high level before the first control signal (ΦT) changes from the high level to the low level (Fig. 5, Fig. 6) so that said sensing means (12) starts to sense and amplify data on the first and second pairs of bit lines (BL, BL ; α, α ) while said MOS transistors (T1, T2) of said transmission control means are on, and said MOS transistors (T1, T2) of said transmission control means are turned off after said sensing means (12) has started to sense said data and the potential difference across the second bit line pair (α, α ) is further increased by the sensing means (12) after said MOS transistors (T1, T2) of said transmission control means have been turned off; (l) said sensing means (12) is activated when the second control signal (Φ1) changes form the low level to the high level after the read control signal ( RAS ) has changed from the high level to the low level, and is deactivated when the second control signal (Φ1) changes from the high level to the low level after the read control signal ( RAS ) has changed from the low level to the high level; and (m) said data output line means (DL, DL ) outputs said data sensed by said sensing means (12). The apparatus according to claim 1, wherein said sensing means (12) comprises a pair of transistors (N1, N2) connected between said second bit line pair (α, α ) with each other to constitute a flip-flop, states of wich being determined in accordance with the potential difference between said second bit line pair when said activation n-channel MOS transistor (N3) is turned on, thereby sensing said potential difference; said apparatus further comprises restoring means (11) including a pair of transistors (P1, P2) having a channel different from that of the pair of transistors (N1, N2) of said sensing means (12), and being connected between said second bit line pair (α, α ) to constitute a flip-flop, for restoring the potential difference between said second bit line pair in accordance with the input of a third control signal (RS); and said control means (15) further comprises means for supplying said third control signal (RS) during said first predetermined time interval. The apparatus according to claim 1, wherein said sensing means (12) comprises a pair of transistors (N1, N2) connected between said second bit line pair (α, α ) with each other to constitute a flip-flop, states of wich being determined in accordance with the potential difference between said second bit line pair when said activation n-channel MOS transistor (N3) is turned on, thereby sensing said potential difference; said apparatus further comprises restoring means (11) including a pair of transistors (P1, P2) having a channel different from that of the pair of transistors (N1, N2) of said sensing means (12), and being connected between said first bit line pair (BL, BL ) to constitute a flip-flop, for restoring the potential difference between said first bit line pair in accordance with the input of a third control signal (RS); and said control means (15) further comprises means for supplying said third control signal (RS) during said first predetermined time interval. The apparatus according to any of the preceding claims, wherein said data output line means (DL, DL ) are electrically arranged with respect to said transmission control means on the side of said second bit line pair (α, α ) and are connected to said sensing means (12). The apparatus according to claim 4, wherein said data output line means (DL, DL ) is connected to said second bit line pair (α, α ) through a pair of transistors (13, 14) controlled by a selection signal (CSL). The apparatus according to claim 5, wherein said selection signal (CSL) is supplied by additional control means (16) receiving the read control signal ( RAS ). A method of sensing data at high speed in a dynamic semiconductor memory apparatus according to any of the preceding claims, comprising setting of a first control signal (ΦT) at a first level in response to the input of a read control signal ( RAS ), thereby setting n-channel MOS transistors (T1, T2) connected between first and second bit line pairs (BL, BL ; α, α ) at a low impedance; reading out data from memory cells ((C1, C2) connected between said first bit line pair (BL, BL ); when the read out data has been transferred from said first bit line pair (BL, BL ) to said second bit line pair (α, α ), and after a first predetermined time interval has elapsed after the read control signal ( RAS ) is input, setting the first control signal (ΦT) at a second level for a second predetermined time interval, an impedance of said n-channel MOS transistors (T1, T2) obtained when the first control signal (ΦT) is at the second level being higher than that obtained when the first control signal (ΦT) is at the first level; and setting the first control signal (ΦT) at the first level after the second predetermined time interval has elapsed. The method according to claim 7, comprising sensing the potential difference by sensing means (12) during the first predetermined time interval.

Inventors: OGIHARA MASAKI, OGIHARA, MASAKI, OGIHARA, MASAKI C/O PATENT DIVISION K.K.TOSHIBA
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1987
Main classification: G11C7
IPC codes: G11C7, G11C11