Microprocessor for retrying data transfer

Abstract: A microprocessor (100) and a peripheral equipment communicate data through a bus (140). If an error occurs during the communication, the microprocessor starts the next bus cycle and commands retry of the data communication. If a predetermined number of times of retry fail, or if an address signal corresponds to access to an unmounted area of the peripheral equipment or an area of an I/O equipment, the microprocessor inhibits the retry.

Description: BACKGROUND OF THE INVENTION The present invention relates to a microprocessor having an improved method for retrying data transfer cycle. A microprocessor of this type is disclosed in U.S. Patent 4,348,722. In this microprocessor, a normal end signal (DTACK) as well as an abnormal end signal (BERR) and a retry request signal (HALT) are used as data transfer response signals in order to retry a data transfer cycle. Figs. 1 and 5B of the U.S. Patent 4,348,722 are quoted in Figs. 7 and 8. As shown in Fig. 8, when the data transfer ends abnormally and the retry is requested, the signals BERR and HALT are asserted. In requesting the retry, the following items must be checked: (1) Whether does the number of times of retry exceed a limit? (2) Whether is the data transfer retryable? That is, whether is access to a control register included? (3) Whether is the retry significant? That is, whether is access to an unmounted area included? The retry cannot be requested unless those items have been checked. In the prior art, timing of the BERR and HALT signal generation circuit is critical and it is difficult to design an external circuit of the microprocessor. SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprocessor which solves the problems encountered in the prior art microprocessor, makes it easy to design an external circuit and improves a retry method of data transfer cycle. In accordance with one aspect of the present invention, if data transfer between the microprocessor and an external equipment ends abnormally, the number of times of retry of the same data transfer is counted, and if the number of times exceeds a predetermined limit, further retry is inhibited. Other objects and features of the present invention will be apparent from the description of the preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram of a data processing system in which a microprocessor of the present invention is connected with peripheral equipments through a bus, Fig. 2 shows a block diagram which shows a detail of the microprocessor of Fig. 1. Fig. 3 shows a block diagram which shows a detail of a bus cycle control circuit of Fig. 2, Figs. 4a, 4b, 4c and 4d show time charts of signal waveforms in transferring data in the data processing system, Fig. 5 shows a relationship of assertion between an address space and a special access response signal RMA, Fig. 6 shows a flow chart of a data transfer operation of the data processing system, Fig. 7 shows a known microprocessor, and Fig. 8 shows a time chart of signal waveforms for explaining the operation of the microprocessor of Fig. 7. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 shows a data processing system in accordance with one embodiment of the present invention. Microprocessor 100, memory device 410 and control register device 422 are interconnected through an asynchronous transfer bus 140. The asynchronous transfer bus 140 comprises an address line (A) 141, an address strobe line (AS) 142, a read/write command line (R/W) 143, a data line (D) 144, a transfer acknowledge line (DTACK) 145, a fault line (FAULT) 146, a bus error line (BERR) 147 and a special access response line (RMA) 148. The microprocessor 100 contains a small capacity and high speed cache memory to store input/output data of an arithmetic and logical unit (ALU) contained in the microprocessor 100. High speed data transfer is attainable between the cache memory 401 and the ALU. A memory device 410 is provided to assist the data storing function. The memory device 410 contains a large capacity and low speed semiconductor memory 412. The memory device 410 further contains a magnetic storage device such as a hard disk or floppy disk. A control register device 422 is provided between input/output devices (I/O devices) not shown and the asynchronous transfer bus 140. Data entered by input means of the I/O devices is transferred to the microprocessor 100. In other cases, data from the microprocessor 100 is transferred to output means of the I/O devices. A parity check circuit 402 connected to the data line of the asynchronous transfer bus 140 checks a parity of the data line 144, and if a parity error is detected, it asserts a bus error signal (BERR) 147. The memory device 410 comprises a memory control circuit 411, a memory circuit 412, an error check circuit 413, an error correction circuit 414 and an address check circuit 415. When a bus cycle is started, the memory control circuit 411 checks the address line (A) 141 to determine whether it is an access to a memory space or not. If it is the access to the memory space, it checks whether it is the access to a mounted memory space or not, and if it is the access to an unmounted area, it asserts a fault signal (FAULT) 146. If it is the access to the mounted area, it accesses to the memory circuit 412 and asserts a transfer acknowledge signal (DTACK) 145. In reading data, the read data is supplied to the data line D 144 through an output buffer 416 and error is checked by the error check circuit 413. If an error is detected, a bus error signal (BERR) 147 is asserted to request retry of the bus cycle. The address check circuit 415 detects the request of retry of the bus cycle by the ECC (error check and correction) error and the error correction circuit 144 produces an error-corrected data through an output buffer 417. The address check circuit 415 asserts the DTACK 145. The control register device 420 for the I/O devices comprises a register access circuit 421 and a control register 422. When the bus cycle is started, the register access circuit checks the address 141 to determine whether it is the access to the control register or not. If it is the access to the control register 422 for the I/O devices, (that is, if the address space is an I/O area), the special access response signal RMA 148 is asserted and the control register is accessed and the DTACK 145 is asserted. Fig. 5 shows a relation between the address space and the RMA signal 148. When data is transferred to the I/O area, the special access response signal RMA 148 is asserted to inhibit retry by a bus error. Fig. 2 shows a block diagram which shows a detail of the microprocessor 100. The microprocessor 100 comprises a control unit 110, a bus control unit 120 and a bus cycle control circuit 130. When data is transferred, the control unit 110 produces an I/O request signal IOREQ 111. A read/write command is issued through a line WRT 112, and in a read-modify-write operation, it is issued through a line RMWC 113. The read-modify-write operation means an operation in which data read operation and modify/rewrite operation of the read data are continuously performed. After the data has been transferred, the control unit 110 receives a fetch end signal FEND 114 from the bus cycle control circuit 130. When the fetch end signal is asserted, the bus cycle is terminated and the data transfer to the cache memory 401 of the microprocessor 100 is terminated. If the data transfer ends abnormally, the bus cycle control circuit 130 produces a fetch fault signal FFAULT 115 or fetch bus error signal FBERR 116 instead of the fetch end signal FEND 114. In response thereto, the control unit 110 starts a fault exceptional processing routine or bus error exceptional processing routine which will be explained later in detail. When the bus control unit 120 receives the I/O request signal 111, it produces an address output enable signal (AEN) 121, an internal signal 122 of the address strobe line 142, an internal signal 123 of the read/write command line 143 and a data output enable signal (DEN) 124 to start the bus cycle. It also produces a signal BCYCECOND 125 to start the bus cycle control circuit 130. The bus cycle control circuit 130 comprises an end detection circuit 131, a retry circuit 132, an end report circuit 133 and a retry counter 134. When the start signal 125 is asserted, the end detection circuit 131 samples the transfer acknowledge line 145, fault line 146 and bus error line 147, and if one of the signals is asserted, it produces an end of bus cycle signal to report the end of bus cycle to the bus control unit 120. The retry circuit 132 responds to the end of bus cycle signal 135 to produce a retry signal RETRY 136 when retry is to be done, or an end signal END 137 when retry is not to be done. The retry signal RETRY 136 is supplied to the bus control unit 120 to retry the bus cycle. The end signal END 137 is supplied to an end report circuit 133 which generates, together with the fault line 146 and the bus error line 147, the FEND 114, FFAULT 115 and FBERR 116. The retry counter 134 is cleared by the IOREQ 111 and counted up by the RETRY 136. When the number of times of retry reaches a predetermined limit, it produces a signal MAXR 138 to inhibit further retry. Fig. 3 shows a circuit diagram of the bus cycle control circuit 130. When the BCYCEND 135 is asserted, the retry circuit 132 asserts the END 137 if the BERR 147 is negated or a signal (NORETRY) 201 to inhibit retry is asserted. On the other hand, if the BERR 147 is asserted and the retry inhibit signal NORETRY 201 is negated, the retry circuit 132 asserts the RETRY 136. The retry inhibit signal (NORETRY) 201 is produced by a logical OR of the special access response signal RMA 148 from the external, the read-modify-write command signal 113 from the control unit 110 and the signal MAXR 138 from the retry counter 134. Data transfer errors between the microprocessor 100 and the peripheral equipments (memory device 410, and control register device 420) through the asynchronous transfer bus 140 are classified into several modes. For example, in the data processing system of Fig. 1, if a slight parity error is detected on the data line D 144, the output of the parity check circuit 402 is asserted. On the other hand, if a slight soft error is detected in the memory circuit 412 of the memory device 410, the output of the error check circuit 413 is asserted. In any case, the bus error signal BERR applied to the microprocessor 100 is asserted. In such a case, the retry of bidirectional data transfer between the microprocessor 100 and the peripheral equipments 410 and 420 is significant and the retry is performed. In Fig. 4a, a bus error is detected in one bus cycle, and in the next bus cycle, the retry is performed and the transfer is terminated. As shown in Fig. 4a, when the I/O request signal IOREQ 111 is asserted, the bus control unit 120 of the microprocessor 100 starts a first bus cycle T₁. The address output enable signal AEN 121 is asserted and the address signal A 141, address strobe signal AS 142 and data signal D 144 are supplied from the microprocessor 100 to the asynchronous transfer bus 140. If a slight parity error or soft error is detected in the bus cycle T₁, the bus error signal BERR 147 is asserted. Thus, the end of bus cycle signal BCYCEND 135 and the retry signal RETRY 136 are asserted, and the first bus cycle T₁ ends and a second bus cycle T₂ starts. In the bus cycle T₂, the signal AEN 121 is asserted and the signals A 141, AS 142 and D 144 are supplied from the microprocessor 100 to the bus 140. If the data transfer in the second bus cycle T₂ successes (that is, no parity error nor soft error), the transfer acknowledge signal DTACK 145 is asserted, and the end signal END 137 and the fetch end signal FEND 114 is asserted, and the second bus cycle T₂ is terminated. On the other hand, the retry of data transfer is insignificant for certain access error. For example, when the microprocessor 100 accesses an unmounted area of the address space of Fig. 5 (that is, an area other than address areas of the memory device 410 and the I/O control register 420), it is insignificant. This may occur when a software programmer uses memory functions in excess of the capacity of the memory device 410. In case of such fault, the retry of bidirectional data transfer between the microprocessor 100 and the peripheral equipments 410 and 420 is insignificant and the retry is not performed. In Fig. 4b, a fault is detected in one bus cycle and retry is not performed in the next bus cycle. When the address signal A 141 accesses an unmounted area of the address space of Fig. 5, the memory control circuit 411 of the memory device 410 asserts the fault signal FAULT 146, which is supplied to the bus cycle control circuit 130 of the microprocessor 100 through the asynchronous transfer bus 140. In this case, since the retry signal RETRY 136 is not asserted by the memory control circuit 130 in the bus cycle T₁, the bus control unit 120 does not perform the retry. On the other hand, the bus cycle control circuit 130 asserts the end of bus cycle signal BCYCEND 135, end signal END 137 and fetch fault signal FFAULT 114. In response to the fetch fault signal FFAULT 114, the control unit 110 of the microprocessor 100 commands the fault exceptional processing routine, which informs the fact that the address signal has accessed the unmounted area, to programmer, operator and user through the output means of the I/O devices. On the other hand, let us assume that the address signal A 141 accesses the I/O area of the address space of Fig. 5. If the bus error signal BERR 147 is asserted when the address signal A 141 accesses the input means of the I/O equipments, it means that there is a data error such as a parity error in the data signal D 144 transferred from the input means of the I/O equipments to the microprocessor 100 through the asynchronous transfer bus. The same data as that transferred from the input means of the I/O equipments to the microprocessor 100 by the command from the microprocessor 100 no longer exists in the input means after the transfer. In this case, the bus error signal BERR 147 is asserted and the retry of data transfer from the input means to the microprocessor 100 is insignificant. Fig. 4c shows that retry of data transfer is not performed in such case. When the address signal A 141 accesses the I/O area of the address space of Fig. 5, the register access circuit 421 of the control register device 420 asserts the special access response signal RMA 148. On the other hand, the bus error signal BERR 147 is asserted by the data error in the data signal D 144, as described above. The asserted signal RMA 148 is supplied to the bus cycle control circuit 130 of the microprocessor 100 through the asynchronous transfer bus 140. In this case, since the retry signal RETRY 136 is not asserted by the memory control circuit 130 in the bus cycle T₁, the bus control unit 120 does not retry the data transfer. On the other hand, the bus cycle control circuit 130 asserts the end of bus cycle signal BCYCEND 135, end signal END 137 and fetch bus error signal FBERR 116. In response to the fetch bus error signal FBERR 116, the control unit 110 of the microprocessor 100 commands the bus error exceptional processing routine, which checks status of the input means of the I/O devices and informs to a user through the output means of the I/O equipments that the input job by the input means should be retried. On the other hand, a serious parity error or soft error may take place for a long period of time in the data signal D 144 by the soft error of the memory circuit of the memory device 410 due to electromagnetic interference around the microprocessor or abnormal increase of irradiated α particles. In such a case, the data transfer is not successful even if the retry shown in Fig. 4a is repeated. If the retry of data transfer is endlessly repeated, the microprocessor 100 endlessly repeats useless routine and a significant time is required for the user to recognize such abnormal state. Accordingly, a limit is set to the number of times of repetition of retry, and if the retry does not success before the limit is reached, the bus error exceptional processing routine is executed to inform the abnormal state to the user and further retry is inhibited. Fig. 4c illustrates this operation. If the (n-1)th data transfer does not success, n-th and subsequent retries are inhibited. The bus error signal BERR 147 is asserted in the (n-1)th bus cycle T n-1 but the transfer acknowledge signal DTACK 145 is not asserted. When the (n-2)th retry signal RETRY 136 is applied to the retry counter 134 of the bus cycle control circuit 130 of Fig. 3, the signal MAXR 138 is asserted by the circuit 130. In the n-th bus cycle T n , the retry signal RETRY 136 is no longer asserted while the end of bus cycle signal BCYCEND 135, end signal END 137 and fetch bus error signal FBERR 116 are asserted. In response to the fetch bus error signal FBERR 116, the control unit 110 of the microprocessor 100 executes the bus error exceptional processing routine to inform the abnormal state. Fig. 6 shows a flow chart of the operation of the data processing system shown in Fig. 1. When the data transfer is started, the address is first checked, and if it is a retry cycle by an ECC error (step 510), a corrected data is sent (step 511) and the DTACK 145 is asserted (step 512). The flow of the steps 510 - 512 corresponds to the retry of Fig. 4a. If it is not the retry cycle by the ECC error, whether the access space is a memory area or a register area is checked (step 520), and if it is the register area, the RMA 148 is asserted (step 521), the register is accessed (step 522) and the DTACK 145 is asserted (step 523). The flow Of the steps 520 - 523 corresponds to the non-retry operation of Fig. 4c. On the other hand, if the access space is the memory area, whether it is a mounted area or not is checked (step 530), and if it is unmounted, the FAULT 146 is asserted (step 531). If it is mounted, the memory is accessed (step 540), the DTACK 145 is asserted (step 550) and the ECC check is performed (step 560). If an ECC error is detected, the BERR 147 is asserted (step 561). On the other hand, the flow of the steps 530 - 531 corresponds to the non-retry operation of Fig. 4b. In the present embodiment, the ECC check of the memory device and the correction are divided into two bus cycles. In the first cycle, the memory readout and the ECC check are performed, and in the second bus cycle, the correction and the data transfer are performed. Accordingly, high speed-memory access is attained when ECC error is not included. In the present embodiment, the retry of the bus cycle is started by one external input signal. Accordingly, a timing margin of the retry start circuit is large and high speed data transfer is attained. Further, it is possible to have an external input signal for inhibiting retry. In this case, a malfunction due to the retry access to the control register can be prevented. In the present embodiment, the retry may be inhibited by the command of the control unit in the processor. Accordingly, the retry may be inhibited in the read-modify-write cycle to prevent malfunction. The number of times of retry is counted and if a bus error is still detected when the number of times reaches the limit, the retry is inhibited. Accordingly, an endless loop of retry is prevented and a reliability of the system is improved. In accordance with the present invention, in the data processing system which transfers data to and from the external equipments, if the data transfer ends abnormally, the retry of the data transfer is requested by the signal from the input means. Accordingly, the design of the external circuit is facilitated and the data processing system which performs the retry of the data transfer cycle in a manner suitable to the microprocessor is provided.

Claims: A microprocessor for communicating with a peripheral equipment through a bus (140), comprising (a) a bus control unit (120) for supplying at least an address signal and a data signal to said bus (140), and (b) control means (130) coupled to said bus (140) and said bus control unit (120), said control means including: (b1) first means (131) responsive to a first signal (BERR: 147) from said peripheral equipment indicating that an error has occurred during the communication through said bus (140), said first means (131) being operative to produce a second signal (RETRY:136) to command retry of the communication to said bus control unit (120), characterised in that said control means (130) further includes (b2) second means (132) responsive to a third signal (RMA: 148) from said peripheral equipment, said third signal indicating that said address signal corresponds to access to an area of an I/O equipment of said peripheral equipment in the address space of said microprocessor, for producing an output signal (NORETRY:201) for inhibiting the retry. A microprocessor according to claim 1 further comprising (c) means responsive to the output signal (NORETRY:201) to inhibit the retry supplied from said second means (132) of said control means (130) for informing a user of the fact that said address signal corresponds to the access to the area of said I/O equipment, through output means of said I/O equipment of said peripheral equipment. A microprocessor according to Claim 1, wherein said first signal (BERR:147) from said peripheral equipment indicates that said error has occurred during said communication with a mounted memory area in said address space of said peripheral equipment. A microprocessor according to Claim 3, wherein said control means (130) further includes (b3) third means (134) for counting the number of times of retry commanded by said first means (131) and inhibiting further retry when said number of times reaches a predetermined number.

Inventors: HANAWA MAKOTO, KAWASAKI IKUYA, NISHIMUKAI TADAHIKO, HANAWA, MAKOTO, KAWASAKI, IKUYA, NISHIMUKAI, TADAHIKO
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1987
Main classification: G06F11
IPC codes: G06F11