COMPOUND SEMICONDUCTOR DEVICE

Abstract: A compound semiconductor device having a channel layer which is made of periodically laminated structure of thin-film layers of compound semiconductor substantially being different from each other. The difference of energy be­ tween the conduction band and the valence band of com­ pound semiconductor thin-film layers of one side is less than that of the other side thin-film layers, moreover the electron mobility in low electric field application in the thin-film layers of compound semiconductor of one side is greater than that of the other side thin-film layers, besides the electron mob­ ility in high electric field application in the thin-film layers of compound semiconductor of one side is less than that of the other side thin-film layers, and/or the impact ionization of val­ ence electron generated in high electric field application takes place earlier than the thin-film layers of compound semi­ conductor of the other side. While conduction electron pre­ ferentially flows through the thin-film layers of compound semiconductor of one side in low electric field application, and conversely, while conduction electron having substantial energy intensified by acceleration preferentially flows through other side thin-film layers in high electric field applic­ ation.

Description: The present invention relates to a compound semiconductor device, more particularly, to a compound semiconductor device specially suited for manufacturing component device of integrated circuits (IC) and large-scale integrated circuits (LSI) among those compound semiconductor devices such as field effect transistors (FET), high electron movement transistors (HEMT) and the like. As fabricating method of compound semiconductor devices, particularly electronic devices, the epitaxial growth method is generally employed owing to the thin and uniform growth of layer and ease of control of constituent element composition ratio. Above all, the molecular beam epitaxial (MBE) growth method is known as one of the particularly noticed techniques recently. For example, a device utilizing the MBE growth method and thin layer periodic structure is described in details by W. T. Tsang in Nikkei Electronics No. 308, 163 (1983). According to this MBE growth method, the crystal growth speed can be controlled on a single atomic plane level (see J. P. van der Ziel et al., J. Appl. Phys., 48 (1977), p. 3018), and, furthermore, when combined with the reflective electron diffraction method, the composition of one atomic plane can be accurately controlled (see J. H. Neave et al., Appl. Phys. A 31, 1, 1983). By employing such MBE growth method, it is possible to fabricate a high electron mobility transistor (HEMT) as shown in Fig. 10. Incidentally, microwave elements using conventional compound semiconductors are disclosed, for example, in the Japanese Unexamined Patent Publication Nos. 4085/1984 and 147169/1983. In the HEMT structure shown in Fig. 10, a GaAs layer 12 functioning as a buffer layer is formed on a semi-insulating GaAs substrate 11, and an undoped GaAs layer 13 serving as a channel layer is formed thereon. On the undoped GaAs layer 13 is formed an electron supply layer 14 having a high impurity concentration such as n-Ga x Al 1-x As, and in the middle of the electron supply layer 14 there is a layer 15 made of a semiconductor containing p-type impurities at high concentration and possessing a large electrophilic ability, while a gate electrode 16 is disposed on this layer 15. Furthermore, the surface region 17 of the electron supply layer 14 at both sides of the layer 15 is alloyed, and source and drainage electrodes 18 are formed thereon. In thus composed semiconductor device, when a proper bias voltage is applied to the gate electrode 16, a two-dimensional electron gas 19 is formed at the channel layer 13 side at the interface of the electron supply layer 14 and the channel layer 13. As a result, many electrons flow in the portion of a few tens angstrom units in thickness near the interface in the channel layer 13 where only few impurity ions are present. Therefore, scatter of impurity ions which is one of major causes of limiting the electron mobility is less, so that a high electron mobility may be realized. However, when operating such a conventional compound semiconductor device having the typical constitution mentioned above, the electron mobility is extremely dependent on the intensity of the electric field applied to the two-dimensional electron gas. High electron mobility is realized in low electric field application, conversely the electron mobility lowers in high electric field application. This phenomenon is described by M. Inoue et al. in J.J.A.P.22 357 (1983) for example. FIG. 11 shows one of these examples related to the constitution of the above-mentioned microwave element containing GaAs/n-Ga x Al 1-x As, in which the above phenomenon is expressed by the broken-line curve. Generally, those phenomena including inter-valley scattering, impact ionization, or phonon scattering respectively cause electron scattering mechanism in a semiconductor device in high electric field application. Consequently, those characteristics specified below of the semiconductor crystals used for channel layers of ultra-high-frequency transistors should be improved. (1) To prevent inter-valley scattering from occurrence, a greater value of energy difference ΔE should be provided between valleys of space κ. (2) To prevent impact ionization from occurrence, a greater value should be provided for energy gap Eg. (3) To minimize loss of operating energy of carrier electrons caused by phonon scattering, a lesser value should be provided for effective mass m*. FIG. 7 shows an example of the energy band structure of GaAs crystals in conjunction with parameters of energy difference ΔE between valleys and energy gap Eg. Conventionally, GaAs, InP, and In 0.53 Ga 0.47 As respectively make up compound semiconductors for composing channel layers of conventional FET and HEMT. Table 1 represents approximate values of energy difference ΔE between valleys, energy gap Eg, and the effective mass m* of electrons of those compound semiconductors mentioned above. With reference to the later description, data related to InAs and InSb are also shown in Table 1. Note that the energy difference between valleys of In 0.53 Ga 0.47 As is not yet known. Elements Energy gap Eg (eV) (300k) Energy difference between valleys (eV) Effective Mass m* ΔE ΓL ΔE ΓX GaAs 1.428 0.294 0.46 0.065 InP 1.351 0.5 0.85 0.077 InAs 0.356 0.78 1.47 0.027 In 0.53 Ga 0.47 As 0.75 - - 0.041 InSb 0.18 1.67 2.03 0.016 As is clear from Table 1, if the channel layer is composed of GaAs compound, since there is large energy gap Eg, impact ionization rarely takes place in high electric field application. Conversely, due to small energy difference ΔE between valleys, inter-valley scattering easily takes place. Furthermore, since the effective mass m* of electrons inherent to GaAs is great, a greater amount of operating energy of electrons is lost by phonon scattering, thus preventing electrons from flowing themselves faster. On the other hand, if the channel layer is composed of InP compound, due to substantial values of energy gap Eg, energy differences ΔE ΓL , ΔE ΓX between valleys inherent to Inp, neither impact ionization nor inter-valley scattering easily occurs in high electric field application, thus allowing electrons to flow themselves at a faster speed. Conversely, since the effective mass m* of electrons inherent to InP is great, electrons are presented from flowing themselves at a faster speed in low electric field application. On the other hand, if the channel layer is composed of compound semiconductors made from InAs or InSb, due to small amount of effective mass m*, electrons flow themselves at an extremely fast speed in low electric field application. Conversely, since the energy gap Eg is small, impact ionization easily occurs in high electric field application. For example, impact ionization occurs in the compound semiconductor made of InAs in about 3.3 KV/cm electric field application. Further, if the channel layer is composed of compound semiconductors made of the mixed crystals of In 0.53 Ga 0.47 As, this mixture exhibits a specific characteristic which is between those of compound semiconductor made of InAs and compound semiconductor made of GaAs. Those features thus far described above are apparently identified by referring to FIG. 12 showing the results of tests and theoretical development in conjunction with the dependency of the drift speed of electrons present in compound semiconductors on the intensity of electric field applied thereto. Results of evaluating the characteristic of compound semiconductors made of GaAs are cited by Ruch. J.G. and Kino G.S. in the Phys. Rev., 174, 921 (1969), and by Houston P.A. et al. in Solid State Comm., 20,197 (1977), respectively. Likewise, results of evaluating the characteristic of compound semiconductors made of InP are cited by Nelsen L.D. in the Phys. Lett., A38, 221 (1972) and Boers P.M. in the Electron Lett., 7, 625 (1971), respectively. Results of evaluating the characteristic of compound semiconductors made of InAs are cited by Itoh et al. in the report ED83-77, (1983) presented to Electronic Communication Society of Japan. Covering the results of evaluating the characteristic of compound semiconductors made of InSb, refer to the reports presented by Glicksman M. et al. in the Phys. Rev., 129, 1572 (1963), Neukermans A. et al. in the Appl. Phys. Lett., 17, 102 (1970), and Smith J. et al. in the Appl. Phys. Lett., 37, 797 (1980), respectively. Results of evaluating the characteristic of compound semiconductors made of mixed crystals of In x Ga 1-x As are cited by Itoh et al. in the report ED83-77, (1983) presented to Electronic Communication Society of Japan. Generally, when operating either an FET or an HEMT, since either of these is subjected to several kilovolts per centimeter of electric field, any of these transistors having a conventional structure using channel layers made of InAs or InSb which easily allow occurrence of impact ionization in low electric field incurs much disadvantages. Actually, there is no satisfactory FET incorporating channel layers made of either InAs or InSb. In other words, any of these conventional transistors cannot effectively apply advantageous characteristic of InAs or InSb which allows electrons to flow themselves at an extremely fast speed in low electric field application. Although not shown in FIG. 12, those compound semiconductors made of mixed crystals of In x Ga 1-x As (0 < x < 1.0) or InAs y P 1-y (0 < y < 1.0) vary their dependency of the electron mobility on the intensity of electric field according to values of x and y. However, the electron mobility of these compound semiconductors is lower than that of those which are made of InAs in low electric field application, and yet, the electron mobility of these is also lower than that of those which are made of either GaAs or InP in high electric field application, respectively. T.E. Zipperian et al. disclosed an In 0.2 Ga 0.8 As/GaAS modulation-doped, strained-layer superlatice FET in "International Electron Devices Meeting Technical Digest, 5-7 December 1983, pages 696-698, Washington D.C., USA. In order to securely manufacture high-performance transistors featuring faster operation speed and more satisfactory characteristics, those transistors should allow electrons to flow at an extremely fast speed in low and high electric field applications. Taking this into account, neither GaAs having the low electron mobility in high electric field application nor InP having the low electron mobility in low electric field application is ideally suited for making up channel layers, respectively. A study on a new constitution called "super-lattice constitution" has been underway, the detail of which is presented by L. Esaki, R. Tsu; IBM J. Res. Develop. (1970) P 61 for example. As shown in FIG. 8, using an adequate growth system like MBE growth method for example, thin-film layers made of compound semiconductors comprising different components like GaAs and AlAs for example are alternately and periodically laminated. By comparative evaluation of bulk crystals, specifically quantized levels are then generated in the thin-film layers in the lower portions of the conduction band (which are substantially layers A shown in FIG. 8 and are hereinafter called "well layers"). Although FIG. 8 shows only two levels 1 and 2, actually, the number and the energy of the level are variable dependent on the thickness LW of the well layer, thickness LB of the barrier layer corresponding to the layer B shown in FIG. 8, and the difference between the bottoms of the conduction band of layers A and B as the bulk crystals, respectively. Furthermore, the probability of the presence of electrons in these quantized levels is described by M. Jaros, K.B. Wong; J. Phys. C: Solid State Phys., 17 (1984) L765 for example. Assume that the barrier layer is made of Ga 0.8 Al 0.2 As and the well layer is made of GaAs, respectively, then, as shown in FIG. 9-a, only the quantized levels 1 and 2 can be confined inside of the GaAs layer, whereas the high-energy level above level 3 exceeds the barrier height EB of the barrier layer made of Ga 0.8 Al 0.2 As. FIG. 9-b denotes that there is the greater probability of the presence of electrons on the side of GaAs layer at levels 1 and 2 when the above condition is present. Conversely, there is the greater probability of the presence of electrons inside of the layer made of Ga 0.8 Al 0.2 As. The probability of the presence of electrons is variable by varying the thickness of the barrier layer and the well layer and the height of barrier as well. More particularly, as is clear from FIG. 9, there is the significantly greater probability of the presence of those electrons having more amount of energy than the barrier energy in the Ga 0.8 Al 0.2 As layer than those which move through the GaAs layer. However, since the electron mobility inside of the Ga x Al 1-x As layer of the periodical thin-film constitution made of mixed crystal of GaAs and Ga x Al 1-x As is significantly low both in high and low electric field application, when the high electric field is applied, the electron mobility inside of the Ga x Al 1-x As layer becomes lower than that of the GaAs layer measured in the same intensity of electric field. Taking the above conditions into account, the inventor detected that specific energy band structure identical to those which are shown in FIGS. 8 and 9 could be generated by making up the well layer by using either InAs or InSb and the barrier layer by using either InP or GaAs. First, when making up the well layer and the barrier layer by using InAs and InP, respectively, the inventor detected that the quantized level could be formed inside of the InAs layer. The inventor also detected that only the low-energy levels 1 and 2 could be confined in the InAs layer, whereas the high-energy level 3 could be raised to a point higher than the barrier height EB between InP and InA as shown in FIG. 9. As a result, since the effective energy gap Eg inside of the InAs layer is equal to the difference between the quantized level 1 inside of the conduction band and the quantized level 1 inside of the valence band shown in FIG. 8, this energy gap becomes greater than the essential energy gap Eg of the InAs crystal. Consequently, as described earlier, impact ionization cannot easily take place, thus allowing high electric field of greater magnitude to be applied. Alternatively, in the presence of a specific intensity of electric field prior to the occurrence of impact ionization, the probability of the presence of highly energized electrons can significantly grow on the part of the InP layer (refer to the state of level 3 shown in FIG. 9). Consequently, it is possible for the InAs layer to securely prevent impact ionization from internally taking place. In addition, since those electrons transitted into the InP layer in high electric field application follow the electric characteristic of the InP layer in high electric field application, as shown in FIG. 12, electrons flow themselves through the InP layer at a speed faster than that of those electrons flowing through other crystals even when high electric field is applied. In other words, in low electric field application, since electrons are confined inside of the InAs layer, electrons flow themselves at a speed faster than those electrons flowing through the GaAs and InP bulk crystals, and yet, since highly-energized electrons transit themselves into the InP layer in high electric field application, electrons are allowed to flow themselves at a speed faster than those which flow through the GaAs crystal. This invention is contrived in the light of the above problems, it is hence a primary object of this invention to present a novel compound semiconductor device having a channel layer made of periodically laminated thin-film constitution capable of moving electrons at an extremely fast speed independent of the intensity of the electric field. Another object of the invention is to provide a novel compound semiconductor device having a channel layer made of periodically laminated thin-film constitution which prevents occurrence of inter-valley scattering and impact ionization. To achieve the above objects, a compound semiconductor device as defined in claims 1 to 3 is provided. Since the compound semiconductor device according to this invention featuring the constitution mentioned above is provided with channel layers by periodically laminating compound semiconductor thin-film layers (A) and (B), it is possible for the device to effectively generate energy gap having a specific magnitude enough to prevent impact ionization from occurrence in the compound semiconductor thin-film layers (A) and promote the probability of the presence of highly energized electrons enough to completely prevent impact ionization from occurrence in the compound semiconductor thin-film layers (B). Furthermore, since the device related to this invention causes conduction electrons to be confined in the compound semiconductor thin-film layers (A) in low electric field application in order that the conduction electrons can preferentially flow through the compound semiconductor thin-film layers (A), these conduction electrons are allowed to move themselves at a significantly accelerated speed. Likewise, since the device related to this invention allows the highly energized conduction electrons to preferentially flow through the compound semiconductor thin-film layers (B) after being accelerated by the applied high electric field, the mobility of these electrons can eventually and significantly be accelerated. In particular, before causing the conduction electrons to generate impact ionization of valence electrons and before occurrence of inter-valley scattering in the conduction band by the conduction electrons, the device related to this invention allows the highly energized conduction electrons accelerated by the applied high electric field to transit themselves from the compound semiconductor thin-film layers of (A) to the other compound semiconductive thin-film layers (B), and as a result, the conduction electrons can preferentially flow through the other compound semiconductor thin-film layers (B) at a significantly accelerated speed. The invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of this invention in which: FIG. 1 is the simplified sectional diagram denoting a preferred embodiment of FET as the compound semiconductor device related to the invention; FIG. 2 is the chart denoting the result of evaluating the dependency of the drifting speed of electron in the FET shown in FIG. 1 on the intensity of the applied electric field; FIG. 3 is the chart denoting the result of evaluating the dependency of the drifting speed of electron on the intensity of the applied electric field when varying the thickness of the well layer comprised of InAs against the barrier layer comprised of InP; FIG. 4 is the chart denoting the result of evaluating the dependency of the drifting speed of electron on the intensity of the applied electric field when varying the thickness of the well layer comprised of InAs against the barrier layer comprised of GaAs; FIG. 5 is the chart denoting the result of evaluating the dependency of the drifting speed of electron on the intensity of the applied electric field when varying the thickness of the well layer comprised of In 0.53 Ga 0.47 As against the barrier layer comprised of InP; FIG. 6 is the chart denoting the result of evaluating the dependency of the drifting speed of electron when silicon is doped against the barrier layer comprised of InP against the well layer comprised of InAs and also when neither of these layers is doped with silicon; FIG. 7 is the chart denoting the energy band constitution of the compound semiconductor; FIG. 8 is the chart of energy composition for explaining the quantized level; FIG. 9 is the chart explaining the phenomenon in which highly energized electrons transit themselves from the well layer to the barrier layer; FIG. 10 is the simplified sectional diagram of a conventional HEMT; FIG. 11 is the chart denoting the result of evaluating the dependency of the electron mobility on the intensity of the applied electric field proper to a conventional HEMT; and FIG. 12 is the chart denoting the result of evaluating the dependency of the drifting speed of electron of a variety of conventional compound semiconductors on the intensity of the applied electric field. Referring now more particularly to the accompanying drawings, one of the preferred embodiments of this invention is described below. FIG. 1 represents a novel FET related to this invention incorporating a channel layer comprised of a crystalline compound semiconductor multiple thin-film layer 2 containing each 6 layers of InAs and InP alternately being laminated by about 6.9nm (69Å) and about 10nm (100Å) on the semiinsulated InP substrate 1. The multiple thin-film layer 2 has about 0.1 µm thickness as a whole, which is formed on the semiinsulated InP substrate 1 by applying the MBE growth method. The surface of the multiple thin-film layer 2 is provided with the evaporated AuGeNi ohmic junction electrodes 3, to form the source electrode and drainage electrode. Gate electrode is made of the Al Schottky junction electrode provided on the insulated layer 6 by evaporation. Due to the evaporation and alloying processes done for generating the AuGeNi ohmic junction electrode 3, the Au atoms diffuse itself throughout the crystalline multiple thin-film layer 2 of compound semiconductor. As a result, periodic characteristic of the layer structure in the compound semiconductor crystalline multiple thin-film layer 2 goes out of order, thus causing the crystalline structure in the area 5 to eventually become identical to the conventional InAs y P 1-y mixed crystal. Consequently, the energy band structure in this area 5 also becomes identical to that of the conventional InAS y P 1-y mixed crystal. Due to these phenomena took place during tests, the inventor smoothly formed ohmic junction. N. Holonyak et al. already announced similar phenomenon in which the diffusion of the atoms causes the destruction of the periodic characteristic of the layer structure of compound semiconductor multiple thin-film layers in A.P.L. 39 (1981) 102. By applying conventional techniques for making up conventional FET structures, the inventor confirmed that the source electrode 3, drainage electrode 3, and the gate electrode, 4 shown in FIG. 1 properly executed functions needed for FET. FIG. 2 is the chart denoting the result of evaluating the dependency of the drifting speed of electrons inside of the multiple thin-film layer 2 shown in FIG. 1 on the intensity of the applied electric field. As is clear from the comparison to FIG. 12, while low electric field is applied, the multiple thin-film layer 2 allows electrons to flow themselves at a specific speed almost corresponding to that is available inside of InAs. In addition, the multiple thin-film layer 2 doesn't cause impact ionization to occur even when high electric field is applied, while allowing electrons to flow themselves at a specific speed almost corresponding to that is available inside of InP. In other words, by implementing the multiple thin-film layer constitution shown in FIG. 1, the dependency of the electron mobility on the intensity of electric field is significantly improved. In addition, by varying the thickness of the InAs thin-film layer from about 2.4nm (24Å) to about 7.5nm (75Å), the inventor observed satisfactory effect corresponding to those which are mentioned above. Concretely, the inventor confirmed the dependency of the drifting speed of electrons on the applied electric field by providing the thickness of the InAs layer at about 2.1nm (21Å), 2.4nm (24Å), 4.5nm (45Å), 7.5nm (75Å), and 7.8nm (78Å) (refer to e, c, b, a, and d shown in FIG. 3) against the thickness of the InP layer of about 10nm (100Å). When the InAs layer had thickness at about 2.1nm (21Å), electrons flowed themselves at a low speed in low electric field application. Conversely, when the InAs layer had thickness at about 7.8nm (78Å), the drifting speed of electrons was increased until applied electric field rose to a certain level. When the applied electric field exceeded a certain critical level, the specimen was eventually destroyed. Taking this into account, the dependency of the electron mobility on the applied electric field can securely be improved by setting the thickness of the InAs layer at a certain value between about 2.4nm (24Å) and a maximum of 7.5nm (75Å). It was probable that, since the InAs layer had a too large thickness, preferential flow of electrons inside of the InP layer didn't occur even when high electric field was applied, thus causing a large amount of current to flow through only the InAs layer to eventually destroy the specimen. Although the above preferred embodiment employed the well layer and the barrier layer respectively being composed of InAs and InP, the inventor also achieved the identical effect by employing the well layer and the barrier layer respectively being composed of InAs and GaAs. Use of these layers composed of the latter components resulted in the lowered electron mobility in high electric field application, which was slower than those which are shown in FIGs. 2 and 3, while the electron mobility became almost equal to that was observed from the GaAs bulk crystal. This characteristic was observed only when the thickness of the InAs layer was varied from about 2.4nm (24Å) to about 6.0nm (60Å). FIG. 4 is the chart denoting the result of evaluating the dependency of the drifting speed of electrons on the applied electric field when employing the well layer and the barrier layer respectively being composed of InAs and GaAs. The inventor confirmed the results shown in FIG. 4 by evaluating the dependency of the drifting speed of electrons on the applied electric field by providing the thickness of the InAs layer at about 2.1nm (21Å), 2.4nm (24Å), 6.0nm (60Å), and 7.2nm (72Å) (refer to c, b, a, and d) against the thickness of the GaAs layer at about 5.0nm (50Å). Concretely, when the InAs layer has the thickness at about 2.1nm (21Å) under low electric field, electrons flow themselves at a low speed in low electric field application, and therefore, the InAs layer should be provided with a minimum thickness at about 2.4nm (24Å). According to the test results, when the InAs layer had the thickness at about 7.2nm (72Å), a variety of defects took place with the specimen due to unsatisfactory surface condition of the tested specimen. However, the specimen generated mirror surface when the InAs layer had the thickness at about 2.1nm (21Å), 2.4nm (24Å), and 6.0nm (60Å), respectively. Taking this into account, the dependency of the electron mobility on the applied electric field can securely be improved by providing the thickness of the InAs layer at from about 2.4nm (24Å) to about 6.0nm (60Å). Of the multiple thin-film layer 2 of the FET shown in FIG. 1, when using well layers which are respectively comprised of In 0.53 Ga 0.47 As and provided with the thickness at minimum of about 6.8nm (68Å) against the barrier layer comprised of InP, the inventor confirmed that the electron mobility in high electric field application was almost equal to that was shown in the InP. FIG. 5 is the chart denoting the result of evaluating the dependency of the drifting speed of electrons on the applied electric field when employing the well layer and the barrier layer respectively being comprised of In 0.53 Ga 0.47 As and Inp. Concretely, the inventor confirmed the dependency of the drifting speed of electrons on the applied electric field by providing the thickness In 0.53 Ga 0.47 As layer at about 6.5nm (65Å), 6.8nm (68Å), 10nm (100Å), and 20nm (200Å) (refer to d, c, b, and a shown in FIG. 4) against the thickness of InP layer at about 10nm (100Å). When the layer comprised of In 0.53 Ga 0.47 As had the thickness at about 6.5nm (65Å), the drifting speed of electrons slowed down in low electric field application, and thus, the In 0.53 Ga 0.47 As layer should be provided with a minimum thickness at about 6.8nm (68Å). When using the well layer comprised of InSb against the barrier layer comprised of GaAs or InP, the inventor confirmed that satisfactory result identical to that of FIG. 2 was obtained. When low electric field was applied, electrons flow themselves at a speed almost equal to the electron mobility inside of the InSb. Likewise, when high electric field was applied, electrons flowed themselves at a speed almost equal to the electron mobility inside of GaAs or InP. It was also confirmed from these experiments that impact ionization was completely prevented from occurrence inside of the InSb layer. The invention also provides other constitutions, in which the well layer may be comprised of either InAs or InSb and the barrier layer may also be comprised of InAs y P 1-y (0 < y < 1.0). In addition, the well layer may also be comprised of InAS y P 1-y (0.5 < y < 1.0) and the barrier layer may also be comprised of InAs y P 1-y (0 < y < 0.5). As a result of doping n-type impurities such as silicon (Si), tin (Sn), tellurium (Te), and the like against only the barrier layer portions of all those combinations mentioned above, the inventor successfully promoted the electron mobility by 20% through a maximum of 50% in low electric field application. FIG. 6 is the chart denoting the results of evaluating the dependency of the drifting speed of electrons on the intensity of the applied electric field when using the well layer comprised of InAs crystal having the thickness at about 7.5nm (75Å) and the barrier layer of InP crystal having the thickness at about 10nm (100Å). Reference character "a" in FIG. 6 indicates the result of the doping of silicon against only InP layer portion, whereas reference character "b" indicates the result without doping silicon against both InAs and InP layers. By referring to these results, the inventor eventually confirmed the effect described above. As is clear from the foregoing description of the preferred embodiments of this invention, the thickness of the entire channel layer can be set in the submicron order. Accordingly, by effectively applying those constituents of the preferred embodiments to a variety of compound semiconductor devices for making up IC and LSI, it is possible for all the electronic elements to securely accelerate their operation speed independent of variable conditions of the applied electric field. Although the foregoing description of the preferred embodiments totally refers to the use of FET, it is obvious for those skilled in the art that the constituents of the invention can securely generate the same characteristics as the above by effectively being applied to other compound semiconductor devices like HEMT and others.

Claims: A compound semiconductor device incorporating a channel layer which is made of periodically layering compound semiconductor thin-film layers (A,B) substantially being different from each other comprising; one compound semiconductor thin-film layers (A) having a specific energy difference between conduction band and valence band being less than that of the other compound semiconductor thin-film layers (B), a specific electron mobility which is greater than that of the other compound semiconductor thin-film layers (B) in low electric field application, a specific electron mobility which is less than that of the other compound semiconductor thin-film layers (B) in high electric field application, causing impact ionisation of valence electron to occur in high electric field application earlier than the other compound semiconductor thin-film layers (B); and said compound semiconductor thin-film layers (A,B) allowing conduction electrons to preferentially flow through said one compound semiconductor thin-film layers (A) in low electric field application and conduction electrons highly energized by acceleration to preferentially flow through said other compound semiconductor thin-film layers (B) in high electric field application, and allowing conduction electrons highly energized by acceleration in high electric field application to transit themselves from said one compound semiconductor thin-film layers (A) to said other compound semiconductor thin-film layers (B) before said conduction electrons cause impact ionisation of valence electrons to occur inside of said one compound semiconductor thin-film layers (A) and inter-valley scattering to occur in said conduction band, respectively, characterized in that said one compound semiconductor thin-film layers (A) are substantially composed of InAs compound semiconductor, whereas said other compound thin-film layers (B) are substantially composed of InP compound semiconductor, where said one compound semiconductor thin-film layers (A) are provided with a certain thickness ranging from about 2.4nm to a maximum of about 7.5nm. A compound semiconductor device incorporating a channel layer which is made of periodically layering compound semiconductor thin-film layers (A,B) substantially being different from each other comprising; one compound semiconductor thin-film layers (A) having a specific energy difference between conduction band and valence band being less than that of the other compound semiconductor thin-film layers (B), a specific electron mobility which is greater than that of the other compound semiconductor thin-film layers (B) in low electric field application, a specific electron mobility which is less than that of the other compound semiconductor thin-film layers (B) in high electric field application, causing impact ionisation of valence electron to occur in high electric field application earlier than the other compound semiconductor thin-film layers (B); and said compound semiconductor thin-film layers (A,B) allowing conduction electrons to preferentially flow through said one compound semiconductor thin-film layers (A) in low electric field application and conduction electrons highly energized by acceleration to preferentially flow through said other compound semiconductor thin-film layers (B) in high electric field application, and allowing conduction electrons highly energized by acceleration in high electric field application to transit themselves from said one compound semiconductor thin-film layers (A) to said other compound semiconductor thin-film layers (B) before said conduction electrons cause impact ionization of valence electrons to occur inside of said one compound semiconductor thin-film layers (A) and inter-valley scattering to occur in said conduction band, respectively, characterized in that said one compound semiconductor thin-film layers (A) are substantially composed of InAs compound semiconductor, whereas said other compound semiconductor thin-film layers (B) are substantially composed of GaAs compound semiconductor, where said one compound semiconductor thin-film layers (A) are provided with a certain thickness ranging from about 2.4nm to a maximum of about 6.0nm. The compound semiconductor device in accordance with claim 1 or 2, in which n-type impurities are doped in the other compound semiconductor thin-film layers (B).

Inventors: MATSUI, YUICHI C/O OSAKA WORKS
Applicants: SUMITOMO ELECTRIC INDUSTRIES LIMITED
Application year: 1987
Main classification: H01L29
IPC codes: H01L21, H01L29