DATA DEMODULATION SYSTEM

Abstract: Disclosed is a data demodulation system for reproducing the data being divided and recorded in plural blocks in a re­ cording medium, comprising the steps of modulating by adding specified data bit patterns to the data bits of dividing portions of each block, and reproducing the data from the recording medium in which record patterns obtained by adding specified code bit patterns are added after modulation are recorded, wherein bit rows are independently demodula­ ted by demodulation clocks differing mutually in phase, the demodulation bit pattern of the above code bit pattern added at the time of recording and the bit pattern demodulated by the different modulation clock are compared with each other to check if wrong or not, and the correct one of the two sets of demodulated data is selected according to this result and de­ livered.

Description: This invention relates to a data demodulation system and its apparatus used in magnetic recording, optical recording, etc. Conventionally, one known sequential coding method of constant ratio data codes of variable word length, is the 2-7 modulation/demodulation system as described in United States Patent Specification US-A-4,115,768 (the disclosure of which is included herein by way of reference). In the 2-7 modulation/demodulation system, as shown in Fig. 2, 2-bit codes are used for 1-bit data, and when demodulating, in order to convert 2-bit codes into the original 1-bit data, a demodulation clock DMCK is needed. Fig. 3 refers to an example of a conventional demodulation circuit employed in the 2-7 modulation/demodulation system. In this system the read data RDDT is introduced into a shift register 11 which is operated by a read clock RDCK. The output of the shift register 11 is introduced into a logic gate circuit 12, and this output is synchronized by the 1/2 period read clock RDCK introduced into a demodulation clock generator circuit 13, that is, a demodulation clock DMCK, thereby obtaining demodulated data S20. Thus, in the conventional circuit, since the demodulation clock DMCK is obtained by compressing the read clock RDCK to 1/2 period by flip-flop 22 and AND gate 21, if a wrong inversion occurs in the demodulation clock DMCK due to noise or some other cause, all the subsequent demodulated data S20 is wrong. WO-A-85/01402 describes a synchronisation pattern encoding system for data sectors written on a storage medium. The system generates a unique sync pattern that is appended to a selected data sector of a disc storage system. The sync pattern is generated by encoding a prescribed data word and introducing an error during encoding so that the sync pattern does not correspond to a valid sequence of data. This invention aims to ameliorate some of the above-discussed problems. In accordance with this invention there is provided a data demodulation apparatus for demodulating a signal which includes coded data signal portions using a demodulation clock the signal further includes a signal portion comprising a predetermined signal pattern, characterized in that the signal is demodulated using a plurality of mutually phase-shifted demodulation clock signals, each providing a demodulation version of the signal, the correct demodulation pattern of the predetermined signal pattern producing a known demodulation pattern and there being provided means for comparing the demodulated versions of the predetermined signal pattern obtained using the different clock signals with said known demodulation pattern to determine which of the demodulating clock signals is producing the correct demodulation of the coded data signal portions. Preferably the signal to be demodulated is divided into signal blocks, each including coded data signal portions and one predetermined signal pattern. The comparing means then compares the demodulated versions of the signal pattern of that block with the known demodulation pattern to determine which of the demodulating clock signals will produce the correct demodulation of the coded data signal portions of that block. Preferably first and second demodulation means are provided for demodulating the signal using first and second said demodulating clock signals respectively. A signal selection means is coupled to receive the demodulated signals from the first and second demodulation means and controlled in accordance with the output of the comparing means to select the correctly demodulated signal for output from the system. The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: Fig. 1 is a block diagram of a system configuration for performing the demodulation system according to this invention; Fig. 2 is an explanatory diagram to show the coding type of the 2-7 modulation/demodulation system; Fig. 3 is a circuit diagram of a conventional demodulation circuit; Fig. 4 is an explanatory diagram of a recording format in recording medium; and Fig. 5 and Fig. 6 are explanatory diagrams of bit patterns. Referring now to the drawings, this invention is described herein in details, specifically relating to some of its embodiments. Fig. 4 shows an example of the recording format employed in magnetic recording, optical recording, etc. Fig. 1 is a block diagram of the system configuration for the demodulation system of this invention. The tracks on the recording medium are, for example, divided into n₁ sectors as shown in Fig. 4(a). A drive unit (DU) 100 in Fig. 1 writes data in the units of these sectors. Each sector is composed of, a control signal area comprising ID, SYNC, etc., shown in Fig 4(b), and a user data recording area comprising n₂ blocks. Each block is composed of n₃ bytes as shown in Fig. 4(c). At the beginning or at the end of this block, a resynchronisation signal is added composed of a specified data bit pattern and a code bit pattern. The above specified data bit pattern and code bit pattern are briefly described below. The data bit pattern is a bit pattern before modulation. It comprises a row of consecutive data, for example a data row as shown in Fig. 5(a). When this bit pattern is 2-7 modulated, as shown in Fig. 5(b), as the word length of the 2-7 modulation/demodulation system is variable, a bit pattern that cannot be modulated using the 2-7 conversion rule may occur at the end of a data row or at the dividing portion of block. Accordingly, a specified data bit pattern is added in order to satisfy the 2-7 conversion rule to ensure that the entire data of a block or row can be modulated. One example of a suitable specified data bit pattern for application to the end of a data row or block is shown in Fig. 5(c). The specified code bit pattern is a bit pattern after modulation. It is used in the detection of the beginning of a block during demodulating. In order to enhance the reliability of demodulation, a pattern not produced as a result of modulation using the 2-7 conversion code, such as the code bit pattern shown in Fig. 6(a) is preferable. Part (1) of the pattern of Fig. 6(a) is the same as the pattern after modulation of the specified data bit pattern shown in Fig. 5(c). By adding part (2) of Fig. 6(a) to this data row, a pattern which is not produced by modulation using the 2-7 conversion rule is obtained. When the pattern of Fig. 6(a) is demodulated, the result is always the pattern of Fig. 6(b). In the system shown in Fig. 1, the data being read out by the drive unit (DU) 100 for recording and reproducing data is synchronised by a PLL circuit 200, from which read data RDDT and read clock RDCK are delivered. The RDDT and RDCK signals are fed into a pattern detector circuit 10 composed of a shift register, a pattern discriminator, and a 2-7 demodulation circuit 23. The pattern detector circuit 10 discriminates the RDDT, and detects the specified code bit pattern and SYNC pattern, and delivers a detection signal to the comparator 17. The RDDT fed into the 2-7 demodulation circuit 23 is converted into parallel by the shift register 11, and is assembled by a gate group 12 to be returned to serial data S23. the read clock RDCK is directly divided into RDCK and RDCK through NOT circuit 24, which are respectively fed into demodulation clock generator circuits 15, 16, to generate demodulation clock signals DMCK1, DMCK2. DMCK1 and DMCK2 are respectively fed into flip-flops (FF) 13, 14. In the flip-flops (FF) 13, 14, the serial data S23 is synchronised for conversion back into data before modulation. As the data is demodulated in the flip-flops (FF) 13, 14 by demodulation clocks DMCK1, DMCK2 differing in phase, the data output from the respective flip-flops (FF) is different. Only one of the outputs corresponds to the original data before modulation. The outputs of the flip-flops (FF) 13, 14 are fed into a comparator 17, which receives the detection signal of a specified code bit pattern shown in Fig. 6(a) from the pattern detector circuit 10. The outputs of the flip-flops (FF) 13, 14 are compared with the bit pattern of Fig. 6(b) on receipt of the detection signal, and a judgement signal is delivered to a multiplexer (MPX) 18 depending on which output of the flip-flops (FF) 13, 14 corresponds to the bit pattern of Fig. 6(b). The multiplexer (MPX) 18 receives this judgement signal, and selects which output corresponds to the correctly demodulated data signal each time the signal of Fig. 6(a) is detected to ensure that a signal corresponding to the original data signal is delivered to the shift register 19. The present invention can thereby keep the spread of error in the demodulated data to a minimum when an incorrect inversion occurs in the read clock RDCK. Besides, as shown in Fig. 1, having two demodulation clock generator circuits 15, 16 and hence a normal demodulation clock DMCK1 and an inverted demodulation clock DMCK2, if an incorrect inversion occurs in the normal demodulation clock DMCK1, the next time the signal of Figure 6(a) is detected, the multiplexer (MPX) 17 selects the other demodulation clock DMCK2 for demodulation of the signal, so that any error in demodulation is limited to a single block, allowing normal demodulation of subsequent blocks. As is clear from the description above, through the use of two demodulation clocks differing in phase, even if an incorrect inversion occurs in the read demodulation clock due to skipping, overflow or some other cause during the demodulation of any one block, normal operation is restored for demodulation of the next block. The reliability of the demodulated data is thereby enhanced. In order to operate securely, it is important to detect the beginning portion of a block. In this invention, by using a pattern not produced by modulation of a signal using the 2-7 conversion code, that is, by using a pattern which is not produced in the coded data, the beginning of a block can be detected without fail. Incidentally, the pattern of Fig. 6 (a) may be also used as the bit pattern of SYNC information.

Claims: A data demodulation apparatus for demodulating a signal which includes coded data signal portions using a demodulation clock, the signal further including a signal portion comprising a predetermined signal pattern (Fig. 6a), characterized in that the signal is demodulated using a plurality of mutually phase-shifted demodulation clock signals (DMCK1, DMCK2), each providing a demodulation version of the signal, the correct demodulation pattern of the predetermined signal pattern producing a known demodulation pattern (Fig 6b) and there being provided means (17) for comparing the demodulated versions of the predetermined signal pattern obtained using the different clock signals with said known demodulation pattern to determine which of the demodulating clock signals is producing the correct demodulation of the coded data signal portions. A data demodulation apparatus according to claim 1 wherein the signal to be demodulated is divided into signal blocks, each including coded data signal portions and one said predetermined signal pattern (Fig. 6a), and wherein said comparing means is operable for each signal block to compare said demodulated versions of the signal pattern of that block with said known demodulation pattern and to determine which of the demodulating clock signals will produce correct demodulation of the coded data signal portions of that block. A data demodulation apparatus according to claim 1 or claim 2 characterized in that there are provided first and second demodulation means (13, 14) for demodulating the signal using first and second said demodulating clock signals respectively, and in that a signal selection means (18) is coupled to receive the demodulated signals from said first and second demodulation means and controlled in accordance with the output of said comparing means (17) to select that one of said demodulated signals which is correctly demodulated, for output from the apparatus. A data demodulation apparatus according to any of claims 1 to 3 characterised in that said predetermined signal pattern (Fig. 6a) is a pattern which cannot be produced by the encoding apparatus used to produce said coded data signal portions.

Inventors: DEGUCHI, TOSHIHISA DAIYA-HEIGHTS GAKUENMAE C-722, FUJIWARA, TSUNEO, KOBAYASHI, SHOZOU, MAEDA, SHIGEMI, TSUJI, KENTAROH, YAMAGUCHI, TAKESHI
Applicants: SHARP KABUSHIKI KAISHA
Application year: 1987
Main classification: H03M5
IPC codes: G11B20, G11B27, H03M5