SEMICONDUCTOR MEMORY CIRCUIT HAVING A FAST READ AMPLIFIER TRISTATE BUS DRIVER

Abstract: The invention relates to a C-MOS semiconductor memory circuit having a read amplifier and a tristate bus driver. The read amplifier is a two stage amplifier. The bit lines in the memory are connected via P-MOS pull-up transistors to the supply voltage. The logic low level is 1 Volt below the supply voltage. In order to bring the input signals for the difference amplifier at a most sensitive and fast level, a d.c.-shifting amplifier of the "emitter follower" type is connected between each input thereof and the associated bit line. Bot the difference amplifier and the two follower amplifiers are activated only for a short period of time by means of a selection signal which gives a strong restriction in the power dissipation. The tristate driver comprises a push-pull output stage and an inverting AND gate which is controlled by the output of a difference amplifier and by an equalisation signal which is also applied to the difference amplifier and therefore is simple of design and gives only a low signal delay.

Description: The invention relates to a CMOS semiconductor memory circuit, having memory cells (M) with a selectable connection to a read amplifier (SA), the read amplifier feeding a tristate data bus driver (TSD) which has a push-pull output stage comprising a first (P5) and a second (N5) output transistor with their channels in serial arrangement, the memory circuit having control means (DEQ) for making the first and second output transistors simultaneously non-conductive in order to bring the output (O2) of the output stage in a high impedance state. Such a semiconductor memory circuit is known from the conference ISSCC 1984, February 23, pp . 214-215 and 340, in which it was stated already that delay times occuring in word and bit lines and also in read amplifiers and bus drivers are of vital importance for memory circuits of large capacity (for example, 256 k bit). A small dissipated power and compact buffers in a memory of comparatively large capacity are also of importance. It is the object of the invention to provide a tristate buffer which is compact. A semiconductor memory circuit according to the invention is characterized in that the read amplifier feeds the output stage via an inverting AND circuit (N41, N42, P41, P43), the read amplifier being coupled to a first input of the AND circuit formed by respective connected gates of a first (N41) and a second (P41) AND transistor, the AND circuit also having a second input formed by further respective connected gates of a third (N42) and fourth (P42) AND transistors, respective channels of the second (P41) and fourth (P42) AND transistors being connected in a parallel arrangement, which is connected in series with successively the further channnels of the third (N42) and first (N41) AND transistors, a first node between the parallel arrangement (P41, P42) and the third AND transistor (N42) being coupled to a gate of the first output transistor (P5), a second node between the channels of the first (N41) and third (N42) AND transistors being coupled to the second output transistor (N5), wherein the first output transistor (P5), the second (P41) and fourth (P42) AND transistor are all of a first transistor type, being either NMOS or PMOS, and the second output transistor (N5), the first (N41) and third (N42) AND transistors are all of a second transistor type, different form the first transistor type and wherein the control means (DEC are arranged for in the high impedance state of said output (O2) controlling the first and second input such that the first AND transistor (N41) and the fourth AND transistor become conductive (P42). The use of such a tristate buffer is compact and is active only if the control means do not make both the first and fourth AND transistors conductive which need be only of a very short duration (for example, during the active state of the read amplifier or ony at the end of the active period thereof). The invention will be described in greater detail with reference to an embodiment shown in the drawing. The drawing shows a simplification of a memory circuit 1 according to the invention. The memory circuit 1 comprises memory cells which are arranged in columns and rows and of which only one cell M in a column J is shown in the drawing. The memory cell M is a C-MOS cell which is known per se and which is connected to the two bit lines B and B via two pass transistors I1 and I2. The two pass transistors I1 and I2 are controlled via the word line I for accessing the cell M for a read or write action. The two bit lines B and B are each connected, via pull up transistors P1 and P2, respectively, to a supply point VDD. An equalising transistor BE is connected between the bit lines B and B and is made conductive for a moment by means of an equalisation signal REQ before a memory cell M in said column is connected to the bit lines B and B . Via two pass transistors J1 and J2, which are controlled by means of a column selection signal YJ, the two bit lines B and B are connected to the read amplifier SA . Via the transistors J3, J4 or J5, J6 or J7, J8, the two bit lines of the columns J+1 or J+2 or J+3 can be connected to the read amplifier SA . The read amplifier SA comprises three amplifiers; a first and a second follower amplifier and a difference amplifier. The first and the second follower amplifiers, respectively, comprise the transistors N11, N12 and N21, N22, respectively. The difference amplifier comprises three P-MOS transistors P31, P32 and P33 and three N-MOS transistors N31, N32 and N33. By using the pull-up transistors P1 and P2 the logic "high" voltage approaches approximately the supply voltage VDD, while the logic low level is set approximately 1 Volt below VDD. In order to bring voltage levels of the logic high and logic low signals on the bit lines B and B at the level which is most senstive for the difference amplifier with the input transistors N31 and N32, the two d.c.-shifting follower amplifiers are used with the transistors N11, N12 and N21, N22. The three amplifiers are activated with a selection signal SEC which is supplied to three transistors N12, N22 and N32. The selection signal SEC activates the three amplifiers only for a comparatively short period of time. It is hence permitted, due to gain in velocity, to permit a comparatively high dissipation in the amplifiers. As long as the selection signal SEC is not active, an equalisation signal DEQ which is applied to the transistor P33 can keep said transistor turned on for equalising the voltage levels in the two amplifier branches with the transistors P31, N31 and P32, N32. An output 01 of the read amplifier SA is applied to an output of a C-MOS inverting AND gate of a tristate driver TSD. The inverting AND gate comprises the P-MOS transistors P41, P42 and the N-MOS transistors N41, N42 and further receives the equalisation signal DEQ. The output of the inverting AND gate is connected to the gate electrode of P-MOS transistors P5 of the push pull output stage of the tristate bus driver TSD. The N-MOS transistor N5 of the output stage is connected to the junction between the N-MOS transistors N41 and N42. The output 0 2 is connected to an internal read bus of the memory which via a latch circuit known per se is applied to an output buffer. It will be recognized that as long as the equalisation signal DEQ is low, the transistor P42 is turned on and the transistors P5 and N42 are turned off. The N-MOS transistor N41 will further be blocking N-MOS transistor N5 or will be blocking this transistor due to a signal received via output 01 of the read amplifier SA in which the equalisation signal DEQ turns on the transistor P33 and in which the transistors N12, N22 and N33 will be turned off again. The output of the bus driver TSD is now floating (has a high output impedance).

Claims: CMOS semiconductor memory circuit, having memory cells (M) with a selectable connection to a read amplifier (SA), the read amplifier feeding a tristate data bus driver (TSD) which has a push-pull output stage comprising a first (P5) and a second (N5) output transistor with their channels in serial arrangement, the memory circuit having control means (DEQ) for making the first and second output transistors simultaneously non-conductive in order to bring the output (O2) of the output stage in a high impedance state, characterized, in that the read amplifier feeds the output stage via a inverting AND circuit (N41, N42, P41, P43), the read amplifier being coupled to a first input of the AND circuit formed by respective connected gates of a first (N41) and a second (P41) AND transistor, the AND circuit also having a second input formed by further respective connected gates of a third (N42) and fourth (P42) AND transistors, respective channels of the second (P41) and fourth (P42) AND transistors being connected in a parallel arrangement, which is connected in series with successively the further channels of the third (N42) and first (N41) AND transistors, a first node between the parallel arrangement (P41, P42) and the third AND transistor (N42) being coupled to a gate of the first output transistor (P5), a second node between the channels of the first (N41) and third (N42) AND transistors being coupled to the second output transistor (N5), wherein the first output transistor (P5), the second (P41) ad fourth (P42) AND transistor are all of a first transistor type, being either NMOS or PMOS, and the second output transistor (N5), the first (N41) and third (N42) AND transistors are all of a second transistor type, different form the first transistor type, and wherein the control means (DEQ) are arranged for in the high impedance state of said output (O2) controlling the first and second input such that the first AND transistor (N41) and the fourth AND transistor (P42) become conductive. A CMOS semiconductor memory circuit according to Claim 1, characterized, in that control means (DEQ) in the high impedance state of said output (O2) make a levelling transistor (P33) in the read amplifier conductive.

Inventors: HARTGRING, CORNELIS DIETWIN
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: G11C7
IPC codes: G11C7, G11C11