Method of detecting and correcting an error in a digital computer

Abstract: The present invention relates to a method of de­ tecting and correcting an error taken place in a digital computer, which comprises the steps of: counting the number of mark bits in each predeter­ mined area of each of component units constituting data, each of the component units being expected to be re­ presented by one of reference inner representations; detecting the occurrence of an error in the area when the count value is not identical with any of preset reference values in the corresponding areas;and correcting the component unit of the data in which the error has been detected, by a reference inner re­ presentation having a reference value in the correspond­ ing area which is the closest to the count value. The present invention provides a method of detect­ ing and correcting an error taken place in a digital computer, by which method detecting and correcting an error of change in a plurality of bits of data are easily carried out.

Description: Background of the Invention Field of the Art The present invention relates to a method of detecting and correcting an error that has taken place in a digital computer. Prior Art In a conventional digital computer, there are instances where the contents of data are erroneously changed during data transmission or data processing mainly due to hardware errors such as noise. In a digital computer, numerical data are generally represented internally by binary numbers. For example, a numeral "9" in a decimal notation is internally represented as "1001" in a binary notation. Accordingly, a change in one bit of the most significant bit of the data due to noise or the like, causes the data to be internally represented as "0001". This presents a disadvantage that the inner representation "0001" is treated as "1" in the decimal notation. Further, it is not possible to correct the numerical data in which such error has taken place, to the original numeral "9" in the decimal notation. As to character data, if a 2-bit error takes place in, for example, an ASCII code with a parity bit, such error cannot be detected and corrected. Thus, conventionally there are no detector means for directly detecting, in data internally represented by a plurality of bits, an error of change in a plurality of bits of these bits, even though the number of such changed bits is small. Therefore, for example in banking business, such error might provoke an accident where an amount of money to be handled is changed by one digit. Objects of the Invention It is an object of the present invention to provide a method of detecting and correcting an error taken place in a digital computer, by which method detecting and correcting the error above-mentioned are easily performed. Summary of the Invention In order to achieve the object above-mentioned, the present invention provides an error detecting and correcting method which comprises the steps of: counting the number of mark bits in each predetermined area of each of component units constituting data such as numerical data, character data or the like, in which an error is to be detected and corrected, each of the component units being expected to be expressed by one of a predetermined number of reference inner representations consisting of mark and space bits: detecting the occurrence of an error in the predetermined area if the number of mark bits thus counted is not identical with any reference number of mark bits in the corresponding areas of any of the reference inner representations; and correcting the component unit including the error thus detected, by one of the reference inner representations having a reference number of mark bits in the corresponding area which is the closest to the number of mark bits in the area of which the error has been detected. It is appreciated that the present invention also includes a method in which "space bits" are used instead of "mark bits". Data such as numerical data, character data and the like are constituted by one or more component units. Each component unit is expected to be expressed by one inner representation, which is selected out of a predetermined number of reference inner representations. Each component unit includes a plurality of areas. The count numbers of mark bits in the respective areas are previously set as the reference numbers for each reference inner representation. The following will discuss how to compare data with the reference inner representations to detect and correct an error taken place during transmission, processing and the like of such data. First, the number of mark bits in one area of one component unit of the data is counted. The mark bit number thus counted is compared with a reference number of mark bits in a corresponding area of each reference inner representation. When the mark bit number is not identical with the reference number, it is detected that an error has been taken place in this area of the data. When the error is detected, the component unit of the data including such error is corrected by one of the reference inner representations having a reference number of mark bits in the corresponding area which is the closest to the mark bit number in the area of which the error has been detected. The error detecting and correcting operations above-mentioned are carried out for every area of every component unit, whereby error detection and correction can be carried out for the entire data. As discussed hereinbefore, the present invention provides a method of detecting and correcting an error taken place in a digital computer, which is capable of easily detecting and correcting even error of change in the contents of a plurality of bits of data. In accordance with the present invention, processing based on space bits can also be executed instead of processing based on mark bits. Brief Description of the Drawings Figure 1 is a flowchart showing an embodiment of the present invention; Figure 2 is a view showing an illustrative set of reference inner representations; Figure 3 is a flowchart applied to the reference inner representations in Fig. 2, showing an example of the steps 2 to 4 in the flowchart in Fig. 1; Figure 4 is a view showing the inner representation of a component unit of data including no error, to which the flowchart in Fig. 3 is applied; Figure 5 is a view showing the inner representation of a component unit of data in which an error has taken place, to which the flowchart in Fig. 3 is applied; Figure 6 is a view showing another illustrative set of reference inner representations; Figure 7 is a flowchart applied to the reference inner representations in Fig. 6, showing another example of the steps 2 to 4 in the flowchart in Fig. 1; Figure 8 is a view showing the inner representation of a component unit of data including no error, to which the flowchart in Fig. 7 is applied; Figure 9 is a view showing the inner representation of a component unit in which an error has taken place, to which the flowchart in Fig. 7 is applied. Detailed Description of the Preferred Embodiments The following description will discuss embodiments of the present invention with reference to the attached drawings. Figure 1 is a flowchart showing an embodiment of the present invention. In this embodiment, data are constituted by A pieces of component units U(I) (I = 1 to A). An inner representation D(I) (I = 1 to A) of each of component units U(I) constituting data of which an error is to be detected and corrected, is selected out of B pieces of reference inner representations R(J) (J = 1 to B). M pieces of areas E(I, K) (I = 1 to A, K = 1 to M) are set in each of component units U(I). Correspondingly, M pieces of areas S(J, K) (J = 1 to B, K = 1 to M) are set in each of reference inner representations R(J). For the reference inner representations R(J), mark bit count values T(J, K) (J = 1 to B, K = 1 to M) of the areas S(J, K) are previously set as reference values. The following description will discuss the respective steps of the flowchart in succession. Counted at the step 1 is the number of mark bits of an area E(I, K) of a component unit U(I) of data of which an error is to be detected and corrected, whereby a count value X(I, K) is obtained. At the step 2, it is judged whether or not this count value X(I, K) is identical with any of reference values T(J, K) of the areas concerned. When there is a reference value identical with the count value X(I, K), no error is considered to have taken place, and the processing is finished. On the contrary, if there is no reference value identical with the count value X(I, K), an error in an area E(I, K) of the component unit U(I) is detected at the step 3. Searched at the step 4 is a reference inner representation R(J) having a reference value T(J, K) which is the closest to the count value X(I, K). The component unit U(I) of the data including such error is rewritten by this reference inner representation R(J) to correct the error. The processing is then finished. The following description will discuss an example of the steps 2 to 4 of the flowchart with the use of an example of the reference inner representations R(J) (J = 1 to B). Fig. 2 shows an illustrative set of reference inner representations with B being equal to 8. Each of the reference inner representations R(J) (J = 1 to 8) is constituted by 8 x 8 bits, or 64 bits, and a mark bit is represented by "x". In Fig. 2, an 8-box row represents 1 byte, and the length of one reference inner representation is equal to 8 bytes. Each reference inner representation R(J) is constituted by four portions. A portion I is constituted by 16 bits, i.e., the upper 4 bits of the former-half 4 bytes, while a portion II is constituted by 16 bits, i.e, the lower 4 bits of the former-half 4 bytes. Each of a portion III and a portion IV is constituted by 16 bits, i.e., the upper or lower 4 bits of the latter-half 4 bytes. A reference inner representation R(1) shown in Fig. 2 (a) has the portions I and II in which all bits are mark bits, and the portions III and IV in which all bits are space bits. A reference inner representation R(2) shown in Fig. 2 (b) has the portions I and III in which all bits are mark bits, and the portions II and IV in which all bits are space bits. A reference inner representation R(3) shown in Fig. 2 (c) has the portions I and IV in which all bits are mark bits, and the portions II and III in which all bits are space bits. A reference inner representation R(4) shown in Fig. 2 (d) has the portions I, II, III and IV in which all bits are mark bits. As shown in Fig. 2 (e) to (h), reference inner representations R(5) to R(8) are those in which the mark bits and the space bits in the reference inner representations R(1) to R(4) are inverted. The number of areas is equal to 4. For J which is from 1 to 8, an area S(J, 1) is constituted by the portions I and IV, an area S(J, 2) is constituted by the portions I and II, an area S(J, 3) is constituted by the portions I, II and III, and an area S(J, 4) is constituted by the portions I, II, III and IV. When the reference inner representations R(J)(J = 1 to 8) and the areas S(J, K) (J = 1 to 8, K = 1 to 4) are determined as above-mentioned, the reference values T(J, K)(J = 1 to 8, K = 1 to 4) are determined as shown in Table 1. Data will be judged according to the flowchart in Fig. 3, whereby an error is detected and corrected. More specifically, by counting the number of mark bits in an area E(I, K) of a component unit U(I), a count value X(I, K)(K = 1 to 4) is obtained, after which, at the step 1, a distance Y(I, J)(J = 1 to 8) between an inner representation D(I) and each reference inner representation R(J) is calculated according to the following equation (1): Y(I, J) = (X(I, 1) - T(J, 1)) * * 2 + (X(I, 2) - T(J, 2)) * * 2 + (X(I, 3) - T(J, 3)) * * 2 + (X(I, 4) - T(J, 4)) * * 2 (J = 1 to 8) (1) It is here noted that "* * 2" is a mark representing an operation of raising to the second power, and the distance Y(I, J) is a square sum of a difference between a reference value and a count value obtained for each area. Searched at the step 2 is a minimum value Y(I, L) out of values Y(I, 1) to Y(I, 8) calculated at the step 1. At the step 3, it is judged whether or not this minimum value Y (I, L) is equal to 0. When the minimum value Y is equal to 0, it means that no error has taken place. Thus, the inner representation D(I) is not corrected and the processing is finished. If the minimum value Y(I, L) is not equal to 0, it is judged that an error has taken place in the inner representation D(I) of the component unit U(I) and that a reference inner representation R(L) is closest to the inner representation D(I). At the step 4, the inner representation D(I) is corrected to the reference inner representation R(L). According to the flowchart above-mentioned, the count values X(I, 1), X(I, 2), X(I, 3) and X(I, 4) of, for example, an inner representation D(I) shown in Fig. 4, are 16, 32, 32 and 32, respectively. Out of the distance values Y(I, 1) to Y(I, 8), the Y(I, 1) is the minimum distance value which is equal to 0. Accordingly, it is judged that no error has taken place. On the other hand, it is now supposed for example that, out of 64 bits of the inner representation D(I) shown in Fig. 4, 12 bits are inverted to produce an error, so that the inner representation D(I) becomes as shown in Fig. 5. In such case, the count values X(I, 1), X(I, 2), X(I, 3) and X(I, 4) are 14, 25, 27 and 30, and the distance values Y(I, 1) to Y(I, 8) are 82, 114, 530, 1970, 754, 210, 306 and 2450, respectively. Of these, the minimum distance value is Y(I, 1) which is not equal to 0. Accordingly, an error is detected and this inner representation D(I) is corrected to the reference inner representation R(1). The following description will discuss another example of the steps 2 to 4 of the flowchart shown in Fig. 1 with the use of another example of the reference inner representations R(J) (J = 1 to B). Fig. 6 shows an illustrative set of reference inner representations with B being equal to 13. Each of the reference inner representations R(J) (J = 1 to 13) is constituted by 8 x 8 bits or 64 bits, and a mark bit is represented by "x". Likewise the previous example, an 8-box row represents one byte, and the length of one reference inner representation is 8 bytes. The number of areas M is equal to 4. For J which is from 1 to 13, an area S(J, 1) is constituted by 16 bits of the first and second bytes. Areas S(J, 2), S(J, 3) and S(J, 4) are constituted by the third & fourth bytes, the fifth & sixth bytes, and the seventh & eighth bytes, respectively. The reference inner representations R(1) to R(13) shown in Fig. 6 (a) to (m) are those for numerical data and respectively represent "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "+", "-" and ".". When the reference inner representations R(J) (J = 1 to 13) and the areas S(J, K) (J = 1 to 13, K = 1 to 4) are determined as above-mentioned, the reference values T(J, K) (J = 1 to 13, K = 1 to 4) are determined as shown in Table 2. According to a flowchart shown in Fig. 7, data are to be judged to detect and correct an error. In such case, every reference value T (J, K) (J = 1 to 13, K = 1 to 4) of any area of any reference inner representation is equal to 0 or 16, and does not become other numeral than 0 and 16. Therefore, count values X(I, K) obtained by counting the numbers of mark bits in the areas E(I, K) can be divided into two groups, i.e., one equal to or greater than 9 and the other equal to or smaller than 8. Accordingly, when it is judged that a count value X(I, K) is not equal to 0 or 16 with an error taken place, the error is detected and corrected by a reference inner representation having a reference value closest to the count value above-mentioned. For example, for an inner representation D(I) shown in Fig. 8, the count values X(I, 1), X(I, 2), X(I, 3) and X(I, 4) are 16, 16, 0 and 16, respectively. Through the processings at the steps 1, 2, 3, 4, 5, 7, 8 and 9, this inner representation is judged to be numerical data "2" represented by a reference inner representation R(2). It is now supposed for example that an error has taken place in which 14 bits out of 64 bits of the inner representation D(I) in Fig. 8 have been inverted as shown by an inner representation D(I) in Fig. 9. In such case, the count values X(I, 1), X(I, 2), X(I, 3) and X(I, 4) are 13, 14, 5 and 12, respectively, which are neither 0 nor 16. Thus, an error is detected. In this case too, the processing proceeds at the same steps as those for the inner representation shown in Fig. 8, and the error is corrected to numerical data "2" represented by the reference inner representation R(2). In this case, it is possible to detect and correct the error by merely checking a relationship in size between the count value X(I, K) and the reference inner representations at most three or four times. When using one of the inner representations above-mentioned for each component unit, each of these inner representations represents one digit of a decimal number. For example, numerical data "+12" are represented by a successive combination of the reference inner representations which are shown in Figs. 6 (k), (b) and (c) in this order, and have total 192 bits. These numerical data as expressed by the inner representations can be operated when the operation rule is determined in the same manner as for the operation of the decimal notation. More specifically, the method in accordance with the present invention can be applied not only for detection and correction of an error taken place at the time of data transmission between a main memory device and an auxiliary one or between digital computers, but also for detection and correction of an error taken place in the operation in the CPU. That is, the method of the present invention can be made in firmware and incorporated in the CPU, so that an error can be detected and corrected each time the CPU fetches data for data transmission or data operation. The use of the above-mentioned inner representations having a sufficient redundancy requires a large-capacity memory and a high-speed CPU. Such requirements can be met with a recent tendency of decreased costs of memories and the advancement of high-speed CPU technology.

Claims: Method of detecting and correcting an error that has taken place in a digital computer, comprising the steps of: counting the number (X) of mark bits in each predetermined area (S) of each of component units (U) constituting data such as numerical data, character data or the like, in which an error is to be detected and corrected, each of said component units being expected to be represented by one of a predetermined number (R) of reference inner representations consisting of mark and space bits; detecting the occurrence of an error in said area when said number (X) of mark bits is not identical with any reference number (T) of mark bits in the corresponding areas of any of said reference inner representations; and correcting said component unit of which the error has been detected, by one of said reference inner representations (R) having a reference number (T) of mark bits in the corresponding area which is the closest to the number of mark bits (X) in said area of which the error has been detected.

Inventors: IMAZU RYUZO, IMAZU, RYUZO
Applicants: FUJI SANGYO CO LTD, FUJI SANGYO CO., LTD.
Application year: 1987
Main classification: G06F11
IPC codes: G06F11