SEMICONDUCTOR DEVICE HAVING A BURRIED LAYER

Abstract: A semiconductor device has a structure in which two semiconductor substrates (1, 2) are coupled to each other through a semiconductor oxide film (3) and a metal silicide film (9), and a semiconductor element, for example, a bi-polar transistor is formed in the semicon­ ductor substrate (2) on the metal silicide film side, whereby a metal silicide layer (9) having a high melting point is provided beneath one region of the bi-polar transistor for example, an n⁺ buried collector layer (5) and in ohmic contact with the n⁺ buried collector layer. An electrical isolation between the adjacent semiconduc­ tor elements is made by an insulating layer (12, 18).

Description: The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a bi-polar transistor suitable for high speed operation and high density integration. An example of a prior art concerning a semiconductor device including a bi-polar transistor is disclosed in Japanese patent application JP-A-59-80968. In a semiconductor device according to the disclosed prior art, a collector region is formed by a highly doped layer of n conductivity type buried in a substrate and an isolation between device elements such as transistors is made by the combination of a pn junction and a thick silicon oxide (hereinafter referred to as SiO₂) film formed by means of selective oxidation. Fig. 1 shows a cross-sectional structure of a bi-polar transistor included in the semiconductor device according to the above-mentioned prior art. In the figure, reference numeral 30 designates a silicon substrate of p⁻ type, numeral 31 a buried collector layer of n⁺ type, numeral 32 a p⁺ layer for isolation between device elements, numeral 33 a region for isolation between device elements, numeral 34 an emitter, numeral 35 a base layer, and numeral 36 an SiO₂ film. This bi-polar transistor is constructed in such a manner that the n⁺ buried collector layer 31, the base layer 35 and the emitter layer 34 are formed successively in that order on the p⁻ substrate 30 and the inter-element isolation region 33 including the p⁺ isolation layer 32 and the SiO₂ film 36 is provided between the adjacent device elements. In general, a collector series resistance r CS of the bi-polar transistor is an important factor in implementing a device of high speed. Namely, when the collector series resistance r CS is high, it is difficult to operate the transistor at a high speed since a product f T of gain and band width is lowered and the transistor is liable to its saturated state in a large-current region. Therefore, it is necessary to control the collector series resistance r CS into a sufficiently low value. The collector series resistance r CB of the conventional bi-polar transistor shown in Fig. 1 is formed by a series resistance including a resistance r CS1 between a collector layer pulling region and the n⁺ buried collector region 31, a resistance r CS2 of the n⁺ buried collector layer 31, and a resistance r CS3 between the n⁺ buried collector layer 31 and a lightly doped collector layer of n⁻ type, as is shown in the figure. A dominant resistance component which determines the magnitude of the collector series resistance r CS , is the resistance r CS2 or the resistance of the n⁺ buried collector layer 31. Usually, the sheet resistance of the n⁺ buried layer which is formed by doping with a donor type impurity such as Sb or As, has a magnitude on the order of 100 Ω/▭. With reduction in the size of device elements such as transistors formed in a semiconductor device, it is required to further narrow the depth of the n⁺ buried collector layer in a direction of its thickness. Accordingly, the semiconductor device shown in Fig. 1 has a problem that if high density is aimed with a structure which stands as it is, the collector series resistance r CS becomes more large, thereby making a high speed operation of the device difficult. Also, in the above-mentioned conventional semiconductor device, if the width d of the isolation between the adjacent device elements formed by the combination of the SiO₂ film 36 and the pn junction is designed into a small value, the application of a negative bias to the collector layer causes a punch-through effect or the depletion of the p⁺ isolation layer 32 provided in the inter-element isolation region 33, thereby rendering a conductive state between the adjacent buried collector layers of n⁺ and n⁺. Therefore, it is necessary to make the width d of the inter-element isolation region 33 larger than a distance at which no punch-through of the p⁺ isolation layer 32 takes place. Accordingly, the conventional semiconductor device has a problem that the fine delineation of the inter-element isolation width is difficult and hence a high integration of the device cannot be achieved. Further, the above-mentioned prior art has a problem that a relatively large electrostatic capacitance is produced the pn junction between the p+ isolation layer 32 and the n+ buried collector layer 31 and this pn junction increases an electrostatic capacitance between the collector and the substrate, thereby making the operation speed of the semiconductor device slow. The US-A-3 614 558 discloses a semiconductor device of the so-called DI (dielectric isolation) structure in which two semiconductor substrates are coupled to each other through a semiconductor oxide film and a metal silicide film. A bipolar transistor is formed in the semiconductor substrate on the metal silicide film side and the collector region of said transistor is connected to said metal silicide film. The buried metal layer reduces the collector series resistance. Said transistor and additional circuit elements are buried inside one of the substrates so that the semiconductor elements are naturally isolated from each other by not only an insulating layer but also a part of said substrate. EP-A2-0 107 902 discloses that a groove covered by an insulating layer is provided between the islands. Therefore, the islands are electrically conductive with each other through a p-type semiconductor layer so that it would involve a problem of failure such as latch-up due to parasitic pnpn-thyristor function between the elements. An object of the present invention is to provide a bi-polar type semiconductor device suitable for high speed and higher integration by providing a semiconductor device structure by which the above-mentioned problems of the prior art are solved, the collector series resistance r CS as well as the electrostatic capacitance between the collector and the substrate can be made sufficiently small and the isolation width d between device elements can be set to a sufficiently small value. Said object is achieved, according to the present invention, by a semiconductor device comprising a semiconductor substrate having a substantially flat main surface, an insulating layer fomred on said main surface of said semiconductor substrate and a plurality of monocrystalline/metal-silicide islands formed on said insulating layer, said islands being isolated from one another with an insulating material other than the material of said substrate, each island including a metal-silicide layer disposed over a portion of said insulating layer, a monocrystalline layer formed on said metal-silicide layer and a semiconductor element formed into said monocrystalline layer, said insulating material extending through said metal-silicide layer to said insulating layer. The metal silicide layer provided beneath the n⁺ buried collector layer is connected to the collector layer in ohmic contact therewith. Therefore, the value of the collector series resistance r CS is determined by the sheet resistance of the metal silicide layer and hence can be greatly reduced in comparison with the case of the prior art. For example, in the case where a tungsten silicide (WSi₂) layer of having a thickness of 350 nm (3500 Å), the sheet resistance of the silicide layer is about 2 Ω/▭ which is about one fiftieth of the sheet resistance of the n⁺ buried collector layer in the case of the prior art. Thereby, the value of the collector series resistance r CS is also reduced to the similar extent and hence a high speed operation of the device is possible. Further, since the adjacent device elements are isolated from each other by only the insulating layer, the problem of punch-through in the case of the isolation using a pn junction according to the prior art is not encountered so that the isolation width between the device elements can be made small to a value determined by the breakdown strength of the insulating layer. Thus, a high integration of elements in the semiconductor device can be easily attained. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a vertical cross-sectional view of a semiconductor device according to the prior art; Fig. 2 is a vertical cross-sectional view of a semiconductor device according to an embodiment of the present invention; Figs. 3a to 3f are vertical cross-sectional views for respectively explaining the steps for fabrication of the semiconductor device shown in Fig. 2; and Fig. 4 is a view for explaining the etching characteristic of an etchant used in the fabrication step. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention will now be explained in detail by virtue of the accompanying drawings. In the drawings, Fig. 2 shows a vertical cross-sectional view of a semiconductor device according to an embodiment of the present invention, Figs. 3a to 3f are vertical cross-sectional views of the semiconductor device at respective fabrication steps thereof, and Fig. 4 shows a view for explaining a relationship between the concentration of an n-type impurity in silicon and the silicon etching rate for an etchant used in the fabrication step. In Figs. 2 and 3, reference numeral 1 designates an n⁻ silicon substrate, numeral 2 an n⁺ silicon substrate, numeral 3 an SiO₂ film, numeral 4 a monocrystalline silicon layer, numeral 5 an n⁺ collector layer, numeral 6 a polycrystalline silicon film, numerals 7 and 8 Mo films, numeral 9 an MoSi₂ layer, numerals 10 and 12 SiO₂ films, numeral 11 an inter-element isolation region, numeral 13 a collector layer pulling region, numeral 14 a base region, numeral 15 an emitter electrode, numeral 16 an emitter region, numeral 17 a base drawing region, numeral 18 a phosphosilicate glass PSG film, and numeral 19 an electrode wiring layer. A bi-polar transistor which is the semiconductor device according to the present invention, is constructed in such a manner that as shown in Fig. 2, the SiO₂ film 3, the metal silicide (MoSi₂) layer 9, the n⁺ collector layer 5 of high impurity concentration connected to the metal silicide layer 9 in ohmic contact therewith, the base layer 14, the emitter layer 16 are laminated successively in this order on the n⁻ silicon substrate 1, and an insulating layer including the SiO₂ film 12 and the PSG film is provided as an inter-element isolation region between the adjacent device elements. Next, the steps for fabrication of the semiconductor device shown in Fig. 2 will be explained by use of Figs. 3a to 3f which show vertical cross sections for the respective fabrication steps. As shown in Fig. 3a-1, a substrate A is fabricated in which an SiO₂ film 3 of about 500 nm (5000 Å) thickness is disposed on an n⁻ silicon substrate 1 having an impurity concentration of 10¹⁵ cm⁻³ and an Mo film 7 of 150 nm (1500 Å) is disposed on the SiO₂ film 3. On the other hand, as shown in Fig. 3a-2, a substrate B is fabricated in which a monocrystalline silicon layer 4 having an impurity concentration on the order of 10¹⁷ cm⁻³ is epitaxially grown on an n⁺ silicon substrate 2 having an impurity concentration of 2 x 10²⁰ cm⁻³, an n⁺ collector layer 5 is thereafter formed by implanting ions of As, and a polycrystalline silicon film 6 of about 550 nm (5500 Å) thickness and an Mo film 8 of 50 nm (500 Å) thickness are successively provided on the n⁺ collector layer 5. By carrying out a heat treatment at about 900°C in a state where the surfaces of the substrates A and B having the Mo films 7 and 8 respectively are disposed into close contact under pressure with each other, the Mo films 7 and 8 are reacted with the polycrystalline silicon film 6, thereby forming an MoSi₂ film 9 of about 450 nm (4500 Å) thickness (see Fig. 3b). After a resist, such as Si₃N₄ film (not shown) is formed on each of the side faces of the laminate of the substrates A and B thus secured to each other, for masking the silicide exposed at the side faces, etching is carried out by using an etchant having a component ratio of HF:HNO₃:CH₃COOH = 1:3:16 to remove only the n⁺ silicon substrate 2 (see Fig. 3c). Since the etchant used has an etching characteristic exhibiting such an etching rate for an n-type impurity concentration as shown in Fig. 4 and can selectively etch away only n conductivity type silicon of high impurity concentration, it is possible to leave the n⁻ epitaxial layer 4 by self-selection. Next, an SiO₂ film 10 is deposited by selective oxidation. Thereafter, the n⁻ monocrystalline silicon layer 4, the n⁺ collector layer 5 and the MoSiO₂ film 9 are removed like a groove by a usual dry etching method to form an inter-element isolation region 11. Then, the entire surface of the substrate is oxidized to form an SiO₂ film 12 (see Fig. 3d). Thereafter, a collector layer pulling region 13 is formed through selective implantation of As ions and heat treatment and a base region 14 is then formed through selective implantation of B ions and heat treatment. Further, after selectively removing a portion of the SiO₂ film in a region where an emitter is to be formed, a polycrystalline silicon film is deposited on the entire surface of the resultant structure. Ions of As are implanted into the polycrystalline silicon film and the structure is subjected to a heat treatment to form an emitter region 16. Then, the polycrystalline silicon film is selectively worked to provide an emitter electrode 15. Thereafter, a base drawing region 17 is formed through selective implantation of B ions and heat treatment (see Fig. 3e). Next, a PSG film 18 is provided on the entire surface of the resulting structure. By selectively removing the PSG film 18 and the SiO₂ film 12, a through-hole is formed on each region of the collector, emitter and base. Thereafter, a conductive film made of, for example, Al is deposited on the entire surface of the structure and then selectively etched to provide an electrode wiring layer 19 (see Fig. 3f). In this manner, a bi-polar type transistor can be obtained which is a semiconductor device according to the present invention. In the bi-polar type semiconductor device according to the above-mentioned embodiment of the present invention, since the n⁺ collector layer 5 of high impurity concentration and the collector pulling region 13 are connected to the underlying MoSi₂ film 9 in ohmic contact therewith, the collector series resistance r CS can be made small to a value which is substantially determined by the sheet resistance 2 Ω/▭ of the MoSi₂ film 9. Accordingly, in this semiconductor device, a saturation in a large-current region can be inhibited and a product f T of gain and band width can be made large, thereby allowing a high speed operation of the device. Further, since the inter-element isolation region 11 is provided by an insulating layer which includes the SiO₂ film 12 and the PSG film 18, the width of the isolation region 11 can be made small to a value determined by the breakdown strength of the insulating films 12 and 18. Furthermore, since the inter-element isolation region has no pn junction, an electrostatic capacitance between the collector and substrate can be made small. Therefore, high speed operation, high integration and high density can be easily attained in the device according to the above-mentioned embodiment. In the foregoing embodiment, the MoSi₂ film 9 has been provided as a metal silicide film beneath the n⁺ collector layer 5 of high impurity concentration and the collector pulling region 13. However, the metal silicide film may be made of WSi₂ or TiSi₂. Any other material can be used for the metal silicide film so long as the material is a metal silicide having a high melting point and a low resistance. Since the features of the present invention are to reduce the collector series resistance r CS by providing a low resistance material beneath the collector layer and to implement high integration of the device by isolating the device elements from each other by means of an insulating layer, similar effects can be attained even if any difference in structure except the just-mentioned features exists or even if any difference in fabrication method exists, for example, the isolation between the collector 13 and the base 14 may be achieved by forming a thin film of SiO₂ in a narrow slot disposed therebetween in place of the SiO₂ layer 10 used in the illustrated embodiment. As has been explained, according to the present invention, the collector series resistance r CS can be reduced to a value equal to or smaller than (one)/(several tens) of the collector series resistance in the conventional device and an electrostatic capacitance between the collector and the substrate can be also made small. Therefore, the device of high speed can be attained. The isolation between device elements is made by means of an insulating layer. Therefore, the device of high integration and high density can be easily attained.

Claims: A semiconductor device comprising a semiconductor substrate (1) having a substantially flat main surface, an insulating layer (3) formed on said main surface of said semiconductor substrate (1) and a plurality of monocrystalline/metal-silicide islands formed on said insulating layer (3), said islands being isolated from one another with an insulating material (12, 18) other than the material of said substrate (1), each island including a metal-silicide layer (9) disposed over a portion of said insulating layer (3), a monocrystalline layer (4) formed on said metal-silicide layer (9) and a semiconductor element formed into said monocrystalline layer (4), said insulating material (12, 18) extending through said metal-silicide layer (9) to said insulating layer (3). A semiconductor device according to claim 1, wherein said semiconductor element is a bi-polar transistor the collector region of which is connected to said metal silicide layer (9).

Inventors: HOMMA, HIDEO, MISAWA, YUTAKA, MOMMA, NAOHIRO
Applicants: HITACHI, LTD.
Application year: 1987
Main classification: H01L21
IPC codes: H01L29, H01L21