Solid state image pick-up device

Abstract: A solid state image pick-up device includes means for cancelling difference of impedance between photo-sensing areas in a photo-sensitive array. The impedance difference cancelling means cancels or makes the difference of impedance at each photo-sensing area negligible so as to render uniform the handling charge in respective photo-sensing areas. In practice, the impedance difference cancelling means provides a resistance high enough to enable the impedance difference between respective photo-sensing areas to be ignored.

Description: The present invention relates generally to a solid-state image pick-up device utilizing a charge coupled device (CCD). More specifically, the invention relates to a solid state image pick-up device which can render more uniform the picture quality at each pixel. Solid state image sensors comprising a charge transfer device such as a charge coupled device (hereinafter referred to as CCD) are classified broadly into the frame transfer type and the interline transfer type. Such solid state image sensors comprising a CCD have been given attention as devices able to realize a compact image pick up apparatus, namely, a television camera in miniaturized size operative with low power consumption and with high reliability. However, on the contrary to the above advantage, previously proposed solid state image sensors comprising the CCD have encountered with several problems as for the undesirable phenomena called ''blooming'' and ''smear''. Considering the solid state image sensors of the interline transfer type, such as sensing device comprises a sensing and vertical transfer portion including a plurality of photo-sensing areas provided to make horizontal rows and vertical rows, vertical charge transfer portions provided along each of the vertical rows of the photo-sensing areas and transfer gate areas provided between each of the photo-sensing areas the corresponding one of the vertical charge transfer portions, a horizontal charge transfer portion coupled with the vertical charge transfer portion and an output portion coupled with the horizontal charge transfer portion. The sensing and vertical transfer portions, horizontal charge transfer portions and output portions are formed on a common semiconductor substrate. The photo-sensing area is provided for producing a signal charge in response to the light received thereby and storing the signal charge therein. The transfer gate area is provided for transferring the signal charge stored in the photo-sensing area to the vertical charge transfer portion at each period corresponding to a vertical blanking period. The vertical charge transfer portion is provided for transferring the signal charge transferred from the photo-sensing area to the horizontal charge transfer portion in order at every period corresponding to a horizontal blanking period. The horizontal charge transfer portion is provided for transferring the signal charge transferred from the vertical charge transfer portion at each one of the periods corresponding the horizontal blanking periods to the output portion during a period corresponding to a horizontal video period. Further, the output portion is provided for taking out an image pickup signal output in response to the signal charge transferred from the horizontal charge transfer portion. In solid state image sensors of the interline transfer type using the CCD (hereinafter referred to as interline transfer CCD image sensors) previously proposed, when the light received by the photo-sensing area reaches to the inside of the semiconductor substrate placed under the photo-sensing area through the latter and a charge is produced thereby at the inside of the semiconductor substrate, such a charge partially flows into the vertical charge transfer portion undesirably without becoming the signal charge and is undesirably transferred by means of the charge transfer operation of the vertical charge transfer portion. This undesirably transferred charge becomes a noise component in the image pick-up signal output derived from the sensor which causes an eyesore, namely a white line on a picture obtained on an image display apparatus such as a picture tube in response to the image pick-up signal output. The effect of phenomenon which causes the white line eyesore on the picture is called "smear" and is one of the unsolved problems encountered with the previously proposed interline transfer CCD image sensors. Smear on the reproduced picture may also occur due to excessive carrier undesirably overflowing to other photo-sensing areas, when high intensity light is irradiated on the photo-sensing area to generate higher charge than the handling charge of the photo-sensing areas. In order to prevent smear on the picture, a so-called "overflow drain" is preferably provided in the image pick-up device. In recent years, a "channel stop region" has been used as the overflow drain for the excessive carrier generated in the photo-sensing areas in interlane transfer CCD. A CCD structure with the channel stop region has been illustrated on pp 39 of "CHARGE-COUPLED DEVICES: TECHNOLOGY AND APPLICATION" published by IEEE Press, and written by Walter F. Kosonocky in June, 1972. In the disclosure, the diffusion channel stop region is formed surrounding the sensing and vertical transfer section, in which the photo-sensing areas are arranged in a form of matrix to constitute a photosensitive array. When excessive carriers are generated, one of the carrier components, e.g. electrons, are drained to a base layer of the semiconductor substrate, which base layer serves as overflow drain. The other component, e.g. holes, of the carrier is then transferred to the channel stop region to be drained. However, because of the difference of the impedance at respective photo-sensing areas due to the differing distance between the photo-sensing area and the channel stop region, differences of carrier drain characteristics are caused. These differences in carrier drain characteristics with respect to each photo-sensing area result in differences in handling charge at individual photo-sensing areas. Since the brightness of the photo-sensing area is determined depending upon the handling charge thereof, due to the differences in the handling charge at different positions of the photo-sensing areas, the brightness of respective pixels on the reproduced image differ. This degrades the quality of the picture reproduced. According to the present invention, there is provided a solid state image pick-up device comprising: a photosensing means including a plurality of photosensing elements, each being adapted to receive light and produce a charge signal corresponding to the amount of incident light; charge transferring means for receiving said charge signal from said photosensing elements and transferring said charge signal to an output section; and drain means for providing a path for draining to ground or a power supply excess holes generated in each of said photosensing elements of said photosensing means and said charge transferring means; characterised by resistance means for providing a relatively high additional resistance in said path, said resistance being sufficiently high with respect to differences between other impedances in said path, which impedances may be different between different ones of said photosensing elements and said ground or power supply, that the potentials at different ones of said photosensing areas are substantially the same such that the depth of the potential wells in the different photosensing areas, and thus the handling charge of the respective photosensing areas are rendered substantially uniform. This is accomplished by a solid state image pick-up device according to the present invention which includes resistance means which makes the difference of impedance at every photo-sensing area insignificant to render uniform the handling charge in respective photo-sensing areas. In practice, the resistance means provides a resistance high enough to make the impedance difference between respective photo-sensing areas insignificant. The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. In the drawings: Fig. 1 is a plan view of the preferred embodiment of a solid state image pick-up device according to the invention; Fig. 2 is a cross-section of the solid state image pick-up device of Fig. 1; Fig. 3 is a fragmentary plan view of another embodiment of a solid state image pick-up device according to the invention; and Fig. 4 is a fragmentary plan view of a modification of the solid state image pick-up device of Fig. 3. Referring now to the drawings, particularly to Fig. 1, the preferred embodiment of an image pick-up device according to the invention comprises an interline transfer-type charge coupled device (CCD). The image pick-up device generally comprises a semiconductor substrate 10, a sensing and vertical transfer section 20 and a horizontal charge transfer section 30. The semiconductor substrate 10 is constituted of a base substrate 12, a first region 14 and a second region 16 (Fig. 2). In the shown embodiment, the base substrate 12 is formed of N-type semiconductor. More practically, the base substrate 12 is N-type silicon substrate. The first region 14 is formed by P-type layer which is deposited on the N-type silicon substrate. The second layer is formed by P⁻-type or N⁻-type layer and deposited on the first region 14. The first and second regions are deposited on the base substrate 12 by epitaxial growth. The surface of the second region 16 serves as a primary surface 18 of the semiconductor substrate 10 by selective diffusion or ion implantation. The sensing and vertical transfer section 20 includes a plurality of photo-sensing areas 22 and vertical shift registers 24. Each of the photo-sensing area 22 serves as a picture element or pixel for receiving the light to produce and store a signal charge therein. A given number of photo-sensing areas 22 are arranged in spaced apart relationship to each other and aligned along the associated vertical shift register 24. The vertical shift register 24 receives signal charge from the associated photo-sensing areas and vertically transfers the signal charge at every period corresponding to the horizontal blanking period. Each of the shift registers 24 and the associated photo-sensing areas 22 constitute a vertical transfer portion 26. The vertical shift registers 24 are associated with a horizontal shift register 32 in the horizontal charge transfer section 30 to output the signal charge therethrough to an output section 34. In the shown embodiment, an inner channel stop region 40 are formed surrounding the aforementioned sensing and vertical transfer section 20. This inner channel stop region 40 is a low impurity concentration region formed by doping impurity, such as boron B. In a practical implementation, the inner channel stop region 40 is formed by doping boron as impurity in the order of 10¹² atoms/cm³ by diffusion or ion implantation. The inner channel stop region 40 is connected to an outer channel stop region 42 at both ends thereof through bridging section 44. The outer channel stop region 42 comprises an inner low impurity concentration region 46 and an outer high impurity concentration region 48. The low impurity concentration region 46 of the outer channel stop region 42 has the identical composition to that of the inner channel stop region 40 and preferably formed simultaneously to formation of the inner channel stop region. On the other hand, the high impurity concentration region 48 has higher impurity concentration than that in the inner channel stop region. In practice, the high impurity concentration region 48 is formed by doping impurity, such as boron B,in the order of 10¹⁴ atoms/cm². The high impurity concentration region 48 is formed in advance of formation of the inner channel stop region 40 and the low impurity concentration region 46. The high impurity concentration region 48 is formed with a plurality of contacting points 50 through which it contact with A1 wiring 52. These contacting points 50 have applied to them a potential at the ground level or a predetermined level, through the wiring 52. Therefore, the contact points 50 serves as a terminal section. Between the inner channel stop region 40 at the low impurity concentration region 46 of the outer channel stop region 42, a resistor region 54 is formed. Namely, the resistor region 54 is formed in a space defined by the inner channel stop region 40, the low impurity concentration region 46 and the bridging section 44. In the preferred construction, the resistor region 54 is formed of a meshed structure. By forming the resistor region 54 in the meshed structure, influence of damaging of part of the resistor region 54 can be eliminated or reduced. As shown in Fig. 2, in the shown embodiment, the base substrate 12 is formed of N-type semiconductor substrate. The first region 14 is formed into P⁺-type region by doping P⁺-type impurity and the second region 16 is formed into N⁻-type region by doping N⁻-type impurity. Each photo-sensing area 22 is formed in the second region 16 by doping N⁺-type impurity by selective diffusion or ion implantation, in a predetermined area and through a given depth in conjunction with the primary surface 18 of the semiconductor substrate 10. The upper surface of each photo-sensing area 22 is covered bya mutually separate, independent surface region 26. The surface regions 26 are electrically conductive. Similarly to the photo-sensing area 22, each of the surface regions 26 are formed by doping P⁺-type impurity by way of selective diffusion or ion implantation, in a predetermined area and substantially thin given depth. The surface regions 26 are exposed to the primary surface 18 of the semiconductor substrate 10. Forming the surface region 26 will successfully eliminate noise to be created by influence of defects in the crystal structure at the surface area of the semiconductor substrate 10. On the other hand, the shift register 24 comprises a vertical charge transfer region 28 formed on the primary surface 18 of the semiconductor substrate 10. The vertical charge transfer region 28 is also formed by doping N⁺-type impurity by way of selective diffusion or ion implantation, similarly to the photo-sensing areas 22. The primary surface 18 of the semiconductor substrate 10 is coated by an insulating layer 60. The insulating layer may comprise a SiO₂ layer. A surface electrode 62 is formed over the insulating layer 60. The surface electrode 62 is formed of a transparent material for passing the light. A given fixed potential is applied to the sensing and vertically transfer section 20 through the surface electrode 62. Transfer electrodes 64 are provided, to which a two-phase clock voltage for the vertical shift register 24, is applied. The transfer electrodes 64 also serve as transfer gate electrodes for transferring the signal charge of respectively associated photo-sensing sreas 22 to the corresponding charge transfer region 28. As seen from Fig. 2, each of the transfer electrodes 63 is disposed within the insulating layer 60 and thus electrically insulated from surface electrode 62. In practice, the surface electrode 62 and the transfer electrodes 64 are formed of a silicon monocrystalline dopped impurity to provide low specific contact resistance. The channel stop regions 40 and 42 are also formed in the second region 16. As will be seen from Fig. 2, the inner channel stop region 40 and the low impurity concentration region 44 of the outer channel stop region 42 are formed by doping P⁻-type impurity at low rate. The inner channel stop region 40 adjoins with the adjacent photo-sensing areas 22 and the surface regions 26. The high impurity concentration region 46 are formed by doping P-type impurity at high rate. A P-type region (not shown) is formed through the second region 16 to establish electric communication between the high impurity concentration region 46 and the first region 14 of the semiconductor substrate 10. In the construction set forth above, a given positive voltage, e.g. 10V is applied to the base substrate 10 to enable the operation of the image pick-up device. Electrons are thus generated in each photo-sensing area 22. The number of electrons generated in the photo-sensing area 22 will be determined corresponding to the amount of the light received. When the amount of electrons generated in the photo-sensing area 22 exceeds a possible handling charge of the photo-sensing area, and further exceeds the value of an overflow barrier established in the first region 14, the excessive carriers, i.e. the overflown electrons are absorbed in the base substrate 12 which serves as an overflow drain. On the other hand, the other carrier, e.g. the holes, are drained through the inner channel stop region 40. As set forth above, since the inner channel stop region 40 is connected to the terminal section 50 through high resistance registor region 54, to be connected to the ground or power supply, the potential at every sections of the inner channel stop region 40 becomes substantially uniform. As a result, the distance between each individual photo-sensing area 22 and the inner channel stop region 40 can not influence to carrier absorbing characteristics of each section of the inner channel region 40. This allows the depth of the potential well in the photo-sensing areas 22 and thus the handling charge in respective photo-sensing area to be rendered uniform. Fig. 3 shows another embodiment of the image pick-up device according to the invention. A P⁺-type region 70 is formed between N-type base substrate and N⁻- type surface layer of the N-type semiconductor substrate 72, in substantially similar manner to that illustrated in Fig. 2. As is well known, the P⁺-type region 70 is formed by exitaxial growth on the N-type base substrate. A sensing and vertically transfer section 74 is formed on the aforementioned N⁻-type surface layer at the position approximately corresponding to the center of the P⁺-type region 70. The structure of the sensing and vertical transfer section 74 is substantially the same as that illustrated in Figs. 1 and 2 and thus does not described in detail in order to avoid redundant recitation. A horizontal shift register 76 is also formed within the well region 70 and located adjacent the aforementioned sensing and vertical transfer section 74. Adjacent one end of the horizontal shift register 76, an output section 78 is formed. The output section 78 is located away from the sensing and vertically transfer section 74. A channel stop region 75 is formed along the boundary of the sensing and vertical transfer section 74. With the construction set forth above, and as discussed with respect to the former embodiment, one component of the carriers, e.g. electrons are drained to the N-type base substrate via the P⁺-type region 70 and the other carrier component, e.g. holes, are drained to the channel stop region 75. A first grounding wiring 80 is also formed on the N⁻-type surface layer and located in an area corresponding to the P⁺-type region 70. The grounding wiring 80 is arranged on the channel stop region 75 and connected thereto. The first grounding wiring 80 substantially surrounds the sensing and vertical transfer section 74 with leaving one edge of the sensing and vertical transfer section 74 open, which edge opposes to the horizontal shift register. The grounding wiring 80 is connected to the ground level 82 through a resistor 84. A second grounding wiring 86 is further formed on the N⁻-type surface layer adjacent the horizontal shift register 76. As shown in Fig. 3, the second grounding wiring 86 extends substantially along the longer edge at the side remote from the sensing and vertical transfer section 74 and along the shorter edge at the side remote from the output section 78. This second grounding wiring 86 is directly connected to the ground level. A third grounding wiring 88 is formed on the surface layer of the semiconductor substrate adjacent the output section 78. The third grounding wiring substantially surrounding the output section 78 with leaving an edge portion opposite one edge of the horizontal shift register open. Similarly to the aforementioned second grounding wiring 86, the third grounding wiring is directly connected to the ground level. As will be seen from Fig. 3, in the shown embodiment, the P⁺-type region 70 is formed on the semiconductor substrate with providing portions 90 and 92 where the P⁺-type layer is not deposited and is the bear N-type substrate. As seen from Fig. 3, the portion 90 is located between ends of the first and second grounding wirings 80 and 86 to define a high resistance region 96. Also, the portion 92 is located between the first and third grounding wirings 80 and 88 to define therebetween a high resistance region 98. With this construction, respective first, second and third grounding wirings 80, 86 and 88 are separated to each other by the high resistance regions 96 and 98 defined therebetween. Therefore, the potentials at the second and third grounding wirings 86 and 88 which are directly connected to the ground level, will never influence to the sensing and vertical transfer section 74. It should be appreciated that, though the shown embodiment provides the high resistance regions 96 and 98 by providing the portions 90 and 92, it would be possible to form such high resistance regions by reducing the depth of the channel stop region to provide high resistance. Also it would be possible to form a substantially high resistance region or insulating region by dopping suitable impurity by way of ion implantation in order to reduce conductivity. On the other hand, the resistor 84 can be formed on the semiconductor substrate 72 or can be interposed between the ground level 82 and the grounding wiring 80 as an external accessory. By providing the high resistance regions and by providing the resistor between the first grounding wiring and the ground level, the potential at the sensing and vertical transfer section is provided at different level to the ground level. This isolates the sensing and vertical transfer section from the directly grounded grounding wirings. With this arrangement, the potential becomes different at respective portions in the sensing and vertical transfer section 74, because of difference of distance to the grounding wiring. However, by providing sufficient impedance which is determined by combined resistance of the high resistance region and the resistor inserted between the first grounding wiring and the ground level, the potential difference at respective portions in the sensing and vertical transfer section can be relatively small to be ignored. Therefore, by adjusting the resistance in the high resistance region and the resistor, the potential in each portion of the sensing and vertically transfer section can be held uniform. Therefore, handling charge in each of the photo-sensing areas in the sensing and vertically transfer section become substantially uniform. In practice, the required combined resistance for maintaining the potential at every portions of the sensing and vertical transfer section uniform will be different depending upon the size of the sensing and vertical transfer section, capacity Cox of the oxide layer of gate electrode, level of the pulse to be applied to the electrode, and so forth. However, in practice, the combined resistance may be set in a range of 10 to 100 Ω. Fig. 4 shows a modification of the aforementioned another embodiment of the image pick-up device of Fig. 3. In this modification, the first and second grounding wirings in the former embodiment are integrally formed to constitute a single grounding wiring 102. Similarly to the foregoing embodiment, the grounding wiring 102 is connected to the ground level through a resistor 84. This grounding wire 102 is disconnected from the third grounding wiring 88 which is directly connected to the ground level by the portions 92 and 94 defining the high resistance regions 98 and 100. Even in this modification, the potential at every portion of the sensing and vertical transfer section 74 can be maintained uniform by adjusting combined resistance of the high resistance regions 98 and 100 and the resistor 84. Therefore, handling charge in each photo-sensing areas in the sensing and vertical transfer section 74 become substantially uniform.

Claims: A solid state image pick-up device comprising: a photosensing means (20; 74) including a plurality of photosensing elements (22), each being adapted to receive light and produce a charge signal corresponding to the amount of incident light; charge transferring means (24, 30, 32; 76) for receiving said charge signal from said photosensing elements (22) and transferring said charge signal to an output section (34; 78); and drain means (40, 42, 44; 75, 80) for providing a path for draining to ground or a power supply excess holes generated in each of said photosensing elements (22) of said photosensing means and said charge transferring means (24, 30, 32; 76); characterised by resistance means (54; 84) for providing a relatively high additional resistance in said path, said resistance being sufficiently high with respect to differences between other impedances in said path, which impedances may be different between different ones of said photosensing elements and said ground or power supply, that the potentials at different ones of said photosensing areas are substantially the same such that the depth of the potential wells in the different photosensing areas, and thus the handling charge of the respective photosensing areas are rendered substantially uniform. A solid state image pick-up device according to claim 1, wherein said drain means (40, 42) comprises a channel stop region formed around said photo-sensing means and transferring means. A solid state image pick-up device according to claim 2, wherein said channel stop region is connected to a wiring means (52) which in use is connected to a voltage source which applies a given voltage to said wiring means (52). A solid state image pick-up device according to claim 3, wherein said given voltage source is arranged to apply a ground level voltage to said wiring means (52). A solid state image pick-up device according to claim 3 or 4, wherein said channel stop region comprises a first low resistance region (48) and a second low resistance region (46, 40). A solid state image pick-up device according to claim 5, wherein said resistance means comprises a resistor region (54) formed within said second low resistance region. A solid state image pick-up device according to claim 6, wherein said wiring means is connected to a high impurity region in said channel stop region. A solid state image pick-up device according to claim 6 or 7, wherein said resistor region (54) is formed into a meshed structure. A solid state image pick-up device according to claim 3, wherein said resistance means comprises a resistor (84) interposed between said wiring and said voltage source which applies ground level as said given voltage. A solid state image pick-up device according to claim 9, wherein said charge transferring means includes a vertical transferring means (24) for vertically transferring said charge signal of said photosensing elements and a horizontal transferring means (32) for receiving said charge signal transferred through said vertical transferring means (24) and horizontally transferring said charge signal to said output section (34). A solid state image pick-up device according to claim 10, wherein said wiring means comprises a first wiring means (80) extending around said sensing and vertical transferring means (74), a second wiring means (86) extending around said output section (34), and a third wiring means (88) extending around said horizontal transferring means (76), said first wiring means (80) being connected to said voltage source via said resistor and said second and third wiring means (86, 88) being directly connected to ground. A solid state image pick-up device according to claim 11, which further comprises means for defining a high resistance region (96, 98) between said sensing and vertical transferring means (74) and said horizontal transferring means (76). A solid state image pick-up device according to claim 12, which further comprises means for defining a high resistance region (100) between said horizontal transferring means and said output section (78). A solid state image pick-up device according to claim 10, wherein said wiring means comprises a first wiring means (80) extending around said sensing and vertically transferring means (74) and said horizontally transferring means (76), and a second wiring means (80) extending around said output section, said first wiring means (80) being connected to said voltage source via said resistor (84) and said second wiring means being directly connected to ground. A solid state image pick-up device according to claim 14, which further comprises means for defining a high resistance region (100) between said sensing and vertically transferring means (74) and said output section (78).

Inventors: HAMASAKI MASAHARU C O SONY COR, ISHIKAWA KIKUE C O SONY CORPOR, KAGAWA YOSHIAKI C O SONY CORPO, SUZUKI TOMOYUKI C O SONY CORPO, YONEMOTO KAZUYA C O SONY CORPO, HAMASAKI, MASAHARU C/O SONY CORPORATION, ISHIKAWA, KIKUE C/O SONY CORPORATION, KAGAWA, YOSHIAKI C/O SONY CORPORATION, SUZUKI, TOMOYUKI C/O SONY CORPORATION, YONEMOTO, KAZUYA C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1987
Main classification: H04N3
IPC codes: H01L21, H01L27, H04N5