Array-word-organized memory system

Abstract: An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of said CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of said RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of said CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.

Description: The present invention relates in general to a display memory and an address generator for addressing the display memory and in particular to an array-word-organized display memory and an address generator with a time-multiplexed address bus for addressing word-aligned and non-word-aligned arrays of pixels in the display memory. Images are displayed on a display screen by scanning pixels in a display memory. To avoid flicker, updating a frame of pixels should be done in less than a typical frame time, e.g. 1/60 of a second. Hence, for a screen with 1Kx1K pixels, the bandwidth required is approximately 60 megapixels/second. In order to satisfy the above-described required bandwidth, it has been the practice to organize display memories by words wherein each word comprises a plurality of pixels. Heretofore, one such type of display memory has comprised a plurality of words which are aligned along a scan line so that the video refresh controller could simply load each word in a shift register and shift them out as video data for the screen. On the other hand, in order to change the image appearing on the screen, a word of data was accessed and one or more pixels in the word were changed, each such access comprising a read and a write, requiring a minimum of two memory cycles. A disadvantage of the above-described horizontally word-aligned organization was that, if the pixels to be updated crossed word boundaries, not only in a horizontal direction but also in a vertical direction, as in the case of vectors and characters, an unnecessarily high number of memory cycles were required to complete an update. For example, to load an 8x10 character that spans two words could take as many as 20 memory cycles instead of the 10 cycles required in the aligned case. To at least partially overcome the disadvantages of horizontally word-aligned display memory organizations, word-array memory organizations have been proposed. In an article entitled, A VSLI Architecture for Updating Raster-Scan Displays by S. Gupta and R.F. Sproull, Computer Graphics, Vol. 15, Number 3, August 1981, pp. 71-78, the authors disclose a display memory in which the pixels are organized in 8x8 arrays with each array comprising 64 pixels. In this organization, it is stated that an 8x10 character can be transferred in maximum 4 memory cycles. In the apparatus proposed by Gupta et al, a plurality of 64 16-kilobit memory chips with each chip providing one of the pixels in an 8x8 array, a plurality of 8 address buses, each bus comprising 7 address lines, 8 lines, 8 lines and a graphics processor having two address outputs, are provided. The 64 chips may be considered as being arranged in 8 rows and 8 columns. One of the 8 address buses and one of the lines is routed through each of the 8 columns of memory chips. One of the 8 lines is routed through each of the 8 rows of memory chips. The 8 address buses are coupled to a pair of address outputs of the graphics processor. The lines are coupled in parallel to a strobe output of the graphics processor. The lines are coupled to separate strobe outputs of the graphics processor. Assuming that the pixels in an arbitrary 8x8 pixel array fall within the boundaries of four 8x8 word-aligned arrays, that the address of the upper leftmost word-aligned array is X,Y, that the address of the array to the right of X,Y is X+1,Y, that the address of the array below X,Y is X,Y+1, and that the address of the pixels in the array to the right of X,Y+1 is X+1,Y+1, then the address of a pixel in the X,Y array is X*X+i , y*8+j , where i is the number of pixels from the left edge of the word-aligned array X,Y and j is the number of pixels below the top edge of the word-aligned array X,Y. To address the arbitrary array, wherein the upper leftmost pixel is located at (X*8+i,Y*8+j) , takes three time periods. In the first time period, t₁, the address Y is placed on all of the 8 address buses and the lines on the (8-j) rows from the bottom of the display memory array are strobed. In the second time period, t₂, the address Y+1 is placed on all of the 8 address buses and the lines on the j rows from the top of the display memory are strobed. At this point, all of the chips have the correct Y address. In the third time period, the address X+1 is placed on the first (8-i) address buses of the display memory, the address X is placed on the rest of the i address buses of the display memory and the lines to all of the memory chips are strobed. At this point, all of the chips have the correct X and X+1 addresses and the pixel data for the selected 8x8 unaligned-word-array is available. While the above-described prior known array-word addressing scheme is advantageous in that it allows for addressing an arbitrary 8x8 word-array in three time periods, it also has a number of disadvantages. For example, the large number of conductors required between the graphics processor and the memory chips, e.g. 8 buses of 7 wires each for an 8x8 array of 16 kilobit chips, all of which carry identical information in the first and second memory cycles, is very difficult to fabricate because the conductors are so narrow and closely spaced. Moreover, as the size of the chips is increased the number of such conductors must also be increased, making the fabrication of the memory system even more difficult. For example, a 64 kilobit chip requires 8 address lines, a 256 kilobit chip requires 9 address lines, etc. Additionally, the graphics processor requires a special port dedicated to outputting the X+1 address at the same time as the X address, the scheme disallows partial X access to the 8x8 array thereby disallowing banking in the X direction, the size of the elementary array can't be changed dynamically from the original 8x8 array and the scheme disallows interleaved banking. The term "banking" as used here is a term defining the use of two distinct groups of 64 memory chips. "Interleaving" is a scheme that allows alternating arrays to belong to alternate banks. For example: array X,Y belongs to bank 0, array X+1,Y belongs to bank 1, array X+2Y belongs to bank 0, array X+3,Y belongs to bank 1, etc. We will describe a method and apparatus comprising an array-word-organized display memory system. In the system there is provided a graphics processor comprising an address generator for addressing a plurality of arbitrary arrays of pixels wherein each array is AWS x pixels wide and AWS y pixels long and a predetermined number of banks of memory chips, each of said banks comprising a plurality of rows and a plurality of columns of memory chips, each of said memory chips having a plurality of rows and a plurality of columns of pixels. A single address bus is routed through all of the memory chips for addressing rows and columns of the pixels in the memory chips in a time-multiplexed manner. The row and column address of each pixel is designated by a pair of coordinates y and x. A plurality of lines are provided wherein one of said lines is routed through each one of said plurality of columns of memory chips. A plurality of lines is provided wherein one of said lines is routed through each one of said plurality of rows of memory chips. In accordance with the present invention there is provided an array-word-organized memory system including an addressing means for addressing a plurality of arbitrary arrays of pixels in said memory system wherein each array comprises a plurality of columns of pixels each AWS y .NB y pixels long and a plurality of rows of pixels each AWS x . NB x pixels long, and y and x are, respectively, the overall row and column address of a pixel on the display screen within the memory system in the first row and first column of that array, comprising: NB x .NB y banks of memory chips, each of said banks comprising AWS y rows and AWSx columns of memory chips, each of said memory chips having a plurality of rows and a plurality of columns of pixel cells; an address bus routed through all of said memory chips; a plurality of CAS lines wherein each one of said CAS lines is routed through each chip of a respective one of said plurality of columns of memory chips; a plurality of RAS lines wherein each one of said RAS lines is routed through each chip of a respective one of said plurality of rows of memory chips; means (2) for applying a row address Y to said address bus during a time t₁ for addressing a first predetermined row of pixels cells in each of said memory chips, where Y = the integer value of and NB y is the number of said banks of said memory chips in a y direction; means for strobing said RAS lines in AWS y. NB y -j rows of row numbers from j to AWS y .NB y of said memory chips during said time t1 where j is the remainder of means for applying a row address Y+1, to said address bus during a time t₂ for addressing a second predetermined row of said pixels cells in each of said chips; means for strobing said RAS lines in the remainder of said rows of said memory chips during said time t₂; means for applying a column address X to said address bus during a time t₃ for addressing a first predetermined column of said pixels cells in each of said memory chips, where X = the integer value of and NB x is the number of said banks in an x direction; means for strobing said CAS lines in AWS x .NB x -i columns of column numbers from i to AWS x .NB x of said memory chips during said time t₃, where i is the remainder of means for applying a column address X+1 to said address bus during a time t₄ for addressing a second predetermined column of said pixels cells in each of said chips; and means for strobing said CAS lines in the remainder of said columns of said memory chips during said time t₄. In a further aspect the present invention provides a method of addressing an array-word-organized memory system having an addressing means for addressing a plurality of arbitrary arrays of pixels in said memory system wherein each array comprises a plurality of columns of pixels each AWS y .NB y pixels long and a plurality of rows of pixels each AWS x .NB x pixels long, and y and x are, respectively, the overall row and column address of a pixel on the screen within the memory system in the first row and first column of that array, NB x .NB y banks of memory chips, each of said banks comprising AWS y rows and AWS x columns of memory chips, each of said memory chips having a plurality of rows and a plurality of columns of pixel cells, an address bus routed through all of said memory chips, a plurality of CAS lines wherein one of said CAS lines is routed through each chip of a respective one of said plurality of columns of memory chips and a plurality of RAS lines wherein one of said RAS lines is routed through each chip of a respective one of said plurality of rows of memory chips, comprising the steps of: applying a row address Y to said address bus during a time t₁ for addressing a first predetermined row of pixel cells in each of said memory chips, where Y = the integer value of and NB y is the number of said banks of said memory chips in a y direction; strobing said RAS lines in AWS y .NB y -j rows of said memory chips during said time t₁ where j is the remainder of applying a row address Y+1 to said address bus during a time t₂ for addressing a second predetermined row of said pixels in each of said chips; strobing said RAS lines in the remainder of said rows of said memory chips during said time t₂; applying a column address X to said address bus during a time t₃ for addressing a first predetermined column of said pixels in each of said memory chips, where X = the integer value of and NB x is the number of said banks in an x direction; strobing said CAS lines in AWS x .NBx -j columns of said memory chips during said time t₃, where i is the remainder of applying a column address X+1, to said address bus during a time t₄ for addressing a second predetermined column of said pixels in each of said chips; and strobing said CAS lines in the remainder of said columns of said memory chips during said time t₄. In embodiments of the present invention, where multiple banks of memory chips are provided, which extend in an x and/or y direction for expanding the capacity of the memory system. In operation, the memory chips in each of the banks are addressed in an interleaved fashion. By utilizing a single address bus which is routed through all of the memory chips instead of multiple address buses as heretofore used in prior known array-word-organized memory systems, problems associated with fabricating boards requiring large numbers of address lines are avoided. Also, a single port of the graphics processor is all that is required to supply all of the addresses to the chips, the array-word size can be changed dynamically, for example, from 8 x 8 to 4 x 4, and interleaved banking in both the x and y direction are readily possible. Brief Description of the Drawings The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the accompanying drawings, in which: Fig. 1 is a block diagram of a single memory bank embodiment of the present invention; Fig. 2 is a block diagram of the / decoder of the apparatus of Fig. 1; Fig. 3 is a block diagram of another embodiment of the present invention showing a pair of memory banks extending in a horizontal or x direction; Fig. 4 is a block diagram of the / decoder in the apparatus of Fig. 3; Fig. 5 is another embodiment of the present invention showing a pair of memory banks extending in a vertical or y direction; Fig. 6 is a diagram of four different-sized memory chips which can be used with the apparatus of the present invention; Fig. 7 is a diagram of a display screen according to the present invention; Fig. 8 is a diagram of a display memory showing an arbitrary array-word; Fig. 9 is a timing diagram in accordance with the present invention; Figs. 10 and 11 are tables showing the and lines which are strobed during the time periods t₁-t₄ for addressing an arbitrary word-array when only a single bank of memory chips is being used; Figs. 12 and 13 are tables which show the and lines which are strobed during the time periods t₁-t₄ for addressing an arbitrary word-array when two banks of memory chips are used in an x direction and two banks of memory chips are used in the y direction, respectively; Fig. 14 is a diagram of non-interleaved banking; Fig. 15 is a diagram of interleaved banking in the x direction; Fig. 16 is a diagram of interleaved banking in the y direction; and Fig. 17 is a diagram of interleaved banking in both the x and y directions. Detailed Description of the Drawings Referring to Fig. 1, there is provided in accordance with the present invention an array-word-organized memory system designated generally as 1. In the system 1 there is provided a graphics processor 2, a RAS / CAS decoder 3, and a single memory bank designated generally as 4. In the graphics processor 2 there is provided a time-multiplexed address output coupled to an address bus 10, a RAS enable control signal output ( RASEN1 ) coupled to a control signal line 11. A CAS enable control signal output ( CASEN ) coupled to a control signal line 12 and a RAS / CAS data output coupled to a RAS / CAS data bus 13. In the embodiment of Fig. 1, the address bus 10 comprises seven address lines and the RAS / CAS bus 13 comprises eight data lines. The lines 11 and 12 and bus 13 are coupled to inputs of the RAS / CAS decoder 3. In the RAS / CAS decoder 3 there is provided a first output coupled to a RAS signal bus 15 and a second output coupled to a CAS signal bus 16. Each of the buses 15 and 16 comprises eight RAS and CAS lines, respectively. In the memory bank 4 there is provided a plurality of 64 16-kbit memory chips. The address bus 10 is routed through all of the memory chips. Each of the eight CAS lines of the bus 16 is routed through one column of the memory chips. Similarly, each of the eight lines of the bus 15 is routed through one row of the memory chips. For convenience, the lines routed through each of the columns of memory chips are designated ₀- ₇, respectively. Similarly, the lines routed through each of the rows of the memory chips are designated ₀- ₇, respectively. Referring to Fig. 2, there is provided in the / decoder 3 a pair of registers 20 and 21. In the register 20 there is provided a clock input coupled to a source of clock pulses by a clock signal line 22, an enable input coupled to the control signal line 11, eight data inputs coupled to the data bus 13 and a plurality of outputs Q₀-Q₇ coupled to the lines ₀- ₇, respectively. Similarly, there is provided in the register 21 an input coupled to the source of clock pulses by means of a clock signal line 23, an enable input coupled to the control signal line 12, eight data inputs coupled to the data bus 13 and a plurality of outputs Q₀-Q₇ coupled to the lines ₀- ₇, respectively. Referring to Fig. 3, there is provided in another embodiment of the present invention, an array-word-organized memory system designated generally as 20. In the system 20 there is provided a graphics processor 21, a / decoder 22 and a pair of memory banks 23 and 24 which are coupled in parallel to ₀- ₇ and extend in an x direction. In the processor 21 there is provided an address output coupled to a 7-line address bus 25, a enable control signal output ( ) coupled to a control signal line 26, a first enable control signal output ( ) coupled to a control signal line 27, a second CAS enable output ( ) coupled to a control signal line 28 and a RAS/CAS data output ( ) coupled to an 8-line data bus 29. In the / decoder 22 there is provided inputs coupled to the control signal lines 26-28 and the data bus 29 and three outputs coupled to three / buses 30, 31 and 32, respectively. Bus 30 comprises eight lines designated ₀- ₇. Bus 31 comprises eight lines designated ₀- ₇. Bus 32 comprises eight lines designated ₈- ₁₅. In each of the memory banks 23 and 24, as in memory bank 4, there is provided 64 16-kbit memory chips. The memory chips are arranged in eight rows and eight columns. Each of the lines ₀- ₇ is routed through each of the columns of the memory chips in memory bank 23. Each of the lines ₈- ₁₅ is routed through each of the columns of the memory chips in memory bank 24. Each of the lines ₀- ₇ is routed through each of the rows of both memory banks 23 and 24. Referring to Fig. 4, there is provided in the / decoder 22 three registers 40, 41 and 42. In register 40 there is provided a clock input coupled to a source of clock pulses by means of a clock line 43, an enable input coupled to the bus 26 and eight data inputs coupled to the / data bus 29 and a plurality of outputs Q₀-Q₇ coupled to the RAS lines ₀- ₇. In the register 41 there is provided a clock input coupled to the source of clock pulses by means of the line 43, an enable input coupled to the control signal line 27, eight data inputs coupled to the data bus 29 and a plurality of outputs Q₀-Q₇ coupled to lines - . In the register 42 there is provided a clock input coupled to the source of cloak pulses by means of the clock signal line 43, an enable input coupled to the control signal line 28, eight data inputs coupled to the data bus 29 and a plurality of outputs Q₀-Q₇ coupled to the lines ₈- ₁₅. Referring to Fig. 5, there is provided in another embodiment of the present invention an array-word-organized memory system designated generally as 50. In the system 50 there is provided a graphics processor 51, a / decoder 52 and a plurality of memory banks 53 and 54. In the graphics processor 51 there is provided an address output coupled to a 7-line address bus 55, an control signal output coupled to a control signal line 56, an control signal output coupled to a control signal line 57, a control signal output coupled to a control signal line 58 and eight data outputs coupled to an 8-line data bus 59. In the / decoder 52 there is provided an input coupled to each of the control signal lines 56, 57 and 58, eight data inputs coupled to the data bus 59 and three 8-line output buses designated 60, 61 and 62, respectively. The lines in bus 60 are designated ₀- ₇. The lines in bus 61 are designated ₈- ₁₅ and the lines in bus 62 are designated ₀- ₇. In the memory banks 53 and 54, one of the lines ₀- ₇ is routed through each column of the memory banks 53 and 54. One of the lines ₀- ₇ is routed through each of the rows of the memory bank 53. One of the lines ₈- ₁₅ is routed through each of the rows of the memory bank 54. There is provided in the / decoder 52 three registers substantially identical to the registers 40-42 of Fig. 4 except that in the / decoder 52 the register 42 has an enable input coupled to the control signal line 57 and a plurality of outputs Q₀-Q₇ coupled to RAS lines ₈- ₁₅. Referring to Fig. 6, there is shown four memory chips 70, 71, 72 and 73. In memory chip 70 there is provided 16k pixels which are organized in 128 rows and 128 columns. To address each of the pixels, there is provided a 7-bit address bus 74. In memory chip 71 there is provided 64k pixels organized in 256 columns and 256 rows. To address the pixels in chip 71, there is provided an address bus 75 comprising eight address lines. In chip 72 there is provided 256k pixels organized in 512 rows and 512 columns. To address chip 72, there is provided an address bus 76 comprising nine address lines. Similarly, in chip 73 there is provided one million pixels organized in 1024 rows and 1024 columns. To address the pixels in chip 73, there is provided an address bus 77 comprising ten address lines. Each of the memory chips in the memory bank 4 of the apparatus of Fig. 1, the memory banks 23 and 24 of the apparatus of Fig. 3 and the memory banks 53 and 54 of the apparatus of Fig. 5 were described above as comprising a plurality of 16k chips. For this reason, address buses 10, 25 and 55 were described above as each comprising seven address lines. As will become apparent, if larger size memory chips are required, such as memory chips 71, 72 or 73, the number of address lines in each of the address buses 10, 25 or 55 must correspond to the number of lines in the address buses 75, 76 and 77, respectively. Referring to Fig. 7, there is shown a diagram of a portion of a display screen comprising a plurality of arrays of pixels 80, 81, 82, 83 and 84. Each of the arrays 80-84 comprises a 64-pixel word organized in rows and columns of eight pixels each. Arrays 80-83 are aligned arrays whereas 84 is an unaligned array. The upper case letters designate the row of the pixels. The lower case letters designate the columns of the pixels. Referring again to Fig. 1, in operation each of the 64 memory chips in the memory bank 4, for convenience numbered 0-63, stores and provides one of the pixels in each of the arrays 80-83. For example, pixel Aa in array 80 is stored in bit 0 of chip 0. Pixel Ab is stored in bit 0 of chip 1. Pixel Ac is stored in bit 0 of chip 2. Pixel Ba is stored in bit 0 of chip 8. Pixel Ca is stored in bit 0 of chip 16. Bit Hh is stored in bit 0 of chip 63, etc. Similarly, each of the memory chips 0-63 stores and provides one of the pixels in the array 81. For example, pixel Ai is stored in bit 1 of chip 0. Pixel Aj is stored in bit 1 of chip 1. Pixel Ak is stored in bit 1 of chip 2. Pixel Bi is stored in bit 1 of chip 8. Pixel Ci is stored in bit 1 of chip 16. Pixel Hp is stored in bit 1 of chip 63, etc. Since each 16k-bit chip comprises 128 rows and 128 columns of pixels, each such chip is addressed by means of a 7-bit pixel row address and a 7-bit pixel column address. For example, to address a particular one of the arrays 80-83, a 7-bit address X and a 7-bit address Y is applied in a time-multiplexed manner to all of the chips in the memory bank 4. For example, to address the pixels in the array 80, the addresses X=0 and Y=0 are applied to the chips 0-63. Since the addresses X=0 and Y=0 will address the bit 0 in each of the chips, all of the pixels in the array 80 will be addressed. Similarly, to address the pixels in array 81, the row address Y and the column address X+1 are applied to the memory chips 0-63. To address the pixels in array 82, the addresses X and Y+1 are applied to the memory chips 0-63. To address the pixels in array 83, the addresses X+1 and Y+1 are applied to the memory chips 0-63. In each of the above examples, X and Y are assumed to be 0. All of the lines ₀- ₇ were strobed when the addresses Y and Y+1 were applied to the address lines and the lines ₀- ₇ were strobed when the addresses X and X+1 were applied to the address lines. In general, the addresses X and Y are integers which are generated in the graphics processor by the integer division of the row and column addresses x,y of a pixel on the screen by the product of a number corresponding to the size of the array in the horizontal and vertical direction and the number of banks of memory chips in the X and Y direction, as follows: where AWS y = the number of pixels in an array in the y direction, AWS x = the number of pixels in an array in the x direction, NB y = the number of memory banks in the y direction, and NB x = the number of memory banks in the x direction. Referring to Fig. 14, there is shown a diagram of non-interleaved banking. All of the pixels having an address x between 0-7 have a corresponding array address X=0. Similarly, all of the pixels having an address x between 8 and 15 have a corresponding array address X=1, etc. Referring to Fig. 15, there is shown a diagram of interleaved banking. All of the pixels having addresses x between 0 and 15 have a corresponding array address X=0. Similarly, all of the pixels having an address x between 16 and 31 have a corresponding array address X=1, etc. Referring to Fig. 16, there is shown a diagram of interleaved banking in the y direction. All of the pixels having addresses y between 0-15 have a corresponding array address Y=0. Similarly, all of the pixels having addresses y between 16-31 have a corresponding array address Y=1, etc. Referring to Fig. 17, there is shown a diagram of interleaved banking in both the x and the y direction. Referring to Figs. 8 - 13 as well as Fig. 7, the arrays 80, 81, 82 and 83 are called word-aligned arrays because addresses x and y are integer multiples of AWS x and AWS y , respectively. By means of the present invention, it is also possible to address the pixels in a non-word-aligned array which overlaps two or more word-aligned arrays. For example, in Figs. 7 and 8 there is shown an array which overlaps the arrays addressed by the addresses (X,Y), (X+1,Y), (X,Y+1) and (X+1, Y+1). In Fig. 7, the above-described non-aligned array is defined by the corner pixels Cg, Cn, Jg and Jn. For convenience, this array is designated by the number 84. To address the array 84, it is necessary to generate the addresses X, Y, X+1 and Y+1, as well as to strobe selected ones of the and lines. The and lines which are strobed are set forth in the tables shown in Figs. 10 and 11. It will also be appreciated that i and j comprise the remainder of the integer divisions described above with respect to the calculation of the addresses Y and X, as follows: For example, referring to Fig. 9, during a first time period t₁, the address Y is applied to the memory chips 0-63 and with j=2(010) is enabled and lines ₂- ₇ are strobed. During time period t₂, the address Y+1 is applied to the memory chips 0-63 and the lines ₀- ₁ are strobed. During time period t₃, with i=6(110), the address X is applied to the memory chips 0-63, is enabled and lines ₆- ₇ are strobed. During time period t₄, the address X+1 is applied to the memory chips 0-63 and lines ₀- ₅ are strobed. From the foregoing, it can be seen that by applying the addresses X,Y, X+1 and Y+1 to the memory chips 0-63 in a time multiplexed manner in conjunction with the strobing of selected and lines, only those pixels in the array 84 will be selected. In an alternative embodiment, j is an arbitrary number between 0 and AWS y -1 and i is an arbitrary number between 0 and AWS x -1. Referring to Figs. 12 and 13, there are shown, as described above with respect to Figs. 10 and 11, tables of and lines which are strobed when a system comprises in the x and y direction two memory banks as shown in the apparatus of Fig. 3 and/or two memory banks as shown in the apparatus of Fig. 5, respectively. The foregoing description of the preferred embodiment of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. For example, the size of the pixel/word arrays in the x and y direction, i.e. AWS x and AWS y , may be varied dynamically so long as the number of pixels in the x and y direction in each array is a power of 2. Similarly, the number of banks of memory chips in the x and y direction, i.e. NB x and NB y also may be changed, again so long as the number of banks comprises a power of 2. Moreover, within the above constraints, any size memory chip may be used for storing the pixels of an array so long as the number of address lines provided is sufficient for addressing each pixel in the array. In addition, by controlling the CAS lines with a control signal different from i, an array having less than AWS x columns can be addressed. By controlling the RAS lines with a control signal different from j, an array having less than AWS y rows can be addressed. In this way, subarrays of an array of AWS x by AWS y size can be addressed with the proposed system.

Claims: An array-word-organized memory system including an addressing means for addressing a plurality of arbitrary arrays of pixels (84) in said memory system wherein each array comprises a plurality of columns of pixels each AWS y .NB y pixels long and a plurality of rows of pixels each AWS x .NB x pixels long, and y and x are, respectively, the overall row and column address of a pixel on the display screen within the memory system in the first row and first column of that array, comprising: NB x .NB y banks (4,23,24,53,54) of memory chips, each of said banks comprising AWS y rows and AWSx columns of memory chips (0 to 63), each of said memory chips having a plurality of rows and a plurality of columns of pixel cells; an address bus (10) routed through all of said memory chips; a plurality of CAS lines ( CAS 0-7) wherein each one of said CAS lines is routed through each chip of a respective one of said plurality of columns of memory chips; a plurality of RAS lines ( RAS 0-7) wherein each one of said RAS lines is routed through each chip of a respective one of said plurality of rows of memory chips; means (2) for applying a row address Y to said address bus during a time t₁ for addressing a first predetermined row of pixels cells in each of said memory chips, where Y = the integer value of and NB Y is the number of said banks of said memory chips in a y direction; means (3) for strobing said RAS lines in AWS y NB y -j rows of row numbers from j to AWS y .NB y of said memory chips during said time t1 where j is the remainder of means (2) for applying a row address Y+1, to said address bus during a time t₂ for addressing a second predetermined row of said pixels cells in each of said chips; means for strobing said RAS lines in the remainder of said rows of said memory chips during said time t₂; means (2) for applying a column address X to said address bus during a time t₃ for addressing a first predetermined column of said pixels cells in each of said memory chips, where X = the integer value of and NB x is the number of said banks in an x direction; means for strobing said CAS lines in AWS x .NB x -i columns of column numbers from i to AWS x .NB x of said memory chips during said time t₃, where i is the remainder of means (2) for applying a column address X+1 to said address bus during a time t₄ for addressing a second predetermined column of said pixels cells in each of said chips; and means for strobing said CAS lines in the remainder of said columns of said memory chips during said time t₄. A system according to Claim 1 wherein each of the terms AWS x , AWS y , NB x and NB y is a number equal to a power of 2. A system according to Claim 1 wherein said plurality of CAS lines is equal in number to the product of AWS x and NB x and said plurality of RAS lines is equal in number to the product of AWS y and NB y . A system according to Claim 1 wherein said AWS y -j rows of said plurality of memory chips comprises the lower AWS y -j rows of said plurality of rows of memory chips and said AWS x -i columns of said plurality of memory chips comprises the rightmost AWS x -i columns of said plurality of columns of memory chips. A system according to Claim 2 wherein AWS x =AWS y =8 and NB x =NB y =1 . A system according to Claim 2 wherein AWS x =AWS y =4 and NB x =NB y =1 . A system according to Claim 2 wherein AWSx=AWS y =8 , NB x =2 and NB y =1. A system according to Claim 2 wherein AWS x =AWS y =8 , NB x =1 and NB y =2. A system according to Claim 1 wherein said address bus comprises a predetermined number of address lines and said predetermined number of address lines corresponds to the number of pixels in each of said rows and each of said columns of pixels in each of said memory chips. A system according to claim 9 wherein said number of pixels in each of said rows and each of said columns of pixels in each of said memory chips equals 2 n , respectively, and said predetermined number of address lines in said address bus equals n. A system according to claim 1, wherein each of said plurality of memory chips provides one pixel for each of said plurality of arrays of words. A system according to claim 1, wherein the number of said memory chips in said plurality of memory chips is equal to the number of pixels in each of said arrays of pixels. A system according to claim 1, wherein said means for strobing said lines and said lines comprises: a / decoder having a first input for receiving a enable control signal , a second input for receiving a enable control signal , a third input for receiving a enable control signal , a fourth input for receiving a enable control signal , a plurality of time multiplexed and strobe signals, a first output coupled to said lines for providing to said lines in response to said control signal a first plurality of said strobe signals during said time t₁ and a second plurality of said strobe signals in response to said RASEN2 control signal during said time t₂ and a second output coupled to said CAS lines for providing to said CAS lines in response to said CASEN1 control signal a first plurality of CAS strobe signals during said time t₃ and a second plurality of CAS strobe signals during said time t₄ in response to said CASEN2 control signal. A method of addressing an array-word-organized memory system having an addressing means for addressing a plurality of arbitrary arrays of pixels in said memory system wherein each array comprises a plurality of columns of pixels each AWS y .NB y pixels long and a plurality of rows of pixels each AWS x .NB x pixels long, and y and x are, respectively, the overall row and column address of a pixel on the screen within the memory system in the first row and first column of that array, NB x .NB y banks of memory chips, each of said banks comprising AWS y rows and AWS x columns of memory chips (0 to 63), each of said memory chips having a plurality of rows and a plurality of columns of pixel cells, an address bus (10) routed through all of said memory chips, a plurality of CAS lines ( CAS 0-7) wherein one of said CAS lines is routed through each chip of a respective one of said plurality of columns of memory chips and a plurality of RAS lines ( RAS 0-7) wherein one of said RAS lines is routed through each chip of a respective one of said plurality of rows of memory chips, comprising the steps of: applying a row address Y to said address bus during a time t₁ for addressing a first predetermined row of pixel cells in each of said memory chips, where Y = the integer value of and NB y is the number of said banks of said memory chips in a y direction; strobing said RAS lines in AWS y .NB y -j rows of row numbers from j to AWS y .NB y of said memory chips during said time t₁ where j is the remainder of applying a row address Y+1 to said address bus during a time t₂ for addressing a second predetermined row of said pixels in each of said chips; strobing said RAS lines in the remainder of said rows of said memory chips during said time t₂; applying a column address X to said address bus during a time t₃ for addressing a first predetermined column of said pixels in each of said memory chips, where X = the integer value of and NB x is the number of said banks in an x direction; strobing said CAS lines in AWS x .NB y -j columns of column numbers from i to AWS x .NB x of said memory chips during said time t₃, where i is the remainder of applying a column address X+1, to said address bus during a time t₄ for addressing a second predetermined column of said pixels in each of said chips; and strobing said CAS lines in the remainder of said columns of said memory chips during said time t₄. A method according to Claim 14 wherein each of the terms AWS x , AWS y , NB x and NB y is a number equal to a power of 2. A method according to Claim 14 wherein said plurality of CAS lines is equal in number to the product of AWS x and NB x and said plurality of RAS lines is equal in number to the product of AWS y and NB y . A method according to Claim 14 wherein said NB y .AWS y -j rows of said plurality of memory chips comprises the lower NB y .AWS y -j rows of said plurality of rows of memory chips and said NB x .AWS x -i columns of said plurality of memory chips comprises the rightmost NB x .AWS x -i columns of said plurality of columns of memory chips. A method according to Claim 15 wherein AWS x =AWS y =8 and NB x =NB y =1 . A method according to Claim 15 wherein AWS x =AWS y =4 and NB x =NB y =1 . A method according to Claim 15 wherein AWS x =AWS y =8 , NB x =2 and NB y =1. A method according to Claim 15 wherein AWS x =AWS y =8 , NB x =1 and NB y =2. A method according to Claim 14 wherein said address bus comprises a predetermined number of address lines and said predetermined number of address lines corresponds to the number of pixels in each of said rows and each of said columns of pixels in each of said memory chips. A method according to Claim 22 wherein said number of pixels in each of said rows and each of said columns of pixels in each of said memory chips equals 2 n , respectively, and said predetermined number of address lines in said address bus equals n. A method according to Claim 14 wherein each of said plurality of memory chips provides one pixel for each of said plurality of arrays of words. A method according to Claim 14 wherein the number of said memory chips in said plurality of memory chips is equal to the number of pixels in each of said arrays of pixels. A method according to Claim 14 wherein said steps of strobing said RAS lines and said CAS lines comprises the steps of: provding a RAS / CAS decoder having a first input for receiving a RAS enable control signal RASEN1 , a second input for receiving a RAS enable control signal RASEN2 , a third input for receiving a CAS enable control signal CASEN1 , a fourth input for receiving a CAS enable control signal CASEN2 , a plurality of time multiplexed RAS and CAS strobe signals, a first output coupled to said RAS lines for providing to said RAS lines in response to said RASEN1 control signal a first plurality of said RAS strobe signals during said time t₁ and a second plurality of said RAS strobe signals in response to said RASEN2 control signal during said time t₂ and a second output coupled to said CAS lines for providing to said CAS lines in response to said CASEN1 control signal a first plurality of CAS strobe signals during said time t³ and a second plurality of CAS strobe signals during said time t₄ in response to said CASEN2 control signal.

Inventors: GOETTSCH RANDY, SFARTI ADRIAN, GOETTSCH, RANDY, SFARTI, ADRIAN
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1987
Main classification: G11C8
IPC codes: G06T1, G09G5, G11C8, G06F12, G11C7, G06F3, G09G1, G11C11