ASSOCIATIVE MEMORY DEVICE

Abstract: An associative memory device in which a detection or determination is made if same information as that to be written in the associative memory cells has been stored therein before storing the information to be written in the memory cells and if the result of the detection is that the same information has been stored therein, the information to be written is inhibited from storing while when the same information has not been stored therein, the information to be written is permitted to be stored in a predetermined memory cell, so as not to store the same information into a plurality of different addresses of the memory cells.

Description: The present invention relates to an associative memory device comprising associative memory cells for storing information; retrieval starting means for applying retrieval information to said memory cells and for starting a retrieval operation; detecting means for detecting whether or not information the same as the retrieval information has been stored in said memory cells; and writing means for storing information to be written into a selected memory cell among the associative memory cells. Such a memory device is known from US-A-4 296 475. In recent computers, there is a tendency that high speed operation of the computers is required in order to improve the processing capability, and this in turn necessitates a high speed operation of memories, as well. To this end, high speed cashe memories are being widely used as an auxiliary memory of a main memory although they have a smaller memory capacity compared with the main memory having a large capacity but a low speed operation. Since only information which is frequently used is stored in this cashe memory, when a processor has an access to the main memory, the information thus accessed is to be stored in the cashe memory at random. It is therefore necessary to determine in which address among addresses of the cashe memory the information demanded by the processor is being stored and to access thereto. In processing these cashe memories, there is used, for instance, an associative memory wherein an address in which particular information has been stored, can be known from the contents of the memory. It is constructed in such a manner that addresses of the cashe memory are related to those of the addresses of the addresses of the associative memory having same memory capacity as that of the cashe memory where the information has been stored, and the addresses of the information on the cashe memory are stored into the addresses of the associative memory which correspond to those of the cashe memory. With this construction, the associative memory is accessed by each of the addresses of the main memory where the information has been stored, i.e., by the information to be stored in the associative memory in order to obtain necessary information for the processor. In this case, when it is found that the information has been stored in the associative memory, a particular address in the associative memory can be determined by the associative memory function. As a result, when access to the cashe memory is carried out by the address thus determined, the information necessary for the processor can be obtained from the cashe memory at high speed. However, there are often such cases that same information might be stored in different addresses in the associative memory. Consequently, when retrieval operation of the information stored in the different addresses is carried out in this case, a plurality of addresses corresponding to the same information are to be produced. Therefore, when such a case as described above occurs in the associative memory used in the processing of the cashe memory, it becomes no longer possible to access the cashe memory. In order to prevent the drawbacks or disadvantages described above, when a plurality of same information are produced by detecting the output information in the reading-out of the information from, for instance, the associative memory, it becomes necessary to stop the subsequent operation or to take some measures for producing the selected information in accordance with a predetermined priority order preliminarily set up. As a result, it also becomes necessary to provide a specific means for that operation as well as resulting in a problem that a high speed performance of the cashe memory is lowered by the operation time necessary to provide a specific means for that operation as well as resulting in a problem that a high speed performance of the cashe memory is lowered by the operation time necessary for operating the specific means. It is therefore an object of the present invention to overcome the above drawbacks and to provide an associative memory device capable of preventing same information from being stored at different addresses of the associative memory device. It is another object of the present invention to provide an associative memory device in which a detection or determination is made if same information as that to be written has been stored therein before storing the information to be written in the memory cells and if the result of the detection is that the same information has been stored therein, the information to be written is inhibited from being stored while when the same information has not been stored therein, the information to be written is allowed to be stored in a predetermined memory cell, so as not to store the same information into a plurality of different addresses of the memory cells. According to one aspect of the invention, the memory device initially defined is characterized in that the memory device is arranged to apply said information to be written to said retrieval starting means for starting a retrieval operation; said detecting means is arranged to detect whether or not the information to be written exists in the memory cells and dependent on the result to produce a same information non-existence signal; write control circuit means which is responsive to said non-existence signal is provided for producing a write acknowledge signal; and said writing means is arranged to store said information to be written in accordance with said write acknowledge signal produced by said write control circuit means. According to another aspect of the invention, there is provided a method of operating an associative memory device comprising: storing information in associative memory cells; applying retrieval information to said memory cells and starting a retrieval operation using retrieval starting means; detecting whether or not information the same as the retrieval information has been stored in said memory cells; and storing information to be written into a selected memory cell among the associative memory cells; characterized by: applying said information to be written to said retrieval starting means for starting a retrieval operation; detecting whether or not the information to be written exists in the memory cells and dependent on the result producing a same information non-existence signal; producing a write acknowledge signal responsive to said non-existence signal; and storing said information to be written in accordance with said write acknowledge signal. These and other objects, features, and advantages of the invention will be better understood from the following description with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of an associative memory device according to the present invention; Fig. 2 is one embodiment of the associative memory cell to be used in the device of Fig. 1, according to the present invention; Fig. 3 is one embodiment of a word line control circuit to be used in the associative memory device and the associative memory cells shown in Figs. 1 and 2; Fig. 4 is another embodiment of the associative memory cell according to the present invention; and Fig. 5 is another embodiment of the word line control circuit to be used in the memory device of Figs. 1 and 4. Referring to Fig. 1 associative memory device for controlling the output of a cashe memory (not shown) comprises a memory 1 having associative memory cells, a retrieval starting circuit 3, a detecting circuit 5 for detecting the existence of duplicate information at different addresses of memory 1, a write control circuit 7, and a write circuit 9. In the write mode, information is stored from the write circuit 9 in an address of the memory 1, designated by the address to be written. In the retrieval mode, when retrieval information is applied from the retrieval starting circuit 3, the information which coincides with the retrieval information is retrieved and an address or addresses into which the information in question has been stored is determined. When retrieval information is applied thereto, the retrieval starting circuit supplies the retrieval information to the memory 1 after the memory 1 is put in a retrieval mode state. On the other hand, when write information is applied to the retrieval starting circuit 3, it supplies the write information to be stored in the memory 1 to a certain cell and the retrieval operation of the write information is performed for the memory 1 after putting the memory 1 in the retrieval mode state. In this operation, if same information as the information to be retrieved has not been stored in any memory location of the memory 1, the detecting circuit 5 for detecting the existence or non-existence of duplicate information produces a same information non-existence signal which indicates that there is no duplicate information stored therein and it supplies the signal to the write circuit 7 and a memory controller, not shown. On the other hand, however, when a plurality of duplicate data have been stored in a plurality of memory locations of the memory 1 the addresses into which the duplicate data have been stored are applied to the cashe memory (not shown here). The write control circuit 7 receives the same information non-existence signal and produces and applies a write acknowledge signal for instructing the write operation of the information by the write circuit 9 to the same. When receiving the write acknowledge signal, the write circuit 9 stores the information to be written into a predetermined address of the memory 1. The operation of the associative memory device is as follows; When the information to be written is applied to the retrieval starting circuit 3 and the write circuit 9 in the write mode of the associative memory device, retrieval operation of the information is carried out in the memory 1 by the retrieval starting circuit 3. As the result of the retrieval operation, when same information as the information to be written has not been stored in the memory 1, the same information non-existence signal is produced from the detecting circuit 5 and is then applied to the write control circuit 7 and a memory controller, not shown. After receiving the non-existence signal, the write control circuit 7 applies the write acknowledge signal to the write circuit 9, so as to store the information to be written in a predetermined address of the memory through the write circuit 9, as well as to store the same in the cashe memory by the memory controller which received the same information non-existence signal. On the other hand, when the same information as that of the information to be written has been stored in the memory 1, the non-existence signal is no longer applied to the write control circuit 7 and also the write acknowledge signal is no longer applied to the write circuit 9. Accordingly, the write circuit 9 does not perform the write operation, so that the information to be written can not be stored in the memory 1. In such a write mode as described above, the information to be written is searched prior to storing the information into the memory 1 so that duplicate information is never stored in different addresses of the memory 1. Fig. 2 shows the construction of a first embodiment of an associative memory cell of the asociative memory device according to the present invention. The memory cell is comprised of an information hold circuit 11, transfer gates 13 and 15, a retrieval circuit 17, a word line WL, bit lines BL and BL , and an output address line AL. The information hold circuit 11 comprises inverter circuits 19 and 21, with each of the input and output terminals connected to each other. The input terminal of the inverter circuit 19 is connected to the bit line BL through the transfer gate 13 while the output terminal thereof is connected to the bit line BL through the transfer gate 15. The information hold circuit 11 is provided so as to store the information applied from the bit line BL as well as its inverted information applied from the bit line BL in the write operation. Furthermore, the information hold circuit 11 functions So as to send the information stored in the hold circuit 11 to the bit lines BL and BL through the transfer gates 13 and 15 in the read operation. P-channel MOS transistors (referred to hereinafter as P-MCS transistors) are used as the transfer gates 13 and 15 with their gate electrodes connected to the word line WL. Thus, they can be rendered either conductive or non-conductive by a signal applied from the word line WL and can transfer information between the information hold circuit 11 and bit line BL and between the hold circuit 11 and the bit line BL . The retrieval circuit 17 is constructed by N-channel MOS transistors, each of which is referred to hereinafter as an N-MOS transistor. The N-MOS transistor 23 is interconnected in such a manner that its gate electrode G is connected to the source electrode S of the transfer gate 15, its drain electrode D is connected to the output address line AL and its source electrode S is connected the drain electrode D of the N-MOS transistor 25. The N-MOS transistor 25 has its gate electrode G connected to the bit line BL and its source electrode S connected to the ground. The N-MOS transistor 27 is interconnected such that its gate electrode G is connected to the source electrode S of the transfer gate 13, its drain electrode D is connected to the output address line AL and its source electrode S is connected to the drain electrode D of the N-MOS transistor 29. The N-MOS transistor 29 has its gate electrode G connected to the bit line BL and its source electrode connected to ground. The actual memory array of the associative memory device is constructed, with each of the memory cells thus constructed arranged in a matrix form and each of the output address lines AL connected in a respective wired OR configuration. Description will now be given of the retrieval operation of the information to be written in the memory cell thus constructed. Before starting the retrieval operation, the bit lines BL and BL are precharged to ground level i.e., at O V, normally. After this operation, the output address line AL is precharged to the power supply potential V DD . Moreover, when, for instance, low level information has been stored in the information hold circuit 11, the gate electrode of the N-MOS transistor 23 is placed in the high level condition, and the gate electrode of the N-MOS transistor 27 is put in the low level condition while the N-MOS transistor 23 is in the conductive condition and the N-MOS transistor 27 is in the non-conductive condition. With the predischarged condition of the bit lines BL and BL and the precharged condition of the output address line AL, when the information to be written is applied to the bit line BL and its inverted information is applied to the bit line BL , the retrieval operation is performed. For instance, when the information having the high level is applied to the bit line BL while the inverted information having the low level is applied to the bit line BL is applied, the gate electrode of the N-MOS transistor 25 attains a high level condition while the N-MOS transistor 29 is rendered non-conductive. As a result, current flows in the N-MOS transistors 25 and 23 from the output address line AL, so that the potential of the output address line AL becomes ground potential. On the other hand, when low level information is applied to the bit line BL while its inverted information having the high level is applied to the bit line BL , the gate electrode of the N-MOS transistor 25 reaches the low level condition, while the gate electrode of the N-MOS transistor 29 is rendered non-conductive, with the result that the N-MOS transistor 25 is rendered non-conductive and the N-MOS transistor 29 is rendered conductive, thereby maintaining the potential of the output address line AL at the V DD potential. Namely, when the information to be written coincides with the stored information in the information hold circuit 11, the potential of the output address line AL is maintained at the potential V DD while when the two do not coincide with each other, the output address line AL becomes the ground potential. Consequently, when the same information as that to be written has been stored in the memory cells, all of the output address lines AL reach ground potential, so that by detecting this condition by a circuit provided outside of the memory cells, a same information non-existence signal, which indicates that the same information as that to be written has not been stored in the memory cells, is produced from the circuit. Fig. 3 shows a word line control circuit for receiving the non-existence signal and for storing the information to be written in a certain memory location of a predetermined memory cell shown in Fig. 2. The word control circuit comprises an inverter 31, a NOR circuit 33 and a NAND circuit 37. In this circuit, when the information in question has not been stored in the memory cells after terminating the retrieval operation of the information in the write mode, the same information non-existence signal of the high level is applied to one input terminal of the NOR circuit 33 through an inverter circuit 31 while a low level write signal is applied to the other input terminal of the NOR circuit 33 from the write control circuit 7. Then the NOR circuit 33 produces a low level write signal in the write mode operation, thereby producing and supplying a high level output signal to a NAND circuit 37 therefrom. As a result, the NAND circuit 37 receives the high level signal and a write address signal and produces a low level signal therefrom. Accordingly, the word line WL connected to the output terminal of the NAND circuit 37 attains a low level condition and a particular memory cell which is connected to the word line WL is selected. In the above condition of the word line WL, the transfer gates 13 and 15, with their gate electrodes connected to the word line, are now rendered conductive. In this condition, when the information to be written and its inverse are applied to the bit lines BL and BL respectively, which have preliminarily been predischarged to the ground potential, they are applied to the information hold circuit 11 through the transfer gates 13 and 15 and stored therein, thus realizing the write operation. On the other hand, however, when it turns out that, after terminating the search operation of the information to be written, the same information as that to be written was not stored in the memory cells, the same information non-existence signal is not produced from the detecting circuit 5, since at least one output address line AL attains the power supply potential V DD . As a result, no write operation is carried out in this case, as there is no word line selected. Fig. 4 shows another embodiment of the associative memory cell according to the present invention. In this embodiment, the transfer gate circuits are constructed by the N-MOS transistors 13' and 15' while the transistors in the retrieval circuit 39 are constructed by P-MOS transistors 23', 25', 27' and 29'. This associative memory cell operates in the similar manner as that shown in Fig. 2. Namely, when the information to be written coincides with the stored information in the memory cell, the output address line AL is maintained at the ground potential while when the information does not coincide the potential of the output address line AL is increased from the ground potential to the power supply potential V DD , thereby performing the retrieval operation. Fig. 5 shows another word line control circuit for selecting a predetermined word line WL of the memory cells, which is adapted to the memory cell of Fig. 4. In operation, when a write acknowledge signal from the write control circuit 7 (in Fig. 1) as well as the same information non-existence signal is received by the word line control circuit of Fig. 5 in the write mode, a predetermined word line WL is selected, so as to render conductive the transfer gate circuits 13' and 15' having gate electrodes connected to the word line, by supplying a high level signal to the word line WL via inverter 34 and the NAND-circuit 37'. In the embodiments according to the present invention shown in Figs. 1 through 3, it may occur that the write operation is delayed because the search operation of the information to be written is performed prior to the write operation. However, since the write operation for the associative memory device is carried out only when transferring the information from the memory cells to the cashe memory, the frequency of producing the delay is normally small, so that only the access time of the low speed main memory becomes a predominating factor and there will be no problems affecting the associative memory device. As described in the foregoing embodiments, in the associative memory device according to the present invention, a determination is made whether or not same information as the information to be written into an memory cell has been stored in the memory cells of the associative memory before storing the information in the cell in the write operation. When the same information has been stored therein, the information to be written is inhibited from being stored while when the same information has not been stored therein, the information to be written is allowed to be stored in a predetermined memory cell, so as not to store the same information into a plurality of different addresses of the memory cells. As a result, in the write operation, no particular means for dealing with the case where a plurality of same information are produced is required, as well as obviating any additional time necessary for that operation. Accordingly, in the associative memory device according to the present invention, same information can be prevented from being produced from a plurality of different addresses of the associative memory, without delaying the access time to the memory.

Claims: An associative memory device comprising: associative memory cells (1) for storing information; retrieval starting means (3) for applying retrieval information to said memory cells and for starting a retrieval operation; detecting means (5) for detecting whether or not information the same as the retrieval information has been stored in said memory cells; and writing means (9) for storing information to be written into a selected memory cell among the associative memory cells; characterized in that: the memory device is arranged to apply said information to be written to said retrieval starting means (3) for starting a retrieval operation; said detecting means (5) is arranged to detect whether or not the information to be written exists in the memory cells (1) and dependent on the result to produce a same information non-existence signal; write control circuit means (7) which is responsive to said non-existence signal is provided for producing a write acknowledge signal; and said writing means (9) is arranged to store said information to be written in accordance with said write acknowledge signal produced by said write control circuit means (7). An associative memory device as claimed in claim 1, further comprising a word line control circuit having a NOR circuit (33), one input terminal of which is connected to said write control means and other input terminal of which is connected to receive the same information non-existence signal through an inverter (31), and a NAND circuit (37) having a plurality of input terminals, one of which is connected to the output terminal of said NOR circuit so as to control a word line. An associative memory device as claimed in claim 1 or 2 further comprising a word line control circuit having a NOR circuit (33'), one input terminal of which is connected to receive the same information non-existence signal through an inverter (31') and the other input terminal of which is connected to said write control means, and a NAND circuit (37') having a plurality of input terminals, one of which input terminals being connected to the output terminal of said NOR circuit through a second inverter (34). An associative memory device according to any preceding claim wherein said detecting means (5) is further arranged to determine the address in which information the same as said retrieval information has been stored. A method of operating an associative memory device comprising: storing information in associative memory cells (1); applying retrieval information to said memory cells and starting a retrieval operation using retrieval starting means (3); detecting whether or not information the same as the retrieval information has been stored in said memory cells; and storing information to be written into a selected memory cell among the associative memory cells (1); characterized by: applying said information to be written to said retrieval starting means (3) for starting a retrieval operation; detecting whether or not the information to be written exists in the memory cells (1) and dependent on the result producing a same information non-existence signal; producing a write acknowledge signal responsive to said non-existence signal; and storing said information to be written in accordance with said write acknowledge signal.

Inventors: HORI, CHIKAHIRO TOSHIBA-SHINKOYASUDAIICHI-RYO
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: G11C15
IPC codes: G11C15