SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device comprises an array of memory cells (MCll-MC24) in a folded bit line configuration. The memory cells are arranged as pairs and the cells of each pair share a contact hold (l0) and are surrounded by an isolation trench (l2). Data charge storage capacitance for the cells is formed on the entire sidewall of the isolation trench (l2) except parts of the isolation trench where an isolation oxide film (2′) is provided to separate the two memory cells of each pair from one another. One word line (7a-7d) and two bit lines (6a-6d) pass through a region (UR) corresponding to one bit memory cell.

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor memory device and particularly to a device with memory cells configured for a high level of integration. BACKGROUND TO THE INVENTION A semiconductor memory device of the type with which the present invention is concerned was proposed in lecture number FAM l7.4 of the IEEE International Solid-State Conference (ISSCC) l985 and is described in more detail hereinafter. Although this type of device decreases the planar areas needed for the creation of the data charge storage capacitance of the memory cells the configuration still imposes a limitation on the degree of integration. A general object of the present invention is to provide an improved semiconductor memory device and memory cell configuration. SUMMARY OF THE INVENTION According to one aspect of the invention, there is provided a semiconductor memory device composed of an array of memory cells and accessible via bit lines and word lines, the bit lines being of folded configuration; said device comprising: memory cells arranged in pairs, the cells of each pair sharing a contact hole and being surrounded by an isolation trench, the memory cells including data charge storage capacitance means at least part of which is formed on the entire sidewall of one of the isolation trenches except for a region where an isolation oxide film is present to separate memory cells, wherein each word line passes through a region of one bit memory cell and two bit lines pass through a region for one bit memory cell. According to another aspect of the invention there is provided a semiconductor memory device composed of an array of memory cells in a folded bit line configuration; said device comprising: memory cells arranged generally in rows and columns to form a matrix, each memory cell comprising a data charge storage capacitor and a transfer gate provided by a channel of a transistor, word lines extending parallel to one another in a first direction to pass over the channels of the transistors, bit lines extending parallel to one another and in a second direction substantially orthogonal to the first direction with every two adjacent bit lines forming a folded bit line pair; wherein adjacent memory cells are arranged in pairs with the cells of each pair sharing a common contact for connection with a respective bit lines, the memory cells being arranged in lines parallel to the word lines, with the transistors of first ones of the memory cells of the respective memory cell pairs in a memory cell pair line having channels positioned under one of the word lines so as to be controlled thereby and the transistors of second memory cells of the respective memory cell pairs in the same memory cell pair line having channels positioned under another word line adjacent to said one word line, to be controlled thereby and wherein the adjacent memory cell pair lines and the memory cell pairs adjacent to each other in the same memory cell pair line are separated by isolation trenches, so that each pair of memory cells is surrounded by an isolation trench, the data charge storage capacitors of the memory cells being at least partly formed by capacitors on the sidewalls of the isolation trenches surrounding the pairs of memory cells. Preferably, the memory cells are elongated in the direction of the word lines while the overall surface area is unchanged. As a result, a margin or a space is created which can be used for forming an isolation oxide film between the transfer gates of the memory cells and the periphery of the memory cells. A device constructed in accordance with the invention can be at a high level of integration yet is free of the need to provide an isolation trench particularly close to the channel regions of the transfer gates. Consequentially the leakage currents are minimized and the transistors can be reliably turned OFF. Even where isolation trenches are formed throughout the entirety of the periphery of each memory cell and the data charge storage capacitors are formed practically throughout the entire trench sidewalls, the leakage currents can still be maintained at the level found in normal LOCOS (local oxidization of silicon). BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood more readily, and various other features of the invention may become apparent from consideration of the following description, in conjunction with the accompanying drawings, wherein:- Fig. lA is a plan view of part of a conventional semiconductor memory device; Fig. lB is a cross-section along the line lb-lb of Fig. lA; Fig. 2 is a sectional plan view taken along the line II-II of Fig. lA on a somewhat larger scale; Fig. 3 is a plan view showing a part of a semiconductor memory device constructed in accordance with the invention; Fig. 4 is a circuit diagram depciting how the memory cells of the device of Fig. 3 are connected; Fig. 5 is a sectional view taken along the line V-V of Fig. 3; and Fig. 6 is a perspective representation of part of the device of the invention composed of two memory cells with a common contact hole. An example of a highly intergrated dynamic semiconductor memory device of the type proposed in the lecture number FAM l7.4 of ISSCC l985 is shown in Figs. lA, lB and 2. As illustrated, the device comprises a p-­ type semiconductor substrate l, a field oxide film 2 at the base of an isolation trench in the substrate, a first poly-silicon layer 3 overlying the film 2, a capacitor insulating film 4, and an n⁺ diffusion layer 5 on the flat portion of the substrate l. A first Al interconnection layer 6 forms bit lines. A second poly-silicon layer 7 and a second Al layer 8 forms word lines 9. Although not illustrated as such, the second poly-silicon layer 7 is electrically connected at regular intervals with the second Al interconnection layer 8 to reduce the effective resistance of the word lines 9. Contact holes l0 serve for electrical connection of the first Al interconnection layer 6 to the n⁺ diffusion layer 5. Cp represents a data charge storage capacitor formed from the poly-silicon layer 3 and the n⁺ diffusion layer 5 on the respective sides of the trench and isolated from one another by the capacitor insulating film 4 serving as a dielectric. Cf represents a data charge storage capacitor formed of the poly-silicon layer 3, the insulating film 4 and the n⁺ diffusion layer 5 on the flat part of the substrate l. By utilizing the sidewalls of the isolation trenches to form the data charge storage capacitance Cp, the area neded for the data charge storage capacitance Cf on the flat part of the substrate l is reduced. As a result, any reduction in the overall chip area does not necessarily lead to a reduction in the operational characteristics and the data charge storage capacitance can be secured against minority carriers injected because of external influences e.g. radiation such as alpha particles. As the periphery of the memory cells is lengthened, the trench may be made shallower in order to maintain the same collective data charge storage capacitance Cp+Cf. A conventional highly-­ integrated dynamic semiconductor memory of a folded-bit line configuration (further described in Japanese Published Patent Application No 74535/l976) can use the above-described memory cells in which case the device will take the form depicted in Fig. 2. As illustrated, the layer 3 must be etched so that its edges lie at the bottom of the trenches 2. However, where the trenches are to have a minimal width, etching the layer 3 to create terminal edges at the bottom of the trenches is difficult. Moreover, there are normally isolation trenches on both sides of the channel region of the transistor transfer gate controlled by the layer 7 forming the word line. Leakage currents tend to flow through the sidewalls of the isolation trenches making it difficult to ensure the relevant transistors are turned off. DESCRIPTION OF PREFERRED EMBODIMENT Figs. 3 to 6 depict part of a memory device constructed in accordance with the invention. As illustrated, the device comprises memory cells MCll-MC24 arranged in columns and rows to form a matrix. As with the known device, the cells are provided on a p-type substrate l. Throughout Figs. 3 to 6: 2 denotes field oxide film used to isolate the elements, and 2′ a similar oxide film on the sidewalls of the isolation trenches designated l2. 3 denotes a first poly-silicon layer which provides electrodes for data charge storage capacitors l5 which have a dielectric insulation film 4. An n⁺ diffusion layer 5 provides the other electrodes for the capacitors l5. A first Al interconnection layer 6 forms bit lines while a second poly-silicon layer 7 forms word lines. Contact holes l0 provide connection between the layers 6 and 5. Cp denotes the capacitor formed on the sidewalls of the trenches l2 by the layers 3, 4, 5 which form part of the data charge storage capacitors l5. Cf denotes the capacitor on the flat part of the substrate l formed by the layers 3, 4, 5 and also forming part of the data charge storage capacitors l5. Each of the memory cells comprises a transistor transfer gate and a data charge storage capacitor l5 and the channels of the transitors (FETs or MOSFETs) which provide the gates are designated ll. The source and drain of the MOSFETs are provided by regions of the n⁺ diffusion layer 5 while the gate electrodes are provided by one of the word lines 7a-7d. Beneath the isolation films 2, 2′ on the flat part of the substrate l and the bottom sidewalls of the trenches l2 are p-type impurity-diffused layers l4, similar to that provided for ordinary LOCOS isolation. The word lines 7a-7d extend parallel to one another in a first direction to pass over the channels ll of the transistors. The bit lines 6a-6d also extend parallel to one another but in a second direction orthogonal to the first direction. Each of the alternate bit lines 6a and 6c and the adjacent one of the interleaving bit lines 6b and 6d, e.g., one immediately below said each of the alternate bit lines form a folded bit line pair. Every two memory cells Mll and Ml2; Ml3 and Ml4; M2l and M22; and M23 and M24 adjacent to each other form a memory cell pair sharing a contact hole l0 for connection with a respective bit line 6a-6d. The memory cell pairs are arranged in memory cell pair lines Ll, L2 parallel to the word lines 7a-7d. The transistors of the first ones Mll, Ml3, M2l, M23 of the memory cells of the respective memory cell pairs in a memory cell pair line Ll or L2 have their channels ll positioned under one of the word lines 7a, 7c so as to be controlled thereby. The transistors of second memory cells Ml2, Ml4, M22, M24 of the respective memory cell pairs in the same memory cell pair lines Ll, L2 have their channels ll positioned under another word line 7b, 7d adjacent to the word lines 7a, 7c, so as to be controlled thereby. The memory cells Mll, Ml2, M2l, M22 of the memory cell pairs in alternate memory cell pair lines (Ll et al) are connected to alternate bit lines 6a, 6c, and the memory cells Ml3, Ml4, M23, M24 of the memory cell pairs in adjacent memory cell pair lines (L2 et al) are connected to the intervening bit lines 6b, 6d. The memory cell pair lines Ll, L2 adjacent to each other are separated by parts l2W of the isolation trenches l2 extending in the direction of the word lines. The memory cell pairs adjacent to each other in the same memory cell pair line Ll, L2 are separated from each other by parts l2B of the isolation trenches l2, extending in the direction of the bit lines. As a result, each of the memory cell pairs are surrounded by isolation trench parts l2W, l2B. The date charge storage capacitor l5 of each memory cell is partly formed by capacitors (Cp Fig. 5) on the sidewalls of the isolation trench parts l2W, l2B surrounding the memory cell pairs. The data charge storage capacitor Cp of one of the memory cells of each memory cell pair is separated from the data charge storage capacitor Cp of the other memory cell of the memory cell pair by the isolation oxide film 2′ (Fig. 6) formed on the sidewalls of the isolation trench parts 12B. The channel ll of the transistor of each memory cell is separated from the data charge storage capacitor l5 by the isolation oxide film 2 formed on a flat part of the substrate l between the channel ll and the isolation trench part l2B. Each data charge storage capacitor Cp comprises a first electrode formed by the n⁺ diffusion layer 5 on the sidewall of the isolation trench l2, an insulating film 4 as a dielectric formed on the n⁺ diffusion layer 5 and a second electrode formed by the poly-silicon layer 3 on the insulating film 4. The bit lines 6a, 6c connected to the memory cells MCll, MCl2, MC2l, MC22 in a memory cell pair line Ll pass over the isolation trench parts l2B separating adjacent memory cell pairs from each other in an adjacent memory cell line L2. Thus, the memory cell pairs in a memory cell pair line Ll are offset by half a pitch, i.e. the interval between successive memory cell pairs in the same line, in the direction of the word lines with respect to the memory cell pairs in another memory cell pair line L2 adjacent to the memory cell pair line Ll. As shown in Fig. 3, a region for one bit memory cell comprises one channel ll which extend in a vertical direction from the lower half of an Al interconnection 6b to the upper half of an Al interconnection 6d, and, in the horizontal direction from the centre of a contact hole l0 to the centre of an isolation trench l2, as indicated by chain line UR. Two bit lines (one half of 6b, one half of 6d and an entirety of 6c) pass through the one bit memory cell region UR, and one word line (the entire width of 7b) passes through the one bit memory cell region UR. Every two bit lines (e.g., 6c and 6d) adjacent to each other are connected externally (not shown) to form a folded bit line pair as known per se. When a word line, e.g., 7a is at a high potential, the transistors with their channels ll under the word line 7a are conductive and hence those transistors connect the respective data charge storage capacitors l5 to the respective bit lines such as 6c, while the adjacent bit lines such as 6d are disconnected from the corresponding data charge storage capacitors l5 because the corresponding transistors with their channels under the word lines such as 7c are non-conductive. In other words, when a memory cell connected to a bit line, e.g., 6c is selected, none of the memory cells connected to the other bit line of the folded bit line pair, e.g., 6d is selected. With the structure described above, isolation trenches l2 are formed along the entire periphery of the memory cells and data charge storage capacitors Cp are formed on the sidewalls of the isolation trenches. Because a flat isolation oxide film 2 is provided on both sides of each transfer gate ll, it is not necessary to pattern the first poly-silicon layer 3 to have its edge within the region of the isolation trenches as shown in Fig. 2. Therefore, the fabrication process is simplified. Furthermore, the isolation trenches l2 and the transistor channel regions ll are not close to each other, so that control of the leakage current from the word line 7 is minimized. As a result, the data charge retention characteristic is improved. As shown in Fig. 6, by providing the data charge storage capacitors Cp with electrodes formed through the entire sidewalls of the isolation trenches l2, except for a portion of the sidewalls used for separating the two memory cells sharing the contact hole l0 from one another where the isolation oxide film 2′ is present, means that a relatively large capacitance can be obtained even if the trenches l2 are shallow. As an example, Fig. 3 shows memory cells designed on a 0.8 micron basis. Where the cell area = 2.6 microns × 4.2. microns = l0.92 square microns, the capacitance of 50 fF (l fF = l0 ⁻¹⁵ F) can be obtained, if the thickness of the capacitance insulating film is l00Å and the depth of the isolation trenches is l.94 microns. Thus, the isolation trenches can be shallower than those of the memory cells of a known 4M bit DRAM. In the embodiment described, memory cells having a transfer gate with an n-type channel ll formed on a p-type substrate l are described. However, it may be so arranged that the memory cells have a transfer gate with a p-type channel formed on an n-type substrate.

Claims: 1. A semiconductor memory device composed of an array of memory cells and accessible via bit lines and word lines, the bit lines being of folded configuration; said device comprising: memory cells (MCll-MC24) arranged in pairs, the cells of each pair sharing a contact hole (l0) and being surrounded by an isolation trench (l2), the memory cells including data charge storage capacitance means (l5) at least part of which is formed on the entire sidewall of one of the isolation trenches except for a region where an isolation oxide film (2′) is present to separate memory cells, wherein each word line (7a-7d) passes through a region (UR) of one bit memory cell and two bit lines (6a-­ 6d) pass through a region for one bit memory cell. 2. A semiconductor memory device composed of an array of memory cells in a folded bit line configuration; said device comprising: memory cells (MCll-MC24) arranged generally in rows and columns to form a matrix, each memory cell comprising a data charge storage capacitor and a transfer gate provided by a channel (ll) of a transistor, word lines (7a-7d) extending parallel to one another in a first direction to pass over the channels (ll) of the transistors, bit lines (6a-6d) extending parallel to one another and in a second direction substantially orthogonal to the first direction with every two adjacent bit lines forming a folded bit line pair; wherein adjacent memory cells are arranged in pairs with the cells of each pair sharing a common contact (l0) for connection with a respective bit lines, the memory cells being arranged in lines parallel to the word lines, with the transistors of first ones of the memory cells of the respective memory cell pairs in a memory cell pair line having channels (ll) positioned under one of the word line (7a-7d) so as to be controlled thereby and the transistors of second memory cells of the respective memory cell pairs in the same memory cell pair line having channels (ll) positioned under another word line adjacent to said one word line, to be controlled thereby and wherein the adjacent memory cell pair lines and the memory cell pairs adjacent to each other in the same memory cell pair line are separated by isolation trenches (l2), so that each pair of memory cells is surrounded by an isolation trench, the data charge storage capacitors (l5) of the memory cells being at least partly formed by capacitors (Cp) on the sidewalls of the isolation trenches (l2) surrounding the pairs of memory cells. 3. A device according to claim 2, wherein the data charge storage capacitor (Cp) of one of the memory cells of each memory cell pair which is formed on a sidewall of the associated trench is separated from the data charge storage capacitor (Cp) of the other memory cell of the memory cell pair by an isolation oxide film (2′) formed on the sidewall of the associated trench. 4. A device according to claim 2 or 3, wherein the channel of the transistor of each memory cell is separated from the data charge storage capacitor thereof by an isolation oxide film formed on a flat part of a substrate between the channel and the isolation trench. 5. A device according to claim 3 or 4, wherein the isolation film (2′, 2) is supplemented by an impurity diffusion layer (l4). 6. A device according to any one of claims 2 to 5, wherein each data charge storage capacitor (Cp) formed on a sidewall of one of the trenches comprises a first electrode formed by a heavily diffused region (5) on the sidewall, an insulating film (4) as a dielectric on the first electrode, and a second electrode formed by a poly­ silicon layer (3) on the insulating film (4). 7. A device according to any one of claims 2 to 6, wherein the memory cells of the memory cell pairs in one of the memory cell pair lines (Ll, L2) are connected to alternate bit lines (6a, 6c) and the memory cell pairs in adjacent memory cell pair lines are connected to the other interleaving bit lines (6b, 6d). 8. A device according to any one of claims 2 to 7, wherein each bit line connected to the memory cells in a memory cell pair line passes over isolation trenches separating adjacent memory cells pairs from each other in adjacent memory cell lines. 9. A device according to any one of claims 2 to 8, wherein the memory cell pairs in one of the memory cell pair lines (Ll) are offset by half a pitch in the direction of the word lines with respect to the memory cell pairs in another memory cell pair line (L2) adjacent to said one of the memory cell pair lines. l0. A device according to any one of claims 2 to 9, wherein the isolation trenches which separate the adjacent memory cell pairs in the same memory cell pair line extend in the direction of the bit lines. 11. A device according to any one of claims 2 to l0, wherein the isolation trenches which separate the adjacent memory cell lines from one another extend in the direction of the word lines.

Inventors: ARIMOTO, KAZUTAMI, FURUTANI, KIYOHIRO, MASHIKO, KOICHIRO
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1987
Main classification: H01L27
IPC codes: H01L21, H01L27, G11C11