SEMICONDUCTOR MEMORY DEVICE HAVING ERRONEOUS WRITE OPERATION PREVENTING CIRCUIT

Abstract: In a semiconductor memory device such as an E²PROM, or a NOVRAM a write enable signal (WE) is supplied to a buffer formed by an enhancement-type transistor (Q₁₁) and a depletion-type transistor (Q₁₂) having a node (N₃). The potential at this node is applied to a set terminal of a flip-flop (FF), and only when the potential at the node is higher than a trip point of the flip-flop, is the flip-flop set to generate an internal write enable signal (IWE) for an actual write operation. This prevents spurious signals occurring during powering up and powering down of the memory device.

Description: The present invention relates to the improvement of a circuit to prevent an erroneous write (or erase) operation in a semiconductor memory device such as an electrically erasable and programmable read-only memory (E²PROM) or a nonvolatile random access memory (NOVRAM). In an E²PROM or NOVRAM, a write/erase voltage, which is significantly higher than a normal power supply voltage V CC (for example, 5 V), is required. For this purpose, a step-up circuit has been incorporated into each chip to generate an internal write/erase mode, voltage IVP of 20 to 25 V. That is, in a write/erase mode, a write enable signal is supplied to the step-up circuit, thereby increasing the write/erase voltage IVP. As a result, this high voltage IVP is applied to a memory cell to perform a write/erase operation thereupon due to a tunnelling effect. However, even when the power supply voltage V CC is not high (for example, lower than 3.5 V), the step-up circuit and other circuits such as address buffers may be operated, thus erroneously carrying out a write/erase operation. That is, when the power supply voltage V CC rises or falls because the power supply thereof is turned ON or OFF, an erroneous write/erase operation may be carried out, thus destroying data stored in the cells. To avoid this, a V CC sense circuit is incorporated into each chip for detecting whether or not the power supply voltage V CC is higher than a predetermined value, and therefore, only when the power supply voltage V CC is higher than the predetermined value are the step-up circuit and the like operated. A circuit for preventing an erroneous write/erase operation conventionally comprises such a V CC sense circuit. Prior art or proposed erroneous write/erase operation preventing circuits comprise a first power supply terminal means; a second power supply terminal means; a write enable terminal for receiving a write enable signal; an erroneous write operation preventing circuit, connected to the first and second power supply terminal means and to the write enable terminal, for receiving the write enable signal and generating an internal write enable signal for an actual write operation only when a potential of the high power supply terminal means is higher than a predetermined value; and, resetting means, connected to the erroneous write operation preventing circuit, for resetting the circuit after receiving the internal write enable signal. However, their power consumption is relatively large and their configuration is relatively complex, as will be explained later. According to the invention as specified in claim 1 such an erroneous write operation preventing circuit comprises an enhancement-type MIS transistor having a drain connected to the first power supply terminal means, a gate for receiving the write enable signal, and a source; a depletion-type MIS transistor having a drain connected to the source of the enhancement-type MIS transistor, and a gate connected to a source of it and to the second power supply terminal means; and, a flip-flop having a set terminal connected to the drain of the depletion-type MIS transistor, a reset terminal for receiving an output signal from the resetting means, and an output for generating the internal write enable signal. In this circuit, the write enable signal WE can be a trigger signal, so that only a transient current flows through the buffer formed by the enhancement type transistor and the depletion transistor, thereby reducing its power consumption. Also, the configuration is simple. A particular embodiment of a circuit in accordance with this invention will now be described and contrasted with the prior art with reference to the accompanying drawings, wherein: Figure 1 is a block circuit diagram illustrating all of an E²PROM to which the present invention applies; Figure 2 is a circuit diagram of a previously proposed erroneous write/erase operation preventing circuit; Figure 3 is a circuit diagram of another previously proposed erroneous write/erase operation preventing circuit; Figure 4 is a circuit diagram of the embodiment of the erroneous write/erase operation preventing circuit according to the present invention; Figure 5 is a timing diagram showing the operation of the circuit of Figure 4; Figure 6 is a graph showing the trip point characteristics of the flip-flop of Figure 4; and, Figure 7 is a circuit diagram of a trigger circuit interposed into the circuit of Figure 4. First, an example of an E²PROM will be explained with reference to Fig. 1. In Fig. 1, reference numeral 1 designates a memory cell array including memory cells. For example, a memory cell CL ij is provided at an intersection between a word line W i and a bit line BL j . P j designates a program line. Reference numeral 2 designates row address buffers each receiving an X-address signal A i (i = 0 to n); 3 row address decoders; 4 column address buffers each for receiving a Y-address signal A i ′ (i = 0 to n); 5 column address decoders; and 6 Y-gates. Output data is transmitted from the Y-gates 6 via a sense amplifier 7 and an output data buffer 8 to an output terminal DO, and input data is supplied from an input terminal DI via an input data buffer/latch circuit 9, a write/erase control circuit 10, and a charge pump circuit 11 to the Y-gates 6. Reference numeral 14 designates a mode selection circuit for receiving a chip-enable signal CE , a write-enable signal WE , an output-enable signal OE , and the like, to select an operation mode. That is, the mode selection circuit 14 controls the elements 2, 3, 4, 5, 8, 9, and 10, in accordance with the signal CE , WE , OE , and the like. Reference numeral 15 designates a clock generating circuit which generates a write enable clock signal WE when a write/erase operation is carried out. Reference 16 designates an erroneous write/erase operation preventing circuit which receives the write enable clock signal WE and generates an internal write enable signal IWE for a step-up circuit 17. The step-up circuit generates a high voltage INV during a write/erase mode (IWE = "1"). That is, the high voltage of the step-up circuit 17 is supplied to each of the charge pump circuits 11, 12, and 13. Reference 18 designates a timer activated by the internal write enable signal IWE. That is, when a predetermined time period has passed after the generation of the internal write enable signal IWE, the timer 18 generates a reset signal RST to reset the mode selection circuit 14 and the erroneous write/erase operation preventing circuit 16. A writing operation for the memory cell CL ij is carried out by applying a high voltage (20 V to 25 V) to the word line WL i and to the bit line BL j . An erasing operation for the memory cell CL ij is carried out by applying a high voltage (20 V to 25 V) to the word line WL i and to the program line P j . Note, generally, in an E²PROM, a "writing operation" denotes the writing of data "0" into a cell, and an "erasing operation" denotes the writing of data "1" into a cell. The read operation for the memory cell C ij is carried out by applying a power supply voltage V CC (= 5 V) to the word line WL i and applying a predetermined bias voltage (about 2 V) to the program line P j . In Fig. 2, which illustrates a proposed erroneous write/erase operation preventing circuit, this circuit is comprised of a V CC sense circuit SC, a flip-flop FF, and an AND circuit G₁. The sense circuit SC is comprised of depletion-type transistors Q₁ and Q₂ forming a voltage divider, a depletion-type transistor Q₃ serving as a feedback means, a depletion-type transistor Q₄ and an enhancement-type transistor Q₅ forming an inverter INV₁ , and a depletion-type transistor Q₆ and an enhancement-type transistor Q₇ forming an inverter INV₂. In the circuit of Fig. 2, since the transistor Q₂ is always conductive to pull down the potential at node N₁ to the ground GND, the potential at node N₁ is 0 V when the power supply voltage V CC is 0 V. Next, when a power supply is turned ON to raise the power supply voltage V CC , a current flowing through the transistors Q₁ and Q₂ increases so that the potential at node N₁ is increased in accordance with the conductance ratio of the transistor Q₁ to the transistor Q₂. As a result, when the potential at node N₁ exceeds a trip point of the inverter INV₁ , the inverters INV₁ and INV₂ are operated to increase the potential at node N₂ , which is fed back to the gate of the transistor Q₃. Therefore, the potential at node N₁ is rapidly increased, and accordingly, the potential at node N₂ is also rapidly increased. As a result, the flip-flop FF is set to generate an internal write enable signal IWE via the AND circuit G₁. In this case, the transistor Q₃ remains in a conductive state, so that the potential at node N₁ is stable and holds the operation of the inverters INV₁ and INV₂. Conversely, when the power supply is turned OFF, the power supply voltage V CC is decreased. As a result, when the potential at node N₁ becomes lower than the trip point of the inverter INV₁ , the potential at node N₂ is decreased. Therefore, in the circuit of Fig. 2, when the trip point of the inverter INV₁ is designed to meet the case wherein the power supply voltage V CC is a predetermined value such as 3.5 V, the circuit of Fig. 2 exhibits an excellent V CC sense circuit function. In the circuit of Fig. 2, since the initial stage such as Q₁ to Q₃ is comprised of depletion-type transistors which are resistant to noise, it is not affected by the fluctuation of each element. In the circuit of Fig. 2, however, since the inverter INV₁ is operated only when a difference between the potential at node N₁ and the power supply voltage reaches a constant value, the above-mentioned voltage divider is necessary for effectively operating the inverter INV₁. Therefore, when the power supply is being turned ON, a current always flows through the voltage divider (Q₁ and Q₂), thus raising a problem of a large power consumption. Also, in this case, a current flows through at least one of the inverters INV₁ and INV₂ , thus also raising a problem of a large power consumption. In Fig. 3, which illustrates another proposed erroneous write/erase operation preventing circuit which solves the power consumption problems in the circuit of Fig. 2, a complementary MOS (CMOS) inverter INV₃ , a P-channel MOS transistor Q₈ , and an N-channel MOS transistor Q₉ are added to the elements of Fig. 2, and the inverters INV₁ and INV₂ are also CMOS type. An inverted signal WE of the write enable signal WE is applied to the gates of the transistors Q₈ and Q₉ , as a result, even after the power supply is turned ON, if the signal WE is at a high level (non write/erase mode), the transistor Q₈ is turned OFF while the transistor Q₉ is turned ON. As a result, no current flows through the V CC sense circuit SC. That is, only when the signal WE is at a low level (write/erase mode), is the V CC sense circuit SC operated. Further, in the circuit of Fig. 3, since the V CC sense circuit SC is controlled by the power supply voltage V CC and the inverted signal WE of the write enable signal WE, the configuration and operation thereof are complex. Furthermore, in the circuit of Fig. 3 as well as the circuit of Fig. 2, a hysteresis phenomenon occurs when the power supply is turned ON and OFF. It is, however, impossible to avoid this hysteresis phenomenon, since the potential at node N₂ is fed back to the base of the transistor Q₃. In order to reduce the hysteresis phenomenon, the size of the feedback transistor Q₃ may be reduced. In this case, however, since the rise time of the power supply is on the order of milliseconds while the operation speed of the inverters is on the order of nanoseconds, the V CC sense circuit SC may be oscillated when the power supply voltage CC rises, thus inviting a malfunction in the operation of the internal circuits. In Fig. 4, which illustrates an embodiment of the erroneous write/erase operation preventing circuit according to the present invention, an N-channel enhancement-type transistor Q₁₁ and an N-channel depletion-type transistor Q₁₂ are connected in series between the power supply terminals labelled V CC and GND, to form the V CC sense circuit SC. That is, the transistor Q₁₁ has a drain connected to the power supply V CC , a base for receiving a write enable signal WE, and a source connected to a node N₃. Also, the transistor Q₁₂ has a drain connected to the node N₃ , and a gate connected to a source thereof, which is also connected to the power supply GND. Connected to the node N₃ is a flip-flop FF formed by two cross-coupled NOR circuits G₂ and G₃. In this case, the NOR circuits G₂ and G₃ are comprised of well known CMOS transistors. The operation of the circuit of Fig. 4 will be explained with reference to Figs. 5 and 6. When the power supply voltage V CC rises from time t₀ , the write enable signal WE and the inverted signal WE thereof also rise, however, these signals cannot exceed the power supply voltage V CC , since they are internal signals. At time t₁ , when the write enable signal WE rises due to noise or the like to turn ON the transistor Q₁₁ , the potential at node N₃ also rises, but in this case, this potential cannot exceed a trip point V tp1 of the flip-flop FF which is dependent upon the power supply voltage V CC (= V CC1 ) at time t₂ , as shown in Fig. 6. Contrary to above, at time t₃ , when the write enable signal WE rises to turn ON the transistor Q₁₁ , the potential at node N₃ rises, and in this case, this potential exceeds a trip point V tp2 of the flip-flop FF where V CC equals V CC2 , as shown in Fig. 6. Thus, if the trip point characteristics of the CMOS flip-flop FF are suitably adjusted, the flip-flop FF is not set before the power supply voltage V CC reaches a level which is, for example, between the two levels V CC1 and V CC2 . Therefore, an erroneous write/erase operation due to noise can be avoided when the power supply voltage V CC is relatively low. Once the potential at node N₃ reaches the above-mentioned level for 5 to 6 nanoseconds, the flip-flop FF can not be inverted by any kind of noise. Also, in the circuit of Fig. 4, the hysteresis phenomenon does not occur when the power supply is turned ON and OFF. Further, if a trigger pulse WE′ is used instead of the write enable signal WE, current flows through the V CC sense circuit SC for only a very short time period, thus further reducing the power consumption. Note that such a trigger pulse WE′ can be generated by a trigger circuit 19 as shown in Fig. 7. In Fig. 7, INV₄ designates a CMOS inverter, R a resistor, C a capacitor, and G₄ a CMOS NOR circuit. As explained above, the erroneous write/erase operation preventing circuit of the present invention has an advantage over the proposed circuits, in that the configuration is simple; the hysteresis phenomenon does not occur when the power supply is turned ON and OFF; and, the circuit does not operate before the power supply voltage V CC reaches a predetermined voltage, so that the operation of the circuit is not affected by noise. Further, since the control signal of the current cut-off transistor Q₁₁ can be a trigger pulse, only a transient current flows through the transistors of the V CC sense circuit, and thus it is possible to realize a very low power dissipation circuit.

Claims: A semiconductor memory device comprising: a first power supply terminal means (V CC ); a second power supply terminal means (GND); a write enable terminal for receiving a write enable signal (WE); an erroneous write operation preventing circuit (16″), connected to the first and second power supply terminal means and to the write enable terminal, for receiving the write enable signal (WE) and generating an internal write enable signal (IWE) for an actual write operation only when a potential of the high power supply terminal means is higher than a predetermined value; and, resetting means, connected to the erroneous write operation preventing circuit (16"), for resetting the circuit after receiving the internal write enable signal (IWE), characteristised in that the erroneous write operation preventing circuit (16") comprises: an enhancement-type MIS transistor (Q₁₁) having a drain connected to the first power supply terminal means, a gate for receiving the write enable signal, and a source; a depletion-type MIS transistor (Q₁₂) having a drain connected to the source of the enhancement-type MIS transistor (Q₁₁), and a gate connected to a source of it and to the second power supply terminal means; and, a flip-flop (FF) having a set terminal connected to the drain of the depletion-type MIS transistor (Q₁₂), a reset terminal for receiving an output signal from the resetting means, and an output for generating the internal write enable signal (IWE). A device according to in claim 1, wherein the flip-flop comprises cross-coupled CMIS NOR circuits (G₂, G₃). A device according to claim 1 or 2, further comprising a trigger circuit (19) connected between the write enable terminal and the erroneous write operation preventing circuit. A device according to any one of the preceding claims, further comprising a write enable signal generating circuit (14, 15), connected to the write enable terminal, for generating the write enable signal. A device according to any one of the preceding claims, wherein the resetting means comprises a timer (18) for resetting the write operation preventing circuit when a predetermined time period after receiving said interal write enable signal has elapsed.

Inventors: ARAKAWA, HIDEKI
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C7
IPC codes: G11C16, G11C29, G06F12, G11C17, G11C11, G11C7