Semiconductor device comprising a MOS transistor, and method of making the same

Abstract: A semiconductor apparatus comprises a semiconductor body (15, 16) of one conductivity type; a first impurity region (14) of an opposite conductivity type, which is formed in the surface area of the semiconductor body (15, 16); impurity regions (29a and 29b) of the opposite conductivity type, formed in the surface area of the semiconductor body (15, 16), at locations away from the first impurity region (14); second and third impurity regions (17 and 18) of one conductivity type, which serve as source and drain regions, respectively, and are formed in the impurity regions (29a and 29b) of an opposite conductivity type, so as to sandwich a channel region; and a gate electrode (20) formed on the channel region, through an insulative layer. In this semicon­ ductor apparatus, the impurity regions of the opposite conductivity type include fourth and fifth impurity regions (29a and 29b), formed in the channel region such that at least parts of the fourth and fifth impurity regions overlap.

Description: The present invention relates to a semiconductor apparatus including an MOS structure and a semiconductor device having an impurity concentration higher than a channel region of the MOS structure, and also relates to a method of manufacturing such a semiconductor apparatus. As disclosed in JP-A 60-74678, for example, a thyristor and a TRIAC in which an MOS structure is compounded have hitherto been known. Fig. 1 shows an example of the structure of a semiconductor apparatus including a thyristor having the MOS structure. In this case, the planar type is assumed. The semiconductor apparatus shown in Fig. 1 includes thyristor 11 and MOS transistor 12 for short-circuiting gate G and cathode K of thyristor 11. Thyristor 11 comprises: N-type emitter region 13; a P-type base region 14; N-type base region 15; and P-type emitter region 16. On the other hand, MOS transistor 12 comprises: N type source region 17; N-type drain region 18; gate insulative film 19; and gate electrode 20. MOS transistor 12 is formed in p-type well region 21. P-type well region 22, for driving the gate of MOS transistor 12, is surrounded by guard ring 23a. To obtain the desired characteristics in the foregoing constitution, the surface impurity concentration of P-type base region 14 of thyristor 11 must be set to approx. 2 × 10¹⁷ cm⁻³, and the surface impurity concentration of P-type well region 21, in which MOS transistor 12 is formed, must be set to approx. 5 × 10¹⁶ cm⁻³. Thus, it is necessary to form P-type regions 14 and 21 having surface impurity concentrations different from each other, and the impurities must be implanted and diffused into each of these regions in different steps. Therefore, as can be clearly seen, there are drawbacks to the present method of manufacturing this type of semiconductor device, such as the increased complexity of the manufacturing process, along with the inevitable increase in manufacturing cost and the reduction in yield. Figs. 2A to 2G show several of the steps involved in the manufacturing of a thyristor including an MOS structure with much attention to the formation of P-type regions 14 and 21. First, as is shown in Fig. 2A, in relatively thick oxide film 24 formed on N-type base region 15, the portion corresponding to the region where P-type base region 14 will be formed is etched to thereby form opening 25. Next, as is shown in Fig. 2B, buffer oxide film 26 whose thickness is about 100 nm (1000Å)is formed on N-type base region 15 exposed in opening 25. Then, P-type impurities are ion implanted into base region 15, through oxide film 26, to a predetermined concentration. Thereafter, a heat treatment is performed, and the P-type impurities are annealed and diffused, thereby forming P-type impurity layer 14A serving as P-type base region 14, as shown in Fig. 2C. Next, as is shown in Fig. 2D, the portion corresponding to oxide film 24, on the region where P-type well region 21 of MOS transistor 12 will be formed, is etched to thereby form opening 27. Buffer oxide film 28 is formed on the exposed surface of N-type base region 15 in opening 27. As this buffer oxide film 28 is formed. the buffer oxide film 26 simultaneously increases thickness. P-type impurities are implanted into base region 15 through only buffer oxide film 28. The dose amount at this time is set to a value lower than that used in formation of P-type impurity layer 14A. Next, a heat treatment is performed to diffuse and anneal the P-type impurities. As a result, as is shown in Fig. 2E, the impurities in P-type impurity layer 14A are deeply diffused and P-type impurity layer 14A serves as P-type base region 14. After this, P-type well region 21 is formed. After buffer oxide film 28 has been removed (this film may be left and used as a gate oxide film without removing), as is shown in Fig. 2F, gate oxide film 19 is formed, with gate electrode 20 being formed thereon. Thereafter, N-type impurities are ion implanted, using gate electrode 20 and oxide film 24 as masks, after which annealing and diffusing are performed. As a result, as can be seen in Fig. 2G, source region 17 and drain region 18 are formed in P-type well region 21. The foregoing manufacturing method does, however, have drawbacks, such as that the manufacturing steps are complicated and the overall manufacturing process, therefore, time-consuming, and that it is difficult to control the surface impurity concentrations, diffusion depths, and the like of P-type base region 14 and P-type well region 21. US-A-3 608 189 shows a diffusion method for forming diffused well regions, to form a complementary N channel and P channel FET device. The channel region is formed by lateral diffusion. It is an object of the present invention to provide a semiconductor apparatus in which an active region having a low surface impurity concentration and an active region having a high surface impurity concentration can be formed simultaneously, so as to respectively have desired impurity concentrations, and to provide a method of manufacturing such a semiconductor apparatus. According to the invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming an insulative layer on a semiconductor region of one conductivity type in a semiconductor body of the opposite conductivity type; forming first and second opening portions on said insulative layer, such that said portions are located away from each other; forming an insulative film thinner than said insulative layer on said semiconductor region exposed by said first and second opening portions; forming a gate electrode on said insulative film in said second opening portion; forming simultaneously a first impurity region in the portion corresponding to said first opening portion, and second and third impurity regions in the portion corresponding to said second opening portion, so that parts of said second and third impurity regions overlap, by implanting and diffusing impurities of an opposite conductivity type in said semiconductor region, through the respective opening portions, by using said insulative layer and said gate electrode as a mask, thereby forming a channel region including at least a part of the overlap portion of said second and third impurity regions , said channel region having a lower surface impurity concentration than that of the central positions of said first, second and third impurity regions; and forming fourth and fifth impurity regions, serving as a source and a drain, respectively, by implanting impurities of one conductivity type into said second and third impurity regions, through the second opening portion. According to a manufacturing method of the semiconductor apparatus embodying the present invention, the channel region at the MOS device is formed by a coupling portion of the second and third impurity regions, which are formed by the same step in which the first impurity region is formed. Therefore, the channel region having an impurity concentration lower than the active region of the first impurity region can be formed simultaneous with the formation of the first impurity region. This invention can be more fully understood by way of example from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a cross-sectional structure of a conventional semiconductor apparatus having a P-type base region and a P-channel region; Figs. 2A to 2G show several of the steps involved in the manufacture of the semiconductcr apparatus shown in Fig. 1; Fig. 3 relates to an embodiment of the present invention and shows a cross-sectional structure of a semiconductor apparatus having a P-type base region and a P-channel region; and Figs. 4A to 4F show several of the steps involved in the manufacture of the semiconductor apparatus shown in Fig. 3. Fig. 3 shows a cross sectional structure of a semiconductor apparatus according to an embodiment of the present invention. Figs. 4A to 4F show a part of the manufacturing steps of a thyristor including the MOS structure in which two P-type active regions having different surface impurity concentrations are formed by the same step. In Fig. 3, the same parts and components as those shown in Fig. 1 are designated by the same reference numerals. The constitution of Fig. 3 is similar to that of Fig. 1 except for the P-type well region which forms MOS transistor 12. Namely, in Fig. 3, P-type well region 30 is formed by connecting two P-type impurity diffusion regions 29a and 29b by diffusing them in the horizontal direction. A part of the manufacturing steps of the semiconductor apparatus including P-type base region 14 and P-type well region 30 having different surface impurity concentrations will now be described with reference to Figs. 4A to 4F. First, as shown in Fig. 4A, relatively thick oxide film 31 is formed on N-type base region 15. The regions where P-type base region 14 and P-type well region 30 will be formed are etched to thereby form openings 32 and 33. Thereafter, as shown in Fig. 4B, gate oxide film 19 having a thickness of about 100 nm (1000Å) is formed on N-type base region 15 exposed in openings 32 and 33. Next, as shown in Fig. 4C, gate electrode (polysilicon gate) 20 having a length ℓ (ℓ is set to a value not larger than the value which is twice as long as diffusion length xj in the horizontal direction after the diffusion of the P-type impurity region; for example, ℓ ≦ 2xj ) is formed on gate oxide film 19 on the region where P-type well region 30 will be formed. Then, as shown in Fig. 4D, P-type impurities are ion implanted. At this time, surface impurity concentration Qd was set to 1 × 10¹⁴ cm⁻² and accelerating voltage V was set to 50 keV. Next, the heat treatment is performed to anneal and diffuse the ion implanted P-type impurities. Thus, as shown in Fig. 4E, P-type impurity regions 14, 29a, and 29b are formed. Regions 29a and 29b are connected by the diffusion in the horizontal direction and P-type well region 30 is formed. When the diffusion was performed until xj = 20 µm , the surface impurity concentration of P-type base region 14 in thyristor 11 was 2 × 10¹⁷ cm⁻³ and the surface impurity concentration of P-type well region 30 forming MOS transistor 12 was 6 × 10¹⁶ cm⁻³ at the lowest position (at the middle point of gate electrode 20). Next, as shown in Fig. 4F, N-type impurities are selectively ion implanted into the region where MOS transistor 12 will be formed by use of gate electrode 20 as a mask. Then, the annealing and diffusion are performed to thereby form source region 17 and drain region 18. It has been confirmed that the characteristics of sole MOS transistor 12 formed by the foregoing steps can be controlled by the channel length and the length ℓ of gate electrode and when this manufacturing method is applied to production of the thyristor including the MOS structure therein, the thyristor can correctly operate. According to such a manufacturing method, two diffusion layers having different surface impurity concentrations can be formed by a single impurity implanting and diffusing step, so that the manufacturing steps can be simplified and the cost can be reduced. In addition, since the implantation and diffusion of impurities can be performed by only a single step, a concentration of impurities and a depth of diffusion thereof can be easily controlled. Although polysilicon gate 20 has been used as a mask when the P-type impurities are ion implanted in the foregoing embodiment, it is also possible to form a thick oxide film on the channel and to use this thick oxide film as a mask. On the other hand, although an example of formation of the N-channel type MOS transistor has been described above, a P-channel type MOS transistor can be also formed in a manner similar to the above. Further, in the step of Fig. 4D, impurity regions can be formed in substrate 15 by a diffusion process after selectively etching out corresponding portions of oxidation films 19.

Claims: A method of manufacturing a semiconductor device comprising the steps of: forming an insulative layer (31) on a semiconductor region (15) of one conductivity type in a semiconductor body (16) of the opposite conductivity type; forming first and second opening portions (32 and 33) on said insulative layer, such that said portions are located away from each other; forming an insulative film (19) thinner than said insulative layer (31) on said semiconductor region (15) exposed by said first and second opening portions (32 and 33); forming a gate electrode (20) on said insulative film (19) in said second opening portion (33); forming simultaneously a first impurity region (14) in the portion corresponding to said first opening portion (32), and second and third impurity regions (29a and 29b) in the portion corresponding to said second opening portion (33), so that parts of said second and third impurity regions overlap, by implanting and diffusing impurities of an opposite conductivity type in said semiconductor region (15), through the respective opening portions, by using said insulative layer (31) and said gate electrode (20) as a mask, thereby forming a channel region including at least a part of the overlap portion of said second and third impurity regions , said channel region having a lower surface impurity concentration than that of the central portions of said first, second and third impurity regions (14, 29a, 29b); and forming fourth and fifth impurity regions (17 and 18), serving as a source and a drain, respectively, by implanting impurities of one conductivity type into said second and third impurity regions (29a and 29b), through the second opening portion (33). A method according to claim 1, further comprising the step of forming: a sixth impurity region (13) of one conductivity type, in said first impurity region (14).

Inventors: JITSUKATA KOUJI A - TOSHIBA-DA, YAKUSHIJI SHIGENORI C O PATENT, JITSUKATA, KOUJI A1-1, TOSHIBA-DAISAN-MIYUKI-RYO, YAKUSHIJI, SHIGENORI C/O PATENT DIVISION
Applicants: TOSHIBA COMPONENTS, TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA, TOSHIBA COMPONENTS CO., LTD.
Application year: 1987
Main classification: H01L27
IPC codes: H01L29, H01L21, H01L27