Display apparatus

Abstract: A display apparatus, comprises a plurality of pixels ar­ ranged in pluralities of rows and columns a plurality of first con­ trol lines each connecting a column of pixels in common, and a plurality of second control lines each connecting a row of pix­ els in common. The first control lines are divided into a plurality of blocks. Third control lines are disposed so that the first con­ trol lines in each of the blocks are commonly connected by a third control line. A multiplexing switching element is disposed at each connection between the third control lines and the first control lines. Further, a difference in output voltage between two multiplexing switching elements disposed at a boundary between a neighboring pair of blocks is 50 mV or less.

Description: FIELD OF THE INVENTION AND RELATED ART The present invention relates to a display apparatus, particularly an apparatus using a liquid crystal display panel. As a representative liquid crystal display apparatus comprising an active matrix circuit substrate, one using TFTs (thin film transistors) as analog switching elements has been used. With respect to this type of liauid crystal display apparatuses, a high density arrangement and a large area display have progressed so that the number of signal lines has increased to nearly 2000. Corresponding thereto, the problems of connection with external circuits and increase in number of driver ICs become serious, which results in lowering in production yield and increase in production cost. Document FR-A-2 507 366 discloses a display apparatus having a plurality of pixels arranged in pluralities of rows and columns. A plurality of first control lines each connecting a column of pixels is divided into a plurality of blocks, while a plurality of second control lines each connect a row of pixels. Furthermore, third control lines are branched into a plurality of lead lines so that corresponding ones of said first control lines in each of the blocks are commonly connected by a respective one of said third control lines through corresponding ones of said plurality of lead lines. A plurality of multiplexing switching elements each corresponding to a respective one of said first control lines are disposed at each connection between said plurality of lead lines and said first control lines. Finally fourth control lines supply control signals to said multiplexing switching elements and are disposed so that said multiplexing switching elements in each of the blocks are commonly connected by a respective one of said fourth control lines. Figure 18 shows an example of such a conventional active matrix type liquid crystal (hereinafter sometimes abbreviated as "LC") display apparatus. Referring to the figure, reference numeral 1 denotes a display unit; ANM, a TFT switching element for driving a pixel; 2, a signal line driver circuit; 3, a scanning line driver circuit; and 4, a connection between the display unit 1 and the signal line driver circuit. Figure 19 is a time chart illustrating an image signal which is sampled and held by the signal line driver circuit 2 to be sent to signal lines S(1) - S(M), and scanning signals applied to scanning lines G(1) - G(M). When N scanning lines and M signal lines are arranged to form a matrix, the number of connections 4 becomes M. As for the density, where an LC-full color television panel comprising 480(N) scanning lines, a diagonal picture size of 7 inches and an aspect ratio of 3:4, is considered; the number of signal lines (M) becomes 1920 (= 480 x 3 x 4/3) and the transverse picture length l is given by: l = 7 x 25.4 mm x 4/5 ≃ 142 mm As a result, the signal line density (d) is given by: d = M/ l = 1920/142 = 13.5 lines/mm (Incidentally, M is given as the total number of the signal lines for respective colors including red(R), green(G) and blue(B). If it is assumed that one pixel is constituted by R, G and B elements, the picture is composed of a matrix of N x M/3 pixels). The necessity of connecting such a large number of signal lines in a high density with the external signal line driver circuit 2, there have arisen several problems heretofore, such as lowering in reliability of manufacturing and production yield and increase in production cost due increase in number of external driver ICs. Further, in order to dispose the ICs, a large size of substrate is required, and there results in a problem of imbalance that the external circuit unit occupies a large area compared with the display unit. SUMMARY OF THE INVENTION The present invention has been accomplished in view of the above problems of the prior art and aims at reducing connections of signal lines for a display panel with an external driver circuit, thereby to achieve simplification of manufacturing, increase in production yield, decrease in manufacturing cost, and further decrease in number of external signal line driver ICs, reduction in scale and size of the external driver circuits, and reduction in cost accompanying the above. According to the present invention there is provided a display apparatus comprising a plurality of pixels arranged in pluralities of rows and columns; a plurality of first control lines each connecting a column of pixels, said first control lines being divided into a plurality of blocks; a plurality of second control lines each connecting a row of pixels; third control lines each branched into a plurality of lead lines so that corresponding ones of said first control lines in each of the blocks are commonly connected by a respective one of said third control lines through corresponding ones of said plurality of lead lines; a plurality of multiplexing switching elements each corresponding to a respective one of said first control lines, said switching elements being disposed at each connection between said plurality of lead lines and said first control lines, and said multiplexing elements being divided into the plurality of blocks; and fourth control lines supplying control signals to said multiplexing switching elements and being disposed so that said multiplexing switching elements in each of the blocks are commonly connected by a respective one of said fourth control lines, said display apparatus being characterized in that said fourth control lines are disposed so that a substantially equal number of corresponding lead lines are disposed on each side of said respective one of said fourth control lines for each of the plurality of blocks, and when similar control signals are applied to adjacent blocks as supplied by said fourth control lines, a difference in voltage between corresponding first control lines of two multiplexing switching elements for the adjacent blocks disposed at a boundery between a neighboring pair of blocks is at most 50 mV. The output voltages used herein for defining the uniformity of the signal output system are based on a constant arbitrary level of input signal in the operational range supplied from the signal line driver circuit. In order to suppress the difference in output voltages from the signal lines, it is preferred that a lead line for supplying a control signal to a control line for each block is connected to a part of the control line which divides the control line into substantially equal halves each commonly connecting a substantially half (generally in the range of 40 - 60 %) of the multiplexing switching elements for the block. These and other objects, features and advantages of the present invention will become more apparent upon a consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic plan view of an embodiment of an active matrix type liquid crystal display apparatus (N x M pixels) according to the present invention; Figure 2 is a partially enlarged view of an n x m matrix wiring circuit connected to M signal lines (m < M) for the N x M active matrix; Figure 3 is an image signal output circuit diagram for supplying image signals to m signal lines in a multiplexing matrix according to the present invention; Figure 4 is a time chart of image signals, switching signals to signal lines and M switching elements according to the present invention and a pixel scanning signal; Figure 5 illustrates a signal line arrangement with a lower density according to the present invention; Figure 6 illustrates a signal line arrangement with a low density according to another embodiment of the present invention; Figure 7 illustrates a preferred arrangement of a gate line or switching line according to the present invention; Figures 8 and 9 are enlarged partial views of Figure 6; Figures 10A and 11A are enlarged views of an intersection and a TFT, respectively, and Figures 10B and 11B are corresponding sectional views across thickness; Figure 12 is an equivalent circuit diagram illustrating a gate pulse delay; Figure 13 is a time chart showing a relation between an applied voltage and a charge time; Figure 14 is a plan view showing another wiring arrangement according to the present invention; Figures 15A - 15C show sections of three parts in Figure 14; Figures 16 and 17 are enlarged partial views of Figure 1; Figure 18 is a schematic plan view showing an N x M active matrix liquid crystal display apparatus; and Figure 19 is a time chart showing a time-serial relationship of image signals and scanning signals. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Figure 1 shows an embodiment of the present invention, which comprises an N x M active matrix liquid crystal display unit comprising N x M pixels each provided with a switching element (which may be a TFT or a non-linear element such as an MIM (metal-insulator-metal)) as shown in Figure 18, and also an additional n x m active matrix circuit 5 disposed on the same substrate as the N x M active matrix display unit and encircled with a dashed line in the figure. Figure 2 illustrates the internal arrangement of the n x m active matrix circuit which comprises analog or multiplexing switching transistors (hereinafter sometimes abbreviated as "AS transistor(s)") 6 for image or video signals; image signal sample-and-hold capacitors 7 each following one of the AS transistors 6; image signal lines S(1) - S(m) for supplying latched image signals to the AS transistors 6; and switching or gate line g(1) - g(n) for switching the AS transistors 6. More specifically, the matrix circuit shown in Figure 2 is constituted by dividing M signal lines for constituting the N x M display matrix shown in Figure 18 into n blocks each having m lines ( n and m are integers satisfying n ≧ M/m). Thus n lines gathered by selecting one from each of the n groups are commonly connected to one of the signal lines S(1) - S(m) through corresponding AS transistors 6 so that they are selectively supplied with an image signal from one of the signal lines S(1) - S(m) through a transistor 6, which is to be stored in a corresponding capacitor 7. In this way, the n x m matrix circuit shown in Figure 2 is constituted by m image signal lines S(1) - S(m), n switching signal lines g(1) - g(n), and n x m AS transistors 6 and capacitors 7. Now, when image signals are treated with an image signal latch circuit or source driver shown in Figure 3 and supplied to the signal line S(1) - S(m) shown in Figure 2, time relations as shown in Figure 4 among the image signals, the signals at AS transistors (source drivers) 6, the voltage level of the counter electrode (ITO (indium-tin-oxide)), switching signals g₁, g₂, and a scanning signal for a display transistor (represented by G₁ as shown in Figure 1) may be obtained. More specifically, with reference to Figure 3, input analog image signals 9 are supplied under the control of pulses supplied from a shift register 8 at time ₁, sequentially sampled by transistors 10, held by capacitors 11 and amplified by amplifiers (source follow buffers) 12. The thus A/D-converted image signals are latched by transistors 13 at the same time ₂ and supplied to the signals lines S(1) - S(m) shown in Figure 1 or 2. The points of time for the latching with respect to the respective switching signal lines g(1) - g(n) or with respect to respective outputs to the signal lines S(1) - S(m) are denoted by t₁, t₂, ... t n (n = 8 in Figure 4), which correspond to phases 1, 2, ... 8 of the video signal shown in Figure 4. The AS transistors 6 controlled by g(1) - g(n) are respectively turned on for Δt = t₂-t₁ = t₃-t₂ = ... and supply the image signals from the latch circuit shown in Figure 3 to the corresponding capacitors 7 at each time of Δt. Then, after the image signals for the final block are held in the corresponding capacitors 7 by turning on the corresponding transistors 6 through the switching signal line g(n) at the time t n , a switching signal line for transistors in the display unit 1 shown in Figure 1, i.e., one of the pixel scanning lines G(1) - G(N), is turned on to supply the A/D-converted image signals to the pixels on the scanning line in a period of t G including a horizontal fly-back time for image signals and before the subsequent latch time for a first block of signal lines S(1) - S(n) with respect to the subsequent scanning line. By repeating the above operation for a number of times equal to the number of scanning lines, image data for one picture are transferred to the respective pixels to provide a display of one picture. Now, a case where television signals according to the NTSC system are displayed on a panel having a pixel matrix of N = 480 and M = 1920 with a frame frequency of 60 Hz by using an n x m signal distribution of m = 240 and n = 8, is considered. In this case, one horizontal scanning period is 63.5 µsec and one horizontal fly-back time is 11.5 µsec, so that the time Δt for driving one block of signal lines S(1) - S(m) is given by: Δt ≦ (63.5-11.5)/9 = 5.78 µsec (one Δt is additionally taken as a time for A/D conversion), and the time t G which is the maximum time available for supplying image data to the pixels on one scanning line is given by: t G ≦ 63.5 - 5.8 x 8 = 17.1 µsec. In this regard, it is to be noted that the time Δt of 5.8 µsec for the final block operation time t n may also be used as a part of t G . More specifically, the synchronizing the time t n for turning-on the last switching line g(n) and the time for turning on an arbitrary scanning line, e.g. G(i) (= i-th scanning line), actually has a meaning that the image signals sampled-and-held by a circuit shown in Figure 3 are directly sent to the pixels through AS transistors 6, and thus can be effected without problem. By doing so, the charging time for pixel switching transistors can be extended to decrease the load of the transistors, so that small-capacity transistors will be sufficient. In this case, the number of connections between the external signal processing circuit shown in Figure 3 and the signal lines S(1) - S(m) shown in Figure 1 or Figure 2 is equal to m (= 240), so that the signal line density can be lowered to d = m/ l = 240/142 = 1.69 lines/mm. Figure 5 shows an example of low-density layout of signal lines S(1) - S(m). Figure 6 shows another example of low density arrangement of S(1) - S(m) in combination with g(1) - g(n). In this case, the signal line density is increased to d = (240+8)/142 = 1.75 lines/mm, but the increase is so slight that the effect of decreasing the number of connection is hardly affected thereby, and on the other hand, there can be attained an advantage that the required performances of the amplifiers 12 in the external signal processing unit shown in Figure 3 are made uniform. More specifically, in the arrangement shown in Figure 6, the wiring capacitance provided by overlappings or intersections of the lines g(1) - g(n) and the lines S(1) - S(m) on the matrix circuit substrate is made uniform, so that data fluctuation against the outputs from the external circuit shown in Figure 3 is uniformized and the designing for suppressing image fluctuation becomes easier. Incidentally, the AS transistors 6 for block division can have basically the same structure as the pixel switching transistors, and the data holding capacitors 7 may be produced by using a known technique in parallel with the production of the transistors or can be omitted by using wiring capacitances etc., so that it would be apparent that the n x m active matrix circuit 5 for block division may be formed on the same substrate as the display unit 1. In the display apparatus according to the present invention, as shown in Figure 4, video signals are transformed by a source driver as shown in Figure 3 into digital signals which are polarity-inverted in each horizontal scanning period, and the digital signals are supplied to the signal lines S(1) - S(m) in the n x m active matrix circuit 5. In this instance, according to Figure 4, after the gates of pixel switching transistors on a scanning line (e.g., G₁) is turned off, the polarity of the common electrode (ITO) is inverted and then the gates of the first block AS transistors are turned on (g₁) followed by the operation of subsequent blocks, so that the magnitude of actual delay in polarity inversion of the common electrode determines the durations of the gate-on pulses of the AS transistors 6 in the n x m active matrix circuit 5 and the gate-on pulses of the pixel switching transistors 14, and accordingly the charge efficiency of the pixel switching transistors, which in turn determines the magnitude of effective voltage applied to the liquid crystal and the electro-optical characteristics of the display unit 1. This means that the delay in polarity inversion of the common electrode should be minimized so that enough time is left as the durations of the gate-on pulses for the AS transistors 6 and the pixel switching transistors 14 in the period of t G (= 17.1 µsec) as described above. More specifically, if a duration Δt of 5.8 µsec is secured for an AS transistor 6 and a duration of 15.5 to 16.5 µsec is secured for the gate-on pulse of a pixel switching transistor 14 so as to allow the use of a small pixel TFT, the delay in polarity-inversion of the control electrode should be suppressed to only 0.5 - 1.5 µsec. In the display apparatus according to the present invention, the delay in polarity inversion of the common electrode may be suppressed to 1.5 µsec or less by disposing a low-resistivity conductor of a metal such as silver, aluminum, chromium, gold or an alloy of such a metal which preferably provides a sheet resistivity on the order of 0.4 Ω/□ or below which is lower than a sheet resistivity on the order of 100 Ω/□ of a uniform ITO film forming a common electrode. Herein, the sheet resistivity may be measured according to ASTM D-257. The low-resistivity conductor may be disposed in the form of a frame surrounding a uniformly disposed transparent common electrode of, e.g., ITO, or stripes or mesh (cross stripes) formed on a uniformly disposed common electrode so as to extend or to face either one or both of the scanning electrodes and the signal electrodes on the active matrix circuit substrate. It is further preferred that the low-resistivity conductor is disposed in the form of a combination of the frame with the stripe or further preferably with the mesh conductor. In the case of a frame conductor, it is possible to dispose terminals of the common electrode at at least two of the four corners of the frame. The stripe or mesh (cross stripe) conductor is formed, e.g., in a thickness of 50-150 nm (500 - 1500 Å)and a width of 1 - 50 µ so as to leave a transparent display area at a rate of 60 % or more. The stripe or mesh conductor may also be formed in alignment with the arrangement of the switching elements formed on the active matrix circuit so as to interrupt incident light from entering a thin film semiconductor constituting a TFT as a switching element. In the present invention, it is also possible to provide a conductive color filter used for color display on a common electrode or to dispose a metal stripe mask used for color display on a common electrode to decrease the delay in signal polarity inversion due to the common electrode. The present invention further provides an improved arrangement of switching or gate lines (g(1) - g(n)) in the above mentioned n x m active matrix, i.e., a multiplexing TFT matrix for block division of signal lines. More specifically, depending on the arrangement of the gate lines, there arise remarkably different degrees of delay of gate pulses applied to the respective TFTs which lead to a difference or lowering in luminance on a picture. The delay comprises principally the following two types depending on the causes: a) A delay caused by capacitances (C cross ) occurring at the intersections of the source lines S₁, S₂, ... and the gate lines g₁, g₁, ..., and the wiring resistance (R g ). b) A delay caused by channel parasitic capacitances (C gs and C gd ) and channel capacitance (C channel ) of TFTs. The delay is represented by an equivalent circuit shown in Figure 12, and will be explained in more detail based on an embodiment. Figure 16 is an enlarged partial view of the n x m active matrix circuit unit 5 shown in Figure 1, and Figure 17 is a further enlarged view. Referring to the figures, among the intersections (some are denoted by ○ in Figure 17) of the gate lines (g₁ - g g ) and the source lines (S₁ - S₂₄₀), at each of the intersections on the lowermost row, a TFT 93 is formed. From each TFT 93, an output line (signal line) 94 is led out extending to pixel switching elements (14 in Figure 1). Figure 10A is an enlarged view of the above mentioned intersection not provided with a TFT, and Figure 10B is a sectional view across the thickness. Figure 11A is an enlarged view of a TFT 93, and Figure 11B is a sectional view across the thickness. Referring to Figures 10A and 10B, the gate line 91 has a width of 20 µm and the source line 92 has a width of 20 µm. Between these metal layers, an ohmic resistance layer 95 of n⁺-a-Si (a-Si denotes amorphous silicon), a semiconductor layer 96 of a-Si, and an insulating layer of SiNH are disposed. When it is assumed that the semiconductor layer 96 has a thickness di = 0.2 µm and a dielectric constant ε i = 12, and the insulating layer 97 has a thickness d SiNH = 0.3 µm and a dielectric constant ε SiNH = 6.6, the capacitance C cross for an intersection is calculated to be 5.7 x 10⁻¹⁴ F from the following equation (1): C cross = ε₀S ε i /d i ·ε SiNH /d SiNH ε i /d i + ε SiNH /d SiNH wherein S is the area of an intersection (=20 µm x 20 µm) and ε₀ is the dielectric constant of vacuum (8.85 x 10⁻⁴). As for the parasitic capacitances C gs and C gd of a TFT 93 which are to be considered when it is turned off, the laminar structures of these parts are the same as that of the intersection shown in Figure 10B and only the area is different, so that C gs = C gd = {C cross /(20µx20µ)} x 3µ x 3000µ = 1.28 pF The channel capacitance C channel which is to be considered when a TFT is turned on, can be calculated by assuming that the semiconductor layer is regarded as a conductor as follows: C channel = ε₀ x (6µ+8µ) x 3000µ x ε SiNH /d SiNH = 8.18 pH As for the gate line resistance Rg in the matrix, a gate line composed of a laminate of 0.1 µm-thick Al on 0.1 µm-thick Cr has a resistance similar to that of the Al layer alone as Al has a larger conductivity than Cr by two figures, so that the gate line with a 20 µm-width has a resistance per unit length of about 200 Ω/cm. Based on the above data, the total values for the matrix arrangement shown in Figure 16 for a 7-inch panel, wherein 1920 signals lines are divided into 8 blocks each including 240 source lines, 240 TFTs, and a gate line length of 1.68 cm, may be calculated as follows for the last TFT (i.e., the rightmost TFT inFigure 16) in an i-th block (i = 1 to 8): (ΣC cross ) i 5.7x10⁻¹⁴F x 240 x i = 13.5 x i pF; (ΣR) i = 200 x 1.63 x i = 336 x i pF. As a result, the time constants for gate pulse delay when a TFT is turned off (τ off ) and turned on (τ on ) are as follows with respect the last TFT in an i-th block: As a result, with respect to the first four blocks, the results shown in the following Table 1 are obtained. Now, in a case where a charging time allotted to a multiplexing TFT matrix is 5.8 µsec as described above, the effective charge time is decreased by τ off and τ on as follows; Effective charge time = 5.8 µsec - τ off - τ on . This is shown in Figure 13. As the effective charge efficiency η eff for the above system can be calculated by: η eff = 1 - 0.4 exp (-1.5 x 10⁶·t), the changes in effective charge efficiency and output voltage due to decrease in effective charge time are calculated and shown in the following Table 2. L/W = 8/3000, µ = 0.3, c = 17 pF, Vg = 20 V, Vth = 5 V, V S = 6 V, V s (t=0) = -6 V, d ins = 0.3 µm, ε ins = 6.6. The above Table 2 shows that, in the gate line arrangement shown in Figure 16, the gate pulse delay increases as it goes to a righter block and the decrease in output voltage becomes very substantial already in the fourth block. Figure 6 show a gate line arrangement which has been improved in the above problem. An enlarged partial view of Figure 6 corresponding to Figure 11 is shown in Figure 8. In this case, the output voltage change between the blocks has been essentially removed but the output voltage change between TFTs at both ends in an individual block is not ignorable. In the case of Figure 6, the respective factors concerning the gate pulse delay are calculated with respect to the last TFT (leftmost one in Figure 6) in each block as follows corresponding to the embodiment of Figure 16: ΣC cross = 5.7 x 10⁻¹⁴ x 240 x 2 = 27.4 pF (ΣTFT) off = 2.56 pF x 240 = 615 pF (ΣTFT) on = 8.18 pF x 240 = 1963 pF ΣR = 200 x 1.68 x 1.6 = 538 Ω, wherein the coefficient 1.6 is a shape factor indicating the increase in gate line length with respect to the vertical portion in the embodiment of Figure 6 compared with that of Figure 16. The above values do not change depending on the number of a block concerned. Correspondingly, the delay time constants for the leftmost TFT are as follows: τ off = 0.35 µsec, τ on = 1.07 µsec. These cause a decrease in effective charge time from 5.8 µsec to 4.38 µsec (= 5.8 - 0.35 - 1.07), providing a charge efficiency of 99.3 % (5.958 V). On the other hand, the rightmost TFT in a block in Figure 6 involves capacitances at 240 intersections and a registance in the gate line-source line matrix area and its own C gs , C gd and C channel , so that the factors concerning the delay are as follows: ΣC cross = 5.7 x 10⁻¹⁴ x 240 = 13.7 pF R = 200 x 1.68 x 0.6 = 202 Ω ΣTFT off = 1.28 x 2 = 2.56 pF ΣTFT on = 8.18 pF. Thus, τ off = 3.28 x 10⁻³ µsec, τ on = 4.42 x 10⁻³ µsec. The effective charge time in this case is 5.79 µsec (= 5.8 - 3.28x10⁻³ - 4.42x10⁻³), the charge efficiency is 99.85 % (5.991 V). From the above results, there occurs a gain difference of 0.55 % (33 mV in output voltage). This means that the arrangement in Figure 6 provides a voltage difference of 33 mV between the two TFTs respectively belowing to one and the other of a neighboring pair of blocks as shown in Figure 8. The above difference in output voltage of 33 mV might appear to be small. However, human eyes are sensitive to a difference in luminance at a boundary between neighboring areas (a differential luminance difference) and can recognize a difference of more than 3 %, particularly more than 5 %, in transmittance as a luminance difference at a boundary, which remarkably impairs picture quality. Experimental results show that a voltage change exceeding 0.3 % of a driving voltage can cause a difference in transmittance of 3 - 5 % or more, and in the above embodiment uses a gradation amplitude of ±3 V for video signals, so that the tolerable voltage change is limited to 3.0x0.3 % = 9 mV. As a result, the above difference of 33 mV at the boundary is not tolerable. This leads to a substantial loss of advantages accompanying the simplification of an external circuit for signal lines and decrease in number of communications. Morover, the above difference in output voltage increases as the number of TFTs and source lines included in a block increases corresponding to a desire of increasing the size and fineness of a picture. The present invention provides a display apparatus using a multiplexing active matrix for block division of signal lines capable of providing a good quality of display by solving the above problems without introducing technical difficulty in pattern designing and production process. The present invention also provides a signal supplying or output apparatus suitable for use in such a display apparatus and other apparatus using a multiplicity of parallel signals. In a preferred embodiment according to the present invention, in substantially the same arrangement of active matrix shown in Figure 6, a gate line is led in substantially the middle of the matrix and branched into mutually opposite directions so as to form a letter of "reverse T" and connect TFTs almost equally distributed to the left and right. As a result, the gate pulse delay assumes a minimum at the center TFT and a maximum at TFTs at both ends in a block, but the maximum delay occurs equally at two TFTs at a boundary of two neighboring blocks, so that no difference in charge efficiency or luminance occurs at the boundary. Figure 7 is a plan view of such a preferred embodiment. Referring to Figure 7, a gate line 91 for each block is led in so as to pass almost the center 98 (preferably within one tenth of the number of source lines (i.e., TFTs) from the center) of the block matrix and is branched into a reverse T and intersects with source lines 92 so as to distribute almost the same number (generally in the range of 40 - 60 % of the total) on the left and right sides at respective intersections with the source lines. The gate pulse delay at this time becomes minimum at the center, and maximum at both ends. However, the absolute value of the maximum is reduced to nearly a half (involving 4 intersections and TFTs) compared with that for the leftmost TFT as in an arrangement shown in Figure 8 (corresponding to 8 intersections and TFTs). Moreover, two TFTs at the boundary of blocks i and i+1 equally receives a delay time for 4 intersections and TFTs, so that no difference in charge efficiency (thus ΔV 0) or luminance occurs. Moreover, the above arrangement does not accompanying any increase in difficulty of mask designing or production process, so that the effect of improvement is very remarkable. Figure 14 is a partial plan view showing a more precise layout of a multiplexing TFT matrix for block division in combination with a part of a panel matrix, in which BT denotes a block or multiplexing TFT, PG denotes a panel gate, PS denotes a panel source, and PT denotes a panel or pixel TFT. Referring to Figure 14, a gate line g₈ for an eight block, for example, is introduced along a line passing through the center of the TFT array (BT₁₆₈₀- BT₁₉₂₀) in the block and branched at point "A" to form a reverse T. The layout apparently does not increase may difficulty as compared with an embodiment of Figure 8 wherein the gate line is introduced through the left end (not shown) or the right end ("B"). In this instance, the arrangement of block TFTs may be arbitrary, but an arrangement wherein the source-drain channel of a TFT extends perpendicularly to the input-output lines for data (i.e., data lines (PS) for conveying image data in a case of Figure 14 showing a display picture frame), is desirable in order to increase the arrangement density of the block TFTs. Figures 15A, 15B and 15C are sectional views taken along lines a-a, b-b and c-c, respectively, in Figure 14. The present invention may also be applicable to a display apparatus comprising a passive matrix-type ferroelectric liquid crystal device as disclosed in, e.g., U.S. Patent No. 4,367,924, instead of an active matrix type liquid crystal device using switching elements disposed at respective pixels as described above. More specifically, the signal lines of such a ferroelectric liquid crystal device may be divided (or grouped) into blocks for using a commonly connected less number of source lines in the manner described above. In this instance, a ferroelectric liquid crystal in a chiral smectic phase, particularly C phase, H phase, J phase, K phase or G phase may suitably be used. As described hereinabove, according to the present invention, the number of signal lines requiring connection with an external circuit can be remarkably reduced (a number of signal lines: from 1920 lines to 240 or 248 lines and a signal line density: from 13.5 lines/mm to 1.69 lines/mm (87.5 % decrease) to 1.75 lines/mm (87.0 % decrease) in the above examples). Accordingly, many advantages are attained including simplification of manufacturing, increase in production yield, decrease in number of external signal-processing ICs, etc., which provide economical advantages as well as realization of reduction in scale size and cost of external signal circuits. Further, a delay in a mode of reversal in each horizontal scanning period may be minimized. Further, the above explanation of the present invention has been made with reference to an example using analog image signals, but the present invention may also be applicable to a device or apparatus using signal lines for other types of signals such as digital signals. Further, according to the present invention, an improved signal output or supplying apparatus capable of supplying parallel signals from signal lines divided into plural blocks, with a uniform signal level and without a remarkable difference in signal level at a boundary of blocks, can be provided. By combining the signal supplying apparatus with a display device using parallel signals from the signal supplying apparatus, a display apparatus providing a good quality of display may be provided by preventing a difference in luminance at a boundary between neighboring blocks or display areas without increasing any difficulty in pattern designing or process designing.

Claims: A display apparatus comprising: a plurality of pixels arranged in pluralities of rows and columns; a plurality of first control lines (S(1) to S(M)) each connecting a column of pixels, said first control lines (S(1) to S(M)) being divided into a plurality of blocks; a plurality of second control lines (G(1) to G(M)) each connecting a row of pixels; third control lines (s(1) to s(m)) each branched into a plurality of lead lines so that corresponding ones of said first control lines (S(1) to S(M)) in each of the blocks are commonly connected by a respective one of said third control lines (s(1) to s(m)) through corresponding ones of said plurality of lead lines; a plurality of multiplexing switching elements (6) each corresponding to a respective one of said first control lines (S(1) to S(M)), said switching elements (6) being disposed at each connection between said plurality of lead lines and said first control lines (S(1) to S(M)), and said multiplexing elements (6) being divided into the plurality of blocks; and fourth control lines (g(1) to g(n)) supplying control signals to said multiplexing switching elements (6) and being disposed so that said multiplexing switching elements (6) in each of the blocks are commonly connected by a respective one of said fourth control lines (g(1) to g(n)), said display apparatus being characterized in that said fourth control lines (g(1) to g(n)) are disposed so that a substantially equal number of corresponding lead lines (92) are disposed on each side of said respective one (91) of said fourth control lines (g(1) to g(n)) for each of the plurality of blocks, and when similar control signals are applied to adjacent blocks as supplied by said fourth control lines (g(1) to g(n)), a difference in voltage (Δ V) between corresponding first control lines (S(1) to S(M)) of two multiplexing switching elements (6) for the adjacent blocks disposed at a boundary between a neighboring pair of blocks is at most 50 mV. A display apparatus according to claim 1, characterized in that said difference in voltage between two multiplexing elements (6) is 20 mV or less. A display apparatus according to claim 1, characterized in that each of said plurality of blocks comprises the same number of intersections between the third control line (s(1) to s(m)) commonly connecting to plurality of the multiplexing switching elements (6) in the block and the lead lines each connected to one of the multiplexing switching elements (6). A display apparatus according to claim 1, characterized in that said multiplexing switching element (6) is a thin film transistor. A display apparatus according to claim 1, characterized in that a liquid crystal is disposed at said pixels. A display apparatus according to claim 5, characterized in that said liquid crystal is a ferroelectric liquid crystal. A display apparatus according to claim 5, characterized in that said liquid crystal is a nematic liquid crystal. A display apparatus according to claim 1, characterized in that each of said pixels is provided with a pixel switching element (ANM). A display apparatus according to claim 1, characterized in that said pixel switching element (ANM) comprises a thin film transistor. A display apparatus according to claim 1, characterized in that said fourth control lines (g(1) to g(n)) are disposed so that, when similar control signals are applied to adjacent blocks as supplied by said fourth control lines, a ratio between voltages from any two first control lines (S(1) to S(M)) of said adjacent blocks is within the range of 1±0.10, and a ratio between voltages from two first control lines (S(1) to S(M)) of said adjacent blocks at a boundary between a neighboring pair of blocks is in the range of 1±0.01. A display apparatus according to claim 10, characterized in that said ratio between voltages from any two first control lines (S(1) to S(M)) is within the range of 1±0.05; and said ratio between voltages from two first control lines (S(1) to S(M)) at a boundary between a neighboring pair of blocks is in the range of 1±0.003.

Inventors: INOUE HIROSHI, KANNO HIDEO, MIZUTOME ATSUSHI, OSADA YOSHIYUKI, SAKAMOTO EIJI, INOUE, HIROSHI, KANNO, HIDEO, MIZUTOME, ATSUSHI, OSADA, YOSHIYUKI, SAKAMOTO, EIJI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1987
Main classification: G09G3
IPC codes: G09G3, G02F1