Loosely coupled pipeline processor

Abstract: A central processing unit includes an instruction decoder (1), an operand address computation unit (2), an operand pre-fetch unit (3), a control information buffer (5), an arithmetic unit (4), an instruction fetch unit (6), a chip bus (7), and a bus controller (8). A process relating to the fetch of a memory operand is independent from main pipeline process having an instruction fetching stage, an instruction decoding stage, and an instruction execution stage. As a result, control information (13) in an instruction that the fetch of the memory operand is not required does not pass through the pipeline stage relating to the fetch of the memory operand thereby improving bus band width for memory operand accesses.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to a method and apparatus for processing a microprogram for the execution of a machine language instruction in a computer controlled by a microprogram, and particularly to a central processing unit having loosely coupled pipeline stages. 2. Prior Art One example of conventional pipeline processors is described in "Branch Prediction Strategies and Branch Target Buffer Design" by Jonny K. F. Lee and Alan Jay Smith, on pages 6-22 in COMPUTER; IEEE 1984 (17). A conventional pipeline processor comprises an instruction decoder, an operand address computation unit, an operand pre-fetch unit, and an arithmetic unit, and each unit processes an instruction by a cascade system. In the instruction decoder, an instruction code is decoded and control information for an instruction execution is sent to a following device. In the operand pre-fetch unit, the reading of data is performed in accordance with a computed address sent from the operand address computation unit. Here, when the fetch of an operand is required, such read data and the control information for the instruction execution are sent to the arithmetic unit. When the fetch of an operand is not required, control information for the instruction execution is sent to the arithmetic unit. It is to be noted that the control information is passed through pipeline stages relating to the fetch of the operand even when the fetch of the operand address is not required. As a result, there is a drawback that bus band width is limited by unnecessary passing of the control information. Patent Abstracts of Japan vol. 7, no. 192, (P-218)[1337], 23rd August 1983; & JP-A-58 90 247 (Nippon Denshin Denwa Kosha) discloses a pipeline controlling system of information processor which is capable to skip an address qualified stage and at the same time to start the decoding of subsequent instructions in case of executing an instruction which does not require address qualification. Hereby, a stage A is described which receives only the control information for address computation and the control information for memory access, respectively. However, in such a controlling system the stage A (b) receives all control information similarly, thereby, delaying the instruction execution process. Consequently, the effective band width is limited by unnecessary passing of control information. SUMMARY OF THE INVENTION The present invention has been developed in order to remove the above-described drawback inherent to the conventional pipeline processor. It is, therefore, an object of the present invention to provide a new and useful pipeline processor having loosely coupled pipeline stages. It is another object of the present invention to provide a loosely coupled pipeline processor for processing an instruction without unnecessary transmission of control information for instruction execution through pipeline stages when the fetch of a memory operand is required. It is a further object of the invention to provide a loosely coupled pipeline processor for improving bus band width. According to the present invention this object is accomplished by having an instruction fetch unit for fetching an instruction, an instruction decoder for decoding the instruction fetched by the instruction fetch unit, for generating and outputting first control information relating to execution for the instruction and second control information for a memory access and for generating and outputting third control information for an operand address computation in case where a fetching of an operand in a memory is required for execution of the decoded instruction, an operand address computation unit for receiving the second control information and the third control information, for computing an operand address in accordance with the third control information and for outputting the computed operand address, an operand pre-fetch unit for receiving the computed operand address and the second control information from the operand address computation unit, for fetching a memory operand in accordance with the received operand address and for outputting the fetched memory operand and an operation unit for receiving the first control information in case where a fetching of an operand in a memory is not required for execution of the decoded instruction, for receiving the memory operand from the operand pre-fetch unit and also receiving the first control information in case where a fetching of an operand in a memory is required for execution of the decoded instruction, and for executing an operation in accordance with the first control information in case where a fetching of an operand in a memory is not required for execution of the decoded instruction, and in accordance with the memory operand and the first control information in case where a fetching of an operand in a memory is required, the central processing unit, characterized in that the operand pre-fetch unit queues the fetched memory operand and outputs said memory operand and a first signal representing that the memory operand has been queued therein, the operation unit comprises a control information buffer for queuing and outputting the first control information, and for outputting a second signal for causing a request to output the first control information and an arithmetic unit for receiving the second signal and for outputting a third signal representing that the arithmetic unit requires the first control information queued in the control information buffer, the control information buffer receives the first control information from the instruction decoder, the control information buffer outputs the first control information to the arithmetic unit in response to the third signal and when an operand in the memory is required, and when the first signal is sent to the operation unit, an outputting of the first control signal from the control information buffer is delayed until the first signal is sent to the operation unit. Thus, access to an operand is effected by making independent sections of the pipeline processor operate asynchronously. On the one hand, in case of executing an instruction which does not require memory access, the instruction can be executed by a very high speed as a result of reduction in the number of pipeline stages. On the other hand, in case of executing another instruction which requires memory access, the instruction can be also executed at a very high speed as a result of a parallel performing of processings other than the memory access. Consequently, also the effective band width can be increased. BRIEF DESCRIPTION OF THE DRAWINGS The advantages of the invention will become apparent and obvious to those skilled in the pertinent art upon referring to the following description provided in connection with the accompanying drawings, of which: Fig. 1 is a schematic block diagram useful for understanding an embodiment of the data processing system in a loosely coupled pipeline processor according to the present invention; Fig. 2 is a detailed diagram for the description of a part of the diagram of Fig. 1; Fig. 3 is a timing chart useful for understanding the operation of the system illustrated in Figs. 1 and 2; Fig. 4 is a schematic block diagram useful for understanding a second embodiment of the data processing system in the loosely coupled pipeline processor according to the present invention; Fig. 5 is a detailed diagram for the description of a part of the diagram of Fig. 4; Fig. 6 is a detailed diagram useful for understanding a third embodiment of the data processing system in the loosely coupled pipeline processor according to the present invention; Fig. 7 is a detailed diagram useful for understanding a fourth embodiment of the data processing system in the loosely coupled pipeline processor according to the present invention; Fig. 8 is a schematic block diagram useful for understanding a conventional data processing system in a conventional pipeline processor; and Fig. 9 is a timing chart useful for understanding the operation of the system illustrated in Fig. 8. The same or corresponding elements and parts are designated at like reference numerals throughout the drawings. DETAILED DESCRIPTION OF THE INVENTION Prior to describing the embodiments of the present invention, a conventional method will be discussed first for a better understanding of the present invention. Fig. 8 illustrates one example of a conventional data processing method. A conventional pipeline processor comprises an instruction decoder 101, an operand address computation unit 102, an operand pre-fetch unit 103, an arithmetic unit 104, an instruction fetch unit 106, a chip bus 107, and a bus controller 108. In the instruction decoder 101, an instruction code fetched at the instruction fetch unit 106 is decoded. Then, control information relating to instruction execution is generated at the instruction decoder 101, and is sent to the operand address computation unit 102. When the fetch of an operand in memory is required, control information for an operand address computation and control information for a memory access are also sent to the operand address computation unit 102. Besides, if the writing into the memory is required, control information for an operand address computation is sent to the operand address computation unit 102. In the operand address computation unit 102, a required operand address thereof is computed and is sent to the operand pre-fetch unit 103, and control information for a memory access and the control information relating to the instruction execution are also sent to the operand pre-fetch unit 103. In the operand pre-fetch unit 103, a memory operand is accessed via the bus controller 108 and the chip bus 107, and the reading out of the memory operand is performed in accordance with the operand address sent from the operand address computation unit 102. Then, the read out operand data, the address for the writing into the memory, and the control information relating to the instruction execution are sent to the arithmetic unit 104. In the arithmetic unit 104, an operation is executed in accordance with the read out operand data sent from the operand pre-fetch unit 103 and the control information relating to the instruction execution. If the writing into the memory is required, the result of the operation is written into the memory via the bus controller 108 and the chip bus 107 in accordance with the writing address sent from the operand pre-fetch unit 103. The operation of the conventional pipeline processor having the above-mentioned structure will be described hereinbellow with reference to Fig. 9. Fig. 9 illustrates a timing chart of the operation of the conventional pipeline processor of Fig. 8. In Fig. 9, the number of clock pulses in each unit is assumed as follows: one clock for the instruction decoder 101, one clock (pulse) for the operand address computation unit 102, three clocks for the operand pre-fetch unit 103, and one clock for the arithmetic unit 104. It is also assumed that the executing instruction sequence consists of three instructions, i.e. one instruction in which fetching a memory operand and two instructions in which fetching the same. Namely, instructions (1), (4), and (7) require the fetch of a memory operand, and instructions (2), (3), (5), (6), (8), and (9) do not require the fetch thereof. Moreover, it is assumed that the begining state on the pipeline process is an initialized state, for example, a state just after the execution of a branch instruction. The instruction (1) is decoded in the instruction decoder 101 in the time period of clock t1, and the control information relating to the instruction execution and the control information for the memory access and operand address computation are sent to the operand address computation unit 102. In clock t2, the operand address is computed in the operand address computation unit 102 in accordance with the control information for the memory access and operand address computation. The operand address, the control information relating to the instruction execution, and the control information for the memory access are also sent to the operand pre-fetch unit 103. While clocks t3-t5, the memory operand is read out in the operand pre-fetch unit 103 in accordance with the control information for the address computation and memory access, and the control information for the memory access and the control information relating to the instruction execution are sent to the arithmetic unit 104. In clock t6, the operation is executed in the arithmetic unit 104 in accordance with the control information relating to the instruction execution. The instruction (2) is decoded in the instruction decoder 101 in the clock t2, only control information relating to the execution of the instruction (2) is sent to the operand address computation unit 102 because the instruction (2) does not require the fetch of the memory operand. In the clock t3, although this instruction (2) is passed through the operand address computation unit 102 as a pipeline stage, since there are no control information for the address computation and memory access, the control information relating to the execution of the instruction (2) is sent to the operand pre-fetch unit 103. However, since the execution of the instruction (1) in the operand pre-fetch unit 103 is not completed, the sending of the control information relating to the execution of the instruction (2) is actually delayed until clock t6. In the clock t6, although the instruction (2) is also passed through the operand pre-fetch unit 103 as a pipeline stage, since there is no control information for the operand address computation and memory access, only the control information for the execution of the instruction (2) is sent to the arithmetic unit 104. In clock t7, the operation is executed in the arithmetic unit 104 in accordance with the control information for the execution of the instruction (2). Such pipeline process is continued as shown in Fig. 9. However, the above-mentioned pipeline process brings about the following disadvantage. The transmission of unnecessary information in instructions is required even when an instruction relates to the operation of registers, where the fetch of a memory operand is not required. Therefore, such unnecessary passing of the information brings about a limitation of bus band width used for operand access in a block of instruction that the fetch of a memory operand is required. As will be seen from Fig. 9, assuming that the ratio of the number of instructions in which the fetch of memory operand is required to the number of instructions in which the fetch of the same is not required is 1:2, and that the ratio of an executing time for fetching the same to an excecuting time for non-fetching is 3:1, the using of the bus band. width is limitted to 60%. Fig. 1 illustrates a schematic block diagram showing an embodiment of the data processing system of a loosely coupled pipeline processor according to the present invention. The loosely coupled pipeline processor comprises an instruction decoder 1 for decoding instructions, an operand address computation unit 2 for computing the address of an operand, an operand pre-fetch unit 3 for previously fetching an operand, an arithmetic unit 4 for executing operations, a control information buffer 5, an instruction fetch unit 6 for fetching instructions, a chip bus 7, and a bus controller 8. In the instruction decoder 1, an instruction code accepted at the instruction fetch unit 6 is decoded. Then, control information for an address computation is sent to the operand address computation unit 2, and control information for instruction execution is sent to the control information buffer 5. In the operand address computation unit 2, the address of an operand is computed, and control information for memory access is sent to the operand pre-fetch unit 3. In the operand pre-fetch unit 3, operand data in a memory is accessed via the bus controller 8 and the chip bus 7, and an operand ready signal 9 is sent to the control information buffer 5. In the control information buffer 5, the control information sent from the instruction decoder 1 is queued, and is sent to the arithmetic unit 4 in accordance with a request signal from the arithmetic unit 4. The above is a brief description of the operation of the system of Fig. 1. Fig. 2 is a detailed diagram for the description of a part of the block diagram of Fig. 1. The instruction decoder 1 comprises an instruction register (IR) 10 and a decoder 11. In the instruction decoder 1, an instruction code read out in the instruction fetch unit 6 is stored into the IR 10, and decoded by the decoder 11. When the fetch of a memory operand is required, control information 12 for an address computation and a memory access is sent to the operand address computation unit 2 and control information 13 for instruction execution is sent to the control information buffer 5. The control information 12 comprises information (OAG) for operand address computation and information (ACS) for a memory access. When the fetch of an operand in the memory is not required, only the control information 13 is sent to the control information buffer 5. The control information 13 comprises information (OP) showing the kind of operation, information (SRC) designating a source operand, information (DST) showing a destination operand, and information (MEM) showing whether an operand in the memory is required or not. In the operand address computation unit 2, the address of the operand is computed in accordance with the information OAG in the control information 12, and control information 14 is sent to the operand pre-fetch unit 3. The control information 14 comprises an operand address (OA) and the information ACS. The operand pre-fetch unit 3 comprises an operand reader 20, a data queue portion 15, and a control unit 21. In the operand pre-fetch unit 3, if the fetch of an operand in memory is required, the operand reader 20 outputs a request signal (not shown) to the bus control unit 8. Then, the memory operand is read out in accordance with the operand address OA and the information ACS in the control information 14 sent from the operand address computation unit 2, and such read out memory operand data (OD) is queued in the data queue portion 15. The data OD is sent to the arithmetic unit 4 as an input data for executing an operation. The control unit 21 referres to the status of the data queue portion 15, and outputs the operand ready signal 9 to the control information buffer 5 when at least one operand datum OD exists in the data queue portion 15. The control information buffer 5 comprises a data queue portion 30 for the information OP, SRC, and DST, a data queue portion 31 for the information MEM, a control unit 32 for controlling the sending of the information in the data queue portion 30, and a synchronizing circuit means 33. In the control information buffer 5, the information OP, SRC, and DST in the control information 13 sent from the instruction decoder 1 is queued in the data queue portion 30, and the information MEM in the control information 13 is queued in the data queue portion 31. The control unit 32 outputs a signal 34 to the synchronizing circuit means 33 when the information OP, SRC, and DST, i.e. information 16 is queued in the data queue portion 30, and sends the information 16 to the arithmetic unit 4 when receiving the request signal 50 from the arithmetic unit 4. The synchronizing circuit means 33 generates an enabling signal 17 representing that the information 16 is valid in accordance with the operand ready signal 9, the information MEM sent from the data queue portion 31, and the signal from the control unit 32. Thus, information 16 in the control information 13 is sent to the arithmetic unit 4 in accordance with a request signal 50 fed therefrom. Namely, if the information 16 needs the fetch of memory operand data, it is required that the status of the data queue portion 15 is considered. In other words, whether the operand ready signal 9 is outputted or not is referred by the synchronising circuit means 33. If the operand ready signal 9 is not sent from the operand pre-fetch unit 3, i.e. if there is no read out operand datum in the data queue portion 15, the transmission of the information 16 is delayed. It is to be noted that when the enabling signal 17 is invalid, the arithmetic unit 4 does not send the request signal 50 to the control information buffer 5. More specifically, when the information MEM indicates that an operand in memory has to be fetched, and when the operand ready signal 9 is not sent, the control information 16 is in invalid state. Therefore, the sending of the information 16 is delayed until the operand ready signal 9 is sent to the control information buffer 5. The arithmetic unit 4 comprises an arithmetic logic unit (ALU) 40, a register bank 18 having a plurality of general (purpose) registers, and a control unit 42. In the arithmetic unit 4, the control unit 42 outputs the request signal 50 to the control unit 32 in the control information buffer 5 in accordance with the enabling signal 17 sent from the control information buffer 5. It is to be noted that the transmission of the information 16 can be performed by a handshake control. In this case, the request signal 50 can be outputted before the enabling signal 17 is recieved in the control unit 42. When executing operation in accordance with the information 16 and the enabling signal 17, if the information SRC and the information DST in the information 16 shows a general register number, its data is read out from its general register in the register bank 18, and the operation is performed in accordance with the information OP. Then, the result of the operation is stored in the general register where the information DST shows. If the information SRC or the information DST shows the memory operand, the data OD sent from the operand pre-fetch unit 3 is used as input data of the ALU 40. In addition, if the information DST shows the memory operand, it is performed that the result of its operation is written into the memory via the bus control unit 8. The actual operation of the loosely coupled pipeline processor having the above-mentioned structure of Fig. 1 and Fig. 2 according to the present invention will be described hereinbelow with reference to Fig. 3 showing a timing chart associated with an embodiment of the present invention. In Fig. 3, instructions executed in the instruction decoder 1, the operand address computation unit 2, the operand pre-fetch unit 3, and the arithmetic unit 4, and the resulted queueing status in the data queue portion 30 of the control information buffer 5 are shown by the unit of a clock. It is assumed that the required number of the clock pulses in each unit for pipeline process is as follows: one clock for the instruction decoder 1, one clock for the operand address computation unit 2, three clocks for the operand pre-fetch unit 3, and one clock for the arithmetic unit 4. It is also assumed that executing instruction sequence consists of three instructions, i.e. one instruction that the fetch of a memory operand is required and two instructions that the fetch is not required. Namely, instructions (1), (4), (7), (10), and (13) require the fetch of a memory operand, and instructions (2), (3), (5), (6), (8), (9), (11), (12), (14), and (15) do not require the fetch thereof. Moreover, it is assumed that the begining state of the pipeline process is an initialized state, e.g. a state just after the execution of a branch instruction. The instruction (1) is decoded in the instruction decoder 1 in a clock t1, and control information 12 is sent to the operand address computation unit 2, as well as control information 13 is sent to the control information buffer 5. However, since the operand ready signal 9 is not ready in the control information buffer 5, control information 16 is held in the control information buffer 5. Thus, the transmission of the control information 16 is delayed. In clock t2, an operand address is computed in the operand address computation unit 2 in accordance with the control information 12. While clocks t3-t5, the operand is read out in the operand pre-fetch unit 3, and the operand ready signal 9 is sent to the control information buffer 5. Then, the control information 16 being stored in the data queue portion 30 of the control information buffer 5 is sent to the arithmetic unit 4. In clock t6, the operation is executed in the arithmetic unit 4 in accordance with the control information 16. The instruction (2) is decoded in the instruction decoder 1 during the clock t2, and then only control information 13 according to the instruction (2) is sent to the control information buffer 5 because the instruction (2) does not need the fetch of the memory operand. However, since the sending of the operand ready signal 9 is not completed yet, control information 16 according to the instruction (2) is held in the data queue portion 30. The sending of this control information 16 is delayed until clock t7. In this embodiment, the operand pre-fetch unit 3 acts as a control factor, or a velocity controlling step, and therefore 100% of the bus band width is used for the operand access as shown in Fig. 3. Fig. 4 illustrates the structure of the second embodiment of loosely coupled pipeline processors according to the present invention. In Fig. 5, elements, except for a control information buffer 5A, and an arithmetic unit 4A, designated at the same reference numerals as in Fig. 1 respectively have the same function as those in Fig. 1. The operand ready signal 9 is not sent to the control information buffer 5A but is sent to the arithmetic unit 4A. The control information buffer 5A and the arithmetic unit 4A will be described with reference to Fig. 5. Fig. 5 illustrates a detailed diagram of Fig. 4. In Fig. 5, the control information buffer 5A comprises data queue portions 30 and 31 and control unit 32, and the arithmetic unit 4A comprises ALU 40, register bank 18, synchronizing circuit means 33, and a control unit 42A. Since the arithmetic unit 4A has the synchronizing circuit means 33, the operand ready signal 9 is sent to the arithmetic unit 4A. The control unit 32 sends signal 34 representing that information 16 has been queued in data queue portion 30 to the control unit 42A. When the control unit 42A accepts signal 34 outputted from control unit 32, a signal 19 representing that the signal 34 has been received is outputted to the synchronizing circuit means 33. The synchronizing circuit means 33 outputs the enabling signal 17 to the control unit 42A in accordance with the operand ready signal 9, the information MEM sent from the control information buffer 5A, and the signal 19. Then, the request signal 50 is outputted to the control unit 32 for accepting the information signal 16 from the control information buffer 5A. Thus, an operation is executed at the arithmetic unit 4A. Fig. 6 is a detailed diagram useful for understanding a third embodiment of the data processing system in the loosely coupled pipeline processor according to the present invention. In Fig. 6, the instruction decoder 11 comprises instruction register 10 and a decoder 11A, and a control information buffer 5B comprises data queue portion 30, a decoder 36, synchronizing circuit means 33, and a control unit 32A. The decoder 11A sends only the information 16 to the control information buffer 5B. If the information 16 is queued in the data queue 30, since the decoder 36 can read the information 16A having SRC and DST, the information 16A can be decoded for generating a signal 35 representing that the information SRC and/or DST require the memory operand. Then the signal 35 is sent to the synchronizing circuit means 33, and operates as the information MEM in Fig. 2. The decoder 36 also sends the information 16A to the arithmetic unit 4 when the control unit 32A recieves the request signal 50 from the arithmetic unit 4. At this time, the information 16A may not pass through the decoder 36. Fig. 7 is a detailed diagram useful for understanding a fourth embodiment of the data processing system in the loosely coupled pipeline processor according to the present invention. In Fig. 7, a control information buffer 5C comprises data queue portion 30 and contol unit 32B, and arithmetic unit 4B comprises decoder 36, synchronizing circuit means 33, a control unit 42C, ALU 40, and register bank 18. When the control unit 42B recieves the enabling signal 17, the information 16 is sent to the arithmetic unit 30. At this time, the information 16A may send from the decoder 36 to the register bank. As will be seen from the above description of the present invention, the control information 12 for controlling the operand address computation unit 2 and the operand pre-fetch unit 3 and the control information 13 for controlling the arithmetic unit 4 are separately outputted from the instruction decoder 1. The control information 13 is queued to the control information buffer 5, and the information OP, SRC, and DST are sent to the arithmetic unit 4 in accordance with the request signal 50 from the arithmetic unit 4. It is to be noted that the transmission of the information 16 can be performed by a handshake control. In this case, the request signal 50 can be outputted before the enabling signal 17 is recieved in the control unit of the arithmetic unit. Thus, a process relating to the fetch of an operand is independent as a secondary pipeline stage from the main pipeline stage comprising steps of an instruction fetch, an instruction decoding, and an instruction execution. When the instruction does not contain a process of the fetch of the memory operand, e.g. the instruction execution of an operation between registers, only the main pipeline stage is acted. Therefore, control information (13) in an instruction that the fetch of the memory operand is not required does not pass through the pipeline stage relating to the fetch of the memory operand thereby improving the bus band width. As a result, overhead, required for filling of pipeline processes just after the execution of a branch instruction, is avoidable. Moreover, in these embodiments, since the operand pre-fetch unit 3 has a queueing function, the method of the pipeline process according to the present invention is adaptable even if the ratio of the number of instructions in which the fetch of memory operand is required to the number of instructions in which the fetch of the same is not required is partly changed. From the foregoing, it will be understood that effective pipeline process can be actualized by using a loosely coupled pipeline processor of the present invention. In the above-mentioned embodiments, an address converting unit may be provided to the operand pre-fetch unit 3, the instruction fetch unit 6, or the bus controller 8 when the present invention is applied to a virtual memory technique. Besides, a cache memory may also be provided to the operand pre-fetch unit 3, the instruction fetch unit 6, or the bus controller 8 when a cache memory technique is applied to the present invention. Particularly, if a data cache memory is provided to the operand pre-fetch unit 3, the number of the required clock pulses in the operand pre-fetch unit 3 can considerablly be reduced. In addition, the operand address computation unit 2 and the operand pre-fetch unit 3 may be combined each other as one unit, and each unit may comprise a plurality of pipeline stages.

Claims: A central processing unit having an instruction fetch unit (6) for fetching an instruction, an instruction decoder (1) for decoding the instruction fetched by the instruction fetch unit, for generating and outputting first control information (16; or OP) relating to execution for the instruction and for generating and outputting second control information (ACS) for a memory access and third control information (OAG) far an operand address computation in case where a fetching of an operand in a memory is required for execution of the decoded instruction, an operand address computation unit (2) for receiving the second control information and the third control information, for computing an operand address in accordance with the third control information and for outputting the computed operand address, an operand pre-fetch unit (3) for receiving the computed operand address and the second control information from the operand address computation unit, for fetching a memory operand in accordance with the received operand address and for outputting the fetched memory operand and an operation unit (4 and 5; 4' and 5'; 4 and 5B; 4B and 5C) for receiving the first control information in case where a fetching of an operand in a memory is not required for execution of the decoded instruction, for receiving the memory operand from the operand pre-fetch unit and also receiving the first control information in case where a fetching of an operand in a memory is required for execution of the decoded instruction, and for executing an operation in accordance with the first control information in case where a fetching of an operand in a memory is not required for execution of the decoded instruction, and in accordance with the memory operand and the first control information in case where a fetching of an operand in a memory is required, the central processing unit, characterized in that the operand pre-fetch unit queues the fetched memory operand and outputs said memory operand and a first signal (9) representing that the memory operand has been queued therein, the operation unit comprises a control information buffer (5; 5'; 5B; 5C) for queuing and outputting the first control information, and for outputting a second signal (17 or 34) for causing a request to output the first control information and an arithmetic unit (4; 4'; 4B) for receiving the second signal and for outputting a third signal (50) representing that the arithmetic unit requires the first control information queued in the control information buffer, the control information buffer receives the first control information from the instruction decoder, the control information buffer outputs the first control information to the arithmetic unit in response to the third signal and when an operand in the memory is required, and when the first signal is not sent to the operation unit, an outputting of the first control signal from the control information buffer is delayed until the first signal is sent to the operation unit. The central processing unit as claimed in Claim 1, characterized in that the instruction decoder further generates fourth control information (MEM) indicating whether or not an operand in the memory is required, fifth control information (SRC) designating a source operand and sixth information (DST) representing a destination operand, wherein the first signal is sent to the control information buffer, wherein the control information buffer outputs the second signal, which is a signal (17) representing that the first control information, the fifth control information and the sixth information are valid in accordance with the first signal and the fourth control information. The central processing unit as claimed in Claim 2, characterized in that the operand pre-fetch unit includes: (i) an operand reader (20) for reading the memory operand; (ii) a first storage means (15) for queuing the memory operand to send the memory operand to the arithmetic unit; and (iii) a first control unit (21) for sending the first signal to the control information buffer when the memory operand is queued in the first storage means. The central processing unit as claimed in Claim 2, characterized in that the control information buffer (5) includes: (i) a second storage means (30) for queuing the first control information to send the first control information to the arithmetic unit (4); (ii) a third storage means (31) for queuing and outputting the fourth control information; (iii) a second control unit (32) for outputting a fourth signal (34) indicating that the first control information has been queued in the second storage means, and for receiving the third signal; and (iv) a synchronizing circuit means (33) responsive to the first and fourth signals and the fourth control information from the third storage means for outputting the second signal. The central processing unit as claimed in Claim 2, characterized in that the arithmetic unit (4) includes: (i) an arithmetic logic unit (40) (ii) a register bank (18) having general purpose registers; and (iii) a third control unit (42) for receiving the second signal and for outputting the third signal to the control information buffer. The central processing unit as claimed in Claim 1, characterized in that the second signal is a signal (34) representing that the first control information has been queued in the control information buffer, and wherein the first signal is sent to the arithmetic unit. The central processing unit as claimed in Claim 6, characterized in that the operand pre-fetch unit includes: (i) an operand reader (20) for reading the memory operand; (ii) a first storage means (15) for queuing the memory operand to send the memory operand to the arithmetic unit; and (iii) a first control unit (21) for sending the first signal to the control information buffer when the memory operand is queued in the first storage means. The central processing unit as claimed in Claim 6, characterized in that the control information buffer (5') includes: (i) a second storage means (30) for queuing the first control information to send the first control information to the arithmetic unit (4'); (ii) a third storage means (31) for queuing and outputting the fourth control information; and (iii) a second control unit (32) for outputting the second signal (34) indicating that the first control information has been queued in the second storage means, and for receiving the third signal. The central processing unit as claimed in Claim 6, characterized in that the instruction decoder further generates fourth control information (MEM) indicating whether or not an operand in the memory is required, wherein the control information buffer receives the fourth control information from the instruction decoder, and wherein the arithmetic unit (4') includes: (i) an arithmetic logic unit (40) (ii) a register bank (18) having general purpose registers; and (iii) a third control unit (42') for receiving the second signal, for outputting the third signal to the control information buffer (5'), for outputting a fourth signal (19) representing that the second signal has been received and for receiving a fifth signal (17) representing that the first control information is valid in accordance with the first signal and the fourth control information; and (iv) a synchronizing circuit means (33) responsive to the first and second signals and the fourth control information from the control information buffer for outputting the fifth signal. The central processing unit as claimed in Claim 1, characterized in that the instruction decoder further generates fourth control information (SRC + DST) indicating a source operand and a destination operand, wherein the first signal is sent to the control information buffer (5B), wherein the control information buffer generates a fourth signal (35) by decoding the fourth control information and outputs the second signal, which is the signal (17) representing that the first control information and the fourth control information are valid in accordance with the first signal and the fourth signal (35), and wherein the fourth signal indicates whether or not an operand in the memory is required. The central processing unit as claimed in Claim 10, characterized in that the operand pre-fetch unit includes: (i) an operand reader (20) for reading the memory operand; (ii) a first storage means (15) for queuing the memory operand to send the memory operand to the arithmetic unit; and (iii) a first control unit (21) for sending the first signal to the control information buffer when the memory operand is queued in the first storage means. The central processing unit as claimed in Claim 10, characterized in that the control information buffer (5B) includes: (i) a second storage means (30) for queuing the first control information and the fourth control information to send the first control information and the fourth control information to the arithmetic unit (4); (ii) a second control unit (32A) for outputting a fifth signal (34) indicating that the first control information and the fourth control information have been queued in the second storage means, and for receiving the third signal; (iii) a decoder (36) for decoding the fourth control information thereby outputting the fourth signal (35); and (iv) a synchronizing circuit means (33) responsive to the first, fourth and fifth signals for outputting the second signal. The central processing unit as claimed in Claim 10, characterized in that the arithmetic unit (4) includes: (i) an arithmetic logic unit (40) (ii) a register bank (18) having general purpose registers; and (iii) a third control unit (42) for receiving the second signal and for outputting the third signal to the control information buffer. The central processing unit as claimed in Claim 1, characterized in that the instruction decoder further generates fourth control information (SRC + DST) indicating a source operand and a destination operand, wherein the first signal is sent to the arithmetic unit (4B), wherein the control information buffer (5C) outputs the second signal, which is a signal (34) representing that the first control information and the fourth control information have been queued, and wherein the arithmetic unit generates a fourth signal (35) by decoding the fourth control information and wherein the fourth signal indicates whether or not an operand in the memory is required. The central processing unit as claimed in Claim 14, characterized in that the operand pre-fetch unit includes: (i) an operand reader (20) for reading the memory operand; (ii) a first storage means (15) for queuing the memory operand to send the memory operand to the arithmetic unit; and (iii) a first control unit (21) for sending the first signal to the control information buffer when the memory operand is queued in the first storage means. The central processing unit as claimed in Claim 14, characterized in that the control information buffer (5C) includes: (i) a second storage means (30) for queuing the first control information and the fourth control information to send the first control information and the fourth control information to the arithmetic unit (4B); and (ii) a second control unit (32) for outputting the second signal (34), and for receiving the third signal. The central processing unit as claimed in Claim 14, characterized in that the arithmetic unit (4B) includes: (i) an arithmetic logic unit (40) (ii) a register bank (18) having general purpose registers; (iii) a decoder (36) for decoding the fourth control information thereby outputting the fourth signal (35); (iv) a third control unit (42B) for receiving the second signal, for outputting a fifth signal (19) representing that the second signal has been received and for outputting the third signal to the control information buffer; and (v) a synchronizing circuit means (33) responsive to the first, fourth and fifth signals for outputting a sixth signal (17) representing that the first control information and the fourth control information are valid in accordance with the first signal, the fourth signal and the fifth signal, and wherein the third control unit inputs the sixth signal generated by the synchronizing circuit.

Inventors: DEGUCHI MASASHI, KIYOHARA TOKUZO, DEGUCHI, MASASHI, KIYOHARA, TOKUZO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1987
Main classification: G06F9
IPC codes: G06F9