ADAPTIVE DIGITAL FILTER

Abstract: In an adaptive digital filter, the inputs to the variable-coefficient scalers (26-m, 25-m) of an adaptive digital filter are mutually orthogonal and their mean square values are equal. As a result, the rate of convergence of the variable coefficients of the variable-coefficient scalers is rapid. The adaptive filter is suitable for use echo cancelers.

Description: Field of the invention This invention relates to an adaptive digital filter capable of generating an arbitrary transfer function. In particular, it relates to an adaptive digital filter having a fast rate of convergence, suitable for use in a device such as an echo canceler. Background of the invention Recent rapid progress in digital signal-processing technology has created great interest in adaptive digital filters due to their wide range of applications. Typical of these applications is system identification, which is a process of estimating an unknown system characteristic from input and output data. Means for the identification of an unknown system by use of an adaptive digital filter are shown in schematic form in Fig. 1. These means comprise a signal input terminal 41, an error output terminal 42, an unknown system 43, an adaptive digital filter (referred to hereinafter and in the Figures as ADF) 44, and an adder 45. In the figure, x(k), is the input to the unknown system 43 and the adaptive digital filter 44 at time k, (k) is the output from the unknown system 43 at time k, y(k) is the output from the adaptive digital filter 44 at time k, e(k) is the estimation error at time k, (z) is the transfer function of the unknown system, and H(z) is the transfer function of the adaptive digital filter 44. In the configuration shown, if the evaluation function is J = e(k)² , then when J = 0 the adaptive digital filter 44 is regarded as correctly estimating the characteristic of the unknown system 43. A specific type of device using an adaptive digital filter like the one described above is an echo canceler. Echo cancelers are used, for example, in teleconferencing systems. Fig. 2 is a schematic diagram of a teleconferencing system employing an echo canceler. This system comprises a pair of microphones 51-1 and 51-2, a pair of loudspeakers 52-1 and 52-2, a pair of echo cancelers 53-1 and 53-2, a pair of transmission lines 54-1 and 54-2, and a pair of adaptive digital filters 55-1 and 55-2, and includes a pair of acoustically coupled paths or channels 56-1 and 56-2. In most teleconferencing systems the loudspeaker and microphone shown in Fig. 2 are integrated into a single unit called a voice terminal. This gives rise to an acoustic coupling between the loudspeaker and the microphone: the signal output from the loudspeaker is coupled into the microphone and greatly degrades the quality of the voice transmission. In Fig. 2 there are acoustic coupling paths, labeled 56-1 and 56-2, between the loudspeaker 52-1 and the microphone 51-1, and between the loudspeaker 52-2 and the microphone 51-2, but the echo cancelers 53-1 and 53-2 act to reduce the signal coupled from the loudspeaker into the microphone. Fig. 3 shows the type of adaptive digital filter used in such an echo canceler in the prior art. (See the Proceedings of the 1985 Symposium on Information Systems of the Institute of Electronics and Communication Engineers of Japan, No. 366, pp. 2-107.) The adaptive digital filter in Fig. 3 comprises M basic sections, where M is a positive integer. Each basic section except the M-th comprises a second-order recursive digital filter F1 (having unit delay elements 62-1 and 63-1), a second-order non-recursive digital filter F2, and a first-order non-recursive digital filter F3. The zeros of the second-order non-recursive digital filter F2 are mirror images of the poles of the second-order recursive digital filter with respect to the unit circle. The M-th basic section comprises a second-order recursive digital filter and a first-order non-recursive digital filter. The first outputs (OUT1) of the M basic sections are connected to the inputs of an adder 64, the output of which is the output of the adaptive digital filter. The second outputs (OUT2) of the first through M-1-th basic sections are connected to the inputs of the next higher basic section. The input of the first basic section is the input to the adaptive digital filter. In an adaptive digital filter configured as above, let ø₁(k), ø₁(k-1), ø₂(k), ø₂(k-1), ..., ø M (k), ø M (k-1), be the input signals to the variable-coefficient scalers 60-1, 61-1, 60-2, 61-2, ..., 60-M, 61-M, the variable coefficients of which are p₁, q₁, p₂, q₂...,p M , q M . Then the following relationships hold: Where i = 1,2,..., M; 1 = 1, 2,..., M; and i ≠ ℓ. The overbar denotes the result of an averaging operation at time k. The above equations indicate that the inputs to the variable-coefficient scalers of ADF-i and ADF-1 are orthogonal. Summary of the Invention This invention applies to an adaptive digital filter comprising M basic sections (where M is a positive integer) connected in series, in which the first M-1 basic sections include an input terminal, a first output terminal, and a second output terminal, the M-th basic section includes an input terminal and a first output terminal, the input terminal of the first basic section is the signal input terminal of the adaptive digital filter as a whole, the input terminal of each of the other basic sections is connected to the second output terminal of the immediately preceding basic section, and the output of the adaptive digital filter as a whole is the sum of the signals output from the first output terminals of each of the basic sections. In such an adaptive digital filter, this invention provides that: (a) In each of the M basic sections, the path from the input terminal to the first output terminal comprises three circuits connected in series: a first scaler for multiplying a signal input thereto by a coefficient Q m ; a second-order recursive digital filter; and a first-order nonrecursive digital filter, the input of which is connected to the zero delay output node of the second-order recursive digital filter. (b) In each of the first through the (M-1)-th basic sections, the path from the input terminal to the second output terminal comprises three circuits connected in series: the above first scaler; the above second-order recursive digital filter; and a second-order nonrecursive digital filter. (c) In the m-th basic section (1 ≦ m ≦ M), the first-order nonrecursive digital filter comprises a second scaler for multiplying the input signal u m (k) by a coefficient R m , a first adder for adding the output of the second scaler to the signal u m (k-1), which is the signal U m (k) delayed by one unit of time, a third scaler for multiplying the output of the first adder by a coefficient S m , a first variable-coefficient scaler for multiplying the output û m (k) of the third scaler by a variable coefficient d m (k) to form a first product d m (k)û m (k), a second variable-coefficient scaler for multiplying the signal u m (k) by a variable coefficient c m (k) to form a second product c m (k)u m (k), and a second adder for adding these two products. In an alternative arrangement, the first-order nonrecursive digital filter of the m-th basic section (1 ≦ m ≦ M) comprises a second scaler for multiplying the one-unit time delayed signal u m (k-1) by a coefficient R m , a first adder for adding the output of the second scaler to the input signal u m (k), a third scaler for multiplying the output of the first adder by a coefficient S m , a second variable-coefficient scaler for multiplying the output û m (k) of the third scaler by a variable coefficient c' m (k) to form a first product c' m (k)u m (k), a first variable-coefficient scaler for multiplying the signal u m (k-1) by a variable coefficient d' m (k) to form a second product d' m (k)u m (k-1), and a second adder for adding these two products. (d) The coefficient Q m of the first scaler is selected so that the mean square value of the signal at the point at which the second-order recursive digital filter and the second-order nonrecursive digital filter are connected in series in each basic section is equal to the mean square value of the signals at the corresponding series connection points in the other basic sections. (e) The coefficient R m of the second scaler is selected so that the first one of the signals u m (k) and u m (k-1) and the signal û m (k) are orthogonal. (f) The coefficient S m of the third scaler is selected so that the mean square value of the first one of the signals u m (k) and u m (k-1) and the mean square value of the signal û m (k) are equal. The input signal p₁(k) is fed to the input terminal of the first basic section passes through the first scaler, the second-order recurslve digital filter, and the second-order nonrecursive digital filter to the second output terminal. The output signal p₂(k) from this second output terminal is fed to the input terminal of the second basic section, which acts on it in the same way as in the first basic section and outputs the result at the second output terminal. This process continues through the M-1-th section. The signal p M (k) that is output from the second output terminal of the M-1-th basic section is fed to input terminal of the M-th basic section. The input signal p₁(k) fed to the input terminal of the first basic section also passes through the first scaler, the second-order recursive digital filter, and the first-order nonrecursive digital filter to the first output terminal, generating the output signal y₁(k) Similarly, the input signal p₂(k) fed to the input terminal of the second basic section generates an output signal y₂(k) at the first output terminal of that section. Signals y₃(k),..., y M (k) are generated in the same way at the first output terminals of the other basic sections through the M-th. The signals y₁(k),y2(k),..., y M (k) are added to create the output of the digital filter. Owing to the provision of the first through third scalers in this invention and the selection of their coefficients Q m , R m , and S m as set forth above: 1. The mean square value of the signal at the point at which the second-order recursive digital filter and second-order nonrecursive digital filter are connected in series is equal to the mean square values of the signals at the corresponding series connection points in the other sections; 2. In each section, the inputs to the first and second variable-coefficient scalers are orthogonal; and 3. The mean square values of these inputs are equal. The variable coefficients of the variable coefficient scalers may converge quickly. The invention also provides a section for an adaptive digital filter comprising M basic sections (ADF-1 to ADF-M: where M is a positive integer) connected in series, which section includes an input terminal, and a first output terminal wherein: (a) the path from the input terminal to the first output terminal comprises a first scaler for multiplying a signal input thereto by a coefficient Q m , a second-order recursive digital filter, and a first-order nonrecursive digital filter, which are connected in series, and the input of the first-order nonrecursive digital filter is connected to a zero delay output node of the second-order recursive digital filter: and (b) the first-order nonrecursive digital filter comprises a second scaler for multiplying a first one of the zero-delay input signal u m (k) and the signal u m (k-1), which is the signal U m (k) delayed by one unit of time, by a coefficient R m , a first adder for adding the output of the second scaler to a second one of the signal u m (k) and the signal u m (k-1), a third scaler for multiplying the output of the first adder by a coefficient S m , a variable-coefficient scaler for multiplying the output û m (k) of the third scaler by a variable coefficient (d m (k);c' m (k)) to form a first product, a variable-coefficient scaler for multiplying the first one of the signal u m (k) and the signal u m (k-1) by a variable coefficient (c m (k);d' m (k)) to form a second product, and a second adder for adding together the first and second products: Drawings Fig. 1 is a block diagram showing an arrangement for identifying an unknown system in which the invention may be used; Fig. 2 is a schematic diagram showing a teleconference system using an ADF for echo canceler cancelling the echos due to acoustic coupling between the loudspeaker and the microphone in which the invention may be used, Fig. 3 is a block diagram showing a conventional ADF. Fig. 4A is a block diagram showing the general construction of a first embodiment of the invention. Fig. 4B is a block diagram showing the construction of ADF-m (m ≠ M) in Fig. 4A. Fig. 4C is a block diagram showing the construction of ADF-M in Fig. 4A. Fig. 5A is a block diagram showing the construction of ADF-m(m ≠M) of a second embodiment of the invention. Fig. 5B is a block diagram showing the construction of ADF-M of the second embodiment of the invention. Description of examples of invention First the basic configuration of this embodiment will be explained with reference to Fig. 4A. The adaptive digital filter comprises the blocks within the dashed line 9. The blocks ADF-1, ADF-2,..., ADF-(M-1), ADF-M of the adaptive digital filter 9 are connected in series. At time k, ADF-1 receives at its input terminal 10-1 the signal p₁(k) (which is the same as x(k), the input signal of the adaptive digital filter 9 at the input terminal 1 of this embodiment). The signal p₂(k) is sent at the same time k to the input terminal 10-2 of ADF-2 (which is an output terminal from the point of view of ADF-1, and will be referred to below as its second output terminal). Simultaneously, the signal y₁(k) is sent to the first output terminal 11-1. At time k, ADF-2 receives the signal p₂(k) at its input terminal 10-2, sends the signal p₃(k) to the input terminal 10-3 of ADF-3, and simultaneously sends the signal y₂(k) to its first output terminal 11-2. This process is repeated from ADF-3 through ADF-(M-1). The final section (ADF-M) receives at its input terminal 10-M at time k the signal p M (k) sent from the second output terminal (10-M) of ADF-(M-1), and simultaneously sends the signal y M (k) to its first output terminal 11-M. ADF-M does not have a second output terminal. The adder 8 adds the signals y₁(k), y₂(k),,...,y M-1 (k), y M (k) from the first output terminals 11-1, 11-2,..., 11-(M-1), 11-M, of the sections ADF-1, ADF-2, ..., ADF-(M-1), ADF-M to generate the signal y(k), which is the output of the adaptive digital filter 9 at time k. The adder 7 subtracts this output y(k) from the output (k) of the unknown system 3, generating the signal e(k) at the output terminal 2 in the general configuration of Figure 1. Next the configuration of ADF-m (m ≠ M) will be described with reference to Fig. 4B. ADF-m (m ≠ M) comprises a first scaler 12-m, a second-order recursive digital filter E m -1, a second-order nonrecursive digital filter E m -3, and a first-order nonrecursive digital filter E m -2. The zeros of the second-order nonrecursive digital filter E m -3 and the poles of the second-order recursive digital filter E m -1 are mirror-image at each other in relation to their location. The second-order recursive digital filter E m -1 comprises a pair of adders 13-m and 14-m, a pair of scalers 15-m and 16-m, and a pair of unit delay elements 19m-1 and 19m-2. The second-order nonrecursive digital filter E m -3 comprises the pair of unit delay elements 19m-1 and 19m-2, a pair of scalers 17-m and 18-m, and a pair of adders 20-m and 21-m. The first-order nonrecursive digital filter E m -2 comprises the unit delay element 19m-1, a pair of adders 23-m and 27-m, a second scaler 22-m, a third scaler 24-m, a first variable-coefficient scaler 26-m, and a second variable-coefficient scaler 25-m. The input of the first-order nonrecursive digital filter E m -2 is connected to the 0th-order circuit in the second-order recursive digital filter E m -1 as shown in the drawing. The elements of this circuit configuration are connected as follows. On the path from the input terminal 10-m to the first output terminal 11-m, the first scaler 12-m, the second-order recursive digital filter E m -1, and the first-order nonrecursive digital filter E m -2 are connected in series. On the path from the input terminal 10-m to the second output terminal 10-(m+1), the first scaler 12-m, the second-order recursive digital filter E m -1, and the second-order nonrecursive digital filter E m -3 are connected in series. Next the configuration of ADF-M will be described with reference to Fig. 4C. ADF-M comprises a first scaler 12-M, a second-order recursive digital filter E M -1, and a first-order nonrecursive digital filter E M -2. The second-order recursive digital filter E M -2 comprises a pair of adders 13-M and 14-M, a pair of scalers 15-M and 16-M, and a pair of unit delay elements 19M-1 and 19M-2. The first-order nonrecursive digital filter E M -3 comprises the unit delay element 19M-1, a pair of adders 23-M and 27-M, a second scaler 22-M, a third scaler 24-M, a first variable-coefficient scaler 26-M, and a second variable-coefficient scaler 25-M. The input of the first-order nonrecursive digital filter E M -2 is connected to the 0th-order circuit in the second-order recursive digital filter E M -1 as shown in the drawing. The first scaler 12-M, the second-order recursive digital filter E M -1, and the first-order nonrecursive digital filter E M -2 are connected in series on the path from the input terminal 10-M of ADF-M to its first output terminal 11-M as the drawing indicates. Next the operation of this embodiment will be described. The circuit ADF-m (m ≠ M) in Fig. 4B operates as follows. At time k the input terminal 10-m receives the signal p m (k) sent from ADF-(m-1). (The signal p₁(k) received at the input terminal 10-1 of ADF-1 is the signal x(k) fed to the input terminal 1.) The input signal p m (k) at time k is multiplied by the coefficient Q m in the scaler 12-m to create the signal t m [= Q m p m (k)]. Also at time k, the signal u m (k-1) is multiplied by a m in the scaler 15-m to create the signal a m u m (k-1), the signal u m (k-2) is multiplied by b m in the scaler 16-m to create the signal b m u m (k-2), this signal is inverted to create the signal -b m u m (k-2), and the result is added to a m u m (k) in the adder 14-m to obtain the signal v m (k). The signals v m (k) and t m (k) at time k are added to obtain the signal u m (k), which is fed to the unit delay element 19m-1 and shifted in the time domain by passage through the unit delay elements 19m-1 and 19m-2. The adder 23-m adds the signal u m (k-1) which is input to the unit delay element 19m-2 at time k and the signal R m u m (k) obtained by multiplying the signal u m (k) input to the unit delay element 19m-1 at time k by R m , and the scaler 24-m multiplies the result by S m to create the signal û m (k). This signal is multiplied by d m (k) in the variable-coefficient scaler 26-m, then added in the adder 27-m to the product of the signal u m (k) and the variable coefficient c m (k) to create the signal y m (k), which is sent to the output terminal 11-m. Also at time k, the signal u m (k-1) is multiplied by a m in the scaler 18-m and the product a m u m (k-1) is inverted and added to the signal u m (k-2) in the adder 21-m. The result is added in the adder 20-m to the product of the signal u m (k) and b m generated by the scaler 17-m, and the result p m+1 (k) is fed to the input terminal 10-(m+1) of ADF-(m+1). The circuit ADF-M in Fig. 4C operates as follows. At time k the input terminal 10-M receives the signal p M (k) sent from ADF-(M-1). The input signal p M (k) at time k is multiplied by the coefficient Q M in the scaler 12-M to create the signal t M [=Q M p M (k)]. Also at time k, the signal u M (k-1) is multiplied by a M in the scaler 15-M to create the signal a M u M (k-1), the signal u M (k-2) is multiplied by b M in the scaler 16-M to create the signal b M u M (k-2), this signal is inverted to create the signal -b M u M (k-2), and the result and a M u M (k) are added in the adder 14-M to obtain the signal v M (k). The signals v M (k) and t M (k) at time k are added to obtain the signal u M (k), which is fed to the unit delay element 19M-1 and shifted in the time domain by passage through the unit delay elements 19M-1 and 19M-2. The adder 23-M adds the signal u M (k-1) which is input to the unit delay element 19M-2 at time k and the signal R M u M (k) obtained by multiplying the signal u M (k) input to the unit delay element 19M-1 at time k by R M , and the scaler 24-M multiplies the result by S M to create the signal û M (k). This signal is multiplied by d M (k) in the variable-coefficient scaler 26-M, then added in the adder 27-M to the product of the signal u M (k) and the variable coefficient c M (k) generated by the variable-coefficient scaler 25-M to create the signal y M (k), which is sent to the output terminal 11-M. In the above-described embodiment, the inputs to the variable-coefficient scalers 25-m, 26-m are made to be mutually orthogonal and the mean square values of the input signals are made to be equal, so that the rate of convergence is high. This will be explained in further detail. In the prior art, the inputs to the variable-coefficient scalers in ADF-i and ADF-1 (where i ≠ 1) are mutually orthogonal as shown in equation (1), but the inputs to the variable-coefficient scalers in the same ADF-i (i = 1, 2,..., M) are not orthogonal, as shown in equation (2). The average value of the product of the input signal Ø i (k) of the variable coefficient scaler 60-i and the input signal Ø i (k-1) of the variable-coefficient scaler 61-i in the i-th basic section is: Ø i (k)Ø i (k-1) ≠ 0 (i = 1, 2,..., M) (2) The mean square values Ø₁²(k), Ø₂²(k),..., Ø M ²(k) of the input signals Ø₁(k), Ø₂(k),..., Ø m (k) are: Ø i ²(k) = Ø₁²(k) (i ≠ 1) (3) the mean square values of the signals Ø i (k) in ADF=i (i = 1, 2, ..., M) are unequal, as shown in Equation (3). In this embodiment, in contrast, if the coefficients Q m , R m , and S m of the scalers 12-m, 22-m, and 24-m are selected as described below, the signals input to the variable-coefficient scalers 25-m and 26-m are mutually orthogonal, and their mean square values are equal. [Criteria for Q m ] The coefficients Q m are to be selected so that: [Criteria for R m and S m ] R m (m = 1, 2, ..., M) is to be selected so that the signals u m (k) and û m (k) are orthogonal, and S m is to be selected so that are equal. Specifically, this means that R m must satisfy: With the above selections, the inputs to the variable-coefficient scalers in ADF-m and ADF-n (where m ≠ n) will be mutually orthogonal, the inputs to the pair of variable-coefficient scalers in ADF-m will be mutually orthogonal, and the mean square values of the inputs to all the variable-coefficient scalers will be equal. As a result, the correlation matrix of the variable-coefficient scalers of the adaptive digital filter 9 will be diagonalized, and all of the diagonal elements will be equal. The eigenvalues of this matrix are all the same. Convergence is therefore rapid even when the well-known and easily implemented gradident method (or method of steepest descent, learning identification method, etc.) is used as the method of adaptive control of the variable coefficients. Figs. 5A and 5B show a second embodiment of the invention. The general construction of the second embodiment is identical to that of the first embodiment illustrated in Fig. 4A. The construction of ADF-m(m ≠ M) of the second embodiment is shown in Fig. 5A. The construction of ADF-M of the second embodiment is shown in Fig. 5B. The ADF-m(m ≠ M) shown in Fig. 5A differs from the ADF-m(m ≠ M) shown in Fig. 4B in the following respects: 1. A scaler 22′-m is connected to multiply u m (k-1). 2. An adder 23′-m is connected to add the output of the scaler 22′-m to u m (k). 3. A scaler 24′-m is connected to multiply the output of the adder 23′-m by Sm. 4. A variable-coefficient scale 25′-m is connected to multiply the output of the miltiplier 24′-m by c′ m (k). 5. A variable-coefficient scaler 26′-m, similar to the variable-coefficient scaler 26-m is connected to multiply u m (k-1) by d′ m (k). The ADF-M shown in Fig. 5B has similar modifications with respect to scalers 22′-M, 24′-M, an adder 23′-M, and variable coefficient scalers 25′-M, 26′-M. The operations of the second embodiment is as follows: The circuit ADF-m (m ≠ M) in Fig. 5A operates as follows. At time k the input terminal 10-m receives the signal p m (k) sent from ADF-(m-1). (The signal p₁(k) received at the input terminal 10-1 of ADF-1 is the signal x(k) fed to the input terminal 1.) The input signal p m (k) at time k is multiplied by the coefficient Q m in the scaler 12-m to create the signal t m [= Q m p m (k)]. Also at time k, the signal u m (k-1) is multiplied by a m in the scaler 15-m to create the signal a m u m (k-1), the signal u m (k-2) is multiplied by b m in the scaler 16-m to create the signal b m u m (k-2), this signal is inverted to create the signal -b m u m (k-2), and the result is added to a m u m (k) in the adder 14-m to obtain the signal v m (k). The signals v m (k) and t m (k) at time k are added to obtain the signal u m (k), which is fed to the unit delay element 19m-1 and shifted in the time domain by passage through the unit delay elements 19m-1 and 19m-2. The adder 23′-m adds the signal u m (k) which is input to the unit delay element 19m-1 at time k and the signal R m u m (k-1) obtained by multiplying the signal u m (k-1) input to the unit delay element 19m-2 at time k by R m , and the scaler 24′-m multiplies the result by S m to create the signal û m (k). This signal is multiplied by c′ m (k) in the variable-coefficient scaler 25′-m, then added in the adder 27′-m to the product of the signal u m (k-1) and the variable coefficient d′ m (k) to create the signal y m (k), which is sent to the output terminal 11-m. Also at time k, the signal u m (k-1) is multiplied by a m in the scaler 18-m and the product a m u m (k-1) is inverted and added to the signal u m (k-2) in the adder 21-m. The result is added in the adder 20-m to the product of the signal u m (k) and b m generated by the scaler 17-m, and the result p m+1 (k) is fed to the input terminal 10-(m+1) of ADF-(m+1). The circuit ABF-M in Fig. 5B operates as follows. At time k the input terminal 10-M receives the signal p M (k) sent from ADF-(M-1). The input signal p M (k) at time k is multiplied by the coefficient Q M in the scaler 12-M to create the signal t M (k) [= Q M p M (k)]. Also at time k, the signal u M (k-1) is multiplied by a M in the scaler 15-M to create the signal a M u M (k-1), the signal u M (k-2) is multiplied by b M in the scaler 16-M to create the signal b M u M (k-2), this signal is inverted to create the signal -b M u M (k-2), and the result and a M u M (k) are added in the adder 14-M to obtain the signal v M (k). The signals v M (k) and t M (k) at time k are added to obtain the signal u M (k), which is fed to the unit delay element 19M-1 and shifted in the time domain by passage through the unit delay elements 19M-1 and 19M-2. The adder 23′-M adds the signal u M (k) which is input to the unit delay element 19M-2 at time k and the signal R M u M (k-1) obtained by multiplying the signal u M (k-1) input to the unit delay element 19M-2 at time k by R M , and the scaler 24′-M multiplies the result by S M to create the signal û M (k). This signal is multiplied by c′ M (k) in the variable-coefficient scaler 25′-M, then added in the adder 27-M to the product of the signal u M (k-1) and the variable coefficient d′ M (k) generated by the variable-coefficient scaler 26′-M to create the signal y M (k), which is sent to the output terminal 11-M. The coefficients Q m , R m and S m can be selected in a manner similar to that descibed in connection with the first embodiment, so as to make the signals input to the variable-coefficient scalers 25′-m and 26′-m mutually orthogonal, and to make their mean square values equal. Thus similar results are obtained from the constructions of the second embodiment shown in Figs. 5A and 5B. As described above, in this invention the inputs to the variable-coefficient scalers of an adaptive digital filter are mutually orthogonal and their mean square values are equal. As a result, the rate of convergence of the variable coefficients of the variable-coefficient scalers is rapid. This invention is suitable for use in devices such as echo cancelers.

Claims: An adaptive digital filter comprising M basic sections (ADF-1 to ADF-M: where M is a positive integer) connected in series, in which the first M-1 basic sections (ADF-1 to ADF-(M-1)) include an input terminal (10-m), a first output terminal (11-m), and a second output terminal (10-(m+1)), the M-th basic section includes an input terminal (10-M) and a first output terminal (11-M), the input terminal (10-1) of the first basic section (ADF-1) is the signal input terminal of the adaptive digital filter as a whole, the input terminal (10-m) of each of the other basic sections (ADF-2 to ADF-M) is connected to the second output terminal of the immediately preceding basic section (ADF-(m-1)), and the output of the adaptive digital filter as a whole is the sum of the signals output from the first output terminals (11-m) of each of the basic sections, wherein ; (a) in each of the M basic sections (ADF-m), the path from the input terminal (10-m) to the first output terminal (11-m) comprises a first scaler (12-m) for multiplying a signal input thereto by a coefficient Qn, a second-order recursive digital filter (E m -1) and a first-order nonrecursive digital filter (E m -2) which are connected in series, and the input of the first-order nonrecursive digital filter (E m -2) is connected to a zero delay output node (u m (k) of the second-order recursive digital filter (E m -1); (b) in each of the first through the M-1-th basic sections (ADF-m), the path from the input terminal (10-m) to the second output terminal (10-(M+1)) comprises the above first scaler (12-m), the above second-order recursive digital filter (E m -1), and a second-order nonrecursive digital filter (E m -3) which are connected in series; (c) in the m-th basic section (1 ≦ m ≦ M), the first-order nonrecursive digital filter (E m -2) comprises a second sealer (22-m; 22'-m) for multiplying a first one of the zero-delay input signal u m (k) and the signal u m (k-1), which is the signal U m (k) delayed by one unit of time, by a coefficient R m , a first adder (23-m; 23'-m) for adding the output of the second scaler (22-m; 22'-m) to a second one of the signal u m (k) and the signal u m (k-1), a third scaler (24-m; 24'-m) for multiplying the output of the first adder (23-m; 23'-m) by a coefficient S m , a variable-coefficient scaler (26-m; 25'-m) for multiplying the output û m (k) of the third scaler (24-m; 24'-m) by a variable coefficient (d m (k);c' m (k)) to form a first product, a variable-coefficient scaler (25-m; 26'-m) for multiplying the first one of the signal u m (k) and the signal u m (k-1) by a variable coefficient (c m (k);d' m (k)) to form a second product, and a second adder (27-m) for adding together the first and second products; (d) the coefficient Q m of the first scaler (12-m) is selected so that the mean square value of the signal at the point at which the second-order recursive digital filter (E m -1) and the second-order nonrecursive digital filter (E m -3) are connected in series in each basic section is equal to the mean square value of the signals at the corresponding series connection points in the other basic sections; (e) the coefficient R m of the second scaler (22-m; 22'-m) is selected so that the first one of the signals u m (k) and u m (k-1) and the signal û m (k) are orthogonal; and (f) the coefficient S m of the third scaler (24-m; 24'-m) is selected so that the mean square value of the first one of the signals u m (k) and u m (k-1) and the mean square value of the signal û m (k) are equal. An adaptive digital filter according to claim 1 wherein in the m-th basic section (1<m<M), the first-order nonrecursive digital filter (E m -2) comprises a second scaler (22-m) for multiplying the input signal u m (k) by a coefficient R m , a first adder (23-m) for adding the output of the second scaler (22-m) to the signal u m (k-1), which is the signal U m (k) delayed by one unit of time, a third scaler (24-m) for multiplying the output of the first adder (23-m) by a coefficient S m , a variable-coefficient scaler (26-m) for multiplying the output û m (k) of the third scaler (24-m) by a variable coefficient d m (k) to form a first product d m (k)û m (k), a variable-coefficient scaler (25-m) for multiplying the signal u m (k) by a variable coefficient c m (k) to form a second product c m (k)u m (k), and a second adder (27-m) for adding together the first and second products d m (k)U m (k), C m (k)U m (k). An adaptive digital filter according to claim 1, wherein in the m-th basic section (1 < m < M), the first-order nonrecursive digital filter (E m -2) comprises a second scaler (22'-m) for multiplying the signal u m (k-1), which is the signal U m (k) delayed by one unit of time, by a coefficient R m , a first adder (23'-m) for adding the output of the second scaler (22'-m) to the input signal u m (k), a third scaler (24'-m) for multiplying the output of the first adder (23'-m) by a coefficient S m , a variable-coefficient scaler (25'-m) for multiplying the output û m (k) of the third scaler (24'-m) by a variable coefficient c' m (k) to form a first product c' m (k)u m (k), a variable-coefficient scaler (26'-m) for multiplying the signal u m (k-1) by a variable coefficient d' m (k) to form a second product d' m (k)u m (k-1) and a second adder (27'-m) for adding together the first and second products c' m (k)U m (k), d' m (k)U m (k-1). A section (ADF-M) for an adaptive digital filter comprising M basic sections (ADF-1 to ADF-M: where M is a positive integer) connected in series, which section (ADF-M) includes an input terminal (10-m), and a first output terminal (11-m) wherein: (a) the path from the input terminal (10-m) to the first output terminal (11-m) comprises a first scaler (12-m) for multiplying a signal input thereto by a coefficient Q m , a second-order recursive digital filter (E m -1), and a first-order nonrecursive digital filter (E m -2) which are connected in series, and the input of the first-order nonrecursive digital filter (E m -2) is connected to a zero delay output node (u m (k) of the second-order recursive digital filter (E m -1); and (b) the first-order nonrecursive digital filter (E m -2) comprises a second scaler (22-m; 22'-m) for multiplying a first one of the zero-delay input signal u m (k) and the signal u m (k-1), which is the signal U m (k) delayed by one unit of time, by a coefficient R m , a first adder (23-m; 23'-m) for adding the output of the second scaler (22-m; 22'-m) to a second one of the signal u m (k) and the signal u m (k-1), a third scaler (24-m; 24'-m) for multiplying the output of the first adder (23-m; 23'-m) by a coefficient S m , a variable-coefficient scaler (26-m; 25'-m) for multiplying the output û m (k) of the third scaler (24-m; 24'-m) by a variable coefficient (d m (k);c' m (k)) to form a first product, a variable-coefficient scaler (25-m; 26'-m) for multiplying the first one of the signal u m (k) and the signal u m (k-1) by a variable coefficient (c m (k);d' m (k)) to form a second product, and a second adder (27-m) for adding together the first and second products. A section (ADF-m) according to claim 4, further comprising a second output terminal (10-(m+1)) wherein the path from the input terminal (10-m) to the second output terminal (10-(m+1)) comprises the first scaler (12-m), the second-order recursive digital filter (Em-1), and a second-order nonrecursive digital filter (Em-3), which are connected in series, wherein: (a) the coefficient Rm of the second scaler (22-m; 22'-m) is selected so that the first one of the signals u m (k) and u m (k-1) and the signal Ûm(k) are orthogonal; and (b) the coefficient Sm of the third scaler (24-m; 24'-m) is selected so that the mean square value of the first one of the signals u m (k) and u m (k-1) and the mean square value of the signal Ûm(k) are equal. A section (ADF-m) according to claim 4 or claim 5 wherein in the m-th basic section (1<m<M), the first-order nonrecursive digital filter (E m -2) comprises a second scaler (22-m) for multiplying the input signal u m (k) by a coefficient R m , a first adder (23-m) for adding the output of the second scaler (22-m) to the signal u m (k-1), which is the signal Um(k) delayed by one unit of time, a third scaler (24-m) for multiplying the output of the first adder (23-m) by a coefficient S m , a variable-coefficient scaler (26-m) for multiplying the output û m (k) of the third scaler (24-m) by a variable coefficient d m (k) to form a first product d m (k)u m (k), a variable-coefficient scaler (25-m) for multiplying the signal u m (k) by a variable coefficient c m (k) to form product c m (k)u m (k) and, a second adder (27-m) for adding together the first and second products d m (k)Û m (k), C m (k)U m (k). A section according to claim 4 or claim 5 wherein in the m-th basic section (1 < m < M), the first-order nonrecursive digital filter (E m -2) comprises a second scaler (22'-m) for multiplying the signal u m (k-1), which is the signal Um(k) delayed by one unit of time, by a coefficient R m , a first adder (23'-m) for adding the output of the second scaler (22'-m) to the input signal u m (k), a third scaler (24'-m) for multiplying the output of the first adder (23'-m) by a coefficient S m , a variable-coefficient scaler (25'-m) for multiplying the output û m (k) of the third scaler (24'-m) by a variable coefficient c' m (k) to form a first product c' m (k)u m (k), a variable-coefficient scaler (26'-m) for multiplying the signal u m (k-1) by a variable coefficient d' m (k) to form a second product d' m (k)u m (k-1), and a second adder (27'-m) for adding together the first and second products c' m (k)U m (k), d' m (k)U m (k-1).

Inventors: ITOH, YOSHIO OKI ELECTRIC INDUSTRY CO LTD., KOBAYASHI MASAKI OKI ELECTRIC INDUSTRY CO LTD.
Applicants: OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1987
Main classification: H03H21
IPC codes: H03H21, H04B3