Data modulation and demodulation system for magnetic recording system

Abstract: A system for modulating and demodulating write data and read data in a magnetic recording system in accordance with a (1,7) RLL method. The modulating and demodulating system includes a first clock pulse generating circuit (1') receiving a reference signal from a recording medium and generating a first clock pulse (CLK SYS , SCK CD ) having a first frequency equal to a data write frequency in accordance with a phase of the reference signal; a second clock pulse generating circuit (2', 12) receiving the first clock pulse and generating a second clock pulse (SCK BD ) having a second frequency, the second frequency being two-thirds of the first frequency; and a unit (13) for encoding data to be written in accordance with a (1,7) encoding and decoding other data to be read in accordance with a (1,7) decoding, in response to the first and second clock pulses.

Description: The present invention relates to a data modulation and demodulation system for use in a magnetic recording system. More particularly, it relates to a run length limited (RLL) type data modulation and demodulation system for a magnetic recording system. In a magnetic recording system, such as a magnetic disc system, write data is modulated under synchronization with a system clock signal and the modulated data is stored in a magnetic disc. Conversely, the modulated and stored data is read and demodulated to restore original data used outside of the magnetic disc system. A data modulation and demodulation system is employed to achieve the above data encoding and decoding. A variety of modulation methods have been proposed for increasing the recorded density of data on magnetic media such as a magnetic disc. Recently, a modulation method, known as "variable length constant rate coding" and using a run length limited (RLL) format, has been applied to the magnetic recording system. The variable length constant rate coding is carried out various ways, such as a coding of a (1,7) or 1/7 format with a rate of 2/3, hereinafter 1/7 coding, a coding of (2,7) or 2/7 format with a rate of 1/2, hereinafter 2/7 coding, and a coding of (1/8) or a 1/8 format. The 1/7 coding converts a data with a rate of 2/3: two bits to three bits, and inserts a zero ("0") bit(s), up to seven zero bits, between consecutive one ("1") bits data. The 2/7 coding converts a data with a rate of 1/2: one bit to two bits, and inserts at least two series zero ("0") bits, up to seven zero bits, between consecutive one ("1") bit data. Comparing 1/7 coding with 2/7 coding, the 1/7 coding does not require a high-speed operable circuit and has a wide data detection window, but has a disadvantage of a low recording density. Conversely, the 2/7 coding achieves a high recording density, but requires a high-speed operation circuit. US-A-4 488 142 discloses a [1,7] format encoding and decoding with a rate of 2/3. Embodiments of the present invention also use [1,7] format encoding and decoding with a rate of 2/3, i.e. 1/7 coding. However, U.S. patent 4,488,142 does not disclose a data modulation and demodulation system in which 1/7 coding is applied. US-A-4 503 420 discloses a system according to the preamble of accompanying claim 1. US-A-4 348 640 discloses a digital circuit in which a divide by one and one-half circuit clocks a divide by two flip-flop resulting in a symmetrical divide by three output. US-A-3 996 613 discloses a data magnetic recording and reproducing system in which when recording data, a clock pulse signal recorded on a clock track of a magnetic medium is used as a reference signal. EP-A-0 090 047 discloses an encoding and decoding system for binary data employing a 1/3 frequency divider and an AND gate for producing a reading clock signal having a period of 2/3 of an original clock signal. According to the present invention, there is provided a system for modulating and demodulating data written into and read from a magnetic recording medium in accordance with a [1,7] run length limited method, comprising:- a first clock pulse generating circuit generating a first clock pulse having a first frequency, comprising a variable frequency oscillator arranged to receive a reference signal and to generate said first clock pulse in accordance with the phase of the reference signal; and a second clock pulse generating circuit arranged to receive said first clock pulse from said first clock pulse generating circuit, for generating a second clock pulse having a second frequency, said second frequency being two-thirds of a data write frequency; and encoding means for encoding data to be written in accordance with a [1,7] encoding, and decoding means for decoding other data to be read in accordance with a [1,7] decoding, in response to at least said second clock pulse; said first and second clock pulse generating circuits being provided in common for said encoding means and said decoding means; characterised in that:- said first frequency is the data write frequency, and said encoding means and said decoding means are responsive to said first clock pulse; in that said first clock pulse generating circuit further comprises switch means receiving a control signal and responsive thereto to switch a source of said reference signal supplied to said variable frequency oscillator between a reference clock and read data, for use in encoding and decoding respectively; and in that said second clock pulse generating circuit comprises a one-third frequency divider receiving said first clock pulse and generating a gate pulse, said gate pulse having a frequency one-third that of said first frequency of said first clock pulse and a timing and duration such as to mask every third pulse of said first clock pulse, an AND gate receiving said first clock pulse and said gate pulse, a delay circuit delaying a signal output from said AND gate by a time between a one cycle time and a one-and-a-half cycle time of said first clock pulse, and an OR gate receiving said signal output from said AND gate and a delayed signal from said delay circuit and outputting said second clock pulse. Thus, embodiments of the present invention can provide a data modulation and demodulation system to which a 1/7 coding is applied, and which is useful in a magnetic recording system. The system may be operable at low speed and can have a simple circuit construction. Reference will now be made, by way of example, to the accompanying drawings, in which:- Fig. 1 is a circuit diagram of a first data modulation system, not in accordance with the present invention but useful for explaining the principles thereof; Fig. 2 is a circuit diagram of a variable frequency oscillator shown in Fig. 1; Fig. 3 is a circuit diagram of a 1/3 frequency divider shown in Fig. 1; Figs. 4a to 4c are views of wave forms of signals in Fig. 3; Fig. 5 is a circuit diagram of a 1/2 frequency divider shown in Fig. 1; Fig. 6 is a circuit diagram of an encoding and decoding unit shown in Fig. 1; Fig. 7 is a circuit diagram of an encoding and decoding circuit shown in Fig. 6 when that circuit is operated as an encoder; Fig. 8 is a circuit diagram of the encoding and decoding circuit shown in Fig. 6 when that circuit is operated as a decoder; Fig. 9 is a circuit diagram of a data modulation and demodulation system embodying the present invention; Fig. 10 is a circuit diagram of one version of a two-pulse generator used in the system of Fig. 9; Figs. 11a to 11c are views of wave forms of signals in Fig. 10; Figs. 12a to 12j are timing charts illustrating the write operation of the system shown in Fig. 9 when the circuit shown in Fig. 10 is applied thereto; Figs. 13a to 13j are timing charts illustrating the read operation of the system shown in Fig. 9 when the circuit shown in Fig. 10 is applied thereto; Fig. 14 is a circuit diagram of another version of the two-pulse generator used in the system shown in Fig. 9; Figs. 15a to 15c are views of wave forms of signals in Fig. 14; Figs. 16a to 16j are timing charts illustrating the write operation of the system shown in Fig. 9 when the circuit shown in Fig. 14 is applied thereto; and Figs. 17a to 17j are timing charts illustrating the read operation of the system shown in Fig. 9 when the circuit shown in Fig. 14 is applied thereto. Referring to Fig. 1, a first data modulation and demodulation system (not in accordance with the invention) will be described with a view to explaining the principles of the present invention. In Fig. 1, the data modulation and demodulation system includes a switch 8, a variable frequency oscillator (VFO) 1, a 1/3 frequency divider 2, a half (1/2) frequency divider 3, an AND gate 7, a bit register 4, a code register 5, and an encoding and decoding circuit 6. Since a data read is carried out under the 1/7 decoding, the bit register 4 has two bits. On the other hand, as a data write is carried out under the 1/7 encoding, the code register 5 has three bits. The encoding and decoding circuit 6 is used for the 1/7 encoding and the 1/7 decoding. The 1/3 frequency divider 2 and the 1/2 frequency divider 3 are used for a two bit to three bit conversion (encoding) when a data read operation is carried out, and a three bit to two bit conversion (decoding) when a data write operation is carried out. The switch 8 receives read data RD-DATA and a servo clock SERVO-CK and outputs the read data RD-DATA to the VFO 1 when the data read operation is carried out, or outputs the servo clock SERVO-CK when a data write operation is carried out. The VFO 1 receives the read data RD-DATA or the servo clock SERVO-CK as an input signal S IN and outputs a system clock CLK SYS having a stable frequency. The VFO 1 is realized by a phase-locked loop (PLL) circuit as shown in Fig. 2. The VFO 1 includes a phase comparator 111, a low pass filter 112, and a voltage controlled oscillator (VCO) 113. The VFO 1 also may include a 1/N frequency divider 114. The VFO 1 generates the system clock CLK SYS on the basis of the phase of the input signal S IN . Figure 3 shows a circuit diagram of the 1/3 frequency divider 2. The 1/3 frequency divider 2 includes two J-K flip-flop (FF)s 21 and 22. The 1/3 frequency divider 2 outputs a bit data shift clock SCK BD , as shown in Fig. 4b, having a frequency that is one-third of the frequency of the system clock SLK SYS as shown in Fig. 4a. Figure 5 shows a circuit diagram of the 1/2 frequency divider 31. The 1/2 frequency divider 3 includes a D-FF 31. The 1/2 frequency divider 3 outputs a code data shift clock SCK CD having a frequency that is a half of that of the system clock SLK SYS . The AND gate 7 receives the bit data shift clock SCK BD from the 1/3 frequency divider 2 and the code data shift clock SCK CD from the 1/2 frequency divider 3 and outputs a parallel load signal P-LOAD as shown in Fig. 4c. Figure 6 shows a circuit diagram of an encoding and decoding unit 13 shown in Fig. 3 and consisting of the bit register 4, the code register 5, and the encoding and decoding circuit 6. The bit register 4 includes an NAND gate 41 receiving a read and write control signal R/W-CNT and the parallel load signal P-LOAD and outputting a mode signal S41 indicating a read mode or a write mode in response to the read and write control signal R/W-CNT. The read and write control signal R/W-CNT is a logical one: "1" when a read operation is carried out, but otherwise is a logical zero: "0". The bit register 4 also includes a BIT1 circuit having AND gates 42 and 43, an OR gate 44, and a D-FF 45, and a BIT0 circuit having AND gates 46 and 47, an OR gate 48, and a D-FF 49. The bit data shift clock SCK BD from the 1/3 frequency divider is supplied to clock terminals C of the D-FF's 45 and 49. A BIT WRITE DATA is supplied to a terminal of the AND gate 42 and to the D-FF 45 through the OR gate 44, and a positive (Q) output of the D-FF 45 is supplied to the AND gate 46 and to the D-FF 49. Decoded bit data, which will be described later, can be supplied to the AND gates 43 and 47. Q outputs from the D-FF's 45 and 49 can also be supplied to the encoding and decoding circuit 6. Since the bit register 4 is used for both encoding and decoding, the decoded bit data is read when a data read operation is carried out, and the Q outputs are supplied when a data write operation is carried out. The bit register 4 operates in response to the parallel load signal P-LOAD from the AND gate. The code register 5 includes an inverter 51 and a NAND gate 52. These circuits correspond to the NAND gate 41 and function as a mode selector, except that a polarity of an output there from is an inversion of that of the NAND gate 41. The code register 5 also includes a CODE2 circuit having AND gates 53 and 54, an OR gate 55, and a D-FF 56, a CODE1 circuit having AND gates 57 and 58, an OR gate 59, and a D-FF 60, and a CODE0 circuit having AND gates 61 and 62, an OR gate 63, and a D-FF 64. The code data shift clock SCK CD from the 1/2 frequency divider 3 is supplied to clock terminals C of the D-FF's 56, 60, and 64. A CODE READ DATA is supplied to the D-FF's 56, 60, and 64 through the gates 53 and 55, the gates 57 and 59, and the gates 61 and 63, respectively. Similar to the bit register 4, the code register 5 is also used for both encoding and decoding, and thus encoded bit data from the encoding and decoding circuit 6 can be supplied to the AND gates 54, 58 and 62, and Q outputs of the D-FF's 56, 60 and 64 also can be supplied to the encoding and decoding circuit 6. Figure 7 shows a circuit diagram of the encoding and decoding circuit 6 when operated as a 1/7 encoder upon receipt of the read and write control signal R/W-CNT of "0", indicating a data write operation, and Figure 8 shows a circuit diagram of the encoding and decoding circuit 6 when operated as a 1/7 decoder. In Fig. 7, the encoding and decoding circuit 6 includes an encoding address generation circuit 61 having D-FF's 61a to 61d, a read-only-memory (ROM) 60a, and an encoded output circuit 62 having D-FF's 62a to 62c. The 1/7 coding is shown in Table 1 as an example. DATA CODE 01 X00 10 010 11 X01 0001 X00001 0010 X00000 0011 010001 0000 010000 where X denotes a bit complementary to a preceding bit. Data is supplied from the bit register 4 as BIT0 and BIT1. Another 1/7 coding can be carried out as shown in the Table 2 disclosed in U.S.P. 4,488,142, and is known as an "Encoder State Dependent Table". Current Data Word Next Data Word CODE X1 X2 X3 X4 Z1 Z2 Z3 1 0 0 * 1 0 1 1 0 1 * 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 * 0 0 1 0 0 1 * 0 0 0 0 1 0 * 0 0 1 0 1 1 * 0 0 0 0 0 0 * 0 0 1 0 0 1 * 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 where, * denotes "don't care", and 00 means "not 00" In Table 2, the portion above the dotted line indicates the coding when the last bit Z3 of a previous coded data is zero ("0"), e.g. "100", and the portion below the dotted line indicates the coding when the last bit Z3 is one ("1"), e.g. "101". Symbols X1 to X4 and Z1 to Z3 in Fig. 7 correspond to those in Table 2. To realize the above encoding, the ROM 60a stores a coding table as shown in Table 3. Note that Table 3 shows only a part of that coding table. ADDRESS DATA IN0 IN1 IN2 IN3 IN4 OUT0 OUT1 OUT2 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 1 In Fig. 8, the encoding and decoding circuit 6 includes a decoding address generation circuit 63 having D-FF's 63a to 63h, a ROM 60b, and a decoded output circuit 64 having D-FF's 64a and 64b. The encoding and decoding circuit 6 decodes data in accordance with the following Table 4, which is called a "Decoder State Dependent Table" in U.S.P.4,488,142. Y -1 X 0 X 1 Z2Z1 X10 000 XXX 00 X00 000 XXX 01 XXX 100 XXX 11 XX0 010 00 X 10 XX0 010 00X 11 XXX 101 XXX 10 X00 001 XXX 01 X10 001 XXX 00 XX1 001 XXX 00 XX1 010 00 X 00 XX1 010 00X 01 XX1 000 XXX 01 where, 00 means "not 00", and X denotes "don't care". Symbols Y -1 , X 0 , X 1 , Z2 and Z1 in Table 4 correspond to those in Fig. 8. To realize the above decoding, the ROM 60b stores a decoding table as shown in Table 5. Note, Table 5 shows only a part of that decoding table. ADDRESS DATA IN0 IN1 IN2 IN3 IN4 IN5 IN6 OUT0 OUT1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 To simplify the description and enable an easy understanding thereof, the encoding and decoding circuit 6 is illustrated separately in Figs. 7 and 8. In practice, the encoding and decoding circuit 6 is combined with the circuits shown in Figs. 7 and 8. The ROMs 60a and 60b are formed by a single ROM. To enable a separate encoding and decoding, bi-directional busses are provided between the bit register 4 and the encoding and decoding circuit 6, and between the encoding and decoding circuit 6 and the code register 4. These busses are not shown in the Figures. Conversely, the encoding circuit shown in Fig. 7 and the decoding circuit shown in Fig. 8 can be provided independently. Referring again to Fig. 1, in order to carry out a two bit to three bit coding and a three bit to two bit decoding, the 1/2 frequency divider 3 provides the code data shift clock SCK CD used as a shift clock in the code register 5, i.e., a three bit shift register as shown in Fig. 6, and the 1/3 frequency divider 2 provides the bit data shift clock SCK BD used as a shift clock in the bit register 4, i.e., a two bit shift register as shown in Fig. 6. The code data shift clock SCK CD and the bit data shift clock SCK BD must be maintained in a fine synchronization state with a relationship of 2:3. To realize this condition, the system clock CLK SYS must have a frequency f CLKSYS of the least common multiple of a frequency f SCKCD of the code data shift clock SCK CD and a frequency f SCKBD of the bit data shift clock SCK BD . Note, f SCKCD is defined by a speed of the data write operation, and f SCKBD is defined by a speed of the data read operation. When f SCKCD is 54 MHz and f SCKBD is 36 MHz, the frequency f CLKSYS of the system clock CLK SYS is 108 MHz. The VFO 1 generates a system clock CLK SYS of 108 MHz. The data write operation will be described. The switch 8 outputs the servo clock SERVO-CK to the VFO 1, to generate the system clock CLK SYS . The 1/3 frequency divider 2 outputs the bit data shift clock SCK BD , and the 1/2 frequency divider 3 outputs the code data shift clock SCK CD . The BIT WRITE DATA to be stored is supplied to the bit register 4 in synchronization with the system clock CLK SYS . The data input into the bit register 4 is shifted by the bit data shift clock SCK BD and stored in the D-FF's 45 and 49 shown in Fig. 6 as BIT1 and BIT0. This BIT1 and BIT0 data is loaded into the encoding and decoding circuit 6 in response to the parallel load signal P-LOAD from the AND gate 7, as shown in Fig. 4c. The loaded BIT1 and BIT0 are encoded (modulated) into three bit data in accordance with the 1/7 coding set forth above, and the encoded three bit data is read from the encoding and decoding circuit 6 to the code register 5 in response to the read and write control signal R/W-CNT, and stored in the D-FF's 56, 60 and 64 in the code register 5 as CODE2, CODE1 and CODE0, in response to the code data shift clock SCK CD . This three bit coded data is output as WRITE DATA to the magnetic disc. The output frequency of the WRITE DATA (or modulated data) from the code register 5 is 54 MHz. The data read operation will be described. The switch 8 outputs the read data RD-DATA to the VFO 1, generating the system clock CLK SYS . CODE READ DATA, which is read out in synchronization with the system clock CLK SYS , is supplied to the code register 5, and the data supplied to the code register 5 is stored in the D-FF's 56, 60 and 64 shown in Fig. 6 by the code data shift clock SCK CD from the 1/2 frequency divider 3. The CODE2 to CODE0 in the D-FF's 56, 60 and 64 are loaded into the encoding and decoding circuit 6 in response to the parallel load signal P-LOAD. The loaded three bit data is decoded (demodulated) into two bit data in accordance with the 1/7 decoding set forth above, and the decoded data is supplied to the bit register 4 in response to the read and write control signal R/W-CNT and stored in the D-FF's 45 and 49 in response to the bit data shift clock SCK BD from the 1/3 frequency divider 2. The output frequency of a READ DATA (or modulated data) from the bit register 4 is 36 MHz. In Fig. 1, the VFO 1 requires a source clock of 108 MHz when the read data frequency is 36 MHz and the write data frequency is 54 MHz. The realization of a VFO 1 operable over 100 MHz is difficult from the viewpoints of stability and cost. Referring to Fig. 9, a data modulation and demodulation system embodying the present invention, in which the above defect of the first system is eliminated, will be described. In Fig. 9, the data modulation and demodulation system includes the switch 8, a VFO 1', a 1/3 frequency divider 2', a two pulse generator 12, and the encoding and decoding unit 13 consisting of the bit register 4, the encoding and decoding circuit 6, and the code register 5. The switch 8 and the encoding and decoding unit 13 are substantially the same as those shown in Fig. 1. The circuit construction of the VFO 1', per se, is similar to that shown in Fig. 2, except that the VFO 1' operates at a lower frequency than that of the VFO 1 shown in Fig. 1. The 1/3 frequency divider 2' can be realized by the circuit shown in Fig. 3. In this embodiment, a Q output of the J-K FF 22 of the 1/3 frequency divider is called a bit data shift gate clock SCKG BD , and a Q output of the J-K FF 21 provides the parallel load signal P-LOAD as shown in Fig. 3 and Fig. 4C. The two pulse generator 12 is provided instead of the 1/2 frequency divider 3 shown in Fig. 1. The two pulse generator 12 generates two train pulses used for the bit data shift clock SCK BD on the basis of a bit data shift gate clock SCKG BD from the 1/3 frequency divider 2' and the system clock CLK SYS from the VFO 1'. One version of the two pulse generator 12 used in the system of Fig. 9, is shown in Fig. 10. In Fig. 10, the two pulse generator 12 is an OR gate 121. The timing of the generation of the bit data shift clock SCK BD is shown in Figs. 11a to 11c. The bit data shift clock SCK BD has a frequency which is two-thirds that of a frequency of the system clock CLK SYS . Particular note should be taken of this frequency relationship. Accordingly, the system clock CLK SYS also can be used for the code data shift clock SCK CD supplied to the code register 5. The bit data shift clock SCK BD from the two pulse generator 12 is supplied to the bit register 4. Under the same conditions as those of the Fig. 1 system, when the frequency of the bit data shift clock SCK BD is 36 MHz, the frequency of the code data shift clock SCK CD : the system clock CLK SYS is 54 MHz. Therefore, the VFO 1' is operable at a frequency of 54 MHz, which is a half of that of the VFO 1 shown in Fig. 1. The bit data shift clock SCK BD shown in Fig. 11C is not evenly distributed, but is synchronized with the code data shift clock SCK CD : the system clock CLS SYS at a start of every bit data shift clock SCK BD as marked by small circles in Figs. 11a to 11c. This satisfies the requirement of the synchronization therebetween. The data write operation of a data modulation and demodulation system, in which the circuit shown in Fig. 10 is applied, will be described with reference to Figs. 12a to 12j. Figures 12a to 12c correspond to Figs. 11a to 11c, Figures 12f and 12g show the two bit data BIT1 and BIT0 of the bit register 4, and Figures 12h to 12j show the three bit data CODE2 to CODE0 of the code register 5. The VFO 1' receives the servo clock SERVO-CK from the switch 8 and generates the system clock CLK SYS : the code data shift clock SCK CD of 54 MHz (Fig. 12a). The 1/3 frequency divider 2' outputs the parallel load signal P-LOAD (Fig. 12d), and the two pulse generator 12 outputs the bit data shift clock SCK BD of 36 MHz (Fig. 12c) to the bit register 4. The BIT WRITE DATA supplied to the bit register 4 is shifted by the bit data shift clock SCK BD and stored in the D-FF's 45 and 49 shown in Fig. 6 (Figs. 12e to 12g). The data BIT1 and BIT0 is loaded into the encoding and decoding circuit 6 in response to the parallel load signal P-LOAD, and the encoding and decoding circuit 6 carries out the two bits to three bits encoding in response to the read and write control signal which indicates the data write, and outputs the encoded data to the code register 5. The encoded data is stored in the code register 5 in response to a next parallel load signal P-LOAD and stored in the D-FF's 56, 60, and 64 shown in Fig. 6 by the code data shift clock SCK CD . The stored data CODE2 to CODE0 is output as code write (modulated) data. Figures 13a to 13j are timing charts representing the data read operation. Another version of the two pulse generator 12 used in the system of Fig. 9 is shown in Fig. 14. The two pulse generator includes an AND gate 125, a delay circuit 126, and an OR gate 127. Figures 15a to 15c are timing charts representing the bit data shift clock SCK BD . The delay circuit 126 delays an output signal from the AND gate 126 by a time ΔT between times ΔT 1 and ΔT 2 . Compared with the bit data shift clock SCK BD of the OR gate 121 shown in Fig. 10, the bit data shift clock SCK BD of Fig. 14 is evenly distributed. Figures 16a to 16j are timing charts representing the data write operation of the data modulation and demodulation system in which the circuit shown in Fig. 14 is applied. The operational principle of the data write is similar to that described above with reference to Figs. 12a to 12j. Figures 17a to 17j are timing charts illustrating the data read operation and correspond to Figs. 13a to 13j. Many widely different embodiments of the present invention may be constructed without departing from the scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims: A system for modulating and demodulating data written into and read from a magnetic recording medium in accordance with a [1,7] run length limited method, comprising:- a first clock pulse generating circuit (8, 1') generating a first clock pulse (CLK SYS , SCK CD ) having a first frequency, comprising a variable frequency oscillator (1') arranged to receive a reference signal and to generate said first clock pulse in accordance with the phase of the reference signal; and a second clock pulse generating circuit (2', 12) operatively connected to said first clock pulse generating circuit to receive said first clock pulse (CLK SYS , SCK CD ) for generating a second clock pulse (SCK BD ) having a second frequency, said second frequency being two-thirds of a data write frequency; and encoding means for encoding data to be written in accordance with a [1,7] encoding, and decoding means for decoding other data to be read in accordance with a [1,7] decoding, in response to at least said second clock pulse; said first and second clock pulse generating circuits being provided in common for said encoding means and said decoding means; characterised in that:- said first frequency is the data write frequency, and said encoding means and said decoding means are responsive to said first clock pulse; in that said first clock pulse generating circuit further comprises switch means (8) receiving a control signal (R/W-CNT) and responsive thereto to switch a source of said reference signal supplied to said variable frequency oscillator between a reference clock and read data, for use in encoding and decoding respectively; and in that said second clock pulse generating circuit comprises a one-third frequency divider (2') receiving said first clock pulse (CLK SYS , SCK CD ) and generating a gate pulse (SCKG BD ), said gate pulse having a frequency one-third that of said first frequency of said first clock pulse and a timing and duration such as to mask every third pulse of said first clock pulse (CLK SYS , SCK CD ), an AND gate (125) receiving said first clock pulse and said gate pulse, a delay circuit (126) delaying a signal output from said AND gate by a time (ΔT) between a one cycle time (ΔT 1 ) and a one-and-a-half cycle time (ΔT 2 ) of said first clock pulse, and an OR gate (127) receiving said signal output from said AND gate and a delayed signal from said delay circuit and outputting said second clock pulse. A system according to claim 1, wherein said encoding means and said decoding means are constituted by a common encoding and decoding unit (13) comprising a first shift register (4) having two bits and receiving said second clock pulse and said write data, an encoding and decoding circuit (6) operatively connected to said first shift register, and a second shift register (5), operatively connected to said encoding and decoding circuit, having three bits and receiving said first clock pulse and said read data; said encoding and decoding circuit receiving said write data from said first shift register, encoding said write data in accordance with said [1,7] coding, and outputting said encoded data to said second shift register, when a data write operation is carried out; and said encoding and decoding circuit receiving said read data from said second shift register, decoding said read data in accordance with said [1,7] decoding, and outputting said decoded data to said first shift register, when a data read operation is carried out. A system according to claim 1 or 2, wherein said one-third frequency divider (2') comprises two J-K flip-flops (21, 22), clock terminals thereof receiving said first clock pulse (CLK SYS ), a J terminal of said first flip-flop (21) being connected to a positive output terminal (Q) of said second flip-flop (22), and a J terminal of said second flip-flop being connected to a negative output terminal ( Q ) of said first flip-flop. A system according to any preceding claim, wherein said variable frequency oscillator (1') comprises a phase-locked loop circuit. A system according to any preceding claim, comprising means for reading said reference clock from said magnetic recording medium.

Inventors: HASHIMOTO SHUICHI, HASHIMOTO, SHUICHI, Hashimoto, Shuichi, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1987
Main classification: G11B20
IPC codes: G11B20, H03M5