ELECTROCARDIOGRAPH

Abstract: An electrocardiograph (2) having input terminal means (32, 34, 36, 38, 40), an analog to digital converter (62) for converting electrical signals applied to the input terminal means (32, 34, 36, 38, 40) into digital signals, a memory device (78) for storing the digital signals and display means (6) for graphically displaying the digital signals.

Description: ELECTROCARDIOGRAPH This invention relates to an electrocardiograph. It is the object of the present invention to provide a compact, portable electrocardiograph device which can display heart beat pulses in graphical form, and include analysis of the waveform for standard medically diagnosed heart problems. According to the present invention there is provided an electrocardiograph comprising input terminal means, an analog to digital converter for 0 converting electrical signals on said input terminal means into digital signals, a memory device for storing said digital signals and electronic display means for graphically displaying the digital signals. Preferably said electrocardiograph comprises 5 processor means which is capable of receiving said digital signals and recognising the digital signals as being data representative of electrocardiograph signals. Preferably said processor means upon receiving Z-tt said data, divides the data into waveform data which is representative of a heart beat trace. It is preferred that the display means comprises a liquid crystal display having a screen having from 60 X 150 to 128 X 516 pixels so as to provide good trace resolution of the digital signals, which are representative of electrocardiograph signals applied to the input terminal means. It is further preferred that the device includes a microprocessor for controlling various aspects of the display of information on the LCD display. The features of the display control will be apparent from the detailed description which follows. It will be appreciated by those skilled in the art that the electrocardiograph device could be used for other applications and hence could be regarded as a portable oscilloscope for general application rather than for use as an electrocardiograph. The invention will now be further described with reference to the accompanying drawings, in which: Figure 1 is a schematic view of an embodiment of the invention; Figure 2 shows the underside of the device; Figure 3 shows an end view of the device; Figure 4 shows a typical circuit realisation for an embodiment of the invention; and Figures 5 to 13 show the preferred logic for the device of the invention. The device shown in Figures 1 to 3 comprises a portable electrocardiograph 2 having a housing 4 and an LCD screen 6. The device has control switches 8 which the user can use for controlling the selection of input information, display parameters, and output functions, as will be described hereinafter. In the illustrated embodiment, the underside of the housing 4 is provided with three electrodes 10, 12, 14 which can be placed directly upon the skin of a patient, pre¬ ferably near the patient's heart, and have induced thereon electrocardiograph signals. The device analyses the signals and displays them as a trace 16 on the screen 6. The device may also include a loudspeaker or similar electro-acoustic device 18 for generating an audible signal each time a heart beat pulse is detected, as indicated by the pulses 20, 22 in the trace 16. As best seen in Figure 3, the end of the housing includes a multi-terminal connector 24 for input/output of data and control information to peripheral devices such as printer, transmitters or external computers (not shown) . The device also includes terminals 26 for battery charging and input leads for remote electrodes which can be applied at various points on the patient's body, in accordance with known practices. If external leads are connected to the terminals 26, the electrodes 10, 12, 14 could be automatically isolated. Figure 4 illustrates a circuit realisation for implementing the principles of the invention. The circuit includes a battery 28 which is preferably rechargable. Output from the battery is connected to a power regulating circuit 30 which also produces the necessary supply levels for the remainder of the circuitry. The illustrated circuit includes four input terminals 32, 34, 36, 38 and a common input terminal 40. In the simplest arrangement, the input terminals 32 and 34 would be connected to the elec¬ trodes 10 and 12 mounted on the housing 4. The common terminal 40 would be connected to the central electrode 14 on the housing. This configuration would provide sufficient signal from the patient's skin in order to display a trace 16 on the LCD screen 6. It is possible however to utilize leads and remote electrodes and in the illustrated circuit there is provision for four remote electrodes as well as the common electrode. It will be appreciated of course that extra inputs could be provided if required. The input terminals are connected via input buffers 42 to selector switches 44 to the inputs of a differential amplifier 46. The common terminal 40 is connected to the outputs of the buffers 42 so as to effectively remove DC offsets which would affect all of the input terminals. The switches 44 operate as selector switches so as to determine which of the terminals 32, 34, 36, 38 are connected to the differ¬ ential amplifier 46. The switches 44 are controlled by control signals generated by a microprocessor 50 in response to inputs on the manual switches 8. The control signals are applied via control lines 52. Output from the differential amplifier 46 is applied to the input of a pair of notch filters 54, 56 via a buffer amplifier 58. The filters 54 and 56 have their notches at 50Hz and 60Hz so as to remove induced noise signals at those frequencies from mains supplies. Both filters are provided so that the same equipment can be used in the environment of 50Hz and 60Hz main supplies. Output from the notch filter 56 is -applied to a low pass filter 60 which typically has a cut off frequency of say 100Hz. Output from the filter 60 is applied to an analog to digital converter 62 via a high sensitivity line 64 or via a low sensitivity line 66 which reduces the amplitude by means of a resistive divider. The selection of the high or low sensitivity input to the converter 62 is subject to the control of programmes within the microprocessor 50. The converter 62 preferably comprises an ADC 0844 circuit which has an eight bit parallel output and a sampling rate which is selectable in accordance with programmes stored within the microprocessor 50. Typically, the sampling rate would be 1ms. Output from the converter 62 is input- ted via lines 68 to the microprocessor 50 and to a graphics controller circuit 70 for the LCD screen 6. The microprocessor preferably includes sufficient memory for storage of programmes to control the display parameters and input/output functions associ- ated with the circuit. The microprocessor has exter¬ nal input/output lines 72 which extend to the connec¬ tor 24 shown in Figure 3. The microprocessor has data input/output lines 74 which connect into data ports on the controller circuit 70. The circuit 70 has data input/output lines 76 coupled to a memory RAM 78. The RAM 78 has sufficient memory to store data represent¬ ative of the heart beat trace 16 for display purposes and for holding purposes. The capacity of the RAM 64 is typically 64k. In one circuit realisation, the microprocessor 50 comprises a 6801 circuit, the circuit 70 comprises an E-1330 circuit and the RAM 78 comprises a 6116 circuit. The logic involved in the display programmes for displaying the trace 16 on the screen 6 are shown in Figures 5 to 9. The logic involved in the system programs for displaying the trace 16 on the screen 6 are shown in Figures 5 to 13. Figure 5 shows the overall flow chart which commences at power-on at step 80. After power-on, there is an initialising step 82 in which various parts of the circuits such as the microprocessor 50, memory 78, display controller 70 and input circuits 44 and 62 are initialised to the proper modes of opera¬ tion. The next step 84 presents copyright notice, basic system status information and current setup state for the user for a short time. Information for display at this time could include time base and sensitivity settings, as well as any recorded abnor¬ malities memorised on previous operating sessions. The program would then pass to step 86, which prepares the display for normal operating state, and starts the real-time generating hardware, which creates the regular time interval interrupts on which the measure¬ ment and timing of events rely. The program then passes to step 88, which determines if a one second interval has occurred. If no, then next is step 92, as nothing is required to be done yet. If yes, then step 90 is performed which is a subprogram, to carry out all the system operations required once every second. The logic in step 90 is separately shown in Figure 6. The routine returns back to step 92 which is a check if the display queue is empty. If yes, no new waveform points are ready, so next is step 96. If no, there is at least one point of the sampled input waveform to be displayed, thus step 94 is carried out. Step 94 is a subprogram to prepare and display the waveform, and its logic is shown in Figure 7. The following step is 96 which checks if any operator functions have been requested by depression of one of the input switches 8. If no, the program loops back to step 88 to repeat the above sequence continuously. If yes, the step 98 is carried out. Step 98 is a subprogram to carry out any requested operations from the user and its logic is shown in Figure 8. Figure 6 shows the subprogram which processes operations required only occasionally, such as at one second intervals. The subprogram enters at step 100, from there to step 102, which resets the flag which was used to indicate that this subprogram operation is required, then the heart beat rate is calculated and displayed. This then proceeds to step 104, which analyses the waveform for fundamental deviations from normal. Step 106 checks for if any notable deviations exist. If no, proceeds to step 110 and exits from the subprogram. If yes, step 108 is carried out, which signals the fault on the display and audibly, then memorises the fault for latter recall. Step 110 is then performed exiting from the subprogram. Figure 7 shows the waveform display processing. The subprogram is entered at step 120, which leads to step 122 where the display scrolling flag is tested. If no, step 126 is next. If yes, step 124 is per¬ formed. This clears the flag, then updates the display scroll position and clears the current display column. Step 126 is next carried out which fetches the next display point which was determined to be available at step 92. The data is adjusted for scaling and offset, then converted to a display dot location and placed into the display memory. .The program proceeds to step 128 and exits back to the main program of Figure 5. The flow chart of Figure 8 details the operations carried out for the operator keyboard processing. Step 140 is entered from step 98 of Figure 5. The program proceeds to decision box step 142, where it is determined if a display control function is required. If yes, the program passes to step 144. Step 144 decides if display scaling adjustment is required. If yes, step 146 increases the range if a "+" button (one of the control switches 8) is also depressed and decreases the range if a "-" button (one of the control switches 8) is also pressed. If no, decision step 148 is next, which determines if display offset adjustment is required. If yes, step 150 proceeds to increase the offset if the "+ M button is pressed, or decrease the offset if the "-" ' button is pressed. If no, decision step 152 determines if scan rate adjust- ment is required. If yes, step 154 increases the scan rate if the "+" button is pressed, or decreases the scan rate when the "-" button is pressed. If no, decision step 156 determines if display freeze is requested. If yes, step 158 sets the display hold flag, used by step 332 of Figure 13 to cease recording of more waveform points when a full screen trace is obtained. If no, next step 178 is carried out. All the steps 146, 150, 154, 158 all proceed to step 178 as described below. If no at step 142, then step 160 follows, here a decision is carried out, whether input or output is requested. If yes, step 162 calling subprogram D (shown in Figure 9) is carried out. If no, decision step 164 determines if a storage operation is, required. If yes, subprogram E (shown in Figure 10) is called at step 166. If no, decision step 168 determines if a waveform analysis is requested. If yes, step 170 calls subprogram F (shown in Figure 11) . If no, step 172 decides if a power off request has been made. If no, step 178 is carried out. If yes, step 174 turns off the display logic, enables backup power if any data is to be retained, sets several 5 parameters to be used next time the power is turned on. Then step 176 turns the power circuits 30 off, thus putting the circuits and processor out of opera¬ tion. Each subprogram call at steps 162, 166, 170 returns and proceeds to step 178, like other steps - • - above. This step clears the operator function request flag interrogated in step 96, and proceeds to step 180 which returns to the main program of Figure 5. Figure 9 shows the operations of the subprogram D, which performs input, output requests. Entry is 15 at step 200, which proceeds to step 202, deciding if a waveform print is requested. If yes, step 204 determines from user entry which waveform is requested, and sent graphically to an external printer (not shown) which can be coupled via connector 24. If 20 no, the program proceeds to step 206, which decides if a waveform listing is requested. If yes, step 208 determines which waveform to print and then sends the numerical waveform points to the printer coupled via connector 24. • If no, step 210 determines if a 25 waveform should be loaded into memory from an external device coupled via connector 24. If yes, step 212 determines from user input which waveform is to be loaded, and then reads the waveform numerical.data from the device connected at connector 24. If no, 30 step 214 determines if a waveform analysis is requested. If no, step 222 exits from the subprogram. If yes, step 216 determines which waveform to analyse from user input. Step 218 follows and it calls the waveform analysis subprogram F. On return from the subprogram F, step 220 proceeds to print the results of the analysis on an external printer (not shown) which can be coupled via connector 24. All the steps 204, 208, 212, 220 proceed to step 222 which exits the subprogram D returning to step 162 of Figure 8. Figure 10 shows the flow chart of subprogram E, which processes requests for storage of waveforms. Entry is at step 240 which is followed by step 242 in which the user selects which of several stored waveforms is to be operated on. Next, a decision step 244 determines if a recall of the selected waveform is required. If yes, step 246 places the waveform display on hold, then transfers the saved waveform into the display. If no, decision step 248 determines if a save waveform operation is required. If yes, decision step 250 checks if the selected waveform is protected. If step 250 is yes, then step 254 displays a "protected" message to the user. If step 250 is no, then the content of the current waveform buffer is transferred to the selected storage area, then gener¬ ate a signal demonstrating that the memory has a stored waveform. If step 248 is no, then step 256, decides if the protect state is to be changed. If yes, the selected waveform protect flag is toggled to the opposite condition by step 258. This protects and unprotects alternately. The protected state is indicated. If no, decision step 260 determines if the selected waveform is to be removed. If yes, step 262 determines if the waveform is protected. If step 262 is yes, then step 254 signals the "protected" error. If step 262 is no, then clear the waveform buffer usage flag, effectively forgetting the stored waveform. If step 260 is no, the program passes to step 266. All the steps 246, 254, 258 and 264 proceed to step 266 which exits the subprogram back to step 166 of Figure 8. Figure 11 shows the logic of subprogram F, which analyses the heart beat waveforms. Entry is at step 280, proceeds to step 282. The display function is halted then the buffered waveform is checked against the standard medical conditions. Decision step 284 determines if a medical problem was found in the analysis. If no, then proceed with step 286 which indicates normal heart pattern and waveform statistics or characteristics. If no, then step 288 indicates the one or more possible diagnostic conditions found by the analysis, and permit display of statistics of the waveform. Both steps 286 and 288 proceed to step 290 where it is decided if a reanalysis is required. If yes, return to step 282, or if no, proceed to step 292 which exits back to Figure 5 step 170. Figure 12 shows the flow chart for the real time interupt process, which runs as a separate program from the main program. It is started at a regular interval by a counter in the microprocessor 50. It is responsible for regular timing events. Entry is at step 300, which proceeds to step 302, which triggers a new input reading from the converter circuit 62. Step 304 next determines if a scan interval period has expired. If yes, then step 306 sets a flag for the main program to signal the scan time event and then restarts the scan interval counter. If no, or after step 306, step 308 checks if a one second period has elapsed. If yes, step 310 sets a one second flag and restarts the one second period counter. If no, or after step 310, step 312 scans the control switches 8 and processes the key pressed signals. Step 314 is next carried out which exits the interupt process. Figure 13 shows the flow chart for data conver¬ sion interupt process, which runs as a separate program. It is started when the converter circuit item 62 has completed the operation triggered by the step 302 in Figure 12. Entry is at step 320, which proceeds to step 322 which reads the converted input data from item 62, and places it into the waveform buffer. Step 324 then checks if a scan period has elapsed. If yes, step 326 updates the cursor location and flags that a display scroll is required, step 328 follows checking if the screen end has been reached. If step 324 is no, or step 328 is no,-then step 330 follows. If step 328 is yes then step 332 determines if the display halt flag is set. If step 328 is yes, the program proceeds to step 334. If step 328 is no, step 330 follows. Step 330 puts the new data point into the display queue. Step 334 follows which checks the waveform buffer for a pulse peak. Step 336 determines if a pulse was detected. If yes, step 338 stores the last pulse interval, signals a new pulse period is avail¬ able and give an audible pulse indication on item 18. Step 340 follows. If no, step 340 exits from the interupt process, stopping the interupt program and returning to the main program at the point prior to entry of the data conversion interupt program. It will be.apparent to those skilled in the art that the programs for carrying out the steps in the flow charts can be readily devised. The table which I 0 is set out below contains some of the programming instruction set out in Table 1 below. These instructions are given by way of example only. Further, they are only in respect of some of the basic operating programs of the device. The programs are written in 6801 assembler language. In the preferred embodiment of the invention, the housing 4 is very compact and typically has the following dimensions 185 x 74 x 27 mm. Many modifications will be apparent to those skilled in the art without departing from the spirit and scope of the invention. ;PROCESSOR REGISTER DEFINITIONS 0000 pldir equ 0 0001 p2dir equ 1 0002 pldat equ 2 0003 p2dat equ 3 0004 p3dir equ 4 0005 ρ4dir equ 5 0006 p3dat equ 6 ;CAN NOT USE THIS IN EXPANDED ;MODES 0007 p4dat equ 7 ;MUST BE INPUT ONLY IN EXPANDED ;MODES ;Output addresses 8-15 on output lines ;while expanded modes are used 0008 tcsr equ 8h timer control & status register ; Allocations of bits on TCSR 0080 icf equ 80h Bit 7 = Input capture flag 0040 ocf equ 40h Bit 6 = Output comapre flag 0020 tof equ 20h Bit 5 = Timer overflow interupt 0010 eici equ lOh Bit 4 = Enable input capture interupt 0008 eoci equ 8 Bit 3 = Enable output comapre interupt 0004 etoi equ Bit 2 = Enable timer overflow interupt 0002 iedg equ 2 Bit 1 = Input capture edge 0001 olvl equ 1 Bit 0 = Output level 0009 timer equ 9h Double byte register of running counter 000B ocomp equ Obh double byte timer compare register 000D icomp equ Odh double byte input capture register 000F p3csr equ Ofh Port 3 Control and status register ; Allocation of P3CSR 0080 is3flg equ 80h ; Input strobe flag 0040 is3irq equ 40h ; Input strobe interupt enable 0010 oss equ lOh ; output strobe 3 on read(0) or 7/06447 write(l) 0008 laen equ 8 Latch enable on port 3 input 0010 rmcr equ lOh Rate and Mode control register 0000 ssOO equ 0 Highest baud rate 0001 ssOl equ 1 Lower Baud rate 0002 sslO equ 2 lower again 0003 ssll equ 3 lowest baud rate 0000 ccbiph equ 0 use Bi-Phase/internal clock 0004 ccOl equ 4 use NRZ/internal clock 0 0008 cclO equ 8 use NRZ/internal clock with output OOOC cell equ Och use NRZ/external clock 0011 trcsr equ llh transmit/receive control/status register 15 0001 wu equ 1 Wakeup on idle flag 0002 te equ 2 transmit enable 0004 tie equ 4 transmit interupt enable 0008 re equ 8 receive enable 0010 rie equ lOh receive interupt enable 20 0020 tdre equ 20h transmit data register empty 0040 orfe equ 40h overrun/framing error 0080 rdrf equ 80h Receive register full 0012 rdr equ 12h receive data register 0013 tdr equ 13h transmit register 25 0014 ramcr equ 14h RAM control register I Bits all ations on RAMCR 0080 stbypwr equ 80h Standby power was OK flag 0040 rame eeqquu 4 400hh ;RAM enable (1) or disable (0) ; Ports 15h-lfh are reserved for later 6801 versions 30 ;& derivatives ; Special definitions of port lines from 6801 uC to ; PECGM system 0004 button equ 4 ;mask for port 22 button sensing 0002 adtrig equ 2 ;_nask for port 21 ADC trigger line 35 0001 adeoc equ 1 ;mask for port 20 ADC ; e.nd-of-conversion ;DEFINTIONS OF LCD CONTROLLER ADDRESSES AND FUNCTIONS 4000 glc equ 4000h ;base adiUt-.-a_.-_5- tff %CD controller 16 4000 glcstat equ glc ;(in) status register of LCD ; controller 4001 glcdin equ glc+1 (in) data input from LCD controller 4000 glcdout equ glc (out) data out to VRAM and registers 4001 glccmd equ glc+1 (out) Command register of the LCD controller 0080 erabsy equ 80h mask for GLCSTAT, when high the GLC is busy doing an erase, when 0 ok to write to GLC 0040 xstby equ 40h mask for display suspended, when 0 the cpu may write to display ram without affecting the display. GLC Commands 0040 sysset equ 40h ; Initialise setup of GLC, ; req 8 parameters 0053 sleepin equ 53h ; sleep the GLC 0059 dison equ 59h ; display on, 1 parameter ; setting cursor mode and individual screen sel. 0058 disoff equ 58h display off, 1 parameter as above (no effect) 0044 scroll equ 44h set display start and area, 10 parameters 005D csrform equ 5dh set cursor shape, 2 parameters 004C csrdirr equ 4ch cursor direction, right 004D csrdirl equ 4dh left 004E csrdiru equ 4eh "P 004F csrdird equ 4fh down,...after next char 005B ovlay equ 5bh method of mixing overlayed screens, 1 param 005C cgradr equ 5ch base address of CG ram in display memory,2 parameters 005A hdtscr equ 5ah sets horizontal dot scroll position, 1 param 0046 csrw equ 46h ;set cursor register, 2 parameters 0047 csrr equ 47h ; gets cursor register, reads 2 bytes back 0052 erase equ 52h erase the screen 0042 write equ 42h sets up to write into display storage may have 'n' parameters as cursor advances in the CSDIRx direction, 0043 mread equ 43h gets the display storage at the cursor, may get 'n' bytes, as cursor advances in CSDIRx ; direction. ;Processor RAM allocations. RAM exists from 80h to ;0FFh, with stack allocated at the top of this area. 0080 RAMBASE org 80h 0080 qbase rmb 8 0088 qcount rmb 1 0089 qend rmb 1 pointer to next data byte 008A offsdat rmb 2 offset for center screen 008C minval rmb 1 lowest peak from A/D 008D maxval rmb 1 highest peak from A/D 008E horzoffs rmb 1 horizontal scroll offset 008F horzpos rmb 1 next point to plot location 0090 current rmb 2 current VRAM cursor position 0092 scalindx rmb 1 scale factor index 0093 rateindx rmb 1 scan rate index 0094 rtvalue rmb 2 last output compare time, used to make regular interval rate 0096 seccnt rmb 2 1 second timer counter 0098 sampl rmb 1 sampling counter 0099 flagl rmb 1 flags used by the software 009A oldp2 rmb 1 keeps previous port 2 "state processed by timing routine 0080 samplflg equ 80h bit 7 used to signal sample required 0040 secflg equ 40h bit 6 used to signal 1 second period 0020 buttflg equ 20h bit 5 signals button held to freeze 0010 buttdown equ lOh bit 4 signals button down state 18 0008 clrcolmn equ 8 ;bit 3 signals to clear current ;column the display scanning Working ;space for processing routines 009B convdat rmb 1 009C scatemp rmb 1 009D mask rmb 1 ;used for bit set/clear masking ;*********** stack space is 32 bytes so this address must ;be less than Odfh ********** 009E stacklim equ * ; ******************************************************** E000 org OeOOOh ;base of 8K EPROM ; SYSTEM ROM PARAMETERS ; OFFSET for centre line E000 00 5F dofs fdb 127-32 ; amount to shift input ;by to centre the trace E002 04 msca fcb 4 E003 01 inrate fcb 1 E004 09 C4 msecper fdb 2500 ; timer increment for 2.5 ;msec periods E006 01 90 second fdb 400 ; counter for 1 sec intervals E008 E8 axscan fcb 232 ;number of graphics ;waveform columns to be scanned, remainder ; is for character field columns (256-232=24 ;= 3 characters 8bits wide) E009 01 ratetbl fcb 1 1*2.5 msec intervals 0.5sec/screen E00A 02 fcb 2 2*2.5 msec intervals 1 sec/screen E00B 04 fcb 4 4*2.5 msec intervals 2 sec/screen E00C 0A fcb 10 10*2.5 msec intervals 5 sec/screen E00D 14 fcb 20 20*2.5 msec intervals 10 sec/screen E00E 28 fcb 40 40*2.5 msec intervals 20 sec/screen E00F 3C fcb 60 60*2.5 msec intervals 30 sec/screen 19 E010 78 fcb 120 ; 120*2.5 msec intervals 60 ; sec/screen E011 00 33 scatbl fdb 51 0.2x E013 00 80 fdb 128 0.5x E015 00 CO fdb 192 0.75x E017 01 00 fdb 256 lx E019 01 80 fdb 384 1.5x E01B 02 00 fdb 512 2x E01D 05 00 fdb 1280 5x E01F OA 00 fdb 2560 lOx ; LCD control blocks E021 08 lcdcset fcb 8 ; number of parameters ; included E022 40 fcb sysset ; command to set system ; parameters E023 10 fcb 00010000b ;no correc, master, display type 0,int CG rom 32 char CG ram, 8 dots. E024 05 fcb 00000101b ;wf=0,fx=7(8 bits/char) E025 07 fcb 00000111b ;fy-7(8dots/char vertical) E026 29 fcb 41 ;42 character fields/line (256/8) E027 2E fcb 46 ;TC/R=2eh (see tbl 5.2) fosc=1.77mhz?? E028 3F fcb 63 L/F=64-l lines E029 2A fcb 42 42 character fields wide virtual screen E02A 00 fcb 0 high virtual width =0 E02B 08 lcdset ffccb 8 ;number of parameters included E02C 40 ffccb sysset ; command to set system ;parameters E02D 10 fcb 00010000b ; no correc,master, jdisplay type 0,int CG rom ; 32 char CG ram, 8 dots. E02E 07 fcb 00000111b ;wf=0,fx=7 (8bits/char) E02F 07 fcb 00000111b ; fy=7(8dots/char vertical) E030 IF fcb 31 ;32 character ;fields/line (256/8) E031 22 fcb 34 TC/R=22h (see tbl 5.2) fosc=1.77mhz?? E032 3F fcb 63 L/F=64-l lines E033 20 fcb 32 32 character fields wide virtual screen E034 00 fcb 0 high virtual width =0 E035 08 scrlset fcb 8 8 parameters follow E036 44 fcb scroll E037 00 fcb 0 E038 00 fcb 0 screen 1 starts at 0 (Characters) E039 3F fcb 3fh 64 lines (not used, not enabled) E03A 00 fcb 0 graphics screen starts at address 0 E03B 00 fcb 0 screen 2 (GRAPHICS) E03C 3F fcb 3fh 64 lines displayed E03D 00 fcb 0 screen 3 E03E 00 fcb 0 ; (not used, not enabled) E03F 01 inhdtscr fcb 1 E040 5A fcb hdtscr E041 00 fcb 0 E042 01 inovlay fcb 1 E043 5B fcb ovlay E044 00 fcb 0 E045 01 lcdgen fcb 1 E046 59 fcb dison ; turn on the display E047 10 fcb 00010000b ; 1st,3rd blocks off, nd ; block on, cursors off E048 02 cursh fcb 2 E049 46 fcb csrw E04A 00 fcb 0 E04B 00 fcb 0 ; set cursor to zero ; DOCMD outputs a command with parameters located at index ; location E04C A6 01 docmd Ida a,l,x E04E B7 40 01 sta a, lccmd . send command E051 E6 00 Ida b,0,x 21 E053 27 09 beq done E055 A6 02 docml Ida a,2,x E057 B7 40 00 sta a.glcdout E05A 08 inx 5 ' E05B 5A dec b E05C 26 F7 bne docmlp E05E 39 done rts ; SETCURS sets the cursor location in AB E05F 36 setcur psh a 10 E060 86 46 Ida a,#csrw E062 B7 40 01 sta a, glccmd E065 32 pul a E066 F7 40 00 sta b,glcdout E069 B7 40 00 sta a,glcdout 15 E06C 39 rts E06D 39 delu rts INITIALISE routine sets up the entire hardware ; and then starts scanning ; at the rate defined by the entry at the start 20 ;of the ROM E06E 86 FF in j Ida a,#0ffh E070 97 03 sta a,p2dat E072 86 01 Ida a,#l E074 97 08 sta a.tcsr 25 E076 DC 09 ldd timer E078 C3 00 14 addd #20 E07B DD OB std ocomp E07D 4F clr a E07E 97 10 sta a.rmcr ; set for highest 30 ; biphase baud rate E080 97 11 sta a, trcsr ; force serial I/O off ;Give the led controller some ;more time to power up E082 CE FF FF ldx #0ffffh 35 E085 09 inilpO dex E086 26 FD bne inilpO E088 CE E0 21 ldx #lcdcset ; setup a character ; screen of 6x8 cells E08B BD EO 4C jsr docmd ; send command string to led E08E CE EO 35 ldx #scrlset ; set up screen RAM ; locations E091 BD EO 4C jsr docmd E094 CE EO 48 ldx #cursh E097 BD EO 4C jsr docmd E09A CE EO 3F ldx #inhdtscr E09D BD EO 4C jsr docmd E0A0 CE EO 42 ldx #inovlay E0A3 BD EO 4C jsr docmd E0A6 86 59 Ida a,#dison E0A8 B7 40 01 sta a,glccmd EOAB 86 04 Ida a,#00000100b EOAD B7 40 00 sta a,glcdout EOBO 86 52 Ida a,#erase E0B2 B7 40 01 sta a,glccmd ; start clearing the ; display Can initialise the storage registers E0B5 FC E0 00 ldd dofs ; get initial offset for ; centre screen E0B8 DD 8A std offsdat ;set into offset ; register in RAM E0BA DC FF ldd 255 ; get min/max values for ; initial setup E0BC DD 8C std minval ; store both minimum and ;maximum values E0BE 97 8F sta a,horzpos ; set horizontal cursor E0C0 97 8E sta a,horzoffs ; horizontal scroll offset E0C2 B6 E0 02 Ida a, insca ; initial scale factor ; index E0C5 97 92 sta a.scalindx E0C7 B6 E0 03 Ida a, inrate ; initial rate of scanning E0CA 97 93 sta a, rateindx E0CC B6 E0 06 Ida a,second E0CF 97 96 sta a,seccnt ; setup the count for 1 ; second periods ;Must initialise the internal interupt enables, and other ; control registers of the processor E0D1 86 18 Ida a,#eici+eoci ; enable capture and ;compare interupts and set output level low on ;next campare and trigger on negative edge E0D3 97 08 sta a.tcsr E0D5 4F clr a E0D6 97 10 sta a,rmcr ;set for highest jbiphase baud rate E0D8 97 11 sta a.trcsr ; force serial I/O off ;Must wait for the screen clearing to be completed EEOODDAA 8866 0022 Ida a,#2 EODC CE FF FF ldx #0ffffh EODF 09 inilpl dex E0E0 26 FD bne inilpl E0E2 4A dec a EE00EE33 2266 FFAA bne inilpl E0E5 86 4C Ida a,#csrdirr E0E7 B7 40 01 sta a,glccmd ;set horizontal cursor ; travel ******** DEBUG ONLY FOLLOWING **************** FORCE DISPLAY OF SOME MESSAGES ***DEBUG ONLY*** Enable characters display on screen 1 E0EA 86 59 Ida a,#dison E0EC B7 40 01 sta a,glccmd E0EF 86 04 Ida a,#00000100b E E00FF11 B B77 4 400 0 000 sta a.glcdout Set cursor to line 2 char 5 E0F4 CE El 13 ldx #msg0 E0F7 BD El 5C jsr domesg E0FA CE El 2A ldx #msgl E E00FFDD B BDD E Ell 5 5CC jsr domesg E100 CE El 47 ldx #msg2 E103 BD El 5C jsr domesg E106 CE El 63 ldx #msg3 E109 BD El 8E jsr domesg ;****** INITIAL MESSAGE TIMING LOOP *********** E10C CE FF FF ldx #0ffffh E10F C6 IF Ida b,#01fh Elll 09 delayl dex 24 E112 26 FD bne delayl E114 5A dec b E115 26 FA bne delayl E117 7E El A3 jmp delay2 EllA 00 5A msgO fdb 2*42+6 EllC 50 6F 72 74 fee 'Portable ECG Monitor' E120 61 62 6C 65 E124 20 45 43 47 E128 20 4D 6F 6E E12C 69 74 6F 72 E130 00 fcb 0 E131 00 AB msgl fdb 4*42+3 E133 62 79 20 42 fee 'by BINACOM SYSTEMS P E137 49 4E 41 43 E13B 4F 4D 20 53 E13F 59 53 54 45 E143 4D 53 20 50 E147 74 79 20 4C E14B 74 64 E14D 00 fcb 0 E14E 01 02 msg2 fdb 6*42+6 E150 28 43 29 20 fee ' (C). Copyright 1986' E154 43 6F 70 79 E158 72 69 67 68 E15C 74 20 31 39 E160 38 36 E162 00 fcb 0 E163 01 26 msg3 fdb 7*42+0 E165 37 38 20 48 fee '78 Hawtin St. Tempi Vic. AUSTRALIA' - E169 61 77 74 69 E16D 6E 20 53 74 E171 2E 20 54 65 E175 6D 70 6C 65 E179 73 74 6F 77 E17D 65 20 56 69 E181 63 2E 20 41 E185 55 53 54 52 E189 41 4C 49 41 E18D 00 fcb 0 ; Message display routine E18E EC 00 domesg ldd 0,x E190 BD E0 5F jsr setcurs E193 86 42 Ida a,#mwrite E195 B7 40 01 sta a, lccmd ; set up to write ; essage E E119988 A A66 0 022 ddoommssll Ida a,2,x ; et next character E19A 26 01 bne doms2 ;if a character E19C 39 rts ; return on ;terminator E19D B7 40 00 doms2 sta a,glcdout E E11AA00 0 088 inx E1A1 20 F5 bra domsl ; loop for next ; character ; Now setup the-proper screen mode for normal display of ;waveforms, etc E1A3 CE E0 2B delay2 ldx #lcdset E1A6 BD E0 4C jsr docmd E1A9 CE E0 45 ldx #lcdgen ; go on here after ; delay timeout E1AC BD E0 4C jsr docmd E1AF CE EO 48 ldx #cursh E1B2 BD E0 4C jsr docmd E1B5 01 01 01 E1B8 86 52 Ida a,#erase E1BA B7 40 01 sta a,glccmd E1BD 01 01 01 E1C0 86 04 Ida a,#4 E1C2 CE FF FF ldx #0ffffh E1C5 09 inilp 2 dex E1C6 26 FD bne inilp2 E1C8 4A dec a E1C9 26 FA bne inilp2 ; Can start readinj ξ inputs ; Force reading on next 2.5 msec time increment E1CB 86 01 Ida a,#l E1CD 97 98 sta a,sampl E1CF 4F clr a E1D0 97 99 sta a,flagl E1D2 97 88 sta a,qcount E1D4 97 89 sta a,qend ;zero the input queue E1D6 97 8F sta a.horzpos E1D8 96 08 Ida a,tcsr E1DA 84 FE and a,#0feh ;set output low at ; compare interupt E1DC 97 08 sta a,tcsr ; to force the ; reading of data next time E1DE DC 09 ldd timer E1E0 F3 EO 04 addd msecper E1E3 DD OB std ocomp ; set compare register E1E5 DD 94 std rtvalue Must determine if the button is pressed E1E7 OE noinputs cli ; clear interupt Ida a,p2dat and a,#button bne nobutton ; As the button is pressed, flag this case and wait till ; released s ei Ida b.flagl ora b,#buttflg sta b, flagl cli buttwait Ida a,p2dat and a,#button beq buttwait nobutton sei Ida b, flagl and b,#not(buttflg) ; ensure jbutton flag is cleared sta b, flagl cli E1E8 D6 99 Ida b, flagl E1EA C4 40 and b,#secflg E1EC 27 00 beq nolsec ;skip when no second ; expired ;***** Do 1 second update of character displays ;****** INSERT PROCESSING ROUTINES HERE ****** ;AS SCROLLING NOT YET IMPLEMENTED ADVANCE THE CURSOR, WRAP ; SCANNING AT SCREEN LIMITS E1EE 96 99 nolsec Ida a, flagl E1F0 84 08 and a,#clrcolmn ; if column ; clearing is required E1F2 26 03 bne wipe E1F4 7E E2 DA jmp pointplot ; go to plot next ; point if any ; get column top location E1F7 OF wipe sei ;no interupts here, while ;FLAG1 is E1F8 96 99 Ida a, flagl ; updated E1FA 84 F7 and a,#not(clrcolmn) E E11FFCC 9 977 9 999 sta a, flagl E1FE 0E cli jrenable interupts E1FF D6 8F Ida b,horzpos E201 54 lsr b E202 54 lsr b E E220033 5 544 lsr b ; have position along x axis ; Set direction of writting to down E204 86 4F Ida a,#csrdird E206 B7 40 01 sta a, glccmd E209 86 46 Ida a,#csrw ; set cursor command E E2200BB B B77 4 400 0 011 sta a, glccmd ; Now output cursor location of top byte in the column E20E 4F clr a E20F F7 40 00 sta b.glcdout E212 B7 40 00 sta a.glcdout ; Now can start writting to VRAM E215 C6 42 Ida b,#mwrite E217 F7 40 01 sta b,glccmd ; Now write 64 bytes of O's, to fill the column 28 ;at 4 cycles per instruction = 64*4 = 256 cycles (ie ;256 usec) E21A B7 40 00 sta a, lcdout E21D B7 40 00 sta a, lcdout E220 B7 40 00 sta a, lcdout E223 B7 40 00 sta a, glcdout E226 B7 40 00 sta a, lcdout E229 B7 40 00 sta a,glcdout E22C B7 40 00 sta a,glcdout E22F B7 40 00 sta a, lcdout E232 B7 40 00 sta a,glcdout E235 B7 40 00 sta a,glcdout E238 B7 40 00 sta a, lcdout E23B B7 40 00 sta a, lcdout E23E B7 40 00 sta a,glcdout E241 B7 40 00 sta a,glcdout E244 B7 40 00 sta a, glcdout E247 B7 40 00 sta a, lcdout E24A B7 40 00 sta a, lcdout E24D B7 40 00 sta a, lcdout E250 B7 40 00 sta a,glcdout E253 B7 40 00 sta a,glcdout E256 B7 40 00 sta a, glcdout E259 B7 40 00 sta a,glcdout E25C B7 40 00 sta a,glcdout E25F B7 40 00 sta a, lcdout E262 B7 40 00 sta a, glcdout E265 B7 40 00 sta a, glcdout E268 B7 40 00 sta a,glcdout E26B B7 40 00 sta a,glcdout E26E B7 40 00 sta a,glcdout E271 B7 40 00 sta a,glcdout E274 B7 40 00 sta a,glcdout E277 B7 40 00 sta a, glcdout E27A B7 40 00 sta a, glcdout E27D B7 40 00 sta a, lcdout E280 B7 40 00 sta a,glcdout E283 B7 40 00 sta a,glcdout E286 B7 40 00 sta a, lcdout E289 B7 40 00 sta a,glcdout E28C B7 40 00 sta a, lcdout E28F B7 40 00 sta a, lcdout E292 B7 40 00 sta a, lcdout E295 B7 40 00 sta a, glcdout E298 B7 40 00 sta a, lcdout E29B B7 40 00 sta a,glcdout E29E B7 40 00 sta a, lcdout E E22AA11 B B77 4 400 0 000 sta a, lcdout E2A4 B7 40 00 sta a,glcdout E2A7 B7 40 00 sta a,glcdout E2AA B7 40 00 sta a,glcdout E2AD B7 40 00 sta a,glcdout E E22BB00 B B77 4 400 0 000 sta a, glcdout E2B3 B7 40 00 sta a, glcdout E2B6 B7 40 00 sta a, glcdout E2B9 B7 40 00 sta a, glcdout E2BC B7 40 00 sta a.glcdout E E22BBFF B B77 4 400 0 000 sta a, glcdout E2C2 B7 40 00 sta a.glcdout E2C5 B7 40 00 sta a,glcdout E2C8 B7 40 00 sta a,glcdout E2CB B7 40 00 sta a, glcdout E E22CCEE B B77 4 400 0 000 sta a, lcdout E2D1 B7 40 00 sta a, glcdout E2D4 B7 40 00 sta a,glcdout E2D7 B7 40 00 sta a,glcdout Now see if any display data exists E E22DDAA 9 966 8I 388 pointplot Ida a.qcount E2DC 26 1 33 bne doinput ; if no data to plot E2DE 7E 1 31 1 17 jmp noinputs ;Have received input data, calculate the next point on the ; display after the capture interupt has come. ;( Comes 103 to 114 usec after trigger at 640kHz clock) E2E1 D6 03 doinputs Ida b,p2dat E2E3 C8 08 eor b,#8 E2E5 D7 03 sta b,p2dat E2E7 OF sei E2E8 CE 00 80 ldx #qbase E2EB D6 89 Ida b,qend E2ED 3A abx ; Update queue with interupts disabled ( 18 cycles) E2EE 5C inc b ;point next byte E2EF C4 07 and b,#7 ; allow only 8 byte ; queue length E2F1 96 88 Ida a,qcount E2F3 4A dec a E2F4 DD 88 std qcount ; update queue pointers E2F6 E6 00 Ida b,0,x ; get data E2F8 0E cli ; allow interupts again E2F9 D7 9B sta b.convdat ; save working in ;put data value ;Do not process the input other than multiplying by ; scaling factor and offsetting for centre screen. ;When the trace goes off screen no point will be shown. Ida b,scalindx ldx fscatbl abx Ida b,l,x ;get low 8 bit scaling factor mul addd #80 sta a,scatemp ;save intermediate result Ida a,0,x Ida b,convdat mul add b,scatemp adc a,#0 ; scaling(16)*conv(8)=result (16) ; retain top 2 bytes of 3 byte result ; Ida b.horzpos E2FB 4F clr a E2FC 93 8A subd offsdat ;adjust for the ; centre screen offset ;Check for lower screen limit E2FE 25 0B bio toolow ; if lower than zero ;plot at lower E300 01 01 01 .edge of the screen ;Check for top of screen limit E303 Cl 40 cmp b,#64 E305 23 06 bis displok ; If above top of screen, so show top edge E307 C6 40 Ida b,#64 E309 20 02 bra displok E30B C6 00 toolow Ida b,#0 ; Reverse display orientation, + up - down E30D 86 40 displok Ida a,#64 E30F 10 sba ;form index from top to jbottom, into screen line E310 C6 20 Ida b,#32 ; number of ram bytes ; in a line on the display E312 3D mul ; calculate vertical ; index offset E313 36 psh a E314 37 psh b E315 D6 8F Ida b.horzpos ; et horizontal ; position E317 86 20 Ida a,#32 E319 3D mul E31A 33 pul b E31B IB aba E31C 16 tab E31D 32 pul a E31E 8B 00 add a,#0 ; transfer carry ; Have the true current cursor position in AB E320 37 psh b E321 D6 03 Ida b,p2dat E323 C8 10 eor b,#10h E325 D7 03 sta b,p2dat E327 33 pul b E328 DD 90 std current E32A BD E0 5F jsr setcurs E32D 86 43 Ida a,#mread E32F B7 40 01 sta a,glccmd E332 86 40 01 Ida a,glcdin ;Now determine the bit offset E335 D6 8F Ida b.horzpσs E337 BD E3 55 jsr setbits E33A 9A 9D ora a,mask ;set the required bit E33C 36 psh a ;save it for now E33D DC 90 ldd current E33F BD EO 5F jsr setcurs E342 86 42 Ida a,#mwrite EE334444 BB77 4400 0011 sta a, glccmd E347 32 pul a E348 B7 40 00 sta a,glcdout ; put back in ; display memory E34B 7E El E7 jmp noinputs ; o back to get ;next input ;BIT set and clear utilities alters the bit jspecified in B (0-7) of register A. E34E BD E3 55 clrbits jsr setbits ; get setting ;pattern, then... E E335511 5 533 com b ; invert bit pattern E352 D7 9D sta b,mask E354 39 rts E355 CE E3 60 setbits ldx #setptrn E358 C4 07 and b,#7 ; extract bit position E E3355AA 3 3AA abx E35B E6 00 Ida b, 0,x E35D D7 9D sta b.mask E35F 39 rts ; Table of bitset patterns, corresponding to display bits 0 ;to 7 of each graphics characters field. E360 80 setptrn fcb 10000000b E361 40 fcb 01000000b E362 20 fcb 00100000b E363 10 fcb 00010000b E364 08 fcb 00001000b E365 04 fcb 00000100b E366 02 fcb 00000010b E367 01 fcb 00000001b 33 {CHARACTER PATTERNS FOR DISPLAY OF OTHER INFORMATION ON ;THE GRAPHICS BOUNDARY E368 3C zero fcb 00111100b E369 42 fcb 01000010b E36A 46 fcb 01000110b E36B 4A fcb 01001010b E36C 52 fcb 01010010b E36D 62 fcb 01100010b E36E 42 fcb 01000010b E36F 3C fcb 00111100b E370 08 one fcb 00001000b E371 18 fcb 00011000b E372 28 ' fcb 00101000b E373 08 fcb 00001000b E374 08 fcb 00001000b E375 08 fcb 00001000b E376 08 fcb 00001000b E377 7E fcb 01111110b E378 3C two fcb 00111100b E379 42 fcb 01000010b E37A 02 fcb 00000010b E37B 04 fcb 00000100b E37C 08 fcb 00001000b E37D 10 fcb 00010000b E37E 20 fcb 00100000b E37F 7E fcb 01111110b E380 3C three fcb 00111100b E381 42 fcb 01000010b E382 04 fcb 00000100b E383 18 fcb 00011000b E384 04 fcb 00000100b E385 02 fcb 00000010b E386 42 fcb 01000010b E387 3C fcb 00111100b E388 02 four fcb 00000010b 34 E389 06 fcb 00000110b E38A 0A fcb 00001010b E38B 12 fcb 00010010b E38C 22 fcb 00100010b E38D 7E fcb 01111110b E38E 02 fcb 00000010b E38F 02 fcb 00000010b E390 7E five fcb 01111110b E391 40 fcb 01000000b E392 40 fcb 01000000b E393 38 fcb 00111000b E394 04 fcb 00000100b E395 02 fcb 00000010b E396 42 fcb 01000010b E397 3C fcb 00111100b E398 1C six fcb 00011100b E399 22 fcb 00100010b E39A 40 fcb 01000000b E39B 40 fcb 01000000b E39C 5C fcb 01011100b E39D 62 fcb 01100010b E39E 42 fcb 01000010b E39F 3C fcb 00111100b E3A0 7E seven fcb 01111110b E3A1 02 fcb 00000010b E3A2 04 fcb 00000100b E3A3 08 fcb 00001000b E3A4 10 fcb 00010000b E3A5 20 fcb 00100000b E3A6 20 fcb 00100000b E3A7 20 fcb 00100000b E3A8 3C eight fcb 00111100b E3A9 42 fcb 01000010b E3AA 42 fcb 01000010b 35 E3AB 3C fcb 00111100b E3AC 42 fcb 01000010b E3AD 42 fcb 01000010b E3AE 42 fcb 01000010b E3AF 3C fcb 00111100b E3B0 3C nine fcb 00111100b E3B1 42 fcb 01000010b E3B2 42 fcb 01000010b E3B3 3C fcb 00111100b E3B4 02 fcb 00000010b E3B5 02 fcb 00000010b E3B6 42 fcb 01000010b E3B7 3C fcb 00111100b ; TIMING is required to process the 2.5msec period ; interupts and maintain the 1 second time base. E3B8 96 98 timing Ida a.sampl ; et the time period ; counter E3BA 4A dec a E3BB 26 0E bne notrig E3BD 96 99 Ida a, flagl E3BF 8A 80 ora. a,#samρlflg E3C1 97 99 sta a, flagl ; signal that this ; input must go into the display queue also ; setup the next count for sampling period E3C3 D6 93 Ida b,rateindx E3C5 CE E0 09 ldx #ratetbl E3C8 3A abx E3C9 A6 00 Ida a,0,x Clear the trigger, reload.- sampling » rate and start next 2.5 msec period E E33CCBB 9 977 9 988 notrig sta a.sam l E E33CCDD 9 966 0 088 Ida a.tcsr E E33CCFF 8 8AA 0 011 ora a,#l E E33DD11 9 977 0 088 sta a.tcsr E E33DD33 D DCC 0 099 ldd timer E E33DD55 C C33 0 000 00AA addd #10 E E33DD88 D DDD 0 0BB std ocomp ; The trigger line is forced high again, by the immediate ;compare reset for A/D trigger next time E3DA 96 08 Ida a.tcsr E3DC 84 FE and a,#0feh ; force next time to ; trigger the A/D E3DE 97 08 sta a.tcsr E3E0 DC 94 ldd rtvalue E3E2 F3 EO 04 addd msecper ; calculate the next ; compare time 10 E3E5 DD 0B std ocomp ; have setup next ; compare time interupt E3E7 DD 94 std rtvalue ;keep for the future ;Must process the 1 second timing E3E9 DC 96 ldd seccnt 15 E3EB 83 00 01 subd #1 E3EE 26 09 bne nosec ;Have a second over, so set the flag E3F0 96 99 Ida a,flagl E3F2 8A 40 ora a,#secflg • 20 E E33FF44 9 977 9999 sta a,flagl E3F6 FC E0 06 ldd second ; value to reload 1 ; second timer E3F9 DD 96 nosec std seccnt ;save for next time ; around 25 ;Must process the port 2 button sensing operation E3FB 96 03 Ida a,p2dat E3FD 16 tab E3FE 98 9A eor a,oldp2 E400 D7 9A sta b,oldp2 ; set current state 30 ; into 0LDP2 E402 84 04 and a,#button ; mask for button bit E404 26 14 bne buttchng jbutton changed if ;not zero ;Since button is stable over a 2.5 msec period accept 35 ; reading as stable ; If zero (button pressed) then toggle button flag. E406 96 99 Ida a,flagl E408 C4 04 and b,#button ;mask current 37 {condition of button bit E40A 26 0A bne notbutt ;Since button is down check if already known to be down E40C 85 10 bit a,#buttdown E40E 26 0A bne buttchng ; if already {processed this button press ; do not do it again E410 8A 10 ora a,#buttdown ;set button {pressed acknowledge E412 88 20 eor a,#buttflg {complement {button flag E414 20 02 bra setbutt ;all done E416 84 EF notbutt and a,#not(buttdown) {signal {button off E418 97 99 setbutt sta a, flagl E41A 3B buttchng rti {CONVERSION reads the completed A/D conversion result and {places this in the buffer queue E41B 96 08 conversion Ida a.tcsr E41D DC 0D ldd icomp ; clear capture interupt {Check if data is to be retained E41F D6 99 Ida b,flagl E421 2A 19 bpl noadvance ; do not need to {advance to next column yet E423 C4 7F and b,#low(not(samplflg) ) {clear the sampling period flag which determines advancing {rate of the display scan. Update the horizontal screen {position every time a sample period is passed. E425 96 8F Ida a.horzpos E427 4C inc a E428 Bl E0 08 cmp a.maxscan E42B 25 05 bio nowrap ;As wrap around required set cursor pointer to 0 E42D 4F clr a ;At the end of a screen scan, when the button pressed flag ;is on cease placing waveform data into the queue, so {scanning will hold. The screen position will not advance {till freeze is released by button pressing. E42E C4 20 and b,#buttflg E430 26 21 bne othconv ; do other conversions E432 97 8F nowrap sta a.horzpos {Must check whether to clear the next column for next data {display. For simplicity just clear a column of bytes" {whenever the bit position of the current column is on a {byte boundary. E434 85 07 bit a,#7 {check if bit position = 0 E436 26 02 bne nowipe ;not required to clear ; a column E438 CA 08 ora b,#clrcolmn {set flag to ; clear a new column E43A D7 99 nowipe sta b, flagl {clear sampling {required flag (if req. set clear column flag) ; Form pointer to the queue E43C 96 02 noadvance Ida a.pldat {get A/D data and {send into the queue E43E D6 88 Ida b.qcount E440 Cl 08 cmp b,#8 {check if queue has {maximum length E442 24 10 bhs qfull E444 CE 00 80 ldx #qbase E447 DB 89 add b,qend {offset to head of ; the queue - E449 C4 07 and b,#7 ;wrap around at 8 ;byte boundary E44B 3A abx E44C A7 00 sta a,0,x ;save new A/D result E44E D6 88 Ida b.qcount E450 5C inc b E451 D7 88 sta b.qcount {Go on to other processing of input sampling. ;******** CURRENTLY NOTHING IMPLEMENTED YET ********* E453 3B othconv rti ; done fetching {conversion result E454 7E FF E0 qfull jmp startup {full so restart the {unit as this is only possible when a serious {error exists in the system. {The following are invalid interupts and shall be ignored E457 serio equ * E457 tovl equ * E457 interupt equ * E457 swtrap equ * E457 0E invalid cli E458 3B rti ;****** DO NOT MAKE CHANGES BEYOND HERE ****** FFEO org OffeOh {MUST BE HERE FOR POWER {ON RESET FFEO OF startup sei {keep other interupts {off FFE1 8E 00 FF Ids #0ffh {force stack to be ; valid FFE4 86 FF Ida a,#0ffh FFE6 97 05 sta a,p4dir {set port 4 as outputs FFE8 CC 00 1A ldd #lah ; port 1 all inputs , ;P21 output FFEB DD 00 std pldir FFED 7E E0 6E jmp initialise {SYSTEM VECTORS FFF0 org OfffOh FFF0 E4 57 scint fdb serio FFF2 E4 57 tofl fdb tovl FFF4 E3 B8 ocint fdb timing FFF6 E4 IB icint fdb conversion FFF8 E4 57 intl fdb interupt FFFA E4 57 swi fdb swtrap FFFC E4 57 nmi fdb invalid FFFE FF E0 reset fdb startup 0000 END No error(s) SUBSTITUTE SHEET RAMBASE 0080 adeoc 0001 adtrig 0002 buttchng E41A buttdown 0010 buttflg 0020 button 0004 ccOl 0004 cclO 0008 cell OOOC ccbiph 0000 cgradr 005C clrbits E34E clrcolmn 0008 convdat 009B conversi E41B csrdird 004F csrdirl 004D csrdirr 004C csrdiru 004E csrform 005D csrr 0047 csrw 0046 current 0090 cursh E048 delayl Elll delay2 E1A3 delu E06D disoff 0058 dison 0059 displok E30D docmd E04C docmlp E055 dofs E000 doinputs E2E1 domesg E18E domsl E198 doms2 E19D done E05E eici 0010 eight E3A8 eoci 0008 erabsy 0080 erase 0052 etoi 0004 ive E390 flagl 0099 four E388 glc 4000 glccmd 4001 gledin 4001 glcdout 4000 glcstat 4000 hdtscr 005A horzoffs 008E horzpos 008F icf 0080 icint FFF6 icomp 000D iedg 0002 inhdtscr E03F inilpO E085 inilpl E0DF inilp2 E1C5 initiali E06E inovlay E042 inrate E003 insca E002 intl FFF8 interupt E457 invalid E457 is3flg . 0080 is3irq 0040 laen 0008 ledeset E021 ledgen E045 lcdset E02B mask 009D maxscan E008 maxval 008D minval 008C mread 0043 msecper E004 msgO EllA msgl E131 msg2 E14E msg3 E163 mwrite 0042 nine E3B0 nmi FFFC nolsec E1EE noadvanc E43C noinputs E1E7 nosec E3F9 notbutt E416 notrig E3CB nowipe E43A nowrap E432 ocf 0040 ocint FFF4 ocomp 000B offsdat 008A oldp2 009A olvl 0001 one E370 orfe 0040 OSS 0010 othconv E453 ovlay 005B pldat 0002 pldir 0000 p2dat 0003 p2dir 0001 p3csr 000F p3dat 0006 p3dir 0004 p4dat 0007 p4dir 0005 pointplo E2DA qbase 0080 qcount 0088 qend 0089 full E454 ramcr 0014 rame 0040 rateindx 0093 ratetbl E009 rdr 0012 rdrf 0080 re 0008 reset FFFE rie 0010 rmcr 0010 rtvalue 0094 sampl 0098 samplflg 0080 scalindx 0092 scatbl E011 scatemp 009C scint FFF0 scrlset E035 scroll 0044 seccnt 0096 secflg 0040 second E006 serio E457 setbits E355 setbutt E418 setcurs E05F setptrn E360 seven E3A0 six E398 sleepin 0053 ssOO 0000 ssOl 0001 sslO 0002 ssll 0003 stacklim 009E startup FFEO stbypwr 0080 swi FFFA swtrap E457 sysset 0040 tcsr 0008 tdr 0013 tdre 0020 te 0002 three E380 tie 0004 timer 0009 timing E3B8 tof 0020 tofl FFF2 toolow E30B tovl E457 trcsr 0011 two E378 wipe E1F7 wu 0001 xstby 0040 zero E368

Claims: CLAIMS 1. An electrocardiograph (2) comprising input terminal means (32, 34, 36, 38, 40), an analog to digital converter (62) for converting electrical signals on said input terminal means (32, 34, 36, 38, 40) into digital signals, a memory device (78) for storing said digital signals and electronic display means (6) for graphically displaying the digital signals. 2. An electrocardiograph (2) as claimed in claim 1 further comprising processor means (50) which is capable of receiving said digital signals and recognising the digital signals as being data representative of electrocardiograph signals. 3. An electrocardiograph (2) as claimed in claim 2 , wherein said processor means (50) upon receiving said data, divides the data into waveform data representative of a heart beat trace (16). 4. An electrocardiograph as claimed in claim 3 wherein said processor means (50) calculates a heart beat rate on the basis of said waveform data and causes said heart beat rate to be displayed on said display means (6). 5. An electrocardiograph as claimed in claim 3 or 4, wherein said processor means (50) analyses said waveform data in order to determine whether the waveform data represents fundamental deviations from normal behaviour and if notable deviations are detected the processor means (50) causes an SU indication to a user of the device. 6. An electrocardiograph as claimed in any one of claims 3 to 5 wherein said processor means (50) causes hear beat traces corresponding to waveform data to be displayed on said display means (6) when sufficient data to do so has been received by said processor means (50). 7. An electrocardiograph as claimed in any one of claims 3 to 6 further comprising command input means (8) which allows a user to control display parameters, input and output of waveform data, storage of waveform data or analysis of waveform data, wherein said processor means (50) is responsive to said command input means (8). 8. An electrocardiograph as claimed in claim 7 wherein in response to said command signal means (8) said processor means (50) is capable of causing the display scale, the display offset or the scan rate, associated with the display of a trace (16), to be altered. 9. An electrocardiograph as claimed in claims 7 or 8, wherein in response to said command input means (8) said processor means (50) is capable of causing a heart beat trace (16) to be continuously displayed once a full screen trace of the trace (16) has been displayed. 10. A electrocardiograph as claimed in claim 7 wherein in response to said command input means (8) said processor means (50) is capable of outputting graphically or numerically waveform data to an external device connected to output terminal means (24); inputting waveform data from said external device; or causing an external printer, connected to said output terminal means (24), to print an analysis of selected waveform data. 11. An electrocardiograph as claimed in claim 7 or 10 wherein in response to said command input means (8) said processor means (50) is capable of recalling waveform data stored in said memory device (78) and causing the trace (16), corresponding to the recalled data, to be displayed; storing waveform data in said memory drive, (78); deleting waveform data; or placing or removing protection on waveform data. 12. An electrocardiograph as claimed in claims 7, 10 or 11 wherein in response to said command input means (8) said processor means (50) is capable of analysing waveform data by halting display of a selected trace (16) and comparing the waveform data corresponding to the selected trace against predetermined data representative of standard medical conditions, and if no medical problem is detected said processor means (50) causes indication to a user that a normal heart pattern is present and causes display of waveform data statistics, yet if a medical problem is detected causes indication to a user of one or more possible diagnostic conditions and causes display of waveform data statistics. 13. An electrocardiograph as claimed in any one ot the preceding claims wherein said display means (6) comprises a liquid crystal display having a screen having from 60 x 150 to 128 x 516 pixels so as to provide good trace resolution of the digital signals, which are representative of electrocardiograph signals applied to the input terminal means (32, 34, 36, 38, 40). 14. An electrocardiograph as claimed in any one of the preceding claims wherein at least one input terminal of said input terminal means (32, 34, 36, 38, 40) is a common terminal (40) connected to a central electrode (14) and at least two other input terminals (32, 34) are connected respectively to at least two other electrodes (10, 12), said electrodes (10, 12, 14) being positioned on the underside of a housing (4) of said electrocardiograph (2), said electrodes being adapted to receive electrocardio¬ graph signals when placed upon the skin of a patient near the patient's heart. 15. An electrocardiograph as claimed in claim 14 wherein the signals received by said at least two other terminals (32, 34) are inputted to respective buffers (42) and the signals received by the common terminal (40) is inputted to the outputs of the buffers (42) so as to remove any DC offset that would affect said electrical signals received by the input terminal means (32, 34, 36, 38, 40). 16. An electrocardiograph as claimed in any one of the preceding claims further comprising a notch filter (54 or 56) to filter said electrical signals so as to remove noise signals of a predetermined frequency induced by a mains supply. 7 46 17. An electrocardiograph as claimed in any one of claims 2 to 16 wherein said analog to digital converter (62) has a high and a low sensitivity input for selectively receiving said electrical signals having high or low voltage, in accordance with control signals received from said processor means (80). 18. An electrocardiograph as claimed in any one of claims 2 to 16 wherein said analog to digital converter (62) samples said electrical signals at a predetermined rate in accordance with control signals received from said processor means (50) . 19. An electrocardiograph as claimed in any one of claims 2 to 16 further comprising graphic control means (70) for controlling said display means (6) and accessing said memory device (70) in response to signals received from said processor means (50). 20. An electrocardiograph substantially as hereinbefore described with reference to the accompanying drawings.

Inventors: CERNJAVIC DRAGO, SCHULTES HANS HELMUTH, VODICKA VLADIMIR WEBER, CERNJAVIC, DRAGO, SCHULTES, HANS, HELMUTH, VODICKA, VLADIMIR, WEBER
Applicants: CERNJAVIC DRAGO, SCHULTES HANS HELMUTH, VODICKA VLADIMIR WEBER, CERNJAVIC, DRAGO, SCHULTES, HANS, HELMUTH, VODICKA, VLADIMIR, WEBER
Application year: 1987
Main classification: A61B5
IPC codes: A61B5, G06F17