DIFFERENTIAL CIRCUIT

Abstract: To increase a voltage gain of a differential circuit, constant current source type FETs in which a source and a gate are short circuited are used as a load element (Q L1 , Q L2 ) and as a current source (Q CS ), and a constant voltage type FET (Q C1 , Q C2 ) is used as a clamp to clamp the load element. Therefore the temperature characteristic and the deterioration of an AC characteristic, which cause problems in a conventional diode clamp type differential circuit, can be improved.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential circuit using a field effect type semiconductor element (FET), and particularly, it relates to a differential circuit mounted on a semiconductor integrated circuit. 2. Description of the Related Art Hereinafter, the explanation of a differential circuit will be given, as an example, when a gallium arsenide MESFET (metal-semiconductor junction FET) is used. The basic type of FET differential amplifier circuit is usually formed by transistors as a differential pair, and has load resistors connected between a high potential source and a low potential source. But, in such a circuit, a sufficient voltage gain cannot be obtained because of the load resistors. Therefore, to improve the voltage gain, it has been proposed to replace the load elements and the current source with a constant current type FET in which a short-circuit is made between the gate and the source. Such a configuration is known from "Bipolar and MOS analog integrated circuit design", A.B. Grebene, Fig. 6.22, published 1984 by John Wiley and Sons. However, this type of circuit has the following drawbacks: 1. When an input is high level a current flows into a gate of a driver FET, and if the value of this current is large, a break down of a wire or a deterioration of the Schottky characteristic may occur. 2. The dependency of a circuit characteristic on an element characteristic is high, and thus the circuit characteristic is easily changed by a variation in the element characteristic. To solve this problem, it has been proposed that both ends of the load FET be clamped by diodes, to obtain a stable operation. However, this clamping by the diodes causes other problems, such as: A large temperature characteristic at the low output level, which occurs because the low output level is determined by a forward ON voltage of the I-V characteristic of the diode; and a deterioration of the AC characteristic because the junction capacitance of the diode becomes a load. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the drawbacks of a conventional FET differential circuit, and to provide a differential circuit in which a sufficient voltage gain and a stable operation can be obtained. This object can be achieved by providing a differential circuit according to Claim 1, in which a FET clamp is connected in parallel with each constant-current-type load FET, the utilization of the FET clamp having the following effects: 1. The FET clamp does not have a temperature characteristic, unlike a diode. 2. The capacitance between the drain and the source is added to the load, but this is a very small value when compared with the junction capacitance of the diode, and thus a deterioration of a transient characteristic can be prevented. Further features and advantages of the present invention will be apparent from the ensuing description with reference to the accompanying drawings to which, however, the scope of the invention is in no way limited. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A, 1B, and 1C are examples of conventional differential amplifier circuits, respectively; Fig. 2 shows one embodiment of the differential amplifier circuit according to the present invention; Fig. 3 shows another embodiment of the differential amplifier circuit according to the present invention; Figs. 4A to 4C are diagrams explaining an analysis of the differential amplifier circuit according to the present invention; Fig. 5 is a diagram of the circuit in the embodiment of the present invention used in an analysis in which an output low level is clamped to V GG ; Figs. 6A and 6B are diagrams showing a plan view and a section view of the integrated circuit shown in Fig. 5; Figs. 7A and 7B are diagrams of the differential circuit when the present invention is applied to a logic construction similar to a conventional CML; Figs. 8 and 10 are diagrams for converting the SiECL level in the application of the present invention to the GaAs DCFL level and BFL level; and, Fig. 9 is a level diagram for the circuit shown in Fig. 8. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1A shows a basic type of conventional FET differential amplifier circuit which is formed by transistors Q₁ , Q₂ as a differential pair, load resistor R₁ and R₂ , and a resitor R₀. V DD is a high potential source and V EE is a low potential source. However, in such a circuit, a sufficient voltage gain cannot obtained because of the load resistors. Therefore, to improve a voltage gain, the circuit has been proposed as shown in Fig. 1B, wherein the load elements and the current source are replaced by constant current type FETs Q L1 , Q L2 and Q CS , in which a short-circuit is made between the gate and the source. However, this circuit has the drawbacks discussed in the previous section. Therefore, to solve this problem, the circuit as shown in Fig. 1C has been proposed, wherein both ends of the load FET Q L1 , Q L2 are clamped by diodes D₁ , D₂ , to obtain a stable operation. However, this clamping by the diodes, as already mentioned, provokes new problems, such as a large temperature characteristic at a low output level, and a deterioration in the AC characteristic. In the present invention, to increase the voltage gain of the differential circuit, a constant current type FET in which a gate and a source are short-circuited is used as a load element and a current source, and an FET clamp is used instead of the above-mentioned diode clamp. Figure 2 shows a differential amplifier basic circuit of one embodiment of the present invention. As in the case shown in Fig. 1C, the load elements and the current source of the differential amplifier circuit are replaced by constant current type FETs Q L1 , Q L2 and Q CS in which the source and the gate are short-circuited. In Fig. 2 the same symbols are used to denote the same portions shown in Fig. 1. Further, a FET (hereinafter called a clamp FET) Q C1 , Q C2 acting as clamping element is provided between the source and the drain of a respective constant current type FET Q L1 , Q L2 acting as load element. Each clamp FET operates as a constant voltage source having a gate connected to a reference electric potential V GG . Further, in this case, an input is connected to the gate of one drive FET Q₁ of the differential pair, and a suitable reference voltage V REF is applied to the gate of another drive FET Q₂ to obtain an output OUT and a reverse output OUT . Note this may be also applied to a reverse signal of the input IN. The condition wherein a stable circuit operation can be obtained by a constant voltage type operation of the FET Q C1 , Q C2 will be described. To assist with this analysis, Fig. 4A shows a partial circuit of the differential amplifier circuit of one embodiment of the present invention, wherein the load FET is designated as Q L , the clamp FET as Q C , and the drive FET as Q. Further Fig. 4B shows the transistor Q C used as the clamp FET, and Fig. 4C shows the voltage vs current characteristic of the load FET Q L and the clamp FET Q C . In Fig. 4C, the abscissa shows the difference of the voltages between the output OUT and the supply voltage V DD , and the ordinate shows the current I L in the FET Q L and I X between the source and the drain of Q L and Q C when the drive FET Q is made ON and the current flows to this differential side. When the current I L flows in the FET Q L as the load element, since the source and the drain thereof are commonly connected, the drive FET Q is made ON and the voltage of the output OUT is lowered, and when the voltage difference between the power source and the output is increased, the constant current characteristic as shown in Fig. 4C is obtained. On the other hand, since the gate voltage is fixed to V X , the current of the clamp FET Q C is suddenly increased at a region where the gate/source voltage rises beyond the threshold value V th of Q C , to obtain the constant voltage characteristic region. The voltage/current characteristic of the parallel circuit of the FET Q L and Q C becomes as shown by the broken line obtained by combining these two characteristics, so that the constant voltage operation region appears. Then, as shown in the drawing, if the current I CS of the current source of this differential pair enters a constant voltage region of the parallel circuit of Q L , Q C , the output voltage, i.e., the low level output, can be clamped at a value smaller by V D than the power source, V D being the voltage drop of parallel circuit of Q L , Q C . However, in the case of a MESFET, for example, the gate/source voltage is restricted at a voltage V F by which the Schottky junction of the gate is made ON, i.e. forward-biased, so that the current is saturated. Therefore, the constant voltage characteristic region of the parallel circuit of Q L , Q C appears only at the side lower than the ON voltage V F of the Schottky junction of the clamp FET Q C . Therefore, for the functioning of the clamp FET Q C in the circuit shown in Fig. 4A, the following condition should first be satisfied: I L < I CS (I) Next, the condition in which the gate/source voltage of the FET clamp is at a maximum is that corresponding to the ON voltage V F of the Schottky junction of the gate of the MESFET: that is, I L + I X (V F ) > I CS (2) wherein I X (V F ) is the current which flows between the source and the drain when the ON voltage V F of the Schottky junction is applied to the gate of the MESFET of the FET clamp. The existence of these two conditions allows the output level to be clamped at the crosspoint of the I CS and the combined characteristic curve (constant voltage region) is obtained. That is, when the other side of the differential pair is completely cut off and all I CS of the current source flow in the considered side, the current I L of the load FET Q L becomes constant and the remaining currents flows in the clamp FET Q C , whereby the low level output is clamped at the level V D at the crosspoint with the constant voltage region of the characteristic curve. The adjustment for satisfying the above-mentioned conditions (1) and (2) is carried out by adjusting the circuit constant of the differential amplifier cirucit, for example, the gate width of three FET's (a drive FET Q, a load FET Q L , and a clamp FET Q C ). Next, Fig. 3 shows another embodiment of the differential amplifier circuit according to the present invention. This embodiment is different from Fig. 2 in that a differential input IN is applied. Further, in the circuits of Fig. 2 and Fig. 3, the load FET Q L1 , Q L2 , the clamp FET Q C1 , Q C2 , and the constant current source FET Q CS are manufactured by the same process, have a similar distribution of impurities and have the same value of V TH , K value and gate length, and only the gate width is different. The K value of a FET is given by the formula K = I/[W(V GS -V th )²] where I is the current flowing via the FET, W is the gate width thereof, V th is the threshold voltage, and V GS is the voltage between the gate and the source thereof. In this embodiment, when the gate width of the load FET Q L1 , Q L2 is designated as W L , the gate width of the clamp FET Q C1 , Q C2 as WC , and the gate width of the constant current source FET Q CS as W CS , the following condition occurs, W CS = W L + W C (3) By setting this condition, the low level output can be made the same level as the gate potential V GG of the clamp FET Q C . Hereinafter, this condition (3) will be described with reference to the differential amplifier circuit shown in Fig. 5 and Figs. 6A and 6B. Here, the drive FET is designated as Q S , Q R , the load FET as Q L , Q L , the clamp FET as Q C , Q C , a high level source as V DD , and the low level source as V EE . 1. High level output When the drive FET Q S or Q R is made completely OFF, the OUT signal rises to the V DD level. Therefore, the high level output satisfies V OH = V DD . 2. Low level output When the drive FET Q S or Q R is made completely OFF and Q CS , Q L , and Q C are saturated, I L = K L ·W L ·(-V thL )² but if Q L and Q CS have the same characteristic, the above equation can be changed as follows, I L = K CS ·W L ·(-V thCS )² and the current of the clamp FET becomes I C = K C ·W C ·(V GSC - V thC )² = K C ·W C ·(V GG - V OL - V thC )² and the current of the current source FET Q CS becomes I CS = K CS ·W CS ·(-V thCS )² Wherein, K L , K CS , and K C are the value of K of each FET; V thL , V thC , and V thCS are the threshold value of each FET; and W L , W C , and W CS are the gate width of each FET. When the current is set as I CS = I L + I C and solved by V OL , If the setting is, V thCS = V thL = V thC , K CS = K L = K C and W CS - W L = W C of each transistor, the low level output becomes V OL = V GG (4) That is, when the K values and V th of the load FET Q L , clamp FET Q C , and the current source FET Q CS of the differential circuit are made equal, and the sum of the gate width W L of the load FET Q L and the gate width W C is made equal to the gate width W CS of the current source of the differential amplifier circuit, the voltage V GG supplied to the gate of the clamp FET appears as the low level output. The operation of the differential amplifier circuit in the embodiment of the present invention described above may be stabilized by combining the circuits shown in Fig. 2 and Fig. 3. That is, in the circuit shown in Fig. 3, when the circuit for generating the reference voltage V REF and the clamp level (low level output) V GG is designed by bringing the inverse signal of the input signal IN of the gate of the driving FET Q₂ to the reference voltage V REF , as shown in Fig. 2, if the variations δ V GG , δ V REF due to variations in the temperature and the parameter between the gate potential V GG of the clamp FET Q C1 , Q C2 and the V REF is as shown below: the V REF , which is the threshold value of the differential amplifier circuit, can be placed midway between the high level V DD and the low level V GG , thus preventing a decrease of the noise margin and realizing a stable operation. Further, in addition to the embodiment shown above, a logic construction similar to a conventional CML (current mode logic) may be possible, and an example of a circuit (NOR circuit) having two inputs IN₁ , IN₂ is shown in Figs. 7A and 7B, wherein portions corresponding to those in Fig. 2 and Fig. 3 are denoted by the same symbols or the same symbol with [′]. Further, although in the NOR construction the drive FET Q₁ , Q′₁ ... is arranged in parallel, a series gate construction may be realized. The application of the present invention will be now explained. Figure 8 shows a circuit to which the present invention is applied, where the ECL level is converted by using an Si substrate to a GaAs DCFL (direct-coupled FET logic) level. In the DCFL of GaAs, V SS is the reference voltage of the logic, and thus when V SS is varied, the internal level is changed. On the other hand, in the SiECL, V DD not V SS is used as the logic reference, andthus even if V SS is varied, the internal logic level is not changed. For example, in Si ECL, V cc = 0 "H" level → -0.5 or -0.8 V "L" level → -1.8 V, and in GaAs DCFL, V DD = 0, V EE = -3.6 V, V SS = -2.0 V. Therefore, when the Si integrated circuit and DCFL are connected, a converter circuit must be provided so that a complete interface is obtained by making the input low level from the SiECL following the change of the V SS level in the GaAs DCFL. Figure 8 is a diagram of the converter circuit which is realized by applying a differential amplifier circuit according to the present invention. In Fig. 8, (1) denotes SiECL and (II) the converter circuit to which the differential amplifier circuit according to the presetn invention is applied. Further, (III) is a GaAs DCFL internal circuit, and a load GaAs FET Q LL and a drive FET Q D are shown as one part thereof. P₁ , P₂ designate an output terminal of SiECL, and a differential input IN, and a reverse signal thereof IN or a reference voltage V REF are output from the SiECL and are input to gates of the FET Q i1 and Q i2 of the input circuit of the converter circuit. This input circuit is formed by the FET Q i1 , Q i2 , level shift diodes S D1 , D D2 , and current sources Q j1 , Q j2 , and the input signals are shifted via the diodes S D1 and S D2 and applied to the gates of the drive FET Q₁ and Q₂ of the differential amplifier circuit, as in the embodiment described previously. V SS (V SS of DCFL) is applied to the gates of the clamp FET Q C1 and Q C2 of the differential amplifier circuit. The signal level passed through the differential amplifier circuit rises to V DD in the high level. On the other hand, the low level is clamped and output at a level which is determined by the V SS applied to the gates of Q C1 , Q C2 and a circuit constant of each FET of the differential amplifier circuit. Then, if the circuit constant is suitably determined and the output low level is clamped by V SS , DCFL may be driven by the SiECL level. The condition satisfying the above equation (3) with reference to Fig. 3, may be the gate width (W CS ) of the current source FET = the sum (W L + W C ) of the gate width of the load FET, and the gate width of the clamp FET. For example, W L + W C - W CS = 10 + 10 - 20 or 15 + 5 - 20. Figure 9 shows a relationship between the logic levels in the SiECL and the GaAs DCFL. That is, in the SiECL circuit, the voltage V DD (ground) is used as a reference voltage and V OH and V OL use -0.8 V and -1.8 V, respectively, as the logic high level and the logic low level. In the GaAs DCFL, the low level output of the converter circuit is clamped by a reference level V SS and the threshold level V TH (+0.2 V to V SS ) of the drive FET QD is set based on the reference voltage V SS . Then, if the reference voltage V SS decreases or increases, the low level follows the increase or decrease of the reference voltage V SS , and therefore the internal logic does not change. If the condition of the equation (3) as already mentioned is satisfied, the output low level V L can be made equal to the reference level V SS . Next, an embodiment of another application of the present invention will be described with reference to Fig. 10. This is a circuit for converting the SiECL level to GaAs BFL (buffered FET logic). The symbols used for each portion are the same symbols used for the same portions in Fig. 8. This is a converter circuit (II′) which is formed by adding the level shift circuit (IV) (the same current as the level shift circuit of the GaAs BFL internal circuit), to the same circuit as the converter circuit (II) for the DCFL level in Fig. 8. In Fig. 10, as a portion of the GaAs BFL internal circuit, a gate circuit formed by a drive FET Q LLL , a drive FET Q DD , and a level shift circuit which is formed by a FET Q SS , diode D SS and a current source FET Q SL to convert the output level of the gate circuit, are shown representatively. The BFL is different in that the level shift circuit is provided at the output of the DCFL. In DCFL, if the V th of the drive FET is not (+), switching can not be carried out when the low level is applied to the input, but in BFL, even if the V th of the drive FET is (-), switching is possible because the level shift is carried out by the buffer. This is an advantage in that, in a GaAs IC, when the V th is (-), it is easier to manufacture. The difference in operation is that, in DCFL, the output falls until V OL = V SS when the drive FET is made ON. On the other hand, in the BFL, when the drive FET is made ON, the level in the former stage also falls to V SS . However, as the threshold value of the drive FET is (-), then to make the FET OFF, the low level is made (-) and lower than the threshold value of the drive FET, via the level shift circuit. Therefore, as shown in Fig. 10, the low level output is clamped by the converter circuit (II) to V SS and is output, and this low level is applied to the level shift circuit (IV) by which the low level is made (-) and lower than the threshold value V th of the drive FET, to turn OFF the drive FET (the threshold value V th is (-)). According to the present invention, a similar operation to that of the conventional diode clamp can be realized by the constant voltage type FET, so that the problem occurring in the diode clamp type differential amplifier circuit, that is, the temperature characteristic and the deterioration of the AC characteristic, can be solved, by the following actions. 1. Temperature characteristic As the FET level clamp is not used, the temperature characteristic is not received. Furthermore, the temperature characteristics of the I-V curves of the constant current FET and the FET level clamp are exactly the same, and therefore an advantage is obtained in that the temperature characteristic of the clamp level is cancelled. 2. AC characteristics The capacitances between a source and a drain of the FET and between a gate and a source of the FET are very small when compared to those of the diode, and thus the deterioration of the AC characteristic can be considerably reduced.

Claims: A differential circuit comprising : a first drive FET (Q₁) and a second drive FET (Q₂) each having a gate connected to an input, and sources of said first drive FET and said second drive FET being commonly connected, a constant current FET (Q CS ) being connected between commonly connected sources of said first and second drive FETs and a tow voltage power source, a load circuit for each of the first and second drive FETs (Q₁, Q₂), being provided between the drain of the respective drive FET and a high voltage power source; each of said load circuits comprising a load FET (Q L1 , Q L2 ) the drain of which is connected to said high voltage power source, and the gate and the source are short-circuited and connected to the drain of the respective drive FET (Q₁,Q₂), and output terminals being respectively connected to the drains of said first and second drive FETs (Q₁, Q₂), characterized in that each of said load circuits further comprises a second load FET (Q C1 , Q C2 ), the drain of which is connected to said high voltage power source and the source is connected to the source of said first load FET (Q L1 , Q L2 ), a constant voltage (V GG ), less than the voltage (V DD ) of said high voltage power source, being commonly applied to the gates of said second load FETs (Q C1 , Q C2 ), wherein the source current (I CS ) which flows via the constant current FET (Q CS ) satisfies the following conditions: I L <I CS < I L + I X (V F ) where I L is the current which flows via one first load FET (Q L1 , Q L2 ), and I X (V F ) is the current which flows via one second load FET (Q C1 , Q C2 ) when the forward-bias voltage V F of its gate junction is applied between the gate and the source thereof. A differential circuit according to claim 1, wherein said first load FETs (Q L1 , Q L2 ), said second load FETs (Q C1 , Q C2 ) and said constant current FET (Q CS ) have substantially equal threshold voltage and K value, the K value of a FET being given by the formula K = I/[W(V GS - V th )²] where I is the current flowing via the FET, W is the gate width thereof, V th is the threshold voltage and V GS is the voltage between the gate and the source thereof. A differential circuit according to claim 1 or 2, wherein each of said FETs is formed by a MESFET. An integrated circuit device comprising : a high voltage power source, a low voltage power source and an intermediate voltage power source, the voltage (V GG ) of the latter being comprised between the respective voltages (V DD , V EE ) of the former two power sources, input terminals, and a converter circuit including : a first drive FET (Q₁) and a second drive FET (Q₂) each having a gate connected to a respective input terminal, and sources of said first drive FET and said second drive FET being commonly connected, a constant current FET (Q CS ) being connected between commonly connected sources of said first and second drive FETs and the low voltage power source, a load circuit for each of the first and second drive FETs (Q₁, Q₂), being provided between the drain of the respective drive FET and the high voltage power source; each of said load circuits comprising a load FET (Q L1 , Q L2 ) the drain of which is connected to said high voltage power source, and the gate and the source are short-circuited and connected to the drain of the respective drive FET (Q₁,Q₂), and output terminals being respectively connected to the drains of said first and second drive FETs (Q₁, Q₂), characterized in that each of said load circuits further comprises a second load FET (Q C1 , Q C2 ), the drain of which is connected to said high voltage power source and the source is connected to the source of said first load FET (Q L1 , Q L2 ), said intermediate voltage (V GG ) being commonly applied to the gates of said second load FETs (Q C1 , Q C2 ), wherein the source current (I CS ) which flows via the constant current FET (Q CS ) satisfies the following conditions: I L <I CS < I L + I X (V F ) where I L is the current which flows via one first load FET (Q L1 , Q L2 ), and I X (V F ) is the current which flows via one second load FET (Q C1 , Q C2 ) when the forward-bias voltage V F of its gate junction is applied between the gate and the source thereof, and in that the integrated circuit device further comprises an internal circuit being provided between said high voltage power source and said intermediate power source and providing twice a load FET (Q LL ) and a drive FET (Q D ) in series, each of said output terminals of said converter circuit being connected to the gate of a respective drive FET (Q D ) in said internal circuit. An integrated circuit device according to claim 4, wherein a level shift circuit is provided between the output terminals of said converter circuit and the gates of said drive FETs (Q DD ) of said internal circuit.

Inventors: TOHYAMA, KAY
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: H03F3
IPC codes: H03K19, H03F3