A DISPLAY SCREEN OF MULTIPLE MATRIX CONSTRUCTION

Abstract: Display screen which comprises a plurality of matrices. The display screen is constructed from modules, each of which operates as an independent unit. Each module has a display matrix (2) having picture elements or pixels placed thereon in a two-dimensional grid. The picture matrix has an associated module memory (13). The module memory has written thereinto information concerning those parts of an incoming video signal which are to be shown on the picture matrix in that part of the display screen where the picture matrix is placed. The picture matrix is controlled so as to show video information one whole row at a time and is constructed to steer the rows in a selected sequence. This is effected with the aid of a control arrangement (14, 15) which controls a device (16) having drive stages, one for each picture element along a row, and coupled to receive information from the module memory (13) and an activating arrangement (18) for activating all picture elements in a row to receive information from their respective drive stages. The control arrangement (14, 15) for updating the information shown on the picture matrix operates in a rhythm which is totally independent of the rhythm in which the write-in arrangement writes information into the module memory (13).

Description: A display screen of multiple matrix construction The present invention relates to a display screen of the kind set forth in Claim 1. A number of matrix displays are known to the art, for use in illuminated advertisements (signs), large television screens, etc., in which the individual pixels are illumina¬ ted with the aid of light bulbs or light emitting diodes which are alternatingly ignited and extinguished. The pos¬ sibility of producing display screens of mutually different shapes and sizes is highly desirable, particularly in the advertising field, by which is meant screens of square con¬ figuration, vertically or horizontally extending elongated screens, cruciform screens, and screens of other configura- tions. Another desideratum in this regard relates to the possibility of producing display screens which can readily be adapted to the configuration desired. Another problem relating to matrix displays intended for advertising purposes etc., resides in the time taken to service a defective screen, this time being ideally as short as possible. It is desirable to shorten to a minimum both the on-site service time for each individual display screen and the time needed to carry out a workshop service. Another extremely important desideratum is to obtain a display screen which is as flicker-free as possible. It is, of course, conceivable in this regard to control each pixel separately with the aid of an individual control device and to maintain the light emitting devices or light points con- stantly in an activated state, in addition to those short time periods during which changes in luminance occur. This solution, however, places such high demands on the system used to drive the picture element control devices and on the mutual uniformity between the drive units and the pic¬ ture elements as to render the problems associated herewith almost insurmountable. Displays are known to the art in which the matrix screen is divided into rows and columns, in which each row or alternatively each column is divided into a number of picture elements or pixels, in which a holding circuit is provided for each picture element of one row or for a limited number of rows, and in which there is provided for each row or for each unit of a limited number of rows (or columns) an activator unit which will activate all the picture elements in said one row or in said limited number of rows, while receiving at the same time the sepa-r rate input data stored in all of the holding circuits and steering the row (or column) activator units to activation in a cyclic sequence. An example of such an arrangement for liquid crystal matrix displays is described in US Patent Specification 4,520,302. Even though one whole row (or column) of the display is illumiunated at one and the same time with this known arrangement, there is still obtained nevertheless a certain amount of flicker, which can cause irritation to the viewer, particularly in the case of large displays. It is therefore desirable to reduce the flicker still further. These desiderata are fulfilled with a display screen that has the characteristic features set forth in the characte¬ rizing clause of the following claim 1. Further features of the invention are set forth in the depending claims. The inventive display screen is constructed from a multi¬ plicity of modules, each of which operates as a small indi¬ vidual unit which is in itself a small display screen. Each unit, or module, has an associated maintenance part which registers in sequence on its small individual display screen an image or picture of the information stored in a model memory. The information in the model memory is upda- ted when the incoming video signal is concerned with that part of the total display screen in which the module is located. Only then does the maintenance part cease to ope¬ rate. By constructing the display screen from modules which ope¬ rate as independent units, display screens of mutually dif¬ ferent shapes and sizes can be readily constructed from a plurality of modules of mutually identical construction, and can also be readily serviced by replacing a defective module with a serviceable one. Furthermore, far less flicker is experienced, since each module has its own drive system which updates at its own rhythm all the data shown on the screen, this rhythm being faster than the rate of updating the information in the incoming video signal. The invention will now be described in more detail with reference to the accompanying drawings, in which Fig. 1 is a block schematic illustrating the module con¬ struction and the transfer of signals thereto; Fig. 2 is a block schematic illustrating the video inter¬ face for delivering appropriate data and control signals to the module circuits; Fig. 3 illustrates the fundamental construction of a module circuit; Figs. 4a-4d are diagrams which illustrate a number of sig¬ nals in the inventive circuit; Figs. 5a-5e are diagrams which illustrate various signals in the inventive circuit in a larger time scale than in Figs. 4a-4d; Figs. 6a-6d illustrate further signals in the inventive circuit; Fig. 7 illustrates an embodiment of a module circuit in greater detail than Fig. 3; and Fig. 8 illustrates a further embodiment of the module cir¬ cuit used in accordance with the invention. In the Fig. 1 illustration a video signal which, for exam- * pie, may have the same composition and the same line (or horizontal) and frame (or vertical) frequency as a standard TV-signal, is fed to an interface 1. The function of the interface 1 is to retrieve line-sync and frame-sync infor- mation from the video signal, to divide the video signal into appropriate small time units each representing a pic¬ ture element, to construct an address for each time unit during each frame scan, and to produce for each picture element an output signal suitable for temporary storage in a memory. The interface outputs are connected to respective inputs on each of the modules, said modules having part- picture matrices 2 in the display screen 1. Fig. 2 illustrates one embodiment of an interface 1. A clock signal generator 4 produces a clock signal on a clock signal output. The incoming video signal is fed to a frame- sync sensor 5 which detects the frame-sync component of the video signal and sends a signal to a reset signal out- put. When scanning is interlaced, one signal is transmitted with each frame change and not with each field or part-fra- me change. Thus, the use of interlacing is an optional pos¬ sibility that lies within the scope of the invention. Whether ot not interlacing is used depends to some extent on the purpose for which the screen is intended, e.g. whether the screen is to present television pictures or data text, and also on the input signal contingent thereon. It is, in certain cases, conceivable to construct the screen from a multiple of modules such that solely each alternate line, each third line and so on can be shown. The video signal is also supplied to a line-sync sensor 6, which detects the line-sync component of the video signal. The output signal from the line-sync sensor 6 is fed to a setting input on the clock signal generator 4, such as to set the generator at the beginning of each line. This is done in order to avoid lateral displacement of the picture as a result of small time differentials in the clocking of each line in the picture. The counter unit comprises two counters 7a, 7b in series. The first counter 7a is intended to count as many clock pulses as there are picture element divisions (M) along a line in each part-picture matrix of a module 2, and to pro¬ duce a pulse on the output upon completion of the count. The second counter 7b is intended to receive the pulses from the first counter 7a and to change therewith the count setting with each pulse received from the first counter 7a. The second counter 7b, designated the a. counter, thus has on its parallel outputs a count setting which represents the part-picture matrices 2 in the a-direction (see Fig. 19), designated the a-address for respective modules. The output signal of the line-sync sensor 6 is applied to the reset input of the a-counter 7b, so as to reset the counter 7b to zero in preparation for receiving each new line in the video signal. The output signal from the line-sync sensor 6 is also fed to the setting input of a counter 8a, which counts to the same number as the number of lines in a part-picture matrix 2, before producing a pulse on its own output. The input of a further counter 8b is connected to the output of the first mentioned counter 8a and is stepped forwards with each pulse, and hence the count setting on its parallel output will represent the address in the b-direction (see Fig. 1) for that module concerned with the receipt of video information in the incoming video signal. The video signal is also applied to the input of a conver¬ ter or transducer 9. The output signal from the clock sig¬ nal generator 4 is fed to a clock input on the converter 9. Data representing the grey scale and optionally also the colour information contained in the video signal is supplied to the output or outputs of the converter 9 in rhythm with the clock signal. The converter output may be a parallel output with digital representation of the grey scale or an analogue signal output. Fig. 3 is a block schematic of a module having a part-pic¬ ture matrix comprising M x N picture elements or pixels. M is the number of picture elements contained along one line in the matrix and N is the number of lines. All modules are of mutually similar construction, with the sole exception that one address decoder 10, connected so as to receive on its input the a-address and b-address from the interface, is provided with individual addresses adapted to the loca¬ tions of respective part-picture matrices in the display screen 1. The address decoder 10 namely has stored therein the a- and b-address combination which belongs to that part-picture matrix 2 of the total picture matrix 3 (see Fig. 3) to which the module belongs. The output signal S of the address decoder 10 is high when agreement is found between the incoming address and the stored address, other¬ wise the signal is low (the reverse is also conceivable). Fig. 4a illustrates the video signal fed to the interface 1. Fig. 4b illustrates a suitable reset signal obtained from the frame-sync sensor 5 of Fig. 2. Fig. 4c illustra¬ tes the line-sync signal deriving from the line-sync sensor 6 of Fig. 2. Fig. 4d illustrates the signal S which is obtained from the address counter 10 for that module of modules 2 located in the upper-left hand corner of the screen 3 of Fig. 1 and designated 0.0. Fig. 4a illustrates that part of the frame-sync signal between the time points t, and t~. during which time period the reset signal is negative. Upon termination of the reset signal, the signal pulse S is obtained directly after each line-sync pulse. For instance, when one row con¬ sists of five matrices, each pulse S takes up one fifth of each line-data component of the video signal. It will also be seen from Fig. 4d that no pulses S are obtained prior to the frame change between t, and t 2 , due to the fact that the b-address part of the address signal is not stored in the address decoder 10 for this part of the video sig¬ nal, since video information signals in this case are writ¬ ten into modules located in the lowermost rows of modules ((0,8) - (A,B)) and not in the uppermost rows referred to here by way of example. Fig. 5a illustrates the video signal between the time points X> 2 and t in larger scale than in Fig. 4a. The clock signal is illustrated in Fig. 5b. For the sake of clarity, the clock signal frequency is illustrated in the Figures at a much lower value than its actual value in rea¬ lity. A suitable part-picture matrix of a module includes 1024 pixels, arranged in 32 rows and 32 columns. When the screen is to show colour pictures, each pixel includes three or four light emitting diodes or light bulbs. This means that each module may include 3072 or 4096 light emitting diodes or bulbs. The video signal of the Fig. 4a embodiment is divided into five parts (more clearly seen from Fig. 5d) each of which corresponds to one module of one row. The clock signal illustrated in Fig. 5b has six pulses for each one-fifth of the video input signal instead of 32. The frame informa¬ tion contained in the video signal is illustrated in Fig. 5c in the form of a stepped curve with sampling at each clock pulse. Fig. 5d illustrates those time periods during which respective modules in one row are activated during the video signal period, provided that information relating to a line is to be written into the module concerned. The part-picture matrices 2 of the Fig. 1 embodiment are desig- nated (0,0) - (A,B) where the first digit or character identifies the column (a-direction) and the last digit or character designates the row (b-direction) for the part- picture matrix in the whole picture matrix 3. In Fig. 5d the references 0...A designate respective part-picture matrices along one row. Fig. 5e illustrates the signal S for the module 0,0. In Fig. 3 the clock signal with clock pulses (Fig. 5b) from the interface 1 is supplied to the setting input of a write counter 11. The signal S (Fig. 5e) from the address decoder 10 is applied to an activating input of the write counter 11. The write counter 11 counts upwards for each clock pul¬ se, provided that the signal S is high. The write counters of all the modules are set to zero by the resetting signal from the interface 1. The output from the write counter 11 is preferably a paral¬ lel output SR with digital representation of the count set¬ ting of the counter 11. The signal SR is changed during the duration of the signal S. The output signal SR is applied to the one input of a multiplex unit 12. The output signal S of the address decoder 10 is applied to a control device on the unit 12. When the signal S is high, the multiplex unit 12 connects the input on which the signal SR is found to its output, which is in turn connected to the address input of a module memory 13 containing M x N addresses, i.e. containing as many addresses as the part-picture matrix 2. The output signal S of the address decoder 10 is also coup¬ led to a write input on the module memory 13, which is set to the write mode when the signal S is high. The module memory 13 receives the data signal from the converter 9 in the interface of Fig. 2. During a high signal S, the incom- ing video signal is successively written into the addresses of the module memory 13, said addresses being given by the signal SR. The memory 13 is switched to its reading mode when the signal S is low. The module memory 13 is preferably a digital memory, in which case the converter 9 (Fig. 2) is an analogue/digital converter and the data signal is transferred from the con¬ verter 9 in the form of a digital signal on a parallel con¬ ductor. It is also possible, however, to use an analogue memory for the module memory 13. In this case, the conver¬ ter 9 converts the video signal to appropriate levels for storage in the module memory 13. The data signals are then transmitted over a single conductor. When the signal S is low, the multiplex unit 12 is switched so as to transmit a read address signal LR to the module memory 12, which is then also set to a read-only mode. The incoming video signal is most often taken-up with the line scan, so that information concerning different lines will occur sequentially. It will be understood that incom¬ ing information is written into the memory 13 in the sequence in which it occurs. When reading-out the memory 13 in order to update the picture shown on the part-picture matrix, there is no dependency on the sequence in which the data was written in. This means that there is freedom of 10 choice as to whether whole lines or whole columns are per¬ mitted to be shown in a selected sequence. Fig. 3 illustrates an embodiment with column display, i.e. sequential display of vertical rows which migrate from left to right for example. It is equally as possible, however, to use a desired sequence other than a sequential sequence, for example interlaced display etc. The pulse circuit 14 produces alternating pulse trains and pulse-train interspaces, as will be described in more detail hereinafter (Fig. 6b). Each pulse train includes a number of pulses equal to the number of picture lines (M) . The output signal F of the pulse circuit 14 is fed to a read counter (15) having M x N counting stages. The output signal produced by the read counter 15 is the signal LR, which is applied to the address input of the module memory 13 via the multiplex unit 12. Connected to the data output of the memory 13 is a unit 16 which contains the same amount of part-circuits as the num¬ ber of lines in the part-picture matrix 2. That part of the signal LR which represents the n-component of the address to the module memory 13 is also applied to the unit 16. Each part-circuit in the unit 16 includes a converter part which converts the data content of the addressed cell in the module memory in suitable form for supply to a mainte¬ nance circuit. The maintenance circuit of this embodiment is a latching circuit, in which case the converter circuit is a digital analogue converter. A drive unit 18 has an output for each column in the part- picture matrix 2. That part of the signal LR which repre¬ sents the m-component (i.e. the address component for the line direction) of the address to the module memory 13 is also applied to an address input on the drive unit 18. The 11 drive unit activates that output which corresponds to the incoming address. The signal S is also applied to control inputs on the read counter 15 and on the unit 16, so as to inactivate these circuits during the time period in which information is written into the memory 13. Alternatively, the pulse cir¬ cuit 14 can be inactivated instead of inactivating the counter 15. Thus, each maintenance device in the unit 16 obtains fresh information during each pulse train, this information being shown in a vertical row on the picture matrix determined by the drive unit 18. The time for which a column is illuminated may not be excessively short. Con- seqeuently, the pulse train interspacing is adapted to pro- vide the requisite length of illuminating time. The illumi¬ nating time for a column is equal to l/(updating rate x M) . Updating rates should be 100 times per second and .there- above in order to obtain a picture free from flicker. A suitable illuminating time is roughly 0.3 ms, provided that N = 32. Fig. 7 illustrates a preferred embodiment of a module unit. The illustrated address output MS 0 - MS 7 of the interface 1 is connected to an address decoder 20. The output signal S (Fig. 4d, 5e) is applied to the one input of an AND-gate 21, whereas the clock signal, CLOCK 1, from the interface 1 is applied to the other input of said gate. The output of the AND-gate 21 is connected to a write counter 22, which may be a 10-bit counter for example. The reset signal (RESET) from the interface 1 is connected to the reset input of the counter 22. A multiplex unit 23 is controlled by the signal S to couple the signal SR or the signal LR to its output. The output of 12 the multiplex unit 23 is coupled to the address input of the module unit 24, which is divided into a red, a green and a blue memory section. The converter 9 of the interface 1 herewith divides the video signal into a red, a green and a blue signal and applies each of the three digitalized output signals to a respective parallel databus connected to a respective section of the memory 24. The picture is illustrated in this embodiment line for line in the picture matrix as opposed to the embodiment illu¬ strated in Fig. 3. The databus for the red memory section is also connected to a digital/analogue converter 25. The output of the converter 25 is connected to an analogue mul¬ tiplex unit 26 having a multiple of outputs e.g. 32. A light point drive stage is connected to each output. The control stage of the illustrated embodiment comprises a field-effect transistor 27, the gate electrode connected to the multiplex unit 26, whereas the source electrode is con¬ nected to earth and the drain electrode is connected to all light points one above the other, i.e. with the same line position in all the lines of the part-picture matrix 2. A holding capacitor 28 is connected between the gate and the source electrode. The databus intended for the green memory is similarly connected to a digital/analogue converter 29, the output of which is connected to an analogue multiplex unit 13 of the same type as the multiplex unit 26 and hav¬ ing the same type of driving stage for each light point. The databus intended for the blue memory is similarly con¬ nected to a digital/analogue converter 31, the output of which is connected to an analogue multiplex unit 32 of the same kind as the multiplex unit 26. Preferably the light emitters from which a pixel is comprised are located in a square so that there is one red, one green and two blue light points. For this reason a double drive unit compris- ing two field-effect transistors 33 and 34 is coupled in a similar manner to the field-effect transistor 27 from each 13 output line on the multiplex unit 32. The drain electrode of the transistor 33 is connected to the one blue light point B, and the drain electrode of the other transistor 34 is connected to the other blue light point B . The three multiplex units 26, 30 and 32 are steered simultaneously by an address signal LOW on an address input. The signal LOW is the m-address component of the signal LR which is coupled to the address input of the memory 24 via the multiplex unit 23. This m-address component arrives from the output of an m-address counter 35. Then M = 32, for example, the counter 35 is a 5-bit counter and is arranged to count from zero to 31. The coun¬ ter is set to zero at 32. The counter 35 counts the pulses arriving from an oscillator 36, these pulses being supplied to the counter 35 via two AND-gates 37 and 38. The output signal CLOCK 2 of the oscillator 36 is illustrated in Fig. 6c. The operating mode of the AND-gates will be described in more detail hereinafter. The AND-gate 38 receives the signal S from the address decoder 20 on an inverted input, so that the signal S is blocked during that period in which information is written into the memory 24. When the counter 35 is set to zero by the 32nd pulse in a series of pulses from the oscillator 36, the counter sends a "l"-signal to the resetting input of an RS flip-flop 39, via a separate output. The Q output of the flip-flop is then low. The output of the flip-flop is connected to an input on the AND-gate 37, wherewith the AND-gate will no longer allow pulses from the oscillator 36 to pass through. The output signal F from the gate 37 is shown in Fig. 6b. The Q-output of the RS flip-flop is, at the same time, set to "1". The Q-output is connected to the one input of an AND-gate 40, the output of the oscillator 36 being connec¬ ted to the other input of said AND-gate. The AND-gate 40 will then allow the pulses, CLOCK 2 from the oscillator 36, shown in Fig. 6, to pass to its output, which is connected 14 to a counter 41. The counter 41 counts a large number of pulses, e.g. 384, before it produces a "l"-signal on its output. The counter 41 is the counter which maintains the signal between each pulse train, as beforementioned. The signal Q is shown in Fig. 6c. The "l"-signal from the counter 41 is fed to the input of an n-address counter 42, which then counts up one step. The "l"-signal from the counter 41 is also fed to the setting input of the SR flip-flop 39, so that the flip-flop is reset and so that the Q-signal becomes high and the Q-sig- nal becomes low. The AND-gate 37 will then again allow the signal CLOCK 2 from the oscillator 36 to pass through, whereas the AND-gate 40 blocks the signal CLOCK 2 prevent- ing the signal from being fed to the counter 41 and the cycle which commences by counting up the address counter 35 is recommenced. The output signal Q from the flip-flop 39 is illustrated in Fig. 6c. The output signal on the n-address counter 42 is the n-part of the LR-signal. The output signal from the n-address counter 42 is fed to the address input of an analogue mul¬ tiplex unit which has many outputs, e.g. 32, for activation of the row in the picture matrix 2 given by the n-address. Also shown is an example of drive means for a whole " row. Fig. 6d illustrates that the lines 0.1 ... are activated successively. The drive means includes an NPN-transistor Tl with the base connected to the one output of the multiplex unit 43, the emitter connected to earth and the collector connected to the Junction point of-two resistors Rl and R2. Since each pixel includes four light points which are pla¬ ced in two lines, each output of the multiplex unit 43 dri¬ ves two part-lines in the picture matrix, of which the one includes the right points R,G for red and green signals and the others contain the two blue light points B-, , B . Consequently, two PNP-transistors T and T-, the bases 15 of which are connected to the collector of the transistor T, , via a respective resistor Rl, R2 and the emitters of which are connected to a respective voltage source VI, V2. The collector of one transistor T is connected to the R,G-line whereas the collector of the other transistor T, is connected to the B, , B -line in a line containing M pixels, each of which pixels comprises four light points arranged in two part-lines. Fig. 8 illustrates an embodiment of the invention in which the maintenance circuit is pulse-ratio-modulated. In this embodiment the pulse-ratio-modulated circuit operates with a multiple of cycles with cyclic rotation and with simulta¬ neous illumination of all light points of a column. Another type of pulse-ratio-modulated circuit, e.g. with separate individual illumination of each light point in the row or column during illumination point by point is also fully possible, but not preferred. Large parts of the circuit illustrated in Fig. 8 coincide with the circuit illustrated in Fig. 3. These previously described parts of the circuit have been identified with the same references and will not be described further. The maintenance circuit includes a pulse oscillator 44, the output pulses of which are fed to a read counter 45, which incorporates a series of counters connected in cascade. The first counter is a line counter 46 which is stepped forward in a cyclic sequence by the pulses emanating from the oscillator 44. This output signal is the n-address, i.e. the line-address in this embodiment. The other counter is a level counter 47 which counts in the reverse direction, from a high level N, which may be 64 for example, down to zero, and is stepped backwards in a cyclic sequence once for each counting cycle of the row counter 46. The third counter is a column counter 48 which is stepped forwards in 16 cyclic sequence once for each cycle of the level counter * 47. The output signal from the counter 48 is the m-address i.e. the column address in this embodiment. This sequence of the counters is provided when simultaneous activation of all the light points in a column is wanted. If separate activation point by point is wanted the counters 46 and 47 shall be interchanged. The address signal for the module memory 13 is composed of mutually combined row and column signals. The oscillator 44 produces an output signal continuously, except when the signal S from the address decoder 10 is activated. The oscillator 44 will thus remain inactive during the period in which fresh information is written into the module memo- ry 13. The output from the level counter 47 is fed to one input of a digital comparator 49. The digital value on the address in the memory 13 given by the signal LR is fed to the other input of the comparator 49. The comparator 49 produces an "l"-signal each time that the two signals present on the comparator input are equal, or otherwise it produces a "0". The output of the comparator 49 is- fed to the input of a digital multiplex unit 50, i.e. a multiplex unit which transmits a digital signal. The multiplex unit 50 has as many latch circuits as there are rows in the picture matrix 2. The output signal from the row counter 46 is applied to the switching input of the multiplex unit 50. All latch cir¬ cuits are set to zero by a signal appearing on a resetting input of the unit 50, when the count setting of the level counter 57 is zero. Each latch circuit in the unit 50 is connected to a separate row-drive element in a row-drive unit 51. Each row-drive element is connected to a respec- tive row in the picture matrix 2. The output signal from the column counter 48 is applied to the input of a column drive unit 52 which activates one column at a time in the picture matrix 2. The maintenance arrangement in Fig. 8 functions in the following manner: When a new column in the picture matrix 2 has been newly activated by the column drive unit 52, the output of the level counter has the value N and the output of the row counter 46 the value "0", which represents the uppermost row. At the same time, the signal LR points to correspond¬ ing pixel addresses in the picture memory and the picture information is fed to the second input of the comparator 49 and compared with the prevailing value of the level counter 47. When the two values are equal, the latch circuit in the unit 50 is set to the first row, but not otherwise. As soon as a latch circuit is set, the latch circuit will maintain its associated row-drive unit activated during the remain¬ der of the prevailing level counter cycle. The values of the respective output signals on the level counter and the module memory 13 are compared with one another by the comparator 49, successively from the top and downwards, in order to ascertain whether or not all the pixels in the column concerned have the highest luminance, corresponding to the value N in the level counter 47, whereupon the level counter 47 counts downwards one step to N-l, and the cycle of the row counter 46 is repeated and a comparison made by the comparator 49 for the nearest lower luminance. The level counter then counts down a further step, etc., until the count setting of the level counter is zero. When the column counter 48 counts up one step and when the level counter has been set to the value N by the row counter 46, the whole working procedure is repeated for the next column in the picture matrix and for the memory content corresponding to this column in the module memory 13. This results in pulse-ratio-modulation, since the light points shine at full luminance when they are ignited, although the time during which they are illuminated within the activation time for the column to which they belong varies in accordance with the grey scale, so that the light emitted by a light point becomes brighter to the viewer the longer the light point is ignited within the column activa- ting interval. It will be understood that the module unit circuit illu¬ strated in Fig. 8 can be constructed to provide a multi¬ colour picture, in full analogy with the circuit illustra- ted in Fig. 7. In this case, the D/A converters 25, 29, 31 are replaced with comparators, one input of which is con¬ nected to the level counter 47 and the other input to the memory section of memory 24 intended for respective colours. The multiplex units 26, 30, 32 for transmitting analogue signals are replaced with multiplex units for transmitting digital signals, these units being arranged to control a multiple of latch circuits which, when activated, hold a light point ignited, optionally via some further coupling means, such as a transistor, until the circuits have been reset by a signal produced when the level counter has counted down to zero. Many modifications are possible within the scope of the invention. In the description above it has been stated that the main¬ tenance circuit to update the picture works with one column at the time and lets the lightened part of the picture move from the left to the right, for example, in a cyclic sequence. It is evident, however, that the maintenance cir¬ cuit can work with one line at the time as well and then 19 let the lightened part of the picture move from the top to the bottom, for example, in a cyclic sequence.

Claims: 20 CLAIMS 1. A display screen of the kind in which picture elements or pixels are placed in a two-dimensional grid and in which, for the purpose of producing a total picture, the video signal is arranged to be written continuously into a memory for storage of individual picture elements, element for element, and in which a picture recording device col¬ lects, In a cyclic sequence, from the memory information relating to one whole row or one whole column at a time and activates the picture elements in said row or column in accordance with the information stored in the memory, ch¬ aracterized in that the display screen is constructed from a multiple of modules, each of which operates as an inde¬ pendent unit and each of which includes a small, individual module display screen (2) of the kind set forth in the preamble and having its own individual separate control arrangement; in that the memory for the whole display screen is divided into separate memory units, of which one module memory (13; 24) is arranged for each module; in that a write arrangement (10, 11; 20-22) is provided for each module memory, said write arrangement being intended to detect those time intervals in which the incoming video signal relates to the picture region of the modules and to write in response thereto information pertaining hereto into appropriate parts of the module memory; in that there is provided for each module a separate maintenance arrange¬ ment (14-18; 25-43; 44-52) which is intended to activate the picture elements in a cyclic sequence in rows or columns in the module display screens in accordance with the information written into the module memory, indepen- dently in relation to the write arrangement and to remain¬ ing modules. 21 2. A display screen according to Claim 1, characterized in that the write arrangement is arranged to stop the function of the maintenance arrangement temporarily during the time in which information is written into the memory. 3. A display screen according to Claim 1, characterized in that while information is written-into the memory, the write arrangement is arranged to prevent temporarily address signals sent from the maintenance arrangement to the module memory from reaching said memory. 4. A display screen according to any of the preceding claims, characterized in that the maintenance arrangement is intended to steer the drive stages at a rate which is faster than the rate in which the write arrangement writes information into the module memory (13; 24). 5. A display screen according to any of the preceding claims, characterized in that the maintenance arrangement is constructed so as to feed addresses to the module memory (24) in sequences of the same number of successive addres¬ ses as the number of picture elements along a row or column and with a pause prior to commencing the next sequence for activating the next row or column, said pause being adapted to a predetermined time duration for maintaining a row or column in the module display screen (2) in an illuminated state. 6. A display screen according to any of the preceding claims, characterized in that each maintenance arrangement has a drive stage for each pixel or picture element along one row or column; in that each drive stage includes an analogue/digital converter (25, 29,31) connected to the databus of the module memory (24) and a holding circuit (27,28) connected to a respective light point along one row or column; and in that all holding circuits obtain a 22 changed level in sequence during each sequence of succes¬ sive addresses sent to the module memory (24) from the maintenance arrangement, said level being held until the next address sequence. 5 7. A display screen according to any of Claims 1-5, charac¬ terized in that the maintenance arrangement operates in accordance with the principle of pulse-ratio-modulation, so that with each time period of illumination of one row or 10 column in the module picture matrix each separate picture element in said row or column is maintained in an illumina¬ ted state during a time period which is located within this interval and which is proportional to the content of the module memory for said picture element (Fig. 8). T5 8. A display screen according to Claim 7, characterized in that during each time interval in which a row or column is illuminated successively in cyclic sequence, the mainte¬ nance arrangement is intended to compare cyclicly and 20 successively for each picture element in the whole row or the whole column data stored in the module memory for the picture image concerned against a value which represents a luminance value, and in that for the first cycle interval said comparison is made with a value which corresponds to 25 the highest luminance and the comparison value is stepped down by one integer for each cycle, down to zero at the end of the interval; and in that each picture element along one row or one column is associated with a latch circuit which is set to zero at the beginning of said interval and which 0 is set to "1" when said comparison is true and which thereafter maintains the picture element in an illuminated state during the remainder of said interval.

Inventors: GRAFSTROEM MATS, GRAFSTROEM, MATS
Applicants: COMVIEW AB
Application year: 1987
Main classification: G09F9
IPC codes: G06F3, G09F9, G09G3