DYNAMIC RANDOM ACCESS MEMORY HAVING TRENCH CAPACITOR

Abstract: A random access memory having a trench capacitor in­ cludes: a semiconductor substrate (21); a trench (24) formed in the semiconductor substrate; an insulating layer (41) formed on an inner surface of the trench and having a bottom opening; a first conductive layer (25) formed at the bottom opening posi­ tion and on the insulating layer (41), the first conductive layer being ohmically connected to the semiconductor substrate (21) at the bottom opening. The device further includes a di­ electric layer (26) formed on the first conductive layer (25) and a second conductive layer (27) formed on the dielectric layer so as to fill the trench (24); the first conductive layer (25), the die­ lectric layer (26), and the second conductive layer (27) con­ stituting a charge storage capacitor (SC); and a MIS transistor (TR) formed in the semiconductor substrate, wherein the sec­ ond conductive layer (27) is ohmically connected to a source or drain region (29A, 29B) of the MIS transistor (TR).

Description: The present invention relates to an information storage device and, more particularly, to a dynamic random access memory (DRAM) having a trench capacitor. In a previous DRAM cell having a trench capacitor, a charge storage capacitor is connected to a MIS transistor between a source or drain region and an inversion layer, and the inversion layer on the substrate side serves as a charge storage electrode for storing information charges. A charge storage capacitor of an adjoining cell is formed near each DRAM cell through an isolation layer. In this case, a depletion layer may extend through the substrate to cause a punch-through between cells. A trench capacitor cell of this type has an advantage of a high integration, compared with a memory cell of a planar type, but has the following problems. The first problem is that of a punch-through between cells in the capacitors. In order to reduce a write voltage loss caused by a decrease in a write voltage due to the presence of a threshold voltage, an impurity concentration of a substrate must be lowered. However, when the impurity concentration is excessively low, a depletion layer can extend further to cause a punch-through cells between the trench capacitors of adjacent cells. These capacitors are then electrically coupled to lose information stored in the cells, which degrades the reliability of the memory system. In a so-called Hi-C capacitor structure wherein a region having a conductivity type opposite to that of the substrate is formed on the wall surface in a trench, the write voltage loss can be reduced. However, the distance between the adjacent trench capacitors is reduced by a diffusion depth of the region having the opposite conductivity type, thus increasing the possibility of the punch-through between cells. In this case, an ion implantation or diffusion process must be used for doping an impurity into a trench side wall thus increasing difficulties in memory fabrication. The second problem is that of soft errors. A large depletion layer extends from a storage electrode (i.e., an inversion layer) in a substrate, and minority carriers generated in the depletion layor or the substrate can be easily captured in the depletion layer and injected into the storage electrode, thus causing a soft error when α-rays are incident on the memory cell. The third problem is that of the write voltage loss. The charge storage capacitor uses a capacitor formed between a cell plate and an inversion layer of a MOS structure formed in the trench. Accordingly, the maximum write voltage obtained corresponds to a difference between a power supply voltage and a threshold voltage for forming the inversion layer for a voltage applied to the cell plate. More specifically, the maximum voltage available for writing a "HIGH" level is lower than the power supply voltage by about 1 V. JP-A-59 141 262 discloses a memory cell structure in which a groove is formed in a substrate, a centre portion of the groove being filled by a first conductive layer and side portions being filled by second conductive layers belonging to adjacent memory cells. Insulating layers separate the conductive layers and line the surface of the groove. This structure has limited dielectric strength around the second conductive layers, leading to a low yield. EP-A-0 149 799 discloses a memory cell structure in which trench capacitors of adjacent memory cells are formed side-by-side, a diffused layer being formed on the side walls of each trench so as to surround a storage electrode. This structure is liable to punch through between the diffused layer and a source or drain of the adjacent memory cell transistor. According to a first aspect of the invention, there is provided a dynamic random access memory having a trench capacior, comprising:- a semiconductor substrate; a trench formed in said semiconductor substrate; an insulating layer formed on an inner surface of said trench; a first conductive layer, a dielectric layer and a second conductive layer formed in said trench, said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor formed in said semiconductor substrate, wherein said second conductive layer is ohmically connected to a source or drain region of said MIS transistor; wherein said trench has an opening at its bottom, characterised in that:- said first conductive layer is formed at the position of said opening and on said insulating layer, thereby being ohmically connected to said semiconductor substrate at said opening, an upper end of said first conductive layer being located lower than the top of said trench so as to prevent said first conductive layer from being exposed outside said trench; said dielectric layer is formed on said first conductive layer, and said second conductive layer is formed on said dielectric layer so as to form a storage electrode filling said trench; and in that said first conductive layer is made of polycrystalline silicon and constitutes an electrode cell plate which surrounds said storage electrode formed by said second conductive layer in an integrated form on said insulating layer, but does not cover said storage electrode in the vicinity of the top of said trench. According to a second aspect of the invention, there is provided a dynamic random access memory having a trench capacitor, comprising:- a semiconductor substrate of one conductivity type; a trench formed in said semiconductor substrate; an insulating layer formed on an entire inner side surface of said trench; a first conductive layer, a dielectric layer and a second conductive layer formed in said trench, said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor formed in said semiconductor substrate; wherein said second conductive layer of said charge storage capacitor is ohmically connected to a source or drain region of said MIS transistor; characterised in that:- said insulating layer has a thickness which allows a passage of carriers therethrough by a tunnel phenomenon; said first conductive layer is formed on said insulating layer and maintained at the same potential as that of said semiconductor substrate through said insulating layer, the top of said first conductor layer being located lower than the top of said trench for preventing said first conductive layer from being exposed outside said trench;; a dielectric layer is formed on said first conductive layer, said second conductive layer being formed on said dielectric layer and being of the other conductivity type to said substrate. An embodiment of the present invention may provide a dynamic random access memory having an improved trench capacitor. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 is a side sectional view of a previously proposed capacitor cell; Figs. 2 and 3 are respectively a plan view and a side sectional view illustrating a trench capacitor cell according to an embodiment of the present invention; Figs. 4A to 9A are plan views showing steps in manufacturing the trench capacitor cell shown in Figs. 2 and 3; Figs. 4B to 9B are sectional views showing steps in manufacturing the trench capacitor cell shown in Figs. 2 and 3; Figs. 10 and 11 are respectively a plan view and a side sectional view illustrating a trench capacitor cell according to another embodiment of the present invention; Figs. 12A to 17A are plan views showing the steps in manufacturing the trench capacitor cell shown in Figs. 10 and 11; Figs. 12B to 17B are sectional views showing the steps in manufacturing the trench capacitor cell shown in Figs. 10 and 11; Figs. 18 and 19 are respectively a plan view and a side sectional view illustrating a trench capacitor cell according to still another embodiment of the present invention; Fig. 20 is a plan view showing a pattern of a buried layer and a trench according to the embodiment shown in Figs. 18 and 19; Figs. 21 to 26 are sectional views showing the steps in manufacturing the embodiment shown in Figs. 18 and 19; Figs. 27 and 28 are a plan view and a side sectional view illustrating a trench capacitor cell according to still another embodiment of the present invention; Figs. 29A to 34A are plan views showing the steps in manufacturing the trench capacitor cell shown in Figs. 27 and 28; and Figs. 29B to 34B are sectional views showing the steps in manufacturing the trench capacitor cell shown in Figs. 27 and 28. A previous type trench capacitor cell will be described with reference to Fig. 1, to distinguish the present invention more clearly and to give a better understanding of the present invention. Figure 1 is a sectional view showing this trench capacitor cell. Referring to Fig. 1, reference numeral 11 denotes a p type silicon (p type Si) substrate as a semiconductor substrate; 12, a silicon dioxide (SiO₂) layer serving as a field insulating layer for defining the cell area; 13, electrons in an inversion layer serving as a charge storage electrode; 14, a dielectric layer; and 15, a cell plate (counter electrode) of polycrystalline silicon (poly-Si) layer. The inversion layer 13, the dielectric layer 14, and the cell plate 15 constitute a charge storage capacitor. Reference numeral 16 denotes a gate dielectric layer; 17, a poly-Si word line; and 18A and 18B, high impurity regions serving as n⁺ type source or drain regions. The source or drain regions 18A and 18B and the word line 17 serving as the gate constitute a MIS transistor. A bit line 19 made of, e.g., aluminum (Al), is formed to be in contact with the source or drain region 18A on the substrate and extends in a direction perpendicular to the word line 17. In this case, the charge storage capacitor is connected to the MIS transistor between the source or drain region 18B and the inversion layer 13. Therefore, the inversion layer 13 on the substrate side serves as a charge storage electrode for storing information charges. Each DRAM cell is formed away from a charge storage capacitor of an adjacent cell through the field insulating film 12. The broken line represents the boundary of a depletion layer extending within the substrate. Fig. 1 shows a state wherein a punch-through between cells in the adjacent capacitor has occurred. A trench capacitor cell of this type has an advantage of a high integration, compared with a cell of a planar type, but has the following disadvantages: (1) a punch-through between cells in the adjacent capacitors (2) soft errors and (3) a write voltage loss can easily occur. The present invention attempts to solve the above problems and will be described in detail with reference to preferred embodiments below. Figure 2 is a plan view illustrating a trench capacitor cell according to a first embodiment of the present invention, Fig. 3 is a side sectional view thereof, Figs. 4A to 9A are plan views showing the steps in manufacturing the trench capacitor cell, and Figs. 4B to 9B are sectional views thereof. Figs. 10 and 11 are respectively a plan view and a side sectional view illustrating a trench capacitor cell according to another embodiment of the present invention, Figs. 12A to 17A are plan views showing the steps in manufacturing the trench capacitor cell in Figs. 10 and 11, and Figs. 12B to 17B are sectional views thereof. Referring to Figs. 2 and 3, reference numeral 21 denotes a p type Si substrate as a semiconductor substrate; 23, an SiO₂ layer serving as a field insulating layer for defining a cell area; 24, a trench formed so as to include a field region; and 41, a SiO₂ insulating layer having a side wall thickness of 100 to 500 Å (10Å = 1nm) and defining the capacitor area. Reference numeral 25 denotes a cell plate (a counter electrode) of p⁺ type poly-Si formed in the entire area of the trench having the SiO₂ insulating layer 24, except for the area near the opening of the trench. The cell plate 25 is in contact with the substrate at the bottom of the trench. The cell plate serves as a first conductive layer. Reference numeral 26 denotes a dielectric layer made of silicon nitride (Si₃N₄); and 27, a charge storage electrode of an n⁺ type poly-Si serving as a second conductive layer. The cell plate 25, the dielectric layer 26, and the charge storage electrode 27, all of which are defined by the SiO₂ insulating layer 41, constitute a charge storage capacitor. Reference numeral 28 denotes an SiO₂ layer serving as a gate dielectric layer. Reference numerals 29A and 29B, n⁺ type source or drain (S/D) regions; 29C, an n⁺ type region formed simultaneously with the source or drain regions 29A and 29B; 30A, a word line (i.e., a gate electrode) of a self cell (this cell) which is made of titanium silicide (TiSi₂); and 30B, a word line of a cell adjacent to the self cell. The p type Si substrate 21, the gate dielectric layer 28, the n⁺ type S/D regions 29A and 29B, and the word line 30A constitute a transistor (i.e., a cell transistor) of the self memory cell (i.e. of this cell). Reference numeral 31 denotes an SiO₂ insulating layer; 32A, a third conductive layer made of an n⁺ type poly-Si layer; and 32B, an n⁺ type poly-Si layer as a third conductive layer electrically connecting a transistor S/D region, e.g., 29B, to the charge storage electrode 27 of the charge storage capacitor. The third conductive layer 32B connects the charge storage capacitor to the cell transistor to constitute a DRAM cell. Reference numeral 33 denotes an insulating interlayer; 34, a wiring contact hole; and 35, a bit line made of aluminum (Al) which is in contact, with the S/D region 29A through the third conductive layer 29B and which is formed on the insulating interlayer and extends in a direction perpendicular to the word line. In the trench capacitor cell according to the present invention, the source or drain region 29B of the transistor is electrically connected to the charge storage electrode 27 through the third conductive layer 32 (32B). The second conductive layer 27 in the trench 24 serves as a charge storage electrode for storing information charges. The first conductive layer 25 on the substrate side serves as a cell plate (i.e., a counter electrode). The functions of these conductive layers are reversed to those in the previous arrangement. The above structure prevents the spread of the depletion layer in the substrate, and thus coupling (interference) between the adjacent capacitors can be eliminated. The third conductive layer, i.e., the n⁺ type Si layer 32 (32B) for connecting the S/D region 29B of the transistor to the charge storage electrode 27 of the charge storage capacitor can be formed by self alignment with the word line by growing the conductive layer on an Si surface exposed between the word lines 30A and 30B without using a mask process. Therefore, micropatterning and a high packing density of the cells can be achieved. In the structure according to the present invention, since the insulating layer 31 is formed on the side wall surface of the trench to define the capacitor region, a decrease in impurity concentration in the first conductive layer can be desirably prevented. Such a decrease occurs in the subsequent oxidation process or annealing process after the formation of the S/D regions 29A and 29B wherein impurity ions are diffused, from the p⁺ type poly-Si layer (the first conductive layer) 25 having a high concentration of about 10¹⁹ cm⁻³, i.e., the cell plate (the counter electrode) having a high impurity concentration and formed on the inner surface of the trench, to the p type Si substrate around the trench 24. Therefore, a decrease in charge storage capacitance of the capacitor, which is caused by formation of a depletion layer at the interface between the p+ type poly-Si layer (the first conductive layer) 25 and the dielectric layer 26, is prevented. In the above structure, the first conductive layer (the cell plate) 25 is ohmically connected to the substrate 21 in the opening of the capacitor defining SiO₂ insulating layer 31 formed in the bottom of the trench and is kept at the same potential as that of the substrate 21. A method of manufacturing the trench capacitor cell according to this embodiment will be described with reference to the plan views of Figs. 4A to 9A and the sectional views of Figs. 4B to 9B as well as Figs. 2 and 3. As shown in Figs. 4A and 4B, for example, an Si₃N₄ layer (or a composite layer of Si₃N₄ an SiO₂) 22 is formed as an antioxide film for selective oxidation on an element formation region on the surface of the p type Si substrate 21. The Si substrate 21 is oxidized using the Si₃N₄ layer 22 as a mask to form a 4,000 Å thick SiO₂ layer 23 as a field insulating layer. As shown in Figs. 5A and 5B, using the conventional photolithographic techniques and reactive ion etching (RIE), a trench 24 having a depth of 3 to 4 µm is formed in the antioxide region including part of the field insulating layer 23. Thermal oxidation is then performed to form a capacitor area defining an SiO₂ insulating layer 41 having a thickness of 300 Å on the inner surface of the trench 24. The thickness of the layer 41 is not limited. However, if the thickness is excessive, the effective size of the trench is reduced. Therefore, the thickness of the layer 41 is preferably less than 1,000 Å. The SiO₂ insulating layer 41 at the bottom of the trench 24 is selectively removed by an anisotropic etching means such as reactive ion etching (RIE) which is effective in the vertical direction of the substrate surface. Therefore, an opening 42 is formed in such a manner that the surface of the p type Si substrate 21 is exposed. As shown in Figs. 6A and 6B, a 1,000 Å thick p⁺ type poly-Si layer is formed by doping arsenic ions having a high concentration by CVD in the entire surface of the substrate including the inner surface of the trench 24. Isotropic etching (e.g., plasma etching) is performed to leave a p⁺ type poly-Si layer 25 on only the inner wall surface of the trench 24. The p⁺ type poly-Si layer 25 is in contact with the p type Si substrate 21 at the bottom of the trench 24 through the opening 42 of the SiO₂ layer 41. The p⁺ type poly-Si layer 25 aims at forming a high-impurity region on the wall surface of the trench 24 such a manner that the high-impurity region has the same potential as that of the substrate 21, thereby using the substrate portion as the cell plate (i.e., the counter electrode). The p⁺ type poly-Si layer 25 is formed on the SiO₂ insulating layer 41 to define the side wall surface of the trench 24. In the subsequent annealing of the fabrication process, the doped impurity atoms (boron atoms in this case, if an n type substrate is used, the impurity atoms are arsenic or phosphorus atoms) are not diffused and scattered into the substrate 21. The p⁺ type poly-Si layer, i.e., the cell plate 25, is kept as a high-impurity region. Therefore, a decrease in capacitance caused by formation of a depletion layer can be prevented when the p⁺ type poly-Si layer is used as a capacitor electrode. After the antioxide film 22 used in selective oxidation is removed, a 100 Å thick Si₃N₄ layer (or a composite film of the Si₃N₄ and SiO₂ layers) 26 as a dielectric layer is formed by oxidation or growth on the entire surface, including the inner surface of the trench 24, with the p⁺ type poly-Si layer 25. It is known that a dielectric withstand voltage of the layer 25 is increased when the layer 25 is annealed in an oxygen atmosphere. As shown in Figs. 7A and 7B, an arsenic- or phosphorus-doped n⁺ type poly-Si layer is grown on the substrate 21 including the trench 24 to sufficiently fill the trench. The poly-Si layer on the substrate is selectively removed by an isotropic etching means, thereby forming an n⁺ type poly-Si layer 27 which is completely layer 26. The n⁺ type poly-Si layer 27, i.e., the second conductive layer, serves as a charge storage electrode. As shown in Figs. 8A and 8B, the dielectric layer 26 outside the trench 24 is removed to expose the surface of the Si substrate 21. The surface of the substrate 21 is oxidized according to the conventional method of forming a MOS transistor. The MOS transistor of each cell is formed, and a 280 Å thick SiO₂ layer 28 is formed as a gate insulating layer for peripheral circuit MOS transistors. In this case, when oxidation is performed at a low temperature of 900°C, the thickness of the SiO₂ layer 28 on the surface of the p⁺ type poly-Si layer (the charge storage electrode) 27 becomes about 6000 Å. A material serving as a gate material, such as titanium silicide (TiSi₂), having a thickness of about 2,000 Å is deposited on the major surface, i.e., the surface having the elements. A 1,000 Å thick SiO₂ layer 31A is formed on the gate electrode and is patterned to form a TiSi₂ word line pattern having the SiO₂ layer 31 thereon. An SiO₂ layer 31B having a thickness of about 1,500 Å is formed on the major surface. The SiO₂ layer 31A or 31B is left on the upper and side surfaces of the word line pattern by the anisotropic etching means (the conventional technique), thereby forming TiSi₂ word lines 30A and 30B covered with the SiO₂ layer 31 (31A and 31B) serving as the insulating layer. In this case, the surface of the poly-Si layer 27 on the Si substrate 21 not covered with the word line and the surface of the poly-Si layer 27 surrounded by the trench are exposed. Using the word line (the gate electrode) 30A as a mask, arsenic ions are implanted according to a conventional method to form n⁺ type source or drain regions 29A and 29B. An n⁺ type impurity region 29C is formed in the n⁺ type poly-Si layer 27 filled in the trench 24. As shown in Figs. 9A and 9B, a 4,000 Å thick arsenic- or phosphorus-doped n⁺ type poly-Si layer is formed on the substrate by a selective deposition method. In this case, the poly-Si layer is not grown on the SiO₂ layers 31 and 23. Third conductive layers 32A and 32B of n⁺ type poly-Si are formed on the Si surface portion at the source or drain region 29A and 29B and the n⁺ type poly-Si layer 27, i.e., the charge storage electrode. The n⁺ type poly-Si layer is not grown on the exposed dielectric layer 26 and the ends of the capacitor defining SiO₂ layer 41. However, the thickness of the n⁺ type poly-Si layer is less than 200 Å, so that the poly-Si layer on the source/drain region 29B is continuous with the poly-Si layer on the charge storage electrode 27 to constitute the third conductive layer 32B. Therefore, the source/drain region 29B is electrically connected to the charge storage electrode 27. As shown in Figs. 2 and 3, an insulating interlayer 33 is formed on the entire surface of the substrate according to the conventional method, and a contact hole 34 is formed on the source or drain region 29A at a position where th bit line is in contact with the cell. A bit line 35 made of aluminum or the like is formed on the source or drain region 29 through the contact hole 34. The memory cell of this embodiment has the following advantages. The counter electrode, i.e., the cell plate of the charge storage capacitor is formed in the substrate itself, and more specifically, on the insulating layer formed on the side wall surface of the trench. The counter electrode is in contact with the substrate in the bottom of the trench and is defined as a conductive layer having the same potential as that of the substrate through the contact portion. Accordingly, when the substrate is grounded, the counter electrode potential is very stable. In other words, a decrease in operating margin caused by a so-called voltage bump as well as operation errors do not occur. The substrate serves as a large electrode plate having a uniform potential distribution. Even if adjacent capacitors are close together, the substrate does not cause interference between these adjacent capacitors. The interference is defined by charge leakage caused by a punch-through between cells between the capacitors and by a stored charge change given such that the adjacent capacitors are in contact with each other through a depletion layer and charging or discharging of one capacitor influences the operation of another capacitor by electrostatic coupling. The charge storage electrode is surrounded by an insulating layer (the dielectric layer) and the depletion layer does not extend into the substrate. Soft errors thus do not occur. The charge storage capacitor has a structure of an n⁺ type poly-Si layer, a dielectric layer, and a p⁺ type poly-Si layer. An inverting layer is not used, and thus a write voltage loss does not occur. The capacitor is buried under the source or drain regions of the MIS transistor due to the structural feature of the memory cell. The size of the memory cell can be greatly reduced, to that corresponding to one transistor, compared with the previous type memory cell. At the same time, the cell plate is not formed on the substrate, unlike in the previous type memory cell. Also, alignment margins for the cell plate with the capacitor and the transistor need not be considered, thereby further reducing the size of the memory cell. The counter electrode of the charge storage capacitor comprises a ploy-Si layer having a high impurity concentration and formed on the inner surface of the trench formed in the substrate. The poly-Si layer is in selective contact with the side wall surface of the trench through the thin insulating layer. This poly-Si layer is maintained at the same potential as that of the substrate from the electrical viewpoint. However, the impurity of diffusion from the side wall surface of the trench into the substrate is prevented. Even after annealing is performed, there is very little decrease in the impurity concentration of the poly-Si layer. In the capacitor consisting of the n⁺ type semiconductor, the dielectric layer, and the p⁺ type semiconductor, when a voltage is applied to the storage electrode, a depletion layer is formed in the semiconductor substrate. If the n⁺ and p⁺ type ion concentrations are low, the depletion layer overlaps the dielectric layer. The effective charge storage capacitance is undesirably reduced depending on the voltage. However, according to the structure of the present invention, the impurity concentration of the counter electrode is not decreased, and thus a decrease in capacitance by the formation of the depletion layer can be prevented. The cell plate is formed in the substrate, but not formed on the substrate. The word line running next to the word line of the cell is in contact with the charge storage electrode through a thin oxide film equivalent to the gate oxide film, thereby generating a capacitive coupling. In the DRAM, when a given word line is selected, the next word line is basically clamped to the ground potential. The charge storage capacitance of the cell is slightly increased by the capacitive coupling. Figures 10 and 11 are respectively a plan view and a side sectional view illustrating a trench capacitor cell according to another embodiment of the present invention. In this structure, a memory cell is formed in an n well on a p substrate. Referring to Fig. 10 and 11, reference numeral 36 denotes an n well; 107, a charge storage electrode of p⁺ type poly-Si serving as a second conductive layer buried in the trench through a dielectric layer; 109A and 109B, p⁺ type S/D regions, respectively; 109C, a p⁺ type region formed together with the source or drain region; 112A, a third conductive layer of a p⁺ type poly-Si layer; and 112B, a p⁺ type poly-Si layer serving as a third conductive layer which electrically connects the source or drain region, e.g., 109B to the charge storage electrode 107 of the charge storage capacitor. The above structure can be also applied to a semiconductor substrate having a p type well on an n type substrate. In this case, the conductivity type of the conductive layers and the source or drain region is opposite to that in Fig. 3. A method of manufacturing the trench capacitor cell according to this embodiment will be described below. The n well 36 having a depth of about 2 µm is formed in a p type Si substrate 21. Following the same procedures as in Fig. 4, an Si₃N₄ layer 22 is formed on an element formation region of the n well 36. Using the Si₃N₄ layer 22 as a mask, thermal oxidation is performed to form a 4,000 Å thick field SiO₂ layer 23 (Fig. 12). Following the same procedures as in the previous embodiment using RIE, a trench 24 having a depth of 3 to 4 µm reaching the p type substrate 21 is formed in an antioxide region including part of the field insulating layer 23. Thermal oxidation is then performed to form a 300 Å thick SiO₂ insulating layer 41 on the inner wall surface of the trench 24 to define the capacitor region. The SiO₂ insulating layer 41 at the bottom of the trench 24 is selectively removed by RIE to form an opening 42 so as to expose the surface of the p type Si substrate 21 (Fig. 1). Subsequently, a 1,000 Å thick boron-doped p⁺ type poly-Si layer 25 is formed on the inner wall surface of the trench 24. The p⁺ type poly-Si layer 25 is electrically connected to the p type Si substrate 21 at the bottom of the trench 24 through the opening 42 of the SiO₂ layer 41. A 100 Å thick Si₃N₄ layer (or an SiO₂ layer, or a composite film of the Si₃N₄ and SiO₂ layers) 26 as a dielectric layer is formed by oxidation or growth on the entire surface including the inner wall surface of the trench 24 having the p⁺ type poly-Si layer 25 (Fig. 14). A p⁺ type poly-Si layer 107 serving as a charge storage electrode is completely filled in the trench 24 through the dielectric layer 26 (Fig. 15). The dielectric layer 26 exposed outside the trench 24 is removed to expose the surface of the n well 36. A gate SiO₂ layer 28 is formed on the surface of the n well 36 according to the conventional formation method of MOS transistors. For example, TiSi₂ word lines 30A and 30B covered with an SiO₂ layer 31 (31a and 31b) serving as an insulating layer are formed on the gate SiO₂ layer 28. Subsequently, using a word line (a gate electrode) 30A exposed on the n well 36 as a mask, boron ions are implanted to form p⁺ type source or drain regions 109A and 109B. In this case, a p⁺ type impurity region 109C is formed in a p⁺ type poly-Si layer 107 filled in the trench 24 (Fig. 16). Selective depostion method is performed to form third conductive layers 112A and 112B of p⁺ type poly-Si on the exposed Si surface at the source or drain regions 109A and 109B and the p⁺ type region 109c on the p⁺ type poly-Si layer 107. The poly-Si layer on the source or drain region 109A is continuous with the poly-Si layer on the charge storage electrode 107. The source or drain region 109 is thus electrically connected to the charge storage electrode 107 (Fig. 17). According to a conventional method, an insulating interlayer 33 is formed to cover the entire surface of the substrate. A contact hole 34 is formed in the source or drain region 109A at a position where the bit line is in contact with the cell. A bit line 35 made of aluminum or the like is formed. The resultant memory cell according to this embodiment has the following further advantages. Since the well receives a voltage by a bias generator or the like, the voltage tends to be unstable. When the counter electrode of the capacitor is in contact with the well, the voltage of the charge storage electrode of the capacitor is changed according to a change in well voltage, thereby reducing the reliability of charge storage information. However, in the structure according to this embodiment, the trench extends through the well and reaches the substrate. Therefore, the counter electrode is electrically connected to the substrate, having a stable potential. The potential of the charge storage electrode of the capacitor does not vary according to disturbance, and thus the reliability of storage information is improved. In addition, since the counter electrode and the charge storage electrode have the same conductivity type, a depletion layer is not formed in the counter electrode. As a result, the effective storage capacitance is not decreased. The present invention can be also applied to a DRAM cell having a conductivity type opposite to that of this embodiment. Still another embodiment of the present invention will be described with reference to Figs. 18 and 19. Figure 18 is a plan view of this embodiment and Fig. 19 is a side sectional view thereof. Figure 20 is a plan view showing a buried layer and trench pattern inside the substrate, and Figs. 21 to 26 are sectional views for explaining the steps in manufacturing this embodiment. Referring to Figs. 18 and 19, reference numeral 51 denotes a p type silicon (p type Si) substrate serving as a semiconductor substrate; 52, an n⁺ type buried layer having an impurity concentration of about 10¹⁹ cm⁻³; 53, a p type epitaxial layer; 54, a field SiO₂ layer defining a cell region; 55, a trench formed to include the field region, the bottom of the trench 55 reaching the buried layer 52; 56, an SiO₂ insulating layer having a thickness of about 800 to 1,000 Å and formed on the side wall surface of the trench 55; 57, a charge storage capacitor counter electrode on an n⁺ type poly-Si layer having a thickness of about 1,000 Å and a concentration of about 10¹⁹ cm⁻³; 58, a charge storage capacitor dielectric layer having a thickness of about 150 Å and made of Si₃N₄ or the like; and 59, a charge storage capacitor electrode having an impurity concentration of about 10¹⁹ cm⁻³ and made of an n⁺ type poly-Si layer. The charge storage capacitor of the memory cell consists of the counter electrode (the cell plate) 57 formed on the SiO₂ insulating layer 56 formed on the wall surface of the trench 55 and having a lower portion ohmically connected to the n⁺ type buried layer 52 within the trench 55, the dielectric layer 58 formed on the cell plate 57 in the trench 55, and the charge storage electrode 59 of the n⁺ type poly-Si layer. Reference numeral 60 denotes an SiO₂ layer serving as a gate dielectric layer; 61A, a word line (a gate electrode) of a self cell, made of a titanium silicide (TiSi₂) layer or the like; 61B, a word line of an adjacent cell; 62, an SiO₂ insulating layer having a thickness of about 1,000 Å; 63A and 63B, n⁺ type source or drain (S/D) regions each having an impurity concentration of about 10¹⁹ cm⁻³; and 63C, an n⁺ type region simultaneously formed with the S/D regions. The p type Si substrate 51, the gate SiO₂ layer 60, the word line 61A, and the S/D regions 63A and 63B constitute a transistor (a cell transistor) of the memory cell. Reference numeral 64A denotes a third conductive layer made of, e.g., titanium silicide; and 64B, a third conductive layer made of titanium silicide and serving to connect the S/D region 59B of the charge storage electrode 57 to the charge storage electrode 57 of the charge storage capacitor. Therefore, the charge storage capacitor is electrically connected to the cell transistor by the third conductive layer 64B to constitute a DRAM cell. Reference numeral 65 denotes an SiO₂ insulating interlayer having a thickness of about 8,000 Å; 66, a wiring contact hole; and 67, a bit line made of aluminum (Al) which is in contact with the S/D region 64B through the n⁺ type poly-Si layer 66 and the third conductive layer 64B and which extends in a direction perpendicular to the word line 62 (A and B) on the insulating interlayer 65. Figure 18 is a plan view illustrating the pattern of the trench capacitor cell according to this embodiment. Fig. 20 is a plan view illustrating the buried layer and trench pattern which corresponds to the pattern of Fig. 18. As shown in Figs. 18, 19, and 20, in the trench capacitor cell according to the present invention, the S/D region 63B of the transistor is electrically connected to the second poly-Si layer 59 of the charge storage capacitor through the third conductive layer 64B. Therefore, the second poly-Si layer 59 filled in the trench serves as a charge storage electrode for storing an information charge. The first poly-Si layer 57 surrounding the second poly-Si layer 59 serves as the counter electrode. The arrangement of these capacitor electrodes is reverse to that of the previously proposed memory cells. The n⁺ type buried layer 52 is selectively formed on the p type Si substrate 51 as a semiconductor substrate subjected to the formation of memory cells. The p type Si epitaxial layer 53 is formed on the p type Si substrate 51, and the resultant substrate is used as a bulk substrate. The charge storage capacitor extends through the p type Si epitaxial layer 53 and reaches the n⁺ type buried layer 52. The capacitor consists of the counter electrode 57 of the n⁺ type poly-Si layer formed on the SiO₂ insulating layer 56 on the side wall surface of the trench 55, the dielectric layer 58 formed on the entire surface on the counter electrode 57 in the trench, and the charge storage electrode 59 of n⁺ type poly-Si filled in the trench 55 through the dielectric layer 58. The trench capacitor is surrounded by the capsule-like SiO₂ insulating layer 56 formed on the side wall surface of the trench 55 and is insulated from the p type Si epitaxial layer 53 through the SiO₂ insulating layer 56. The n⁺ type buried layer 52 electrically insulated from the p type Si substrate 51 and the p type Si epitaxial layer 53 serves as the conventional cell plate, i.e., the conventional wiring layer for supplying a voltage to the counter electrode 57. A method of manufacturing the trench capacitor cell according to this embodiment will be described with reference to the sectional views of Figs. 21 to 26 and Fig. 19. Arsenic ions (Ar) are implanted at a high dose of about 10¹⁶ cm⁻² into the p type Si substrate 51 having a resistivity of about 1 Ωcm by using a mask pattern (not shown). The implanted ions are activated to form the n⁺ type buried layer 52 (Fig. 21). The p type Si epitaxial layer 53 having a thickness of about 2 to 3 µm and a resistivity of about 10 Ωcm is formed on the substrate. For example, an Si₃N₄ layer (or a composite film of the Si₃N₄ and SiO₂ layers) 71 as an antioxide film for selective oxidation is formed on an element formation region. Using the layer 71 as a mask, the surface of the p type Si epitaxial layer 53 is oxidized for form a 4,000 Å thick field SiO₂ layer 54 (Fig. 22). Using the conventional photolithographic techniques and reactive ion etching (RIE), a trench 55 is formed in the antioxide region including part of the field insulating layer 54 in such a manner that the bottom thereof reaches the buried layer 52. Subsequently, a capacitor region defining SiO₂ insulating layer 56 having a thickness of about 800 Å is formed on the inner wall surface of the trench 55 by thermal oxidation. The thickness of the insulating layer 56 is not specified. However, if the thickness is excessive, the effective size of the trench is reduced. Therefore, the thickness is preferably less than 1,000 Å. The SiO₂ insulating layer 56 at the bottom of the trench 55 is selectively removed by RIE to expose the n⁺ type buried layer 52 (Fig. 23). A 1,000 Å thick n⁺ type poly-Si layer is formed by CVD to cover the entire surface including the wall surface of the trench 55. Anisotropic etching (RIE) is performed to remove the n⁺ type poly-Si layer on the surface of the substrate. In this case, the counter electrode 57 comprising the first n⁺ type poly-Si layer is left on the side wall surface of the trench 55. Thereafter, slight wet or plasma etching is performed to remove the poly-Si layer near the opening of the trench 55. Upon etching, the upper end of the counter electrode 57 is removed by 0.5 µm from the opening of the trench 55. This is to increase the dielectric breakdown strength of the capacitor (Fig. 24). When the above etching is completed, the first n⁺ type poly-Si layer may be left on the exposed surface of the buried layer 52 at the bottom of the trench 55. The lower portion of the n⁺ type Si counter electrode 57 is electrically connected to the n⁺ type buried layer 52. The surface of the counter electrode 57 is oxidized (not shown) by a thickness of 50 Å, and a 100 Å thick dielectric layer 58 of an Si₃N₄ layer is formed on the substrate surface including the inner surface of the trench 55. It is known that the dielectric breakdown strength of the dielectric layer is improved by annealing in an oxygen atmosphere. An arsenic- or phosphorus-doped second n⁺ type poly-Si layer is grown on the substrate including the wall surface of the trench 55 having the dielectric layer 58 and is etched by an anisotropic etching means, thereby forming the charge storage electrode 59 of the second n⁺ type poly-Si layer completely fitted in the trench 55 through the dielectric layer 58. In this case, the charge storage electrode can be formed in only the trench 55 in a self-aligned manner without using masking. Therefore, the occupying area of the trench capacitor can be reduced. Subsequently, the dielectric layer 58 exposed on the substrate is removed, and the Si₃N₄ layer 71 formed for selective oxidation is removed. The active region constituting the transistor and the upper surface of the charge storage electrode 59 filled in the trench 55 are exposed. As described above, the upper end portion of the counter electrode 56 is removed from the opening of the trench 55. Even if the charge storage electrode 59 is slightly overetched, the upper end of the counter electrode 57 does not appear on the surface, and as a result a decrease in capacitor dielectric breakdown strength does not occur, and a short circuit of the capacitor is not formed (Fig. 25). The surface of the p type Si epitaxial layer is oxidized by the conventional formation method of MOS transistors. A 220 Å thick SiO₂ layer 60 is formed as a gate dielectric layer for the MOS transistor of the memory cell and MOS transistors of the peripheral circuits. In this case, when oxidation is performed at a low temperature of about 900°C, the SiO₂ layer 60 on the surface of the p⁺ type poly-Si charge storage electrode 59 has a thickness of about 600 Å. A gate material such as a titanium silicide (TiSi₂) layer having a thickness of about 2,000 Å is formed on the major surface and is patterned to form TiSi₂ word lines 61A and 61B. A 1,000 Å thick SiO₂ insulating layer 62 is formed on the surface of the word lines 61A and 61B according to a known technique. Arsenic ions are selectively implanted into the surface of the p type Si epitaxial layer 53 and the charge storage electrode 59 by using the word line (the gate electrode) 61A as a mask, thereby forming n⁺ type S/D regions 63A and 63B. At the same time, an n⁺ type impurity region 63C filled in the trench 55 is formed. The surfaces of the S/D regions 63A and 63N and the n⁺ type (impurity-doped) region 63C of the charge storage electrode 59 are exposed by a means such as wet etching. A 1,000 Å thick titanium (Ti) layer is formed on the substrate by sputtering. The titanium layer is annealed and selectively converted into a silicide layer. The remaining Ti layer is selectively etched to obtain titanium silicide (TiSi₂) third conductive layers 64A and 64B. In this case, the S/D region 63B is closed to the n⁺ type (impurity-doped) region 63C, and the integral third conductive layer 64B is formed thereon. As a result, the n⁺ type S/D region 63B is electrically connected to the n⁺ type charge storage electrode 59 (Fig. 26). The third conductive layer may be formed by selectively growing poly-Si on the surface of the silicon substrate. According to conventional methods, an insulating interlayer 65 is formed to cover the entire surface of the substrate. A wiring contact hole 66 is formed in the source or drain region 63A at a position where the bit line is in contact with the cell. A bit line 67 made of aluminum or the like is formed. The resultant trench capacitor cell shown in Figs. 18 and 19 has the following advantages. Since the n⁺ type buried layer 52 serves as the power supply line (the cell plate) for the counter electrode 57 of the capacitor, the cell plate need not be formed on the surface of the substrate. The alignment margin for the transistor and the cell plate need not be considered, and the size of the memory cell can be greatly reduced. Since the buried layer 52 is formed deep in the substrate, the relative positional relationship between the buried layer 52 and the gate of the transistor need not be considered. A wide buried layer can be formed, and only rough alignment is required to bring the capacitor region into contact with the buried layer 52. Therefore, use of the buried layer 52 does not interfere with the micropatterning of the memory cell. Since the charge surrounded by the counter electrode 59 of the capacitor is surrounded by the counter electrode 57, an electric field generated by the charge storage electrode 59 is shielded and does not leak outside the cell. Even if the adjacent memory cells are close to each other, an intercell interference such as a punch-through between cells does not essentially occur. The depletion layer does not extend in the substrate, i.e., the p type Si epitaxial layer. Therefore soft errors caused by α-rays can be greatly reduced. The high-impurity counter electrode 57 is surrounded by the insulating layer 56 and is in contact with the bulk substrate, i.e., the p type Si epitaxial layer 53 through the insulating layer 56. The impurity ions within the counter electrode are not diffused or scattered in the substrate. Even if annealing is performed, the impurity concentration of the counter electrode 57 is not degraded. The decrease in capacitance caused by the formation of the depletion layer within the counter electrode 57 can be prevented. The counter electrode 57 of the capacitor is electrically insulated from the substrate, i.e., the p type Si epitaxial layer 53 through the capsule-like insulating layer 56. The counter electrode 57 is powered by the buried layer 52 electrically insulated from the substrate through a junction. Therefore, a voltage can be independently applied to the counter electrode. For example, a voltage of 1/2 the cell transistor logical amplitude voltage applied to the charge storage electrode 59 of the capacitor can be applied to the counter electrode 57 through the buried layer 52. The voltage applied to the dielectric layer 52 is substantially 1/2 the logical amplitude voltage. The margin of the dielectric breakdown strength of the dielectric layer is increased. Therefore, reliability of the capacitor can be improved, and hence the service lift thereof can be prolonged. When a structure is taken into consideration wherein the counter electrode is not electrically insulated from the substrate and the substrate itself serves as the counter electrode (i.e., the cell plate). This structure has a disadvantage in that the potential of the counter electrode is a reverse-biased substrate potential V BB (e.g., -3 V) so that a large voltage obtained by adding the logical amplitude voltage of about 5 V to the reverse-biased component is applied to the dielectric layer of the capacitor, thereby greatly shortening the service lift of the capacitor. In the memory cell shown in Figs. 18 and 19, the capacitor consists of an n⁺ type poly-Si layer, a dielectric layer, and another n⁺ type poly-Si layer. In this manner, since an inverting layer is not used, a write voltage loss does not occur. Since the capacitor is formed under the source or drain regions of the MIS transistor, the size of the memory cell substantially corresponds to one transistor, thus greatly reducing the cell area as compared with the previously proposed type cell. The present invention can be also applied to an DRAM having a conductivity type opposite to that of the above embodiment. In the memory cell of Figs. 18 and 19, there is provided a DRAM cell having a trench capacitor structure which allows micropatterning and a high packing density. At the same time, the impurity concentration of the counter electrode of the capacitor is not decreased during annealing, thus preventing a decrease in charge storage capacitance. In addition, the amplitude of the voltage applied across the charge storage electrode and the counter electrode of the capacitor can be reduced to prolongs the service life of the capacitor and improve the reliability thereof. Still another embodiment of the present invention will be described with reference to Figs. 27 and 18. Figure 28 is a sectional view of this embodiment, Figs. 29A to 34A are plan views for explaining the steps in manufacturing the trench capacitor cell, and Figs. 29B to 34B are sectional views thereof. Referring to Figs. 27 and 28, reference numeral 81 denotes an n type Si substrate serving as a semiconductor substrate; 83, an SiO₂ layer serving as a field insulating layer defining the cell area; 84, a trench formed including the field region; 85, a first conductive layer which is formed on the entire area excluding a region near the opening of the trench and which serves as a cell plate (a counter electrode) made of n⁺ type poly-Si; 86, a dielectric layer made of silicon nitride (Si₃N₄); 87, a second conductive layer which is filled in the trench through the dielectric layer and which serves as a charge storage electrode made of p⁺ type poly-Si; and 101, an SiO₂ layer of a thin tunnel insulating layer which has a thickness of about 20 to 60 Å and which allows transmission of the carriers but not impurity atoms. The cell plate 85, the dielectric layer 86, and the charge storage electrode 87 constitute the charge storage capacitor. Reference numeral 88 denotes an SiO₂ layer serving as a gate dielectric layer; 89A and 89B, p⁺ type source or drain (S/D) regions, respectively; 89C, a p⁺ type region simultaneously formed with the source or drain regions; 90A, a word line (a gate electrode) of a self cell, which is made of a titanium silicide (TiSi₂) layer; and 90B, a word line of an adjacent memory cell. The n type Si substrate 81, the gate dielectric layer 88, the p⁺ type S/D regions 89A and 89B, and the word line 90A constitute a transistor (i.e., a cell transistor) of the memory cell. Reference numeral 91 denotes an SiO₂ insulating layer; 92A, a third conductive layer made of a p⁺ type poly-Si layer; 92B, a third conductive layer of a p⁺ type poly-Si layer for electrically connecting the S/D region, e.g., 89B of the transistor to the charge storage electrode 87 of the capacitor, thereby connecting the charge storage capacitor to the cell transistor to constitute a PRAM cell; 93, an insulating interlayer; 94, a wiring contact hole; and 95, a bit line of aluminum (Al) which is in contact with the S/D region 89A through the third conductive layer 89A and which extends on the insulating interlayer in a direction perpendicular to the word line. In the trench capacitor cell of Figs. 27 and 28, the S/D region 89B of the transistor is electrically connected to the charge storage electrode 87 of the charge storage capacitor through the third conductive layer 92 (92B). The second conductive layer 87 in the trench 84 serves as a charge storage electrode for storing an information charge, and the first conductive layer 85 on the substrate side serves as a cell plate (i.e., a counter electrode). This configuration is reversed to that of the previously proposed type memory cell. The p⁺ type poly-Si layer 92 (92B), i.e., the third conductive layer for connecting the S/D region 89B of the transistor to the charge storage electrode 87 of the capacitor is selectively deposited on the exposed Si surface between the word lines 90A and 90B. The layer 92 can be self-aligned without using a mask process. Micropatterning and a high packing density of the cell can be achieved. In the memory cell shown in Figs. 27 and 28, the very thin tunnel SiO₂ layer 101 is formed on the entire wall surface of the trench and has a thickness of, for example, about 20 Å. The layer 101 allows transmission of carriers therethrough but controls diffusion of the impurity atoms into the substrate. The first conductive layer, i.e., an n⁺ type poly-Si layer as the cell plate (the counter electrode) having the same conductivity as that of the substrate 81 and a high impurity concentration of about 10¹⁹ cm⁻³ is formed on the entire wall surface of the trench through the tunnel SiO₂ layer 101. In the memory cell shown in Figs. 27 and 28, even if annealing is performed as a subsequent process for forming the S/D regions 89A and 89B, diffusion of the impurity atoms from the cell plate 85 to the substrate 81 is prevented by the tunnel SiO₂ layer 101, thereby preventing a decrease in impurity concentration of the cell plate 85. The decrease in capacitor capacitance caused by the formation of a depletion layer at the interface between the dielectric layer 86 and the tunnel SiO₂ layer 101 can be thus prevented. As described above, since the carriers can pass through the tunnel SiO₂ layer 101, the potential of the cell plate 85 is the same as that of the substrate 81. A method of manufacturing the memory cell in Figs. 27 and 28 will be described with reference to the plan views of Figs. 29A to 34A and the sectional views of Figs. 29B to 34B as well as Figs. 27 and 28. For example, an Si₃N₄ layer (or a composite film of Si₃N₄ and SiO₂ layers) 82 as an antioxide film for selective oxidation is formed on an element formation area on the surface of the n-Si substrate 81. The Si substrate 81 is oxidized using the Si₃N₄ film as a mask to form a 4,000 Å thick SiO₂ layer 83 serving as a field insulating layer (Figs. 29A and 29B). Using photolithographic techniques and reactive ion etching (RIE), a trench 84 having a depth of 3 to 4 µm is formed in an antioxide region including part of the field insulating layer 83. Thermal oxidation is then performed to form a 20 Å thick tunnel SiO₂ layer 101 on the inner wall surface of the trench 84. The tunnel SiO₂ layer 101 serves as an insulating layer having a thickness that will allow majority carriers (electrons) to flow as a tunnel current through the semiconductor (Si) substrate 81 (Figs. 30A and 30B). The tunnel insulating layer may be made of another material such as Si₃N₄ if it allows tunneling of the carriers therethrough. The tunnel layer has a maximum thickness of about 60 Å if an SiO₂ layer is used as the tunnel layer. A 1,000 Å thick phosphorus-doped n⁺ type poly-Si layer is formed by CVD on the entire substrate surface including the inner wall surface of the trench 84. Isotropic etching (plasma etching) is performed to leave the n⁺ type poly-Si layer 85 in only the trench 84 (Fig. 31). In this case, the poly-Si layer 85 at the opening of the trench is slightly etched. This slight etching is preferable to improve dielectric breakdown strength between the poly-Si layer 85 and the source or drain regions to be formed to constitute junctions therewith. The formation of the n⁺ type poly-Si layer 85 within the trench aims at formation of a high-impurity region within the trench so as to provide the same conductivity type as that of the substrate thereto. The n⁺ type poly-Si layer 85 allows a substrate portion to serve as the cell plate (the counter electrode). Since only the very thin insulating layer which allows passage of the carriers therethrough is formed between the n⁺ type poly-Si layer 85 and the n type Si substrate 81, the layer 85 is electrically connected to the substrate 81. As a result, the n⁺ type poly-Si layer 85 has the same potential as that of the substrate 81. A defect may be caused by an accidental pinhole in the very thin insulating layer. However, the n⁺ type poly-Si layer (the cell plate) 85 can be electrically connected to the substrate 81 even through such a defect. The formation of the very thin tunnel layer aims at preventing diffusion of the impurity ions from the cell plate 85 into the substrate, and hence preventing a decrease of the impurity concentration of the cell plate in the subsequent heat cycles such as the formation of the source or drain regions and the reflow of the insulating interlayer. The formation of the very thin tunnel insulating layer is aimed at preventing the following; a decrease in impurity concentration of the cell plate 85, i.e., the n⁺ type poly-Si layer, that causes the formation of the depletion layer in the surface layer of the poly-Si layer 85, and thereby decreases the capacitance of the capacitor. The tunnel insulating layer prevents the passage of the impurity atoms therethrough. Even if a pinhole is formed in the tunnel insulating layer, the number of impurity atoms diffused through the pinhole is small, and most of the impurity atoms remain in the poly-Si layer 85. For this purpose, an Si₃N₄ layer is suitable for the insulating material, since the Si₃N₄ layer has a narrower band gap than that of the SiO₂ layer and thus the carriers tend to easily pass through the film. At the same time, the Si₃N₄ film texture is denser than the SiO₂ film to provide a better prevention of the transmission of the impurity atoms therethrough. When a p-type substrate is used, the impurity atoms to be doped in the cell plate are boron ions since they are light in weight. Therefore, the Si₃N₄ layer which is denser than that of the SiO₂ film is suitable for the tunnel insulating layer. A 100 Å thick Si₃N₄ layer (or an SiO₂ layer, or a composite film of the SiO₂ and Si₃N₄ layers) 86 as a dielectric layer is formed by oxidation or growth to cover the entire surface including the inner wall surface of the trench 84 having the n⁺ type poly-Si layer 85. It is known that the dielectric breakdown strength of this film can be improved by annealing in an oxygen atmosphere. A boron-doped p⁺ type poly-Si layer having a thickness sufficient to fill the trench is formed on the substrate 81 including the trench 84. Isotropic etching is performed to selectively remove the poly-Si layer from the substrate, thereby forming the p⁺ type poly-Si layer 87 filled in the trench 84 through the dielectric layer 86. The p⁺ type poly-Si layer 87, i.e., the second conductive layer serves as the charge storage electrode (Fig. 32). The dielectric layer 86 exposed outside the trench 84 is removed to expose the surface of the Si substrate 81. The surface of the substrate 81 is oxidized according to the conventional method of forming MOS transistors, thereby forming a 280 Å thick SiO₂ layer 88 as the gate dielectric layer. In this case, oxidation is performed at a low temperature of about 900°C, and the thickness of the SiO₂ layer 88 on the surface of the p⁺ type poly-Si layer (the charge storage electrode) 87 is about 600 Å. A gate material such as titanium silicide (TiSi₂) having a thickness of, e.g., about 4,000 Å, is formed on the major surface having elements thereon. An SiO₂ layer 91A having a thickness of about 1,500 Å is formed on the titanium silicide film and is patterned to form a TiSi₂ word line pattern having the SiO₂ layer 91A thereon. Another SiO₂ layer 91B having a thickness of about 1,500 Å is formed. The SiO₂ layer 91A or 91B is left on the upper and side surfaces of the word line pattern according to the anisotropic etching means (the known techniques), thereby forming the TiSi₂ word lines 90A and 90B covered with the SiO₂ layer 91 (91A or 91B) serving as the insulating layer. The Si substrate 91 not covered with the word line and the surface of the poly-Si layer 87 filled in the trench 84 are exposed to the outer atmosphere. Boron ions are selectively implanted by a conventional method using the word line (the gate electrode) 90A as a mask, and thus the p⁺ type S/D regions 89A and 89B are formed. At the same time, the p⁺ type impurity-doped region 89C is formed in the p⁺ type poly-Si layer 87 filled in the trench (Figs. 33A and 33B). A 4,000 Å thick boron-doped p⁺ type poly-Si layer is selectively grown on the substrate according to the conventional selective deposition means. The poly-Si layer is not grown on the SiO₂ layers 91 and 83. The third conductive layers 92A and 92B are formed on the exposed Si surfaces of the S/D regions 86A and 86B and the p⁺ type poly-Si layer 87, i.e., the p⁺ type region 89C, on the upper surface of the charge storage electrode. The p⁺ type poly-Si layer is not grown on the ends of the dielectric layer 86 and the tunnel SiO₂ layer 101. The thickness of the SiO₂ layer 101 is 200 Å. The poly-Si layer on the S/D region 86B is continuous with the poly-Si layer on the charge storage electrode 87 to constitute the third conductive layer 92B. Therefore, the S/D region 89B is electrically connected to the charge storage electrode 87. The insulating interlayer 93 is deposited to cover the entire surface according to the conventional method. A contact hole 94 is formed in the S/D region 89A at a position where the bit line contacts the cell. A bit line 95 made of aluminum is then formed. The memory cell shown in Figs. 27 and 28 has the following advantages. The counter electrode, i.e., the cell plate of the charge storage capacitor is formed on the substrate, more specifically on the substrate through the tunnel insulating layer, to allow easy passage of the carriers according to a tunnel effect. The cell plate has the same potential as that of the substrate through the tunnel insulating layer, and the same conductivity type as that of the substrate. Accordingly, when the substrate is grounded, the counter electrode potential is stabilized, and as a result, a decrease in operating margin caused by a so-called voltage bump as well as operation errors does not occur. The substrate serves as a large electrode plate having a uniform potential distribution. Even if the capacitors are close together, interference therebetween does not occur. The interference indicates that charge leakage by a punch-through between cells in the capacitors and an electrical contact between the adjacent capacitors through a depletion layer cause charging or discharging of one capacitor to influence the operation of another capacitor, thereby changing the amount of storage charge. The charge electrode is surrounded by the insulating layer and the depletion layer does not extend in the substrate. Memory operation errors due to the interference between cells do not occur. Since the charge storage capacitor has a structure of an n⁺ type poly-Si layer, a dielectric layer, and a p⁺ type poly-Si layer, and any inversion layer is not used, write voltage loss does not occur. Since the capacitor is formed below the S/D regions of the MIS transistors due to the structural convenience of the memory cell, the cell can be greatly reduced to a size corresponding to that of one transistor, as compared with the previously proposed cell. Unlike in the previously proposed memory cell, the cell plate need not be formed on the substrate, and since alignment margins for the cell plate, the capacitor and the transistor need not be considered, the size of the resultant memory cell can be further reduced. In the capacitor having the structure of an n⁺ type semiconductor, a dielectric layer, and a p⁺ type semiconductor, a depletion layer is formed in the substrate when a voltage is applied to the charge storage electrode. When the n⁺ type or p⁺ type concentration is low, the depletion layer overlaps the dielectric layer. The storage capacitance is undesirably reduced depending on the magnitude of the voltage. In the memory cell of Figs. 27 and 28, however, the counter electrode serving as the information storage section of the capacitor is the second conductive layer of a high impurity concentration formed on the wall surface of the trench through the tunnel insulating layer. Even if the same voltage applied to the substrate is applied to the second conductive layer through the tunnel insulating layer, the impurity atoms do not substantially pass through the insulating layer. Therefore, in subsequent annealing, the impurity atoms are not diffused into the substrate, and the impurity concentration of the counter electrode is not decreased. A decrease in storage capacitance caused by the formation of the depletion layer on the surface of the counter electrode does not occur. In addition, the storage capacitance does not change depending on the magnitude of the voltage. The present invention is not limited to the particular embodiments described above, in that the present invention is also applicable to a DRAM cell having a trench capacitor structure formed in an epitaxial layer or a well. The present invention is also applicable to a DRAM cell having a conductivity type opposite to that of the above embodiments.

Claims: A dynamic random access memory having a trench capacitor, comprising:- a semiconductor substrate (21, 51, 81); a trench (24, 55, 84) formed in said semiconductor substrate; an insulating layer (41, 56) formed on an inner surface of said trench; a first conductive layer (25, 57, 85), a dielectric layer (26, 58, 86) and a second conductive layer (27, 107, 59, 87) formed in said trench, said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor (TR) formed in said semiconductor substrate, wherein said second conductive layer (27, 107, 59, 87) is ohmically connected to a source or drain region of said MIS transistor (TR); wherein said trench (24, 55, 84) has an opening (42) at its bottom; characterised in that:- said first conductive layer (25, 57, 85) is formed at the position of said opening and on said insulating layer (41, 56), thereby being ohmically connected to said semiconductor substrate (21, 51, 81) at said opening, an upper end of said first conductive layer (25, 57, 85) being located lower than the top of said trench so as to prevent said first conductive layer from being exposed outside said trench; said dielectric layer (26, 58, 86) is formed on said first conductive layer (25, 57, 85), and said second conductive layer (27, 107, 59, 87) is formed on said dielectric layer so as to form a storage electrode filling said trench; and in that said first conductive layer (25, 57, 85) is made of polycrystalline silicon and constitutes an electrode cell plate which surrounds said storage electrode formed by said second conductive layer (27, 107, 59, 87) in an integrated form on said insulating layer (41), but does not cover said storage electrode in the vicinity of the top of said trench (24, 55, 84). A memory according to claim 1, wherein said second conductive layer (27, 107, 59, 87) is ohmically connected to the source or drain region through a third conductive layer (32B, 112B, 64B, 92B). A memory according to claim 1 or 2, wherein said semiconductor substrate (21, 81) is a single semiconductor substrate of one conductivity type. A memory according to claim 1 or 2, wherein said semiconductor substrate comprises a semiconductor substrate (21) of one conductivity type having a semiconductor layer of the other conductivity type (36) thereon, said trench (24) penetrates through said semiconductor layer (36) of the other conductivity type, and said first conductive layer (25) is ohmically connected to said semiconductor substrate (21) through said opening (42). A memory according to claim 1, wherein:- said semiconductor substrate (51) is of one conductivity type, a buried layer (52) of the other conductivity type being formed in said semiconductor substrate; a semiconductor layer (53) is formed on said semiconductor substrate having said buried layer; said trench (55) extends through said semiconductor layer (53) and reaches the buried layer (52) of the other conductivity type; and said first conductive layer (57) is supplied through said buried layer (52) of the other conductivity type, with a bias voltage different from that supplied to said semiconductor substrate (51). A memory according to claim 5, wherein said second conductive layer (59) is ohmically connected to said one of said source and drain regions of said MIS transistor through a third conductive layer (64B). A dynamic random access memory having a trench capacitor, comprising:- a semiconductor substrate (81) of one conductivity type; a trench (84) formed in said semiconductor substrate; an insulating layer (101) formed on an entire inner side surface of said trench; a first conductive layer (85), a dielectric layer (86) and a second conductive layer (87) formed in said trench, said first conductive layer (85), said dielectric layer (86), and said second conductive layer (87) constituting a charge storage capacitor (SC); and a MIS transistor (TR) formed in said semiconductor substrate; wherein said second conductive layer (87) of said charge storage capacitor (SC) is ohmically connected to a source or drain region of said MIS transistor (TR); characterised in that:- said insulating layer (101) has a thickness which allows a passage of carriers therethrough by a tunnel phenomenon; said first conductive layer (85) is formed on said insulating layer and maintained at the same potential as that of said semiconductor substrate (81) through said insulating layer (101), the top of said first conductor layer (85) being located lower than the top of said trench (84) for preventing said first conductive layer from being exposed outside said trench;; a dielectric layer (86) is formed on said first conductive layer (85), said second conductive layer (87) being formed on said dielectric layer (86) and being of the other conductivity type to said substrate (82). A memory according to claim 7, wherein said second conductive layer (87) is ohmically connected to said source or drain region of said MIS transistor (TR) through a third conductive layer (92B).

Inventors: TAGUCHI, MASAO
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29, G11C11