INTERMEDIATE FREQUENCY AMPLIFICATION CIRCUIT CAPABLE OF DETECTING A FIELD STRENGTH WITH LOW ELECTRIC POWER

Abstract: In an intermediate frequency amplification circuit comprising first through n-th differential amplifiers (Q i1 ,Q i2 ) which are connected in cascade to one another with the first amplifier (Q₁₁,Q₁₂) supplied with a circuit input signal and which successively produce amplifier output signals with an n-th amplifier (Q n1 ,Q n2 ) output signal produced as a circuit output signal from the n-th amplifier, first through (n+1)-th rectification circuits (Q if ,Q is ) are supplied with the respective amplifier output signals with the circuit input signal given to the first rectification circuit (Q 1f ,Q 1s ). Each rectification circuit comprises a differential unit comprising at least one pair of transistors have different emitter areas from each other to rectify each amplifier output signal and to produce a collector current which is summed up by an adder circuit to be produced as a field strength signal. The rectification circuits may carry out either half-wave rectification or full-wave rectification. A plurality of the above-mentioned pairs may be included in each rectification circuit.

Description: Background of the Invention: This invention relates to an intermediate frequency amplification circuit for use in a mobile radio station (unit), a cordless telephone set, and/or a telemeter system, and, more particularly, to an intermediate frequency amplification circuit which is capable of measuring or detecting a field strength. A conventional intermediate frequency amplification circuit of the type described comprises an amplification part which is supplied with a circuit input signal to produce a circuit output signal subjected to amplification therein. In addition, a signal strength measuring part is included in the intermediate frequency amplification circuit to measure or detect a field strength of the circuit input signal. More particularly, the amplification part of such an amplification circuit comprises a plurality of differential stages connected in cascade to one another. Each of the differential stages comprises a first pair of transistors having emitters coupled in common to each other. On the other hand, the signal strength measuring part measures the field strength by detecting a d.c. level of the circuit input signal. For this purpose, the signal strength measuring part comprises a plurality of rectification circuits for rectifying output signals of the differential stages to produce rectified signals, respectively, and capacitors coupled to the respective rectification circuits so as to add the rectified signals to one another. Each of the rectification circuits is implemented by a plurality of transistors to carry out half-wave rectification. With this structure, each capacitance of the capacitors in the rectification circuits inevitably become large with a reduction of an intermediate frequency necessary in the intermediate frequency amplification circuit. On manufacturing such an intermediate frequency amplification circuit by the use of a semiconductor integration technique, necessity of a large capacitance gives rise to an increase of a chip size. In order to reduce a chip size, it might be considered that the respective capacitors are connected as external capacitors outside of a chip. However, use of the external capacitors results in an increase of terminals derived from the chip and makes it difficult to apply an integration technique to such an amplification circuit. At any rate, the above-mentioned amplification circuit requires the capacitors equal in number to the rectification circuits. Moreover, each rectification circuit has a bad temperature characteristic. In order to improve the temperature characteristic, complicated compensation must be carried out in each rectification circuit. In Unexamined Japanese Patent Publication Syo 60-246108, an intermediate frequency amplification circuit is disclosed which comprises first through last full-wave rectification circuits connected in cascade to one another. Each of the full-wave rectification circuits comprises first and second differential amplifiers and third and fourth differential amplifiers connected to the first and the second differential amplifiers in series across a power source, respectively. Each of rectified output signals is sent through a current mirror circuit to a current summation circuit to produce a field strength signal. The current summation circuit may include a single capacitor. Incidentally, the first differential amplifier of each full-wave rectification circuit serves to supply an amplified signal to a next following one of the full-wave rectification circuits. As a result, a circuit input signal is supplied to the first full-wave rectification circuits and subjected to amplification through each of the full-wave rectification circuits to produce a circuit output signal through the last full-wave rectification circuit. With this structure, it is possible to improve a temperature characteristic and to produce the field strength signal by the use of a single capacitor. However, the intermediate frequency amplification circuit is disadvantageous in that a source voltage must comparatively be high because the first and the second differential amplifiers must be connected to the third and the fourth differential amplifiers in series across the power source. In fact, it is difficult to drive the amplification circuit at a voltage lower than 2 volts or so. This shows that power consumption becomes large in the intermediate frequency amplification circuit. An intermediate frequency amplification circuit which is substantially constructed as described above and which has all features of the preamble of claim 1 is disclosed in US-A-4 429 416. In IEEE Transactions on Nuclear Science, Vol. NS-29 (1982), February, No. 1, pages 160-163, a logarithmic amplifier is disclosed which comprises a six-stage differential amplifier circuit, a rectifier block and an adder wherein the rectifier block comprises a balanced emitter coupled pair of transistors. In this logarithmic amplifier, the base regions of primary differential circuits are connected to amplifier input terminals of a cascade of amplifiers whereby the collector regions of said primary differential circuits are connected to the logarithmic amplifier output where a summation takes place. It is an object of the invention to provide an intermediate frequency amplification circuit which can readily be manufactured by use of a semiconductor integration technique even when the intermediate frequency is low. It is another object of the invention to provide an intermediate frequency amplification circuit of the type described which is stable in temperature characteristic. It is still another object of this invention to provide an intermediate frequency amplification circuit of the type described which can reduce the power consumption in the circuit. These objects are achieved by an intermediate frequency amplification circuit as defined in claim 1; the dependent claims are related to further developments of the invention. An intermediate frequency amplification circuit to which this invention is applicable is operable in response to a circuit input signal to produce a circuit output signal subjected to amplification. The intermediate frequency amplification circuit comprises first through n-th differential amplifiers which have first through n-th amplifier input terminal pairs and first through n-th amplifier output terminal pairs, respectively, and which are connected in cascade from the first to the n-th differential amplifiers by successively connecting the amplifier output terminal pair of each differential amplifier to the amplifier input terminal pair of the next following differential amplifier. The circuit input signal is supplied across the first amplifier input terminal pair while the circuit output signal is produced at the n-th amplifier output terminal pair. The intermediate frequency amplification circuit further comprises a measuring circuit responsive to the circuit input signal for measuring a field strength to produce a field strength signal representative of the field strength. According to this invention, the measuring circuit comprises first through (n+1)-th differential units which have first through (n+1)-th unit input terminal pairs connected to the first through n-th amplifier input terminal pairs and to the n-th amplifier output terminal pair, respectively, and first through (n+1)-th unit output terminal pairs supplied with first through (n+1)-th unit output signals, respectively, and an adder circuit connected to the first through (n+1)-th unit output terminal pairs for adding the first through (n+1)-th unit output signals to one another to produce the field strength signal. Each of the first through (n+1)-th differential units comprises a primary differential circuit of first and second primary transistors which have first and second base regions, first and second emitter regions, and first and second collector regions, respectively. The first and the second base regions are connected to the amplifier input terminal pair, respectively, while the first and the second emitter regions have an area ratio of l:k, where k is greater than unity, and are coupled in common to each other. The first and the second collector regions are connected to the unit output terminal pair, respectively. Brief Description of the Drawing: Fig. 1 is a circuit diagram of an intermediate frequency amplification circuit according to a first embodiment of this invention; Fig. 2 is a graphical representation for use in describing operation of a single unit included in the amplification circuit illustrated in Fig. 1; Fig. 3 is another graphical representation for use in describing a combination of a plurality of the units illustrated in Fig. 1; Fig. 4 is a circuit diagram of an intermediate frequency amplification circuit according to a modification of the first embodiment illustrated in Fig. 1; Fig. 5 is a circuit diagram of an intermediate frequency amplification circuit according to a second embodiment of this invention; Fig. 6 is a graphical representation for use in describing a single unit included in the amplification circuit illustrated in Fig. 5; Fig. 7 is another graphical representation for use in describing a combination of the units included in the amplification circuit illustrated in Fig. 5; Fig. 8 is a circuit diagram of an intermediate frequency amplification circuit according to a modification of the second embodiment illustrated in Fig. 5; Fig. 9 is a circuit diagram of an intermediate frequency amplification circuit according to a third embodiment of this invention; Fig. 10 is a graphical representation for use in describing operation of a single unit included in the amplification illustrated in Fig. 9; Fig. 11 is another graphical representation for use in describing operation of a combination of the units included in the amplification circuit illustrated in Fig. 9; and Fig. 12 is a circuit diagram of an intermediate frequency amplification circuit according to a fourth embodiment of this invention. Description of the Preferred Embodiments: Referring to Fig. 1, an intermediate frequency amplification circuit according to a first embodiment of this invention comprises an amplification part 21 which is operable in response to a circuit input signal V IN to produce a circuit output signal V OUT subjected to amplification. The circuit input signal V IN is given across a pair of circuit input terminals while the circuit output signal V OUT is developed across the circuit output terminals. More particularly, the amplification part 21 comprises first through n-th stages of differential amplifiers which comprises first through n-th amplifier input terminal pairs and first through n-th amplifier output terminal pairs. The first through n-th stages of differential amplifiers may simply be called first through n-th amplifiers, respectively, and are connected in cascade to one another by successively connecting the amplifier output terminal pair of each amplifier to the amplifier input terminal pair of the next following stage of the amplifiers. In this case, the first amplifier input terminal pair is connected to the circuit input terminal pair while the n-th amplifier output terminal pair is connected to the circuit output terminal pair. The first through n-th amplifiers are similar in structure to one another and comprise circuit elements specified by double suffixes first ones of which are indicative of stage numbers and second ones of which are indicative of element numbers. Taking this into consideration, an i-th amplifier alone will be described as a representative of the first through n-th amplifiers, where i is a natural number between unity and n, both inclusive. The i-th amplifier comprises first and second transistors Q i1 and Q i2 which have bases connected to an i-th amplifier input terminal pair, emitters connected in common to a constant current source I i0 , and collectors which are connected to an i-th amplifier output terminal pair. The collectors of the first and the second transistors Q i1 and Q i2 are connected through first and second resistors R i1 and R i2 in common to a first source terminal which is supplied with a source voltage V cc which is supplied across a first source terminal and a second source terminal grounded. With this structure, an amplifier output signal V i is developed across the collectors of the i-th amplifier which may be regarded as the amplifier output terminal pair, as illustrated in Fig. 1. The collectors of the first and the second transistors Q i1 and Q i2 of the i-th stage are connected to the bases of the second and the first transistors Q (i+1)2 and Q (i+1)1 of the (i+1)-th stage. Such connections may be called twisted connections. The illustrated intermediate frequency amplification circuit further comprises a measuring part 22 for measuring a field strength of a reception signal given to a receiver including the amplification circuit. Such measurement of the field strength is carried out by detecting a d.c. level of the circuit input signal V IN . For this purpose, the illustrated measuring part 22 has a half-wave rectification and saturation characteristic which simulates a logarithmic characteristic. More particularly, the measuring circuit 22 comprises first through (n+1)-th differential units as shown downwards of Fig. 1. The first through (n+1)-th differential units may simply be called first through (n+1)-th units as depicted in Fig. 1, respectively. The second through (n+1)-th units have second through (n+1)-th unit input terminal pairs connected to the first through n-th amplifier output terminal pairs of the first through n-th amplifiers, respectively, while the first unit has a first input terminal pair connected to the first amplifier input terminal pair or to the circuit input terminal pair. In this connection, the first unit is supplied with the circuit input signal V IN . The second through (n+1)-th units are supplied with the first through n-th amplifier output signals, respectively. The first through (n+1)-th units further have first through (n+1)-th unit output terminal pairs which are connected to an adder circuit 23 in parallel and which are supplied with first through (n+1)-th unit output signals, respectively. As readily understood from Fig. 1, the first through (n+1)-th units are similar in structure and operation to one another. Therefore, a single one of the units alone will be described as a representative of the first through (n+1)-th units and may be depicted at the same suffix i as the amplifiers, although i is a natural number between unity and (n+1), both inclusive. The i-th unit comprises first and second transistors Q if and Q is which may be called first and second primary transistors, respectively, for convenience of description and which are specified by the second ones (f and S) of the double suffixes, respectively. The first and the second primary transistors Q if and Q is have first and second emitter regions, first and second base regions, and first and second collector regions when such transistors are manufactured by a semiconductor integration technique. Herein, it is to be noted that the first and the second emitter regions have a first area S o and a second area kS o where k is a factor greater than unity. The factor may be called an area factor. In other words, the first and the second emitter regions have different areas from each other. In this connection, the second emitter region is specified by a double line in Fig. 1. In the i-th unit, the first and the second emitter regions are connected in common to a constant current source I i1 . The first and the second base regions are connected to the circuit input terminal pair and the i-th amplifier output terminal pair when the i-th unit is the first unit and either one of the second through (n+1)-th amplifiers, respectively. More specifically, the first and the second primary transistors Q 1f and Q 1s of the first unit have the first and the second base regions connected to the bases of the first and the second transistors Q₁₁ and Q₁₂ of the first amplifier, respectively, while the first and the second primary transistors of each of the second through (n+1)-th units have the first and the second base regions connected to the collectors of the second and the first transistors Q i2 and Q i1 , respectively, of the preceding amplifier stage. Thus, the base regions of the second through (n+1)-th units are connected to the collectors of the first through n-th amplifiers in a twisted manner like the connections between two adjacent ones of the first through n-th amplifiers. In addition, the first collector regions of the first through (n+1)-th units are connected in common to a first adder terminal of the adder circuit 23 while the second collector regions of the first through (n+1)-th units are connected in common to a second adder terminal of the adder circuit 23. At any rate, first through (n+1)-th collector currents of a first kind are caused to flow through the first collector regions of the first primary transistors Q if of the first through (n+1)-th units, respectively, and are depicted at I c11 through I c1(n+1) , respectively, while first through (n+1)-th collector currents I c21 to I c2(n+1) of a second kind are caused to flow through the second collector regions of the second primary transistors Q is of the first through (n+1)-th units, respectively. The collector currents I c1i and I c2i might often simply be referred to as first- and second-kind collector currents, respectively. The first collector regions of the first primary transistors Q if form first ones of the unit output terminal pairs and are connected in common to a first adder input terminal of the adder circuit 23 while the second collector regions of the second primary transistors Q is form second ones of the unit output terminal pairs and are connected in common to a second adder input terminal of the adder circuit 23. The adder circuit 23 comprises a current mirror circuit composed of a first additional transistor Q o1 and a second additional transistor Q o2 . The first additional transistor Q o1 has a collector and an emitter connected to the first and the second adder input terminals, respectively. In other words, the collector of the first additional transistor Q o1 is connected to the first collector regions of the first primary transistors Q if of the first through (n+1)-th units while the emitter of the first additional transistor Q o1 is connected to the second collector regions of the second primary transistors Q is of the first through (n+1)-th units. The collector of the first additional transistor Q o1 is connected in common to a base of the first additional transistor Q o1 and also to a base of the second additional transistor Q o2 . The second additional transistor Q o2 has an emitter which is connected in common to the emitter of the first additional transistor Q o1 on one hand and which is connected to the first source terminal (V cc ) on the other hand. A collector of the second additional transistor Q o2 is connected to a smoothing circuit comprising a resistor R o1 and a capacitor C o1 which are connected in parallel. As a result, a collector current I o of the second additional transistor Q o2 is sent to the resistor R o1 to be converted into an output voltage V log from an adder output terminal 25. The collector current I o is substantially equal to a sum of the first through (n+1)-th collector currents I c11 to I c1(n+1) of the first kind. In Fig. 1, the sum is represented by I o '. Therefore, the output voltage V log is representative of the d.c. level of the circuit input signal V IN and may therefore be referred to as a field strength signal. Now, consideration will be directed to the i-th unit which is operable in cooperation with the (i-1)-th amplifier on the assumption that the (i-1)-th amplifier produces an (i-1)-th amplifier output signal V i-1 . As readily understood from Fig. 1, the following equation holds; V bef - V bes + V i-1 = 0, (1) where V bef is representative of a base-emitter voltage of the first primary transistor Q i1 ; V bes , a base-emitter voltage of the second primary transistor Q i1 . As known in the art, each of the base-emitter voltages can be related to a saturation current of a transistor and to V T which is generally called the voltage equivalent of temperature and which is given by: V T = k'T/q, where k' represents the Boltzmann constant; q, an electronic charge; and T, an absolute temperature. It is to be noted here that the above-mentioned area factor k has no direct connection with the Boltzmann constant k'. Taking this into consideration, V bef and V bes are given by: V bef = V T 1n (I ci1 /I sil ) (2) and V bes = V T 1n (I ci2 /I si2 ), (3) where I si1 and I si2 represent saturation currents of the first and the second primary transistors Q if and Q is , respectively. In addition, suffixes i are also attached to the saturation currents to specify the i-th unit, as are the cases with the first- and the second-kind collector currents I ci1 and I ci2 . In order to calculate the first- and the second-kind collector currents I ci1 and I ci2 , consideration will be made about a current amplification factor of each of the first and the second primary transistors depicted at α F . In this event, a relationship between a constant current of the constant current source I i1 and the first- and the second-kind collector currents I ci1 and I ci2 is given by: I ci1 + I ci2 = (1/α F ) I i1 . (4) On the other hand, the saturation currents I si1 and I si2 are proportional to the areas of the emitter regions of the first and the second primary transistors Q if and Q is and a relationship between the above-mentioned saturation currents is therefore given by: I si1 /I si2 = 1/k. (5) From Equations 1, 2, 3, 4, and 5, the first-and the second-kind collector currents I ci1 and I ci2 are represented by: I ci1 = α F I i1 / (1 + kexp(-V i-1 /V T )) (6) and I ci2 = α F I i1 / (1 + (1/k)exp(V i-1 /V T )) (7) Referring to Fig. 2, wherein the abscissa and the ordinate represent a ratio of (V i-1 /V T ) and I ci1 , respectively, a curve 30 represents a relationship expressed by Equation 6 on the assumption that α F and k are equal to unity and exp 2, respectively. Herein, let exp 2 be approximately equal to 7.389. As readily understood from Fig. 2, the curve 30 exhibits a half-wave rectification and saturation characteristic. This shows that the first-kind collector current I ci1 has the half-wave and saturation characteristic with respect to V i-1 given from the (i-1)-th amplifier. Accordingly, each of the first through (n+1)-th units produces a collector current having a current waveform shown at a curve 31 when a waveform of an input signal varies with time as specified by a curve 32. At any rate, the collector current has a d.c. current level depicted at I ci1 in Fig. 2. Referring back to Fig. 1, the amplifier output signal V i becomes large with an increase of the number i because each amplifier has a gain which is summed up from the first stage to the n-th stage. In other words, the n-th amplifier output signal V n has a maximum level and the amplifier output signals V i become successively small with a decrease of the number i. This shows that saturation at first begins at the first-kind collector current I c1(n+1) of the (n+1)-th unit of the measuring circuit 22 when the circuit input signal V IN is increased. Thereafter, the remaining collector currents I c1n through I c11 are successively put into saturated states. As a result, the first-kind collector current I c11 of the first unit is finally saturated. Such first-kind collector currents I ci1 of the first through (n+1)-th units are summed up by the adder circuit 23 to be smoothed into the output voltage V log by the parallel circuit of the resistor R o1 and the capacitor C o1 . The resultant collector current I o exhibits, with respect to the circuit input signal V IN , a logarithmic characteristic approximated by a straight line. Consideration will be made about an additional output current I o ′ which flows through the collector of the first additional transistor Q o1 and which is substantially equal to the output current I o . The additional output current I o ′ is equal to a total sum of the first-kind collector currents I ci1 of the first primary transistors Q if . Therefore, the additional output current I o ′ is given by: If a d.c. component of the additional output current I o ′ is represented by I o ′, the following equation holds: Referring to Fig. 3 together with Fig. 1, a characteristic of the d.c. output current I o is illustrated on the assumption that k and the gain of each stage of the amplifiers are equal to 7.389 and G o dB, respectively. Under the circumstances, the output voltage V log is given by: V log = R o1 x I o . Therefore, the output voltage V log has the logarithmic characteristic with respect to the circuit input signal V IN . Referring to Fig. 4, an intermediate frequency amplification circuit according to a modification of the first embodiment is similar in structure to that illustrated in Fig. 1 except that the adder circuit 23 comprises a series circuit of a resistor R o1 and a capacitor C o1 instead of a combination of the parallel circuit of the resistor and the capacitor and the current mirror circuit. As shown in Fig. 4, the resistor R o1 is connected between the first source terminal and the output terminal 25 while the capacitor C o1 is connected between the output terminal 25 and a second source terminal grounded. The collector regions of the first primary transistors Q if are connected in common to the output terminal 25 while the collector regions of the second primary transistors Q is are connected to the first source terminal (V cc ). In the illustrated circuit, the output voltage V log is given by: V log = Vcc - R o1 I o , where Vcc represents the first source voltage supplied to the first source terminal. With this structure, it is possible to reduce the first source voltage Vcc to 1.0 volt or so. Therefore, the first source voltage V cc becomes low in comparison with that illustrated in Fig. 1. As readily understood from Fig. 3, it is possible to expand a dynamic range of the logarithmic characteristic by increasing both of the amplifier stages and the units and to improve linearity of the logarithmic characteristic by selecting each gain of the amplifier stages and the units. Thus, only one capacitor may be included in the illustrated circuit and may be connected to the output terminal 25 for V log . This shows that the capacitor C o1 may be connected outside of an integrated circuit. It is, therefore, possible to lower an intermediate frequency. Referring to Fig. 5, an intermediate frequency amplification circuit according to a second embodiment of this invention is similar to that illustrated in Fig. 1 except that each of the first through (n+1)-th differential units illustrated in Fig. 5 comprises an internal circuit different from that of Fig. 1 and is depicted at B₁ through B n+1 . In this connection, the first through n-th differential amplifier stages are depicted at A₁ to A n in Fig. 5. Therefore, description will be mainly directed to an i-th differential unit B i as a representative of the differential units B₁ to B n+1 . Briefly, each of the illustrated differential units B₁ to B n+1 has a full-wave rectification characteristic, differing from the units illustrated with reference to Fig. 1. In order to accomplish such a full-wave rectification characteristic, the i-th differential unit B i comprises a primary differential circuit of first and second primary transistors Q if and Q is similar to those illustrated with reference to Fig. 1. Accordingly, the emitter regions of the first and the second primary transistors Q if and Q is have the emitter areas specified by 1:k. Therefore, the area factor is represented by k, as is the case with Fig. 1. In the example being illustrated, the i-th differential unit further comprises an additional differential circuit of first and second subsidiary transistors Q it and Q io which may be similar to the second and the first primary transistors Q if and Q is , respectively. Therefore, the first subsidiary transistor Q it has the emitter area equal to k-times the emitter area of the second subsidiary transistor Q io . Anyway, an area factor between the emitter areas of the first and the second subsidiary transistors Q it and Q io is represented by k. For brevity of description, the first and the second primary transistors Q if and Q is may be named first and second transistors, respectively, while the first and the second subsidiary transistors Q it and Q io may be called third and fourth transistors, respctively. The third and the fourth transistors Q it and Q io have the emitter regions connected in common to a subsidiary constant current source depicted at I i2 . The base region of the third transistor Q it is connected in common to the base region of the first transistor Q if while the base region of the fourth transistor Q io is connected in common to the base region of the second transistor Q is . Moreover, the collector regions of the second and the third transistors Q is and Q it are connected in common to each other while the collector regions of the first and the fourth transistors Q if and Q io are also connected in common to each other. From this fact, it is seen that the base regions of the third and the fourth transistors Q it and Q io are supplied with the output signal V i-1 of the (i-1)-th amplifier stage A i-1 in the manner illustrated in Fig. 5 while the base regions of the third and the fourth transistors Q 1t and Q 1o are supplied with the circuit input signal V IN . As a result, the collector regions of the first and the fourth transistors Q if and Q io are connected to the first adder input terminal of the adder circuit 23 while the collector regions of the first and the second transistor Q if and Q is are connected to the second adder input terminal of the adder circuit 23. The adder circuit 23 is similar in structure and operation to that illustrated in Fig. 1 and sums up collector currents I ci1 and I ci4 of the first and fourth translators Q if and Q io of the respective differential units B₁ to B n+1 . A result of the above-mentioned sum is produced through the collector of the transistor Q o2 as the output current which is depicted at a d.c. component I o of the output current I o in Fig. 5. The output current I o is converted into a d.c. output voltage V log by the capacitor C o1 and the resistor R o1 . Now, description will be made about the i-th differential unit B i on the assumption that the collector currents of the first and the fourth transistors Q i1 and Q i4 are represented by I ci1 and I ci4 and the output signal of the (i-1)-th amplifier stage A i-1 is represented by V i-1 . A sum I i of the collector curents I ci1 and I ci4 can be calculated in a manner similar to that mentioned in conjunction with Fig. 1 and is given by: Inasmuch as cosh (V₁/V T ) be equal to cosh (-V₁/V T ) as known in the art, Equation (8) represents an even function. Therefore, the sum I i exhibits a characteristic symmetrical with respect to V i-1 = 0. Referring to Fig. 6, wherein the abscissa and ordinate represent (V i-1 /V T ) and α F I i , respectively, a relationship between V i-1 and I i is specified by a curve 41 when k is equal to three. When the V i-1 varies with time as shown at a curve 42, the output current I i also varies as depicted at a curve 43. From the curve 41, it is seen that each differential unit has the full-wave rectification characteristic and a limiting characteristic. Referring back to Fig. 5, saturation and limiting take place from the collector currents of the first and the fourth transistors Q n+1,1 and Q n+1,4 of the (n+1)-th differential unit B n+1 , like in Fig. 1. On occurrence of such saturation, the collector current I n+1 is nearly equal to zero. Under the circumstances, the logarithmic characteristic is accomplished by summing up the collector currents I ci1 and I ci4 and by smoothing them. For example, the collector current I i of the i-th differential unit B i is equal to α F I i1 / (1+k) on reception of no signal. On the other hand, the collector current I i becomes zero when saturation occurs as a result of reception of a large signal. Taking the above into consideration, a d.c. component I o of the output current I o in the adder circuit 23 is given by: Referring to Fig. 7, a curve 45 shows a variation of the d.c. component I o shown by Equation (9) on condition that the area factor k and the gain of each differential unit are equal to 3 and G o , respectively. The illustrated curve 45 is drawn as a result of addition of curves 45₁ through 45 (n+1) which specify the collector currents I₁ to I n+1 . Inasmuch the output voltage V log is given by: V log = R o1 I o , the output voltage V log varies as depicted at a curve 46. As shown by the curves 45 and 46, the output current I o and the output voltage V log have the logarithmic characteristics approximated by polygonal lines. The amplification circuit illustrated in Fig. 5 is operable by the source voltage V cc of 1.5V. Therefore, it is possible to reduce the source voltage V cc . Referring to Fig. 8, an intermediate frequency amplification circuit according to a modification of the second embodiment is similar in structure and operation except that the adder circuit 23 comprises a series connection of a resistor R o1 and a capacitor connected to the first and the second source terminals, instead of a combination of the current mirror circuit and the parallel connection of the resistor R o1 and the capacitor C o1 illustrated in Fig. 5. With this structure, the output voltage V log is given by: V log = V cc - R o1 I o , and can be further reduced in comparison with that illustrated in Fig. 5. In fact, the amplification circuit illustrated in Fig. 8 is operable by the source voltage V cc of 1.0V. Referring to Fig. 9, an intermediate frequency amplification circuit according to a third embodiment of this invention comprises similar parts designated by like reference numerals and symbols. In Fig. 9, the illustrated amplification circuit is supplied with the circuit input signal V IN through an antenna 51, a radio frequency (RF) amplifier 52, a frequency converter 53, and an intermediate frequency (IF) filter 54 to supply the circuit output signal V out and the field strength signal or output signal V log to a detector 56 and an analog-to-digital (A/D) converter 57, respectively. Like in Fig. 5, the amplification circuit has the first and the second source terminals supplied with the source voltage V cc thereacross and comprises an amplification part 21 similar to that illustrated in Fig. 5, a measuring part 22 to be described in detail later, and an adder circuit 23 of a series connection of a resistor R o1 and a capacitor C o1 which is similar to that illustrated in Figs. 4 and 7. The field strength signal V log is derived from a point P1 of connection between the resistor R o1 and the capacitor C o1 . The point P1 of connection may therefore be called an output terminal. Now, the illustrated measuring part 22 comprises first through (n+1)-th differential units B₁ to B n+1 which are connected to the amplifier stages A₁ to A n in the manner described in conjunction with Figs. 1 and 5, respectively, and which are similar in structure to one another. Under the circumstances, the first differential unit B₁ alone will be described as a representative of the differential units B₁ and B n+1 . In Fig. 9, the illustrated differential unit B₁ comprises first through sixth unit transistors Q₁₁, Q₁₂, Q₁₃, Q₁₄, Q₁₅ and Q₁₆ which may be generally represented by Q i1 to Q i6 , respectively, and which are divided into an odd number group of the first, the third, and the fifth unit transistors Q i1 , Q i3 , and Q i5 and an even number group of the second, the fourth and the sixth unit transistors Q i2 , Q i4 , and Q i6 . The unit transistors Q i1 , Q i3 , and Q i5 of the odd number group have collector regions connected in common to the point P1 of connection and which may collectively be referred to as a first group of transistors. The unit transistors of the first odd number group further have emitter regions each of which has an emitter area depicted at S o . The unit transistors Q i2 , Q i4 , and Q i6 of the even number group have collector regions connected in common to the first source terminal (V cc ) and emitter regions which have emitter areas equal to k₁₁S o , k₁₂S o , and k₁₃S o where k₁₁, k₁₂, and k₁₃ are greater than unity. The base regions of the odd number group transistors of the first differential unit B₁ are connected in common to the base of the transistor Q₁₁ of the amplifier stage A₁ while the base regions of the even number group transistors of the first differential unit B₁ are connected in common to the base of the transistor Q₁₂ of the amplifier stage A₁. As readily understood by comparing Fig. 9 with Fig. 5, the base regions of the odd number group transistors of the second through (n+1)-th differential unit are connected in common to the collector of the second transistor Q (i-1)2 of the (i-1)-th amplifier stage A i-1 while the base regions of the even number group transistors of the second through (n+1)-th differential units A₂ to A n+1 are connected in common to the collector of the first transistor Q (i-1)1 of the (i-1)-th amplifier stage A i-1 . Each transistor of the odd number group is paired with a selected one of the even number transistors. More particularly, the first and the second transistors Q₁₁ and Q₁₂ have the emitter regions connected in common to a first subsidiary constant current source specified by a constant current I₁₁ through first and second emitter resistors R e1 and R e2 , respectively. The first and the second unit transistors Q₁₁ and Q₁₂ may be made to correspond to the first and the second primary transistors Q if and Q is described with reference to Fig. 1. The third and the fourth unit transistors Q₁₃ and Q₁₄ have the emitter regions connected to a second subsidiary constant current source (I₁₂) through third and fourth emitter resistors R e3 and R e4 , respectively. The third and the fourth unit transistors Q₁₃ and Q₁₄ may be made to correspond to the second and the first additional transistors Q io and Q it illustrated in Fig. 5, respectively. Likewise, the fifth and the sixth unit transistors Q₁₅ and Q₁₆ have the emitter regions connected to a third subsidiary constant current source (I₁₃) through fifth and sixth emitter resistors R e5 and R e6 , respectively, and may be called first and second subsidiary transistors, respectively. It is assumed that the second, the fourth, and the sixth emitter resistors R e2 , R e4 , and R e6 are given by: R e2 = (l/k₁₁) R e1 R e4 = (l/k₁₂) R e3 and R e6 = (l/k₁₃) R e5 Herein, the number of the transistor pairs may be generalized into m₁ in addition to the number of the emitter register pairs. In this event, the transistors Q₁₁, Q₁₃, and Q₁₅ of the odd number group can be represented by Q 1,2m₁-5 ; Q 1,2m₁-3 ; and Q 1,2m₁-1 , respectively, while the transistors Q₁₂, Q₁₄, and Q₁₆ of the even number group can be represented by Q 1,2m₁-4 ; Q 1,2m₁-2 ; and Q 1,2m₁ , respectively, when m₁ = 3. Likewise, the resistors R e1 , R e3 , R e5 may be generalized into R e2m₁-5 , R e2m₁-3 , R e2m₁-1 while the resistors R e2 , R e4 , R e6 can be replaced by R e2m₁-4 , R e2m₁-2 , and R e2m₁ . As regards Fig. 9, collector currents of the first, the third, and the fifth unit transistors Q₁₁, Q₁₃, and Q₁₅ are assumed to be represented by I c₁₁ , I c13 , and I c15 , respectively. Under the circumstances, relationship among the circuit input signal V IN , the collector currents I c11 , I c13 , and I c15 , and the constant currents, I₁₁, I₁₂, and I₁₃ are given by: where α F is representative of a current amplification factor. When, each of the first through (n+1)-th differential units B₁ to B n+1 may comprise first through m₁-th pairs of the transistors selected from the odd and the even number groups of the transistors, introduction may be made about a variable j which is variable between unity and m₁, both inclusive. Taking this into account, Equation (10) is generalized into: V IN = V T 1n (l/kj) ((α F I 1j /I c1,2j-1 ) - 1) + (R ej /α F ) (((l/k 1j ) + 1) I c1,2j-1 +α F I 1j ) (11) Differentiation of Equation (11) with respect to I c1,2j-1 gives: dV IN /dI c1,2j-1 = -(V T α F I 1j ) / I c1,2j-1 ² ((αF I 1j /I c1,2j-1 ) - 1 + R e1 /α F ((1/k 1j ) + 1). (12) If I c1,2j-1 = α F I 1j /2, Equation (12) is rewritten into: dV IN /dI c1,2j-1 = (-4V T /α F I 1j ) + (R ej /2) ((l/k 1j ) + 1). (13) Likewise, Equation (11) is rewritten into: V T = (1/2) R ej I 1j ((1/k 1j ) + 3) - V T 1n k 1j . (14) If a tangential line specified by Equation (12) passes through an origin, division of Equation (14) by (α F I 1j /2) gives: Accordingly, the following equation (15) holds: R e1 I 1j = V T (-2 + 1n k 1j ). (15) Referring to Fig. 10, the collector current I c1,2j-1 exhibits a half-wave rectification waveform in response to the circuit input signal V IN , as shown by curves 61 and 62 as long as k 1j is equal to or greater than exp 2, because Equation (15) is positive when k 1j falls within the above-mentioned range. With this structure, it is possible to respond to a wide range of the circuit input signal V IN and therefore to expand a dynamic range. With an increase of the circuit input signal V IN , saturation takes place and the collector current gradually becomes near to α F I 1j . On the other hand, consideration will be made about a predetermined constant determined by: y 1j = 4 / (k 1j + (1/k 1j ) + 2), and about gain g o1 of the first amplifier stage A1 given by: g o1 = (R₁₁ I1/ 2V T ). As regards the gain g o1 , it is possible to design the area factors k 1j and k 1j+1 of the transistors of the first differential unit B₁ such that the following equation (18) holds: In this event, each input signal level which gives the relationship of I c1,2j-1 = (α F I 1j /2) differs from one another in each differential unit B₁ and B n+1 by Therefore, the output current I o of the adder circuit 23 is given by: Since each collector current I c1,2j-1 has the same phase, a d.c. component of each collector current I c1,2j-1 never disappears even on a sum of the respective collector currents. Therefore, the output current I o is given as a logarithmically approximated value with respect to the circuit input signal V IN . Herein, Equation (18) may be generalized into: Similar logarithmic characteristic can be accomplished by the use of Equation (20) in relation to the circuit input signal V IN . If the source voltage and the d.c. component of the output current I o are represented by V cc and I o , respectively, the field strength signal V log is given by: V log = V cc - R o1 I o . Thus, a logarithmic value of the circuit input signal V IN is produced in the form of a d.c. voltage. Referring to Fig. 11, a relationship between the circuit input signal V IN and the output current I o is specified by the logarithmic characteristic. Referring to Fig. 12, an intermediate frequency amplification circuit according to a fourth embodiment of this invention is specified only by each differential unit which is represented by an n-th differential unit. The illustrated differential unit comprises third through (2m+4)-th transistors Q₃ to Q 2m+4 which are divided into an odd number group and an even number group. The transistors of the odd number group have base regions connected in common to one another while the transistors of the even number group have base regions connected in common to one another. Let the transistors represented by Q n,2j+2 and Q n,2j+3 have emitter areas represented by 1 and the transistors represented by Q n,2j+1 and Q n,2j+4 have emitter areas given by km, as symbolized by thick lines in Fig. 12. Each emitter region of the transistors is connected to an emitter resistor depicted at a corresponding suffix. Herein, a relationship between a pair of the resistors is defined by: R n,2j+1 = kj R n,2j+2 , where j = 1, 2 ....., m. Anyway, the emitter regions of the transistors Q n,2j+1 and Q n,2j+2 or Q n,2j+3 and Q n,2j+4 are connected to each other through the corresponding resistors. The illustrated differential unit B n is divisible into first through m-th full-wave rectification units which are driven by constant current sources I n1 , I n2 ..., I nm and which are represented by B n1 , B n2 , ..., B nm . Each rectification characteristic of the rectification circuits has a gentle inclination in compliance with a product of R n,2j+1 and I nj as compared with that illustrated in Fig. 10. When such a product of R n,2j+1 and I nj is changed with a variation of the number j, it is possible to improve logarithmic approximation because the number of the rectification circuits is increased. With this structure, a dynamic range of the logarithmic characteristic can be expanded because the circuit input signal level becomes large due to addition of each emitter resistor.

Claims: An intermediate frequency amplification circuit operable in response to a circuit input signal (V IN ) to produce a circuit output signal (V OUT ) subjected to amplification, said intermediate frequency amplification cirucit comprising first through n-th differential amplifiers (1st STAGE ... n-th STAGE; A₁ ... A n ) which have first through n-th amplifier input terminal pairs and first through n-th amplifier output terminal pairs, respectively, and which are connected in cascade from said first to said n-th differential amplifiers by successively connecting the amplifier output terminal pair of a differential amplifier to the amplifier input terminal pair of the next following differential amplifier, said circuit input signal being supplied across said first amplifier input terminal pair while said circuit output signal is produced at said n-th amplifier output terminal pair, said intermediate frequency amplification cirucit further comprising a measuring circuit (22) responsive to said circuit input signal for measuring a field strength to produce a field strength signal (V log ) representative of said field strength, said measuring circuit comprising: first through (n+1)-th differential units (1st UNIT ... (n+1)-th UNIT; B₁ ... B n+1 ) which have first through (n+1)-th unit input terminal pairs connected to said first through n-th amplifier input terminal pairs and to said n-th amplifier output terminal pair, respectively, and first through (n+1)-th unit output terminal pairs supplied with first through (n+1)-th unit output signals, respectively; and an adder circuit (23) connected to said first through (n+1)-th unit output terminal pairs for adding said first through (n+1)-th unit output signals to one another to produce said field strength signal (V log ); each of said first through (n+1)-th differential units comprising: a primary differential circuit of first and second primary transistors (Q 1f ...Q (n+1)f , Q 1s ...Q (n+1)s ; Q₁₁,Q₁₂; Q n5 , Q n6 ) which have first and second base regions, first and second emitter regions, and first and second collector regions, respectively, said first and said second collector regions being connected to said unit output terminal pair, respectively, characterized in that said first and said second base regions are connected to the amplifier input terminal pair of the related differential amplifier, respectively, while said first and said second emitter regions have an area ratio of 1:k, where k is greater than unity, and are coupled in common to each other. An intermediate frequency amplification circuit as claimed in claim 1, wherein each differential unit comprises: an additional differential circuit of first and second transistor parts which are differentially connected to each other and which are linked to both of the amplifier input terminal pair of said related differential amplifier and the unit output terminal pair. An intermediate frequency amplification circuit as claimed in claim 2, each of said amplifier input terminal pairs consisting of a first and a second amplifier input terminal, wherein: said first and said second base regions are connected to said first and said second amplifier input terminals, respectively; said first transistor part comprising: a first additional transistor (Q₁₀; Q₁₃; Q n4 ) which has an emitter region having a predetermined emitter area, a base region connected to said second amplifier input terminal, and a collector region connected in common to the first collector region of said first primary transistor; said second transistor part comprising: a second additional transistor (Q 1t ; Q₁₄; Q n3 ) having an emitter region which has an emitter area equal to k-times said predetermined emitter area of said first additional transistor and which is coupled in common to the emitter region of said first additional transistor, said second additional transistor having a base region connected in common to said first base region, and a collector region connected in common to said second collector region of said second primary transistor. An intermediate frequency amplification circuit as claimed in claim 2, each of said first through n-th amplifier input terminal pairs consisting of first and second amplifier input terminals while each of the unit input terminal pairs consists of first and second unit input terminals, each of the unit output terminal pairs consisting of first and second unit output terminals, wherein: said first transistor part comprises: a plurality of first subsidiary transistors (Q₁₃ , Q₁₅; Q n4 ,Q n8 ,Q n9 , ..., Q n2m+2 , Q n2m+3 ) having collector regions connected in common to said first collector region of said first primary transistor, emitter regions having emitter areas substantially equal to that of said first emitter region, and base regions connected in common to said first amplifier input terminal; said second transistor part comprising: a plurality of second subsidiary transistors (Q₁₄,Q₁₆; Q n3 ,Q n7 ,Q n10 , ..., Q n2m+1 , Q n2m+4 ) which equal in number to said first subsidiary transistors and which have collector regions connected in common to the second collector region of said second primary transistor, base regions connected in common to the second base region of said second primary transistor, and emitter regions having emitter areas substantially equal to that of said second emitter region and coupled to the emitter regions of said first subsidiary transistors.

Inventors: KIMURA, KATSUJI
Applicants: NEC CORPORATION
Application year: 1987
Main classification: G01R29
IPC codes: H03G7, G01R29, H03F3