Process for isolating semiconductor devices on a substrate

Abstract: A process is disclosed for improving the isolation between semi-oxide insulated devices, formed on mesa structures. In the fabrication of such devices, a silicon substrate is provided. Patterned regions of one type of conductivity are formed in a major surface of the sub­ strate and an epitaxial layer of silicon is formed on the substrate over the major surface. A patterned mask layer is formed on the epitaxial layer and is etched to expose portions of the epitaxial layer. The exposed portions of the epitaxial layer are removed to form the mesa struc­ tures, which overlie the doped patterned regions. Regions of opposite conductivity, called channel stops, are then formed in the substrate between the patterned regions. After filling in the areas between the mesa structures with a field oxide, the devices (bipolar or MOS transis­ tors) are formed on the mesa structures. The process of the invention utilizes as a mask structure a mask having a combination of properties (com­ position and thickness) related to the subsequent process­ ing. The mask permits use of an anisotropic etchant to define the mesa structures and to undercut the mask. An oxide layer is formed on the side walls of the mesa struc­ tures and on those portions of the substrate exposed during the mesa-defining step. Those portions of the oxide layer underlying openings in the mask structure are removed to expose portions of the substrate, which encom­ pass regions between the doped patterned regions. The channel stop dopant is introduced into the regions between the patterned regions.

Description: This invention relates to a process for fabricating a plurality of semiconductor devices on a single substrate, and, more particularly, to a process for improving the isolation between such devices. Bipolar integrated devices are manufactured on silicon wafers having a buried layer which is patterned to provide low collector resistance over a P-type substrate over which an epitaxial layer is grown. It is necessary to isolate one device from the next. This has in the past been done by creating an island or mesa structure of an N-type epitaxial layer including the buried layer by masking and diffusing a P-type plug from the surface. Thermal oxidation is then provided with a separate mask to define active regions within the island. The thermal drive required to drive the P-type impurity into the P-type substrate between the buried layers also allows lateral diffusion, thereby making the island itself smaller. It is also necessary to keep the devices fabricated on the island away from the diffusion. Hence, close packing of the devices to improve density is difficult. The P region with the N epi layer also increases the capacitance values and reduces circuit speed. Further, formation of the field oxide between the islands tends to reduce the active area on the islands available for the fabrication of devices thereon. In order to reduce the drive requirement of diffusion, an etch has been introduced which etches the isolation regions down part way prior to diffusion. This reduces the side diffusion of the P-type dopant, but is still has the problem of requiring the devices to be spaced away from the side of the isolation etch and diffusion, which limits the feasibility of high density products such as gate arrays. This process also has the disadvantage of completely diffused isolation in that it still has higher capacitance due to the P region in the epitaxial layer along the side wall of the isolation oxide. Again, formation of the field oxide between the islands tends to reduce the active area on the islands for the fabrication of devices thereon. Processes in which island or mesa structures are formed by etching into a silicon epitaxial layer through a patterned masked are disclosed in several documents cited in the European Search Report, particularly IBM Technical Bulletin Vol. 27, No. 3, August 1984 p. 1465-1466; Technical Digest IEDM 1982, p. 22-227; and US Patent No. 4271583. In the IBM document the mask is a bi-layer of silicon dioxide and silicon nitride, and the side walls of the mesa are protected with a silicone dioxide layer during diffusion of the P-type dopant. In the IEDM document the side walls are further protected with a silicon nitride layer. The US Patent similarly protects the side walls with silicon dioxide and silicon nitride, and also uses alternating multilayers of silicon dioxide and silicon nitride as the mask structure. In summary, the prior art provides a process for fabricating semi-oxide insulated devices, which includes providing a silicon substrate, and forming N-type doped patterned regions on a major surface of said substrate, then (a) forming an epitaxial silicon layer on said substrate over said major surface, (b) forming a patterned mask layer on said epitaxial layer with openings through said patterned mask to expose portions of said epitaxial layer, (c) removing said exposed portions of said epitaxial layer by etching through said openings to expose portions of said substrate and to form beneath said patterned mask mesa structures which overlie said patterned regions, (d) forming a silicon dioxide layer on the mesa walls and exposed substrate portions, (e) removing silicon dioxide from substrate portions between said patterned regions by etching through said openings to expose corresponding regions of said substrate, (f) forming P + -type doped regions, in said exposed substrate regions by introducing a P-type dopant between said mesa structures, (g) forming a field oxide between said mesa structures, and (h) forming devices on said mesa structures, wherein said devices are isolated from each other by said P + -type regions. The present invention provides an improvement on the above process which reduces unwanted diffusion of the P-type dopant. Relative to the prior art process summarised above, the present invention is as defined in claim 1. In summary the invention involves: (a') forming said epitaxial layer to have a crystallographic orientation of its (100) planes parallel to said major surface of said substrate; (b') forming said patterned mask from a multilayer structure that comprises a first layer of a buffer oxide (20), a second layer of silicon nitride (22), a third layer of undoped silicon dioxide (24) and a fourth layer of silicon nitride (26); (c') removing said exposed portions of said epitaxial layer by an at least partially anisotropic etchant which etches least along the (111) planes of said epitaxial layer thereby to undercut portions of said patterned mask, form said mesa structures having side walls shielded by said undercut portions. and expose portions of said substrate; (e') removing those portions of said silicon dioxide layer laying under said openings in said patterned mask to expose corresponding regions of said substrate. without removing or while only partially removing said patterned mask layer so as to leave a cap of mask material on said mesa structures; (f') forming said P + -type doped regions in said exposed substrate regions between said patterned regions by introducing a P-type dopant between said capped mesa structures and through openings formed in said silicon dioxide layer. In the process of the invention, the remaining layers of the mask layer after step (e') act as a mask during the formation of the field oxide layer, thereby preventing unwanted consumption of the active area of the mesa structures. Also employing an at least partially anisotropic etchant to undercut the mask in step (c'), followed by oxidation of the side walls of the mesa structures and the exposed surface of the substrate and then removing only those portions of the oxide directly beneath the openings in the mask, means that step (f') will result in self-aligned channel stop regions having the desired dimensions and characteristics. The described process may also advantageously be employed to provide isolated mesa structures for MOS devices, using appropriately doped substrate materials and diffusion species. The drawings referred to in the following description of one example of the invention should be understood as not being drawn to scale except if specifically noted. Moreover, the drawings are intended to illustrate only one portion of an integrated circuit fabricated in accordance with the present invention. In the description and the claims, 1 Å equals 0.1 nm (one Angström = 0.1 nanometer). In the drawings, FIGS la-f depicts, in cross-section, the sequence of processing steps. FIG. 1a depicts a substrate 10 in which a patterned set of buried layer regions 12 are formed. A region 14 is left between adjacent buried layer regions 12; it is in this region that a channel stop region will subsequently be formed. Further, it will be appreciated that a plurality of mesa structures will eventually be formed, with each mesa structure registered so as to overlie a buried layer region 12. In the particular embodiment disclosed herein, the substrate 10 is silicon, processed in a conventional manner so as to provide the buried layer regions 12. The buried channel regions 12 are formed in the substrate employing conventional silicon processing technology. In particular, the regions 12 are defined by the use of masks, with a dopant introduced, such as by diffusion, into exposed regions of the substrate 10. In this embodiment, an N region is formed, using antimony as the dopant species. The buried channel regions are typically doped to a level of about 10 19 to 10 20 cm -3 . The regions 12 are about 3 to 3.5 micrometers thick, as is common in this art, and have a resistivity of about 5 ohms/square. An epitaxial layer 16 of silicon is next formed on the substrate 10 with its buried channel regions 12. The epi layer 16 is conveniently formed by thermal decomposition of a silicon-containing species, such as silane, as is well-known. The epi layer 16 is typically grown to a thickness of about 1 to 2.5 micrometers. A mask structure 18 is formed on the exposed surface of the epi layer 16. The mask structure comprises a first layer 20 of a buffer oxide, a second layer 22 of silicon nitride, a third layer 24 of undoped silicon dioxide and a fourth layer 26 of silicon nitride. An undoped deposited layer of oxide is used, since such an oxide, after thermal densification has the same etch rate as a thermally grown oxide, which is slower than the etch rate of a doped layer in a wet chemical etch. The buffer oxide layer 20 is thermally grown, employing well-known processing parameters, to a thickness of about 300 to 500 Angstroms (Å). The silicon nitride layers 22, 26 are conveniently formed by chemical vapor depostion (CVD), also employing well-known processing parameters. The innermost silicon nitride layer 22 is formed to a thickness of about 1000 to 1200 Å, while the outermost silicon nitride layer 26 is formed to a thickness of about 700 to 1000 Å. Conveniently, the silicon dioxide layer 24 is a comparatively low temperature oxide, deposited at a temperature of about 450°C and formed to a thickness of about 1500 to 2000 Å. Advantageously, the Silox process, which is a thermal decomposition of gases to deposit the oxide, is employed. The mask structure 18 is etched, as shown in FIG. 1b, to expose portions of the epi layer 16. An active mask, used for defining the active area of the mesa structure, such as photoresist (not shown), is used to define the portions of the mask layer 18 to be removed. Plasma etching, employing fluorine chemistry, such as CF 4 or CHF 3 , is used to etch through the component layers of the mask structure 18. Openings 28 are thereby formed in the mask structure 18 and have a diameter of about 1.2 to 2 micrometers. The mask openings are registered by techniques well-known in this art to lie only above those regions 14 between the patterned buried layer regions 12. Up to this stage in the processing, the use of a mask layer 18 to define the portions of the epi layer 16 to be exposed is conventional. However, the particular component layers of the mask layer 18, namely, layers 20, 22, 24 and 26 of oxide, nitride, oxide and nitride, respectively, and their thicknesses are uniquely coupled to the processing sequence of the invention, as described below. In accordance with the invention, the epi layer 16 is etched, employing an etchant which is at least partially anisotropic, to expose portions of the underlying substrate 10 and thereby form mesa structures 30, as depicted in FIG. 1c. The epi layer 16 is formed with the (100) plane parallel to the substrate 10. The anisotropic etchant is one which preferentially etches along a particular direction. In this case, it is desired to undercut the mask structure 18. Thus, for (100) silicon, an etchant which etches least on the (111) plane is used. Such etchants are well-known in this art, and include chromium trioxide/HF, for example. The result is an undercut, which is at an angle of about 47° to 57°, depending upon the etchant composition used. It is not necessary to completely etch down to the substrate 10 if thermal oxidation will be subsequently employed, as described below, since the thermal oxidation would consume part of the remaining silicon. However, the etching should be close enough to the substrate 10 to ensure that the P-diffusion in the region 14 between the buried layers 12 at the end of the process disclosed herein will be well-defined and that the oxide formed by the thermal oxidation will consume the remaining N-type material comprising the epi layer 16 between the mesa structures 30 and thereby provide good isolation between the mesa structures 30. An oxide layer 32 is formed on the side walls 34 of the mesas 30 and the exposed portions of the substrate 10, as shown in FIG. 1d. The oxidation is preferably performed by the well-known dry thermal process, which is carried out at about 1000°C. The oxide layer 32 is formed to a thickness sufficient to prevent diffusion of the dopant, which will subsequently be used to form the channel stop, into the underlying semiconductor material. For this particular embodiment, in which the diffused species is boron, a thickness of at least about 1000 Å is adequate. The upper limit is dictated by economic considerations, since portions of the oxide layer 32 will be subsequently removed, and thus should be as thin as possible. Consistent with this consideration, the upper limit is about 1500 Å. Openings 36 are formed in the oxide layer 32 to expose portions of the substrate 10, as depicted in FIG. le. In particular, the openings 36 are registered to expose the regions 14, which lie between the buried layer regions 12. The openings 36 are formed by reactive ion etching (RIE), which etches the silicon dioxide layer 32. Fluorine chemistry, as described above, is conveniently employed to generate fluoride ions for the etching process. It will be appreciated that since there is no layer to naturally stop the etching process when the oxide layer 32 is completely etched through, then the process is dependent on the known etching rate. In particular, to ensure complete etching, the oxide layer 32 is over-etched to the extent of about 200 Å. In this connection, the thickness of the oxide layer 24 given above as ranging from about 1500 to 2000 Å, is predetermined to be at least about 200 Å greater than that of the oxide layer 32, since the silicon nitride layer 26 will be completely removed and the oxide layer 24 will be partially removed during the RIE process. A dopant species is introduced into the exposed regions of the substrate 10 through the openings 36 to form channel stops 38 in the regions 14, as shown in FIG. le. Where the buried layer is N-type, the channel stop is P-type, conveniently employing boron as the dopant species. The dopant is preferably introduced by a diffusion process, carried out at about 750° to 1000°C, as is well-known in this art. However, other means of introducing the dopant, such as by ion beam, may also be employed, making suitable adjustment in dopant species and oxide thickness, as is well-known in the art. BCl 3 is advantageously employed as the diffusion source. The P + channel stops 38 have a dopant concentration, after drive, of about 10 18 to 10 19 cm -3 . The structure is annealed, primarily to remove any damage caused by the introduction of the dopant. The annealing is done at about 850°C for about 30 minutes, although lower temperatures associated with longer times or higher temperatures associated with shorter times may also be employed. The oxide layer 24 is removed by a wet dip etchant, employing a buffer oxide etch solution, such as |NH 4 F-HF| solution, which is commercially available, or an aqueous solution of HF. The etchant also removes a portion of the side wall oxide 32, but since a portion of the undoped oxide layer 24 has previously been removed, the side wall oxide 32 may not be completely removed. A field oxide layer 40 is next formed, advantageously employing a dry oxygen/steam process, well-known in this art for growing a layer of silicon dioxide. For the dimensions of the various layers given herein, a typical time for the oxidation process is about 180 minutes, although there will be some variation. Commonly, it is desired to form the field oxide 40 to about the same thickness as the epi layer 16. The remaining layers of the mask layer 18, namely, the buffer oxide layer 20 and the silicon nitride layer 22, act as a mask during the formation of the field oxide layer 40, thereby preventing unwanted consumption of the active area of the mesa structures 30. The wafer is subsequently processed, employing conventional parameters, to form devices (not shown), such as bipolar or MOS transistors, on the mesas. Such additional processing is conventional and forms no part of this invention. In the prior art, reactive ion etching could not be employed to form the opening in the silicon dioxide overlying the undoped regions between the buried structures without also removing the side wall oxide. Further, the region for diffusing in the dopant species to form the channel stop would not be well defined. Thus, it will be appreciated that employing an anisotropic etchant to undercut the mask 18, followed by oxidation of the side walls 34 of the mesa structures 30 and the exposed surface of the substrate 10 and then removing only those portions of the oxide directly beneath the openings 28 in the mask 18 will result in self-aligned channel stop regions 38, having the desired dimensions and characteristics. It is possible that the invention may be practiced in other fabrication technologies in MOS or bipolar processes.

Claims: A process for fabricating semi-oxide insulated devices, which includes providing a silicon substrate (10), and forming N-type doped patterned regions (12) on a major surface of said substrate, leaving regions (14) between adjacent N-type doped patterned regions (12), then (a) forming an epitaxial silicon layer (16) on said substrate over said major surface, (b) forming a patterned mask layer (18) on said epitaxial layer (16) with openings (28) to expose portions of said epitaxial layer (16) lying only above the regions (14) between the N-doped patterned regions (12), (c) removing said exposed portions of said epitaxial layer (16) by etching through said openings (28) to expose portions of said substrate and to form beneath said patterned mask mesa structures (30) which overlie said N-type doped patterned regions (12), (d) forming a silicon dioxide layer (32) on the mesa walls and exposed substrate portions, (e) removing silicon dioxide from substrate portions between said N-type doped patterned regions (12) by etching through said openings (28) to expose regions of said substrate, (f) forming P + -type doped regions (38), in said exposed substrate regions by introducing a P-type dopant between said mesa structures, (g) forming a field oxide (40) between said mesa structures, and (h) forming devices on said mesa structures, wherein said devices are isolated from each other by said P + -type regions, characterised by: (a') forming said epitaxial layer (16) to have a crystallographic orientation of its (100) planes parallel to said major surface of said substrate; (b') forming said patterned mask (18) from a multilayer structure that comprises a first layer of a buffer oxide (20), a second layer of silicon nitride (22), a third layer of undoped silicon dioxide (24) and a fourth layer of silicon nitride (26); (c') removing said exposed portions of said epitaxial layer by a partially anisotropic etchant which etches least along the (111) planes of said epitaxial layer, thereby to undercut portions of said patterned mask. form said mesa structures (30) having side walls (34), and expose portions of said substrate; (e') removing those portions of said silicon dioxide layer (32) laying under said openings (28) in said patterned mask thereby forming openings (36) exposing regions (14) of said substrate between said N-type doped patterned regions (12); (f') forming said P + -type doped regions (38) in said exposed substrate regions between said N-type doped patterned regions by introducing a P-type dopant through said openings (36) formed in said silicon dioxide layer. The process of claim 1, wherein said first layer is formed to a thickness of about 30 to 50 nm (300 to 500 Å), said second layer is formed to a thickness of about 100-120 nm (1000 to 1200 Å), said third layer is formed to a thickness of about 150-200nm (1500 to 2000 Å) and said fourth layer is formed to a thickness of about 70-100 nm (700 to 1000 Å.) The process of claim 1 or 2. wherein said first layer is formed by a thermal process: said second and fourth layers are formed by a chemical vapor deposition process and said third layer is formed by an oxidation deposition process. The process of any one of claims 1 to 3. wherein said openings in said mask are formed by etching through portions of said mask with a plasma. The process of any one of claims 1 to 4, wherein said oxide is formed on the side walls of said mesa structures and on said exposed portions of said substrate by a dry thermal process. The process of claim 7, wherein said oxide is formed to a thickness of about 100 to 150 nm (1000 to 1500 Å). The process of claim 5 or 6, wherein said exposed portions of said epitaxial layer are removed by said at least partially anisotropic etchant to the extent that any epitaxial layer remaining over said substrate is completely converted to oxide by said dry thermal process. The process of any one of claims 1 to 7, wherein that portion of said oxide layer underlying said openings is removed by reactive ion etching employing fluoride ions. The process of any one of claims 1 to 8, wherein said P-type dopant consists essentially of boron. The process of claim 11, wherein said boron is introduced by a diffusion process. The process of any one of claims 1 to 10, wherein said substrate carrying said mesa structures is annealed to remove damage caused by introducing said dopant.

Inventors: THOMAS MAMMEN, THOMAS, MAMMEN
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1987
Main classification: H01L21
IPC codes: H01L21