IMPROVED OPERATIONAL AMPLIFIER UTILIZING JFET FOLLOWERS

Abstract: An operational amplifier includes a pair of differentially coupled PNP transistors driving a current mirror circuit. The base of the each of the transistors is coupled to the source of a JFET follower transistor each of which in turn has a gate coupled to one of the amplifier's inputs (10, 12). First and second current sources are coupled to the source electrodes of each of the JFETs for the purpose of supplying a current thereto equal to that JFET's I DSS (its drain current when its gate and source are shorted).

Description: Background of the Invention This invention relates generally to operational amplifiers, and more particularly, to an operational amplifier utilizing JFET followers each of which is driven by a current source generating a current which is proportional to the saturation current I DSS of its respective JFET follower and which tracks its respective I DSS over temperature. In an operation amplifier which utilizes JFET followers for driving a PNP differential stage, it is desirable that the JFETs be supplied each with a current equal to I DSS (the drain current when the gate and source terminals are shorted) and in this manner provide a gate-to-source voltage (V gs ) equal to zero and having a temperature coefficient equal to zero (i.e. dV gs /dT = 0 ). Furthermore, with V gs on both sides of the amplifier (i.e. V gs1 and V gs2 ) equal to zero, the offset voltage Vos which equals V gs1 -V gs2 would also equal zero and dV os /dT would equal zero. Unfortunately, in the past, the required currents equal to I DSS of the JFET followers could not be assured sufficiently to achieve consistently acceptable results. The following patents are noted as disclosing subject matter related to the present invention: US-A-3,703,650 discloses an amplifier circuit with JFET followers conducting I DSS /2 and having constant V DS for providing a zero temperature coefficient thereof, and US-A-4,241,314 features another amplifier circuit with JFET followers. Summary of the Invention It is an object of the present invention to provide an improved operational amplifier circuit utilizing JFET followers. According to a broad aspect of the invention there is provided an amplifier having first and second inputs and comprising first and second emitter coupled transistors (Q₃, Q₄) each having a base, collector and emitter, the emitters being coupled to a first source of supply voltage; current mirror means (D₁, Q₅) having an input and output respectively coupled to the collectors of the first and second transistors; a first JFET (Q₁) having a source coupled to the base of the first transistor, a drain coupled to a second source of supply voltage, and a gate coupled to the first input, and having a first I DSS ; and a second JFET (Q₂) having a source coupled to the base of the second transistor, a drain coupled to the second source of supply voltage, and a gate coupled to the second input, and having a second I DSS , the amplifier circuit characterized by; first means (I₁) coupled to the source of the first JFET for supplying a first current thereto substantially equal to the first I DSS , said first means including, (a) a third JFET (Q₆) having a source coupled to the first source of supply voltage, a drain coupled to the source of the first JFET for conducting said first current, and having a gate, and (b) a first adjustable resistor (R T ) having a first terminal coupled to the first source of supply voltage and a second terminal coupled to said gate of said third JFET and to a source of a reference current (I REF ); and second means (I₂) coupled to the source of the second JFET for supplying a second current thereto substantially equal to the second I DSS , said second means including, (a) a fourth JFET (Q₆) having a source coupled to the first source of supply voltage, a drain coupled to the source of the second JFET for conducting said second current, and having a gate, and (b) a second adjustable resistor (R T ) having a first terminal coupled to the first source of supply voltage and a second terminal coupled to said gate of said fourth JFET and to said source of a reference current. The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Brief Description of the Drawings Fig. 1 is a schematic diagram of the inventive operational amplifier circuit; and Fig. 2 is a schematic diagram of a current source for generating currents I₁ and I₂ in Fig. 1. Description of the Preferred Embodiment The operational amplifier shown in Fig. 1 includes a pair of emitter coupled PNP transistors Q3 and Q4 each of which have their collectors coupled to a current mirror circuit comprised of diode means D₁ and NPN transistor Q5. That is, the collector of PNP transistor Q3 is coupled to the anode of diode D1 and to the base of transistor Q5. The collector of transistor Q4 is coupled to the collector of transistor Q5. Both the cathode of diode D1 and emitter of transistor Q5 are coupled to a source of supply voltage (e.g. ground). The tail current required by this circuitry is provided by a current source I t coupled between the emitters of transistors Q3 and Q4 and another source of supply voltage (V CC ). The base electrodes of transistors Q3 and Q4 are coupled respectively to the source electrodes of junction field-effect-transistors (JFETs) Q1 and Q2 respectively each of which have a drain coupled to ground. Q1 has a gate terminal coupled to a first input terminal 10, and Q2 has a gate coupled to a second input terminal 12. The remainder of the operational amplifier represented by amplifier A1 having an input coupled to the collector junction of transistors Q4 and Q5, the output of which (V₀) represents the amplifier output, and a compensation capacitor C c coupled in parallel with amplifier A₁). Finally, current sources I₁ and I₂ are provided for driving junction field-effect-transistors Q1 and Q2 respectively, and it is the nature of these current sources and their relationship to the circuit as a whole which renders the circuit shown in FIG. 1 inventive. The gate to source voltage (V gs ) of a JFET may be represented as V gs = V p (1 - √ I D /I DSS ) (1) where V p is a pinch-off voltage of the JFET, I D is the drain current and I DSS represents the JFET's drain current when its gate and source are shorted. The amplifier's offset voltage (V os ) may then be represented as the difference between the gate to source voltage of Q2 and Q1 or V os = V gsQ2 - V gsQ1 (2) By substituting, there is obtained V os = V pQ2 (1- √ I₂/I DSSQ2 ) - V pQ1 (1-√ I₁/I DSSQ1 ) (3) If dI₂/dT = dI DSSQ2 /dT and dI₁/dT = dI DSSQ1 /dT the rate of change of the offset voltage with respect to temperature may be represented as dV os /dT = (dV pQ2 /dT) (1- √ I₂/I DSSQ2 - (dV pQ1 /dT) (1- √ I₁/I DSSQ1 ) (4) It can be seen that if I₂ is substantially equal to I DSSQ2 and I₁ is substantially equal to I DSSQ1 , then both the offset voltage V os and the rate of change of V os with temperature (dV os /dT) equals zero. That is, by trimming the offset voltage to zero, dV os /dT is also automatically trimmed to zero. Current sources I1 and I2 are be generated by the circuit shown in Fig. 2. Referring to Fig. 2, each inventive current source comprises a JFET Q6 having a source coupled to a source of supply voltage V CC and having a drain at which the required current I₁, I₂ is made available. The gate of Q₆ is coupled via a trimmable resistor R T to the source of supply V CC . The gate is also coupled to the source of a reference current I REF . The reference current I REF is equal to V p /R where V p is the pinch-off voltage of a JFET and R is some resistance. Referring again to FIG. 2, I₁ or I₂ (hereinafter "I d ") may be expressed as I d = I DSS (1 - V gs /V p )² (5) where V gs is the gate to source voltage of Q₆ and V p is the pinch-off voltage of Q₆. Since the source of Q₆ is biased above its gate, V gs may be expressed as V gs = -I REF R T (6) Substituting Equation (6) into equation (5) yields I d = I DSS (1 + I REF R T /V p )² (7) As previously described, I REF equals V p /R. Therefore, I d = I DSS (1 + V p R T /V p R)² (8) As long as JFET Q₆ and the current source generating I REF are in close proximity, their pinch-off voltages will be substantially equal and Equation (8) becomes I d = I DSS (1 + R T /R)² (9) Thus, it can be seen that I d appearing at the drain of JFET Q₆ is proportional I DSS and may be trimmed simply by altering the ratio of R T /R. This is accomplished by adjusting trimmable resistor R T . Through this mechanism, I d may be adjusted so as to be equal to I DSS . If we next assume that resistors R and R T are of the same type, then dR/dT = dR T /dT (10) and the temperature coefficient of R is substantially identical to that of R T . That is dI d /dT = (dI DSS /dT)(1 + R T /R)² (11) This being the case, the temperature coefficient of I D is proportional to that I DSS . Thus, the circuit shown in FIG. 2 when driven by a reference current equal to V P /R produces a current I d which is proportional to I DSS and trimmable and one which has a temperature coefficient which is proportional to that of I DSS . Aside from the above, the operational amplifier shown in FIG. 1 operates in the well known manner. That is, when the voltage at terminal 10 is greater than that at terminal 12, JFET Q1 turns on causing the voltage at the base of transistor Q3 to fall thus turning it on. The current flowing in the collector of Q3 will thus be greater than that flowing in the collector of Q4. Since the current mirror action of diode D1 and transistor Q5 will attempt to mirror the current flowing in the collector of Q3 in the collector of Q5, the voltage at node 14 which is applied to the amplifier's output stage will fall. In contrast, should the potential at input terminal 10 be less than that at terminal 12, JFET Q2 will turn on causing transistor Q4 to conduct harder than transistor Q3. In this case, the current being mirrored to the collector of transistor Q5 is less than that flowing in the collector of transistor Q4 and the voltage at node 14 will rise.

Claims: An amplifier having first (10) and second (12) inputs and comprising first and second emitter coupled transistors (Q₃, Q₄) each having a base, collector and emitter, the emitters being coupled to a first source of supply voltage; current mirror means (D₁, Q₅) having an input and output respectively coupled to the collectors of the first and second transistors; a first JFET (Q₁) having a source coupled to the base of the first transistor, a drain coupled to a second source of supply voltage, and a gate coupled to the first input, and having a first I DSS ; and a second JFET (Q₂) having a source coupled to the base of the second transistor, a drain coupled to the second source of supply voltage, and a gate coupled to the second input, and having a second I DSS , the amplifier circuit characterized by; first means (I₁) coupled to the source of the first JFET for supplying a first current thereto substantially equal to the first I DSS , said first means including, (a) a third JFET (Q₆) having a source coupled to the first source of supply voltage, a drain coupled to the source of the first JFET for conducting said first current, and having a gate, and (b) a first adjustable resistor (R T ) having a first terminal coupled to the first source of supply voltage and a second terminal coupled to said gate of said third JFET and to a source of a reference current (I REF ); and second means (I₂) coupled to the source of the second JFET for supplying a second current thereto substantially equal to the second I DSS , said second means including, (a) a fourth JFET (Q₆) having a source coupled to the first source of supply voltage, a drain coupled to the source of the second JFET for conducting said second current, and having a gate, and (b) a second adjustable resistor (R T ) having a first terminal coupled to the first source of supply voltage and a second terminal coupled to said gate of said fourth JFET and to said source of a reference current. An amplifier according to claim 1 wherein each of the first and second transistors are PNP transistors. An amplifier according to claim 2 wherein said source of a reference current is proportional to the pinch-off voltage of said third and fourth JFETs.

Inventors: SUSAK, DAVID M., VYNE, ROBERT LEONARD
Applicants: MOTOROLA INC.
Application year: 1987
Main classification: H03F3
IPC codes: H03F3