Thin film vertical resistor devices for a thermal ink jet printhead and methods of manufacture

Abstract: The specification describes thermal ink jet (TIJ) processes and device structures produced thereby wherein either heater resistors or heater resistor-diode combinations are constructed vertically upward from a common supporting substrate. A lower or first metal level conductor pattern provides one part of an X-Y matrix multiplex connection to the resistor/diode components, and a second, upper metal level conductor pattern forms the second part of the X-Y matrix multiplex connection. In this manner, the multiplex drive circuitry for the TIJ printhead resistors/diodes may be fabricated (integrated) directly on the thin film resistor (TFR) printhead substrate. Additionally, the second level metal conductors which overlie the resistive heater and diode elements also serve as a barrier shield to ink corrosion and cavitation wear.

Description: Technical Field The present invention relates generally to thermal ink jet (TIJ) printing and more particularly to new and improved thermal ink jet printhead device structures employing vertical resistors and a metal ink barrier having improved resistance to ink corrosion and cavitation wear. Background Art In the field of thermal ink jet printing, it has become a common practice to provide heater resistors on a common substrate and align these heater resistors with individual ink reservoirs and corresponding ink ejection orifices in an outer nozzle plate. These heater resistors are physically defined and electrically driven by conductive traces which are photolithographically formed on the surface of a suitable resistor layer material, such as tantalum-aluminum. These heater resistors have been traditionally isolated from the overlying ink reservoirs by highly inert dielectric materials such as silicon carbide and silicon nitride. This type of thermal ink jet printhead is described, for example, in the Hewlett Packard Journal , Vol. 36, No. 5, May 1985, incorporated herein by reference. Thus, the current flowing in this type of printhead flows laterally in the conductive trace material and then down and again laterally through the resistive tantalum aluminum layer where no trace material appears and then back up and again laterally through the conductive trace material. EP-B-0154515 (Xerox Corporation) discloses a thermal ink jet printing device comprising a multilayered lateral heating resistor in contact with an ink reservoir. The lateral heating resistor comprises a resistor layer of doped polycrystalline silicon, a dielectric isolation layer atop the resistor layer and a protective layer of tantalum atop the dielectric isolation layer to protect the dielectric isolation layer from ink corrosion and cavitation wear. Electric current to heat the resistor flows laterally through the resistor layer via electrodes connected across the resistor layer. The electrodes are electrically insulated from the protective layer of tantalum. According to one embodiment of the thermal ink jet printing device disclosed in EP-B-0154515 the above resistor is formed on a substrate of highly doped, conductive silicon. A thin, lightly doped p-type epitaxial layer separates the resistor from the substrate. The conductive substrate serves as one of the electrodes supplying electric current to the resistive layer, contact with the resistive layer being made through a small phosphorus-doped region of the epitaxial layer located near the edge of the resistor layer. US-A-4353079 (Tsuyoshi Kawanabe) describes and claims an electronic device and thermal ink jet printer combination which comprises: a character generator for generating character information to be recorded on a recording medium; an AND gate, one input terminal of which receives the output of the character generator; a heating resistor for receiving the output of the AND gate and which ejects ink droplets from an orifice in response to the AND gate's output; a keyboard provided with an instruction key for instructing the number of outputs of the AND gate; and a control section connected to another input terminal of the AND gate to control the number of outputs of the AND gate in accordance with the operation of the instruction key. Disclosure of Invention In significant contrast to the above lateral resistor and inert dielectric barrier construction of the prior art, the present invention provides new and improved printhead construction featuring the use of vertical heater resistors in combination with a metal, rather than a dielectric, barrier layer. These vertical heater resistors provide conductive paths from electrically conductive leads on an underlying substrate and through openings in an insulating pattern and then to either a single conductive bus member or to an upper set of leads for the resistors. The upper conductor also serves as the ink barrier layer between the vertical heater resistors and the ink reservoirs. When used as a bus bar, this metal barrier layer may be grounded and thus made nonreactive to the ink which it shields against, and thus offers an improved resistance to ink corrosion and cavitation wear during an ink jet printing operation. In an alternative embodiment of our invention, the vertical resistors may be appropriately doped to form PN junctions (diodes) in the resistive material and may then be selectively connected to certain ones of the electrical leads on both the underside and the topside of these PN junctions so as to form an X-Y matrix type of diode multiplexing circuit which may be integrated on the surface of a single printhead substrate member. Thus, the present invention not only improves the barrier-to-corrosion/cavitation wear, but it simultaneously provides a novel vertical resistor/diode integrated driving multiplex circuit which may be fabricated on the surface of a single substrate. The above advantages and novel features of this invention will become more readily apparent in the following description of the accompanying drawing. Brief Description of the Drawings Figures 1A - 1H are schematic cross section views of a first process used to fabricate one type of printhead device structure and multiplex circuit according to the present invention. Figure 1I is a plan view of the resistor/diode multiplex circuit fabricated by the process of Figures 1A - 1H. Figures 2A - 2G are schematic cross section views illustrating a second process embodiment of the invention. Figure 2H is a plan view illustrating the multiplex circuit connection for a plurality of resistors or diodes formed in accordance with Figures 2A - 2G. Figures 3A-3G illustrate in schematic cross section a third process embodiment of the invention. Figure 3H is a plan view illustrating the multiplex circuit connection for structures fabricated using the process sequence of Figures 3A - 3G. Figures 4A - 4G illustrate in schematic cross section a fourth process embodiment according to the invention. Figure 5 is a schematic diagram for a nine (9) diode and nine (9) resistor XY matrix type multiplex circuit which may be constructed using the vertical resistor/diode construction techniques of the invention. Best Mode for Carrying Out the Invention Referring now to Figure 1, the legend for the insulating substrate (S), the first level metal layer or conductor number 1 (C₁), the insulating layer (I), the resistive layer (R), and the second level conductor or conductor number 2 (C2) apply to all of the four process embodiments described herein as will be indicated in more detail below. Additionally, a table of values for materials, layer thicknesses, resistivities and other significant electrical properties is given below for the various layers formed in the different embodiments of the invention. Accordingly, these various device properties will not be further recited throughout the specification. In a first embodiment of the invention, an insulating substrate 10 is adapted to recieve a first level metal layer 12 which is sputtered or evaporated on the surface of the substrate 10 using conventional metal deposition techniques. Then, as indicated in Figure 1B, the metal layer 12 is patterned to form a first level metal conductor 14. Next, an insulating layer 16 is provided as shown in Figure 1C and then patterned as indicated in Figure 1D to provide an opening 18 therein. Then, a resistive layer 20 is deposited on the surface of Figure 1D to form the structure of Figure 1E which is subsequently masked and etched to leave the vertical resistor pad 22 as shown in Figure 1F. When the resistor pad 22 is to be formed as a combination resistor/diode component for use in diode matrix multiplex circuits, then the resistive layer formation step of Figure 1E must include appropriate PN junction processing such solid state diffusion, ion-implantation, or metal-semiconductor rectifying junction forming processes known in the art. One suitable process for forming a PN junction in the resistor pad 22 would be to first form the pad 22 of polycrystalline silicon using, for example, low-pressure chemical vapor deposition, LPCVD. Then, phosphorous ions can be implanted into the polysilicon pad 22 in a concentration between 10¹⁹ and 10²¹ ions per cubic centimeter and then annealed in a nitrogen atmosphere from between 3-4 hours. Alternatively, this PN junction could be replaced by a Shottky barrier junction which is created by first forming a P-type polysilicon resistor pad and then depositing a gold conductor on this resistor pad to establish a Shottky barrier junction at the polysilicon-gold interface, as is well known in the art. Next, as shown in Figure 1G, a top surface layer or second level metal layer 24 is deposited on the surface of the structure whereafter the conductive pattern 24 is further defined such as by selective etching to leave the second level metal conductor 26 with the geometry shown in Figure 1H. Using photolithographic exposure, masking and etching techniques known to those skilled in the art, one may topographically define the multiplex circuit shown in Figure 1I. In this figure, the substrate 10, the first level metal conductor 14, the insulating layer 16, the heater resistor 22 and the second level metal conductor 26 are designated with reference numerals corresponding to like reference numeral indicating the same materials in previous Figures 1A - 1H. The following TABLE is applicable to all of the fabrication sequences described herein: In Figure 1I, there is shown a multiplex connection of lower electrical leads 1 and 2 used in combination upper electrical leads I and II and connected to fire the resistor/diodes indicated as A, B and C. Thus, a multiplexed combination of leads 1 and I fires resistor/diode A and a multiplexed combination of leads 1 and II fires resistor/diode C. Alternatively, a multiplexed combination of leads 2 and I will fire resistor/diode B. Referring now to Figures 2A - 2G, an insulating substrate 28 is disposed to recieve a first level metal layer 30 of Figure 2A which is then patterned as shown in Figure 2B to provide a first level metal conductor 32. Then, an intermediate insulating layer 34 is deposited as shown in Figure 2C and defined as shown in Figure 2D to leave an opening 36 therein and identical thus far to the process of Figure 1. However, at this point the resistive layer 38 is deposited over the entire top surface of the structure as shown in Figure 2E and is there left intact. Next, an upper, second level metal layer 40 is deposited over the entire surface of the resistive layer 38 as indicated in figure 2F, and thereafter the second level metal conductor pattern is defined as shown in Figure 2G. Referring now to Figure 2H, the multiplex circuit connection shown therein is the same for both the above process of Figure 2A - 2G and the process of Figures 4A - 4G to be described below. In Figure 2H, multiplex signals applied to leads 1 and I will fire the resistor/diode A, whereas multiplex signals applied to leads 1 and II will fire resistor/diode C. Signals applied simultaneously to leads 2 and I will fire the resistor/diode B. Referring now to Figure 3A, in this process embodiment a resistive cover layer 46 is applied as shown to the upper surface of a first level metal layer 48 which in turn was previously formed on the upper surface of an insulating substrate 50. Then, using conventional masking and etching processes, a resistive island 52 is developed as shown in Figure 3B to define the heater resistor. Then, as shown in Figure 3C, the resistive island 52 is used as an etch mask to form the first level metal conductor 54. Next, an intermediate insulating layer 56 is deposited as shown in Figure 3D, and then this layer 56 is masked and etched to form the opening 58 therein as shown in Figure 3E. Then, an upper, second level metal layer 60 is formed atop the entire surface of the structure as shown in Figure 3F and thereafter defined using photolithographic metal etch processes known in the art to form the upper or second level metal conductor pattern 62 as shown in Figure 3G. Referring now to Figure 3H, the firing schedule for the multiplex circuit shown in this figure is identical to the firing schedule of the multiplex circuits shown in Figures 1I and 2H previously described. Referring now to Figure 4, there is shown a forth process embodiment according to the invention. In this embodiment the substrate 64 and first level metal layer 66 of Figure 4A are masked and etched to define a first level metal conductor 68 as shown in Figure 4B. Then, a resistive layer 70 is deposited over the entire surface of the structure of Figure 4B to thereby provide the layered structure as shown in Figure 4C. Next, the structure of Figure 4C is provided with an intermediate insulating layer 72 as shown in Figure 4D which is then masked and etched to provide an opening 74 therein as shown in Figure 4E. Then, an upper second level conductive layer 76 is deposited across the entire surface of the structure as shown in Figure 4F, and finally this conductive layer 76 is photolithographically defined as a second metal level or upper conductor 78 on the top surface of Figure 4G. As previously mentioned, the multiplex circuit of Figure 2H is applicable to the present process of Figure 4, and device structure produced thereby and is not described in further detail herein. Referring now to Figure 5, there is shown in Figure 5A a nine resistor-diode (RD) multiplex circuit which illustrates how the previously described 3-diode (A,B,C) networks of Figures 1-4 can be expanded into a larger X-Y multiplex matrix. In this matrix of Figure 5A, there is no specific relation between the resistor-diode combinations shown therein and the A, B and C diodes of Figures 1-4 which are primarily intended to show a general plan view layout for the adjacent resistor-diodes. In Figure 5A, each resistor-diode (RD) combination fires when a positive-going pulse is applied to the anode of the diode and simultaneously a negative-going pulse is applied to the cathode of the diode. Hence, the timing schedule no. 1 in Figure 5C represents the firing of resistor-diodes RD₁, RD₂ and RD₃ at times t=2, t=3 and t=4 for the six pulse waveforms applied to the X-Y matrix terminals 1, 2 and 3 and I, II and III, respectively. However, when the pulse waveform in Figure 5B is applied to terminal no. 1 in Figure 5A, both resistor-diodes RD₃ and RD₄ will fire at time t=4. Thus, it will be appreciated by those skilled in the art that using the proper selection of pulse waveforms at the X-Y matrix input terminals, any resistor-diode combination in Figure 5A can be fired. This feature greatly enhances the packing density and integration of resistors, diodes and conductive trace patterns on the ink ejection surface area of a printhead substrate. Industrial Applicability This invention is useful in the production of thermal ink jet printheads and printhead integrated circuits which in turn are used in disposable ink jet heads in TIJ printers.

Claims: A process to fabricate a thermal ink jet thin film resistor device for use in a thermal ink jet printhead device, the process comprising the steps of: (a) forming a conductive pattern (14,32,54,68) atop an upper surface of a substrate member (10,28,50, 64); (b) forming an insulating layer (16,34,56,72) on said conductive pattern (14,32,54,68), said insulating layer (16,34,56,72) having openings (18,36,58,74) therein aligned with preselected areas on said conductive pattern; (c) forming a resistive layer (22,38,52,70) of a selected resistivity on said preselected areas on said conductive pattern (14,32,54,68), and (d) depositing a metal barrier layer (26,42,62,78) atop said resistive layer (22,38,52,70), whereby said metal barrier layer provides an electrical path for current flowing through said resistive layer (22,38,52,70) and also shields said resistive layer (22,38,52,70) against ink corrosion and cavitation wear. A process according to claim 1 which includes the intermediate step of forming a PN or other rectifying junction in said resistive layer whereby said device may be used as a diode matrix multiplex circuit. A thermal ink jet printhead comprising a thin film resistor device providing a plurality of thin film heater resistors for heating ink, which thin film resistor device comprises: (a) a substrate member (10,28,50,64); (b) a conductive pattern (14,32,54,68) disposed atop an upper surface of said substrate member (10,28,50,64); (c) an insulating layer (16,34,56,72) disposed on said conductive pattern (14,32,54,68) and having openings (18,36,58,74) therein aligned with preselected areas on said conductive pattern; (d) a resistive layer (22,38,52,70) of a selected resistivity formed on said preselected areas on said conductive pattern (14,32,54,68), and (e) A metal barrier layer (26,42,62,78) disposed atop said resistive layer (22,38,52,70), whereby said metal barrier layer provides an electrical path for current flowing through said resistive layer (22,38,52,70) and also shields said resistive layer (22,38,52,70) against ink corrosion and cavitation wear. A thermal ink jet printhead device according to claim 3 wherein said resistive layer (22,38,52,70) comprises a rectifying junction diode defined therein, whereby said thin film resistor device may be used as a diode matrix multiplex circuit.

Inventors: BEARSS JAMES G, BHASKAR ELDURKAR V, HACKLEMAN DAVID E, BEARSS, JAMES G., BHASKAR, ELDURKAR V., HACKLEMAN, DAVID E.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1987
Main classification: B41J2
IPC codes: B41J2, H01L49