A CIRCUIT FOR BIASING A MAGNETORESISTIVE SENSOR AND AMPLIFYING SIGNALS PRODUCED THEREBY

Abstract: The resistance (Rh) of a magnetoresistive sensor is disposed between the bases of a differential pair of transistors (T1a and T1b) comprising the input stage of an amplifier. Constant bias voltage for the sensor is provided (by J1 and RE) independently of the resistance of the sensor. DC feedback (from g₀) to the input stage balances current flow in both paths of the differential input stage to correct for DC offset arising in the output from the input stage emitter resistor (RE). The amplified signal represents ΔR h /R h , where ΔR h is the change in steady-state resistance, R h , of the sensor.

Description: This invention relates to a circuit for biasing a magnetoresistive sensor and amplifying signals produced thereby. Most existing magnetoresistive (MR) sensors, including particularly sensors for bubble memories and magnetic recording, are biased at a constant bias current by preamplifiers which detect the signal voltage developed at the sensor terminals. Since stripe height is inversely proportional to sensor resistance, and varies from sensor to sensor owing to production variations and varies over the life of the sensor in contact recording applications owing to wear, it is desirable to detect signals produced by the sensor which are independent of stripe height. Thus, it is desirable to detect and amplify a voltage or a current representing ΔR h /R h , where ΔR h is the change in MR sensor resistance, R h , arising from the magnetic input signal from the media being read. European Patent Application No. EP-A-0 241 770, relevant under Article 54(3) EPC, discloses a transimpedance amplifier for biasing a magnetoresistive sensor with a current having a constant time average value, and for amplifying deviations from said constant value produced by changes in the steady-state value of the resistance of the sensor. DC feedback is used to balance the current flow in both paths of a differential input stage to correct for DC offset voltage which can otherwise develop at the output. The invention provides a circuit for biasing a magnetoresistive sensor at a constant bias voltage and for amplifying signals produced thereby, said circuit comprising: a magnetoresistive sensor having a steady state resistance value; amplifier means having an input stage responsive to voltage deviations from said constant bias voltage value across said sensor to produce at an output stage of said amplifier means an amplified output signal representing the change in the steady state resistance value of the sensor arising from changes in the magnetic field to which the sensor is exposed; said input stage including at least two transistors coupled in differential pair configuration and having the magnetoresistive sensor coupled between the bases of said pair of transistors, and an emitter resistor coupled between the emitters of said differential pair of transistors, the emitter of one of said pair of transistors being coupled to a first constant current source, said amplifier means including link means coupling said emitter resistor to the bases of said differential pair of transistors, whereby said bias voltage is referenced to a voltage produced by a current from said first constant current source flowing through said emitter resistor. Two embodiments of an enhanced voltage amplifier embodying the invention are described herein for constant voltage biasing and amplifying the signals produced by an MR sensor. In both circuits, the differential input stage has built-in offset correction derived from emitter resistors and a high impedance current source. The circuits differ in configuration of the transconductive feedback employed to minimise the DC error signal at the amplifier output. Electrically, the resistance, R h , of the MR sensor is disposed between the bases of a differential pair of transistors comprising the input stage of the amplifier. The voltage which biases the MR sensor is held constant because it is provided independently of sensor resistance as the product of the input stage emitter resistor and one-half of the current from a constant current source. In circuit configurations embodying the present invention, the signal representing ΔR h /R h is sensed as a time-varying voltage across the MR sensor. The steady-state value of R h refers to the resistance value of R h while biased but not sensing magnetic field variations. The input stage of the amplifier may be replicated as many times as there are MR sensors in a given system. The remaining components of the amplifier comprise the output and feedback stages which are common to all, and switched among, the input stages in a multiple-head system. Additional circuitry may be added to shorten settling time when MR sensors are activated and deactivated in a multiple sensor system. How the invention can be carried out will now be described by way of example, with reference to the accompanying drawings, in which: Figs. 1A and 1B are basic block diagrams of two amplifiers embodying the present invention; Fig. 2 is a circuit diagram of an amplifier implemented according to Fig. 1A; Fig. 3 is a block diagram which shows the coupling of selectable input stages to the common stage of the amplifier; Fig. 4 is a circuit diagram of each of the selectable input stages of the amplifier of Fig. 3; Fig. 5 is a circuit diagram for the common stage of the amplifier of Fig. 3; Fig. 6 is a circuit diagram of an amplifier implemented according to Fig. 1B; and Fig. 7A and 7B are circuit diagrams of enhancements for reducing the settling time of the amplifiers of Figs. 5 and 6 when MR sensors are activated and deactivated in a multiple-sensor system. Referring first to Figs. 1A and 1B, transistors T1a and T1b form a differential input amplifier stage having built-in offset emitter resistor RE. J1 is a high input impedance current source so that this input stage provides true differential signal processing for AC signals. DC and low frequency error at the output, namely at R4a and R4b, is minimised by feedback circuits in both configurations. The magnetoresistive sensor, shown as an equivalent circuit comprising resistor R h and voltage source V i , is coupled between the bases of transistors T1a and T1b. In the configurations of Figs. 1A and 1B, the output of the feedback stage, g₀, is a current and the input to the feedback is a voltage. Thus, the feedback amplifier g₀ is a transconductance amplifier. An RC network is incorporated into amplifier G in Fig. 1A to provide a dominant pole to separate low frequency error signals from high frequency information signals. The error signal is subtracted from the information signal, V i , at the bases of transistors T1a and T1b. When the error signal is minimised, current from current source J1 is divided equally through transistors T1a and T1b to create a voltage reference, V re , across emitter resistor RE equal to the product of RE and one-half of the current supplied by current source J1. Thus, V re appears between the bases of transistors T1a and T1b and is therefore the voltage which biases MR sensor, R h , independently of the resistance value thereof. In the configuration of Fig. 1A, differential voltage gain stage G couples the input differential stage transistors T1a and T1b to the transconductance amplifier g₀. In addition, as described elsewhere in this specification, gain stage G provides a dominant pole for control of low frequency error signals. The DC voltage across sensor R h is kept constant independently of the value of R h by controlling the current therethrough. The configuration of Fig. 1A provides a ground potential at the common connection of input resistors R1a and R1b which becomes the average potential of the MR sensor. If the average potential of the sensor is ground, corrosion and electrostatic discharge is reduced, and reliability of the sensor is enhanced. However, the average potential of the MR sensor could also be placed at any desired voltage with this circuit. In the configuration of Fig. 1B, transconductance amplifier g₀ comprises a single-ended, push-pull feedback stage with a capacitor at the output. The current through sensor R h is controlled in the same manner as described for the configuration of Fig. 1A. Resistors R1a and R1b determine the amplifier input impedance and act as part of the RC network in a resistor divider configuration with sensor R h . In the configuration of Fig. 1B, capacitor C also reduces noise associated with amplifier g₀ at information signal frequencies. Referring now to Fig. 2 with continuing reference to Fig. 1A, amplifier G comprises a differential voltage follower and the input to transconductance stage g₀. The differential voltage follower includes transistors T3a and T3b, resistors R2a and R2b and current sources J3a and J3b. The input portion to the transconductance stage includes transistors T4a and T4b, resistors R3a and R3b, capacitor C, and current source J4. The remainder of the transconductance stage, g₀, is a current mirror comprising transistors D1a and D1b, T2a and T2b, and current sources J2a and J2b. The general voltage gain transfer function of the entire amplifier is given by The terms for Equation (1) are defined as follows: R b = series base resistance of T₁ B = forward current gain rE = ( k T / q Ic₁ ) rb = series base resistance of T₄ (includes R2) re = ( k T / q Ic₄ ) f t = device transition frequency f pole = dominant pole frequency R h = MR head resistance (steady-state value) Ic₁ = collector current of T₁ Ic₄ = collector current of T₄ k = Boltzmann's constant T = absolute temperature q = electron charge The voltage gain transfer function at high frequencies is given by: The voltage gain transfer function at low frequencies is given by: Transfer functions (1), (2) and (3) are approximate in that they do not consider the transition frequency of transistors nor transistor forward current gain variations. The amplifier has a high pass frequency characteristic. In order to facilitate switching from one MR sensor to another in a multiple sensor system, the circuit of Fig. 2 may be separated into a number of selectable input stages, g₁, g₂, ... g n , each of which is dedicated to one MR sensor. Such input stages are coupled to a common stage, g c , as shown in Fig. 3. Referring to Figs. 4 and 5, input stages g₁ through g n are coupled to common stage, g c , at nodes N1, N2, NF1 and NF2. Transistors T33 and T34 are coupled in cascode to extend the high frequency response when several input stages are coupled to the common stage. Common stage g₀ comprises the voltage follower stage and the input to the transconductance stage of Fig. 2. The RC network to form the dominant pole is located in common stage, g₀, to reduce the number of capacitors required. The RC network comprises capacitor C and resistors R3a and R3b. If resistors R5a, R5b, R5c and R5d in Fig. 4 are equal and resistors are R6a, R6b, R6c, R6d, R6e and R6f are equal, then the transconductance gain will be the same as the gain for the amplifier of Fig. 2 if the emitter area ratios of transistors D1a, D1b, T2a, T2b, D6a and D6b, T6a, T6b, T6c and T6d are equal and current source J6 equals current source J4. To select a desired input stage g₁, current sources JOa, J1, J5 and J6a must be simultaneously activated. The deselected input stage is similarly deactivated by deactivating corresponding current sources. Transistors T6a and T6b correspond to current sources J2a and J2b of Fig. 2. Current source J5, resistor R8 and transistors D5, T5a, T5b and T7 are included to select the appropriate current mirrors as different MR sensors are activated. Feed forward control is used to minimise the DC offset at the output of the common stage while preserving low frequency steady-state bandwidths. Referring to Figs. 4 and 5, current from current source J0b is mirrored by the current mirror comprising D16 and T2b and flows into one terminal of R h while current from current source J0a is drawn from the other terminal of R h . Thus, an offset current is provided through R h whose optimum value is given by With continuing reference to Figs. 4 and 5, the currents provided by current sources J6a and J6b are equal during steady-state operation of the circuit. These currents may be temporarily increased during switchover, that is, when activating and deactivating input stages. To control and reduce transient settling time of the circuit, the currents from J6a and J6b are controlled by an added control line to change the value of the current at the moment of switchover. Thereafter, the sources may be returned to their original value after transients have been given a chance to settle. By increasing the current available from current sources J6a and J6b, the current available to charge or discharge capacitor C is thereby temporarily increased and the loop gain of the circuit is correspondingly increased. Alternatively switchover transient recovery can be controlled by using the feedback circuit configuration of Fig. 7A. Operation of the circuit of Fig. 7A is described in European Patent Application No. EP-A-0 241 770. Nodes N3a, N3b, N4a, and N4b, are coupled to the corresponding nodes of the common stage of Fig. 5. The configuration of Fig. 1B is implemented according to the circuit of Fig. 6 wherein two selectable input stages are shown. Block g₀ consists of a differential voltage follower and a push-pull transconductance stage. The differential voltage follower consists of transistors T3a and T3b, resistors R2a and R2b and current sources J3a and J3b. The push-pull transconductance stage comprises an input stage and left and right current mirrors. The input stage includes transistors T4a and T4b and current source J4. The left current mirror includes transistors D1b, T2b, T27 and T6 and resistors R5c, R5d, R6 and R28. The right current mirror consists of transistors D1a and T2a and resistors R5a and R5b. The resistor divider network of Fig. 1B is selectable in the circuit of Fig. 6. The output of the transconductance amplifier at node 5 is also the common connection for the multiple resistor divider networks. The desired divider network is selected simultaneously with selection of the desired sensor/input-amplifier combination. Thus, for example, if sensor R ha is desired, transistors T29 and T31 are activated simultaneously by applying the appropriate control signal at control node "sel a", which simultaneously selects the desired divider network and the sensor/input-amplifier. Similarly, if sensor R hb is desired, an appropriate control signal is applied at control node "sel b". For the circuit configuration shown, the control signal applied at either input node is a negative voltage. The general voltage gain transfer function of the amplifier of Fig. 6 is given by for f t >> f pole where terms for Equation (5) are defined elsewhere in the specification. Voltage gain transfer function at high frequencies for the circuit of Fig. 6 is given by Voltage gain transfer function at low frequencies for the circuit of Fig. 6 is given by Transfer functions (5), (6) and (7) are approximate in that they do not consider the transition frequency of transistors nor transistor forward current gain variations. The amplifier of Fig. 6 also has a high pass frequency characteristic. As in the circuit configuration of Figs. 4 and 5, feed-forward control is used to minimise DC offset at the output. Current source J0 supplies an offset current through the activated R h . The optimum value of such offset current may be estimated by the relation In a manner similar to that for the circuit configuration of Figs. 4 and 5, the transconductance amplifier gain and the current available to charge or discharge capacitor C can be increased to control switchover transient settling time of the circuit. The increase of gain and charge or discharge current is provided in the same manner as previously described for the circuit configurations of Figs. 4 and 5. Alternatively, switchover transient recovery time can be controlled by using the circuit of Fig. 7B, the operation of which is described in European Patent Application No. EP-A-0 241 770. Nodes 5, 6A and 6B are identified to indicate connection of this circuit at correspondingly identified nodes of the circuit of Fig. 6.

Claims: A circuit for biasing a magnetoresistive sensor at a constant bias voltage and for amplifying signals produced thereby, said circuit comprising: a magnetoresistive sensor (Rh) having a steady state resistance value; amplifier means having an input stage responsive to voltage deviations from said constant bias voltage value across said sensor (Rh) to produce at an output stage of said amplifier means an amplified output signal representing the change in the steady state resistance value of the sensor (Rh) arising from changes in the magnetic field to which the sensor (Rh) is exposed; said input stage including at least two transistors (T1a, T1b) coupled in differential pair configuration and having the magnetoresistive sensor coupled between the bases of said pair of transistors (T1a, T1b), and an emitter resistor (RE) coupled between the emitters of said differential pair of transistors (T1a, T1b), the emitter of one transistor of said pair of transistors (T1a, T1b) being coupled to a first constant current source (J1), said amplifier means including link means coupling said emitter resistor (RE) to the bases of said differential pair of transistors (T1a, T1b), whereby said bias voltage is referenced to a voltage produced by a current from said first constant current source (J1) flowing through said emitter resistor (RE). A circuit as claimed in claim 1, wherein the current flowing in each of the emitters of said differential pair of transistors (T1a, T1b) is substantially equal. A circuit as claimed in any preceding claim, wherein the output stage comprises two resistors (R4a, R4b) having substantially equal resistance value. A circuit as claimed in any preceding claim wherein said link means comprises feedback means coupled from the output stage to the input stage for correcting variations in said bias voltage levels. A circuit as claimed in claim 4, wherein the collectors and bases of said first differential pair of transistors (T1a, T1b) are coupled to the feedback means and the emitters of said first differential pair are coupled to the first constant current source. A circuit as claimed in claim 4 or claim 5, wherein the feedback means includes: at least two transistors (T4a, T4b) coupled in a second differential pair configuration for correcting the voltage at the bases of the first differential pair; and first and second follower transistors (T3a, T3b), coupled to the first differential pair of transistors (T1a, T1b), for coupling the variations in the voltage produced in the input stage to the second differential pair of transistors (T4a, T4b); said second differential pair being coupled to a second constant current source (J4), and said follower transistors (T3a, T3b) being coupled to third (J3a) and fourth (J3b) constant current sources, respectively. A circuit as claimed in any preceding claim, further including feedforward means, coupled to the input and output stages, for controlling the DC offset voltage at the output of the output stage. A circuit as claimed in any of claims 4 to 7, wherein the feedback means includes frequency setting means to set the frequency response of the circuit. A circuit as claimed in claim 8, wherein the frequency setting means is a capacitor. A circuit as claimed in any preceding claim, further including: a plurality of input stages (G,...Gn); and selection means for activating one of the plurality of input stages and deactivating all of the remaining plurality of input stages. A circuit as claimed in claim 10, further including settling means for reducing the time required for said circuit to settle into steady-state operation after one of said plurality of input stages is deactivated and another of said input stages is activated or after activating any input stage. A circuit as claimed in claim 11, wherein the settling means comprise control means for temporarily increasing the available output drive current of said feedback means during activation of any of said plurality of input stages. A circuit as in claim 11, wherein the settling means comprises first and second comparator means coupled to the output of said input stage for controlling the DC offset voltage thereat in response to a change in such DC offset voltage during deactivation of one and activation of another input stage. A circuit as claimed in any of claims 11 to 13, wherein said selection means is effective for deactivating all of said input stages.

Inventors: JOVE, STEPHEN ALAN, KLAASSEN, KLAAS BEREND, NOMURA, CALVIN SHIZUO, VAN PEPPEN, JACOBUS CORNELIS LEONARDUS
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: G01R33
IPC codes: G11B5, G01R33