OVERCURRENT DETECTOR

Abstract: A circuit breaker has a phase selecting circuit (400) for selecting one phase among plural phases, in which the largest current flows. After selecting the largest phase, the judgement whether an accidental overcurrent flows or not in executed by using only output signals from the selected largest phase.

Description: The present invention relates generally to an overcurrent detector which can prevent an erroneous operation. FIG. 7 shows a circuit breaker having an overcurrent detector which is disclosed in EP-A-0 133 968. In FIG. 7, on a set of power lines, namely R, S and T of three phase power lines 10, current transformers 21,22 and 23 of a current sensor means 200 are provided, respectively. Full-wave rectifiers 31, 32 and 33 are connected each with their two input lines across both output lines of the current transformers 21, 22 and 23, respectively. Burden circuits 41, 42 and 43 are connected with their input lines to output lines of the full-wave rectifiers 31, 32 and 33, respectively, and one of the input lines of each of the burden circuits 41, 42 and 43 are connected in common to the ground. The other input terminals of the burden circuits 41, 42 and 43 are connected to input terminals of an OR circuit 130, which consists of three diodes 131, 132 and 133, the output terminals of which are connected in common as an output terminal of the OR circuit 130. Adjustable output terminals of the burden circuits 41, 42 and 43, wherefrom output signals can be obtained in desirably adjusted levels, are connected to input terminals of mean/effective value circuits 91, 92 and 93 of mean/effective value means 90, which produce mean values or effective values of the signals from the burden circuits 41, 42 and 43. The output terminals of the mean/effective value circuits 91, 92 and 93 are connected to input terminals of OR circuit 160 which consists of three diodes 161, 162 and 163 and issues an output signal to the A/D converter 100. A microcomputer 110 is connected to the output terminal of the A/D converter 100. The output terminal of the OR circuit 130, as a second output terminal of the sensor means 200, is connected to the A/D converter 100 and the microcomputer 110 through a power source circuit 300, which is generally a constant voltage circuit. Furthermore, the second output terminal of the current sensor means 200 is connected to a second level discrimination circuit 140 which, for instance, comprises at least one zener diode. The second level discrimination circuit 140 is connected to a second time-current operating circuit 150. Output terminals of the microcomputer 110 and the second time-current operating circuit 150 are connected to an output circuit 120 through an OR gate 121. The output circuit 120, for instance, comprising a thyristor, actuates a releasing device 80 for carrying out disconnection of line switches 201, 202 and 203. An indicator 180 is provided for indicating that the releasing device 80 has operated. The microcomputer 110 comprises a first level discrimination means and a first time-current operating means as is described later herein. The current sensor means 200 issues from the mean/effective value circuit 90 signals corresponding to mean values or effective values of the current in the power lines R, S and T, and also issues from the OR circuit 130 the second output signal corresponding to peak value of the current in the power line R, S and T. The second output signal of the current sensor means is given through the second level discrimination circuit 140 to the second time-current operating circuit 150. The A/D converter 100 and the microcomputer 110 are fed with a constant voltage DC current from the power source circuit 300. When overcurrent(s) flow(s) in the AC power lines 10, output currents of the current transformers 21, 22 and 23, which are coupled to the AC power lines R, S and T of the AC power lines 10, correspondingly produce output currents at predetermined transforming ratio. The output currents are rectified by the full-wave rectifiers 31, 32 and 33, respectively. The rectified output currents of the full-wave rectifiers 31, 32 and 33 are fed to respective burden circuits 41, 42 and 43. The output signals of the burden circuits 41, 42 and 43 are transformed into mean values or effective values thereof by mean/effective value circuits 91, 92 and 93 of the mean/effective value circuit 90. A largest signal among the output signals of the mean/effective value circuits 91, 92 and 93 is given to A/D converter 100. This digital signal is fed to the microcomputer 110. The microcomputer 110 carries out level discrimination of digital input signal thereto in accordance with a predetermined program stored in a read-only memory 114. Furthermore, basing on the results of the level discrimination, a predetermined time-current operation is carried out, thereby to issue an output signal. That is, the microcomputer 110 functions as the first level discrimination means and the first time-current operating means. The above-mentioned time-current operation is carried out, for instance, along the inverse long time-current characteristic of part A of FIG. 5. The output signal issued from the microcomputer 110 is fed to the gate of the thyristor 120, which is then turned on to drive the output device 80. Accordingly, the overcurrent indicator 180 indicates the occurrence of the overcurrent and at the same time the releasing device 80 actuate the interrupting connectors 201, 202 and 203. The above-mentioned time-current characteristic of the curves A, B and C are designed by taking account of the capacity of fuses in the upper stream part of the power line 10. On the other hand, the outputs of the full-wave rectifier 31, 32 and 33 are given to the OR circuit 130 comprising diodes 131, 132 and 133. Since the output terminal of the OR circuit 130 is connected to the second level discrimination circuit 140 which, for instance, comprises at least one zener diode, when one input signal to the OR circuit 130 exceeds the second level, the discrimination circuit 140 gives an output signal to the second time-current operating circuit 150, which accordingly carries out necessary time-current operation, and thereby triggers the gate of the thyristor 120. The time-current operation in this case is, for instance, a short time current inverse characteristic as shown by part B of FIG. 5 or an instantaneous time-current characteristic as shown by part C of FIG. 5. By the above-mentioned turn-on of the thyristor 120, the output device 80 is actuated, thereby its indicator 180 indicates the overcurrent and also drives the interruption connectors 201, 202 and 203. In such prior art circuit breaker, it is necessary to detect the mean/effective value of accidental overcurrent in respective phases and to select the maximum (output of OR circuit) value among the mean/effective values of three phases. Furthermore, if the selected phase frequently changes due to the varying of the input signals of respective phases, the accurate detection of phase difference of the input signal or transmitting of the mean/effective value becomes difficult. Therefore, the circuit becomes complex and expensive and it needs a process for adjusting the output level of each of the mean/effective value circuits. It thus is the object of the invention to provide an improved overcurrent detector having simple circuit which has very low possibility of an erroneous operation. This object according to the present invention is solved by the advantageous features indicated in claim 1. The features of claim 1 are partially already known from EP-A2-0 289 042. In detail, this Document shows an overcurrent detector which comprises a current sensor means for detecting the values of the currents in the respective phases of an AC power line; phase selection means for selecting the largest of the detected current values by comparing the respective mean values of said detected current values with a selecting threshold value, which threshold value is obtained by multiplying the mean value of the currently selected current value by a coefficient greater than 1; signal conversion means for obtaining a mean or an effective value of the current value selected by said phase selection means; and processing means for processing the output signal of said signal conversion means and for issuing a releasing signal. EP-A2-0 289 042, however, is a Document which falls under the terms of Article 54(3) EPC, i.e. is relevant to the subject-matter of the present invention only with respect to novelty. The present invention will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings, in which FIG. 1 is a circuit block diagram showing a preferred embodiment of a circuit breaker in accordance with the present invention; FIG. 2 is a circuit diagram showing a phase selecting circuit 400 of the circuit breaker shown in FIG. 1; FIG. 3 is a block diagram of a microcomputer 110; FIG. 4 is a flow chart showing operation of the microcomputer shown in FIG. 3; FIG. 5 is the current vs. time characteristic graph of a circuit breaker of the prior art; FIG. 6 is a circuit block diagram showing an overcurrent detector in accordance with the present invention; and FIG. 7 is a circuit block diagram showing a circuit breaker of the prior art. Hereinafter, details of the invention are described with reference to the drawings. In FIG. 1, on a set of power lines R, S and T of three phase power lines 10, current transformers 21, 22 and 23 of a current sensor means 200 are provided, respectively. Full-wave rectifiers 31, 32 and 33 are connected each with their two input lines across both output lines of the current transformers 21, 22 and 23, respectively. Burden circuits 41, 42 and 43 are connected with their input lines to output lines of the full-wave rectifiers 31, 32 and 33, respectively, and one of the input lines of each of the burden circuit 41, 42 and 43 is connected to a respective input terminal of an OR circuit 130, which consists of three diodes 131, 132 and 133, the output terminals of which are connected in common as an output terminal of the OR circuit 130. Adjustable output terminals of the burden circuits 41, 42 and 43, wherefrom output signals can be obtainable in desirably adjusted levels, are connected to input terminals of phase selecting circuit 400 having a predetermined operation characteristic. The phase selecting circuit 400 selects, as largest phase, a phase which consists of largest value in inputted values. The largest phase selected by the phase selecting circuit 400 is connected to a signal conversion circuit 900 for obtaining a mean or an effective value of inputted value. The converted output signal of the signal conversion circuit 900 is converted from analog signal into digital signal by an A/D converter 100. The digital output of the A/D converter 100 is inputted to a microcomputer 110. The output of the microcomputer 110 is connected to a gate of thyristor 120 for operating a releasing device 80. The releasing device 80 actuates the disconnectable contact to disconnect. The output of the OR circuit 130 is connected to a second time-current operating circuit 150 through zener diodes 140. An output of the second time-current operating circuit 150 is connected to the gate of thyristor 120 for operating the releasing device 180. The releasing device 80 disconnects the disconnectable contacts 201, 202 and 203 in response to on state of the thyristor 120. A concrete circuit constitution of the phase selecting circuit 400 having a predetermined operation characteristic is shown in FIG.2. Three input terminals 401, 402 and 403 receive output signals from each burden circuits 41, 42 and 43 respectively, and output to operational amplifiers OP₁, OP₂ and OP₃. Each operational amplifiers serve as unity-gain amplifiers, and respective output terminals are connected to one terminals of resistors R₁, R₂ and R₃ and to input terminals of analogue switches AS₁, AS₂ and AS₃. The other terminals of the resistors R₁, R₂ and R₃ are connected to one terminals of capacitors C₁, C₂ and C₃ and to positive input terminals of operational amplifiers OP₄, OP₅ and OP₆, respectively. Output terminals of the operational amplifiers OP₄, OP₅ and OP₆ are connected to anode terminals of diodes D₁, D₂ and D₃, respectively. Cathode terminals of the diodes D₁, D₂ and D₃ are commonly connected with each other to have the same potential, and also connected to negative input terminals of the operational amplifiers OP₄, OP₅ and OP₆ through resistors R₁₆, R₁₇ and R₁₈, respectively. The above-mentioned circuit constitutes a detecting circuit for selecting such a phase in which the largest output is issued. Output terminals of the operational amplifiers OP₄, OP₅ and OP₆ are connected to anode terminals of diodes ZD₁, ZD₂ and ZD₃, respectively, and cathode terminals of the diodes ZD₁, ZD₂ and ZD₃ are connected to bases of transistors TR₁, TR₂ and TR₃ through resistors R₄, R₅ and R₆, respectively. All the transistors TR₁, TR₂ and TR₃ are PNP type transistors, and the collectors of them are connected to negative electric power source -Vcc. Resistors R₁₀, R₁₁ and R₁₂ are connected between the respective bases and collectors of transistors TR₁, TR₂ and TR₃, respectively, for applying biasing potential. Resistors R₇, R₈ and R₉ are connected to emitters of the transistors TR₁, TR₂ and TR₃, respectively, at one terminals thereof, and the other terminals thereof are commonly connected to positive power source Vcc. The emitters of the transistors TR₁, TR₂ and TR₃ are connected to gate terminals of the analogue switches AS₁, AS₂ and AS₃, respectively. Output terminals of the analogue switches AS₁, AS₂ and AS₃ are commonly connected to an output terminal 404 of the phase selecting circuit 400. The emitters of the transistors TR₁, TR₂ and TR₃ are connected to the gate terminals of the analogue switches AS₄, AS₅ and AS₆, respectively. The input terminals of the analogue switches AS₄, AS₅ and AS₆ are connected to the ground, and the other terminals thereof are connected to negative input terminals of the operational amplifiers OP₄, OP₅ and OP₆ through resistors R₁₃, R₁₄ and R₁₅, respectively. Hereupon, the positive electric power source VCC, the negative electric power source -Vcc and the ground GND are connected to a power source for driving the operational amplifiers OP₁ to OP₆ and the analogue switches AS₁ to AS₃. The constitution and operation of the microcomputer 110 are described with reference to FIGs. 3 and 4 hereafter. FIG. 3 is a circuit block diagram of the microcomputer 110. As shown in FIG. 3, the microcomputer 110 comprises a central processor unit 111, a read-only memory 114, a random-access memory 115, an I/O port 116, a data bus 112 and an address bus 113. Parts of the data bus 112 and the address bus 113 are also connected to the A/D converter 100. The read-only memory 114 stores a program for executing necessary signal processing, and also data for a long time characteristic, a short time characteristic and an instant time characteristic of the first time-current operating means. The central processor unit 111 contains clock signal means necessary therefor. The random-access memory 115 functions as a register which is necessary for the signal processing. FIG. 4 is a flow chart of the computer program for the microcomputer 110. The flow chart contains a first level-discrimination step (a step 1001) and a first time-current operating step (a step 1002) for performing a first time-current operation in response to the output of the first level discrimination means. The flow chart also contains decrement means (a step 1003) for decreasing the register in response to radiation characteristics. Such reset means (the step 1003) operates when at least one of the input signal of the time-current operation (the step 1002) or the second time-current operating a circuit 150 (in FIG. 1) becomes below a predetermined level. When overcurrent(s) flows in the AC power lines 10, output currents of the current transformers 21, 22 and 23, coupled to the AC power lines R, S and T of the AC power lines 10, correspondingly produces output currents at predetermined transforming ratios. The output currents are rectified by the full-wave rectifiers 31, 32 and 33, respectively. The rectified output currents of the full-wave rectifiers 31, 32 and 33 are fed to respective burden circuits 41, 42 and 43. The outputs of burden circuits 41, 42 and 43 are inputted to the phase selecting circuit 400 which selects, as largest value phase, a phase which consists of largest value from inputted phases. The selected largest value phase is inputted to the signal conversion circuit 900 and converted into mean or effective signal. The mean or effective output is fed to the A/D converter 100 which converts the analog signal into digital signal. This digital signal is fed to the microcomputer 110, which carries out level discrimination step with respect to the digital signal. Further, the microcomputer carries out first time-current operation and issues an output signal from the output port 116. The output signal is fed to the gate of thyristor 120 for driving the releasing device 80 which disconnects the disconnectable contacts 201, 202 and 203. On the other hand, outputs of the burden circuits 41, 42 and 43 are inputted to OR circuit 130 which consists of the diode 130, 131 and 132. The output of the OR circuit 130 is connected to the second time-current operating circuit 150 through the zener diodes 140 as second level-discrimination. Therefore, when the output of OR circuit 130 is over a zener voltage of the zener diode 140, the output of OR circuit 130 is fed to the second time current operating circuit 150. The second time-current operating circuit 150 carries out the predetermined second time-current operation for triggering the thyristor 120 for driving the releasing device 80. When full-wave signals obtained from the burden circuit 41, 42 or 43 shown in FIG. 1 are given to the input terminals 401, 402 and 403 of the phase selecting circuit 400 shown in FIG. 2 which has a predetermined operation characteristic, the input signals are applied to the input terminals of the analogue switches AS₁, AS₂ and AS₃, and the terminals of the registors R₁, R₂ and R₃, through the operational amplifiers OP₁, OP₂ and OP₃ which constitute unity gain amplifiers, respectively. The resistors R₁, R₂ and R₃ and the capacitors C₁, C₂ and C₃ constitute mean value circuits for obtaining the mean values of the input signals, and obtained mean value signals are entered into the positive input terminals of the operational amplifiers OP₄, OP₅ and OP₆, through the resistors R₁₉, R₂₀ and R₂₁, respectively. The operational amplifiers OP₄, OP₅ and OP₆ and the diodes D₁, D₂ and D₃ constitute a phase selecting circuit for selecting the phase wherefrom the largest mean value among the entered mean values is issued, and the largest mean value is generated on the common cathode of the diodes D₁, D₂ and D₃, and is then fed back to the negative input terminals of the operational amplifiers OP₄, OP₅ and OP₆ through the resistors R₁₆, R₁₇ and R₁₈, respectively. The operational amplifiers whereto the largest mean value of the input signal are not given operate as comparators and the output signals of them are not turned over and maintained the potential mean to that of the negative electric power source -Vcc because the input signals of them have lower potentials than the feedback potential. It is now assumed that the largest signal is entered into the input terminal 402 of the S phase in FIG. 2. The operational amplifier OP₅ operates as a normal phase amplifier and outputs the mean value as a threshold potential to the negative input terminals of the other operational amplifiers OP₄ and OP₆ corresponding to other R and T phases through the diode D₂. Since the input signals entered into the positive input terminals of the operational amplifiers OP₄ and OP₆ do not reach the threshold potential, the operational amplifiers OP₄ and OP₆ operate as comparators and their output signals are maintained in potentials near the negative potential of -Vcc, and the diodes D₁ and D₃ are maintained in negatively biased state. Accordingly, the diodes ZD₁ and ZD₃ are also negatively biased and they supply a sufficient base current for driving the transistors TR₁ and TR₃ of switching operation. Zener voltages of the zener diodes ZD₁, ZD₂ and ZD₃ are selected to be a little lower than the potential of the electric power source Vcc, and the emitter levels of the transistors TR₁, TR₂ and TR₃ are set to be lower than the ground potential GND. When the transistors TR₁ and Tr₃ conduct, signals having sufficiently high potential to cut off the analogue switches are applied on the gate terminals of the analogue switches AS₁ and AS₃, and therefore the analogue switches are turned to cut off state. On the other hand, since the output signal of the operational amplifier OP₅ to which the largest input signal is entered has a positive potential in proportion to the input signal, the zener diode ZD₂ is in cut off state, the base current is not given to the transistor TR₂, and a positive potential is applied to the gate of the analogue switch AS₂ through the resistor R₈. As a result, only the analogue switch AS₂ maintains the conductive state corresponding to the largest input signal and it issues the output signals on the output terminal 404. In this case, the emitters of the transistors TR₁, TR₂ and TR₃ are connected to the gates of the analogue switches AS₄, AS₅ and AS₆, respectively, and therefore a signal is applied to the gate of the analogue switch AS₅ of the S-phase corresponding to the largest input signal, the analogue switch AS₅ turns to the conductive state, and the potential of the negative input terminal is lowered by the resistor R₁₄. Namely the operational amplifier OP₅ serves as a positive phase amplifier and the output potential Vop of the operational amplifier OP₅ is given by the following equation: Hereupon, Vsin is the mean input potential of the S-phase. As a result, only the input signal of that phase corresponding to the largest input signal is raised in proportion to the shown in the above-mentioned equation (1), and the phase selecting circuit 400 has predetermined operation in appearance. Accordingly, by selecting the resistance values of the resistors R₁₄ and R₁₇, the predetermined potential of the threshold value for selecting the largest selecting phase can optionally be set. In respect of other phases, the circuits are constituted in the same way. The microcomputer 110 rises up, and then the computer program shown in flow chart of FIG. 4 starts. The system is initialized (i.e. setting of I/O port, and setting/resetting of flags are made,) at a step F2. Then, the microcomputer 110 controls the A/D converter 100 to convert the output signal of signal conversion circuit 90 into a digital signal (step F3). This digital data is stored in RAM 115. Next, it is determined whether this digital data indicate overcurrent or not (step 1001). When the digital data does not show an overcurrent, the operation jumps from the heat charging routine to the heat discharging routine and then returns to the A/D conversion (step F3). When the digital data shows an overcurrent, a heat charging flag H is set in the step F4, and bits for heat charging is added for every predetermined unit times by utilizing random access memory 115 or a register in the central processor unit 114, so as to count time responding to amount of input signal level. The heat charging bits are selected in order to realize time-current operation along the characteristic curves of FIG. 5. Then, the added bits number is examined whether the time is up for the selected time-current operation of the predetermined characteristic. And as a result, when the added bits number does not yet reach the predetermined number, in other words, when the time is up, an output is issued through the I/O port 116 to drive the thyristor 120, and thereby to actuate the indicator 180 and the output device 80. Nextly, operation of heat discharging routine, namely, the routine for resetting the time-current operation is described. The steps F5, 1003, F8 and F9 together form a heat discharging routine. It is discriminated whether the heat charging flag H has been set or not (step F5). When the heat charging flag H has been set, the heat charging flag H is decreased at the step 1003 for every predetermined unit times. When the counted number of the bits becomes 0 as a result of the subtractions in the step F9, the heat discharging routine goes back from the step F9 to the A/D conversion step F3. When the counted number of the bits is not entirely reset, the heat charging flag H is not reset and the heat discharging routine goes back from the step F8 to the A/D conversion step F3. As above-mentioned, the microcomputer gives most appropriate time-current operating characteristic, taking account of heat charging and heat discharging in the electric power lines and loads. Incidentally, addition or subtraction of the heat charging and heat discharging can be executed in the inverse order to the above-mentioned embodiment. A further preferred embodiment of an overcurrent detector in accordance with the present invention is shown in FIG. 6. Generally an overcurrent detector serves as a sensor of the afore-mentioned circuit breaker or the like, so most parts of their constitutions are identical. Circuit of FIG. 6 is the same as FIG. 1, except the line switches 201, 202 and 203 and the releasing device 80. In FIG. 6, an output device 80' having an output terminal 81 replaces with the releasing device 80.

Claims: An overcurrent detector, comprising: current sensor means (21-23, 31-33, 41-43) for detecting the values of the currents in the respective phases (R, S, T) of an AC power line (10); phase selection means (400; Fig.2) for selecting the largest value of the detected current values by comparing the respective mean values of said detected current values with a selecting threshold value, which threshold value is obtained by multiplying the mean value of the currently selected current value by a coefficient greater than 1; signal conversion means (900) for obtaining a mean or an effective value of the current value selected by said phase selection means (400; Fig.2); processing means (100, 110) for processing the output signal of said signal conversion means (900) and for issuing a releasing signal; and means (R13-R18; Fig.2) for optionally setting the value of said coefficient. An overcurrent detector according to claim 1, characterized in that said processing means includes a microprocessor (110). A circuit breaker, characterized by an overcurrent detector according to claim 1 or 2, wherein at least one disconnectable contact (201) provided in said AC power line (10) is controlled by said releasing signal.

Inventors: ARINOBU, ICHIROU, HATAKEYAMA, YOSHIHIRO
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1987
Main classification: H02H3
IPC codes: H02H3