SWITCHING CIRCUIT WITH HYSTERESIS

Abstract: A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely indepen­ dent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the trans­ conductance of the circuit as it is switching.

Description: The invention relates to semiconductor switching circuits that exhibit hysteresis in which a circuit transition from one state to another occurs as an input voltage rises above one threshold and a circuit transition back to the first state occurs as the input voltage drops below another threshold less than the first. Switching circuits typically employ hysteresis to provide noise immunity or a safety margin. US-A-3 725 673 discloses a hysteresis circuit. Fig. 1 illustrates the basic features of this bipolar circuit. It switches between a pair of states with a hysteresis created by suitably switching a current I H . The circuit of Fig. 1 employs differential portions 11 and 12. Portion 11 amplifies an input voltage V I , which is here the amount by which a signal voltage V IN exceeds a reference voltage V REF , to produce circuit currents and whose difference is representative of V I . The internal configuration (notshown) of portion 11 centers around a pair of Darlington circuits. Each Darlington contains an input PNP transistor whose emitter drives the base of a trailing PNP transistor. The bases of the input transistors differentially receive voltage V I . Currents and are respectively supplied from the collectors of the trailing transistors whose emitters are connected to a current source to receive a supply current. Portion 12, which is configured the same as portion 11, amplifies a control voltage V C to produce circuit currents and whose difference is representative of V C . Currents and are supplied to the inputs of a differential-to-single-ended converter 13. Another such converter 14 generates current I H by subtracting from A switch 15 provides current I H to ground or to one of the inputs of converter 13. A voltage V X is supplied from converter 13 at a value that varies largely in proportion to where m is 1, 0, or -1 depending on the switching of current I H . An amplifier 16 amplifies voltage V X to generate an output voltage V O which controls the position of switch 15. Circuit transitions occur when equals MI H . During a transition, V I passes through a hysteresis threshold approximately equal to mK G V C , where K G is the ratio of the transconductance of portion 12 to that of portion 11. Only two of the three values of m are normally used in any particular embodiment of the circuit. This gives three different cases: (1) m = 0, 1; (2) m = -1, 0; and (3) m = -1, 1. Figs. 2a, 2b, and 2c respectively show the hysteresis characteristics for the three cases. The vertical axes, for example, represent V O . The low and high values of m for each case respectively fix its low and high hysteresis thresholds. Their difference is the magnitude of the hysteresis. In particular, assume that switch 15 is positioned at the high m value to set the circuit at the high threshold. Starting with V I low, the circuit changes state as V I rises above the high threshold. The new V O value causes switch 15 to switch to the lower m value. This sets the circuit at the low threshold. When V I later drops, nothing happens until it passes the low threshold. At that point, the circuit goes back to its original state. Switch 15 thereby returns to the high m value to reset the circuit at the high threshold. The circuit of US-A-3 725 673 has several desirable features. The amount of hysteresis can be controlled by simply adjusting K G or V C . Since K G is a ratio, it is largely independent of temperature and fabrication conditions. V C can be made largely temperature and process independent. Consequently, the hysteresis thresholds are stable with temperature and processing parameters. The flexibility is, however, somewhat limited because the thresholds are not independently controllable. One of them is either fixed at zero (Figs. 2a and 2b) or is the negative of the other (Fig. 2c). It would be desirable to overcome this flexibility limitation without sacrificing the preceding advantages. In accordance with the invention, a circuit switches between a pair of states with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication parameters. The hysteresis is introduced into the circuit by using positive feedback to change the transconductance of a part of the circuit as it switches. The present circuit contains first and second differential portions. The first portion amplifies an input voltage to produce a pair of circuit currents whose difference is representative of the input voltage. The second portion amplifies a control voltage to produce another pair of circuit currents whose difference is representative of the control voltage. The four currents are operated on to cause the circuit to make state transitions as a function of the input voltage with a hysteresis whose magnitude depends on the control voltage. This is done with an arithmetic component and feedback circuitry. The arithmetic component produces a component signal at a value that varies largely in proportion to a linear combination of (1) the difference between the circuit currents of the first portion and (2) the difference between the circuit currents of the second portion. Generation of the component signal in this way establishes a switching region. The circuit makes transitions between its states largely in synchronism with transitions of the component signal. The feedback circuitry then creates the hysteresis by adjusting the transconductance of the second differential portion in response to the circuit transistions. More particularly, the hysteresis consists of (1) a transition of a first type in which the circuit switches from one of its states to the other as the input voltage rises above a high threshold and (2) a transition of a second type opposite to the first as the input voltage drops below a low threshold less than the high threshold. The feedback circuitry decreases the transconductance of the second portion in response to a transition of the first type and vice versa. The primary element in the feedback circuitry is a switch that selectively decouples a part of a current source in the second portion from a pair of like-configured three-electrode amplifiers that are arranged in a differential configuration to receive the control voltage in the second portion. The switch opens as the circuit makes a transition of the first type and vice versa. Fig. 1 is a block diagram of a prior art hysteresis switching circuit. Figs. 2a - 2c are graphs for the hysteresis characteristics of thecircuit of Fig. 1. Fig. 3 is a block/circuit diagram of a circuit that switches with a hysteresis according to the invention. Figs. 4a and 4b are graphs for the hysteresis characteristics of the circuit of Fig. 3. Fig. 5 is a circuit diagram of a preferred embodiment of the circuit of Fig. 3. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. Referring to Fig. 3, it illustrates a circuit that makes transitions between a pair of states with a hysteresis created by changing the transconductance of a part of the circuit during each transition. The condition of the circuit is represented by output voltage V O which switches between a pair of voltage levels as a function of input voltage V I . The circuit makes a transition from one of its states to the other as V O switches from one of its levels to the other, and vice versa. This circuit uses various three-electrode amplifiers. Each has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for controlling current flow between the flow electrodes (E1 and E2). Charge carriers (electrons or holes) moving between the flow electrodes generally originate at the first electrode and terminate at the second electrode. Each three-electrode amplifier may be embodied with a single transistor. In the case of a field-effect transistor (FET) of either the insulated-gate or junction type, its source, drain, and gate are respectively the first, second, and control electrodes. These are the emitter, collector, and base for a bipolar transistor. A three-electrode amplifier could, however, consist of more than a single transistor. One example is a bipolar Darlington circuit in which the emitter of an input transistor is connected to the base of a trailing transistor (to give a total current gain approximately equal to the product of the individual transistor current gains). In this instance, the control electrode is the base of the input transistor, while the first and second electrodes are the emitter and collector of the trailing transistor. As used in describing a pair of three- electrode amplifiers, "like-configured" means that they have corresponding elements interconnected in the same way and that each set of corresponding elements is of the same semiconductor polarity. For example, a pair of three-electrode amplifiers would generally be "like-configured" if both are N-channel FET's but not if they are complementary FET's. Likewise, a pair of Darlingtons are "like-configured" as long as the input transistors are the same polarity and the trailing transistor are the same polarity (even if different from that of the input transistors). In specifying that the difference between a pair of currents is "representative" of a voltage, "representative" means that the magnitude of the difference between the currents has a one-to-one relationship with the magnitude of the voltage as long as the voltage magnitude is not too large. When the voltage magnitude becomes very large, "representative" means that the difference between the currents is largely one value if the voltage is high and another value if the voltage is low. Returning to Fig. 3, voltage V I is supplied to the non-inerting (+) and inverting (-) inputs of a differential portion 21 which differentially amplifies input V I to produce circuit currents and whose difference is representative of V I. Portion 21 contains like-configured three-electrode amplifiers A1 A and A1 B whose control electrodes differentially receive voltage V I . A current source S1 provides a fixed supply current I S1 to the interconnected first electrodes of amplifiers A1 A and A1 B . Their second electrodes respectively supply currents and to the respective inverting (-) and non-inverting (+) outputs of portion 21. Control voltage V C is supplied to the non-inverting and inverting inputs of a differential portion 22 which differentially amplifies voltage V C to produce circuit currents and whose difference is representative of V C . Portion 22 contains like-configured three-electrode amplifiers A2 A and A2 B whose control electrodes differentially receive voltage V C . A current source S2 provides supply current to the interconnected first electrodes of amplifiers A2 A and A2 B . Their second electrodes respectively supply currents and I 2B to the inverting and non-inverting outputs of portion 22. Current source S2 consists of main and switchable portions S2 C and S2 D that provide respective supply currents I S2C and I S2D . Main portion S2 C is permanently connected to the first electrodes of amplifiers A2 A and A2 B . A two-position switch 23 responsive to output V O is located between switchable portion S2 D and the first electrodes of amplifiers A2 A and A2 B . A V O transition in one particular direction causes switch 23 to "close". This establishes a conductive path from portion S2 D to the first electrodes of amplifiers A2 A and A2 B . They now receive additional current I S2D . A V O transition in the opposite direction causes switch 23 to "open". The conductive path between portion S2 D and amplifiers A2 A and A2 B is thereby broken. Current I S2D is diverted to a reference point G such as ground. Alternatively, current source S2 D simply shuts off if point G is an open-circuit position. In response to currents and an arithmetic component 24 generates a component signal V Y at a voltage that varies substantially in proportion to An amplifier 25 of a conventio nal type amplifies voltage V Y to generate voltage V O which is fed back to control switch 23. The polarities of V Y and V O may be the same or opposite depending on the internal characteristics of switch 23. Hysteresis occurs in the circuit as a result of changing the transconductance of portion 22 during each circuit transition. In particular, the transconductance of a differential amplifier such as portion 21 or 22 is the incremental change of its differential output current divided by the incremental change of its differential input voltage. The transconductance is normally largely constant for a significant range centered around zero input voltage and drops gradually to zero as the input voltage moves out of this range. The magnitude of the transconductance at any particular value of the input voltage depends on the amount of amplifier supply current available. The transconductances G M1 and G M2 of respective portions 21 and 22 therefore are and For portion 22, equals where G M2C is the transconductance due to main portion S2 C of current source S2, G M2D is the further transconductance due to using switchable portion S2 D with main portion S2 C , and n is 0 or 1 depending respectively on whether switch 23 is open or closed. During a V O transistion, the difference equals the difference Suitably applying the preceding relationships leads to the following approximate relationship for the threshold values V TH of V I at the transition points: V TH ≈ V C G M2 /G M1 = V C (G M2C + nG M2D )/G M1 (1) Figs. 4a and 4b show the hysteresis characteristics for the case in which V C is greater than zero. The top and bottom of the V O waveform are limited by the upper and lower stage limits of amplifier 25. The gain of amplifier 25 thereby concerts the relatively gradual V Y transitions into sharp V O transitions. If V I is initially low, n is one (switch 23 is closed) so that G M2 equals G M2C + G M2D . V I must rise to a high threshold level T THH approximately equal to V C (G M2C + G M2D )/G M1 to enable V O to make a transition. At that point, n goes to zero (switch 23 opens). G M2 drops to G M2C . V I must now drop to a low threshold voltage V THL approximately equal to V C G M2C /G M1 before V O can make a reverse transition. When this occurs, n goes back to one (switch 23 closes), G M2 returns to G M2C + G M2D . Hysteresis thresholds V THL and V THH are both positive if V C is positive, and vice versa. For a given value of V C , the distance between V THL and V THH can be varied by adjusting G M2D . As a result, the hysteresis thresholds are separately controllable. The components of portion 21 preferably utilize the same type of transistors as the components of portion 22. The circuit is fabricated as a monolithic integrated circuit (according to conventional planar processing techniques). G M2 therefore has approximately the same dependence on temperature and processing parameters as G M1 so that the ratio G M2 /G M1 is largely independent of temperature and fabrication conditions. Voltage V C is preferably generated in such a manner as to be stable with respect to temperature and processing parameters. The result is that temperature and fabrication processes have little effect on V THL and V THH . The same basic hysteresis characteristics arise if component 24 utilizes the opposite of the difference V Y varies in proportion to The only change is a reversal of sign in V THL and V THH . If desired, this can be compensated for by changing the sign of V C . Like comments apply to utilizing the opposite of the difference Before generating V Y , component 24 can (1) multiply the difference between by a non-dimensional factor F₁ and (2) multiply difference between by another non-dimensional factor F₂; in a known way using conventional current mirrors. In this case, V Y varies largely in proportion to the linear combination is modified to : V TH ≈ (F₂/F₁)V C G M2 /G M1 (2) For the reasons given above, each factor F₁ or F₂ may be positive or negative. Suitable design choice enables F₁ and F₂ to have largely the same dependence on temperature and process. The resulting hysteresis is again stable with temperature and process. Furthermore, hysteresis occurs if V Y varies in proportion to a general linear combination of However, such a general combination normally does not result in temperature and process stability. Fig. 5 depicts a complementary-FET embodiment of the circuit of Fig. 3. All the FET's shown in Fig. 5 are enhancement-made insulated-gate FET's. P-channel FET's are indicated by arrows pointing away from their channels. The reverse applies to N-channel FET's. Amplifiers and of Fig. 3 consist respectively of identical input FET's Q1 A , Q1 B , Q2 A , and Q2 B in portions 21 and 22 of Fig. 5, Each current source S1, S2 C , or S2 D is a corresponding FET Q3, Q4 C , or Q4 D whose gate receives a reference voltage V S . The sources of FET's Q3, Q4 C , and Q4 D are tied to a source of a high supply voltage V HH . Switch 23 consists of a pair of identicai FET's Q5 and Q6 arranged in a differential configuration FET Q5 is connected as a diode between the Q4 D drain and the sources of FET's Q2 A and Q2 B . FET Q6 is connected between the Q4 D drain and a source of a low supply voltage V LL corresponding to point G of Fig. 3. Arithmetic component 24 consists of identical FET's Q7 and Q8 arranged as a conventional current mirror with their gates connected together and to the Q7 drain. and are summed at the Q7 drain at the subtracting input of component 24. and are summed at the Q8 drain at the adding input of component 24 where YV Y is produced. Component 24 operates on the summed currents flowing through Q7 and Q8 in such a way as to force to vary largely in proportion to Generation of voltage V Y at the requisite value occurs as a result of the internal resistances of FET's Q8 and Q2 A . Amplifier 25 consists of complementary FET's Q9 and Q1O arranged as an inverter. V Y is provided to the gate of FET Q9 whose drain supplies V O to the Q6 gate at a value inverse to the V Y value. FET Q10 acts as a load for FET Q9. As V Y makes a low-to-high transition, V O goes low. This causes FET Q6 to turn on hard and pulls the voltage at the interconnected sources of FET's Q5 and Q6 down so as to turn off FET Q5. Switch 23 opens. I S2D is diverted to the V LL supply to reduce G M2 . The reverse occurs when V Y later goes low. The resulting high V O value turns FET Q6 off, allowing FET Q5 to turn on and raise G M2 . Voltage V C in Fig. 5 is provided across the middle resistor of a voltage divider 26 consisting of resistors R1, R2, and R3 connected in series between the V LL and V HH supplies. V C thereby equals (V HH - V LL ) times a resistance ratio. The variation of resistors R1 - R3 with temperature and processing parameters is largely cancelled out in the resistance ratio. As a result, V C is largely independent of temperature and process as long as the power supply voltage V HH - V LL is substantially constant. Ignoring the dependence on input voltage, the transconductance for a differential amplifier such as portion 21 or 22 in Fig. 5 is approximately equal to a constant times the square root of the product of the supply current and the width-to-length ratio (W/L) of the input FET's. Letting (W/L)₁ be the W/L for FET's Q1 A and Q1 B and letting (W/L)₂ be the W/L for FET's Q2 A and Q2 B , application of Eq. (1) gives : V THL ≈ V C (I S2C /IS₁)(W/L)₂/(W/L)₁ (3) V THH ≈ V C (I S2C + I S2D )/IS₁)(W/L)₂(W/L)₁ (4) I S1 , I S2C , I S2D , (W/L)₁, and (W/L)₂ vary with process and temperature. These dependencies are cancelled out in the current and width-to-length ratios of eqs. (3) and (4) to make V THL and V THH largely independent of temperature and process. V HH and V LL preferably are 5 and 0 volts, respectively, in the embodiment of Fig. 5. V S is 0.5 - 1.0 volt below V HH . Resistor R2 is 1 kiloohm, while resistors R1 and R3 are each 5 kiloohms. (W/L)1 and (W/L)2 are 40. The Q3 W/L is 20. FET's Q4 C and Q4 D each have a W/L of 7.5. The W/L for FET's Q5 and Q6 is 125. While the invention has been described with respect to a preferred embodiment, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, the control voltage could be variable if it were desirable to dynamically control the hysteresis. If depletion-mode FET's were used to embody the differential portion that receives the control voltage, it could be supplied from a voltage divider consisting of only two resistors. Slew-rate improvement techniques such as those described in US-A-3 668 53 might be used to regulate the supply current in each differential portion independent of the hysteresis.

Claims: A circuit comprising: a first differential means for amplifying a differential input voltage to produce a first pair of currents whose difference is representative of the said input voltage; a second differential means for amplifying a differential control voltage to produce a second pair of currents whose difference is representative of the said control voltage; arithmetic component means responsive to the said pairs of currents for producing an output voltage, the output of the said arithmetic means being coupled to feedback means, for applying a feedback signal to the said second differential means, such that the said output voltage makes transitions between a pair of states as a function of the said input voltage, with hysteresis whose magnitude depends upon the said differential control voltage characterised in that the said arithmetic component means produces a voltage signal that varies substantially in proportion to a linear combination of (i) the difference between the said first pair of currents (ii) the difference between the said second pair of currents, and that the said feedback signal effects a change in the transconductance of the said second differential means. A circuit as claimed in Claim 1 wherein the hysteresis comprises (i) a transition of a first type in which the circuit switches from one of its states to the other as the input voltages rises above a high threshold and (ii) a transition of a second type opposite to the first type as the input voltage drops below a low threshold less than the high threshold, characterized in that the feedback means (ii) decreases the transconductance of the second differential means as the circuit makes a transition of the first type and (ii) increases the transconductance of the second means as the circuit makes a transition of the second type. A circuit as in Claim 2 wherein: each differential means comprises a current source and a pair of like-configured amplifiers; each amplifier has a first flow electrode, a second flow electrode, and a control electrode for controlling current flow between the flow electrodes; the input voltage is differentially supplied to the control electrodes of the amplifiers of the first differential means; the control voltage is differentially supplied to the control electrodes of the amplifiers of the second differential means; the current source of each differential means is coupled to the first flow electrodes of its respective amplifiers to provide a supply current for them; and the second flow electrodes of the amplifiers of each differential means provide its respective pair of circuit currents; characterized in that the feedback means comprises a switch for selectively decoupling a part of the current source of the second differential means from the first flow electrodes of its amplifiers. A circuit as in Claim 3, characterized in that the current source of the second differential means comprises a main portion and a switchable portion, the switch being located between the switchable portion and the first flow electrodes of the amplifiers of the second differential means. A circuit as in Claim 4, characterized in that the switch (1) opens as the circuit makes a transition of the first type and (2) closes as the circuit makes a transition of the second type. A circuit as in Claim 4, characterized in that the position of the switch is controlled by an output signal representative of the state of the circuit. A circuit as in Claim 6, characterized in that the arithmetic component means includes an amplifier for amplifying the arithmetic component signal to produce the output signal. A circuit as in Claim 5 wherein charge carriers that move between the flow electrodes of each amplifier originate at its first flow electrode and terminate at its second flow electrode, characterized in that the amplifiers in each differential means are substantially identical field-effect transistors. A circuit as in Claim 5, characterized in that each amplifier is a field-effect transistor having a source, a drain, and a gate which are respectively the first flow, second flow and control electrodes of that amplifier. A circuit as in Claim 5, characterized by a voltage divider for providing the control voltage. A circuit as in Claim 10, characterized in that the voltage divider comprises at least three resistive elements coupled in series, the differential control voltage being provided across the middle element. A circuit as in Claim 2, characterized in that the linear combination is the difference between (1) the product of a first non-dimensional factor and the difference between the circuit currents of the first differential means and (2) the product of a second non-dimensional factor and the difference between the circuit currents of the second differential means. A circuit as in Claim 12, characterized in that each non-dimensional factor is substantially one.

Inventors: BLAUSCHILD, ROBERT ALAN, TOY, EDMOND
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: H03K3
IPC codes: H03K3