INTEGRATED CIRCUIT CHIP HAVING A PLURALITY OF INTEGRATED CIRCUIT CELLS

Abstract: An integrated circuit has integrated circuit cells (14, 16) drawn from a library. The cells are rectangular with input lines (10, 11) extending from both sides of the cell to a logic element (18) on the cell and outputs (20, 21) taken from the logic element to both sides of the cell. Input and output lines terminate at connection points. Join cells (22, 23) selectively interconnect the connection points across the boundary between adjacent cells. The arrangement permits on-cell series and parallel connection of cells.

Description: This invention relates to integrated circuit devices and particularly to such devices which are fabricated using integrated circuit cells drawn from a library of such cells. Since it is impossible for designers to draw out circuit elements at the microscopic scale currently characterizing VLSI circuits, the circuits are first mapped-out on paper at many times the circuit final size. The first map produced shows a collection of electronic logic blocks (e.g. gates, inverters). This is then translated into a diagram of the electrical elements (e.g. transistors, resistors) that will perform the required functions when fabricated in silicon or another semiconductor. Contained within this drawing is all the data required to generate photomasks used in the production of the chip. A series of photographic reductions are employed to reduce the photomask drawings to the requisite final size. To cope with ever increasing complexities of integrated circuit design, it has been proposed to use automated cellular or modular lay-out systems. In such a system a family of standard "cells" each one representing an electrical logic function such as a logic NAND gate is represented by a functional diagram and is also stored as a thoroughly tested computer model which realistically simulates the behaviour of the cell. In the design of a logic circuit, the standard cells are used as building blocks, and are combined to generate the required function. These logic cells are translated by computer program into corresponding proven circuit lay-outs which are displayed on a terminal. An integrated circuit designer can then manipulate the standard cells which may not be in the exact form that they will be implemented in the silicon but are in a form showing the physical shape, arrangement of connections and other details necessary for the actual lay-out on a chip. Each of the standard cells such as NAND and NOR gates, counters and signal inverters have to conform to stored rules governing parameters such as size, and the location of inputs and outputs. Also the cells must be electrically and logically compatible with one another. With a cellular design method, the interior details of the standard cells are already designed and proven, thus eliminating a considerable amount of design work in generating a new chip design. In the simplest approach to generating an integrated circuit using cells, a row and track approach is used. This approach employs rectangular cells of a uniform height which are placed side-by-side in the chip lay-out to form a row. An integrated circuit consists of several of these rows with interconnections or tracks, routed in the space between the rows. To simplify the interconnection pattern, a grid system is used, the height of all the cells being a common number of grid intervals and their widths being restricted to an integral number of grid intervals. Interconnection points on each cell appear at locations that are an integral number of grids from an assigned cell origin position. Interconnections between the cells extend along the grid lines, horizontal interconnection links being made below the bottom edge of a row of cells. The interconnection pattern may take up several rows of the grid and may occupy several levels of polysilicon or metal in the chip. In arranging the cells for maximum packing density and minimum interconnect, it is known to reverse the cells (top-to-bottom or side-to-side), this function being easily achieved using computer-aided design. In addition to the use of dedicated interconnect regions for example along the bottom of a row of integrated circuit cells, it is known to provide a connection between the sides of adjacent cells. Thus, in addition to input and output lines terminating at the top and bottom edges of such a cell, such cells will also have an input and an output line terminating just short of respective cell sides. The cells are designed such that when the two adjacent cells are placed in a row, the output line end (or connection point) of one cell has a predetermined location relative to the connection point of the input line of the next adjacent cell. Consequently, at the design stage, a routine can be initiated in the computer-aided design process which applies a predetermined interconnect line to join the two ends and so connect the side-sited output of the first cell to the side-sited input of the next cell across a notional boundary between the cells. Clearly dedicated interconnect space between the cell rows is obviated. Henceforth, these side-sited connections across a boundary shall be called "join cells". Frequently both parallel and series connections of two particular cells will be required to perform the circuit logic function. For parallel connection, where the cells meet there will either be a common input to or common output from the two cell logic elements. The other common connection can be implemented only by a dedicated interconnect along the top or bottom of the cell row, outside the cell boundaries. The inputs and outputs of standard cells are interconnected by forming conducting lines in metal and/or polysilicon layers formed on the chip to join a connection point of one cell with a connection point of another cell. Access to inputs and outputs in both metal and polysilicon layers is advantageous where interconnection paths must cross because the conductor paths in one direction can be run in one conducting layer, while the perpendicular paths are run in another conducting layer. The prior design scheme in which there is essentially a dedicated input side and dedicated output side in each cell and in which signals propagate essentially unidirectionally through the cell is expensive on interconnect area outside the cells. At the expense of some conductor area within the confines of each cell, many of these off-cell interconnects can be eliminated. A routing technique suitable for a masterslice LSI Layout, including the channel order and net-transfer method and leading to a device according to the preamble of claim 1, is disclosed by H. Kanada et al. in Journal of Digital Systems, Volume IV, No. 4, pp. 427-441 (1980). The technique processes the routing of channels one by one so that the router requires a small memory space on a host computer. The channel order is developed as the subsystem of computer-aided layout system applied to the layout system applied to the layout design of a DSA MOS masterslice with a double-level metalizations with 624 gate cells. From Patent Abstracts of Japan, Vol. 6, No. 77 (E-106)[955], 14th May 1982 a semiconductor device is known showing an arrangement of output terminals diagonally opposite to each other at opposite sides of a rectangular shaped circuit cell. The logical operation circuit has, for example 3 inputs and 2 outputs and a block pattern may be arranged with several connecting points provided at each input/output terminal. According to the invention, there is provided an integrated circuit device having a plurality of rectangular integrated circuit cells arranged in at least one row, each cell containing a logic element, characterized in that: each cell has at least two input terminals each of which is connected to an input of the logic element, and at least two output terminals each of which is connected to an output of the logic element, a respective one of the input terminals and a respective one of the output terminals being located at each of two opposite sides of each cell with the input terminal at one of said opposite sides being diagonally opposite the input terminal at the other of said opposite sides and the output terminal at said one of said opposite sides being diagonally opposite the output terminal at said other of the opposite sides; the terminals of the cells of each row are arranged along two parallel axes which extend parallel to that row; the cells are arranged side by side with at least one of said opposite sides being located next to one of said opposite sides of an adjacent cell to bring the terminals of each cell into adjacency with terminals of at least one adjacent cell; and at least one join cell is provided comprising a length of conductor to connect at least one pair of adjacent terminals of at least one pair of adjacent cells. Input and output conductors associated with each logic element can be such as to produce vertically coincident terminals whereby interconnection between adjacent cells can be implemented in one of a plurality of separate conductor levels, the conductor levels being insulated one from another. The cells and the terminals of the input and output conductors are preferably located on a Cartesian grid system, the cell areas being rectangular in shape. Each cell can occupy a preset number of grid spacings in height and an integer number of grid spacings in width depending on the size of a logic element contained therein. Some of the cells within the integrated circuit can be mirror images or inversions of other cells. The join cells preferably comprise a short length of conductor. By routing input and output lines to both sides of each cell, two cells can be located side-by-side to provide a series connection between them or one of the two cells can be inverted and the connection scheme altered to provide a parallel connection between the cells. Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:- Figure 1 is a schematic representation of part of an integrated circuit chip having a pair of series connected logic cells; Figure 2 is a schematic representation similar to Figure 1 but showing two such cells connected in parallel; Figure 3 shows a circuit schematic drawing of a cell; Figure 4 shows a circuit schematic drawing of a NOR gate embodying the invention; Figure 5 shows a circuit schematic drawing of an inverter embodying the invention; Figure 6 shows a circuit schematic view of an SR flip-flop embodying the invention; Figure 7 marked PRIOR ART shows an SR flip-flop implemented using known integrated circuit cell technology; Figures 8 and 9 respectively show circuit schematic views of series and parallel connected inverter cells embodying the invention; Figure 10 marked PRIOR ART shows a parallel connected inverter using known integrated circuit cell technology; Figure 11 shows superimposed photomask outlines used in the production of the Figure 5 cell; and Figure 12 is a circuit diagram of a standard CMOS inverter. Referring to Figure 1 in detail, the schematic view shows an arrangement of logic cells 14, 16 on part of an integrated circuit chip embodying the invention. The first logic cell 14 has a height "h" and length "l₁" and contains a logic element 18. A first input line 11 extends from a terminal A to the logic element 18 and a second input line 10 extends to the logic element from a terminal B. Terminals A and B are diagonally opposite at the sides of the cell rectangle. Corresponding output lines 21 and 20 extend from the logic element to terminals C and D where C and D are on the cell boundary and at diagonally opposite points. The terminals B and D are both a distance "s" from the top side or origin of the cell and the terminals A and D have a spacing "d" identical to the spacing of terminals B and C. Integrated circuit cell 16 has a height identical to the logic cell 14 and a length "l₂" somewhat less than "l₁" owing to a logic element 25 having an area smaller than logic element 18. The internal connection scheme of cell 16 is essentially that of cell 14 translated to the right. Thus inputs 11 and 10 extend from points C and E respectively to the logic element 25 and outputs 20 and 21 appear respectively at points B and F. It can be seen that the output 21 of the logic cell 14 and input 11 of the logic cell 16 terminate and originate respectively at point C while input 10 of logic cell 14 and output 20 of logic cell 16 terminate at point B. In fact, the input and output lines all terminate short of the boundary between the cells. In the embodiment shown no connection exists between the lines terminating near C but the lines terminating at B are joined by a short interconnect line or join cell 22. The junction interconnect 22 completes a current path through the two logic cells 14 and 16 from the point E through the logic element 25, across junction point B, through the logic element 18 to the point D. It will be realized that in an alternative series connection using the identical logic cells 18 and 25, the junction interconnect is placed at the point C so that a series path extends through the two logic elements 18, 25 from point A through point C to point F. Referring now to Figure 2, an alternative arrangement of the two cells is shown. Here, the logic element 25 is inverted (left-to-right) compared to logic element 18. With join cells applied at 22 and 23, inputs to the combined logic elements 18, 25 can originate from an upper interconnect level (not shown) at B₁ and an output is available in the upper interconnect level at C₁, the elements thus being effectively connected in parallel with additional outputs being available at both D₁ and E₁. Referring to Figure 3, the schematic diagram shows one arrangement of the routes of input and output lines to and from a logic element. Referring to Figures 4 and 5, a two-input NOR gate and an inverter are shown. It will be understood that the logic element and interconnect shown correspond, in a silicon wafer, to an array of transistors and to a pattern of conductor areas. However connection points 31 of the conductor lines shown in the Figure correspond essentially to connection points on the center line of conductors implemented in wafer form and are properly positioned relative to the outer perimeter 32 of the cells. Referring to Figure 6, a pair of the two-input NOR gates are shown in an SR flip-flop arrangement. Also shown for comparison in Figure 7 is an SR flip-flop implemented using known integrated circuit cells. In the Figure 6 version, a lower interconnection 34 between cells corresponds to the single on-cell interconnection 35 of Figure 7. A second interconnection 36 and conducting leads 37 extending to and from it are used to implement a reverse current path to take the output from a second NOR gate 39 back to the input of a first NOR gate 40 without the use of off-cell interconnect 43 as shown in figure 7. In Figures 8 and 9 there are shown series and parallel connected inverters while Figure 10 shows a parallel connected inverter arrangement implemented in known integrated circuit cell technology. In Figure 8, additional conducting lines 41 for permitting a reverse current path across each of the cells are redundant. However in the case of the parallel inverters, by forming a second connection 42, a reverse path is implemented and the need for off-cell interconnect 43 shown in Figure 10 is obviated. In the examples shown, each of the cells is primitive in the sense that the logic element cannot really be split into subsidiary logic functions. However a combination cell produced by putting two of the primitive cells together does itself resemble a primitive cell in the sense that inputs and outputs having identical positional relationship are available at both sides of the combination cell. In the example shown, a join between adjacent cells is shown as a symbol . In fact, the circuit design software is programmed to position a length of conductor. This is preferably short and straight but can be somewhat longer and non-linear if appropriate in view of other design rules for use of the cell library. In translating the logic diagram shown in the Figures to a series of masks and in translating the masks to an integrated circuit wafer, the existence of discrete cells is lost in the sense that no boundary between primitive cells or combination cells will be apparent and no discrete join cell is apparent although at certain locations a span of metal will traverse the boundary between cells. However in the particular embodiment described, the cell nature of the chip will be apparent on analysis since in a row of logic elements, the elements each have two input and two output lines, one each of the input and output lines leading directly to respective adjacent sides of the cell and the other input and output lines looping towards opposite sides of the cell. Referring to Figure 11 there is shown to an enlarged scale a mask diagram for the CMOS inverter shown schematically in Figure 5 and in circuit schematic form in Figure 12. The outer boundary of the cell is shown at 50. The inverter has a top aluminum region 52 to which V DD is applied in operation and a lower aluminum region 54 to which V SS is applied. Further aluminum regions are located at 56 and 58. One polysilicon area 60 extends between a p-channel transistor 62 and an n-channel transistor arrangement 64 and a smaller polysilicon region exists at 66. It can be seen that at all elements or points 68 both aluminum and polysilicon extend close to the sides of the cell, the polysilicon being at a different wafer level from the aluminum. On the right-hand side, (i) the polysilicon region 60 and aluminum region 58 and (ii) the polysilicon region 66 and aluminum region 56, are electrically joined by vertical contacts 70 and 72 respectively. The contact 70 represents an input port and the contact 72 an output port. The polysilicon area 60 and the aluminum area 56 both extend through to the left hand side of the cell at their respective levels. Connections can be made at either of the two levels and at any of the points 68 in order to achieve the desired interconnection with a neighbouring cell to the left or right of the inverter cell illustrated. Join cell locations are shown schematically as elements 68 which, as previously indicated, may be at the polysilicon or aluminum metal level. The arrangement permits implementation of either of the connection schemes shown in Figures 1 and 2. Also shown in Figure 11 are vias 76, 78 which provide connection between a second aluminum level (not shown) and the first aluminum level. The second level aluminum can be used to provide inputs to and outputs from a row of cells at selected positions along the row. The second level metal can also be used for general routing in the wafer if cell connections are not made at via locations 76 or 78. Essentially, the more join cells that are utilized in a cell row, the more optional input or output terminal sites become available at via locations 76, 78 for routing second level metal interconnect lines. In all embodiments, the cells are rectangular. In the embodiment specifically described, the two output terminals of a cell can be viewed as located at the ends of one cell diagonal with the two input terminals located at the ends of the other diagonal. Together with a computer-aided design routine permitting the cell plan to be reversed (left to right), this enables the parallel and series connection of cells described previously. An arrangement of the two input terminals on opposed sides at a common height and the two output terminals at opposed sides at a different common height would cause a difficulty in making connection to ground and supply voltage lines at top and bottom of a cell row.

Claims: An integrated circuit device having a plurality of rectangular integrated circuit cells (14,16) arranged in at least one row, each cell containing a logic element (18,25), characterized in that: each cell has at least two input terminals each of which is connected to an input of the logic element, and at least two output terminals each of which is connected to an output of the logic element, a respective one of the input terminals and a respective one of the output terminals being located at each of two opposite sides of each cell with the input terminal at one of said opposite sides being diagonally opposite the input terminal at the other of said opposite sides and the output terminal at said one of said opposite sides being diagonally opposite the output terminal at said other of the opposite sides; the terminals of the cells of each row are arranged along two parallel axes which extend parallel to that row; the cells are arranged side by side with at least one of said opposite sides being located next to one of said opposite sides of an adjacent cell to bring the terminals of each cell into adjacency with terminals of at least one adjacent cell; and at least one join cell (22,23) is provided comprising a length of conductor to connect at least one pair of adjacent terminals of at least one pair of adjacent cells. An integrated circuit device as defined in claim 1 having cells of two types, cells of the first of said types having input terminals at a first pair of locations at said opposite sides of said cells and output terminals at a second pair of locations at said opposite sides of said cells, and cells of the second of said types having output terminals at said first pair of locations and input terminals at said second pair of locations, so that cells of said first type are mirror images of cells of said second type. An integrated circuit device as defined in claim 2, wherein an output terminal of a first of said cells of said first type is joined to an adjacent input terminal of a second cell of said first type located adjacent to said first cell to complete a series connection of the logic elements contained in said first and second cells. An integrated circuit device as defined in claim 2, wherein an input terminal of a cell of said first type is joined to an adjacent input terminal of a cell of said second type located adjacent to said cell of said first type and an output terminal of said cell of said first type is joined to an adjacent output terminal of said cell of said second type to complete a parallel connection of the logic elements contained in said cells of said first and second types. An integrated circuit device as defined in claim 1, wherein each cell in a particular row has an identical dimension in a direction transverse to said row. An integrated circuit device as defined in claim 5, wherein the cells and the terminals are located on a Cartesian grid system, each cell occupying a preset number of grid spacings in the direction transverse to the row and an integer number of grid spacings in the row direction.

Inventors: SUNATORI, GO SIMON, SUNTER, STEPHEN KENNETH
Applicants: NORTHERN TELECOM LIMITED
Application year: 1987
Main classification: H01L27
IPC codes: H01L27, H01L23, H01L21