CLOCK SIGNAL GENERATING CIRCUIT

Abstract: In a clock signal generating circuit for a semi­ conductor large scale integrated circuit, the clock signal generating circuit includes: a P-channel transistor (Q₁) and a first N-channel transistor (Q₄), each connected in series between a positive side power source line (V CC ) and a ground side power source line (V SS ); a second N-channel transistor (Q₃) connected between a common connection point of the P-channel transistor and the first N-channel transistor and a gate of the first N-channel transistor through a node, and a clock signal (₁) is applied to a gate of the second N-channel transistor. A capacitor (C₁) is connected between the gate of the first N-channel transistor and a gate of the P-channel transistor; and a bootstrap capacitor (C) is connected to the common connection point. Such a clock signal generating circuit can provide clock signals with improved speed, precision and reliability as compared with those generated by prior art clock signal generating circuits.

Description: The present invention relates to clock signal generating circuitry. In the field of the semiconductor large scale integrated (LSI) circuit, the clock signal generating circuit (or clock generator) is widely used for synchronous operations among a central processing unit, memories and interface units. Accordingly, it is necessary to generate clock signals having a precise timing from the clock generator in order to carry out these synchronous operations. Moreover, the operating speed of these units depends on the clock rate (i.e. clock generating speed from the clock generator). Particularly, the logic operations of the LSI circuit greatly depend on this clock rate. Therefore, it is necessary to realise extremely precise, high speed, and highly reliable clock signals. According to a first aspect of the present invention, there is provided clock signal generating circuitry, for use in a semiconductor large scale integrated circuit, comprising: a first channel-type transistor, of P-channel conductivity type, and a second channel-type transistor, of the opposite channel conductivity type, which transistors have respective current paths connected together in series, at a common output node of the circuitry, between a positive-side power supply line and a ground-side power supply line, a gate of the said first channel-type transistor being connected to receive a first input clock signal, and an output clock signal of the circuitry being produced at the said common output node; a third channel-type transistor, of the said opposite channel conductivity type, having a current path connected between the said common output node and a gate of the said second channel-type transistor, and having a gate connected to receive a second input clock signal; and a bootstrap capacitor having a first electrode connected to the said common output node and a second electrode connected to receive a third input clock signal; characterised by a further capacitor connected between the said gate of the said second channel-type transistor and the said gate of the said first channel-type transistor. EP-A-0098060 proposes clock signal generating circuitry comprising: an N-channel transistor and a first P-channel transistor, which transistors have respective current paths connected together in series, at a common output node of the circuitry, between a first power supply line and a second power supply line, a gate of the said N-channel transistor being connected to receive a first input clock signal, and an output clock signal of the circuitry being produced at the said common output node; a second P-channel transistor having a current path connected between the said common output node and a gate of the said first P-channel transistor, and having a gate connected to receive a second input clock signal; and a bootstrap capacitor having a first electrode connected to the said common output node and a second electrode connected to receive a third input clock signal. According to a second aspect of the present invention, there is provided clock signal generating circuitry, for use in a semiconductor large scale integrated circuit, comprising: a first channel-type transistor, of P-channel conductivity type, and a second channel-type transistor, of the opposite channel conductivity type, which transistors have respective current paths connected together in series, at a common node of the circuitry, between a positive-side power supply line and a further node of the circuitry; a third channel-type transistor, of the said opposite channel conductivity type, having a current path connected between the said further node and a ground-side power supply line; and a bootstrap capacitor having a first electrode connected to the said further node and a second electrode connected to receive an input clock signal; characterised by a fourth channel-type transistor, of the said opposite channel conductivity type, having a current path connected between the said further node and a gate of the said third channel-type transistor, and having a gate connected to receive another input clock signal, and by a further capacitor having a first electrode connected to the said gate of the said third channel-type transistor and a second electrode connected to receive a further input clock signal, respective gates of the said first and second channel-type transistors being connected to receive yet another input clock signal, and an output clock signal of the circuitry being produced at the said common node. GB-A-2156617 proposes clock signal generating circuitry comprising: a P-channel transistor and a first N-channel transistor, which transistors have respective current paths connected together in series, at a common node of the circuitry, between a first power supply line and a further node of the circuitry; a second N-channel transistor having a current path connected between the said further node and a second power supply line; and a bootstrap capacitor having a first electrode connected to the said further node and a second electrode connected to receive an input clock signal. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a circuit diagram of conventional clock signal generating circuitry; Fig. 2 is a signal timing chart of the circuitry shown in Fig. 1; Fig. 3. is a circuit diagram of clock signal generating circuitry according to a first aspect of the present invention; Fig. 4 is a signal timing chart of the circuit shown in Fig. 3; Fig. 5 is a circuit diagram of clock signal generating circuitry according to a second aspect of the present invention; and Fig. 6 is a signal timing chart of the circuit shown in Fig. 5. Firstly, with reference to Figs. 1 and 2, an explanation will be given of clock signal generating circuitry based on that proposed in EP-A-0098060. Referring to Fig. 1, Q1 to Q4 denote MOS transistors, C a bootstrap capacitor, Φ0 to Φ2 input clock signals, OT an output terminal, N1 a node, V cc a voltage level of a positive side power source line, and V ss a voltage level of a ground side power source line. The operations of this circuit will be explained in detail with reference to Fig. 2. In Fig. 2, the left side denotes an active state and the right side denotes a reset state. The clock signal CLK is obtained by alternately repeating these two states. The clock signal CLK is produced at the output terminal OT, and is indicated in Fig. 2 by black dots. The clock signal CLK is pulled down from the V cc level to a V ss0 level, which is lower than the V ss level, by a bootstrap effect of the capacitor C in the active state and pulled up from the V ss0 level to the V cc level in the reset state. In order to obtain these curves, first, when the clock signal Φ0 applied to the gate of the transistor Q1 is pulled up from the V ss level to the V cc level, the P-channel transistor Q1 is turned OFF. Accordingly, the level of the output terminal OT is held to the V cc level. At this time, the clock signal Φ1 applied to the gate of the transistor Q2 is set to the V ss level, and thus the P-channel transistor Q2 is held in the ON state. Accordingly, the node N1 is charged up through the transistor Q2 so as to approach the V cc level. When the node N1 approaches the V cc level, the level of the output terminal OT reaches the V ss level, since the N-channel transistor Q4 is turned ON. Next, when the clock signal Φ1 is pulled up from the V ss level to the V cc level, the P-channel transistor Q2 is turned OFF and the N-channel transistor Q3 is turned ON. Accordingly, the charge of the node N1 is discharged through the transistor Q3 to the output terminal OT. Thus, the level of the node N1 is pulled down to the V ss level, and then the N-channel transistor Q4 is turned OFF. In these states, when the clock signal Φ2 is pulled down from the V cc level to the V ss level, the level of the output terminal OT is pulled down to the V ss0 level lower than the V ss level. This rapid pulling down of the output level depends on the so-called bootstrap effect achieved by the bootstrap capacitor C. That is, when the node N1 is at the V ss level, the charges flow from the V ss side to the output terminal OT when the level of the output terminal OT is pulled down to the V ss - V th level. Accordingly, the level of the output terminal OT cannot be pulled down lower than the above level. In this case, since the N-channel transistor Q3 is turned ON and the node N1 is connected to the output terminal OT, the level of the node N1 can be simultaneously pulled down and the transistor Q4 is held in the OFF state. Accordingly, the level of the output terminal OT can be pulled down to the V ss0 level lower than the V ss level of the ground side power source line. This phenomenon is known as the bootstrap effect. When the node N1 is the V ss level, the level of the output terminal OT is pulled down to the V ss - V th and the charges flow from the V ss side as explained above. This phenomenon will be explained in more detail below. That is, when the node N1 is the V ss level, the output side of the transistor Q4 becomes a source and the ground side thereof becomes a drain, when the output terminal OT is pulled down lower than the V ss level. When the source side of the transistor Q4 becomes V ss - V th , the potential difference between the source and the drain becomes higher than V th . Accordingly, the charges (current) flow from the ground side to the output terminal side. In this case, although the level of the output terminal OT is not pulled down lower than the level of V ss - V th , in actual practice, the level of the output terminal OT is pulled down to the V ss0 level since the transistor Q3 is turned ON and the transistor Q4 is turned OFF. As a result, the bootstrap effect is realized in the output terminal OT. In the reset state, when the clock signal Φ0 is pulled down from the V cc level to the V ss level, the P-channel transistor Q1 is turned ON and the clock signal CLK is pulled up to the V cc level. At this time, since the clock signal Φ1 is held at the V cc level, the transistor Q2 is held in the OFF state and the transistor Q3 is held in the ON state. Accordingly, the node N1 is charged up through the transistor Q3 so as to approach the V cc level. Next, when the clock signal Φ1 is also pulled down from the V cc level to the V ss level, the transistor Q3 is turned OFF and the transistor Q2 is turned ON. Accordingly, the charge of the node N1 is discharged to the signal line L of the clock signal Φ0 through the transistor Q2 and the level of the node N1 is pulled down so as to approach the V ss level. Thus, the N-channel transistor Q4 is turned OFF. There is, however, a problem in the reset state. That is, when the transistor Q2 is turned ON, the charge of the node N1 is discharged to the signal line L. Accordingly, the level of the node N1 is pulled down to nearly the level of the V ss level as shown in Fig. 2. The difference between this level and the V ss level is shown by "LQ2" in Fig. 2. The difference LQ2 is caused by a threshold level V th of the transistor Q2. Accordingly, assuming that the threshold level of the P-channel transistor Q2 is higher than that of the N-channel transistor Q4, the level of the node N1 cannot be pulled down to a sufficiently low level (i.e. V ss level), and thus the N-channel transistor cannot be completely turned OFF. Consequently, it is difficult to obtain an extremely precise, high speed, and highly reliable clock signal CLK in the conventional clock generator. A clock signal generating circuit embodying the first aspect of the present invention will be explained in detail hereinafter with reference to Figs. 3 and 4. Referring to Fig. 3, the same reference numbers are attached to the same components as that of the circuit shown in Fig. 1. In this embodiment, the P-channel transistor Q2 is omitted and a capacitor C1 is added between the node N1 and the signal line L. The operations of this circuit will be explained in detail with reference to Fig. 4. In Fig. 4, when the clock signal Φ0 applied to the gate of the transistor Q1 is pulled up from the V ss level to the V cc level, the P-channel transistor Q1 is turned OFF and the level of the output terminal OT (clock signal CLK is output) is held to the V cc level. At this time, the level of the node N1 is pulled up by the capacitor C1 so as to approach the V cc level. When the level of the node N1 is pulled up, the level of the clock signal CLK is pulled down to the V ss level since the first N-channel transistor Q4 is turned ON. Next, when the clock signal Φ1 applied to the gate of the transistor Q3 is pulled up from the V ss level to the V cc level, the second N-channel transistor Q3 is turned ON. Accordingly, the charge of the node N1 is discharged through the transistor Q3 to the output terminal OT, then, the node N1 is pulled down to the V ss level, and thus the N-channel transistor Q4 is turned OFF. In these states, when the clock signal Φ2 applied to the bootstrap capacitor C is pulled down from the V cc level to the V ss level, the level of the clock signal CLK is pulled down to the V ss0 level lower than the V ss level by the bootstrap effect of the capacitor C. In the reset state, when the clock signal Φ1 is pulled down from the V cc level to the V ss level, the N-channel transistor Q3 is turned OFF. When the clock signal Φ0 is pulled down from the V cc level to the V ss level, the P-channel transistor Q1 is turned ON. Accordingly, the clock signal CLK is pulled up to the V cc level and the level of the node N1 is pulled down further. As explained above, the N-channel transistor Q3 is turned OFF when the clock signal Φ1 is pulled down from the V cc level to the V ss level. The clock signal CLK is pulled up from the V ss0 level to the V cc level when the, clock signal Φ0 is pulled down from the V cc level to the V ss level. Accordingly, the node N1 is charged up through the transistor Q3. When the threshold level of the transistor Q3 is V th , the level of the node N1 becomes V ss - V th . Consequently, it is possible for the transistor Q4 to completely turn OFF since the level of the node N1 is sufficiently pulled down. As explained in Figs. 1 and 2, conventionally, the level of the node N1 becomes V ss + V th . Therefore, it is difficult for the transistor Q4 to completely turn OFF since the level of the node N1 can not be sufficiently pulled down. Clock signal generating circuitry embodying the second aspect of the present invention will now be explained with reference to Figs. 5 and 6. Referring to Fig. 5, the P-channel transistor Q5 and the first N-channel transistor Q6 are newly added to the output stage. Accordingly, the output terminal OT is provided at the common connection point of both transistors Q5 and Q6. The clock signal Φ3 is also newly applied to the common connection point of both gates of the transistors Q5 and Q6. Each of the transistors Q5 and Q6 is constituted by a complementary MOS transistor (CMOS transistor). In the active state, when the clock Signal Φ0 is pulled down from the V cc level to the V ss level, the level of the first node N1 is pulled down from the near level of the V cc level to the V ss level and the second N-channel transistor Q4 is turned OFF. At this time, when the clock signal Φ1 is pulled up from the V ss level to the V cc level, the third N-channel transistor Q3 is turned ON, then, the node N1 is connected to the second node N2. In this state, when the clock signal Φ3 is pulled up from the V ss level to the V cc level, the P-channel transistor Q5 is turned OFF and the N-channel transistor Q6 is turned ON, thus, the clock signal CLK is pulled down from the V cc level to the V ss0 level. At this time, when the clock signal Φ2 is pulled down from the V cc level to the V ss level, the level of the node N2 is pulled down lower than the V ss level by the bootstrap effect of the capacitor C. Since the node N2 is pulled down lower than the V ss level at the same time as the transistor Q6 is turned ON, the clock signal CLK is rapidly pulled down from the V cc level to the V ss0 level lower than the V ss level by the bootstrap effect of the capacitor C. In the reset state, when the clock signal Φ3 is pulled down from the V cc level to the V ss level, the P-channel transistor Q5 is turned ON and the N-channel transistor Q6 is turned OFF. Accordingly, the level of the output terminal OT (clock signal CLK is output) is pulled up from the V ss0 level to the V cc level. At this time, the charge of the node N2 is slightly discharged to the output terminal. In this state, when the clock signal Φ2 is pulled up from the V ss level to the V cc level, the levels of the nodes N1 and N2 are pulled up to V ss + V th since the node N1 is connected to the node N2 through the transistor Q3. This value V ss + V th is a limitation value at which the transistor Q4 is not turned ON. Next, when the clock signal Φ1 is pulled down from the V cc level to the V ss level, the N-channel transistor Q3 is turned OFF. After this step, when the clock signal Φ0 is pulled up from the V ss level to the V cc level, the level of the node N1 is pulled up and the N-channel transistor Q4 is turned ON. Accordingly, the level of the node N2 is held at the V ss level. In the specification, all of the clock signals Φ0, Φ1, Φ2 and Φ3 are generated from control means (not shown) in the LSI circuit, and since a conventional control means can be used, an explanation thereof will be omitted.

Claims: Clock signal generating circuitry, for use in a semiconductor large scale integrated circuit, comprising: a first channel-type transistor (Q₁), of P-channel conductivity type, and a second channel-type transistor (Q₄), of the opposite channel conductivity type, which transistors (Q₁, Q₄) have respective current paths connected together in series, at a common output node (OT) of the circuitry, between a positive-side power supply line (V CC ) and a ground-side power supply line (V SS ), a gate of the said first channel-type transistor (Q₁) being connected to receive a first input clock signal (Φ₀), and an output clock signal (CLK) of the circuitry being produced at the said common output node (OT); a third channel-type transistor (Q₃), of the said opposite channel conductivity-type, having a current path connected between the said common output node (OT) and a gate of the said second channel-type transistor (Q₄), and having a gate connected to receive a second input clock signal (Φ₁); and a bootstrap capacitor (C) having a first electrode connected to the said common output node (OT) and a second electrode connected to receive a third input clock signal (Φ₂); characterised by a further capacitor (C₁) connected between the said gate of the said second channel-type transistor (Q₄) and the said gate of the said first channel-type transistor (Q₁). Clock signal generating circuitry, for use in a semiconductor large scale integrated circuit, comprising: a first channel-type transistor (Q₅), of P-channel conductivity type, and a second channel-type transistor (Q₆), of the opposite channel conductivity type, which transistors (Q₅, Q₆) have respective current paths connected together in series, at a common node (OT) of the circuitry, between a positive-side power supply line (V CC ) and a further node (N₂) of the circuitry; a third channel-type transistor (Q₄), of the said opposite channel conductivity type, having a current path connected between the said further node (N₂) and a ground-side power supply line (V SS ); and a bootstrap capacitor (C) having a first electrode connected to the said further node (N₂) and a second electrode connected to receive an input clock signal (Φ₂); characterised by a fourth channel-type transistor (Q₃), of the said opposite channel conductivity type, having a current path connected between the said further node (N₂) and a gate of the said third channel-type transistor (Q₄), and having a gate connected to receive another input clock signal (Φ₁), and by a further capacitor (C₁) having a first electrode connected to the said gate of the said third channel-type transistor (Q₄) and a second electrode connected to receive a further input clock signal (Φ₀), respective gates of the said first and second channel-type transistors (Q₅, Q₆) being connected to receive yet another input clock signal (Φ₃), and an output clock signal (CLK) of the circuitry being produced at the said common node (OT).

Inventors: TAKEMAE YOSHIHIRO
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: H03K5
IPC codes: H03K17, H03K19, H03K5