SEMICONDUCTOR INTEGRATED CIRCUIT CONTAINING ANALOGOUS AND DIGITAL COMPONENTS

Abstract: This invention discloses a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip. The semiconductor inte­ grated circuit includes a p-type semiconductor region (11), an n⁺-type buried region (12) formed on the p-type semiconductor region (11), an n-type semiconductor region (13) formed on the n⁺-type buried region (12), a first isolation portion (19), extending through the n-type semiconductor region (13) and the n⁺-type buried region (12), and reaching the p-type semiconductor region (11), for isolating adjacent transistors in an analog circuit (27) formed on the n-type semiconductor region (13), and a second isolation portion (17), formed in the n-type semiconductor region (13), for isolating adjacent transistors in the n-type semiconductor region (13).

Description: The present invention relates to a semiconductor integrated circuit and, more particularly, to a hybrid semiconductor integrated circuit in which semiconductor elements are isolated by the trench isolation method, and analog and digital circuits are formed on a single chip. In this specification, the expression "digital circuit" means an integrated circuit of integrated injection logic (I²L) type, MOS type or CMOS type, and the expression "analog circuit" means a bipolar semiconductor integrated circuit. EP-A-0 013 508 discloses an integrated circuit which includes isolation grooves (76,77) reaching the substrate (1) and totally isolating parts of the active layer (3) and further grooves (71-75) which separate parts of said active layer (3) electrically connected by the underlying highly doped buried layer (2) of the same conductivity type. No analog circuits are disclosed in the integrated device. US-A-4 536 945 discloses CMOS structures integrated with Schottky clamped bipolar transistors. Each bipolar transistor is formed in an isolated region on top of an N+ buried layer restricted to the isolated region. The trench isolation method is a known conventional method of isolating semiconductor elements. Using the trench isolation method, a vertical trench is formed on a semiconductor substrate by reactive ion etching (to be referred to as RIE hereinafter), a dielectric (insulation material) is selectively left in this trench, thereby utilizing it for element isolation. Using the trench isolation method, a trench having a small pattern transfer difference can be formed at an arbitrary depth. Since a dielectric is filled into the trench, the parasitic capacitance is decreased as compared with other p-n junction isolation methods. For this reason, trench isolation is widely used for VLSIs. However, when transistors are isolated by use of the trench isolation method, they are complete isolated from each other. Thus, in the case of a bipolar semiconductor integrated circuit which requires an electrode for providing a reference voltage to be formed on the lower surface of a chip, an integrated injection logic circuit (hereinafter referred to as an I²L circuit) cannot be formed on a single chip. The reason the I²L circuit cannot be formed is that the emitters of vertical transistors, each of which uses an n-type conductive buried layer, are completely isolated from each other. Particularly in the case where analog and digital circuits are formed together on a single chip, the above-described situation presents a serious problem. Thus, a conventional I²L circuit is arranged by leading electrodes from the emitters of the respective transistors, to connect them to each other by way of lines. Elements, however, cannot be micropatterned by such a method. It is an object of the present invention to provide a semiconductor integrated circuit in which, when analog and digital circuits are formed on a single chip, each element can be adequately isolated, and an IC can be miniaturized. According to the invention, there is provided a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip, comprising: a first semiconductor region, containing an impurity of a first conductivity type; a first high-impurity semiconductor region formed on part of said first semiconductor region and containing an impurity of a second conductivity type at a high concentration; a second semiconductor region, formed entirely on said fire high-impurity semiconductor region and containing an impurity of the second conductivity type; a third semiconductor region, formed on said first semiconductor region, adjacent to said second semiconductor region, and containing an impurity of the first conductivity type; a first isolation portion, extending through said second semiconductor region and said first high-impurity semiconductor region, and reaching said first semiconductor region, for isolating adjacent transistors in said analog circuit formed in said second semiconductor region and for isolating the region containing said analog circuit from the region containing said digital circuit; and at least one second isolation portion, which does not reach said first semiconductor region, for isolating adjacent transistors in said digital circuit formed in said second semiconductor region and said third semiconductor region. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1G are sectional views for explaining the steps in manufacturing a semiconductor integrated circuit which does not represent an embodiment of the invention as claimed, in which Fig. 1A is a sectional view wherein an n⁺ -type buried layer, n-type semiconductor regions, and n⁺ -type diffused layers are formed on a p-type silicon substrate, and a thermal oxide film is formed on the n-type semiconductor regions; Fig. 1B is a sectional view wherein the thermal oxide film shown in Fig. 1A is etched using a patterned photoresist film as a mask, and second trenches as second isolation portions are formed on the n-type semiconductor regions; Fig. 1C is a sectional view wherein, after the above photoresist film is entirely removed, first trenches are formed as first isolation portions in the same manner as in Fig. 1B, by using another patterned photoresist film; Fig. 1D is a sectional view wherein, after the above photoresist film is completely removed, an undoped CVD-SiO₂ film is deposited, and portions thereof remaining in the bottom regions of the second trenches are selectively etched by using a photoresist having openings corresponding to the positions of the second trenches, so as to form boron ion-implanted regions in the bottom regions of the second trenches; Fig. 1E is a sectional view wherein, after the above photoresist is entirely removed and the ion-implanted regions are converted into p⁺-type diffused regions by annealing, an insulating film is formed on the surface of a silicon oxide film on side surfaces of the first and second trenches, an undoped polysilicon layer is filled into the first and second trenches, the surfaces of the n-type semiconductor regions are exposed, and a thermal oxide film is then formed; Fig. 1F is a sectional view wherein boron ions are implanted into the n-type semiconductor regions, to form p⁻⁻-type diffused regions, a p⁻-type diffused region, and p⁺-type diffused regions; and Fig. 1G is a sectional view wherein a semiconductor integrated circuit is finished by forming n⁺-type diffused regions in the p⁻-type diffused region and the p⁻⁻-type diffused regions, and by forming metal electrodes; Fig. 2 is a circuit diagram showing an equivalent circuit of the semiconductor integrated circuit shown in Fig. 1G; and Fig. 3 is a sectional view showing an embodiment of the invention. The structure and a method of manufacturing a semiconductor integrated circuit will now be described, with reference to Figs. 1A to 1G. First, 4-µm thick n⁺-type buried layer 12 containing an n-type impurity such as antimony (Sb) of a high dose, e.g., 10¹⁹/cm², and having a sheet resistance ρs ≅ 20 Ωcm is deposited on p-type silicon substrate 11. After this, 2-µm thick n-type semiconductor region 13 containing an n-type impurity such as phosphorus of a low dose, e.g., 3 X 10¹⁵/cm², and having a sheet resistance of ρs ≅ 2 Ωcm is deposited on n⁺-type buried layer 12, by epitaxial growth. Then, impurity ions are selectively difrused into n-type diffused region 13, to a depth of about 2.5 µm, by using a P-As silicate glass (not shown) containing phosphorus and arsenic, or the like as a diffusion source, so as to form n⁺-type diffused layers 14A and 14B whose bottom portions reach n⁺-type buried layers 12. After this, thermal oxidation is performed in an oxygen atmosphere at 1,000°C, to form 300nm (3,000-Å) thick thermal oxide film 15 on the surface of n-type semiconductor region 13. Photoresist film 16 is formed on the entire surface, and is then patterned. Unmasked portions of thermal oxide film 15 are selectively removed in a CF₄ and H₂ gas atmosphere, by the RIE method using patterned photoresist film 16 as a mask. In addition, 2-µm deep vertical trenches 17 as second isolation portions are formed in region 13 at an RF power of 150 W/unit area and 53.3 Pa (0.4) Torr, by the RIE method using a gas mixture of chlorine gas (C₁₂) and hydrogen gas (H₂). In this case, since n-type semiconductor region 13 has a thickness of 2 µm, trenches 17 are formed such that the bottom portions thereof reach n⁺-type buried layer 12 under n-type semiconductor region 13 (shown in Fig. 1B). After photoresist 16 is completely removed, another photoresist film, 18, is formed and patterned. Then, after thermal oxide film 15 is etched by means of the RIE method, in the same manner as described above, vertical trenches 19 having a depth of 7 µm are formed as first isolation portions, again by means of the RIE method. In this case, since photoresist film 18 is filled in trenches 17 formed in the previous step, trenches 17 are not further etched. N-type semiconductor region 13 and n⁺-type buried layer 12 have thicknesses of 2 µm and 4 µm, respectively. For this reason, trenches 19 are formed such that the bottom portions thereof extend through n-type semiconductor region 13 and n⁺-type buried layer 12, and reach p-type silicon substrate 11 (Fig. 1C). Note that trenches 17 may be formed before trenches 19. Next, photoresist film 18 is completely removed, and a silicon oxide film not containing an impurity, i.e., so-called undoped silicon oxide film 20, having a thickness of 100nm (1,000 Å) is deposited by the chemical vapor deposition method (to be referred to as the CVD method hereinafter). At this time, undoped silicon oxide film 20 is deposited on the wall surfaces of trenches 17 and 19. Then, photoresist film 21 is formed on the surface of oxide film 20 again, and patterning is performed to form openings at positions corresponding to only trenches 19 having a depth greater than that of trenches 17. Undoped oxide film 20 present in trenches 19 is selectively etched by the RIE method, using patterned photoresist film 21 as a mask. When photoresist film 21 is patterned, it is known that an alignment error always occurs with respect to trenches 19. However, since a two-layer film consisting of thermal oxide film 15 and undoped silicon oxide film 20 is formed on the surfaces of n-type semiconductor region 13, even if an alignment error occurs between patterned photoresist film 21, and hence the openings are misaligned in relation to trenches 19, the two-layer film serves as a protective barrier against etching, thereby preventing n-type semiconductor region 13 from being exposed. Then, impurity ions are implanted, using photoresist film 21 and thermal oxide film 15 as masks, at an acceleration voltage of 50 keV and a dose of 1 x 10¹⁵/cm², so as to form ion-implanted regions 22 (shown in Fig. 1D). Next, photoresist film 21 is completely removed. The resultant structure is thermally annealed in a nitrogen atmosphere at 1,000°C, so that ion-implanted regions 22 are activated and converted into p⁺-type diffused regions 23. Then, thermal oxidation is performed in an oxygen atmosphere at 1,000°C, to form a 100nm (1,000-Å) thick thermal oxide film. By forming the thermal oxide film in this manner, two-layer insulating film 24 consisting of undoped silicon oxide film 20 and this thermal oxide film are formed on the wall surfaces of trenches 17 and 19. Additionally, undoped polysilicon layer 25 is deposited by use of the CVD method. In this case, undoped polysilicon layer 25 is deposited to a thickness at which the layer completely fills trenches 17 and 19. For example, if trenches 17 and 19 are formed to have a width of 1 µm, the thickness of undoped polysilicon layer 25 is set to be greater than half the width of the trenches, e.g.700nm (7,000 Å) After this, a photoresist film is formed on the surface of the resultant structure, and the deposited layer consisting of undoped silicon oxide film 20 and thermal oxide film 15, formed on the surface of n-type semiconductor region 13, is etched. Then, after the surface of n-type semiconductor region 13 is exposed, thermal oxidation is performed again in an oxygen atmosphere at 1,000°C, to form 100nm (1,000-Å) thick thermal oxide film 26. After this, the region where trenches 19 are formed serves as analog circuit region 27 where transistors for the analog circuit are formed. The region where trenches 17 are formed serves as digital circuit region 28 where transistors for the digital circuit are formed (shown in Fig. 1E). Boron ions are implanted into n-type semiconductor region 13 of analog and digital circuit regions 27 and 28, to activate them, thereby sequentially forming p⁻⁻type diffused regions 31 and 32, p⁻-type diffused region 33, p⁺-type diffused regions 34, 35, 36, 37, and 38. More specifically, boron ions are implanted twice, i.e., first, at an acceleration voltage of 40 keV and a dose of 2 X 10¹²/cm²; second, at an acceleration voltage of 200 keV and a dose of 2 x 10¹²/cm², so as to form ion-implaned regions (not shown) for p⁻⁻-type diffused regions 31 and 32. Next, impurity ions are implanted at an acceleration voltage of 40 keV and a dose of 3 x 10¹³/cm², to form an ion-implanted region (not shown) for p⁻-typed diffused region 33. In addition, impurity ions are implanted at an acceleration voltage of 40 keV and a dose of 1 x 10¹⁵/cm², to form ion-implanted regions (not shown) for p⁺-type diffused regions 34, 35, 36, 37, and 38. P⁻⁻-type diffused regions 31 and 32 are formed deeper than p⁺-type diffused regions 34, 35, 36, 37, and 38 (Fig. 1F). Next, thermal oxide film 26 is selectively removed by etching, to partially expose the surfaces of p⁻⁻-type diffused regions 31 and 32, and p⁻-type diffused region 33. Then, polysilicon containing arsenic (As) having a dose of 1 x 10²⁰/cm³ as an n-type impurity is deposited, and the resultant structure is thermally annealed to form 350nm (3,500-Å)thick n⁺-type polysilicon layer 39. After this, n⁺-type polysilicon layer 39 is patterned. Then, silicon oxide film 40 having a thickness of 500nm (5,000 Å) is deposited by means of the CVD method, and 700nm (7,000-Å) thick phosphosilicate glass (to be referred to as PSG) 41 is deposited thereon, also by use of the CVD method. Conventional phosphorus gettering and diffusion from n⁺-type polysilicon layer 39 are performed to form n⁺-type diffused regions 42, 43, and 44, respectively, inside p⁻⁻-type diffused regions 31 and 32, and p⁻-type diffused region 33. PSG film 41 and silicon oxide film 40 are selectively etched to form contact holes. Then, an electrode material such as aluminum is deposited by vacuum deposition or the like, and is patterned to form metal electrodes 45 to 52. After this, a semiconductor integrated circuit is finished by sintering (Fig. 1G). The semiconductor integrated circuit having the structure shown in Fig. 1G, p⁻-type diffused region 33, in analog circuit region 27, serves as a base region, n⁺-type diffused region 44 serves as an emitter region, n-type semiconductor region 13 serves as a collector region, and p⁺-type diffused region serves as a base contact region, thereby forming an npn transistor having metal electrodes 50, 51, and 52, respectively, as its base, emitter, and collector electrodes. This npn transistor is isolated from other transistors by trenches 19. In digital circuit region 28, an I²L gate is formed consisting of a vertical npn transistor and a lateral pnp transistor for injection. The vertical transistor has p⁻⁻-type diffused region 31, n⁺-type diffused region 42, n-type semiconductor region 13, and p⁺-type diffused region 34, respectively serving as its base, collector, emitter, and base contact regions. The lateral pnp transistor for injection has p⁺-type diffused region 35, n-type semiconductor region 13, and p⁺-type diffused region 34, respectively serving as its emitter, base, and collector regions. Another I²L gate is formed consisting of a vertical npn transistor and a lateral pnp transistor for injection. The vertical transistor has p⁻⁻-type diffused region 32, n⁺-type diffused region 43, n-type semiconductor region 13, and p⁺-type diffused region 36, respectively serving as its base, collector, and emitter, and base contact regions. The lateral transistor for injection has p⁺-type diffused region 37, n-type semiconductor region 13, and p⁺-type diffused region 36, respectively serving as its emitter, base, and collector regions. Metal electrode 45 serves as one input electrode; metal electrode 47, as the other input electrode; metal electrodes 46 and 48, as injection electrodes; and polysilicon layers 39 left in n⁺-type diffused regions 42 and 43, as an output electrode. Metal electrode 49, formed on the surface of n⁺-type diffused region 14B which is formed to reach n⁺-type buried layer 12, serves as a common emitter electrode. The I²L gate consisting of the above vertical and lateral transistors is isolated from the other I²L gate by trenches 17. Analog circuit region 27 and digital circuit region 28 are isolated from each other by trenches 19. Fig. 2 is an equivalent circuit of a semiconductor integrated circuit having the cross sectional structure shown in Fig. 1G. Referring to Fig. 2, npn transistor 61 is the one which is formed in analog circuit region 27. Transistor 61 is isolated from other transistors by trenches 19, in the above-described manner. Since trenches 19 reach the inside n-type semiconductor region 13, as described above, analog circuit region 28 is completely isolated from other transistors. Therefore, the parasitic capacitance between the respective transistors can be reduced, thereby improving its overall electrical characteristics as an analog circuit. Note that p⁺-type diffused regions 23 are formed on the bottom region of trenches 19 in Fig. 1G, so that a parasitic transistor consisting of p-type silicon substrate 11 and n⁺-type buried layer does not have to be formed. On the other hand, npn transistors 62 and 63 in Fig. 2 serve as the vertical transistors of the I²L gate formed in digital circuit region 28, and pnp transistors 64 and 65 serve as the lateral transistors for injection of the I²L gate. The I²L gates are isolated from each other by shallow trenches 17 reaching n⁺-type buried layer 12. Thus, an influence of the parasitic capacitance between the I²L gates can be reduced. In addition, since n⁺-type buried layer 12 used as a common emitter is not isolated from each other, lines 66 in Fig. 2 can be arranged continuously. Therefore, elements can be micropatterned, as compared with a conventional case in which electrodes are respectively led and connected to the emitters. Fig. 3 is a cross sectional view of an arrangement in which the present invention is applied to a Bi-CMOS logic circuit. In this embodiment, n⁺-type buried layer 12a is formed on a part of p-type silicon substrate 11, n-type well layer 72 is formed on n⁺-type buried layer 12a, and p-type epitaxial layer 73 is formed on silicon substrate 11 excepting n⁺-type buried layer 12a. In analog circuit region 27, an npn transistor is formed to have p⁻-type diffused region 33, n⁺-type diffused region 44, n-type diffused layer 14, and p⁺-type diffused region 38, respectively serving as base, emitter, collector, and base contact regions. The npn transistor is isolated from other transistors in analog circuit region 27 by deep trenches 19 reaching p-type silicon substrate 11. Analog circuit region 27 and digital circuit region 28 are isolated from each other by deep trenches 19 reaching p-type silicon substrate 11. In digital circuit region 28, p-channel MOS transistors and n-channel MOS transistors are respectively formed in n-type well layer 72 and p-type epitaxial layer 73. More precisely, a plurality of p-channel MOS transistors having p⁺-type diffused regions 74 and 75 as source and drain regions are formed in n-type well layer 72. Note that reference numerals 76 denote n⁺-type polysilicon layers serving as gate electrodes of these p-channel MOS transistors; and, 77 and 78, source and drain electrodes made of aluminium. A plurality of n-channel MOS transistors having n⁺-type diffused regions 79 and 80, respectively serving as source and drain regions, are formed in p-type epitaxial layer 73. Note that reference numerals 81 denote n⁺-type polysilicon layers serving as gate electrodes made of these n-channel MOS transistors; and 82 and 83, source and drain electrodes mode of aluminium. Trenches 17, whose bottom regions reach silicon substrate 11, are formed between the respective p-channel MOS transistors and also between the respective n-channel MOS transistors. In this embodiment, the bipolar transistors of the analog circuit are completely isolated from each other by trenches 19, in the same manner described in the first embodiment. As a result, the parasitic capacitance between the adjacent transistors can be reduced, and the overall electrical characteristics of this circuit, as an analog circuit, can be improved. Thus, analog and digital circuits are formed on a single chip, and each transistor of the analog circuit is isolated by the first isolation portion extending through the third semiconductor region and the second high impurity semiconductor region, and reaching the first semiconductor region, thereby completely isolating each transistor of the analog circuit. Thus, parasitic capacitance between the adjacent transistors can be reduced so as to improve the overall characteristics of the analog circuit. Since each transistor of the digital circuit is isolated by the second isolation portion formed in the third semiconductor region, the second high-impurity semiconductor region can be commonly used by each transistor of the digital circuit. Therefore, the second high-impurity semiconductor region can be used as a common emitter for each transistor, thereby micropatterning the elements.

Claims: A semiconductor integrated circuit in which an analog circuit (27) and a digital circuit (28) are formed on a single chip, comprising: a first semiconductor region (11), containing an impurity of a first conductivity type; a first high-impurity semiconductor region (12a) formed on part of said first semiconductor region (11) and containing an impurity of a second conductivity type at a high concentration; a second semiconductor region (72), formed entirely on said first high-impurity semiconductor region (12a) and containing an impurity of the second conductivity type (N); a third semiconductor region (73), formed on said first semiconductor region (11), adjacent to said second semiconductor region (72), and containing an impurity of the first conductivity type; a first isolation portion (19), extending through said second semiconductor region (72) and said first high-impurity semiconductor region (12a), and reaching said first semiconductor region (11), for isolating adjacent transistors in said analog circuit (27) formed in said second semiconductor region (72) and for isolating the region containing said analog circuit (27) from the region containing said digital circuit (28); and at least one second isolation portion (17), which does not reach said first semiconductor region (11), for isolating adjacent transistors in said digital circuit (28) formed in said second semiconductor region (72) and said third semiconductor region (73). A circuit according to claim 1, wherein a second high impurity semiconductor region (23) is formed in said first semiconductor region (11), at the bottom of said first isolation portion (19), and contains an impurity of the first conductivity type at a high concentration. A circuit according to claim 1 or 2, wherein the bottom of said at least one second isolation portion (17) reaches a boundary between said first high impurity semiconductor region (12a) and said second semiconductor region (72). A circuit according to any preceding claim wherein said first isolation portion (19) comprises a first trench, vertically formed in said first semiconductor region (11), said first high impurity semiconductor region (12a), and said second semiconductor region (72), an insulating film (24) formed on a wall surface of said first trench, and a polysilicon layer (25) buried in a wall surface of said insulating film (24). A circuit according to any preceding claim, wherein said at least one second isolation portion (17) comprises a first trench, vertically formed in said second semiconductor region (72), a second trench vertically formed in said third semiconductor region (73), an insulating film (24) formed on a wall surface of said first and second trenches, and a polysilicon layer (25) buried in a wall surface of said insulating film (24).

Inventors: TAGUCHI, MINORU C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: H01L21
IPC codes: H01L21, H01L27