SENSE AMPLIFIER FOR A SEMICONDUCTOR MEMORY DEVICE

Abstract: In a sense amplifier, the first input terminal of the differential amplifier (26) is connected to a first MOS transistor (23) operating as a transfer gate, a first floating gate transistor (22) operating as a memory cell, and a first load (24). The gates of the first MOS transistor (23) and the first floating gate transistor (22) are respectively connected to the column-­ select line (BL) and the word line (WL). The second input terminal of the differential amplifier (26) is connected to a second load (28), a second MOS transistor (31) operating as a transfer gate, and a second floating gate transistor (32) operating as a dummy cell. The second load (28) has the same characteristics as the first load (24). The second load (28) is composed of first and second load elements (28A, 28B). The second floating gate transistor (32) is constantly supplied with power voltage. When a shift in the thre shold voltage of the first floating gate transistor (22) is monitored, the first load element (28A) of the second load (28) is disconnected from the input terminal of the differential amplifier (26), and only the second load element (28B) remains connected to the input ter­ minal. The gate of the second MOS transistor (31) is supplied with the high potential. A gradually increas­ ing potential is applied to the gates of the first MOS transistor (23) and the first floating gate transistor (22). The potential is detected when the data of the first floating gate transistor changes from "0" to "1".

Description: This invention relates to a semiconductor memory device, and more particularly, to the improvement of a sense amplifier of a semiconductor memory device used for sensing a change in the threshold voltage of a non-­ volatile, erasable memory cell contained in an EPROM, for example. Generally, the sense amplifier for the memory cell of, for example, an EPROM which includes a differential amplifier, has a circuit arrangement as shown in Fig. 1. In this figure, word line WL is connected to the control gate electrode of floating gate transistor 11 operating as a memory cell. Column-select line BL is connected to the gate of MOS transistor 12 operating as a transfer gate. MOS transistor 12 is also connected to load 13. The first input terminal of differential amplifier 15 is connected to a connection point of load 13 and MOS tran­ sistor 12 via sense line 14. The second input terminal of differential amplifier 15 is connected to the output terminal of reference potential generator 16 operating as an internal test circuit. Reference potential gen­ erator 16 contains dummy cell 17, MOS transistor (trans­ fer gate) 18, and load 19. Dummy cell 17 is the same size as floating gate transistor (transfer gate) 11, and receives, at the gate, power voltage Vcc. Load 19 pro­ vides an intermediate level VR between high ("H") and low ("L") levels on sense line 14. With such an arrangement, in a write mode, high potential Vpp is applied to the gate of transistor 11. In a read-out mode, power voltage Vcc is applied there­ to. Voltages Vpp and Vcc are externally applied through respective terminals. A shift ΔV TH in threshold voltage V TH of the sense amplifier changes its value in relation to power voltage Vcc, as is shown in Fig. 2. The sensitivity of the sense amplifier can be expressed by a shift ΔV TH in the threshold voltage V TH necessary for detecting that data has been stored in a memory cell. In the sense ampli­ fier constructed as shown in Fig. 1, as can be seen from Fig. 2, the shift ΔV TH in the threshold voltage V TH necessary for detecting the data-stored state of the memory cell is 3V, even when power voltage Vcc is in­ creased to 8V. Shift ΔV TH is 4V at most, even for 10V of power voltage Vcc. When considering the breakdown voltage of the transistors used in the peripheral cir­ cuit of the sense amplifier, it is difficult to set power voltage Vcc at 10V or more. Therefore, it is impossible to monitor a shift ΔV TH of 4V or more in this threshold voltage. A prior art sense amplifier, which eliminated the above disadvantage, is illustrated in Fig. 3. The Fig. 3 circuit differs from the Fig. 1 circuit only in the following points: Loads 13 and 19 are designed so as to have the same electrical characteristics. Low voltage Vc, which is not dependent on power voltage Vcc and is lower than the power voltage, is applied to the gate of dummy cell 17 from constant-voltage generator 20, which is formed on the chip of the memory cells. The sense amplifier shown in Fig. 3 has a circuit arrangement which is symmetrically arrayed with respect to differential amplifier 15. Therefore, a point where mutual conductance gm of memory cell 11 is equal to that of memory cell 17 corresponds to a critical point, where a unit of stored data changes it's level. The current I₁₁ flowing through memory cell 11 can be expressed by I₁₁ α Vcc - V TH11 = Vcc - (V TH0 + ΔV TH ). where V TH11 is the threshold voltage of floating gate transistor (memory cell) 11 when data has been written thereinto, viz., carriers have been injected into the transistor. V TH0 is a threshold voltage of the tran­ sistor when no data has been written thereinto, viz., no carriers have been injected into the transistor. The current I₁₇ flowing into dummy cell 17 can be expressed by I₁₇ α Vc - V TH0 . The state of the memory cell, i.e., a data-stored state or a non-data-stored state, is detected when I₁₁ = I₁₇. At this time, the following relation holds Vcc - (V TH0 + ΔV TH ) = Vc - V TH0 ΔV TH = Vc - Vcc. As can be seen from the above, when fixed potential Vc is applied to the gate of dummy cell 17, if power voltage Vcc is changed, the level of the data stored in transistor 11 changes. By detecting the level of power voltage Vcc at this time, a shift ΔV TH in the threshold voltage V TH of transistor (memory cell) 11 can be deter­ mined. In the prior art shown in Fig. 4, the internal test circuits of the sense amplifier of Figs. 1 and 3 are combined. Either of these test circuits is selected by control signals A and externally applied. Control signal A goes high (Vcc level) in a read-out mode, and goes low when the internal test circuit is used, viz., in a monitor mode. Therefore, when in the read-out mode, MOS transistors 21 and 18₁ are in an "on" state, and MOS transistor 18₂ is in an "off" state. Under these conditions, the data read out from dummy cell 17₁ is subjected to comparison by differential amplifier 15. At this time, loads 19₁ and 19₂ operate to provide in­ termediate potential V R . When shift ΔV TH of threshold voltage V TH of the memory cell is monitored, control signal A goes low, and transistor 18₂ is in the "on" state, while transistors 21 and 18₁ are in the "off" state. Under these conditions, the data read out from dummy cell 17₂ is compared with the data from transistor (memory cell) 11, by means of differential amplifier 15. At this time, only load 19₂ operates. In the device of the type in which high potential is applied to the memory cell (such as an EPROM), in the write mode, the MOS transistor to which high poten­ tial Vpp is applied, in the write mode, is designed to have a different structure from the MOS transistor to which normal power voltage Vcc is applied, in the same mode. The high voltage applied to the transistor is such that, in order to withstand the high potential applied thereto, a long channel length or a lightly doped drain (LDD) is employed, so as to increase the breakdown voltage at the surface junction. In the case of the power voltage applied to the transistor, in the course of normal operation, it rarely occurs that an especially high voltage is applied thereto. For this reason, this transistor is designed to have a short channel length. This feature enables transistor to operate at high speed. With the high packaging density of recent semicon­ ductor devices, the channel length and the junction breakdown voltage of the power voltage applied to the MOS transistor contained in the peripheral circuit of the sense amplifier are respectively shorter and de­ graded considerably. With the progress made in the microfabrication of these devices, the level of power voltage Vcc applicable to the devices has also decreas­ ed. For example, the applicable power voltage Vcc has decreased from 10V to 8V. In the circuit of Fig. 3, the shift ΔV TH in the threshold voltage V TH of the memory cell is related to power voltage Vcc and the constant voltage Vc from constant voltage generator 20 by ΔV TH = Vcc - Vc, as described above. This relation­ ship indicates that if the applicable power voltage Vcc drops, the shift ΔV TH which can be monitored is also decreased. In the circuit of Fig. 3, the fixed output potential Vc of constant voltage generator 20 is used. In other words, the output potential Vc as the fixed potential is generated within the chip. This makes it impossible to externally determine an exact value of the shift value ΔV TH of the selected memory. Accordingly, an object of this invention is to pro­ vide a sense amplifier in a semiconductor memory device with an internal test circuit, which can precisely moni­ tor a shift in the threshold voltage of each memory cell, and even a large shift in the threshold voltage. To achieve the above object, a sense amplifier of a semiconductor memory device is provided, comprising a first floating gate transistor operating as a memory cell, whose control gate is connected to a word line; a first MOS transistor operating as a transfer gate, for selecting the first floating gate transistor, the gate of the first MOS transistor being connected to a column-­ select line; a first load, connected to the first MOS transistor; a second floating gate transistor operating as a dummy cell, whose control gate is connected to a first power terminal; a second MOS transistor operating as a transistor gate, for selecting the second floating gate transistor, the gate of the second MOS transistor being selectively connected to a first power terminal or a second power terminal for applying a high potential; a second load, connected to the second MOS transistor; and a differential amplifier, whose first input terminal is connected to the connection point of the first load and the first MOS transfer, and whose second input terminal is connected the connection point of the second load and the second MOS transistor. According to the present invention, in the read-out mode, the word line and the column-select line are supplied with a signal corresponding to the potential at the first power terminal. The second MOS transistor is connected, at its gate, to first power terminal. In the write mode, the word line and the column-select line are supplied with a signal corresponding to the potential at the second power terminal. The second MOS transistor is connected, at its gate, to the second power terminal. In the test mode, the word line, the column-select line, and the gate of the second MOS tran­ sistor are connected to the second power terminal. By externally applying a voltage to the second power ter­ minal, a shift in the threshold voltage of the first floating gate transistor is monitored. According to the present invention, in the write mode, a high potential is applied to the word line and the column-select line. When the internal test circuit is used, that is, when the shift in the threshold volt­ age of the first floating gate transistor is monitored, the first floating gate transistor and the first MOS transistor can be connected, at their gates, to the second power terminal of the high potential. At this time, the potential applied from the second power ter­ minal is gradually increased from low to high. When it reaches a predetermined level, and the data is changed from "0" (data-stored state) to "1" (non-data-stored state), the potential at that time is measured, and the shift in the threshold voltage of the memory cell can thus be determined. Since a high potential must be applied to the word line and the column-select line, the MOS transistors constituting the row and column decoders are structured so as to be able to withstand high voltages. This feature allows a high potential to be applied to the first MOS transistor, even when the internal test cir­ cuit is used. It also enables the shift V TH to be moni­ tored throughout a wider range. This invention can be more fully understood from the following detailed description when taken in con­ junction with the accompanying drawings, in which: Fig. 1 shows a circuit diagram of a prior art sense amplifier; Fig. 2 shows a graph illustrating a relationship between a shift V TH of the threshold voltage of the memory cell in the sense amplifier of Fig. 1, and power voltage Vcc; Fig. 3 shows a circuit diagram of another prior art sense amplifier using a constant voltage generator as a reference voltage generator; Fig. 4 shows a circuit diagram of a further prior art sense amplifier, in which the reference voltage generators shown in the circuits of Figs. 1 and 3 are combined; Fig. 5 shows a circuit diagram of a sense amplifier of a semiconductor memory device according to an embodi­ ment of the present invention; Figs. 6A and 6B show circuit diagrams of circuits for applying power voltage Vcc and high potential Vpp to the memory cell and the MOS transistor of the sense amplifier of Fig. 5; and Fig. 6C shows a circuit diagram of a modification of the circuit of Fig. 6B. An embodiment of the present invention will now be described, with reference to the accompanying drawings. In Fig. 5, the control gate of floating gate transistor 22, operating as a memory cell, is connected to word line WL. One end of floating gate transistor 22 is connected to earth point Vss. The other end of transis­ tor 22 is connected to the first end of MOS transistor 23 which operates as a transfer gate. The gate of MOS transistor 23 is connected to column-select line BL. The second end of MOS transistor 23 is connected to load 24. The connection point of load 24 and MOS transistor 23 is connected to the first input terminal of differen­ tial amplifier 26 via sense line 25. The second input terminal of differential amplifier 26 is connected to the output terminal of reference potential generator 27 as an internal test circuit. Reference potential gen­ erator 27 comprises load 28, MOS transistor 30, MOS transistor 31, and floating gate transistor 32. Load 28 is composed of load elements 28A and 28B which are connected to the second input terminal of differential amplifier 26. MOS transistor 30 performs switching operation when it is supplied with control signal , and decides whether or not load element 28A is connected to the input terminal of differential amplifier 26. MOS transistor 31 is applied at the gate with power voltage Vcc (in the read-out mode) or high voltage Vpp (in the write mode and when the internal test circuit is used), and operates as a transfer gate. Floating gate tran­ sistor 32 is applied at the gate with power voltage Vcc. Floating gate transistor 32 operates as a dummy cell. Column select line BL and word line WL are supplied with a signal of the Vcc system in the read-out mode, and with a signal of the Vpp system in the write mode or when the internal test circuit is used. Load 24 and load element 28 have the same electrical character­ istics. Reference numeral 46 designates Vpp level voltage generator. When the internal test circuit is used, that is, the shift amount of threshold voltage of floating gate transistor 22 is monitored, Vpp level voltage generator 26 applies floating gate transistor 22 and MOS transistor 23 with the potential of a level that corresponds to high voltage Vpp. In this case, applica­ tion of the voltage is made by gradually increasing that voltage. The operation will now be given. When the internal test circuit is used, control signal is "H" in level, and MOS transistor 30 is turned off. Since load 24 and load element 28B have the same electrical character­ istics, the sense amplifier has a circuit arrangement which is symmetrical arrayed with respect to both the input terminals of differential amplifier 26. There­ fore, current I₂₂ flowing through floating gate tran­ sistor (memory cell) when the internal test circuit is used, is I₂₂ α Vpps - V TH22 = Vpps (V TH0 + ΔV TH ) where Vpps is a voltage applied from Vpp level voltage generator 46, V TH22 a threshold voltage of transistor 22 when data is written into transistor 22 as a memory cell, and V TH0 a threshold voltage of transistor 22 when no data is written into transistor 22. Current I₃₂ flowing through dummy cell 32 is I₃₂ α Vcc - V TH22 = Vcc - V TH0 . As described above, when I₂₂ = I₃₂, the potential at the connection point of load 24 and MOS transistor 23, and reference potential V R of reference potential generator 27 are equal to each other with respect to differential amplifier 26. At this time, the following relation holds. Vpps - (V TH0 + ΔV TH ) = Vcc - V TH0 The potential applied to floating gate transistor 22 and MOS transistor 23 from Vpp level voltage genera­ tor 46 is gradually increased in level, and when the data of transistor 22 is changed, viz., when the logical state of the output signal of differential amplifier 26 is changed, potential Vpps is read. At this time, one can read the shift amount (write amount) ΔV TH , accura­ tely. Figs. 6A and 6B show a configuration of a circuit for selectively applying power voltage Vcc and high voltage Vpp to floating gate transistor 32 (memory cell) and MOS transistor 31 in the sensor amplifier of Fig. 5. Fig. 6A shows a circuit for selecting power voltage Vcc and high voltage Vpp. Control signals and A are applied to AND gate 33. In the write mode, control signal PGM goes high. When the internal test circuit is used, control signal A goes low. The output signal of AND gate 33 is supplied to inverter 34. Inverter 34 inverts the input signal of the Vcc system and outputs its inverted signal of the Vpp system. The signal at the output terminal of inverter 34 is supplied to the gate of MOS transistor 35, which is coupled at the first terminal with MOS transistor 35. The signal of the out­ put terminal of AND gate 33 is supplied to the gate of MOS transistor 36, which is coupled at the first ter­ minal of MOS transistor 36. At the connection point of the second terminals of MOS transistors 35 and 36, power voltage 35 or high voltage Vpp appears, which depends on control signals and A. The select output is suppli­ ed to terminals 37 and 38 of row decoder (column deco­ der) shown in Fig. 6B. The row decoder comprises NAND gate 39, MOS transistor 40, depletion type MOS transis­ tor 41, and CMOS inverter 44. NAND gate 39 is supplied with address signal Add. MOS transistor 40 is supplied at the first end with the output signal of NAND gate 39, and is made conductive by power voltage Vcc. Depletion type MOS transistor 41 is connected to the second ter­ minal of MOS transistor 40 and to terminal 37. CMOS converter 44 is made up of MOS transistors 42 and 43 connected in series between earth point Vss and terminal 38. The input terminal of CMOS converter 44 is connect­ ed to the second end of MOS transistor 40. The output signal of CMOS inverter 44 is supplied to word line WL. With such an arrangement, in the write mode, word line WL and column select line BL are applied with high voltage Vpp. In the read-out mode, these lines are applied with power voltage Vcc. When the internal test circuit is used, the gate of MOS transistor 31 is connected to high voltage Vpp. Vpp level voltage generator 46 applies a potential corresponding to high voltage Vpp to floating gate transistor 22 and MOS tran­ sistor 23. At this time, the potential applied by Vpp level potential generator 46 is gradually increased. When the potential reaches a predetermined level, and the data stored in transistor 22 is changed from "0" data of data storage state to "1" data of non-data storage state, if measuring the potential applied from Vpp level voltage generator 46, one can know a shift of the threshold voltage of the memory cell by using the equation Vpps - Vcc = ΔV TH . In the row decoder (column decoder) shown in Fig. 6B, depletion type MOS transistor 41 is used. As an alternative, enhancement type MOS transistor 45 may be used. In this case, as shown in Fig. 6C, enhancement type MOS transistor 45 is connect­ ed between terminal 37 and MOS transistor 40. MOS transistor 45 is controlled by CMOS inverter 44. To supplement the description of the specification of the present invention, "Reprinted from IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 1, pages 422-427, February 1985" "Fast Programmable 256K Read Only Memory with One-chip Test Circuits" will be incorporated.

Claims: 1. A sense amplifier for a semiconductor memory device, characterized by a first floating gate transistor (22), operating as a memory cell, whose control gate is connected to a word line; a first MOS transistor (23), operating as a trans­ fer gate for selecting said first floating gate tran­ sistor (22), the gate of said first MOS transistor (23) being connected to a column-select line; a first load (24), connected to the first MOS tran­ sistor (23); a second floating gate transistor (31), operating as a dummy cell, whose control gate is connected to a first power terminal (Vcc); a second MOS transistor (31), operating as a transfer gate for selecting said second floating gate transistor (32), the gate of said second MOS transistor (31) being connected to a second power terminal (Vpp), for supplying a high potential which is higher than the power voltage from said first power terminal (Vcc); a second load (28), connected to said second MOS transistor (31); and potential-difference detecting means (20), whose first input terminal is connected to the connection point of said first load (24) and said first MOS tran­ sistor (27), and whose second input terminal is con­ nected to the connection point of the second load (28) and the second MOS transistor (31). 2. A sense amplifier for a semiconductor memory device according to claim 1, further characterized by means (39, 40, 41, 44) for applying, in a data-­ write mode, the high potential from said second power terminal (Vpp) to the gate of said second MOS transistor (31), and for supplying a signal corresponding to a potential at the second power terminal (Vpp), to the gates of said first MOS transistor (23) and said first floating gate transistor (22), via the word line and the column-select line. 3. A sense amplifier for a semiconductor memory device according to claim 1, characterized in that the potential at the connection point of said second load (28) and said second MOS transistor (32) is a constant potential. 4. A sense amplifier for a semiconductor memory device, characterized by a first floating gate transistor operating (22) as a memory cell, whose control gate is connected to the word line, and to which is applied a potential corre­ sponding to that at a second power terminal (Vpp), for supplying a potential higher than the power voltage supplied from a first power terminal (Vcc), the control gate of said first floating gate transistor being con­ nected to the word line; a first load (24), connected to said first MOS transistor; a second floating gate transistor (31), operating as a dummy cell, whose control gate is connected to said first power terminal (Vcc); a second MOS transistor (31), operating as a trans­ fer gate for selecting said second floating gate tran­ sistor (32), the gate of said second MOS transistor (32) being connected to the second power terminal (Vpp); a second load (28), connected to said second MOS transistor (31); and a differential amplifier (26) whose first input terminal is connected to the connection point of said first load (24) and said first MOS transistor (22), and whose second input terminal is connected to the connec­ tion point of said second load (28) and second MOS tran­ sistor (32). 5. A sense amplifier for a semiconductor memory device according to claim 4, characterized in that, when a shift in the threshold voltage of said first floating gate transistor (22) is monitored, the potential corre­ sponding to that at said second power terminal (Vpp) is gradually increased, and, upon a change in the level of the data stored in said first floating gate transistor (22), said potential is detected by said differential amplifier (27). 6. A sense amplifier for a semiconductor memory device according to claim 4, further characterized by means (46) for gradually increasing the potential corresponding to that at said second power terminal (Vpp). 7. A sense amplifier for a semiconductor memory device according to claim 4, characterized in that said second load (28) includes first and second load elements (28A and 28B), said first load element (28A) being turned off when the shift in the threshold voltage of said first floating transistor (22) is monitored, and said second load element (28B) being connected to said second MOS transistor (32), in parallel with said first load element (28A). 8. A sense amplifier for a semiconductor memory device according to claim 7, characterized in that said first load element (28A) is supplied with the power voltage via a third MOS transistor (30) which is turned off when the amount of shift in the threshold voltage of said first floating gate transistor (22) is monitored. 9. A sense amplifier for a semiconductor memory device according to claim 7, characterized in that said first load (24) and said second load element (28B) of said second load have the same electrical character­ istics. 10. A sense amplifier for a semiconductor memory device according to claim 4, characterized in that the potential at the connection point of said second load (28) and the second MOS transistor (32) is a constant potential.

Inventors: ATSUMI, SHIGERU C/O PATENT DIVISION, KAMEI, TAKASHI C/O PATENT DIVISION, OTSUKA, NOBUAKI C/O PATENT DIVISION, TANAKA, SUMIO C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-COMPUTER ENGINEERING CORPORATION
Application year: 1987
Main classification: G11C7
IPC codes: G11C16, G11C7, G11C17, G11C29