Step-cut insulated gate static induction transistors and method of manufacturing the same

Abstract: A step-cut insulated gate static induction transistor can accurately make a channel length and a gate length and is excellent as a high speed transistor but is greatly: affected by a deviation in mask alignment in the manufacturing process. This invention utilizes the fact that a gate portion formed in a previous processes is used as a mask in a post portion to thereby self-adjustably form the post portion, thus eliminating the influence of the deveation in mask alignment. In addition, a construction has been invented in which a current flowing through a protion apart from a gate between a drain and a source can be restricted. The aforesaid manufacturing method is also used for this improved construction.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a step-cut insulated gate static induction transistor capable of carrying out high-speed switching, a high-speed and low power step-cut insulated gate static induction transistor integrated circuit, and method of manufacturing the same. Description of the Prior Art Insulated gate transistors for high frequency amplification and integrated circuits have been heretofore used but have a disadvantage that the drivability is small. For example, a complementary metal-oxide-semiconductor transistor integrated circuit (C-MOS) has been known as an application of an insulated gate transistor. However, this circuit (C-MOS) operates at low dissipation power but operates at low switching speed, because of small drivability To overcome such disadvantages as noted above, one of the present inventors has previously proposed an insulated gate static induction transistor (for example, see Japanese Patent Application No. 1756/1977) and a step-cut insulated gate static induction transistor (for example, see Japanese Patent Application No. 13,707/1977). The insulated gate static induction transistor is designed so that the depletion layer spread from the drain region reaches the source region. So, a current flowing from source to drain is controlled not only by the gate voltage but also by the drain voltage and the current flows into not only an interface between a semiconductor and an insulator but a substrate. Therefore, the insulated gate static induction transistor has non-saturating current-voltage characteristics and has large drivability. Particularly, the step-cut insulated gate static induction transistor has a channel formed depthwise of a semiconductor substrate, thus providing a good controllability for a channel length and a gate length, and said transistor is well suited for shortening a channel to improve its drivability. Thus, the step-cut insulated gate static induction transistor is able to increase its drivability and decrease a parastic capacitance and therefore exhibits an excellent performance as a high speed switching transistor and a high-speed and low power integrated circuit. Prior art will be described hereinafter with reference to FIG.1. FIG.1(a) shows an example of a construction in section of a conventional step-cut insulated gate static induction transistor. In FIG. 1(a) 10 designates a semiconductor substrate, a main surface of which is partly provided with a U-shaped groove. A drain region 11, a channel region 13 and a source region 12 are provided in said order depthwise from the main surface along the side wall of the U-shaped groove, and a drain electrode 11′ is connected to the drain region 11. A source electrode, which is not shown, is provided vertically as viewed from the paper surface. The drain region 11 and the source region 12 have the impurity concentration of the order 10¹⁸of to 10²¹ cm⁻³, the conductivity type of which is shown as P type but N type can be used. In addition, the region 11 can be used as a source region and the region 12 used as a drain region. The channel region 13 has the impurity concentration of the order of 10¹² to 10¹⁶ cm⁻³, the conductivity type of which can be of the same as or opposite to that of the drain region 11 and the source region 12, and a multi-layered construction can be also employed. The impurity concentration as well as the depth of the aforesaid U-shaped groove are determined so that a depletion layer spread from the drain region 11 reaches the source region 12 at least a part of the operating condition thereof. A gate insulator 14 such as an oxide film is provided in contact with the channel region 13 and has a thickness of the order of 100 to 1,000 Å (10 Å = 1nm). On the side opposite the gate insulator 14 is provided a gate electrode 14′ formed of metal, polycrystalline silicon or the like. 15 designates a field oxide film. Since a conventional step-cut insulated gate static conduction transistor as shown in FIG. 1(a) is formed depthwise with respect to a semiconductor substrate. dimensions of a transistor can be controlled with precision of deposition and etching providing a good controllability for the channel length and gate length and being well suited for shortening the channel to improve drivability. Accordingly, such a transistor as noted above has a large drivability and can decrease a parastic capactance and therefore exhibits an excellent performance as a high speed switching transistor and a high speed low power integrated circuit. One example of a well known fabrication process for manufacturing the aforesaid step-cut insulated gate static conduction transistor will be described with reference to FIG. 2. FIG. 2(a) An epitaxial layer 22 constituting a channel is grown on a semiconductor substrate 21 used as a drain, a channel impurity is introduced by thermal diffusion or ion implantation and thereafter a U-shaped groove is formed in a part of a main surface of the semiconductor substrate by anisotropic plasma etching or the like. FIG. 2(b) A conventional photolithography and a selective oxidation are used to form a field oxid film 23 and windows, which are provided in a part of a main surface of a semiconductor substrate and are including at a part of the side wall of a U-shaped groove to form a gate oxide film 24. FIG. 2(c) A polycrystalline silicon 25 constituting a gate electrode is deposited, which is subjected to etching by a conventional photolithography so as to have it remained on a gate oxide film of the side wall of a U-shaped groove, and thereafter a source region 26 is formed by thermal diffusion or ion implantation. FIG. 2(d) A passivation film 27 is deposited and contact hole is opened to form a drain electrode 21′, a gate electrode 25′ and a source electrode 26′. The impurity concentration of the aforesaid drain region 21 and source region 26 is of the order of 10¹⁸ to 10²¹ cm⁻³. It is noted of course that the conductive type can be of either P type or N type, and the 21 can be used as a source region and the 26 as a drain region conversely to the former. The impurity concentration of the channel region 22 is of the order of 10¹² to 10¹⁶ cm⁻³, and the conductive type thereof can be the same as or opposite to that of the aforementioned drain region and source region, a multi-layered construction being possibly used. However, at least in a part of the operating condition a depletion layer spread from the drain region must reach the source region, and to meet this requirement, the impurity concentration thereof as well as the depth of the U-shaped groove are determined. The thickness of the gate oxide film 24 is set to be of the order of 100 to 1,000 Å, and the gate electrode is ordinarily formed of polycrystalline silicon or the like, the thickness being of the order of 1000 Å to 1 µm. In the above-described conventional process of manufacturing an step-cut insulated gate static induction transistor, a conventional photolithography is used and therefore a margin for mask alignment is required. Consequently, this margin make it difficult to form the gate electrode 25 only on the side wall of the U-shaped groove. For example, FIG. 3 shows an example of a plan construction of a conventional step-cut insulated gate static induction transistor, which corresponds to the fabrication process shown in FIG. 2. In FIG. 3. 31 designates a side wall of a U-shaped groove, 32 a window provided by selective oxidation, 33 a gate electrode of a polycrystalline silicon, 34 and 35 a drain contact hole and a gate contact hole, respectively, and 36 and 37 a drain electrode and a gate electrode, respectively. In FIG. 3, the section of B-B′ is shown in FIG. 2(d). ℓb and ℓc denote mask alignment margins with respect to the photolithography of the FIG. 2 processes (b) and (c), the margin being normally designed approximately 0.1 to 2 µm. An example of the drain current-drain voltage characteristics of a transistor different in mask alignment margin ℓc is shown in FIGS. 4 (a) to (c). In this case, it is designed so that the channel length is approximately 0.5 µm; the dosage of the channel impurity is approximately 1.5 x 10¹³ cm⁻²; and the thickness of the gate oxide film is approximately 250 Å, the mask alignment margin ℓc being 0 um in the (a), and 1 µm and 2 µm in the (b) and (c), respectively. In the case of the (a), there exhibits the unsaturated type current-voltage characteristic, the drivability is large and the characteristic of the step-cut insulated gate static induction transistor is conspicuous but there gives rise to a disadvantage that yield is poor. On the other hand, in the case of the (b) and (c), since a portion corresponding to the mask alignment margin works similarly to a planar type transistor, the effective channel length becomes extended, deteriorating the drivability. In the conventional step-cut insulated gate static induction transistor, the drain region 11 is opposed to the source region 12 with the channel region 13 sandwiched therebetween, and therefore if the channel is shortenned to attain higher speed, a current flows between drain and source even at a point away from the gate surface by being affected by the drain field. This current component cannot be controlled by a gate voltage. This results in disadvantages that a leak current is large at the off state, etc. For example, FIG. 1 (b) shows an example of the drain current-drain voltage characteristics of a conventional step-cut insulated gate static induction transistor so designed that the channel length is approximately 0.5 µm, the dosage of channel impurity is approximately 2 x 10¹³ cm⁻², and the thickness of the gate oxide film is approximately 250 Å. Even when the gate voltage is 0 Volt, the drain current flows as the drain voltage increases. It is noted of course that such a current flowing on the bulk side can be suppressed to some extent by selecting the impurity concentration of the channel region 3. FIG. 1 (c) shows an example of the drain current - drain voltage characteristics of a conventional step-cut insulated gate static induction transistor so designed that the channel length is approximately 0.5 µm, the dosage of channel impurity is approximately 6 x 10¹³ cm⁻², and the thickness of the gate oxide film is approximately 250 Å. A leak current at the off state was improved but drivability is sacrificed to some extent because the static induction effect on the drain side became hard to extend to the source side, and the threshold voltage is increased. An object of the present invention is to provide a method of manufacturing a step-cut insulated gate static induction transistor wherein the above described problem of mask alignment in formation of the gate oxide film and the gate electrode can be avoided. According to the present invention there is provided a method of manufacturing a step-cut insulated gate static induction transistor, characterized by the following sequence of steps: anisotropic etching of a main surface of a semiconductor substrate to form a U-shaped groove; deposition of mask material for selective oxidation on said main surface; anisotropic etching of said mask material to leave a first portion of said mask material on a side wall of said groove in a self-aligned manner and to leave a second portion of said mask material on an area of said main surface intended for eventual formation of a source or drain region; selective oxidation to form a field oxide film over said main surface and removal of said mask material portions to create a window at said side wall and at said area; formation of a thin gate oxide film in said window on said side wall; deposition of material to form a gate electrode and anisotropic etching to leave said material over said thin gate oxide film; and formation of a source or drain region. Attention is drawn to applications no. 92101661.4 divided herefrom. The document GB-A-2103879 relates to an MOS type of field effect transistor and an object thereof is to solve a problem arising in the positional adjustment of a deposition source which occurs when a gate electrode is formed on the side wall of a mesa by oblique deposition. In order to meet that object there is described a thick oxide film formed over the entire surface of a semiconductor substrate. A mesa is formed and an undercut is made therein resulting in an overhang of the oxide film which is in turn utilized to form a gate electrode on the side wall. An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows one example of a conventional step-cut insulated gate static induction transistor, Figure 1(a) showing a sectional structural view, FIG. 1 (b) showing one example of the drain current - drain voltage characteristics, and FIG. 1 (c) showing another example of the drain current-drain voltage characteristics; FIG. 2 is an explanatory view of the fabrication process showing one example of a conventional method of manufacturing an step-cut insulated gate static induction transistor; FIG. 3 is a plan view showing a plane construction of a conventional step-cut insulated gate static induction transistor; FIG. 4 is a characteristic view showing one example of the drain current - drain voltage characteristics caused by a difference of mask alignment margin of a conventional step-cut insulated gate static induction transistor; FIG. 5 is an explanatory view of the fabrication process showing one embodiment of a method of manufacturing a step-cut insulated gate static induction transistor according to this invention; FIG. 6 is a detailed explanatory view of the process of forming a mask material; FIG. 7 is a plan view showing a plane construction of a step-cut insulated gate static induction transistor according to the manufacturing method of this invention; FIG. 8 is a sectional view showing one embodiment of an integrated circuit of a step-cut insulated gate static induction transistor according to the manufacturing method of this invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 5 shows one embodiment of the fabrication process, according to this invention, step-cut insulated gate static induction transistor shown in FIG. 1. FIG. 5 (a) An epitaxial layer 52 constituting a channel is grown on a semiconductor substrate 51 used as a drain, a channel impurity is introduced therein by thermal diffusion or ion implantation and thereafter a U-shaped groove is formed in a main surface of a semiconductor substrate by anisotropic plasma etching or the like. FIG. 5 (b) A mask material 53 for selective oxidation is deposited, and conventional photolithography and anisotropic plasma etching are combined to leave mask material on a region as a source of the main surface of a semiconductor substrate and on a region as a gate of the side wall of a U-shaped groove. FIG. 5 (c) A selective oxidation is used to form a field oxide film 55, and at the same time a window is formed in a region as a source of the main surface of a semiconductor substrate and in a region as a gate of the side wall of a U-shaped groove to form a gate oxide film 54. FIG. 5 (d) A polycrystalline silicon 56 constituting a gate electrode is deposited and then subjected to etching so as to be left on a gate oxide film 54 of the side wall of a U-shaped groove by conventional photolithography after which a source region 57 is formed by thermal diffusion or ion implantation. FIG. 5 (e) A passivation film 58 is deposited and a contact hole is made to form a drain electrode 51′, a gate electrode 56′ and a source electrode 57′. In this case, the impurity concentration of a drain region 51 and a source region 57 is of the order of 10¹⁸ to 10²¹ cm⁻³. Of course, the conductivity type can be either P type or N type, and the 51 can be used as a source region and the 57 as a drain region. The impurity concentration of the channel region 52 is of the order of 10¹² to 10¹⁶cm⁻³, and the conductivity type thereof can be the same as or opposite to that of said drain region 51 and source region 57, and a multi-layer construction can be employed. However, at least a part of the operating condition the impurity concentration as well as the depth of the U-shaped groove are determined so that a depletion layer spread from the drain region reaches the source region. The thickness of the gate oxide film 54 is set to approximately 100 to 1,000 Å. According to this fabrication process, a gate oxide film which most influences upon the characteristic of the device can be self-adjustably formed only on the side wall of the U-shaped groove, and therefore, a step-cut insulated gate static induction transistor can be obtained which has excellent in reproducibility and reliability and has an drain current - drain voltage characteristic such as in FIG. 4 (a). FIG. 6 further shows in detail the step of forming the mask material 53 shown in FIG. 5 (b). FIG. 6 (a) An epitaxial layer 62 constituting a channel is grown on a semiconductor substrate 61 used as a drain, a channel impurity is introduced therein by thermal diffusion or ion implantation and thereafter a U-shaped groove is formed in a part of the surface of a semiconductor by anisotropic plasma etching or the like. FIG. 6 (b) A polycrystalline silicon 64 constituting a mask material for etching of silicon nitride film 63 and a silicon nitride film 63 constituting a mask material for selective oxidation is continuously deposited by CVD method or the like. FIG. 6 (c) Conventional photolithography and anisotropic plasma etching are combined to thereby leave a polycrystalline silicon 64 on a region as a source of the main surface of a semiconductor substrate and on a region as a gate of the side wall of the U-shaped groove. The anisotropic plasma etching of the polycrystalline silicon 64 can be made under gas pressure of approximately 0.1 Torr (1 torr = 133.3 Pa) using PCl₃, for example. FIG. 6 (d) The polycrystalline silicon 64 is used as a mask material to apply etching to a silicon nitride film 63 constituting a mask material for selective oxidation. By the process as described above, the silicon nitride film which is the mask material for selective oxidation can be self-adjustably formed only on the side wall of the U-shaped groove. Of course, the silicon nitride film can be directly subjected to anisotropic etching but according to this method, etching of a silicon nitride film can be effected by wet etching such as boiled phosphoric acid, etc., without damage. One example of a plane construction of an step-cut insulated gate static induction transistor corresponding to the fabrication process shown in FIGS. 5 and 6 is shown in FIG. 7. In FIG. 7, 71 designates a side wall of a U-shaped groove, 72 a window caused by selective oxidation constituting an active area, 73 a gate electrode of a polycrystalline silicon, 74 and 75 a drain contact hole and a gate contact hole, respectively, and 76 and 77 a drain electrode and a gate electrode, respectively. In FIG. 7, the section taken by A-A′ is shown in FIG. 5 (e). ℓd denotes the mask alignment margin with respect to the photolithography in the step (d) shown in FIG. 5, the margin being normally set to approximately 0.1 µm to 2 µm. However, this part is a thick field oxide film, and so even if it is superposed by the gate electrode, no significant influence is extended to device characteristic. One example of a sectional construction of a inverter gate in the case where the step-cut insulated gate static induction transistor is applied to a complementary metal-oxide-semiconductor transistor integrated circuit is shown in FIG. 8. In FIG. 8, 80 designates a semiconductor substrate, and the main surface thereof is partly formed with a U-shaped groove. 81 designates an N⁺ drain region, 82 a P⁺ drain region, 83 an N⁺ source region, and 84 a P⁺ source region, these regions having the impurity concentration of approximately 10¹⁸ to 10²¹ cm⁻³. 85 designates a P channel region and 86 an N channel region, these regions having the impurity concentration of approximately 10¹² to 10¹⁶ cm⁻³. At least in a part of the operating condition the impurity concentration as well as the depth of the U-shaped groove are determined so that a depletion layer spread from the drain region reaches the source region. 87 designates a gate insulator such as an oxide film which has a thickness of approximately 100 to 1,000 Å, 87′ a gate electrode, and 88 a field oxide film. 89 designates a P well for separating a P channel transistor from an N channel transistor. The gate electrode 87′ comprises a logical input while the drain electrodes 81′ and 82′ comprise a logical output, a power-supplied voltage is applied to source electrodes connected to the source regions 83 and 84, respectively. When the logical input is in a high level, the N channel transistor assumes an on state while the P channel transistor assumes an off state, and therefore the logical output is a low level. The same is true for the reversal case. Even such an integrated circuit can be manufactured nearly similarly to the fabrication process shown in FIG. 5 except the construction of the substrate, thus providing a complementary metal-oxide-semiconductor transistor integrated circuit which has a good reproducibility and reliability and has high speed and low power. For example, a propagation delay time of 430 psec is obtained at a dissipation power of 10 mW, by a ring oscillator of the complementary metal-oxide-semiconductor transistor integrated circuit shown in FIG. 8. As described above, the present invention improves the disadvantages encountered in the conventional fabrication process of step-cut insulated gate static induction transistor, whereby a gate oxide film and a gate electrode can be self-adjustably formed only on the side wall of the U-shaped groove. Accordingly, the step-cut insulated gate static induction transistor which can effect high speed switching and the high speed and low power step-cut insulated gate static induction transistor integrated circuit can be manufactured with good reproducibility and reliability, thus providing a great industrial value.

Claims: A method of manufacturing a step-cut insulated gate static induction transistor, comprising the following sequence of steps: anisotropic etching of a main surface of a semiconductor substrate (51) to form a U-shaped groove; deposition of mask material (53) for selective oxidation on said main surface; anisotropic etching of said mask material (53) to leave a first portion of said mask material on a side wall of said groove in a self-aligned manner and to leave a second portion of said mask material on an area of said main surface intended for eventual formation of a source or drain region; selective oxidation to form a field oxide film (55) over said main surface and removal of said mask material portions to create a window (72) at said side wall and at said area; formation of a thin gate oxide film (54) in said window on said side wall; deposition of material to form a gate electrode (56) and anisotropic etching to leave said material over said thin gate oxide film (54); and formation of a source or drain region (57). A method according to claim 1 characterized in that: said deposition of mask material comprises deposition of a silicon nitride film (63); said anisotropic etching of said mask material includes deposition of a polycrystalline silicon film (64) on said silicon nitride film (63), anisotropic etching of said polycrystalline silicon to leave portions on said side wall and on said area, and removal of the unmasked remainder of said silicon nitride film using said polycrystalline silicon film portions as a mask. A method according to claim 1 or claim 2 characterized in that a plurality of said transistors are integrated and formed on said substrate by said method.

Inventors: NISHIZAWA JUNICHI, SUZUKI SOUBEI, TAKEDA NOBUO ARAMOTO, NISHIZAWA, JUNICHI, SUZUKI, SOUBEI, TAKEDA, NOBUO ARAMOTO-APARTMENT
Applicants: JAPAN RES DEV CORP, NISHIZAWA JUNICHI, SUZUKI SOUBEI, TAKEDA NOBUO, NISHIZAWA, JUNICHI, RESEARCH DEVELOPMENT CORPORATION OF JAPAN, SUZUKI, SOUBEI, TAKEDA, NOBUO
Application year: 1987
Main classification: H01L21
IPC codes: H01L21, H01L29