TIMEBASE GENERATOR WITH IMPROVED LINEARITY AND RECOVERY TIME

Abstract: A timebase generator includes a transistor switch performing a sweep gate function, alternately providing a current path for retrace and then disconnecting such current path to allow generation of a time base ramp. The bias current delivered to the switch is controlled to be at a high level for bringing about proper retrace, but at a low level at the beginning and ending of the time base sweep itself to prevent undesired transients and nonlinearity effects. The low current is maintained from the end of the retrace period until the start of the following retrace period. A baseline stabilizer loop comprises a transistor circuit for accurately predetermining the baseline reference wherein the emitter current of the transistor is controlled to a substantially constant value during operation for enhanced stability. The undesirable effect produced by inherent capacitance of a semiconductor device current source used for charging the timebase generator timing capacitor is neutralized by means of a matching semiconductor device interposed between the timebase generator output and an input electrode of the first mentioned semiconductor device.

Description: Background of the Invention The present invention relates to time base generator and the method of operating it and particularly to such generator which is adapted to provide a linear sweep with fast recovery. In a cathode ray oscilloscope or similar device, a varying signal can be displayed as a function of time by applying the signal to vertical deflection means of a cathode ray tube, while a linear sweep signal or time base signal is applied to the horizontal deflection means. Between "sweeps", the horizontal deflection means provides retrace back to the starting point at the left hand side of the cathode ray tube screen, the electron beam generally being blanked out during such retrace period. The horizontal deflection is then held at a stable starting position awaiting the occurrence of the next repetition of the input signal that is to be displayed. A suitable form of time base circuitry for operating the horizontal deflection means of the cathode ray tube involves a timing capacitor and means for supplying a substantially constant current to the capacitor whereby a linear ramp voltage is provided across the capacitor for application to the aforementioned horizontal deflection means. In a typical circuit, (see US 4,009,399) a current switch alternately connects a secondary current path to the timing capacitor for discharging the timing capacitor at the end of each sweep (to provide retrace) and further for establishing bias during baseline stabilization awaiting the beginning of the next sweep. At the beginning of the next sweep, the additional current path is interrupted whereby the timing capacitor is allowed to charge up once again in a linear manner. Large current requirements were imposed upon this secondary current path in order to bring about rapid retrace. Thus, the current from the capacitor during the retrace period may well be five to ten times as much as the current provided thereto during the linear sweep. Unfortunately, at the beginning of a following sweep after retrace, this fairly large current had to be interrupted, i.e. the switch had to be turned off, whereby undesirable transients appeared in the circuit as a consequence of the current interruption and the presence of parasitic inductances and capacitances in the circuit. The result tended to be a non-linear sweep signal especially for very high sweep speeds, as well as interference with the vertical channel signals of the oscilloscope. The above problem is aggravated when many selectable sweep speeds are desired, while using a comparatively small number of switchable timing capacitors. To obtain a wide range of sweep speeds with few capacitors, it is necessary to apply a large range of selectable currents to the timing capacitors. This inevitably means extremely high current during some retrace periods since fast recovery is required after a sweep is finished. The interruption of these high currents aggravated the problem of undesired transients. Furthermore, undesirable transients can also occur when the aforementioned current switch turns "on" for discharging the timing capacitor at the beginning of retrace. It would be desirable to eliminate the problems occurring both at the beginning and at the end of the time base sweep. A further problem with this kind of timebase generator is associated with the stability of circuitry for maintaining an accurate baseline value, or initial starting point, for the time base sweep signal. It would be desirable to establish a very stable initial baseline value. An additional problem present with the aforementioned type of timebase generator is associated with the current source utilized in charging the timing capacitor during the time base sweep. The current source generally involves a semiconductor device which itself exhibits an inherent capacitance, and the charging current for the latter capacitance subtracts from the current as would otherwise be supplied to the timing capacitor. It would be of advantage to remove this source of inaccuracy. Summary of the Invention In accordance with the present invention, a timebase generator includes a timing capacitor, means for providing a constant current to the timing capacitor for generating a time base sweep, and switching means for coupling a second current path to the timing capacitor in order to establish a retrace period. The switching means has a first or disconnected position during which the timing capacitor is allowed to charge up and provide a linear time base sweep, and a second switching position providing the aforementioned second current path for rapidly discharging the timing capacitor. In accordance with the present invention, an adjustable current source couples a first current through the switching means during the retrace period, and a lower current through the switching means after the retrace period, whereby only the lower value of current needs to be interrupted by the switching means at the beginning of the next time base sweep. Advantageously, the lower value of current is maintained through the next time base sweep, and until the next retrace period, thereby avoiding a pronounced switching transient not only at the beginning of the time base sweep, but also at the end thereof. In accordance with another feature of the present invention, a baseline stabilizing loop is operative in the period between the end of retrace and the start of the next time base sweep. This stabilizer circuit advantageously comprises a transistor having its emitter connected to the timing capacitor as well as to the switching means terminal coupled to the timing capacitor. An adjustable control loop holds the emitter current at a substantially constant value while the aforementioned adjustable current source supplies a current through the switching means substantially matching the selectable current from the constant current source that was used to charge the timing capacitor during the time base sweep. Consequently the stability of the circuit is enhanced. According to a further aspect of the present invention, the constant current source utilized for charging the timing capacitor during a time base sweep comprises a semiconductor device, while a second and matching semiconductor device is coupled between the time base sweep output and the first-mentioned semiconductor device to supply current in a reverse sense from the current drawn by the inherent capacitance of the first-mentioned semiconductor device. It is accordingly an object of the present invention to provide an improved timebase generator for providing a linear output with fast recovery time. It is another object of the present invention to provide an improved timebase generator which is less prone to the generation of high current switching transients than prior art generators. It is another object of the present invention to provide improved timebase generator current switching at the beginning and end of each time base sweep signal. Another object of the present invention is to provide an improved timebase generator having a stable control loop for holding a baseline voltage on the generator timing capacitor between time base sweeps. It is a further object of the present invention to provide an improved timebase generator wherein current drawn by the inherent capacitance of a semiconductor constant current source, utilized for charging a timing capacitor, is neutralized. The subject matter of the present invention is particularly pointed out and distinctly claimed in the concluding portion of this specification. However, both the organization and method of operation, together with further advantages and objects thereof, may best be understood by reference to the following description taken in connection with accompanying drawings wherein like reference characters refer to like elements. Drawings FIG. 1 is a schematic diagram of a timebase generator circuit in accordance with the present invention, FIG. 2 is a waveform chart illustrating operation of the FIG. 1 circuit, and FIG. 3 is a schematic diagram of a more detailed version of the timebase generator according to the present invention, illustrating additional features. Detailed Description Referring to the schematic diagram of FIG. 1 illustrating a timebase generator according to the present invention, such timebase generator includes a timing capacitor 10 to which current is delivered from a constant current source 12 for the purpose of generating a time base ramp across capacitor 10. The voltage across capacitor 10 is delivered via buffer amplifier 14 to the horizontal deflection circuitry of a cathode ray tube, herein schematically indicated at 16. It will be understood that a vertical input signal is coupled to the vertical deflection means of the cathode ray tube whereby a plot or trace of the vertical input signal, versus time, will be displayed, assuming the ramp signal is a substantially proportional function of time. The FIG. 1 circuit further includes a current switch comprising transistors Q₂ and Q₃ functioning as a sweep gate. According to the present invention, the commonly connected emitters of transistors Q₂ and Q₃ are coupled to an adjustable current source 18. The current switch delivers a "bias" current from source 18 via either the collector of transistor Q₂ or the collector of transistor Q₃, depending upon the state of the "gate" signals applied to the bases of the transistors. The positive-going gate signal applied to the base of transistor Q₃ (and the inverse thereof applied to the base of transistor Q₂) is generated in a conventional manner pursuant to a trigger signal or the like. During the presence of the gate signal, the current source 12 and timing capacitor 10 circuit is substantially disconnected from adjustable source 18 inasmuch as transistor Q₂ is cut off. At this time, constant current source 12 is allowed to charge timing capacitor 10 thereby providing the ramp function which is amplified in buffer amplifier 14 and delivered to the horizontal deflection circuitry of the cathode ray tube. This action is illustrated in the waveform chart of FIG. 2 (phase 1) where it is seen that during the presence of the gate the ramp runs up providing a linear sweep output. Although only one timing capacitor 10 and only one constant current source 12 are illustrated in FIG. 1, a typical oscilloscope instrument would provide a choice of currents and timing capacitances for generating sweeps of selectable speed. The end of the time base sweep ramp occurs when the gate signal concludes, usually pursuant to an end-of-sweep signal that turns off the gate when the ramp has risen to some predetermined value. The end-of-sweep circuitry is well known to those skilled in the art and will not be described herein. At the end of the time base sweep in the phase 1 period of FIG. 2, it is necessary to bring about rapid retrace so that the circuitry is ready for the next occurrence of the gate signal which may occur relatively soon after retrace and after the circuitry has returned to original conditions. At the conclusion of the aforementioned gate signal, transistor Q₂ is switched on while transistor Q₃ is switched off, thereby providing an additional or second current flow path from timing capacitor 10 through transistor Q₂ to adjustable current source 18. At this time appreciably more current flows from timing capacitor 10 through transistor Q₂ than flowed theretofore in timing capacitor 10 during the sweep. The "bias" current through source 18 overcomes the timing current from source 12, and the voltage across capacitor 10 falls rapidly during the retrace period as illustrated in phase 2 in FIG. 2. In addition to the rapidly falling ramp signal, the increase in I BIAS is illustrated (at 32) in FIG. 2. The return of the time base sweep ramp signal to its initial level, specified as the baseline value, is detected by baseline stabilizer amplifier 20 in FIG. 1. Amplifier 20 comprises a comparator receiving the ramp output from buffer amplifier 14 on its inverting input lead and receiving a base-line reference voltage on its non-inverting input lead. A stabilizing circuit according to the present invention further includes transistor Q₁ having its base driven from the output of amplifier 20 and having its emitter connected to the collector of transistor Q₂ whereby, when the retrace of the ramp as illustrated in phase 2 in FIG. 2 reaches the baseline reference, transistor Q₁ is caused to conduct and prevent further drop in the voltage across timing capacitor 10. A control loop, including amplifier 20, transistor Q₁, and buffer amplifier 14, maintains the voltage across timing capacitor 10 at substantially the baseline reference value. This baseline reference value forms an accurately predetermined starting point for the horizontal trace and is maintained during sweep phase 3. The baseline value is indicated by reference numeral 22 in FIG. 2. The I BIAS current continues to flow through transistor Q₂ until the end of sweep phase 3, whereupon the reoccurrence of the gate signal turns off transistor Q₂ and turns on transistor Q₃. As during the previous time base sweep, capacitor 10 is then permitted to charge from constant current source 12, and the I BIAS current is diverted via transistor Q₃ of the current switch to clamp transistor Q C . The collector of transistor Q₃ goes low, rapidly cutting off transistor Q₁. I BIAS , rather than comprising a relatively constant value, is instead controlled during the various phases of operation of the circuit so that it will be sufficiently large in sweep phase 2 for bringing about rapid retrace, but will then be reduced in value during at least the subsequent phase 3 in FIG. 2 whereby the current switch does not have to switch a large current from transistor Q₂ to transistor Q₃ at the beginning of each time base sweep. As a consequence, transient problems and non-linearities are substantially eliminated at the start of the next time base sweep, but the I BIAS current may be made relatively large during sweep phase 2 to bring about proper retrace. The current I BIAS is produced by adjustable current source 18 comprising transistor 24 having its collector connected in common to emitters of transistors Q₂ and Q₃, and having its emitter returned to a negative voltage via resistor 26. A junction between the base of transistor 24 and a resistor 28 returning the junction to a negative voltage source receives a current I in from the collector of a transistor Q S having its emitter connected to the collector of transistor Q₁ and having its base grounded. As a consequence, when transistor Q₁ is turned on as the retrace of the ramp signal drops to the baseline reference, the collector of transistor Q₁ drops, reducing the current through transistor Q S and causing transistor 24 to reduce the value of the I BIAS current. As will be seen from FIG. 2, I BIAS drops from a relatively high value, depicted by level 32 in FIG. 2 during the retrace period, to a relatively low level, depicted at 34 in FIG. 2, at the conclusion of the retrace period. In a particular circuit, the I BIAS current during phase 2 was approximately 35 ma. while the I BIAS current during phase 3 was on the order of 2 ma. Therefore, transistor Q₂ interrupts a much lower current when switching takes place pursuant to the gate signal at the start of the next time base sweep, and a clean ramp beginning is brought about. It will be seen the value of I BIAS , during the baseline stabilization period of phase 3, substantially equals the current from current source 12 plus current from transistor Q₁. According to another feature of the invention, the current in the emitter of transistor Q₁ is maintained at a substantially constant value during sweep phase 3 of circuit operation. The baseline stabilizer loop including transistor Q₁, buffer amplifier 14, and baseline stabilizer amplifier 20, is dependent on the output impedance of transistor Q₁ and that impedance varies with emitter current. It is of appreciable benefit for the emitter current of transistor Q₁ to be made stable whereby the circuit as a whole can work effectively at different timing currents. In the present embodiment, a further control loop comprises transistor Q S and adjustable current source 18, whereby the current through transistor Q₁ is maintained substantially constant while I BIAS is adjusted to equal the current through transistor Q₁ as well as whatever timing current is provided from current source 12 (different for various sweep speed settings of the instrument). Thus, as current through transistor Q₁ tends to increase, I BIAS tends to decrease, and vice versa. According to another feature of the present invention, the current I BIAS is maintained at its lower level until the beginning of retrace in phase 2 in FIG. 2. Transistor Q₁ receives its collector current from resistor 30, operating substantially as a current source, while the collector of clamp transistor Q C is also returned to current source resistor 30 at node N. The clamp transistor Q C has its base grounded (or connected to a reference voltage) and its emitter connected to the base of transistor Q₁ and to the collector of transistor Q₃. It will be recalled transistor Q₃ is turned on by the gate signal during the time base sweep so as to divert current from transistor Q₂. At this time, the collector of transistor Q₃ is low, pulling down the base of transistor Q₁ for turning off the latter. Transistor Q C operates as a "catch" transistor or clamp transistor to catch the collector of transistor Q₃ and the current I BIAS flows through transistors Q₃ and Q C . According to one alternative embodiment, the collector of transistor Q C could just be connected to a selected reference level. Then when node N would rise at the start of sweep as Q₁ turns off, the higher value of the I BIAS current would be brought about at the start of sweep inasmuch as node N is coupled in control relation to the adjustable current source 18 through transistor Q S . Thus, the adjustable current source would go from high current to low current, and reverse, in accordance with the off or on states of transistor Q₁. However, in accordance with the preferred embodiment, the collector of transistor Q C is returned to node N as illustrated. Then, even though transistor Q₁ turns off at the beginning of the time base sweep, transistor Q₃ being turned on at this time draws current through transistor Q C from node N and holds node N at a low level. Consequently, the current I BIAS from adjustable current source 18 remains at lower level 34′ during sweep phase 1 of FIG. 2, until after the conclusion of the time base sweep when transistor Q₃ is turned off by the conclusion of the gate signal. Then, neither transistor Q₁ nor transistor Q₃ are on, and node N may rise whereby adjustable current source 18 produces the larger I BIAS to accommodate the fast retrace. Therefore, not only does the current switch Q₂-Q₃ not switch a large current at the beginning of the sweep, it also need not switch a large current at the end of the sweep, and a switching transient is avoided at this time also. At the end of the sweep, the rise of node N is delayed slightly by capacitor 36 returned to ground, but I BIAS rises rapidly enough to produce the desired retrace. Of course it is immaterial whether the retrace waveform is absolutely linear since it is not seen. Correct baseline stabilizer loop phase margins are established by series combination of resistor 38 and capacitor 40 interposed between the output of amplifier 20 and ground. Turning now to the more detailed schematic diagram of FIG. 3, illustrating portions of the circuit in somewhat greater detail, the baseline stabilizer amplifier 20 comprises a differential amplifier including common emitter connected transistors 42 and 44, wherein the emitters are returned to a positive voltage through resistor 46. The collector of the transistor 44 is coupled to a negative voltage and the collector of transistor 42 is connected to the base of transistor Q₁ for bringing about turn on of transistor Q₁ when the retrace reaches the baseline reference. The baseline reference is provided by the base connection of transistor 44, here shown to be ground. However, the baseline reference voltage can be some other voltage value as desired. The same reference value is suitably connected to the base of clamp transistor Q C . The base of transistor 42 receives the ramp output from buffer amplifier 14 for comparison purposes as hereinbefore explained. Buffer amplifier 14 includes a first FET 48 coupled to timing capacitor 10, and has its drain-source path connected in series with FET 50 in a well known manner to provide a constant current source to accomplish zero offset with unity gain. FET 48 drives transistor 52, and the ramp output is taken from the emitter of transistor 52. The buffer amplifier circuit acts as a voltage follower with a one diode drop offset for reasons which will shortly become evident. Current source 12 comprises a current source transistor 54 having its collector connected to the emitter of a transistor 56 which operates as a cascode device. The collector of transistor 56 is connected to timing capacitor 10 for supplying the charging current thereto during the time base sweep. The base of transistor 56 is returned to a positive voltage through resistor 59. The emitter and base of transistor 54 are provided with various emitter resistances and input currents from time base switching circuit 60. The latter may be digitally operated for selecting the charging current for timing capacitor 10 and therefore controlling the sweep speed. Also, the value of capacitor 10 may be selected via time base switching circuit 60 through control of the coupling of one or more time base capacitors in circuit at the location illustrated in FIG. 3 for capacitor 10. Such switching circuits are well known to those skilled in the art. As hereinbefore mentioned, the semiconductor device which provides the constant current to timing capacitor 10, i.e. transistor 56 in this case, has an inherent capacitance which draws a current subtracting from the timing current and resulting in a slower than expected sweep. This inherent capacitance comprises the collector-base capacitance of transistor 56. However, in accordance with the present circuit, a matching transistor 58 is provided having its collector connected to the ramp output of buffer amplifier 14, and having its emitter and base connected to the emitter of transistor 56. Transistor 58 never conducts. However, the current due to transistor 58's collector-base capacitance enters transistor 56's emitter and adds to the timing current. Since transistors 56 and 58 are of the same type the capacitance related currents should substantially cancel. Moreover, the transistors 56 and 58 are operated at the same bias. Note that the buffer amplifier 14 operates as a voltage follower with a one diode drop offset attributable to transistor 52. The voltage present on the output of buffer amplifier 14, when fed to the collector of transistor 58, results in a collector-base voltage on transistor 58 which matches the collector-base voltage on transistor 56. Therefore, the capacitance related currents contributed by transistors 56 and 58 can substantially cancel resulting in approximately zero effective capacitance at the collector of transistor 56. This eliminates the effects of non-linear collector-base capacitance of the current source semiconductor device upon output ramp linearity. While a preferred embodiment of the present invention has been shown and described, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the invention in its broader aspects. The appended claims are therefore intended to cover all such changes and modifications as fall within the scope of the invention.

Claims: A timebase generator of the type having a timing capacitor (10), means (12) for charging the capacitor (10) to provide a timebase sweep signal (RAMP) starting from an initial baseline value, and means for discharging the capacitor (10) to provide a retrace period concluding with return of the timebase sweep signal (RAMP) to the initial baseline value, the discharging means including a current switch (Q2, Q3) having a first switching position to decouple the discharging means from the timing capacitor (10) and having a second switching position to provide an additional current path (Ibias) to discharge the capacitor (10) during the retrace period, the timebase generator being characterized by means (18) for supplying a first value (32) of current through the current switch (Q2, Q3) during the retrace period and a lower value (34) of current through the current switch (Q2, Q3) thereafter so that the lower value of current is present when the current switch (Q2, Q3) returns to the first switching position for initiation of the timebase sweep signal (RAMP). The timebase generator recited in claim 1 wherein the supplying means is further characterized by providing the lower value of current from the end of the retrace period of one cycle of the timebase sweep signal (RAMP) to the beginning of the retrace period of a next cycle of the timebase sweep signal (RAMP). The timebase generator recited in claim 1 further being characterized by means (Q1) for stabilizing the voltage on the capacitor (10) at the initial baseline value after the retrace period. The timebase generator recited in claim 3 further being characterized by means (Qs) responsive to the stabilizing means for causing the lower value of current to be commensurate with a timing current (Itiming) provided by the charging means (12). The timebase generator recited in claim 4 wherein the current switch is characterized by a pair of emitter coupled transistors (Q2, Q3) and the stabilizing means includes a third transistor (Q1) having its emitter coupled to the timing capacitor (10) as well as to the collector of one of the pair of transistors (Q2, Q3). The timebase generator recited in claim 5 wherein the supplying means is characterized by an adjustable current source (18) responsive to operation of the third transistor (Q1) when the timebase sweep signal (RAMP) returns to the initial baseline value at the end of the retrace period to change the current in the additional current path from the first value to the lower value. The timebase generator recited in claim 6 further characterized by the collector of the other of the pair of transistors (Q2, Q3) being coupled to the base of the third transistor (Q1), by means (Qs) coupling the collector of the third transistor (Q1) in control relation to the adjustable current source (18), by a clamp transistor (Qc) interposed between the collector and base of the third transistor (Q1), and by a current source resistor (30) coupled to the collector of the third transistor (Q1) such that the adjustable current source (18) continues to provide the lower value of current until current is not being diverted from the current source resistor (30) through the clamp transistor (Qc) and the other of the pair of transistors (Q2, Q3). The timebase generator recited in claim 1 wherein the charging means is characterized by: a semiconductor device (56) functioning as a source of current (Itiming) for the timing capacitor (10), the semiconductor device having an inherent capacitance that reduces the current provided to the timing capacitor (10); and means (58) for providing a compensating current for the timing capacitor (10). The timebase generator recited in claim 8 wherein the semiconductor device is characterized by a first transistor (56) connected as a cascode device driving the timing capacitor (10), the inherent capacitance being the collector-base capacitance of the transistor, and the providing means is characterized by a second transistor (58) having a collector-base capacitance connected in driving relation to the emitter of the first transistor (56), the timebase sweep signal (RAMP) being coupled for driving the collector-base capacitance of the second transistor (58) to provide compensating current for the timing capacitor (10). The timebase generator recited in claim 9 further characterized by a buffer amplifier (14) interposed between the timing capacitor (10) and the second transistor (58), the buffer amplifier (14) providing the timebase sweep signal (RAMP) to the second transistor (58) and having a diode drop offset matching the offset provided by the second transistor (58). The method of operating a timebase sweep generator including a timing capacitor (10) and means (12) for providing a first current path (Itiming) to the timing capacitor (10) to provide a timebase sweep signal (RAMP) from an initial value comprising the steps of: coupling an additional current path (Ibias) to the timing capacitor (10) to provide a retrace period during which the timebase sweep signal (RAMP) returns to the initial value; decoupling the additional current path (Ibias) from the timing capacitor (10) for the initiation of the timebase sweep signal (RAMP); characterized by limiting the current in the additional current path (Ibias) from the end of the retrace period until the initiation of the timebase sweep signal (RAMP) to a value below the current value during the retrace period. The method recited in claim 11 wherein the limiting step is characterized by limiting the current in the additional current path (Ibias) from the end of the retrace period of one cycle of the timebase sweep signal (RAMP) until the beginning of the retrace period of a next cycle of the timebase sweep signal (RAMP).

Inventors: DILLER, CALVIN DEAN
Applicants: TEKTRONIX, INC.
Application year: 1987
Main classification: G01R13
IPC codes: H03K4, G01R13, H04N3