PLASMA DISPLAY APPARATUS

Abstract: A plasma display apparatus comprising a plurality of dis­ charge cells is driven in two different modes. In an address mode a potential difference much larger than the discharge voltage is applied to selected cells to discharge while a pot­ ential difference smaller than the discharge voltage is applied to the non-selected cells so that they not discharge. In the following hold mode period the voltages are lowered but de­ termined such that the selected cells can continue the dis­ charge state while the non-selected cells require time to start discharge. By this means a high brightness, small power consump­ tion and a larger operating range are achieved.

Description: This invention relates to a plasma display apparatus and more particularly to driving AC refresh-type plasma display panel. A typical example of conventional AC refresh-type plasma display panel (PDP) to be used in the present invention comprises two glass plates having electrode groups which are coated with dielectric layer. The two glass plates are arranged in a manner to make electrode groups thereof opposed to each other but electrodes in each group intersect each other perpendicularly to form a so called matrix display type. The glass plates being sealed air-tightly with glass frits, and neon gas is filled in the sealed space surrounding the glass plates. When the driving circuit applies pulsed voltage to only one electrode group while maintaining the other electrode group at potential zero to cause discharge between electrodes, the voltage discharged at the cell which is most easily to discharge within the PDP is defined as the minimum unilateral discharge voltage (VDmin) and the voltage discharged at the cell which is most unlikely to discharge within the PDP is defined as the maximum unilateral discharge voltage (VDmax). If one electrode group of the PDP is applied with a first pulse train of high voltage (V₀) which is higher than VDmin but lower than VDmax while the other electrode group is applied with a second pulse train of low voltage (V1) which has the phase same as or opposite to the first pulse train, the discharge does not occur when the relation holds; VDmin > |V0| - |V1| and discharge occurs when the relation holds; VDmax < |V0| + |V1] . US Patent US-A-3,869,644 issued on March 4, 1975 discloses a so called phase-select method using the above condition as one example of the prior art AC refresh-type driving circuits for plasma display panels (PDP). In this prior art driving circuit, while a first pulse train of high voltage is applied to scanning electrodes in a time division mode, a second pulse train of low voltage having the phase opposite to the first pulse, train is applied to selected data electrodes associated with the selected cell to discharge. In addition, a third pulse train of low voltage having the phase same as the first pulse train is applied to remaining data electrodes associated with non-selected cells so as not to discharge the non-selected cells and thereby securing stable operation. In this prior art driving circuit, however, driving circuits are electrically connected via stray capacities between adjacent data electrodes provided on the substrate of PDP, and when the adjacent data electrodes are to be driven for discharging and non-discharging concurrently, the power consumption of the driving circuits for the adjacent data electrodes becomes maximum. Although the brightness of AC refresh-type PDP is determined by the number of pulses contained in a unit time, the larger the number of pulses become, the larger power consumption of the driving circuits becomes. Thus the restrictions on driving frequency present a formidable obstacle in obtaining sufficient brightness. The prior art driving circuit is further detrimental in that if there is mismatching in time in high frequency pulses between voltages applied to the scanning electrodes and the data electrodes, the range of driving voltage becomes narrow. Moreover, if transparent electrodes are used for data electrodes, a distributed constant circuit is formed via stray capacity between the transparent electrodes, and as the waveforms and voltages at a top end of the transparent electrodes differ from those at input end thereof, the brightness fluctuates unevenly. This also causes a delay in time and changes in voltage between the first pulse train for the scanning side and the second and third pulse trains for the data side, and the range of driving voltage inconveniently becomes narrower. It is, therefore, an object of this invention to provide a driving method for plasma display panel which results in a high brightness, small power consumption and a larger operating range. According to this invention, the potential difference applied to either selected cells or non-selected cells during one scanning cycle includes a period of address mode and a period of hold mode. In the address mode period, the potential difference larger than VD max is applied to the selected cells to discharge while the potential difference smaller than VD min is applied to the non-selected cells not to discharge. In the hold mode period, on the other hand, the potential difference applied to both of the selected cells and the non-selected cells is reduced but have the same amplitude which is determined such that the selected cells can continue the discharge state while the non-selected cells requires time to start discharge. The time delay may vary depending on the amplitude of the potential difference, but generally becomes 5 micro sec. or more in the AC refresh-type method. The response to discharge is extremely fast once started, and is less than 100 nano sec. due to ions and electrons filled in the selected cells. The present invention uses this phenomenon of discharge jitter. More particularly, the address mode can be obtained by applying pulse train of low voltage to data electrode with the phase opposite to or identical to the pulse train of high voltage applied to scanning electrode. The hold mode can be obtained by applying DC voltage to the data electrode. FIGs. 1A to 1E are waveform diagrams showing a relationship between the voltages applied to a scanning electrode and data electrodes according to a first preferred embodiment of this invention. FIGS. 2A to 2E are waveform diagrams showing a pulse train applied at scanning electrodes in a time-division mode. FIGs. 3A to 3E are waveform diagrams showing a relationship between the voltage applied to a scanning electrode and data electrodes according to a second preferred embodiment of this invention. FIGS. 4A to 4E are waveform diagrams showing a relationship between the voltages applied to a scanning electrode and data electrodes according to a third preferred embodiment of this invention. FIG. 5 is a block diagram of a driving circuit for a plasma display panel according to the first preferred embodiment of this invention. Referring to FIG. 1, while a first pulse train of peak voltage V₀ is applied to the first scanning or row electrode for one scanning period Th as shown in FIG. 1A, a second pulse train of peak voltage V₁ is applied to the m th data or column electrode for a period Ta shorter than the period Th as shown in FIG. 1B. Following the pulse train for the period Ta, a direct current voltage is applied to the m th column electrode for a period Tb as shown in FIG. 1B. The period represented by the letter Tc in FIG. 1 is a blanking period. Thus the sum of the periods, Ta + Tb + Tc , indicates the one scanning period Th. As is shown in FIG. 1B, the second pulse train has the phase opposite to the first pulse train so as to produce a first pulsing potential difference shown in FIG. 1D larger than the firing voltage of the selected cell formed at the intersection of the first row electrodes and the m th column electrode. When the n th column electrode is associated with non-selected cell not to be discharged, a third pulse train of peak voltage V₁ is applied to the n th column electrode for the period Ta with the phase identical to the first pulse train as shown in FIG. 1C. During the period Tb, the n th column electrode is also applied with a direct current voltage. FIG. 1E shows the potential difference applied to non-selected cell formed at the intersection of the first row electrode with the n th column electrode. The operation during the period Ta in the one scanning period Th is identical to the operation disclosed in the aforementioned, UP Patent No. 3,869,644. The period Ta is defined herein as an address mode. The potential difference V₀ applied to the selected cells and non-selected cells during the period Tb in the one scanning period Th are completely identical to each other as shown in FIGs. 1D and 1E. This period is referred herein as a hold mode. At the address mode, if the relations below hold, the selected cells to glow are discharged and the non-selected cells not to glow are not discharged; VDmax < |V1| + |V0| (1) VDmin > |V0| - |V1| (2) In the hold mode, the potential difference V₀ is applied irrespective to glow/not to glow the cells to maintain the state created at the address mode which preceded the hold mode. More particularly, as the selected cell is discharged at the period Ta, the selected cell is filled with charged particles generated by the discharge, thus following discharge is actuated easily even in the hold mode where potential difference lower than in the address mode is being applied. Since the non-selected cell is not discharged in the address mode period Ta, the non-selected cell is not filled with charged particles. Therefore, it takes a certain time before the non-selected cell starts discharge in the subsequent period Tb with the potential difference V₀. Accordingly, if a suitable period is selected, for instance, at 20 micro second or less for the perior Tb, it is possible to determine the voltage which will not start discharge at the hold mode. Needless to say, in order to drive a conventional plasma display panel, the scanning electrode group is selected for the period T h with horizontal synchronizing signals shown in FIG. 2E, and the first electrodes are applied with a pulse train having the peak value of V₀ shown in FIG. 2A. after a certain period (blanking period), the second scanning electrode is selected, and the pulsed voltage having the peak value of V₀ is applied to the second scanning electrode only for the period T h . (Refer to FIG. 2B.) The third scanning electrode is applied with a pulsed voltage after a pulsed voltage is applied to the second scanning electrode, and this operation is repeated sequentially until the time when vertical synchronizing signal arrives or for the period T v . The state then returns to the state which allows selection of the first scanning electrode when the vertical synchronizing signal, arrives. According to this invention, each of the scanning electrodes is sequentially scanned with horizontal synchronizing signals, and the state is returned to the initial state with a vertical synchronizing signal which is inputted after all the scanning electrodes are scanned. The vertical synchronizing signal is coincidental to the refresh frequency in display and generally is determined as 55 cycles or higher. An example will be described below for the case wherein a plasma display panel having display cells of 640 x 400 dots is driven by the aforementioned driving method. When the applied voltage V₀ shown in FIG. 1A was set at 180 V, its frequency at 800 KHz, the applied voltage V₁ in FIGs. 1B, and 1C at 30 V, their frequency at 800 KHZ, the period T a at 20 micro sec., and the period T b at 10 micro sec., the plasma display panel shows stable performance without erroneous discharge to obtain the following results: Prior art phase-select method This invention method Power 40 W 28 W Brightness 10 fL 9.4 fL As shown above, when the address mode at the period T a and the hold mode at the period T b have the same frequency, the power consumption will be decreased by an increase of the period T b , but this inevitably entails a decrease in brightness. It is therefore preferable to design the period T b shorter than the period T a . Description will now be given to an example which can reduce the power consumption and still increase the brightness. FIG. 3 shows arrangement of pulse trains of the second embodiment. FIG. 3A shows a pulse train of peak voltage V₀ applied on the scanning electrodes at the N th row in a plasma display panel. FIG. 3B shows a pulse train of peak voltage V₁ applied on the data electrodes of the m th column, and FIG. 3C the pulse train of peak voltage V₁ applied on the data electrodes of the n th column. FIG. 3D shows the pulsed potential difference applied on the selected (the N th row, the m th column) cells defined at the intersections of the Nth row electrodes and the m th electrodes, and FIG. 3E the pulsed potential difference applied on the non-selected ( N th row, the n th column) cells formed at the intersections of the N th row electrodes and the n th column electrodes. In the drawings, the period represented by the letter T c is the blanking time while the period represented by the letter T a is the time when display is made in the address mode. The period represented by the letter T b is the time when display is made in the hold mode. The sum of the periods, T a + T b + T c , indicates one scanning time T h where one scanning electrode is being selected. An example where a plasma display panel having the display points of 640 x 400 dots is driven with the pulsed voltages shown in FIG. 3 is described below. When the voltage V₀ shown in FIG. 3A was set at 170 V, the frequency in the address mode at 500 KHz, the frequency in the hold mode at 2 MHz, the voltage V₁ shown in FIGS. 3B and 3C at 30 V, its frequency in the address mode at 500 KHz, and the frequency in the hold mode in DC, the panel showed a stable operation. The following table shows the comparison of the power consumption and brightness of the plasma display panel driven by this invention method under the above conditions, and the plasma display panel driven by the prior art phase-select method (driven by 800 KHz). Power consumption Brightness Phase-select method 40 W 10 fL This invention method 15 W 12 fL The power consumption and brightness change in proportion to the ratio between the time period T a in address mode and the period T b in hold mode in FIG. 3. The ratio was set at 1:2 in the above example. In the second example, the power consumption can be reduced and at the same time the brightness can be increased by lowering the frequency in the address mode and increasing the frequency in the hold mode. The frequency during the period T a may be selected from the range of 400 KHz to 600 Hz, and the frequency for the period T b may be selected from the range of 1.5 MHz to 3 MHz. It is preferable that the duration of the period T b is 1 to 2.5 folds of the duration of the period T a . The third example is now described. FIG. 4 shows the voltage waveform applied to respective electrodes of the third example. FIG. 4A shows the pulse train of peak voltage V₀ applied to the scanning electrode in the N th row for one scanning period T h ; as shown in the drawing, the period T a is an address mode, and the period T b a hold mode, and the period T c a blanking mode. While the N th row electrodes are being scanned, as shown in FIG. 4B, the m th column electrode is applied with a pulse train of peak voltage V₁ with the phase opposite to the phase of the pulse train applied on the N th row electrodes. Therefore, the selected cell of (the N th row, the n th column) at the intersection of the N th row electrode and m th column electrode is applied with the pulsed potential difference having the amplitude of V₀ + V₁ at the address mode as shown in FIG. 4D. As the amplitude is selected to be higher than VD max , the selected cell of (the N th row, the n th column) is lit in display. As the pulse train of peak voltage V₁ applied to the n th column electrode and the pulse train of peak voltage V₀ applied to the N th row electrode are of the same phase, the display cell of (the N th row, the n th column) have the potential difference of V₀ - V₁ at the address mode and do not discharge. The display cells which started discharge in the period T a and the cells which did not start discharge in the period T a are applied with high frequency pulses of the potential difference of V₀ in the subsequent period T b . As the voltage applied in the period T b is selected to be higher than the voltage to start unilateral discharge, if the duration of the period T b is sufficiently long (or more than 20 micro sec.), the non-selected cell (the N th row, the n th column) will start discharge in the hold mode, but if the hold mode is switched to the address mode before the non-selected cell starts discharge in the period T b , the potential difference applied on the non-selected cell becomes V₀ - V₁ to thereby preventing the non-selected cell from discharging both in the periods T a and T b . As stated above, stable display can be obtained by providing an address mode, a hold mode, an address mode and a hold mode within one scanning period T h . Description will now be given to an example where a panel, having display cells of 640 x 400 dots is driven by pulse waveforms shown in FIG. 4. The panel was driven by setting one scanning time at 43 micro sec., blanking period T c at 3 micro sec., an address mode period T a at 10 micro sec., a hold mode period T b at 10 micro sec., V₁ at 30 V, the frequency in the address mode at 500 KHz, the frequency in the hold mode at 2 MHz. The panel was operated stably with the voltage V₀ ranging from 163 V to 175 V. When compared to a plasma display panel driven by the prior art phase-select method with frequency of 800 KHz, this invention method improves the brightness by 1.1 folds, power consumption by 50%, and operating voltage range by two folds. As described above, the plasma display panel according to this invention can remarkably improve the brightness, power consumption and operating voltage range. FIG. 5 is a block diagram to show a plasma display system according to the present invention. The plasma display system comprises a matrix display type of plasma display panel 1, a driving circuit for the row electrode group 2, a driving circuit for the column electrode group 3, a latch circuit 4 for storing data, a shift register 5 for storing data temporarily, and a shift register 6 for sequentially shifting row electrodes. The pulse train of peak voltage V₀ to be applied at row electrodes is generated by a complimentary inverter circuit at the last stage of the driving circuit 2 and has the peak value of V₀. The input signals of this circuit 2 are the output from the shift register 6 and the high frequency pulse signal 10 inputted from outside which are mixed at an AND gate. The output signal of the AND gate is amplified upto the value of high voltage source V₀ by the inverter circuit. Thus the high frequency pulse signal inputted from outside and the output from the driving circuit 2 at the last stage have the same frequency of opposite phases. The shift register 6 receives scanning data signal 11 and scanning clock signal 12 as input, and the scanning data signal 11 is sequentially transferred by the scanning clock signal 12 to the AND gate in the driving circuit 2. The column electrodes driving circuit 3 comprises a complimentary inverter circuit which receives the output from an exclusive OR circuit as input to be inverted at the driving circuit. The data inputted at the shift register 5 with the dot data input 17 and the data shift clock signal 18 are transmitted to the latch circuit 4 by latch pulse signal 16. The outputs from the latch circuit 4 are inputted at the exclusive OR circuit in the driving circuit 3 to be mixed with the high frequency pulse signal 15 inputted from outside. If there is no output from the latch circuit 4, the output from the exclusive OR circuit becomes of the phase opposite to the one of the high frequency pulse signal 15 which is inputted from outside. The high frequency pulse 15 is then amplified up to the value of voltage source V₁ by the inverter circuit and thus the pulse train obtained from the column electrodes driving circuit 3 has the same phase as the high frequency pulse signal 15. Conversely, if there is an output from the latch circuit 4, the output from the exclusive OR circuit has the phase identical to the phase of the high frequency pulse signal 15 inputted from outside and the pulse train in the output circuit has the phase opposite thereto. The DC voltage needed for a hold mode can be obtained by converting the high frequency pulse signal 15 to DC signal. The conversion in frequency which is necessary for the hold mode as in the second preferred embodiment may be conducted by switching the frequency of the high frequency pulse signal 10 inputted from outside. According to the present invention, although the power consumption during the period the voltage similar to the prior art phase-select method is applied is identical to the one by the prior art method, the power consumed in the period when the voltage entirely irrelevant to the waveform applied to the scanning electrodes or the direct current voltage is applied to the data electrodes is remarkably reduced as the power consumed between adjacent data electrodes becomes negligible. Further the driving becomes stable with a smaller power consumption in this invention circuit by lowering driving frequency for the period of driving similar to the phase-select method and by increasing the frequency of the period when DC voltage is being applied to data electrodes.

Claims: A plasma display apparatus comprising a first electrode group and a second electrode group disposed in an opposed relation to each other by the intermediary of a discharge gas to form cells therebetween, first means for applying a first pulse train of first voltage to said first electrode group for a first period (Tn) in a time-division mode at a predetermined interval, second means for applying a second pulse train of second voltage to at least one selected electrode in said second electrode group for a second period (Ta) shorter than said first period in synchronism with said first pulse train so as to produce a first pulsing potential difference between the electrodes associated with a selected cell in combination with said first pulse train, said first pulsing potential difference being larger than a firing voltage of said cell, third means for applying a third pulse train of third voltage pulses to non-selected electrodes in said second electrode group for said second period in synchronism with said first pulses train so as to produce a second pulsing potential difference between the electrodes associated with non-selected cells in combination with said first pulses train, said second pulsing potential difference being smaller than the firing voltage of said cell, and fourth means for applying a first direct-current voltage component to said at least one selected electrode in said second electrode group for a third period (Tb) shorter than said first period after application of said second voltage pulses so as to produce a third pulsing potential difference between the electrodes associated with said selected cell in combination with said first pulse train, said third pulsing potential difference being smaller than the firing voltage of said cell but large enough to continue the discharge of said selected cell due to previous discharging state of said selected cell. The apparatus of claim 1, further comprising fifth means for applying a second direct-current voltage component to said non-selected electrodes in said second electrode group for said third period after application of said third pulse train so as to produce a fourth pulsing potential difference between the electrodes associated with said non-selected cell in combination with said first pulse train, said fourth pulsing potential difference being smaller than the firing voltage of said cell, the period of applying said fourth pulsing potential difference being smaller than the period required to cause a discharge of said non-selected cell, The apparatus of Claim 1, wherein said first pulse train includes a first pulse train portion having pulses of a first frequency and continuing for said second period and a second pulse train portion having pulses of a second frequency higher than said first frequency and continuing for said third period. The apparatus of Claim 1, wherein the phase of said second pulse train is opposite to that of said first pulse train and the phase of said third pulse train is identical to that of said first pulse train. The apparatus of Claim 4, wherein the amplitude of said second pulse train is the same as that of said third pulse train. The apparatus of Claim 4, wherein the frequency of said first pulse train in said second period pulsing potential difference is smaller than that of said first pulse train in said third period.

Inventors: HADA, HIROSHI C/O NEC CORPORATION, IWAKAWA, TSUNEKIYO C/O NEC CORPORATION, NAKAMURA, TADASHI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1987
Main classification: G09G3
IPC codes: G09G3