TRANSFER GATE CIRCUIT

Abstract: A transfer gate circuit including a first MIS transistor (Q₁) which transmits an input signal ( ) supplied from an input side thereof to an output side thereof in accordance with a control signal ( ) supplied to a gate of the first MIS transistor (Q₁); an inverter circuit (Q₄,Q₅) connected between power supply lines which inverts the potential of the input signal; and an output level guarantee circuit comprising second and third MIS transistors (Q₂,Q₃) which have a conductivity type opposite to that of the first MIS transistor (Q₁) and are connected in series between one of the power supply lines (V cc2 ) and the output side (V), and an output signal (A) of the inverter circuit (Q₄,Q₅) being supplied to a gate of the second MIS transistor (Q₂), an inverted signal () of the control signal ( ) supplied to the gate of the first MIS transistor (Q₁) being supplied to a gate of the third MIS transistor (Q₃).

Description: The present invention relates to a transfer gate circuit for reliably transferring an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal. Generally, a transfer gate circuit of this kind comprises CMOS type transfer gate transistors including a P-channel type transistor and an N-channel type transistor connected in parallel. The gates of the P-channel type transistor and the N-channel type transistor are supplied with a control clock signal and its inverted signal, respectively. When the above pair of transistors are turned on in accordance with the potential levels of the control clock signal and its inverted signal supplied thereto, an input signal supplied to the input side of the CMOS type transfer gate transistors is transferred to the output side thereof. Here, the reason why the transfer gate circuit comprises the above pair of transistors constructed in the CMOS form, is that if the transfer gate were comprised only of the P-channel transistor, in the low level (zero level) state of the input signal, the potential of the output side would not fall below the threshold voltage of the P-channel transistor and if the transfer gate were comprised only of the N-channel transistor, in the high level (e.g., V CC1 level) state of the input signal, the potential of the output side would not rise above the value of the high level potential of the inverted control clock signal minus the threshold voltage of the N-channel transistor. On the other hand, by constructing the transfer gate in the above CMOS form, the low level and high level of the input signal can be transferred as they are to the output side in accordance with the potential level of the control clock signal. Note that the above high level potential V CC1 of the input signal is produced through an inverter circuit, for example. When the above pair of CMOS transistors are formed in a P-type substrate, for example, source and drain regions of the N-channel transistor are formed in the above P-type substrate, and also, source and drain regions of the P-channel transistor are formed in an N-type well formed in the P-type substrate. The input signal having the potential V CC1 in the high level side is supplied to one of the source (drain) regions of each of the N-channel and the P-channel transistors, and the above input signal is taken out as the output signal from the other source (drain) region of each of the N-channel and the P-channel transistors. Note that the N-type well in which the P-channel transistor is formed is supplied with a predetermined potential V CC2 (as mentioned later, which is lower than V CC1 ) from a power supply line which is common with the above inverter circuit. As mentioned above, the N-type well in which is formed the P-channel transistor comprising the CMOS type transfer gate is supplied with the predetermined potential V CC2 from the power supply line which is common with a circuit for production of the input signal to be transferred (e.g., the inverter circuit), but the power supply line inevitably includes a wiring resistance. Particularly, if some circuits belonging to another system, for example, are provided between the inverter circuit and the above transfer gate transistors, the length of the power supply line between the inverter circuit and the transfer gate transistors becomes relatively long, and thus, the value of the wiring resistance due to the above length of the power supply line becomes relatively high. Further when the power current is supplied to some peripheral circuits provided on the same substrate through the power supply line, the value of the power current flowing through the power supply line also becomes high. Therefore, in such a case, a relatively large potential difference occurs between the potential V CC1 supplied from the power supply line to the inverter circuit and the potential V CC2 supplied from the power supply line to the N-type well. The potential V CC2 therefore becomes lower than the potential V CC1 (that is, V CC1 > V CC2 ). On the other hand, as a current (i.e., the input signal) flowing through a signal line is small, the high level potential of the input signal supplied to the transfer gate transistors is nearly equal to the high level potential V CC1 supplied from the inverted circuit, so in the high level state of the input signal, a PN junction turns on between the source (drain) of the P-channel transistor to which the potential V CC1 is supplied and the N-type well to which the potential V CC2 is supplied. Due to this, there is a chance of occurrence of so-called latch-up by the thyristor equivalently comprised by the PNPN layers formed in the above P-type semiconductor substrate. In such a case, subsequent to this, there is the problem that current will continue to flow in the semiconductor substrate through the PNPN layers. The present invention addresses this problem. An embodiment of the present invention may provide a transfer gate circuit which inhibits the chance of occurrence of latch-up as in the above conventional CMOS type transfer gate circuit and further enables reliable transfer of the input signal supplied from the input side thereof to the output side thereof in accordance with the potential level of the control clock signal supplied to a gate of a single transfer gate transistor. According to the present invention, there is provided a transfer gate circuit comprising a first MIS transistor operable to transmit an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal supplied to a gate of the first MIS transistor; an inverter circuit connected between power supply lines and operable to invert the potential of the input signal; and an output level guarantee circuit comprising second and third MIS transistors which have a conductivity type opposite to that of the first MIS transistor and are connected in series between one of the power supply lines and the output side, wherein, in use, an output signal of the inverter circuit is supplied to a gate of the second MIS transistor, an inverted signal of the control signal supplied to the gate of the first MIS transistor being supplied to a gate of the third MIS transistor. According to the above-mentioned constitution, the transfer gate transistor which transmits the input signal supplied from the input side thereof to the output side thereof is not comprised in the CMOS form as in the above-mentioned conventional circuit, but is comprised by a single transistor (i.e., the first MIS transistor), so the chance of occurrence of latch-up as mentioned above is eliminated. Further, when the potential of the input signal supplied to the first MIS transistor comprising the transfer gate transistor is a first level (e.g., high level), the second and third MIS transistors are turned on and the potential of the first level of the output side of the transfer gate transistor is guaranteed. On the other hand, when the potential of the input signal supplied to the first MIS transistor becomes a second level (e.g., low level), the second MIS transistor are turned off, and the potential of the second level of the input signal is transferred to the output side through the first MIS transistor. Reference is made, by way of example, to the accompanying drawings in which: Figure 1 is a circuit diagram showing an example of the constitution of a previous transfer gate circuit; Fig. 2 is a diagram showing the state of formation of the CMOS type transfer gate transistors shown in Fig. 1 in a semiconductor substrate; Fig. 3 is a circuit diagram showing the constitution of a transfer gate circuit according to a first embodiment of the present invention; and Fig. 4 is a circuit diagram showing the constitution of a transfer gate circuit according to a second embodiment of the present invention. In order to clarify the background of the present invention, an example of the constitution of a previously proposed transfer gate circuit is shown in Fig. 1. Namely, in Fig. 1, reference symbols Q₆ and Q₃′ are P-channel MOS transistors (in general, MIS transistors). These P-channel transistors are given the O mark in the figure. Further, Q₇ and Q₁ are N-channel MOS transistors (in general MIS transistors). The P-channel transistor Q₆ and N-channel transistor Q₇ comprise an inverter circuit. On the other hand, the P channel transistor Q₃′ and N channel transistor Q₁ comprise CMOS type transfer gate transistors. The potential of the input signal A supplied to the input side of the inverter circuit comprised of the transistors Q₆ and Q₇ is inverted by the inverter circuit. The inverted signal A is supplied to the input side of the transfer gate transistors. The gates of the transistors Q₃′ and Q₁ are supplied with control clock signal  and its inverted signal  . When the clock signal  becomes the low level (therefore the inverted signal  becomes the high level), the transistors Q₃′ and Q₁ are turned on and the signal A having a predetermined potential supplied to the input side is transferred to the output side of the transfer gate transistors as the output potential V. Here, the reason why the transfer gate is comprised in a so-called CMOS form by the P-channel transistor Q₃′ and N-channel transistor Q₁ is that if the transfer gate were comprised only of the P-channel transistor Q₃′, in the low level (zero level) state of the input signal A , the potential of the output side would not fall below the threshold voltage Vth (Q₃′) of the transistor Q₃′ and if the transfer gate were comprised only of the N-channel transistor Q₁ , in the high level (level of potential V CC1 supplied from the inverter circuit) state of the input signal A , the potential of the output side would not rise above the value of the high level potential of the inverted control signal  minus the threshold voltage Vth (Q₁) of the transistor Q₁. On the other hand, by constructing the transfer gate in the so called CMOS form, the low level and high level of the input signal A can be transferred as they are to the output side by the control clock signals  and  . Figure 2 shows the state of the above-mentioned transistors Q₁ and Q₃′ formed in a semiconductor substrate. In a P-type substrate 1 are formed source (drain) regions (N-type region) 11 and 12 of the N-channel transistor Q₁. In an N-type well 2 formed in said P-type substrate 1 are formed source (drain) regions (P-type regions) 21 and 22 of the P-channel transistors Q₃′. The input signal A is supplied to the N-type region 11 and the P-type region 21. By the control clock signal, these transistors Q₁ and Q₃′ are turned on, whereby the input signal A is taken out as the output potential V from the N-type region 12 and the P-type region 22. Note that the N-type well 2 in which the P-channel transistor Q₃′ is formed is supplied with a predetermined potential V CC2 (as mentioned later, which is lower than V CC1 ) from a power supply line which is common with the inverter circuit. As mentioned above, the N-type well 2 in which is formed the P-channel transistor Q₃' comprising the CMOS type transfer gate is supplied with the predetermined potential V CC2 from the power supply line which is common with a circuit for production of the input signal A to be transferred (in the above-mentioned Fig. 1, the inverter circuit), but the power supply line inevitably includes a wiring resistance R. Particularly, if some circuits belonging to another system, for example, are provided between the inverter circuit and the transfer gate transistors, the length of the power supply line becomes relatively long, and accordingly, the value of the wiring resistance R becomes relatively high. Further, when the power current is supplied to some peripheral circuits (not shown) provided on the same substrate through the power supply line, the value of the power current flowing through the power supply line also becomes high. Therefore, in such a case, relatively large potential difference occurs between the potential V CC1 supplied from the power supply line to the inverter circuit and the potential V CC2 supplied from the power supply line to the N-type well. The potential V CC2 therefore becomes lower than the potential V CC1 (that is, V CC1 > V CC2 ). On the other hand, as the current flowing through the signal line is small the high level potential of the input signal A supplied to the transfer gate transistors is nearly equal to the high level potential V CC1 supplied from the inverter circuit, so in the high level state of the input signal A , a PN junction turns on between the source (or drain) of the P-channel transistor Q₃, to which the potential V CC1 is supplied and the N-type well 2 to which the potential V CC2 is supplied. Due to this, there is a chance of occurrence of so-called latch-up by the thyristor equivalently comprised by the PNPN layers formed in the semiconductor substrate. In such a case, subsequent to this, there is the problem that current will continue to flow in the semiconductor substrate through the PNPN layers. The present invention addresses this problem, and Fig.3 shows the constitution of a transfer gate circuit according to a first embodiment of the present invention, in which portions corresponding to those in Fig. 1 are given the same reference symbols as in Fig. 1. In Figs. 3, Q₂ , Q₃ , Q₄ , and Q₆ are P-channel MOS transistors (in general, MIS transistors), which P-channel transistors are given the O mark in the figure. Further, Q₁ , Q₅ , and Q₇ are N channel MOS transistors (in general, MIS transistors). The P-channel transistor Q₆ and N-channel transistor Q₇ comprise an inverter circuit (corresponding to the inverter circuit in Fig. 1). An input signal A is supplied from the output side of the inverter circuit to the N-channel transistor Q₁ comprising the transfer gate. When the control clock signal  supplied to the gate of the transistor Q₁ becomes the high level, the potential of the input signal A is transferred to the output side of the transfer gate as the output potential V. Between the power source line which is common with the inverter circuit and the output side of the transfer gate transistor Q₁ are connected in series two P-channel (that is, conductivities opposite to the above-mentioned N-channel transistor Q₁) transistors Q₂ and Q₃. To the gate of the transistor Q₂ is supplied a signal A inverted by an inverter circuit X comprised of the transistors Q₄ and Q₅ from an input signal A supplied to the N-channel transistor Q₁. On the other hand, a clock signal  inverted from a control clock signal  supplied to the gate of the N-channel transistor Q₁ is supplied to the gate of the transistor Q₃. Here, these two transistors Q₂ and Q₃ comprise an output level guarantee circuit Y, so the high level potential transferred to the output side of the transfer gate (N-channel transistor Q₁) is guaranteed by the output level guarantee circuit Y. In such a transfer gate circuit of the present invention described above, since the transfer gate is comprised by a single transistor (that is, the N-channel transistor Q₁ in the case of Fig. 3), even if a potential difference occurs based on the above wiring resistance R and the power current flowing through the above-mentioned power supply line, the chance of occurrence of the above-mentioned latch-up as in the previous circuit comprised of the CMOS type transfer gate is completely eliminated. Further, at the high level state of the input signal A (that is, the V CC1 level), when the control clock signal  becomes the high level, it is not possible to transfer the predetermined high level potential as mentioned above by just the above-mentioned N-channel transistor Q₁, but in the present invention, both the inverted signal A supplied to the gate of the transistor Q₂ and the inverted signal  supplied to the gate of the transistor Q₃ become low level, both the P-channel transistor Q₂ and Q₃ are turned on, and the potential of the output side of the transfer gate transistor Q₁ is made the V CC2 level, which can substantially be estimated (considered) as a high signal level. Namely, when considering the signal lever, it is possible to ignore the potential difference caused by the above-mentioned power supply line and the high level potential of the transfer destination is guaranteed to be made the high level potential of V CC2 which can be estimated as the high signal level. On the other hand, in the low level state of the input signal A (that is, the zero level), when the control clock signal  becomes the high level and the transistor Q₁ is turned on, the transistor Q₂ is turned off and the low level potential of the transfer destination is made equal to the ground potential through the transistor Q₁ and the transistor Q₇. Note that in the illustrated embodiment, the inverter circuit X for supplying the above-mentioned inverted signal A to the gate of the transistor Q₂ is connected to the input side of the transistor Q₁ , but the inverter circuit X clearly may also be connected to the output side of the transistor Q₁. Further, in the illustrated embodiment, the transistor Q₁ comprising the transfer gate was made an N-channel transistor, but the transistor Q₁ may also be made a P-channel transistor, in accordance with which the transistors Q₂ and Q₃ are made N-channel transistors and these transistors Q₂ and Q₃ are connected in series between the output side of the transistor Q₁ and the ground, whereby it is possible to supply a predetermined gate signal to these transistors Q₂ and Q₃ , in the similar way as above and to guarantee the low level potential of the transfer destination. Figure 4 shows the constitution of a transfer gate circuit according to a second embodiment of the present invention. In this embodiment, a P-channel MOS transistor Q₈ and an N-channel MOS transistor Q₉ (in general, MIS transistors) comprise another inverter circuit for supplying the inverted clock signal  of the clock signal  generated from a clock generator C to the gate of the transfer gate transistor Q₁. Note that in the transfer gate circuit shown in Fig. 4, portions corresponding to those in Fig. 3 are given the same reference symbols as in Fig. 3. In this connection, a source side of the P-channel transistor Q₈ is connected to the power supply line at the connecting point adjacent to that of the above inverter circuit X (i.e., the connecting point having the potential level substantially equal to V CC2 ). In this connection, if the potential of the control clock signal  becomes high level, which is higher than a predetermined level from one cause or another (e.g., if the potential level of the clock signal  becomes the above V CC1 plus the above threshold voltage Vth (Q₁), and the output potential V becomes equal to V CC1 which is higher than V CC2 ), there is a chance of occurrence of the latch-up of the P-channel transistor Q₂ provided in the output level guarantee circuit Y. In more detail, the potential level of a drain region of the P-channel transistor Q₂ is equal to the value V, an N-type well (not shown) in which the P-channel transistor Q₂ is formed is supplied with the potential V CC2 , and therefore, if the potential of the control signal  becomes higher than the predetermined level as above-mentioned, the latch-up of the transistor Q₂ may occur, as in the case of the latch-up of the above-mentioned P-channel transistor Q₃′ provided in the circuit shown in Fig. 1. However, in the above circuit shown in Fig. 4, the potential level of  is set to be equal to V CC2 in high level side (i.e., when the P-channel transistor Q₈ having the source connected to the power supply line at the point having the potential level substantially equal to V CC2 is turned on and the N-channel transistor Q₉ is turned off). Thus, the output potential V (i.e., the potential level  minus the threshold voltage Vth (Q₁)) becomes equal to V CC2 - Vth (Q₁)), and as a result, the output potential V become lower than V CC2 . Therefore, according to the circuit shown in Fig. 4, it is possible to surely prevent the occurrence of the latch-up of the P-channel transistor Q₂ provided in the output level guarantee circuit Y. As above-mentioned, by an embodiment of the present invention, it is possible to obtain a transfer gate circuit which inhibits the chance of occurrence of latch-up as in the previous CMOS type transfer gate circuit and further enables reliable transfer of the input signal supplied from the input side thereof to the output side thereof in accordance with the potential level of the control clock signal supplied to the single transfer gate transistor.

Claims: A transfer gate circuit comprising: a first MIS transistor (Q₁) operable to transmit an input signal ( A ) supplied from an input side thereof to an output side thereof in accordance with a control signal (  ) supplied to a gate of said first MIS transistor; an inverter circuit (Q₄, Q₅) connected between power supply lines and operable to invert the potential of said input signal ( A ); and an output level guarantee circuit comprising second and third MIS transistors (Q₂, Q₃) which have a conductivity type opposite to that of said first MIS transistor (Q₁) and are connected in series between one of said power supply lines and said output side, wherein, in use, an output signal (A) of said inverter circuit (Q₄, Q₅) is supplied to a gate of said second MIS transistor (Q₂), an inverted signal () of the control signal supplied to the gate of said first MIS transistor (Q₁) being supplied to a gate of said third MIS transistor (Q₃). A transfer gate circuit according to claim 1, further comprising another inverter circuit (Q₈, Q₉) for supplying said control signal (  ) to the gate of said first MIS transistor (Q₁), said another inverter circuit being connected between said power supply lines, said one of power supply lines having high potential level being connected to said another inverter circuit at a connecting point adjacent to that of said inverter circuit (Q₄, Q₅). A transfer gate circuit according to claim 1 or 2, wherein said first MIS transistor (Q₁) is an N-channel type transistor, and said second and third MIS transistors (Q₂, Q₃) are P-channel type transistors connected in series between one or said power supply lines having a high potential level and said output side of said first MIS transistor (Q₁). A transfer gate circuit according to claim 1 or 2, wherein said first MIS transistor (Q₁) a P-channel type transistor, and said second and third MIS transistors (Q₂, Q₃) are n-channel type transistors connected in series between said output side of said first MIS transistor (Q₁) and one of said power supply lines having a low potential level. A transfer gate circuit according to claim 1,2,3, or 4, wherein the input of said inverter circuit (Q₄, Q₅) is connected to said input side of said first MIS transistor. A transistor gate circuit according to claim 1,2,3, or 4, wherein the output of said inverter circuit (Q₄, Q₅) is connected to said output side of said first MIS transistor (Q₁) through the second MIS transistor (Q₂). A transfer gate circuit according to any preceding claim ,wherein a third inverter circuit (Q₆, Q₇) is provided which is connected between said power supply lines and which is operable to supply said input signal ( A ) to said first MIS transistor (Q₁).

Inventors: NAKANO, MASAO, NOMURA, HIDENORI, OHIRA, TSUYOSHI
Applicants: FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1987
Main classification: H03K17
IPC codes: H03K17, H01L21, H01L27