EXTENDED RASTER OPERATING IN A DISPLAY SYSTEM

Abstract: A display system has a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, a controller for controlling image data operations and extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes, and a separate interplane operation unit for performing operations, specified by the controller, on image data in at least two memory planes selected by the controller, the extended raster operation circuitry being so connected to the memory planes that the results thereof are written back to the frame buffer. The interplane operation unit consists of a plurality of operation circuits respectively corresponding to the plurality of memory planes, and a plurality of delay means respectively related to the plurality of operation circuits, each of the operation circuits receives, as the inputs, image data in a memory plane selected by the command and its own output delayed a predetermined period of time by the related delay means, and the final operation result only is written into the corresponding memory plane.

Description: The present invention relates to extended raster operating in display systems. Most of the recent display systems have a frame buffer comprising a plurality of memory planes so that a plurality of bits corresponding to one pixel are concurrently available to retain information such as colour, intensity, etc. There exists a system for manipulating such information in the frame buffer, called BitBlt. The raster operations which can be performed in the BitBlt system have been defined as the Boolean operations between sources and destinations or between sources, destinations and additionally provided third rectangular areas called patterns or masks. The details of the BitBlt system are described in "Smalltalk-80 The Language and its Implementation," A. Goldberg and D. Robson, Addison-Wesley, 1983, pages 354 - 361, for example. Further, U.S. Patent US-A-3,976,982 (published 24.08.76) discloses an image processing system for performing logical operations on images. Briefly speaking, the BitBlt is a function of designating a rectangular area in a frame buffer by bits and transferring it to another display area. In its transfer, logical operations such as AND, OR, XOR, etc. are performed on the contents stored in the source and the destination. Thus this kind of operation is often regarded as being synonymous with raster operations. When raster operations are performed in a frame buffer comprising a plurality of memory planes, it is usual to employ a single raster operation circuit in common to all of the planes or to provide a separate raster operation circuit for each of the planes. In conventional raster operation circuits, the logical operations have been limited to only one of the memory planes, whether a single raster operation circuit is provided in common to all of them or a separate raster operation circuit is provided to each of them. For example, if a frame buffer is assumed to comprise four memory planes and a source and a destination are denoted by Si and Di, where i = 0, 1, 2, and 3 respectively, conventional raster operation circuits can perform operations such as Di ⇐ f(Si, Di) where f is a given logical function, but cannot not easily perform operations including interplane operations such as:- D0 ⇐ S0 . S1 . D3 D1 ⇐ S2 + D2 D2 ⇐ (S3 + D2) . S0 D3 ⇐ D2 To overcome this, the present invention provides a display system having a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, a controller for controlling image data operations and extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes, and a separate interplane operation unit for performing operations, specified by the controller, on image data in at least two memory planes selected by the controller, the extended raster operation circuitry being so connected to the memory planes that the results thereof are written back to the frame buffer. Thus the bit manipulations are performed at the frame buffer level and not in the controller. The intraplane operation unit performs operations on image data in each of the memory planes, separately, while the interplane operation unit performs operations on image data in at least two memory planes selected by the controller. There are no restrictions as to the positional relation between the intraplane operation unit and the interplane operation unit, though the embodiment described hereinafter has the input from the plane passing to the intraplane logic, feeding, in turn, via a multiplexer, to the interplane logic which is coupled back to the memory planes. The Japanese Patent Unexamined Published Application No. 55 - 79,486 discloses a display device employing an inter-layer operation circuitry which performs interplane or inter-layer operations. The inter-layer operation circuitry, comprising a plurality of separate logical circuits, is provided between a frame buffer or a refresh memory and a TV monitor. The circuitry has no capability of writing the operation results back to the refresh memory, and therefore, cannot perform such complex logical operations as are mentioned above. The present invention will be described further by way of example with reference to embodiments thereof as illustrated in the accompanying drawings in which:- Figure 1 is a block diagram illustrating the structure of one form of display system according to the present invention; Figure 2 is a block diagram illustrating a concept of the interconnection between the frame buffer and the extended raster operation circuitry (EROP); Figure 3 is a block diagram illustrating a structure of the intraplane operation unit; Figure 4 is a block diagram illustrating a structure of the interplane operation unit; and Figure 5 is s circuit diagram illustrating an operation circuit for one bit. Fig. 1 illustrates a structure of a display system according to the present invention which is provided with a controller 10, such as a microprocessor, which controls the entire system, a frame buffer 12 which comprises a plurality of memory planes and into which image data to be displayed are written, extended raster operation circuitry (EROP) 14 which performs specified raster operations on the image data in the frame buffer 12, a display drive 16 which converts the images read out of the frame buffer 12 into an appropriate form to be displayed, and a display device 18, such as a CRT display, which visually displays the images. The controller 10 writes the images to be displayed into the frame buffer 12 and transfers operation commands to the EROP 14 through a bus 20. Upon receipt of the operation commands, the EROP 14 accesses the frame buffer 12 through a bus 22 and performs the specified raster operations. The images to be displayed in the frame buffer 12 are read into the display drive 16 under the control of the controller 10 to receive necessary processing such as an analog-digital conversion, and then displayed by the display device 18. Since the controller 10, the display drive 16, and the display device 18 are well known and are not directly related to the present invention, they are not detailed here. As illustrated in Fig. 1, the EROP 14 is divided into an intraplane operation unit 14A and an interplane operation unit 14B. The intraplane operation unit 14A, which, in isolation, corresponds to the conventional raster operation circuits, performs the operations in each individual one of the memory planes comprising the frame buffer 12. The interplane operation unit 14B, which is a hardware element that does not appear in known prior arrangements, performs those operations that involve more than one memory plane. Although, in the present embodiment, the frame buffer 12 comprises four memory planes, the present invention is not limited thereto, but may also be applied to other frame buffers comprising different numbers of memory planes in the similar manner. The frame buffer 12 and the EROP 14 may conceptually be interconnected as illustrated by Fig. 2. In the example illustrated by Fig. 2, the intraplane operation unit 14A comprises eight raster operation circuits ROP0 - ROP7. A first group of raster operation circuits ROP0 - ROP3 perform the specified operations on the data from the source areas in the planes 0 - 3 and predetermined pattern data B0 - B3 so that the respective planes are corresponded. A second group of raster operation circuits ROP4 - ROP7 perform the specified operations on the operation results C0 - C3 of the first group and the data D0 - D3 from the destination areas in the planes 0 - 3 so that the respective planes are corresponded. The operation results E0 - E3 of the second group are transferred to the interplane operation unit 14B, and the outputs F0 - F3 of the interplane operation unit 14B are written into the final destination areas or display areas in the planes 0 - 3. The operation of the circuitry illustrated by Fig. 2 may be expressed as follows. Ci ⇐ fj (Ai, Bi) E₁ ⇐ fk (Ci, Di) Fi ⇐ fe (E0, E1, E2, E3) In the above expressions, the i denotes the numbers of the memory planes and the fj, fk, and fe denote the specific logical functions, all of which are specified by the controller 10. In the example illustrated by Fig. 2, although the intraplane operation unit 14A is coupled sequentially to the interplane operation unit 14B, their positional relationship can be reversed. In that case, the interplane operation unit 14B would receive, as the input, the plane data A0 - A3 from the source areas and the operation results F0 - F3 would be input into the first group of raster operation circuits ROP0 - ROP3 together with the pattern data B0 - B3. The pattern data B0 - B3 represents contiguous patterns such as a checker-board pattern and is supplied directly from the controller 10 or have been stored in a dedicated pattern memory (not shown) together with other patterns. The pattern data also consists of four bits per pixel. The intraplane operation unit 14A comprises four raster operation circuits in each group. However, each group may be replaced by a single raster operation circuit so that the data in different planes may be sequentially supplied thereto, but is still operated on one plane's worth at a time. Further, the intraplane operation unit itself may be replaced by a single operation circuit. Fig. 3 illustrates an example of the structure of the intraplane operation unit 14A. In the illustrated example, the first and second groups of raster operation circuits are shown in blocks as "#1 ROP" and "#2 ROP," respectively. As stated above, each group may be replaced by a single operation circuit. The image data consisting of four bits per pixel read out of the frame buffer 12 (Fig. 1) are loaded into a buffer register 30 through the bus 22. In the present embodiment, it is assumed that one byte of image data are read out of each of the corresponding stored areas in the four memory planes of the frame buffer 12. Therefore, the buffer register 30 requires the capacity of at least four bytes (32 bits). The outputs of the buffer register 30 are connected to the one inputs of the first and second groups of raster operation circuits 32 (#1 ROP) and 34 (#2 ROP). The data A0 - A3 from the source areas are supplied to the first group 32, while the data D0 - D3 of the destination areas are supplied to the second group 34. A pattern register 36 receives the pattern data consisting of four bits per pixel from the controller 10 or a dedicated pattern memory (not shown) and supplies the pattern data B0 - B3 to the other inputs of the first group of raster operation circuits 32. The outputs of the first group of raster operation circuits 32 are connected to the other inputs of the second group of raster operation circuits 34 to supply the operation results C0 - C3 thereto. The second group of raster operation circuits 34 output the final operation results E0 - E3 of the intraplane operation unit 14A and transfer them to the interplane operation unit 14B. The commands which specify the operations to be performed in the first and second groups of raster operation circuits 32 and 34 as well as in the respective raster operation circuits in the interplane operation unit 14B, to be explained later, are transferred from the controller 10 to a command circuit 38 through the bus 20. Each of the raster operation circuits performs the operations specified with operation specifying signals, namely OP codes, from the command circuit 40. In the present embodiment, the OP codes, each consisting of four bits, can specify 16 types of operations, as shown in the following table : In the above table, the X and Y denote the inputs to each operation circuit (X denotes the left input and Y denotes the right input) and the Z denotes the output. Each of the inputs and output consists of one byte and the operations are performed so that the respective bits are corresponded. It would be convenient to render the meanings of the OP codes shown in Table 1 the same to all of the operation circuits. To the respective operation circuits in the interplane operation unit 14B to be described below, the command circuit 38 transfers plane selection signals together with the OP codes. It should be understood that the number and types of the operations which can be performed in the present invention are not limited to those shown in Table 1. Fig. 4 illustrates a structure of the interplane operation unit 14B according to the present invention. The interplane operation unit 14B consists of four operation circuits 40 (ROP8), 42 (ROP9), 44 (ROP10), and 46 (ROP11), each of which is provided for each of the planes, and four eight-bit-delay registers 48, 50, 52, and 54, each of which returns the output of each of the operation circuits back to one of the inputs thereof with the delay of one cycle. The one of the inputs of each of the operation circuits is connected to the output of the related delay register (D), while the other of the inputs thereof is connected to the outputs of the second group of raster operation circuits 38. The operations to be performed by the respective operation circuits 40 - 46 are specified with the OP codes from the command circuit 38. To cause the interplane operation unit 14B to operate, the command circuit 38 supplies the plane selection signals which specify the data of the planes to be manipulated in the respective operation circuits 40 - 46, together with the OP codes. Each of the plane selection signals consists of four bits, each bit corresponding to each of the different planes, and each of the operation circuits 40 - 46 receives, as an input, the data of the plane corresponding to "1" bit. The selection of the plane data may be performed with a multiplexer (not shown), for example. Each of the operation circuits 40 - 46 may be the same as each of the ROP0 - ROP7 illustrated in Fig. 2, except for the plane selection, and may be constituted with a general-purpose operation circuit or a program array logic. Fig. 5 illustrates an example thereof. The circuit illustrated by Fig. 5 performs the operation of the "i"-th bit (i = 0, 1, 2, ..., and 7), and therefore, such eight circuits are required for each of the ROP0 - ROP11. As seen from the figure, the logical function of the circuit may be expressed as follows. Zi ⇐ Xi . Yi . OP0 + X i . Yi . OP1 + X i . Yi . OP2 + X i . Y i . OP3 In the above expression, the Xi, Yi, and Zi denote the "i"-th bits of the X, Y and Z shown in Table 1, respectively and the OP0 - OP3 denote the four bits of an OP code to be supplied from the command circuit 38. In the present example, OP0 is the rightmost bit of the OP code and OP3 is the leftmost bit thereof. Thus, depending upon whether each of the OP0 to OP3 is 0 or 1, the operations shown in Table 1 are performed. The details of the operation of the circuit illustrated by Fig. 5 are clear from the face of the diagram and are not further explained. Example 1 : Extraction of Specified Colour In a colour display system, it is a basic function to manipulate the areas of one specific colour or the areas of the other colours on a colour image surface. In the prior art, as disclosed for example EP-A-xxxxxxx, 8410779, BC9-83-008, the comparison of colours has been performed with a dedicated comparator. However, in the context of the disclosed embodiments, this can be easily realised with general-purpose operation circuits. Now assume that the bit configuration of a pixel having a colour desired to be extracted in the image written into the frame buffer 12 is P0 = 1, P1 = 0, P2 = 1, and P3 = 1. The P0 - P3 denote the four memory planes comprising the frame buffer 12. Further, assume that the data representing the areas of the colour desired to be extracted are to be written into the plane 0 (P0). Fundamentally speaking, the extraction of a colour may be accomplished by inverting the image data of the planes having the "0" bits (P1 in the above example) among the four bits of the pixel having the specified colour, and then ANDing all the planes. In the present example, the final AND operation results are written into the plane 0 (P0). For the intraplane operation unit 14A, the controller 10 transfers, to the command circuit 38, the commands which cause the operation circuit ROP1 (or ROP5) corresponding to the plane 1 (P1) to perform the operation Z = X and cause the other operation circuits to perform the operation Z = X. In response to these commands, the command circuit 38 transfers the OP code "1100" to the ROP1 (or ROP5), and transfers the OP code "0011" to the ROP0, ROP2, ROP3, ROP4, ROP5 (or ROP1), ROP6, and ROP7. Thus, at the outputs of the intraplane operation unit 14A, the operation results of E0 = A0, E1 = A1, E2 =A2, and E3 = A3 are obtained. In case that the first and second groups of raster operation circuits 32 and 34 comprise respectively a single operation circuit, the command circuit 38 supplies the OP codes stated above in an appropriate sequence. For the interplane operation unit 14B, the controller 10 transfers, to the command circuit 38, the commands which cause the operation circuit ROP8 corresponding to the plane 0 (P0) to perform the operations and plane selections shown in the following table and cause the other operation circuits ROP9 - ROP11 to perform the operation of Z = "00": indicating that the operations of one byte are completed in four successive cycles. The operations may be expressed as follows using the symbols in Fig. 2: F0 ⇐ E0 . E1 . E2 . E3 If the two-dimensional size of the image including the areas of the specified colour is equivalently n bytes, it would be required to repeat n times the operations of the four cycles just shown. Since the ROP9 - ROP11 output only the bytes of all zeros in all of the cycles, the image data including only the areas of the specified colour are finally written into the final destination area or display area in the plane 0 (P0). In this case, the bit configuration of each pixel becomes "1000," differing from the original one "1011." Thus, in the present example, the areas of the specified colour have been extracted by converting the specified colour into another colour. If it is desired to extract it without such a conversion, it may be accomplished by causing also the ROP10 and ROP11 to perform the same operations. Example 2 : Synthesis of Images In case of monochromatic images, it is possible to synthesise more than two images among the different images written into the four planes, respectively, only by employing OR operations. For example, when the images in the plane 0 and the plane 1 are to be synthesised and written into the plane 3, the ROP0, ROP1, ROP4, and ROP5 are caused to perform the operation of Z = X and the ROP11 is caused to select the plane 0 and the plane 1 and perform the operations Z ⇐ X and Z ⇐ X + Y. In case of colour images, since only such OR operations may cause different colours to be produced in overlapping portions, it would be required to synthesise such images by giving priorities thereto. Namely, a colour image with a lower priority is synthesised only in the background area of another colour image with a higher priority. Since the background area can be extracted with the procedure of Example 1, the background area and the colour image with the lower priority are ANDed, and the results and the colour image with the higher priority are ORed, thereby to obtain a synthesised image. Particularly, now assume that a colour image having four colours (two bits per pixel) with higher priorities have been written into the plane 0 and the plane 1 and that another colour image having four colours with lower priorities have been written into the plane 2 and the plane 3, for example. When the bit configuration of a pixel in the background area is "1⊥" and a synthesised image is to be written into the destination areas in the plane 0 and the plane 1, the operation circuit ROP10, which corresponds to the plane 2 in the interplane operation unit 14B, is caused to perform the operation F2 ⇐ E0 . E1 . E2 and the operation circuit ROP11, which corresponds to the plane 3, is caused to perform the operation F3 ⇐ E0 . E1 . E3. These operations are similar to those shown in the previous table. However, since three planes are ANDed in this case, only three cycles are required for each byte. The operation results are written into the plane 2 and the plane 3, respectively. Next, the operation circuit ROP8, which corresponds to the plane 0, is caused to perform the operation F0 ⇐ E0 + E2 and the operation circuit ROP, which corresponds to the plane 1, is caused to perform the operation F1 ⇐ E1 + E3 thereby to obtain a synthesised colour image. Each of the operation circuits ROP0 - ROP7 in the intraplane operation unit 14A is specified to perform only the operation Z ⇐ X. Besides the above, various other applications of the disclosed arrangement are possible.

Claims: A display system having a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, a controller for controlling image data operations and extended raster operation circuitry comprising an intraplane operation unit for performing operations, specified by the controller, on image data in each of the memory planes, and a separate interplane operation unit for performing operations, specified by the controller, on image data in at least two memory planes selected by the controller, the extended raster operation circuitry being so connected to the memory planes that the outputs thereof are written back to the frame buffer. A display system as claimed in Claim 1, wherein the extended raster operation circuitry includes a buffer register for retaining image data read out of the frame buffer and a command circuit for receiving commands, from the controller, which specify operations to be performed by the circuitry and select memory planes. A display system as claimed in Claim 2, wherein the input of the intraplane operation unit is connected to the buffer register, the input of the interplane operation unit is connected to the output of the intraplane operation unit, and operation results of the interplane operation unit are written back to the frame buffer. A display system as claimed in Claim 2, wherein the input of the interplane operation unit is connected to the buffer register, the input of the intraplane operation unit is connected to the output of the interplane operation unit, and operation results of the intraplane operation unit are written back to the frame buffer. A display system as claimed in any preceding Claim, wherein the interplane operation unit consists of a plurality of operation circuits respectively corresponding to the plurality of memory planes, and a plurality of delay means respectively related to the plurality of operation circuits, each of the operation circuits receives, as the inputs, image data in a memory plane selected by the command and its own output delayed a predetermined period of time by the related delay means, and the final operation result only is written into the corresponding memory plane, directly or via the intraplane operation unit.

Inventors: HATTORI, ETSUO, IWAMI, TOMOYUKI, MIYAZAKI, YOSHIHIRO, OHBUCHI, RYUTAROH
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: G09G1
IPC codes: G06T1, G06T11, G06F3, G09G5