Synchronous array logic circuit

Abstract: Synchronous array logic circuitry and a system for automatically laying out such circuitry for the fabrication of integrated circuits are described. The synchronous array logic circuitry includes as many cells (10, 20...) as necessary to perform the desired functions with each cell including a transistor array (12) for evaluating a Boolean function and supplying the result to a storage element (18) through a multiplexer (15). The storage element (18) latches the output signal and supplies it to other transistor arrays and/or other cells. The transistor array (12) includes serially connected transistors for performing AND functions and parallel connected transistors for performing OR functions. The multiplexer (15) operates under control of a test signal to configure the storage elements serially, thereby enabling complete testability of all cells (10, 20). Our system includes a method for automatically laying out such circuitry. The method includes steps of arranging the storage elements (18) in a desired order, assigning transistors within a given cell to positions along a first axis, assigning transistors within the cell to a position along a perpendicular axis, and laying out an interconnecting diffusion path. Once all cells are specified, the cells may be interconnected in a desired manner.

Description: Field of the Invention This invention relates to a circuit for implementing logic functions and having built-in testability. A circuit which exhibits the features set forth in the preamble of claim 1 is described in the publication MICROPROCESSORS AND MICROSYSTEMS, vol. 10, # 3, April 1986, p. 139-147, London, GB. The design of the combinational logic circuit disclosed in this document is not discussed in detail. The publication IT/INFORMATIONSTECHNIK, vol. 28, # 3, 1986, p. 142-149, Munich, DE compares static and dynamic CMOS circuits and discloses clocked dynamic CMOS circuits having an evaluation phase and a hold phase. It is the object of the present invention to improve the testable circuit of the prior art by reducing the number of transistors and simplifying routing. Claim 1 defines the present invention while claim 2 defines a combination of such circuits. Description of an Embodiment Figure 1 is a block diagram of a portion of an integrated circuit Figure 2 is a schematic illustrating a conceptual layout of transistors within the array shown in Figure 1; Figure 3 is a series of timing diagrams illustrating the operation of the circuit of Figure 2; Figure 4 is a schematic illustrating the inventive alternate conceptual layout for the array of Figure 1; Figure 5 is a schematic illustrating a transistor array implementing a Boolean function; Figure 6 is a schematic illustrating the implementation of an equivalent Boolean function using fewer transistors; Figure 7 is a schematic illustrating in further detail the multiplexer and storage element shown in Figure 1; Figure 1 is a block diagram illustrating conceptually the manner in which integrated circuits are implemented. Figure 1 is a small portion of a much larger integrated circuit, and illustrates the circuit implementation of two Boolean equations. It will be appreciated that as many such portions as illustrated in Figure 1 may be combined to produce the overall functionality desired for the integrated circuit. Figure 1 includes two cells 10 and 20, each for implementing a single Boolean equation. Cells 10 and 20 are identical to each other at the level of the block diagram, and accordingly only cell 10 is described here. Cell 10 generally includes an array of transistors 12, a multiplexer 15, and a storage element 18. These elements are shown in block form; their components are described in detail below. Storage element 18 implements scan testability and synchronous operation of the cells with each other. Transistor array 12, which provides the means by which the logic function desired from cell 10 is implemented, is switchably connected between a power supply V DD and a lower potential V SS by transistors 21 and 22. Signal lines for a clock signal 25, a test signal 27 and signal Q (28) extend into cell 10 from exterior of the cell. If desired, a signal Q , the inverse of signal Q, could be supplied instead. Line 28 originates from a cell (not shown) preceding cell 10, or in the case when cell 10 is the first cell, from signals supplied from off the chip. Clock line 25 is driven by a well-known oscillator and is connected to supply a clock signal to storage element 18 and to transistor 21, while its inverse is supplied to transistor 22. For clarity, transistors 21 and 22 are shown outside array 12. In the actual circuitry, however, they are implemented within array 12 or within a clock buffer used to drive the clock lines. Multiplexer 15 is connected to storage element 18 to control the signals supplied to the storage element. Signals on test line 27 control multiplexer 15 and determine whether multiplexer 15 will supply to storage element 18 the signal Q on line 28, or the output signal from transistor array 12 received over line 30. Cell 10 may be operated in two different modes--normal and test. In normal operation the test line 27 will be off. Array 12, in response to signals supplied to its input nodes 35a, 35b, etc., will evaluate a Boolean equation and supply the result over line 30 to multiplexer 15. Because the test line 27 is off, multiplexer 15 will pass the result of that evaluation to storage element 18, which latches the array output signal, on output lines 32. Output line 32 is connected as an input line to the storage element in the next cell 20 and, typically, also provides one or more input signals to transistor arrays in other cells. If feedback is employed in the array 12, line 32 may even be connected to the originating array 12 in the same cell 10. During testing, the circuit shown within cell 10 in Figure 1 will be configured in a different manner under control of test line 27. A signal on this line will cause multiplexer 15 to allow the Q signal on line 28 to be supplied directly to storage element 18, ignoring the signal on line 30. In such a configuration a chain of storage elements in adjoining cells is created which acts as a shift register. The shift register allows complete testing of the integrated circuit, including the transistor arrays. Broadly speaking, the test data may be clocked into the circuitry using storage elements in shift register form. Then the system is switched into normal operation for one or more cycles to perform a specified operation. Finally, the system is returned to test mode, and the results of the specified operation clocked out to be compared with the data provided by a properly functioning circuit. This process may be repeated as many times as desired to verify proper functionality of all circuit components. Such test operation is discussed further below. In our system each transistor array supplies a single storage element, and each group of cells 10, 20, etc., receive the same clock signal. If necessary, a clock buffer circuit is employed to distribute the incoming clock signal to all of the desired storage elements. The clock signal is not restricted in the number of phases it may have, nor is there a restriction on whether the storage elements are dynamic or static. The essence of the cell 10 is transistor array 12. This transistor array, typically employing only N-channel transistors, performs the logical operation on the input signals 35, while storage element 18 saves the result. The array 12, like the Boolean equation it evaluates, may be of any desired size. The array usually will be in one of several different formats. The general structure of one embodiment of the transistor array 12 is shown in further detail in Figure 2. The array itself consists of "sticks" of buried diffusion 37 joined at the top and bottom, with the transistors, for example, transistors 42 and 43, on any one stick performing a logical AND function. The joining of the sticks at their tops and bottoms provides the logical OR function. For simple sum of products arrays, the number of sticks determines the width of the array and is equal the number of OR terms in the Boolean equation. The number of transistors in each stick determines the array height and represents the number of AND terms. Although theoretically unlimited, the size of the array actually is limited by circuit performance considerations. Furthermore, as discussed below, the size of the array may be reduced by factorizing. For the exemplary partial circuit shown in Figure 2, the lower node 52 will be connected to the upper node 50 if either (1) both transistors 42 and 43 are on or (2) transistor 44 and one of transistors 45 or 46 are on. Thus, the simple circuit shown evaluates the function: Output evaluates to zero if transistors 42 and 43 equal one, or if transistor 44 equals one and one of transistors 45 and 46 equals one. The operation of the circuit shown in Figure 2 is illustrated using timing diagrams in Figure 3. During the first-half clock cycle, while the clock signal Clk is high, the top node 50, and all other nodes connected to it by transistors which are on, are charged to a digital state high. This is the precharge phase. During the next half cycle, the bottom node 52, and all other nodes connected to it by transistors which are off, are discharged to a digital low. This is the evaluation phase. If a conducting path exists through the array from the top to the bottom nodes (i.e., all of the AND transistors in any one OR stick are on), then the top node will also be discharged to low. Upon the next clock edge, that is, immediately before the next precharge, the storage element will read the digital level at the top of the array, detecting whether it is high or low, and latching the result. Thus, using the storage element, the array output is stored and propagated to subsequent cells and arrays, and the array is freed for the next data and the precharge/evaluation cycle. For the hypothetical input data used in Figure 3, during cycles 1 and 2 a conducting path exists between nodes 50 and 52, and accordingly the node 50 is pulled low. No conducting path exists during cycle 3, and accordingly node 50 remains high. The precharge and evaluation functions may be carried out in several different ways. One such approach was shown in Figure 2, wherein each array includes a P-channel precharge transistor and an N-channel evaluation transistor. The alternate approach of the present invention is shown in Figure 4. As shown in Figure 4, each array includes an N-channel precharge transistor and communally uses the clock line as the evaluation node. Apart from lowering the number of transistors required, the approach of Figure 4 has advantages in layout and routing. Because the clock line goes through each cell (as shown in Figure 1), the clock line provides an easy linear target at the bottom of the array for automatic routing, unlike an evaluation transistor which is a point target. An example of "factorizing" to reduce the transistor count of an array is depicted in Figures 5 and 6. As shown in Figure 5, an array includes a first transistor 60 serially connected to a second transistor 62. These serially-connected transistors are themselves connected in parallel with third and fourth transistors 64 and 66. Each of transistors 60 and 64 receives an input signal designated A, while transistor 62 is controlled by signal B and transistor 66 by signal C. Thus, the output will match the input if either A and B or A and C are on. To implement the array in this manner requires four transistors. Figure 6 illustrates the concept of factorizing in which transistor 64 has been omitted and transistor 60 serially coupled to the parallel connected transistors 62 and 66. As a result this circuit implements the same function as in Figure 5 but with one fewer transistor. We employ factorizing to reduce the transistor count, improve speed, reduce load and reduce chip area in large arrays. The overall operating speed of the transistor array is limited by the precharge and evaluation times, which in turn are controlled by the loads inside the array to be charged and discharged. Larger arrays tend to operate more slowly than smaller arrays. The performance degrading features of an array are transistor conductivity and parasitic load. The on resistance will represent the conductivity of the transistors. As a result, the more series devices which are present the more capacitance to be charged and discharged and the more resistance for that capacitance to be charged and discharged through. A worst case occurs when only one of the AND paths is conducting and all but the bottom transistor of all other paths are OFF, thereby causing all of the parasitic capacitances to be discharged through a single transistor. Another factor which affects performance of the transistor array is the length of the interconnect diffusion between the transistors and the array. Longer lines of interconnect have more resistance and more capacitance. Additionally, array performance is affected by the delay between the precharge phase starting and the input signals to the array being valid. This is a result of the delay in signal propagation through the storage elements which causes an increase in the time that the clock must remain in the precharge phase. Accordingly, the maximum clock rate is limited by the sum of signal propagation delay, worst case precharge time, and worst case evaluation time. Figure 7 is a detailed schematic of the combination multiplexer 15 and storage element 18 shown in block form in Figure 1. For illustration, an amplifier stage has been added to the storage element 18 to illustrate one technique for amplifying the output signals from the storage element. Such amplification is necessary when the storage element is driving many other.transistor arrays or driving fewer arrays spaced far from the storage element. The purpose of the storage element is to synchronize the transistor arrays in all of the cells of the integrated circuit, as well as provide a scan path for testing. The storage element stores the result of an evaluation, and amplifies the result for subsequent stages. The output from a transistor array evaluation is stored by the circuit which behaves like an edge-triggered d-type latch. The storage elements themselves may be of dynamic or static design. The dynamic circuits are smaller and faster, while the static circuits provide the opportunity for stopping the system clock. The central portion of the circuit shown in Figure 7 and designated "Dynamic Storage Element (Latch)" operates from a single clock signal, is compact for layout, and includes amplification stages. The amplifier circuit on the right side of Figure 7 is employed to compensate for large loads. This amplification is particularly critical in very large scale integrated circuits because the overhead of the interconnecting routing is so great. Figure 7 also shows in detail the multiplexer which controls which signals are supplied to the storage element. If the Test signal is supplied, then the storage element receives the signal from the node designated Scan Input, while if Test is not present, the storage element line 120 is coupled to the transistor array. It should be appreciated that the circuitry shown in Figure 7 is only for the purpose of explanation. Other well known circuits may be employed as latches, multiplexers, or in place of the amplifier shown. For example, stages may be eliminated from the storage element and the amplifier for small loads. The operation of the circuit depicted in Figure 7 is as follows. When the test signal is asserted, transistor 100 is turned on and transistor 101 turned off to cause the scan input signal to be supplied on line 120 to the storage element. Alternatively, in normal operation, when the test signal is off, transistor 101 is on and transistor 100 off to cause the signal from the array to be supplied on line 120 to the storage element. The dynamic storage element latches the signal presented it on line 120 onto line 130. After the signal is latched on line 130, it may be supplied directly to downstream storage elements and to other transistor arrays elsewhere on the chip. In the event that the loading on line 130 exceeds the capability of the storage element, an amplifier may be provided. A typical amplifier is depicted in Figure 7, although it will be appreciated that other amplifiers may also be employed. Ultimately, the amplified output signal is supplied on line 140 to the next storage element. If an inverted output signal is desired, a well known inverter may be driven by line 140.

Claims: A circuit comprising: a test node (27); a clock node (25); a scan input node (28); a scan output node (32); a storage element (18) connected to the clock node and to the scan output node; and switching means (15) connected to the test node, the scan input node, and the storage element; characterized by a first node for receiving a first source of positive electrical potential (V DD ); precharging means including a N-channel transistor responsive to a clock signal provided on the clock node and connected between said first node and a top node; an evaluation node directly connected to said clock node; an array (12) of transistors for evaluating a Boolean function connected between said top node and said evaluation node, wherein said top node will be connected to said evaluation node if a conducting path exists through the array; and wherein said switching means is also connected to said array so that said switching means supplies, under control from the test node, signals from said scan input node or from said top node to said storage element. A circuit combination comprising at least a first and a second circuit each having the features set forth in claim 1, wherein said scan output node (32) of said first circuit (10) is the scan input node of said second circuit (20), all circuits in the combination sharing said test node (27) and clock node (25). A circuit as recited in claim 1 or claim 2 wherein the storage element comprises a latch. A circuit as recited in claim 1 or claim 2 wherein the switching means comprises a multiplexer. A circuit as recited in claim 1 wherein the array is further characterized by: ones of the plurality of transistors (42, 43) for implementing AND functions being serially connected; and ones of the plurality of transistors (45, 46) for implementing OR functions being parallel connected. A circuit as recited in claim 1 wherein each transistor in the array has a control gate; and all transistors (60, 64) in the array corresponding to the same term in the Boolean function have commonly connected control gates.

Inventors: BAHRA AVI SINGH, COOKE DAVID, GILL JASPAL SINGH, GLENNON MICHAEL JOSEPH, HESKETH JOHN ALBAN, MCVICAR ALISON C, REES DAVID B, ROSS NIGEL KEIR, TURNBULL KEITH WARWICK, WARREN ROBERT G, BAHRA, AVI SINGH, COOKE, DAVID, GILL, JASPAL SINGH, GLENNON, MICHAEL JOSEPH, HESKETH, JOHN ALBAN, MCVICAR, ALISON C., REES, DAVID B., ROSS, NIGEL KEIR, TURNBULL, KEITH WARWICK, WARREN, ROBERT G.
Applicants: FAIRCHILD SEMICONDUCTOR, FAIRCHILD SEMICONDUCTOR CORPORATION
Application year: 1987
Main classification: H03K19
IPC codes: H03K19, H01L27, G01R31, H01L21, G06F17