METHOD OR SYSTEM FOR PROCESSING IMAGE DATA

Abstract: Disclosed is a method of processing image data, including controlling to output multi-level value image data for reproducing a multi-level value image and bi-level value image data for reproducing a bi-level value image with respect to a predetermined area, thereby reproducing the multi-level and bi-level value images which constitute a single image. Also disclosed is an interface system including a multi-level converter for converting the multi-level value image data into the bi-level value image data and vice versa, a resolution converter operated in synchronism with the multi-level converter to convert a resolution of the multi-level value image data, an area data memory for storing area data corresponding to an instruction input representing a multi-level or bi-level value image area, and an output device for selecting the multi-level value image data from the resolution converter or the multi-level value image data from the multi-level converter on the basis of the area data and for outputting selected data to the image output device.

Description: The present invention relates to a method and apparatus for processing composite image data. In particular it concerns a method of processing image data for producing an image that is a composite of line-image and tone-graphic features, which method comprises: providing multi-bit digital first data representing respective pixels of at least the tone-graphic features amongst the composite of features; providing single-bit digital second data representing respective pixels of at least the line-image features amongst the composite of features; and using the first and second data to provide output third data representing respective pixels of the composite of line-image and tone-graphic features. It also concerns image processing apparatus for providing output data for producing an image that is a composite of line-image and tone-graphic features, the apparatus comprising: first means for providing multi-bit digital first data representing respective pixels of at least the tone-graphic features amongst the composite of features; second means for providing single-bit digital second data representing respective pixels of at least the line-image features amongst the composite of features; and third means co-operative with both of the first means and the second means for using the first and second data to provide output third data representing respective pixels of the composite of line image and tone graphic features. Typically conventional image data processing systems are directed to two types of system, that is, a processing system for processing bi-level value (i.e. single-bit digital) image data for line image features such as in documents, characters, and drawings and a multi-level value (i.e. multi-bit digital) image data processing system for processing the tone graphic features of a halftone image (a multi-level value image) such as a photograph. The bi-level value image data processing system primarily aims at improvement of resolution rather than that of gradation expression. The multi-level value image data processing system primarily aims at improvement of gradation expression rather than that of resolution. When an image including characters and a photograph is to be input to a conventional image processing system, gradation (or reproducibility of gray scale levels) of the photograph area is limited in the bi-level value image data processing system whilst the resolution of the character area is low in the multi-level value image data processing system. Multi-level value image data can be expressed in a pseudo halftone mode by converting the same into bi-level value image data using either a dither method or a density pattern method. However, such conventional techniques have limitations, gradation and resolution are undesirably impaired, and a moire pattern is often formed. Consequently, image degradation inevitably occurs. Examples of these methods are given in GB 2160738A and EP-A2-0122430 each of which is discussed below. GB 2160738A concerns a method and an apparatus for processing image data for the common purpose of producing an image that is composite of both line image and tone graphic features. An original on a drum is scanned using collocated sensors and line image and tone graphic analogue signals produced. The line image signal is amplified and passed to a comparator where it is converted into bi-level value data. Optionally this is stored in a memory. In parallel with this, the tone graphic signal is converted by an analogue to digital converter to multi-level value data and then passed to a half tone dot generating circuit i.e. a density pattern generating circuit, wherein it is converted to bi-level value data. Either line image or tone graphic bi-level value data is then selected by means of a switching circuit and is used to drive an exposure head thereby to produce an image on a photosensitive medium carried on a recording drum. The operation of the switching circuit is co-ordinate driven. Optionally a memory may be provided in the processing channel for processing the tone graphic image signals. This may be an alternative to the memory already mentioned, or may be used in conjunction therewith. EP-A2-0122430 concerns an image processing apparatus in which line image data is stored as high resolution single bit data in an image memory and tone graphic image signals are stored in a multi-level value format in an image buffer memory. Tone graphic image signal is converted from multi-level value data to bi-level value data using a dither circuit. The output data for producing the image passes through a common OR gate and is all of single level value. Another conventional technique is also available to recognise character and halftone areas of document data and to reproduce only the halftone area in a pseudo halftone mode. However, gradation and resolution are inevitably degraded. The present invention provides both a method and an apparatus for producing images of high quality and which avoid the drawbacks just mentioned. The method of processing image data is, in accordance with this invention, characterised by steps which include converting the single bit digital data representing line image features of the composite into multi-bit digital data and producing multi-bit digital output data from this and the multi-bit digital data representing tone graphic features. The image processing apparatus is characterised by conversion means and processing means for performing the steps of converting the single-bit digital data and of producing multi-bit digital output data. There is also provided in accordance with a further aspect of this invention an image processing apparatus comprising memory means structured and arranged to store therein data representing a plurality of pixels of image data, each such pixel being represented by a respective multi-bit digital datum, and data representing a plurality of pixels of image data, each such pixel being represented by a respective single-bit datum; characterised by: output means for reading from said memory means and for outputting, as multi-bit digital data, each datum representing one pixel, both the multi-bit digital data and the single-bit digital data stored in said memory means. Since the output data for tone graphic features is multi-level valued and is produced from multi-level valued data, these features can be expressed with good gradation. Also, although the output data for line image features is multi-level valued, it is produced from bi-level valued data and sharpness and high contrast is nonetheless preserved. In the drawings accompanying this specification: Figs. 1 and 6 are block diagrams of data processing systems according to an embodiment of the present invention; Figs. 2-1 and 4 are plan views showing display contents; Figs. 2-2 and 5 are views for explaining selection signals; Fig. 3-1 is a block diagram showing a selection control circuit; Fig. 3-2 is a timing chart for explaining the operation of the selection control circuit shown in Fig. 3-1; Fig. 3-3 is a view showing the structure of a memory; Figs. 7 and 8 are views for explaining a technique for supplying a selection signal (SEL SIG) which designates the type of logical operation; Fig. 9 is a table showing the relationship between the selection signals and logical operations; Fig. 10 is a table showing actual results of the logical operations; Fig. 11 is a perspective view of an image data processing system according to another embodiment of the present invention; Fig. 12 is a block diagram of the image data processing system shown in Fig. 11; Fig. 13A is a view for explaining operation (shift) of a BMU 117 shown in Fig. 12; Fig. 13B is a view for explaining operation (extraction) of the BMU 117 shown in Fig. 12; Fig. 14 is a block diagram showing the detailed arrangement of an SP-I/F 114 shown in Fig. 12; Fig. 15 is a view for explaining a technique for causing an operator to designate a character area and a photographic area; Fig. 16 is a view for explaining a technique for causing an image area separating circuit 139 to automatically designate a character area and a photographic area without designation by an operator; Figs. 17 to 20 are flow charts for explaining the control sequence of the image data processing system shown in Fig. 11; Fig. 21 is a view for explaining recording of an image including character and photographic areas in an OD 105; Figs. 22-1 and 22-2 are flow charts for explaining an operation for printing out image data recorded in the OD 105; Fig. 23 is a block diagram of an image processing system employing an interface circuit according to still another embodiment of the present invention; Fig. 24 A is a view showing image data input from an image scanner; Fig. 24 B is view showing print-out image data representing that the photographic area of image data of Fig. 24A is shifted; Figs. 25 (a) to 25(e) are views showing image editing procedures and changes in states of buffers during image editing; and Fig. 26 is a block diagram showing a modification of the image processing system employing the interface circuit shown in Fig. 23. So that this invention can be better understood, embodiments thereof will now be described and reference will be made to the drawings. The description that follows is given by way of example only. Fig. 1 is a CRT display system according to a first embodiment of the present invention, in which bi-level value image data such as character and graphic patterns and multi-level value image data such as photographs are simultaneously displayed, and an area of multi-level value image data can be arbitrarily designated. A recording medium 1 stores a multi-level digital video signal (e.g. 4 bits/pixel) for displaying multi-level value image data. This medium will be referred to as a multi-level value memory 1 hereinafter. A recording medium 2 stores a bi-level digital video signal (1 bit/pixel) for displaying bi-level image data. This recording medium will be referred to as a bi-level value memory 2 hereinafter. A multi-level-digital video signal 3 is then read out from the multi-level value memory 1. A data selector 6 selects the multi- or bi-level digital video signal 3 or 4 in response to a selection signal 5. The signal selected by the data selector 6 is converted into an analog signal by a D/A converter 7. An amplifier 8 amplifies the analog video signal converted by the D/A converter 7 and the amplified signal is used to luminance-modulate a CRT 9. The CRT 9 is operated in response to vertical (V) and horizontal (H) sync signals 10. A multi-level value reading signal 11 instructs the read of data from the memory 1 and also is used as an address signal for the memory. A bi-level digital video signal 4 is read out from the bi-level value memory 2. A bi-level value reading signal 12 instructs the read of data from the memory 2 and also is used as an address signal for the memory. A control circuit 13 controls the read/write from and into the memories 1 and 2, and the selection of the memory 1 or 2. Fig. 2-1 shows a case wherein multi-level value data in a rectangular area is displayed in bi-level value data, and Fig. 2-2 shows addressing of the rectangular area. Fig. 4 shows a case wherein multi-level value data in a free area is displayed in bi-level value data, and Fig. 5 shows a memory for control of addressing of the free area. The operation for displaying the pattern shown in Fig. 2-1 will be described. In this case, parameters WX, WY, WW, and WH shown in Figs. 2-2 are given before-hand. The multi- and bi-level value reading signals 11 and 12 are output in response to the sync signals 10, so that the multi- and bi-level value signals 3 and 4 are respectively output from the multi- and bi-level value memories 1 and 2. The bi-level digital video signal 4 is first selected in response to the selection signal 5. When a point represented by the parameters WX and WY is obtained, the multi-level digital video signal 5 is selected correspondingly to a width represented by the parameter WW. When this operation is performed by the number of lines designated by the parameter WH, the display screen shown in Fig. 2-1 can be obtained. The above operation will be described in more detail to readily understand it with reference to a circuit of Fig. 3-1 and a timing chart of Fig. 3-2. Referring to Fig. 3-1, X and W counters count pixel clocks CL, i.e., dots. The X counter aims at obtaining a point represented by the parameter WX, and the W counter aims at obtaining a point represented by the parameter sum (WX + WW). The Y and H-counters count pulses of the horizontal sync signals HSYNC, i.e., the lines. The Y counter aims at obtaining a point represented by the parameter WY, and the H counter aims at obtaining a point represented by the parameter sum (WY + WH). The parameters WX, WW, WY, and WH are respectively preset in the X, W, Y, and H counters. The location of the multi-level value image in the X and Y directions can be changed in accordance with values represented by the parameters WX, WW, WY, and WH. These counters and a circuit for generating the selection signal in response to the outputs from the counters are included in the control circuit 13. Assume that data are read out from memory areas at addresses of the memories 1 and 2 which correspond to origin O, and that origin O is defined as a display start reference point and corresponds to the vertical sync signal VSYNC. The X counter starts counting pixel clocks in response to the vertical sync signal HSYNC. When the count of the X counter reaches a value of the parameter WX, a flip-flop FF2 is set. The W counter starts counting in response to the count corresponding to the value of the parameter WX. When the count of the W counter reaches a value of the parameter WW, the flip-flop FF2 is reset. As shown in Fig. 3-2, an output from the flip-flop FF2 serves as an H selection signal 5″. However, a display position does not reach a point represented by the parameter WY in the vertical (V) direction, and memory read access is not yet performed. When the Y counter starts counting in response to the vertical sync signal VSYNC and line scanning progresses to cause the count of the Y counter to correspond to a valve represented by the parameter WY, a flip-flop FF1 is set. At the same time, the H counter starts counting. When the count of the H counter reaches a value corresponding to the parameter WH, the flip-flop FF1 is reset. As a result, an output from the FF1 serves as a vertical (V) selection signal 5′. The H selection signal 5″ serves as the selection signal 5 (i.e., an output from a gate G1) supplied to the data converter 6 while the V selection signal 5′ is output. When the selection signal 5 is set at "1", the multi-value digital video signal is reproduced and output in place of the bi-level digital video signal. It should be noted that the multi-level value reading signal 11 may be output in response to the first transition into "1" (WX1 in Fig. 3-2) of a frame in the selection signal 5 and then read access of the multi-level value memory 1 may be initiated. In this case, a specific halftone image to be reproduced can be displayed or printed out in an arbitrary position. The control circuit 13 outputs address data for address 0 and subsequent addresses of the multi-level value memory 1 at a point (Fig. 2-2) defined by the parameters WX and WY. If the magnitudes of the parameters WW and WH correspond to the size of the multi-level value memory 1, the capacity of the memory 1 can be reduced (Fig. 3-3). It is therefore convenient to display a portrait or the like. In this case, the read line of the memory 1 is shifted by one line in the Y direction whenever the selection signal 5 is changed to "1". The halftone data represented by the multi-level value data from the memory 1 may be fitted in the area represented by the parameters WW and WH. As shown in Fig. 5, a control memory may be arranged in which the areas represented by logic "1" and logic "0" are predetermined. The contents of the control memory are output as the selection signal 5. If the selection signal 5 is set at "0", the bi-level digital video signal 4 is selected. However, when the selection signal 5 is set at "1", the multi-level digital video signal 3 is selected, thereby obtaining the display contents of Fig. 4. The control memory will be described as an image area memory later. The above operation applies to the case wherein bi-level digital video data is displayed in the multi-level digital video data, as shown in Fig. 6. In Fig. 6, a selection signal 5 instructs to select the type of logical operation for the multi- and bi-level digital video signals 3 and 4. A logical operation unit 6 performs a logical operation between the multi- and bi-level digital video signals 3 and 4. Other arrangements in Fig. 6 are the same as those in Fig. 1. Figs. 7 and 8 show techniques for supplying the selection signal 5 shown in Fig. 6. Fig. 9 shows a relationship between the selection signals and the types of logical operations. Fig. 10 shows actual results of the logical operations. As shown in Fig. 7, the type of logical operation is to be changed in the rectangular area, parameters WX, WY, WW, and WH are preset. When the multi- and bi-level value reading signals 11 and 12 are output in response to the sync signals 10, the multi- and bi-level digital video signals 3 and 4 are respectively output from the multi- and bi-level value memories 1 and 2. When the selection signal 5 is set at "0", the AND operation between the multi- and bi-level digital video signals 3 and 4 is performed by the logical operation unit 6. When the selection signal 5 is set at "1", the OR operation per bit between the multi- and bi-level digital video signals is performed by the logical operation unit 6. Furthermore, if area assignment of the control memory is determined, as described above, and the contents of the control memory serve as the selection signals 5, four logical operations in Fig. 9 can be performed in units of areas. An output from the logical operation unit 6 is converted by a D/A converter 7, and an analog signal from the D/A converter 7 is amplified by an amplifier 8. An output from the amplifier 8 is displayed on a CRT 9. Other logical operations in addition to those shown in Fig. 9 may be used. If one of the multi- and bi-level video signals 3 and 4 has a priority over the other, switching between the multi- and bi-level values can be performed as described above. Negative/positive conversion can be easily performed by bit inversion. Fig. 11 is a perspective view of an image data processing system according to a second embodiment of the present invention. The image data processing system recognizes a multi-level value image area and a bi-level value image area in an original image and store the multi- and bi-level value data. The image data processing system includes a controller 101, a keyboard 103, a CRT 104, an optical disk (to be referred to as an OD hereinafter) 105, an image scanner 106, and an image printer 107. A pointing device 102 such as a mouse is connected to the keyboard 103. The CRT 104, the keyboard 103, and the pointing device 102 constitute an operation unit. The controller 101 controls the OD 105, the image scanner 106, and the image printer 107 in accordance with a command from the operation unit and performs image processing. It should be noted that the CRT 104 preferably has a high resolution e.g (400 dots/cm(1000 DPI)). Fig. 12 is a block diagram of the image data processing system shown in Fig. 11. A portion surrounded by the alternate long and short dashed line in Fig. 12 defines the controller 101. A CPU (central processing unit) 110 executes control programs stored in a PMEM (program memory) 113 and controls the image data processing system. The PMEM 113 stores the control programs and various control data such as a control flag. The control programs are shown in Figs. 17 to 20. A DISK-I/F (disk interface) 111 controls an HD (hard disk) 120 and an FD (floppy disk) 121 in accordance with an instruction from the CPU 110. The control programs to be stored in the PMEM 113 may be loaded from the HD 120 or the FD 121. An OD I/F (optical disk interface) 112 controls the OD 105 in accordance with an instruction from the CPU 110. An SP-I/F (scanner/printer interface) 114 controls the IS (image scanner) 106 and the IP (image printer) 107 in accordance with an instruction from the CPU 110. The detailed arrangement of the SP-I/F 114 will be described in Fig. 14. A KEY-I/F (keyboard interface) 115 serves as an interface for signalling operating states of the keyboard (KEY) 103 and the PD (pointing device) 102 to the CPU 110. The CPU 110 detects an operating state of the PD 102 and controls the position of a cursor displayed on the CRT 104 to be described later. A VMEM (video memory) 116 stores image data displayed on the CRT 104. The VMEM 116 reads out image data in response to a sync signal for the CRT 104 and converts the image signal into a raster signal. The raster signal is supplied to and displayed as an image on the CRT 104. A LAN-I/F (local area network interface) serves as an interface for exchanging data with other devices through a LAN (local area network) 122. An ICU (image compression unit) 119 is a unit for compressing or expanding an image according to an MMR (modified modified READ) scheme used in a FAX (facsimile system). The ICU 119 is used to store an image in the OD 105. <BMU Function> A BMU (bit manipulation unit) 117 transfers image data in a rectangular shape and performs image processing such as enlargement, reduction, or rotation. The BMU 117 also performs logical operations between the transfer source image data and the transfer destination image data. The logical operations are logical AND and OR operations between pixels. All the above image processing operations can be performed at bit boundaries. Fig. 13A is a view for explaining image enlargement/transfer as an operation of the BMU 117 shown in Fig. 12. An image memory 170 corresponds to IMEMs 131 and 132 to be described later. Image data of a transfer source area 140 in Fig. 13A is enlarged through the BMU 117 and the enlarged image data is transferred to a transfer designation area 141. Fig. 13B shows another application of the BMU 117 in Fig. 12. An image data extraction function is affected such that a 160 dot/cm (400-DPI) image is displayed on the CRT 104 (the resolution is 40 dots/cm (100 DPI) in this embodiment). If image data having a resolution of 160 dots/cm (400 DPI) is stored in the image memory 170, it is read out and extracted to reduce to 1/4. The image signal is thus converted into image data having a resolution of 40 dots/cm (100 DPI). This image data is transferred to the VMEM 116 for displaying it on the CRT 104. In this case, the BMU 117 discards three pixels every four pixels in both X and Y directions, thereby reducing the image data to 1/4. In this embodiment, the 160 dots/cm (400-DPI) image read by the IS 106 is displayed and monitored on the CRT 104 because the operator can visually distinguish the bi-level value image area from the multi-level value image area in the read image. <Sp-I/F Function> The function of the SP-I/F114 is the characteristic feature of this embodiment. Fig. 14 is a block diagram showing the detailed arrangement of the SP-I/F 114 in Fig. 12. Referring to Fig. 14, an SPC (scanner/printer controller) 130 having a control function communicates with the IS 106 and the IP 107 in accordance with an instruction from the CPU 110 and controls circuits (to be described later) in the SP-I/F 114. A bi-level value IMEM (bi-level value image memory) 131 stores bi-level value image data and has a bit density of 160 dots/cm (400 DPI). A multi-level value IMEM (multi-level value image memory) 132 stores multi-level value image data and has a pixel density of 40 dots/cm (100 DPI). An image area MEM (image area memory) 133 stores image recognition data for recognizing the character (bi-level value)/photograph (halftone) image area and has a bit density of 160 dots/cm (400 DPI). An output operation (i.e., output to the printer (IP) 107) is taken into consideration. A bi-level digitalizing circuit 134 converts bi-level value image data stored in the bi-level value IMEM 131 into 8-bit multi-level value data. "0" is converted to "0", and "1" is converted to "255" according to MIN/MAX conversion. An interpolating circuit 135 linearly interpolates the multi-level value image data stored in the multi-level value IMEM 132 and having a resolution of 40 dots/cm (100 DPI) and converts it into multi-level value image data having a resolution of 160 dots/cm (400 DPI). A combining circuit 137 selectively combines image data from the bi-level digitalizing circuit 134 and the interpolating circuit 135 in accordance with the image recognition data from the image area MEM 133. The combining circuit 137 also calculates a logical OR or AND of the image data from the bi-level digitalizing circuit 134 and the interpolating circuit 135 in accordance with an instruction from the SPC 130. Therefore, the image data output from the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133 are finally set to be 160 dots/cm (400 DPI). In the SP-IF 114 bi- and multi-level value images are neither compressed nor expanded at the time of output/reproduction. Since the image area MEM 133 has a bit density of 160 dots/cm (400 DPI), the bi-level value image stored in the bi-level value IMEM 131, the multi-level value image stored in the bi-level value IMEM 132, and the image recognition data stored in the image area MEM 133 and representing the type of image are given in one-to-one correspondence. Of the reproduced images output to the IP 107, the bi-level value image component corresponds to the bi-level value image data stored in the bi-level value IMEM 131 and multi-level value image component corresponds to the multi-level value image data stored in the multi-level value IMEM 132. <Input to SP-I/F> An input from the image scanner (IS) 106 will be described below. A binarizing circuit 136 compares 8-bit 160 dots/cm (400-DPI) multi-level value image data from the IS 106 with a predetermined slice level (a fixed threshold value) and converts the multi-level value data into 160 dots/cm (400-DPI) value image data. The resultant image data is stored in the bi-level value IMEM 131. The IS 106 causes a CCD or the like to read document data and converts the read data into a digital signal, thereby outputting multi-level digital image data representing halftone data according to 256 gray scale levels. An extract circuit 138 receives multi-level value image data having a resolution of 160 dots/cm (400 DPI) from the IS 106 and calculates an average density of 16 (=4 x 4) pixels. The average density is defined as a density of one pixel, and the 160 dots/cm (400-DPI) multi-level value image data is converted into 40 dots/cm (100-DPI) image data. Therefore, the 8-bit data/dot is stored in the multi-level value IMEM 132. An image area separating circuit 139 analyzes the features of the multi-level value image from the IS 106 and separates the image into character and photographic areas. Image recognition data of logic "0" is assigned to the character area, and that of logic "1" is assigned to the photographic area. The data are stored in the image area MEM 133 correspondingly to each pixel (dot). In this case, it should be noted that data are parallelly or simultaneously input to the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133. The image recognition data is stored in the image area MEM 133 by the image area separating circuit 139. In addition, the image recognition data is stored as follows. The operator designates a halftone image area with the pointing device 102 while observing an image monitored on the CRT 104, and image recognition data associated with the designated area is written in the image area MEM 133 through a bus BUS under the control of the CPU 110. In the image area separating circuit 139, an 8-bit image signal (per pixel) read by the IS 106 is filtered by a differential filter or the like. If a sum of filtered outputs within the predetermined area exceeds a predetermined value, the central pixel within the predetermined area is detected as a pixel of the bi-level value image. In this case, the value for the image area MEM 133 which corresponds to the predetermined area is set to be "0". The bi-level value image data stored in the bi-level value IMEM 131 is stored as image data most suitable for bi-level value images such as character images. The image data stored in the multi-level value IMEM 132 is most suitable for halftone images. If an image such as a photograph is stored in the bi-level value IMEM 131, or a bi-level value image is stored in the multi-level value IMEM 132, it is not suitable to output the stored contents without conversion. However, in this embodiment, the image areas can be switched in response to the image recognition data. The above description has been made for the overall arrangement of this embodiment. This embodiment will be described in more detail below. Two operation modes, two input modes for inputting images from the IS 106 while image recognition data is being input to the image area MEM 133, each output mode for outputting image to the IF 107 or CRT 104 in accordance with the recognition data stored in the image area MEM 133, and an application with an optical disk will be exemplified below. <Operation Mode : Fig. 15> Referring to Fig. 15, an image 150 including a character portion 152 and a photographic portion 151 is read by the IS 106 and the read image components are stored in the bi- and multi-level value IMEMs 131 and 132. The data stored in the bi-level value IMEM 131 is displayed on the CRT 104. The operator can designate a photographic area 153 while visually observing an image displayed on the CRT 104. Image recognition data of "1" corresponding to the area 153 is defined as data 154 in the image area MEM 133. The character portion is read out from the bi-level value IMEM 131, and the photographic portion is read out from the multi-level value IMEM 132, and the composite image is displayed on the CRT 104. As described above, in a state wherein corresponding data are stored in the bi- and multi-level value IMEMs 131 and 132, the bi-level vlaue image data stored in the bi-level value IMEM 131 has good reproducibility of characters but good reproducibility of a photograph. The multi-level value image data stored in the multi-level value IMEM 132 has good reproducibility of a photograph but poor reproducibility of characters. An excellent image is including character and photographic portions finally displayed on the CRT 104. <Operation Mode : Fig. 16> Necessary data read by the IS 106 and stored in the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133 are parallelly or simultaneously read out in accordance with the image recognition data 154 stored in the image area MEM 133. An image having character and photographic portions having high quality is displayed on the CRT 104. In this case, the recognition data 154 stored in the image area MEM 133 is automatically generated by the image area separating circuit 139 without a manual operation. <Input Control Sequence : Fig. 17> Referring to Fig. 17, an image 150 is read by the IS 106 and the read image components are stored in the bi- and multi-level value IMEMs 131 and 132. The data stored in the bi-level value IMEM 131 is displayed on the CRT 104, and the operator designates the photographic area 153 while visually observing the image displayed on the CRT 104. Image recognition data corresponding to the area 153 is stored in the image area MEM 133. In step S2, the CPU 110 instructs the IS 106 to read the image via the IS 106. The SPC 130 communicates with the IS 106 and instructs to cause the IS 106 to read the image. The contents in step S4 are performed in the SP-I/F 114, as described above. The IS 106 reads the image in accordance with the instruction and outputs 8-bit (per dot) 160 dots/cm (400-DPI) multi-level value image data. This data is simultaneously supplied to the binarizing circuit 136 and the extract circuit 138. The image data binarized by the binarizing circuit 136 is stored in the bi-level value IMEM 131 as the bi-level value image data having a resolution of 160 dots/cm (400 DPI). The image data, the resolution of which is converted by the extract circuit 138, is stored in the multi-level value IMEM 132 as the multi-level value image data having a resolution of 40 dots/cm (100 DPI). The bi-level value image data from the bi-level IMEM 131 is resolution-converted by simple extraction by means of the BMU 117. As a result, 40 dots/cm (100-DPI) bi-level value data for the CRT 104 is transferred to the VMEM 116 in step S6 and is displayed on the CRT 104 in step S8. The operator manipulates the PD 102 to designate the photographic portion 151 while visually observing the image on the CRT 104 and designates the photographic area or frame 153 (step 10). Image recognition data corresponding to the designated photographic area is stored in the image area MEM 133 (step 12). <Input Control Sequence : Fig. 18> Unlike in the control sequence of Fig. 17, Fig. 18 shows a control sequence for automatically obtaining image recognition data without a manual operation. The operation in step S20 is the same as that of step S2 in Fig. 17. When the original or image 150 including the photographic and character portions 151 and 152 is read in step S22, the read image components are simultaneously stored in the bi- and multi-level value IMEMs 131 and 132 through the binarizing circuit 136 and the extract circuit 138. The image recognition data recognized by the image area separating circuit 138 is also stored in the image area MEM 133. The image recognition data 154 corresponding to the photographic portion 151 is set at logic "1". The input sequences of this embodiment has been described above. The input sequences allow a large decrease in the number of multi-level value image data input from the IS 106, and the resultant multi-level value image data is stored in the image memory, which is the characteristic feature of the present invention. The bi-level value image can be compressed without sacrificing its resolution by its nature. Even if the resolution is degraded, no problem occurs in the multi-level value image. Therefore, the number of bits of the images can be reduced by sacrificing the resolution. <Output to CRT 104 : Fig. 19> A sequence for outputting data to the CRT 104 will be described with reference to Fig. 19. Predetermined data are stored in the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133. In step S30, the contents of the image area MEM 133 are read out by one pixel. The CPU 110 determines in step S32 whether the contents represent "0" or "0". If "0" is determined, the contents represent the bi-level value image (i.e., a character image). In step, S34, the CPU 110 causes the BMU 117 to convert the 160 dots/cm (400-DPI) bi-level value image data in the bi-level value IMEM 131 into 40 dots/cm (100-DPI) data (Fig.13B). The 40 dots/cm (100-DPI) data is transferred to the VMEM 116. However, if the image recognition data is set at "1", the multi-level value image data in the multi-level value IMEM 132 is transferred to the VMEM 116. In this case, since the WMEM 116 comprises a multi-level value memory having a resolution of 40 dots/cm (100 DPI), the multi-level value image data has a resolution of 40 dots/cm (100 DPI) accordingly. Therefore data can be transferred without resolution conversion. In this manner, if data of all pixels are transferred to the VMEM 116 (step S38), the image is displayed on the CRT 104 in step S40. <Output to Printer (IP) 107 : Fig. 20> A sequence for outputting data to the IP 107 will be described with reference to a flow chart in Fig. 20. Assume that predetermined data are stored in the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133. When the CPU 110 instructs the IP 107 to output an image via the SPC 130 in step S50, the SPC 130 communicates with the IP 107 to start the IP 107 in step S52. The CPU 110 instructs circuits in the SP-I/F 114 to start outputting an image signal in synchronism with the IP 107 and reads out the contents of the image area MEM 133 by one pixel. The bi-level value image data having a resolution of 160 dots/cm (400 DPI) read out from the bi-level value IMEM 131 is converted into 8-bit multi-level value image data by the bi-level digitalizing circuit 134. The converted data is supplied to the combining circuit 137. The 8-bit multi-level value image data having a resolution of 40 dots/cm (100 DPI) and read out from the multi-level value IMEM 132 is resolution-converted into the 160 dots/cm (400-DPI) multi-level value data by the interpolating circuit 135. The image recognition data for designating the character or photographic portion is read out from the image area MEM 133 and is input to the combining circuit 137. In steps S56 to S62, the combining circuit 137 selects one of the digitalized and interpolated outputs from the digitalizing circuit 134 and the interpolating circuit 135 on the basis of the image area designation data read out from the image area MEM 133. An output image signal is then output to the IP 107. This image signal is printed on paper at the IP 107 in synchronism with the operation of the IP 107. In the IP 107, the 8-bit (per pixel) multi-level value data is converted into analog data and the width of the ON pulse of the laser can be changed, thereby printing out a halftone electrophotographic picture expressed in 256 gray scale levels. <Application with/Recording of Optical Disk : Fig. 21> Fig. 21 shows an application in which an image including both character and photographic areas is recorded in the OD (or optical disk) 105. This operation is performed in association with the DISK-I/F 111, the ICU 119, the SP-I/F 114, and the bus BUS. Image data associated with the bi-level value image area, image data associated with the multi level value area, image recognition data, and header data for discriminating the image data from image recognition data are simultaneously stored in the OD 105. In this case, only a character area 156 excluding a photographic area 155 from the data in the bi-level value IMEM 131 is compressed by the ICU 119, and predetermined header data H1 is added to the compressed data, and the composite data is stored in the OD 105. Predetermined header data H2 is added to only a photographic area 157 excluding a character area 158 in the multi-level value IMEM, and the composite data is stored in the OD 105. Since the resolution of the multi-level value image data is compressed into 1/4, the quantity thereof is compressed to 1/16. A further data compression operation is not performed. The image recognition data stored in the image area MEM 134 is compressed by the ICU 119 and is defined by predetermined header data H3. The above data are controlled as a single image file in association with the header data. Compression of data excluding a specific area can be performed by the logical AND function of the BMU 117 together with the ICU 119. Control data (not shown) including the header data is stored in the HD 120. <Application with/Reading of Optical Disk : Figs. 22-1 and 22-2> Figs. 22-1 and 22-2 show a sequence for outputting image data from the OD 105. A desired optical disk file is detected by the control data stored in the HD 120. When header data H1 is read, bi-level value image data is read out from the OD 105 and is expanded by the ICU 119. The expanded data is stored in the bi-level value IMEM 131. When the header data H3 is read, the image recognition data is read out from the OD 105 and is expanded by the ICU 119. The expanded data is stored in the image area MEM 133. When the expanded data are to be printed out, the corresponding data are read out from the memories in synchronism with the operation of the IP 107 and are combined by the combining circuit 136. The area of the image area MEM 133 which is assigned with "1" represents the photographic area 154. As for the photographic area, data is read out from the multi-level value IMEM 132. As for the remaining area, data is read out from the bi-level value IMEM 131. The resultant combined image is output to the IP 107. Therefore, an image including character and photographic areas having high quality can be obtained. In the above embodiment, the image scanner is used as a multi-level value image data input means. However, another input device such as a TV camera or a flying spot scanner may be used. A laser beam printer, an ink-jet printer, a thermal printer or the like may be used as a multi-level value printer. In the above embodiment, a random access memory is used as a memory for storing image recognition data. However, start/end point data of the x- and y-coordinates of the photographic area (halftone) may be stored in registers. In the above embodiment, the multi-level value image data is resolution-converted,and the 40 dots/cm (100-DPI) converted data is stored in the memory. However, the resolution of the converted image data may be, for example, 80 dots/cm (200 DPI). Fig. 23 shows an image processing system using an interface circuit according to a third embodiment of the present invention. A CPU 201 serves as a host computer processor and includes a main memory adapted to store control programs and used as a work area. A frame buffer 202 stores image data of at least one frame. A CRT 203 displays image data from the frame buffer 202 and contents of inputs from a keyboard 204 and a pointing device 205. The keyboard 204 is used to input various commands and control data. The pointing device (PD) 205 is used to designate a specific area of an image displayed on the CRT 203. A disc drive 206 stores image data input from an image scanner 207 or the like. A system bus 207 connects the CPU 201 to various buffers. The CPU 201 can access each buffer via the system bus 207. These components are included in the host computer side. An image scanner 208 photoelectrically reads image information and input it as multi-level value image data. A printer 209 prints a multi-level value image on paper. An interface circuit 210 is controlled by a controller 211. The multi-level value data from the image scanner 208 is simultaneously input to a multi-level/bi-level converter 213 and a resolution conversion circuit 214 via a video bus 212. In the multi-level/bi-level converter 213, the input multi-level value data is converted into bi-level value data in accordance with threshold value processing. The resultant bi-level value data is stored in a bi-level value buffer 215. The resolution conversion circuit 214 extracts the input multi-level value data and converts it into data having a lower resolution. The converted data is stored in a multi-level value buffer 216. When the image data is output to the printer 209, the bi-level value data in the bi-level value buffer 215 is min/max-converted by the multi-level/bi-level converter 213 into multi-level value data. The multi-level value data in the multi-level value buffer 216 is subjected to interpolation by the resolution conversion circuit 214. Low-resolution data is expanded so that its dot density coincides with that of the multi-level value data from the multi-level/bi-level converter 213. An address counter 217 generates read/write address data for the multi-level value buffer 216 and an area control buffer 218. A switching circuit 219 switches between the image data from the multi-level/bi-level converter 213 and the resolution conversion circuit 214 in accordance with area data 220 from the area control buffer 218 when the image data are output. When the bi-level or multi-level value image area is designated with the PD 205 in the image displayed on the CRT 203, the area control buffer 218 stores the data in the area control buffer 218 such that "1" is assigned to the bi-level value area and "0" is assigned to the multi-level value area. The area control buffer 218 outputs area data 220 of logic "0" or "1" in synchronism with read access of the bi-level or multi-level value buffer 215 or 216. <Description of Image Editing Application : Figs. 24A to 25(e)> Fig. 24A shows image data input from the image scanner 208. This image includes a photographic area 250 and a character area 251. Fig. 24B shows print-out image data in which the photographic area 250 is shifted. Image input operations, the states of buffers at the time of image output, and operations during image shifting will be described with reference to Figs. 25(a) to 25(e). When multi-level value image data is input from the image scanner 208, the bi-level value data output from the multi-level/bi-level value converter 213 is stored in the bi-level value buffer 215. At the same time, the multi-level value image data, the resolution of which is lowered by the resolution conversion circuit 214, is stored in the multi-level value buffer 216. This state is shown in Fig. 25(a). The image in Fig. 25(a) includes a photographic area 230 and a character area 231. Referring to Fig. 25(b), the CPU 201 fetches the multi-level value data from the multi-level value buffer 216 via the system bus 207 and causes the frame buffer 202 to store the fetched data. This data is displayed on the CRT 203. The operator designates the photographic area 230 with the PD 205 while visually observing the image on the CRT 203. The bits of an area 232 which corresponds to the photographic area 230 are inverted, thereby storing the area data (Fig. 25(c)). When the operator designates shifting of the photographic area 230 with the PD 205, the photographic area 230 is shifted in the frame buffer 202, as shown in Fig. 25(d). The photographic area on the CRT 203 is shifted accordingly. When the above editing operation is completed, the photographic area 230 is shifted in the bi-level value buffer 215, the multi-level value buffer 216, and the area control buffer 218 in accordance with the editing end instruction input by the operator (Fig. 25(e)). The image data and area data 220 are simultaneously read out from the buffers 215 to 218 in accordance with a printing instruction from the keyboard 204. The bi-level value data from the bi-level value buffer 215 is converted by the multi-level/bi-level converter 213 into the multi-level image data. The low-resolution multi-level value data in the multi-level value buffer 216 is expanded by the resolution conversion circuit 214 such that the resolution thereof matches with the resolution (dot density) of the bi-level value data. These two data are switched by the switching circuit 219 in accordance with the area data 220 read out from the area control buffer 218. As for the photographic area 232, the output from the resolution conversion circuit 214 is selected. As for the remaining area, the output from the multi-level/bi-level converter 213 is selected. The selected outputs are supplied to the printer 209. As a result, the character area is expressed by a high-resolution bi-level value image, and the photographic area is expressed by the low-resolution multi-level value data with 256 gray scale levels. If the resultant data is to be stored in the disc drive 6, the bi-level/multi-level image data extracted according to the area data 20 are properly compressed, and the compressed data are stored in the disc drive 6, thereby greatly compressing the image data. Image editing is exemplified in the above embodiment. However, a variety of applications may be utilized within the scope of the invention. In the above embodiment, bi-level and multi-level value images are processed. However, the same techniques as described above can be applied to area control of predetermined threshold value processing and dither processing for only a bi-level value image. According to the above embodiment, the high-resolution bi-level image and the low-resolution multi-level image which are prepared on the basis of single high-resolution multi-level data can be input to or output from the independent bi-level and multi-level value buffers. At the same time, each buffer can be randomly accessed via the system bus on the host computer side. The host computer can arbitrarily use each buffer to process high-quality images by using a small number of data. Fig. 26 shows a system in which an image area discrimination circuit 221 is added to the arrangement of Fig. 23. The image area discrimination circuit 221 uses the density values of the pixels adjacent to the image data from the image scanner 208 and discriminates an edge portion from a nonedge portion in the image. The edge portion is discriminated as the bi-level value area, and the nonedge portion is discriminated as the multi-level value area. The discrimination result is output as area data 220. An area buffer 218 stores the area data 220 from the image area discrimination circuit 221 such that the bits of the photographic area 232 are inverted. The timing of the area buffer 218 shown in Fig. 25(a) is the same as that in Fig. 25(c). A combining circuit for combining outputs from the multi-level/bi-level converter 213 and the resolution conversion circuit 214 and outputting a composite signal may be arranged in place of the switching circuit 219 shown in Figs. 23 and 26. In this case, after the step in Fig. 25(e) during image editing, the operator must designates the photographic area in the image displayed on the CRT 203 and clears the area 230 in the bi-level value buffer and the area 231 in the multi-level value buffer 216 in Fig. 25(e) in order to prevent double overlapping when two images are combined.

Claims: A method of processing image data for producing an image that is a composite of line-image and tone-graphic features, which method comprises: providing multi-bit digital first data representing respective pixels of at least the tone-graphic features amongst said composite of features; providing single-bit digital second data representing respective pixels of at least the line-image features amongst said composite of features; and using said first and second data to provide output third data representing respective pixels of said composite of line-image and tone-graphic features, which method is characterised in that: said using of said first and second data comprises converting said single-bit digital second data into multi-bit digital data and producing multi-bit digital output third data from this and from the multi-bit digital first data. Image processing apparatus (Fig. 1; Fig. 6; Fig. 14), for providing output data for producing an image that is a composite of line-image and tone-graphic features, said apparatus comprising: first means (1; 106, 138, 132) for providing multi-bit digital first data representing respective pixels of at least the tone-graphic features amongst said composite of features; second means (2; 106, 136, 131) for providing single-bit digital second data representing respective pixels of at least the line-image features amongst said composite of features; and third means (4, 6, 13; 134, 135, 137), co-operative with both of said first means (1; 106, 138, 132) and said second means (2; 106, 136, 131), for using said first and second data to provide output third data representing respective pixels of said composite of line image and tone graphic features; said apparatus being characterised in that: said third means (6, 13; 134, 135, 137) includes a conversion means (4; 134) for converting said single-bit digital second data into multi-bit digital data and a processing means (6; 135 & 137) for producing from this converted data and said multi-bit digital first data, output third data that is multi-bit digital. Apparatus (fig. 14; fig. 23/fig.26) as claimed in claim 2 wherein said processing means (135 & 137; 214 & 219) is adapted for producing said multi-bit digital output third data from first data and second data that are of a lower resolution and a higher resolution respectively, said processing means (135 & 137; 214 & 219) including resolution conversion means (135; 214) that is operable on said lower resolution multi-bit digital first data to convert said first data to multi-bit digital data of higher resolution. Apparatus (Fig. 14), as claimed in either one of claims 2 and 3, further characterised in that: said first means (106, 138, 132) and said second means (106, 136, 131) include a common source (106) of multi-bit digital data representing respective pixels of said composite of features; and said second means (106, 136, 131) includes binarization means (136) for converting said common source multi-bit digital data to said single-bit digital second data. Apparatus (Fig. 14), as claimed in both claims 3 & 4, further characterised in that: said first means (106, 138, 132) includes conversion means (138) for converting said common source multi-bit digital data to multi-bit digital first data representing respective pixels of said composite of features at a lower resolution than the resolution of said common source multi-bit digital data. Apparatus (Fig. 1; Fig. 14), as claimed in any one of claims 2 to 5, wherein said first means (1,106,138,132) and said second means (2; 106, 136, 131) include memory means (1, 2; 131, 132) for storing said first and second data. Apparatus (Fig. 1; Fig. 14), as claimed in any one of claims 2 to 6, wherein said third means (6, 13; 134, 135, 137) includes: selection means (6; 137), co-operative with both said first means (1; 106, 138, 132) and said second means (2; 106, 136, 131), for selecting said first data and said second data, respectively; and selection control means (13; 133) arranged for controlling said selection means (6; 137) so that said first data shall be selected for providing third data representing a tone-graphic feature and said second data shall be selected for providing third data representing a line-image feature. Apparatus (Figs. 1 to 3-1), as claimed in claim 7, wherein said selection control means (13) includes: co-ordination means for providing image position co-ordinate data (YSYNC, HSYNC) associated with each of said second data; and comparator means (Y COUNTER, H COUNTER, X COUNTER, W COUNTER) for comparing said image position co-ordinate data (Y SYNC, H SYNC) with boundary co-ordinate data (WY, WH, WX, WW) representing each boundary between the line-image features and tone-graphic features of said image. Apparatus (Fig. 14), as claimed in claim 7, wherein said selection control means (133) includes a memory (133) for storing selection control data. Apparatus (Fig. 14) as claimed in claim 9, wherein said memory (133) contains, or is arranged for receiving and storing, selection control data, each one of which selection control data corresponds to a respective one of said second data and is indicative of whether the same corresponds to a tone-graphic feature or to a line-image feature. Apparatus (Figs. 12 and 14), as claimed in claim 10, wherein said selection control means (133) includes input means (103, 115) for entering said selection control data into said memory (133) thereof manually. Apparatus (Fig. 14) as claimed in both of claims 11 and 4 or in both of claims 10 and 4, wherein said selection control means (133) includes feature discriminative means (139) co-operative with said common source (106) for receiving said common source multi-bit digital data, for determining therefrom whether each respective one of said single-bit digital value second data converted therefrom corresponds to a tone-graphic feature or to a line-image feature, and for providing said selection control data accordingly. Apparatus (fig. 6) as claimed in claim 2 wherein said processing means (6) comprises logical operator means (6) which is operable on the individual bits of said multi-bit digital first data and of said multi-bit digital data converted from said single-bit digital second data to produce said third data as logical result. Apparatus as claimed in claim 13 wherein said logical operator means (6) is operable to perform logic AND, logic OR, MAX, and MIN functions, each of which functions is selectable under the control of a control means (13) also part of said apparatus. An image processing apparatus (figs. 1;6;14;23;26) for use in performing the method of claim 1 comprising: memory means (1,2; 1,2; 131,132; 215,216; 215,216) structured and arranged to store therein data representing a plurality of pixels of image data, each such pixel being represented by a respective multi-bit digital datum, and data representing a plurality of pixels of image data, each such pixel being represented by a respective single-bit datum; characterised by: output means (6;6; 134,135,137; 213,214,219; 213,214,219) for reading from said memory means and for outputting, as multi-bit digital data, each datum representing one pixel, both the multi-bit digital data and the single-bit digital data stored in said memory means. Apparatus (figs. 23,26) as claimed in claim 15 wherein: said memory means (215,216) includes: a single-bit digital data buffer means (215); and a multi-bit digital data buffer means (216); and said output means (213,214,219) includes: a first conversion means (213) for converting single-bit digital data stored in said single-bit digital data buffer means (215) to multi-bit digital output first data; a second conversion means (214) for converting multi-bit digital data stored in said multi-bit digital data buffer means (216) to multi-bit digital output second data with a higher resolution, the same resolution as that of said single-bit digital data and said multi-bit digital output first data; a selector circuit means (219), arranged to receive said multi-bit digital output first and second data from said first and second conversion means (213,214), for selecting either said multi-bit digital output first or second data to output multi-bit digital output third data composed thereof; and a selection control buffer means (218) for storing selection control data, a single-bit digital datum corresponding to each single-bit digital datum stored in said single-bit digital data buffer means (215), for controlling selection of said multi-bit digital output first or second data according to whether line image or tone graphic features are to be represented in the image that is to be produced using said multi-bit digital output third data. Apparatus (figs. 23,26) as claimed in claim 16 wherein in place of said selector circuit means (219) and said selection control buffer means (218) there are provided: a combining circuit means arranged to receive said multi-bit digital output first and second data from said first and second conversion means (213,214) for selectively combining said multi-bit digital output first and second data to output as a result multi-bit digital output third data; and a combination selection control buffer means for controlling the selected combination of said multi-bit digital output first and second data produced by said combining circuit means for each multi-bit digital output datum. Apparatus (figs. 23,26) as claimed in either claim 16 or 17, including first data input means (201-207) comprising a first data bus (207) that is connected to said single-bit digital data buffer means (215), said multi-bit digital data buffer means (216), and either said selection control buffer means (218), or said combination selection control buffer means for entering directly and/or editing said single-bit digital data, multi-bit digital data, and control data. Apparatus (figs. 23,26) as claimed in any one of the preceding claims 16-18, including: second data input means (208), 212), 213, 212) comprised of: a second data bus (212); a third conversion means (213) interposed between said data bus (217) and said single-bit digital data buffer means (215) for converting multi-bit digital data on said second data bus (212) to single-bit digital data to be stored in said single-bit digital data buffer means (215); and a fourth conversion means (214) interposed between said second data bus (212) and said multi-bit digital data buffer means (215) for converting multi-bit digital data on said second data bus (212) to multi-bit digital data to be stored in said multi-bit digital data buffer means (216) with a lower resolution. Apparatus (fig.26) as claimed in claim 19 when dependant directly or indirectly from claim 16, including: an image area discrimination circuit means (221) interposed between said second data bus (212) and said selection control buffer means (218) for producing said selection control data from multi-bit digital image data on said second data bus (212) by discriminating edge and non-edge portions of the image represented thereby. Apparatus (figs. 1 & 6) as claimed in any one of the preceding claims 2 to 20 including a digital-to-analogue converter means (7) arranged to receive said multi-bit digital output third data. A method as claimed in claim 1 wherein in converting said single-bit digital second data into multi-bit digital data and producing multi-bit digital output third data from this and from the multi-bit digital first data, said multi-bit digital first data is used directly without any change as said multi-bit digital output third data. A method as claimed in claim 22 wherein said multi-bit digital output third data includes, inter alia, unchanged multi-bit digital first data. Apparatus as claimed in claim 2 wherein there is a display unit (9) following said third means (6). Apparatus as claimed in claim 2 wherein there is a printer (107) following said third means (137).

Inventors: CHYO, KENJIRO, ISHIZAWA, YASUHISA, MIURA, SHIGEKI, NONOSHITA, HIROSHI, SAITO, SEIJI, SHIGEHARA, YASUHISA
Applicants: CANON KABUSHIKI KAISHA
Application year: 1987
Main classification: H04N1
IPC codes: H04N1, G06T11