COMMUNICATION SYSTEM HAVING A CONTROL CHANNEL AND AN IMAGE CHANNEL

Abstract: A two-channel communications network having a plurality of nodes with one channel acting as a control channel, and the other as an image channel. The control channel employs the standard protocol layers and is used primarily for data transmission between nodes of the network. Access to and reservations on the image channel are made by the control channel. The transmitting and receiving nodes are predesignated to communicate in a specific time slot on the image channel by scheduling software which communicates between the nodes on the control channel prior to the occurrence of the specific time slot. Scheduling and the direction of flow of data on the control channel may be controlled by one or more of the nodes without external control. Likewise, image sources may be provided by one or more of the nodes.

Description: COMMUNICATION SYSTEM HAVING A CONTROL CHANNEL AND AN IMAGE CHANNEL 1) Technical Field This invention relates to a communication system, and more particularly, to a communication system providing for the rapid transmission of digital images and data. (2) Background Art The present trend toward distributed data processing, coupled with the increased emphasis on office automation and the widespread use of automatic office terminals, displays, and computers has created a demand for a more comprehensive approach to terminal interconnection systems. Today's channel transmission technology permits the transfer of data at high rates with simple error recovery procedures in control protocols. These transmission rates also permit a large number of data terminals to share the common physical interconnection link with a minimum of interference from one another. The physical topology of a share-access link permits the simultaneous access to the transmission facility by all attached nodes. Thus, it is possible for two or more nodes to transmit at the same time, resulting in interference between the electrical signals. Control mechanisms, both physical and logical must be introduced to resolve the contention. For a bus topology, one class of random-access method is called the Carrier Sense Mutliple Access with Collision Detection (CSMA/CD). Prior to initiating a transmission, a node senses whether or not a carrier signal is present. If so, another node is transmitting, and origination of a new transmission is delayed until the carrier signal is removed. Once the transmission is started, the node continues to monitor the transmission for a collision (destruction of the transmitted electrical signals), indicating the presence of another transmitting node. Transmission is halted, and the node either waits a random period of time before attempting to transmit again, or waits a predetermined (node-specific) time interval. Selective polling is another type of centralized-control access mechanism for a bus topology. This mechanism is extensively employed for control of multi-point configurations of telecommunication links. This access mechanism is based on a group poll. A single control node transmits a unique poll frame to the other nodes that grants them permission to transmit. For a bus topology, each poll frame is addressed to a particular node on the bus. That node will either initiate the transmission of data, or return a negative response to the poll. Systems Channel Architecture in the International Organization for Standardization (IOS) as well as other channel architectures previously mentioned employ mutliple layer reference models. Separation of the channel functions into layers facilitates the description of the protocol, as well as the implementation. The data frame format is the general structure used for transmitting information in what is called a "frame". The portion of a frame labeled "data" is generally variable in length but generally on the order of 1 kilobyte, and contains information processed by Functions above the physical transmission layer. As illustrated in Fig. 1, the data field is preceded by a physical header, which contains three sub-fields, the first is a delimiter (DEL) that identifies the start of the frame. Next, is a field that is used for controlling access to the transmission facility, and is known as the physical control field. Finally, the header includes a field that contains the address of the node that originated the information and the address of the- node or nodes destined to receive the information. The data field is followed by a physical trailer. The first portion of the trailer contains a Frame Check Sequence (FCS), used for detecting errors that occur during transmission within the second byte of the physical control field, the address field, or the data field itself. Next, a delimiter is provided to identify the end of the frame. This is followed by a modifier (MOD) field which, in conjunction with the ending delimiter is employed for certain physical control functions. Three of these functions are: error detection, address recognize, and frame copy. In the conventional type channel discussed above, the size of the data field is typically less than one kilobyte. If one were interested in transmitting a data message representing a typical compressed bi-tonal document image that is on the order of 100 kilobytes, it can be seen that it would take a minimum of 100 frame transmissions to transfer the compressed bitonal image. Thus, it can be seen that an incredible amount of processing functions at the physical transmission layer must take place in order to transmit 100 kilobytes of image information. Approximately 700,000 instructions per second would be required just to handle the protocol associated with the data transfer for a single compressed, bi-tonal document image. This in no way accounts for the increased time that may be required to transmit the image data if the bus is extremely busy and the source encounters substantial delays in obtaining access to the bus each time it attempts to transmit a frame. In an attempt to overcome such a problem, data has been segregated into two categories, one being deemed "bursty" or the kind that arrives in spurts such as data from a computer terminal, or some type of sensing device. The other category is deemed "continuous data", such as voice or image information. Attempts to accommodate both types of data on a common communication channel has resulted in the use of buffers on the various inputs in conjunction with statistical multiplexing. This worked well so long as the bulk of the traffic on the channels was of a "bursty" nature. However, as "continuous data" became more prevelant, continuous data transmission would monopolize the channel, resulting in the saturation of the buffers on the waiting input lines, ultimately resulting in the loss of information. United States Patent 4,445,213 discloses the use of several programmable station controllers, each at a different location and each arranged with ports into which continuous data inputs can be plugged and with ports into which "bursty" data inputs can be plugged. Transmission compatibility between the types of data transmissions received from the "bursty" and "continous data" inputs is assured by sub-dividing the transmission on the single channel into frames having four time slots. A ixed number of time slots for each frame is assigned by a central controller to active ones of the "continuous data" inputs while other time slots of each frame are assigned to the multiplex "bursty" data inputs. One of the time slots of each frame is utilized for communicating control information between the programmable station controller and the central switching network controller. Disclosure of the Invention These and other problems are solved by the present invention that provides a digital data communication network having a plurality of peripheral nodes. The network has a control channel which is connected to each of the nodes. Located at one or more of the nodes is an image source, which may take the form of a microfilm storage and retrieval apparatus or an automatic optical disk library. Indexing means, such as a computer is also provided either at the image source, or remote therefrom to provide the physical location of the images within the image source. An image channel is connected to all of the nodes. Scheduling means may be located at one or more of the nodes, and controls the communications on the control channel, and provides access to the image channel by the image source and the nodes. By way of the foregoing general summary, a network is described which by virtue of its arrangements of parts, reduces the time it takes to transmit large data packets such as images from one station to another in the network. Brief Description of the Drawings Figure 1 shows the frame protocol used in the prior art; Figure 2 is a block diagram in accordance with the present invention; Figures 3-5 are block diagrams of further embodiments of the configuration of a network; Figure 6 illustrates a segment of a network using a bus type control channel; Figure 7 illustrates a segment of a network using a multiline control channel; Figure 8 is a data flow diagram; Figure 9 is a timing diagram for the logic messages on the control channel and the image transmission on the image channel; Figures lOa-d illustrate a flow chart showing the operation of the transmitter (the indication of letters "a-d" indicates that this is all one Figure, but is continued onto pages "a-d"); Figures lla-b illustrate a flow chart showing the operation of the receiver; Figures 12a-b illustrate a flow chart showing the operation of the scheduler; Figure 13 illustrates the connection of the image transmitter and image receiver to the image channel; Figure 14 is an electrical schematic diagram of the image transmitter; Figures 15a-b are electrical schematic diagrams of the transmitter tap; Figure 16 is an electrical schematic diagram of the receiver tap; Figures 17a-b are electrical schematic diagrams of the image receiver; Figure 18 illustrates signal timing diagrams for both the image transmitter and image receiver; Figure 19 is an electrical block diagram of the dual channel workstation; Figure 20 is an electrical block diagram of the buffer memory shown in Figure 19; Figure 21 is an electrical block diagram of the electronic processing circuit shown in Figure 19; and Figure 22 is an electrical block diagram of the bit-map memory shown in Figure 19. Mode of Carrying out the Invention The present invention is directed toward a local area communication network. The network uses two communication channels. One channel handles general data communication and also acts as a control channel for a second channel. The second channel is designated as the image channel, and is intended to carry images, digitized voice information, or large packet data exclusively. Use of a two channel network of this type may have either distributed control or centralized control. The preferred embodiment will be described as showing central control primarily because such a network as a practical matter, is used in conjunction with a centralized data base which more than likely is managed by a large, central processing unit (CPU). The primary function of such a network is to give remote users access to that centrally located data base. Because it is very likely that the large CPU would have some unutilized capacity, it could then very easily be expected to handle the scheduling operations required of a network scheduler. In an effort to deliver the inventive concept herein with the least amount of ambiguities, a discussion of terminology and definitions are initially set forth as follows. The term "channel" is intended to define a single path for transmitting electrical signals and is used in the broad sense to include separation by frequency division or time division. For example, a single broad band transmission could contain two or more channels separated by frequency. Similarly, use of a central computer connected to a plurality of nodes or workstations by RS-232 lines to individual workstations, for carrying control signals would still be considered a single channel. The term "channel" is to encompass a two-way path, thereby providing transmission in two directions. In addition, the use of RS-232 or RS-422 interface specifications are not intended to be limited to that particular type of interface, but are used in an exemplary manner taking into account that these are Electronic Industries Association (EIA) Standards. Clearly, many other interface specifications could be employed by a designer and. still achieve satisfactory results. The information transmitted through the channels may be carried by a number of different mediums, such as e.g. coaxial cables, optical fibres, or could conceivably take the form of transmitted electromagnetic signals with each channel being separated by frequency. The description unless otherwise noted, is directed to the transmission, manipulation, display, and storage of digital images. It should be understood that in the event one wishes to use analog type signals instead of digital signals, the general structure disclosed herein would be capable of accommodating those types of signals. Any modifications required to accommodate these analog signals in the disclosed apparatus would clearly be within the abilities of one skilled in the art. All lines connecting functional boxes in a block diagram may, in fact, comprise more than one signal path. In some instances, a diagonal slash is placed across the line to indicate multiple conductors, but it is not to be assumed that lines without such slashes are meant to represent a single conductor; there may, in fact, be more than one electrical conductor in such lines. Figure 2 illustrates a preferred embodiment of a communication network using the two channel network to transmit images at high speed to remote workstations located at a plurality of nodes. The images are formed by scanning images of documents on microfilm, or images stored on optical disks. The type of document images requested by an operator of a remote workstation may take the form of an insurance claim premium, or documents used in the processing of a medical claim. Figure 2 illustrates a central processing unit (CPU) 2, which among other things, is connected to a plurality of nodes or workstations 4 through 12 by RS-232 lines 14 through 22. (RS-232--A uniform standard for serial interfaces set by the Electronic Industries Association (EIA). It establishes standards for signal and cabling.) Likewise, the CPU 2 is connected to an image source 24 via cable 26. Also connected to the CPU 2 by cable 28 is a raster image processor (RIP) and printer combination 30. It is these connections that constitute the control channel 32. The image source 24 is connected to workstations 4 through 12 and the RIP printer combination 30 via the image channel 34. Temporary storage of digital images may be placed on a magnetic disk media 36 which is connected to the image source 24 through cable 38. Index information relating to specific documents, for example, by name, date, insurance number, etc. is stored on magnetic disk 40, and database information from the CPU 2 is established through a dialog between the operator operating terminals 42 and 44. The index information regarding a document's physical location in the storage media and other characteristics relating to the document, is established by viewing the documents that have been placed on microfilm or optical disk and establishing an index relationship that will enable image retrieval at a later date. In addition, text printer 46 provides output data relating to index information and system status. Index information is preserved for archival purposes on magnetic tape 48. The communication between the central processing unit 2 and the workstations 4 through 12 takes place exclusively through RS-232 lines 14 through 22, with a single RS-232 line communicating with each specific workstation, while imaging information takes place exclusively on the image channel 34. In addition, the RIP printer combination 30 is connected to the image channel 34 and to a separate RS-232 line 28. The image management system shown in Figure 2 can be used in a number of ways. A common use would be for an operator sitting, for example at workstation 4 to type on keyboard 4a a description of the document which can be referenced to the database stored in CPU 2, on both magnetic disk 40 as well as the magnetic tape 48. It should be noted that the magnetic tape data is used primarily to back up or to bring to the machine indexed data which will be presumably transferred from the magnetic tape 48 to disk 40 to establish the actual working database. Accessing of the database with the operator's description, specifies the document image which the operator at workstation 4 wishes to see displayed on the screen 4b. The information regarding the description of the document passes as keystrokes down line 22 to CPU 2 requesting that the CPU access the information on disk 40 or on magnetic tape 48, to determine the specific command to be sent to the image source 24 via line 26 on the control channel 32 specifying the desired image to be transmitted. Once the image source 24 has located the image, it sends a signal through line 26 requesting the scheduling software running in CPU 2 to grant access to the image channel 34. The scheduling software is programmed to give one of two responses, the first being the granting of access to the image channel 34, or alternatively, denying the image source access to the image channel by sending a signal through line 26 requesting the image source to wait. Eventually, access is granted, and this is communicated from CPU 2 to the image source 24 through line 26. The image source 24 then informs the receiving workstation 4 through the control channel 32 (line 26 to CPU 2 and then through RS-232 line 22 to the workstation 4), that an image will be coming. The receiving workstation 4 then acknowledges via control channel 32 (through RS-232 line 22 to the CPU 2, then to the image source via line 26) that it is ready to receive the image. The scheduling software in the CPU 2 communicates with the image source 24 and permits it to transmit the image. The image source 24 sends the image on the image channel 34 to the receiving workstation 4. Shortly after the image transmission has begun, the image source 24 sends a message to the scheduling software in CPU 2 that it has accepted its permission to use image channel 34. Once the complete image has been transmitted, the image source 24 informs the receiving station via lines 26 and RS-232 line 22 that the complete image data has been transmitted. The receiving workstation 4 sends a deactivation signal informing the image source 24 that the workstation 4 has ceased to listen to the image channel 34. The image source 24 then responds to the scheduling software in CPU 2 with a channel release signal. The scheduling software in the CPU 2 may now arrange for the image source 24 to transmit further images to other workstations 4 through 12, or to the RIP printer combination 30 depending on the type of request received by the scheduling software in CPU 2. Figure 3 shows an alternative embodiment of the two channel communication network for an office environment, in which the CPU 50 and workstations 52 through 60 as well as RIP printer combination 62 joined by both the image channel 34 and the control channel 32, this latter being implemented in the ® ETHERNET (trademark of Xerox Corp., Stamford, CT) format (as compared to the RS-232 format in Figure 2). The change in con iguration results in the following difference to the overall structure. One difference is that the terminal or workstations 52 through 60 must be more intelligent, and therefore more complex and as a result, more expensive than the terminals 4 through 12 in Figure 2. This is required because of the greater level of computation power required to support an ® ETHERNET type format on the control channel 32, as compared an RS-232 format used in the control channel of Figure 2. Thus, each workstation, along with display electronics, includes a receiver and transmitter capable of performing the required ® functions associated with an ETHERNET type format, as well as an image channel receiver, and a processor controlling the data transmission, on the control channel which, in turn, controls the access to the image channel 34. This compares to the terminal-type workstations 4 through 12 in Figure 2 which required a less sophisticated microprocessor to support the RS-232 communications on the control channel 32 and image channel 34. In a manner similar to that shown in Figure 2, communication is established by first having the operator working at a workstation 52 request an image of a document by typing through keyboard 52a, a descriptor that when processed by the indexing software, would access the database information to determine the physical location of the document the operator wishes to view on display 52b. This information is sent on the control channel 32 to CPU 50 which references database information in disk 64 to identify the location of the specific document within the image source 66. Once the image source 66 has located the image to be transmitted on the image channel 34, it sends a request via channel 32 to the scheduling software running in CPU 50 to schedule the transmission of the image on the image channel 34. The scheduling program responds by granting access to the image channel 34 and if the image channel is not available, assigning a particular number to the request so that when the image channel is available, access may be granted to waiting users on some type of a priority basis. Eventually, access is granted to the transmitter, in this case, the image source 66 which in turn informs the receiver through the control channel 32 that an image will be coming. At this time, the receiver will commence monitoring the image channel 34. Once this has occurred, the workstation 52 (receiver) responds to the image source 66 on the control channel 32 that it is ready to receive an image. The image transmission then begins on the image channel 34. Shortly after the image transmission has begun, the image source 66 sends a message to the scheduling software in CPU 50 that it has accepted its permission to use the image channel 34. Once sent, the transmitter in the image source 66 communicates on control channel 32 to the workstation 52 (receiver) that the image has been sent, resulting in the deactivation of the receiver. The workstation 52 (receiver) acknowledges the deactivation back through control channel 32 to the image source 66. The image source 66 then informs the scheduling program through control channel 32 to CPU 50 that the image channel 34 is now free. Thus, it can be seen that the sequence of events in the protocol is similar to those discussed with regard to the topology shown in Figure 2. It should be understood that the scheduling program may run in either the CPU 50, image source 66, or possibly even in one of the workstations 52 through 60. In this case, communication would be between the scheduling program (where ever it may reside) and the requesting workstation (receiver) and image source 66 in the manner already discussed. Figures 4 and 5 illustrate two additional topological con igurations of the network wherein the image channel 34 is "daisy chained" or loops through from one workstation to the other, rather than using a T connection known as a "tap" (to be discussed later) as shown in Figures 2 and 3. Figure 4 shows the topological configuration wherein the control channel uses a bus type format similar ® to ETHERNET to connect the workstations 70 through 80 with the two image sources 69 and 71. In this topological configuration, the indexing software would reside in one or both of the image sources 69 or 71 with the scheduling software residing in one of the workstations, for example 80. Figure 5 shows the control channel 32 configured in a point-to-point connection between the CPU 79 and each of the workstations 82 through 92 and image source 81, similar to an RS-232 format for a multi-user distributed terminal network. In both cases, the image channel (34) connects into and out of each and every workstation, and in this way avoids the need for providing tapping points external to the workstations 70 through 80 or 82 through 92. Each workstation or node in the system may simply loop the signal through from input to output or alternatively, it may include a bi-directional repeater at each point to receive the signal and re-transmit it. PROTOCOL In order to more fully understand the communications involving an image source, a receiver, and a scheduler for the transmission of a single image from the image source to the receiver, the following communication scenario will be described. Figure 6 shows the essential components needed to describe this communication scenario, keeping in mind that although Figure 6 shows a bus structure, the communication scenario described herein can be applied to other types of dual channel topologies already discussed earlier. In addition, the connections 108a and 108b may have active components to allow the lines to the image source 108 to be of considerable length. Similarly, active connections at 110a and 110b allow the workstation 110 connection to be extended. The image source 108 must have two connections, one to control channel 32 and one to image channel 34, as must an image receiver 110 (workstation). The scheduler software 109 is connected only to control channel 32 and may reside anywhere within the system including the image source 108 or the image receiver 110. For the purpose of clarifying this discussion, it will be assumed that the image source 108 has address # 1, the image receiver 110 has address # 2, and the scheduler 109 has address # 3. An image source or image receiver internally comprises two elements, a computer section and an image section with channel 1 being connected to the computer section and channel 2 being connected to the image section. Each of the sections at a given address has a communications control link between them so that the computer section may control the activities and monitor the status of the image section. In order to better understand how the topology of Figure 6 relates to alternate bus topologies, for example an RS-232 communication, an alternative configuration is shown in Figure 7. In this case, channel 32A is part of control channel 32 and is line A of control channel 32. It connects image source 112 to the control computer 114. Image source 112 has address # 10. Similarly, channel 32B is the line to workstation 116; channel 32C is the line to workstation 118, all comprise separate RS-232 lines which are part of control channel 32. This means that when communication is referred to between address # 10 and address # 20 in subsequent parts of this explanation in fact, two communications are occurring on the RS-232 line, one from the image source 112 via channel 32A, to control computer 114 followed by a subsequent re-transmission by control computer 114 via channel 32B to workstation 116 at address # 20. Again, the scheduling software may run anywhere within the network but is most likely to run in in the control computer 114. In Figure 7, the image channel 34 is connected between image sources 112 and workstations 116 and 118. The image channel 34 need not be connected to the control computer 114 unless there is a requirement that the control computer 114 have access to the image information. Let us now consider the communication scenario between an image source transmitter (address # 1) and workstation 110 (receiver) address # 2 illustrated in Figure 6 in which the image source 108 (transmitter) has already determined through separate processes not described herein, that it needs to send an image which it already accessed via indexing software and located within the image source, and which is ready to be transmitted to the workstation 110 (receiver) at address # 2. It should be appreciated that other transactions need to take place on the control channel to establish this condition. The following table illustrates the messages to be transmitted, the direction of the transmission and a brief description of the type of message being sent. A more detailed description of these logic message transmissions will be presented below. LOGIC MESSAGE TRANSMISSIONS # 1 → # 2 Receiver-initialization RI # 2 → # 1 Receiver-initialization-acknowledge RIA # 1 -> # 3 Channel-access-request CAR # 3 -> # 1 Channel-access-postponement CAP # 3 -> # 1 Channel-access-grant CAG # 1 → # 2 Receiver-activation RA # 2 -> # 1 Receiver-activation-acknowledge RAA # 1 → # 2 Image transmission (on image channel 34) IT # 1 → # 3 Channel-grant-acknowledge CGA # 1 → # 2 Receiver-deactivation RD # 2 → # 1 Receiver-deactivation-acknowledge RDA # 1 → # 3 Channel-release CR # 3 -> all senders Request-request RR Figure 8 illustrates a data flow diagram indicating the senders and receivers of all of the messages transmitted on control channel 32 and the direction of those transmissions as well as the type of logic message being sent, when using the following protocol. The first transaction termed "receiver-initialization" (RI) involves a communication on control channel 32 from the image source 108 (address # 1) to the workstation 110 (receiver) address # 2. This transaction informs the workstation 110 (receiver) that it should get ready to receive an image signal and this activity will include setting aside the appropriate amount of space in the buffer memory (to be discussed later) by the image section of the workstation 110, in order to ensure when the image signal is transmitted on image channel 34 that it will be able to accept the entire image transmission. Once the workstation 110 (receiver) is in a condition to receive an image, it sends a "receiver-initialization-acknow- ledge" (RIA) message from workstation 110 (receiver) address # 2 to image source 108 address # 1. Once the image source 108 (transmitter) receives the RIA message from workstation 110 (receiver) address # 2 to image source 108 address # 1, the image source 108 and workstation 110 (receiver) are in a condition ready to communicate on the image channel 34. The image source 108 address # 1 next sends a "channel-access-request" (CAR) message to the scheduler software 109 at address # 3. This message requests of the scheduler software 109 permission to access the image channel 34. At this point, the scheduler software 109 may reply with one of two messages, "channel access postponement" (CAP) which indicates that the image channel 34 is not at this time available for transmission of an image signal. Note, however, that this may be because the image channel 34 is already in use, or that other requests have been made for the image channel 34 which must be served prior to the request being considered presently. Note that this also implies that the transmissions "RI", "RIA", "CAR", and "CAP" may all occur during the time that the image channel 34 is being used for some other transmission, or for the transmission of some other image, which presumably was requested prior to the one being considered in this scenario. It should also be noted that associated with each "CAR" transmission is a number so that if for any reason the request needs to be sent again, for example, due to an incomplete transaction in the communication scenario, the scheduler 109 address # 3 can re-establish the priority already assigned in the initial "CAR" message for the image transmission being considered presently. It is of course possible within the "CAR" message not only to include a number, but to imbed a priority so that the scheduling software can grant high priority requests ahead of lower priority requests. Scheduling algorithms with different priorities are well known within the art and a variety of different scheduling algorithms exist to optimize the utilization of computer and processing resources for a specific application. Once the scheduler 109 address # 3 determines that the image channel is available for the transmission of the image, a "channel access grant" (CAG) message is transmitted by the scheduler 109 address # 3 to the image source 108 address # 1. Note that the CAG may follow immediately after the CAR message or may be subsequent to a CAP message, depending on whether or not the image channel 34 was available at the time. Once the image source 108 address # 1 receives the CAG message from the scheduler 109 at address # 3, it sends a "receiver activation" (RA) message to the receiver at address # 2. This RA message indicates to the receiver 110 that it should now be activated to receive the image. The RA command may carry with it an identification number to insure that the receiver 110 can identify the image which it is to receive, should the system support the sending of multiple images to a single receiver. The receiver responds to the RA message with a "receiver activation-acknowledge" (RAA) message acknowledging its activation. The image source 108 begins sending the image transmission IT message on the image channel 34. This IT message may be of variable length but is no larger than the receiver 108 can accommodate in its buffer memory (to be discussed later). In setting up the network, the length of the image transmissions may be set at a maximum limit for all receivers and transmitters, or may be variable and the size may be specified in the RI and RIA messages. Shortly after the IT message has begun on the image channel 34, the image source 108 address # 1 sends a "channel-grant-acknowledge" (CGA) command through the scheduler 109 at address # 3 via control channel 32, and this provides confirmation to the scheduler 109 that the CAG command has been received and is being acted on. Once the image source 108 has completed sending the IT message, it sends a "receiver-deactivation" (RD) message indicating to the receiver 110 on control channel 32 that it has received the complete message, and should now deactivate the listening process on the image channel 34. The receiver 110 acknowledges this message by sending a "receiver-deactivation- acknowledge" (RDA) message on control channel 32 to the image source 108 address # 1. Once the image source 108 has received the RDA information indicating that the receiver 110 is deactivated, it sends a "channel release" (CR) message to the scheduler 109 program residing at address # 3. This CR message sent on control channel 32 indicates that the use of the image channel 34 has been completed, and the image channel 34 is available for additional transactions. One final message is the "request-request" (RR) message which the scheduler 109 can send to all image sources or senders. This message is sent on control channel 32 to indicate to the senders that no valid transactions are currently in progress. It should be noted that communication on the control channel 32 can occur even during use of the image channel 34. For example, as may be seen in the table entitled "Logic Message Transmission" the "channel grant acknowledge" (CGA) occurs shortly after transmission of the image has begun. For the sake of efficiency, it would be desirable to have other logic message communication on the control channel 32 occur during previous or subsequent image transmissions. Fields used in message transmissions protocol and their timing are shown in Figure 9. The data fields used in the dual channel communication network described herein are preceded by six logic messages on the control channel 32 to gain access to the image channel 34. Each of the six logic messages are sent separately on an ® ETHERNET format over the control channel 32. Thus, the first logic message "receiver-initialize" (RI) would be preceded by a physical header 113 in ® the conventional ETHERNET format with the data field following containing the logic message 115 "RI". This data field is followed by a physical trailer 117, in the conventional ETHERNET® format. Each of the remaining four logic messages or protocol would in turn be sent preceded by a physical header 113 and physical trailer 117 that ® conforms to the ETHERNET standards. ® Each logic message 115 in the ETHERNET data field is a portion of the two-way communication protocol on the control channel 32, between the transmitter 108, scheduler 109, and the receiver 110, so that the transmitter can obtain access to the image channel 34 from the scheduler 109. All of the logic messages 115 on the control channel 32 contain six sub-fields 119. The first is the tag 120; it is an integer code that differentiates between the various possible logic messages, such as RI, CAG, etc. Next, is a field that identifies the address of the source of the message and is known as the source address 122 which is an integer number indicating the source of the message. The third field contains the sequence number 124, which is an integer count originating at the transmitter designating which image is being sent. This count would be incremented after each image transmission is complete. The copy number 126 follows next; that consists of an integer count that is incremented when a control message gets re-transmitted. The preceding three sub-^fields 122, 124, 126 are used to detect duplicate control messages, and to aid diagnostics. The fifth field contains a time due 128 logic message and is used when important time-out periods are computed, such as image grant time-out. The absolute time of the time-out is transmitted to the transmitter so that the requestor of the image channel knows the maximum amount of time it has access to the channel. Additionally, the "receiver deactivation acknowledge" (RDA) which is the penultimate logic message, contains an error code 132 which is computed from the received image data and transmitted on control channel 32 back to the image source 108. Figures 10, 11, and 12 illustrate the flow charts for the transmitter, receiver and scheduler, respectively. In the last section, the communications that take place on the control channel 32 and related protocols were discussed in detail. Attention will now be given to the hardware associated with the image channel 34. In Figure 13, reference is made to the image transmitter 134 which has two input signals, the first being the image data input 136 which receives the image data from an image source, such as a microfilm retrieval unit or an optical disk (not specifically shown). The second input is a transmitter enable/disable line 138 that receives signals from the computer section (not shown) of the image source which handles the communication on the control channel 32. Signals on line 138 either enable or disable the image transmitter 134. The image transmitter 134 encodes the data it receives from the image data input 136 into what is known as biphase mark encoding and puts this signal onto data path 140 to the transmitter tap 142 which receives the data to be put on the image channel 34. The transmitter tap 142 takes differential pair signals (RS-422 type, which is an EIA Standard for "Electrical Characteristics of Balanced-Voltage Digital Interface Circuits") and converts them into appropriate voltages that are placed on the image channel 34 via "tee" connector 143a. It is also the function of the transmitter tap to disconnect from the image channel 34 when the power is shut off, or when the image transmitter 134 receives a disable signal on enable/disable line 138. The image signal is transmitted over the image channel 34 where the receiver tap 144 takes the voltages off the image channel 34 via "tee" connector 143b and converts it back to a signal consisting of differential paired signal levels (RS-422 type). This signal is sent on data path 146 to the image receiver 148 where the biphase mark encoded signal is decoded into separate differential pairs, image data and clock signals. The image data signal is outputted on the image data output line to the buffer memory of an image section of a workstation (to be discussed later). In a manner similar to the image transmitter 134, the image receiver 148 also has a receiver enable/disable line 152 which receives signals from the computer section of the receiver and is used to enable or disable the reception of data. The image net transmitter shown in Fig. 14 has two input ports, the first being the image data input 136 which consists of three pairs of differential inputs: (1) data valid 136a; (2) video data 136b and (3) video clock 136c. The data valid 136a is just an enable line that is used to assure that the incoming data is good and it also assures that the cables are connected and that the power is activated. The video data 136b is a differential paired signal that is a flow of digital video information. It should be noted that the representation of a one or zero is up to the designer of the equipment. However, whatever the convention used for the video data signal 136b in the image transmitter 134, will take the same format when it appears at the output 150b of the receiver 148. The signal that appears at the video clock input 136c is also a differential signal that is used to separate the different bits. Each incoming bit is clocked with the video information and permitted to change level upon the upward transition of the video clock 136c. The image transmitter 134 samples the video data 136b on the downward transition of the video clock 136c. The other input port of the image transmitter 134 is the transmitter enable/disable line 138. As mentioned earlier, this line is used to enable and disable transmission. Specifically, when the transmitter enable/disable line 138 goes high, transmission is enabled and a signal will be placed on the image channel 34. When the control signal goes low, transmission is disabled and the image channel 34 (coax cable) is left floating so that other transmitters on the network may use the image channel 34. The output port to data path 140 on the image transmitter 134 carries power and ground lines in addition to two signals. One signal is the enable signal 140a which is identical to the signal that appeared on the transmitter enable/disable line 138. The other signal is the image data 140b that has been encoded using biphase mark encoding. As mentioned earlier, the video clock 136c is used to sample the video data 136b on the downward transition of the video clock 136c. This is accomplished by flip-flop 154 latching the data on the downward transition of the video clock 136c which provides the latching signal after passing through inverter 156, thereby preserving the state of the video signal TD1 for further use in the circuit. The downward transition of the video clock 136c signal must be detected to operate the encoding circuitry. This is accomplished by inputting the clock signal to flip-flops 158 and 160 which are connected together to function as a shift register. The output of each of the flip-flops 158 and 160 are inputted to NAND gate 162. Thus, when flip-flop 158 is low and flip-flop 160 is high the output of NAND gate 162 is a negative going pulse. The output of NAND gate 162 is TCI which is intended to be used as a clock signal. Signals TCI and TD1 are inputted to flip-flops 164 and 166, respectively which provides synchronization of the signals by removing any delay that may exist in the data signal TD1. Signal TC2 is outputted from flip-flop 164 and is delayed two clock periods by using flip-flops 168 and 170. Then, the delayed signal TC4 and synchronized data signal TD2 are inputted to AND gate 172 which provides an output every time TC4 and TD2 are present; this signal is inputted to one of the inputs of OR gate 174. The undelayed signal TC2 is placed on the other input of OR gate 174 which in turn will produce an output when TC2 or TC4 and TD2 are present. This signal is sent to the input of a D-type flip-flop 176 which is wired to function as a T-type flip-flop so that each time the flip-flop 176 receives a clock pulse, the output level will change state. At the output of OR gate 174 a single pulse will appear if the data is a zero, and a pair of pulses will be generated if the data is a one. Therefore, on the data path 140 of the image transmitter 134 a single edge or transition will represent a zero bit and two edges or transitions will represent a one bit. The operation of the transmitter tap, Fig. 15 will now be described. For clarity, the schematic has been subdivided into sections numbered I to V. The general function of each section will be described first. Section I is used to enable transmission and provides a "watchdog" timer that limits the maximum time that a node can transmit. Section II is used to prevent noise from being placed on the image channel 34 when the power is not fully applied (i.e. when the equipment is first turned on). Section III is used to drive a reed relay 202 that connects the image data to the image channel 34. This Section receives outputs from Sections I and II, thereby combining the enable signals and "watchdog" timer of Section I with the power monitoring circuitry of Section II. Thus, transmission may occur only when all of the monitored conditions have been met. Section IV is a power regulation section that uses the voltage reference on the shield 203 of the coaxial cable of the image channel 34 and provide an active ground which closely (within ± 1 volt) follows the shield voltage. Section V is the data driver section; it takes the data coming from the image transmitter 134 that appears on data path 140, (Fig. 13) and sends it through the reed relay 202 via "tee" connector 143a onto the image channel 34. In Section I, the differential enable signal is passed through the image transmitter 134 and is carried on data path 140. This signal appears as a pair 140a of input enable lines in Section I. Each of the enable lines is connected to ground by a metal oxide varistor (MOV) 182 and 183 to act as a voltage limiter in the event of a static discharge or other high voltage condition that may occur between the potential of the internal circuitry and the cable while being connected. A differential receiver 184 (such is manufactured by Advance Micro Devices and which is identified as: AM 26LS33) is used to convert the signal that appears at its inputs. The inverted logic signal is used as an input for a timer 186 (such as a Texas Instruments timer identified as: NE 555). The timer 186 has a 10 microfarad capacitor 188 connected between pin No. 2 and ground that is normally in the discharged state. When an enable signal appears on pair 140a, the output of the differential receiver 184 will go low. This inverter turns off transistors Ql and Q2, which are normally on. This allows capacitor 188 to begin charging slowly. The timer 186 monitors the voltage on capacitor 188. When the voltage across capacitor 188 equals the threshold point, the output of timer 186 pin 3 will go low. This will only happen if the enable signal has been on for an excessive period of time. Transistor Q2 operates the reset pin No. 4 of the timer 186. When the enable is first turned on, the reset signal on pin No. 4 is removed and the output will remain high. It should be noted that during normal operation, the enable signal will be removed in a much shorter time than it takes for capacitor 188 to charge through a 1 megohm resistor 190 and cause the output to go low. In other words, in normal operation, the timer output will follow the logic enable level (not the output of the differential receiver 184 (26LS33) which is inverted from the logical meaning of the input enable signal). When the enable signal is removed from the input 140a, the capacitor 188 will discharge rapidly through a IK resistor 192. With the arrangement just described, it is permissible if transmitting multiple images from the same node to be enabled for a reasonably long period of time, i.e. one-half to one second and then be turned off for a short amount of time i.e. one-tenth of a second, and it will still operate properly. Section II maintains the power supply at a reasonable level. In the event the power supply level falls outside a reasonable range, transmission on the image channel 34 is precluded. A zener diode 194 is used to monitor the level of the positive regulated power supply. Transistor Q3 is only turned on when the power " supply is close to its full voltage level. If the voltage level of the power supply drops below the normal operating level to 4 volts, Q4 is turned on which quickly discharges 100 microfarad capacitor 196. If Q4 is turned off, the capacitor 196 will charge slowly through the 27K resistor 198. Thus, it is the voltage level across the capacitor 196 that is used as an input to Section III. Section III monitors the voltage across capacitor 196 in Section II through a zener diode 200 (2.8 volt), the purpose of which is to determine if the voltage level is adequate and has been so for a while. This provides a bit of a margin to ensure that the circuit has been turned on and has actually reached an operating voltage level before any transmissions are allowed. Section III combines the timer in Section I to operate the reed relay 202that switches the transmission of data onto the image channel 34. The output of the timer 186 in Section I is used to control the operation of transistor Q5 which in turn provides a low signal to drive transistor Q7. Transistor Q6 provides an active low signal to drive transistor Q8. When both Q7 and Q8 are operating, the reed relay 202 is driven via transistor Q9. Operation of the reed relay 202 allows the transmission of image data on the image channel 34. Section IV acts as a voltage follower which uses the shield 203 on the coaxial cable as a reference and uses transistors Q10, Qll, Q12 and Q13 as a voltage follower (it follows the reference voltage within 1 volt). Connected between the coaxial shield 203 and signal ground (SG) is capacitor 204 (4.7 μf non-polarized) with a second capacitor 206 (1 μf non-polarized) being connected between active ground (AG) and signal ground. As a result of this, the voltage offset between the shield signal ground and active ground will not change very rapidly. Active ground is established by transistor Q10 through Q13 and is used as the reference ground for a pair of voltage regulators 208 and 209, which provide +5 volts and -5 volts respectively. It is this power supply relative to the active ground that is used to power all of the integrated circuits within the transmitter tap as well as the majority of the discrete components. Section V, the final section, is a data driver. It receives the differential data signal of the image in RS-422 format via differential receiver 210, the output of which is sent to the input of an open collector inverter 212 (such is manufactured byTexas Instruments and which is known as: SN 74S05) which operates on the data signal such that when the logic signal is low, the inverter 212 will drive the level to active ground (AG). When the logic state of the data is high, the inverter 212 will allow the voltage to go high, turning off Q14 and Q15. Transistors Q14, Q15, Q16 and Q17 form together the driver circuit which drives the cable voltages between -4 volts and +4 volts. When the data signal is at a logic low, both Q14 and Q15 are conducting. As a result of the operation of Q14, the voltage across the 820 ohm resistor 214 is raised to a level very close to that of the positive supply (+5 volts). Thus, with Q14 and Q15 turned on, the cable voltage will be lowered to near the level of the negative power supply voltage (-5 volts). When the data level is high, both Q14 and Q15 are turned off and as a result of this, Q15 can no longer cause Q17 to conduct. With Q14 turned off, the resistor 214 will activate Q16 causing the output voltage to approach the level of the positive supply (+5 volts). It should be noted that the 24 ohm resistors 226 and 227 are used to provide impedance matching between the output of this driver stage and the coaxial cable of the image channel 34. Because 50 ohm coaxial cable is used and the output is connected to the image channel by a "tee" connector 143a with a cable going out in two directions or two pieces of cable, the drive impedance must be 25 ohms. The receiver tap circuit is shown in Fig. 16. The receiver tap 144 connects to the image channel 34 in a manner similar to the transmitter tap 142 discussed earlier. A "tee" connector 143b is used to physically connect the tap 144 to thecoaxial cable. The input port to the receiver tap 144 uses an MOV 216 to limit the relative voltage between the shield 203 and the signal ground. A 1 μf non-polarized capacitor 218 limits the rate of change between the two voltages. Transistors Q18, Q19, Q20 and Q21 act as a voltage follower and provide an active ground, within 1 volt of the shield 203, to all the integrated circuits in the receiver tap 144. Voltage regulators 220 and 221 are used to reference to the active ground at the output of the voltage follower. The data signal is fed to the input of comparator 222 which converts the signal to transistor transistor logic (TTL) levels. The output of the comparator is sent to a differential driver 224 which in response to that input, produces differential signals in RS-422 format. Figure 17 shows the schematic for the image receiver 148. As discussed earlier, the image receiver 148 has two input ports, one is the control connection from the computing section of the receiver which places a single logic signal on the receiver enable/disable line 152. The second input port is connected to data path 146a, which is also a single differential signal pair and corresponds to the image data coming in from the output of the receiver tap 144. In this data input path 146a is a differential receiver 228. The differential signals are converted to TTL signals which appear at the output of the differential receiver 228. This logic signal is fed to flip-flops 230 and 231 which are connected to act as a shift register which samples the incoming data at a 50 MHz rate and then sends the outputs of the two flip-flops 230 and 231 to the inputs of an exclusive OR gate 232, which provides edge detection. Any time there is an edge detected in the input data signal, there will be a pulse for one 50 MHz clock cycle on the output of exclusive OR gate 232. This edge detection is an important part of the receiver. A single edge will generate a single pulse at the output of gate 232, indicating a data zero bit, while a sequence of two edges will generate a pair of pulses, indicating a data one bit. The output of exclusive OR gate 232 is fed to a three-bit shift register that consists of a series string as follows: flip-flop 234, NAND gate 235, flip-flop 236, NAND gate 237, flip-flop 238, and NAND gate 239. The three-bit shift register is necessary because of a timing skew, which will allow the two pulses representing a logic one to manifest itself in three different forms each of which would be a valid logic one. The three forms that may occur are (1) two pulses adjacent each other; (2) two pulses with a single 50 MHz clock period in between; and (3) two pulses with two blank 50 MHz clock periods in between. Therefore, a three-bit shift register must be used because a second pulse could be in any one of three different positions. The three positions in this shift register correspond to these three possible cases. The final output of the shift register is sent to an additional flip-flop 240. When the first of the two possible pulses reaches flip-flop 240, the three-bit shift register will indicate whether the data bit is a zero or a one. When the first of the two pulses gets to flip-flop 240, the three positions of this shift register must be monitored to see if a second pulse was received. In the event a second pulse is found in any one of those three positions, it would indicate the existence of a data logic one. However, if a pulse is not present in any of those three positions, the bit of data would be a logic zero. At the output of flip-flop 240 is a clock pulse, the presence of which indicates the existence of either type of logic bit (this signal is labeled RC2). After the clock pulse has passed through the three-bit shift register, the NAND gates 235, 237, and 239 are used to cancel the second pulse so that the next bit of data will not be incorrectly interpreted as a clock pulse. The output of flip-flops 234, 236, and 238 are fed to OR gate 242 which will have an output RD2 if a pulse is present at the output of any one of these three flip-flops. Thus, when RC2 is high a bit is present with RD2 indicating the logic state of that bit (i.e., whether it is a one or a zero). Because RD2 is only valid for one clock period of the 50 MHz clock, it must be retained. Signals RD2 and RC2 are fed into flip-flops 243 and 244 respectively for the purpose of re-synchronizing the data. (Because of the limited number of gates that may be used between flip-flops due to the high operating speed, it is necessary to introduce the additional pair of flip-flops in order to maintain the correct timing sequence) A two input multiplexer is formed by NAND gates 246, 247, and 248 the output of which feeds flip-flop 250 wired in such a configuration that it acts as a register for holding data. The multiplexer formed by NAND gates 246, 247, and 248 can output one of two signals into flip-flop 250. It can load the RD3 signal or it can reload flip-flop 250 with its own contents, thereby preserving the data. The output of the multiplexer formed by NAND gates 246, 247, and 248 is selected by signal RC3 so that when RC3 is present, thatindicates that new data is present and flip-flop 250 is loaded with the new data. When RC3 is removed, the content of flip-flop 250 remains the same. The output of flip-flop 250 is the equivalent to the originally transmitted image data. It is also necessary to provide an output clock signal which should be approximately a 50 nanosecond, pulse, commencing subsequent to the period in which RC3 is high. To accomplish this, flip-flop 252 is used with its data input driven by OR gate 251 so that when flip-flop 252 is set, it remains so until it is cleared by AND gate 256. Therefore, RC3 will set flip-flop 252 at the proper time, and AND gate 256 will be used to clear it 50 nanoseconds later. A 40 nanosecond delay is created by flip-flops 253 through 255, arranged as a shift register, and AND gate 256 adds a 10 nanosecond delay because its other input is connected to the inverted 50 MHz clock. Thus, the output of flip-flop 252 is a 50 nanosecond pulse placed on clock line 150c. It should be noted that the active-low data valid signal is recreated at the output of flip-flop 260. It is asserted simultaneously with the rising edge of the output video clock, and remains in that state until the enable line 152 from the computer (not shown) in the receiver is turned off. Figure 18 shows the timing signals associated with the image receiver 148 and illustrates the manner in which the incoming signal is decoded back into differential paired signal levels (RS-422 type). THE WORKSTATION The individual workstations used in conjunction with a dual channel communication network will now be discussed in detail. Image information generally involves substantially more data than control information, and if this data is communicated within the workstation or the image source, there can either be a substantial loss of performance of the system, or on the other hand, if an effort is made to accommodate this additional data within a conventional workstation, the bus structures and data processing electronics within the workstation or image source must be considerably more complicated to support the increased amount of data associated with the image transmissions. Thus, the workstation 262 shown in Fig. 19 separates the handling of image information from the handling of control information within the workstation 262. This is accomplished by dividing the workstation 262 into two sections, a data processing section 264 and an image section 266. The architecture for this type of workstation must be able to perform both the basic workstation functions normally associated with a personal computer, plus the capability to handle high-resolution compressed bit-mapped images entering the workstation on the image channel 34. The control channel 32 enters the data processing section 264 of the workstation 262 and is connected to the control channel interface module 267 which comprises a conventional interface module ® such as an RS-232 interface or an ETHERNET interface. The CPU 268 performs the normal functions associated with a workstation or personal computer. CPU 268 communicates through data path 270 with keyboard 271 to provide the necessary operator interface. CPU 268 communicates with other components in the data processing section 264 viaCPU bus 269. In addition, the disk drive 273 communicates through disk drive controller 274 with CPU 268 via the CPU bus 269. The functions of the components (267, 268, 272 and 274) all perform functions normally associated with a personal computer type of workstation. A control signal interface module 276 is used to handle communications between the image section 266 and the CPU 268. Image channel 34 is connected via a "tee" connector 143b to receiver tap 144 which in turn is connected via data path 146 to image receiver 148. The image receiver 148 decodes the information from the image channel 34 and sends the decoded image signal out on data path 150 to a buffer memory 278 which stores the data associated with one or more images or image packets sent on the image channel 34. These images or image packets are sent to an electronic processing circuit 280 on data path 281. The function of the electronic processing circuit 280 is to receive and manipulate the image data from the buffer memory 278. If the image data is compressed, it must be decompressed into a form suitable for bit mapping. The electronic processing circuit may perform such functions as scaling, rotation, zooming, or windowing of the image information prior to sending the information on data path 282 to bit-map memory 283. It is the function of the bit-map memory 283 to store in bit map format, the image data passed through it and to repeatedly refresh the display 284 via data path 285 to provide a steady display of the image. It is also possible that the CPU 268 may send additional data to the control signal interface module 276 such as graphics which would, in turn, be sent on data path 286 to the electronic processing circuit such that this information may be processed and sent to the bit-map memory 283 via data path 282 so that such things as characters and other information may be placed on display 284, in addition to the images received on the image channel 34. The control signal interface is connected directly to the buffer memory 278, electronic processing circuit 280 and the bit-map memory 283 by data paths 288, 286 and 289 respectively. The control signal interface module 276 in turn generates control signals to buffer memory 278 through data path 288, to an electronic processing circuit 280, through data path 286, and to bit-map memory 283, through data path 289. The data information may be image information or the status of particular functional components within the system. While the control information will generally be originally generated by CPU 268, its function is to execute both control and data processing programs associated with the overall function of the workstation. The control programs generally send control information through bus 269 to the specific module to be controlled, for example, control channel interface module 267, disk drive controller 274, and the control signal interface module 276. The various data and control paths within the workstation provide considerable flexibility in terms of the specific functions which the workstations can perform. By way of example, consideration will now be given to a description of the path and flow of control signals which occur when an image is received from the image channel by the image receiver 148, and placed on the display 284 and that same image is stored in the disk drive 273. As already discussed, the first step in the process of receiving an image is for the control channel 32 to communicate through control interface 267 to CPU 268 via bus 269. The CPU then sends control signals through bus 269 to control signal interface module 276 which generates further control signals on data path 288 to buffer memory 278. These control signals define the locations within buffer memory 278 where the image signal coming in on data path 150 is to be placed. The CPU 268 then continues to monitor the image transfer process coming from the image receiver 148 via data path 150 to buffer memory 278 (again through control line 288 and control interface module 276), until the buffer memory 278 contains the required image or images. At this time, the CPU 268 sends additional control signals to control signal interface module 276 to cause further control signals to be passed through data path 286 to electronic processing circuit 280. The control signals are generated in response to an input on keyboard 271 by the operator through line 270 specifying how the electronic processing circuit 280 is to process the image in buffer memory 278. Processing options such as compression or decompression, zooming or scaling, and rotation are activated through the control signals that are generated by CPU 268 and sent to control signal interface module 276. These signals are passed to both buffer memory 278 through data path 288 and electronic processing circuit 280 through data path 286, to orchestrate the passage of the data from the buffer memory 278 to the electronic processing circuit 280. Control signals are also generated to bit-map memory 283 specifying where and how the image which electronic processing circuit 280 will send on line 282 will be stored in bit-map memory 283. Once these control signals are sent to the buffer memory 278, electronic processing circuit 280 and bit-map memory 283, the CPU 268 generates a command for the process of transferring the information from buffer memory 278 through data path 281 to control processing circuit 280. The processed signal is then sent on data path 282 to bit-map memory 283, where it is stored. All the control signals needed to initiate the process just described are generated by the control signal interface module 276 in response to commands from the CPU 268. Once the image has been read from buffer memory 278 to electronic processing circuit 280 and the processed data passed and stored in bit-map memory 283, the CPU 268 generates further control signals to activate the bit-map memory 283 to repeatedly send the image through data path 285 to display 284 to maintain on the display the image of the processed data stored in bit-map memory 283. It should be understood that the original image data may still reside in buffer memory 278 but to make the buffer memory 278 available for further images, this image data may be erased or it may, before being erased, first be passed through data path 290 to disk drive control 274, and then to disk drive memory 273. Again, the passage of this data is orchestrated by CPU 268 through CPU bus 269, using standard techniques for transferring data from memory to a disk drive. Figure 20 shows the detail of the buffer memory 278 which receives the image channel data from image receiver 148 on data path 150 where it is sent to a serial to parallel converter 301 which receives the serial data on line 150 and under the control of control and address generator 310 converts the image data into a parallel stream along tri-state data bus 303. The data from the serial to parallel converter 301 is passed via the tri-state data bus 303 to memory 304 where it is stored synchronously with the receipt of the image on data path 150 (which is referred to as the image receiver data output). As the data flows from the image receiver 148 along the output data path 150, the serial to parallel converter converts the serial data stream on line 308 which is the actual image data into a parallel signal on tri-state data bus 303. In order to insure that this process occurs synchronously, the clock signals on line 309 are received by the control and address generator 310. The control and address generator 310 then generates a clock signal on line 311 to drive the serial to parallel converter 301 and also generates an output control signal on line 312 to enable the output of serial to parallel converter 301. In addition the control and address generator 310 generates control and address signals on line groups 313 and 314. These signals specify to memory 304 when to receive and where to store the data entering on the tri-state data bus 303, which is the output from serial to parallel converter 301. Simultaneously with this process, the optional error detection function 305 receives the image data from tri-state data bus 303 and checks for the presence of errors in the incoming data. As we have discussed previously, the error detection circuit may be preloaded with the error detection code through control signal interface module 276 and via data path 288, which generates control signals to both the control and address generator 310, the disk input/output interface 306, and the error detection circuit 305. Thus, the error detection code may have been received on control channel 32 in conjunction with operation of control channel interface module 267, CPU bus 269, and CPU 268 to send to the control signal. interface module 276 and thence on data path 288. The error detection code is resident in the error detection circuit 305 during the time that the images are being received on the image channel 34. It will be appreciated that there are within the workstation described in Figure 19, alternate means of implementing error detection functions. For example, the error detection code could be left in the CPU 268 and the error detection circuit 305 could provide data to CPU 268 allowing it to compare the error detection code and the output of the error detection circuit 305 as each complete Image or as each image block is received. As an alternative, it can be appreciated that if an error should be detected, then the CPU in conjunction with the control channel 32 and the image channel 34 can request the re-transmission of an image. Once the image data has been written into memory 304, it may be read from memory on tri-state data bus 303 and passed to disk input/output interface 306, and thence to the disk drive via line group 290. The image data stored -in memory 304 may also be outputted through tri-state data bus 303 to buffer 307, and thence on line 281 to electronic processing circuit 280. Whether the memory 304 is being read from or written into, the control and address generator 310 actively performs the function of generating appropriate address and control signals in order to cause the memory 304 to function appropriately. Furthermore, through control lines 288, the initial values and incremental values of these addresses may be adjusted upon command from CPU 268. In addition, the control and address generator 310 is responsible for generating appropriate clock signals on data path 315 to the disk input/output interface 306 and on data path 316 to the error detection circuit 305. Data path 317 also contains control signals which are sent to buffer 307. These same signals are passed through buffer 307 and sent on data path 281 to enable synchronous receipt and optionally acknowledge when data is being passed to electronic processing circuit 280 through data path 281. Alternatively, when an image is stored on disk drive 273 and is to be sent to display 284, a slightly different routing occurs. The signal is sent from disk drive 273 to disk drive control 274 and then on data path 290 to disk input/output interface 306 which in turn places the image signal onto tri-state data bus 303 to memory 304. The selection of these control paths of course, is supervised by CPU 268 in each case. The bus 303 may be, for example four, eight or sixteen bits wide, and interfaces into memory 304, into error detection circuitry 305, and also into the disk I/O interface 306, as well as being interfaced to the buffer 307 to connect to the electronic processing circuit 280 through data path 281. Figure 21 shows the electronic processing circuit 280 in more detail. Line 281 from buffer memory 278 contains data which is passed to the decompressor circuit 326 (e.g. integrated circuit AMD-7970) so that images read from memory 304 may be decompressed into bit-mapped form. This process is performed under the control of the control and address generator 328 which receives data from the control signal interface module 276 on data path 286, which establishes the conditions required to send data during decompression. The control and address generator 328 receives synchronizing and/or acknowledging data from data path 281, part of which is sent on data path 330 and is used to generate control information for decompressor 326 via address line 332. The address information is sent to decompressor circuit 326 via address lines 334. (It will, of course, be appreciated that as an alternative, the control and address generator 310 could be used to generate some of the control signals and address signals found in address lines 332 and 334). The output of decompressor circuit 326 is sent to buffer memory 336 on a line-by-line basis or data path 342. The bit map pattern of the image under control of signals being sent on control line 338 and address lines 340, the latter having been generated by control and address circuit 328 in conjunction with the decompressor circuit 326. Buffer memory 336 is a dual port buffer memory such that data may simultaneously be written into the buffer memory 336 through the data path 342 which carries the output signal from the decompressor 326 in the form of bit-mapped data. Data may simultaneously be read through data paths 344 and 346 to shift registers 348 and 350. Control signals from control and address generator 328 on line 352 generate a control signal to synchronize shift registers 348 and 350. The purpose of buffer memory 336 is to provide a partial bit map buffer which is used in the process of scaling. This process is performed by shift registers 348, 350, memory 354, and address clock and generator 356. Previous line information required by certain decoding functions is provided to decompressor 326 via data path 342. The scaling functionality operates by providing to memory 354 a region of pixels, for example a two-by-two array, two lines by two pixels; however, the number may be more, for example, three-by-three or four-by-four, so that memory 354 can output on data path 355 the value of one or more pixels in the resulting scaled image. These pixels correspond to pixels within the region defined by the pixel values and appear on the output of shift registers 348 and 350 on data paths 358 and 360 respectively. This process is synchronized by address and clock generator 356 which also supplies to the second port of buffer memory 336 the address of the data, which is to be clocked out on data paths 344 and 346, via the clocking signal on line 362. The signal on data path 355 is then sent to buffer 364 the output of which is sent on data path line 282 to bit-map memory 283. Also included on data path 282 is synchronizing clock signals which are generated by address and clock generator 356 on clock line 366. The control and address generator 328 and the address and clock generator 356 both receive control signals on data path 286 from the control signal interface module 276 which are under control of CPU 268. Any required synchronism between control and address generator 328 and address and clock generator 356 is accomplished by line connection 376. Figure 22 shows the detail of bit-map memory 283. Bit-map memory 283 comprises video memory 368 which is comprised of a video RAM chip array which receives data from data path 282 from electronic processing circuit 280 and in conjunction with control circuit 370 generates address data to the video memory 368 to enable the writing from data on data path 282 into video memory 368. The address data passes from control circuit 370 on line group 372 while some of the lines in data path 282 provide control and timing information to the control circuit 370. This control and timing information is generated by address and clock generator 356 and the signals placed on clock line 366. This signal is passed through buffer 364 onto data path 282. The control and timing signals are then sent via line group 374 to control circuit 370. The control circuit 370 is initiated by the signals on data path 289 from the control signal interface module 276 which also generates an internal timing signal to provide for the generation of synchronizing signals for display 284 through connector 285 which connects to display 284 through output buffer 380. This timing and address information associated with driving the memory is also sent on line 372 from control circuit 370 to video memory 368 to enable the video memory to output on data path 382 the video information associated with the image stored in video memory 368 which was written by the signal present on data path 282. Additional writing paths into video memory 368 are also implemented through data path .384 from control circuit 370. This enables the CPU 268 to write into video memory 368 via CPU bus 269, control signal interface module 276, data path 289, control circuit 370 and also to read data from video memory 368. Thus, it can be seen that use of a network of the type just described reduces the time it takes to transmit large data packets such as images from one station to another in the network. Advantages and Industrial Applicability In order to better appreciate the advantages realized by transmitting image data on a two channel network, the following table is provided. Compared is a single channel network vs. a two channel network that uses a control channel and an image channel in accordance with the present invention. Single Channel Dual Channel Category Network Network Maximum Effective 2 Mega bits/sec. 9.5 Mega bits/sec Date Rate Approximate Pro¬ 700,000 instruc¬ 12,000 instruc¬ cessor Cycles at tions/sec. tions/sec. the receiver and transmitter to support maximum data rate Number of Medium 100-200 IC's 25 IC's (in Image Size Integrated Channel); 5-200 I Circuits (IC's) (in Control Chann Approximate num¬ 100 data packets I data packet ber of Packets per 100 Kilobytes 100 Kilobytes 100 Kilobytes of image data Packet Size 1 Kilobyte 256 Kilobytes Effective Data 6% - 20% 80% - 95% Rate as % of Maximum Data Rate Such a networking approach imposes certain requirements on the nodes using it. These requirements include (1) that the nodes must be capable of communicating with both the control channel and the image channel; (2) each node must be able to receive and/or transmit 100 kilobytes of data at the full 10 megabit per second data rate used on the image channel without a pause; (3) scheduling of the image channel time slots would be the responsibility of one or more of the nodes. The use of centralized computer systems is giving way to networks with the goal being to make all programs, data, and other resources available to anyone on the network without regard to the physical location of the resource and the user. Such a system could find application in companies or government agencies that require a large database of document images. Computer aided education is another possible candidate for use of a network of the type described above. Another major area of potential use for such a system that would access remote databases would be making reservations for airplanes, trains, ships, hotels, restaurants, and theatres, and automated retrieval of documents such as in libraries, newspapers, and insurance companies or other financial institutions.

Claims: CLAIMS: 1. A digital data communications network having a plurality of peripheral nodes, said network characterized by: a control channel connected to said plurality of nodes; an image source located at one or more nodes; an image channel connecting said plurality of nodes; scheduling means located at one or more nodes; said scheduling means controlling the communications on said image channel and controlling access to said image channel by said image source and said nodes; and indexing means for providing the physical location of the images within said image source. 2. The invention set forth in Claim 1 wherein one of said nodes is a raster image printer. 3. The invention set forth in Claim 1 wherein said control channel takes the form of an RS-232 type connection between nodes. 4. The invention set forth in Claim 1 wherein said control channel is in the form of a bus configuration. 5. The invention set forth in Claim 1 wherein means are provided for supplying additional images to said image source and updating said indexing means as to the physical location of said additional images. 6. The invention set forth in Claim 1 wherein scheduling means further includes means for establishing priorities associated with said nodes regarding access to said image channel. 7. A digital image data communications network having a plurality of peripheral nodes, said network characterized by: a control channel connected to said plurality of nodes; said control channel being capable of bi-directional communication in conjunction with a given transaction; an image source located at one or more nodes; an image channel connected to said plurality of nodes and being capable of mono-directional communication between nodes in conjunction with a given transaction; scheduling means for controlling direction, duration and priority of the communication on said image channel via said control channel and controlling access to said image channel by said image source and said nodes; indexing means for providing the physical location of said images within said image source; and said indexing further including means for supplying additional images to said image source and updating said indexing means as to the physical location of said additional images. 8. The invention set forth in Claim 7 wherein said control channel carries error detection information on said image channel. 9. A digital data communications network having a plurality of peripheral nodes, said network characterized by: a control channel connected to said plurality of nodes; a first image source located at one or more nodes; a second image source located at one or more nodes; first and second image channels connecting said plurality of nodes; a first group of nodes connected to said first image source by said first image channel; a second group of nodes connected to said second image source by said second image channel; a third group of nodes connected to said first and second image sources by said first and second image channels; scheduling means located at one or more nodes; said scheduling means controlling the communications on said control channel and providing access to said images channels by said image sources and said nodes; and indexing means associated with each of said image sources for providing the physical location of the images within the respective image source.

Inventors: KUEHL ROBERT BURNEY, MORTON ROGER ROY ADAMS, SCHUECKLER JAMES ROBERT, SCOTT KEVIN CRAIG, KUEHL, ROBERT, BURNEY, MORTON, ROGER, ROY, ADAMS, SCHUECKLER, JAMES, ROBERT, SCOTT, KEVIN, CRAIG
Applicants: EASTMAN KODAK CO, EASTMAN KODAK COMPANY
Application year: 1987
Main classification: H04N1
IPC codes: H04L12, H04N1