METHOD OF MAKING HIGH DENSITY INTERCONNECTION SUBSTRATES USING STACKED MODULES AND SUBSTRATES OBTAINED

Abstract: In order to provide for interconnection of a plurality of electronic components, thin sheets (20, 21) of an appropriate dielectric material have holes (22) drilled therethrough. The holes (22) are then filled with a conducting material (23) and the surfaces of the substrates (24) are lapped to insure smoothness. A conducting pattern (25, 26) (i.e. of conducting traces) is formed on the surfaces of the dielectric sheets. Conducting regions are also formed on the dielectric sheet surfaces. A first sheet (21) of dielectric material has conducting dots (27) applied to the conducting regions on a first surface. A second sheet (20) of dielectric material is aligned with the first sheet so that conducting regions of a second surface of the second dielectric sheet (20) can be coupled to the conducting dots (27). The structure is processed so that the conducting dots (27) cause the two dielectric sheets (20, 21) to be joined both physically and electrically at the conducting regions. By appropriate arrangement of the conducting regions, conducting traces (26) on adjacent surfaces of adjoining dielectric sheets (20, 21) and conducting traces (26) on opposite surfaces of a dielectric sheet (20, 21) can be coupled to provided appropriate interconnection of electronic components.

Description: Method of making high density interconnection substrates using stacked modules and substrates; obtained. BACKGROUND OF THE INVENTION 1. Field of the Invention This i vention relates general ly to electronic circuits and more particularly to the structure of substrates, to which the electrical components are coupled, that provides the conducting paths electrically coupling the components. 2. Description of the Related Art It is known in the related art to fabricate interconnection structures providing the electrical coupling between electronic components in which thin film technology provides layers of con ucting paths (e.g. sputtered and plated chromium copper) on top of layers of insulating dielectric material (e.g. polyimide). The interlayer conductive coupling is provided by reactive ion etching or similar dry etching techniques to provide openings (or vias) in the layers and filling the resulting openings with metal. The multilayer structure is formed on a base ceramic or similar stable material. The layers are formed one over the other with one layer processed at a time. The resulting substrate can provide a very high interconnection density and can be made hermetic by sealing the substrate. Thus, the desired substrate configuration is developed in a multiplicity of serial, process s eps. T e usefulness of this technique for providing an interconnection structure is limited by the yield, cost and fabrication cycle time. In addition, as the thickness of the dielectric layers decreases, the interlayer capacitance increases and can limit the signal propagation in the structure. It is also known in the related art that a multilayer interconnection structure can be based on the printed wiring board technology consisting of reinforced polymer dielectric material sheets. The interlayer conducting paths are formed by mechanical riLling of the sheets and πietalizatio of the interlayer paths by electrodeless and electro¬ plating. The sheets are coupled by lamination techniques using polymer material to bond the layers together. This technique for providing an interconnection structure is limited by material stability, moisture absorption, feature resolution in processing the inner sheet, process limitations in drilling and plating, processing, and density and reliability problems resulting from process tolerances. To overcome these limitations, subassemblies with reduced layer count are processed as multilayer sheets assembled * in the conventional manner. Because of the lower number of layers and the reduced board thickness, the length of the in erlayer con u ting pa tis can be reduced. The subassemblies can be laminated together to provide a total interconnection structure. In erconnection paths between the subassemblies can then be drilled and electroplated. This technique re uces but does not eliminate the limitations found in the conventional multilayer substrate fabrication technique. It is also known in the related art to use hybrid technology techniques (i.e. thick film or cofired techniques) using a ceramic dielectric material) and thick film conducting materials. The resulting structures are very stable, can wi hstand ' higher processing and operating temperatures and provide hermeticity. However, the technique has severe processing restrictions that limit the density of the conducting traces (and the spaces therebetween) and the vias on the in erconnecxt substra e . An additional characteristic of serial techniques is that discrepancies in the placement of one layer on the adjacent layer are retained or magnified when additional layers are added. Also discrepancies in the planarity of one layer are retained or magnified when additional layers are added. These characteristics result in a limitation in the number of layer hat an in erconnect substrate can have. An opening (or via), in which a conductive path from one side of the layer to the other is desired, can be required only in a single layer of the substrate. The conducting path In a singLe substrate layer is difficult to accomplish with conventional techniques, so openings are typically drilled through all layers of the substrate. This procedure imposes design limitations because of the traces that must be routed around the the openings. Still another limitation in serial processing techniques occurs because the substrate can be tested only at the end of the fabrication process. A need has therefore been felt for a technique for providing interconnect substra-tes that can achieve high density interconnection coupling paths without the limitations on yield, number, cost and cycle time of the serial processing techniques. FEATURES OF THE INVENTION It is an object of the present invention to provide an improved interconnection structure for coupling electronic components. It is a feature of the present invention to provide an interconnection structure that is fabricated as a plurality of subassemblies and, after -5- testing, the subassemblies are coupled in a the final structure. It is still another feature of the present invention to provide an interconnection s ructure that is comprised of a plurali y of stacked dielectric layers, each dielec r'ic layer separated a gap- It is a still further feature of the present invention to provide an interconnection structure that has a high density of conducting paths without the limited yield and cycle time resulting from multiple serial processes. SUMMARY OF THE INVENTION The aforementioned and other objects are obtained, according to the present invention, by abricating a lu ality of diele ric sheets airs. The dielectric sheets have holes drilled therein and the the holes are filled with a conducting material. The sheets are then lapped to the appropriate dimensions and the conducting traces and conducting regions (or pads) are deposited on both surfaces of the dielectric sheets. A conducting bonding material (dot) is placed on conducting testing regions of a dielectric sheet to be electrically coupled to a conducting regions of an adjoining dielectric sheet. The two dielectric sheets are aligned so that the dielectric sheet conducting regions to be electrically coupled are contiguous and the two dielectric sheets are joined together. The two dielectric sheet subassembly is fired to bond the two sheets together. In a similar manner, a plural ity of dielectric sheet pairs can be joined together to form a multilayer circuit board. These and other features of the present invention will be understood upon reading of the following description along with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a flow diagram of the steps involved in fabricating a dielectric sheet pair for a circuit board. Figure 2A through Figure 2H show cross-sec ions of the two dielectric layers illustrating the steps in the fabrication of a dielectric sheet subassembly. Figure 3 shows a perspective view of an interconnect substrate having a plurality of dielectric sheets and illustrating the presence of coupled electrical components. Figure 4 illustrates the effect of the air gap of the present invention providing an air dielectric medium between sets of conducting paths on the surfaces of the dielectric layers. DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Detailed Description of the Figures Referring now Figure 1 , he f brication of a interconnec substrate begins in step 100 with two sheets of dielectric material. In the preferred embodiment, the sheets of dielectric material are fused quartz of thickness 2 to 10 mils, however other sui able Le I o L r i c: ma erials c n lie used. I n slop 101, holes are formed in the dielectric sheets. In the preferred embodiment, the holes are produced by a C0-, laser and have a diameter of 1 to 4 mils. In step 103, the holes are filled with a conducting material, such as JMI 4270, produced by Johnson- Matthey Electronic Materials Division, and the dielectric sheets are' dried and fired to. provide coupling of the fill materials to the sheet. If necessary, step 104 repeats step 103 until the fill material generally extends above the plane of the dielectric sheets. In step 105, the surface of the sheet is lapped so that the sheets have the desired thickness and flatness. In step 106, the pattern of conducting traces are deposited on the surfaces of each of the dielectric sheet using a thin film process. In the preferred embodiment, a chrome-copper seed layer is deposited. In step 107, the conducting traces are plated up to the desired thickness (by electroplating process) and conducting regions are formed. In step 108, this process is repeated for all the sheets that will comprise the final structure. In step 109, the -8- conducting traces are tested to insure that the process h s been u ces ful. In step I I 0, contlucLLng dots are contact printed to selected conducting regions of the top surface of he bott m dielectric sheet. In step 111, the sheets are aligned (so that appropriate conducting dots of a oining dielectric sheets are properly aligned) and the two dielectric sheets are joined. In step 112, the dielectric sheet pair is dried and fired joining the two dielectric sheets. These processes are repeated for each dielectric sheet pair to be joined . n the interconnect substrate in step 113. In step 114, an inspection and electrical test of the interconnect substrate are performed. , Referring next to Fig. 2A through Fig. 2B, the process steps described in Fig. 1 are illustrated by cross-sectional views of sheets of dielectric materials 20 and 21. In Fig. 2A, the holes 22 fabricated in the dielectric sheets are shown. In Fig. 2B, the filling of the holes with conducting material 23 is shown. In Fig. 2C, the result of the lapping operation sheet surfaces 24 is shown. In Fig. 2D, the process of depositing conducting seed layers 25 on the surfaces of the dielectric sheet is illustrated, while the result of the process of increasing the thickness of the conductors 26 is shown in Fig. 2E. In Fig. 2F, the placing of the conducting dots 27 on the top orti.on of the bottom sheet of the dielectric sheet is shown, while in Fig. 2G, the joining of the sheets and the contacting of the conducting dots 27 with the conductin regions is illustrated. A portion of the circuit board showing the coupling of dielectric sheet irs 28 and dielectric sheet pairs 29 by means of conducting dots 27 is shown in Fig. 2H. Referring to Fig. 3, an interconnection structure 30 is shown. The illustrated interconnect substrate includes dielectric sheet pairs 31, 32 and 33.° The top-most sheet of the structure includes the mounting apparatus for coupling electronic com onents 34 to the structure 30. The spacing between the individual dielectic sheets is exaggerated for purposes of illustration and portions of the conducting dots 27 and the conductor traces 26 are displayed . Referring next to Fig. 4, a feature of the interconnect substrate is illustrated. On sheet 41, the top conducting traces transmit information signals, while the bottom conducting traces transmit power • signals . Sheet 42 has the ground potential on the top conducting traces, while the bottom traces carry information si nals. On sheet 43, the top traces carry information signals, while the bottom conducting traces transmit power signals. On dielectric sheet 44, the top conducting traces maintain the ground potential, while the bottom conducting traces carry information signals. Between traces separated by a dielectric sheet, the impedance is determined by dielectric constant e. (for quartz, this value is appro imately 3.8), whi le for conducting traces separated by air, the impedance and propagation delay are determined by e~, (the dielectric constant of air is approximately 1). 2. Operation of the Preferred Embodiment For the interconnect substrates of the pre¬ sent invention, the density of conducting traces on a surface is the same as can be achieved with thin film .technology. In this technique, the ability to achieve small interlayer conducting traces of the order of 0.5-2 mils in size is important to achieve the required density. The filling of the holes with conducting material increases the cross-sectional area of the path as compared with non-filled hole techniques. This increase in cross-sectional area decreases the resistance and increases the reliability.- Moreover, because each surface with traces can be tested prior to incorporation in the interconnec ion structure, the problem resulting from yield of multiple serial processes can be minimized by using only the defect-free dielectric sheet pairs. The dielectric sheet material and the fill material can be chosen to withstand the thermal stre ses f he roce ing operat ion. These materials can also be chosen to be impervious to moisture. In addition, the structure can be hermetically sealed for additional stability. The thickness of the dielectric sheets can be controlled by the lapping process, permitting the impedance of the conducting traces with respect to reference dielectric sheet surface conducting traces on to be precisely controlled. In ig. 4, the dielectric material is interposed between information signals and the ground and power dielectric sheet surface conducting traces. Depending on the manner in which the signal conducting traces are referenced to the power or ground potential dielectric surface conducting traces, the option is available of using air or quartz as the dielectric medium separating the signal dielectric surface conducting traces and the reference dielectric surface conducting traces. An air dielectric medium between the signal plane and the reference plane is more appropriate for rapid signal propagation, but control of the impedance for the air dielectric medium is less precise because of the effects of moisture on the dielectric constant. It will be clear to those skille in the art 4 that the technique for fabricating a interconnect substrate, according to the present invention, permits great flexibility in providing conducting paths between trace patterns on adjoining dielectric sheet surfaces. When the adjoining surfaces are on opposite sides of the a dielectric sheet, then the filled holes can be located at any position in a ielectric sheet h would be convenient for the electrical coupling, i.e. where the conducting traces to coupled overlap on opposite sides of the dielectric sheet. Similarly, the conducting dot electrically coupling two conducting traces on dielectric sheets on opposite sid.es of an air gap can be positioned wherever the conducting traces overlap on the aligned, dielectric sheets. n addition, a filled hole electrical coupling between conducting -trace surfaces on a dielectric sheet need only be coupled by a conducting trace to the location of a conducting dot to continue the electrical coupling to conducting traces on adjoining dielectric sheet surfaces. The design of the interconnect substrate therefore has addition freedom in the location of the conducting paths (or vias) between planes of conducting traces and in the pattern of the conducting traces in each plane (i.e. dielectric sheet surface) . The foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would yet be encompassed by the spirit and scope of the invention.

Claims: CLAI S ; 1. A interconnect substrate for providing a predetermined electrical coupling of components comprising; a plurality of dielectric sheets, said sheets having conducting traces on each surface of said sheet, wherein said conducting traces on each surface of said sheet are coupled by holes filled with a conducting material .in said sheet; and means for electrically coupling neighboring dielectric sheets. 2. The, interconnect substrate of Claim 1 wherein coupling means also provides a means for maintaining a separation between said neighboring sheets. 3. The interconnect substrate of Claim 2 wherein said coupling means is a conducting material, said dielectric sheets being aligned to position preselected conducting regions on a first dielectric sheet surface relative to conducting regions on a neighboring dielectric sheet surface. 4. The interconnect substrate of Claim 3 wherein said conducting traces are tested prior to coupling of a tested dielectric sheet into said interconnect s u b s t ra te . 5. The interconnect substrate of Claim 4 wherein an impedance of said structure is determined by a dielectric constant of said sheet. 6. The interconnect substrate of Claim 4 wherein an impedance of said structure is determined by a dielectric constant of air. 7. The interconnect substrate of Claim 4 wherein a one of said substrates is adapted to have said components coupled thereto. 8. The process for fabricating interconnect substrate for electrically coupling components comprising the steps of: forming holes in a plurality of sheets of dielectric material in predetermined locations on said sheets ; filling said holes with a conducting material; applying conducting traces and conducting regions having a predetermined configuration to surfaces of said sheets; placing conducting dots on preselected conducting regions of a first surface f a bottom dielectric sheet; aligning said first surface wi h a second surface of top dielectric sheet wherein said conducting dots are aligned with predetermined conducting regions on said second surface; joining said top and said bottom sheets by said conducting dots to form a interconnect substrate dielectric sheet pair. 9. The meLhod for fabricating a inLercoiuiect substrate of Claim 8 further including the step of coupling dielectric sheet pairs by performing said placing step, said aligning step and said joining step for said dielectric sheet pairs to be coupled. 10. The method for fabricating a interconnect substrate of Claim 8 wherein said filling step includes the steps of drying and firing said conducting fill material. 11. The method for fabricating a interconnect substrate of Claim 9 wherein said drying and firing steps are repeated a plurality of times until said conducting fill material is generally coplanar with said dielectric sheet. « 12. The method for fabricating an interconnect substrate of Claim 8 further comprising the step of electrically testing said dielectric sheet traces. 13. The method for fabricating an interconnect substrate of Claim 12 further comprising the step of coupling said components to a preselected dielectric shee . 14. The method for fabricating an interconnect substrate of Claim 9 further comprising the step of selecting a one of a dielectric constant of said dielectric sheet and a dielectric constant of air to determine an impedance between sets of said conducting- traces. 15. An interconnect substrate for electrically coupling components comprising: a plurality of dielectric sheets, each of said dielectric sheets including; a predetermined pattern of conducting traces on each dielectric sheet surface, and a plurality of hole filled with a conducting material, each of said holes electrically coupling a conducting trace on a first surface of said dielectric sheet with a conducting trace on a second surface of said dielectric sheet; and, SUB TT TESHEET a plurality of conducting structures mechanically coupling a first dielectric sheet to a second dielectric sheet, said conducting structures electrically coupling a conducting trace on said first dielectric sheet with a conducting trace on said second dielectric sheet. 16. The interconnect substrate of Claim 15 further comprising additional conducting structures for coupling additional dielectric sheets to said interconnect substrate. 17. The interconnect structure of- Claim 16 further comprising at least one dielectric substrate coupled to said interconnect substrate to which said components can be coupled. 18. The interconnect substrate of Claim 17 wherein each of said dielectric substrates is electrically tested before being coupled to another dielectric i substrate. 19. The interconnect substrate of Claim 18 wherein said coupling structures maintain a predetermined separation between said coupled substrates. 20. The interconnect substrate of Claim 19 wherein an impedance between adjacent conducting trace patterns can be determined by a one of a dielectric constant of air and a dielectric constant of said dielectric sheets.

Inventors: CZEREPAK STANLEY, SANKAR N GOWRI, CZEREPAK, STANLEY, SANKAR, N., GOWRI
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1987
Main classification: H05K3
IPC codes: H05K1, H05K3