SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CIRCUIT PORTION

Abstract: A semiconductor memory device including a regular memory cell array (41) in which a plurality of word lines (e.g., WL1) bit lines (e.g., BL1) are provided, and a plurality of memory cells (e.g., MC₁₁) are arranged at each intersection of the word lines and bit lines; a redundancy memory cell array (42) in which one or more word lines (WL R ) and bit lines (e.g. BL1) are provided, and a plurality of memory cells (e.g. MCR₁₁) are arranged at each inter­ section of the word lines and bit lines; a control unit (1) for generating a first control signal (ø WLA ); a unit (8) for programming defective address bits corresponding to a defective memory cell existing in the regular memory cell array (41); a unit (9) for comparing each logic of input address bits (a₀..a n ) with each of the defective address bits; a first switch for generating a second control signal (ø WLB ) when at least one logic of the input address bits does not coincide with the corresponding defective address bit and for supplying a third control signal (ø WLR ) to a pre­ determined word line or bit line belonging to the redundancy memory cell array without generating the second control signal (ø WLB ) when each logic of the input address bits coincides with each of the defective address bits; a unit (11), for identifying whether or not any defective address bits are programmed in the programming means (8); and a second switch (12) for supplying the second control signal (ø WLB ) input from the first switch (10) to a selected word line or bit line belonging to the regular memory cell array (41) when the identifying unit (11) indicates that defective address bits are programmed in the programming means (8) and for supplying the first control signal input (ø WLA ) from the control unit (1) to the selected word line or bit line when the identifying unit (11) indicates that no defective address bits are programmed in the programming unit (8).

Description: The present invention relates to a semiconductor memory device. Particularly, the present invention relates to a semiconductor memory device having a redundancy memory cell array. Generally, a conventional semiconductor memory device is provided with a row control circuit, a row address buffer, a row decoder and driver, a regular memory cell array, a sense amplifier, a column address buffer, a column decoder, and so on. A row address strobe signal ( RAS ) is input to the row control circuit from the outside, and the row control circuit supplies control signals to the row address buffer and the row decoder and driver at a predetermined timing, respectively. When the potential level of the signal RAS becomes low the control signal is supplied from the row control circuit to the row address buffer. The row address buffer then supplies row address bit signals to the row decoder and driver, and when the potential levels of the row address bit signals output from the row address buffer have been established, the control signal is supplied from the row control circuit to the row decoder and driver. The row decoder and driver then select a predetermined work line, and the potential thereof is raised in accordance with the potential levels of the input row address bit signals. Thus, in the read mode, data stored in a predetermined memory cell arranged at the intersection of the selected word line and a selected bit line provided in the regular memory cell array is read out through the selected bit line, sense amplifier, and data bus provided in the column decoder. Also, in the write mode, predetermined data is written from the outside to the predetermined memory cell connected to the selected word line through the data bus and the selected bit line. In this connection, the column decoder selects a predetermined bit line in accordance with potential levels of the input column address bit signals supplied from the column address buffer. There has been proposed a type of semiconductor memory device having a redundancy memory cell array in addition to the regular memory array. Provided in such a memory device are: a programming circuit for programming defective address bits corresponding to a defective memory cell existing in the regular memory cell array, a comparison circuit for comparing each logic of the input address bits (for example, input row address bit signals) with each of the programmed defective address bits and for detecting whether or not each logic of the input row address bits coincides with each of the programmed address bits, and a switching circuit for supplying control signals to the row decoder and driver for the regular memory cell array or for the redundancy memory cell array, respectively, in accordance with the result of the above comparison. Accordingly, when the potential levels of the row address bit signals output from the row address buffer have been established, a control signal is supplied from the row control circuit to the comparison circuit. The comparison circuit then compares each logic of the input row address bits with each logic of the defective address bits programmed in the programming circuit, and an output signal having a predetermined potential level is supplied from the comparison circuit to the switching circuit in accordance with the result of the comparison. Further, when the potential level of the output signal from the comparison circuit has been established, a control signal is supplied from the row control circuit to the switching circuit, and the switching circuit carries out a switching operation in accordance with the logic of the output signal from the comparison circuit. Namely, when the comparison circuit detects that at least one logic of the input row address bits does not coincide with the corresponding defective row address bit programmed in the programming circuit, the potential of the output signal from the comparison circuit becomes low level, for example, and when the potential level of the output signal from the comparison circuit has been set to low level, the above control signal from the row control circuit is supplied through the switching circuit to the row decoder and driver, to select a predetermined work line provided in the regular memory cell array in accordance with the potential levels of the input row address bit signals. Thus, data stored in a predetermined memory cell arranged at the intersection of the selected word line and the selected bit line provided in the regular memory cell array is read out, or predetermined data is written from the outside to the predetermined memory cell. On the other hand, when the comparison circuit detects that each logic of the input row address bits coincides with each of the defective row address bits programmed in the programming circuit, the potential of the output signal from the comparison circuit becomes high level, for example, and when the potential level of the output signal from the comparison circuit has been set to high level, the above control signal from the row control circuit is supplied through the switching circuit to the redundancy row decoder and driver, to select a predetermined redundancy word line provided in the redundancy memory cell array in accordance with the input row address bit signals corresponding to the programmed defective address bits. Accordingly, data stored in a predetermined redundancy memory cell arranged at the intersection of the selected redundancy word line and the selected bit line provided in the redundancy memory cell array is read out, or predetermined data is written from the external to the predetermined redundancy memory cell. At this time, the word line corresponding to the defective row address bits provided in the regular memory cell array is in the non-selected state. As above-mentioned, in the memory device having the redundancy memory cell array, the time required for selecting a predetermined word line provided in the regular memory cell array or the redundancy memory cell array is delayed by the time required for establishing the potential level of the output signal supplied from the comparison circuit to the switching circuit, compared with the time required for selecting a predetermined word line provided in the regular memory cell array in the memory device not having the redundancy memory cell array. Therefore, in this type of memory device having the redundancy memory cell array, a problem arises in that, even if a defective memory cell does not exist in the regular memory cell array and the redundancy memory cell array is not used (i.e., even if defective address bits are not programmed in the programming circuit), the operation timing for electing a predetermined word line provided in the regular memory cell array (i.e., the access timing for a selected memory cell connected to the selected word line) is delayed by the above-mentioned time, compared with the corresponding timing in the memory device not having the redundancy memory cell array. The present invention has been made in view of the above-mentioned problem, and an embodiment of the present invention may increase the access speed for the predetermined memory cell corresponding to the selected address bits when defective address bits are not programmed in the programming circuit in a semiconductor memory device having a redundancy memory cell array. According to the present invention, there is provided a semiconductor memory device comprising a regular memory cell array in which a plurality of word lines and bit lines are provided, and a plurality of memory cells are arranged at intersections of the word lines and bit lines; a redundancy memory cell array in which one or more word lines and bit lines are provided, and a plurality of memory cells are arranged at intersections of the word lines and bit lines; control means for generating a first control signal; programming means for programming i.e. storing defective address bits corresponding to defective memory cells existing in the regular memory cell array; means for comparing the bits of input address bits with the defective address bits; a first switching means for generating a second control signal when at least one bit of the input address bits does not coincide with the corresponding defective address bit and for supplying a third control signal to a predetermined word line or bit line belonging to the redundancy memory cell array without generating the second control signal when the bits of the input address bits coincide with the defective address bits; means for identifying whether or not any defective address bits are programmed in the programming means; and a second switching means for supplying the second control signal input from the first switching means to a selected word line or bit line belonging to the regular memory cell array when the identifying means indicates that the defective address bits are programmed in the programming means and for supplying the first control signal input from the control means to the selected word line or bit line when the identifying means indicates that no defective address bits are programmed in the programming means. By use of the above construction, when the identifying means indicates that the defective address bits are not programmed in the programming means, a predetermined memory cell corresponding to the input address bits may be directly selected without comparing the logics of the input address bits with the defective address bits, and thus, it is possible to increase the access speed for the predetermined memory cell corresponding to the input address bits when the defective address bits are not programmed in the programming means. Figure l shows an example of the construction of a conventional semiconductor memory device; Fig. 2 shows an example of the construction of a previously proposed semiconductor memory device having a redundancy memory cell array; Fig. 3 shows the construction of a semiconductor memory device according to one embodiment of the present invention; Fig. 4 shows an example of the circuit diagram of the switching circuit 12 shown in Fig. 3; Fig. 5 is a timing chart concerning the potential changes of several signals and a selected word line in the device shown in Fig. 1; Fig. 6 is a timing chart concerning the potential changes of several signals and a selected word line in the device shown in Fig. 2; and Fig. 7A and Fig. 7B are timing charts concerning the potential changes of several signals and a selected word line in the device shown in Fig. 3. In order to clarify the background of the present invention, an example of the construction of a conventional semiconductor memory device is shown in Fig. 1. In this connection, Fig. 5 is a timing chart concerning the potential changes of several signals and a selected word line in the device shown in Fig. 1. In Fig. 1, reference numeral l is a row control circuit to which a row address strobe signal RAS is input from the outside, and generated control signals ø ADD and ø WL each generated at a predetermined timing as described below. Reference numeral 2 is a row address buffer to which external row address bit signals A₀ to A n having TTL (Transistor-Transistor-Logic) potential levels are input, and at the timing when the potential level of the signal RAS becomes low, the control signal ø ADD is supplied from the row control circuit l to the row address buffer 2. Accordingly, the row address buffer 2 outputs row address bit signals A₀ to A n and A₀ (an inverted bit signal of A₀) to A n (an inverted bit signal of A n ) each having a MOS potential level (i.e., the high level and the low level corresponding to the V CC level and V SS level, respectively), as shown in Fig. 5. Reference numeral 3 is a row decoder and driver to which the row address bit signals A₀ to A n and A₀ to A n are supplied from the row address buffer 2, and at the timing "t₀" shown in Fig. 5 at which potential levels of the above signals A₀ to A n and A₀ to A n output from the row address buffer 2 have been established (in this connection, Fig. 5 shows that the potential levels of row address bit signals A i and A j are high, and therefore, the potential levels of the corresponding inverted row address bit signals A i and A j are low), the control signal ø WL is supplied from the row control circuit l to the row decoder and driver 3. Accordingly, the row decoder and driver 3 selects a predetermined word line, for example, WL₁, in accordance with the potential levels of the input row address bit signals A₀ to A n and A₀ to A n . In this connection, a circuit portion 31 provided in the above row decoder and driver 3 is an example of a decoder and driver circuit for selecting the word line WL₁ when the potential levels of the input row address bit signals A₀ to A n are all low (i.e., the potential levels of the input row address bit signals A₀ to A n are all high). Namely, in the circuit 31, the potential level of a control signal ø changes in phase with that of the signal RAS , and when the potential level of the signal ø is high, a precharging transistor Q₁₀ is turned ON, and the potential of a node p corresponding to the connecting point between the precharging transistor Q₁₀ and decoding transistors Q₁₁ to Q 1n becomes high level (V CC level). Next, when the potential level of the signal ø becomes low (i.e., when the precharging transistor Q₁₀ is turned OFF), if the potential levels of the input row address bit signals A₀ to A n are all low, all decoding transsistors Q₁₁ to Q 1n are turned OFF, and the high potential of the node p is supplied to a gate of a transistor Q 1s through a transfer gate transistor Q 1t . Thus, the transistor Q 1s is turned ON, the above-mentioned control signal ø WL is supplied to the word line WL₁ through the transistor Q 1s , and the potential level WL of the selected word line (in this case, WL₁) becomes high, as shown in Fig. 5. However, at this time, if at least one of the potential levels of the input row address bit signals A₀ to A n is high (i.e., at least one potential levels of the input row address bit signals A₀ to A n is low), at least one of the decoding transistors Q₁₁ to Q 1n is turned ON, and thus the potential of the node p in the above circuit 3l becomes low. Accordingly, the potential of the corresponding word line WL₁ does not become high. As a result, the word line WL₁ is non-selected, and another predetermined word line is selected by the corresponding decoder and driver circuit in accordance with the potential levels of the input row address bit signals A₀ to A n and A₀ to A n . Reference numeral 41 is a regular memory cell array in which a plurality of word lines (WL₁, and so on) and a plurality of bit lines (BL₁ to BL m ) are provided, and a plurality of memory cells (MC₁₁ to MC 1m , and so on) are arranged at each intersection of the word lines and bit lines. Each of the memory cells (for example, MC₁₁) comprises a transfer gate transsistor Q₁₁ and a capacitor C₁₁ for storing data. When reading data stored in the predetermined memory cell MC₁₁ , for example, the potential of the selected word line WL₁ is raised as above-mentioned. Accordingly, the data stored in the capacitor C₁₁ is supplied to a sense amplifier 51 through the transfer gate transistor Q₁₁ and the selected bit line BL₁. This data is then sensed and amplified by the sense amplifier 51 and is output as output data D out through the selected bit line BL₁ and data bus provided in a column decoder 6. Also, when writing data D in from the external to the predetermined memory cell MC₁₁, for example, the data D in is supplied to the memory cell MC₁₁ through the above data bus, the selected bit line BL₁, and the transfer gate transistor Q₁₁ connected to the selected word line WL₁. In this connection, the column decoder 6 selects a predetermined bit line (for example, BL₁) in accordance with the potential levels of the input column address bit signals A′₀ to A′ n and A'₀ to A' n . Reference numeral 7 denotes a column address buffer to which external column address bit signals A′₀ to A′ n are input, and the column address buffer 7 supplies the column address bit signals A′₀ to A′ n and A'₀ to A' n to the column decoder 6, in the same way as the row address buffer 2. Figure 2 shows an example of the construction of a previously proposed semiconductor memory device in which a redundancy memory cell array 42 is provided in addition to the regular memory cell array 41. In Fig. 2, the same reference numerals or symbols as in Fig. 1 are given to the portions or signals corresponding to those in Fig. 1. Figure 6 is a timing chart for the potential changes of several signals and a selected word line in the device shown in Fig. 2. In a memory device as shown in Fig. 2, the test for the regular memory cell array 41 is carried out before forwarding the device to the next process, in order to detect whether or not a defective memory cell exists in the regular memory cell array 41. Accordingly, if a defective memory cell is detected, the defective address bit signals corresponding to the defective memory cell (in this case, defective row address bits) are programmed (stored) in a programming circuit (for example, a read only memory) 8 for programming the defective address bits. Thus, in the operation of the device, when the potential levels of the row address bit signals A₀ to A n and A₀ to A n output from the row address buffer 2 have been established at the timing "t₀" shown in Fig. 6, a control signal ø CM is supplied from the row control circuit 1 to a comparison circuit 9. The comparison circuit 9 compares each logic (in this case, each potential) of the row address bit signals (for example, A₀ to A n ) input thereto with each logic of the defective address bits programmed in the programming circuit (ROM) 8, and an output signal ø CMP having a predetermined potential level is supplied from the comparison circuit 9 to a switching circuit 10 in accordance with the result of the comparison. As shown in Fig. 6, the output signal ø CMP is generated at the above timing "t₀" by supplying the above control signal ø CM from the row control circuit 1 to the comparison circuit 9. Further, when the potential level of the output signal ø CPM has been established at the timing "t′₀" shown in Fig. 6, the control signal ø B is supplied from the row control circuit 1 to the switching circuit 10, and the switching circuit 10 carries out the switching operation in accordance with the logic (in this case, the potential level) of the output signal ø CMP . Namely, when the comparison circuit 9 detects that at least one logic of the input row address bits A₀ to A n does not coincide with the corresponding defective row address bit programmed in the programming circuit 8, the potential of the output signal ø CMP becomes low level, for example. Thus, at the above timing "t′₀", at which the potential level of the above signal ø CMP has been set to a low level, the above control signal ø B is supplied through the switching circuit 10 to the word decoder and driver 3, as the control signal ø WL for a selected word line. As a result, the word decoder and driver 3 raises the potential WL (shown in Fig. 6) of the selected word line (for example, WL₁) provided in the regular memory cell array 41, in accordance with the potential levels of the input row address bit signals A₀ to A n and A₀ to A n . Thus, data stored in a predetermined memory cell MC₁₁, for example, arranged at the intersection of the selected word line (for example, WL₁) and the selected bit line (for example, BL₁) is read out as the output data P out , or the input data D in is written to the predetermined memory cell (for example, MC₁₁), as above-mentioned. On the other hand, when the comparison circuit 9 detects that each logic of the input row address bits A₀ to A n coincides with each of the defective row address bits programmed in the programming circuit 8, the potential of the output signal ø CMP becomes high level, for example. Thus, at the above timing "t′₀", at which the potential level of the above signal ø CMP has been set to a high level, the above control signal ø B is supplied through the switching circuit l0 to a redundancy word line WL R provided in the redundancy memory cell array 42, as a control signal ø WLR for the above redundancy word line. As a result, the potential WLR (shown in Fig. 6) of the redundancy word line WL R becomes high level. Accordingly, data stored in a predetermined redundancy memory cell MC R11 , for example, arranged at the intersection of the redundancy word line WL R and the selected bit line (for example, BL₁) is read out as the output data D out , or the input data D in is written to the predetermined redundancy memory cell (for example, MC R11 ). At this time, the word line coresponding to the defective row address, for example, WL₁ , provided in the regular memory cell array 4l is in a non-selected state. As above-mentioned, in the memory device having the redundancy memory cell array as shown in Fig. 2, the time required for selecting a predetermined word line provided in the regular memory cell array 4l or the redundancy memory cell array 42 is delayed compared with the above time in the memory device not having the redundancy memory cell array as shown in Fig. l, due to the switching operation of the switching circuit l0 based on the potential level of the output signal ø CMP supplied from the comparison circuit 9. Namely, in the memory device shown in Fig. 2, the timing "t′₀" shown in Fig. 6 at which the potential WL of the selected word line or the potential WLR of the selected redundancy word line rises is delayed compared with the timing "t₀" shown in Fig. 5 at which the potential WL of the selected word line rises in the memory device shown in Fig. l. Therefore, in such a type of memory device as shown in Fig. 2, a problem arises in that, even if a defective memory cell does not exist in the regular memory array 4l and the redundancy memory cell array 42 is not used (i.e., even if defective address bits are not programmed in the programming circuit 8), the operation timing for selecting a predetermined word line provided in the regular memory cell array (i.e., the access timing for a selected memory cell connected to the selected word line) is delayed compared with the corresponding timing in the memory device as shown in Fig. l. The present invention has been made in view of the above-mentioned problem; Figure 3 shows the overall construction of the semiconductor memory device according to one embodiment of the present invention. In Fig. 3, the same reference numerals or symbols as in Fig. 2 are given to the portions or signals corresponding to those in Fig. 2. Figure 7A and Fig. 7B are timing charts concerning the potential changes of several signals and a selected word line in the device shown in Fig. 3. In this connection, Fig. 7A corresponds to the time chart in the case wherein defective address bits are not programmed in the programming circuit (ROM) 8, and Fig. 7B corresponds to the time chart in the case wherein the defective address bits are programmed in the programming circuit (ROM) 8. As above-mentioned concerning the memory device shown in Fig. 2, when the potential level of the output signal ø CMP has been established at the timing "t′₀" shown in Fig. 7B, the control signal ø B is supplied from the row control circuit l to the switching circuit l0, and the switching circuit l0 carries out the switching operation in accordance with the logic of the output signal ø CMP supplied from the comparison circuit 9. Namely, when the comparison circuit 9 detects that at least one logic of the input row address bits A₀ to A n does not coincide with corresponding defective row address bit programmed in the programming circuit 8, the potential of the output signal ø CMP becomes low level, for example. Accordingly, at the above timing "t′₀", at which the potential level of the above signal ø CMP has been set to a low level, the above control signal ø B is supplied from the row control circuit l to the switching circuit l0, and thus, the switching circuit l0 supplies a control signal ø WLB to a switching circuit l2 as described below. On the other hand, when the comparison circuit 9 detects that each logic of the input row address bits A₀ to A n coincides with each of the defective row address bits programmed in the programming circuit 8, the potential of the output signal ø CMP becomes high level, for example. Accordingly, at the above timing "t′₀", at which the potential level of the above signal ø CMP has been set to a high level, the above control signal ø B is supplied through the switching circuit l0 to the redundancy word line WL R as the control signal ø WLR . As a result, the potential WLR (shown in Fig. 7B) of the redundancy word line WL R becomes high level. Accordingly, data stored in the predetermined redundancy memory cell MC R11 , for example, is read out as the output data D out , or the input data D in is written to the predetermined redundancy memory cell (for example, MC R11 ). At this time, the word line corresponding to the defective row address, for example WL₁, provided in the regular memory cell array 4l is in a non-selected state. Although in the memory device shown in Fig. 2, only one redundancy word line WL R is provided in the redundancy memory cell array 42, it is also possible to provide a plurality of redundancy word lines in the redundancy memory cell array and to select a predetermined redundancy word line in accordance with selected defective row address bits programmed in the programming circuit by using a redundancy row decoder and driver. As above-mentioned, in the semiconductor memory device having the redundancy memory cell array, the test is carried out before forwarding the device to the next process, in order to detect whether or not a defective memory cell exists in the regular memory cell array 41. Thus, if a defective memory cell is detected in the regular memory cell array, the defective address bits (for example, defective row address bits) corresponding to the defective memory cell are programmed in the programming circuit (for example, ROM) 8. Accordingly, when each logic of the input address bit signals (for example, input row address bit signals) coincides with each logic of the programmed defective address bits, the control signal ø WLR is supplied from the switching circuit 10 to the redundancy word line WL R , and the access for a predetermined redundancy memory cell is carried out instead of the access for a corresponding memory cell arranged in the regular memory cell array. However, if it is detected that a defective memory cell does not exist in the regular memory cell array, it is not necessary to use the redundancy memory cell array, and defective address bits are not programmed in the programming circuit (ROM) 8. Accordingly, in this embodiment, another programming circuit 11 (for example, a ROM) for programming data identifying whether or not any defective address bits are programmed in the programming circuit 8 (i.e., whether or not the redundancy memory cell array is used) is provided in addition to the above programming circuit 8. Accordingly, when any defective address bits are programmed in the programming circuit 8 (i.e., when the redundancy memory cell array is used), the potential of an output signal RDT supplied from the programming circuit 11 is set to high level by programming a high level data "1" in the programming circuit 11, and when defective address bits are not programmed in the programming circuit 8, (i.e., when the redundancy memory cell array is not used), the potential of the output signal RDT is set to low level by programming a low level data "0" in the programming circuit 11. In this connection, the above predetermined one bit logic data identifying whether or not the defective address bits are programmed in the programming circuit 8 is previously written to the programming circuit (ROM) 11 before the operation of the memory device in accordance with the result of the above-mentioned test carried out before the forwarding (shipping) of the device. Therefore, the output signal RDT having a predetermined potential level is also supplied from the above programming circuit 11 to the switching circuit l2 during the operation of the memory device. When the potential level of the output signal RDT supplied to the switching circuit 12 is low (i.e., when defective address bits are not programmed in the programming circuit 8), the signal path through which a control signal ø WLA output from the row control circuit 1 is supplied to the word decoder and driver 3 as the control signal ø WL is formed by the switching circuit 12. In this connection, the control signal ø WLA is supplied from the row control circuit 1 to the switching circuit 12 at the timing "t₀" shown in Fig. 7A which corresponds to the timing "t₀" shown in Fig. 5, and then the control signal ø WL for selecting a predetermined word line provided in the regular memory cell array 41 is supplied from the switching circuit 12 to the word decoder and driver 3, as shown in Fig. 7A. On the other hand, when the potential level of the output signal RDT supplied to the switching circuit 12 is high (i.e., when defective address bits are programmed in the programming circuit 8), the signal path through which the control signal ø WLB output from the switching circuit 10 is supplied to the word decoder and driver 3 as the control signal ø WL is formed by the switching circuit 12, and then the control signal ø WL is supplied from the switching circuit 12 to the word decoder and driver 3, as shown in Fig. 7B. In this connection, the setting of one of the above-mentioned signal paths is completed in the switching circuit 12 before the operation (word line selection) of the memory device in accordance with the potential level of the output signal RDT. Therefore, when defective address bits are programmed in the programming circuit 8 (i.e., when the redundancy memory cell array is used), the access timing for a predetermined memory cell provided in the regular memory cell array 41 in the memory device shown in Fig. 3 is substantially the same as that in the memory device shown in Fig. 2. However, when no defective address bits are programmed in the programming circuit 8 (i.e., when the redundancy memory cell array is not used), the access timing for a predetermined memory cell provided in the regular memory cell array 41 in the memory device shown in Fig. 3 is substantially the same as that in the memory device shown in Fig. 1, and thus, it is possible to increase the access speed in the latter case. Figure 4 is a circuit diagram showing an example of the switching circuit 12. In Fig. 4, when the potential level of the output signal RDT supplied from the programming circuit (ROM) 11 is set to high level, a transistor Q₄ is turned ON through a turned-ON transistor Q₂ , and the control signal ø WLB is supplied from the switching circuit 10 to the word decoder and driver 3 as the control signal ø WL . On the other hand, when the potential level of the output signal RDT is set to low level (i.e., when the potential level of the inverted output signal RDT is set to high level), a transistor Q₅ is turned ON through a turned ON transistor Q₃ , and the control signal ø WLA is supplied from the row control circuit 1 to the word decoder and driver 3 as the control signal ø WL . Although, in the above embodiment, the defective row address bits are used as defective address data, it is also possible to use defective column address bits as such defective address data. In embodiments of the invention, therefore, it is possible, to increase the access speed for a selected memory cell arranged in a regular memory cell array provided in a semiconductor memory device having a redundancy memory cell array, when defective address bits are not programmed in the programming circuit (i.e., when the redundancy memory cell array is not used).

Claims: A semiconductor memory device comprising: a regular memory cell array (41) in which a plurality of word lines and bit lines are provided, and a plurality of memory cells are arranged at intersections of said word lines and bit lines; a redundancy memory cell array (42) in which one or more word lines and bit lines are provided, and a plurality of memory cells are arranged at intersections of said word lines and bit lines; control means (1) for generating a first control signal ( WLA ); programming means (8) for storing defective address bits corresponding to a defective memory cell, if any, existing in said regular memory cell array; means (9) for comparing each bit of input address bits with each of said defective address bits; a first switching means (10) for generating a second control signal ( WLB ) when at least one bit of said input address bits does not coincide with a corresponding one of said defective address bits, and for supplying a third control signal ( WLR ) to a predetermined word line or bit line belonging to said redundancy memory cell array, without generating said second control signal, when each bit of said input address bits coincides with each of said defective address bits; characterized by identifying means (11) for identifying whether or not any said defective address bits are stored in said programming means (8); and a second switching means (12) for supplying said second control signal ( WLB ) input from said first switching means (10) to a selected word line or bit line belonging to said regular memory cell array, when said identifying means (11) indicates that said defective address bits are stored in said programming means (8), and for supplying said first control signal ( WLA ) input from said control means (1) to said selected word line or bit line, when said identifying means (11) indicates that no said defective address bits are stored in said programming means (8). A semiconductor memory device according to claim 1, wherein said identifying means comprise a ROM cell which is programmed in advance of operation of the device with information identifying whether or not any said defective address bits are stored in said programming means. A semiconductor memory device according to claim 1 or 2, wherein the signal path for supplying said first control signal or said second control signal to said selected word line or bit line through said second switching means is completed in accordance with the output signal from said identifying means before said input address bits are received.

Inventors: TAKEMAE, YOSHIHIRO
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C29
IPC codes: G11C29