Input voltage signal check circuit for a semiconductor integrated circuit

Abstract: Output signals of input buffers (INBUF1, INBUF2, ..., INBUFn) connected to the external input terminals (IN1, IN2, ..., INn) of the semiconductor circuit are stored in respective memories (MEM1, MEM2, ..., MEMn). The memories are connected in series. Data of the memories are serially output from an external output terminal (OUTter) of the semiconductor circuit. In the above-mentioned operations, a pulse for storing the output signals of the input buffers into the memories, for selecting one of an output signal (OUTy) of the internal circuit and the data stored in the memories, and outputting the selected one from the external output terminal (OUTter), is supplied via another external input terminal (INt) for a test. A pulse (INx) for connecting the memories in series is also supplied via a further external input terminal (INx). The output signals of the input buffers can be output from the semiconductor circuit, without any operation of the internal circuit.

Description: This invention relates to an input buffer check circuit for a semiconductor integrated circuit having a plurality of internal circuits. Generally, a semiconductor integrated circuit is constructed with a number of transistors fabricated on a single silicon wafer chip. In order to check whether or not the manufactured semiconductor circuit responds to an input signal of a predetermined voltage, the entire semiconductor circuit is operated in an AC test mode or a function test mode. However, in the check operation of the input voltage signal, the results of the check are greatly influenced by the measuring instruments used, because the check involves the operation of the entire semiconductor circuit. Specifically, in the check of the input voltage signal, the internal circuit of the semiconductor circuit is dynamically operated. When therefore, an input voltage signal is input from the measuring system to the internal circuit according to the inspection specification, a change in the characteristic of the internal circuit influences the level of the input voltage signal, possibly causing an erroneous operation of the measuring system. It is difficult to check whether the erroneous operation is due to the internal circuit or the measuring system. Considerable time is required for securing a stable test. Further, when the manufacturing of the semiconductor circuit enters a mass production stage, different measuring systems are used and similar problems are also created, necessitating a significant amount of time for the inspection process. Such problems were largely solved by a circuit shown in "HCMOS Macrocell Manual" Chapter 7 pages 7-33 to 7-35 issued by LSI Logic Corporation. This circuit includes all the features of the preamble of the present claim 1 and uses a NAND tree to enable multiplexing of a plurality of test signals onto one output pin. However, such a design requires that a specific sequence of test patterns be used, in which each succeeding pattern changes by one bit. Thus simultaneous transitions of all bits cannot be tested properly. Also it is known to use shift registers for scan/set testing of functional logic from "Design for Testability - A Survey" by Williams and Parker, Proc of the IEEE, vol 71, no. 1, Jan 1983, pages 98 - 112. An object of the invention is to provide an improved input buffer check circuit in a semiconductor integrated circuit. According to the invention there is provided an input buffer check circuit for a semiconductor integrated circuit having a plurality of internal circuits, the input buffer check circuit comprising: a plurality of external input terminals of the semiconductor integrated circuit; an external output terminal of said semiconductor integrated circuit; a plurality of input buffers each having an input terminal coupled to one of said external input terminals, and an output terminal; each of the internal circuits being coupled to the output terminal of one of said input buffers; and select means for selecting an output; characterized by: a plurality of memories each having a data-input route coupled to an output terminal of a respective one of said input buffers, and a data-output route, the memories each also having a terminal for receiving a data-store timing signal; means for connecting said memories and said external output terminal in series; and means for successively reading out the data stored in said memories via said external output terminal; wherein said select means is operable to select an output from said memories or an output from said internal circuits of the integrated circuit, and to connect the selected one to said external output terminal in accordance with a select signal; and wherein said select signal is connected to the terminal of each of said memories for use as said data-store timing signal. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a circuit diagram of an input buffer check circuit for a semiconductor integrated circuit, according to an embodiment of the present invention; and Fig. 2 shows a signal chart in the operation of the check circuit of Fig. 1. An input buffer check circuit for a semiconductor integrated circuit according to an embodiment of the invention will now be described referring to Figs. 1 and 2. It is assumed in Fig. 1 that IN1, IN2,..., INn, and INx designate input terminals, and assumed in Fig. 2 that they designate the signals at those input terminals. It is also assumed in Fig. 1 that OUTter designates an output terminal of the whole semiconductor circuit, and assumed in Fig. 2 that it designate an output signal of the output terminal OUTter. It is further assumed that, in Figs. 1 and 2, TEST and OUTy designate a test signal and an output signal of the internal circuit, respectively. Input terminals IN1, IN2,..., INn are connected to input terminals of input buffers INBUF1, INBUF2,..., INBUFn, respectively. Input terminal INx is connected to the input terminal of input buffer INBUFx. Input terminal INt forms a test terminal to which test signal TEST is input. The test terminal INt is connected to the input terminal of input buffer INBUFt. The output terminals of input buffers INBUF1, INBUF2,..., INBUFn, and INBUFx are connected to internal circuits INTCKT1, INTCKT2,..., INTCKTn, and INTCKTx (not shown) in the semiconductor circuit, respectively. The output terminals of input buffers INBUF1, INBUF2,..., INBUFn are connected to memories MEM1, MEM2,..., MEMn, respectively. The output terminals of input buffers INBUFx and INBUFt are connected to memories MEM1, MEM2,..., MEMn. Memories MEM1, MEM2..., MEMn have substantially the same configurations, except for some connections. Memory MEM1 comprises 2-input NOR gates 12 and 16, 2-input AND gate 14, and D-type flip-flop (D-FF) 18. The first input terminal of NOR gate 12 is connected to the output terminal of input buffer INBUF1. The second input terminal is connected to the output terminal of input buffer INBUFx. The first input terminal of AND gate 14 is connected to the output terminal of input buffer INBUFx. The second input terminal of AND gate 14 is connected to ground. The output terminals of NOR gate 12 and AND gate 14 are connected to the first and second input terminals of NOR gate 16, respectively. The output terminal of NOR gate 16 is connected to the D-terminal of flip-flop D-FF 18. The CK-terminal of flip-flop D-FF 18 is connected to the output terminal of input buffer INBUFt. The Q output terminal of flip-flop D-FF 18 is connected to the second input terminal of the AND gate (not shown) in memory MEM2. The second input terminal of the AND gate in memory MEM2 corresponds to the second input terminal connected to ground, of AND gate 14 in memory MEM1. Other memories MEM2,..., MEMn have the same circuit configurations, except for some connections. Therefore, the different connections will only be given, for simplicity of the description. The second input terminals of the AND gates in other memories MEM2,..., MEMn, each of which corresponds to the second input terminal connected to ground, of the AND gate 14 in memory MEM1, are connected to the Q output terminals of the flip-flops of the preceding stage memories MEM1,..., MEMn-1, respectively. The Q output terminal of the final stage memory MEMn is connected to output circuit OUTCKT. Output circuit OUTCKT is also connected to the output terminal of input buffer INBUFt. Output signal OUTy of the internal circuit is also input to output circuit OUTCKT. Output circuit OUTCKT comprises inverter 20, AND gate 22, NOR gates 24 and 26, and output buffer 28. The output terminal of input buffer INBUFt is connected via inverter 20 to first input terminals of AND gate 22 and NOR gate 24. The second input terminal of AND gate 22 is connected to the Q output terminal of the D-type flip-flop (not shown) of final stage memory MEMn, which corresponds to the Q output terminal of D-type flip-flop 18 of the first stage memory MEM1. Output signal OUTy of the internal circuit is input to the second input terminal of NOR gate 24. The output terminals of AND gate 22 and NOR gate 24 are connected to the first and second input terminals of NOR gate 26, respectively. The output terminal of NOR gate 26 is connected to external output terminal OUTter of the whole semiconductor circuit via output buffer 28. The operation of the input buffer check circuit shown in Fig. 1 will be described. First, in brief, "L" (low) level input signals of a predetermined voltage are supplied to the input buffer via the external input terminals of the semiconductor circuit. The output signals of the input buffers are stored in the respective memories. Data stored in the memories are successively read out via the external output terminal. If the data read out from the memories are "L" level, one can know that the input buffers respond to the predetermined voltage input signal. On the other hand, "H" (high) level input signals of a predetermined voltage are supplied to the input buffers via the external input terminals of the semiconductor circuit. The output signals of the input buffers are stored in the respective memories. Data stored in the memories are successively read out via the external output terminal. If the data read out from the memories are "H" level, it indicates that the input buffers respond to the predetermined voltage input signal. Specifically, "L" level input signals of a predetermined voltage are supplied to external input terminal IN1, IN2,..., INn, and INx. A clock pulse used as test signal TEST , whose "L" level corresponds to a low power source potential "V SS " and whose "H" level corresponds to a high power source potential "V DD ", is input to external input terminal INt. At this time, if input buffer INBUF1,..., INBUFn, and INBUFx respond to the predetermined voltage input signal, the output signals of input buffers INBUF1,..., INBUFn, and INBUFx are "L" level. The "L" level output signal of input buffer INBUF1 is stored in memory MEM1 as "L" level data. Specifically, the "L" level output signal of input buffer INBUF1 is input to the first input terminal of NOR gate 12 in memory MEM1. The second input terminal of NOR gate 12 is supplied with the "L" level signal from input buffer INBUFx. Accordingly, an "H" level signal is output from NOR gate 12. The "H" level output signal is input to the first input terminal of NOR gate 16. Upon receipt of the "H" level signal, NOR gate 16 outputs an "L" level signal. In synchronism with test signal TEST , i.e., a clock pulse input supplied from test input terminal INt via input buffer INBUFt, the "L" level signal of NOR gate 16 is input to flip-flop D-FF 18 and stored therein. In this way, the output signal of input buffer INBUF1 is stored in memory MEM1. The storing operations of output signal of input buffers INBUF2,..., INBUFn into the respective memories MEM2,..., MEMn are substantially the same as that of the storing of output signal of input buffer INBUF1 into memory MEM1. Specifically, the "L" level output signals of input buffers INBUF2,..., INBUFn are stored as "L" level data in memories MEM2,..., MEMn, respectively. When input clock signal TEST supplied to test terminal INt is changed from high "H" to "L" level, instead of output signal OUTy of the internal circuit, the "L" level data stored in memory MEMn, which corresponds the "L" level signal input to input terminal INn, is output from external output terminal OUTter of the semiconductor circuit. When the input signal to input terminal INx is set to be "H", memories MEM1,..., MEMn are connected in series. Under this condition, when a clock pulse TEST is successively input to input terminal INt, the "L" level data stored in memories MEMn,..., MEM2, MEM1, which correspond to the "L" level signals input to input terminals INn,..., IN2, IN1 are successively output in order. After the number of pulses which is less by one than the number of input buffers INBUF1, INBUF2,..., INBUFn are input, the "L" level data stored in all the memories MEM1, MEM2,..., MEMn are output. Therefore, one can know that input buffers INBUF1, INBUF2,..., INBUFn normally operate with regard to the "L" level input signals of the predetermined voltage supplied to input terminals IN1, IN2,..., INn. The above-mentioned operation, performed when "L" level input signals of a predetermined voltage are input to input terminals IN1, IN2,..., INn, can be applied, by replacing the "L" level with an "H" level, to that operation performed when "H" level input signals of a predetermined voltage are input to the input terminals. Specifically, "H" level input signals of a predetermined voltage are supplied to external input terminals IN1, IN2,..., INn, and INx. A clock pulse used as test signal TEST , whose "L" level corresponds to a low power source potential "V SS " and whose "H" level corresponds to a high power source potential "V DD ", is input to external input terminal INt. At this time, if input buffer INBUF1,..., INBUFn, and INBUFx respond to the predetermined voltage input signal, the output signals of input buffers INBUF1,..., INBUFn, and INBUFx are "H" level. The "H" level output signal of input buffer INBUF1 is stored in memory as "H" level data. Specifically, the "H" level output signal of input buffer INBUF1 is input to the first input terminal of NOR gate 12 in memory MEM1. The second input terminal of NOR gate 12 is supplied with the "L" level signal from input buffer INBUFx. Accordingly, an "L" level signal is output from NOR gate 12. The "L" level output signal is input to the first input terminal of NOR gate 16. Upon receipt of the "L" level signal, NOR gate 16 outputs an "H" level signal. In synchronism with test signal TEST , i.e. a clock pulse input supplied from test input terminal INt via input buffer INBUFt, and "H" level signal of NOR gate 16 is input to flip-flop D-FF 18 and stored therein. In this way, the output signal of input buffer INBUF1 is stored in memory MEM1. The storing operations of output signals of input buffers INBUF2,..., INBUFn into the respective memories MEM2,..., MEMn are substantially the same as that of the storing of output signal of input buffer INBUF1 into memory MEM1. Specifically, the "H" level output signals of input buffers INBUF2,..., INBUFn are stored as "H" level data in memories MEM2,..., MEMn, respectively. When input clock signal TEST supplied to test terminal INt is changed from high "H" to "L", instead of output signal OUTy of the internal circuit, the "H" level data stored in memory MEMn, which corresponds the "H" level signal input to input terminal INn, is output from external output terminal OUTter of the semiconductor circuit. When the input signal to input terminal INx is set to be "H", memories MEM1,..., MEMn are connected in series. Under this condition, when a clock pulse TEST is successively input to input terminal INt, the "H" level data stored in memories MEMn,..., MEM2, MEM1, which correspond to the "H" level signals input to input terminals INn,..., IN2, IN1, are successively output in order. After the number of pulses which is less by one than the number of input buffers INBUF1, INBUF2,..., INBUFn are input, the "H" level data stored in all the memories MEM1, MEM2,..., MEMn are output. Therefore, it is possible to determine that input buffers INBUF1, INBUF2,..., INBUFn operate normally with regard to the "H" level input signals of the predetermined voltage supplied to input terminals IN1, IN2,..., INn. After the "L" or "H" level data stored in all memories MEMn,..., MEM1 are output, it can be determined, by inputting one additional pulse to input terminal INt, whether or not memories MEM1, MEM2,..., MEMn are connected in series. When an additional pulse is supplied to input terminal INt and the output signal appearing on output terminal OUTter is "L" level, it can be determined that all the memories are connected in series. In order to ascertain the critical voltage of input buffers INBUF1, INBUF2,..., INBUFn with regard to the predetermined voltage of the "L" level input signals, the input voltages applied to input terminal IN1, IN2,..., INn are gradually increased. The voltage at which the output signals appearing on output terminal OUTter are changed from "L" level to "H" level is the critical voltage. On the other hand, in order to ascertain the critical voltage of input buffers INBUF1, INBUF2,..., INBUF2n with regard to the predetermined voltage of the "H" level input signals, the input voltages applied to input terminals IN1, IN2,..., INn are gradually decreased. The voltage at which the output signals appearing on output terminal OUTter are changed from "H" level to "L" level is the critical voltage. It should be understood that this invention is not limited to the above-mentioned embodiment. In the embodiment of Fig. 1, the output signals of the internal circuit and the check circuit are output via the common external output terminal of the semiconductor circuit. That is to say, the external output terminal of the semiconductor circuit is used in a multiplex fashion. When a number of input terminals are used, the input terminals may be grouped and one output terminal may be assigned to each of those groups. In the embodiment of Fig. 1, the output signal of input buffer INBUFx is used for control of the memories. Therefore, the input signal check of input buffer INBUFx can be executed by another check block. In such a case, input terminal INx is used as a test terminal to which a clock signal is applied whose high level is a high power source potential "V DD " and whose low level is a low power source potential "V SS ". In the embodiment of Fig. 1, the input voltage signal check is performed in the DC mode. The check operation is performed only for the duration of an "L" level of the input signal applied to input terminal INx, as seen in the signal chart of Fig. 2. This implies that during an "H" level of the input signal to input terminal INx, it is possible to input an external signal to the semiconductor circuit. This implies that, during the "H" level of the input signal applied to input terminal INx, the input voltages applied to input terminals IN1,..., INn can be checked while allowing the operation of the internal circuits. The "H" level duration of the input signal at input terminal INx is a so-called "don't care" period. Conventionally, in checking the input voltage signal of the semiconductor circuit, the output signal of the input buffer cannot be detected directly from the outside of the semiconductor circuit. To cope with this, the internal circuits are operated by the input signals of the check voltage level, and a check is made as to whether the internal circuits are erroneously operated or not. This check requires the dynamic input of the signal. Therefore, the measuring system must be constructed accurately, in order to check precisely whether the cause of the erroneous operation of the internal circuits resides in the internal circuit or in the measuring system. In order to realize a correct check, therefore, a significant amount of time is required. Appropriate circuit modification is required for the test in the mass production stage, consuming a significant amount of time. As described in the above, the input voltage signal can be checked in a DC manner. Therefore, the internal circuits can be stably and easily checked. If the computer-aided design (CAD) system is satisfactorily improved in the future, the present invention is highly suitable for such a semiconductor integrated circuit whose pattern is defined as the standard cell LSI (large scale integration) or the gate array. In the buffer check circuit for a semiconductor integrated circuit described in the above, the output signals of input buffers connected to the external input terminals of the semiconductor circuit are stored in respective memories connected to the output terminals of the input buffers. The memories are connected in series. Output signals of the memories are serially output from an external output terminal of the semiconductor circuit. In the above-mentioned operations, a pulse is supplied via another external input terminal for storing the output signals of the input buffers into the memories and, for selecting one of an internal circuit output and the data stored in the memories, and outputting the selected one from the external output terminal. A pulse for connecting the memories in series is also supplied via a further external input terminal. The output signals of the input buffers are output from the semiconductor circuit, without any operation of the internal circuit.

Claims: An input buffer check circuit for a semiconductor integrated circuit having a plurality of internal circuits (INTCKT1 ...), the input buffer check circuit comprising: a plurality of external input terminals (IN1, IN2, ..., INn) of the semiconductor integrated circuit; an external output terminal (OUTter) of said semiconductor integrated circuit; a plurality of input buffers (INBUF1, INBUF2, ..., INBUFn) each having an input terminal coupled to one of said external input terminals (IN1, IN2, ..., INn), and an output terminal; each of the internal circuits being coupled to the output terminal of one of said input buffers; and select means (OUTCKT), for selecting an output characterized by: a plurality of memories (MEM1, MEM2, ..., MEMn) each having a data-input route coupled to an output terminal of a respective one of said input buffers, and a data-output route, the memories each also having a terminal (CK) for receiving a data-store timing signal; means (INx) for connecting said memories and said external output terminal in series; and means for successively reading out the data stored in said memories via said external output terminal; wherein said select means (OUTCKT) is operable to select an output (Q) from said memories or an output (OUTy) from said internal circuits of the integrated circuit, and to connect the selected one to said external output terminal (OUTter) in dependence on a select signal (TEST); and wherein said select signal is connected to the terminal (CK) of each of said memories for use as said data-store timing signal. An input buffer check circuit according to claim 1, characterized in that said external output terminal (OUTter) is used commonly for outputting both the data read out from said memories and an output data of one of said internal circuits of the semiconductor circuit.

Inventors: KAWASAKI SOICHI C O PATENT DIV, KAWASAKI, SOICHI C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: G01R31
IPC codes: G01R31