ANALOG SIGNAL MULTIPLEXER

Abstract: The multiplexer for differential signals comprises a plurality of channels, each channel having a pair of differential amplifiers (Q₁, Q₂, Q₄, Q₅) forming an input stage for receiving a differential input signal and a pair of output transistors (Q₃, Q₆) for forming an output stage producing a differential output signal. Each differential amplifier has a pair of emitter-coupled transistors, with each transistor having an additional emitter cross-coupled to the additional emitter of the opposite transistor of the other emitter-coupled pair. A plurality of current sources (I₁-I₂) are provided to bias the emitter-coupled and emitter cross-coupled pairs. By selectively enabling the current sources, the input signals forming the differential input signal can be applied with normal polarity or inverted polarity to a respective transistor of the output stage to produce a normal or inverted differential output signal or to both transistors of the output stage to produce no differential output signal.

Description: FIELD OF THE INVENTION This invention relates to analog signal multiplexers and, more particularly, to such a multiplexer that passes an analog signal with its normal polarity or its inverted polarity or prevents passage of the signal entirely. BACKGROUND OF THE INVENTION Analog signal multiplexers switch input signals from one or more input paths to a single output path. These signals are often currents that can be summed or switched separately into the output path. For example, an analog signal multiplexer may receive three input currents and deliver any of these currents individually or summed together as an output signal. Examples of prior art arrangements are disclosed in U.S. Patent No. 3783307, entitled Analog Transmission Gate, and a similar device is described in a book entitled "Analog Integrierte Schaltungen" by Miklos Herpy published by Franzis-Verlag München, having particular regard to the said arrangements described on page 478 thereof. The performance of an analog signal multiplexer is judged primarily on its precision, signal bandwidth, and switching speed. The precision, or linearity, is directly affected by changes in current as different input signals are switched to the output path and produce common mode voltage "bumps" or spikes in the switching process. The present invention overcomes this drawback by maintaining the linearity and signal bandwith while switching between input paths. SUMMARY OF THE INVENTION An object of the invention therefore is to provide an improved analog signal multiplexer that minimizes bandwidth limitation, whose output signal is linearly proportional to its input signals and which provides switching speeds faster than presently available. A second object of the invention is to provide for such a multiplexer a plurality of channels that are simple in design. A third object of the invention is to provide such a channel that can also invert the polarity of its input signal in producing the output signal for the channel. A fourth object of the invention is to provide such a channel that can turn off the signal path from the channel to the multiplexer. These objects are achieved by an analog signal multiplexer according to the independent claims 1 and 8, respectively. Each channel of the analog signal multiplexer may operate in a number of different modes. In a NORMAL mode, current sources are enabled to bias the emitter-coupled pair of each differential amplifier to apply the two input signals comprising the differential input signal to the output transistors and produce a differential output signal of the same polarity as the differential input signal. In the INVERT mode, other current sources are enabled to bias the emitter cross-coupled transistor pairs to apply the input signals to opposite output transistors to produce a differential output signal with an inverted polarity. In an OFF mode each of the current sources is enabled to bias both the emitter-coupled transistor pairs and emitter cross-coupled pairs. With a substantially pure differential signal, both input signals of the differential input signal combine to produce no differential output signal. The foregoing and other objects, features, and advantages of the invention will become more apparent from the following detailed description of a preferred embodiment which proceeds with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a channel of an analog signal multiplexer according to the invention. FIG. 2 is a partial schematic diagram of an analog signal multiplexer showing the connection of two channels. FIG. 3 is a block diagram of an analog signal multiplexer comprising a plurality of channels. DETAILED DESCRIPTION Fig. 1 shows one channel of an analog signal multiplexer 10 embodying the invention. The circuit includes an input stage comprising a pair of differential amplifiers 12 and 14 for receiving a differential input signal comprising +V in and a -V in . The differential amplifier 12 includes a pair of emitter-coupled transistors Q₁ and Q₂, +V in being received by the input stage at the base of Q₁. The differential amplifier 14 similarly includes a pair of emitter-coupled transistors Q₄ and Q₅, -V in being received at the base of Q₄ Each of these transistors Q₁ through Q₄ includes a second emitter for cross coupling the transistor to the opposite transistor of the other differential amplifier. Q₁, for example, is cross coupled to Q₅ to form a first emitter cross-coupled transistor pair. Q₂ is similarly cross-coupled to Q₄ to form a second emitter cross-coupled transistor pair. Q₁ and Q₂ are biased as an emitter-coupled pair by a first selectable current source comprising I₁ and I₂. Although I₁ and I₂ are shown as independent current sources that can be selectively activated, they also represent a single current source that can be turned off or enabled to provide two levels of current, the first level being half of the second level. Q₄ and Q₅ are similarly biased as an emitter-coupled pair by a second selectable current source comprising I₃ and I₄. I₃ and I₄ are independent current sources that also represent a single second current source that can be turned off or enabled to provide the two levels of current. Each emitter cross-coupled transistor pair is provided with its own selectable current source for bias. The first emitter cross-coupled pair comprising Q₁ and Q₅ is biased by a third selectable current source represented by independent sources I₅ and I₈. The second emitter cross-coupled pair comprising Q₂ and Q₄ is biased by a fourth selectable current source represented by independent sources I₆ and I₇. These current sources, as those previously described, represent a single current source that can be turned off or enabled to provide two selectable levels of current. The differential amplifier comprising Q₁ and Q₂ is coupled to an output transistor Q₃ that is biased by a current source I B . The base of Q₃ is coupled to the collector of Q₂, and a resistor R₁ and voltage source that produce the collector current. The emitter of Q₃ is coupled to the base of Q₂ to provide negative feedback and produce a voltage +V o having unity voltage gain at the emitter of Q₃ with respect to the input signal affecting Q₂. The voltage +V o is applied across a gain-setting resistor R₂ whose resistance determines the current gain of +I o at the collector of Q₃. With the negative feedback, +I o is linearly proportional to the input signal applied to Q₂. Similarly, the differential amplifier comprising Q₄ and Q₅ is coupled to an output transistor Q₆ that is biased by current source I B through gain-setting resistor R₅. The base of Q₆ is coupled to the collector of Q₅ and a resistor R₄ and voltage source that produce the collector current. The emitter of Q₆ is coupled to the base of Q₅ to provide negative feedback and produce a voltage -V o having unity voltage gain with respect to the input signal affecting Q₅. The voltage -V o is applied across resistor R₅ to produce an output signal current -I o linearly proportional to the input signal applied to Q₅. Each channel described above of the analog signal multiplexer 10 can operate in three modes: NORMAL, INVERTED, or OFF. The mode chosen determines the form of the differential output signal. As will be explained, the differential input signal in the NORMAL mode is passed from the bases at Q₁ and Q₄ to the collectors of Q₃ and Q₆ to produce an output signal current of the same polarity. In the INVERTED mode, the polarity of the output signal currents is inverted, with +V in appearing as a signal current at the collector of Q₆ and -V in appearing as a signal current at the collector of Q₃. In the OFF mode portions of both +V in and -V in are applied to both Q₂ and Q₅, blocking the passage of any input signal to Q₃ amd Q₆ and producing no differential output signal for the stage. Table 1 for selecting the mode of operation desired is shown below. In the NORMAL mode of operation, the input signal voltage +V in and -V in are reproduced as +V o and -V o across resistors R₂ and R₅. The emitter-coupled transistor pairs are biased by enabling current sources I₁ through I₄ and disabling I₅ through I₈. Assuming transistors Q₁, Q₂ and Q₄, Q₅ are balanced, equal amounts of current are drawn into the collectors of each transistor with the voltage at each base equal. As +V in and -V in vary, the voltage at the emitters of Q₁ and Q₄ will vary, affecting the current drawn through the collector of the emitter coupled transistors Q₂ and Q₅. As +V in rises, for example, the voltage across the base emitter junction of Q₂ will decrease temporarily, decreasing the current drawn into the collector of Q₂ and causing the voltage at the base of Q₃ to rise. The voltage at the emitter of Q₃ rises as a result. With the emitter voltage fed back to the base of Q₂, the rising Q₃ base voltage causes Q₂ to draw more current through its collector and thereby lower its collector voltage. If +V in falls, on the other hand, the voltage across the base emitter junction of Q₂ increases temporarily, increasing the current drawn into the collector of Q₂ and thereby lowering the voltage at the base and emitter of Q₃. The same response occurs with -V in and transistors Q₅ and Q₆. Thus, the differential input voltage equal to +V in -(-V in ) is replicated across R₂ and R₅ The current +I o is therefore proportional to +V in and -I o is proportional to -V in . In the INVERTED mode, the first emitter cross-coupled transistor pair Q₅ and Q₁ and the second cross-coupled pair Q₄ and Q₂ are biased by enabling current sources represented by I₅ through I₈ and disabling I₁ through I₄. The voltage +V in now affects transistor Q₅ and output transistor Q₆, and -V in affects transistor Q₂ and transistor Q₃. Q₃ and Q₆ respond as before, but the output signal currents +I o and -I o now have a polarity opposite of that +V in and -V in , respectively. In the OFF mode, both the emitter-coupled pairs and the emitter cross-coupled pairs are biased by selecting the odd numbered current sources and disabling the even numbered sources, or vice versa. This cross biasing applies +V in and -V in to both Q₂ and Q₅. The effect of applying +V in to the coupled pairs of Q₁, Q₂, and Q₁, Q₅ and applying -V in to the coupled pairs of Q₄, Q₂ and Q₄, Q₅ is best understood by example. Assume that no input signal is applied to the bases of Q₁ and Q₅ and that the bias voltage is zero volts. The emitter of Q₁ will be changed to -.7 volts. The base of Q₂ will attempt to respond to the negative feedback of Q₃ to change to zero volts. However, +V o , the Q₂ base voltage, is also under the influence of -V in through the coupling of the additional emitter of Q₂ to Q₄ In this case, the additional emitter is also at -.7 volts; so no voltage difference across the parallel emitters arises and Q₂ base voltage changes to zero volts. The same result occurs at the base of Q₅ and -V o changes to zero volts. Now assume a small differential voltage is applied to the bases of Q₁ and Q₄, +.1 volts at Q₁ and -.1 volts at Q₄. The currents in the transistors will vary in response to the differing base voltages. Most of I₁ flows through Q₁ because +V in is more positive than +V o . Most of I₇ flows through Q₂ because -V in is less positive than +V o . Most of I₃ flows through Q₅ because -V in is less positive than -V o . Most of I₅ flows through Q₁ because +V in is more positive than -V o . As a result, one unit of current flows in Q₂, and one unit in Q₅; nearly two units of current flow in Q₁; very little current flows in Q₄. The current through the collectors of Q₂ and Q₅ remain constant as +V in and -V in vary. If the input signal voltage is varied by a greater amount, for example, +V in up to 1 volt and -V in up to -1 volt, +V o and -V o continue to remain at zero volts. A +V in of 1 volt raises the emitter voltage of Q₂ to .3 volts approximately. A -V in of -1 volt would cause the additional emitter's voltage to fall to -1.7 volts, but this fall is prevented by the limitation on +V o to zero volts. This voltage limits the emitter voltage of Q₄ and Q₂ to -.7 volts, turning off the emitter of Q₄ coupled to Q₂ and the emitter of Q₂ coupled to Q₁. Similarly, -V o will not drop below zero volts, thereby shutting off the emitter of Q₅ coupled to Q₁ and the emitter of Q₄ coupled to Q₅. The other emitters of Q₅ and Q₂ remain active. Therefore, the collector currents through Q₂ and Q₅ remain constant when +V in and -V in are applied to both Q₂ and Q₅. Fig. 2 shows a schematic section of two multiplexer channels together. The output currents +I o1 and +I o2 are summed at an output node 16 of the multiplexer. With both channels in the NORMAL mode, I oT is the sum of the two currents. With either channel in the INVERTED mode, I oT is the difference between the two currents. With either channel in the OFF mode, I oT will equal only the current of the enabled channel. Similarly, -I oT is the sum of -I o1 and -I o2 at an output node 18. Fig. 3 shows a block diagram of a three channel analog signal multiplexer illustrating how a number of input signals can be multiplexed together. Each channel has a separate input signal path with the outputs of the channels combined in a common output signal path. The advantage of the analog signal multiplexer 10 over the prior art is evident from the continuous flow of current that results when a channel is switched to the OFF mode. Unlike prior art multiplexers, no common mode voltage "bumps" or spikes occur when a channel is switched to the OFF mode or between other modes because the currents in Q₂ and Q₅ remain constant when +V in and -V in are applied to both transistors. The speed of the switching can be therefore higher because the differential amplifiers experience little adverse effect as the result of the rapid switching between modes. Having illustrated and described the principles of the invention in a preferred embodiment, it should be apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. For example, Q₁ through Q₈ are represented by single bipolar transistors. Alternative devices may also be used, such as Darlington pairs, field effect transistors, or combinations thereof.

Claims: An analog signal multiplexer channel comprising first and second differential amplifiers (12,14) for receiving a differential input signal (+V in,-Vin ), each differential amplifier having a pair of transistors (Q₁,Q₂ and Q₄,Q₅); means for selecting one of a plurality of modes of operation of the analogue signal multiplexer channel and output transistor means for producing an output signal responsive to said input signal, characterised in that each transistor (Q₁,Q₂ and Q₄,Q₅) of said first and second differential amplifiers 12 and 14 has first and second emitters, the first emitters of said transistors within each differential amplifier being coupled together, the second emitters of the transistors of said first differential amplifier 12 being cross coupled to the second emitters of the transistors of said second differential amplifier (14), thereby forming a pair of cross coupled second emitters; and in that said mode selecting means includes a first selectable current source (I₁,I₂) for biasing the first emitters of the transistors (Q₁,Q₂) of said first differential amplifier (12), a second selectable current source (I₃,I₄) for biasing the first emitters of the transistors (Q₄,Q₅) of said second differential amplifier (14), a third selectable current source (I₅,I₈) for biasing one of the pair of cross coupled second emitters, and a fourth selectable current source (I₆,I₇) for biasing the other of the pair of cross coupled second emitters, and in that said transistor output means comprises a pair of output transistors (Q₃,Q₆) for producing a differential output signal responsive to said input signal, each output transistor (Q₃,Q₆) being respectively coupled to said first and second differential amplifiers (12,14). The multiplexer channel of claim 1 in which each of the current sources (I₁ to I₈) can be selectably turned off and turned on to provide at least two levels of current. The multiplexer channel of claim 2 in which each current source comprises a pair of independent current sources that can be selectably turned off and on. The multiplexer channel of claim 1 in which the first and second current sources (I₁,I₂ and I₃,I₄) are selected to bias the first emitters of the transistors of said first and second differential amplifiers (12,14) to apply the differential input signal (+V in ,-V in ) with its normal polarity to the output transistors (Q₃,Q₆) to produce the differential output signal (+I o ,-I o ) as one of the modes of operation. The multiplexer channel of claim 1 in which the third and fourth current sources (I₅,I₈ and I₆,I₇) are respectively selected to bias each of the pair of cross coupled second emitters of the transistors of said first and second differential amplifiers (12,14) to apply the differential input signal (+V in ,-V in ) with inverted polarity to the output transistors (Q₃,Q₆) as the differential output signal (+I o ,-I o ) as one of the modes of operation. The multiplexer channel of claim 2 in which each of the current sources is selected to bias the first and second emitters of the transistors of said first and second differential amplifiers to produce no output signal as one of the modes of operation. An analog signal multiplexer according to claim 1 comprising a plurality of multiplexer channels, the multiplexer having separate input signal paths and a common output signal path. An analog signal multiplexer comprising a plurality of channels, each channel comprising first and second differential amplifiers (12,14), an output stage, a plurality of current sources for biasing each differential amplifier, means for selecting one of a plurality of modes of operation of each multiplexer channel and means for combining the output of each channel in a common output signal path, characterised in that said first and second differential amplifiers (12,14) each comprise a pair of transistors (Q₁,Q₂ and Q₄,Q₅) each having first and second emitters, the first emitters of the transistors within each differential amplifiers being coupled together, the second emitters of said first differential amplifier (12) being cross coupled with the second emitters of the transistors of said second differential amplifier (14), thereby forming a pair of cross coupled second emitters, said differential amplifiers (12,14) forming an input stage for receiving a differential input signal (+V in ,-V in ) on an input signal path, and in that said output stage comprises a pair of outputs, the output stage being coupled to the input stage to produce a differential output signal, and in that said means for selecting one of a plurality of modes comprises selecting the current sources in a plurality of arrangements to apply the input signal to the output stage with normal polarity to produce a normal output signal mode, with inverted polarity to produce an inverted output signal mode, and apply both portions to both outputs to the output stage to produce a no output signal mode.

Inventors: QUINN, PATRICK ALLEN
Applicants: TEKTRONIX, INC.
Application year: 1987
Main classification: H03K17
IPC codes: H03K17