BUS MEDIATION SYSTEM

Abstract: The bus mediation system has a number of modules (10,20,30), each of which has a CPU (11,21,31) and a bus control circuit (12,22,32). Each module shares a bus mediation circuit (1), a bus (2), a request signal line (3), a use-of-bus permission line (4) and a bus-is-busy signal line (5). The bus mediation circuit gives use-of-bus permission (BG) if the bus is not in use when a request signal is issued by one of the bus control circuits. Depending on its task level, each module decides whether it issues a request signal in the presence of request signals from other modules, and whether it keeps or abandons the acquired permit after finishing the process. This is made possible by providing each bus control circuits with hard wired logic circuit comprising AND, NAND, OR, NOR gates and flip-flops.

Description: Technical Field The present invention relates to a bus regulating system employing a so-called daisy chain, and more particularly to a bus regulating system for changing bus usage priority with software. There has heretofore been used a bus regulating system having a bus usage permit signal line in the form of a daisy chain. One example of such a bus regulating system is shown in FIG. 4 of the accompanying drawings. Designated in FIG. 4 at 1 is a bus regulating circuit for determining a module that is permitted to use a bus 2 and a request signal line 3 for transferring a request signal *RQ by which each module requests use of the bus. A bus usage permit signal line 4 transfers a bus usage permit signal *BG issued by the bus regulating circuit 1 for permitting each module to use the bus. The bus is shared by modules 10, 20, 30. (In the present description, a signal which is of a logic "0" when it is effective is associated with the sign "*" in front of the alphabetical letters that denote the signal.) In FIG. 4, when one of the modules issues a bus usage request signal *RQ, the bus regulating circuit 1 sends a bus usage permit signal *BG to the line 4 if the bus is not occupied. Each module receives the bus usage permit signal *BG and exclusively uses the bus if it has issued the request signal *RQ. If a module has not issued the request signal *RQ, then it transfers the bus usage permit signal *BG to the next module. With the conventional system, when the modules 10, 20, 30 shown in FIG. 4 simultaneously issue request signals *RQ, since the bus usage permit signal line is in the form of a daisy chain, those modules closer to the left have higher bus usage priority and those closer to the right have a lower bus usage priority. Therefore, bus usage priority is determined by the hardware arrangement, and a module which is processing a task with higher priority may not necessarily be allowed to use the bus with priority. The "Proceedings of the Fall Joint Computer Conference" Nov'67, vol.31, pages 621-633 discloses a bus control system using a dynamic priority order. Elektronische Rechenanlagen" vol.21, no. 4, Aug '79, pages 171-183 discloses a bus control system with a fixed priority system, and it is over this document that the present invention is characterised. It is an object of the present invention to provide a bus regulating system which will solve the aforesaid problem and can allow use of a bus with priority according to the priority of tasks processed by the modules. To eliminate the above-mentioned problem, there is provided a bus regulating system having a plurality of modules, a bus shared by the modules, a bus regulating circuit, a bus request signal line, a bus usage permit signal line in the form of a daisy chain, and a bus busy signal line, said bus regulating system being characterised by each module having overlapping request determining means for determining whether an overlapping request signal is to be issued or not when a request signal is being issued from another module, and continued use determining means for determining whether the obtained right to use the bus is to be abandoned or maintained after said bus has been used. A module which is processing a task of lower priority inhibits the insurance of a request signal when a request signal is being issued from another module, and gives the right to use the bus to a module which is processing a task of higher priority. Conversely, when a module is processing a task of higher priority, it issues a request signal even if a request signal is being issued from another module, so that the right to use the bus is obtained positively. When a module with the right to use the bus is processing a task of higher priority, the module does not immediately abandon but keeps the bus at the time the use of the bus is finished. When a module with the right to use the bus is processing a task of lower priority, the module immediately abandons the bus and gives the bus to a module that is processing a task of higher priority at the time the use of the bus is over. Brief Description of the Drawings FIG. 1 is a block diagram of a bus regulating system according to an embodiment of the present invention; FIG. 2 is a circuit diagram of a bus control circuit shown in FIG. 1; FIG. 3 is a timing chart of bus control operation of the embodiment of the invention; and FIG. 4 is a block diagram of a conventional bus regulating system employing a daisy chain. Best Mode for Carrying Out the Invention An embodiment of the present invention will hereinafter be described in specific detail with reference to the drawings. FIG. 1 shows in block form a bus regulating system according to an embodiment of the present invention. Designated in FIG. 1 at 1 is a bus regulating circuit for determining which module is permitted to use bus 2 and a request signal line 3 for transferring a request signal *RQ by which each module requests use of the bus. (In the present description, as described above, a signal which is of a logic "0" when it is effective is associated with the sign "*" in front of the alphabetical letters that denote the signal.) A bus usage permit signal line 4 transfers a bus usage permit signal *BG issued by the bus regulating circuit 1 for permitting each module to use the bus. Denoted at 5 is a bus busy signal line for transferring a bus busy signal *BBSY. The bus is shared by modules 10, 20, 30. Although the modules are not necessarily identical in structure, they have at least CPUs 11, 21, 31, respectively, and bus control circuits (BC) 12, 22, 32, respectively. Since the modules operate in the same manner for bus control, module 10 will hereinafter be described. The CPU 11 has a ROM and a RAM contained therein, though not shown. The CPU 11 applies, to the bus control circuit 12, a bus request signal IRQ and outputs DO1, DO2 representative of conditions for controlling the bus. The bus control circuit 12 is responsive to the bus request signal *IRQ and the outputs DO1, DO2 from the CPU 11 for performing various control modes such as for requesting the bus, maintaining the right to use the bus, and abandon the right to use the bus. The bus control circuit 12 and controlling of the bus will be described in detail below. The bus control circuits 22, 23 are of the same circuit arrangement. FIG. 2 shows a circuit arrangement of the bus control circuit 12. Various reference characters for circuit elements are defined as follows: AG1 - AG5 AND circuits NG1 - NG2 NAND circuits NOG1 NOR circuit IV1 - IV5 NOT circuit FF1 - FF5 flip-flops Various signals are as follows: A signal IRQ is a request signal from the CPU 11. In response to this signal, the bus control circuit 12 decides whether it should issue a request signal or not. A signal DO1 is a DO signal from the CPU 11. When it is of a logic "1", the module 10 does not issue a request signal *RQ if a request signal is issued from another module even when a request signal IRQ is issued from the internal CPU 11. When the signal DO1 is of a logic "0", the module 10 issues a request signal *RQ if a request signal IRQ is issued from the internal CPU 11 even when a request signal is issued from another module. A signal *BG is a bus usage permit signal which is issued from the bus regulating circuit 1. When this signal is applied at the time the module 10 is issuing a request signal *RQ, the module 10 can, in principle, obtain the right to use the bus. If the module 10 is not issuing a request signal *RQ, the signal *BG is applied to another module requesting the use of the bus. A signal DO2 is a DO signal from the CPU 11. When this signal is of a logic "1", the module 10 is using the bus. Even when the use of the bus by the module 10 is over, unless a request signal *RQ is issued from another module, the module 10 does not abandon the exclusive use of the bus, but maintains the right to use the bus. When this DO signal is "0", the module 10 abandons the right to use the bus immediately upon completion of use of the bus, and gives the right to use the bus to another module. A signal *RQ is a request signal which is delivered over the request signal line 3 to the bus regulating circuit 1. A signal *BG is a bus usage permit signal. When the module 10 does not use the bus, this signal is transferred to the next module. A signal *BBSY is a bus busy signal which is issued when the module 10 is using the bus. Operation of the bus control circuit will be described. A request signal IRQ is issued from the CPU 11. When the signal DO1 from the CPU 11 is "1" and if a request signal *RQ is being issued from another module, the module 10 does not use the bus. Therefore, if a request signal *RQ is being issued from another module, the output *RQ becomes "0" since the common bus line type is employed, and the NG1 issues an output of "0". The FF1 is not set, no request signal *RQ is issued out even if the request signal IRQ is given from the CPU 11, and the bus is not used. Conversely, when the output signal DO1 is "0" and the request signal IRQ is issued, the output from the NG1 is "1" even if a request signal *RQ is issued from another module and the request signal *RQ is "0". With the output IRQ from the CPU 11 being "1", the FF1 is set, and the module 10 attempts to obtain the right to use the bus. The case where a bus usage permit signal *BG is issued from the bus regulating circuit 1 will then be described. The IV3, FF2, FF3, AG2 jointly constitute a negative-going edge detector circuit 13. More specifically, when the bus usage permit signal *BG becomes "0", the AG2 issues an output of "1". If the module 10 is attempting to get the right to use the bus at this time, since the FF1 has been set to "1", the output of the AG4 becomes "1", setting the FF5, and the bus busy signal *BBSY becomes "0". The module 10 now informs the bus regulating circuit 1 of exclusive use of the bus, and keeps the right to use the bus. Conversely, even when the AG2 becomes "1" at a negative-going edge of the bus usage permit signal *BG, the output of the AG4 does not become "1" unless the FF1 has been set, and the output of the AG3 becomes "1", setting the FF4. With the FF4 being thus set, the bus usage permit signal *BG is applied through the FF2, FF3 to cause the output of the NG2 to become "0". The bus usage permit signal *BG is now transferred to the next module, and the bus 10 does not keep the right to use the bus. The function of the signal DO2 from the CPU 11 will be described below. When the DO2 is "1", the module 10, even if it has finished the use of the bus, occupies the bus and keeps it so that the module 10 can use it immediately, unless there is a request signal *RQ from another module. More specifically, even when the request signal IRQ becomes "0" after the CPU 11 has finished the use of the bus, the output of the IV4 is "0", and the output of the NOG 1 is "1" unless the request signal *RQ becomes "0", i.e., the output of the IV2 becomes "1". The output of the AG5 is "0", and the FF5 is not reset, so taht the right to use the bus is maintained. Therefore, when the CPU 11 tries to use the bus next time, it can immediately use the bus without communicating with the bus regulating circuit 1. Conversely, when the DO2 is "0", the output of the IV4 is "1" and the output of the NOG1 becomes "0". When the use of the bus is over and the request signal IRQ from the CPU 11 becomes "0", the output of the AG5 becomes "1", resetting the FF5, and the bus busy signal *BBSY becomes "1". The bus is now open to use by the other modules. The sequence of operation will be described with reference to a timing chart. FIG. 3 shows a timing chart of controlling of the bus. Denoted in FIG. 3 at IRQ is a request signal issued from the CPU 11 in the module, *RQ a request signal from the module, *BG a bus usage permit signal, a *BBSY a bus busy signal, and BUS the condition of how the module 10 uses the bus. These signals are denoted by the same reference characters as those used in FIG. 2. When the CPU 11 issues a request signal IRQ and the signal DO1 is "0", the module 10 issues a request signal *RQ irrespective of the status of request signals *RQ from the other modules. When the request signal *RQ is applied to the bus regulating circuit 1, the bus regulating circuit 1 produces a bus usage permit signal *BG unless the bus is not being used by another module. When the bus usage permit signal *BG is fed to the module 10, the module 10 obtains the right to use the bus and issues a bus busy signal *BBSY. Upon issuance of the bus busy signal *BBSY, the bus regulating circuit 1 and the other modules 20, 30 are informed of the fact that the bus is occupied by the module 10. When the module 10 has finished the use of the bus, and if the output of the DO2 is "1", the module 10 does not abandon the right to use the bus, and the bus is kept by the module 10 unless there is a request signal *RQ from another module. When a next request signal IRQ is issued from the CPU 11, the module 10 can immediately use the bus. Conversely, when the output of the DO2 is "0", the bus is made open to use by other modules immediately upon completion of the use of the bus by the bus 10. This condition is indicated by the dotted lines in FIG. 3. If a request signal *RQ is issued from another module before a next request signal IRQ is produced, the right to use the bus is given to the other module, and the module 10 cannot immediately use the bus. Thus, where there is a conflict among modules about the use of the bus, the priority can be changed according to tasks to be processed by issuing a request signal *RQ or abandon the right to use the bus after the usage of the bus. Therefore, the processing of software can be performed efficiently. While only three modules are involved in the above description, the invention is not limited to the three modules. With the present invention, as described above, each module has means for determining overlapping requests and means for determining continued use. Each module can use the bus with priority according to the priority of the task that is processed by the module. As a result, the processing of software can be performed efficiently.

Claims: A bus regulating system having a plurality of modules (10,20,30), a bus (2) shared by the modules, a bus regulating circuit (1), a bus request signal line (3), a bus usage permit signal line (4) in the form of a daisy chain, and a bus busy signal line (5), said bus regulating system being characterised by each module having overlapping request determining means (DO1) for determining whether an overlapping request signal is to be issued or not when a request signal is being issued from another module, and continued use determining means (DO2) for determining whether the obtained right to use the bus is to be abandoned or maintained after said bus has been used. A bus regulating system according to claim 1, wherein said overlapping request determining means and said continued use determining means can be rewritten by software.

Inventors: YONEKURA MIKIO, YONEKURA, MIKIO
Applicants: FANUC LTD, FANUC LTD.
Application year: 1987
Main classification: G06F13
IPC codes: G06F13