Process and circuit for acquisition of carrier synchronism in coherent demodulators

Abstract: A process and a circuit for the acquisition of a carrier synchronism applicable to coherent demodulators which operate with carriers modulated by phase-shift keying (PSK). A modulated signal is divided into two signals which are multiplied (2,3) by two quadrature carriers, and the resulting signals are then added together (8) and subtracted (9) from each other to obtain a plurality of signals. At least two of them are sampled with a first frequency and at least two others are sampled with another frequency which is an even multiple of the first frequency. The proposed process makes use of a simple, low-cost circuity and gives the phase-lock loop of the demodulator an added frequency characteristic which prevents false locks and ensures lock between the local carrier and the reference signal even for very large frequency variations.

Description: The present invention relates to the field of digital signal transmissions and more specifically to a process and related circuit for the acquisition of carrier synchronism in coherent demodulators which receive at their input a PSK, or more general QAM, modulated signal. It is known that digital radio signal receivers include demodulators and that to demodulate said signals, generally modulated by the Phase Shift Keying (PSK) technique, it is necessary to reconstruct on the basis of the information contained in the received signals a local carrier identical to the one that was suppressed in the transmitted signals. Among the methods used for reconstruction of the local carrier those most widely used are derived from the Costas loop and to generate said carrier require the use of a local voltage controlled oscillator (VCO) inserted in a phase-locked loop (PLL). The VCO is controlled by means of an error signal function only of the phase-offset existing between the local and the suppressed carrier. A first limitation of the Costas loop technique and of all demodulation systems which use an only-phase comparator for carrier locks is the limited capture range. As is known the capture range of the phase-lock loop is given by the maximum frequency difference (Δf) between the ouput signal frequency of the local oscillator in the absence of a reference signal and the ouput signal frequency from the same local oscillator which permits the loop to achieve phase lock in the presence of a reference signal. Because of this limitation it is necessary to equip the phase-lock loop with search devices to increase the capture range thereof as it will be better seen with reference to Fig.1. A second limitation of the Costas loop technique is that it makes possible false locks, i.e. it can happen that the phase-lock loop finds stable points of equilibrium even for particular frequency values of the local oscillator which do not correspond to the input signal frequency, making impossible demodulation of said input signal. In the article of G.L. Hedin, J.K. Holmes, W.C. Lindsey and K.T. Woo entitled "Theory of False Lock in Costas Loops" published in IEEE Transactions on Communications, Vol. COM-26, No. 1, January 1978 the authors examine some of the causes which bring about false locks and show that the Δf i frequencies at which they can occur have values which are a multiple of the symbol frequency fs divided by the number of the modulation phases in accordance with the formula: Δf i = n·fs/m , where n = 1,2,.... and, in case of Quadrature Phase-Shift Keying (QPSK), m = 4. In the same article it is shown that the spectral distribution of the error signal in lock condition is different depending on whether the lock is true or false. In particular the components at multiple frequencies of the symbol frequency have different amplitude. A first process is proposed to achieve correct lock consists first of detecting the presence of false locks by measurement of the amplitude of the aforesaid components and then forcing the phase-lock loop into the correct lock condition. The proposed process is rather complicated, the hardware implementation is difficult to accomplish and in particular it does not always assure correct operation. In other articles there is introduced a parameter called 'False-Lock Margin' represented by the ratio between the continuous component of the error signal under true lock conditions and the continuous component of the error signal in the different possible conditions of false lock, dependent in value on the transmission channel band. It can be noted and experimentally confirmed that the false lock margin is extremely reduced in QPSK systems, in which the first false lock takes place for Δf i = fs/4 . This suggests a second process for avoiding false locks which consists of limiting the range of the local oscillator to values lower than ±fs/8. In this manner all false locks would be avoided. However this solution is not always practicable especially in small-capacity systems for which the term fs/8 can be a very small fraction of the nominal carrier frequency. Indeed, in these systems, because of the instability of the local oscillator, transmission oscillator and local oscillators of the converters contained in the transceiver, the nominal value of the input signal frequency has a certain indefiniteness which can be greater than fs/8. Hence this second process widely used for medium and large capacity systems is absolutely unusable for small-capacity systems unless sophisticated and costly very high stability oscillators are adopted. A phase locked loop circuit, derived from the Costas loop with the addition of means for extending the capture range of the PLL avoiding false locks, is disclosed in the US patent US-A-4,338,574, inventors Fujita et all. The additional means consist of: a delay line which opportunely delays a first error signal generated inside the loop; a comparator which compares said first delayed error signal with the only-phase error signal at the output from the Costas loop, obtaining a third error signal only depending on the frequency offset existing between the local and the suppressed carrier. This third only-frequency depending error signal is low-pass filtered and becomes a second control signal for the VCO. Even if the circuit of Fujita overcomes the main drawbacks of the previous demodulators, it shows however the drawback of generating two different error signals, namely an only-phase and an only-frequency one. A third process proposed for extending the capture range in QPSK demodulators derived from the Costas loop is described in the article by F.D. Natali entitled "AFC Tracking Algorithms" published in IEEE Transactions on Communications, Vol. COM-32 No. 8, August 1984 and which consists of utilizing a phase-frequency comparator. The proposed solution appears to be rather complex in terms of hardware implementation, requiring the use of linear multipliers and analog-to-digital converters difficult to use in small-capacity systems where low cost and small size are of primary importance. The object of the present invention is to overcome the aforesaid drawbacks and indicate a process for acquisition of carrier synchronism in coherent demodulators which by making use of simple and low-cost hardware implementation gives the phase-lock loop of the demodulator an added frequency characteristic, obtaining only one error signal simultaneously depending on both phase and frequency. Said added frequency characteristic ensures locking between the local carrier and the carrier (suppressed) of the received signals, avoiding false locks, and also ensures a sufficiently ample capture range. To achieve said aims the object of the present invention is a process for the acquisition of the carrier sinchronism in coherent demodulators, as better explained in the claim 1. Other object of the present invention is a circuit for the acquisition of carrier synchronism, as better explained in the claim 5. Other aims and benefits of the present invention will be made clear by the detailed description given below and the annexed drawings given merely as an explanatory and nonlimiting example wherein: FIG. 1 shows a block diagram of a demodulator in accordance with the known art, FIG. 2 shows a block diagram of a demodulator in accordance with the present invention, FIG. 3 shows a first hardware implementation of a block of FIG. 2, FIG. 4 shows a second hardware implementation of the same block of FIG. 2, FIG. 5 shows some experimental voltage versus frequency output characteristics of the demodulator, which is the object of the present invention, and FIG. 6 shows some experimental voltage versus frequency output characteristics of the demodulator, which is the object of the present invention, in the presence of thermal noise. FIG. 1 represents a Quadrature Phase-Shift Keying (QPSK) or Offset Quadrature Phase-Shift Keying (O-QPSK) demodulator of the Costas loop type in which 1 indicates a power splitter at the input of which is presented a modulated reception signal IF and the outputs of which are connected to the first input of a mixer 2 and to the first input of a mixer 3 respectively. At the second input of the mixer 2 arrives the output signal of a voltage-controlled local oscillator 4. Said signal, through a 90° phase shifter 5, also reaches the second input of the mixer 3. The output of the mixer 2 is connected to the input of a low-pass filter 6 the output of which is connected to an input of an adder 8, to an input of a subtractor 9 and to the input of a regenerative comparator 10. The output of the mixer 3 is connected to the input of a low-pass filter 7 the output of which is connected to the second input of the adder 8, to the second input of the subtractor 9 and to the input of a regenerative comparator 11. The output of the adder 8 is connected to the input of a regenerative comparator 12 while the output of the subtractor 9 is connected to the input of a regenerative comparator 13. The output of the comparator 10 is connected to an input of a multiplier 14 and to the input D of a flip-flop 17 while the output of the comparator 11 is connected to the other input of the multiplier 14 and to the input D of a flip-flop 18. The outputs of the comparators 12 and 13 are connected to the two inputs of a multiplier 15. The outputs of the two multipliers 14 and 15 are connected to the two inputs of a multiplier 16 the output of which is connected to the input of a low-pass filter 19. The output of the filter 19 is connected to the input of an amplifier 20 the output of which is connected to the first input of an adder 30 to the second input of which is connected the output of a block 21. The output of the adder 30 is connected to the control input of the local oscillator 4. As is known, in operation the intermediate frequency IF signal is split by the splitter 1 to a first input of each of the mixers 2 and 3. To the second input of the mixer 2 arrives the output signal of the local oscillator 4 while at the second input of the mixer 3 arrives the output signal of the local oscillator 4 phase shifted 90° by the phase shifter 5. The demodulated signals at the outputs of the mixers 2 and 3 pass through the low-pass filters 6 and 7, which serve primarily to reduce the noise present in the demodulated signal band and are indicated by A₁ and B₁ respectively. Through the adder 8 and the subtractor 9 the two signals A1 and B1 are added together and subtracted from each other, generating the signals A1+B1 and A1-B1 respectively. The four signals A1, B1, A1+B1 and A1-B1 through the comparators 10, 11, 12 and 13 are digitalized, generating four streams of digitalized data respectively A2, B2, A2+B2 and A2-B2. The signals A2 and B2 reach the input D of the samplers 17 and 18 respectively to the clock input CK of which arrives a clock signal CP taken from the demodulated signal A1 or B1 or from the received signal IF. The samplers 17 and 18 regenerate the signals A2 and B2, reconstructing the data streams transmitted and indicated by A4 and B4 respectively. The signals A2 and B2 are also multiplied together by means of the multiplier 14. The signals A2+B2 and A2-B2 are multipled together by means of the multiplier 15. The output signals from the multipliers 14 and 15 are further multiplied together by the multiplier 16, the output signal of which is the error signal e(ϑ). The signals A2, B2, A2+B2 and A2-B2 being digital on two levels, the multipliers 14, 15 and 16 are logical gates which accomplish the OR-Exclusive function. The blocks enclosed by the broken line of FIG. 1 represent a phase comparator of the Costas loop type the output signal of which e(ϑ) represents the phase error signal for control of the local oscillator 4 and where 8 is the phase shifting angle between the local carrier and the modulation carrier. The information on the modulation carrier phase is then taken from the signals A1 and B1 and the function e(ϑ) is null only when the local carrier phase coincides with that of the modulation carrier. The low-pass filter 19 extracts the continuous component present in the error voltage e(ϑ). Said component after being amplified by the amplifier 20 is applied to the first input of the adder 30, to the second input of which arrives the output signal of the block 21. The output signal of the adder 30 is applied to the control input of the local oscillator 4 to allow it to achieve phase lock with the modulation carrier, keeping this condition steady. The block 21 is a known device for seeking lock which permits extending the capture range and consists primarily of a triangle-waveform oscillator which, when the phase-lock loop is unlocked, periodically varies the frequency of the voltage controlled local oscillator 4 over its entire scanning range. When the lock has taken place the loop reacts to counterbalance the output voltage of the triangle-waveform oscillator and cancel out its effect. FIG. 2, in which the same elements as in FIG. 1 are shown with the same numbers, differs from FIG. 1 only by the addition of a block 22 having four inputs and four outputs and by the absence of block 21 and adder 30. The block 22 is placed between the outputs of the comparators 10, 11, 12 and 13 and the inputs of the multipliers 14 and 15. The blocks enclosed by the broken line of FIG. 2 represent a phase-frequency comparator the output signal e(ϑ,f) of which represent the phase-frequency error signal for control of the local oscillator 4. The error signal e(ϑ,f) generated by the circuit in this configuration compared with the known configuration of FIG. 1 is a function of the phase difference and of the frequency difference between the locally generated carrier and the modulation carrier. The function of the block 22 is to process the four signals A2, B2, A2+B2 and A2-B2 in such a manner that in its output signals A3, B3, A3+B3 and A3-B3 there is present information on the carrier frequency (suppressed) of the signal received, i.e. said block 22 gives to the phase-lock loop an added frequency characteristic and also permits extension of the capture range. FIG. 3 represents an embodiment of the circuit of the block 22 for a QPSK demodulator. Within the block there is a known oscillator 23 which generates a signal the frequency of which is indicated by 2fc. Said signal is sent to the three clock inputs CK of three type-D flip-flops 24, 26 and 27. The output Q of flip-flop 24 is connected to the input D of said flip-flop 24 to achieve the known configuraton of the divider by two. Therefore, at the output Q of the flip-flop 24 there is present a clock signal at frequency fc which together with the frequency 2fc serves for the sampling of the input signals of the block 22. The output Q of the flip-flop 24 is connected to the two clock inputs CK of two flip-flops 25 and 28. The input D of the flip-flop 25 is connected to the output of the comparator 10 while the output Q of said flip-flop is connected to the first input of the multiplier 14. The input D of the flip-flop 28 is connected to the output of the comparator 11 while the output Q of said flip-flop is connected to the second input of the multiplier 14. The input D of the flip-flop 26 is connected to the output of the comparator 12 while the output Q of said flip-flop is connected to the first input of the multiplier 15. The input D of the flip-flop 27 is connected to the output of the comparator 13 while the output Q of said flip-flop is connected to the second input of the multiplier 15. FIG. 4 represents an embodiment of the circuit of the block 22 for an O-QPSK demodulator and differs from FIG. 3 in that between the output of the oscillator 23 and the clock input CK of the flip-flop 24 is inserted an invertor 29 and in that the clock signal at the flip-flop 25 is not fc but f c, i.e. a phase shifted signal by one-half period from fc. In operation the circuit of FIG. 3 samples the signals A2 and B2 at frequency fc and the sampling of signals A2+B2 and A2-B2 with double frequency, i.e. 2fc. The signals A2+B2 and A2-B2 can be sampled with any frequency that is an even multiple of fc. Operation of the circuit of FIG. 4 differs from that of FIG. 3 in that the signal A3 is sampled at frequency f c, i.e. with a signal in phase opposition compared to the signal with frequency fc. As is known, in an O-QPSK system the two demodulated signals A1 and B1 are phase shifted with each other by a half period so that the respective sampling signals must also be phase shifted by a half period. In addition, for both solutions the frequency fc can be equal to or greater than the symbol frequency fs of the signal received. In the first case there is synchronous sampling and in the second case there is asynchronous sampling. With synchronous sampling the oscillator 23 will clearly no longer be a free oscillator but will have to be an oscillator controlled by the input signal so that it oscillates at a frequency such that fc = fs. In addition, to avoid the sampling signals at frequency fc or 2fc falling into the transition zone of signals A2, B2, A2+B2 and A2-B2 which are zones devoid of information a phase shifter is required which will permit regulation of the phase of the sampling signals. With asynchronous sampling it has been found that the behaviour of the circuit depends on the relationship between fc and fs. This behaviour is explained in FIGS. 5 and 6. FIG. 5 represents the voltage versus frequency output characteristic experimentally taken with an open loop of the phase-frequency comparator which is the object of the present invention. Specifically it represents the mean value of voltage e(ϑ,f) at the output of the phase-frequency comparator, dependent in value on the frequency difference Δf between the frequency of the local oscillator 4 and the frequency of the carrier (suppressed) of the input signal, normalized with reference to the symbol frequency fs. FIG. 5 shows three curves indicated with the letters a, b and c. Curve a represents the output characteristic of a phase-only comparator accomplished in accordance with the known art. Curves b and c were obtained from the phase-frequency comparator included in the circuit for the acquisition of carrier synchronism which is the object of the present invention for different values of fc/fs, specifically for fc/fs = 1 (synchronous sampling) and for fc/fs = 3 (asynchronous sampling). Observing curve a it is seen that as freqency Δf varies, the output voltage of the known comparator is always zero, i.e. there is no variation of the error signal e(ϑ) with variations in the frequency. Observing the curves b and c it is seen that as the frequency Δf varies, the error signal e(ϑ,f) which drives the local oscillator for generation of the local carrier at the exact frequency of the signal carrier varies, preventing false locks. Curve c also shows a more extensive capture range than curve b. The capture range is represented by the value Δf so that the error voltage e(ϑ,f) reverses its sign. For an increase in the capture range there is a corresponding reduction of the slope of the curve and hence a reduction in the gain of the phase-frequency comparator. Choice of the sampling frequency will therefore depend on the specific characteristics and performances required of the demodulator. FIG. 6 shows curve c, which is the same as that of FIG. 5 obtained with fc/fs = 3 and in the absence of noise at the input of the demodulator (signal/noise ratio S/N = ∞ ), and curve c1 which is also obtained with fc/fs = 3 with a signal/noise ratio S/N of 4dB. The condition S/N = 4dB is the worst case so that the real curves will stay in the area between c and c1 to assure excellent operation at all times. As is known, the QAM modulation technique is derived from PSK modulation, having in addition amplitude modulation. Consequently everything said for the QPSK modulator applies to a QAM demodulator. In particular for recovery of the modulation carrier the same phase-frequency comparator which is the object of the present invention is applicable. From the description given the advantages of the process and of the circuit for the acquisition of carrier synchronism for coherent demodulators which are the object of the present invention are clear. Specifically they are represented by the fact that the demodulators produced in accordance with the proposed process are free from false locks and have a very extensive capture range obtained without the help of a supplementary search device. Furthermore, by merely varying the sampling frequency fc it is possible to control within fairly extensive limits the capture range. Lastly, the circuit is very simple and economical and being completely digital can be readily accomplished by integrated circuit technology. It is clear that numerous variants of the process and the circuit for acquisition of carrier synchronism for coherent demodulators described as an example are possible for those skilled in the art without thereby exceeding the scope of the claims.

Claims: Process for acquisition of carrier synchronism in coherent demodulators in which an intermediate frequency receiving signal (IF), PSK or QAM modulated, is splitted (1) into two equal signals, a first one being frequency multiplied by a locally generated carrier obtaining a first demodulated signal (A1), a second one being frequency multiplied by an in-quadrature locally generated carrier obtaining a second demodulated signal (B1), the first and second demodulated signals being in turn added and subtracted toghether obtaining a sum and a difference signals (A1+B1, A1-B1) which are digitalized (A2+B2, A2-B2) and multiplied (15) obtaining a first multiplied signal, the first and second demodulated signals (A1, B1) being digitalized (A2, B2) and multiplied (14) obtaining a second multiplied signal, the first and second multiplied signals being multiplied (16) obtaining an only-phase error signal (e(ϑ)), low-pass filtered (19, 20) to control said locally generated carrier, characterized in that: the sum and the difference digitalized signals (A2+B2, A2-B2) are sampled by a first sampling signal with a first frequency (2f c ) higher than the symbol frequency f s of said receiving signal (IF); the first and second demodulated digitalized signals (A2, B2) are sampled by means of a second sampling signal with a second frequency f c even sub-multiple, preferably 1/2, of said first frequency (2f c ) and equal or higher than said symbol frequency f s ; the sampling of said: sum, difference, first and second demodulated digitalized signals adding to said only-phase error signal (e(ϑ)) a further dependance (e(ϑ,f)) from the frequency offset (f) existing between said locally generated carrier and the suppressed modulation carrier of said receiving signal (IF). Process for acquisition of carrier synchronism in accordance with claim 1, characterized in that both said first and second sampling frequencies (2f c , f c ) can be increased or decreased in respect of said symbol frequency f s , in order to respectively extending or reducing the acquisition frequency range of said carrier synchronism. Process for acquisition of carrier synchronism in accordance with claim 1, characterized in that said first and second sampling signals are appropriately shifted of a same phase amount in comparison with said suppressed modulation carrier, avoiding, in case of synchronous sampling with f c = f s , the sampling falling within transition zones of to-be-sampled digitalized signals (A2, B2, A2+B2, A2-B2) devoid of information. Process for acquisition of carrier synchronism in accordance with claim 1, characterized in that said first demodulated digitalized signal (A2) is sampled by the second sampling signal half-period shifted in comparison with said second sampling signal which samples said second demodulated digitalized signal (B2), in order to correctly sample an intermediate frequency receiving signal (IF) O-PSK modulated. Circuit for acquisition of carrier synchronism in coherent demodulators comprising: a power splitter (1) splitting an intermediate frequency receiving signal (IF), PSK or QAM modulated, into two equal signals reaching a first input of a respective first (2) and second (3) mixer whose second inputs are respectively reached by a local carrier generated from a VCO (4) and by an in-quadrature local carrier obtained shifting said local carrier by means of a quarter-wave shifter (5), the mixers output signals being a first and a second demodulated signals (A1, B1) which are in turn added and subtracted together by means of an adder (8) and a subtractor (9) circuit, obtaining a sum (A2+B2) and a difference (A2-B2) signals which are digitalized by regenerative comparators (12, 13) and multiplied (15) obtaining a first multiplied signal; said first and second demodulated signals (A1, B1) being digitalized (A2, B2) and multiplied (14) obtaining a second multiplied signal, the first and second multiplied signals being multiplied (16) obtaining an only-phase error signal (e(ϑ)) which, after low-pass filtering (19, 20), reaches a control input of said VCO (4), characterized in that it further comprises: oscillator means (23) for generating a first sampling signal with a first frequency (2f c ) higher than the symbol frequency f s of said receiving signal (IF); frequency dividing means (24) to divide said first frequency (2f c ) by an even number, preferably 2, obtaining a second sampling signal with a second frequency f c equal or higher than the symbol frequency f s ; and a first and a second sampling circuits (25, 28), clocked by said second sampling signal, for sampling the first and second demodulated digitalized signals (A2, B2); a third and a fourth sampling circuits (26, 27), clocked by said first sampling signal (2f c ), are provided for sampling the sum and the difference digitalized signals (A2+B2, A2-B2); the sampling of said: sum, difference, first and second demodulated digitalized signals adding to said only-phase error signal (e(ϑ)) a further dependance (e(ϑ,f)) from the frequency offset (f) existing between said local generated carrier and the suppressed modulation carrier of said receiving signal (IF). Circuit for acquisition of carrier synchronism in accordance with claim 5, characterized in that said oscillator means (23) include means for increasing or decreasing the value of said first frequency (2f c ) of said first sampling signal in comparison with said symbol frequency f s , in order to respectively extend or reduce the acquisition frequency range of said carrier synchronism. Circuit for acquisition of carrier synchronism in accordance with claim 5, characterized in that: said first (26), second (27), third (25) and a fourth (28) sampling circuits are respectively a first (26), second (27), third (25) and fourth (28) flip-flops; in that said frequency dividing means is a fifth flip-flop (24) dividing said first frequency (2f c ) of said first sampling signal by two; in that both said first (26) and second (27) flip-flops are clocked by said first sampling signal; and in that both said third (25) and fourth (28) flip-flops are clocked by a true output signal of said fifth flip-flop, in order to correctly sample an intermediate frequency receiving signal (IF) PSK or QAM modulated. Circuit for acquisition of carrier synchronism in accordance with claim 5, characterized in that: said first (26), second (27), third (25) and a fourth (28) sampling circuits are respectively a first (26), second (27), third (25) and fourth (28) flip-flops; in that said frequency dividing means is a fifth flip-flop (24) dividing said first frequency (2f c ) of said first sampling signal by two; in that said fifth flip-flop (24) is clocked by a first sampling signal inverted; in that both said first (26) and second (27) flip-flops are clocked by said first sampling signal; in that said fourth flip-flop (28) is clocked by a non-inverted output signal of said fifth flip-flop; and in that said third flip-flop (25) is clocked by an inverted output signal of said fifth flip-flop, in order to correctly sample an intermediate frequency receiving signal (IF) O-PSK modulated. Circuit for acquisition of carrier synchronism in accordance with claim 5, characterized in that: said oscillator means (23) comprise an oscillator controlled by said intermediate frequency receiving signal (IF) for generating a first sampling signal whose first frequency (2f c ) is an exact even multiple of said symbol frequency f s ; and in that shifting means are provided to opportunely shift said first sampling signal in comparison with said suppressed modulation carrier, avoiding the sampling falling within transition zones of the to-be-sampled digitalized signals (A2, B2, A2+B2, A2-B2) devoid of information.

Inventors: CERONI ETTORE, LO CURTO MICHELANGELO, CERONI, ETTORE, LO CURTO, MICHELANGELO
Applicants: SITS SOC IT TELECOM SIEMENS, SIEMENS TELECOMUNICAZIONI S.P.A.
Application year: 1987
Main classification: H04L27
IPC codes: H04L27, H04L7