SEMICONDUCTOR DEVICE HAVING A FUSE CIRCUIT AND A DETECTING CIRCUIT FOR DETECTING THE STATES OF THE FUSES IN THE FUSE CIRCUIT

Abstract: A semiconductor device comprises a fuse circuit having first and second fuses (F1,F2) for storing an information by blown and unblown states of the fuses (F1,F2), an information output circuit for providing an output signal having a first logic level when at least one of the fuses (F1,F2) in blown and an output signal having a second logic level when both the fuses (F1,F2) are unblown, and a detecting circuit for detecting which one of the fuses (F1,F2) is unblown. This detecting circuit has a first transistor (Q1) connected to the first fuse (F1) in parallel and turned ON in response to a first check signal (X), and a second transistor (Q2) connected to the second fuse (F2) in parallel and turned ON in response to a second check signal (Y).

Description: BACKGROUND OF THE INVENTION The present invention generally relates to semiconductor devices having detecting circuits for detecting states of fuses in fuse circuits, and more particularly to a semiconductor device having a fuse circuit provided with pairs of fuses and a detecting circuit for detecting states of each pair of fuses in the fuse circuit. Fuses which are blown by electrical or laser programming are often used in semiconductor devices. For example, fuses are used in a semiconductor memory device employing a redundancy configuration, so that redundancy memory cells may be used in place of defective memory cells. In addition, fuses are often used to select one or a plurality of circuit elements such as resistors provided in a semiconductor device. In the case of the semiconductor memory device such as a random access memory (RAM), a large number of memory cells are arranged along rows and columns. The density of defects generated in the memory device in the manufacturing process is relatively independent of the integration density of the memory device and is dependent on the manufacturing technology. In general, the higher the integration density of the memory device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of the memory device. However, when the memory device includes defective memory cells, the memory device will not operate correctly and must thus be destroyed. As a result, despite the low ratio of defective memory cells to the normal memory cells, the manufacturing yield of the memory device is reduced. In order to overcome this problem of defective memory cells, the memory device employs the redundancy configuration. According to the redundancy configuration, one or two rows or columns of redundancy memory cells are provided, and a row or column of redundancy memory cells is selected instead of a defective row or column of memory cells when a defective memory cell is detected in the defective row or column. A redundancy control circuit is provided to store address information of such a defective row or column of memory cells and to disable regular decoders for selecting normal memory cells, so as to select the row or column of redundancy memory cells in response to an address of the defective row or column. The redundancy control circuit comprises fuse-type read only memories (ROMs) each having an information storing circuit. A unit information storing circuit in a prior art device incorporates one fuse for each bit of the address information to be stored. Therefore, the information storing circuit stores a datum "1" or "0" by a blown or unblown fuse. For example, when writing the datum "1", a polysilicon fuse is blown by electrical or laser programming. However, especially when the polysilicon fuse is blown by the electrical programming, the polysilicon fuse may grow back during the life of the memory device. For this reason, when only one fuse is provided for one bit of the address information and the grow back occurs, it is impossible to make use of the redundancy memory cells and the reliability of the memory device is unsatisfactory. Accordingly, an improved memory device was previously proposed in a United States Patent No.4,592,025 (=EP-A-0 151 849) in which the assignee is the same as the assignee of the present application. According to this previously proposed memory device, two fuses are provided for one bit of the address information. For example, when writing the datum "1", both the two fuses are blown by electrical or laser programming. A detection to determine the states of the fuses may be carried out by obtaining a logical sum of signals obtained via the two fuses. From the logical sum, it is possible to detect whether the two fuses are both unblown or at least one of the two fuses is blown. Hence, in the above case, even when the two fuses are blown by the electrical programming but one of the fuses grows back, it is still possible to detect that the bit of the address information is intended to contain the datum "1". As a result, the reliability of the memory device is greatly improved compared to the prior art device in which only one fuse is provided for one bit of the address information, because the probability that both the two blown fuses will grow back is considerably small compared to the probability that the single fuse will grow back. But in actual practice, the fuses need to be re-programmed if the fuses which should be blown are actually unblown due to incomplete programming or grow back. It is easy to detect the state of the fuse when only one fuse is provided for one bit of the address information. However, when two fuses are provided for one bit of the address information, it is impossible to know from the logical sum described above whether only one of the two fuses is blown or both the two fuses are blown. Furthermore, in the case where only one of the two fuses is blown, it is impossible to discriminate which one of the two fuses is blown. When two fuses are provided for one bit of the address information but one of the two fuses which should be blown is actually unblown, the situation is the same as the prior art device described before. In other words, when the blown fuse grows back, there is a problem in that it is impossible to make use of the redundancy memory cells and the reliability of the memory device is unsatisfactory. Hence, in this case, it is desirable to discriminate which one of the two fuses is unblown and re-program the unblown fuse so that both the two fuses are blown as originally intended. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a semiconductor device having fuse circuit and detecting circuit for detecting states of fuses in the fuse circuit, in which the problems described heretofore are eliminated. Another and more specific object of the present invention is to provide a semiconductor device comprising a fuse circuit having pairs of fuses for storing an information bit by use of one pair of fuses, and a detecting circuit for detecting states of each pair of fuses in the fuse circuit. According to the semiconductor device of the present invention as specified in claim 1, it is possible to detect the state of a fuse in each pair of fuses with ease. Even when only one of the pair of fuses is blown, it is possible to positively detect which one of the pair of fuses is unblown. Therefore, the present invention is especially suited for a semiconductor memory device having a redundancy configuration. The present invention can also be applied to a semiconductor device having a selection circuit for selecting one or a plurality of circuit elements such as resistors, where the fuse circuit stores address information for controlling the selection circuit so as to selectively use predetermined circuit elements on the semiconductor device. The objects and features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a system block diagram showing an embodiment of the semiconductor device according to the present invention applied to the semiconductor memory device employing a redundancy configuration; FIG.2 is a system circuit diagram showing an embodiment of a redundancy control circuit in the semiconductor device shown in FIG.1; FIG.3 is a circuit diagram showing an essential part of the redundancy control circuit shown in FIG.2; and FIG.4 is a system circuit diagram showing another embodiment of the redundancy control circuit in the semiconductor device shown in FIG.1. DETAILED DESCRIPTION FIG.1 shows an embodiment of the present invention applied to a semiconductor memory device having a redundancy configuration. The semiconductor memory device comprises a memory cell array 11, a column decoder 12, a row decoder 13, an output buffer 14, a redundancy memory cells 15, an address buffer 16, a selection circuit 17, a redundancy control circuit 18, and a redundancy row decoder 19. An n-bit address signal applied to terminals 20 l through 20 n is supplied to the address buffer 16, and bits AD l through AD i of the address signal are supplied to the row decoder 13 while bits AD i+l through AD n are supplied to the column decoder 12. The row decoder 13 and the column decoder 12 decode the address bits and respectively designate predetermined row and column addresses in the memory cell array 11. A stored datum at the address designated by the row and column decoders 13 and 12 is read out from the memory cell array 11 and is passed through the output buffer 14. Bits O₁ through O₈ of the read out datum are outputted via terminals 21₁ through 21₈. The redundancy control circuit 18 comprises a memory circuit for storing addresses of defective memory cells in the memory cell array 11, a comparing circuit for comparing the input address and the address of the defective memory cell stored in the memory circuit, and a detecting circuit for detecting states of fuses in the memory circuit. The comparing circuit of the redundancy control circuit 18 is supplied with the address bits AD l through AD n obtained via the address buffer 16, and produces a disable signal a for disabling the row decoder 13 and an enable signal b for enabling the redundancy row decoder 19 when the input address from the address buffer 16 coincides with the address of the defective memory cell stored in the memory circuit. For this reason, when the input address designates a defective memory cell, one of the redundancy memory cells 15 is accessed instead of the defective memory cell. As will be described later, the memory circuit of the redundancy control circuit 18 comprises a fuse read only memory (ROM). Each address bit in the address of the defective memory cell is described by the state of a pair of fuses of the fuse ROM. The selection circuit 17 generates check signals X and Y responsive to bits AD l and AD n of the input address, and the redundancy control circuit 18 produces a detection signal indicative of the states of each fuse constituting the pair of fuses based on the check signals X and Y. For example, the selection circuit 17 comprises inverters (not shown) having high threshold levels, and produces a high-level check signal X when a voltage applied to the terminal 20 l for the address bit AD l is greater than a predetermined voltage and produces a high-level check signal Y when a voltage applied to the terminal 20 n for the address bit AD n is greater than a predetermined voltage. FIG.2 shows an embodiment of the redundancy control circuit 18. The redundancy control circuit 18 comprises a memory part 25 comprising memories 25₁ through 25 n , a comparing circuit 26 comprising coincidence detecting circuits 26 l through 26 n , and a logic circuit 27 comprising an AND circuit. The memories 25 l through 25 n respectively have a circuit construction shown in FIG.3. The memory comprises a memory circuit and a detecting circuit. The memory circuit comprises a pair of polysilicon fuses F1 and F2, transistors Q3 through Q8, inverters IV1 and IV2, a pad PD for blowing the fuse and terminals 38 and 39 for respectively receiving program signals S and S . The detecting circuit comprises transistors Q1 and Q2, an OR gate OG and terminals 40 and 41 for respectively receiving the check signals X and Y. When programming the memory, the program signals S and S are respectively applied to the terminals 38 and 39. The transistors Q3 and Q4 are depletion N-channel transistors and are turned OFF responsive to the program signal S . As a result, the memory is cut off from a power source voltage Vcc. On the other hand, the transistors Q5 and Q6 are enhancement N-channel transistors and are turned ON responsive to the program signal S. A high voltage is applied to the pad PD so that a large current flows through the fuses F1 and F2 and blows these fuses F1 and F2. In this case, since the transistors Q3 and Q4 are OFF, a power source (not shown) for supplying the power source voltage Vcc will be unaffected by the high voltage applied to the pad PD. When the application of the program signals S and S to the terminals 38 and 39 is then stopped, the transistors Q3 and Q4 are turned ON and the transistors Q5 and Q6 are turned OFF. Hence, the power source voltage Vcc is normally supplied to the memory. In the case where the fuses F1 and F2 are completely blown and no grow back occurs, output signals A and B of the inverters IV1 and IV2 both have a high level, and a high-level signal is produced from the OR gate OG. This high-level signal from the OR gate OG obtained via a terminal 42 indicates that the programming for using the redundancy memory cell in place of the defective memory cell within the memory cell array 11 is completed. In FIGS.1, 2 and 4, terminals corresponding to the terminal 42 shown in FIG.3 are designated by reference numerals 42 l through 42 n . In addition, in the case where either one of the fuses F1 and F2 is unblown or has grown back, the level of a corresponding one of the output signals A and B of the inverters IV1 and IV2 becomes low while the level of the other is high. However, the output signal level of the OR gate OG is also high in this case, and it is indicated that the programming is completed. On the other hand, when neither the fuse F1 nor F2 is blown, the output signals A and B of the inverters IV1 and IV2 both have a low level, and the output signal level of the OR gate OG in this case is low. This low level output of the OR gate OG indicates that no programming is made. When only one of the fuses F1 and F2 is blown, it is possible to detect which one of the two fuses F1 and F2 is unblown by applying appropriate check signals X and Y to the terminals 40 and 41. For example, when a high-level check signal x is applied to the terminal 40 and a low-level check signal Y (= X ) is applied to the terminal 41, it is possible to detect that the fuse F2 is unblown when a low-level signal is obtained from the OR gate OG. Similarly, when a high-level check signal Y is applied to the terminal 41 and a low-level check signal X (= Y ) is applied to the terminal 40, it is possible to detect that the fuse F1 is unblown when a low-level signal is obtained from the OR gate OG. Therefore, it is possible to positively detect which one of the two fuses F1 and F2 is actually unblown by carrying out a simple operation. Returning now to the circuit shown in FIG.2, each of the coincidence detecting circuits 26 l through 26 n detects whether the corresponding bit of the input address from terminals 28 l through 28 n coincides with the output signal of the OR gate OG within the corresponding one of the memories 25 l through 25 n . The coincidence detecting circuits 26 l through 26 n each produce a high-level signal when the two input signals thereof coincide. The logic circuit 27 obtains a logical product of all of the output signals of the coincidence detecting circuits 26 l through 26 n . When the input address coincides with the address of the defective memory cell within the memory cell array 11, all of the output signals of the coincidence detecting circuits 26 l through 26 n have a high level, and the logic circuit 27 produces a high-level signal which is obtained via a terminal 29. For example, this high-level signal is supplied to the redundancy row decoder 19 as the enable signal b, and the enable signal b is inverted and is supplied to the row decoder 13 as the disable signal a. FIG.4 shows another embodiment of the redundancy control circuit 18 shown in FIG.1. In FIG.4, those parts which are the same as those corresponding parts in FIG.2 are designated by the same reference numerals, and a description thereof will be omitted. The address bits AD l through AD n of the input address are respectively applied to the terminals 28 l through 28 n , and inverted address bits AD l through AD n are respectively applied to terminals 58₀ through 58 n . The check signals X and Y are respectively applied to terminals 40 and 41. The redundancy control circuit 18 comprises n circuit parts each constituted by a redundancy circuit selection circuit 51 j , 2-input NOR circuits 52 j and 53 j , an address latch circuit 54 j , the memory 25 j and the coincidence detecting circuit 26 j , and the logic circuit 27, where j=0, 1, ..., n. The address bit AD j from the terminal 28 j is supplied to the redundancy circuit selection circuit 51 j , one input terminal of the NOR circuit 53 j , and the address latch circuit 54 j . The inverted address bit AD j from the terminal 58 j is supplied to one input terminal of the NOR circuit 52 j . An output signal of the redundancy circuit selection circuit 52 j is supplied to the other input terminal of the NOR circuit 52 j and to the other input terminal of the NOR circuit 53 j . Output signals of the NOR circuits 52 j and 53 j are respectively supplied to the terminals of the memory 25 j corresponding to the terminals 40 and 41 shown in FIG.3. The coincidence detecting circuit 26 j detects the coincidence of the output signal of the memory 25 j and an output signal of the address latch circuit 54 j . The address latch circuit 54 j latches the address bit AD j responsive to the check signal X from the terminal 40. For example, a latch circuit is used for the redundancy circuit selection circuit 51 j so as to latch the address bit AD j responsive to the check signal Y from the terminal 41. In the present embodiment, the redundancy circuit selection circuit 51 j produces a high-level signal when the check signal Y has a low level, and latches the address bit AD j responsive to a high level of the check signal Y. The output signal level of the redundancy circuit selection circuit 51 j becomes low only when a high-level address bit AD j is latched therein. Accordingly, it is possible to select one of the memories 25 l through 25 n and check the state of the pair of fuses in each memory. In the embodiments described heretofore, the present invention is applied to the semiconductor memory device having the redundancy configuration. However, the application of the present invention is not limited to the semiconductor memory device. For example, fuses are often used to select one or a plurality of circuit elements such as resistors provided in a semiconductor device. In this case, a selection circuit selects a certain connection of the circuit elements to obtain a desired circuit operation, and a memory circuit stores an address information for controlling the selection circuit to make the certain connection. Moreover, in such a semiconductor device having circuit elements which are to be selectively used, it is conceivable to employ the arrangement previously proposed in the United States Patent No.4,592,025 wherein a pair of fuses is provided for one bit of the address information, and the present invention can be applied similarly to the case of the embodiments described heretofore. Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.

Claims: A semiconductor device comprising first and second power supply terminals (Vcc,GND); fuse circuit means, operatively connected between said first and second power supply terminals (Vcc,GND), having first and second fuses (F1,F2) for storing an information bit by blown and unblown states of the fuses (F1,F2); information output circuit means (OG), operatively connected to said fuse circuit means, for providing an output signal having a first logic level when at least one of the fuses (F1,F2) is blown and an output signal having a second logic level when both the fuses (F1,F2) are unblown; characterized by further comprising detecting circuit means, operatively connected to said fuse circuit means, for detecting which one of the fuses (F1,F2) is unblown, said detecting circuit means having a first transistor (Q1), connected to the first fuse (F1) in parallel, being turned ON in response to a first check signal (X), and a second transistor (Q2), connected to the second fuse (F2) in parallel, being turned ON in response to a second check signal (Y). A semiconductor device as claimed in claim 1, characterized in that said first and second check signals (X,Y)have mutually different logic levels, said information output circuit means producing the output signal having the second logic level to indicate that said second fuse (F2) is unblown when the first check signal (X)is applied to said first transistor (Q1) and producing the output signal having the second logic level to indicate that said first fuse (F1) is unblown when the second check signal (Y) is applied to said second transistor (Q2). A semiconductor device as claimed in claim 1 or 2, characterized in that said information output circuit means comprises an OR circuit (OG) for obtaining a logical sum of the signals obtained via said fuses (F1,F2) when said first and second check signals (XY) are applied to the respective bases of said first and second transistors (Q1,Q2). A semiconductor device as claimed in anyone of claims 1 to 3, characterized by further comprising a memory cell array (11) made up of an array of memory cells (25i,i=1,2,...n), said fuse circuit means storing an address information of defective memory cells (25i) in said memory cell array.

Inventors: AKAOGI, TAKAO, KAWASHIMA, HIROMI
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G11C17
IPC codes: G11C17, G11C29