Electrical circuit utilizing a concentric collector PNP transistor

Abstract: A concentric collector PNP transistor is utilized in electrical circuits to determine when the voltages of different parts of a circuit are very close to each other. The transistor has an emitter zone, an inner collector zone that surrounds the emitter zone and an outer collector zone that surrounds both the emitter zone and the inner collector zone. When the voltage of the emitter is slightly higher than the voltage of the inner collector a signal is developed at the outer collector which is used as a trigger or control signal. An oscillator-voltage doubler circuit and a series pass voltage regulator circuit are disclosed that utilize the concentric collector transistor.

Description: This invention relates to electrical circuits that employ a concentric collector PNP transistor that operates to develop a signal at its outer collector when the voltage at its inner collector approaches the voltage of its emitter. Lateral PNP transistors, that have multiple collectors, are known to those skilled in the art, examples being the devices disclosed in US-A-4,328,509 and US-A-4,153,909. In US-A-4,328,509 a multiple collector PNP transistor is disclosed which has an emitter zone and plurality of collector zones. The collector zones do not bound or surround each other. This patent recognizes that if a first collector zone, located adjacent the emitter zone, is open circuited a second collector zone located adjacent the first collector zone will take on a potential close to the emitter potential. This patent also recognizes that if a given collector is biased negatively it will suck up charge carriers so that the current to another collector is reduced. US-A-4,153,909 discloses a multiple collector PNP transistor in Figure 3 that has inner and outer collectors. A circuit for utilizing this transistor is shown in Figure 8. In Figure 8 the inner collector of the PNP transistor is connected to a gating transistor. When the gating transistor is biased conductive current is collected by the inner collector and the outer collector has no signal current. When the gating transistor is biased nonconductive the potential of the inner collector is allowed to float. This causes the collector-to-base junction of the inner collector to saturate and re-emit signal current carriers which are collected by the outer collector. The present invention differs from US 4,328,509 in that, among other things, the concentric collector PNP transistor that is utilized in the electrical circuits of this invention has an outer collector that completely bounds or surrounds the emitter and the inner collector. This invention differs from US 4,153,909 in that, among other things, the concentric collector PNP transistor of this invention is so connected with electrical circuitry that it is capable of detecting a condition of operation wherein the voltage difference of first and second conductors of a circuit differ by only a small amount. One of the objects of this invention is to use an electrical circuit of the type disclosed in FR-A 23 49 217. This circuit includes a concentric collector PNP transistor being so connected to the electrical circuit that when a first conductor of the electrical circuit that is connected to the inner collector of the PNP transistor, has a voltage that is slightly lower than the voltage of a second conductor of the electrical circuit that is connected to the emitter of the PNP transistor, that is, when the PNP transistor is in saturation - a condition which occurs when the collector is less than 500mv. from the emitter potential a signal is developed at the outer collector of the PNP transistor of a magnitude that is high enough to trigger or actuate other circuitry. Conversely, when the voltage at the inner collector is substantially less than the voltage appearing on the emitter (i.e., when the PNP transistor is not saturated), then no signal appears at the outer collector. An object of this invention is to provide an oscillator-voltage doubler circuit that utilizes a concentric collector PNP transistor for connecting a charged capacitor in series with a voltage source and for developing an output signal at its outer collector when the voltage at its inner collector is only slightly lower than the voltage of its emitter. More specifically, the oscillator-voltage doubler circuit includes a capacitor which can be charged when a semiconductor switch is biased conductive. The emitter of the concentric collector PNP transistor is connected to the positive terminal of a direct voltage source and its inner collector is connected to one side of the capacitor. When the concentric collector PNP transistor is biased conductive the emitter-inner collector circuit of the PNP transistor is utilized to connect the voltage source in series with the voltage of the capacitor to thereby provide a voltage doubling function. When the voltage at the inner collector approaches the voltage of the emitter, a signal is developed at the outer collector of the PNP transistor that is utilized to establish a threshold voltage for a comparator that controls the charging and discharging of the capacitor. The oscillator-voltage doubler circuit may be used to provide a gate bias voltage for a metal oxide semiconductor field effect transistor but its use is not so limited. Another object of this invention is to provide a series pass voltage regulator that utilizes a concentric collector PNP transistor to provide a signal when the input voltage to the voltage regulator decreases to a value that is near the output voltage of the voltage regulator. More specifically, the emitter of the concentric collector PNP transistor is connected to a conductor that has the input voltage applied thereto. The inner collector of the PNP transistor is connected to the output conductor of the voltage regulator. When the input voltage drops to a value that is only slightly higher than the output voltage on the output conductor, a signal is developed at the outer collector of the PNP transistor. This signal may be used to provide a reset signal to a microprocessor based computer that receives its input voltage from the output conductor of the series pass voltage regulator. This invention is now described, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a plan view of a concentric collector PNP transistor ; Figure 2 is a sectional view taken along line 2--2 of Figure 1; Figure 3 illustrates collector voltage-current curves for the concentric collector PNP transistor ; Figure 4 is a schematic circuit diagram of a generator voltage regulator circuit that utilizes an oscillator-voltage doubler circuit made in accordance with this invention; Figures 5A and 5B illustrate voltage waveforms that relate to the circuit illustrated in Figure 4; Figure 6 illustrates voltages that relate to a flip-flop and a comparator that are components of the circuit illustrated in Figure 4; Figure 7 is a schematic circuit diagram of a voltage regulator that utilizes a concentric collector PNP transistor ; Figure 8 illustrates a modification of a part of the circuit illustrated in Figure 7; and Figures 9A and 9B illustrate waveforms that relate to the circuit of Figure 7. Referring now to the drawings, Figures 1 and 2 illustrate the concentric collector PNP transistor of this invention that is used in the circuitry to be described. This PNP transistor has been generally designated by reference numeral 10 and it has a substrate 12 that is formed of P-type semiconductor silicon material. The substrate 12 has a rectangular isolation region 12A formed of P-type material for isolating the PNP transistor 10 from other parts of an integrated circuit that have not been illustrated. The PNP transistor has a region 14 that is formed of N-type epitaxial material. Diffused into the region 14 is a rectangular region C 1 which is formed of P-type material. The rectangular region C 1 forms the outer collector for the PNP transistor 10. A contact pad 16 (Figure 1) formed of metallic material is electrically connected to the outer collector C 1 . The PNP transistor 10 has another diffusion which forms a rectangular region C 2 which defines the inner collector. This inner collector or rectangular region C 2 is formed of P-type material. The inner collector C 2 is connected to a contact pad 18 illustrated in Figure 1. The base of the PNP transistor 10 has been designated as B. This base or base region is formed by a diffusion of N+type material. The base B is connected to a contact pad 20. The emitter of the PNP transistor is designated as E. It is formed by a diffusion of P-type material. The emitter or emitter region E is connected to a contact pad 22. It will be evident, from an inspection of Figure 1, that the outer and inner collectors C 1 and C 2 are rectangular and concentric. It will also be evident that the inner collector C 2 entirely surrounds the emitter region E and that the outer collector C 1 entirely surrounds the inner collector C 2 and the emitter region E. The PNP transistor 10 therefore may be characterized as a lateral concentric collector PNP transistor. The voltage-current characteristics of the PNP transistor 10 is illustrated in Figure 3. In Figure 3 collector current I c in ua is plotted against collector-emitter voltage V ce of the inner collector C 2 in volts. The curve labeled C 1 relates to a plot of I c versus V ce (inner collector volts) for the outer collector C 1 of the PNP transistor 10 and the curve labeled C 2 relates to a plot of I c versus V ce (inner collector volts) for the inner collector C 2 of the PNP transistor 10. It can be seen from Figure 3 that when V ce is reduced to less than 0.5 volts there is a dramatic drop in collector current of the inner collector C 2 and a sharp increase in the collector current of outer collector C 1 . Maximum collector current of outer collector C 1 occurs at a V ce of about 0.2 volts. These changes in collector current of outer and inner collectors C 1 and C 2 are caused by a parasitic action in which the collector current of inner collector C 2 instead of being shunted to ground, as happens with a conventional PNP transistor, is recollected by the outer collector C 1 . As compared to a conventional PNP transistor the outer collector C 1 may be viewed as an extra "P" ring that serves to recollect the collector current that would be shunted to ground by a conventional PNP transistor where the inner collector C 2 would be the collector of such a conventional PNP transistor. The outer collector curve C 1 of Figure 3 shows a nearly proportional recollection of inner collector current and this characteristic can be utilized to trigger or turn on other circuitry. This characteristic can be used as an indicator of a saturated condition of PNP transistor 10. The novel use of this characteristic will be described in connection with the circuits illustrated in Figures 4 and 7. One novel use of the concentric collector PNP transistor 10 that has been described is illustrated in Figure 4. In Figure 4 the PNP transistor 10 forms a component of an oscillator-voltage doubler that is utilized to drive a MOSFET (metal oxide semiconductor field effect transistor) that forms a part of a generator voltage regulator. The PNP transistor 10 is shown schematically in Figure 4 where its inner collector is identified as C 2 and its outer collector as C 1 . In Figure 4 the emitter of PNP transistor 10 is identified as E and its base as B. The circuit of Figure 4 illustrates a voltage regulating circuit for a motor vehicle electrical circuit which will be assumed to be a 12 volt system. In Figure 4 the reference numeral 24 designates a direct voltage generator that has a rotor that is driven by the engine of the vehicle. The direct voltage generator 24 is shown feeding a positive output terminal 24A and a negative output terminal 24B that is connected to ground. The direct voltage generator 24 is a three-phase alternating current generator having a three-phase stator winding (not illustrated) which is connected to a three-phase full-wave bridge rectifier (not illustrated) that has direct voltage output terminals connected to positive and negative output terminals 24A and 24B. The alternating current generator has a field winding 26. The positive output terminal 24A is connected to a conductor 28. A storage battery 30 is connected between conductor 28 and ground. Other motor vehicle loads are connected between conductor 28 and ground in a well known manner. The field current of field winding 26 is controlled by an N-channel enhancement mode type of a MOSFET which is identified by reference numeral 32. The MOSFET 32 has a drain D that is connected to conductor 28 and a source S that is connected to one side of field winding 26. The opposite side of field winding 26 is grounded. The gate G of MOSFET 32 is connected to a junction or node 33 via a resistor 34 and a conductor 36. The MOSFET 32 is biased conductive and nonconductive between its drain D and source S, depending upon the magnitude of the direct voltage appearing between conductor 28 and ground. In order to accomplish this a voltage sensing circuit is connected between conductor 28 and ground to sense the voltage across storage battery 30. This voltage sensing circuit comprises voltage divider resistors 38 and 40 having a junction 42. The voltage at junction 42 is a divided down representation of the voltage across storage battery 30 and it is compared with a reference voltage provided by a voltage divider 44. The voltage divider 44 is energized from a terminal or junction 65 that has a constant voltage applied thereto by a circuit that is described hereinafter. Junction 42 is connected to a voltage comparator 46 by conductor 48. Junction 43 of voltage divider 44 is connected to voltage comparator 46 by conductor 49. A substantially constant reference or set point voltage is applied to conductor 49 that is compared to the voltage at junction 42. The output of voltage comparator 46 is applied to the base of an NPN transistor 50 via conductor 52. The emitter of NPN transistor 50 is grounded and its collector is connected to junction 33. When the output of voltage comparator 46 is high, NPN transistor 50 is biased conductive to connect junction 33 to ground which lowers the voltage applied to the gate G of MOSFET 32 to thereby cause MOSFET 32 to be biased nonconductive. When the output voltage of voltage comparator 46 is low, NPN transistor 50 is biased nonconductive. This will allow the voltage at junction 33, which is developed by the oscillator-voltage doubler of this invention, to bias MOSFET 32 conductive. Assuming a 12 volt system, the voltage regulator that has been described operates to maintain a desired regulated voltage of for example, 13.5 volts between conductor 28 and ground. Thus, as the voltage on conductor 28 goes above 13.5 volts MOSFET 32 is biased nonconductive to cut off field current to field winding 26 and when the output voltage of direct voltage generator 24 now drops to a value such that the voltage at conductor 28 is below 13.5 volts, MOSFET 32 is biased conductive to supply field current to field winding 26. The MOSFET 32 therefore switches on and off to provide a field current that will cause the voltage generated by direct voltage generator 24 to be maintained at a desired regulated value. The conductor 28 is connected to a conductor 54. The conductor 54 is connected to a terminal or junction 56. The junction 56 is connected to a junction 58 through a resistor 60 of 200 ohm rating. Junctions 56, 58 and resistor 60 define means connecting the emitter E to the conductor 28. The conductor 54 is connected to one side of a resistor 55 of 50 ohm rating. The opposite side of resistor 55 is connected with a terminal 57. A capacitor 59 is connected between terminal 57 and ground. The terminal 57 is connected to a junction 61. The junction 61 feeds a conventional voltage regulating circuit 63. The output of voltage regulating circuit 63 is applied to the junction 65. Assuming a 12 volt system, the circuit 63 provides a constant voltage of 8 volts at junction 65. This junction 65 is connected to other junctions identified by reference numeral 65 by conductors that have not been illustrated. The junction 58 is connected to the emitter of PNP transistor 10 and to a conductor 62. The conductor 62 is connected to one side of resistor 64 of 10K ohm. The opposite side of resistor 64 is connected to a junction 66. A resistor 68 of 41K ohm is connected between junction 66 and the collector of an NPN transistor Q 2 . The emitter of transistor Q 2 is grounded and its base is connected to a junction 70 and a conductor 72. The base of the PNP transistor 10 is connected to junction 66. Junction 66, resistor 68 and NPN transistor Q 2 define means connecting the base B to the storage battery 30. A circuit is connected between conductor 62 and ground that includes in a series connection a diode 74, terminal or junction CAPH, a resistor 76 of 114K ohm, a junction 78 and a resistor 80 of 57K ohm. A capacitor 82 of 0.1 µf is connected between junction CAPH and junction or terminal CAPL. The terminal CAPH is connected to junction 33 by a resistor 85. The junction CAPL is connected to the inner collector C 2 of PNP transistor 10 by a conductor 84. The conductor 84 is connected to a conductor 86 which in turn is connected to a junction 90. A resistor 92 of 150 ohm is connected between junction 90 and the collector of an NPN transistor Q 4 . The emitter of NPN transistor Q 4 is grounded. The base of NPN transistor Q 4 is connected to a junction 94. The junction 94 is connected to the collector of an NPN transistor Q 3 and to the junction 65. The junction 65 corresponds to the junction 65 connected to voltage regulating circuit 63. The emitter of NPN transistor Q 3 is grounded and its base is connected to junction 70. The circuit of Figure 4 has a flip-flop 96 that has a set terminal ST, a reset terminal R and an output terminal Q. The reset terminal R of flip-flop 96 is connected to the outer collector C 1 of PNP transistor 10 by a conductor 95. The set terminal ST of flip-flop 96 is connected to the collector of a PNP transistor Q 6 . The base of PNP transistor Q 6 is connected to junction 90. A voltage of about 1.75 to 2.3 volts is applied to the emitter of PNP transistor Q 6 . This voltage is developed by a voltage reference circuit 98 that has an output connected to the emitter of PNP transistor Q 6 and an input connected to conductor 54 via a conductor 100. The circuit of Figure 4 has a voltage comparator 104 the output of which is connected to conductor 72. The positive input terminal of voltage comparator 104 is connected to junction 78 by a conductors 106 and 107 and a junction or conductive pad 109. The negative terminal of voltage comparator 104 is connected to a junction 108. A resistive voltage divider is connected between junction 61 and ground that includes, in a series connection, a resistor 110 of 18.7K ohms, junction 108, a resistor 112 of 8K ohms, a junction 114, a resistor 116 of 2.88K ohms and a resistor 118 of 10K ohms. The junction 114 is connected to the collector of an NPN transistor Q 5 . The emitter of NPN transistor Q 5 is grounded and its base is connected to the output terminal Q of flip-flop 96. Conductor 95, flip-flop 96 and NPN transistor Q 5 define means connected to the outer collector C 1 for providing a signal. The operation of the oscillator-voltage doubler of this invention will now be described. This oscillator voltage doubler does not include and does not require the circuit elements that provide the generator voltage regulator such as voltage comparator 46 and NPN transistor 50. This oscillator-voltage doubler is fabricated as an integrated circuit that has the previously described junctions or terminals, 56, CAPL, CAPH, 57 and 109. The oscillator-voltage doubler provides a voltage at junction CAPH that is high enough to bias MOSFET 32 conductive. In this regard, it is pointed out that junction CAPH is connected to the gate G of MOSFET 32 via resistor 85, junction 33, conductor 36 and resistor 34. As will be described, the oscillator-voltage doubler develops a voltage at junction CAPH that is substantially twice or double the voltage on conductor 28. This voltage magnitude (double source voltage) is needed in order to assure that there is sufficient gate voltage for MOSFET 32 to bias it conductive and maintain it biased conductive. Thus, since MOSFET 32 is connected in a so-called high side drive configuration (load connected between source and ground) the voltage that is applied to its gate G must be higher than the voltage that is applied to its drain D in order to bias and maintain MOSFET 32 biased conductive and the oscillator-voltage doubler of this invention performs this function. The operation of the oscillator-voltage doubler of this invention will now be described in detail with the aid of the voltage waveforms illustrated in Figures 5A and 5B and Figure 6. Figure 5A illustrates the voltage at junction CAPH and Figure 5B illustrates the voltage at junction CAPL as a function of time. The voltage waveforms of Figure 6 relate to flip-flop 96 and the output of voltage comparator 104. At time T 0 NPN transistor Q 4 is biased conductive. The capacitor 82 is now charged by the voltage on conductor 28 through a circuit that can be traced from conductor 28 to junction 58, through diode 74 to junction CAPH, through capacitor 82 and conductors 84 and 86 to junction 90 and then through resistor 92 and conductive NPN transistor Q 4 . As previously mentioned, the waveform of Figure 5A illustrates the voltage on junction CAPH and Figure 5B illustrates the voltage on junction CAPL. The voltage V D , shown by legends in Figures 5A and 5B, represents the voltage at junction 58. The voltage level V D -V SAT shown in Figure 5A represents the voltage at junction 58 less the saturation voltage drop between the emitter E and inner collector C 2 of PNP transistor 10. As capacitor 82 charges between times T 0 and T 1 the voltage at junction CAPH increases toward a direct voltage level V LT along line or curve 120. At the same time the voltage at junction CAPL decreases along line or curve 120A (Figure 2B). At this time the output of voltage comparator 104 is low and consequently NPN transistors Q 2 and Q 3 are biased nonconductive. Since NPN transistor Q 2 is biased nonconductive, PNP transistor 10 is biased nonconductive and since NPN transistor Q 3 is biased nonconductive NPN transistor Q 4 is biased conductive. When the voltage at junction CAPL and 35 hence at junction 90 drops to a predetermined value (about one V be below the emitter voltage of PNP transistor Q 6 ) PNP transistor Q 6 is biased conductive. When PNP transistor Q 6 is biased conductive a set pulse 120B (Figure 6) for flip-flop 96 is developed which causes a pulse 120C to be developed at the output terminal Q of flip-flop 96. When pulse 120C is developed it biases the NPN transistor Q 5 conductive. When NPN transistor Q 5 is biased conductive it connects junction 114 to ground and hence the voltage at junction 108 is determined by a voltage divider comprised of series connected resistors 110 and 112. The voltage comparator 104 compares the voltage at junction 108 with the voltage at junction 78 which is a divided down representation of the voltage at junction CAPH. The circuit is arranged such that when the voltage at junction CAPH reaches the level V LT (Figure 5A) the output of voltage comparator 104 switches from a low level to a high level. The pulse 120C will always occur prior to the time that the voltage shown by line or curve 120 (Figure 5A) reaches the level V LT . When the line 120 (Figure 5A) does reach the V LT level at time T 1 the output of voltage comparator 104 goes high to bias NPN transistors Q 2 and Q 3 conductive. The conduction of NPN transistor Q 3 will cause NPN transistor Q 4 to be biased nonconductive and the conduction of NPN transistor Q 2 causes PNP transistor 10 to be biased conductive. When PNP transistor 10 is biased conductive and Q 4 is biased nonconductive the voltage at junction CAPH increases abruptly along line 122 (Figure 5A) to a level that is equal to V LT + V D where the voltage V D is the voltage at junction 58 and where the saturation voltage drop of PNP transistor 10 between its emitter E and inner collector C 2 has been neglected. The reason for this abrupt increase is that the positive voltage at junction 58 has now been added in series with the voltage across capacitor 82. In this regard it should be noted that there is only a small voltage drop across resistor 60 so that voltage V D is near the voltage of conductor 28. The addition of voltage V D to the voltage across the capacitor 82 takes place because at this time PNP transistor 10 is conducting between its emitter E and its inner collector C 2 . The voltage level V LT + V D is high enough to bias MOSFET 32 to a conductive condition and maintain it biased to this condition. The voltage level V LT + V D is about double or twice the voltage V D and hence the circuit operates as a voltage doubler. At time T 1 when NPN transistor Q 4 is biased nonconductive the abrupt voltage transition shown by line 122 will occur and the capacitor 82 will then start to discharge through resistors 76 and 80. At the end of voltage transition shown by line 122 the voltage at junction CAPH is V LT + V D and PNP transistor 10 is biased conductive. At this time the voltage at the inner collector C 2 of PNP transistor 10 has risen to the highest potential possible, its saturated state, which is within 0.2 volts of voltage V D . This voltage is applied to the most negative side of capacitor 82, which has been previously charged to potential V LT and thus is added to it based on the principal of charge conservation. The sum of these voltages (V LT + V D ) appear at junction CAPH and is well in excess of voltage level V UT . With the inner collector C 2 at the voltage that has just been described the outer collector C 1 begins to source current and as a result, current is supplied to the reset terminal R of flip-flop 96 via conductor 95 to cause the flip-flop to reset. This reset function is illustrated as voltage transistion 126 in Figure 6. The reason that outer collector C 1 sources current when the voltage of the inner collector C 2 is raised to the voltage that has been described is as previously explained. That is, the inner collector C 2 ceases to be capable of collecting the current injected by the emitter because of its high bias voltage. The outer collector C 1 detects this saturated condition and assumes the role of collecting the excess current which is then available to provide the reset signal. This role reversal action (as a function of voltage) is shown in Figure 3. Now as the capacitor 82 discharges the voltage V LT +V D (Figure 5A) decreases along line 124 toward a voltage level V UT illustrated in Figure 5A. The voltage level V UT may be about 10% less than the voltage V LT + V D . When voltage transition 126 to reset flip-flop 96 occurs, the output terminal Q of flip-flop 96 goes low and accordingly NPN transistor Q 5 is biased nonconductive. When NPN transistor Q 5 is biased nonconductive the voltage at junction 108 increases as compared to the voltage at junction 108 when NPN transistor Q 5 is conductive. Thus, when NPN transistor Q 5 is biased nonconductive, the voltage at junction 108 is determined by a voltage divider that is comprised of series connected resistors 110, 112, 116 and 118. When NPN transistor Q 5 is biased nonconductive, the voltage at junction 108 will exceed the voltage at junction 78 and accordingly the output of voltage comparator 104 will go high. The resistors 110, 112, 116 and 118 form a switchable voltage divider that has a voltage divider ratio that depends upon whether NPN transistor Q 5 is biased conductive or nonconductive. From the foregoing it will be apparent that at the end of voltage transition shown by line 122 NPN transistor Q 5 has been biased nonconductive and the output of voltage comparator 104 has switched from a low state to a high state. When the output of voltage comparator 104 goes high PNP transistor 10 is biased conductive and NPN transistor Q 4 nonconductive. Accordingly, the capacitor 82 no longer charges and it begins to discharge as has been described. As capacitor 82 discharges the voltage at junction CAPH decreases along line 124 of Figure 5A. When this voltage decreases below the level V UT at time T 2 the output of voltage comparator 104 goes low. In regard to the voltage level V UT it should be noted that a divided down representation of the voltage at junction CAPH appears at junction 78. This voltage is compared with the voltage at junction 108 and the voltage at junction 108 is of such a magnitude that when the voltage at junction CAPH drops below V UT the output of voltage comparator 104 goes low. When the output of voltage comparator 104 goes low at time T2 PNP transistor 10 is biased nonconductive and NPN transistor Q 4 is biased conductive. The voltage at junction CAPH now experiences an abrupt negative transition 128 (Figure 5A) due to the fact that PNP transistor 10 has been biased nonconductive while NPN transistor Q 4 is biased conductive. With NPN transistor Q 4 biased conductive, PNP transistor Q 6 becomes biased conductive when the negative transition 128 drops below approximately one V be of the voltage appearing at the emitter of PNP transistor Q 6 which biases PNP transistor Q 6 conductive to cause the output terminal Q of flip-flop 96 to go high thereby biasing NPN transistor Q 5 conductive. With NPN transistor Q 5 biased conductive, the voltage divider ratio of the resistors that determine the voltage at junction 108 is changed so that the voltage at junction 108 decreases as compared to the condition where NPN transistor Q 5 is nonconductive. Since NPN transistor Q 4 is now conductive capacitor 82 is charged between time periods T 2 and T 3 . The voltage at junction CAPH now increases along line 130 (Figure 5A) and when this voltage attains level V LT the output of voltage comparator 104 goes low. This causes PNP transistor 10 to be biased conductive with the result that the voltage at CAPH makes another abrupt positive transition 132. The circuit now continues to operate through consecutive cycles in a manner that has been described. The oscillator-voltage doubler is a free running oscillator and a voltage doubler. Thus, the frequency of the voltage waveform shown in Figure 5A is constant and is determined by the values of capacitor 82 and resistors 60, 76 and 80. The time periods that correspond to time periods T 1 to T 3 and T 3 to T 5 are substantially equal. The circuit also operates as a voltage doubler in a manner that has been described. Thus, the input voltage is doubled at, for example at times T 1 and T 3 . Moreover, during time periods such as T 1 to T 2 and T 3 to T 4 the voltage at junction CAPH remains high enough to maintain MOSFET 32 biased conductive and even when this voltage decreases slightly to the level V UT it still is of a magnitude that is nearly double the input voltage. As previously mentioned, at time T 1 the voltage at junction CAPH makes the abrupt transition shown by line 122 and rises to the level V LT + V D . It should be noted, however, that the next desired event (at time T 2 ) is when the CAPH voltage decays down to the level V UT . It is important to charge the capacitor 82 to a level above V UT such that it can decay down to this level to trigger the next event at time T 2 . It is also important that the circuit not trigger at voltage level V UT during the short time when the capacitor voltage is being doubled and is initially increasing or crossing through voltage level V UT (voltage transition shown by line 122). False triggering at this point (voltage transition shown by line 122) would either cause a circuit malfunction or an undesirable system glitch. This means that the comparator threshold (voltage at junction 108) must remain at a level that is a divided down representation of V LT until the CAPH voltage level is well above V UT . The PNP transistor 10 of this invention reliably performs this function by sourcing current at the outer collector C 1 when the voltage at its inner collector C 2 rises to a voltage that is within 0.2 volts of the maximum capacitor charging voltage V D . By utilizing the PNP transistor 10 in a manner that has been described, there is no need to provide a voltage comparator in addition to voltage comparator 104 that would sense a voltage level somewhere between V UT and V LT + V D and reset a flip-flop like flip-flop 96 to change the voltage divider ratio that determines the voltage at junction 108. By eliminating the need for an additional comparator, silicon area to fabricate an integrated circuit is reduced and circuit sensitivities and variations associated with an additional comparator are eliminated. In the oscillator-voltage doubler that has been described, the PNP transistor 10 performs a dual function. First of all, it sources a current when it is biased conductive, or putting it another way, it dynamically connects the positive voltage on conductor 28 to junction CAPL. This means that the emitter E and the inner collector C 2 form a conductive circuit that connects the direct voltage between conductor 28 and ground in series with the voltage across capacitor 82. These added voltages supply gate-source current to MOSFET 32. The other function performed by PNP transistor 10 is that it operates as a voltage comparator. Thus, PNP transistor 10 compares the voltage on its emitter E with the voltage on its inner collector C 2 and when the voltage on inner collector C 2 is about 0.2 volts less than the voltage on emitter E an output signal or current is developed at its outer collector C 1 . Referring now to Figure 7, another use for the concentric collector PNP transistor 10 will be described. In Figure 7 the reference numeral 140 identifies a source of direct input voltage which has been illustrated as a battery. The source 140 may be a motor vehicle battery that is supplied with charging current by a battery charging generator in a manner illustrated in Figure 1. The source 140 feeds a computer 142 which is microprocessor-based through a series pass voltage regulator that includes PNP transistor 144. The computer 142 may be an engine control computer. The emitter of PNP transistor 144 is connected to the positive side of source 140 by a conductor 146. The collector of PNP transistor 144 is connected to output conductor 148 which feeds the computer 142. The voltage regulator has a voltage reference developing circuit 150 connected between conductor 146 and ground. The voltage reference developing circuit 150 develops a constant reference voltage on a conductor 152 which is applied as an input to a voltage error amplifier 154. The voltage error amplifier 154 has another input connected to conductor 148 via a conductor 156. The voltage error amplifier 154 has an output on line 158 which controls the conduction of NPN transistors 160 and 162. The collectors of these NPN transistors 160,162 are connected to the base of PNP transistor 144 by a conductor 163. The voltage regulator operates to maintain a substantially constant regulated output voltage on output conductor 148 that is lower than the input voltage applied to conductor 146. The voltage error amplifier 154 compares the reference voltage on conductor 152 with the output voltage on output conductor 148. When the voltage on output conductor 148 is higher than the desired regulated value the conduction of NPN transistors 160 and 162 is reduced which causes the emitter-collector current of PNP transistor 144 to be reduced. When the voltage on output conductor 148 goes below the desired regulated value the conduction of NPN transistors 160 and 162 is increased which causes an increase in emitter-collector current of PNP transistor 144. By way of example, in a 12 volt system where the input voltage is about 12 volts the regulated output voltage on output conductor 148 may be, under normal conditions, maintained at about 5 volts. Figure 9A illustrates the input voltage as line 164 on conductor 146 and the regulated output voltage as line 166 that appears on output conductor 148 plotted against time. The dotted line in Figure 9A represents a microprocessor malfunction voltage level. If the voltage on output conductor 148 drops below the malfunction voltage level the computer 142 will malfunction. As previously described, the line 164 in Figure 9A depicts the input voltage on conductor 146. Straight line portion 164A of line 164 illustrates a normal input voltage and portion 164B illustrates the input voltage decreasing to zero. The regulated output voltage on output conductor 148 is illustrated as line 166 having a straight portion 166A and a portion 166B that depicts a decreasing regulated output voltage. Assume now that the input voltage starts to decrease along portion 164B. At time T 1 the input voltage which is decreasing along portion 164B is just slightly higher than the regulated output voltage represented by straight portion 166A. This condition is indicative of an impending low voltage condition and must be detected in order to provide a reset signal for the computer 142. In order to accomplish this the circuit of Figure 7 utilizes the concentric collector PNP transistor 10 which has been described in connection with Figures 1-3. In Figure 7 the emitter E of PNP transistor 10 is connected to conductor 146. The base B of PNP transistor 10 is connected to the collectors of NPN transistors 160 and 162 and to the base of PNP transistor 144. The inner collector C 2 of PNP transistor 10 is connected to output conductor 148 by a conductor 168. The outer collector C 1 of PNP transistor 10 is connected to the base of an NPN transistor 170 by a conductor 171. The emitter of NPN transistor 170 is grounded and its collector is connected to computer 142 by conductor 172. The conductor 172 is connected to a source of positive voltage by a resistor 173. Since the emitter E and inner collector C 2 of PNP transistor 10 are connected between conductor 146 and output conductor 148 and since the base B of PNP transistor 10 is connected to the collectors of NPN transistors 160 and 162 the conduction of PNP transistor 10 between its emitter E and inner collector C 2 will be controlled by the voltage error amplifier 154 in the same manner that it controls the conduction of PNP transistor 144. Most of the load current for computer 142 will be supplied through PNP transistor 144. Some load current will be supplied through the emitter E to inner collector C 2 current path of PNP transistor 10. Referring again to Figure 9A, let it be assumed that the input voltage on conductor 146 has decreased along portion 164B such that at time T 1 it is only slightly higher than the regulated output voltage depicted by straight portion 166A. During this condition of operation the voltage on the inner collector C 2 of PNP transistor 10 is close to the voltage of the emitter E of PNP transistor 10 and because of this an output voltage is developed at the outer collector C 1 of PNP transistor 10. The output voltage of the outer collector C 1 of PNP transistor 10 is depicted in Figure 9B. At time T 1 this output voltage makes a positive transition 174 due to the fact that the input voltage is close to the output voltage. The positive transistion 174 and attained voltage level 175 will cause the NPN transistor 170 to be biased conductive which applies a low level reset signal to computer 142 via conductor 172. The time T 2 in Figure 9A is indicative of a point in time where the input voltage will eventually drop below the microprocessor malfunction voltage level. The minimum voltage (voltage between emitter E and inner collector C 2 of PNP transistor 10) at which a reset signal is produced at outer collector C 1 may be increased by adding one or more diodes D 1 -D N in series with the inner collector C 2 , as illustrated in the modification of Figure 8. Because of the additional diode voltage drop or drops the PNP transistor 10 will saturate at a correspondingly higher input voltage. In this way the time T 2 -T 1 may be increased, thus giving the computer 142 additional time to perform its final tasks before power down. At the expense of some reiteration it will be appreciated that the circuit of Figure 7 provides a reset signal on conductor 172 when a low input voltage is impending. By producing this reset signal before the input voltage drops below the microprocessor malfunction voltage level the computer 142 has enough time to perform its final "housekeeping" tasks before the input voltage drops below the malfunction level. These so-called housekeeping tasks include storing vital parameters in non-volatile memory, issuing default commands, activating system back-up circuits, etc.

Claims: An oscillator-voltage doubler comprising, a source (30) of direct voltage having positive and negative terminals, a concentric collector PNP transistor (10) having an emitter (E), an inner collector (C 2 ) located adjacent the emitter and an outer collector (C 1 ) located outwardly of the inner collector, a capacitor (82), a semiconductor switch (Q 4 ) connected in series with the capacitor and in series with the source of direct voltage, the capacitor being charged from the source when the semiconductor switch is biased conductive and being allowed to discharge when the semiconductor switch is biased nonconductive, means (56,58,60) connecting the emitter of the concentric collector PNP transistor to the positive terminal of the source, the capacitor being connected between the inner collector of the concentric collector PNP transistor and a junction (CAPH), threshold means (104,Q 2 ,Q 3 ) responsive to the voltage at the junction for biasing the concentric collector PNP transistor conductive and the semiconductor switch nonconductive when the voltage of the junction attains a first predetermined magnitude (V LT ) due to capacitor charging, the emitter-inner collector circuit of the concentric collector PNP transistor when biased conductive connecting the voltage of the source and the voltage of the capacitor in series whereby the voltage at the junction abruptly increases to a second predetermined magnitude (V LT and V D ) that is a function of the sum of the voltage of the source and the voltage of the capacitor, the concentric collector PNP transistor being operative when the voltage at its inner collector is slightly below the voltage of its emitter to develop a signal at the outer collector of the concentric collector PNP transistor, responsive means (96,110-118) responsive to the development of the signal for developing a threshold voltage that corresponds to a third voltage magnitude (V UT ) at the junction that is higher than the first predetermined magnitude and lower than the second predetermined magnitude, the threshold means (104,Q 2 ,Q 3 ) being responsive to the threshold voltage and the voltage at the junction for biasing the concentric collector PNP transistor nonconductive and the semiconductor switch conductive when the voltage at the junction decreases to the third predetermined magnitude during discharge of the capacitor. An oscillator-voltage doubler as claimed in Claim 1, characterised in that the responsive means includes a voltage divider (110-118) and the threshold means includes a voltage comparator (104). An oscillator-voltage doubler as claimed in Claim 2 comprising a second voltage divider (76,80) connected to the junction (CAPH) and having a second junction (78) the voltage of which is a divided down representation of the voltage at the junction, the voltage comparator (104) being responsive to the voltage at the second junction. An oscillator-voltage doubler as claimed in Claim 2 or Claim 3, wherein the voltage divider (110-118) of the responsive means is switchable between at least two voltage divider ratios responsive to the development of the signal for developing the threshold voltage. A voltage regulator comprising, a source (140) of direct voltage having positive and negative terminals, an input conductor (146) connected to the positive terminal, an output conductor (148) adapted to be connected to an electrical load, control means (150,154) connected between the input conductor and the output conductor and responsive to the voltage at the output conductor for maintaining the voltage at the output conductor substantially constant, a concentric collector PNP transistor (10) having an emitter (E), an inner collector (C 2 ) located adjacent the emitter and an outer collector (C 1 ) located outwardly of the inner collector, the concentric collector PNP transistor operative to develop an output signal at its outer collector when the voltage of its emitter is slightly higher by a first predetermined magnitude than the voltage of its inner collector, the emitter being connected to the input conductor, the inner collector being connected to the output conductor, and means (160,162) for biasing the concentric collector PNP transistor conductive whereby when the concentric collector PNP transistor is biased conductive and the input voltage applied to the input conductor drops to a value that is higher than the voltage on the output conductor by the first predetermined magnitude a signal is developed at the outer collector. A voltage regulator as claimed in Claim 5, wherein the control means (150,154) maintains the voltage at the output conductor (148) at a magnitude that is lower than the voltage of the source (140) by a second predetermined magnitude which is greater than the first predetermined magnitude. A voltage regulator as claimed in Claim 6, including a second PNP transistor (144) having its emitter and collector connected between the input conductor (146) and the output conductor (148), the control means (150,154) being connected to the base of the second PNP transistor and responsive to the voltage at the output conductor for controlling the conduction of the second PNP transistor, and to the base of the concentric collector PNP transistor.

Inventors: KEARNEY MARK B, SHREVE JOHN R, KEARNEY, MARK B., SHREVE, JOHN R.
Applicants: GEN MOTORS CORP, GENERAL MOTORS CORPORATION
Application year: 1987
Main classification: H03K17
IPC codes: G05F1, H03K17, H01L29