WRITE COMPENSATOR FOR MAGNETIC DISK APPARATUS

Abstract: A write compensator for a magnetic disk apparatus includes a flip-flop (23) for latching write compensation information using not a recording data format conversion reference clock but converted recording data. The flip-flop (23) latches the write compensation information until the next recording data is input. The recording data is write-compensated on the basis of the latched write compensation information.

Description: The present invention relates to a write com­ pensator for a magnetic recording/reproducing apparatus for performing high-density recording. In a magnetic disk apparatus for performing high-density recording, a peak shift occurs in a data pulse due to the influence of adjacent bits when data is read out from a disk. This decreases time margins for data and clock windows. When the margins are excessively decreased, an error rate is reduced. Figs. lA through lE show a case wherein recording data externally transferred in the nonreturn-to-zero (NRZ) format for high-density recording is converted into recording data in the modified frequency modulation (MFM) format, and the converted data is written in a recording medium. Fig. lA shows a data transfer reference clock, and Fig. lB shows NRZ recording data. The NRZ recording data shown in Fig. lB is transferred in synchronism with the reference clock shown in Fig. lA. The NRZ recording data is converted into MFM recording data shown in Fig. lE in accordance with MFM conversion rules in the magnetic disk apparatus in response to clock and data pulses shown in Figs. lC and lD. The converted data is written in the magnetic recording medium. In this case, peak shifts occur in the data patterns shown in Figs. 2A through 2D. As shown in Figs. 3A through 3P, peak shift directions are changed in accordance with different data pulse trains, as indicated by arrows. For example, referring to Fig. 3B, clock pulse C2 repulses clock and data pulses Cl and Dl. In this case, clock pulse C2 is closer to clock pulse Cl than to data pulse Dl. Therefore, clock pulse C2 repulses clock pulse Cl and is shifted in a direction of an arrow. Referring to Fig. 3D, data pulse D2 is closer to data pulse D3 than to clock pulse C3. Therefore, data pulse D2 repulses data pulse D3 and is shifted in a direction of an arrow. Peak shifts can be predicted in the data write mode in accordance with data pulse patterns. Data patterns subjected to peak shifts are summarized as follows. When data pulse patterns are "000l" and "ll0" shown in Fig. 4, late peak shifts occur. However, if data pulse patterns are "0ll" and "l000", early peak shifts occur, as shown in Fig. 4. Therefore, when recording data have patterns "0ll" and "l000", respectively, the data are shifted in directions of arrows (right direction) in Figs. 2A and 2B, i.e., in directions opposite to the read direction. However, when recording data have patterns "ll0" and "000l", repectively, data are shifted in directions of arrows (left direction) in Figs. 2C and 2D, thereby achieving write compensation. Write compensation is conventionally performed by a write compensator shown in Fig. 5. Shift register ll stores externally transferred NRZ recording data Sl in synchronism with reference clock signal CSl and outputs it to decoder l3. Decoder l3 has a function for converting NRZ recording data Sl into MFM recording data S2 and a func­ tion for producing write compensation information by decoding a pattern of data S2. More specifically, NRZ recording data Sl is converted into MFM recording data S2 in response to reference clock signals CSl and CS2. The pattern of data S2 is decoded to generate signal Sl3a for compensation in an "early: direction (i.e., a direction in which a write timing advances), non-­ compensation signal l3b, or signal l3c for compensation in a "late" direction (i.e., a direction in which a write timing is delayed). Signal l3a, l3b, or l3c is output to NAND gate l5. Delay circuit l7 delays reference clock signal CS2 by delay times D0, Dl, and D2 to obtain signals Sl7a, Sl7b, and Sl7c. Signals Sl7a, Sl7b, and Sl7c are input to NAND gate l5. Signals Sl3a, Sl3b, and Sl3c from decoder l3 are logically NANDed by NAND gate l5 with signals Sl7a, Sl7b, and Sl7c from delay circuit l7. Output signals Sl5a, Sl5b, and Sl5c from NAND gate l5 are input to NAND gate l9. Signals Sl5a, Sl5b, and Sl5c are logically NANDed by NAND gate l9, and NAND gate l9 outputs write-­ compensated MFM recording data Sl9. The operation of the write compensator having the arrangement described above will be described with reference to timing charts of Figs. 6A through 6G. Externally transferred NRZ recording data Sl (Fig. 6C) is input to shift register ll at the trailing edge of reference clock signal CSl (Fig. 6B). In this case, shift register ll comprises a 4-bit shift register. Recording data Sl is shifted in response to every clock CSl. When recording data Sl is stored in shift register ll, data Sl is output to decoder l3. Decoder l3 decodes recording data Sl (Fig. 6C) from register ll in response to reference clock signals CSl and CS2 and generates MFM recording data S2 (Fig. 6D). Two reference clock signals CSl and CS2 are used to assure accurate synchro­ nization timings. In this case, a sync signal required in write compensation is only signal CSl, and signal CSl must be a signal having an accurate waveform. For this reason, signal CS2 having a frequency twice that of signal CSl is produced and is frequency-divided to generate signal CSl having an accurate waveform. Decoder l3 decodes the pattern of converted record­ ing data S2 to determine necessity of write compensation and generates write compensation information as needed. Compensation information signal Sl3a (Fig. 6E) for compensating recording data S2 in the early direction, noncompensation information signal Sl3b and compensation information signal Sl3c (Fig. 6F) for compensating data S2 in the late direction are output from decoder l3 to NAND gate l5. Since the pattern of recording data Sl is "000l", as shown in Fig. 6C, pulse 35 in recording data S2 is delayed, as shown in Fig. 6D. Signal Sl3a for compensating the write timing in the early direction is output between trailing edges 3la and 3lb of reference clock signal CSl. As shown in Fig. 6D, pulse 37 in recording data S2 is advanced, as shown in Fig. 6D. Therefore, signal Sl3c for compensating the write timing in the late direction is output between trailing edges 33a and 33b of reference clock signal CSl. Noncompensation information signal S3b (not shown) is output for pulses not subjected to compensation between the current and next trailing edges of reference clock signal CSl. At the same time, delayed signals Sl7a, Sl7b, and Sl7c obtained by delaying reference clock signal CS2 by delay times D0, Dl, and D2 are output from delay circuit l7 to NAND gate l5. Signals Sl3a, Sl3b, and Sl3c from decoder l3 and signals Sl7a, Sl7b, and Sl7c from delay circuit l7 are logically NANDed by NAND gate l5, and output signals Sl5a, Sl5b, and Sl5c therefrom are output to NAND gate l9. Signals Sl5a, Sl5b, and Sl5c from NAND gate l5 are logically NANDed by NAND gate l9. Write-compensated MFM recording data Sl9 is output from NAND gate l9. Fig. 6G shows write-compensated MFM recording data. No shift occurs in MFM recording data 4l in Fig. 6D. Delay time Dl is assigned to pulse 4l as indicated by pulse 43 in Fig. 6G. However, since pulse 35 in Fig. 6D is shifted in the late direction, delay time D0 shorter than delay time Dl is given to pulse 35 to compensate for the time (Dl - D0) in the early direction (direction indicated by arrow 5l), as indicated by pulse 45 in Fig. 6G. Pulse 37 is shifted in the early direction, as shown in Fig. 6D. Therefore, delay time D2 longer than delay time Dl is given to pulse 37 to compensate for (D2 - Dl) in the late direction (direction indicated by arrow 53), as indicated by pulse 47 in Fig. 6G. In the conventional magnetic disk apparatus for performing high-density recording, the above write compensator is used to automatically shift write timings in a direction to reduce peak shifts. In the write compensator shown in Fig. 5, however, write compensation information is derived using a reference clock signal as a reference. Therefore, the delay time length of the write compensation information signal is determined by the duration of the reference clock signal. Time length J of signal Sl3a for compensating write timings in the early direction and time length K of signal Sl3c for compensating the write timings in the late direction, as shown in Fig. 6E, must fall within the length of time between the current and next trailing edges of reference clock signal CSl due to the following reason. Recording data Sl is shifted and shift register ll outputs different values to decoder l3 whenever reference signal CSl is input to shift register ll. Decoder l3 must completely decode the input before the output signal from register ll is updated. Therefore, each delay time length of signals Sl3a, Sl3b, and Sl3c cannot exceed one cycle of reference signal CSl. Therefore, ranges of delay times D0, Dl, and D2 (i.e., delay times D0, Dl, and D2 of signals Sl7a, Sl7b, and Sl7c) of write-compensated recording data S6 are solely determined. When the circuit is designed in practice, operating times of shift register ll and decoder l3 must be taken into consideration, and the lengths of delay times D0, Dl and D2 are further shortened. Therefore, delay times D0, Dl, and D2 cannot be flexible. The absence of flexibility poses a problem when the recording density is increased. It is an object of the present invention to provide a write compensator for a magnetic disk apparatus, wherein flexibility of delay times for write compensation can be assured by increasing the delay time lengths of write information signals. In order to achieve the above object of the present invention, there is provided data converting means for converting input recording data into a predetermined recording data format, write compensation information generating means for generating write compensation information on the basis of a conversion pattern of the input recording data or a data pattern of the recording data converted by said data converting means, write compensation information storing means for storing the write compensation information from said write compensation information generating means on the basis of the recording data converted by said data converting means, and write-compensating means for performing write compensation of the converted recording data on the basis of the write compensation information stored in said write compensation information storing means. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. lA through lE are timing charts for explaining the MFM conversion scheme, in which Fig. lA shows a data transfer reference clock, Fig. lB shows NRZ recording data, Fig. lC shows a clock pulse, Fig. lD shows a data pulse, and Fig. lE shows MFM-converted recording data; Figs. 2A through 2D are views for explaining peak shifts, in which Figs. 2A and 2B show peak shifts in the early direction, and Figs. 2C and 2D show peak shifts in the late direction; Figs. 3A through 3P are charts showing peak shift directions of data patterns; Fig. 4 is a table showing data patterns subjected to peak shifts; Fig. 5 is a block diagram of a conventional write compensator; Figs. 6A through 6G are timing charts for explaining the operation of the write compensator shown in Fig. 5, in which Figs. 6A and 6B show reference clock signals CS2 and CSl, Fig. 6C shows NRZ recording data, Fig. 6D shows MFM-converted recording data S2, Figs. 6E and 6F show signals Sl3a and Sl3c for compensating the write timings in the early and late directions, respectively, and Fig. 6G shows write-compensated MFM-converted recording data S6; Fig. 7 is a block diagram of a write compensator for a magnetic disk apparatus according to an embodiment of the present invention; and Figs. 8A through 8H are timing charts for explaining the operation of the write compensator shown in Fig. 7, in which Figs. 8A and 8B show reference signals CS2 and CSl, Fig. 8C shows NRZ recording data Sl, Fig. 8D shows signal S22 representing generation of MFM recording data S2 and generated by decoder 2l, Fig. 8E shows MFM recording data S2, Fig. 8F shows signal S23a for compensating the write timing in the early direction, Fig. 8G shows signal S23c for compen­ sating the write timing in the late direction, and Fig. 8H shows write-compensated MFM recording data S20. Fig. 7 is a block diagram of a write compensator for a magnetic disk apparatus according to an embodiment of the present invention. The same reference numerals as in Fig. 5 denote the same parts in Fig. 7, and a detailed description thereof will be omitted. In response to reference clock signals CSl and CS2, decoder 2l decodes NRZ recording data Sl stored in shift register ll. The decoded output serves as MFM recording data S2. Decoder 2l decodes the data pattern of data S2 to determine necessity of compensation and generates write compensation information signals S2la, S2lb, and S2lc as needed. More specifically, write compensation information signal S2la for compensating recording data S2 in the early direction, write compensation information signal S2lb for noncompensation, and write compensation information signal S2lc for compensating recording data S2 in the late direction are output to flip-flop 23. Decoder 2l has a function for supplying signal S22 representing generation of MFM recording data S2 to AND gate 25. Signal S22 (Fig. 8D) output from decoder 23 is a signal representing that recording data S2 shown in Fig. 8E is present. More specifically, signal S22 rises in response to the leading edge of recording data S2 shown in Fig. 8E and falls in response to the leading edge of reference signal CSl shown in Fig. 8B. Signal S22 is supplied to AND gate 25. AND gate 25 supplies trigger signal S24 to flip-flop 23 in response to reference signal CS2 shown in Fig. 8A. Flip-flop 23 retains the contents until trigger signal S24 is supplied from AND gate 25. Signal S22 may be a logical OR signal of signals S2la, S2lb, and S2lc. Flip-flop 23 comprises a D-type flip-flop. When trigger signal S24 is supplied from AND gate 25 to flip-flop 23, write compensation information signals S2la, S2lb, and S2lc which have been retained in flip-flop 23 are output to NAND gate l5 as write compensation information signals S23a, S23b, and S23c. At the same time, new write compensation information signals S2la, S2lb, and S2lc are received by flip-flop 23. Delay circuit l7 receives trigger signal S24 from AND gate 25 and delays it by delay times D0, Dl, and D2 to produce delayed signals Sl5a, Sl5b, and Sl5c. Signals Sl5a, Sl5b, and Sl5c are output to NAND gate l5. Write compensation information signals S23a, S23b, and S23c from flip-flop 23 and delayed signals Sl7a, Sl7b, and Sl7c from delay circuit l7 are logically NANDed by NAND gate l5. Signals Sl6a, Sl6b, and Sl6c are supplied from NAND gate l5 to NAND gate l9 and are logically NANDed by NAND gate l9. NAND gate l9 outputs write-compensated MFM recording data S20. NAND gates l5 and l9 constitute an OR gate and write-compensated recording data S20 is output in accordance with one of signals S2la, S2lb, and S2lc. The operation of the write compensator having the above arrangement will be described with reference to timing charts of Figs. 8A through 8H. Externally transferred NRZ recording data Sl is input to shift register ll at the trailing edge of reference clock signal CSl. Shift register ll stores 4-bit recording data Sl in response to the reference clock signal. When recording data Sl is stored in shift register ll, as described above, data Sl is output to decoder 2l. Decoder 2l decodes recording data Sl from shift register ll in response to reference clock signals CSl and CS2 and outputs MFM recording data S2 shown in Fig. 8E. Decoder 2l decodes a pattern of converted recording data S2 to determine necessity of compensation and generates write compensation information as needed. Write compensation information signals S2la, S2lb, and S2lc are output to flip-flop 23. Pulse 6l of recording data S2 shown in Fig. 8E is delayed. In this case, signal S23a (Fig. 8F) for compensating data S2 in the early direction is output between the leading edge of pulse 6l and the leading edge of the next pulse 63. Pulse 65 in recording data S2 is advanced. Signal S23c (Fig. 8G) for compensating data S2 in the late direction is output between the leading edge of pulse 65 and the leading edge of pulse 67. Signal S23b (not shown) is output for pulses not subjected to compensation between the leading edge of such a pulse and the leading edge of the next pulse. Decoder 2l outputs signal S22 to AND gate 25. Signal S22 represents that recording data S2 has been generated. AND gate 25 receives reference clock signal CS2. Reference clock signal CS2 and signal S22 from decoder 2l are logically ANDed by AND gate 25. Output signal S24 from AND gate 25 is output to flip-flop 23 and delay circuit l7. Write compensation information signals S2la, S2lb, and S2lc from decoder 2l are stored in flip-flop 23 in response to signal S24 as a trigger signal. Flip-flop 23 retains write compensation information signals S2la, S2lb, and S2lc until trigger signal S24 is output from AND gate 25. Trigger signal S24 is output to flip-flop 23 whenever signal S22 shown in Fig. 8D is output, i.e., recording data S2 shown in Fig. 8E is output. Therefore, when recording data S2 is not output, signals S2la, S2lb, and S2lc are retained regardless of the clock period of signal CSl of Fig. 8B. As a result, the pulse widths of write compensation signals S23a and S23c can be increased, as shown in Figs. 8F and 8G, respectively. The pulse width can be increased to a maximum width until the next recording data S2 is input. It should be noted that write compensation information signal S23b for noncompensation is not illustrated but its pulse width can also be increased in the same manner as in signals S23a and S23c. Flip-flop 23 outputs write compensation information signals S2la, S2lb, and S2lc as write compensation information signals S23a, S23b, and S23c to NAND gate l5. Delayed signals Sl8a, Sl8b, and Sl8c from delay circuit l7 are input to and are logically ANDed by NAND gate l5. Signals Sl6a, Sl6b, and Sl6c are output from NAND gate l5 to NAND gate l9. Signals Sl6a, Sl6b, and Sl6c are logically NANDed by NAND gate l9, thereby outputting write-compensated MFM recording data S20. In the write compensator according to the present invention, the write compensation information signals from decoder 2l are temporarily stored in flip-flop 23 by using converted recording data. Write compensation is performed on the basis of the write compensation information signals output from the flip-flop 23. Delay time length M of signal S23a for compensating the write timing in the early direction and delay time length N of signal S23c for compensating the write timing in the late direction can be given with reference to the pulse width of recording data S2. Delay times D0, Dl, and D2 of write-compensated recording data S20 can be prolonged, thus providing flexibility in delay times. In the above embodiment, write compensation information is obtained on the basis of the pattern of the converted recording data. However, write compensation information may be obtained on the basis of the pattern of recording data prior to conversion.

Claims: 1. A write compensator for a magnetic disk apparatus, said write compensator being adapted to convert input recording data into a predetermined recording data format, perform write compensation of converted recording data in accordance with a data pattern of the converted recording data, and record write-compensated recording data in a recording medium, characterized in that there are provided: data converting/write compensation information generating means (2l) for converting the input recording data into the predetermined recording data format and generating write compensation information on the basis of the data pattern of the recording data converted by said data converting means; write compensation information storing means (23) for storing the write compensation information from said data converting/write compensation information generat­ ing means (2l) on the basis of the recording data converted by said data converting/write compensation information generating means (2l); and write-compensating means (l7, l5, l9) for write-compensating the converted recording data on the basis of the write compensation information stored in said write compensation information storing means (23). 2. A compensator according to claim l, characterized in that the recording data format is modified frequency modulation. 3. A compensator according to claim l, charac­ terized in that said data converting/write compensation information generating means (2l) outputs a write recording data presence signal representing that recording data to be written is present, and said write compensation information storing means (23) stores the write compensation information from said data converting/write compensation information generating means in response to the write recording data presence signal and holds current write compensation information until the next write recording data signal is supplied. 4. A compensator according to claim l, charac­ terized in that said data converting/write compensation information generating means (2l) comprises a decoder. 5. A compensator according to claim l, charac­ terized in that said write compensation information storing means (23) comprises a flip-flop. 6. A compensator according to claim 3, charac­ terized in that said compensator further comprises: a delay circuit (l7) for receiving the write recording signal output from said data converting/write compensation information generating means (2l) and generating a first delayed signal for compensating recording data writing in an early direction, a second delayed signal for performing no write compensation of the recording data, and a third delayed signal for compensating recording data writing in a late direction; and a gate circuit (l5, l9) for receiving the write compensation information from said delay circuit (l7) and said write compensation information storing means (23) and outputting a write compensated signal as the recording data when a time corresponding to a supplied one of the delayed signal has elapsed.

Inventors: HASHIMOTO, YASUICHI PATENT DIVISION K.K.
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: G11B20
IPC codes: G11B20, G11B5