HIGH SPEED FREQUENCY DIVIDE-BY-5 CIRCUIT

Abstract: An improved, high-speed frequency divider cir­ cuit (32) is presented. The frequency divider circuit (32) is comprised of three D-type flip-flops (34, 36, 38). The three flip-flops (34, 36, 38) are clocked synchronously for higher speed of operation. The design of the frequency divider circuit (32) embodies a saga­ cious state assignment to minimize the number of bits that change state on any given state transition, thus reducing the possibility of faulty circuit operation.

Description: This invention relates to a high frequency divide-by-5 counter circuit. In various areas of electronics there is a need for circuits that will operate to divide frequency, typically in ultrahigh frequency applications. For example, a phase-locked loop system could require a frequency divider circuit for high frequency application. As is well known in the prior art, a phase-locked loop consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator (VCO) with that of an incoming carrier signal or reference-frequency generator. The output of the phase detector is fed back to the VCO to keep it exactly in phase with the reference frequency. In integrated circuits, the reference frequency for a phase-locked loop is typically provided by a crystal oscillator. However, it is expensive and difficult to manufacture a crystal oscillator that operates above 25 megahertz (MHz). Therefore, in a phase-locked loop which operates at l00-l50 MHz, for example, a frequency-divider circuit is necessary to step down the frequency from the VCO before it is transmitted to the phase detector for comparison to the reference frequency from the crystal oscillator. A divide-by-N frequency divider circuit (also called a counter circuit) will divide by a specific number of counts; that is, for N-clock pulses put into the circuit, only one output pulse is generated. Conventional frequency-divider circuits for binary signals usually consist of master slave, D-type flip-flops. Such a flip-flop has a single data input (D input), either one or a pair of complementary data outputs (Q or Q , or both), and a clock input (CLK). In operation, data in the form of a logic level present at the data input (D input) is transferred to the data output (Q output) when the clock input CLK makes a specified clock pulse edge or transition (i.e., transition from logic "low" or "O" level to logic "high" or "l" level). If provided, complementary data output is available at the Q output. When the clock input CLK level changes from the high state to the low state, the logic state present at the D input prior to the clock transition is retained or latched at the data output or outputs, regardless of subsequent changes in the data input, until such time as the clock input CLK makes a low-to-high transition again. High-frequency circuit design requires that the number of parasitic capacitances and resistances be kept at a minimum. Parasitics associated with any given circuit node increase the delay of circuit operation related to that node. Hence, it is desirable to keep the number of interconnections to a minimum in a circuit designed to operate at high frequencies. The general approach to minimizing interconnections is to reduce the complexity of the circuit. A small number of interconnections in general means a small number of components, particularly of components with three or more terminals (e.g., transistors). In a frequency divider circuit this translates to reducing the gate count through the signal path. Another method of increasing the speed of a frequency-divider circuit is to operate all its flipflops synchronously; that is, all driven by the same clock waveform. A synchronous divider circuit is one in which all flipflops of the circuit change state simultaneously in response to a common clock. Since all flipflops change simultaneously, the output (or count or state) can be decoded quickly because there is no count propagation to wait for. A further objective in designing a high-speed-frequency divider circuit is to reduce total propagation delay to a minimum. For this type of circuit, propagation delay is the time required for the network to stabilize in a new state, as measured from the low to high edge transition of the clock input (CLK) signal. Propagation delay can be reduced by judicious assignment of the states of the counter flipflops. The Article "An ultra low power 500 MHz dual modulus prescaler" by T Ishioka et al, published in the Transactions on Consumer Electronics of the IEEE, August 1985 No 3 (New York, USA), discloses a high frequency divide-by-5 circuit having three flipflop devices with feed back from their outputs to inputs. We will describe a frequency divider circuit capable of operating at frequencies of 125 MHz and above. We will describe a frequency divider circuit which has a minimum number of interconnections to keep parasitic capacitances and resistances to a minimum. We will describe a frequency divider circuit which operates synchronously. We will describe a frequency divider circuit having reduced propagation delay. Accordingly the present invention provides a high frequency divide-by-5 counter circuit comprising first, second and third flipflop devices each having a data input, a non-inverting data output and an inverting data output, and a clock input, each connected to receive, on their respective clock inputs, a frequency to be divided by 5, and connected with feed back between outputs of the second and third flipflop devices and the data input of the first flipflop; characterised in that the data input of the first flipflop device includes a first OR gate having two inputs one of which is connected to the output of a first NOR gate having two inputs; the data input of the second flip device includes a second OR gate having a first input; the non-inverting output of the first flipflop device is connected to the first input of the second OR gate; the non-inverting output of the second flipflop device is connected to the data input of the third flipflop device and to one input of the first NOR gate; the inverting output of the third flipflop device is connected to the other input of the first OR gate and to the other input of the first NOR gate; and the divided-by-5 output of the circuit is taken from the inverting output of the first flipflop device. Other objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures. BRIEF DESCRIPTION OF THE DRAWINGS FIGURE l is a schematic diagram of a frequency divider circuit known in the prior art. FIGURE 2 is a diagram of the timing waveforms for the frequency divider circuit of FIGURE l. FIGURE 3 is a schematic diagram of the frequency divide-by-5 circuit according to a preferred embodiment of the present invention. FIGURE 4 is a diagram of the timing waveforms for a frequency-divide-by-5 circuit of the present invention. DETAILED DESCRIPTION OF THE INVENTION Reference is now made, in detail, to a specific embodiment of the present invention which illustrates the best mode presently contemplated by the inventor for practicing the invention, the preferred embodiment of which is set forth in the accompanying drawings. The drawings referred to in this description are understood to be not drawn to scale and to illustrate only one portion of an integrated circuit fabricated in accordance with the present invention. FIGURE l shows a frequency divide-by-5 circuit 2 of the prior art. The frequency divider circuit 2 includes D-type flip-flops 4, 6, 8, l0. Such flip-flops are well known in the prior art. The flip-flops 4, 6, 8, l0 each have a data input D₁ through D₄, respectively. The flip-flops 4, 6, 8, l0 also each have noninverting data outputs Q₁ through Q₄, respectively, and complementary, or inverting data outputs Q ₁ through Q ₄, respectively. Finally, the flip-flops 4, 6, 8, l0 each have clock inputs l2, l4, l6, l8, respectively. A frequency input 20 of the frequency divider circuit 2 is coupled to the clock input l2 of the flip-flop 4. The data input D₁ and the data output Q ₁ are coupled together to a first input of NOR gate 22. The data output Q₁ of the flip-flop 4 is coupled to the clock input l4 of the flip-flop 6. The data output Q ₂ of the flip-flop 6 is coupled to the data input D₂ of the flip-flop 6. The other data output Q₂ of the flip-flop 6 is coupled to a second input of NOR gate 22. The data output Q₂ of the flip-flop 6 is coupled to the clock input l6 of the flip-flop 8. The data output Q ₃ of the flip-flop 8 is coupled together with the data input D₃ of the flip-flop 8 to a third input of NOR gate 22. The data output Q₃ of the flip-flop 8 is the frequency output for the frequency divider circuit 2. The output of the NOR gate 22 is coupled to the data input D₄ of the flip-flop l0. The frequency input 20 of frequency divider circuit 2 is coupled through an inverter 24 to the clock input l8 of the flip-flop l0. Finally, the data output Q₄ of the flip-flop l0 is coupled collectively to a set input 26 of the flip-flop 4, a clear input 28 of the flip-flop 6 and a clear input 30 of the flip-flop 8. The operation of the frequency divider circuit 2 can be explained as follows: Assuming a starting internal state of < 0,0,0,0 >, i.e., each of the data outputs Q₁ to Q₄ is zero, (<Q₄, Q₃, Q₂, Q₁> = <0,0,0,0>), upon the first rising edge of a clock pulse at the frequency input 20, the flip-flop 4 will change state such that the data output Q₁ will be a logic HIGH or one. This is so because the flip-flop 4, like the flip-flops 6 and 8, has its inverting output coupled back to its data input. Thus, each of the flip-flops 4, 6, 8 will change state when a rising clock edge is presented at its respective data input. The logical one output of the flip-flop 4, in turn, clocks the flip-flop 6, causing the flip-flop 6 to change state such that the data output Q₂ will be a logical one. Similarly, the logical one output of the flip-flop 6 clocks the flip-flop 8, causing the flip-flop 8 to change state such that the data output Q₃ will be a logical one. Thus, after the first rising edge of a clock pulse at the frequency input 20, the internal state of the frequency divider circuit 2 will be < Q₄, Q₃, Q₂, Q₁ > = < 0,l,l,l >. It will be noted that after the rising edge of the first clock pulse at the frequency input 20, each of the inverting data outputs Q ₁, Q ₂, Q ₃ is a logical zero. Next, on the falling edge of the first clock pulse at the frequency input 20, the flip-flop l0 is clocked. This is due to the inverter 24, which changes the logical zero from the falling edge of any clock pulse of the frequency input 20 to a logical one. The flip-flop l0, however, will not change state until a logical one is presented at the data input D₄, from the output of the NOR gate 22. The NOR gate 22 operates to sense the states of the flip-flops 4, 6, 8. When the data outputs Q₃, Q₂, Q₁ equal logical one, logical zero, and logical one, respectively, (i.e., < l,0,l >) the output of the NOR gate 22 will go "HIGH" (i.e., to a logical one). The next falling edge of a clock pulse on the frequency input 20 will cause the flip-flop l0 to change state such that the data output Q₄ will be a logical one. The effect of this transition is discussed below. On the rising edge of a second clock pulse at the frequency input 20, the flip-flop 4 again changes state such that the data output Q₁ becomes a logical zero. The flip-flop 6 and, subsequently, the flip-flop 8, however, will not change state because the logical zero at data output Q₁ will not clock the flip-flop 6, which, in turn, will not clock the flip-flop 8. Thus, the internal state of the frequency divider circuit 2 at this time is < Q₄, Q₃, Q₂, Q₁ > = < 0,l,l,0 >. On the rising edge of a third clock pulse at the frequency input 20, the flip-flop 4 once again changes state such that the data output Q₁ becomes a logical one. The logical one at data output Q₁ in turn clocks the flip-flop 6, causing the flip-flop 6 to change state such that the data output Q₂ becomes a logical zero. At this point, the internal state of the frequency divider circuit 2 is < Q₄, Q₃, Q₂, Q₁ > = < 0,l,0,l >. Note that when Q₃ = l, Q ₃ = 0; and when Q₁ = l, Q ₁ = 0. Since the three inputs to NOR gate 22 are Q ₃, Q₂ and Q ₁, at this point in the counting sequence NOR gate 22 is presented with an input of < 000 >, causing the output of the NOR gate 22 to change to a logical one. Thus, a logical one is presented to the data input D₄ of the flip-flop l0. Next, on the falling edge of the third clock pulse at the frequency input 20, the flip-flop l0 is clocked, causing the flip-flop l0 to change state such that the data output Q₄ becomes a logical one. As can be seen in FIGURE l, data output Q₄ is coupled to "clear" terminals 28, 30 of the flip-flops 6 and 8, respectively. Data output Q₄ is also coupled to a "set" terminal 26 of the flip-flop 4. The set terminal 26 of the flip-flop 4 operates to set the data output Q₁ to a logical one when a logical one is presented to the set terminal 26. The clear terminals 28, 30 operate to set the data output Q₂ and Q₃, respectively, to a logical zero when a logical one is presented to the clear terminals 28, 30. The set terminal 26 and the clear terminals 28, 30 are coupled to circuitry internal to the flip-flops 4, 6 and 8, respectively, that functions to override the operation of the clock inputs l2, l4, l6 so long as a logical one is present on the set terminal 26 and the clear terminals 28, 30. Thus, data output Q₁ remains at logical one and data outputs Q₂ and Q₃ remain at logical zero until the next falling edge of a fourth clock pulse at frequency input 20, which returns data output Q₄ to a logical zero. Next, on the rising edge of the fifth clock pulse on frequency input 20, the flip-flop 4 is clocked causing the flip-flop 4 to change state such that the data output Q₁ becomes a logical zero. The frequency divider circuit 2 is thus once again in its starting internal state; i.e., < Q₄, Q₃, Q₂, Q₁ > = < 0,0,0,0 >. The counting sequence of the prior art frequency divider circuit 2 is shown below in Table l. FIGURE 2 shows the timing pattern described above for the frequency divider circuit 2. Note that the frequency on the frequency out terminal Q₃ is reduced by five times from the frequency on the frequency input terminal 20. Thus, for every five input pulses on frequency input 20, the frequency divider circuit 2 delivers one output pulse at data output Q₃ (frequency output terminal). Using current bipolar technology with minimum current density gates, the frequency divider circuit 2 is only capable of operating up to speeds less than l00 MHz. If the frequency rate at the frequency input 20 should exceed the l00 MHz timing constraint, the circuit will malfunction, escaping from the desired count sequence. The critical timing, limiting the speed of the frequency divider circuit 2, occurs during the "HIGH" portion of the third clock pulse on the frequency input 20. The following timing events, initiated by the rising edge of the third clock pulse, must be completed prior to the falling edge of the third clock pulse: l. Propagation delay of a signal from the frequency input 20 to the data output Q₁ : ≈ 2.5 nanoseconds (ns); 2. Propagation delay of a signal from the data output Q₁ to the data output Q₂ : ≈ 2.5 ns; 3. Propagation delay of a signal from the data outputs Q₁ and Q₂ to the output of NOR gate 22 : ≈ 2 ns; and 4. The set-up time of the output of NOR gate 22 at the data input D₄ : ≈ l ns. TOTAL: 8 ns. Thus, three propagation delays and a set-up time must occur all within one-half of the frequency-in period. A further problem with the design of the frequency divider circuit 2 is the probability of disturbance of the count sequence from spurious states. This arises because of the number of bits that switch simultaneously. Referring to Table l, it can be seen that when the frequency divider circuit 2 changes from clock pulse l to clock pulse 2, three bits change simultaneously (0,0,0 to l,l,l); and when the circuit changes from clock pulse 3 to clock pulse 4, two bits change simultaneously. FIGURE 3 shows a schematic diagram of a frequency divider circuit 32 in accordance with the present invention. The frequency divider circuit 32 is comprised of D-type flip-flops 34, 36, 38. The flip-flops 34, 36, and 38 each have a data input, D₁ through D₃, respectively, and a data output, Q₁ through Q₃, respectively. Each of the flip-flops 34, 36, 38 also has an inverting data output, Q ₁ through Q ₃, respectively. The data output Q₁ of the flip-flop 34 is coupled to a first input of an OR gate 40. The inverting output Q ₁ of the flip-flop 34 is the frequency output for the frequency divider circuit 32. The data output Q₂ of the flip-flop 36 is coupled to the data input D₃ of the flip-flop 38, and is further coupled to a first input of a NOR gate 42. The inverting data output Q ₂ of the flip-flop 36 is coupled to a first input of a NOR gate 44. The data output Q₃ of the flip-flop 38 is coupled to a second input of the NOR gate 44. The output of the NOR gate 44 is coupled to a second input of the OR gate 40. The output of the OR gate 40 is coupled to the data input D₂ of the flip-flop 36. The inverting data output Q ₃ of the flip-flop 30 is coupled to a first input of an OR gate 46, and is further coupled to a second input of the NOR gate 42. The output of the NOR gate 42 is coupled to a second input of the OR gate 46. The output of the OR gate 46 is coupled to the data input D₁ of the flip-flop 34. (Note: The OR gate 46 is actually internal to the flip-flop 34, but is shown externally for purposes of illustration.) Frequency input 48 is coupled to clock inputs 50, 52, 54 of the flip-flops 34, 36 and 38, respectively. The following discussion of the operation of the frequency divider circuit 32 can be followed by referring to the circuit connections described above. The operation of the frequency divider circuit 32 of the present invention is as follows: Assume a starting internal state of < Q₁ , Q₂, Q₃ > = < 0,0,0 >. When < Q₁, Q₂, Q₃ > = < 0,0,0 >, then each of Q ₁, Q ₂ and Q ₃ will be a logical one. When Q₁ = 0, one input of the OR gate 40 will be logical zero. When Q₂ = 0, a first input of the NOR gate 42 will be logical zero. A second input of the NOR gate 42 is a logical one, because Q ₃ = l. Thus, the output of the NOR gate 42 will be logical zero at this point. Therefore, one input of the OR gate 46 will also be logical zero. The other input to the OR gate 46 is a logical one because Q ₃ = l. Therefore, data input D₁ is presented with a logical one from the output of the OR gate 46. Also during the starting state of < Q₁, Q₂, Q₃ > = < 0,0,0 >, one input of the NOR gate 44 will be a logical one because Q ₂ = l. The other input of the NOR gate 44 will be a logical zero because Q₃ = 0. Therefore, the output of the NOR gate 44 is a logical zero which is presented at one input of the OR gate 40. The other input of the OR gate 40 is a logical zero because Q₁ = 0. Therefore, the output of the OR gate 40 equals a logical zero, which is presented at the data input D₂ of the flip-flop 36. Referring to FIGURE 3, it can be seen that during the starting state of < Q₁, Q₂, Q₃ > = < 0,0,0 >, the three data inputs D₁, D₂, and D₃ equal logical one, logical zero and logical zero, respectively. On the rising edge of a first clock pulse at the frequency input 48, all three flip-flops 34, 36, 38 are clocked simultaneously. As can be seen from the discussion above, only the flip-flop 34 will change state because only the flip-flop 34 has a logical one on its data input. Therefore, after the rising edge of a first clock pulse on the frequency input 48, the internal state of the frequency divider circuit 32 is < Q₁, Q₂, Q₃ > = < l,0,0 >. After the rising edge of the first clock pulse at the frequency input 48, the following circuit nodes will have changed logical signal levels: Q₁ equals a logical one; therefore, one input of the OR gate 40 equals a logical one; and thus the output of the OR gate is a logical one which is presented at the data input D₂ of the flip-flop 36. Also, since Q₁ = l, Q ₁ = 0. On the rising edge of a second clock pulse at the frequency input 48, all three flip-flops 34, 36, 38 are again clocked simultaneously. Only the flip-flop 36 will change state, however, because it is the only flip-flop that has an input ("l") different from its output ("0") at the time it is clocked. Thus, after the second clock pulse on the frequency input 48, the data output Q₂ equals a logical one, and the internal state of the frequency divider circuit 32 is < Q₁, Q₂, Q₃ > = < l,l,0 >. After the rising edge of the second clock pulse at the frequency input 48, the following circuit nodes will have changed logical signal levels: Because Q₂ now equals logical one, Q ₂ = 0; the data input D₃ = l; and a second input of the NOR gate 42 now equals logical one. Since Q ₂ = 0, a second input of the NOR gate 44 now equals zero. Therefore the output of the NOR gate 44 is a logical one. On the rising edge of the third clock pulse at the frequency input 48, the three flip-flops 34, 36, 38 are clocked simultaneously; only the flip-flop 38 changes state since its input ("l") is different from its output ("0") immediately prior to the third clock pulse. Thus, after the third clock pulse at the frequency input 48, the data output Q₃ equals a logical one, and the internal state of the frequency divider circuit 32 is < Q₁ Q₂, Q₃ > = < l,l,l, >. After the third clock pulse, the following circuit nodes will have changed logical signal levels: Because Q₃ now equals logical one, Q ₃ = 0, and one input of the NOR gate 44 equals logical one. The output of the NOR gate 44 therefore equals logical zero which is presented at one input of the OR gate 40. Because Q ₃ now equals logical zero, the second input of the NOR gate 42 equals logical zero and a second input of the OR gate 46 equals logical zero. With both inputs of the OR gate 46 being logical zero, the output of the OR gate 46 is logical zero, which is presented at the data input D₁ of the flip-flop 34. On the rising edge of the fourth clock pulse at the frequency input 48, the three flip-flops 34, 36 and 38 are again clocked simultaneously; only the flip-flop 34, however, changes its state, since its input ("0") is different from its output ("l") immediately prior to the fourth clock pulse. Thus, after the fourth clock pulse, the data output Q₁ equals logical zero, and the internal state of the frequency divider circuit 32 is < Q₁, Q₂, Q₃ > = < 0,l,l >. After the fourth clock pulse, the following circuit nodes will have changed logical signal levels: Because Q₁ now equals logical zero, Q ₁ = l; and a second input to the OR gate 40 equals logical zero. Since both inputs to the OR gate 40 are logical zero, the output of the OR gate 40 is logical zero, which is presented at the data input D₂ of the flip-flop 36. On the rising edge of the fifth clock pulse at the frequency input 48, the three flip-flops 34, 36, 38 are simultaneously clocked. On the fifth clock pulse only the flip-flop 36 changes state, since its input ("0") is different from its output ("l") immediately prior to the fifth clock pulse. Thus, after the fifth clock pulse, the data output Q₂ is a logical zero, and the internal state of the frequency divider ciruit 32 is < Q₁, Q₂, Q₃ > = < 0,0,l >. After the fifth clock pulse, the following circuit nodes will have changed logical signal levels: since Q₂ = 0, Q ₂ becomes a logical one; the data input D₃ of the flip-flop 38 becomes a logical zero; and the second input of the NOR gate 42 becomes a logical zero. The output of the NOR gate 42 now becomes a logical one which is presented to one input of the OR gate 46. The output of the OR gate 46 thus becomes a logical one which is presented to the data input D₁ of the flip-flop 34. Finally, since Q ₂ = l, a second input of the NOR gate 44 becomes a logical one. On the rising edge of the sixth clock pulse at the frequency input 48 (the beginning of a second timing cycle), the three flip-flops 34, 36, 38 are once again clocked simultaneously. On this clock pulse, two of the flip-flops, 34 and 38, change state. The data output Q₁ of the flip-flop 34 becomes a logical one and the data output Q₃ of the flip-flop 38 becomes a logical zero. Thus, the frequency divider circuit 32 is now back to the internal state following the first clock pulse in the count sequence; i.e., < Q₁, Q₂, Q₃ > = < l,0,0 >. The counting sequence of the frequency divider circuit 32 is shown below in Table 2. FIGURE 4 shows the timing pattern described above for the frequency divider circuit 32. Note that the frequency on the frequency out terminal Q ₁ is reduced by five times from the frequency on the frequency input terminal 48; i.e., for every five input pulses on the frequency input 48, the frequency divider circuit 32 delivers one output pulse at the data output Q ₁. The minimum propagation delay in the design of the frequency divider circuit 32 was achieved by sagacious state assignment. Except for the transition from the final state to the initial state in the counting sequence, each successive count in the sequence differs by only a single bit. This eliminates spurious state changes and avoids excessive delay. The maximum operating frequency of the frequency divider circuit 32 is limited by the transition from the final state to the initial state in the counting sequence. The maximum frequency is given by the following equation: where t s(34) = set-up time of the flip-flop 34, t pd(36) = propagation delay of the flip-flop 36, and t pd(42) = propagation delay of the NOR gate 42. (Note, that since the OR gate 46 is internal to the flip-flop 34, it only appears as a set-up to the flip-flop 34 and not as a gate delay in the signal path.) Computer simulations of circuit operation predict the following performance under worst-case conditions at 155° centigrade: t s(34) = 1.2 ns t pd(36) = 3.5 ns t pd(42) = 1.6 ns Total = 6.3 ns Maximum input frequency = 158.7 MHz While the above represents worst-case conditions, with current bipolar technologies, the frequency divider circuit 32 is capable of operating at speeds up to 250 MHz. It will be noted that in any 3-flip-flop binary counter circuit (i.e., 3 output bits), there are eight possible count states. It will also be noted that the counting sequence of the frequency divider circuit 32 utilizes only five of the possible eight states. In such a situation, there is a possibility that the frequency divider circuit 32 could, by chance, find itself in any one of the three unused states. This could occur when the circuit is powered-up or could result from external noise affecting the state of a flip-flop. For every state in the counting sequence shown in Table 2, the state to which the circuit goes at the next input clock pulse is known; but the next state for an unused state is not known. Thus, there is the further possibility that when a flip-flop is "thrown" into an unused state, the counter might oscillate from unused state to unused state, never arriving at a used state. A circuit whose unused states have this feature is said to suffer from "lockout." If, by chance, the frequency divider circuit 32 should enter any unused state (Q₁, Q₂, Q₃ = 0,0,0; 0,1,0; 1,0,1), it will quickly return to the correct counting sequence, thus preventing lockout. This is accomplished by OR gate 46 or NOR gate 44. For example, if the frequency divider circuit 32 was powered-up to state < Q₁, Q₂, Q₃ > = < 1,0,1 >, the NOR gate 44 would hold Q₂ equal to a logical zero until the count entered either state < Q₁, Q₂, Q₃ > = < 0,0,1 > or state < Q₁, Q₂, Q₃ > = < 1,0,0 >. If, instead, the frequency divider circuit 32 was powered up to state < Q₁, Q₂, Q₃ > = < 0,1,0 >, Q₂ would be held equal to a logical one until the count entered the state < Q₁, Q₂, Q₃ > = < 0,1,1 >. Without the NOR gate 44, the frequency divider circuit 32 would oscillate between states < Q₁, Q₂, Q₃ > = < 0,1,0 > and < 1,0,1 >. Likewise, if state < Q₁, Q₂, Q₃ > = < 0,0,0 > should occur, the first input of the OR gate 46 (which is coupled to the data output Q ₃) ensures that the next state will be < Q₁, Q₂, Q₃ > = < 1,0,0 >, thus returning to the correct count sequence.

Claims: A high frequency divide-by-5 counter circuit comprising first (34), second (36) and third (38) flipflop devices each having a data input, a non-inverting data output, an inverting data output, and a clock input; each connected to receive, on their respective clock inputs, a frequency to be divided by 5, and connected with feed back between outputs of the second and third flipflop devices and the data input of the first flipflop; characterised in that the data input (D1) of the first flipflop device (34) includes a first OR gate (46) having two inputs one of which is connected to the output of a first NOR gate (42) having two inputs; the data input (D2) of the second flip device (36) includes a second OR gate (40) having a first input; the non-inverting output (Q1) of the first flipflop device is connected to the first input of the second OR gate; the non-inverting output (Q2) of the second flipflop device is connected to the data input (D3) of the third flipflop device and to one input of the first NOR gate; the inverting output ( Q 3) of the third flipflop device is connected to the other input of the first OR gate and to the other input of the first NOR gate; and the divided-by-5 output of the circuit is taken from the inverting output ( Q ,) of the first flipflop device. A high frequency divide-by-5 circuit according to Claim 1, characterised in that the second OR gate has a further input connected to the output of a second NOR gate (44) having two inputs; and one input of the second NOR gate is connected to the non-inverting output (Q3) of the third flipflop device while the other input of the second NOR gate is connected to the inverting output ( Q 2) of the second flipflop device. A high frequency divide-by-5 circuit according to claim 1 or 2 characterised in that said circuit counts according to the following counting sequence: Clock Pulse from External Means for Providing Clock Pulses 1st Flipflop Device Non-inverting output 2nd Flipflop Device Non-inverting Output 3rd Flipflop Device Non-inverting Output 1st Clock Pulse 1 0 0 2nd Clock Pulse 1 1 0 3rd Clock Pulse 1 1 1 4th Clock Pulse 0 1 1 5th Clock Pulse 0 0 1 A high frequency divide-by-5 circuit according to claim 1, 2 or 3, characterised in that said first, second and third flipflop means each comprise a D-type flipflop.

Inventors: BEREZNAK, BRADLEY J.
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1987
Main classification: H03K23
IPC codes: H03K23