AN APPARATUS FOR CONTROLLING PERIPHERAL EQUIPMENTS

Abstract: An apparatus for controlling peripheral equipments comprises means for driving the peripheral equipments, first and second means for storing conditions under which the peripheral equipments are conducting a predetermined operation, and a timer for counting a time of the predetermined operation of the peripheral equipment stored in the second means. The content of the first means is written into the second means when there is no peripheral equipment stored in the latter. When the counted time of the timer becomes equal to a predetermined time, a time over signal indicating that an operation time of a peripheral equipment stored in the second means is longer than a normal operation time is produced so that it is possible that a single common timer counts an operation time of a plurality of peripheral equipments.

Description: The invention relates to an apparatus for controlling peripheral devices, and more particularly to an apparatus for controlling peripheral devices in which an operation time of peripheral devices such as a seek time of disc drives is counted to be compared with a predetermined operation time. BACKGROUND OF THE INVENTION One of conventional apparatus for controlling peripheral devices which are adapted to control, for instance, disc drives comprises a processor for controlling a plurality of disc drives, and a plurality of timers each counting a seek time of a corresponding one of the disc drives. In operation, a control signal is supplied from the processor to one of the disc drives whereby a head is controlled to move from an original track to a designated track on a recording medium like a magnetic disc or an optical disc so that an information is read from the recording medium or written thereinto. In the control of the disc drive, a timer counts a seek time during which the head moves from the original track to the designated track whereby the counted time is compared with a predetermined time. In a case where the head can not seek the designated track in the predetermined time, the processor produces a control signal again to re-control a corresponding disc drive so that the head moves again toward the designated track. When the head can not reach the designated track even after a predetermined number of addressing trials, the disc drive can be detected to be "failed". According to the conventional apparatus for controlling peripheral devices, however, there has been a disadvantage that the amount of hardware is increased because a plurality of timers are provided independently in each of the disc drives. As a result, the number of disc drives which can be controlled by one semiconductor chip disc controller is limited. Further, means for controlling plurality of timers becomes very complicated. SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to provide an apparatus for controlling peripheral devices in which a single timer is provided to count a seek time for a plurality of peripheral equipments like disc drives. It is a further object of the invention to provide an apparatus for controlling peripheral devices in which peripheral devices like disc drives which can be controlled by one semiconductor chip controller are increased in its number. It is a still further object of the invention to provide an apparatus for controlling peripheral devices in which a very complicated means for controlling a plurality of timers is not necessary to be provided. According to the invention, an apparatus for controlling peripheral devices comprises, means for driving a plurality of peripheral devices, first means for storing units of information, each unit indicating that a peripheral device among said plurality of peripheral devices is under a predefined operation, said units of information being changed therein according to when and which one of said plurality of peripheral devices is under said predefined operation, second means for storing said units of information which are written thereinto from said first means only when there is stored no units of information in said second means, said units of information being erased therein according to when and which one of said plurality of peripheral devices finishes said predefined operation, and a timer for counting a time during which at least one of said units of information is stored in said second means to compare said time with a predetermined time, wherein said timer produces a time over signal when said time becomes equal to said predetermined time. The invention will be explained in more detail in accordance with following drawings, Fig. 1 is a block diagram showing an apparatus for controlling peripheral devices in a first embodiment according to the invention, Fig. 2 is a timing chart explaining an operation in the apparatus for controlling peripheral devices in the first embodiment according to the invention, and Fig. 3 is a block diagram showing an apparatus for controlling peripheral devices in a second embodiment according to the invention. In Fig 1, there is shown an apparatus for controlling peripheral devices comprising a plurality of disc drives 1₁, 1₂, 1₃ ----- 1n each driving a head to move from an original track to a designated track on a magnetic disc or optical disc, a first register 2 having flags F₁₁, F₁₂, F₁₃ ----- F 1n of n bits respectively connected through signal lines 8 to the disc drives 1₁, 1₂, 1₃ ----- 1n and turned "1" when the corresponding disc drive 1k (k=1, 2, 3 ----- n) is under a seek operation, a second register 3 having flags F₂₁, F₂₂, F₂₃----- F 2n of n bits respectively connected through the signal lines 8 to the disc drives 1₁, 1₂, 1₃ ----- 1n and into which the content of the first register 2 is written when all the n bits of the second register 3 are "0", a control circuit (CPU) 4 which controls the disc drives 1₁, 1₂, 1₃ ----- 1n, first and second register 2 and 3, and so on in accordance with a program stored in a ROM (not shown), especially to write the content of the first register 2 into the second register 3 when all the flags F₂₁, F₂₂, F₂₃ ----- F 2n of the second register 3 are "0" as mentioned before, a timer 5 for counting a seek time for at least one of the disc drives 1₁ , 1₂, 1₃ ----- 1n stored in the second register 3 to produce a time over signal when the counted time becomes equal to a predetermined time, and a host processor 6 which is connected through a bus 9 to the control circuit 4 and to which the time over signal is supplied from the timer 6. In the first and second registers 2 and 3 each flag of "1" is turned "0" when a corresponding one of the disc drives 1₁, 1₂, 1₃ ----- 1n has finished the seek operation. In the construction of the apparatus for controlling peripheral devices described above, the first and second registers 2 and 3, control circuit 4, and timer 5 may be fabricated by one semiconductor chip, while the disc drives 1₁, 1₂, 1₃ ----- 1n may be provided externally to the semiconductor chip. In operation, it is assumed that there is no disc drive which is under a seek operation at the initial stage (prior to time t₁) as shown in Fig. 2 so that all the flags of the first and second registers 2 and 3 are "0". At this stage, the timer 5 has been reset. Next, the control circuit 4 produces a control signal to control the disc drive 1₃ thereby demanding a seek operation at time t₁ so that the flag F₁₃ of the first register 2 is turned "1". At the present stage, all the flags of the second register 3 are "0" so that the content of the first register 2 is written through the control circuit 4 into the second register 3, while the content of the first register 2 including the flag F₁₃ remains unchanged. As a result, the flags F₂₃ of the second register 3 is turned "1". At this moment, the timer 5 is driven to count a seek time of the disc drive 1₃. Thereafter, it is assumed that the disc drives 1₄ and 1₅ are controlled to conduct a seek operation respectively at times t₂ and t₃ so that the flags F₁₄ and F₁₅ of the first register 2 and turned "1". At these times t₂ and t₃, the content of the first register 2 is not written into the second register 3 because all the flags of the second register 3 are not "0" due to the fact that the flag F₂₃ is "1". At time t₄, the disc drive 1₃ finishes the seek operation so that the flags F₁₃ and F₂₃ of the first and second registers 2 and 3 are turned "0". Consequently, the timer 5 is controlled to be reset before counting a predetermined time so that no time over signal is produced. At this time, all the flags of the second register 3 are "0" so that the content of the first register 2 is written through the control circuit 4 into the second register 3. As a result, the flags F₂₄ and F₂₅ of the second register 3 are turned "1" so that the timer 5 is controlled to count a seek time again under the condition where at least one flag of the second register 3 becomes "1". In this occasion, the timer 5 counts a seek time for the disc drives 1₄ and 1₅ . At time t₅, the disc drive 1₅ finishes the seek operation so that the flags F₁₅ and F₂₅ of the first and second registers 2 and 3 are turned "0", while the flags F₁₄ and F₂₄ of the first and second registers 2 and 3 which correspond to the disc drive 1₄ remain unchanged. Therefore, the timer 5 continues counting a seek time for the disc drive 1₄ as long as the disc drive 1₄ is ordered to conduct the seek operation. At times t₆ and t₇, the disc drives 1₁ and 1₂ are controlled to conduct a seek operation so that the flags F₁₁ and F₁₂ of the first register 2 are turned "1". In spite of the change of the content of the first register 2, the content of the second register 3 remain unchaged because the flag F₂₄ thereof are still "1". At time t₈, the value of the timer 5 becomes equal to the predetermined time so that a time over signal is produced therein to be supplied to the host processor 6. Coincidentally, the disc drive 1₂ finishes the seek operation so that the flag F₁₂ of the first register 2 is turned "0". The time over of the seek operation is detected in the disc drive 1₄ so that the flags F₁₄ and F₂₄ of the first and second registers 2 and 3 are turned "0". Therefore, the content of the first register 2 is written through the control circuit 4 into the second register 3 because all the flags of the second register 3 are "0". As a result, the flag F₂₁ of the second register 3 is turned "1" so that the timer 5 is controlled to count a seek time in the same manner mentioned before. At time t₉, the disc drive 1 finishes the seek operation so that the timer 5 is controlled to be reset. At the same time, the flags F₁₁ and F₂₁ of the first and second registers 2 and 3 are turned "0". According to the disc drives 1₁, 1₂, 1₃ ----- 1n to be controlled by the control circuit 4, the above described sequential operation will be repeated. In the first embodiment described above, it may happen that more than two disc drives associated with the second register 3 can not reach the designated tracks respectively. Even in such a case, the host processor 6 can distinguish disc drives associated with the second register 3 from other disc drives not stored therein. Further, a third register may be provided in addition to the first and second registers 2 and 3 wherein the content of the second register 3 is written into the third register when all the bits of the third register are "0". Although the disc drives are controlled in the first embodiment, other peripheral devices like a plurality of tape drives for driving magnetic tapes may be controlled according to the invention. In Fig. 3, there is shown an apparatus for controlling peripheral devices in a second embodiment according to the invention. The apparatus for controlling peripheral devices comprises a plurality of disc drives 1₁, 1₂, 1₃ ----- 1n, a disc controlling processor 30 which is fabricated as one semiconductor chip, and a host processor 36. The disc controlling processor 30 comprises input and output ports 31 and 32, a CPU 33, a RAM 34, a ROM 35, and a time base signal generator 37. The host processor 36 is connected through a bus 41 and signal line 42 to the port 31, and the disc drives 1₁, 1₂, 1₃ ----- 1n are connected through seek request signal lines 43 and seek operation signal lines 44 to the port 32. In the disc controlling processor 30, the port 31 and 32, CPU 33, RAM 34, and ROM 35 are connected by an internal bus 45. The RAM 34 includes first and second areas 34A and 34B, and timer area 34C respectively corresponding to the first and second registers 2 and 3, and timer 5 described in the first embodiment wherein each of the first and second areas 34A and 34B is of an area of the disc drives 1₁, 1₂, 1₃ ----- 1n, while the timer area 34 is of an area of bits to be decided in accordance with a predetermined seek time. In operation, the RAM 34, and ports 31 and 32 are controlled to be reset at the initial stage by the CPU 33. When the control data designating at least one of the disc drives 1₁, 1₂, 1₃ ----- 1n to be driven are supplied through the bus 41 from the host processor 36 to the port 31, the CPU 33 produces a seek request signal which is supplied through the seek request signal line 43 from the port 32 to at least one of the disc drives 1₁, 1₂, 1₃ ----- 1n. The disc drive 1k(k=1, 2, 3 -----n) which has received the seek request signal is controlled to conduct the seek operation so that a seek operation signal which is supplied through the seek operation signal line 44 to the port 32 is produced therein. Then, the seek operation signal is written into a bit corresponding to the disc drive 1k in the first area 34A of the RAM 34 so that the subject bit becomes "1". The CPU 33 scans the ports 31 and 32, and RAM 34 at a predetermined period so that designated disc drives among the disc drive 1₁, 1₂, 1₃ -----1n are controlled to conduct the seek operation in accordance with the scanning of the port 31, and the RAM 34 is controlled to store seek operation signals in accordance with the scanning of the port 32. In the RAM 34, in a case where at least one bit of the first area 34A is "1", and all the bits of the second area 34B are "0", the content of the first area 34A is written into the second area 34B, while the first area 34A remains unchanged in its stored condition. At the same time, the timer area 34C is controlled to conduct a timer operation in which the content thereof is increased at each predetermined period by one so that a time over signal is produced in the CPU 33, when all the bits of the timer area 34C become "1" to result in an over flow in that area. Before the timer operation, the time base signal generator 37 supplies a time base signal to the CPU33 so that an interrupt occurs in the CPU33. The timer operation in which the content thereof is increased is performed by counting the time base signal which is generated at the predetermined period from the time base signal generator 37. After the over flow occurs in the timer area 34, the interrupt is finished in the CPU33. When the disc drive 1k finishes the seek operation, the seek operation signal is ceased to be produced so that the bit corresponding to the disc drive 1k becomes "0" in the first and second areas of the RAM 34. When the bit in the second area 34B becomes "0", the timer area 34C is controlled to finish the timer operation so that the content thereof is reset. On the other hand, if at least one bit of the second area 34B is "1", the timer area 34C continues the timer operation. In the event, that overflow occurs in the timer area 34C, a time over signal is produced in the CPU 33 to be supplied from the port 31 through the signal line 42 to the host processor 36. In the same manner as described in the first embodiment, the content of the first area 34A is written into the second area 34B, when all the bits of the second area 34B are "0" whereby the third area 34C is controlled to conduct the timer operation again. As being apparent from the first embodiment, repeated explanations will be omitted in the second embodiment.

Claims: An apparatus for controlling peripheral devices (1₁-1 n ) comprising, means for driving a plurality of peripheral devices, first means (2, 34A) for storing units of information, each unit indicating that a peripheral device among said plurality of peripheral devices is under a predefined operation, said units of information being changed therein according to when and which one of said plurality of peripheral devices is under said predefined operation, second means (3, 34B) for storing said units of information which are written thereinto from said first means only when there is stored no units of information in said second means, said units of information being erased therein according to when and which one of said plurality of peripheral devices finishes said defined operation, and a timer (5, 34C) for counting a time during which at least one of said units of information is stored in said second means to compare said time with a predetermined time, wherein said timer produces a time over signal when said time becomes equal to said predetermined time. An apparatus for controlling peripheral devices according to claim 1, wherein said plurality of peripheral devices (1₁-1 n ) are disc drives each driving a head for writing an information into a magnetic disc or optical disc and reading an information therefrom, said first and second means are first (2) and second registers (3) respectively each having a predetermined number of bits, said predetermined number being equal to the number of said plurality of peripheral devices, each of said predetermined number of bits being "1" when a corresponding one of said disc drives is under a seek operation, and said timer (5) counts a seek time of one of said disc drives stored in said second register. An apparatus for controlling peripheral devices (1₁-1 n ) according to claim 1, wherein said plurality of peripheral devices are disc drives each driving a head for writing an information into a magnetic disc or optical disc and reading an information therefrom, said first and second means are first (34A) and second (34B) areas of a random access memory respectively each area having a predetermined number of bits, said predetermined number being equal to the number of said plurality of peripheral devices, each of said predetermined number of bits being "1" when a corresponding one of said disc drives is under a seek operation, and said timer is a third area (34C) of said random access memory which is increased in its content at a predetermined period by one bit. An apparatus for controlling peripheral devices according to claim 1 further comprising, third means for storing said units of information which are written thereinto from said second means when there is stored no unit of information therein, one of said units of information being erased therein when one of said plurality of peripheral devices finishes said predetermined operation, wherein said timer counts said time during which said units of informations are stored in said third means.

Inventors: ARAI, TOMOHISA C/O NEC CORPORATION, TANAKA, SHIGENOBU C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1987
Main classification: G11B20
IPC codes: G11B20, G06F11, G06F3