Data processing system and method for the direct and indirect execution of uniformly structured object types

Abstract: In a data processing system, uniformly structured objects are indifferently mixed in object memory with object pointers. The objects address prologues of object execution sequences in memory. The object pointers address other objects. The objects are properly evaluated whether directly or indirectly addressed. A pointer selectively points to or addresses objects or object pointers. When an object is directly addressed by the pointer, the addressee of the object's addressee in memory is addressed which initiates the object execution sequence. When an object is indirectly addressed, the pointer addresses an object pointer. The object pointer addresses an object. The object's addressee in memory is addressed which initiates the object execution process. which initiates the object execution process.

Description: This invention relates generally to systems and methods for data processing and more particularily to systems and methods for performing arithmetic and other data processing operations on pluralities of uniformly structured data objects, stored in an area of main or auxilliary memory, for example, and additionally to arrangements and methods for sequentially or selectively evaluating each of the objects. Background Art In prior art data processing systems, as described in the publication Structured Computer Organization, Andrew S. Tanenbaum, Prentice-Hall, New Jersey, USA, 1976, there are two principle processing methods or architectures used in evaluating data. These are direct evaluation schemes and indirect evaluation schemes. In the direct evaluation schemes of the prior art, the interpreter pointer, which determines the order of evaluation of the objects, always points directly at the object. That is, it never points at a pointer to the object, that is, an object pointer. When the object is evaluated, code or data associated with the object is executed and the interpreter pointer is updated to address the next object in the sequence of objects. In the indirect evaluation schemes of the prior art, the interpreter pointer always points at a pointer to the object. When the object is evaluated, the code or data associated with the object is executed and the interpreter pointer is updated to address the next pointer. In the direct evaluation scheme in prior art devices, the simple inclusion of a pointer amoung the data objects would lead to the misinterpretation of the object and consequential undesired results. Similarly, in the indirect case in prior art devices, the simple inclusion of an object amoung the pointers would also lead to undesirable effects. In prior art data processing systems, there have been several attempts at ameliorating the above described deficiency. In particular, in the direct evaluation scheme, occasionally there has been introduced the concept of an object whose body is interpreted as a pointer. This object, however, cannot itself be indirectly evaluated. In the indirect evaluation schemes, in the prior art, the notion of an indirect object with a body embedded in the execution sequence is fairly standard. This has the severe shortcoming, however, that its location, that is, directly in the evaluation sequence, is fixed by its structure and such an object can only be evaluated in this peculiar indirect-with-an-embedded-body manner. Disclosure of Invention Improvements over such typical prior art as described above are achieved with the inventive data processing system according to claim 1 and the object execution process of this invention as recited in claim 8, which provide for correct and automatic evaluation of both objects and object pointers which are now indifferently included in the execution sequence. Moreover, the objects are provided with a uniform structure so that all objects can be indifferently executed, either directly or indirectly. Objects of different types are still uniformly structured. Each comprises at least a prologue address and a body. These two parts are contiguous in memory. The prologue address addresses a prologue which describes execution of the object. The body is data. An object is pointed to, or addressed, if its prologue address part is pointed to or addressed. The object may be a single object or a composite object. If its body is a sequence of objects and/or object pointers it is a composite object. In the direct execution of an object, an interpreter pointer points to the prologue address of an object. This prologue address addresses a prologue of object execution in memory which directly identifies an object to execute. In indirect execution of an object the interpreter pointer points to an object pointer which in turn points to or addresses the prologue address of an object which is the object to execute. Since the object pointer does not address a prologue in memory, there is no direct identification of an object to execute. Thus in providing uniformity of structure among the objects, in which each comprises a prologue address and a body, in the provision of prologues of object execution and in the use of object pointers and interpreter pointers in which interpreter pointers and object pointers may selectively identify objects by pointing to their prologue address parts and, additionally, in which an interpreter pointer may point to an object pointer, a simple technique is provided, permitting intermixing of objects and object pointers for direct or indirect object execution with a minimum of processing steps. This reduces programming and conserves memory which significantly reduces processing overhead. Brief Description of Drawing Figure 1, conceptually depicts the unique structure of an object according to this invention. Figure 2, illustrates the initiation of direct object execution using a composite object structured according to this invention. Figure 3, illustrates initial steps in indirect object execution using a composite object structured according to this invention. Figures 4a, 4b and 4c, depict differing object sizing techniques providing object size information used in incrementing pointers. Figure 5, is a general block diagram of a data processing system having architecture, comprising: objects in memory, pointers, counters and processing capabilities for implementing this invention. Figures 6a through 6e, illustrate the respective process steps, together with the data processing components and their organization, in the unique direct execution of an object according to this invention. Figures 7a through 7e, illustrate the respective process steps, together with the data processing components and their organization, in the unique indirect execution of an object according to this invention. Figures 8a through 8d, are execution sequence flow charts, further developing the unique object execution steps and data processor organization of Figures 6a through 6e and 7a through 7e; and Figures 9a and 9b, is a flow chart of a program for incrementing the interpreter pointer. Best Mode for Carrying Out the Invention This invention provides an object storage area and an immobile code area in which object execution or processing instructions are stored. Objects and object pointers are stored together indifferently in the object storage area. Each object comprises a prologue address addressing a location in the immobile code area. Each object pointer addresses an object in the object storage area. The immobile code area comprises one area, called a prologue, storing object execution sequences and a second area storing prologue redirection sequences. The object addresses are called prologue addresses. Each prologue location addressed by a prologue address, addresses the prologue redirection sequence. An interpreter pointer addresses objects and object pointers selectively. When an object is addressed by the interpreter pointer, its prologue address addresses a prologue location which in turn addresses the prologue redirection sequence. This, among other functions, identifies and initiates the direct execution of an object involving redirection sequences and execution sequences. Object pointers used in indirect object execution are stored among the objects. Each object pointer addresses a specific object. When the interpreter pointer points to an object pointer, a specific object is indirectly addressed, i.e., the prologue address of that specific object is indirectly addressed. The prologue address of that specific object, again, addresses a prologue location. This, among other functions, identifies and initiates indirect object execution which differs from direct object execution and does not involve the redirection sequences. Definitions Prologue Redirection Sequence (PRLG) The prologue redirection sequence is in the immobile code area or memory at a fixed location which is determined by a prologue initialization sequence (IS). The prologue redirection sequence PRLG adjusts an interpreter pointer by a microprocessor word length to point past the body of an object and redirects execution to the data processing segment of the prologue. Prologue The prologue is any code slice in the immobile code area or memory and comprises a prologue initialization sequence (IS), an indirect adjustment sequence (AS) and a data processing sequence (PS). The prologue initialization sequence IS is the address of the prologue redirection sequence PRLG. This initialization sequence serves the dual purpose of causing the prologue redirection sequence PRLG to be executed when an object is directly addressed and executed, and causes the prologue indirect adjustment sequence AS to be executed instead when an object is addressed indirectly, via an object poiter. The prologue data processing sequence (PS) carries out conventional data processing for any type of object. Object An object comprises a prologue address and a body which is data. The prologue address and the body are contiguous in object storage or memory. The prologue in the immobile code area or memory as described above distinquishes objects from object pointers. The objects may be of different types. The different types, while uniformly structured, being classified or distinguished by the prologue address. Thus two objects are of the same type if the prologue address parts are equal. In this case the bodies will have the same logical structure. Therefore, a prologue address serves the dual prupose of initiating object execution and identifying the object type. Figure 1, conceptually depicts an object in its simplest form, in object storage or memory, comprising a prologue address and a body. Figures 2 and 3 depict composite objects in object storage or memory. Pointer A pointer as employed in this application is defined to be an address and may be either a location pointer or an object pointer. A location pointer addresses any segment of the memory map while an object pointer specifically addresses an object. The importance of this distinction is evident in the execution of an object, as will become apparent, wherein an interpreter pointer I, which directs interpretive execution, addresses the prologue address of an object in direct execution, and addresses an object pointer, which in itself is an address and specifically addresses an object, in indirect object execution. The prologue address part of an object is a location pointer. The interpreter pointer I, as used herein, is the address of the next object or object pointer OP in an executing object. The current object pointer O (not object pointer OP), as used herein, is the address of the current object which is being executed. Direct/Indirect Object Execution Figures 2 and 3 respectively illustrate the initiation of direct and indirect object execution. These figures depict composite objects in the object area of memory. These composite objects comprise an indifferent mix of objects and object pointers. All objects comprise the prologue address and body shown in Figure 1, although, in Figure 2, only the selected object is shown in this detail. In Figure 2, the interpreter pointer I points to the prologue address of the selected object which is identified as the object to execute. In Figure 3, the interpreter pointer I points to an object pointer OP which points to the prologue address of the object to execute and thus indirectly selects the object to execute. As will be explained, a program counter initiates object execution, referred to as the start of the inner loop. In direct object execution, Figure 2, the interpreter pointer I points to the prologue address of an object in the object area of memory, which object comprises the illustrated prologue address and the body and is identified as the object to execute by direct object execution. Briefly stated, the inner loop is the interpretive mechanism by which the components of the object area are sequentially or selectively executed. These components may be either objects or object pointers. In the former case, the object itself is executed by the inner loop and this is defined to be direct object execution. In the latter case, the object addressed by the object pointer is executed by the inner loop. This latter case is depicted in Figure 3, and is defined to be indirect execution. In direct execution, the inner loop sets a current object pointer O to the prologue address of an object in immobile memory and increments the interpreter pointer I to point to the body of the object in object memory. The inner loop then loads a program counter with the contents of the immobile memory location addressed by the current object pointer O which is thereafter incremented to point to the rest of the executing prologue which is then, of course, executed. In the case of indirect execution, the inner loop is executing an object pointer. Figure 3 depicts a portion of the object storage area or memory, at the start of the inner loop. Here, the interpreter pointer I points to an object pointer OP, which in turn points to the prologue address of the object to execute, which prologue address determines the type of the object. As will be explained, the inner loop loads the current object pointer O with the contents of the object pointer OP (or the prologue address) which is pointed to by the interpreter pointer I. The object pointer OP contains the address of the object to be executed. The interpreter pointer I is now incremented to point past the object pointer and a program counter is loaded with the contents of the memory addressed by the current object pointer O, the prologue address, to point to a first part of a prologue having a data processing sequence and is thereafter incremented to point to the rest of the executing prologue which is then, of course, executed. All prologues are location-fixed, that is, either reside at fixed addresses in immobile memory, or are logically implemented in a list of small program steps called Microcode, or in hardware. Object Sizes In incrementing the interpreter pointer I, the current object pointer O, and the program counter PC, it is necessary to know the size of the individual objects. Figures 4a, 4b and 4c depict three different object sizing techniques. In Figure 4a, the size of the object is determined by the prologue alone. In Figure 4b, the size of the object is determined jointly by the prologue and a length indicator in the object body. This object is defined as a counted size object. In Figure 4c, which depicts a composite or secondary object. the size is determined recursively from the sizes of all of the objects and object-pointers which comprise the object, up to and including the end-marker which has a structure corresponding to the prologue. The end marker is defined as a fixed object or object-pointer. Data Processing System Figure 5, is a block diagram of a data processing system DPS for implementing the presently preferred embodiment of this invention. The data processing system DPS includes a micro processor MP, a read only memory ROM, and a random access memory RAM, all of which are interconnected by a bus B. The microprocessor MP, includes an arithmetic logic unit ALU, an interpreter pointer I, a current object pointer O, a program counter PC, an internal read only memory IROM, and an internal random access memory IRAM. The internal random access memory IRAM, comprises an auxilliary register AR and an internal counter IC. The bus B, provides bi-directional connections with the random access memory RAM, the read only memory ROM, the microprocessor MP, and an input/output device I/O. The bi-directional coupling between the bus B and the microprocessor MP implies bi-directional connection of the bus with all of the elements of the microprocessor. Additionally all of the elements of the micropressor are bi-directional connected internally of the microprocessor, primarily for control, by the arithmetic logic unit ALU, and, additionally for access to one another, for the purpose of incrementing the interpreter pointer I, incrementing the current object pointer O, for loading, off-loading and incrementing the program counter PC, for addressing and accessing the internal read only memory IROM and for addressing and accessing the internal random access memory IRAM, its auxilliary register AR and its internal counter IC. Multiplexing in Figure 5 is simulated spatially, for drawing convenience, with separate, address, read/write and data communication links between the different resources. The arithmetic logic unit ALU initiates requests in response to inputs or as part of logical processing steps. Address and read/write commands are placed on the bus to ROM/RAM and data is returned for interpretation and loading in designated microprocessor locations. The program counter PC indicates where the data processing is and where it is going. The random access memory ROM, is also referred to herein as the immobile code area. Part of this read only memory ROM includes an object area. Frequently used objects are stored in the object area of the read only memory ROM. The random access memory RAM is primarily an object storage area in which user created objects are stored and accessed. The function of this system is primarily involved with data processing operations. These processing operations comprise the evaluation of objects. To evaluate an object means to return its value or to execute its definition. The microprocessor performs the following operations. 1. Copy the contents of the location (a place in main memory or auxilliary memory where a unit of data may be stored or retrieved) pointed to by the interpreter pointer, to the current object pointer. (O <- [I]) 2. Decode and execute the sequence of instructions residing at the location memory location addressed by the memory location current object pointer. (PC <- [O]) 3. Increment the interpreter pointer by the size of an address. The size is represented by W which is the word size of the microprocessor, for example. (I <- I + W) 4. Copy the interpreter pointer to the current object pointer. (O <- I) 5. Increment the current object pointer by the size of an address. (O <- O + W) 6. Copy the current object pointer O to an auxilliary register AR in the internal random access memory IRAM. (AR <-O) 7. Copy the contents of the location pointed to by the interpreter pointer to the auxilliary register. (AR <- [I]) 8. Set the internal counter IC to zero (0). (IC <-0) 9. Increment and decrement the internal counter IC. (IC <- IC +1) (IC <- IC -1) 10. Test and branch on the internal counter IC being zero (0). (IC = 0?) 11. Test and branch, on the value of the location pointed to by the auxilliary register AR being equal to any one of a predetermined but arbitrary set, as seen in the flow charts. (COMPOSITE ?) (END MARKER ?) ([AR] = PRLG ?) 12. Perform a sequence of data processing operations (called the prologue initialization sequence) which are non-branching, non-destructive to any of the information mentioned above and whose encoding occupies a segment at least as long as an address and whose initial segment when interpreted as an address can refer to the immobile code area. 13. Other data processing operations. Read only memory ROM preferably includes the data which comprises the immobile code area. In particular, it may include the prologue redirection sequence (PRLG) and the prologues for each of the supported object types. It may additionally contain part of the object area. The random access memory RAM preferably includes that part of the object area where new objects may be created during data processing operations. Object Execution Several typical functions of the data processing system of Figure 5 are described below. Others will be apparent as this description develops. In executing O <- [I], the following takes place: (1) ALU places the address I on the bus to ROM or RAM with an order to read. (2) The data [I] at address I is returned to ALU. (3) ALU addresses the data it has just received to the current object pointer O, Figure 6b. (See also data processing block 2, Figure 8a.) This data is an address for a location in immobile code memory, for example, and is now processed by ALU as follows: PC <- [O] (1) ALU places the address O on the bus with an order to read. (2) The data [O] at address O is returned to ALU which loads this data into the program counter PC, Figure 6d. (See data processing block 4, Figure 8a). This data is an address for a redirection execution sequence for direct object execution (Figure 6d) or an address for indirect object execution (Figure 7d). The arithmetic logic unit ALU, after execution of O <- [I] increments the interpreter pointer I, I <- I + W, by the word size of the microprocessor to point to the body of the selected object, Figure 6c. (See also data processing block 3, Figure 8a). Figures 6a to 6e, 7a to 7e, 8a to 8d, and 9a and 9b illustrate the execution sequence in the preferred embodiment of the present invention. These figures illustrate the key steps in the object execution sequence performed by the data processing apparatus as well as the organization of the essential elements of the data processor in each object execution sequence. It is apparent that this unique process and processor organization may be implemented with conventional microprocessors. Specific sequences and specific steps in evaluating the objects of this invention using an interpreter pointer I, a current object pointer O and an object pointer OP, depend upon the exact type of microprocessor which is chosen in practicing this invention. Figures 6a through 6e and 7a through 7e illustrate the key steps in the execution of an object. In these figures the interpreter pointer I addresses a memory location in the object area as depicted by the arrow. The current object pointer O addresses a memory location either in the object area of the random access memory RAM, Figure 5, or the object area of the immobile code area in the read only memory ROM, Figure 5. The program counter PC addresses a memory location in the immobile code area of the read only memory ROM, as depicted by the arrow. For simplicity, when the location addressed by one of, the interpreter pointer I, the current object pointer O or the program counter PC, is either irrelevant or may be deduced from the rest of the structure, the arrow illustrating the location addressed will be omitted. A representative seqment of the object area is illustrated in each of these figures. In particular the sequence of objects O1, O2 and O3 and object pointer OP are shown. The first object O1 comprises a prologue address P1 and a data segment comprising the body B1 whose structure is determined by the prologue P4 addressed by the prologue address P1. The second and third objects O2 and O3 similarly have prologue addresses P2 and P3 and bodies B2 and B3 whose structures are determined by the prologue P5 which is addressed by both of the prologue addresses P2 and P3. The arrow between the prologue address P1 and the prologue P4, the arrows between the prologue addresses P2, P3 and the prologue P5 and the arrows between OP and P3 symbolize the locations in immobile code area addressed by those prologue addresses. A representative segment of the immobile code area of the read only memory ROM is also illustrated in these figures. In particular, the prologue redirection sequence PRLG and the two prologues P4 and P5 are shown. The first prologue P4 includes the prologue initialization sequence IS4, the indirect adjustment sequence AS4 and the data processing sequence PS4. Similarly the second prologue P5 includes the prologue initialization sequence IS5 and indirect adjustment sequence AS5 and a data processing sequence PS5. The dashed arrows connecting the prologue initialization sequences IS4 and IS5 with the prologue redirection sequence PRLG, are meant to indicate that if the program counter PC is set to point at one of the prologue initialization sequences IS4 or IS5, as in indirect object execution, then the prologue execution sequence is executed. On the other hand, if the program counter PC is loaded with the contents of either the prologue initialization sequence IS4 or the prologue initialization sequence IS5, as in direct object execution, then the program counter PC points to the prologue redirection sequence PRLG which is then executed. The inner loop data processing functions are shown in the data processing sequences PS4 and PS5 in each of these figures. These are: O <- [I] I <- I + W PC <- [O] The execution of these individual inner loop functions is discussed above in connection with Figure 5 and hereinafter in connection with Figure 6a. Direct Object Execution Sequence Figure 6a, illustrates the initial state for direct execution. In particular the interpreter pointer I points to the prologue address P1 of the object O1 in the object area of one of the memories RAM or ROM, Figure 5. The prologue address PI addresses the prologue initialization sequence IS4 of the prologue P4. The program counter under the control of the arithmetic logic unit ALU, points to O <- [I] of the prologue P4. This initiates loading of the current object pointer O with the address [I] for IS4, as seen in Figure 6b. Figure 6b, illustrates the first step in direct object execution wherein the contents [I] of the memory location identified in Figure 6b as P1 and pointed to by the interpreter pointer I, are loaded into the current object pointer O. this is indicated by the dashed line. The result, in this case, is that the current object pointer O addresses or points to the prologue initialization sequence IS4 of the prologue P4. The arithmetic logic unit ALU increments the program counter PC to point to I <- I + W of the prologue P4 for incrementing the interpreter pointer I by a microprocessor word size. Figure 6c, illustrates the second step in direct object execution where the interpreter pointer I is incremented to point past the memory location P1 and now points at the body B1 of the first object O1. The arithmetic logic unit ALU increments the program counter PC to point to PC <- [O] of the prologue P4. Figure 6d, illustrates the third step in direct execution. Here, the arithmetic logic unit ALU responding to the instruction PC <- [O] loads the contents [O] of the prologue initialization sequence memory location IS4 pointed to by the current object pointer O, into the program counter PC. The result is that the program counter PC now addresses or points to the prologue redirection sequence PRLG and the prologue redirection sequence is executed. Figure 6e, illustrates the fourth and last step in direct execution, wherein the result of executing the prologue redirection sequence is shown. In particular, the interpreter pointer I has been incremented (Figure 8b processing block 9) to point beyond the body B1 of the object O1 and, hence, points to the object pointer OP which is next in the object area. No processing activity with respect to direct object execution is initiated by this pointing of the interpreter pointer I. The current object pointer O now points to the body B1 of the object O1 and the program counter PC points to the data processing sequence PS4 of the prologue P4. Processing of the data of the body B1 now takes place. Indirect Object Execution Figures 7a through 7e illustrate the indirect object execution sequence. In these figures, Figure 7a illustrates the initial state in which the interpreter pointer I points to an object pointer OP which in turn points to the prologue address P3 of the object O3. As in direct object execution, here also the program counter PC initiates execution of O <- [I] but in prologue P5 which is addressed by the object O3. Figure 7b, illustrates the first step in indirect object execution. The arithmetic logic unit, responding to the execution sequence O <- [I], loads the contents [I] now the address of the prologue address P3 of the object pointer OP into the current object pointer O, as indicated by the dashed line. The result is that the current object pointer O points to the prologue address P3 of object O3. The program counter PC is incremented and initiates execution of I <- I + W of the prologue P5. Figure 7c, illustrates the second step in indirect object execution. The interpreter pointer I is incremented by the arithmetic logic unit ALU, responding to the execution sequence I <- I + W, to point past the memory location of object pointer OP and now points at the prologue address P2 of the object O2. No further activity in the processing of object O3 results from this incrementation of the interpreter pointer I. The program counter PC is incremented and initiates execution of PC <- [O] of the prologue P5. Figure 7d, illustrates the third step in indirect object execution. The arithmetic logic unit ALU, responding to execution sequence PC <- [O], loads the prologue address P3, which is [O], into the program counter PC. The result is the program counter PC now points to the prologue initialization sequence IS5 of the prologue P5 and that prologue execution sequence is executed. Figure 7e, illustrates the fourth step in indirect object execution wherein the result of executing the prologue initialization sequence IS5 is shown. In particular, the current object pointer O has been incremented to point past the prologue address P3 and, hence, points to the body B3 of the object O3. The program counter PC has been incremented and now points to the data processing sequence PS5 of the prologue P5. Processing of the data of the body B3 now takes place. Data Processing Flow Charts Figures 8a through 8d and 9a and 9b are flow charts of the operation of a data processing apparatus in accordance with the present invention. Only those portions of the data processing operations which are relevant to the present invention are outlined in these figures. Other data processing operations being conventional in nature, are not illustrated. The flow charts of figures 8a through 8d, 9a and 9b depict a preferred embodiment of the key steps employed in practicing this invention. Figures 8a through 8d illustrate the flow chart of the operation involved in automatic, combined, direct and indirect object execution, in accordance with this invention. Since this is a repetitive execution loop, a conventional entry has been chosen to agree with Figures 6a and 7a. Initial Processing Phase (Inner Loop Figure 8a, illustrates the initial segment of the flow chart with the conventional entry point at connector C1. In the first processing block 2, the contents [I] of the memory location P1 addressed by the interpreter pointer I are loaded into the current object pointer O under the control of arithmetic logic unit ALU as explained in connection with Figure 5. In the second processing block 3, the interpreter pointer I is incremented by the word size W of the microprocessor MP. In the third processing block 4, the program counter PC is loaded with the contents [O] of the memory location addressed by the current object pointer O. In the examples described above, in direct object execution the memory location is IS4 and in indirect object execution the memory location is P3. In the case of direct object execution, this implies that the prologue redirection sequence PRLG will be executed next ([O] addresses PRLG, Figure 6d), and, in the indirect object execution case, this implies that the prologue initialization sequence IS5 will be executed next ([O] addresses AS5, Figure 7d). This situation is indicated by the connectors C5 and C6. Prologue Redirection Sequence (Direct Execution) Figure 8b, illustrates the operation of the prologue redirection sequence PRLG and deals with direct object execution, Figures 6a through 6e. This sequence is entered via the connector C2 from the connector C2 of Figure 8a. In the first processing block 7, the value of the current object pointer O is loaded into an auxilliary register AR (Figure 5). This value is called O′ for convenience. In the second processing block 8, the value of the interpreter pointer I is loaded into the object pointer O, which now points to the body of the object O1, Figure 6e. In the third processing block 9, the interpreter pointer I is incremented to point beyond the body of the object. This is also seen in Figure 6e. This is based upon the value O′ in the auxiliary register AR. A flow chart illustrating this process is shown in figures 9a and 9b, yet to be discussed. In the fourth processing block 10, those operations are done which are necessary to adjust for the fact that the prologue initialization sequence has not been executed. These are convential in nature and depend strongly on the details of the prologue operations assigned to the prologue. Connector C4 connects the processing block 10 to the data processing block 17 of Figure 8d. Operation Of A Prologue (Indirect Execution) Figure 8c illustrates the operation of a prologue. This sequence is entered via the connector C3 from connector C3 of Figure 8a, in the case of indirect execution. In the first processing block 13, the prologue initialization sequence is performed (Figure 7d). This is conventional in nature and depends strongly on the detail operations of the microprocessor MP. In the second processing block 14, the current object pointer O is incremented to point past the memory location that it currently addresses (Figure 7e). Execution continues with the data processing operations assigned by the prologue. Connector C4 connects the processing block 14 to the processing block 17 of Figure 8d. Figure 8d, illustrates the final part of the object execution sequence. It is entered via connector C4 from connector C4 of Figure 8b in the direct object execution case and from connector C4 of Figure 8c in the indirect object execution case (Figures 6e and 7e). In this sequence, conventional data processing operations assigned to the prologues (PS4 or PS5) are carried out by processing block 17 and execution returns via connector C1 to the conventional entry point at connector C1 of Figure 8a. Processing Program The flow chart of Figures 9a and 9b illustrates a program embodied in the operations of the processing block 9 of figure 8b. This is the processing block in which the interpreter pointer I is incremented to point past the object body based on the value of O called O′ which is stored in the auxilliary register AR. Entry to this program is via an entry point 19. As a first step, in the processing block 20, the internal counter IC (Figure 5) is set to zero. Next, in the decision block 22, the program tests to determine whether the value O′, in the auxilliary register AR, addresses a composite class prologue. In the event that the value O′ in the auxilliary register AR does not address a composite class prologue, the program increments the interpreter pointer I by an amount determined by where if O′ addresses a prologue which characterizes a fixed-size object, Figure 4a, then is that fixed size, or, if O′ addresses a prologue which characterizes a counted-size object, Figure 4b, then is computed from the length indicator which is currently addressed by the interpreter pointer I (process block 25). Next the program tests whether the internal counter IC is zero (decision block 27). In the event that the internal counter IC is zero, the program exits at exit terminal block 28. In the contrary event the program continues via connector C7 to connector C7 of Figure 9b. In the event that the value O′ in the auxilliary register AR does not address a composite class prologue, as determined by decision block 22, the internal counter IC is incremented (process block 23) and the program continues via connector C7 from process block 23 to connector C7 of Figure 9b. In either of the non-terminal cases described above the program next loads the auxilliary register AR with the contents [I] of the memory location addressed by the interpreter pointer I, as indicated in process block 31, and increments the interpreter pointer I to point past this memory location, as indicated by process block 32. The program then tests whether the auxilliary register AR addresses and end marker of a composite object (Figure 4c), as seen in decision block 33. In the event that the contents [I] of the auxilliary register AR address an end marker, the program decrements the counter, as seen in process block 34, and continues via connector C6 to connector C6 of Figure 9a. In the event that the contents of the auxilliary register AR do not address an end marker, as determined by the decision block 33, the program tests whether the auxilliary register AR addresses an object (as opposed to an object-pointer), as seen in decision block 36. That is, if the contents [I] of the memory location O addressed by the value O′ of the auxilliary register AR, in turn addresses a memory location IS4 the contents [O′] of which is the address of the prologue redirection sequence PRLG, then the auxilliary register AR addresses an object, otherwise it addresses an object pointer OP. In the event that the contents of the auxilliary register AR address an object, the program continues via connector C5 to the connector C5 of Figure 9a. In the event that the auxilliary register AR does not address an object, as determined by decision block 36, the program reexecutes the sequence from process block 31 on. The provision of having prologues whose prologue initialization sequences comprise the address of the prologue redirection sequence PRLG and microprocessor executable instructions for object executions, is a feature which allows both direct and indirect object execution. The uniform structure of the objects, as evidenced in Figures 4a through 4c, in which each object comprises a prologue address and a body, which are contiguous in memory, together with definitions of the size of each object, as defined in the prologue address, Figure 4a, or in a length indicator or in the prologue address and the length indicator, Figure 4b, or is calculatable, Figure 4c, permits sequential or selective, or skipping object execution involving specific incrementing of the interpreter pointer I. This minimizes both programming and storage or memory space, conserving processor overhead. In interpretive execution, execution of the object (direct execution) is execution of the object's prologue, and, execution of the object pointer's addressee (indirect execution) is execution of the addressee of the addressee's prologue. Although specific architectual examples and procedures have been presented herein, in describing the preferred embodiment of this invention and the best mode of practicing this invention, it will be appreciated by those skilled in the art that variations in both the architecture and procedures may be made. Industrial Applicability This invention is applicable in data processors for performing arithmetic, symbolic mathematical and other data processing operations involving the processing of defined objects.

Claims: A data processing system, comprising: a. a memory; (RAM,ROM) b. object data execution sequences in said memory; c. objects (01) and object pointers (OP) in said memory, the objects and object pointers being intermixed in the execution sequences; d. each object including a body (B1) comprising data to be processed and a location address (P1) which is the address of a location of object data execution sequences in said memory, the location address (P1) and the body (B1) being contiguous in memory; e. each object pointer (OP) including an object address which is the address of one object; f. addressing means (I) for selectively individually accessing an object (01) or an object pointer (OP) for directly or indirectly selecting one object (P3) at a time for execution, and g. means (MP, I) responsive to accessing of said one object for accessing object data execution sequences in said memory at the location address of said object which is accessed, for executing the body of data of the accessed object. The data processing system according to claim 1, in which; a. said addressing means (I) selectively, individually accesses an object (01) and an object pointer (OP) for directly and indirectly selecting one object at a time for execution. The data processing system according to claims 1 or 2, in which: a. said memory comprises an object memory for storing objects and object pointers and an object execution memory (RAM ROM) for storing object data execution sequences. The data processing system according to claims 1, 2 or 3, comprising: a. means (PRLG) for incrementing said addressing means (I) for selecting a next object (02) or object pointer (OP); b. a current object pointer (O), and c. means (PC, I) for controlling said current object pointer to access and to maintain access of said one object (01) for data execution as said addressing means is being incremented. The data processing system according to claim 3, in which: a. said object execution memory (RAM ROM) comprises memory segments (P4, P5) of data execution sequences, each object execution memory (RAM ROM) being addressed by a location address (P1, P2, P3) of an object (01). The data processing system according to claim 3, in which: a. said object execution memory (RAM ROM) comprises first memory segments (P4, P5) addressed by said location address, each memory segment comprising sections of data execution sequences, and b. a second memory segment (PRLG) for initiating incrementing of said addressing means and for controlling functions of said first memory segments for executing the body of data of a selected object. The data processing system according to claim 6, in which: a. each first memory segment (P4, P5) comprises an initialization sequence segment (IS), an indirect adjustment segment (AS) and a data processing sequence segment (PS) and an address for said second memory segment; b. said initialization sequence segment (IS) accessing said second memory segment (PRLG) to initiate incrementing of said addressing means and to redirect object data execution to said data processing segment (PS) during direct object execution and to access and initiate execution of said indirect adjustment sequence (AS) during indirect object execution. A method of processing data in a data processing system having a code memory (P4, P5) with object execution instructions and an object memory (RAM, ROM), the object memory having objects (O1), object pointers (OP), and initialization sequence (IS), a direct object execution sequence (PRLG), and an indirect object execution sequence (AS), the method comprising the steps of: a. providing the objects each with a code memory address (P1) and a body (B1) including data; b. intermixing the objects and the object pointers in object memory; c. providing an object initialization sequence at a first location (IS) in code memory (P4, P5) d. performing a direct object execution by using the contents of the object initialization sequence (IS) memory location to address the direct object execution sequence (PRLG) which is common to all direct object execution for starting the execution of an object; and e. performing an indirect object execution by using the initialization sequence (IS) to start object execution via the indirect object execution sequence (AS).

Inventors: GRODD LAURENCE, PATTON CHARLES M, WICKES WILLIAM C, GRODD, LAURENCE, PATTON, CHARLES M., WICKES, WILLIAM C.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1987
Main classification: G06F9
IPC codes: G06F12, G06F9