PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks (51, 52, 53) of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer (17) in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer (32) in contact with the epitaxial layer. Walls (61) of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon (81) in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

Description: PROCESS FOR MANUFACTURING SEMICONDUCTOR Devices Background of the Invention This invention relates to semiconductor processing and more particularly to a semiconductor process that can produce bipolar transistor and field effect transistors (BICMOS) on the same chip. Several BICMOS processes have been disclosed in the prior art which can result in a combination of bipolar and field effect transistors on the same semiconductor device. Examples of these prior art processes can be found in Patent No. 4,536,945 issued August 27, 1985 to G. Bruce et al and Patent No. 4,484,388 issued November 27, 1984 to I. Hiroshi. Both of these prior art processes have been found to be limited in producing very high-speed semiconductor devices. In both of the processes the gate structure itself is used as an alignment mechanism in determining the position of the contacts that are made to the active elements of the device. In both processes the metallic contacts are made directly to the source and drain regions. The dimension of these regions is dependent upon the precision with which a hole can be placed with respect to the gate structure. This fact causes the source and drain regions to be larger than desirable, thereby causing these regions to have a larger parasitic capacitance than desirable which in turn limits high¬ speed operation. In addition, the p-region that is established in these processes for the PMOS device is created by implanting boron directly into the semiconductor material. As is well-known in the art, the boron cannot be doped too heavily since it tends to channel quite readily through the crystalline structure of the semiconductor material during implantation thereby causing a larger junction depth than desired. On the other hand, a light doping of boron produces an element 5 of the semiconductor device which has a higher resistance than desirable. These problems are solved by the present invention. Summary of the Invention The dimensional size of the source and drain ID. and base regions is reduced in accordance with the present invention wherein stacks of materials are created over the areas of the substrate corresponding to the gate elements of the field effect transistors and the emitter elements of the bipolar transistors that are 15 to be created in the resulting devices. An insulating layer is deposited over the entire wafer including the stacks. This layer is then reactive ion etched such that the insulating layer remains only as walls around the stacks. A polycrystalline layer is then deposited 20 over the entire wafer including the walls and the stacks. Portions of this polycrystalline layer are then removed outside of the areas that define the individual transistor devices thereby, creating islands of isolated polycrystalline silicon material where appropriate. 25 " Appropriate dopants are then deposited into these islands of polycrystalline silicon material to create reservoirs of dopant materials, and the doped islands are then etched back to the point where the walls around the stacks form insulating boundaries between the 30 material within the walls and polycrystalline silicon material outside the walls. The wafer is then heated so as to drive the dopants from the polycrystalline silicon material into the substrate wherever the polycrystalline silicon material is in contact with the substrate. A 35 low resistance material is then selectively deposited over the polycrystalline silicon material so as to establish contact with the elements of the individual transistors. Brief Description of the Drawing FIGS. 1 through 13 are sectional views of a semiconductor wafer showing various processing steps for manufacturing a BICMOS structure. Detailed Description Techniques well-known to those in the semiconductor processing art are used to create a semiconductor wafer having a cross-section of the type illustrated in FIG. 1. In brief, a p-type semiconductor silicon wafer is cleaned, and an oxide layer is deposited thereon which layer is etched in accordance with a mask to expose surface areas of the wafer 12. Arsenic is then implanted into these areas and driven into the wafer structure to create n+ buried wells 11 and 12. After the oxide layer is removed, a p-type epitaxial layer of about 1 μm is grown over the wafer. Areas corresponding to n wells 13 and 14 in FIG. l, . are defined using a mask and a photolithography process step and then the wells are created by driving in a phosphorus implant. A pad oxide growth and nitride deposition are then performed over the entire wafer structure followed by a lithographic step which defines all of the active areas corresponding to the NMOS, PMOS and bipolar devices that are to be created during the following steps, such areas being designed by legends in FIG. 1. The areas in between the devices corresponding to the field isolation regions 16 can then be selectively etched and filled in with a field oxide growth thereby isolating the active elements. The next mask can then be used to block out the wells corresponding to the PMOS and bipolar devices, and the NMOS device is exposed to a doubly ionized boron implant in order to isolate the NMOS device. Removal of the pad oxide and nitride stacks can then be performed, followed by a sacrificial oxide growth which is removed followed by a gate oxide growth of about 200 angstroms, thereby creating the oxide regions 17 in FIG. 1. Finally, a deposition of polycrystalline silicon (POLY) material is created over the entire wafer in order to provide 5 layer 18, which layer has a dimension of about 50 nm. All of these processing steps described thus far are well-known to those skilled in the silicon semiconductor processing art and are similar to those that have been described in prior art patents relating to this 10" technology. After forming the wafer illustrated in FIG. 1, a lithography technique is used to establish a photoresist layer 21 (FIG. 2) over the bipolar active elements on the wafer thereby blocking them from 15 subsequent implantation of the dopant. Ionized boron, B+, is then implanted at a dose of about 8x10' ' to 2x10 12 atoms/cm 7 with an energy of 30 to 100 KeV. As a result, a threshold implant is established for the MOS devices on the wafer. The photoresist layer 21 is then 20 stripped from the wafer, and a photolithography step is then used to create another photoresist layer 31 (FIG. 3) over the areas of the wafer corresponding to the MOS devices. The polycrystalline silicon layer (18) covering the bipolar devices is etched, and a wet oxide 25 etch of BHF is used to remove the gate oxide layer (17) over the bipolar devices, thereby exposing the n-type layer corresponding to the area 14 of the substrate. A boron fluoride, BF-, implant can then be made at a dopant level of 1 to 5 x 10 13 atoms/cm 2 and an 3.0 energy of 25 to 50 KeV in order to create a p-type layer 32 which will eventually serve as the base of the bipolar device. The photoresist layer 31 is then stripped from the wafer and a polycrystalline silicon layer 41 (FIG._4) of 350 nm is then deposited over the 35 entire wafer. This polycrystalline silicon layer also increases the thickness of the polycrystalline silicon layer 18 remaining over the MOS devices. This entire polycrystalline silicon layer 41 is then implanted with an arsenic dopant having a dosage of 1 x 10 atoms/crrr at an energy of about 40 KeV. As a result, the entire polycrystalline silicon layer 41 is embedded with an n- type dopant. This dopant reservoir in layer 41 will subsequently serve as the source of dopant material for the creation of an emitter over the base layer 32 of the bipolar device. A silicon nitride layer 42 is then deposited with a thickness of about 50 to 100 nm over the entire wafer, and a polycrystalline silicon layer 43 is also deposited over the entire wafer with a thickness of about 600 nm. A photolithography step, including reactive ion etching, is then used to define the stacks of material designated in FIG. 5 by the numerals 51, 52 and 53. These stack formations are positioned over those areas of the wafer which will eventually correspond to the gate electrodes of the MOS devices and the emitter electrode of the bipolar devices. A conformal oxide 61 which will serve as the sidewall oxide is then deposited over the entire wafer to a thickness of about 200 nm as indicated in FIG. 6. An anisotropic reactive ion etching process is then used to remove portions of the oxide. This reactive ion etching process removes all of the oxide which was deposited over the tops of the stacks 51, 52 and 53 and all of the oxide between the walls of oxide adjacent to the stacks thereby resulting in silicon dioxide walls 71 surrounding the stacks as indicated in FIG. 7. This sidewall formation results due to the highly directional nature of the reactive ion etching process. The wafer is then cleaned and a polycrystalline silicon layer 81 having a thickness of 200 nm is deposited over the entire wafer as shown in FIG. 8. A photolithography process is used to define the polycrystalline layer between active devices. The polycrystalline silicon is etched isotropically so that individual devices are isolated. As indicated in FIG. 9, a next photolithography step defines photoresist layer 91 which covers the PMOS and bipolar devices thereby permitting the polycrystalline silicon layer covering the NMOS devices and the collector region 15 of the bipolar device to be implanted with a phosphorus ion implant. This phosphorus ion implant is delivered at a dose of 1 to 5 x 10 15 atoms/cm 2 and an energy of 25 to 75 KeV to create an n+ doping of the polycrystalline layers covering the collector region 15 and the NMOS device areas. Photoresist layer 91 positioned over the PMOS and bipolar devices is then stripped. A next photolithography step is then used to establish a photoresist layer over the NMOS active devices and the collector region 15 thereby establishing a photoresist layer 95 in FIG. 10 which is the complement of the one shown as 91 in FIG. 9. The PMO * S and bipolar devices are then exposed to a boron fluoride BF- ion implant having a dosage of 1 to 10 x 10-' • atoms/cm 2 and an energy of 25 to 35 KeV as shown in FIG. 10. This BF 2 implant causes the polycrystalline material covering the PMOS and parts of the bipolar devices to achieve P+ type doping. The photoresist is then removed. The entire wafer is then covered (FIG. 11) with a silicon nitride deposition (102) having a thickness of about 80 nm. This silicon nitride deposition will protect the polycrystalline silicon in a subsequent step during which a photoresist layer is selectively etched back. The next step in the process requires that a planerizing photoresist material with a uniform thickness of 3 to 5 μm be applied to the entire wafer, resulting in photoresist layer 101 in FIG. 11. This photoresist layer 101 is then etched back to a point where the tops of the stacks 51, 52 and 53 are clearly exposed. The cross-sectional view of the wafer is not as yet as shown in FIG. 12 since the nitride layer and polycrystalline silicon layer are still covering the tops of the silicon dioxide walls. At this point, the exposed silicon nitride is removed by using a reactive ion etching process which results in the removal of about 80 nm of material. The remaining photoresist material is then hardened and the exposed polycrystalline material is etched back. The remaining photoresist material is then removed. The critical areas of polycrystalline material which remain are those shown and designated in FIG. 12 as areas 111, 112, 113 and 114. Areas 111 of polycrystalline material surrounding the silicon dioxide walls for the NMOS device were previously exposed in the step corresponding to FIG. 9 to a dopant of phosphorus ions thereby' resulting in a reservoir of n-type dopant in this polycrystalline mate-rial. Areas 112 and 113 of polycrystalline material surround the silicon dioxide walls corresponding to the PMOS and bipolar devices. These areas of polycrystalline material were implanted in the step corresponding to FIG. 10 with a boron fluoride dopant, thereby making these areas reservoirs of p-type material. In addition, the polycrystalline material designated as area 114 in the cross-section shown in FIG. 12 is what remains from the polycrystalline silicon which was deposited as layer 41 in FIG. 4 and implanted with arsenic so as to create a reservoir of n-type material. At this point in the process the entire wafer is heated to a temperature of about 950 degrees Centigrade for about 60 minutes in order to cause these reservoirs of implanted dopants to diffuse into the silicon substrate thereby creating source and drain regions 115, 116, 117 and 118, the extrinsic base region 119, and a region 120 under stack 53 of the bipolar device, thereby creating an emitter base junction between it and the p-type base region 32 previously created. A wet etch of phosphoric acid at 155 degrees in a reflux system is then performed to remove the remaining silicon nitride over the entire wafer. The wafer is then subjected to a selective deposit of tungsten or to a self-aligned suicide reaction thereby creating a conductive deposit 121 having a thickness of about 100 nm over all of the exposed areas of polycrystalline silicon as shown in FIG. 13. The protruding oxide wall structures improve the selective process so that no conductive material will form or remain over the areas of silicon dioxide. The entire wafer can then be annealed in order to reduce the resistivity of the conductive material. The high oxide wall protruding above the gate surface is removed using a wet oxide etch. After cleaning the entire wafer, a CVD deposition creates a layer of silicon dioxide 138 over the entire wafer as shown in FIG. 14, thereby joining the silicon dioxide walls with the field oxides that separate the individual elements of the device. This silicon dioxide layer has a thickness of about 400 nm. Using a photolithography process and a mask that defines the positions of the holes that are to be created in this silicon dioxide layer to make contact to the previously deposited conductive materials, a combination of a wet etch and reactive ion etch can be used to create the holes through the silicon dioxide 138 down to the level of the tungsten or suicide deposit. The photoresist material used during the lithography step is then removed. Finally, aluminum is deposited and patterned to form the electrodes shown as 131 through 136 in FIG. 14. Contact to the emitter and collector elements of the bipolar device can be made in a similar fashion in a plane not shown in the FIG. 14 cross- section. The wafer is then heated in a final sintering step. The inventive process is equally applicable to a semiconductor wafer wherein only field effect transistors are created. in this case, the stacks of semiconductor material are positioned over the gate structures only and the steps necessary for the processing of the bipolar devices may be eliminated. The self-aligned polysilicon contact still results in lowering the source and drain capacitance of the field effect transistors that are much closer than the spacing that can be achieved in prior art processes. Similarly," the process may be applicable to bipolar devices alone and the emitter-base structure created by the process is again lower capacitance and resistance, and therefore capable of operating at higher speeds, than the devices produced in prior art processes.

Claims: Cla ims 1. In a process for creating transistor devices in selected areas of a semiconductor wafer wherein stacks (51, 52, 53) of appropriate materials have been created over predetermined portions of the selected areas corresponding to elements of the transistors, the steps characterized by depositing an insulating layer (61) over the entire wafer including the stacks, directionally selective etching said * insulating layer such that the insulating layer remains only as walls around the stacks, depositing a polycrystalline silicon layer (81) over the wafer including the walls and stacks, removing the polycrystalline layer outside of the areas that define the individual transistors thereby creating islands of isolated polycrystalline silicon material, depositing appropriate dopants into the islands of polycrystalline silicon material, etching the doped islands of polycrystalline silicon material back to the point where the oxide walls form protruding insulating boundaries between the polycrystalline silicon material within the walLs and outside of the walls, heating the wafer so as to drive the dopants from the polycrystalline silicon material into the substrate where the polycrystalline * silicon ' aterial is in contact with said substrate, and selectively depositing a low resistance material (132) over the polycrystalline silicon material so as to establish contact with elements of the individual transistors. 2. In a process as defined in claim 1 wherein the transistor devices include both NMOS and PMOS devices and the step of depositing appropriate dopants into the islands of polycrystalline silicon material comprises the following steps: masking the areas of the semiconductor wafer corresponding to the NMOS devices, depositing a p-type implant into the polycrystalline silicon covering the areas corresponding to the PMOS devices, masking the areas of the semiconductor wafer corresponding to the PMOS devices, and depositing an n- type implant into the polycrystalline silicon covering the areas corresponding ' to the NMOS devices. 3. A process for forming field effect transistors and bipolar transistors in a semiconductor wafer characterized by the steps of creating layer (111,114) of appropriately doped polycrystalline silicon material over areas of the semiconductor wafer that are to become source and drain regions of the field effect transistors and emitter regions of the bipolar transistors, and heating the semiconductor wafer such that the dopants from the polycrystalline silicon layers are diffused into the semiconductor wafer thereby simultaneously forming the source and drain regions of the field effect transistors and the emitter regions of the bipolar transistors. 4. In a process as defined in claim 3 wherein the field effect transistors include both NMOS and PMOS devices and the step of creating layers of appropriately doped polycrystalline silicon material comprises the following steps: implanting a p+type dopant into the polycrystalline silicon material over the PMOS and bipolar devices, and implanting an n+type dopant in'to the polycrystalline silicon material over the NMOS devices. 5. In a process as defined in claim 4, where, as known, n-i- buried wells have been implanted in a p- type silicon substrate, a p-type epitaxial layer has been grown over the substrate, and field isolation regions have been created to isolate the CMOS and bipolar transistor regions on the wafer, said process characterized by the following steps: growing a gate oxide over the entire layer; depositing a polycrystalline silicon material over the entire wafer; selectively etching the wafer to remove the polycrystalline silicon layer and the gate oxide that cover areas to be occupied by the bipolar transistors; implanting a p-type dopant in the exposed epitaxial layer; depositing a polycrystalline silicon layer over the entire wafer; implanting the polycrystalline layer 5 with an n-type dopant to create a reservoir of n-type dopant; depositing a silicon nitride layer over the entire wafer; depositing a second polycrystalline layer over the silicon nitride layer; selectively etching the polycrystalline silicon and nitride layers to create 10" stacks of polycrystalline silicon and silicon nitride over the regions of the wafer corresponding to gate elements of the CMOS devices and emitter elements of the bipolar devices; depositing a conformal oxide over the entire wafer; selectively etching the entire wafer so as 15 to remove all of the conformal oxide except that which is adjacent to the stacks of polycrystalline silicon and silicon nitride to create walls of silicon dioxide around the stacks; depositing a polycrystalline silicon layer over the entire wafer; selectively etching the 20 last deposited polycrystalline silicon layer to create islands of polycrystalline silicon over the CMOS and bipolar transistors; selectively implanting an n-type dopant in the islands of polycrystalline silicon corresponding to the N OS transistors to create a 25. reservoir of n-type dopant; selectively implanting a p+ type dopant in the islands of polycrystalline silicon corresponding to the PMOS and bipolar devices to create a reservoir of p-type dopant; selectively removing the polycrystalline silicon layer to a predetermined 30 distance from the epitaxial layer such that the silicon nitride inside the walls of silicon dioxide is fully exposed; heating the wafer to pause the reservoirs of implanted dopants to diffuse into the epitaxial layer thereby simultaneously creating source and drain regions 35 for the CMOS transistors and an emitter region for the bipolar transistors; removing the silicon nitride within the walls of silicon dioxide; and depositing a conductive material over the exposed polycrystalline silicon layers in order to permit conductive coupling to the elements of the CMOS and bipolar transistors. 6. In a process as defined in claim 5 wherein the step of selectively removing the polycrystalline silicon layer to a predetermined distance from the epitaxial layer comprises the following steps: depositing a silicon nitride layer over the entire wafer; depositing a uniform thickness of photoresist material over the entire wafer; etching the photoresist material back to a point where the tops of the stacks are clearly exposed; reactive ion etching the exposed silicon nitride thereby exposing polycrystalline material; etching the exposed polycrystalline silicon material thereby exposing the silicon nitride inside the walls of silicon dioxide.

Inventors: CHIN GEN MAN, CHIU TZU-YIN, HANSON RONALD CURTIS, LAU MAUREEN Y, LEE KWING FAI, MORRIS MARK D, VOSHCHENKOV ALEXANDER MICHAEL, CHIN, GEN, MAN, CHIU, TZU-YIN, HANSON, RONALD, CURTIS, LAU, MAUREEN, Y., LEE, KWING, FAI, MORRIS, MARK, D., VOSHCHENKOV, ALEXANDER, MICHAEL
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1987
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29