Clock signal multiplexers

Abstract: A clock signal multiplexer for combining a plurality n of input clock signals (A to D) of the same frequency but differing phases into a single channel, by selectively passing one of the n input clock signals (A to D) to an output of the multiplexer to the exclusion of the other n-1 input clock signals (A to D), comprises n input circuits (1 to 4) to each of which a respective one of the n input clock signals (A to D) is supplied together with a respective clock enable signal, a logic circuit (13, 14) coupling the input circuits (1 to 4) to a signal synchronizer (15), the logic circuit (13, 14) operating to enable said signal synchronizer (15) in respect of the input clock signal (A to D) corresponding to that one of the n clock enable signals which is in a select condition, and further operating on return of the one of said clock enable signals to a non-select condition and transition of another of the clock enable signals to the select condition to disable the signal synchronizer (15) in respect of the previously selected input clock signal (A to D), and to enable the signal synchronizer (15) in respect of the input clock signal (A to D) corresponding to the other clock enable signal, and a clock signal selector (16) to which the input clock signals (A to D) are supplied and to which the signal synchronizer (15) is connected, the signal synchronizer (15) enabling the clock signal selector (16) to pass the enabled input clock signal to the output (18) of the multiplexer via a clock regenerator (17).

Description: This invention relates to clock signal multiplexers. The need to multiplex a plurality of clock signals together, that is, to combine the clock signals serially into a single channel by selectively passing one of the clock signals to the exclusion of the others, arises in various circuits. Consider, for example, a digital video tape recorder which is deriving four binary data signals via respective reproducing heads, where all four data signals are to be stored in a single memory, such as a field store. In this case, a respective clock signal will be derived from each reproduced data signal for use in controlling the memory when that data signal is to be stored. All four clock signals are of the same frequency, and ideally they will remain in a constant phase relationship, but in practice, due to jitter, this may not be so, and as a consequence there may be a clash of control of the memory. In these and other circuits there is, therefore, a requirement for a clock signal multiplexer capable of multiplexing a plurality of clock signals of the same frequency but differing phases, to provide a single output clock signal, with the assurance that the output clock signal will always be continuous, and will always contain complete clock cycles and be glitch-free. Previously proposed clock signal multiplexers, such as simple switching devices, do not provide these assurances. U.S. patent 4,521,810 discloses a simple signal multiplexer for selecting one from among several video signal sources. U.S. patent 4,229,699 discloses a clock signal multiplexer which inhibits the clock output for a sufficient time, after selecting a new signal source, to allow spurious signals and glitches to die out. According to the present invention as defined in claim 1 there is provided a clock signal multiplexer for combining a plurality n of input clock signals of the same frequency but differing phases into a single channel, by selectively passing one of said n input clock signals to an output of the multiplexer to the exclusion of the other n-1 input clock signals, the multiplexer being characterized by: n input circuits to each of which a respective one of said n input clock signals is supplied together with a respective clock enable signal; a logic circuit coupling said input circuits to a signal synchronizer, said logic circuit operating to enable said signal synchronizer in respect of the input clock signal corresponding to that one of said n clock enable signals which is in a select condition, and further operating on return of said one of said clock enable signals to a non-select condition and transition of another of said clock enable signals to the select condition to disable said signal synchronizer in respect of the previously selected input clock signal, and to enable said signal synchronizer in respect of the input clock signal corresponding to said another clock enable signal; and a clock signal selector to which said input clock signals are supplied and to which said signal synchronizer is connected, said signal synchronizer enabling said clock signal selector to pass the enabled said input clock signal to said output of the multiplexer. The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows in block form a first embodiment of clock signal multiplexer according to the present invention; Figure 2 shows waveforms of signals at various points in the circuit of Figure 1; Figure 3 shows in block form a second embodiment of clock signal multiplexer according to the present invention; Figure 4 shows waveforms of signals at various points in the circuit of Figure 3; Figure 5 shows part of the clock signal multiplexer of Figure 3 in more detailed block form; and Figure 6 shows waveforms of signals at various points in the circuit of Figure 5. Referring to Figure 1, the first embodiment of clock signal multiplexer to be described is to be used to multiplex four input clock signals A, B, C and D which are all of the same frequency, but which may vary in phase relative to each other. The input clock signals A to D may, for example, be respectively derived from four reproduced signals supplied by four heads of a digital video tape recorder; it being required that any selected one of the input clock signals A to D be supplied to an output, for example to control a data store, such as a field store, and that the output clock signal should be continuous, should only contain complete clock cycles, and should be glitch-free even when switching from one of the input clock signals A to D to another. The clock signal multiplexer comprises four input terminals 1 to 4 to which the input clock signals A to D respectively are supplied, and which are respectively connected to the clock terminals of four pulse generators 5 to 8. To the pulse generators 5 to 8 are also respectively connected four further input terminals 9 to 12 to which are respectively supplied clock enable signals EN A to EN D which, as explained below, control selection of which of the input clock signals A to D is to form the output clock signal of the clock signal multiplexer. Where some plurality of clock signals other than four are to be multiplexed, then the elements of the clock signal multiplexer so far mentioned are each provided that plurality of times. The outputs of the pulse generators 5 to 8 are connected to a combinational logic circuit 13, to which are also supplied the clock enable signals EN A to EN D from the input terminals 9 to 12. The logic circuit 13 supplies four outputs to a control signal selector 14, which supplies four outputs to a synchronizer 15, which in turn supplies four outputs to a clock signal selector 16, which supplies an output to a clock signal regenerator 17 from which the required output clock signal is derived and supplied to an output terminal 18. To the synchronizer 15 are also supplied inverted input clock signals A to D via respective input terminals 19 to 22, and to the clock signal selector 16 are also supplied the four input clock signals A to D via respective input terminals 23 to 26. The operation will now be described with reference also to Figure 2 which shows the waveforms at various points in the clock signal multiplexer of Figure 1, these points being designated with the corresponding figure numbers. The pulse generator 5, for example, receives as inputs the clock signal A (Figure 2A) and the clock enable signal EN A (Figure 2B) which is active low. The output of the pulse generator 5 is a clock enable pulse (Figure 2C). The output of the pulse generator 5 is normally low, and it produces a high pulse (Figure 2C) on the negative edge of the input clock enable signal EN A. The pulse duration is one clock cycle of the system. The pulse generators 6 to 8 operate similarly for the input clock signals B to D. The required function of each of the pulse generators 5 to 8 can, for example be realised using flip-flop circuits and NOR gates. The logic circuit 13 receives as inputs the clock enable signals EN A to EN D (for example Figure 2B) which are active low, and the clock enable pules (for example Figure 2C) from the pulse generators 5 to 8. The output signal is a control signal pulse (Figure 2D). The logic circuit 13 supplies one output signal for each input clock enable signal EN A to EN D. Each output signal is normally high, but a low control signal pulse (Figure 2D) is produced on a given one of the four outputs in response to a high pulse on the respective clock enable pulse input, provided that all the input clock enable signals (EN A to EN D) not relating to the given output are high. The required function of the logic circuit 13 can, for example, be realised using NAND gates. The control signal selector 14 receives as inputs the control signal pulses (Figure 2D) from the logic circuit 13, corresponding to the input clock signals A to D, and it supplies output control signals (for example Figure 2G), there being one for each of the input clock signal A to D. For a given input control signal pulse (Figure 2D), the control signal selector 14 produces a low control signal (for example Figure 2E) on the respective output in response to low on the respective input. At the same time, it causes all the other output control signals to go high. The required function of the control signal selector 14 can, for example, be realised using flip-flop circuits and AND gates. The synchronizer 15 receives as inputs the four control signals (for example Figure 2E) from the control signal selector 14 and also be four inverted input clock signals A to D . The outputs are four synchronized control signals (for example Figure 2F). The synchronzer 15 thus synchronizes the input control signal to the falling edge of the respective input clock signal A to D. The required function of the synchronizer 15 can, for example, be realised using flip-flop circuits. The clock signal selector 16 is basically a multiplexer and receives as inputs the four synchronized control signals (for example Figure 2F) from the synchronizer 15 and the input clock signals A to D. The output is an intermediate output clock signal (Figure 2G). Thus the clock signal selector 16 combines the input clock signals A to D according to the input synchronized control signals (for example Figure 2F). The required function of the clock signal selector 16 can, for example, be realised using AND gates and OR gates. The clock signal regenerator 17 receives as an input the intermediate output clock signal (Figure 2G) from the clock signal selector 16, and supplies as an output the output clock signal (Figure 2H). The clock signal regenerator 17 maintains the required mark/space ratio of the output clock signal and removes glitches. The output clock signal is thus continuous and always contains complete clock cycles even when there is a transition from one input clock signal to another. This latter point will be more fully described in relation to the second embodiment, which is shown in Figure 3 and which will now be described. In the second embodiment the individual circuits of the clock signal multiplexer are shown in more detail, but it is emphasized that this is only by way of example as the required functions can be realised in other ways. The second embodiment of clock signal multiplexer comprises four input terminals 31 to 34 to which the input clock signals A to D respectively are supplied, and which are respectively connected to the clock terminals of four D-type flip-flop circuits 35 to 38. To the D input terminals of the flip-flop circuits 35 to 38 are respectively connected four further input terminals 39 to 42 to which are respectively supplied clock enable signals EN A to EN D which, as explained below, control selection of which of the input clock signals A to D is to form the output clock signal of the clock signal multiplexer. Respectively associated with the flip-flop circuits 35 to 38 are four two-input NOR gates 43 to 46 and four four-input NAND gates 47 to 50. The Q output terminals of the flip-flop circuits 35 to 38 are respectively connected to one input of the associated one of the NOR gates 43 to 46, the outputs of which are respectively connected to one input of the associated one of the NAND gates 47 to 50. The further input terminals 39 to 42 are also respectively connected to the other input terminal of the associated one of the NOR gates 43 to 46, and to a respective one of the input terminals of each of the three non-associated NAND-gates 47 to 50. The flip-flop circuit 35 and the NOR gate 43, for example, form a pulse generator, and the NAND gates 47 to 50 form a combinational logic circuit. The output of the NAND gate 47 is connected to the set terminal of a D-type flip-flop circuit 51, the Q output terminal of which is connected to the D input terminal of a D-type flip-flop circuit 55, the Q output terminal of which is connected to one input of a two-input AND gate 59. The outputs of the NAND gates 48, 49 and 50 are similarly connected to similarly-connected D-type flip-flop circuits and two-input AND gates 52, 56 and 60; 53, 57 and 61; and 54, 58 and 62, respectively. Four three-input AND gates 63 to 66 have their outputs connected to the clear terminals of the flip-flop circuits 51 to 54, respectively. The outputs of the NAND gates 47 to 50 are also connected to the respective inputs of the AND gates 64, 65 and 66; 65, 66 and 63; 66, 63 and 64; and 63, 64 and 65, respectivley. The input terminals 31 to 34 are respectively connected to the other input terminals of the AND gates 59 to 62. Four further input terminals 67 to 70 to which inverted input clock signals A to D respectively are supplied, are respectively connected to the clock terminals of the flip-flop circuits 55 to 58. The outputs of the AND gates 59 to 62 are respectively connected to the four inputs of an OR gate 71, the output of which is connected by way of a clock signal regenerator 72 to an output terminal 73. The flip-flop circuits 51 to 54 are the AND gates 63 to 66 form a control signal selector, the flip-flop circuits 55 to 58 form a synchronizer, and the AND gates 59 to 62 and the OR gate 71 form a clock signal selector. The operation will now be described with reference also to Figure 4, which shows the waveforms of signals 4A to 4L at various similarly-designated points in the circuit of Figure 3. The operation will be described in particular for use two of the input clock signals A to D, but from this the way in which the circuit operates for all four (or for any different plurality of input clock signals) will be readily apparent. The two input clock signals A and B (Figures 4A and 4B) are supplied to the input terminals 31 and 32 respectively, and are of the same frequency but differ in phase. Associated with each of the four input clock signals A to D is a respective one of four clock enable signals EN A to EN D which are independent of each other, and are active when low. That is, any or none of the clock enable signals EN A to EN D may be low at any given time, and at any given time the one of the clock enable signals EN A to EN D which has most recently gone low designates the one of the input clock signals A to D which is required to form the output of the multiplexer. The clock enable signals EN A and EN B (Figures 4C and 4D) are supplied to the further input terminals 39 and 40 respectively. A transition between the input clock signal A (Figure 4A) and the input clock signal B (Figure 4B) will be considered. As initially the input clock signal A (Figure 4A) has been supplied to the output terminal 73, the clock enable signal EN A (Figure 4C) must have been low and the other clock enable signals EN B (Figure 4D), EN C and EN D must have been high. The clock enable signals EN C and EN D must remain high during the transition to be described. With the clock enable signal EN A (Figure 4C) low, the outputs of the NAND gates 38 to 50 are held high, and as a result the clock enable signals EN B (Figure 4D), EN C and EN D are prevented from causing the input clock signals B (Figure 4B), C and D from being supplied to the output terminal 73. It is therefore necessary for the clock enable signal A (Figure 4C) to go high, that is inactive, as shown in Figure 4, before the transition to the input clock signal B (Figure 4B) can take place. At a later time, as shown in Figure 4, the clock enable signal EN B (Figure 4D) goes low, signalling a request for a transition to the input clock signal B (Figure 4B). The flip-flop circuit 36 operates as a latch circuit and in cooperation with the NOR gate 44 causes a single positive pulse, with a duration of one input clock signal B (Figure 4B) cycle long, to be generated following the negative edge of the clock enable signal EN B (Figure 4D). This pulse will pass through the NAND gate 48 and become a single negative pulse 4E. The effect of the pulse 4E is two-fold. Firstly, via the AND gate 63 it will cause the flip-flop circuit 51 to be cleared. The output of the flip-flop circuit 51 will go low and the flip-flop circuit 55 will then be clocked by a negative edge of the inverted input clock signal A to cause the output signal 4F of the flip-flop circuit 55 to go low. Since this signal 4F and the input clock signal A (Figure 4A) are gated together by the AND gate 59, the result of the signal 4F going low is to de-select the input clock signal A (Figure 4A) and take the signal 4I supplied by the AND gate 59 to the OR gate 71 low. Secondly, this signal 4E sets the flip-flop circuit 52 so that the output signal 4G goes high. The next negative edge of the inverted input clock signal B will cause the output signal 4H of the flip-flop circuit 56 also to go high. The signal 4H enables the AND gate 60 to supply the input clock signal B (Figure 4B) to the OR gate 71 as the signal 4J. Thus, the input clock signal A (Figure 4A) will have been de-selected and the input clock signal B (Figure 4B) will have been selected, so that the output signal 4K from the OR gate 71 will have changed from the input clock signal A (Figure 4A) to the input clock signal B (Figure 4B). However, as seen in Figure 2, the result of the input clock signals A and B (Figures 4A and 4B) being out of phase is that the signal 4K contains a reduced space period. As this could well cause a problem in subsequent circuitry, the signal 4K is supplied to the clock signal regenerator 72 which operates to maintain the mark/space ratio of the output signal 4L within predetermined bounds. From the above description it will be understood how the multiplexer operates in the case of a transition from the input clock signal A to the input clock signal B, but it will also be readily apparent how transitions can occur from any one of the input clocks A to D to any other one of the input clock signals A to D. In each case, the selection of the previously-selected input clock signal A to D is relinquished by the corresponding clock enable signal EN A to EN D going high, and a new input clock signal A to D is selected by the corresponding clock enable signal EN A to EN D going low. One example of the clock signal regenerator 72 will now be described with reference to Figures 5 and 6. As shown in Figure 5, the clock signal regenerator 72 comprises D-type flip-flop circuits 81 and 82 and a delay line 83 which produces a total delay of 30 nanoseconds with an intermediate tap at 15 nanoseconds. The output of the OR gate 71 (Figure 3) is connected to an input terminal 84, which is connected to the clock terminal of the flip-flop circuit 81. The Q output terminal of the flip-flop circuit 81 is connected to the input of the delay line 83 and also to the set terminal of the flip-flop circuit 82. The output tap of the delay line 83 is connected to the set terminal of the flip-flop circuit 81, and the intermediate tap of the delay line 83 is connected to the clock terminal of the flip-flop circuit 82. The Q output terminal of the flip-flop circuit 82 is connected to the output terminal 73 of the clock signal multiplexer (Figure 3). Alternatively, the Q output terminal of the flip-flop circuit 82 can be used to supply the output, or indeed both the Q and the Q output terminals may be used if required. The operation of the clock signal regenerator 72 will now be described with reference also to Figure 6, which shows the waveforms of signals 6A to 6E at various similarly-designated points in the circuit of Figure 5. A pulse signal 6A is supplied by the OR gate 71 (Figure 3) to the terminal 84 and in consequence the flip-flop circuit 81 supplies a pulse 6B, the leading edge of which is delayed by say 6 nanoseconds relative to the positive edge of the pulse signal 6A, due to the delay inherent in the flip-flop circuit 81. The negative edge of a pulse 6C supplied from the intermediate tap of the delay line 83 to the flip-flop circuit 82 is delayed by a further 15 nanoseconds, while the negative edge of a pulse 6D which sets the flip-flop circuit 81 is delayed by 30 nanoseconds relative to the negative edge of the pulse 6B. Considering therefore an output signal 6E, the positive edge of the output pulse 6E is set by the negative edge of the pulse 6B, and the negative edge of the output pulse 6E is set by the positive edge of the pulse 6C. The mark period is therefore the interval between the above two times, that is: (15 + 30) + 6 nanoseconds that is: 51 nanoseconds. Thus, it will be seen that the mark/space ratio of the output clock signal is determined exclusively by the clock signal regenerator circuit 72, and not by the pulse signal 6A. Various modifications are of course possible without departing from the invention as defined by the appended claims. Thus, for example, the frequency and times quoted above are given by way of example only, as are the number of input clock signals, and various modifications can be made to the circuit elements used, for example other suitable forms of latch circuit can be used in place of the flip-flop circuits mentioned.

Claims: A clock signal multiplexer for combining a plurality n of input clock signals (A to D) of the same frequency but differing phases into a single channel, by selectively passing one of said n input clock signals (A to D) to an output (18) of the multiplexer to the exclusion of the other n-1 input clock signals (A to D), the multiplexer being characterized by: n input circuits (5 to 8) to each of which a respective one of said n input clock signals (A to D) is supplied together with a respective clock enable signal (EN A to EN D); a logic circuit (13, 14) coupling said input circuits (5 to 8) to a signal synchronizer (15), said logic circuit (13, 14) operating to enable said signal synchronizer (15) in respect of the input clock signal (A to D) corresponding to that one of said n clock enable signals (EN A to EN D) which is in a select condition, and further operating on return of said one of said clock enable signals to a non-select condition and transition of another of said clock enable signals to the select condition to disable said signal synchronizer (15) in respect of the previously selected input clock signal (A to D), and to enable said signal synchronizer (15) in respect of the input clock signal (A to D) corresponding to said another clock enable signal; and a clock signal selector (16) to which said input clock signals (A to D) are supplied and to which said signal synchronizer (15) is connected, said signal synchronizer (15) enabling said clock signal selector (16) to pass the enabled said input clock signal to said output (18) of the multiplexer. A clock signal multiplexer according to claim 1 wherein said n input circuits (5 to 8) respectively comprise n pulse generators (5 to 8) respectively including n first latch circuits (35 to 38) to each of which a respective one of said n input clock signals (A to D) is supplied together with a respective clock enable signal (EN A to EN D), said logic circuit (13, 14) comprises an arrangement of gates (47 to 50, 63 to 66) coupling said n first latch circuits (35 to 38) to n second latch circuits (51 to 58) forming said signal synchronizer (15), said gate arrangment (43 to 50, 63 to 66) operating to enable a selected one only of said second latch circuits (51 to 58) corresponding to that one of said n clock enable signals (EN A to EN D) which is in a select condition, and further operating on return of said one of said clock enable signals to a non-select condition and transition of another of said clock enable signals to the select condition to cause said selected one of said second latch circuits (51 to 58) to be disabled and another of said second latch circuits (51 to 58) corresponding to said another clock enable signal to be enabled, and said clock signal selector (16) comprises n output gates (59 to 62; 71) to each of which a respective one of said input clock signals (A to D) is supplied and to which said n second latch circuits (51 to 58) are respectively connected, the said enabled second latch circuit (51 to 58) enabling the corresponding output gate (59 to 62; 71) to pass the enabled said input clock signal to said output (18) of the multiplexer. A clock signal multiplexer according to claim 2 wherein the outputs of said output gates (59 to 62; 71) are connected to a clock signal regenerator (72), the output of which (73) is connected to said output (18) of the multiplexer. A clock signal multiplexer according to claim 2 or claim 3 wherein each of said n first latch circuits (35 to 38) is a respective flip-flop circuit (35, 38). A clock signal multiplexer according to claim 2, claim 3 or claim 4 wherein each of said second latch circuits (51 to 58) comprises a respective pair of flip-flop circuits (51 to 58). A clock signal multiplexer according to any one of the preceding claims wherein n is four.

Inventors: AVIS RICHARD JOSEPH ANDREW, AVIS, RICHARD JOSEPH ANDREW
Applicants: SONY CORP, SONY CORPORATION
Application year: 1987
Main classification: G06F1
IPC codes: G11B20, G06F1, H03K5