NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Abstract: A nonvolatile semiconductor memory device includes a pulse signal generator (ROS, IV6, IV7, BR) for applying a pulse signal to a capacitor (C), a first diode (T31) connected at an anode to the capacitor (C), a charging circuit (T29, T30, T33) for charging the capacitor (C) in a programming mode, a voltage limiter (T35, T36) for preventing a potential at the output node (SO) from increasing above a predetermined level, memory cells of nonvolatile MOS transistors (TM11 to TMMN), a load MOS transistor (T8) connected to a high-voltage terminal (Vp), a row decoder (RDC, WSC) for selecting a set of memory cells arranged in one row, column gate MOS transistors (T91 to T9N) connected between respective sets of memory cells arranged in one column and the load MOS transistor (T8), a data generator (DG, DID) respon­ sive to the voltage at the output node (SO) to turn on or off the load MOS transistor (T8), and a column decoder (CSC, CDC) responsive to the voltage at the output node (SO) to selectively energize the column gate MOS tran­ sistors (T91 to T9N). It further comprises a second diode (T32) connected between the cathode of the first diode (T31) and the output node (SO), and a discharging circuit (T38, T39) for discharging the cathode of the first diode (T31) to a reference voltage level during a time other than a programming mode.

Description: The present invention relates to a nonvolatile semiconductor memory device having a booster circuit. Such a memory is known from GB-A-2 094 086 and reflected in the preamble according to claim 1. Figs. 1 and 2 respectively show a source voltage switching circuit and a nonvolatile memory device used in a conventional CMOS erasable and programmable (EP) ROM. The source voltage switching circuit in Fig. 1 includes inverter INV to which write control signal W is supplied from an external circuit (not shown), p-channel MOS transistor T1 having a gate connected via n-channel MOS transistors T2 and T3 to the output terminal of inverter INV, and n-channel MOS transistor T4 connected at a gate thereof to the output terminal of inverter INV. The gates of MOS transistors T2 and T3 are respectively connected to power source voltage terminal VC and high voltage terminal Vp. MOS transistor T4 has one end connected to high-voltage terminal Vp via MOS transistor T1 and the other end connected to reference voltage terminal Vs. The connection node between MOS transistors T1 and T4 is connected to the gate of p-channel MOS transistor T5 connected between high-voltage terminal Vp and the gate of MOS transistor T1. The connection node between MOS transistors T1 and T4 is also connected to the gate of n-channel MOS transistor T6 connected between high-voltage terminal Vp and switchover power source terminal SWO. Between power source terminal Vc and switchover power source terminal SWO is connected depletion type (D-type) n-channel MOS transistor T7 whose gate is connected to receive signal W . A voltage higher than that applied to power source terminal Vc is applied to high-voltage terminal Vp. In Fig. 2, data generator DG and data driver DDR constitute data input decoder DID, whereas column selection circuit CSC and column drivers CDR1 to CDRN constitute column decoder CDC. Word line selection circuit WSC and word line drivers WDR1 to WDRM constitute row decoder RDC. The output terminal of data driver DDR is connected to the gate of MOS transistor T8 which serves as a load transistor during data programming. The output terminals of column drivers CDR1 to CDRN are connected to the respective gates of column gate transistors T91 to T9N. The output terminals of word line drivers WDR1 to WDRM are connected to the gates of respective rows of nonvolatile MOS transistors TM11 to TMMN constituting memory cells. Data driver DDR includes a CMOS inverter which is constituted by p- and n-channel MOS transistors DT10 and DT11 and which receives a data signal from data generator DG via n-channel transmission MOS transistor DT12 whose gate is connected to power source terminal Vc, and p-channel feedback MOS transistor DT13 connected between switchover power source terminal SWO and the input terminal of the CMOS inverter and having a gate for receiving the output signal of the CMOS inverter. Each of column drivers CDR1 to CDRN and each of word line drivers WDR1 to WDRM are constructed in the same manner as data driver DDR. That is, MOS transistors CT10 to CT13 constituting column driver CDR1 and MOS transistors WT10 to WT13 constituting word line driver WDR1 are arranged in the same manner as MOS transistors DT10 to DT13. During a data readout operation, the levels of signals W and W are set to "0" and "1", respectively. As a result, transistors T1 and T4 are respectively rendered nonconductive and conductive, thereby setting the gate potential of MOS transistor T6 to "0" (zero). MOS transistor T6 becomes nonconductive, whereas MOS transistor T7 becomes conductive, whereby source voltage Vc is derived at switchover power source terminal SWO. During data programming, signals W and W are set to "1" and "0" levels, respectively. Therefore, MOS transistor T6 becomes conductive, and MOS transistor T7 becomes nonconductive, whereby a voltage which is lower than high-voltage Vp by the threshold voltage of MOS transistor T6 is generated at switchover power source terminal SWO. During data programming, the drain voltage of memory cell transistors TM11 to TMMN is dropped by an amount corresponding to the sum of the threshold voltages of MOS transistors T6 and T8. The voltage to be applied to the drain of memory cell TMij should preferably be as high as possible within a range that does not cause a punch-through of memory cell TMij. For this reason, in the case wherein programming voltage Vp is fixed, it is not desirable that a voltage drop takes place in internal switching MOS transistors T6 and T8. Further, since the data programming characteristic depends upon the threshold voltage and conductance of memory cell TMij and switching MOS transistors T6 and T8, the disadvantage arises in that the margin of the programming voltage reduces according to variations in the manufacturing process. The object of the invention is to provide a nonvolatile semiconductor memory device which has a large margin for a programming voltage and permits high-speed data programming. The object is achieved by the nonvolatile semiconductor memory device as specified in claim 1. It comprises: a high voltage terminal to which a high voltage is applied in a programming mode; a capacitor; a pulse signal-generator for applying a pulse signal to one end of the capacitor; a first diode connected at an anode electrode thereof to the other end of the capacitor; an output node; a second diode having an anode electrode connected to a cathode electrode of the first diode, and a cathode electrode connected to the output node; a charging circuit which is activated in the programming mode, for charging the other end of the capacitor up to a predetermined voltage level; a discharging circuit which is activated during a time other than the programming mode, for discharging the cathode electrode of the first diode down to the reference voltage level; a voltage limiter connected to the cathode electrode of the second diode, for preventing a potential at the cathode electrode from increasing above the predetermined voltage level; memory cells constituted by a plurality of nonvolatile MOS transistors; a load MOS transistor having one end connected to the high voltage terminal; a row decoder for selecting a set of memory cells which are arranged in one row; column gate MOS transistors connected at one end to respective sets of memory cells arranged in one column, and connected at the other end to the other end of the load MOS transistor; a data input decoder responsive to the voltage at the output node to energize or de-energize the load MOS transistor; and a column decoder responsive to the voltage at the output node to alternatively energize the column gate MOS transistors. In the present invention, a booster circuit is provided in the source voltage switching circuit, so that the boosted voltage is applied to the buffer of the input decoder and column decoder. It is therefore possible to compensate for a drop in the drain voltage of the memory cell caused during a data programming operation, and thereby perform high-speed data programming. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a diagram showing a conventional source voltage switching circuit; Fig. 2 is a diagram showing a conventional nonvolatile memory circuit which is driven by a source voltage generated by the source voltage switching circuit of Fig. 1; Fig. 3 is a diagram showing a source voltage switching circuit for a nonvolatile memory device, according to one embodiment of the invention; Fig. 4 is a diagram showing a nonvolatile memory circuit which is driven by a source voltage generated by the source voltage switching circuit shown in Fig. 3; Fig. 5 is a circuit diagram showing a booster circuit section in the source voltage switching circuit of Fig. 3; Figs. 6 and 7 are graphs showing signal waveforms by way of explanation of the operation of the booster circuit shown in Fig. 5; Fig. 8 is a diagram showing a modified form of the booster circuit shown in Fig. 5; Fig. 9 is a graph showing a signal waveform by way of explanation of the operation of the booster circuit shown in Fig. 8; Figs. 10 and 11 are diagrams showing still other modified forms of the booster circuit shown in Fig. 5. Figs. 3 and 4 respectively show a source voltage switching circuit and nonvolatile memory circuit according to one embodiment of the present invention. The source voltage switching circuit in Fig. 3 includes ring oscillator ROS constituted by inverters IV1 to IV5, and inverter IV6 having an input terminal connected to the output terminal of ring oscillator ROS and an output terminal connected to node A via inverter IV7 and buffer BR. Inverter IV7 and buffer BR comprise n-channel MOS transistors T23 to T25 and n-channel MOS transistors T26 to T28, respectively, connected in series between high voltage terminal Vp and reference voltage terminal Vs. MOS transistors T23 and T26 are of a D-type. The gate and source of MOS transistor T23 are connected to the gate of MOS transistor T26. The gates of MOS transistors T24 and T27 are connected to the output terminal of inverter IV6. MOS transistors T25 and T28 receive at their gates boost control signal HD which is synchronous with write control signal W. Node A is connected to node B via capacitor C. MOS transistors T29 and T30 are connected in series between power source terminal Vc and node B. Node B is connected to output terminal SO via MOS transistors T31 and T32. The gates of MOS transistors T31 and T32 are respectively connected to nodes B and D between MOS transistors T31 and T32. The gate and drain of MOS transistor T30 are connected through MOS transistor T33 to high-voltage terminal Vp. MOS transistors T35 and T36 are series-connected between high-voltage terminal Vp and output terminal SO, and D-type MOS transistor T37 is connected between terminals Vc and SO. D-type MOS transistor T38 and MOS transistor T39 are series-connected between reference voltage terminal Vs and node D. Node D is connected to the gates of MOS transistors T33 and T35. The gates of MOS transistors T29 and T37 to T39 are connected to respectively receive signal HD, signal W , power source voltage Vc and signal HD synchronized with signal W . The nonvolatile memory circuit shown in Fig. 4 is constructed and operated basically in the same manner as the circuit shown in Fig. 2, except that the circuit in Fig. 4 receives at switchover power source terminal SI the output voltage from output terminal SO of the circuit shown in Fig. 3. The operation of the nonvolatile memory device shown in Figs. 3 and 4 will now be described. During an ordinary data readout operation, power source voltage Vc is applied to power source terminals Vp and Vc, and the levels of signals W , HD and HD are respectively set to "1", "0" and "1". As a result, the potential at node D becomes "0" to render MOS transistors T33, T35 and T32 nonconductive, and MOS transistor T37 becomes conductive, whereby voltage Vc is generated at output terminal SO and applied to switchover power source terminals SI of the circuit shown in Fig. 4. At this time, MOS transistors T25, T28 and T29 are nonconductive, preventing current from flowing from the power source terminal to the reference voltage terminal in the switching circuit of Fig. 3. During data programming, a voltage higher than voltage Vc (5 V, for example), e.g., 12.5 volts, is applied to high voltage terminal Vp. The levels of signals W , HD and HD are set to "0", "1" and "0" respectively. Therefore, MOS transistors T25, T28 and T29 become conductive, whereas MOS transistors T37 and T39 become nonconductive. In this case, a clock signal is supplied from ring oscillator ROS to MOS transistors T24 and T27 of inverter IV7 and buffer BR, respectively, via inverter IV6. At first, node B is charged through MOS transistors T29 and T30, and then, upon application of the clock signal from ring oscillator ROS, it is charged through MOS transistors T33 and T30, and the potential at output terminal SO increases due to the presence of MOS transistors T31 and T32 acting as a diode. The potential at terminal SO is finally stabilized when it reaches a voltage higher than high voltage Vp by an amount corresponding to the threshold voltage of MOS transistor T36. In Fig. 3 n-channel MOS transistors T30 and T31 can be replaced by intrinsic type n-channel MOS transistors MOS transistors having a threshold voltage of substantially 0 V, making it possible to shorten the time for increasing the potential at terminal SO to a preset potential level. Switchover power source terminal SI is connected to the sources of p-channel MOS transistors DT10, DT13, CT10, CT13, WT10 and WT13. During data programming, the gates of MOS transistors T8, T9i and TMij are applied with a voltage higher than high voltage Vp by the threshold voltage of the n-channel MOS transistor, preventing the voltage drop in the drain voltage of the memory cell and permitting high-speed data programming. A CMOS type EPROM employs a decoder as shown in Fig. 4. In this type, an optimum decoding operation can be achieved by changing the level of the potential at switchover power source terminal SI during data readout and write operations. Further, in order to save power consumption during a standby condition, the levels of signals HD and HD are set to "1" and "0" respectively, in the same manner as in the case of the data readout operation, so that MOS transistor T39 becomes conductive. As a result, the gate voltage of MOS transistor T35 is set to "0", whereby a leak current flowing through MOS transistors T37 and T36 from power source Vc is suppressed even when the voltage at high-voltage terminal Vp is set at "0". Fig. 5 shows a circuit section corresponding to part of the circuit shown in Fig. 3, by way of explanation of the boost operation performed in the circuit. In Fig. 5, the same reference symbols as used hereinbefore refer to corresponding parts or elements, and the description thereof is omitted. In Fig. 5, oscillator 1 includes ring oscillator ROS and inverter IN6 shown in Fig. 3. In response to a clock signal supplied from oscillator 1, a signal containing pulse components as shown in Fig. 6 is generated at node A. When the level of boost control signal HD is set at "1", MOS transistor T29 becomes conductive, thereby charging node B via MOS transistor T30. The potential at node B becomes lower than source voltage Vc by the threshold voltages (Vth) of MOS transistors T29 and T30. At the same time, the OSC circuit starts to operate, and when the level of the clock signal changes from "H" to "L" level, node A is rapidly charged up to high voltage Vp through MOS transistor T26. In response to a voltage increase from "0" to Vp at node A, the potential at node B is also boosted due to the capacitive coupling. For example, the voltage at node B which has been charged at source voltage Vc level is boosted by about 4 volts (i.e., to approximately 9 volts), in response to a level change from "H" to "L" of the clock signal from oscillator 1. When a clock signal from oscillator 1 becomes "H" level, the potential at node "A" becomes "0", lowering the potential at node "B". However, since node D is connected to node B via diode-connected MOS transistor T31, the potential does not decrease and the potential at node B is applied to the gate of MOS transistor T33, thereby making transistor T33 conductive. Thus, a voltage lower than a voltage on node D by the threshold voltage of MOS transistor T33 is applied to MOS transistor T30, and node B is charged to a level higher than power source voltage Vc. When, thereafter, the level of the clock signal from oscillator 1 becomes "L", node B is further boosted. Node B is charged up to source voltage Vc -2 × threshold voltage of n-channel MOS transistor MOS transistor T29. However, after the voltage at node B exceeds (power source voltage Vc -2 × threshold voltage of n-channel MOS transistor) node B is boosted by MOS transistor T33 since MOS transistor T29 is then nonconductive. The voltage at node D, boosted as above, is applied to output terminal SO through MOS transistor T32. The maximum output voltage that is applied to output terminal SO is determined by a limiter constituted by MOS transistors T35 and T36. That is, when the output voltage becomes higher than high voltage Vp by an amount larger than threshold voltages VthB of MOS transistor T36 which is set responsive to the substrate bias effect, a current flows through MOS transistors T35 and T36 to terminal Vp, thereby dropping the output voltage. Therefore, the output voltage is approximately equal to the sum of high voltage Vp and threshold voltages VthB of MOS transistor T36 which is set responsive to the substrate bias effect, i.e., approximately equal to the saturation voltage. If, in this case, the voltage at node A increases while a discharge occurs through MOS transistors T30 and T33 the voltage at node B is also temporarily increased, whereby the pulse components of approx. 2 V as shown, for example, in Fig. 7 are contained in the output voltage. If the output voltage containing such pulse components is applied to switchover power source terminal SI of the memory circuit shown in Fig. 4, the following problems will be caused. If the output voltage SO contains pulse components, the voltages at, for example, the P-type drain regions of MOS transistors DT10 and DT13 of data driver DDR will increase more quickly than the N-well regions. As a result, a current flows from the drain region to the N-well region, possibly causing a latch-up. When an output signal from data generator DG in data driver DDR is at "0" level, an "H"-level signal is fed back to the gate of MOS transistor DT13, and MOS transistor DT13 becomes nonconductive, and accordingly, no current flows through MOS transistor DT13. However, when the pulse component contained in output voltage SO is applied to switchover power source terminal SI, voltage SI is applied to the gate of MOS transistor DT13 through MOS transistor DT10. After a certain delay time, the pulse component is applied to the same transistor. Therefore, while the gate potential of MOS transistor DT13 is kept lower than the source potential thereof by an amount equal to threshold voltage Vth of MOS transistor DT13, MOS transistor DT13 is kept conductive. A current therefore flows through MOS transistor DT13, causing switchover voltage SI, which has been boosted, to be lowered. Fig. 8 shows a booster circuit which is free from the disadvantages described above. This booster circuit has a structure similar to that shown in Fig. 5, except that capacitor CX is connected between reference voltage terminal Vs and the connection node between MOS transistors T23 and T24. Capacitor CX comprises, for example, an MOS transistor having a gate connected to the connection node between MOS transistors T23 and T24 and a source and drain connected to reference voltage terminal Vs. Capacitor CX serves to make changes in potential of the output pulse of inverter IV7 moderate or gentle. Thus, changes of current flow from the drain to the source of MOS transistor T26 and the rate of charging at node A becomes moderate. When the potential at node A is applied via capacitor C to node B and further to switchover power source terminal SO via MOS transistors T31 and T32, the potential changes at nodes B and D become moderate, and the potential at switchover power source terminal SO in no way increases above the sum of the high voltage Vp and the threshold voltage of MOS transistor T36, since charging rate at node A is moderate. In this case, switchover power source voltage SO does not contain pulse components, as shown in Fig. 9. Fig. 10 shows another booster circuit in which changes in potential at node B are made moderate or gentle, in order to eliminate the afore-described disadvantages. This booster circuit has a structure similar to that shown in Fig. 5, except that a polysilicon resistor RX is provided between node A and capacitor C. In this booster circuit, the potential at node A increases rapidly. However, since the potential at node A is applied via resistor RX and capacitor C to node B, the potential at node B changes moderately. As a result, switchover power source voltage SO does not contain pulse components in the same manner as shown in Fig. 9. The booster circuit shown in Fig. 11 is similar to that shown in Fig. 5 but additionally includes D-type MOS transistor TX. MOS transistor TX is connected at its drain to the source of MOS transistor T32 and connected at its gate and source to output terminal SO. That is, MOS transistor TX is diode-connected between MOS transistor T32 and output terminal SO, so that rapid changes in potential at the source of MOS transistor T32 can be made moderate or gentle. The potential thus obtained is applied to output terminal SO. The output voltage does not contain pulse components, as in the case shown in Fig. 9. It should be noted that the present invention is not limited to the embodiment described above. For example, the gate of N channel MOS transistor DT11 can be separated from MOS transistor DT12 and directly connected to the output terminal of data generator DG. This can enlarge the operational margin for fluctuation in the power source voltage. Further, in the memory circuit shown in Fig. 4, output voltage SO of the source voltage switching circuit in Fig. 3 is applied to each of word line drivers WDR1 to WDRM. Alternatively, the output voltage of a conventional source voltage switching circuit, as shown in Fig. 1, may be applied to each of the word lines. In this case, MOS transistor T6 can be of a depletion type. With the depletion MOS transistor, a high voltage Vp is derived form switchover power source terminal SWO at the programming time. Further, in the power source voltage switching circuit shown in Fig. 3, MOS transistor T36, diode-connected between high voltage terminal Vp and switchover power source terminal SO constituting a limiter, is not limited to one, but may be changed in number as desired.

Claims: A nonvolatile semiconductor memory device comprising a high-voltage terminal (Vp) to which a voltage higher than a source voltage (Vc) is applied in a programming mode; capacitive means (C); pulse signal generating means (ROS, IV6, IV7, BR, CX, RX; 1, IV7, BR, CX, RX) for applying a pulse signal to one end of the capacitive means (C); first diode means (T31) connected at an anode electrode thereof to the other end of the capacitive means (C); an output node (SO); a charging circuit (T29, T30, T33) which is activated in a programming mode, for charging said other end of the capacitive means (C) to a predetermined voltage level; voltage limiting means (T35, T36) connected to the output node (SO), for preventing a potential at the output node (SO) from increasing above the predetermined voltage level; memory cells constituted by a plurality of nonvolatile MOS transistors (TM11 to TMMN); a load MOS transistor (T8) connected to the high voltage terminal (Vp); row decoding means (RDC, WSC) for selecting a set of memory cells which are arranged in one row; column gate MOS transistors (T91 to T9N) connected at one end to respective sets of memory cells arranged in one column, and connected at the other end to the load MOS transistor (T8); data generating means (DG, DID) having an input (SI) connected to the voltage at the output node to turn on or off the load MOS transistor (T8); and column decoding means (CSC, CDC) having an input (SI) connected to the voltage at the output node (SO) to alternatively energize the column gate MOS transistors (T91 to T9N); characterized by further comprising: second diode means (T32) having an anode electrode connected to a cathode electrode of the first diode means (T31), and a cathode electrode connected to the output node (SO); and a discharging circuit (T38, T39) which is activated during a time other than the programming mode, for discharging the cathode electrode of the first diode means (T31) to a reference voltage level. A device according to claim 1, characterized in that the data generating means includes a data generator (DG) and a data driving circuit (DDR) having a CMOS inverter which includes MOS transistors (DT10 and DT11) connected in series between the output node (SO) and a reference voltage terminal (Vs) and which is connected at an output terminal thereof to a gate of the load MOS transistor (T8), a transmission MOS transistor (DT12) connected between an output terminal of the data generator (DG) and the CMOS inverter, and a feedback MOS transistor (DT13) connected between the output node and the transmission MOS transistor (DT12) and connected at a gate to the output terminal of the CMOS inverter. A device according to claim 1 or 2, characterized in that the column decoding means includes a column selection circuit (CSC) having a plurality of output terminals; and column driving circuits (CDR1 to CDRN) each including a CMOS inverter which is constituted by MOS transistors connected in series between the output node (SO) and reference voltage terminal (Vs) and having an output terminal connected to a corresponding one of the gates of the column gate MOS transistors (T91 to T9M),, a transmission MOS transistor (CT12) connected between a corresponding one of the output terminals of the column selection circuit (CSC) and the CMOS inverter, and a feedback MOS transistor (CT13) connected between the output node (SO) and said transmission MOS transistor (CT12) and connected at a gate to the output terminal of the corresponding CMOS inverter. A device according to claim 2 or 3, characterized in that said CMOS inverter in each of data driving circuit (DDR) and column driving circuit (CDC) includes P and N channel MOS transistors (DT10, DT11, CT10 and CT11) whose gates are connected to the output terminal of said data generator (DG) and column selection circuit (CSC) through said transmission MOS transistor (DT12, CT12). A device according to claim 2 or 3, characterized in that said CMOS inverter in each of data driving circuit (DDR) and column driving circuit (CDR) includes a P channel MOS transistor (DT10, CT10) whose gate is connected to the output terminal of said data generator (DG) and column selection circuit (CDC) through said transmission MOS transistor (DT12, CT12) and an N channel MOS transistor (DT11, CT11) whose gate is directly connected to the output terminal of said data generator (DG) and column selection circuit (CSC), respectively. A device according to claim 1, 2 or 3, characterized in that the pulse signal generating means includes an oscillating circuit (ROS, IV6; 1), and inverting means (IV7, BR, CX, RX) responsive to an output signal of the oscillating circuit (ROS, IV6; 1) to apply a pulse signal to the capacitive means (C). A device according to claim 6, characterized in that the oscillating circuit (ROS, IV6; 1) includes a ring oscillator (ROS), and an inverter (IV6) for inverting an output signal of the ring oscillator (ROS). A device according to claim 6 or 7, characterized in that the inverting means includes a first load MOS transistor (T23) and a first driving MOS transistor (T24) which are series-connected between the high voltage terminal (Vp) and the reference voltage terminal (Vs), and a second load MOS transistor (T26) and a second driving MOS transistor (T27) which are series-connected between the high voltage terminal (Vp) and the reference voltage terminal (Vs), the first load MOS transistor (T23) being connected at a gate thereof to a connection node between the first load MOS transistor (T23) and the first driving MOS transistor (T24) and to a gate of the second load MOS transistor (T26), and the first and second driving MOS transistors (T24, T27) having gates thereof connected to an output terminal of the oscillating circuit (ROS, IV6; 1). A device according to claim 8, characterized in that the inverting means further includes first and second selection MOS transistors (T25, T28) which are respectively connected in series with the first and second driving MOS transistors (T24, T27) and which become conductive in the programming mode. A device according to claim 8 or 9, characterized in that the inverting means further includes a capacitor (CX) connected between a gate of the second load MOS transistor (T26) and the reference voltage terminal (Vs). A device according to claim 8 or 9, characterized in that the inverting means further includes a resistor (RX) connected between the capacitive means (C) and a connection node (A) between the second load MOS transistor (T26) and the second driving MOS transistor (T27). A device according to any one of claims 1 to 11, characterized in that the charging circuit includes first and second charging MOS transistors (T29, T30) which are series-connected between the source voltage terminal (Vc) and the other end of the capacitive means (C), and a third charging MOS transistor (T33) connected at a gate thereof to the cathode of the first diode means (T31) and having one end connected to the high voltage terminal (Vp) and the other end connected to a gate and drain of the second charging MOS transistor (T30), the first charging MOS transistor (T29) being rendered conductive in the programming mode. A device according to claim 12, characterized in that said second charging MO transistor (T30) is formed of an N channel MOS transistor having a threshold voltage of substantially 0 V. A device according to any one of claims 1 to 13, characterized in that the discharging circuit includes a MOS transistor (T38, T39) series-connected between the cathode of the first diode means (T31) and the reference voltage terminal (Vs) being rendered nonconductive in the programming mode. A device according to any one of claims 1 to 14, characterized in that the limiting means includes at least one diode (T35, T36) connected at a cathode thereof to the high voltage terminal (Vp) and connected at an anode thereof to the cathode of the second diode means (T32). A device according to claim 15, characterized in that the limiting means further includes an MOS transistor (T35) connected in series with the at least one diode (T36) and having a gate connected to the anode of the second diode means (T32). A device according to any one of claims 1 to 16, characterized by further comprising a depletion type MOS transistor (TX) coupled at a drain thereof to the cathode of the second diode means (T32) and coupled at a source and gate thereof to the output node (SO). A device according to any one of claims 1 to 17, characterized by further comprising a switching MOS transistor (T37) which is connected between the source voltage terminal (Vc) and the output node (SO) and which is rendered conductive in the data readout mode. A device according to any one of claims 1 to 18, characterized in that said first diode means (T31) is formed of an N channel MOS transistor having a threshold voltage of substantially 0 V.

Inventors: ASANO, MASAMICHI C/O PATENT DIVISION, IWAHASHI, HIROSHI C/O PATENT DIVISION, KUMAGAI, SHIGERU, NAKAI, HIROTO C/O PATENT DIVISION, SATO, ISAO, SUZUKI, KAZUTO
Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-COMPUTER ENGINEERING CORPORATION
Application year: 1987
Main classification: G11C16
IPC codes: G11C16