DRIVING A MATRIX TYPE DISPLAY DEVICE

Abstract: For driving a display device or panel (1) of matrix type (e.g. an electroluminescence display panel) a compensation (V cp , V c , V cp1 , V cp2 ) pulse is applied to all the cells of the panel prior to or immediately at the beginning of a pedestal pulse (V pp , V p , V pp1 , V pp2 ) on every frame cycle. The level of the compensation pulse is higher than that of the pedestal pulse but low enough not to light the cells by itself. The duration of the compensation pulse is sufficient to saturate charge polarization in the EL material of a cell, as a dielectric, at the applied voltage. The brightness of lighted cells is kept constant regardless of the number of lighted cells on the same data electrode. Each of two power-receiving terminals (15, 16) of push-pull scan drives (7-1 to 7-n) is connected to a pulse generator (3, 4; 3′, 4′) respectively. One of the two power-receiving terminals (15, 16) may be floated from the pulse generator (3, 4; 3′, 4′) whilst a data pulse is applied to the data electrodes (Di). This configuration prevents damage of the CMOS drivers by latch-up, and reduces power consumption produced by charging current of the data pulses into non-lighted cells.

Description: This invention relates to methods of and apparatus for driving a matrix type display device or panel, for example in which an electrically luminous material is driven, such as a so-called electroluminescence (referred to hereinafter as EL) display panel of matrix type. In a matrix type EL display panel, an EL cell located at an intersection of a scan electrode and a data electrode is selectively lit by application of a scan pulse voltage on the scan electrode with simultaneous application of a data pulse voltage, on the data electrode, having a polarity opposite to that of the scan pulse. The applied pulse voltage, effective between the scan and the data electrodes, which is the sum of the respective absolute values of the scan pulse voltage and data pulse voltage, is called cell voltage. The polarity of the cell voltage may be altered every frame cycle, in order to attain brighter light output as well as normal operation of the EL cell. Furthermore, in order to reduce the voltage rating of the scan driver, the scan pulse may be composed of a pedestal pulse whose duration is approximately 15.0 ms, for example, for a frame cycle time of 16.7 ms (60 frames per second), and an additional scan pulse of duration 25 to 30 µs, for example, when there are 400 scan electrodes. Such a pedestal pulse has been employed for driving a PDP (plasma display panel); see PCT application, publication No. WO-A-8303021 (HARJU, Terho, Teuvo). In the following description reference is made, by way of example, to the accompanying drawings, in which: Figs. 1(a), 1(b) and 1(c) illustrate voltage waveforms, illustrating a pedestal pulse, a data pulse and a scan pulse applied in a case in which a single cell on a data electrode is lit; Figs. 1′(a), 1′(b) and 1′(c) are voltage waveforms illustrating pedestal data pulses and a scan pulse applied in a case in which all cells on a data electrode are lit; Figs. 2(a) to 2(f) are timing charts illustrating application of pulses over two frame cycles; Fig. 3 is a schematic circuit diagram illustrating a previously proposed driving circuit configuration; Fig. 4 is a graphical illustration of the effect of different virtual pedestal pulse voltages on the brightness of the lighted cells; Fig. 5 is a voltage waveform diagram illustrating a cell voltage waveform; Fig. 6 is a graphical illustration of brightness vs. virtual pedestal voltage characteristics, for a case embodying the present invention (e) and a case not embodying the invention (d); Fig. 7 is a diagram illustrating behaviour of polarization charge in a cell when an embodiment of the present invention is not applied; Figs. 8(a) and 8(b) illustrate the application of compensation pulses in accordance with respective embodiments of the present invention; Fig. 9 is a diagram illustrating behaviour of polarization charge in a cell when operated in accordance with an embodiment of the present invention; Fig. 10 is a schematic circuit diagram of apparatus embodying the invention; Figs. 11(a) to 11(g) are timing charts of applied pulses, provided for example by the apparatus of Fig. 10, according to an embodiment of the present invention; Fig. 12 is a schematic circuit diagram of another apparatus embodying the present invention; Fig. 13(a) to 13(g) are timing charts of applied pulses, provided for example by the apparatus of Fig. 12, according to an embodiment of the present invention; Fig. 14 is a schematic sectional diagram of a CMOS structure, for assistance in explaining a latch-up which can take in a CMOS driver; Fig. 15 is a graphical illustration of power consumption vs. percentage of the lighted cells; and Figs. 16(a) to 16(e) and Figs. 17(a) to 17(e) are timing charts. Fig. 1(a) illustrates a voltage waveform applied to a data electrode, where V dp indicates a data pulse having a positive voltage Vd, and having a pulse width basically the same as that of a scan pulse. Fig. 1(b) illustrates a voltage waveform applied to a scan electrode, where V pp indicates a pedestal pulse having a negative voltage -Vp and a pulse width T p , and V sp indicates a scan pulse having a negative voltage -Vs superposed on the negative pedestal pulse V pp . Thus, when a scan electrode is selected, the total scan pulse voltage Vp + Vs, a so-called half-selective voltage, is applied thereto. The levels of the individual pulses Vd and Vp + Vs are chosen so that they are not adequate, by themselves, to light a cell. Fig. 1(c) illustrates a voltage waveform applied to a cell (the cell to which the above-mentioned data pulse and scan pulse are applied) measured relative to the scan electrode. The peak level Va, which is the sum of the absolute values of Vd, Vp and Vs, is chosen to be high enough to light the cell, for example 215 V. Thus, this peak pulse is called a write pulse. In the case of Fig. 1, only a single cell at the centre of the data electrode is lit. With the illustrated constitution of driving pulses, a scan driver, composed of an integrated circuit (IC), has only to switch a low voltage Vs, such as 25 V, which, in other words, is the difference between the half-selective pulse voltage (e.g. 190 V) and the pedestal pulse voltage (e.g. 165 V) and therefore is much less than the total scan voltage, 190 V. Timing charts of scan, data and cell pulse voltages are illustrated in Figs. 2, for a case in which n scan electrodes are provided. Fig. 2(a) shows the voltage waveform applied to an i-th data electrode. Figs. 2(b) to (d) show voltage waveforms of respective scan electrodes S₁ to S n . Figs. 2(e) to (g) show cell voltage waveforms arising at the respective intersections of the i-th data electrode and the scan electrodes S₁ to S n . Generally, data electrodes D₁ to D m are driven in parallel by a data driver. A frame cycle time T f (e.g. for a kth frame cycle) is the time required to scan all of the n scan electrodes, and then to return to a first scan electrode for a next frame cycle. During one (i.e. the kth) frame cycle a negative pedestal pulse of a level of -165 V is employed. During the next (i.e. k+1 th) frame cycle, the pedestal pulse is reversed (positive) and its level is, for example, +190 V, an absolute value different from that of the pedestal pulse of the previous frame cycle. This is to take account of the fact that the data electrode is biased at a high level (+25 V) and "negative" data pulses of 0 V are delivered to the data electrodes to provide that write pulses of the same height are produced in both cycles. A typical scan pulse generator/driver is shown in Fig. 3 - see the above-mentioned patent application. When pedestal pulses are employed, there is a problem in that the brightness of a particular lighted cell varies depending on the number of the lighted cells connected to the same data electrode through a frame cycle. A description of the nature of this problem will be given below for a case in which a still picture is to be provided, where the data pulses are the same for every frame cycle, in order to simplify the explanation. Figs. 1′(a), 1′(b), 1′(c), illustrate an extreme case, where all the cells on a data electrode are lit, in comparison with Figs. 1(a), 1(b), 1(c) where only a single cell on a data electrode is lit. As observed in Fig. 1′(c), the pedestal pulse level becomes virtually Vp + Vd, because data pulses for lighting all the cells are continuously superposed on the pedestal level. Brightness characteristics relating to the two cases of Figs. 1 and Figs. 1′, depending on the virtual pedestal pulse level, are illustrated in Fig. 4, where the level of the write pulse is variable. Curve "b" relates to a case in which a 165 V pedestal pulse is provided to simulate the single lighted cell of Figs. 1, and curve "c" relates to a case in which a 190 V pedestal pulse is provided to simulate the all-lighted cells of Figs. 1′. The brightness of the curve "c" is obviously lower than that of the curve "b". Brightness characteristics in cases where the number lit cells on a data electrode is between "a single cell" and "all cells" lie between the curves "b" and "c". In order to simulate such a state, curve "d" of Fig. 6 is obtained by measurement in relation to a sample EL panel. In the Figure, the pedestal pulse voltage is variable while write pulse and the data pulse voltages are kept constant, respectively at 240 V and 25 V. Accordingly "the pedestal pulse voltage + the scan pulse voltage" is kept constant. As observed from curve "d", brightness decreases as the virtual pedestal voltage increases over 150 V. This means that brightness decreases as the number of the lit cells on a data line increases. When the EL material produces light in response to a write pulse, electrical charges in the EL material, a dielectric material, are displaced by the electric field applied thereto, causing a charge polarization effect. The mechanism of this phenomenon is hereinafter explained. The brightness of the produced light of a cell depends on the amount of the polarization charge produced therein. The relationship between applied pulses and the polarization charges produced in a cell was investigated and is shown in Fig. 7. The solid lines illustrate a case in which a single cell on a data electrode is lit; the broken lines illustrate a case where all the cells on a data electrode are lit. The timing at which a pedestal pulse is applied to the scan electrode is indicated by "tp", and the timing at which a write pulse is applied to the electrodes is indicated by "tw". Polarization charge present before tp is residual charge from the previous frame cycle, during which the polarity of the cell voltage was reversed. The increment charge curve "f" with a low effective pedestal level ("a single lit cell") at tw is larger than that at tp. The word "increment" used above and hereinafter means the difference between charge present before and after the application of a pulse voltage, and the word "difference" includes not only difference in level of a particular polarity of charge but also charge difference from a positive charge to a negative charge and vice versa. However, the increment of charge curve "g" with a high effective pedestal level ("all cells lit") at tw is smaller than that at tp. Furthermore, overall increment Qb (0.38 µ coulomb/cm²) of the charge curve "g" is smaller than the overall increment Qa (0.48 µ coulomb/cm²) of the charge curve "f". This indicates that differences of virtual or effective pedestal level influence the charge increment at tp as well as the overall charge increment, accordingly causing deterioration of brightness characteristics. Fig. 5 is a more detailed waveform diagram of cell voltage (cf. Figs. 2(e) to 2(g)) over two frame cycles (each T f ) with a pedestal pulse duration of T p . Fig. 5 illustrates the pedestal pulse, data pulses (e.g. 1 to 5), a scan pulse and a write pulse j. DE-A-2 739 675 discloses a method of driving a display panel of matrix type having a plurality of scan electrodes and a plurality of data electrodes crossing the scan electrodes to form display cells at the crossing points, the method comprising cycles of applying scan pulses selectively to the scan electrodes, and applying data pulses selectively to the data electrodes, so that a selected cell which is to provide a display suffers the application of a write pulse voltage thereto, the sum of pulse voltages applied to the scan and data electrodes, to light the cell. According to the present invention there is provided a method of driving a display panel of matrix type having a plurality of scan electrodes and a plurality of data electrodes crossing the scan electrodes to form display cells at the crossing points, the method comprising cycles of applying scan pulses selectively to the scan electrodes, and applying data pulses selectively to the data electrodes, so that a selected cell which is to provide a display suffers the application of a write pulse voltage thereto, the sum of pulse voltages applied to the scan and data electrodes, to light the cell, characterised in that in each cycle a compensation pulse is applied to all the cells prior to application of the scan pulses, the compensation pulse voltage being insufficient itself to light the cells, a pedestal pulse is applied, to either the scan electrodes or the data electrodes, so that scan pulses are superposed on a pedestal pulse if the pedestal pulse is applied via the scan electrodes, or data pulses are superposed on a pedestal pulse if the pedestal pulse is applied via the data electrodes, and characterised in that the polarity of the compensation pulse voltage is the same as that of the pedestal pulse voltage, the compensation pulse voltage is higher than the pedestal pulse voltage, and the voltage and duration of the compensation pulse are adequate to generate a polarization charge in a cell equal to or more than a maximum polarization charge generated by a maximum virtual pedestal pulse voltage level effective at the cell. According to a method embodying the present invention, a compensation pulse is applied to all cells prior to the application of a pedestal pulse thereto. For each frame cycle, the polarity of the compensation pulse is the same as that of the pedestal pulse. The level of the compensation pulse is higher than that of the pedestal pulse, generally almost equal to the sum of the pedestal pulse and the data pulse, but not high enough to light a cell by itself. The duration of the compensation pulse is long enough to "saturate" charge polarization corresponding to the level of the applied compensation pulse: any half-selective pulse applied to a cell during a frame cycle does not affect this polarization charge produced by the compensation pulse. Therefore, the increment of polarization charge produced by application of a write pulse voltage is uniform regardless of the number of the half-selective pulses in a frame cycle, thus allowing fully selected cells to produce light of constant brightness. In the following description, reference is made to a case in which a still picture is to be displaced, i.e. the pattern of applied data pulses is constant through every frame cycle. Cell voltage waveforms provided when embodiments of the present invention are employed are illustrated in Figs. 8(a) and (b). By way of example, pedestal pulse voltage Vp is 165 V, scan pulse voltage Vsp is 25 V and data pulse voltage Vd is 25 V. Therefore, the level of the compensation pulse applied in accordance with the illustrated embodiments of the invention is chosen as 195 V, a little higher than the half-selective pulse level, 190 V, which is the sum of the pedestal pulse voltage Vp and the data pulse voltage Vd, but lower than a level at which the cell starts to produce light. A compensation pulse thus having a level of 195 V is applied to a cell prior to the pedestal pulse, with the same polarity as that of the pedestal pulse, but of course below write pulse voltage, 215 V. Some of these exemplary voltage values are different from those referred to in connection with the sample panel used for providing the data on which Fig. 6 is based because data are now taken from a practical panel in production. As seen in Figs. 8(a) and 8(b), in a second frame cycle, the polarity of the compensation pulse is reversed together with that of the pedestal pulse. The compensation pulse may be applied before the front or leading edge of the pedestal pulse, with some time interval between the compensation pulse and the pedestal pulse, as shown in Fig. 8(a). The compensation pulse may be applied so as to contact the front edge of the pedestal pulse, as shown in Fig. 8(b). The duration of the compensation pulse is approximately 1 ms, which is adequately longer than the approximately 0.5 ms required to "saturate" polarization of electric charges in the EL material, as a dielectric, of a cell: any half-selective pulse, i.e "the pedestal pulse + the data pulse " applied to a cell during a frame cycle does not affect the polarization charges produced by the compensation pulse. When a write pulse, i.e. a fully selective pulse, having a voltage level 215 V, is then applied to a cell it produces an essentially constant increment of the polarization charge additionally in the EL material of the cell, and at this time, the cell simultaneously produces light depending on the size of the increment of the polarization charge. Owing to this essentially constant increment of the polarization charge, brightness of the produced light is essentially constant regardless of the number of the half-selective pulses applied to the cell, i.e the number of the data pulses during a frame cycle. The above-described effect of the compensation pulse on the polarization charge is further explained in Fig. 9, where the solid lines and the broken lines relate to "single cell lit" and "all cells lit" cases, as in Fig. 7. The charge increments shown by the solid line and by the broken line at tp have similar values. The overall increments, Qb and Qc, after application of the compensation pulse are equal (0.38 µ coulomb/cm²). The result of employing the compensation pulse in accordance with an embodiment of the present invention is illustrated by curve "e" in Fig. 6, where all the conditions are the same as those for curve "d" (see above), except for the application of the compensation pulse in accordance with an embodiment of the present invention. As observed in the Figure, the brightness of a lighted cell is almost constant despite variation of pedestal voltage, though the maximum value of the brightness is somewhat reduced. The compensation pulse may be either independent as shown in Fig. 8(a), or superposed on the pedestal pulse as shown in Fig. 8(b). Attention is directed to "Proceedings of the 6th International Display Research Conference, October 1, 1986", a paper entitled "A Symmetric Drive with Low Voltage Drivers for ac TFEL" by the present inventors. A schematic block circuit diagram for explaining supply of driving pulses, including the compensation pulse as provided in embodiments of the present invention, is shown in Fig. 10. 1 is an EL panel, on which m data electrodes, D₁ to D m , generally made of a transparent material, such as ITO (indium tin oxide), and n scan electrodes, S₁ to S n , generally made of aluminum, are arranged orthogonally to one another. 2 is a data pulse generator/driver in which m pairs of single-ended push-pull drivers, 6-1 to 6-m, as switching elements, each composed of a p-channel MOS transistor and an n-channel MOS transistor and a DC power source 5 (+25 V), are included. Commonly connected drains of the two transistors of each single-ended push-pull driver provide the driver output terminal, which is connected to a corresponding data electrode. Scan drivers 7 are composed of n pairs of CMOS single-ended push-pull drivers 7-1 to 7-n, as switching elements. Each CMOS driver includes a p-channel MOS transistor and an n-channel MOS transistor therein. Commonly connected drains of the two transistors of each CMOS single-ended push-pull driver provide a driver output terminal and are connected to a corresponding scan electrode. Between the drain and source of each transistor of a CMOS driver, a natural diode (a parasitic diode) 21 or 22 exists as indicated by broken lines in the Figure, so as to bypass a current in the reverse direction to the conduction through each associated transistor. All the sources of the n-channel transistors are commonly connected to a power-receiving terminal 15. All the sources of the p-channel transistors are commonly connected to a power-receiving terminal 16. A first driving pulse generator 3 is connected to the terminal 15. The first driving pulse generator 3 comprises a first pedestal pulse generator 8, a first scan pulse generator 10, and a first compensation pulse generator 13 and a ground switch 17. The first pedestal pulse generator 8 comprises a negative DC power source (-165 V) 8-1, a positive DC power source (+190 V) 8-2 and a three-position switch 8-3 which selectively connects the power source 8-1 or 8-2 to the terminal 15. The first scan pulse generator 10 comprises a negative DC power source (-190 V) 10-1 and a positive DC power source (+190 V) 10-2 and a three-position switch 10-3 which selectively connects the power source 10-1 or 10-2 to the terminal 15. The first compensation pulse generator 13 comprises a negative DC power source (-195 V) 13-1 and a positive DC power source (+195 V) 13-2, and a three-position switch 13-3 which selectively connects the power source 13-1 or 13-2 to the terminal 15. A second driving pulse generator 4 is connected to the terminal 16. The second driving pulse generator 4 comprises a second pedestal pulse generator 9, a second scan pulse generator 11, a second compensation pulse generator 14 and a ground switch 18. The second pedestal pulse generator 9 comprises a negative DC power source (-165 V) 9-1, a positive DC power source (+190 V) 9-2 and a three-position switch 9-3 which selectively connects the power source 9-1 or 9-2 to the terminal 16. The second scan pulse generator 11 comprises a negative DC power source (-165 V) 11-1, a positive DC power source (+215 V) 11-2 and a three-position switch 11-3 which selectively connects the power source 11-1 or 11-2 to the terminal 16. The second compensation pulse generator 14 comprises a negative DC power source (-195 V) 14-1, a positive DC power source (+195 V) 14-2, and a three-position switch 14-3 which selectively connects the power source 14-1 or 14-2 to the terminal 16. Each of the above-mentioned three-position switches has a centre position, which is connected to nothing, i.e. a floating position or an open position. Between the terminals 15 and 16, a zener diode 12 is connected, whose anode is connected to terminal 15 and the cathode to terminal 16. Each terminal opposite to the output terminal of each DC power source mentioned above is grounded. A manner of applying driving pulses to the electrodes of the cells of the EL panel 1 is hereinafter described, with reference to Fig. 10 and to the timing charts of Figs. 11. It is general for the data pulse generator/driver 2 to drive all the data electrodes, D₁ to D m , in parallel. Fig. 11(a) shows a pulse voltage waveform applied to data electrode D i from a data pulse driver 6-i. Figs. 11(b) to (d) illustrate pulse voltage waveforms applied to scan electrodes S₁ to S n , respectively from scan pulse drivers 7-1 to 7-n. Fig. 11(e) to (g) show cell voltage waveforms measured with reference to scan electrodes. A previous (k-1 th) scan cycle (not shown in the Figure) during which the applied cell voltage was negative is finished and the cell voltage is to be positive for a k-th scan cycle. Then, driven by control signals (not shown in the Figure), such as an enable signal, etc., switches 13-3 and 14-3 are connected to power sources 13-1 and 14-1 respectively, while all other switches are kept at their central or open position. Thus, -195 V is applied to terminal 15 and to terminal 16. Consequently, all scan electrodes are charged at -195 V through diodes 21 and 22. Thus, a positive compensation pulse voltage, +195 V, is applied to the cells. After approximately 1 ms application of the compensation voltage, the switches 13-3 and 14-3 are opened, and the ground switches 17 and 18 are closed so as to return the terminal 15 and 16 to 0 V. During application of this compensation pulse, all the data electrodes D₁ to D m are kept at 0 V by the push-pull drivers 6-1 to 6-m switched by control signals (not shown in the Figure) applied to the gates of the respective push-pull drivers. A variation of the circuit for supplying the compensation pulse shall be described after the description of the operation of the circuit of Fig. 10. After application of the compensation pulse, cells are driven as described below. After the ground switches 17 and 18 are opened, the switches 8-3 and 9-3 are respectively switched to the pedestal power sources 8-1 and 9-1 of -165 V, while the data drivers deliver 0 V to all the data electrodes. Then all the scan electrodes are charged through the diodes 21 and 22 at -165 V, and thus a positive pedestal pulse voltage, +165 V, is applied to the cells. Timing of switching-on the switches 8-3 and 9-3 may be either at the time of, or later than, the end of the compensation pulse, as shown in Fig. 8(a) or 8(b). In order to select the first scan electrode S₁, the switches 10-3 and 11-3 are switched to the power source 10-1 (-190 V) and to the power source 11-1 (-165 V) respectively, while all the other switches 8-3, 9-3, 13-3, 14-3, 17 and 18 are kept open (neutral). At this time, the potential difference between the terminals 15 and 16 is 25 V, so the scan drivers 7 (7-1 to 7-n) have only to switch a voltage as low as 25 V. In a driver (e.g. 7-1) first n-ch transistor is switched conductive, while the paired p-ch transistor is kept non-conductive, but in all other drivers the p-ch transistors are kept conductive, and all the n-ch transistors in the other drivers 7-2 to 7-n are kept non-conductive, all controlled by control signals (not shown in the Figure) applied to the gates of the transistors. Thus, the total scan voltage, -190 V, which is a half-selective voltage, is selectively applied to the first scan electrode S₁, and -165 V is applied to all other scan electrodes, as shown by Fig. 11(b). After approximately 25 µs of holding this state, the scan driver 7-1 is switched making the p-ch transistor conductive and the n-ch transistor non-conductive so as to deliver -165 V to the first scan electrode. Then, the second scan electrode S₂ has -190 V selectively applied thereto, in the same manner as the first scan electrode, and the process is repeated sequentially for successive scan electrodes, as illustrated by Figs. 11(c) and 11(d). Driving of the data electrodes is as described below. For lighting cells on the i-th data electrode D i , a push-pull driver connected to the data electrode D i is selectively switched by control signals (not shown in the Figure) applied to each gate thereof so as to deliver a +25 V pulse to the data electrode D i , essentially in synchronism with the application of the half-selective voltage -190 V to a corresponding scan electrode where a cell is to be lit, as indicated by Fig. 11(a). At this time, as shown in Figs. 11(e) to 11(g), cell voltage becomes as high as +215 V, which is called "fully selective" or a write pulse, high enough to light the cell. After the final scan electrode is selected, the pedestal pulse is terminated, and then, in general, refresh pulses may be applied, so that the total brightness of the cell during a frame cycle is enhanced. After completion of the k-th frame cycle, in the next (k+1 th) frame cycle, cell voltage polarity is reversed. Driven by control signals (not shown in the Figure), such as an enable signal, etc., the switches 13-3 and 14-3 are connected to the power sources 13-2 and 14-2 respectively, while all other switches are kept neutral or open. Thus, +195 V is applied to terminal 15 as well as to terminal 16, while the data drivers 6-1 to 6-m deliver 0 V to all the data electrodes D₁ to D m . Therefore, all the scan electrodes are charged at +195 V through diodes 21 and 22, and thus negative compensation voltage, -195 V, is applied to the cells. After approximately 1 ms application of the compensation voltage, the power sources 13-2 and 14-2 are disconnected and the terminals 15 and 16 returned to 0 V by closing the ground switches 17 and 18. In order to supply the pedestal pulse, switches 8-3 and 9-3 are switched to pedestal power sources 8-2 and 9-2 respectively, both having +190 V. Thus, all the scan electrodes are charged at +190 V through the diodes 21 and 22. In order to select the first scan electrode S₁, the switches 10-3 and 11-3 are switched to the power sources 10-2 (+190 V) and 11-2 (+215 V), respectively, while all other switches 8-3, 9-3, 13-3, 14-3, 17 and 18 are kept open (neutral). At this time, the potential difference between the terminals 15 and 16 is 25 V, so the scan driver 7 has only to switch a voltage as low as 25 V. The p-ch transistor of the first scan driver 7-1 is switched conductive, while the paired n-ch transistor is kept non-conductive. All other n-ch transistors in the scan drivers 7-2 to 7-n are kept conductive, and all other p-ch transistors in the scan drivers 7-2 to 7-n are kept non-conductive, all controlled by control signals (not shown in the Figure) applied on the gates of the transistors. Thus +215 V is selectively applied to the first scan electrode S₁, and +190 V is applied to all other scan electrodes, as shown in Figs. 11(b). After approximately 25 µs of holding this state, the second scan electrode S₂ and so on are sequentially selected and have +215 V applied thereto (Figs. 11(c) and 11(d)). Driving of the data electrodes is as described below. Because a data signal is provided by a negative pulse during the k+1 th frame cycle, the data electrodes are biased at +25 V by making conductive the p-ch transistors of the data drivers 6. The cell voltage is 25 V - 215 V = -190 V, which is half-selective. For lighting cells on the i-th data electrode D i , the push-pull driver connected to the data line D i is selectively switched by control signals (not shown in the Figure) so as to deliver a 0 V pulse to the data line D i , as shown by Fig. 11(a), essentially in synchronism with the above-described application of the +215 V pulse onto a corresponding scan electrode where a cell is to be lit. Then, as shown in Figs. 11(e) to 11(g), the cell voltage becomes -215 V, high enough to light the cell. During the k-th frame cycle, though the power sources 13-1 and 14-1, for providing a compensation pulse, or power sources 8-1 and 9-1, for providing a pedestal pulse (the power sources of each pair having the same voltage) are simultaneously connected to the two terminals 15 and 16 respectively in the above-described embodiment, the connection of the power sources 13-1 and/or 8-1 may be omitted. The advantage of using two pulse generators (3 and 4 in Fig. 10, or 3′ and 4′ in Fig. 12 - see below) having same voltage is that deformation of pulse shape caused by ringing, etc., can be prevented by clamping the terminals 15 and 16 with both pulse generators. Not only the connection of one of the pulse generators can be omitted as above-described, but also the pulse generator itself can be omitted. The above-described methods, and the configurations of Fig. 10 or 12, may be applied to a case where the pedestal voltage is very low or zero, as long as the driver circuit can withstand the voltage. Pulse application may be carried out in a similar manner during the k+1 th frame cycle also. Referring to Figs. 12 and 13(a) to 13(g), a variation of the driving pulse generator/driver for supplying the compensation pulse as well as driving pulses is hereinafter described. Instead of using ±195 V for the compensation pulse, as described in relation to the embodiment illustrated in Fig. 10, the level of the compensation pulse may be chosen to be 190 V, which is equal to the half-selective voltage, i.e. pedestal pulse + the data pulse. In this case the configuration of pulse driving circuits shown in Fig. 12 may be used. In the Figure, parts similar to those in Fig. 10 are designated by similar reference signs. A first driving pulse generator 3′ connected to the common power-receiving terminal 15 comprises DC power sources V₃₁, V₃₂, and V₃₃ outputting +190 V, -190 V, and -165 V respectively, and series switches 31-1, 32-1, 33-1 which respectively connect the associated DC power sources to the terminal 15, and a ground switch 17. A second driving pulse generator 4' connected to the common power-receiving terminal 16 comprises power sources V₄₁, V₄₂, and V₄₃, outputting +215 V, +190 V, and -165 V respectively, and series switches 41-1, 42-1, 43-1 which respectively connect the associated DC power sources to the terminal 16, and a ground switch 18. Fig. 13(a) illustrates the voltage waveform of the i-th data electrode. Figs. 13(b) to 13(d) illustrate voltage waveforms of scan electrodes S₁ to Sn. Figs. 13(e) to 13(g) illustrate voltage waveforms of the cell voltages of the cells D i - S₁ to D i -S n . For a k-th frame cycle, the pedestal voltage -165 V is applied to all scan electrodes through the diodes 21 (and 22) at time t₁ by closing switch 43-1 and switch 33-1 (33-1 may not be used, as mentioned in the description of operation of the circuits of Fig. 10) while all other switches in the driving pulse generators 3′ and 4′ are kept open. At the same time T₁, +25 V is applied to all the data electrodes, D₁ to D m , from power source 5 of the data pulse generator/driver 2, by causing all p-ch transistors, QX pl to QX pm , of the data drivers 6-1 to 6-m to conduct, while all n-ch transistors, QX nl to QX nm , are kept non-conductive. Therefore, the cell voltage is 190 V = 165 V + 25 V. Thus, a positive compensation pulse voltage is applied to all the cells. At the time t₂, after holding this state for approximately 1 ms, i.e. after the duration of the compensation pulse, the data drivers discontinue the supply of +25 V: all the p-ch transistors, QX pl to QX pm , become non-conductive while all the n-ch transistors, QX nl to QX nm , are made conductive. Thus, at the time t₂ the compensation pulse is ended and the cell voltage becomes +165 V, the pedestal pulse level. For the k+l th frame cycle, during which the polarity of the cell voltage is reversed, at the time t₁₁, +190 V (DC power source V31) is supplied through the diodes 22 to all the scan electrodes by closing the switch 31-1 (perhaps as well as 42-1, but the latter may not be used, as described in relation to Fig. 10) while all other switches in the driving pulse generators 3′ and 4′ are kept open. At this time, all the data drivers supply 0 V to all the data electrodes, by causing all the n-ch transistors, QX nl to QX nm , to be conductive, while all the p-ch transistors, QX pl to QX pm , are non-conductive. Thus, a negative compensation pulse voltage, -190 V, is applied to all the cells. At time t₁₂, approximately 1 ms later than t₁₁, all the data electrodes are switched to +25 V, which is the bias voltage of the data pulses for this frame cycle. Thus, at the time t₁₂, the compensation pulse is ended, and the cell voltage becomes -165 V, the pedestal pulse level. After the compensation pulse, total scan pulses may be produced by switching the switches 32-1 and 33-1 alternately for the k-th frame cycle, or by switching the switches 41-1 and 42 alternately for the k-l th frame cycle. In synchronism with the produced total scan pulses, one of the scan drivers 7-1 to 7-n selectively passes the produced total scan pulses on to the associated scan electrodes. The advantage of this circuit configuration is that the cost of the circuit construction is less. While the scan pulses are produced and applied to the scan electrodes from one of pulse generators 3′ and 4′, the other pulse generator 4′ or 3′ may be disconnected from the respective terminal 16 or 15 by opening all the switches of the pulse generator to be disconnected. In this state the relevant terminal is floated. The advantage of the configuration having two sets of power generators 3 and 4 (3′ and 4′), at the two power-receiving terminals 15 and 16 for the scan drivers 7 to receive power or pulses as shown in Figs. 10 and 12 respectively, is that a latch-up phenomenon taking place in a CMOS scan driver is prevented. As illustrated in Fig. 14 and as well known, an NPN parasitic transistor 25 and a PNP parasitic transistor 26 are naturally formed in a CMOS structure. When a large pulse, such as the compensation pulse or pedestal pulse, charges or discharges the scan electrodes of the configuration of Fig. 3, the charging/discharging current flowing through the parasitic diode 21 or 22 may be considerable, and this diode current acts as a base-emitter current of the parasitic transistor 25 or 26, thus both the parasitic transistors 25 and 26 are latched up by positive feedback, allowing a current to flow from the source electrode of the p-ch MOS transistor to the source electrode of the n-ch MOS transistor through the CMOS structure, resulting in fatal damage thereto. However, the configuration of Fig. 10, and that of Fig. 12, having pulse generators (3, 4, or 3′, 4′) connected to the both power-receiving terminals 15 and 16 of the push-pull drivers, does not allow the latch-up phenomena to occur because the voltages of the terminals are equal (if the forward voltage drop of the zener diode is neglected), or one of the terminals is floated. Consequently, this advantage also allows an increase of the reliability of the device as well as the use of inexpensive ICs. Though, as described above, pulses are applied in synchronism, in a practical circuit the timing of rising and falling of nominally synchronous applied pulses may be intentionally or unintentionally deviated from each other to some degree. Therefore, there is a chance that a transistor of a driver IC could have a higher voltage than 25 V, for example 215 V, applied thereto. In order to protect the driver IC from an unexpected high voltage applied thereto, zener diode 12 having a zener breakdown voltage lower than the withstand voltage of the scan driver may be provided between the terminals 15 and 16. The zener breakdown voltage of the zener diode 12 must be of course the same as or larger than the normal voltage difference imposed on these transistors, 25 V for this case, but the optimum value of the zener breakdown voltage will be discussed below. With the above-described configuration of Fig. 12, after the scan electrodes are charged up to the pedestal voltage from the power source V43, the power source V43 may be disconnected by opening the switch 43-1, i.e. the terminal 16 may be floated, then or while the scan pulse is applied from the first pulse generator 3′ through the terminal 15. Details of the timing of the applied pulses will be described below. As for the next frame cycle, having reversed polarity of pulses, after the scan electrodes are charged up to the pedestal voltage from the power source V31, the power source V31 may be disconnected, i.e. the terminal 15 may be floated, then or while the scan pulse is applied from the second pulse generator 4′ through the terminal 16. The purpose of this floating of one power-receiving terminal 15 or 16 is to prevent the (flow of) charging current of (in connection with) the data pulses applied to the data electrodes through cells which are on non-selected scan electrodes, but to which the data pulses are applied, so that power consumption is reduced. In other words, when the average potential of all the data electrodes confronting a scan electrode is changed by a change in the number of selected data electrodes according to the displayed pattern, the potential of the scan electrode can quickly change following the average potential of the data electrodes, thus unnecessary charging current flowing into the non-selective cells can be prevented. The degree of reduction of power consumption varies depending on the zener voltage of the zener diode 12. Characteristics of power consumption vs. percentage of light cells for different zener voltages are illustrated in Fig. 15, for a case in which the number of data electrodes is 640 and the number of scan electrodes is 400. In the Figure, curve "a" relates to a case in which the zener voltage is equal to the scan voltage Vs, 25 V. The power consumption of the configuration of Fig. 3 is also given by the curve "a". Power consumptions when the zener voltage is Vs + Vd/2, 32.5 V, and when it is Vs+ Vd, 50 V, are illustrated by curves "b" and "c" respectively. As the zener voltage is increased, the power consumption at more than 50% lighted cells is decreased. This is explained as follows. A positive charging current, for the k-th frame cycle, due to positive data pulses from the data driver through non-lighted cells on non-selected scan electrodes cannot flow to the terminal 16, because these non-selected scan electrodes are floating, and thus flows into other non-lighted cells on the same non-selected scan electrodes but facing other data electrodes having no data pulse thereon, and so flows into these data electrodes, then to conductive n-ch transistors of the data drivers 6, and returns to the ground terminal of the power source 5. The amplitude of this current is determined by the impedance between the terminals of the data electrodes to which data pulses are applied and the terminals of the data electrodes to which data pulse is not applied. Therefore, this impedance, which is the series connection of the cells to which data pulses are applied and the cells to which data pulse is not applied, is minimum, thus the charging current is maximum, where the lighted cells are 50%, then the power consumption is maximum. This means that this charging current decreases as the percent of the lighted cells increases beyond 50%. When the zener voltage is lower than Vs + Vd, the scan electrodes are clamped to the zener voltage beyond a particular percentage point, in other words, the floated terminal 16 is no longer floating, due to the conduction of the zener diode, into which the charging current through the non-lighted cells flows while consuming power therein. When the zener voltage is equal to Vs, the charging current through the non-lighted cells always flows into the zener diode, and this state is equivalent to a case where the terminal 16 is not floated (so connected to the power source V43). Thus the power consumption is shown by the curve "a". When the zener voltage is increased, the withstand voltage of the scan driver must of course be increased. The same phenomena occurs also in the k+l th frame cycle of the opposite cell voltage polarity. Therefore, the value of the zener voltage is chosen in accordance with design policy for the system, trading off withstand voltage of the driver IC against power consumption. Though, in the above description, the floating of the power-receiving terminal is carried out continuously after the pedestal pulse voltage is applied, there are other possible types of timing modes, such as one in which terminal floating may be intermittent depending on the pulse widths of the data pulses and the width of the scan pulse and their mutual timing relationship. Two samples of the timing relationships of data pulses and scan pulses are shown in the timing charts of Figs. 16(a) to 16(e) and Figs. 17(a) to 17(e). In the Figures, broken line waveforms of pulses indicate that the pulses are floated. Similarly in Figs. 13, the broken lines in the waveforms illustrate that the pulses are floating. In the case of Figs. 16, where data pulses are wide enough such that one may be continuous with an adjacent data pulse, the pedestal power source V43 of -165 V connected to the power-receiving terminal 16 of the push-pull driver is disconnected, namely floated, at or before the time t₃ when the front edge of the first data pulse is applied to the data electrode. The floating is discontinued at time t₉ when or after the final data pulse is ended. In the case of Figs. 17, where data pulses are not wide enough for adjacent data pulses to become continuous, the pedestal power source V43 of -165 V previously connected to the power-receiving terminal 16 is disconnected, namely floated, at the time t₄ when the front edge of the first data pulse is applied to the data electrode, and connected again at the time t₆ when the first data pulse is ended. The floating is thus repeated during every period during which a data pulse is applied to the data electrode. In either case shown in Figs. 16 or Figs. 17, before or at the time when a data pulse is applied to a data electrode, the power-receiving terminal 16 becomes floating. A data pulse is applied to a data electrode for approximately 5µ sec, for example, prior to the application of the scan pulse. This is in order to cover (take account of) a delay of data pulse to charge up the cells caused by the electrical resistance of the data electrodes which are made of very resistive material (such as ITO which has a resistance of 8 K ohm per electrode). This early application of the data pulse prior to the scan pulse is mentioned in the U.S. Patent No. 4 636 789 by H. Yamaguchi et al. Though in the above description of embodiments of the invention the level of the compensation pulse is 195 V or 190 V, which is higher than the half selective voltage, i.e "pedestal pulse voltage Vp + data pulse voltage Vd", it may be lower than the half selective voltage, when some deterioration of brightness uniformity is acceptable. Though in the above description of embodiments of the invention the compensation pulse as well as the pedestal pulse is supplied through the scan drivers to the cells, these pulses may be supplied through the data drivers. Though in the above description of embodiments of the invention single-ended push-pull drivers of the data drivers and the scan drivers are composed of CMOS, other kinds of transistors may be used, for example, pairs of PNP and NPN bipolar transistors, pairs of NPN transistors, pairs of PNP transistors, or similarly p-ch or n-ch MOS transistors. Though in the above description of embodiments of the invention the single-ended push-pull drivers of the data drivers and the scan drivers are described as being such that when one push-pull driver driver drives its output (electrode), the other push-pull drivers are all switched reversely, in other words, the p-ch transistors are non-conductive and the n-ch transistors are conductive, it is possible that both of the paired transistors, i.e. also the n-ch transistors, may be made non-conductive. Though in the above description reference is made to a frame cycle of 60 HZ, embodiments of the present invention may be applied also to other frame cycles. Though in the above description applied cell voltage is symmetric, embodiments of the present invention can be applied in cases in which the cell voltage may be asymmetric. Though in the above description scan or data electrodes are driven respectively by single groups of drivers, embodiments of the present invention may be applied in cases in which the drivers are composed of a plurality of the groups of push-pull drivers, each group having two power-receiving terminals which are connected to respective pulse generators. Though in the above description of embodiments of the invention many power sources and switches are referred to, so that the timing of the application of each pulse can be understood clearly, these power sources and their associated switches may be unified and simplified as long as the necessary pulse forms are provided at the electrodes. Though the switches are illustrated as mechanical switches in the Figures, these switches may be of course formed constituted as semiconductor switches. Though in the above description of embodiments of the invention, a zener diode is connected between power-receiving terminals 15 and 16, any other constant-voltage means, such as a varistor, a capacitor or a DC power source, may be employed in place of the zener diode. Though in the above description of the present invention embodiments no reference is made to the application of refresh pulses to the cells, it will be understood that refresh pulses may be employed in embodiments of the present invention, and can be of good effect in enhancing total brightness of the lighted cells through a frame cycle. For driving a display device or panel (1) of matrix type (e.g. an electroluminescence display panel) a compensation (V cp , V c , V cp1 , V cp2 ) pulse is applied to all the cells of the panel prior to or immediately at the beginning of a pedestal pulse (V pp , V p , V pp1 , V pp2 ) on every frame cycle. The level of the compensation pulse is higher than that of the pedestal pulse but low enough not to light the cells by itself. The duration of the compensation pulse is sufficient to saturate charge polarization in the EL material of a cell, as a dielectric, at the applied voltage. The brightness of lighted cells is kept constant regardless of the number of lighted cells on the same data electrode. Each of two power-receiving terminals (15, 16) of push-pull scan drives (7-1, to 7-n) is connected to a pulse generator (3, 4; 3', 4') respectively. One of the two power-receiving terminals (15, 16) may be floated from the pulse generator (3, 4; 3', 4') whilst a data pulse is applied to the data electrodes (Di). This configuration prevents damage of the CMOS drivers by latch-up, and reduces power consumption produced by charging current of the data pulses into non-lighted cells.

Claims: A method of driving a display panel of matrix type having a plurality of scan electrodes (S₁ to S n ) and a plurality of data electrodes (D₁ to D m ) crossing the scan electrodes to form display cells at the crossing points, the method comprising cycles of applying scan pulses (V s , V sp ) selectively to the scan electrodes, and applying data pulses (V d , V dp ) selectively to the data electrodes, so that a selected cell which is to provide a display suffers the application of a write pulse voltage thereto, the sum of pulse voltages applied to the scan and data electrodes, to light the cell, characterised in that in each cycle a compensation pulse (V c , V cp ) is applied to all the cells prior to application of the scan pulses, the compensation pulse voltage being insufficient itself to light the cells, a pedestal pulse (V p , V pp ) is applied, to either the scan electrodes or the data electrodes, so that scan pulses are superposed on a pedestal pulse if the pedestal pulse is applied via the scan electrodes, or data pulses are superposed on a pedestal pulse if the pedestal pulse is applied via the data electrodes, and characterised in that the polarity of the compensation pulse voltage (V cp ) is the same as that of the pedestal pulse voltage, the compensation pulse voltage (V cp ) is higher than the pedestal pulse voltage, and the voltage and duration of the compensation pulse (V c ) are adequate to generate a polarization charge in a cell equal to or more than a maximum polarization charge generated by a maximum virtual pedestal pulse voltage level effective at the cell. A method as claimed in claim 1, wherein the level of the compensation pulse voltage (V cp ) is substantially equal to the sum of the pedestal pulse voltage (V pp ) and the data (V dp ) or scan (V sp ) pulse voltage. A method as claimed in claim 2, wherein the compensation pulse voltage (V cp ) is formed by superposition of the pedestal pulse (V p ) and a scan (V s ) or data (V p ) pulse, or is provided from a source independent of those pulses. A method as claimed in any preceding claim, wherein pulse polarities are reversed from one cycle to the next. A method as claimed in any preceding claim, there being respective pluralities of switching elements (6-1 to 6-m; 7-1 to 7-n) for applying pulses to the data (D₁ to D m ) and scan (S₁ to S n ) electrodes, one of those pluralities comprising switching elements (7-1 to 7-n) of a push-pull configuration, each such element (7-1 to 7-n) having an output terminal connected to an electrode (S₁ to S m ) and having two power-receiving terminals connected, each in common (15, 16) with the corresponding terminals of the other such elements, to one of two pulse generators (3, 4; 3', 4'). A method as claimed in claim 5, wherein one such pulse generator (3, 4; 3', 4') is disconnected, to float the corresponding power-receiving terminal (15, 16), when the other said pulse generator (3, 4; 3', 4') is supplying pulses to the switching elements (7-1 to 7-n). A method as claimed in claim 6, wherein the said two pulse generators (3, 4; 3', 4') provide, respectively, supplementary (10, 11) pulses and pedestal (8, 9) pulses for providing scan voltage pulses to the scan electrodes (S₁ to S n ).

Inventors: AOKI, TETSUO FUJITSU LIMITED PATENT DEPT., KAWADA, TOYOSHI FUJITSU LIMITED PATENT DEPT., KOBAYASHI, TETSUYA FUJITSU LIMITED PATENT DEPT., MIYATA, HIROYUKI FUJITSU LIMITED PATENT DEPT., YAMAGUCHI, HISASHI FUJITSU LIMITED PATENT DEPT.
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: G09G3
IPC codes: G09G3