A thin film transistor array for liquid crystal display panel

Abstract: A thin film transistor array board includes an insulator substrate, a matrix of gate electrodes formed on the insulator substrate and covered with a gate insulator film, a matrix of semiconductor islands formed on the gate insulator film positioning on the gate electrodes, source wirings connected to the source regions of the semiconductor islands, drain wirings connected in common to the drain regions of the semiconductor islands aligned in the same line in parallel with the columns of the gate electrode matrix, a second insulator film covering the whole surface including the drain wirings, the source wirings, the semiconductor islands and the pixel electrodes, the second insulator film having grooves exposing the drain wirings with and auxiliary wirings formed in the grooves in contact with the drain wirings.

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a thin film transistor array, and more specifically to that used for a liquid crystal display panel. Description of the Related Art: The liquid crystal display panel has a thin film transistor array board in which a plurality of thin film transistors are disposed in a matrix form. Examples disclosing such thin film transistor arrays are United States Patent No. US-A-3,840,695 granted for Albert G. Fischer on October 8, 1974 and Japanese Un-examined Patent Publication No. JP-A-61-5577. Each transistor in those thin film transistor arrays has the so-called inverse-staggered structure and is formed of a gate electrode disposed on a transparent insulator substrate, a first insulator film formed on the insulator substrate to cover the electrode, a semiconductor layer covering the first insulator film on the gate electrode, source and drain electrodes of metal contacting upper surface of the semiconductor layer, the source and drain electrodes being separated from each other to form a gap above the gate electrode, a second insulator film covering all the structure, and a light-shield layer formed on the second insulator film above the gap between the source and drain electrodes. Each of the source and drain electrodes is formed of two layers, that is, an ohmic contact layer and a wiring layer. First of the two wiring layers is connected to a pixel electrode formed in adjacent to the semiconductor layer. Second of the two wiring layers is formed commonly to connect the corresponding wiring layers of a line of thin film transistors in the matrix. On the thin film transistor array board, a plurality of the semiconductor layers are disposed to form the matrix, the second wiring layer covering edges of the semiconductor layers. Therefore, if the second wiring layer is formed thin, the wiring layer easily generates an open-circuit at the edges of the semiconductor layers. In order to avoid the open-circuit the second wiring layer is usually made thick, for example, 2,000 Å which corresponds to 200nm. If the second wiring layer is made thick, the second insulator film must be made thick, for example, 300nm (3,000 Å), to protect it from generation of many cracks at edges of the wiring layers. The cracks cause short-circuit between the light-shield layer and the source or drain electrodes. The thick film of the second insulator film simultaneously covers the pixel electrodes and lowers electric field applied to liquid crystal to deteriorate contrast of displayed image. Patent Abstracts of Japan, Vol. 10, No. 141 (E-406) [2198] May 24, 1986 and JP-A-61 5576 teaches that each of the source and drain electrodes is formed by a transparent electrode and a column wiring layer is then formed in contact with each of the electrodes, the column wiring layer also serving as a light-shielding layer. Thus, the electrodes are arranged in the same column direction connected to one another by a single wiring layer. By this feature it is possible to form a light-shielding film without increasing in number the manufacturing steps. It is a primary object of the present invention to provide a thin film transistor array board which is formed with high production yield and without deteriorating the electrical performance. This object is achieved by the device according to the attached claims. Furthermore, the second column wiring layer is additionally provided as an upper layer on the source or drain electrodes. Even with the open-circuit of the first column wiring layer, the source or drain electrodes are maintained common-connected, by the second column wiring layer. Additionally,the source and drain electrodes and the first column wiring layers can be made thin, so that the second insulator film may be made thin to avoid generation of cracks therein. The thin film transistor array board is suitable to form a liquid crystal display panel in which a plurality of pixel electrodes are formed in connection to the other of respective pairs of source and drain electrodes and is covered with the second insulator film to apply electric field to liquid crystal through the second insulator film. The electric field applied to the liquid crystal is improved by making the second insulator film thin, to obtain an enhanced contrast of displayed image. BRIEF DESCRIPTION OF DRAWINGS The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings, wherein: Fig. 1 shows a circuit diagram of a liquid crystal display panel; Fig. 2 shows a partial plan view showing a thin film transistor array board according to a preferred embodiment of the present invention; Fig. 3 shows a sectional view taken along a line A-A′ of Fig. 2; and Fig. 4 shows a sectional view of a liquid crystal display panel using the thin film transistor array board of the present invention, the section of the thin film transistor array board corresponding to the line B-B′ of Fig. 2. DESCRIPTION OF THE PREFERRED EMBODIMENT A liquid crystal display panel has an equivalent circuit shown in Fig. 1. A plurality of data lines A₁, A₂, A₃, A₄, A₅ .... A n and a plurality of address lines B₁, B₂, B₃, B₄ .... B m cross orthogonally to form a lattice. At every crossing points, a picture element 1 is disposed. The picture element 1 has a thin film transistor 4 having a gate connected to an address line 7, a drain connected to a data line 6 and a capacitor 5 formed of a pixel electrode, a grounded common electrode and a liquid crystal interposed therebetween. Thin film transistors connected to address lines applied with address signals and data lines applied with data signals turn on to change the liquid crystal in the capacitors connected to the transistors into opaque state. The liquid crystal display panel is formed of a thin film transistor array board 120, a common electrode board 121 and a liquid crystal interposed therebetween, as shown in Fig. 4. The common electrode board 121 is composed of a transparent insulator substrate 115 and a common electrode layer 114 metalized on the substrate 115. The thin film transistor array board 120 is also shown in Fig. 2 in plan view and in Fig. 3 in sectional view. A thin film transistor array is formed on a glass substrate 101 or other transparent insulator substrate. A plurality of gate electrodes 102 of Cr having a thickness of 1,500 Å (1Å = 0.1nm) are formed on the substrate 101 in form of a matrix. The gate electrodes 102 in the same row lines are electrically connected in common with address lines 117. An insulator film 103 of SiNx having a thickness of 2, 000 Å is formed on the glass substrate 101 covering the gate electrodes 102 so as to operate as a gate insulator film but is not formed on the electrode pad region of the substrate 101. On the insulator film 103 above the gate electrodes 102 and their peripheries, amorphous silicon (a-Si:H) films 104 having a thickness of 1,500 Å are formed without impurity doping. Pixel electrodes 106 of ITO (indium-tin-oxide) having a thickness of 1,000 Å or other transparent metal are formed in adjacent to respective amorphous silicon films 104. Ohmic contact layers 105 of n⁺-amorphous silicon (a-Si:H) having a thickness of 100 Å are formed on source and drain regions of respective amorphous silicon films 104. On the contact layers 105 on the source regions, source wirings are deposited so as to extend on the pixel electrode 106. Drain wirings 108 are formed on the ohmic contact layers 105. The drain wirings 108 are extended on the insulator film 103 as data lines 119. The source wirings 107, the drain electrodes 108 and the data lines 119 are formed in the same process with the ITO or a metal such as Ti or Cr having a thickness in a range from 500 to 1,000 Å. The data lines 119 electrically connect the drain electrodes 108 in the same columns in common and are led out to the edge portion of the glass substrate 101 where the data lines 119 are widened and directly disposed on the substrate 101 to form pad electrodes 118. A passivation film 109 of SiOx (x = 1.6 to 2.4) having a thickness of 2,000 Å or SiNx (x = 1.1 to 1.5) having a thickness of 3,000 Å covers the source and drain wirings 107 and 108, the address and data lines 117 and 119, the amorphous silicon films 104 exposing between the source and drain wirings 107 and 108, the pixel electrodes 106 and the insulator film 103. The passivation film 109 has grooves or elongated apertures which extend from one edge of the array to the opposite edge and expose a part (partial width) of the drain wirings 108 and the data lines 119 throughout each column. The length of each groove (aperture) is as long as each column and its width is smaller than the width of the drain wiring 108 and the data line 119. Auxiliary column wiring layers 111 are additionally formed in every columns, overlapping every data lines 119. The width of the auxiliary column wiring layer 111 is larger than that of the groove in the passivation film 109, so that the layers 111 are formed within the every grooves to contact with the exposed portion of the drain wirings 108 and the data lines 119 and their side edges are extended onto the film 109 on the both sides of each groove. The wirings 111 are formed of Aℓ or Cr in a thickness within a range from 2,000 Å to 5,000 Å by evaporation process and selective etching process. Through the same processes, light-shielding metal islands 110 are formed on the film 109 above the gate electrodes. The thin film transistor array board 120 according to the preferred embodiment of the present invention has the auxiliary wiring 111 contacting with the drain wirings 108 and the data lines 119. Therefore, the data lines 119 can be made thin to an extent that open-circuit may occur at edges of the amorphous silicon films 104 because the broken wirings are connected by the auxiliary wirings 111 which can be made so thick that open-circuit may not occur. The thin data lines 119 allow the passivation film 109 to be thin enough to avoid cracks. The manufacturing loss due to the open-circuit of the data lines and cracks of the passivation film 109 can be reduced to a value of 0.01% to 0.001% from the conventional value of 0.5 to 1%. Moreover, since the passivation film 109 can be made thin, electric field applied to the liquid crystal 113 from the pixel electrodes 106 becomes strong to achieve a high contrast image. Although only one preferred embodiment has been explained, many modifications are applicable to the preferred embodiment. The amorphous silicon can be extended under all the data lines 119 with contacting thereto. It is sufficient that each auxiliary wiring 111 is partially connected to each data line 119. Therefore, the auxiliary wiring can be absent at the portions over the drain wirings 108. Furthermore, the pixel electrodes 106 may be formed in the same process as the formation of the source wirings with the same material. The amorphous silicon (a-Si:H) may be replaced with other semiconductor material such as II-VI compound semiconductor or polycrystalline silicon.

Claims: A thin film transistor array (120) comprising: an insulator substrate (101); a plurality of gate electrodes (102) formed on said insulator substrate in form of a matrix of columns and rows; a plurality of row connecting means formed on said insulator substrate connecting said gate electrodes in the same rows in common; a first insulator film (103) covering at least said gate electrodes and said row connecting means; a plurality of semiconductor layers (104) formed on said first insulator film at locations above said gate electrodes and peripheral portions thereof, each of said semiconductor layers having a source region (105), a drain region (105) and a channel region locating therebetween; a plurality of source electrodes (107) connected to said source regions of said semiconductor layers, respectively; a plurality of drain electrodes (108) connected to said drain regions of said semiconductor layers, respectively; a second insulator film (109) covering at least said channel region, said source electrodes and said drain electrodes; and a plurality of first column wiring layers (111) running column direction; characterized in that said drain electrodes (108) are extended in said column direction to form second column wiring layers (119) which connect said drain regions arranged in the same column in common to one another and that each of said second column wiring layers (119) is connected to a corresponding one of said column wiring layers (111) through an aperture (112) provided in said second insulator film (109). A thin film transistor array as claimed in claim 1, wherein said thin film transistor array (120) is employed in a liquid crystal display pannel in which liquid crystal (113) is interposed between said array (120) and a common electrode board (121).

Inventors: NOGUCHI KESAO C O NEC CORPORAT, NOGUCHI, KESAO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1987
Main classification: H01L27
IPC codes: G09F9, G02F1, H01L29, H01L27