CIPHER SYSTEM

Abstract: In a cipher system used in trasmission or storage of digital data, the encipherment section comprises a first modulo-2 adder (108) for adding, bit by bit, the k-bit contents of a first shift register (106) storing latest k bits of ciphertext information and the k-bit contents of a first register (107). The k-bit output of the first modulo-2 adder is expanded into m × n bits, which are sotred in a second register (110), and extracted in sequence, a set of n bits at a time. Each set of n bits is converted into a single bit. A second modulo-2 (113) adder adds the 1 bit output to the contents of a third register (112) or bistable means, which stores the output of the second adder. A fifth register (115) or bistable means stores plaintext information input through the input terminal. A third modulo-2 (103) adder adds the output of the second adder to the contents of a register or bistable means storing plain text information to produce ciphertext information. A sixth register (104) or bistable means stores the output of the third adder. The contents of the sixth register or bistable means are fed back to the first shift register (106), and are also output as ciphertext information.

Description: Field of Invention The invention relates to a cipher system used in transmission or storage of digital data for preserving secrecy on the transmission path or the storage media and to encipherment methods and decipherment methods for use in such a system and to terminals and apparatus for use in such a system or method. Background of the Invention Examples of prior art cipher systems are shown in proceedings of the 3rd Symposium on Information Theory and its Application, Nov. 1980, pp 371-377 'Some Consideration on a Simple Self-Synchronizing Encryption System' (this publication will be hereinafter referred to as Reference 1), a Cryptography: A New Dimension in Computer Data Security, by Stephen M. Matyas, published by John Wiley and Sons, New York, U.S.A., pp. 88-100 (this publication will be hereinafter referred to as Reference 2). Figure 9 is a block diagram showing an encryption system described in Reference 2. A similar system is also disclosed in patent number CH 648167. In this system, 64-bit block cipher is used in a 1 bit CFB (Cipher Feed Back) mode. The left hand side of the Figure is an encipherment section including an input terminal 901, a modulo-2 adder 902, a shift register 903, a 64-bit block encipherment unit 904, and a register 905. The right hand side of the Figure is a decipherment section including a shift register 907, a 64-bit block encipherment unit 908, a register 909, a modulo-2 adder 910, and an output terminal 911. The encipherment section and the decipherment section are connected by a transmission path 906. A bit series of plaintext is input through the input terminal 901 of the encipherment section, and is added at the adder 902 to the 1 bit at the left end of the register 905, to be enciphered. The enciphered bit series (ciphertext) is transmitted through the transmission path 906 to the decipherment section. The enciphered bit series is also fern back to the shift register 903, and stored in it for a predetermined time, or for a predetermined number of operation cycles being shifted through the shift register 903 The 64-bit contents of the shift register 903 are input in parallel to the 64-bit block-encipherment unit 904 and converted into 64-bit data. The data output from the block-encipherment unit 904 are stored in a 64-bit register. Only the leftmost bit of the register 905 is applied to the modulo-2 adder 902 for encipherment. The above operations are repeated, and the plaintext input through the input terminal 901 is enciphered bit by bit and transmitted through the transmission path to the decipherment section. The ciphertext received at a decipherment section is stored in a shift register 907 for a predetermined time and is also sent to the modulo-2 adder 910, at which the ciphertext and the leftmost bit of the register 909 is added, by which decipherment is performed. The deciphered text is output through an output terminal 911. The shift register 907, the 64-bit block-encipherment unit 908, and the register 909 perform operations similar to those of the shift register 903, the 64-bit block encipherment unit 904 and the register 905. Only if the encipherment key set in the 64-bit block encipherment unit 904 and the decipherment key set in the 64-bit block encipherment unit 908 are identical do the contents of the registers in the encipherment section and the decipherment section coincide with each other. The information identical to the information input through the input terminal 901 is output through the output terminal 911. Figure 10 is a block diagram showing a cipher system disclosed in Reference 1. In the illustrated system, instead of the 64-bit block-encipherment units code converters (such as ROM) 924 and 928 storing code patterns corresponding to the respective encipherment keys are used. The system further includes an input terminal 921, modulo-2 adders 922 and 926, shift registers 923 and 927, a transmission path 925, and an output terminal 929. Summary of the invention The invention provides apparatus comprising an encipherment unit for enciphering plaintext bit by bit into ciphertext and a decipherment unit for deciphering ciphertext bit by bit into plaintext; the encipherment unit including a k -bit shift register for receiving successive ciphertext bits, encoding means for generating a single output bit as a function of the k bits of the shift register and means for combining successive bits output from the encoding means with successive plaintext bits to generate the ciphertext; the decipherment unit including a k -bit shift register for receiving successive ciphertext bits, encoding means for generating a single output bit as a function of the k bits of the shift register and means for combining successive bits output from the encoding means with successive ciphertext bits to generate the plaintext; the encoding means of the encipherment unit and the decipherment unit being identical and being characterized by including means for combining the content of the respective encipherment or decipherment shift register once with a cipher key and then expanding the result to give an m x n bit output, a code converter for encoding m successive blocks of n bits of the expanded output into a sequence of m bits by encoding each block o f n bits into a single bit and means for sequentially combining those m bits to produce the single output bit of the encoding means; where k , m and n are integers satisfying m x n > k . The encipherment unit and the decipherment unit may reside in a common terminal and share a single encoding means in a time-sharing manner. The invention also provides a method of enciphering plaintext bit by bit into ciphertext and deciphering ciphertext bit by bit into plaintext, comprising the steps of: enciphering the plaintext by storing successive ciphertext bits in a k -bit shift register, encoding the content of the shift register to generate successive single output bits and combining the successive single output bits with successive plaintext bits to generate the ciphertext; deciphering the ciphertext by storing successive ciphertext bits in a k -bit shift register, encoding the content of the shift register to generate successive single output bits and combining the successive single output bits with successive ciphertext bits to generate the plaintext; the operation of encoding the content of the shift register being identical during encipherment and decipherment and being characterized in that it consists of combining the content of the respective shift register once with a cipher key and then expanding the result to an m x n bit output, followed by converting m successive blocks of n bits of the expanded output into a sequence of m bits by encoding each block of n bits into a single bit according to a predetermined code and sequentially combining those m bits to produce the single encoded output bit; where k , m and n are integers satisfying m x n > k . Preferably, during encipherment the successive encoded single bits are added to the successive plaintext bits to generate the ciphertext and during decipherment the successive encoded single bits are added to the successive ciphertext bits to generate the plaintext. The method may be implemented simply in dedicated hardware for quick, real time operation. The correlation between the plaintext and the ciphertext may be made small, that is to say the ciphertext provides no clue as to the structure of the plaintext, and synchronization is automatically restored upon expiration of time proportional to the length of the shift register even after the occurrence of a transmission path error or after synchronization has been lost. The whole enciphered word formed by adding the shift register word and the encipherment key can be used for code conversion, not merely one bit thereof. The encipherment portion can be constructed fairly simply and cheaply and can be implemented in hardware form to provide a relatively high throughput without requiring necessarily any software assistance. The code converter can operate with a large encipherment key and a long shift register without unrealistic code conversion items. Other preferred features of the invention are described by reference to Figures 1 to 8 and the claims. DRAWINGS: Figure 1 is a block diagram showing a general configuration of a first embodiment of the invention; Figure 2 is a block diagram showing an environment in which the encipherment section and the decipherment section are used; Figure 3 is a circuit diagram showing a configuration of an encipherment unit; Figure 4 is a circuit diagram showing a configuration of a decipherment unit; Figure 5 is a timing chart showing data signals and control signals; Figure 6 is a diagram showing an example of truth table explaining the operation of the code converter; Figure 7 is a block diagram showing a second embodiment of the invention; Figure 8 is a timing chart showing data signals and control signals; Figures 9 and 10 are block diagrams showing prior art cipher systems shown and described in the Literatures 2 and 1, respectively. Description of Inventive Embodiments With reference to Figure 1 its left side is an encipherment section comprising an input terminal 101 for inputting plaintext information into a register 102 for storing the inputted plaintext, a modulo-2 adder 103 adding one bit of the plaintext stored in the register 102 and one bit stored in the register 115 which stores one-bit output of the modulo-2 adder 113, a register 104 storing the output of the adder 103, a feedback path or loop 105 for feed back of the output of the adder 103 stored in the register 104 to a shift register 106 whose length is k bits, a modulo-2 adder 108 for adding the bits of the contents of the shift register 106 to the respective bits of the contents of the register 107, an expander 109 for expanding the k-bit output of the modulo-2 adder 108 into m x n bit data, a register 110 for storing the output of the expander 109, a controller for controlling the contents of the register 110 to be input, n bits at a time to a code converter 112 which converts each set of n bits into a single bit, a modulo-2 adder 113 for adding the output of the code converter 112 and the output of the register 114, which stores the 1-bit output of the adder 113, a register 115 for storing the output of the adder 113, an output terminal 116 for outputting the contents of the register 104 as ciphertext, and a control signal generator (not shown) for generating, responsive to a master clock and a transmission clock, a control signal by which input the contents of the register 110 are sequentially input, n bits at a time, into the code converter 112, a RESET signal for the register 114, a WRITE signal for the register 114, a WRITE signal for the register 115, a WRITE signal for the register 104, and the like. The output from terminal 116 passes along a signal transmission path 117 to a decipherment section. The right side of Figure 1 is the decipherment section, which comprises an input terminal 118 for inputting ciphertext information from the encipherment section, a register 119 for storing the ciphertext input through the input terminal 118, a modulo-2 adder 120 for adding the Single bit ciphertext information stored in the register 119 to the output of the adder 129 stored in the register 131, a feedback path or loop 121 for feeding back the ciphertext to a shift register 122 having a k-bit length, a register 123 storing a k-bit decipher key, a modulo-2 adder 124 for adding bit by bit the contents of the shift register 122 to the contents of the register 123, an expander 125 for expanding the k-bit output of the adder 124 into m x n bits, a register 126 for storing the output of the expander 125, a controller 127 for performing control to input the contents of the register 126, n bits at a time, into a code converter 128, which converts each set of n bits output from the controller 127 into single bit data, a modulo-2 adder 129 adding the output of the code converter 128 and the output of the register 130 which stores the 1-bit output of the adder 129, another register 131 which stores the 1-bit output of the adder 129, a register 132 which stores the output of the adder 120, an output terminal 133 for outputting the contents of the register 132 as a deciphered information, and a control signal generator, not shown, that receives a master clock and a transmitted clock and produces a control signal for controlling the contents of the register 126 to be input into the code converter 128, in sequence, n bits at a time, a RESET signal for the register 130, a WRITE signal for the register 130, a WRITE signal for the register 131, a WRITE signal for the register 132, and the like. In the above description k, m, and n are arbitrary integers that satisfy m x n > k. Figure 2 is a block diagram showing the overall arrangement of the above embodiment. Figure 3 and Figure 4 are circuit diagrams showing the encipherment section 202 and the decipherment section 206 of the embodiment of Figure 2. In Figures 3 and 4, it is assumed that k = 32, m = 8, n = 8. The invention does not limit k, m and n to the above values. In Figure 2, data signal generated from the data generator 201 and a timing signal indicating the READ timing of the data signal are supplied to the encipherment section 202. At the encipherment section 202, the data being supplied is enciphered and the timing signal is sent to the transmitter 203. The transmitter 203 converts the data into a form of signal suitable for transmission via the transmission path, and transmits the converted data over the transmission path. The receiver 205 receives the signal from the transmission path 204 and extracts, from he received signal, the data signal and the timing signal and sends them to the decipherment section 206. The decipherment section 206 deciphers the data and sends the deciphered data to the data receiver 207. In a conventional data transmission in which the transmitted information is not enciphered, a data signal line for transmission of data, and a timing signal for synchronizing the transmission of data signal are required. According to the embodiment of the invention, the signals which must be provided in the working environment are these two signals: the data signal and the timing signal. The encipherment section will be described in detail with reference to Figure 3. Figure 5 shows the relative timing of the data signal and the control signals. The timing signal Tc indicates the READ timing of the input data. Other control signals Sc, Dr, Wc, SEL1 to SEL8, Dc and Lc are generated by a controller, not shown, having logic circuit configured to generate the signals at timings shown in Figure 5, using the timing signal Tc as a trigger and using the internal clock CLK. The control signal Sc, triggered by the falling edge of the timing signal Tc, shifts the contents of the four shift registers 306-1 to 306-4 one bit to the right. Simultaneously therewith, the data that have been held in the flip-flop 304 are shifted in the shift register 306-1. The control signal Dr is generated at the same timing as the control signal Sc, by which the flip-flop 312 is reset. Four registers 307-1 to 307-4 store encipherment keys and are called encipherment key registers. The encipherment keys are set in advance from the outside. Data from the shift register 306 (306-1 to 306-4) and data from the registers 307 (307-1 to 307-4) are added at modulo-2 adders 308 (308-1 to 308-4). The result of the addition are written in the registers 309 (309-1 to 309-8). The outputs of the adder 308 and the input of the register 309 are so connected that each bit of the result of the addition is supplied to two registers. The output of the registers 309 are three-state outputs. When one of the control signals SEL (SEL1 to SEL8) is high, the signal from the corresponding register is input into the code converter 310. As shown in Figure 5, first the control signal SEL1 is made high, and the contents of the register 309-1 are input into the code converter 310. The code converter 310 is formed of a ROM (read-only-memory) or a random logic circuit. It outputs either '1' or '0'. Its input consists of 8 bits and its output consists of one bit. The value of the output '1' or '0' is unequivocally defined against each of the 2⁸ = 256 values of the input. An example of the truth table showing the input-output relationship of the code converter 310 is shown in Figure 6. The output of the code converter 310 is passed through the modulo-2 adder 311, after the flip-flop 312 is reset, and applied to the flip-flops 312 and 313 and held at the flip-flop 312 at the timing of the control signal DC. Next the control signal SEL 2 is turned high and the contents of the register 309-2 are input into the code converter 310. The output of the code converter 310 is added at the modulo-2 adder 311 to the output of the flip-flop 312, and the result of the addition is held in the flip-flop 312 at the timing of the control signal Dc. Similar processes are repeated responsive to the control signals SEL3 to SEL7. When the last control signal SEL8 is turned high, the contents of the register 309-8 are input into the code converter 310, whose output is added at the adder 311 to the output of the flip-flop 312. The result of the addition is applied to the flip-flops 312 and 313 and is held in the flip-flop 313 at the timing of the control signal Lc. The plaintext data input through the input terminal 301 is held in the flip-flop 302 at the rising edge of the timing signal Tc. The outputs of the flip-flops 313 and 302 are added at the adder 303, and the sum is held at the falling edge of the timing signal Tc. The contents of the flip-flop 304 is output to a ciphertext through the output terminal 305. The decipherment section will now be described with reference to Figure 4. As illustrated, it comprises an input terminal 401, a flip-flop 402, an adder 403, a flip-flop 404, an output terminal 405, shift registers 406-1 to 406-4, registers 407-1 to 407-4, adders 408-1 to 408-4, registers 409-1 to 409-8, a code converter 410, an adder 411, and flip-flops 412 and 413. The operation of the decipherment section is identical to the operation of the encipherment section except that the information input through the input terminal is ciphertext, and the information output through the output terminal is a deciphered text, and the data fed back to the shift register is not the output of the flip-flop 404 corresponding to the flip-flop 304 of Figure 3 but the output of the flip-flop 402 corresponding to the flip-flop 302 of Figure 3. In the above embodiment, the relationship between the plaintext Pt, and the ciphertext Ct and the deciphered text P't at time t can be expressed as follows: in the below expression e₁, e₂,....e₃₂ and d₁, d₂, ....d₃₂ denote encipherment key and decipherment key, respectively, and F denotes the function of the code converters 118 and 128. C t = P t + ○F(e₂₉+ ○C t-29 ,e₃₀+ ○C t-30 e₃₁+ ○C t-31 ,e₃₂ + ○C t-32 ,e₁+ ○C t-1 , ... e₄+ ○C t-4 ) + ○F(e₁+ ○C t-1 ,e₂+ ○C t-2 ,e₃+ ○C t-3 ,e₄ + ○C t-4 ,e₅+ ○C t-5 , ... e₈+ ○C t-8 ) + ○F(e₅+ ○C t-5 ,e₆+ ○C t-6 ,e₇+ ○C t-7 ,e₈ + ○C t-8 ,e₉+ ○C t-9 , ... e₁₂+ ○C t-12 ) + ○F(e₉+ ○C t-9 ,e₁₀+ ○C t-10 ,e₁₁+ ○C t-11 ,e₁₂ + ○C t-12 ,e₁₃+ ○C t-13 , ... e₁₆+ ○C t-16 ) + ○F(e₁₃+ ○C t-13 ,e₁₄+ ○C t-14 ,e₁₅+ ○C t-15 ,e₁₆ + ○C t-16 ,e₁₇+ ○C t-17 , ... e₂₀+ ○C t-20 ) + ○F(e₁₇+ ○C t-17 ,e₁₈+ ○C t-18 ,e₁₉+ ○C t-19 ,e₂₀ + ○C t-20 ,e₂₁+ ○C t-21 , ... e₂₄+ ○C t-24 ) + ○F(e₂₁+ ○C t-21 ,e₂₂+ ○C t-22 ,e₂₃+ ○C t-23 ,e₂₄ + ○C t-24 ,e₂₅+ ○C t-25 , ... e₂₈+ ○C t-28 ) + ○F(e₂₅+ ○C t-25 ,e₂₆+ ○C t-26 ,e₂₇+ ○C t-27 ,e₂₈ + ○C t-28 ,e₂₉+ ○C t-29 , ... e₃₂+ ○C t-32 ) P' t =C t + ○F(d₂₉+ ○C t-29 ,d₃₀+ ○C t-30 ,d₃₁+ ○C t-31 ,d₃₂ + ○C₁₋₃₂,d₁+ ○C t-1 , ... d₁+ ○C t-4 ) + ○F(d₁+ ○C t-1 ,d₂+ ○C t-2 ,d₃+ ○C t-3 ,d₄ + ○C t-4 ,d₅+ ○C t-5 , ... d₈+ ○C t-8 ) + ○F(d₅+ ○C t-5 ,d₆+ ○C t-6 ,d₇+ ○C t-7 ,d₈ + ○C t-8 ,d₉+ ○C t-9 , ... d₁₂+ ○C t-12 ) + ○F(d₉+ ○C t-9 ,d₁₀+ ○C t-10 ,d₁₁+ ○C t-11 ,d₁₂ + ○C t-12 ,d₁₃+ ○C t-13 , ... d₁₆+ ○C t-16 ) + ○F(d₁₃+ ○C t-13 ,d₁₄+ ○C t-14 ,d₁₅+ ○C t-15 ,d₁₆ + ○C t-16 ,d₁₇+ ○C t-17 , ... d₂₀+ ○C t-20 ) + ○F(d₁₇+ ○C t-17 ,d₁₈+ ○C t-18 ,d₁₉+ ○C t-19 ,d₂₀ + ○C t-20 ,d₂₁+ ○C t-21 , ... d₂₄+ ○C t-24 ) + ○F(d₂₁+ ○C t-21 ,d₂₂+ ○C t-22 ,d₂₃+ ○C t-23 ,d₂₄ + ○C t-24 ,d₂₅+ ○C t-25 , ... d₂₈+ ○C t-28 ) + ○F(d₂₅+ ○C t-25 ,d₂₆+ ○C t-26 ,d₂₇+ ○C t-27 ,d₂₈ + ○C t-28 ,d₂₉+ ○C t-29 , ... d₃₂+ ○C t-32 ) Each terminal of the cipher system can comprise an encipherment section and a decipherment section as shown in Figure 3 and Figure 4. But as many of the circuit elements and interconnections of the encipherment section are identical to those of the decipherment sections and as they are not used for the two-purposes simultaneously' they can be shared for encipherment and decipherment if a suitable reconnection arrangement is provided. Figure 7 shows an example of a terminal having such an arrangement. As shown it comprises an input terminal 701 for receiving a plaintext, a flip-flop 702, an input terminal 801 for receiving ciphertext, a flip-flop 802, adders 703, 803, flip-flops 704, 804, output terminals 705, 805, shift registers 706-1 to 706-4, 806-1 to 806-4, registers 707-1 to 707-4, adders 708-1 to 708-4, registers 709-1 to 709-8, a code converter 710, an adder 711, a flip-flop 712, flip-flops 713, 813, switches 751, 752, 753, and 754-1 to 754-4. Signals similar to those shown in Figures 3 and 4 are denoted by identical numberals with a prime ('). In the embodiment of Figure 7, all circuit elements in the encipherment section and the decipherment section, except the shift registers, are shared. Part of their interconnections are altered by the switches for operation as an encipherment section or as a decipherment section. In other words, they are used in a time-sharing manner. Plaintext is input through the terminal 701 and ciphered and output through the terminal 705. The ciphertext that is received is input through the terminal 801 and the deciphered text is output through the terminal 805. The timings of various data and control signals are shown in Figure 8. Switching between encipherment and decipherment is effected by means of a control signal E/D. The operation of the terminal connected for encipherment is identical to that described in connection with Figure 3. The operation of the terminal connected for decipherment is identical to that described in connection with Figure 4. As has been described, according to the invention, the contents of the shift register are added to the contents of the register storing the encipherment key or of the register storing the decipherment key, and the sum is applied to the code converter. Regardless of the number of keys, the code converter needs only one set of patterns. Moreover, data consisting of m x n can be divided into sets of n bits, and each set of n bits are input into the code converter. The number of patterns of the code converter need not be more than 2 n . The size of the code converter can therefore be reduced or the capacity of ROM can be reduced. For instance the code converter formed of a ROM, and m = 16, n = 8, k = 64 the capacity of the ROM need only to be 2⁸ = 256 bits. Moreover, the complicated divisional processing or the repeated process bit manipulation as a 64-bit block encipherment, DES for instance, need not be performed but minute variation in the encipherment/decipherment key or in the plaintext information can be enlarged in the ciphertext information or deciphered text information.

Claims: Apparatus comprising an encipherment unit for enciphering plaintext bit by bit into ciphertext and a decipherment unit for deciphering ciphertext bit by bit into plaintext; the encipherment unit including a k -bit shift register (106) for receiving successive ciphertext bits, encoding means for generating a single output bit as a function of the k bits of the shift register (106) and means (103) for combining successive bits output from the encoding means with successive plaintext bits to generate the ciphertext; the decipherment unit including a k -bit shift register (122) for receiving successive ciphertext bits, encoding means for generating a single output bit as a function of the k bits of the shift register (106) and means (120) for combining successive bits output from the encoding means with successive ciphertext bits to generate the plaintext; the encoding means of the encipherment unit and the decipherment unit being identical and being CHARACTERIZED BY including means (108,124) for combining the content of the respective encipherment or decipherment shift register (106,122) once with a cipher key and then expanding the result to give an m x n bit output, a code converter (112,128) for encoding m successive blocks of n bits of the expanded output into a sequence of m bits by encoding each block o f n bits into a single bit and means for sequentially combining those m bits to produce the single output bit of the encoding means; where k, m and n are integers satisfying m x n > k . Apparatus according to claim 1, wherein the encipherment unit and the decipherment unit reside in a common terminal. Apparatus according to claim 2, wherein the encipherment and decipherment units share a single encoding means in a time-sharing manner. Apparatus according to any preceding claim, wherein the encoding means further comprises: a first register (107,123) storing the cipher key of k bits; a first adder (108,124) for adding bit by bit the k bits of the respective shift register (106,122) to the k bits of the cipher key; an expander (109,125) for expanding the k -bit output of the first adder (108,124) into m x n bits; a second register (110,126) for storing the m x n bits output by the expander (109,125); a controller (111,127) for extracting in sequence the contents of the second register (110,126), a block of n bits at a time, for input to the code converter (112,128); a single bit third register (114,130); a second adder (113,129) for adding the m successive single bits output by the code converter (112,128) to the content of the third register (114,130) and storing each result in the third register (114,130), the final result of the m successive additions by the second adder (113,129) forming the output of the encoding means. Apparatus according to any preceding claim, wherein: the means (103) in the encipherment unit for combining the successive bits output from the encoding means with the successive plaintext bits to generate the ciphertext is an adder; and the means (120) in the decipherment unit for combining the successive bits output from the encoding means with the successive ciphertext bits to generate the plaintext is an adder. A method of enciphering plaintext bit by bit into ciphertext and deciphering ciphertext bit by bit into plaintext, comprising the steps of: enciphering the plaintext by storing successive ciphertext bits in a k -bit shift register, encoding the content of the shift register to generate successive single output bits and combining the successive single output bits with successive plaintext bits to generate the ciphertext; deciphering the ciphertext by storing successive ciphertext bits in a k -bit shift register, encoding the content of the shift register to generate successive single output bits and combining the successive single output bits with successive ciphertext bits to generate the plaintext; the operation of encoding the content of the shift register being identical during encipherment and decipherment and being CHARACTERIZED IN THAT it consists of combining the content of the respective shift register once with a cipher key and then expanding the result to an m x n bit output, followed by converting m successive blocks of n bits of the expanded output into a sequence of m bits by encoding each block o f n bits into a single bit according to a predetermined code and sequentially combining those m bits to produce the single encoded output bit; where k, m and n are integers satisfying m x n > k . A method according to claim 6, wherein: during encipherment, the successive encoded single bits are added to the successive plaintext bits to generate the ciphertext; and during decipherment, the successive encoded single bits are added to the successive ciphertext bits to generate the plaintext.

Inventors: NAKAI, TOSHIHISA
Applicants: OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1987
Main classification: H04L9
IPC codes: G09C1, H04L9