Input/output apparatus and method of processing image data

Abstract: There is disclosed an apparatus comprising: input means for inputting multi-value data having gradation; identifying means for identifying a tone-graphic part and a line-image part from data inputted through said input means; and output means for combining the tone-graphic part and the line-image part and outputting thus combined data. By this means data representing tone-graphic and line image parts of an image are identified, processed and combined to reproduce the image. There is detailed an apparatus including a multi-level converter for converting multi-level value image data into bi-level value image data and vice versa, a resolution converter operated in synchronism with the multi-level converter to convert a resolution of the multi-level value image data, an area data memory for storing area data corresponding to an instruction input representing a multi-level or bi-level value image area, and an output device for selecting the multi-level value image data from the resolution converter or the multi-level value image data from the multi-level converter on the basis of the area data and for outputting selected data to an image output device.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method or system for processing composite image data. Related Background Art Typical conventional image data processing systems are directed to two types of systems, that is, a processing system for processing bi-level value image data such as document, character, and drawing data and a multi-level value image data processing system for processing a halftone image (a multi-level value image) such as a photograph. The bi-level value image data processing system primarily aims at improvement of resolutions rather than that of gradation expressions. The multi-level value image data processing system primarily aims at improvement of gradation expressions rather than that of resolutions. When an image including characters and a photograph is to be input to a conventional image processing system, gradation (or reproducibility of gray scale levels) of the photograph area is limited in the bi-level value image data processing system while a resolution of the character area is low in the multi-level value image data processing system. Multi-level value image data can be expressed in a pseudo halftone mode by converting the same into bi-level value image data according to a dither method or a density pattern method. However, such a conventional technique has limitations, gradation an resolution are undesirably impaired, and a moiré pattern is formed. In this manner, image degradation inevitably occurs. Another conventional technique is also available to recognise character and halftone areas of document data and to reproduce only the halftone area in a pseudo halftone mode. However, gradation and resolution are inevitably degraded. US-A-4 004 079 describes a method for reproducing images in which the images are scanned at high resolution and the high resolution signals so obtained are combined to produce signals of lower resolution which may then be used for producing continuous tone gray level image information. EP-A-0122430 discloses an image processing apparatus which has a character code buffer for receiving decoded character signals and generating data presenting the designated character image portion in response to a character read address signal. The apparatus also has a character generator for converting the read-out data to dot data, a character image memory for storing the dot data in a memory area in response to a character write address signal, an image buffer memory for receiving decoded image data and for outputting data representing a designated half-tone image region in response to a half-tone read address signal, processing circuit blocks for performing a series of predetermined operations for the read-out data and a halftone image memory for storing the processed data in response to a halftone write address signal. Attention may also be drawn to EP-A-0158155. In accordance with one aspect of the present invention there is provided a method of processing information in accordance with claim 1. In accordance with another aspect of the present invention there is provided an image processing apparatus in accordance with claim 5. The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 and 4 are block diagrams of data processing systems according to embodiments of the present invention; Figs 2 is a plan view showing display contents; Fig. 3 is a view for explaining selection signals; Fig. 5 is a view for explaining a technique for supplying a selection signal (SEL SIG) which designates types of logical operation; Fig. 6 is a table showing the relationship between the selection signals and logical operations; Fig. 7 is a table showing actual results of logical operations; Fig. 8 is a perspective view of an image data processing system according to another embodiment of the present invention; Fig. 9 is a block diagram of the image data processing system shown in Fig. 8; Fig. 10A is a view for explaining operation (shift) of a BMU 117 shown in Fig. 9; Fig. 10B is a view for explaining operation (extraction) of the BMU 117 shown in Fig. 9; Fig. 11 is a block diagram showing the detailed arrangement of an SP-I/F 114 shown in Fig. 9; Fig. 12 is a view for explaining a technique for causing an operator to designate a character area and a photographic area; Fig. 13 is a view for explaining a technique for causing an image area separating circuit 139 to automatically designate a character area and a photographic area without designation by an operator; Figs. 14 to 17 are flow charts for explaining the control sequence of the image data processing system shown in Fig. 8; Fig. 18 is a view for explaining recording of an image including character and photographic areas in an OD 105; Figs. 19-1 and 19-2 are flow charts for explaining an operation for printing out image data recorded in the OD 105; Fig. 20 is a block diagram of an image processing system employing an interface circuit according to still another embodiment of the present invention; Fig. 21A is a view showing image data input from an image scanner; Fig. 21B is view showing print-out image data representing that the photographic area of image data of Fig. 21A is shifted; Figs. 22 (a) to 22(e)are views showing image editing procedures and changes in states of buffers during image editing; and Fig. 23 is a block diagram showing a modification of the image processing system employing the interface circuit shown in Fig.20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 is a CRT display system according to a first embodiment of the present invention, in which bi-level value image data such as character and graphic patterns and multi-level value image data such as photographs are simultaneously displayed, and an area of multi-level value image data can be arbitrarily designated. A recording medium 1 stores a multi-level digital video signal (4 bits/pixel) for displaying multi-level value image data. This medium will be referred to as a multi-level value memory 1 hereinafter. A recording medium 2 stores a bi-level digital video signal (1 bit/pixel) for displaying bi-level image data. This recording medium will be referred to as a bi-level value memory 2 hereinafter. A multi-level digital video signal 3 is then read out from the multi-level value memory 1. A data selector 6 selects the multi- or bi-level digital video signal 3 or 4 in response to a selection signal 5. The signal selected by the data selector 6 is converted into an analog signal by a D/A converter 7. An amplifier 8 amplifies the analog video signal converted by the D/A converter 7 and the amplified signal is used to luminance-modulate a CRT 9. The CRT 9 is operated in response to vertical (V) and horizontal (H) sync signals 10. A multi-level value reading signal 11 instructs theread of data from the memory 1 and also is used as an address signal for the memory. A bi-level digital video signal 4 is read out from the bi-level value memory 2. A bi-level value reading signal 12 instructs the read of data from the memory 2 and also is used as an address signal for the memory. A control circuit 13 controls the read/write from and into the memories land 2, and the selection of the memory 1 or 3. Fig. 2 shows a case wherein multi-level value data in a free area is displayed in bi-level value data, and Fig.3 shows a memory map for control of addressing of the free area. As shown in Fig. 2, a control memory may be arranged in which the areas represented by logic "1" and logic "0" are predetermined. The contents of the control memory are output as the selection signal 5. If the selection signal 5 is set at "0", the bi-level digital video signal 4 is selected. However, when the selection signal 5 is set at "1", the multi-level digital video signal 3 is selected, thereby obtaining the display contents of Fig.2. The control memory will be described as an image area memory later. The above operation also applies to the case wherein bi-level digital video data is displayed in the multi-level digital video data, as shown in Fig.4. In Fig. 4 a selection signal 5 instructs to select the type of logical operation for the multi- and bi-level digital video signals 3 and 4. A logical operation unit 6 performs a logical operation between the multi- and bi-level digital video signals 3 and 4. Other arrangements in Fig. 4 are the same as those in Fig. 1. Fig. 5 shows a technique for supplying the selection signal 5 shown in Fig. 4. Fig. 6 shows a relationship between the selection signals and the types of logical operations. Fig. 7 shows actual results of the logical operations. When the multi- and bi-level value reading signals 11 and 12 are output in response to the sync signals 10, the multi- and bi-level digital video signals 3 and 4 are respectively output from the multi- and bi-level value memories 1 and 2. When the selection signal 5 is set at "0", the AND operation between the multi- and bi-level digital video signals 3 and 4 is performed by the logical operation unit 6. When the selection signal 5 is set at "1", the OR operation per bit between the multi- and bi-level digital video signals is performed by the logical operation unit 6. Once area assignment of the control memory is determined, the contents of the control memory serve as the selection signals 5. Four logical operations in Fig. 6 can be performed in units of areas. An output from the logical operation unit 6 is converted by a D/A converter 7, and an analog signal from the D/A converter 7 is amplified by an amplifier 8. An output from the amplifier 8 is displayed on a CRT 9. Other logical operations in addition to those shown in Fig.6 may be used. If one of the multi- and bi-level video signals 3 and 4 has a priority over the other, switching between the multi- and bi-level values can be performed as described above. Negative/positive conversion can be easily performed by bit inversion. Fig. 8 is a perspective view of an image data processing system according to a second embodiment of the present invention. The image data processing system recognizes a multi-level value image area and a bi-level value image area in an original image and stores the multi- and bi-level value data. The image data processing system includes a controller 101, a keyboard 103, a CRT 104, an optical disk (to be referred to as an OD hereinafter) 105, an image scanner 106, and an image printer 107. A pointing device 102 such as a mouse is connected to the keyboard 103. The CRT 104, the keyboard 103, and the pointing device 102 constitute an operation unit. The controller 101 controls the OD 105, the image scanner 106, and the image printer 107 in accordance with a command from the operation unit and performs image processing. It should be noted that the CRT 104 preferably has a high resolution (1000 DPI or dots per inch (1 inch 2.54cm) in this embodiment). Fig. 9 is a block diagram of the image data processing system shown in Fig. 8 A portion surrounded by the alternate long and short dashed line in Fig. 9 defines the controller 101. A CPU (central processing unit) 110 executes control programs stored in a PMEM (program memory) 113 and controls the image data processing system. The PMEM 113 stores the control programs and various control data such as a control flag. The control programs are shown in Figs.14 to 17. A DISK-I/F (disk interface) 111 controls an HD (hard disk) 120 and an FD (floppy disk) 121 in accordance with an instruction from the CPU 110. The control programs to be stored in the PMEM 113 may be loaded from the HD 120 or the FD 121. An OD-I/F (optical disk interface) 112 controls the OD 105 in accordance with an instruction from the CPU 110. An SP-I/F (scanner/printer interface) 114 controls the IS (image scanner) 106 and the IP (image printer) 107 in accordance with an instruction from the CPU 110. The detailed arrangement of the SP-I/F 114 will be described in Fig. 11. A KEY-I/F (keyboard interface) 115 serves as an interface for signalling operating states of the keyboard (KEY) 103 and the PD (pointing device) 102 to the CPU 110. The CPU 110 detects an operating state of the PD 102 and controls the position of a cursor displayed on the CRT 104 to be described later. A VMEM (video memory) 116 stores image data displayed on the CRT 104. The VMEM 116 reads out image data in response to a sync signal for the CRT 104 and converts the image signal into a raster signal. The raster signal is supplied to and displayed as an image on the CRT 104. A LAN-I/F (local area network interface) serves as an interface for exchanging data with other devices through a LAN (local area network) 122. An ICU (image compression unit) 119 is a unit for compressing or expanding an image according to an MMR (modified modified READ) scheme used in a FAX (facsimile system). The ICU 119 is used to store an image in the OD 105. <BMU Function> A BMU (bit manipulation unit) 117 transfers image data of a rectangular area and performs image processing such as enlargement, reduction, or rotation. The BMU 117 also performs logical operations between the transfer source image data and the transfer destination image data. The logical operations are logical AND and OR operations between pixels. All the above image processing operations can be performed at bit boundaries. Fig.10A is a view for explaining image enlargement/transfer as an operation of the BMU 117 shown in Fig. 9. An image memory 170 corresponds to IMEMs 131 and 132 to be described later. Image data of a transfer source area 140 in Fig.10A, is enlarged through the BMU 117 and the enlarged image data is transferred to a transfer designation area 141. Fig. 10B shows another application of the BMU 117 in Fig. 9 An image data extraction function is effected such that a 400-DPI image is displayed on the CRT 104 (a resolution is 100 DPI or dots per inch in this embodiment). If image data having a resolution of 400 DPI is stored in the image memory 170, it is read out and extracted to reduce to 1/4. The image signal is thus converted into image data having a resolution of 100 DPI. The 100-DPI image data is transferred to the VMEM 116 for displaying it on the CRT 104. In this case, the BMU 117 extracts one pixel in every four pixels in both X and Y directions, thereby reducing the image data to 1/4. In this embodiment, the 400-DPI image read by the IS 106 is displayed and monitored on the CRT 104 because the operator can visually distinguish the bi-level value image area from the multi-level value image area in the read image. <SP-I/F Function> The function of the SP-I/F114 is the characteristic feature of this embodiment. Fig. 11 is a block diagram showing the detailed arrangement of the SP-I/F 114 in Fig. 9. Referring to Fig. 11 an SPC (scanner/ printer controller) 130 having a control function communicates with the IS 106 and the IP 107 in accordance with an instruction from the CPU 110 and controls circuits (to be described later) in the SP-I/F 114. A bi-level value IMEM (bi-level value image memory) 131 stores bi-level value image data and has a bit density of 400 DPI. A multi-level value IMEM (multi-level value image memory) 132 stores multi-level value image data and has a pixel density of 100 DPI. An image area MEM (image area memory) 133 stores image recognition data for recognizing the character (bi-level value)/photograph (halftone) image area and has a bit density of 400 DPI. An output operation (i.e., output to the printer (IP) 107) is taken into consideration. A bi-level digitalizing circuit 134 converts bi-level value image data stored in the bi-level value IMEM 131 into 8-bit multi-level value data. "0" is converted to "0", and "1" is converted to "255" according to MIN/MAX conversion. An interpolating circuit 135 linearly interpolates the multi-level value image data stored in the multi-level value IMEM 132 and having a resolution of 100 DPI and converts it into multi-level value image data having a resolution of 400 DPI. A combining circuit 137 selectively combines image data from the bi-level digitalizing circuit 134 and the interpolating circuit 135 in accordance with the image recognition data from the image area MEM 133. The combining circuit 137 also calculates a logical OR or AND of the image data from the bi-level digitalizing circuit 134 and the interpolating circuit 135 in accordance with an instruction from the SPC 130. Therefore, the image data output from the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133 are finally set to be 400 DPI. In the SP-I/F 114, the bi- and multi-level value images are neither compressed nor expanded at the time of output/reproduction. Since the image area MEM 133 has a bit density of 400 DPI, the bi-level value image stored in the bi-level value IMEM 131, the multi-level value image stored in the bi-level value IMEM 132, and the image recognition data stored in the image area MEM 133 and representing the type of image are given in one-to-one correspondence. Of the reproduced images output to the IP 107, the bi-level value image component corresponds to the bi-level value image data stored in the bi-level value IMEM 131 and multi-level value image component corresponds to the multi-level value image data stored in the multi-level value IMEM 132. <Input to SP-I/F> An input from the image scanner (IS) 106 will be described below. A binarizing circuit 136 compares 8-bit 400-DPI multi-level value image data from the IS 106 with a predetermined slice level (a fixed threshold value) and converts the multi-level value data into 400-DPI bi-level value image data. The resultant image data is stored in the bi-level value IMEM 131. The IS 106 causes a CCD or the like to read document data and converts the read data into a digital signal, thereby outputting multi-level digital image data representing halftone data according to 256 gray scale levels. An extract circuit 138 receives multi-level value image data having a resolution of 400 DPI from the IS 106 and calculates an average density of 16 (=4 x 4) pixels. The average density is defined as a density of one pixel, and the 400-DPI multi-level value image data is converted into 100-DPI image data. Therefore, the 8-bit data/dot is stored in the multi-level value IMEM 132. An image area separating circuit 139 analyzes the features of the multi-level value image from the IS 106 and separates the image into character and photographic areas. Image recognition data of logic "0" is assigned to the character area, and that of logic "1" is assigned to the photographic area. The data are stored in the image area MEM 133 correspondingly to each pixel (dot). In this case, it should be noted that data are parallelly or simultaneously input to the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133. The image recognition data is stored in the image area MEM 133 by the image area separating circuit 139. Alternatively, the image recognition data is stored as follows. The operator designates a halftone image area with the pointing device 102 while observing an image monitored on the CRT 104, and image recognition data associated with the designated area is written in the image area MEM 133 through a bus BUS under the control of the CPU 110. In the image area separating circuit 139, an 8-bit image signal (per pixel) read by the IS 106 is filtered by a differential filter or the like. If a sum of filtered outputs within the predetermined area exceeds a predetermined value, the central pixel within the predetermined area is detected as a pixel of the bi-level value image. In this case, the value for the image area MEM 133 which corresponds to the predetermined area is set to be "0". The bi-level value image data stored in the bi-level value IMEM 131 is stored as image data most suitable for bi-level value images such as character images. The image data stored in the multi-level value IMEM 132 is most suitable for halftone images. If an image such as a photograph is stored in the bi-level value IMEM 131, or a bi-level value image is stored in -the multi-level value IMEM 132, it is not suitable to output the stored contents without conversion. However, in this embodiment, the image areas can be switched in response to the image recognition data. The above description has been made for the overall arrangement of this embodiment. This embodiment will be described in more detail below. Two operation modes, two input modes for inputting images from the IS 106 while image recognition data is being input to the image area MEM 133, each output mode for outputting image to the IP 107 or CRT 104 in accordance with the recognition data stored in the image area MEM 133, and an application with an optical disk will be exemplified below. <Operation Mode : Fig.12 Referring to Fig.12, an image 150 including a character portion 152 and a photographic portion 151 is read by the IS 106 and the read image components are stored in the bi- and multi-level value IMEMs 131 and 132. The data stored in the bi-level value IMEM 131 is displayed on the CRT 104. The operator can designate a photographic area 153 while visually observing an image displayed on the CRT 104. Image recognition data of "1" corresponding to the area 153 is defined as data 154 in the image area MEM 133. The character portion is read out from the bi-level value IMEM 131, and the photographic portion is read out from the multi-level value IMEM 132, and the composite image is displayed on the CRT 104. As described above, in a state wherein corresponding data are stored in the bi- and multi-level value IMEMs 131 and 132, the bi-level value image data stored in the bi-level value IMEM 131 has good reproducibility of characters but poor reproducibility of a photograph. The multi-level value image data stored in the multi-level value IMEM 132 has good reproducibility of a photograph but poor reproducibility of characters. An excellent image including character and photographic portions is finally displayed on the CRT 104. <Operation Mode : Fig. 13 Necessary data read by the IS 106 and stored in the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133 are-parallelly or simultaneously read out in accordance with the image recognition data 154 stored in the image area MEM 133. An image having character and photographic portions having high quality is displayed on the CRT 104. In this case, the recognition data 154 stored in the image area MEM 133 is automatically generated by the image area separating circuit 139 without a manual operation. <Input Control Sequence : Fig. 14 Referring to Fig.14, an image 150 is read by the IS 106 and the read image components are stored in the bi- and multi-level value IMEMs 131 and 132. The data stored in the bi-level value IMEM 131 is displayed on the CRT 104, and the operator designates the photographic area 153 while visually observing the image displayed on the CRT 104. Image recognition data corresponding to the area 153 is stored in the image area MEM 133. In step S2, the CPU 110 instructs the IS 106 to read the image via the IS 106. The SPC 130 communicates with the IS 106 and instructs to cause the IS 106 to read the image. The contents in step S4 are performed in the SP-I/F 114, as described above. The IS 106 reads the image in accordance with the instruction and outputs 8-bit (per dot) 400-DPI multi-level value image data. This data is simultaneously supplied to the binarizing circuit 136 and the extract circuit 138. The image data binarized by the binarizing circuit 136 is stored in the bi-level value IMEM 131 as the bi-level value image data having a resolution of 400 DPI. The image data, the resolution of which is converted by the extract circuit 138, is stored in the multi-level value IMEM 132 as the multi-level value image data having a resolution of 100 DPI. The bi-level value image data from the bi-level IMEM 131 is resolution-converted by simple extraction by means of the BMU 117. As a result, 100-DPI bi-level value data for the CRT 104 is transferred to the VMEM 116 in step S6 and is displayed on the CRT 104 in step S8. The operator manipulates the PD 102 to designate the photographic portion 151 while visually observing the image on the CRT 104 and designates the photographic area or frame 153 (step 10). Image recognition data corresponding to the designated photographic area is stored in the image area MEM 133 (step 12). <Input Control Sequence Fig.15 Unlike in the control sequence of Fig. 14, Fig. 15 shows a control sequence for automatically obtaining image recognition data without a manual operation. The operation in step S20 is the same as that of step S2 in Fig. 14. When the original or image 150 including the photographic and character portions 151 and 152 is read in step S22, the read image components are simultaneously stored in the bi- and multi-level value IMEMs 131 and 132 through the binarizing circuit 136 and the extract circuit 138. The image recognition data recognized by the image area separating circuit 138 is also stored in the image area MEM 133. The image recognition data 154 corresponding to the photographic portion 151 is set at logic "1". The bi-level value image can be compressed without sacrificing its resolution by its nature. Even if the resolution is degraded, no problem occurs in the multi-level value image. Therefore, the number of bits of the images can be reduced by sacrificing the resolution. <Output to CRT 104 : Fig.16 A sequence for outputting data to the CRT 104 will be described with reference to Fig. 16. Predetermined data are stored in the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133. In step S30, the contents of the image area MEM 133 are read out by one pixel. The CPU 110 determines in step S32 whether the contents represent "0" or "1". If "0" is determined, the contents represent the bi-level value image (i.e., a character image). In step S34, the CPU 110 causes the BMU 117 to convert the 400-DPI bi-level value imaqe data in the bi-level value IMEM 131 into multi-level data (Fig 10 B). The 100-DPI data is transferred to the VMEM 116. However, if the image recognition data is set at "1", the multi-level value image data in the multi-level value IMEM 132 is transferred to the VMEM 116. In this case, since the VMEM 116 comprises a multi-level value memory having a resolution of 100 DPI, the multi-level value image data has a resolution of 100 DPI accordingly. Therefore, data can be transferred without resolution conversion. In this manner, if data of all pixels are transferred to the VMEM 116 (step S38), the image is displayed on the CRT 104 in step S40. <Output to Printer (IP) 107 : Fig. 17 A sequence for outputting data to the IP 107 will be described with reference to a flow chart in Fig. 17. Assume that predetermined data are stored in the bi-level value IMEM 131, the multi-level value IMEM 132, and the image area MEM 133. When the CPU 110 instructs the IP 107 to output an image via the SPC 130 in step S50, the SPC 130 communicates with the IP 107 to start the IP 107 in step S52. The CPU 110 instructs circuits in the SP-I/F 114 to start outputting an image signal in synchronism with the IP 107 and reads out the contents of the image area MEM 133 pixel by pixel. The bi-level value image data having a resolution of 400 DPI read out from the bi-level value IMEM 131 is converted into 8-bit multi-level value image data by the bi-level digitalizing circuit 134. The converted data is supplied to the combining circuit 137. The 8-bit multi-level value image data having a resolution of 100 DPI and read out from the multi-level value IMEM 132 is resolution-converted into the 400-DPI multi-level value data by the interpolating circuit 135. The image recognition data for designating the character or photographic portion is read out from the image area MEM 133 and is input to the combining circuit 137. In steps S56 to S62, the combining circuit 137 selects one of the digitalized and interpolated outputs from the digitalizing circuit 134 and the interpolating circuit 135 on the basis of the image area designation data read out from the image area MEM 133. An output image signal is then output to the IP 107. This image signal is printed on paper at the IP 107 in synchronism with the operation of the IP 107. In the IP 107, the 8-bit (per pixel) multi-level value data is converted into analog data and the width of the ON pulse of the laser can be changed, thereby printing out a halftone electrophotographic picture expressed in 256 gray scale levels. <Application with/Recording of Optical Disk : Fig. 18 Fig. 18 shows an application in which an image including both character and photographic areas is recorded in the OD (or optical disk) 105. This operation is performed in association with the DISK-I/F 111, the ICU 119, the SP-I/F 114, and the bus BUS. Image data associated with the bi-level value image area, image data associated with the multi-level value area, image recognition data, and header data for discriminating the image data from image recognition data are simultaneously stored in the OD 105. In this case, only a character area 156 excluding a photographic area 155 from the data in the bi-level value IMEM 131 is compressed by the ICU 119, and predetermined header data H1 is added to the compressed data, and the composite data is stored in the OD 105. Predetermined header data H2 is added to only a photographic area 157 excluding a character area 158 in the multi-level value IMEM, and the composite data is stored in the OD 105. Since the resolution of the multi-level value image data is compressed into 1/4, the quantity thereof is compressed to 1/16. A further data compression operation is not performed. The image recognition data stored in the image area MEM 134 is compressed by the ICU 119 and is defined by predetermined header data H3. The above data are controlled as a single image file in association with the header data. Compression of data excluding a specific area can be performed by the logical AND function of the BMU 117 together with the ICU 119. Control data (not shown) including the header data is stored in the HD 120. <Application with/Reading of Optical Disk : Figs. 19-1 and 19-2 Figs. 19-1 and 19-2 show a sequence for outputting image data from the OD 105. A desired optical disk file is detected by the control data stored in the HD 120. When header data H1 is read, bi-level value image data is read out from the OD 105 and is expanded by the ICU 119. The expanded data is stored in the bi-level value IMEM 131. When the header data H3 is read, the image recognition data is read out from the OD 105 and is expanded by the ICU 119. The expanded data is stored in the image area MEM 133. When the expanded data are to be printed out, the corresponding data are read out from the memories in synchronism with the operation of the IP 107 and are combined by the combining circuit 136. The area of the image area MEM 133 which is assigned with "1" represents the photographic area 154. As for the photographic area, data is read out from the multi-level value IMEM 132. As for the remaining area, data is read out from the bi-level value IMEM 131. The resultant combined image is output to the IP 107. Therefore, an image including character and photographic areas having high quality can be obtained. In the above embodiment, the image scanner is used as a multi-level value image data input means. However, another input device such as a TV camera or a flying spot scanner may be used. A laser beam printer, an ink-jet printer, a thermal printer or the like may be used as a multi-level value printer. In the above embodiment, the multi-level value image data is resolution-converted, and the 100-DPI converted data is stored in the memory. However, the resolution of the converted image data may be, for example, 200 DPI. Fig. 20 shows an image processing system using an interface circuit according to a third embodiment of the present invention. A CPU 201 serves as a host computer processor and includes a main memory adapted to store control programs and used as a work area. A frame buffer 202 stores image data of at least one frame. A CRT 203 displays image data from the frame buffer 202 and contents of inputs from a keyboard 204 and a pointing device 205. The keyboard 204 is used to input various commands and control data. The pointing device (PD) 205 is used to designate a specific area of an image displayed on the CRT 203. A disc drive 206 stores image data input from an image scanner 207 or the like. A system bus 207 connects the CPU 201 to various buffers. The CPU 201 can access each buffer via the system bus 207. These components are included in the host computer side. An image scanner 208 photoelectrically reads image information and inputs it as multi-level value image data. A printer 209 prints a multi-level value image on paper. An interface circuit 210 is controlled by a controller 211. The multi-level value data from the image scanner 208 is simultaneously input to a multi-level/bi-level converter 213 and a resolution conversion circuit 214 via a video bus 212. In the multi-level/bi-level converter 213, the input multi-level value data is converted into bi-level value data in accordance with threshold value processing. The resultant bi-level value data is stored in a bi-level value buffer 215. The resolution conversion circuit 214 extracts the input multi-level value data and converts it into data having a lower resolution. The converted data is stored in a multi-level value buffer 216. When the image data is output to the printer 209, the bi-level value data in the bi-level value buffer 215 is min/max-converted by the multi-level/bi-level converter 213 into multi-level value data. The multi-level value data in the multi-level value buffer 216 is subjected to interpolation by the resolution conversion circuit 214. Low-resolution data is expanded so that its dot density coincides with that of the multi-level value data from the multi-level/bi-level converter 213. An address counter 217 generates read/write address data for the multi-level value buffer 216 and an area control buffer 218. A switching circuit 219 switches between the image data from the multi-level/bi-level converter 213 and the resolution conversion circuit 214 in accordance with area data 220 from the area control buffer 218 when the image data are output. When the bi-level or multi-level value image area is designated with the PD 205 in the image displayed on the CRT 203, the area control buffer 218 stores the data in the area control buffer 218 such that "1" is assigned to the bi-level value area and "0" is assigned to the multi-level value area. The area control buffer 218 outputs area data 220 of logic "0" or "1" in synchronism with read access of the bi-level or multi-level value buffer 215 or 216. <Description of Image Editing Application : Figs. 21A to 22 (e). Fig. 21A shows image data input from the image scanner 208. This image includes a photographic area 250 and a character area 251. Fig 21B shows print-out image data in which the photographic area 250 is shifted. Image input operations, the states of buffers at the time of image output, and operations during image shifting will be described with reference to Figs. 22(a) to 22(e). When multi-level value image data is input from the image scanner 208, the bi-level value data output from the multi-level/bi-level value converter 213 is stored in the bi-level value converter 215. At the same time, the multi-level value image data, the resolution of which is lowered by the resolution conversion circuit 214, is stored in the multi-level value buffer 216. This state is shown in Fig. 22a The image in Fig. 22(a) includes a photographic area 230 and a character area 231. Referring to Fig 22(b), the CPU 201 fetches the multi-level value data from the multi-level value buffer 216 via the system bus 207 and causes the frame buffer 202 to store the fetched data. This data is displayed on the CRT 203. The operator designates the photographic area 230 with the PD 205 while visually observing the image on the CRT 203. The bits of an area 232 which corresponds to the photographic area 230 are inverted, thereby storing the area data (Fig. 22(c)). When the operator designates shifting of the photographic area 230 with the PD 205, the photographic area 230 is shifted in the frame buffer 202, as shown in Fig. 22(d). The photographic area on the CRT 203 is shifted accordingly. When the above editing operation is completed, the photographic area 230 is shifted in the bi-level value buffer 215, the multi-level value buffer 216, and the area control buffer 218 in accordance with the editing end instruction input by the operator (Fig. 22(e)). The image data and area data 220 are simultaneously read out from the buffers 215 to 218 in accordance with a printing instruction from the keyboard 204. The bi-level value data from the bi-level value buffer 215 is converted by the multi-level/bi-level converter 213 into the multi-level image data. The low-resolution multi-level value data in the multi-level value buffer 216 is expanded by the resolution conversion circuit 214 such that the resolution thereof matches with the resolution (dot density) of the bi-level value data. These two data are switched by the switching circuit 219 in accordance with the area data 220 read out from the area control buffer 218. As for the photographic area 232, the output from the resolution conversion circuit 214 is selected. As for the remaining area, the output from the multi-level/bi-level converter 213 is selected. The selected outputs are supplied to the printer 209. As a result, the character area is expressed by a high-resolution bi-level value image, and the photographic area is expressed by the low-resolution multi-level value data with 256 gray scale levels. If the resultant data is to be stored in the disc drive 6, the bi-level/multi-level image data extracted according to the area data 20 are properly compressed, and the compressed data are stored in the disc drive 6, thereby greatly compressing the image data. Image editing is exemplified in the above embodiment. However, a variety of applications may be utilized within the scope of the invention. In the above embodiment, bi-level and multi-level value images are processed. However, the same techniques as described above can be applied to area control of predetermined threshold value processing and dither processing for only a bi-level value image. According to the above embodiment, the high-resolution bi-level image and the low-resolution multi-level image which are prepared on the basis of single high-resolution multi-level data can be input to or output from the independent bi-level and multi-level value buffers. At the same time, each buffer can be randomly accessed via the system bus on the host computer side. The host computer can arbitrarily use each buffer to process high-quality images by using a small number of data. Fig. 23 shows a system in which an image area discrimination circuit 221 is added to the arrangement of Fig. 20 The image area discrimination circuit 221 uses the density values of the pixels adjacent to the image data from the image scanner 208 and discriminates an edge portion from a nonedge portion in the image. The edge portion is discriminated as the bi-level value area, and the nonedge portion is discriminated as the multi-level value area. The discrimination result is output as area data 220. An area buffer 218 stores the area data 220 from the image area discrimination circuit 221 such that the bits of the photographic area 232 are inverted. The timing of the area buffer 218 shown in Fig. 22(a) is the same as that in Fig. 22(c). A combining circuit for combining outputs from the multi-level/bi-level converter 213 and the resolution conversion circuit 214 and outputting a composite signal may be arranged in place of the switching circuit 219 shown in Figs. 20 and 23. In this case, after the step in Fig. 22(e) during image editing, the operator designates the photographic area in the image displayed on the CRT 203 and clears the area 230 in the bi-level value buffer and the area 231 in the multi-level value buffer 216 in Fig. 22(e) in order to prevent double overlapping when two images are combined.

Claims: An image processing method comprising the steps of: inputting image binary information to be stored as single-bit data; storing said single-bit data; inputting image multi-value information to be stored as multi-bit data; storing said multi-bit data; and processing said stored image information by selecting or, alternatively, combining by logical operation, the binary information represented by said single-bit data, and the multi-value information represented by said multi-bit data, to produce image output data; characterised by the steps of: inputting control data in one-to-one correspondence with said single-bit data, which control data is coded according to different selections or, alternatively, different combinations, of the binary information and the multi-value information, corresponding to different respective areas of an image represented by said image output data; storing control data; and performing the different selections or, alternatively, the different combinations, denoted by the stored control data. Method according to claim 1 in which the image processing step comprises the selection of either the binary or the multi-valued input image information according to an image area defined by positional information. Method according to claim 1 in which the image processing step comprises, for specified areas (Fig.8), combining the binary and the multi-valued input image information according to a logical rule (Fig.9) defined for each such area. Method according to any preceding claim including the further steps of supplying the image output information to a printer and printing out the image. An image processing apparatus comprising: first input means (106,136) for inputting image binary information to be stored as single-bit data; first memory means (131), co-operative with said first input means (106,136), to store said single-bit data; second input means (106,138) for inputting image multi-value information to be stored as multi-bit data; second memory means (132), co-operative with said second input means (106,138), to store said multi-bit data; and processing means (134,135,137), co-operative with said first and second memory means (131,132), to select or, alternatively, to combine by logical operation, the binary information represented by said single-bit data, and the multi-value information represented by said multi-bit data, to produce image output data; characterised by: third input means (106,139) for inputting control data in one-to-one correspondence with said single-bit data, which control data is coded according to different selections or, alternatively, different combinations, of the binary information and the multi-value information, corresponding to different respective areas of an image represented by said image output data; and third memory means (133), co-operative with said third input means (106,139), to store said control data; said processing means (134,135,137) being responsive to control data stored in said third memory means (133), to perform the different selections or, alternatively, the different combinations, denoted by the control data. Apparatus according to claim 5, wherein the binary information has a first resolution, the multi-value information has a second resolution, and the first resolution is higher than the second resolution. Apparatus according to claim 6, wherein said processing means (134,135,137) includes first conversion means (134) for converting the binary information stored in the first memory means (131) into multi-value information and second conversion means (135) for converting a resolution of the multi-value information stored in said second memory means (132) into a resolution equal to that of the binary information. Apparatus according to any of claims 5 to 7, further comprising output means (107) for outputting the combined information from said output control means (134,135,137). Apparatus according to claim 8, wherein said output means (107) is a multi-value printer. Apparatus according to any of claims 5 to 9 wherein all said input means (106,136,139) includes a multi-value image scanner.

Inventors: CHYO KENJIRO, ISHIZAWA YASUHISA, MIURA SHIGEKI, NONOSHITA HIROSHI, SAITO SEIJI, SHIGEHARA YASUHISA, CHYO, KENJIRO, ISHIZAWA, YASUHISA, MIURA, SHIGEKI, NONOSHITA, HIROSHI, SAITO, SEIJI, SHIGEHARA, YASUHISA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1987
Main classification: H04N1
IPC codes: G06T11, H04N1