FULL WAVE RECTIFIER CIRCUIT

Abstract: A full wave rectifier is embodied in an integrated circuit and includes first and second field effect transistors (7, 11) of a common conductivity type. In a p-channel embodiment, the two FET source regions (5, 10) are formed by a common substrate region (18) coupled to ground and to one side of a DC load (13), the other side of which is coupled to a substrate contact region (19/21). The AC input is coupled between the commonly connected drain and gate electrodes of the field effect transistors (7, 11). The rectifier is suitable for use in a power source for CMOS, NMOS and PMOS circuits and is particularly applicable to power supplies implemented by inductive or capacitive coupling in smart cards or electronic keys.

Description: FULL WAVE RECTIFIER CIRCUIT Technical Field This invention relates to full wave rectifier circuits. The invention is particularly useful for circuit applications where all functions are to be integrated on a common chip fabricated with CMOS field effect transistors operated by DC voltage yet powered from an AC source. A typical application would be one in which the power is transmitted to the chip from an electrical source by electromagnetic or capacitive coupling. Exemplary applications include pacemakers and "smart" credit cards or electronic keys. Background Art In view of the low power requirements of many new integrated circuit designs, it is now feasible to electromagnetically or capacitively couple, through an intervening dielectric, sufficient energy to power an integrated circuit chip for extended operation where the coupled energy is stored by capacitive or rechargeable electrochemical means. One specific example might be a pacemaker which is recharged daily by electromagnetic coupling, while another might be a "smart" credit card or electronic key which is powered by insertion into a mechanism which electromagnet¬ ically couples both power and data to and from the chip, thereby substantially negating the problems associated with electrical contacts. U.S. Statutory Invention Registration No. H64 discloses a full wave rectifier implemented in CMOS integrated circuit chip technology. The known rectifier includes two transistors and two diodes arranged in a bridge circuit. The two transistors may be placed in separate wells in the chip substrate and the two diodes include respective surface-adjacent source/drain regions of opposite conductivity type to the adjacent substrate. Thus, the known rectifier has the disadvantage of not requiring separate wells and using numerous, physically dispersed diffusions and contacts to achieve the necessary p-n junction rectification. Disclosure of the Invention It is an object of the present invention to provide a full wave rectifier circuit, adapted for implementation in an integrated circuit structure, which is of minimal complexity. Therefore, according to the present invention, there is provided a full wave rectifier, including first and second field effect transistors of first conductivity type characterized in that said transistors are resident in a common substrate region of second conductivity type and have respective first and second source/drain regions and gate electrodes; by a first node, defining a common connection of a DC load terminal, said first source/drain region of said first field effect transistor and said first source/ drain region of said second field effect transistor; by a second node, defining a common connection of said second source/drain region and said gate electrode of said first field effect transistor and one connection to a source of AC voltage; by a third node, defining a common connection of said second source/drain region and said gate electrode of said second field effect transistor and a second connection to said source of AC voltage and by a fourth node, defining a common connection of the other DC load terminal and said second conductivity type substrate region of each resident field effect transistor. In addition to being of minimal complexity, the full wave rectifier, according to the invention, has the advantages of not unduly dissipating power under normal operating conditions, and of being readily connectable to other integrated circuit elements to provide filtering and regulation of the rectified DC voltage. Furthermore, the rectifier circuit can be configured to avoid the creation of parasitic bipolar transistors and the resulting latch- up problems. Brief Description of the Drawings Embodiments of the invention will now be described by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a schematic of a p-channel embodiment of the invention. Fig. 2 is a diagram schematically depicting a cross section of a representative p-channel embodiment interconnected to provide full wave rectification. Fig. 3 is a schematic of an n-channel embodiment of the invention. Best Mode for Carrying Out the Invention One preferred embodiment of the present invention is depicted schematically in Fig. 1 of the drawings. A cross section of a p-well CMOS integrated circuit implementation of the schematic is depicted in Fig. 2 of the drawings, retaining for purposes of clarity schematic representations of the electrical connections, AC input, and equivalent DC load. Referring to Fig. 1, AC power is furnished by AC input voltage supply 1 at nodes 2 and 3, which nodes are respectively connected to gate electrode 4 and drain electrode 6 of p-channel field effect transistor 7, and connected to gate electrode 8 and drain electrode 9 of p-channel field effect transistor 11. Both field effect transistors are enhancement type devices. The source electrodes, 5 and 10 (doped region 18 in Fig. 2), of respective transistors 7 and 11 are commonly connected to node 12, which node is connected to ground potential and also serves as one connection to equivalent resistive load 13. The other side of the equivalent resistive load 13 is connected to the node 14, the substrate (doped contact regions 19 and 21 in Fig. 2) . The presence of an AC voltage between nodes 2 and 3 produces a plus DC voltage having a full wave rectified waveform on node 14 with respect to ground node 12. The shape of DC voltage on node 14 is influenced by the shape of the AC input, the threshold voltages of transistor 7 and 11, including any back bias effects on these transistors, and a diode voltage drop. Distributed capacitance filtering effects are also present. For example, the DC voltage on node 14 n range from a slightly clipped full wave rectified sinusoidal pattern to a near DC level for a square wave AC input. Fig. 2 illustrates by way of schematic cross section a preferred embodiment of the invention in the context of a p-well CMOS integrated circuit. This embodiment should not be construed as a limitation, in that the invention is fully subject to practice in devices fabricated with an n-well CMOS processes as well as with individual NMOS or PMOS fabrication processes. Likewise, the configuration is amenable to epitaxial structures in lieu of wells. However, in all cases care must be exercised to avoid structures which are susceptible to latch-up. The embodiment depicted in Fig. 2 is formed in an n~ substrate 16, and includes an optional well 17 of p~ impurity. As shown, the structure is comprised of p-channel field effect transistors 7 and 11, individually responsive to respective gate electrodes 4 and 8 situated between p + source/drain regions 6, 9 and 18, the latter being shared by both transistors. The shared source/drain region 18 is Λ connected to ground node 12 and . one side of equivalent load 13. Source/drain region 6 of transistor 7 is connected in common with gate electrode 4 to node 2, which node itself is connected to one side of AC input 1. Similarly, source/drain region 9 is connected in common with gate electrode 8 of transistor 11 to node 3, which node is connected to the other side of AC input 1. The plus DC voltage appears on node 14, which is connected to the other side of equivalent load 13 and to n + diffusions 19 and 21 in substrate 16. The use of multiple n + diffusions, in contrast to the minimum requirement of a single substrate surface contact, as well as the creation of n + channel stops 22, 23, 24 and 26 under a field oxide regions 27, 28, 29 and 31, implements known carrier trapping techniques in view of the charge injected into substrate 16. Charge is injected into substrate 16 when the p-n junctions 6 to 16 or 9 to 16 are forward biased. Note further that layout density and charge injection benefits may accrue by deleting field oxide regions 28 and 29, so as to place p + diffusions 6 and 9 into immediate contact with respective n + contact diffusions 19 and 21, forming the requisite diode therebetween. To understand the operation of the circuit as structurally depicted in Fig. 2 consider a situation in which AC input 1 is a sinusodial voltage source, having peak values of +7 and -7 volts, and field effect transistors 7 and 11 have nominal threshold voltages of -0.9 volts. During that instant of time when AC input 1 is generating a voltage of +7 volts at node 3 with respect to node 2, the junction between p + region 9 and composite substrate 16/n + contact region 21 is positively biased, providing the +7 volts less the p-n junction diode drop to node 14 of equivalent load 13. The other side of equivalent load 13 is connected to AC input 1 through field effect transistor 7, which is conductively biased whenever the instantaneous AC input voltage is greater than the combination of the p-n drop and the threshold voltage of transistor 7, approximately 1.6 volts. The end effect is that load 13 experiences a rectified voltage having a 5.4 volt peak. When the AC input voltage reverses, conventional current conduction is from node 2, through p + region 6, to n + region 19 (and 21), through load 13, to node 12, and through forward biased field effect transistor 11 to node 3. Unfiltered full wave rectified DC voltage is in most cases unacceptable for operating an integrated circuit. However, when the power demands are minimal, such as is common for many CMOS integrated circuits, on-chip capacitive filtering is feasible. With limited power demands, sufficient filtering can often be obtained from the parasitic capacitive effects of n-channel device diffusions in p-wells. If such distributed capacitance proves to be inadequate for effective filtering, it is also feasible to add capacitive structures. For instance, in the context of Fig. 2, there is shown the possibility of forming a junction capacitor between n + region 32 and p-well 17, which can then be connected by line 33 to filter the DC voltage on node 14. As is no doubt understood, though equivalent load 13 represents functional electronic devices on the same substrate 16, it may, if the occasion arises, include elements external to the integrated circuit chip represented by substrate 16. Consideration of the circuit and structure depicted in Fig. 2 will disclose the presence of a number of unique features. First, although the structure is preferably used in conjunction with a CMOS integrated circuit, the underlying concepts are similarly applicable to NMOS and PMOS processed devices. Secondly, the circuit depicted in Fig. 2 s\ does not have local latch-up susceptibility, in that a parasitic bipolar transistor structure is not created. The absence of latch-up susceptibility is valid for p- channel devices formed in an n-type substrate, or in the complementary n-well fabrication process, when n- channel transistors are formed in a p-type substrate. Any attempt to place p-channel transistors in an n- well of a p-type substrate, or an attempt to place n- channel transistors in a p-well of an n-type substrate will create a parasitic vertical bipolar transistor structure susceptible to latch-up. The complement to the circuit schematically depicted in Fig. 1, and shown by way of cross section in Fig. 2, is schematically depicted in Fig. 3. As depicted, AC input 1 at nodes 2 and 3 drives n-channel transistors 34 and 36 to provide a full wave rectified DC voltage across load 13, the load voltage polarity now being opposite that previously generated with respect to the substrate. Again, field effect transistors 34 and 36 are enhancement mode types, here preferably configured to have a threshold voltage of approximately +0.7 volts. The cross sectional schematic depicted in Fig. 2 would be equally applicable to the arrangement in Fig. 3, with an interchange of the impurity types for the various regions and a reversal of the ground and DC voltage connections to equivalent load 13. The establishment of the threshold voltages for p-channel transistors such as 7 and 11 in Fig. 2 must take into account the back bias effects associated with the injection of charge into substrate 16 from diffusions 6 and 9. Note that in the case of the n-channel transistor design schematically depicted in Fig. 3 the substrate is at ground and back bias effects are absent.

Claims: CLAIMS : 1. A full wave rectifier, including first and second field effect transistors (7, 11) of first conductivity type, characterized in that said transistors (7, 11) are resident in a common substrate region (16) of second conductivity type and have respective first and second source/drain regions (5, 10, 6, 9) and gate electrodes (4, 8); by a first node (12), defining a common connection of a DC load terminal, said first source/drain region (5) of said first field effect transistor (7) and said first source/drain region (10) of said second field effect transistor (11); by a second node (2), defining a common connection of said second source/drain region (6) and said gate electrode (4) of said first field effect transistor (7) and one connection to a source of AC voltage (1); by a third node (3), defining a common connection of said second source/drain region (9) and said gate electrode (8) of said second field effect transistor (11) and a second connection to said source of AC voltage (1); and by a fourth node (14), defining a common connection of the other DC load terminal and said second conductivity type substrate region (16) of each resident field effect transistor (7, 11). 2. A full wave rectifier according to claim 1, characterized in that said first source/drain region (5) of said first field effect transistor (7) and said first source/drain region (10) of said second field effect transistor (11) are defined by a single region (18) of first conductivity type. 3. A full wave rectifier according to claim 2, characterized in that said first and second field effect transistors (7, 11) are enhancement type devices. 4. A full wave rectifier according to claim 3, characterized in that said second conductivity type substrate region of each resident field effect transistors (7, 11) is an ohmically continuous single region (16) of second conductivity type. 5. A full wave rectifier according to claim 4, characterized in that said ohmically continuous single region (16) includes multiple heavily doped contact regions (19, 21) for carrier trapping. 6. A full wave rectifier according to claim 2, characterized by a separate well (17) of first conductivity type which includes a region (32) of second conductivity type connected to the load (13) and providing capacitive filtering therein. 7. A full wave rectifier according to claim 1, characterized in that said first and conductivity types are p-type and n-type respectively, and in that said first node (12) is connected to ground potential. 8. A full wave rectifier circuit according to claim 1, characterized in that said first and second conductivity types are n-type and p-type respectively, and in that said fourth node (14) is connected to ground potential.

Inventors: ELLSWORTH DANIEL LLOYD, MOLL MAURICE MICHAEL, ELLSWORTH, DANIEL, LLOYD, MOLL, MAURICE, MICHAEL
Applicants: NCR CO, NCR CORPORATION
Application year: 1987
Main classification: H02M7
IPC codes: H01L27, H01L29, H02M7