BUFFER CIRCUIT

Abstract: A buffer circuit comprises first to third CMOS inverters (23, 26, and 29) whose input terminals are mutually connected, first and second npn transistors (30 and 3l) whose bases are commonly connected to an output terminal of the first CMOS inverter (23) and whose emit­ ters are respectively connected to output terminals of the second and third CMOS inverters (26 and 29), fourth and fifth CMOS inverters (35 and 39) for inverting the output signals of the first and third CMOS inverters (23 and 29), a third npn transistor (43) whose base and emitter are respectively connected to output terminals of the fourth and fifth CMOS inverters (35 and 39), fourth and fifth npn transistors (49 and 53) whose con­ duction states are controlled by the output signals of the first and fourth CMOS inverters (23 and 35), first and second n-channel MOS transistors (4l and 47) which are serially connected to the fourth and fifth npn tran­ sistors (49 and 53), respectively, and whose gates are respectively connected to the third and fifth CMOS inverters (29 and 39), and third and fourth n-channel MOS transistors (45A and 36A) which are respectively connected between the gates of the first and second n-­ channel MOS transistors (4l and 47) and a reference voltage terminal and whose gates are respectively con­ nected to the fourth and first CMOS inverters (35 and 23).

Description: The present invention relates to a buffer circuit for generating signals of the same and opposite polarities with respect to that of an input signal. Hitherto, in the case of obtaining two output signals having different polarities, for example, as shown in Fig. l, a buffer circuit using two CMOS inverter circuits is used. Namely, an input signal D in is supplied to and inverted by a first inverter circuit ll from which, an output is generated as a first signal, and the output of inverter circuit ll is inverted by a second inverter circuit l2, thereby causing an output D out of the same polarity as input signal D in to be generated as a second signal. Suppose that inverter circuits ll and l2 are constituted by CMOS circuits and the transfer delay times by inverter circuits ll and l2 respectively assume t pdA and t pdB . Then, delay times and ΔD out of output signals and D out for input signal D in will become equal to t pdA and (t pdA + t pdB ), respectively. Therefore, there is a drawback that the time difference equal to transfer delay time t pdB due to the presence of inverter circuit l2 occurs between output signals and D out . As mentioned above, the time difference corresponding to the delay time of the CMOS inverter circuit of the post stage occurs between the outputs of both polarities in the conventional CMOS buffer circuits to obtain the outputs of both polarities. Prior art document PATENT ABSTPACTS OF JAPAN, vol. 9 no. 305 (E363) 2028 , 3rd December 1985 (JP-A-60 142 618) discloses an input buffer circuit wherein an address input signal is supplied to a level converting circuit. This level converting circuit is composed of an inverter circuit for level conversion which converts, for example, the input signal of a TTL level into a signal of a CMOS level and an inverter circuit which adjusts leading edge and trailing edge characteristics. An uninverted input buffer circuit and an inverted input buffer generate an uninverted output signal and an inverted output signal, respectively. The uninverted and the inverted input buffer circuits use an MOS bipolar composite circuitry to eliminate differences in delay time between inverted and uninverted output signals, to improve the ability to drive a load, and to perform high-speed switching. It is an object of the present invention to provide a buffer circuit which can reduce the skew of the delay time between the output signals of both polarities. This object is accomplished by a buffer circuit comprising: a first inverter circuit for receiving an input signal and generating the inverted signal of the input signal from first, second, and third output terminals; a second inverter circuit for receiving the signals from the first and third output terminals of the first inverter circuit and generating the inverted signals of these signals from first and second output terminals; first and second bipolar transistors whose bases are commonly connected to the first output terminal of the first inverter circuit and which are connected at one end to a first power source terminal and respectively connected at the other ends to the second and third output terminals of the first inverter circuit; a third bipolar transistor whose base is connected to the first output terminal of the second inverter circuit and which is connected at one end to the first power source terminal and connected at the other end to the second output terminal of the second inverter circuit; first and second bipolar transistor circuits which are respectively connected between the first power source terminal and first and second output nodes and are controlled to be set in the opposite conduction states in response to the output signals from the first output terminal of the second inverter circuit and from the first output terminal of the first inverter circuit, respectively; first and second MOS transistors which are respectively connected between the first and second output nodes and a second power source terminal and are controlled to be set into the opposite conduction states in response to the output signals from the third output terminal of the first inverter circuit and from the second output terminal of the second inverter circuit, respectively; and third and fourth MOS transistors which are respectively connected between the gates of the first and second MOS transistors and the second power source terminal and are respectively controlled to be set into the opposite conduction states in response to the output signals from the first output terminal of the second inverter circuit and from the second output terminal of the first inverter circuit, wherein output signals having the inversion relation are generated from the first and second output nodes in response to the input signal. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. l shows a conventional buffer circuit having two inverters; Fig. 2 is a schematic circuit diagram of a buffer circuit according to an embodiment of the present invention; Figs. 3A to 3E are signal waveform diagrams for explaining the operation of a buffer circuit shown in Fig. 2; Fig. 4 is a circuit diagram showing a practical buffer circuit of the circuit of Fig. 2; and Figs. 5A to 5D are signal waveform diagrams for explaining the operation of the buffer circuit shown in Fig. 4. An embodiment of the present invention will be described hereinbelow with reference to the drawings. Input signal D in is supplied to the input terminal of inverter circuit l3 shown in Fig. 2. The output of inverter circuit l3 is supplied to the input terminal of inverter circuit l4. The output of inverter circuit l4 is supplied to the base of NPN-type bipolar transistor l5 whose collector is connected to power source VC. N-channel type MOS transistor l6 is connected between the emitter of bipolar transistor l5 and the ground. The output of inverter circuit l3 is supplied to the gate of MOS transistor l6. Current control circuit CC₁ and overcurrent inhibit circuit IC₁, which are respectively controlled by the outputs of inverter circuits l3 and l4, are connected between the gate of MOS transistor l6 and the ground. The output of inverter circuit l3 is also supplied to the base of NPN-type bipolar transistor l8 whose collector is connected to power supply VC. N-channel type MOS transistor l9 is connected between the emitter of bipolar transistor l8 and the ground. The output of inverter circuit l4 is supplied to the gate of MOS transistor l9. Current control circuit CC₂ and overcurrent inhibit circuit IC₂ are connected between the gate of MOS transistor l9 and the ground and are controlled by the outputs of inverter circuits l4 and l3, respectively. Output signal D out is obtained from the node of bipolar transistor l5 and MOS transistor l6 through a load circuit having a capacitor C₁ and a resistor R₁. Output signal is obtained from the node of bipolar transistor l8 and MOS transistor l9 through a load circuit having a capacitor C₂ and a resistor R₂. In the foregoing constitution, the schematic operation will now be described. When input signal D in which is supplied to inverter circuit l3 changes from an "L" level to an "H" level as shown in Fig. 3A, the output changes to an "L" level after the delay time caused by inverter circuit l3 as shown in Fig. 38. Thus, bipolar transistor l8 and MOS transistor l6 change from the ON state to the OFF state. In this case, however, since it takes a time until MOS transistor l6 is completely turned off, output signal D out is substantially held at an "L" level at this time, as shown in Fig. 3D. Next, the output of inverter circuit l4 is set to an "H" level after a predetermined delay time as shown in Fig. 3C, so that bipolar transistor l5 and MOS transistor l9 change from the OFF state to ON state. At this time, overcurrent inhibit circuit IC₁ is made operative by the "H" level signal which is output from inverter circuit l4, thereby connecting the gate of MOS transistor l6 to the ground. Therefore, output signals D out and are set to "H" and "L" levels in response to the output signal from inverter circuit l4, as shown in Figs. 3D and 3E, respectively. Next, when input signal D in changes from an "H" level to an "L" level, as shown in Fig. 3A, the output of inverter circuit l3 is inverted and is set to an "H" level, as shown in Fig. 3B. Thus, bipolar transistor l8 is turned on. In this case, the gate of MOS transistor l9 is grounded by overcurrent inhibit circuit IC₂ and MOS transistor l9 is gradually turned towards the OFF state. In this case, since the gate of MOS transistor l6 is grounded by overcurrent inhibit circuit IC₁, MOS transistor l6 is held in the OFF state. Namely, output signal D out is held at an "H" level as shown in Fig. 3D. Next, when the output of inverter circuit l4 is inverted from an "H" level to an "L" level, as shown in Fig. 3C, MOS transistor l9 is turned off and bipolar transistor l5 is turned off and overcurrent inhibit circuit IC₁ is made inoperative. MOS transistor l6 is turned on by the "H" level output of inverter circuit l3. Therefore, output signals D out and are set to "L" and "H" levels in response to the output signal of inverter circuit l4, respectively. With this constitution, such an effect that the skew between output signals D out and can be reduced is obtained. This effect will now be described in detail hereinbelow with reference to Fig. 4 showing a practical constitutional example of the circuit of Fig. 2. In Fig. 4, input signal D in is supplied to each input terminal of CMOS inverter 23 including P-channel type MOS transistor 2l and N-channel type MOS transistor 22, CMOS inverter 26 including P-channel type MOS transistor 24 and N-channel type MOS transistor 25, and CMOS inverter 29 including P-channel type MOS transistor 27 and N-channel type MOS transistor 28. The output terminal of CMOS inverter 23 is connected to the bases of NPN-type bipolar transistors 30 to 32 whose collectors are connected to power source VC and also to the gates of P-channel type MOS transistor 33 and N-channel type MOS transistor 34 which constitute CMOS inverter 35. The emitter of bipolar transistor 30 and the gates of N-channel type MOS transistors 36A and 36B, grounded at one end, are connected to the output terminal of CMOS inverter 26. The emitter of bipolar transistor 3l, the gates of P-channel type MOS transistor 37 and N-channel type MOS transistor 38 which constitute CMOS inverter 39, the gate of N-channel type MOS transistor 4l connected between output terminal 40 and the ground, and the gate of N-channel type MOS transistor 42 which is connected at one end to output terminal 40 are connected to the output terminal of CMOS inverter 29. The bases of NPN-type bipolar transistors 43 and 44, whose collectors are connected to power source VC and the gates of N-channel type MOS transistors 45A and 45B, are connected to the output terminal of CMOS inverter 35. MOS transistor 45A is connected between the gate of MOS transistor 4l and the ground. MOS transistor 45B is connected between the other end of MOS transistor 42 and the ground. The emitter of bipolar transistor 43, the gate of N-channel type MOS transistor 47 connected between an output terminal 46 and the ground, and the gates of N-channel type MOS transistor 48 connected between the other end of MOS transistor 36 and output terminal 46 are connected to the output terminal of CMOS inverter 39. The base of NPN-type bipolar transistor 49, whose collector is connected to power source VC, is connected to the emitter of bipolar transistor 44. Output terminal 40 is also connected to the emitter of bipolar transistor 44 through resistor 50. Output terminal 40 is connected to the emitter of bipolar transistor 49 through resistor 5l. The collector-emitter path of NPN-type bipolar transistor 52 is connected between output terminal 40 and the ground. The node of MOS transistors 42 and 45 is connected to the base of bipolar transistor 52. The base of NPN-type bipolar transistor 53 whose collector is connected to power source VC is connected to the emitter of bipolar transistor 32. Output terminal 46 is also connected to the emitter of bipolar transistor 32 through resistor 54. Output terminal 46 is connected to the emitter of bipolar transistor 53 through resistor 55. The collector-emitter path of an NPN-type bipolar transistor 56 is connected between output terminal 46 and the ground. The node of MOS transistors 48 and 36 is connected to the base of bipolar transistor 56. Output signal D out , having the same phase as input signal D in , is obtained from output terminal 40 through a load circuit including, for example, capacitor C₁ of 50 pF and resistor R₁ of 500 Ω. Output signal D out having the phase opposite to that of input signal D in is derived from output terminal 46 through a load circuit including, for example, capacitor C₂ of 50 pF and resistor R₂ of 500 Ω. CMOS inverters 23, 26, and 29 and bipolar transistors 30 and 3l correspond to inverter circuit l3 in Fig. 2. CMOS inverters 35 and 39 and bipolar transistor 43 correspond to inverter circuit l4. MOS transistors 45A and 45B constitute overcurrent inhibit circuit l7. MOS transistors 36A and 36B constitute overcurrent inhibit circuit 20. Further, in the circuit of Fig. 4, bipolar transistors l5 and l8 of the output stage in Fig. 2 are replaced by Darlington-connected bipolar transistors 44 and 49 and by Darlington-connected bipolar transistors 32 and 53, respectively. MOS transistors l6 and l9 of the output stage are replaced by MOS transistors 4l and 47. Further, current control circuits CC₁ and CC₂ in Fig. 2 are constituted by MOS transistor 42 and bipolar transistor 52, and by MOS transistor 48 and bipolar transistor 56, respectively. The areas of the gates of MOS transistors 4l and 47 are set to values which are tens of times as large as those of MOS transistors 42 and 48. In the foregoing constitution, when input signal D in changes to an "H" level, as shown in Fig. 5A, the outputs of CMOS inverters 23, 26, and 29 change to an "L" level. In Fig. 5B, the output of CMOS inverter 23 is indicated by a solid line and the outputs of CMOS inverters 26 and 29 are shown by broken lines. Therefore, bipolar transistors 30 and 3l are turned off and the emitters of these bipolar transistors are each grounded through MOS transistor 25 or 28, so that MOS transistors 36A, 36B, 4l, and 42 are also turned off. The output of CMOS inverter 35 is set to an "H" level, as shown by a solid line in Fig. 5C, by the "L" level output from CMOS inverter 23. The output of CMOS inverter 39 also changes to an "H" level, as shown by a broken line in Fig. 5C, by the "L" level output from CMOS inverter 29. Bipolar transistors 43 and 44 are turned on by the "H" level output from CMOS inverter 35. The emitter potential of bipolar transistor 43 rises to (VC - VBE). Since the emitter of bipolar transistor 43 is connected to power source VC through MOS transistor 37 of CMOS inverter 39, the emitter potential is further raised and set at the VC level. Thus, MOS transistors 47 and 48 are turned on. In this case, however, since it takes a time until MOS transistor is sufficiently turned ON, output signal is not set at the "L" level at this point in time. Since load capacitor C₂ is connected to output terminal 46, a base current is supplied to bipolar transistor 56 from capacitor C₂ through MOS transistor 48 in the ON state and bipolar transistor 56 is turned on. At this time, as mentioned above, since bipolar transistor 32 is in the OFF state, bipolar transistor 53 is also in the OFF state. In this manner, output signal rapidly decreases to the "L" level. In this case, since the charges in capacitor C₂ are discharged through MOS transistor 47, output signal further rapidly increases. When output signal reaches a preset level, transistor 56 is turned off. However, in this case, MOS transistor 47 is also held in the ON state, thereby reducing output signal to a sufficiently low level. On the other hand, as previously mentioned, since MOS transistors 4l and 42 are turned off by the "L" level output from CMOS inverter 29 and bipolar transistor 44 is in the ON state by the "H" level output from CMOS inverter 35, bipolar transistor 49 is in the ON state. At this time, MOS transistor 45A and 45B are turned on by the "H" level output from CMOS inverter 35. MOS transistor 4l and bipolar transistor 52 are turned off. Namely, as shown by a solid line in Fig. 5D, when bipolar transistor 52 is turned off, output signal D out rapidly changes toward an "H" level. When input signal D in changes to the "L" level, as shown in Fig. 5A, the outputs of CMOS inverters 23, 26, and 29 change to the "H" level, as shown in Fig. 5B. Thus, bipolar transistors 30 and 3l are turned on. Therefore, the emitter potentials of bipolar transistors 30 and 3l increase to (VC - VBE). Each emitter of bipolar transistors 30 and 3l is connected to power source VC through MOS transistor 24 or 27, so that the potential is further raised and set at the VC level. Therefore, MOS transistors 36A, 36B, 4l, and 42 are turned ON. In this case, since it takes a time until MOS transistor 4l is completely turned ON, output signal D out is not immediately set to the "L" level at this point in time. Bipolar transistors 32 and 53 are sequentially turned on by the "H" level signal, which is output from CMOS inverter 23, and the output of CMOS inverter 35 is set to the "L" level. At this time, the output of CMOS inverter 39 is also set to the "L" level by the "H" level signal which is output from CMOS inverter 29. Therefore, bipolar transistors 43, 44, and 49 are turned off and MOS transistors 45A and 45B are set into the OFF state. MOS transistors 47 and 48 are also set into the OFF state. Since load capacitor C₁ is connected to output terminal 40, a base current is supplied to bipolar transistor 52 through MOS transistor 42 set in the ON state, and bipolar transistor 52 is turned ON. Therefore, output signal D out rapidly changes to the "L" level, as shown by a solid line in Fig. 5D. In addition, since bipolar transistor 56 is turned off owing to the OFF state of MOS transistor 48 and the ON state of MOS transistors 36A and 36B, output signal rapidly changes toward the "H" level, as shown by a broken line in Fig. 5D. As described above, when input signal D in changes to the "H" level, output signal D out starts rising when the output signal from CMOS inverter 35 reaches a predetermined value. Further, when MOS transistor 4l and bipolar transistor 52 are turned OFF, output signal D out rapidly decreases. In this case, output signal starts decreasing when the output of CMOS inverter 23 reaches a predetermined value and bipolar transistors 32 and 53 are turned on. Further, when MOS transistor 47 and bipolar transistor 56 are turned ON by MOS transistors 36A and 36B which are turned OFF in response to the output of CMOS inverter 26, output signal rapidly increases. The periods of time after input signal D in reached a predetermined voltage of, e.g., l.5 V from the "L" level (e.g., 0 V) until output signals D out and change to the predetermined voltage level from "L" and "H" levels (e.g., 0 V and 3.5 V), respectively, can be made substantially equal to each other by properly selecting the ratio of the sizes of MOS transistors 4l, 42, 47, and 48. In the case where input signal D in changes to the "L" level, when bipolar transistors 44 and 49 and MOS transistors 45A and 45B start changing to the OFF state by the output signal from CMOS inverter 35, output signal D out starts decreasing. Thereafter, when bipolar transistor 52 is turned ON, output signal D out promptly decreases. In this case, when the output signal of CMOS inverter 23 increases to a predetermined value and bipolar transistors 32 and 53 are turned ON, output signal starts increasing. Thereafter, as MOS transistor 47 and bipolar transistor 56 change to the OFF state, output signal promptly rises. The periods of time after input signal D in decreased to a predetermined voltage of, e.g., l.5 V from an "H" level (e.g., 5 V) until output signals D out and change to the predetermined voltage level from "H" and "L" levels, respectively, can be made substantially equal to each other by properly selecting the ratio of the sizes of MOS transistors 4l, 42, 47, and 48.

Claims: A buffer circuit comprising: a first inverter circuit (23, 26, 29) for receiving an input signal and generating the inverted signal of said input signal from first, second and third output terminals; a second inverter circuit (35, 39) for receiving the signals from said first and third output terminals of said first inverter circuit and generating the inverted signals of these signals from first and second output terminals; first and second bipolar transistors (30, 3l) whose bases are commonly connected to the first output terminal of said first inverter circuit (23, 26, 29) and which are connected at one end to a first power source terminal and respectively connected at the other ends to the second and third output terminals of said first inverter circuit; a third bipolar transistor (43) whose base is connected to the first output terminal of said second inverter circuit and which is connected at one end to the first power source terminal and connected at the other end to the second output terminal of said second inverter circuit; first and second bipolar transistor circuits (44, 49 and 32, 53) which are respectively connected between said first power source terminal and first and second output nodes and are controlled to be set into the opposite conduction states in response to the output signals from the first output terminal of said second inverter circuit (35, 39) and from the first output terminal of the first inverter circuit (23, 26, 29), respectively; first and second MOS transistors (41 and 47) which are respectively connected between the first and second output nodes and a second power source terminal and are controlled to be set into the opposite conduction states in response to the output signals from the third output terminal of said first inverter circuit (23, 26, 29) and from the second output terminal of said second inverter circuit (35, 39), respectively; and third and fourth MOS transistors (45A and 36A) which are respectively connected between the gates of said first and second MOS transistors (41 and 47) and said second power source terminal and are respectively controlled to be set into the opposite conduction states in response to the output signals from the first output terminal of said second inverter circuit (35, 39) and from the second output terminal of said first inverter circuit (23, 26, 29), wherein output signals having the inversion relation are generated from said first and second output nodes in response to said input signal. A buffer circuit according to claim l, characterized in that said first inverter circuit has first to third CMOS inverters (23, 26, and 29) for inverting said input signal and generating output signals from said first to third output terminals thereof, respectively. A buffer circuit according to claim l or 2, characterized in that said second inverter circuit includes a fourth CMOS inverter (35) for inverting the output signal from the first output terminal of said first inverter circuit (23, 26, 29) and generating an output signal from the first output terminal thereof and a fifth CMOS inverter (39) for inverting the output signal from the third output terminal of said first inverter circuit (23, 26, 29) and generating an output signal from the second output terminal thereof. A buffer circuit according to claim l, 2, or 3, characterized by further comprising fourth and fifth bipolar transistors (52 and 56) which are respectively connected between the first and second output nodes and the second power source terminal, fifth and sixth MOS transistors (42 and 45B) which are respectively connected between the base of said fourth bipolar transistor (52) on one hand and said first output node and the second power source terminal on the other, and seventh and eighth MOS transistors (48 and 36B) which are respectively connected between the base of said fifth bipolar transistor (56) on one hand and said second output node and the second power source terminal on the other, and characterized in that the gates of said fifth to eighth MOS transistors (42, 45B, 48, and 36B) are respectively connected to the third output terminal of said first inverter circuit (23, 26, 29), the first and second output terminals of said second inverter circuit (35, 39), and the second output terminal of said first inverter circuit (23, 26, 29). A buffer circuit according to any one of claims l to 4, characterized in that each of said first and second bipolar transistor circuits has two bipolar transistors (44, 49 and 32, 53) which are Darlington-connected.

Inventors: UENO, MASAJI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: H03K5
IPC codes: H03K5, H03K19, H03K17