Step-cut insulated gate static induction transistors and method of manufacturing the same

Abstract: A step-cut insulated gate static induction transistor can accurately make a channel length and a gate length and is excellent as a high speed transistor but is greatly affected by a deviation in mask alignment in the manufacturing process. This process utilizes the fact that a gate portion formed in a previous processes is used as a mask in a post portion to thereby self-adjustably form the post portion, thus eliminating the influence of the deviation in mask alignment. In addition, a construction in which a current flowing through a portion apart from a gate between a drain and a source can be restricted. The aforesaid manufacturing method is also used for this construction.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a step-cut insulated gate static induction transistor capable of carrying out high-speed switching, a high-speed and low power step-cut insulated gate static induction transistor integrated circuit, and method of manufacturing the same. Description of the Prior Art Insulated gate transistors for high frequency amplification and integrated circuits have been heretofore used but have a disadvantage that the drivability is small. For example, a complementary metal-oxide-semiconductor transistor integrated circuit (C-MOS) has been known as an application of an insulated gate transistor. However, this circuit (C-MOS) operates at low dissipation power but operates at low switching speed, because of small drivability. To overcome such disadvantages as noted above, one of the present inventors has previously proposed an insulated gate static induction transistor (for example, see Japanese Patent Application No. 1756/1977) and a step-cut insulated gate static induction transistor (for example, see Japanese Patent Application No. 13,707/1977). The insulated gate static induction transistor is designed so that the depletion layer spread from the drain region reaches the source region. So, a current flowing from source to drain is controlled not only by the gate voltage but also by the drain voltage and the current flows into not only an interface between a semiconductor and an insulator but a substrate. Therefore, the insulated gate static induction transistor has non-saturating current-voltage characteristics and has large drivability. Particularly, the step-cut insulated gate static induction transistor has a channel formed depthwise of a semiconductor substrate, thus providing a good controllability for a channel length and a gate length, and said transistor is well suited for shortening a channel to improve its drivability. Thus, the step-cut insulated gate static induction transistor is able to increase its drivability and decrease a parastic capacitance and therefore exhibits an excellent performance as a high speed switching transistor and a high-speed and low power integrated circuit. Prior art will be described hereinafter with reference to FIG.1. FIG.1(a) shows an example of a construction in section of a conventional step-cut insulated gate static induction transistor. In FIG. 1(a) 10 designates a semiconductor substrate, a main surface of which is partly provided with a U-shaped groove. A drain region 11, a channel region 13 and a source region 12 are provided in said order depthwise from the main surface along the side wall of the U-shaped groove, and a drain electrode 11' is connected to the drain region 11. A source electrode, which is not shown, is provided vertically as viewed from the paper surface. The drain region 11 and the source region 12 have the impurity concentration of the order of 10 18 to 10 21 cm -3 , the conductivity type of which is shown as P type but N type can be used. In addition, the region 11 can be used as a source region and the region 12 used as a drain region. The channel region 13 has the impurity concentration of the order of 10 12 to 10 16 cm -3 , the conductivity type of which can be of the same as or opposite to that of the drain region 11 and the source region 12, and a multi-layered construction can be also employed. The impurity concentration as well as the depth of the aforesaid U-shaped groove are determined so that a depletion layer spread from the drain region 11 reaches the source region 12 at least a part of the operating condition thereof. A gate insulator 14 such as an oxide film is provided in contact with the channel region 13 and has a thickness of the order of 100 to 1,000 Å [1 µm = 10 4 Å]. On the side opposite the gate insulator 14 is provided a gate electrode 14' formed of metal, polycrystalline silicon or the like. 15 designates a field oxide film. Since a conventional step-cut insulated gate static induction transistor as shown in FIG. 1(a) is formed depthwise with respect to a semiconductor substrate. dimensions of a transistor can be controlled with precision of deposition and etching providing a good controllability for the channel length and gate length and being well suited for shortening the channel to improve drivability Accordingly, such a transistor as noted above has a large drivability and can decrease a parastic capacitance and therefore exhibits an excellent performance as a high speed switching transistor and a high speed low power integrated circuit. One example of a well known fabrication process for manufacturing the aforesaid step-cut insulated gate static conduction transistor will be described with reference to FIG. 2. FIG. 2(a) An epitaxial layer 22 constituting a channel is grown on a semiconductor substrate 21 used as a drain, a channel impurity is introduced by thermal diffusion or ion implantation and thereafter a U-shaped groove is formed in a part of a main surface of the semiconductor substrate by anisotropic plasma etching or the like. FIG. 2(b) A conventional photolithography and a selective oxidation are used to form a field oxide film 23 and windows, which are provided in a part of a main surface of a semiconductor substrate and are including at a part of the side wall of a U-shaped groove to form a gate oxide film 24. FIG. 2(c) A polycrystalline silicon 25 constituting a gate electrode is deposited, which is subjected to etching by a conventional photolithography so as to have it remained on a gate oxide film of the side wall of a U-shaped groove, and thereafter a source region 26 is formed by thermal diffusion or ion implantation. FIG. 2(d) A passivation film 27 is deposited and contact hole is opened to form a drain electrode 21', a gate electrode 25' and a source electrode 26'. The impurity concentration of the aforesaid drain region 21 and source region 26 is of the order of 10 18 to 10 21 cm -3 . It is noted of course that the conductive type can be of either P type or N type, and the 21 can be used as a source region and the 26 as a drain region conversely to the former. The impurity concentration of the channel region 22 is of the order of 10 12 to 10 16 cm -3 , and the conductive type thereof can be the same as or opposite to that of the aforementioned drain region and source region, a multi-layered construction being possibly used. However, at least in a part of the operating condition a depletion layer spread from the drain region must reach the source region, and to meet this requirement, the impurity concentration thereof as well as the depth of the U-shaped groove are determined. The thickness of the gate oxide film 24 is set to be of the order of 100 to 1,000 Å, and the gate electrode is ordinarily formed of polycrystalline silicon or the like, the thickness being of the order of 1000 Å to 1 µm. In the above-described conventional process of manufacturing an step-cut insulated gate static induction transistor, a conventional photolithography is used and therefore a margin for mask alignment is required. Consequently, this margin make it difficult to form the gate electrode 25 only on the side wall of the U-shaped groove. For example, FIG. 3 shows an example of a plan construction Of a conventional step-cut insulated gate static induction transistor, which corresponds to the fabrication process shown in FIG. 2. In FIG. 3. 31 designates a side wall of a U-shaped groove, 32 a window provided by selective oxidation, 33 a gate electrode of a polycrystalline silicon, 34 and 35 a drain contact hole and a gate contact hole, respectively, and 36 and 37 a drain electrode and a gate electrode, respectively. In FIG. 3, the section of B-B' is shown in FIG. 2(d). ℓ b and ℓ c denote mask alignment margins with respect to the photolithography of the FIG. 2 processes (b) and (c), the margin being normally designed approximately 0.1 to 2 µm. An example of the drain current-drain voltage characteristics of a transistor different in mask alignment margin ℓc is shown in FIGS. 4 (a) to (c). In this case, it is designed so that the channel length is approximately 0.5 µm; the dosage of the channel impurity is approximately 1.5 x 10 13 cm -2 ; and the thickness of the gate oxide film is approximately 250 Å, the mask alignment margin ℓc being 0 µm in the (a), and 1 µm and 2 µm in the (b) and (c), respectively. In the case of the (a), there exhibits the unsaturated type current-voltage characteristic, the drivability is large and the characteristic of the step-cut insulated gate static induction transistor is conspicuous but there gives rise to a disadvantage that yield is poor. On the other hand, in the case of the (b) and (c), since a portion corresponding to the mask alignment margin works similarly to a planar type transistor, the effective channel length becomes extended, deteriorating the drivability. In the conventional step-cut insulated gate static induction transistor, the drain region 11 is opposed to the source region 12 with the channel region 13 sandwiched therebetween, and therefore if the channel is shortenned to attain higher speed, a current flows between drain and source even at a point away from the gate surface by being affected by the drain field. - This current component cannot be controlled by a gate voltage. This results in disadvantages that a leak current is large at the off state, etc. For example, FIG. 1 (b) shows an example of the drain current-drain voltage characteristics of a conventional step-cut insulated gate static induction transistor so designed that the channel length is approximately 0.5 µm, the dosage of channel impurity is approximately 2 x 10 13 cm -2 , and the thickness of the gate oxide film is approximately 250 Å. Even when the gate voltage is 0 Volt, the drain current flows as the drain voltage increases. It is noted of course that such a current flowing on the bulk side can be suppressed to some extent by selecting the impurity concentration of the channel region 3. FIG. 1 (c) shows an example of the drain current - drain voltage characteristics of a conventional step-cut insulated gate static induction transistor so designed that the channel length is approximately 0.5 µm, the dosage of channel impurity is approximately 6x 10 13 cm -2 , and the thickness of the gate oxide film is approximately 250 Å. A leak current at the off state was improved but drivability is sacrificed to some extent because the static induction effect on the drain side became hard to extend to the source side, and the threshold voltage is increased. United States Patent No. 4,541,166 discloses a semiconductor device having a longitudinal or horizontal structure. The device has a channel region of the same impurity density as adjacent source and drain regions. In such a device, current which cannot be controlled by the gate tends to flow into the interior. US-A-4334235 discloses further SIT, i.e. static induction, transistors. It is an object of the present invention, while eliminating the disadvantages noted above with respect to the aforementioned method of manufacturing step-cut insulated gate static induction transistor, to provide a method of manufacturing a step-cut insulated gate static induction transistor, which can self-adjustably form a gate oxide film only on the side wall of a U-shaped groove, whilst increasing reproducibility and reliability. It is a further object of this invention, while overcoming the disadvantages noted above with respect to the aforementioned step-cut insulated gate static induction transistor to improve the characteristics, to provide a step-cut insulated gate static induction transistor which can carry out higher switching speed, low power dissipation and the method of manufacturing the same. The invention is a step-cut insulated gate static induction transistor comprising: a U-shaped groove in a main surface of a semiconductor substrate; a drain/source region having a high impurity concentration and arranged so as to contact at least a part of an upper portion of one side wall of said groove; a source/drain region having a high impurity concentration provided on said substrate and arranged beneath said drain/source region and in contact with at least a part of a lower portion of said side wall; a first channel region having a low impurity concentration provided in the vicinity of the surface of said side wall, and a second channel region disposed between said source and drain regions; characterised in that a current flowing through said first channel region is controlled by an insulated gate consisting of a thin gate oxide film formed on said first channel region provided on at least a part of said U-shaped groove, and in that the impurity concentration of the second channel region, having the conductivity type opposite to that of the said drain region and said source region, is selected to eliminate current flowing through said second channel region between said drain/source region and said source/drain region in a direction perpendicular to the flow of current through said first channel region. In an improved construction, as shown in FIG, 15 (a), a channel region 153 having a low impurity concentration is provided only in the vicinity of a surface of a side wall of a U-shaped groove of a step-cut insulated gate static induction transistor, and a channel region 153' sandwiched between a drain source 151 and a source region 152 on the bulk side is of a high impurity concentration. The impurity concentration of the channel region 153' on the bulk side is so determined that in a normal operating condition a leakage current does not flow between the drain and source under the influence of a drain electric field. As a consequence, in such a construction as described above, there provides an step-cut insulated gate static induction transistor which can shorter channel to improve drivability without increasing a threshold voltage and without increasing a leak current between the drain and source. An step-cut insulated gate static induction transistor is also advantageously manufactured, similarly to the former, by the step of self-adjustably forming on the side wall of a U-shaped groove a channel region of low impurity concentration a gate oxide film, gate electrode, a source region and a drain region. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows one example of a conventional step-cut insulated gate static induction transistor, FIG. 1 (a) showing a sectional structural view, FIG. 1 (b) showing one example of the drain current - drain voltage characteristics and FIG. 1 (c) showing another example of the drain current-drain voltage characteristics; FIG. 2 is an explanatory view of the fabrication process showing one example of a conventional method of manufacturing an step-cut insulated gate static induction transistor; FIG. 3 is a plan view showing a plane construction of a conventional step-cut insulated gate static induction transistor; FIG. 4 is a characteristic view showing one example of the drain current - drain voltage characteristics caused by a difference of mask alignment mirgin of a conventional step-cut insulated gate static induction transistor; FIG. 5 shows an example of an improved step-cut insulated gate static induction transistor, FIG. 5 (a) being a sectional structural view, and FIG. 5 (b) showing one example of the drain current - drain voltage characteristics; FIG. 6 is a sectional view showing one example of an integrated circuit of an improved step-cut insulated gate static induction transistor; and FIG. 17 is an explanatory view of the fabrication process of an improved undercut insulated gate electrostatic induction transistor according to the manufacturing method of this invention. FIG. 5 (a) shows one example of a sectional construction of an improved step-cut insulated gate static induction transistor. In the figure, 150 designates a semiconductor substrate, the main surface of which is partly provided with a U-shaped groove. A drain region 151 is provided in the main surface so as contact the upper end of the side wall of the U-shaped groove, and a source region 152 is provided beneath the drain region 151 so as to contact the lower end of the side wall of the U-shaped groove, a drain electrode 151' being connected to the drain region 151. A source electrode though not shown is provided, for example, vertically as viewed from the paper surface. The drain region 151 and source region 152 have the impurity concentration of the order of 10 18 to 10 21 cm -3 , and the conductivity type shown is p type but n type can be employed. The region 151 can be used as a source region and the region 152 can be used as a drain region. The channel 153 is provided in the vicinity of the surface of the side wall of the U-shaped groove and has the impurity concentration of the order of 10 12 to 10 16 . The conductivity type can be the same as or opposite to that of the drain region 151 and source region 152. However, at least in a part of the operating condition the conductivity type, the impurity cocentration and the depth of the U-shsped groove are determined so that a depletion layer spread from the drain region 151 reaches the source region 152. A channel region 153' on the bulk side is provided adjacent to the channel region 153 and between the drain region 151 and the source region 152, and has the conductivity type opposite to that of the drain region 151 and the source region 152, and the impurity concentration thereof is set so as not flow a current between the drain and the source under the influence of the drain electric field. A gate insulator 154 such as an oxide film is provided in contact with the channel region 153 and has a thickness of the order of 100 to 1,000 Å. Opposite to the gate insulator 154 is provided a gate electrode 154' formed from metal or polychrystalline silicon or the like. 155 in FIG. 5 (a) designates a field oxide film. Such a channel region 153 in the vicinity of the side wall of the U-shaped groove can be formed by the epitaxial growth after the U-shaped groove has been formed, and also here the thickness can be controlled with the precision of the growth. Particularly, as the growing method, if the molecular layer epitaxy (MLE) is used, the low-temperature growing can be effected. Therefore, redistribution of impurities is small, and the precision of the growth is enhanced up to the order of one molecular layer. FIG. 5 (b) shows the gate voltage - drain current characteristics of the step-cut insulated gate static induction transistor according to the present invention while comparing with that of the prior art. In this case, it is designed so that the channel length is approximately 0.5 um, the dosage of the channel impurity on the bulk side is spproximately 4 x 10 13 cm -2 , and the thickness of the gate oxide film is 250 Å. The channel region adjacent the side wall of the U-shaped groove is formed by the low-pressure eppitaxial growth. Even in the impurity concentration of the channel on the bulk side is same as that of the prior art, a threshold voltage can be reduced. FIG. 6 shows a sectional construction of an inverter gate in which the step-cut insulated gate static induction transistor according to the present invention is applied to a complementary metal-oxide-semiconductor transistor integrated circuit. An N channel transistor in a semiconductor substrate 160 comprises an n + drain region 161, an n + source region 163, a channel region 165, a channel region 165' on the bulk side, a drain electrode 161', a gate insulator 167, and a gate electrode 167' whereas a P channel transistor comprises a p + drain region 162, a p + source region 164, a channel region 166, a channel region 166' on the bulk side, a drain electrode 162', a gate insulator 167, and a gate electrode 167'. The n + drain region, p + drain region 162, n + source region 163 and p + source region 164 have the impurity concentration of the order of the 10 18 to 10 21 cm -3 . The channel regions 165 and 166 have the impurity concentration of the order of 10 12 to 10 16 cm -3 , and at least in a part of the operating cindition the impurity concentration as well as the depth of the U-shaped groove are determined so that a depletion layer spread from the drain regions 161 and 162 reaches the source regions 163 and 164. The channel regions 165' and 166' on the bulk side have the conductivity type opposite to that of the drain regions 161 and 162 and the source regions 163 and 164 (thus, the region 165' is p type, and the region 166' is n type), and the impurity concentrations is determind so that a current comparents flowing through these regions does not flow under the influence of the drain electric field. A gate insulated film 167 such as an oxide film has a thickness of the order of 100 to 1,000 Å. In the figure, 168 denotes a field oxide film. There is provided a p well 169 for separating the p channel transistor from the N channel transistor. The gate electrode 167' comprises a logical input while the drain electrodes 161' and 162' comprise a logical output, a power supplied voltage is applied to source electrodes connected to the source regions 163 and 164, respectively. When the logical input is in a high level, the N channel transistor assumes an on state while the P channel transistor assumes an off state, and therefore, the logical output becomes a low level. The same is true for the reversal case. Even if the shorter channel is attained to easily extend the static induction effect of the drain voltage to the source region to increase the drivability of the device, the step-cut insulated gate static induction transistor according to the present invention is able to minimize a leakage current at the off stock and reduce a standby power by suitable selection of the impurity concentration of the channel regions 165' and 166' on the bulk side. Accordingly, it is possible to provide a high speed and low power complementary metal-oxide-semiconductor transistor integrated circuit. For example, a propagation delay time of 430 psec is obtained at a dissipation power of 10 mW, by a ring oscillator of a complementary metal-oxide-semiconductor transistor integrated circuit. As described above, in the present invention, the disadvantages encountered in the conventional step-cut insulated gate static induction transistor are overcome, and even when the shorter channel is attained to sufficiently obtain the static induction effect of the drain voltage, unnecessary current between the drain and the source may be decreased. Accordingly, the present invention may provide a step-cut insulated gate static induction transistor which can perform high speed switching. In addition, this transistor can be used to provide a high speed and low power insulated gate transistor integrated circuit, thus providing a great industrial value. (Manufacturing method) FIG. 7 shows one example of a process of manufacturing a step-cut insulated gate static induction transistor as described above. This process is the subject of the Applicants' co-pending European Patent Application N° 0 481 965. (a) An epitaxial layer 172' constituting a channel on the bulb side is grown on a semiconductor substrate 171 used as a drain, a channel impurity is introduced therein by thermal diffusion or ion implantation and hereafter a U-shaped groove is formed in a part of the surface of the semiconductor substrate by anisotropic plasma etching or the like. (b) An epitaxial layer 172 constituting a channel region adjacent the side wall is grown and a channel impurity is introduced therein by thermal diffusion from a channel on the bulk side region or by oblique ion implantation or the like. (c) A mask material 173 for selective oxidation is deposited, and the conventional photolithography and anisotropic plasma etching are combined to thereby leave the mask material in a region as a source of the surface of the semiconductor substrate and in a region as a gate of the side wall of the U-shaped groove. (d) The selective oxidation is used to form a field oxide film 175, and at the same time a window is formed in a region as a source of the surface of the semiconductor and in a region as a gate of the side wall of the U-shaped groove to form a gate oxide film 174. (e) A polycrystalline silicon 176 constituting a gate electrode is deposited and then subjected to etching so as to leave it on the gate oxide film 174 of the side wall of the U-shaped groove by the conventional photolithography, after which a source region 177 is formed by thermal diffusion or ion implantation. (f) A passivation film 178 is deposited and a contact hole is made to form a drain electrode 171', a gate electrode 176' and a source electrode 177'. The drain region 171 and the source region 177 have the impurity concentration of the order of 10 19 to 10 21 /cm 3 . The conductivity type shown is N type but it is noted of course that P type can be employed. The 171 can be used as a source region, and the 177 as a drain region. The impurity concentration of the channel region 172 adjacent the side wall of the U-shaped groove is of the order of 10 12 to 10 16 /cm 3 , and the conductivity type thereof can be the same as or opposite to that of the drain region and the source region. However, at least in a part of the operating condition, the impurity concentration as well as the depth of the U-shaped groove are determined so that a depletion layer spread from the drain region reaches the soruce region. The channel region 172 on the bulk side has the conductivity type opposite to that of the drain region and the source region, and the impurity concentration is set so as not to flow a leakage current between the drain and the source under the influence of the drain electric field. The thickness of the gate oxide film 174 is set to approximately 100 to 1,000 Å.

Claims: A step-cut insulated gate static induction transistor comprising: a U-shaped groove in a main surface of a semiconductor substrate (150); a drain/source region (151) having a high impurity concentration and arranged so as to contact at least a part of an upper portion of one side wall of said groove; a source/drain region (152) having a high impurity concentration provided on said substrate and arranged beneath said drain/source region (151) and in contact with at least a part of a lower portion of said side wall; a first channel region (153) having a low impurity concentration provided in the vicinity of the surface of said side wall, and a second channel region (153') disposed between said source and drain regions; characterised in that a current flowing through said first channel region (153) is controlled by an insulated gate (154) consisting of a thin gate oxide film formed on said first channel region (153) provided on at least a part of said U-shaped groove, and in that the impurity concentration of the second channel region, having the conductivity type opposite to that of the said drain region and the said source region, (153') is selected to eliminate current flowing through said second channel region (153') between said drain/source region (151) and said source/drain region (152) in a direction perpendicular to the flow of current through said first channel region (153). A transistor as claimed in claim 1 further comprising a gate electrode (154') on said thin gate oxide film (154). A transistor as claimed in any preceding claim comprising at least one of the constituent elements of a semiconductor integrated circuit.

Inventors: NISHIZAWA JUNICHI, SUZUKI SOUBEI, TAKEDA NOBUO, NISHIZAWA, JUNICHI, SUZUKI, SOUBEI, TAKEDA, NOBUO
Applicants: JAPAN RES DEV CORP, NISHIZAWA JUNICHI, SUZUKI SOUBEI, TAKEDA NOBUO, NISHIZAWA, JUN-ICHI, RESEARCH DEVELOPMENT CORPORATION OF JAPAN, SUZUKI, SOUBEI, TAKEDA, NOBUO
Application year: 1987
Main classification: H01L29
IPC codes: H01L29