MULTI-LEVEL PATTERN DETECTOR FOR A SINGLE SIGNAL

Abstract: A method and apparatus are disclosed which provide for the generation of a trigger signal responsive to the detection of a plurality of selected sequential events in a single monitored signal. A plurality of trigger detect devices operate independently to monitor a signal for the occurrence of selected trigger criteria, and produce indications thereof having selected durations. The duration of the indications function to provide continuous indications of the occurence of the selected trigger conditions over the periods thereof. In one embodiment, a state machine delays each of the indications by an amount of time approximately equal to the time between the respective events and a final event in the sequence, thereafter combining the indications according to preselected logical operations. As a result of the delays, the indications from the trigger detect devices are combined at approximately the same time. The duration of the indications operate to preclude timing differences between events from preventing detection of the series of selected sequential events. In an alternate embodiment, the state machine operates to combined information from the trigger detect devices in a serial fashion according to pre-selected logical operations and delayed by selected time periods to produce the desired trigger signal. Timing differences between sequential events are again precluded from preventing detection of the series of selected sequential events by the duration of the continuous indication produced by each of the trigger detect devices.

Description: This invention relates to the field of electronic trigger devices, and in particular to a method and apparatus for detection of a predefined time sequence of events in a single signal, and the subsequent generation of an indication therefor. In electronic monitoring applications, it is frequently desirable to monitor a signal for the occurrence of selected events, and produce an indication in response thereto. Monitoring activity may be performed with respect to a single signal or a plurality of signals. It is to be understood that the present invention is concerned with monitoring a single signal for the occurrence of a plurality of sequential events occurring therein, and the production of an indication in response thereto. In the past, single signals have been monitored with respect to level and slope criteria. In particular, an indication is generated responsive to the level and slope of a monitored signal becoming equal to a selected level and slope. While such an approach is useful in a wide variety of applications, e.g., a triggered sweep oscilloscope, there are many applications where a more complex monitoring capability is necessary. Level and slope information may be combined with other information to produce more complex trigger criteria. By way of illustration, an indication generated as a result of level and slope criteria being satsfied may be used to trigger a timing device. The timing device thereafter operates to measure a selected period of time, and produce an indication subsequent to the passage of the selected time period. Delayed trigger sweep oscilloscopes are an illustration of such an application. While the foregoing applications have addressed detection of a single event, more complex monitoring operations may involve the detection of a series of sequential events in a single signal. By way of illustration, a plurality of events in a monitored signal may be defined by specifying a level and slope for each of such events. In addition, the amount of time by which each of such events is displaced from either an adjacent event or a final event in such a sequence may be specified. Thereafter, level and slope monitoring apparatus may be employed to detect the occurrence of each of such events, and used with associated timing apparatus to produce a trigger signal at the occurrence of a final event in such a sequence. While such an arrangement is plausible, a number of practical considerations preclude effective use of such an approach. In particular, it is frequently difficult to precisely specify the amount of time between events in such a sequence. In addition, the times at which the events occur may likewise vary. Such timing inaccuracies generally preclude successful detection of a sequence of events in a single signal. In a similar manner, it is frequently desirable to monitor a binary signal for the occurrence of a selected pattern of information. In the past this has generally been accomplished through the use of a state machine which operates to continuously monitor a signal, and change states upon the occurrence of each change in the binary signal. Again, while such an approach in theory is possible, practical considerations frequently operate to limit the effectiveness of such an approach. In particular, as the clock which is associated with the binary signal is generally not available for synchronization purposes, timing differences between the clocks associated with monitoring apparatus and the apparatus which is producing the binary signal frequently preclude reliable detection of such a pattern of information. It is an object of the invention to provide a method and an electronic monitoring apparatus capable of detecting a sequence of events in a single signal, notwithstanding timing differences which may occur between the sequential events therein. In accordance with the method and apparatus of the present invention as characterized in claims 1 and 10, a plurality of selected serial events may be detected in a single monitored signal, notwithstanding uncertainty with respect to the precise times at which each of said events occur. A plurality of trigger detect devices each monitor for the occurrence of one of the selected events, and produce an indication of a selected period in response to the detection of the associated event. The indications so produced are thereafter combined in a state machine to produce a final trigger signal indicating the detection of the selected serial events. In one embodiment of the present invention, the indication from each of the trigger detect devices is delayed by the state machine by an amount of time corresponding to the approximate amount of time by which the event detected by the associated trigger detect device is displaced in time from the final event in the sequence of serial events. The delayed indications from each of the trigger detect devices are thereafter combined in a selected manner to produce a final trigger signal. The periods associated with the indications produced by the trigger detect devices function to provide a continuous indication of the occurrence of the corresponding event for said periods, thereby enabling detection of the plurality of selected serial events, notwithstanding uncertainty with respect to the precise times at which each of said events occur. In an alternate embodiment of the present invention, the indication from a first trigger detect device is delayed by the state machine by a selected period of time corresponding to the approximate amount of time by which the selected event is displaced in time from a subsequent event in the sequence of serial events. An indication from a trigger detect device functioning to detect the subsequent event is then combined in a selected manner with the delayed indication produced by the first trigger detect device. It will be observed in this manner that the period of the signal produced by the first trigger detect device operates to provide a continuous indication of the occurrence of the first event for said period, thereby allowing detection of both the first and second events notwithstanding uncertainty with respect to the precise times at which the first and second event occur. Indications produced by additional trigger detect devices are then combined in a similar manner to provide an indication of the occurrence of the selected serial events. In the drawings: Figure 1 is a functional block diagram of apparatus in accordance with the present invention; Figure 2 is a functional block diagram of an implementation of state machine 7⊘ of Figure 1; Figure 3 is a functional block diagram of an alternate implementation of state machine 7⊘ of Figure 1. Figure 4 illustrates an implementation for trigger detect 2⊘ of Figure 1; Figure 5 illustrates an implementation of logic 15⊘, 16⊘ and 18⊘ of Figure 2, and logic 26⊘ and 28⊘ of Figure 3; and Figure 6 is a waveform diagram illustrating operational features of the present invention. A single input signal is continuously monitored for the serial occurrence of a set of pre-defined conditions, and upon the occurrence thereof, an indication is produced, as broadly illustrated by functional apparatus in Figure 1. Referring now to Figure 1, trigger detect 2⊘ has associated therewith input terminals 22 and 24, and output terminal 26. Trigger detect 2⊘ functions to monitor the signal coupled to terminal 24 to identify a portion of that signal that corresponds to the trigger criteria previously coupled to input terminal 22. Trigger criteria coupled to input terminal 22 may be any of a variety of information descriptive of a desired trigger criteria, including level and slope information, as more fully discussed hereafter. Trigger detect 2⊘ produces a signal on its output terminal 26 having a selected period when trigger criteria coupled to input terminal 22 is found in the input signal coupled to input terminal 24. Any number of a plurality of trigger devices similar to trigger detect 2⊘ may be employed, e.g., trigger detect 3⊘ and 5⊘. Trigger detect 3⊘ and 5⊘ have associated therewith input terminals 32 and 52, 34 and 54, and output terminals 36 and 56, respectively. Each of trigger detect 3⊘ and 5⊘ functions to independently compare the same input signal coupled to their input terminals 34 and 54, respectively, with trigger criteria previously coupled to input terminals 32 and 52, respectively. Trigger criteria coupled to input terminals 32 and 52 may also be any of a variety of information descriptive of desired trigger criteria, as previously discussed with respect to trigger detect 2⊘. Trigger detect 3⊘ and 5⊘ each produces a signal having a selected duration on its output terminals 36 and 56, respectively, when the selected trigger criteria are found present in the input signal. A plurality of trigger detect devices, i.e., trigger detect 2⊘, 3⊘ or 5⊘, may be present, the number of which being determined by the nature of a predefined serial sequence of events which are desired to be detected, as more fully discussed hereafter. Consequently, while Figure 1 illustrates three trigger detect devices, i.e., trigger detect 2⊘, 3⊘ and 5⊘, it is to be understood that any number of a plurality of trigger devices may be employed. Trigger criteria control 6⊘ has associated therewith terminals 62, 64 and 66, and functions to couple selected trigger criteria to each trigger detect device, as more fully discussed hereafter. State machine 7⊘ functions to monitor the signals produced by each trigger detect device, and to produce a trigger signal when a predefined sequence of signals from the trigger detect devices has been found to exist. State machine 7⊘ has a plurality of input terminals, e.g., input terminals 72, 74 and 76, and an output terminal 78. As was the case with the number of trigger detect devices, it is to be understood that the number of input terminals associated with state machine 7⊘ is determined by the number of trigger detect devices employed in a particular application, there being one input terminal for each trigger detect device to couple the signal produced therefrom to state machine 7⊘. The foregoing described apparatus is configured in the following manner. A single signal which is desired to be monitored, i.e., monitored signal 1⊘, is coupled to each of the input terminals of the trigger detect devices, e.g., terminals 24, 34 and 54, respectively. Trigger criteria from trigger criteria control 6⊘ are coupled to each trigger detect device. The foregoing described apparatus operates in the following manner. Trigger criteria control 6⊘ first couples preselected trigger criteria to each of the trigger detect devices. The precise nature of the trigger criteria coupled to each of the foregoing described trigger detect devices is determined by a desired monitoring operation, as more fully discussed hereafter, and could include combinations of level and slope information. Trigger criteria control 6⊘ further couples time period information to each trigger detect device, as more fully discussed hereafter. Thereafter, each of trigger detect devices 2⊘, 3⊘ and 5⊘ operates in an independent manner to continuously compare monitored signal 1⊘ against the trigger criteria previously coupled thereto. When the trigger criteria of interest is found present in monitored signal 1⊘, the corresponding trigger detect device produces an indication thereof on the associated output terminal, having a duration according to the time period information previously coupled thereto. State machine 7⊘ monitors the occurrence of signals appearing on its input terminals, and upon the occurrence of a pre-defined sequence thereon, functions to produce an indication thereof on output terminal 78, as more fully discussed hereafter. It should be observed in this regard that state machine 7⊘ may be configured to detect any of a wide variety of conditions appearing on the input terminals associated therewith. Figure 2 illustrates a functional implementation for state machine 7⊘ (Figure 1). Referring to Figure 2, variable digital delay 1⊘⊘ has an input terminal 1⊘2 and an output terminal 1⊘4. In addition, variable digital delay 1⊘⊘ further has a control terminal 1⊘6 through which control information , i.e., a clock signal, a load signal and a signal containing time period information, is coupled to variable digital delay 1⊘⊘, as more fully discussed hereafter. Variable digital delay 1⊘⊘ functions responsive to a first signal coupled to input terminal 1⊘2 to produce a second signal on output terminal 1⊘4 after a selected period of time. In particular, variable digital delay 1⊘⊘ functions as a delay line having a selected delay period. Consequently if a low-to-high transition occurs on a signal coupled to input terminal 1⊘2, the low-to-high transition will appear on output terminal 1⊘4 subsequent to the expiraton of the selected delay period. The duration of the selected delay period is determined by information previously coupled to control terminal 1⊘6, as more fully discussed hereafter. Variable digital delays 11⊘ and 13⊘ likewise have input terminals 112 and 132, output terminals 114 and 134, and control terminals 116 and 136, respectively. Variable digital delays 11⊘ and 13⊘ function in a manner identical to variable digital delay 1⊘⊘. State machine 7⊘ employs a plurality of such devices, as indicated generally by variable digital delays 1⊘⊘, 11⊘ and 13⊘. The number of variable digital delays employed in a specific implementation is determined by the number of trigger detect devices, e.g., trigger detect 2⊘, 3⊘ or 5⊘ (Figure 1), employed in a particular application. Logic 15⊘ has an input terminal 154 and an output terminal 156. Logic 15⊘ functions to produce a signal on its output terminal 156 responsive to the signal coupled to its input terminal 154 according to a preselected logic operation, as more fully discussed hereafter. Logic 16⊘ and 18⊘ have input terminals 162, 164 and 182, 184, and output terminals 166 and 186, respectively. Logic 16⊘ and 18⊘ function to produce a signal on their output terminals 166 and 186, respectively, responsive to signals coupled to their input terminals 162, 164 and 182, 184, respectively, according to preselected logic operations, as more fully discussed hereafter. State machine 7⊘ has a plurality of such logic devices. The number of logic devices employed in an application is determined by the corresponding number of variable digital delays, there being one logic device associated with each variable digital delay for the functional implementation of state machine 7⊘ illustrated in Figure 2. State machine control 19⊘ functions to produce signals necessary in the operation of the variable digital delays associated with state machine 7⊘. In particular, state machine control 19⊘ functions to couple preselected time periods to variable digital delays 1⊘⊘, 11⊘ and 13⊘. The time period coupled to each variable digital delay corresponds to an approximate period of time between the event detected by the associated trigger detect device and the final event of the serial sequence of events, as more fully discussed hereafter. The manner in which the foregoing described signals would be produced by state machine control 19⊘ would be well known to one of ordinary skill in the art. The foregoing described apparatus is configured in the following way. The output terminal of each trigger detect circuit (Figure 1) is coupled to a different input terminal of the variable digital delay circuits of state machine 7⊘. The output terminal 1⊘4 of the first variable digital delay is coupled to terminal 154 of logic 15⊘. Output terminal 156 of logic 15⊘ is coupled to input terminal 162 of logic 16⊘. In a similar manner as was previously discussed with respect to variable digital delay 1⊘⊘, input terminals 112 and 132 of variable digital delays 11⊘ and 13⊘ are coupled to the corresponding output terminals of the associated trigger detect devices (Figure 1). Output terminal 114 of variable digital delay 11⊘ is coupled to input terminal 164 of logic 16⊘. Subsequent combinations of variable digital delays and associated logic devices are configured in a similar manner. Output terminal 134 of variable digital delay 13⊘ is coupled to input terminal 184 of logic 18⊘. Terminal 182 of logic 18⊘ is coupled to the output of the preceding logic device. In an implementation employing three trigger detect devices, e.g., trigger detect 2⊘, 3⊘ and 5⊘ (Figure 1), output terminal 166 of logic 16⊘ would be coupled to terminal 182 of logic 18⊘. The output of state machine 7⊘, i.e., terminal 78 of Figure 1, is obtained from the output terminal of the last logic device, e.g., terminal 186 of Logic 18⊘. The foregoing described apparatus of Figure 2 operates in the following manner. Responsive to a signal having a selected duration from the associated trigger detect coupled to each of the input terminals of state machine 7⊘, each variable digital delay produces a signal on its output terminal subsequent to the expiration of a time period as determined by the value previously loaded into each variable digital delay individually by state machine control 19⊘. It will be understood in this regard that the time period associated with variable digital delay 1⊘⊘ corresponds to the approximate amount of time between the occurrence of the event detected by trigger detect 2⊘ and a final event of the sequence of serial events, as more fully discussed hereafter. It should consequently be observed that responsive to detection of a trigger criteria in monitored signal 1⊘ and the corresponding generation of an indication thereby of a selected duration by trigger detect 2⊘, variable digital delay 1⊘⊘ functions to delay said indication by an amount of time approximately equal to the time between the occurrence of the detected event and the final event in the sequence of events. Logic 15⊘ in response to the signal from variable digital delay 1⊘⊘ operates to produce a signal in accordance with the pre-selected logic operation performed thereby, as discussed more fully hereafter. In a similar manner, responsive to a signal having a selected duration from trigger detect 3⊘ coupled to terminal 74, variable digital delay 11⊘ produces a signal on terminal 114 subsequent to the expiration of a time period as determined by the value previously loaded into variable digital delay 11⊘ by state machine control 19⊘. It will be understood in this regard that the time period associated with variable digital delay 11⊘ corresponds to the approximate amount of time between the occurrence of the event detected by trigger detect 3⊘ and the final event of the sequence of serial events, as more fully discussed hereafter. As was the case with variable digital delay 1⊘⊘, it should be observed that responsive to detection of a trigger criteria in monitored signal 1⊘ and the corresponding generation of an indication thereby of a selected duration by trigger detect 3⊘, variable digital delay 11⊘ functions to delay said indication by an amount of time approximately equal to the time betwen the occurrence of the detected event and a final event in the sequence of events. It should be particularly observed that the foregoing discussed signals produced by trigger detect 2⊘ and 3⊘ appear on terminals 1⊘4 and 114 of variable digital delays 1⊘⊘ and 11⊘, respectively, at approximately the same time. Consequently, the signals coupled to logic 15⊘ and 16⊘ occur at approximately the same time. It should be understood that as each of these signals has a selected duration, timing differences between the occurrence of the events detected by trigger detect 2⊘ and 3⊘ will not preclude detection of both events by logic 15⊘ and 16⊘, provided the duration of the indications produced by the respective trigger detect devices is greater than any timing differences, as more fully discussed hereafter. Logic 16⊘ in response to the signal from variable digital delay 11⊘ and the signal from logic 15⊘ operates to produce a signal in accordance with the preselected logic operation performed thereby, as discussed more fully hereafter. Further combinations of variable digital delays and logic devices operate in a similar cascaded fashion, with the ultimate output from state machine 7⊘ appearing on terminal 186 of logic 18⊘. It should be observed with respect to the functional implementation of state machine 7⊘ illustrated in Figure 2 that the operation of each of the variable digital delays is contingent only upon the generation of a signal by the trigger detect device coupled thereto. Figure 3 illustrates a functional implementation of an alternate embodiment of state machine 7⊘. Referring now to Figure 3, variable digital delays 2⊘⊘, 21⊘ and 23⊘ have input terminals 2⊘2, 212 and 232, output terminals 2⊘4, 214 and 234, and control terminals 2⊘6, 216 and 236, respectively. Variable digital delays 2⊘⊘, 21⊘ and 23⊘ operate in an identical fashion to variable digital delay 1⊘⊘ previously discussed with respect to Figure 2. Logic 26⊘ and 28⊘ have input terminals 262, 264, and 282, 284, respectively, and output terminals 266 and 286, respectively. Logic 26⊘ and 28⊘ function to produce a signal on output terminals 266 and 286, respectively, responsive to signals coupled to their respective input terminals according to preselected logic operation, as more fully discussed hereafter. State machine control 29⊘ functions in a similar manner to state machine control 19⊘ previously discussed with respect to Figure 2. The foregoing described apparatus is configured in the following way. Output terminal 26 of trigger detect 2⊘ (Figure 1) is coupled to terminal 2⊘2 of variable digital delay 2⊘⊘. Output terminal 2⊘4 of variable digital delay 2⊘⊘ is coupled to terminal 262 of logic 26⊘. Output terminal 36 of trigger detect 3⊘ (Figure 1) is coupled to terminal 264 of logic 26⊘. Output terminal 266 of logic 26⊘ is coupled to terminal 212 of variable digital delay 21⊘. As was the case previously discussed with respect to Figure 2, the number of variable digital delay devices employed in the functional apparatus of Figure 3 is determined by the number of trigger detect devices employed in a particular application; there being an equal number of variable digital delay devices and trigger detect devices. The output signal from a subsequent trigger detect device is coupled to the functional apparatus of Figure 3 in a similar manner as was discussed with respect to trigger detect device 3⊘, logic 26⊘ and variable digital delay 21⊘, i.e., the output from a trigger detect device is coupled to one input of the associated logic device, the second input of the logic device being obtained from the output of the preceding variable digital delay, and the output of the logic device being coupled to the input terminal of the associated variable digital delay. In an application employing three trigger detect devices, e.g., trigger detect 2⊘, 3⊘ and 5⊘ (Figure 1), output terminal 214 of variable digital delay 21⊘ would be coupled to terminal 282 of logic 28⊘. Output terminal 56 from trigger detect device 5⊘ is coupled to terminal 284 of logic 28⊘, and output terminal 286 of logic 28⊘ is coupled to terminal 232 of variable digital delay 23⊘. The output of state machine 7⊘ is obtained from terminal 234 of variable digital delay 23⊘. The foregoing described apparatus of Figure 3 operates in the following manner. Responsive to a signal having a selected duration from trigger detect 2⊘ being coupled to terminal 2⊘2 thereof, variable digital delay 2⊘⊘ operates to produce said signal on terminal 2⊘4 thereof subsequent to the expiration of a time period as determined by the value previously loaded into variable digital delay 2⊘⊘ by state machine control 29⊘. It will be understood in this regard that the time period associated with variable digital delay 2⊘⊘ corresponds to the approximate amount of time between the event detected by trigger detect 2⊘ and the event to be detected by trigger detect 3⊘, as will be more fully discussed hereafter. It should be observed that responsive to the detection of a trigger criteria in monitored signal 1⊘ and the corresponding generation of an indication thereof of a selected duration by trigger detect 2⊘, variable digital delay 2⊘⊘ functions to delay said indication by an amount of time approximately equal to the time between the event detected by trigger detect 2⊘ and the following event, i.e., the event to be detected by trigger detect 3⊘. It is consequently observed that the indications from trigger detect 2⊘ and 3⊘ will appear on terminals 262 and 264 of logic 26⊘ at approximately the same time. It should be further observed that as the indications produced by trigger detect 2⊘ and 3⊘ are of selected durations, timing differences between the respective events detected by trigger detect 2⊘ and 3⊘ will not preclude their simultaneous detection by logic 26⊘, provided the duration of the indications produced by the respective trigger detect devices is greater than any timing differences, as more fully discussed hereafter. Logic 26⊘ operates to combine the signal produced by variable digital delay 2⊘⊘ with a signal produced by trigger detect 3⊘ according to a predetermined logic operation, coupling the signal produced in accordance therewith to terminal 212 of variable digital delay 21⊘. It will be understood in this regard that the time period associated with variable digital delay 21⊘ corresponds to the approximate amount of time between the event detected by trigger detect 3⊘ and the event to be detected by trigger detect 5⊘, as will be more fully discussed hereafter. The remaining apparatus operates in a similar manner. It should be observed with respect to the functional implementation of state machine 7⊘ illustrated in Figure 3, that the operation of each variable digital delay, except for the first one, is contingent not only upon the generation of a signal by the trigger detect device associated therewith, but also the occurrence of a signal from a previous variable digital delay. The delay periods determined by the variable digital delay devices of Figure 2 are absolute, i.e., the time periods are measured in a reverse sense from a final event, whereas those determined by the variable digital delay devices of Figure 3 are relative, i.e., the time periods are measured between sequential events. The functional implementation of state machine 7⊘ by the apparatus of Figure 2 is consequently of a more general nature than the apparatus of Figure 3. While trigger detect 2⊘, 3⊘ or 5⊘ may each be implemented in any of a wide variety of ways, Figure 4 illustrates apparatus for one possible implementation of trigger detect apparatus. Referring now to Figure 4, trigger criteria control 6⊘ (Figure 1) operates to couple a pre-selected numeric value corresponding to the selected period previously discussed with respect to trigger detect 2⊘, 3⊘ and 5⊘, to variable digital delay 36⊘ by placing a signal representative thereof on terminal 362, and a corresponding load command signal on terminal 364. Variable digital delay 36⊘ of Figure 4 operates in an identical manner as variable digital delay 1⊘⊘ previously discussed with respect to Figure 2. A signal having a level representative of a desired trigger level is coupled from trigger criteria control 6⊘ to terminal 3⊘2 of comparator 3⊘⊘ which functions to continuously compare that signal level to the signal level of the signal coupled to terminal 3⊘4, i.e., monitored signal 1⊘, with the signal having a level representative of the desired trigger level. When the level of monitored signal 1⊘ exceeds the desired trigger level, comparator 3⊘⊘ functions to produce an indication thereof on output terminal 3⊘6. For a positive slope setting, the signal on input terminal 314 is a logic zero (low), thus the signal on output terminal 316 is the same as the signal on input terminal 312. For a negative slope setting, the signal coupled to input terminal 314 is a logic one (high), resulting in the signal from terminal 316 being the inverse (complement) of the signal coupled to terminal 312. Capacitor 32⊘ and resistor 322 comprise a differentiation circuit. When a low-to-high transition occurs on the signal from terminal 316, a positive pulse is produced. When a high-to-low transition occurs on the signal from terminal 316, diode 324 will short it to ground. Thus the S-input terminal of R-S flip-flop 33⊘ will see a positive pulse only when monitored signal 1⊘ crosses a selected threshold in the desired direction (slope). The pulse coupled to the S-input terminal of R-S flip-flop 33⊘ will operate to produce a logic one state on the Q-output terminal thereof. On the occurrence of the next pulse from master clock 38⊘, the logic one state coupled from the Q-terminal of R-S flip-flop 33⊘ operates to place a logic one on the Q-output terminal, and a logic zero state on the Q' output terminal of T flip-flop 34⊘. The logic one on the Q-terminal of T flip-flop 34⊘ when coupled to the R-terminal of R-S flip-flop 33⊘ operates to place R-S flip-flop 33⊘ in a reset state. The logic zero state produced thereby on the Q' output terminal of T flip-flop 34⊘ is coupled to terminal 368 of variable digital delay 36⊘, and will appear on terminal 37⊘ thereof subsequent to the selected time period previously coupled to variable digital delay 36⊘. Upon the occurrence of the logic zero on terminal 37⊘, and the subsequent coupling thereof to terminal 346, T flip-flop 34⊘ will be placed in a clear or reset state, i.e., the Q output terminal will return to a logic zero state. It is consequently observed that the signal produced on the Q terminal of T flip-flop 34⊘ is a pulse having a duration determined by the time period previously coupled to variable digital delay 36⊘. Switch 382 provides for the selection of the output signal of the apparatus of Figure 4 to originate from either terminal 316 or from the Q terminal of T flip-flop 34⊘, as more fully discussed hereafter. From the foregoing it is observed that the apparatus of Figure 4 operates to produce an output signal on terminal 316 of exclusive-OR gate 31⊘ responsive to monitored signal 1⊘ becoming equal to a level corresponding to the level coupled to terminal 3⊘2 of comparator 3⊘⊘, with a slope corresponding to slope information coupled to terminal 314 of exclusive-OR gate 31⊘. In addition, a second output signal produced on the Q-output terminal of T flip-flop 34⊘ has a duration determined by the number previously loaded into variable digital delay 36⊘. It is consequently observed that the apparatus of Figure 4 produces two indications responsive to monitored signal 1⊘ satisfying selected level and slope criteria, i.e., the signal produced on terminal 316 of exclusive-OR gate 31⊘, and the signal produced on the Q terminal of T flip-flop 34⊘. It will be observed that the signal produced on terminal 316 occurs when the level of monitored signal 1⊘ exceeds the preselected level, and remains as long as the level of monitored signal 1⊘ is greater than the selected level. However, the signal produced on the Q terminal of flip-flop 34⊘ has a selected duration corresponding to information previously coupled to variable digital delay 36⊘. The duration of the signal so produced is particularly significant, as it provides a continuous indication of the occurrence of the satisfaction of the associated trigger condition over the period thereof, functioning in state machine 7⊘, subsequent to an associated delay, to preclude timing differences between selected events from preventing detection of a sequence of events. While the variable digital delay devices previously discussed with respect to Figures 2, 3 and 4 may be implemented by delay devices, e.g., delay lines, as above discussed, counters may also be employed, as would be apparent to one of ordinary skill in the art. While the foregoing has illustrated apparatus for implementation of a trigger detect device, it is to be understood that such discussion was for illustrative purposes, and is not to be interpreted as limiting the invention herein to the trigger detect apparatus or trigger criteria discussed with respect to Figure 4. Many other types of trigger detect devices may be used in a similar manner, and would be apparent to one of ordinary skill in the art. Figure 5 illustrates a preferred embodiment for the logic devices of Figure 2 and 3, e.g., logic 15⊘, 16⊘, 18⊘, 26⊘ and 28⊘. It is to be understood, however, that such logic devices may be implemented in a wide variety of ways in accordance with preselected logic operations. Consequently, the apparatus of Figure 5 is not to be interpreted as limiting the present invention thereto. Referring to Figure 5, it is understood that terminal 424 of switch 42⊘ corresponds to terminals 162 and 182 of logic 16⊘ and 18⊘, respectively (Figure 2), and to terminals 262 and 282 of logic 26⊘ and 28⊘, respectively (Figure 3). In a similar manner, terminals 4⊘2 and 4⊘8 of inverter 4⊘⊘ and buffer 4⊘6, respectively, collectively correspond to terminals 154, 164 and 184 of logic 15⊘, 16⊘ and 18⊘ (Figure 2), and to terminals 264 and 284 of logic 26⊘ and 28⊘, respectively (Figure 3). Terminal 486 of switch 48⊘ corresponds to terminals 156, 166 and 186 of logic 15⊘, 16⊘ and 18⊘, respectively (Figure 2), and to terminals 266 and 286 of logic 26⊘ and 28⊘ (Figure 3). Switches 412, 42⊘, 45⊘ and 48⊘ provide flexibility in configuring the apparatus of Figure 5 to perform selected logic operations. In particular, with switch 42⊘ configured in a manner to couple terminal 426 to terminal 422 thereof, switch 45⊘ would typically be configured in a manner to couple terminal 456 to terminal 452 thereof. Switches 412 and 48⊘ may be configured so the apparatus of Figure 5 provides a logical inversion operation with respect to the signal coupled to terminals 4⊘2 and 4⊘8 of inverter 4⊘⊘ and buffer 4⊘6, respectively. If, however, switch 42⊘ is configured in a manner to couple terminal 426 to terminal 424 thereof, switch 45⊘ may be configured to select either the logical AND or logical OR operation of a signal coupled to terminal 424 of switch 42⊘, and either the inverted or non-inverted signal coupled to input terminals 4⊘2 and 4⊘8 of inverter 4⊘⊘ and buffer 4⊘6, according to a selection made by the configuration of switch 412. An inverted or non-inverted signal corresponding to the signal resulting from the selected configuration of switch 45⊘ may be selected by switch 48⊘. The functions performed by switches 412, 42⊘, 45⊘ and 48⊘ may be implemented by either manual switches or electronically configurable switches, as would be apparent to one of ordinary skill in the art. We will now describe the operation of the apparatus of the present invention in detecting the occurrence of a series of selected serial events in a single signal, e.g., a selected condition which is preceded by two pre-selected conditions, as broadly illustrated in Figure 6. Figure 6 illustrates a voltage waveform of monitored signal 1⊘ (Figure 1), having a sequence of selected serial events which are desired to be detected. The final event in the sequence of events has a voltage level of L E with a negative slope at a time of T E . The final event is preceded in time by two prior events: a first event wherein the monitored signal 1⊘ has a voltage level of L₁ with a positive slope occurring by an approximate amount of time t₁ prior to the final desired event; a second event wherein monitored signal 1⊘ has a voltage level of L₂ with a positive slope occurring by an approximate amount of time t₂ prior to the final event. Three trigger detect devices will be employed. Each trigger detect device may be implemented by the apparatus previously discussed with respect to Figure 4. Switch 382 is configured to select the signal from the Q terminal of T flip-flop 34⊘ as an output signal for the apparatus of Figure 2 for trigger detect devices 2⊘ and 3⊘. Switch 382 is configured to select the signal from terminal 316 as an output signal for the implementation of trigger detect device 5⊘. In addition, state machine 7⊘ may be implemented according to the functional apparatus previously discussed with respect to Figure 2. In particular, state machine 7⊘ may be comprised of variable digital delay 1⊘⊘, 11⊘ and 13⊘, with logic 15⊘, 16⊘ and 18⊘ (Figure 2). For this discussion, switches 412, 42⊘, 45⊘ and 48⊘ (Figure 5) for the apparatus of logic 15⊘ are configured as follows: switch 412 is configured with terminal 418 coupled to terminal 416, thereby connecting the output of buffer 4⊘6 to terminals 434 and 444 of AND gate 43⊘ and OR gate 44⊘, respectively; switch 42⊘ is configured with terminal 426 coupled to terminal 422, thereby coupling ground potential, i.e., a logic zero, to terminal 432 and 442 of AND gate 43⊘ and OR gate 44⊘, respectively; switch 45⊘ is configured with terminal 456 coupled to terminal 452, thereby connecting the output of OR gate 44⊘ to terminal 472 of buffer 47⊘ and terminal 462 of inverter 46⊘; and switch 48⊘ is configured with terminal 486 coupled to terminal 484 thereof. Switches 412, 42⊘, 45⊘ and 48⊘ assume a different configuration for the apparatus of logic 16⊘ and 18⊘, and are configured as follows: switch 412 is configured with terminal 418 coupled to terminal 416, thereby connecting the output of buffer 4⊘6 to terminals 434 and 444 of AND gate 43⊘ and OR gate 44⊘, respectively; switch 42⊘ is configured with terminal 426 coupled terminal 424, thereby coupling the first input signal to terminals 432 and 442 of AND gate 43⊘ and OR gate 44⊘, respectively; switch 45⊘ is configured with terminal 456 coupled to terminal 454, thereby connecting the output of AND gate 43⊘ to terminals 472 of buffer 47⊘ and terminal 462 of inverter 46⊘; and switch 48⊘ is configured with terminal 486 coupled to terminal 484. Referring first to Figure 1, trigger criteria control 6⊘ first couples trigger information to terminals 22, 32 and 52, respectively of trigger detect 2⊘, 3⊘ and 5⊘. Referring to Figure 4, trigger criteria control 6⊘ will couple information representative of Level L₁ to terminal 3⊘2 of comparator 3⊘⊘, a signal indicating detection of a positive slope to terminal 314, a signal corresponding to time period t uncertainty to terminal 362 of variable digital delay 36⊘ and a corresponding load signal to terminal 364 of the apparatus which implements trigger detect 2⊘. Trigger criteria control 6⊘ will also couple information representative of level L₂ to terminal 3⊘2 of comparator 3⊘⊘, a signal indicating detection of a positive slope at terminal 314, a signal corresponding to time period of t uncertainty to terminal 362 of variable digital delay 36⊘ and a corresponding load signal to terminal 364 of the apparatus which implements trigger detect 3⊘. Trigger criteria control 6⊘ will also couple information representative of level L E to terminal 3⊘2 of comparator 3⊘⊘, a signal indicating detection of a negative slope at terminal 314, a signal corresponding to a time period of t uncertainty to terminal 362 of variable digital delay 36⊘ and a corresponding load signal to terminal 364 of the apparatus which implements trigger detect 5⊘. Referring to Figure 2, state machine control 19⊘ will couple a signal representative of time period t₁ to terminal 1⊘6 of variable digital delay 1⊘⊘. In a similar fashion, state machine control 19⊘ will couple a signal representative of time period t₂ to terminal 116 of variable digital delay 11⊘, and a time period of zero to terminal 136 of variable digital delay 13⊘ . Thereafter, when the level of a monitored signal 1⊘ equals level L₁ with a positive slope, trigger detect 2⊘ (Figure 1) will produce a signal indicating same on terminal 26 having a selected period, i.e., a period of t uncertainty . In particular, the Q-output terminal of T flip-flop 34⊘ (Figure 4) will assume a logic one state for a time period of t uncertainty . The signal so produced by trigger detect 2⊘ in turn operates to generate at the output of variable digital delay 1⊘⊘ (Figure 2) after a time period of t₁, a pulse of duration t uncertainty . The output of variable digital delay 1⊘⊘ is thereafter coupled through logic 15⊘, i.e., through buffer 4⊘6, OR-Gate 44⊘ and buffer 47⊘, and appears at output terminal 156 of logic 15⊘. In a similar fashion, when the level of monitored signal 1⊘ equals level L₂ with a positive slope, trigger detect 3⊘ (Figure 1) will produce a signal indicating same on terminal 36 having a selected period, i.e., a period of t uncertainty . In particular, the Q-output terminal of T flip-flop (Figure 4) will assume a logic one state for a time period of t uncertainty . The signal so produced by trigger detect 3⊘ is in turn coupled to variable digital delay 11⊘ (Figure 2), and appears at terminal 114 thereof subsequent to a period of t₂. The output of variable digital delay 11⊘ is thereafter coupled to logic 16⊘. In particular, the output of variable digital delay 11⊘ is coupled through buffer 4⊘6 to terminal 434 of AND gate 43⊘. As the output from logic 15⊘ appears at terminal 432 of AND gate 43⊘, the output from terminal 436 of AND gate 43⊘ is at a logic one, and is coupled through buffer 47⊘ to terminal 474 thereof, i.e., to terminal 166 of logic 16⊘. When the level of monitored signal 1⊘ equals level L E With a negative slope, trigger detect 5⊘ will produce a signal indicating same on terminal 56 (Figure 1) having a selected period, i.e. a period of t uncertainty . In particular, the Q-output terminal of T flip-flop 34⊘ (Figure 4) will assume a logic one state for a time period of t uncertainty . The signal so produced by trigger detect 5⊘ in turn is delayed by a time period of zero by variable digital delay 13⊘ (Figure 2). The output of variable digital delay 13⊘ is thereafter coupled to logic 18⊘. In particular, the output of variable digital delay 13⊘ is coupled through buffer 4⊘6 (Figure 5) to terminal 434 of AND gate 43⊘. As the output from logic 16⊘ appears at terminal 432 of AND gate 43⊘, the output from terminal 436 of AND gate 43⊘ is at a logic one, and is coupled through buffer 47⊘ to terminal 474 thereof, i.e., to terminal 78 of state machine 7⊘, thereby producing the trigger signal for state machine 7⊘. It should be particularly observed with respect to the foregoing discussion, that as a result of the delay interposed by the operation of variable digital delay 1⊘⊘ and 11⊘, the indications produced by the trigger detect devices are coupled to the associated logic devices, i.e., logic 15⊘, 16⊘ and 18⊘ at approximately the same time. In addition, as each of the indications produced by the respective trigger detect devices has a period of t uncertainty , timing differences between the respective events will not preclude detection of the serial sequence of events, provided the time at which each of said events occurs does not vary from its expected time by more than t uncertainty /2. While the foregoing discussion has assumed that an identical time period of t uncertainty is coupled to each of the variable digital delays 36⊘ of trigger detect devices 2⊘, 3⊘ and 5⊘, it should be understood that differing time periods could likewise have been employed, the duration of the selected time periods serving as tolerance periods during the time period in which the desired final trigger event may occur. While the foregoing has described the operation of the functional apparatus of Figure 1 with state machine 7⊘ implemented according to the functional apparatus of Figure 2, it is to be understood that state machine 7⊘ could likewise be implemented according to the functional apparatus previously discussed with respect to Figure 3. It will be understood in this regard that the time periods coupled to variable digital delays 2⊘⊘, 21⊘ and 23⊘ of Figure 3 would correspond to the approximate time periods occurring between sequential events in the series of events which are desired to be detected, as previously discussed. The foregoing described apparatus of Figure 1 would then operate in a similar manner as previously discussed. It will be apparent to one of ordinary skill in the art that many modifications or alterations may be made to the method and apparatus described herein. All of such variations are to be considered to be within the scope of the inventive concept herein, and are limited only by the scope of the following claims.

Claims: Apparatus for detecting the occurrence of a plurality of selected sequential events in a single monitored signal (10), and producing a trigger signal (78) responsive to the occurrence thereof, characterized by trigger criteria means (60) for defining the plurality of selected events in the monitored signal (10); a plurality of event detection means (20,30,50), each coupled to said trigger criteria means (60) and to receive the monitored signal (10), for producing an indication for a selected period of time thereafter in response to detection of one of said plurality of selected events in the monitored signal (10); and trigger generation means (70), coupled to the plurality of event detection means (20,30,50), for delaying the indications by selected differing periods, and combining the delayed indications according to a preselected manner to produce the trigger signal (78). Apparatus as in claim 1, characterized in that the means for delaying the indications by selected differing periods in said trigger generation means (70) are delay lines (100,110,130;200,210,230). Apparatus as in claim 1, characterized in that the means for delaying the indications by selected differing periods in said trigger generation means (70) are digital counters. Apparatus as in claim 1, characterized in that each of said plurality of event detection means (20,30,50) comprises means (330,340,360) for producing an indication for a selected period of time thereafter responsive to the level and slope of the monitored signal becoming equal to a selected level and slope. Apparatus as in claim 4, characterized in that said means for producing an indication for a selected period of time is a delay line (360). Apparatus as in claim 4, characterized in that said means for producing an indication for a selected period of time is a digital counter. Apparatus as in claim 1, characterized in that said trigger generation means (70) further comprises means (420,430,440,450) for producing an indication responsive to the selective combining of indications from said event detection means according to selective logical AND and OR operations. Apparatus as in claim 7, characterized by means (400,412,460,480) for selectively performing a logical inversion operation on an indication from an event detection means. Apparatus as in claim 7, characterized by means (400,412,460,480) for selectively performing a logical inversion operation on the indication produced by said trigger generation means. A method for detecting the occurrence of a plurality of selected sequential events in a single monitored signal (10), and producing a trigger signal (78) responsive to the occurrence thereof, characterized by the steps of: defining the plurality of selected events in the monitored signal (10); monitoring the monitored signal (10) for each of the plurality of selected events, and producing an indication for a selected period of time thereafter responsive to the occurrence of each of the selected events; and producing the trigger signal (78) responsive to the indications produced by the occurrence of the selected events, delayed by selected differing periods of time, and subsequently combined according to a selected logical operation.

Inventors: THONG, TRAN
Applicants: TEKTRONIX, INC.
Application year: 1987
Main classification: G01R13
IPC codes: G01R13, G01R19, G06F11