Video memory control device

Abstract: A video memory control device for a two-field video signal that is buffered in a memory (6) having capacity for one field. The phase of the writing to and reading from the memory (6) may be such that the fields are being swapped on output. To display the correct sequence without losing any fields, the reading address for one field is delayed by lH (one horizontal scanning line period) or the reading address for the other field is advanced by lH dependent on the detected phase. A similar technique may alternatively be applied to the writing side.

Description: This invention relates to correction of the swapping of fields in a field memory type synchronizer. In many video systems, video information is sequentially transmitted in two fields, here called odd-numbered (ODD or O) fields and even-numbered (EVEN or E) fields. Each field contains a large number of horizontal lines of data which are sequentially scanned across and then down a screen. When the ODD fields has been completed, an EVEN field is processed similarly. However, the horizontal scan lines for the EVEN fields are displayed vertically between the horizontal scan lines in a process called interlacing. Because of cost, it is preferable to employ a 1-field memory small in capacity for a synchronizer which is used for synchronous conversion of video signals. In the 1-field memory system, owing to the phase relation between the input video signal and the reference synchronization of the synchronizer, the odd-numbered (ODD or O) field may be read as an even-numbered (EVEN or E) field, or vice versa. That is, the timing of the reading of the field memory is offset in time from its writing to the extent that the reading of a location in the field memory for one type of field occurs when that location actually contains the other type of field. In this case, the odd-numbered fields and the even-numbered fields are inverted in vertical position. This can be corrected with only a slight offset in screen image by time delaying by one horizontal scanning line period (hereinafter referred to as "1H") the fields which have become the odd-numbered fields by the swapping of fields. This will become more apparent from Figure 1. Part (a) of Figure 1 shows the correctly oriented lines formed by input signals, part (b) shows the case where the fields are simply swapped with each other, and part (c) the case where, after swapping, the odd-numbered fields are delayed by 1H. A conventional field memory synchronizer of this type is as shown in Figure 2. The operation of the field memory synchronizer will be described with reference to Figure 2. In Figure 2, a video signal applied to a video signal input terminal 1 is converted into a digital signal by an A/D (analog-to-digital) converter 2 with the aid of a clock pulse generated by a writing clock pulse generating section 3. The digital signal is written in a field memory 6. On the other hand, with the aid of the writing clock pulse, a writing address generating section 4 outputs a writing address signal, which is applied through a memory control section 5 to the field memory 6 to control the field memory 6. On the read-out side, a reading clock pulse generating section 8 produces a reading clock pulse with the aid of a reference signal applied to a reference signal input terminal 7. The clock pulse is applied to a D/A (digital-to-analog) converter 13 and a reading address generating section 9 so that the reading address generating section 9 produces a reading address signal. Similarly as in the case of the writing address signal, the reading address signal is applied through the memory control section 5 to the field memory 6 so that an address from which data is to be read out of the field memory 6 is specified. A field swap detecting section 10 receives signals based on the writing address and the reading address and outputs a signal to trip the armature of a switch 12 over to its contact b when, during field swapping, the odd-numbered field are read. As a result, when the odd-numbered fields are read after the swapping of the fields, the digital signal read out of the memory 6 is applied to a 1H delay line 11 so that the swapped fields are rearranged. The output signal of the 1H delay line 11 is applied to the D/A converter 13, so that it is provided, as an analog signal, at the output terminal 14. The conventional field memory synchronizer is being designed as described above and therefore needs the 1H delay line 11 and the switch 12. In order to perform the 1H delay in a digital mode as shown in Figure 2, the 1H delay line 11 may be made up of shift registers. However, in this case, a number of shift registers must be used because one clock pulse period is much shorter than one horizontal synchronizing period. If the number of bits quantized is represented by n , then n switch circuits are required because the switch 12 must be provided for each of the bits. Thus, the conventional field memory synchronizer is disadvantageous in that the number of circuits is relatively large and accordingly the manufacturing cost is also relatively high. GB-A-2037530 discloses a circuit for processing reproduced PAL television signals in which a reference field is compared with a playback field for the chrominance and luminance signals. Accordingly, an object of this invention is to eliminate the above-described difficulties accompanying a conventional field memory synchronizer. According to a first aspect of the present invention there is provided a video memory control device for the synchronous conversion of video signals transmitted in a first field and a second field, each field comprising a plurality of lines of 1H in duration, the lines being intended for display in a correct sequence of a line of the first field being followed by a line of the second field, the device comprising: a digital memory having a capacity corresponding to one of the fields; writing means for writing received video signals into the memory according to a writing address; reading means for reading data from the memory according to a reading address; sequential addressing means for sequentially providing both the writing address and the reading address; and, address processing means for correcting the sequential addressing means; characterised by: address processing means including at least two of: first means for advancing the writing address by 1H, second means for delaying the writing address by 1H, third means for delaying the reading address by 1H, and fourth means for advancing the reading address by 1H; and by: means for selecting one of said two means in the address processing means according to a phase relation between first data indicating whether the writing address is for the first field or the second field and second data indicating whether the reading address is for the first field or the second field, whereby the reading or writing addresses are generated in a corrected sequence, allowing a display in the correct sequence. According to a second aspect of the present invention, there is provided a method for controlling a video memory for the synchronous conversion of video signals transmitted in a first field and a second field, each field comprising a plurality of lines of 1H in duration, the lines being intended for display in a correct sequence of a line of the first field being followed by a line of the second field, the method comprising the steps of: writing received video signals into a memory having a capacity corresponding to one of the fields according to a writing address; reading data from the memory according to a reading address; sequentially providing both the writing address and the reading address; correcting the sequentially provided addresses and including at least two sub-steps from: a first sub-step of advancing the writing address by 1H, a second-step of delaying the writing address by 1H, a third sub-step of delaying the reading address by 1H, and a fourth sub-step of advancing the reading address by 1H; and, selecting one of said two sub-steps according to a phase relation between first data indicating whether the writing address is for the first field or the second field and second data indicating whether the reading address is for the first field or the second field, whereby the reading or writing addresses are generated in a corrected sequence, allowing a display in the correct sequence. In the accompanying drawings: Figure 1 is an explanatory diagram showing the vertical positions of scanning lines in the case where fields are swapped; Figure 2 is a block diagram showing the arrangement of a conventional field memory synchronizer; Figures 3a and 3b are timing charts for a description of the difficulties which are caused when addresses are processed; Figure 4 is a block diagram showing one example of a video memory control device according to this invention; and, Figures 5a and 5b are timing charts for a description of the operation of the control device shown in Figure 4. This invention will be described with reference to the case where, for simplification in description, the sampling frequency is an integer multiple of f H (for instance 4 f SC = 910 f H , the horizontal synchronizing frequency f H is the inverse of 1H), and the writing address and the reading address each consist of horizontal and vertical addresses H-ADD and V-ADD. The horizontal addresses H-ADD divide one line of a picture into equal parts. The vertical addresses V-ADD correspond to sequential scanning lines. If, when the fields are being swapped, the top vertical address V-ADD of each of the odd-numbered fields is held for 1H so that the addresses V-ADD are read out with a delay time of 1H, then the pictures of the odd-numbered fields are shifted by 1H. This is equivalent to the application of the addresses to the 1H delay line. However, in the synchronizer, sometimes the phase relation between the input video signal and the reference synchronization is as shown in Figure 3a. In Figure 3a, reference character "W. Field" designates the variation of field based on the reference synchronization on the writing side, and "R. Field" represents the variation of field based on the reference synchronization on the reading side. When, as shown in Figure 3a, "R. Field" precedes "W. Field" and the difference therebetween is within 1H, the content of E′ n of reading is O n of writing, and the content of O′ n+1 of reading is E n of writing. That is, swapping of the fields is occuring. Therefore, if, to compensate in reading an odd-numbered field, R. V-ADD 1 is delayed by 1H as shown for the odd-numbered field, then for instance in reading V-ADD 1, the content of the V-ADD 1 read is O n+1 because E n has been rewritten as O n+1 in the field memory during the 1H delay. That is, in the case of the figure, since the fields are being swapped, the correction is required. However, if in reading an odd-numbered field, the address is delayed by 1H, then the data of even-numbered fields such as E n are lost, while the data of odd-numbered fields are each read out over both the even and odd fields. Therefore in case of Figure 3a, the above-described correction cannot be performed. When the fields are being swapped, the correction may also be made by a method also in which the pictures of the even-numbered fields are advanced by 1H. This can be realized by adding an address corresponding to 1H to the top address V-ADD of each of the even-numbered fields. However, this method cannot be applied to the case shown in Figure 3b. In Figure 3b, similarly as in Figure 3a, by processing V-ADD the data read for E′ n becomes the data written for O n and E n , and the data of odd-numbered fields are lost. As is apparent from the above description, the method of advancing the even-numbered fields by 1H should be employed for the case where the phase relation is as shown in Figure 3a, and the method of delaying the odd-numbered fields by 1H should be employed for the case where the phase relation is as shown in Figure 3b. In these cases, none of the data is lost during swapping correction. Thus, it is essential for the video memory control device of the invention that a plurality of address processing means are suitably switched in operation. One embodiment of this invention will be described with reference to Figure 4, in which the circuit elements corresponding functionally to those which have been already described with reference to Figure 2 are therefore designated by the same reference numerals or characters, and the preceding description is applicable thereto. However, it should be noted that the writing address generating section 4 in Figure 2 is divided into a writing H-address generating section 4a and a writing V-address generating section 4b in Figure 4. Similarly the reading address generating section 9 in Figure 2 is divided into a reading H-address generating section 9a and a reading V-address generating section 9b in Figure 4. Further in Figure 4, a writing field discriminating section 101 produces a pulse whose polarity is changed according to whether the field of an input video signal is an odd-numbered one or an even-numbered one. A reading field discriminating section 102 discriminates reading fields according to the reference synchronizing signal. A field swap detecting section 103 detects the swapping of fields according to a writing field discrimination signal and a reading field discrimination signal. A swap correcting section 104 controls the reading V-address generating section 9b according to the output of the field swap detecting section 103. The field swap detecting section 103 operates in the same manner as the field swap detecting section 10 in Figure 2. Therefore, it can be considered that, in the embodiment, the swap correction section 104 replaces the 1H delay line 11 and the switch 12 of the conventional field memory synchronizer shown in Figure 2. The operation of the video memory control device of the invention shown in Figure 4 will now be described in detail. Each of the four address generating sections 4a, 4b, 9a and 9b is made up of a counter. For instance on the writing side, the clock pulse inputted from the writing clock pulse generating section 3, having a frequency nf H ′, an integer multiple of the horizontal synchronizing frequency f H and being synchronous in phase with the horizontal synchronizing signal, is frequency-divided in the horizontal address generating section 4a, as a result of which the H-address is provided. The 1H period pulse outputted by the H-address generating section 4 is applied, as a clock pulse, to the V-address generating section 4b, so that the V-address is produced. On the other hand, on the reading side, in order to control the V-address when the fields are being swapped, the 1H period pulse e outputted by the H-address counter 9a is applied to the correcting circuit 104, where a clock pulse corresponding to 1H is added thereto or subtracted therefrom, as a result of which a pulse f is outputted by the correcting circuit 104. As was described above, with the aid of the outputs a and b of the writing field discriminating section 101 and the reading field discriminating section 102, the field swap detecting section 103 detects the swapping of fields. The field swap detecting section 103 outputs two pulses c and d . More specifically, when the fields are being swapped, and the even-numbered fields should be advanced by 1H, the pulse c is outputted as an effective pulse; and, when the odd-numbered fields should be delayed by 1H, the pulse d is provided as an effective pulse. When the swapping of the fields is not detected, neither of the pulses c and d is effective. The waveforms of the signals a through f in Figure 4 are as shown in Figures 5a and 5b. Figures 5a and 5b are for the cases which are the same in phase relation as the cases shown in Figures 3a and 3b. The signals a and b correspond respectively to the "W. Field" pulse and the "R. Field" pulse shown in both Figures 3a and 3b. In the embodiment, the field swap detection section 103 detects the fact that, as shown in Figure 5a, the signal a rises within 1H after the rise of the signal b , and only in this case the signal c having a pulse width of H/10 (up to H/2) is produced in synchronization with the rise of the signal b . The periodic nature of the signals allows the signal c to be produced before the rise of the signal a . The signal c is added to the 1H period clock pulse e to form the clock pulse f which is applied to the counter 9b. As a result, the V-address is shifted so that the even-numbered field is advanced by 1H. In the case other than in Figure 5a, the field swap detection section 103 detects the fact that, as shown in Figure 5b, the signal b falls with the signal a at the "H" (high) level, and the field swap detection section 103 outputs the pulse d (1H in pulse width) in response to the fall of the signal b . For this period, the clock pulse e is effectively blocked to thus form the clock pulse f which does not have a clock pulse occuring for the period of 1H as shown in Figure 5b. As a result, the V-address is shifted so that the odd-numbered field is delayed by 1H. As is apparent from the above description, the swapping of fields can be stably corrected by suitably selecting the means for advancing the reading V-address by 1H and the means for delaying the reading V-address by 1H. In the above-described embodiment, in order to correct the swapping of fields, on the reading side, the addresses are controlled. However, the same effect can be obtained by a method in which, on the writing side, the addresses are controlled and are then read in the ordinary order. That is, in the case when the fields have been swapped, delaying the odd-numbered fields by 1H in reading them is equivalent to delaying the even-numbered fields by 1H before writing them, and advancing the even-numbered fields by 1H in reading them is equivalent to advancing the odd-numbered fields by 1H in writing them. In this modification, the arrangement is substantially equal to that shown in Figure 4. However, it should be noted that the correcting means 104 is connected between the writing counters 4a and 4b. In the modification, the addresses should be processed so that the data of the fields on one side may not be eliminated. That is, in the case where the phase relation is as shown in Figure 3a, the even-numbered field writing addresses should be delayed by 1H. In the case of Figure 3b, the means for advancing the odd-numbered fields by 1H should be selected. The correcting signals c and d should be produced in synchronization of the edge of the writing field discriminating signal a . The two means for correcting the swapping of field may be the means for delaying the even-numbered fields by 1H on the writing side and the means for delaying the odd-numbered fields by 1H on the reading side, or the means for advancing the odd-numbered fields by 1H on the writing side and the means for advancing the even-numbered fields by 1H on the reading side. In the above-described embodiment, only in the case of Figure 5a or the like, the means for advancing the even-numbered fields by 1H is selected, and, when the difference between the edges of the signals a and b exceeds 1H, the means for delaying the odd-numbered fields by 1H is selected. The two means may be switched in other ways. In the above-described embodiment, for simplification in description, the system clock pulse frequency is an integer multiple of f H , and the address counters are provided separately according to the H (horizontal) direction and the V (vertical) direction. However, a different clock pulse frequency and a different address counter arrangement may be employed together with the address 1H increasing and decreasing means, providing the same effects. In the above-described embodiment, a line in an ODD field and a line in an EVEN field below that in the ODD field by 0.5H are written into the same position in a field memory. However, it is also possible to write a line in the ODD field and a line in the EVEN field above that in the ODD field by 0.5H into the same position in the memory. In this case, if fields to be subject to address processing are swapped, the same effect can be obtained. As was described above, in the video memory control device of the invention, the address advancing means the address delaying means are suitably selected in order to correct the swapping of addresses. Therefore the control device of the invention is free from the difficulty attributed to the processing of addresses, and can therefore achieve the synchronous conversion of a video signal stably at all times. As a result, the 1H delay means and the number of switch circuits, which are heretofore required for field correction, can be eliminated. This contributes to a reduction of the number of circuit elements and accordingly to a reduction of the manufacturing cost.

Claims: A video memory control device for the synchronous conversion of video signals transmitted in a first field and a second field, each field comprising a plurality of lines of 1H in duration, the lines being intended for display in a correct sequence of a line of the first field being followed by a line of the second field, the device comprising: a digital memory (6) having a capacity corresponding to one of the fields; writing means (5) for writing received video signals into the memory according to a writing address; reading means (5) for reading data from the memory according to a reading address; sequential addressing means (4a,4b,9a,9b) for sequentially providing both the writing address and the reading address; and, address processing means (104) for correcting the sequential addressing means; characterised by: address processing means including at least two of: first means for advancing the writing address by 1H, second means for delaying the writing address by 1H, third means for delaying the reading address by 1H, and fourth means for advancing the reading address by 1H; and by: means (101,102,103) for selecting one of said two means in the address processing means according to a phase relation between first data indicating whether the writing address is for the first field or the second field and second data indicating whether the reading address is for the first field or the second field, whereby the reading or writing addresses are generated in a corrected sequence, allowing a display in the correct sequence. A device according to claim 1, wherein said two means in the address processing means are selected to be the first and second means, and the first means advances the writing address for the first field but not the second field, and the second means delays the writing address for the second field but not the first field. A device according to claim 1, wherein said two means in the address processing means are selected to be the third and fourth means, and the third means delays the reading address for the first field but not the second field, and the fourth means advances the reading address for the second field but not the first field. A method for controlling a video memory for the synchronous conversion of video signals transmitted in a first field and a second field, each field comprising a plurality of lines of 1H in duration, the lines being intended for display in a correct sequence of a line of the first field being followed by a line of the second field, the method comprising the steps of: writing received video signals into a memory (6) having a capacity corresponding to one of the fields according to a writing address; reading data from the memory (6) according to a reading address; sequentially providing both the writing address and the reading address; correcting the sequentially provided addresses and including at least two sub-steps from: a first sub-step of advancing the writing address by 1H, a second-step of delaying the writing address by 1H, a third sub-step of delaying the reading address by 1H, and a fourth sub-step of advancing the reading address by 1H; and, selecting one of said two sub-steps according to a phase relation between first data indicating whether the writing address is for the first field or the second field and second data indicating whether the reading address is for the first field or the second field, whereby the reading or writing addresses are generated in a corrected sequence, allowing a display in the correct sequence. A method according to claim 4, wherein said two sub-steps are selected to be the first and second sub-steps, and the first sub-step advances the writing address for the first field but not the second field, and the second sub-step delays the writing address for the second field but not the first field. A method according to claim 4, wherein said two sub-steps are selected to be the third and fourth sub-steps, and the third sub-step delays the reading address for the first field but not the second field, and the fourth sub-step advances the reading address for the second field but not for the first field.

Inventors: MIYAZAKI HARUHITO PIONEER ELEC, MIYAZAKI, HARUHITO PIONEER ELECTRONIC CORPORATION
Applicants: PIONEER ELECTRONIC CORP, PIONEER ELECTRONIC CORPORATION
Application year: 1987
Main classification: H04N5
IPC codes: H04N5, H04N7