VOLTAGE OUTPUT CIRCUIT

Abstract: In the output circuit a signal (S) from an internal circuit is supplied to the gate of an N-channel type MOS transistor (ll), a node (N) of two resistors (l3, l4) connected in series across a power supply terminal (l2) and ground is connected to one end of the MOS tran­ sistor (ll). An NPN transistor (l5) is connected at its base to the node (N), at its collector to the power supply terminal (l2) and at its emitter to an output terminal (l6). The positive polarity terminal of a power supply (l7) is connected to the power supply terminal (l2) to supply a posi­ tive voltage V CC and the negative polarity terminal of another power supply (l9) is connected through a load resistor (l8) to the output terminal (l6) to supply a negative voltage (-V EE ).

Description: This invention relates to a CMOS (Complementary MOS) to ECL (Emitter Coupled Logic) level shifter for converting a desired logic level from CMOS to ECL. As this type of output circuit, TTL-ECL translators are known in the art. Such an output circuit, however, requires both a positive power supply (for example, +5 volts) for driving a CMOS circuit or a TTL circuit and a negative power supply (for example, -5.2 V) for driving an ECL circuit. This is not desirable from the standpoint of costs. Furthermore, owing to the use of the positive and negative power supplies, elements in the circuit are required to have a breakdown voltage enough great for the sum of both the power supply voltages. Where that output circuit and other circuits are formed on a common chip, they are also required to have a breakdown voltage enough great for the sum of both the power supply voltages. In summary, the conventional output circuit for converting a CMOS or a TTL level voltage signal to an ECL level voltage signal requires both the positive and negative power supplies and, furthermore, when it is formed, together with said other circuit, the latter circuit is also required to have a breakdown voltage enough great for the aforementioned sum voltages. Prior art document US-A-4 437 171 discloses a CMOS buffer in which a CMOS level potential is shifted to an ECS level potential. This prior art buffer comprises a first power source, a second power source, and a third power source. An emitter-follower connected bipolar transistor is connected between the first power source and the second power source. A bias circuit is arranged between the first power source and the third power source to output a bias voltage to the base of the emitter-follower connected transistor. Finally, MOS transistors control the level of the bias voltage of the bias circuit according to an input signal. In this buffer circuit, the first power source is a ground potential, the second power source is a negative potential, and the third power source is also a negative potential. It is accordingly the object of this invention to provide a CMOS to ECL level shifter comprised of a semiconductor integrated circuit including MOS and bipolar type elements, which operates with standard CMOS and ECL power supply levels and which can provide an ECL level voltage output. To solve this object the present invention provides a CMOS to ECL level shifter as stated in claim 1. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a basic circuit diagram showing a CMOS to ECL level shifter according to this invention; Fig. 2 is a circuit diagram of a CMOS to ECL level shifter according to an embodiment of the present invention; and Fig. 3 is a characteristic curve showing a relation of a CMOS input level and an ECL output level with respect to time, of the voltage output circuit of Fig. 2. The fundamental arrangement of a CMOS to ECL level shifter according to this invention is as shown in Fig. 1. A signal S from an internal circuit is supplied to the gate of N-channel type MOS transistor 11. One end of MOS transistor ll is connected to a node N of resistors l3 and l4 in a series array between power supply terminal l2 and ground and the other end and back gate of MOS transistor ll are grounded. NPN type bipolar transistor l5 is connected at its base to the node N, at its collector to power supply terminal l2 and at its emitter, to output terminal l6. The positive polarity terminal of power supply l7 is connected to power supply terminal l2 where a positive voltage V CC is supplied by power supply l7. The negative polarity terminal of power supply l9 is connected through load resistor l8 to output terminal l6 where a negative voltage -V EE is supplied by power supply l9. The negative polarity terminal of power supply l7 and positive polarity terminal of power supply l9 are grounded. The operation of the CMOS to ECL level shifter shown in Fig. l will be explained below. When the signal S is at a high level, then MOS transistor ll is turned ON. When the signal S is at a low level, then MOS transistor ll is turned OFF. With the resistive values of resistors l3 and l4 represented by Rl3 and Rl4, respectively, a voltage on the node N is shifted between and the ground by operating MOS transistor ll in an ON/OFF fashion in accordance with a signal S coming from the internal circuit. Specifically, when transistor ll is turned OFF by the signal S, a base voltage on NPN transistor l5 becomes approximately when transistor ll is turned ON, a base voltage of NPN transistor l5 becomes the ground voltage. Thus a voltage on output terminal l6 is shifted between and -V BEl5 . Where V BEl5 denotes a base-emitter voltage of NPN transistor l5. As clearly be understood from the above, output circuit of Fig. l produces a small negative output while operating with a positive power supply alone. The circuit elements in output circuit require the breakdown voltage only for the positive power supply voltage V CC . A CMOS to ECL level shifter according to an embodiment of this invention will be explained below with reference to Figs. 2 and 3. Same reference characters used in Figs. l and 2 denote same components. A CMOS level signal S from the internal circuit is supplied to the gate of an N-channel type MOS transistor ll. MOS transistor ll is connected at one end to the base of NPN type bipolar transistor l5 and grounded at the other end and back gate. Transistor l5 is connected at its collector to power supply terminal l2 and at its base to a node N. A resistor l3 is connected across the base and the collector of transistor l5. A series circuit of resistors l4₁ and l4₂ is connected across the base of transistor l5 and ground. A node of resistors l4₁ and l4₂ in series connection is connected to the base of NPN type bipolar transistor 2l which is connected between the base of transistor l5 and ground. Transistor l5 is connected at its emitter to the base of NPN type bipolar transistor 22 and to one end of resistor 23. Transistor 22 is connected at its collector to power supply terminal l2 and at its emitter to one end of each of resistors 24 and 25. Output terminal l6 is connected to the other end of each of resistors 23 and 24. NPN type bipolar transistor 26 is connected at its base to the other end of resistor 25, at its emitter to output terminal. The collector of NPN type bipolar transistor 26 is grounded. A combination of transistors 22 and 26 is connected to transistor l5 in a Darlington configuration. An electric current flowing through transistors 22 and 26 is supplied to output terminal l6. Diode 27 is connected across output terminal l6 and ground with the anode connected to output terminal l6 and the cathode grounded. A positive voltage V CC is supplied from power supply l7 to power supply terminal l2 and a negative voltage -V EE is applied from power supply l9 through load resistor l8 to output terminal l6. The, negative polarity terminal of power supply l7 and positive polarity terminal of power supply l9 are grounded. Resistor 25 is used for waveform rectification and diode 27 is used for surge voltage protection. The operation of the aforementioned circuit will now be explained below. With Rl and R2 representing the resistive values of resistors l4₁ and l4₂, respectively, when transistor ll is turned OFF, a base voltage on NPN transistor l5 becomes approximately. (Rl+R2)V BE /R2 , which is made constant irrespective of the power supply voltage V CC . V BE denotes a base-emitter voltage of NPN transistor 21. When transistor ll is turned ON, a base voltage on NPN transistor l5 becomes the ground voltage. In other words, that base voltage undergoes a transient shift between the ground voltage and the voltage (Rl+R2)V BE /R2 In accordance with the ON or the OFF state of MOS transistor ll. Let it be assumed that the signal S from the internal circuit is at a high level. Then MOS transistor ll is turned ON and thus the base voltage of transistor l5 becomes grounded. This voltage level is dropped across respective base-to-emitter paths of transistors l5, 22 and 26 so that a small negative voltage -3V BE appears from output terminal l6. V BE denotes a base-emitter voltage of each of the transistors l5, 22 and 26. With the signal S at a low level, MOS transistor ll is turned OFF and the base voltage on transistor l5 becomes: (Rl+R2)V BE /R2 This voltage is dropped across the base-to-emitter paths of transistors l5, 22 and 26 so that a small voltage (Rl+R2)V BE /R2 - 3V BE emerges from output terminal l6. In the CMOS to ECL level shifter of Fig. 2, NPN transistors l5, 22 and 26 are used to produce an output voltage of an ECL level. Base-emitter voltage V BE of a bipolar transistor decreases as an ambient temperature increases. In the output circuit, the base voltage of NPN transistor l5 drops by a total value, -3V BE , of NPN transistors l5, 22 and 23, rendering the output voltage on output terminal l6 small. The bias circuit comprising resistors l4₁ and l4₂ and NPN transistor 2l is used to decrease the base voltage of NPN transistor l5 when an ambient temperature increases so that, for the temperature variation, the output voltage on output terminal l6 is compensated. Fig. 3 shows the result of simulation performed on the CMOS level input and ECL output level characteristics of the circuit of Fig. 2 through the use of an SPICE simulation program, noting that V CC = 5 V, -V EE = -2 V, Rl8 = 50 Ω and the signal S is a pulse signal whose rise and fall times are l.5 ns each and which varies between 0 V and 5 V. As understood from Fig. 3, the voltage output circuit of Fig. 2 operates with power supply and converts the CMOS level voltage signal to the ECLL level voltage output. A very high speed is achieved for the conversion times Dl and D2 of about l.3 ns in comparison with that (about 5 to 6 ns) of the conventional circuit. As set forth above, according to this invention a semiconductor CMOS to ECL level shifter including MOS and bipolar elements is provided, which operates with the use of only one positive power supply and converts the CMOS or the TTL level voltage signal to the ECL level voltage signal.

Claims: A CMOS to ECL level shifter for converting a desired logic level from CMOS to ECL, wherein: a reference potential (GROUND) supplied from a reference potential source corresponds to the low-level of a CMOS input signal (S) from an internal circuit; said CMOS input signal (S) is applied to the gate of a MOS transistor (11), the source of which is connected to the reference potential (GROUND), and the drain of which is connected to the base of the emitter-follower connected first bipolar transistor (15); the emitter of said first bipolar transistor (15) is connected, via a load resistor (18) to a negative supply voltage (19) and a positive supply voltage (17) substantially equal or higher than the high-level of the CMOS input signal is applied to the collector of said first bipolar transistor (15); a bias current is applied to the base of said first bipolar transistor (15) by a voltage divider (12, 14) connected between the positive supply voltage (17) and said reference potential (GROUND); and the ECL output signal is taken from the emitter (16) of said first bipolar transistor (15). The CMOS to ECL level shifter according to claim 1, characterized in that: said voltage divider comprises first and second resistors (13, 14) connected in series between said positive supply voltage (17) and said reference potential (GROUND), and a node (N) between said first and second resistors (13,14) is connected to the base of said first bipolar transistor (15) whereby a voltage on said node (N) is controlled by said MOS transistor (11). The CMOS to ECL level shifter according to claim 1, characterized in that said voltage divider comprises: a first resistor (13) connected between said positive supply voltage (17) and the base of said first bipolar transistor (15); second and third resistors (14₁, 14₂) connected in series between the base of said bipolar transistor (15) and said reference potential (GROUND); and a second bipolar transistor (21) connected between the base of said first bipolar transistor (15) and said reference potential (GROUND), having its base connected to said node between said second and third resistors (14₁, 14₂). The CMOS to ECL level shifter according to claim 1 or 3, characterized by further comprising: a plurality of third bipolar transistors (22, 26) darlington-connected in a cascade fashion to said first bipolar transistor (15). The CMOS to ECL level shifter according to claim 2, characterized in that: the ECL output signal undergoes a transient shift between where Vcc: the potential of the positive supply voltage (17), R13 and R14: resistance values of said first and second resistors (13, 14), and VBE15: a potential difference across the base and emitter path of said first bipolar transistor (15). The CMOS to ECL level shifter according to claim 4, characterized in that: the ECL output signal undergoes a transient shift between where R1 and R2: resistance values of said second and third resistors (14₁, 14₂), VBE: a potential difference across the base and emitter path of said first bipolar transistor (21), and VBEtotal: sum of potential differences across the base emitter path of said first bipolar transistor (15) and said third bipolar transistors (22, 26). The CMOS to ECL level shifter according to claim 4, charcterized in that said plurality of third bipolar transistors (22, 25) comprises: a fourth bipolar transistor (22) whose collector emitter path is connected between said positive supply voltage (17) and said negative supply voltage (19) darlington-connected to said first bipolar transistor (15); and a fifth bipolar transistor (26) whose collector emitter path is connected between said reference potential (GROUND) and said negative supply voltage (19) darlington-connected to said fourth bipolar transistor (22).

Inventors: SUGIMOTO, YASUHIRO C/O PATENT DIVISION, TSUGARU, KAZUNORI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: H03K19
IPC codes: H03K19