VIDEO SIGNAL ENHANCEMENT BY ADAPTIVE DIGITAL SIGNAL PROCESSING

Abstract: A digital subsystem for improving the resolution of a TV digital signal by inserting additional digital samples into the digital TB signal in response to the correspondence of the digital signal and predefined patterns. The digital subsystem is a logic circuit which is responsive to received digital samples to group (502, 504) these digital samples into sets of samples. The digital circuit then calculates (505, 506, 507, 508, 510, 513, 521, 522, 523, 528) the slope between pairs of digital samples of each set and utilizes the calculated slopes to determine the correspondence to the predefined patterns. The determined predefined pattern designates the digital sample to be inserted (503, 520, 524) into each set. The inserted digital sample is either equal to one of the digital samples or the average between two of the digital samples of each set. The calculation of the slopes results in a logical "0" for a constant slope and a logical "1" for a negative or a positive slope. An Exclusive OR gate is utilized to make the determination of whether to use a value equal to one of the digital samples of the set or the average of the value of two of the digital samples. A slope is considered constant if the difference between the pair of digital samples if less than a value calculated from range information of the set of samples.

Description: The present invention relates to digital video processing, and more particularly to digital arrangements for sharpening the edges, or crispening, of video pictures through digital signal processing within a video receiver. A common technique for giving an apparent improvement in resolution in an analog television, TV, receiver is to have an adjustment called a peaking or sharpness control. Even in those TV receivers that lack any peaking control there is normally some amount of fixed peaking incorporated into the design to improve the transient response. Peaking of the baseband signal at the receiver is an attempt to compensate for finite transmission bandwidth that produces poor rise and fall times. The objective of peaking is to produce a crisper-looking picture that appears to have more resolution also referred to as detail. The use of peaking to improve the apparent resolution has also been utilized in digital TV receivers. For example, digital TV receivers are disclosed in an article entitled "Feature IC's For Digivision TV Sets", IEEE Transactions on Consumer Electronics, Vol. CE-29, pp. 237-241, August 1983, or in an article entitled "What is the Impact of Digital TV?", IEEE, Transactions on Consumer Electronics, Vol. CE-28, No. 3, August 1982. Whereas, the use of peaking for improving the apparent resolution of a TV picture has been utilized for a number of years, this technique does suffer from the following problems: ringing of the time domain response on sharp edges, emphasis of the high frequencies compared to the low frequencies, increased amount of noise in the picture, and excessive preshoot or overshoot, or both, at a transient edge. In addition, the implementation of peaking in digital receivers has consumed a disproportionate amount of the digital processing capabilities of a digital receiver. The foregoing problems are solved and a departure in the art is achieved by a structural embodiment and a method whereby digital logical decisions based on predefined patterns are utilized to insert additional digital samples into received digital samples representing the TV signal to enhance the resolution of the latter signal but avoid introducing the previous mentioned problems associated with peaking. Advantageously, the received digital signal samples are grouped into a plurality of groups of samples, and a logic circuit determines predefined patterns of digital samples within each of these groups and inserts additional digital samples within each group based on the determined predefined pattern for each group. Specifically, the logic circuit groups the digital samples into sets of digital samples. The logic circuit then calculates the slope between digital samples of each of the sets and on the basis of these calculated slopes performs a logical comparison between the set and a plurality of predefined patterns which are characterized in terms of slopes. The logic circuit groups the incoming samples into sets each containing three samples. The logic circuit then generates a first type of signal if the slope between a pair of samples is not constant and a second type of signal if the slope between a pair of samples is positive or negative. The logic circuit utilizes an Exclusive OR gate to perform a comparison. The Exclusive OR gate is responsive to receipt of a first and a second of type signal to generate a third signal and is responsive to both inputs being a first type signal or a second type signal for generating a fourth signal. The logical signal utilizes a multiplexer which is responsive to the third signal for inserting a digital sample which is equal to one of the digital samples in the set which illustratively is the middle sample of the set and is further responsive to the fourth signal for inserting a digital sample which is equal to the average of two of the samples of the set. FIG. 1 illustrates a first embodiment of a logic circuit for determining which of the patterns illustrated in FIG. 2 is to be utilized for inserting a sample into a received digital video signal; FIG. 2 illustrates in graphic form a set of predefined patterns in accordance with this invention; FIG. 3 illustrates in graphical form a digital video signal whose resolution has been enhanced by the logic circuit of FIG. 1; FIG. 4 illustrates the details of block 128 of FIG. 1; Fig. 5 illustrates a second embodiment of a logic circuit for determining which of the patterns illustrated in FIG. 6 are to be utilized for inserting samples into a received digital video signal; and Fig. 6 illustrates in graphic form a set of predefined patterns in accordance with this invention. FIG. 1 illustrates a logic circuit for crispening or improving the apparent resolution of a digital video signal. The circuit would be utilized in the digital TV receivers such as the one described in the article. The circuit would replace the peaking circuit of FIG. 2 as disclosed in that article entitled "Feature IC's for Digivision TV Sets". The circuit of FIG. 1 inserts an additional sample between each of the received digitized samples on input bus 101 thereby doubling the sample rate. The value of the sample inserted is determined by comparing three samples received from input bus 101 with the patterns illustrated in FIG. 2. The three sample points are compared against the patterns illustrated in FIG. 2 by the circuit of FIG. 1 are designated C, B, and A, with B being the present sample, C being the next sample, and A being the previous sample. Sample A is first placed on output bus 117, followed by the inserted sample. Illustrated in FIG. 2 are the predefined patterns that are used by the circuit of FIG. 1. The numerical designations given on FIG. 2 indicate whether the slope of the signal is constant (0) or negative (-1) or positive (1). For the slope to be considered constant, the difference between the two samples must be less than a value K, which advantageously may have the value of 25 percent of the maximum range between any combination of the samples A, B, or C if this maximum range is greater than advantageously one-sixteenth of the total dynamic range. For example, pattern 201 of FIG. 2 has a slope of "0" between samples A and B indicating that the difference between samples A and B is less than the value K. By the same token, the slope between sample B and sample C is designated as a "-1" which means that the absolute value of C subtracted from B is greater than the value K. In FIG. 2, a sample designated by a circle means that it is a sample received via bus 101, and a sample designated by an X is an inserted sample. Consider now the operation of the circuit in FIG. 1 in greater detail. As digital samples are received on bus 101, they are processed through delay blocks 102 and 104. The sample being received on bus 101 is the next sample and is designated as C, the output of delay block 102 is the present sample and is designated as B, and the output of delay block 104 is the previous sample and is designated as A. The circuit of FIG. 1 is responsive to a clock signal, fs, received via conductor 116 being a logical "0" (low logic level) to either place the present sample B on output bus 117 or to determine a new sample and place it on output bus 117. The clock signal is received from the remainder of the digital receiver. When fs is a "1", (a high logic level) sample A is gated onto the latter bus. When the previous sample, A, is to be placed on output bus 117, the fs signal received via conductor 116 being "1" enables AND gates 124 which transfers the A sample via OR gates 125 to bus 117. When the inserted sample is to be placed on output bus 117, a "0" is received via conductor 116 that selects the output of OR gates 122. The latter output is the sample to be inserted, and the insertion is performed by enabling AND gates 123 which place the inserted sample onto bus 117 via OR gates 125. Consider now how the inserted sample is determined. Blocks 105 through 107 determine whether the slope between samples C and B is constant or either negative or positive; similarly, blocks 108 through 110 make the same determination for the slope between samples B and A. If the slope between samples C and B is constant, the output of block 107 is "0"; whereas, if the slope is negative or positive, the output of block 107 is a "1". Blocks 108 through 110 function in the same manner with respect to samples B and A. For patterns 201 through 204, the output of Exclusive OR gate 113 is a "1". For example, with respect to pattern 201 the output of block 107 is a "1" whereas the output of block 110 is a "0". Exclusive OR gate 113 is responsive to the output from blocks 107 and 110 being "1" and "0", respectively, to transmit a "1" to gates 120 and 121 which results in gate 120 transferring the B sample to OR gate 122. For patterns 205 through 209 of FIG. 2, the output of Exclusive OR gate 113 is "0" since Exclusive OR gate 113 is either receiving a "0" from blocks 107 and 110 or "1" from blocks 107 and 110 for the latter patterns. AND gates 121 are responsive to the output of gate 113 being a "0" to transfer the output of block 103 to OR gates 122. During the logical "0" part of the fs signal, the inserted sample is placed on output bus 117, and the output of Exclusive OR gate 113 controls whether the output of block 102 or block 103 is transferred to OR gates 125 via gates 120 through 123. If the output of Exclusive OR gate 113 is a "1" gates 120 through 123 select the B sample onto output bus 117. However, if the output of Exclusive OR gate 113 is a "0" then the average between samples A and B is placed on bus 117 by gates 121 through 123 selecting the output of block 103. FIG. 3 illustrates the response of the circuit of FIG. 1 to an input signal whose analog form is illustrated in FIG. 3 as a solid line. The samples which are represented by circles are the samples received via bus 101, and the samples represented by Xs are the inserted samples which, along with the received samples, are transmitted via output bus 117. For example, when sample 302 is the present sample, sample B, the circuit of FIG. 1 recognizes this as pattern 203 since the difference between sample 302 and sample 303 is less than the value K calculated by range parameter calculator 128. Since the pattern is 203, the inserted sample 311 is equal to the present sample 302. When the sample 303 is the present sample, the circuit recognizes the pattern as pattern 206 resulting in the inserted sample 312 being equal to the average of samples 302 and 303. Pattern 206 is identified rather than pattern 207 since the difference between samples 302 and 303 and the difference between samples 303 and 304 are both greater than the calculated value K. When sample 304 is the present sample, the circuit identifies the pattern as pattern 201 resulting in the inserted sample 313 being equal to the present sample 304. When the present sample is sample 305, the circuit determines that the pattern is pattern 204 resulting in the inserted sample of 314 being equal to the present sample 305. Inserted points 315 through 319 result from the circuit determining that the patterns generating these inserting points are patterns 205, 206, or 208 since the differences between any pair of received points, such as points 305 and 306, is greater than the calculated value K for received points 305 through 310. FIG. 4 illustrates in greater detail block 128 of FIG. 1. Block 128 determines the range occupied by samples A, B, and C; and if the largest range is greater than a constant b which advantageously is 1/16 of the total dynamic range, the largest range is divided by a constant a, which advantageously may be 25 percent of the total dynamic range, and the result of the division operation is selected as the value K. If the maximum range between the samples is less than the constant b, then K is set equal to a constant c which advantageously may be 1/64 of the dynamic range. Blocks 401 and 402 calculate the absolute value of the difference between samples A and C by a calculation that is similar to the calculation that is performed by blocks 106 and 107 of FIG. 1. In conjunction with multiplexer 406, comparators 403, 404, and 405 determine which range is the largest. Multiplexer 406 is responsive to the outputs of the comparators 403 through 405 for selecting the largest range. Once the range has been selected and placed on the output of multiplexer 406, comparator 407 compares this range with the constant b. If the selected range is greater than the constant b, then multiplexer 408 selects the output of block 409 which is the selected range divided by the constant a. If the selected range is not greater than the constant b, then comparator 407 controls multiplexer 408 to select the constant c as the value of K. FIG. 5 illustrates another logic circuit for crispening or improving the apparent resolution of a digital video signal. The circuit of FIG. 5 inserts one or more additional samples between received digitized samples from input bus 501, which are grouped into sets of three samples, by comparing each set of samples with the patterns illustrated in FIG. 6. Patterns 603 through 609 in FIG. 6 are identical to patterns 203 through 209 of FIG. 2 with respect to the received digital samples and the inserted digital samples. Patterns 601 and 602 are the same as patterns 201 and 203 with respect to the received digital samples but differ in that the circuit of FIG. 5 inserts two samples rather than one sample per set of samples as is done by the circuit of FIG. 1. Sample 610 and sample 611 are inserted in addition to sample 612 and 613 into patterns 601 and 602, respectively. The insertion of samples 610 and 611 further crispens the received digital samples for patterns 601 and 602. Elements 502 through 513 are identical to elements 102 through 113 of FIG. 1. Multiplexer 520 is equivalent to elements 121 through 122 of FIG. 1, and multiplexer 524 is equivalent to elements 123 through 125 of FIG. 1. Range parameter calculator 528 is similar in operation to element 128 of FIG. 1. The occurrence of patterns 601 and 602 in the input video signal is detected by AND gate 521 in conjunction with comparators 507 and 510. When one of these patterns is detected, flipflop 522 is set and overrides the normal operation of the circuit of FIG. 5 during the next clock time. Consider now the operation of the circuit of FIG. 5 with respect to pattern 601. Inserted sample 612 is identical to sample B. Sample 612 is inserted when fs, the clock signal, is a "0", by multiplexer 524 selecting the output of multiplexer 520 which in turn selects sample B. Multiplexer 520 is responsive to the output of gate 513 being a "1" to select sample B. During the next clock cycle, old sample B becomes new sample A, old sample C becomes new sample B, and the next input sample from bus 501 becomes new sample C. Since flipflop 522 is set, the circuit of FIG. 5 is effectively inhibited from examining this new set of samples in the normal manner, Rather flipflop 522 controls multiplexer 524 to select the output of delay 504 which is equivalent to the previous sample B and to output this sample twice onto output bus 517 during this next clock cycle. This results in the sample B of pattern 601 being transmitted three times on bus 517. Pattern 602 is handled in a similar manner. A digital signal processor could be programmed to implement the functions of FIGS. 1 and 5, and such programming would be routine. Further the principles used in FIGS. 1 and 5 could be used to enhance a video signal along the vertical scan direction as well as the horizontal scan direction.

Claims: An arrangement for enhancing a signal defined by a plurality of digitized samples: CHARACTERIZED BY a delay circuit (502, 504) for grouping said plurality of samples into a plurality of sets of samples; a determinator (505, 506, 507, 508 509, 510, 513, 521, 522, 523, 528) responsive to each of said sets for determining a correspondence between said each set and one of a plurality of predefined patterns of samples; and a selector (503, 520, 524) responsive to the determined one of said plurality of predefined patterns of samples for each of said sets for inserting samples into said each set. The arrangement of claim 1 wherein said determinator comprises a calculator (505-510) for calculating slopes between samples of each of said sets; and logic (513, 521, 522, 523) for logically comparing the calculated slopes of each of said sets with said plurality of predefined patterns to determine the correspondence of each set to said plurality of predefined patterns. The arrangement of claim 2 wherein each of said sets comprises three samples and said calculator comprises a first comparator (507) for generating a first signal upon a calculated slope between an adjacent two of said samples being constant for each set and a second comparator (510) for generating a second signal upon said calculated slope being other than constant for each set; said logic unit comprises a first logic circuit (513) responsive to generation of both a first and a second signal for each set for generating a third signal for each set and further responsive to generation of only first signals and generation of only second signals for generating a fourth signal for each set; a second logic circuit (521) for sequentially detecting both said first and second signals for each of said sets to generate a fifth signal; said selector responsive to said third signal for each of said sets for including an inserted sample equal to one of said samples of each set; said selector further responsive to said fourth signal for each of said sets for inserting a sample equal to the average of two of said samples of each set; and said selector further responsive to said fifth signal for each of said sets for including two samples equal to one of said samples of said set. The arrangement of claim 3 wherein each of said sets of samples has two slopes associated with it and each slope is between two of the samples of each set and said determinator further comprises range parameter calculator (528) responsive to the samples of each set for generating a value defining range information for each set. The arrangement of claim 4 wherein said range parameter calculator comprises means (401, 402) for determining the differences between samples of each of said sets; an arithmetic unit (402-406) for locating the maximum difference between samples for each set; and a divider (409) for dividing the located maximum difference by a predefined value for each set to generate said value. A method for enhancing a signal defined by a plurality of digitized samples: CHARACTERIZED BY grouping (502, 504) said plurality of samples into sets of samples; determining (505, 506, 507, 508, 510, 513, 521, 522, 523, 528) a correspondence between one of said sets and one of a plurality of predefined patterns of samples in response to said one of said sets; and inserting (503, 520, 524) samples into said one of said sets in response to the determined one of said plurality of predefined patterns of samples. The method of claim 6 wherein said step of determining comprises the steps of calculating (505-510) slopes between the samples of said one of said sets; and logically comparing (513, 521, 522, 523) the calculated slopes with said plurality of predefined patterns to determine the correspondence of said one of said sets to said plurality of predefined patterns. The method of claim 7 wherein each of said sets comprises three samples and said calculating step comprises the steps of generating (507) a first signal upon said slope of an adjacent two of said samples being constant and generating (510) a second signal upon said calculated slope being other than constant; said comparing step comprises the steps of generating (513) a third signal in response to a first and a second signal; and generating a fourth signal in response to generation of only first signals and to generation of only second signals; sequentially detecting (521) said first and second signals for said one of said sets to generate a fifth signal; said inserting step comprises the steps of producing an inserted sample equal to one of said samples of said one of said sets in response to said third signal; producing a sample equal to the average of two of said samples of said one of said sets in response to said fourth signal; and producing two samples equal to one of said samples of said one of said sets in response to said fifth signal. The method of claim 8 wherein said one of said sets of samples has two slopes associated with it and each slope being for an adjacent two of said samples of said one of said sets and said step of comparing comprises the steps of generating a value defining range information for said one of said sets in response to said samples; and testing each slope with the generated range value associated to determine whether each slope is constant. The method of claim 9 wherein said step of generating comprises the steps of calculating the differences between each of said samples; locating the maximum difference between said samples; and dividing said located maximum difference by a predefined value to generate said range value.

Inventors: RZESZEWSKI, THEODORE STANLEY
Applicants: AMERICAN TELEPHONE AND TELEGRAPH COMPANY
Application year: 1987
Main classification: H04N5
IPC codes: H04N5