Photoelectric converting apparatus

Abstract: A photoelectric converting cell has a control electrode region of a semiconductor transistor (S₁). The carriers generated in the control electrode region by the light excitation are accumulated, and the accumulation voltage generated by this accumulation is read out from one of the main electrode regions of the semiconductor transistor. The control electrode region is connected to an excess carrier eliminating circuit (D₁, Lrh, Ve) to perform the switching operation in dependence on the potential difference across the control electrode region.

Description: FIELD OF THE INVENTION The present invention relates to a photoelectric converting apparatus of the system in which the carriers generated in the control electrode region of a transistor by the light excitation are accumulated and, more particularly, to a photoelectric converting apparatus to prevent the outflow of the excess carriers. Related Background Art Fig. 1A shows a schematic cross sectional view of a photoelectric converting apparatus and Fig. 1B is a diagram showing an equivalent circuit of one of the photoelectric converting cells in this apparatus. In Fig. 1A, an n - epitaxial layer 4 is formed on an n silicon substrate 1. Photoelectric converting cells which are electrically insulated from one another by a device separating region 6 are arranged in the layer 4. First, a p base region 9 of a bipolar transistor is formed on the n - epitaxial layer 4. An n + emitter region 15 is formed in the p base region 9. Further, a capacitor electrode 14 to control the potential of the p base region 9 and an emitter electrode 19 connected to the n + emitter region 15 are formed through an oxide film 12, respectively. An electrode 17 connected to the capacitor electrode 14 is formed. An n + region 2 for ohmic contact is formed on the back side of the substrate 1. A collector electrode 21 of the bipolar transistor is formed under the n + region 2. In this manner, a photoelectric converting cell is constructed. The fundamental operation of the photoelectric converting cell will now be described. First, the p base region 9 which is biased to the negative potential is set into the floating state. The holes in the electron/hole pairs generated by the light excitation are accumulated into the p base region 9 (accumulation operation). Subsequently, the positive voltage is applied to the capacitor electrode 14, thereby forwardly biasing the circuit between the emitter and the base. The accumulated voltages generated by the holes accumulated are read out to the emitter side in the floating state (readout operation). Then, the emitter side is grounded and pulses of the positive voltage are applied to the capacitor electrode 14, thereby extinguishing the holes accumulated in the p base region 9. Thus, when the positive voltage pulse for refreshing falls, the p base region 9 is reset to the initial state (refresh operation). In such a photoelectric converting apparatus, after the accumulated charges were amplified by the amplifying function of each cell, they are read out, so that the high output, high sensitivity, and low noise can be accomplished. On the other hand, since the structure is simple, this apparatus is also advantageous to realize the high resolution in future. However, when a photoelectric converting apparatus is constructed by arranging a plurality of photoelectric converting cells mentioned above, there is a problem such that in the case where the light of a saturation light amount or more was irradiated onto a certain pixel, the smear occurs. Namely, when the strong light enters, a large quantity of holes are accumulated in the p base region 9, so that the base potential increases. When the base potential increases to a value in excess of the collector potential, a depletion layer 22 between the base and the collector is extinguished and the accumulated carriers in the base flow into the adjacent cells (as indicated by arrows 23). Thus, the p base region 9 of the adjacent cells enters the accumulation state in which the inflow holes were added. When an image of the readout signal is reproduced, the smear occurs. EP-A-0132076 discloses a photoelectric converting cell substantially as shown in Figures 1A and 1B of the present application. In EP-A-0132076 there is described, with reference to Figure 7 thereof, an arrangement for preventing blooming along vertical lines, as a result of holes flowing from a saturated base through the emitter onto the vertical lines. This proposes that during the accumulation operation, the vertical lines to which the emitters are connected should be grounded through respective MOS transistors provided for each vertical line. SUMMARY OF THE INVENTION According to the present invention there is provided photoelectric converter apparatus as set out in claim 1. The remaining claims set out optional features. In an embodiment of the apparatus of claim 1, the limiter means limits the potential generated in the control region, so that the outflow of excess carriers into the adjacent cells is prevented and the occurrence of the smear of the reproduced image can be prevented. In one embodiment of the invention, the limiter means limits the potential of the control region to a value within a constant potential lower than a saturation potential. The carriers generated by the light excitation are accumulated in the control region. However, when the potential of the control region just exceeds the constant potential, the carriers in the control region are eliminated by the limiter means, so that the potential of the control region is always limited to a value within the constant potential before it reaches the saturation potential. Therefore, the outflow of the carriers when the potential of the control region reaches the saturation potential does not occur and the leakage of the carriers to the adjacent devices is prevented. Embodiments of the present invention, given by way of non-limiting example, will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic cross sectional view of a photoelectric converting cell disclosed in Japanese Laid-Open Patent Gazette Nos. 12759/1985-12765/1985; Fig. 1B is an equivalent circuit diagram of this cell; Fig. 2A is cancelled; Fig. 2B is cancelled; Fig. 3 is cancelled; Fig. 4A is cancelled; Fig. 4B is cancelled; Fig. 4C is cancelled; Fig. 5 is cancelled; Fig. 6 is cancelled; Fig. 7A is cancelled; Fig. 7B is cancelled; Fig. 7C is cancelled; Fig. 7D is cancelled; Fig. 8 is cancelled; Fig. 9A is cancelled; Fig. 9B is cancelled; Fig. 10 is cancelled; Fig. 11 is a cross sectional view of one cell of the embodiment; Fig. 12A is an equivalent circuit diagram for explaining the fundamental operation of the photoelectric converting cell shown in Fig. 11; Fig. 12B is a voltage waveform diagram showing the operation of the cell shown in Fig. 11; Fig. 13 is a schematic circuit diagram in a construction using the cell of Fig. 11; Fig. 14 is a graph showing the relation between the voltages V(A) and V(B) in the construction of Fig. 13; Fig. 15 is a graph schematically showing the photoelectric converting characteristic in the construction of Fig. 13; Fig. 16 is a schematic circuit diagram of a cell in the embodiment of the invention; Fig. 17 is a schematic circuit diagram of a line sensor using the construction of Fig. 13; and Fig. 18 is a timing chart showing an example of timings for respective pulses which are output from a driver 77 shown in Fig. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 11 is a diagram showing a construction of a photoelectric converting cell used in an embodiment of the invention. In the diagram, an n - layer is formed on an n type substrate 501 by an epitaxial growth method. The cells S 1 , S 2 , ..., S n isolated from each other by a device separating region are formed in line on the n - layer. The n - layer serves as a collector region 502 in each cell. Further, a p base region 503 is formed in each cell. An n + emitter region 504 is formed in the p base region 503. In this manner, an npn type bipolar transistor is constructed. A p + region 505 is formed in the p base region 503. A p + region 506 is formed in the n - layer 502 with a constant distance away from the p + region 505. Further, a gate electrode 508 is formed through an oxide film 507. In this manner, a resetting p channel MOS transistor (hereinafter, referred to as a "reset Tr") is constructed. An n channel MOS transistor may be also used as the reset Tr. An insulative film 509 is formed on the bipolar transistor and reset Tr. An electrode 510 connected to the p + region 506 and an emitter electrode 511 connected to the n + emitter region 504 are formed, respectively. Further, an insulative film 512 is formed on the insulative film 509. The portion of the insulative film 512 excluding the opening portion is covered by a light shielding film 513. In addition, a collector electrode 514 is formed on the back surface of the substrate 501. In this construction, the case of the photoelectric converting cell using the npn type bipolar transistor has been described. However, the invention can be also applied to the system using a field effect transistor, an electrostatic inductive transistor, or the like. The invention can be applied to any system using a transistor having a region adapted to accumulate the carriers. The fundamental operation of the photoelectric converting cell will now be explained. Fig. 12A is an equivalent circuit diagram for explaining the fundamental operation of the photoelectric converting cell. Fig. 12B is a voltage waveform diagram showing the operation of this cell. In Fig. 12A, the foregoing photoelectric converting cell is equivalent to the circuit in which the p base region 503 of the npn type bipolar transistor is connected to a drain of a reset transistor 500. A pulse  res is input to the gate electrode 508 of the reset transistor 500. A constant voltage V bg (e.g., 2V) is properly applied to the source electrode 510. The emitter electrode 511 is connected to a terminal 515 through an n channel MOS transistor 500'. A pulse  vrs is input to the gate electrode. A voltage which is sufficiently lower than the voltage V bg or a grounding voltage is properly applied to the terminal 515. First, in the accumulation operation, the potential V b of the p base region 503 is set in the floating state at the initial positive potential and the emitter region 504 is set in the floating state of the zero potential, respectively. The positive voltage V cc is applied to the collector electrode 514. The gate electrode 508 of the reset transistor 500 is set at the positive potential. The reset transistor 500 is in the off state. In this state, the light enters the photo sensitive section. The carriers (in this case, the holes) of the amount corresponding to the light quantity are accumulated into the p base region 503. At this time, since the p base region 503 is set at the initial positive potential, when the carriers are accumulated by the light excitation, the signals corresponding to the accumulated carriers are simultaneously read out to the emitter side in the floating state, so that the photoelectric converted output is derived. Namely, the readout operation is executed simultaneously with the accumulation operation in this case. The operation to extinguish the carriers accumulated in the p base region 503 will now be explained. As shown in Fig. 12B, by first applying the pulse  res of the negative voltage to the gate electrode 508 of the reset transistor 500, the reset transistor 500 is turned on (for the period of time T 1 ). Thus, the potential V b of the p base region 503 is set to the constant voltage V bg irrespective of the accumulated voltage level, namely, irrespective of the illuminance of the incident light. The constant voltage V bg is set to a value which is sufficiently higher than a residual base potential V k after the carrier extinguishing operation was finished. For example, V bg = 2V. Next, the transistor 500' is turned on by the pulse  vrs of the positive voltage. The grounding voltage of the terminal 515 or the voltage which is sufficiently lower than the voltage V bg is applied to the emitter electrode 511 through the transistor 500' (for the period of time T 2 '). The pulse  vrs of the positive voltage can be also applied continuously after the time point when the pulse  res rose (for the period of time T 2 ). Thus, the holes accumulated in the p base region 503 are recombined with the electrons which are implanted into the p base region 503 from the n + emitter region 504, so that the holes are extinguished. As already explained above, the potential V b of the p base region 503 is set to the potential V bg which is sufficiently higher than the residual potential V k irrespective of the accumulated potential level for the period of time T 1 . Therefore, after expiration of the period of time T 2 or T 2 ', the potential V b of the p base region 503 is set to the constant potential V k irrespective of the illuminance of the incident light. After expiration of the period T 2 or T 2 ', the pulse  vrs falls and the transistors 500' is turned off. The emitter electrode 511 enters the floating state. Then, the foregoing accumulation operation and readout operation are executed. In this manner, by providing the period of time T 1 to set the potential of the p base region 503 to the constant potential, at the end of the extinguishing operation for the period of time T 2 or T 2 ', the potential V b of the p base region 503 can be set to the constant potential. The nonlinearity of the photoelectric converting characteristic in the low illuminance state and the phenomenon of the after image can be perfectly prevented. On the other hand, since the potential control of the p base region 503 is not performed by the capacitor, the reduction and variation in output due to the capacitor do not occur. A construction using the foregoing photoelectric converting cell will now be explained in detail hereinbelow with reference to the drawings. Fig. 13 is a schematic circuit diagram of the construction. In the diagram, the constant positive voltage V cc is applied to the collector electrode 514 of the photoelectric converting cell. The foregoing output is derived from the emitter electrode 511. The constant voltage V bg is applied to the source electrode 510 of the reset transistor 500. The gate electrode is grounded through a resistor R 3 and also connected to the source electrode of an n channel MOS transistor Q 100 . The pulse  res is input to the drain electrode of this transistor. The voltage V g obtained by dividing the voltage V cc by resistors R 1 and R 2 is applied to the gate electrode of the transistor Q 100 . The value of the gate voltage V g is decided by the relation with the drain voltage. In this case, the gate voltage V g is set in a manner such that the transistor Q 100 is made conductive in the unsaturation region when the pulse  res is at the low voltage and that the transistor Q 100 is set to the pinch-off state or saturated state in the drain when the pulse  res is at the high voltage. In the above circuit, the voltage at point (A) as the drain voltage of the transistor Q 100 is set to V(A) and the voltage at point (B) as the gate voltage of the reset transistor 500 is set to V(B). The operation of this construction will now be described. Fig. 14 is a graph showing the relation between the voltages V(A) and V(B) in this construction. Fig. 15 is a graph schematically showing the photoelectric converting characteristic in the construction. First, in Fig. 14, in the refresh operation of the photoelectric converting cell, the voltage V(A) falls by the pulse  res and is set to the negative potential for only the period of time T 1 . Thus, the transistor Q 100 is turned on in the unsaturation region as mentioned above. The gate voltage V(B) of the reset transistor 500 is almost equal to the voltage V(A). Therefore, the reset transistor 500 as the p channel MOS transistor is turned on. The voltage V b of the p base region 503 is set to the constant voltage V bg irrespective of the light quantity of the incident light as already explained above. After the elapse of the period of time T 1 , the voltage V(A) rises to a predetermined positive potential, so that the transistor Q 100 enters the saturated state. Since the gate voltage V g is constant so long as the voltage V cc is constant, an almost constant drain-source current flows through the transistor Q 100 . The gate voltage V(B) of the reset transistor 500 is set to the constant positive voltage which is lower than the voltage V(A) by the resistor R 3 . V(B) = V g - V t1 (where, V t1 denotes a threshold voltage of the transistor Q 100 ). In this construction, V(B) is set to be lower than V cc from the relation with the reset transistor 500, which will be explained hereinafter. The reset transistor 500 is turned off by the constant gate voltage V(B) and the refresh operation is executed until the period of time T 2 has passed as already explained above. Subsequently, the accumulation operation and readout operation are performed. Assuming that the threshold voltage of the reset transistor 500 is V t5 , although the reset transistor 500 is in the off state in this construction, when the potential V b of the p base region 503 reaches a constant potential V bm due to the accumulation, the reset transistor 500 is made conductive. The base potential V b is always limited to a value of the constant potential V bm or less. Contrarily speaking, the value of the gate voltage V(B) of the reset transistor 500 is set so as to limit the base potential within V bm . Namely, with an increase in base potential V b , the drain-gate voltage (V(B) - V b ) of the reset transistor 500 decreases. By setting the gate voltage V(B) so that the pinch-off state in the drain occurs when V b = V bm , the reset transistor 500 is made conductive when V b = V bm . The base potential does not increase to a value of V bm or more. At this time, V bm = V(B) + V t5 . Since the constant potential V bm is set to a potential lower than the saturation potential at which the carriers accumulated in the p base region 503 flow out, even if the strong light enters, the leakage of the carriers into the adjacent cells can be prevented. In addition, the outflow of the carriers to the emitter side can be also prevented. By setting the upper limit of the base potential as explained above, the output characteristic in this construction has reached the upper limit before the output signal level reaches the saturation level as shown in Fig. 15. However, by properly selecting the upper limit level, no practical problem occurs. In this construction, the gate voltage V g of the transistor Q 100 is obtained by the voltage V cc serving as not only the collector voltage of the bipolar transistor but also the substrate voltage of the reset transistor 500. Therefore, there is an advantage such that even if the voltage V cc fluctuated, the influence on the photoelectric converting cell is set off. Fig. 17 is a schematic circuit diagram of a line sensor using the photoelectric converting cells of this construction. In this diagram, the gate electrode 508 of the reset transistor 500 of each cell is commonly connected to a line L res . The line L res is grounded through the resistor R 3 and also connected to a terminal 70 through the transistor Q 100 . The pulse  res is input to the terminal 70. The voltage V g is applied to the gate electrode of the transistor Q 100 . This gate voltage V g is obtained by dividing the voltage V cc by the resistors R 1 and R 2 . The source electrode 510 of each reset transistor 500 is commonly connected to a terminal 72. The voltage V bg is applied to the terminal 72. The emitter electrode 511 of each cell is grounded through the transistor 500'. The gate electrodes of the transistors 500' are commonly connected to a terminal 71. The pulse  vrs is input to the terminal 71. Further, the emitter electrode 511 of each cell is connected to an accumulating capacitor C T through a transistor 521. Each capacitor C T is commonly connected to an output line 520 through a transistor 522, respectively. The gate electrodes of the transistors 521 are commonly connected to a terminal 73. A pulse  t is applied to the terminal 73. The gate electrode of the transistor 522 is connected to an output terminal of a shift register 523. The transistors 522 are sequentially turned on by the shift register 523. The shift registers 523 are made operative by a shift pulse  sh which are input from a terminal 79. The positions at the high level are sequentially shifted. The output line 520 is connected to an output terminal 76 through an output amplifier 525. An input terminal of the output amplifier 525 is also connected to a terminal 74 through a transistor 524. A constant voltage V bh is applied to the terminal 74. On the other hand, the pulse  hrs is input to a gate electrode 75 of the transistor 524. The pulses  and constant voltages V bg and V bh are supplied from a driver 77. The driver 77 outputs the pulses at the timings responsive to a clock signal from an oscillator 78. The operation of the foregoing line sensor will now be explained hereinbelow with reference to Fig. 18. Fig. 18 is a timing chart showing an example of the timings for the pulses which are generated from the driver 77. In the diagram,  t (A) and  t (B) indicate timings for the different reading methods. The case of the pulse  t (A) will be first explained. By setting the pulse  res to the low level at time t 2 after the pulses  t and  vrs was set to the high level at time t 1 , all of the reset transistors 500 are turned on as mentioned above. The potential of the p base region 503 of each cell is set to the constant potential V bg . On the other hand, since the pulse  t is at the high level, the transistor 521 is turned on and the charges in the capacitor C T are eliminated through the transistors 521 and 500'. When the pulse  res is set to the high level at time t 3 , the reset transistor 500 of each cell is turned off. Since the pulse  vrs is still at the high level, the carriers accumulated in the p base region are gradually recombined with the electrons and extinguished as already mentioned above. The amounts of residual carriers in the p base regions of all cells at time t 4 are always equal irrespective of the quantity of residual carriers in the p base regions before time t 2 . When the pulse  vrs falls at time t 4 , the emitter electrode 511 of each cell is connected to the capacitor C T through the transistor 521. The accumulation and readout operations are executed until the pulse  t falls at time t 6 as mentioned above. Namely, as the carriers generated by the light excitation in the cells S 1 to S n are accumulated in the p base regions, the carriers as much as the accumulated carriers are accumulated into the capacitors C T , respectively. At this time, even if the strong light entered, the base potential of each cell is limited to a value within the constant value by each reset transistor 500, so that the outflow of the excess carriers is prevented. When the pulse  t falls at time t 6 , the transistors 521 are turned off. The photoelectrically converted signals in the cells S 1 to S n are accumulated in the capacitors C T and stored. Next, the operations to sequentially take out the information stored in the capacitors C T and to serially output them are executed. First, by applying one pulse  hrs at time t 7 , the transistor 524 is turned on and the residual charges in the stray capacitor of the output line 520 are eliminated. By subsequently applying one pulse  sh at time t 8 , the scan of each transistor 522 by the shift register 523 is started. When one of the transistors 522 is turned on, the charges accumulated in the relevant capacitor C T are taken out to the output line 520 and output to the outside from the output terminal 76 through the amplifier 525. Thereafter, the transistor 524 is immediately turned on by the pulse  hrs and the output line 520 is cleared. The foregoing signal fetching operations are sequentially executed at the timings of the shfit pulses  sh with respect to the cells S 1 to S n . The signals which were photoelectrically converted for the period of time from time t 4 to time t 6 and the dark reference signal can be sequentially output. After all of the signals accumulated in the capacitors C T were taken out, the carrier extinguishing operation for the period of time from t 1 to t 4 , the accumulation and readout operations for the period of time from t 4 to t 6 , and the signal taking-out operation after time t 7 are again repeated in accordance with this order. The readout operation in the case of the pulse  t (B) relates to the further improved operation of the operation in the case of pulse  t (A). Namely, the pulses  t are set to the low level for the period of time from t 4 to t 5 . Thus, the carriers generated in the p base region of each cell by the light excitation are not accumulated in the capacitor C T but accumulated in each cell. The signals accumulated in each cell by the pulses  t for the period of time from t 5 to t 6 are transferred to the capacitor C T , respectively. With this method, it has been confirmed by the experiments that as compared with the case of  t (A), the output was improved by 20 to 30 % and the variation in sensitivity was remarkably reduced. Although the pulse  vrs is set to the high level for the period of time from t 1 to t 3 , it may be set to the low level. In this case, the current flowing across the base and emitter of the cell for the period of time from t 1 to t 3 can be shut off. The loss of electric power can be effectively prevented. Each signal of the cells S 1 to S n are serially output as the output signal V out from the terminal 76 of the amplifier 525 to the outside. In the foregoing line sensor, even if the strong light entered, the carriers do not leak to the adjacent cells, so that the smear can be prevented. Fig. 16 is a schematic circuit diagram in the embodiment of the invention. This embodiment has a switch SW to switch the gate voltage V g of the transistor Q 100 . For example, in the photoelectric converting apparatus in which the photoelectric converting cells are arranged like an area, two operation modes are provided: the field accumulation mode to form a one horizontal line signal by simultaneously reading out the signals of the cells of two lines and by adding them; and the frame accumulation mode to form a one horizontal line signal by reading out the signals of the cells of one line. In the field accumulation mode, even if the signal level per cell is the half of that in the frame accumulation mode, the horizontal signal at the equal level is eventually obtained. Therefore, in this example, as shown in Fig. 16, the gate voltage V g in the field accumulation mode is set to a lower value (about the half of that in the frame accumulation mode). Thus, the gate voltage V(B) of the reset transistor 500 also becomes the low value, so that the potential V b of the p base region 503 can reach to the upper limit at a low level. The occurrence of the smear can be effectively prevented. The area sensor can be formed in a manner analogous to the line sensor of Fig. 17. As described in detail above, in the photoelectric converting apparatuses in the embodiment of the invention, the potential of the control electrode region of the photoelectric converting transistor is always limited to a value within the constant potential before it reaches the saturation potential. Therefore, the outflow of the carriers which will occur when the potential of the control electrode region has reached the saturation potential does not occur. The leakage of the carriers to the adjacent devices can be prevented. Therefore, when constituting an area sensor, the occurrence of the smear can be effectively prevented by merely providing the carrier eliminating means with a simple constitution.

Claims: Photoelectric converter apparatus comprising a plurality of cells arranged in rows and columns, each cell comprising a photo transistor having a first main electrode region (504) a second main electrode region (501), a first main electrode (511) connected to the first main electrode region, a second main electrode (514) connected to the second main electrode region, and a control region (503), and in which the current flow between the first and second main electrode regions (504, 501) is controlled by the potential of the control region (503), and the apparatus is operable, in relation to each said photo transistor, to accumulate charge carriers in the control region in response to incident radiation and provide an output to the first main electrode (511) via the first main electrode region (504) corresponding to the potential generated in the control region (503) by the accumulated charge carriers, and subsequently to refresh the control region by removing the accumulated charge carriers from it, each cell further comprising carrier removal means (500) connected to the control region (503) and to a reference potential (VB), so that excess carriers are removed from the control region (503) by the carrier removal means (500) during the accumulation of charge carriers in the control region (503) if the potential of the control region (503) exceeds a level determined by the reference potential (VB), characterised in that the apparatus comprises control means having a first mode of operation in which signals are read simultaneously from a plurality of rows of photo transistors and added to provide a single row of output signals, and a second mode in which signals are read from a single row of photo transistors to provide a single row of output signals, and selector means (SW) to change the characteristics of the carrier removal means (500) in accordance with the selection of the first or second mode of operation of the control means. Apparatus according to claim 1 in which the selector means (SW) changes the said level of the potential of the control region. Apparatus according to claim 2 in which the selector means (SW) changes the level of the reference potential (VB) in accordance with the mode of operation of the control means. Apparatus according to claim 3 comprising reference potential generating means comprising a transistor (Q100) having a first main electrode region connected to the carrier removal means (500) and to one end of a resistor (R3), the other end of the resistor (R3) being connected to a predetermined potential, so that the current through the transistor (Q100) and the resistor (R3) determines the reference potential (VB), the transistor (Q100) receiving a control potential (Vg) at its control region to control the current flowing through it, and the selector means (SW) selecting the control potential (Vg). Apparatus according to any one of the preceding claims in which the carrier removal means comprises a potential-limiting semiconductor element to convey excess charge carriers from the control region (503) to a carrier removal electrode (510). Apparatus according to claim 5 in which the potential-limiting semiconductor element comprises switching means (500) connected to convey excess charge carriers from the control region when the switching means is conductive, the switching means receiving the reference potential and conducting or not conducting in accordance with the difference between the reference potential and a potential applied to it from the control region. Apparatus according to claim 6 in which the switching means comprises a further transistor (500) and the reference potential (VB) is applied to its control region. Apparatus according to claim 7 in which the further transistor (500) is an FET, and the reference potential (VB) is applied to its gate. Apparatus according to any one of the preceding claims in which the reference potential holds the potential of the control region during the accumulation of charge carriers to a level at which the photo transistor is not saturated. Apparatus according to any one of the preceding claims in which the photo transistor is a bipolar transistor.

Inventors: NAKAMURA YOSHIO, SUGAWA SHIGETOSHI, NAKAMURA, YOSHIO, SUGAWA, SHIGETOSHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1987
Main classification: H01L27
IPC codes: H04N3, H01L27