Device for the regeneration of channel-clock information in data transmission and data-recovery arrangement comprising such a device.

Abstract: A sampled synchronous transmission signal Vt is represented by a series of samples J at equidistant sampling instants. A computing circuit 5 computes the po­ sitions R of the sampling instants relative to the rising edges of a virtual reference clock Cref which is phase-­ locked to the channel clock. For each sampling instant the position R is determined on the basis of the position R of a preceding sampling instant and a measure Q of the dif­ ference in time between the sampling interval T and the period L of the virtual reference clock Cref. From the values of the successive samples J an interpolation circuit 2 derives the positions N of the detection-level crossings by the transmission signal Vt, which crosssings represent a fixed phase position of the channel clock. After each detections-level crossing the measure Q of the time diffe­ rence is corrected by means of circuit 3 and 4 depending on the difference between the positions N and R. A data recovery arrangement recovers the data depending on the values determined for the positions R.

Description: The invention relates to a device for the regeneration of channel-clock information from a series of samples which represent the signal values of a band-limited transmission signal at equidistant sampling instants, which transmission signal is synchronous with the channel clock, comprising means for determining, in dependence on an input value, reference phase positions indicative for the phase positions of the sampling instants with respect to the phase of a virtual clock, the differences between two subsequent reference phase positions corresponding to the input value, detection means for determining crossings of a detection level by the transmission signal from the samples, interpolation means responsive to level cross detections for determining the phase positions of the sampling instants with respect to the phase of the channel clock from the samples and means for determining the difference between the phase positions and the corresponding reference phase positions. The invention also relates to an arrangement for the recovery of data represented by the sampled band-limited transmission signal, comprising a device for the regeneration of channel-clock information. Such a device and arrangement are known from European Patent Application EP 0,109,837. The known channel-clock information regeneration device is employed for the recovery of digital data represented by a band-limited binary synchronous data signal obtained from a magnetic-tape reader. In this device the data signal is sampled at a rate which is approximately twice the channel-clock frequency. For each sample the channel-clock information regeneration device determines the phase position of the sample instant with respect to the phase of a virtual reference clock signal. For each sample this reference phase position is adapted by a value corresponding to 180° by means of a cyclic counter whose counting range corresponds to a 360° phase difference. The count of the cyclic counter represents the phase position of the virtual reference clock with respect to the sampling instants. Each time that the count exceeds a value corresponding to a phase position of 0° between two consecutive samples the data recovery arrangement detects one bit of a sign which is dictated by the sign of the last sample. Further, in response to a detection-level crossing, the phase position of a sampling instant adjacent the detection-level crossing with respect to the detection-level crossing is derived from the sampling values of the samples on appoints sides of the detection-level crossing. The phase difference between the channel clock and the virtual reference clock is derived from the count of the counter and the phase position thus determined. The count is adapted by a value which depends on this difference. In this way it is achieved that the phase represented by means of the count of the cyclic counter substantially corresponds to the actual phase of the channel clock at the sampling instants. However, the known device for the regeneration of the channel clock information has the disadvantage that for a reliable operation of the device it is necessary that the sampling rate is substantially equal to twice the channel-clock frequency. If the sampling rate deviates from this value the phase difference between two successive samples no longer corresponds to 180°, so that the phase represented by the count of the cyclic counter deviates increasingly from the actual phase of the channel clock as the time interval between the sampling instants and the last detection-level crossing increases. It is the object of the invention to provide a device of the type defined in the opening paragraph which for a reliable operation imposes less stringent requirement on the relationship between the sampling rate and the channel-clock frequency. According to the invention this object is achieved in that by means for adapting the input value in dependence on the differences determined, such that the differences between the phase positions and corresponding reference phase positions are substantially kept at a constant value. In the device in accordance with the invention the correction of the input value ensures that said difference remains in conformity with the actual difference. On the basis of this difference the positions of the sampling instants are determined, so that a relationship between sampling rate and the channel-clock frequency does not affect the reliability of the positions of the sampling instants thus determined. In one embodiment the device for the recovery of the channel-clock information is characterized in that the means for adapting the input value comprise summing means for forming the sum of the differences and means for the input value from at least the sum of the differences. The averaging-character of the summation means of this embodiment has the advantage that the determination of the measure of the time difference is practically immune to occasional errors in the determination of the difference between the first measure and the second measure, which may occur, for example, as a result of interpolation errors in the determination of the first measure. A further embodiment is characterized in that the means determining the difference comprise correction means for correcting the difference by a value corresponding to the period of the virtual reference clock in response to a detection of a difference larger than a value corresponding to half the period of the virtual reference clock. In this embodiment large differences between the reference phase portions and the phase portions are detected. These large differences generally indicate that the reference phase position is not situated between the same samples as the phase position. This results in a large difference value although the actual difference is only small. By applying a correction by a value corresponding to the interval between the reference instants the difference found between the reference phase position and the phase position is brought into conformity with the actual situation. An embodiment which is suitable on account of its simple computing means is characterized in that the means for determining the reference phase positions are provided with comparing means for determining the difference between the reference phase position determined and a value corresponding to the sampling interval, the means for determining the reference phase position being adapted to determine the next phase position by modifying it by the input-value or a value corresponding with the sampling interval and with a sign opposite to the sign of the input value in dependence on whether the difference period determined by the said comparing means are negative or positive respectively. Suitably, a data-recovery arrangement of the type defined in the foregoing is characterized in that the data-recovery arrangement comprises comparison means for determining whether the values of the reference phase positions are situated within bounds which are situated at an interval corresponding to the sampling interval from each other and counting means for counting the number of times that the reference phase positions between two successive detection level crossings are situated within said bounds. Embodiments of the invention will now be described in more detail, by way of example, with reference to Figs. 1 to 10, in which Fig. 1 shows a series of samples, the transmission signal represented by these samples, and a virtual reference-clock signal, Fig. 2 shows an example of a detection-level crossing by the transmission signal, Fig. 3 shows an example of a series of samples and the reference-clock signal in the proximity of a detection-level crossing, Figs. 4a and 4b show the intervals between successive sampling instants and the reference instants, Fig. 5 shows a device embodying the invention, Figs. 6 to 9 show parts of the device embodying the invention in more detail, and Fig. 10 shows an arrangement which recovers the data transmitted by means of the transmission signal. Fig. 1 shows a series of samples J1 to J12 which are situated at equal time intervals determined by the sampling interval T from one another. The samples represent the signal values of a band-limited synchronous binary transmission signal Vt represented by a broken line in Fig. 1. Such a transmission signal may be obtained, for example, from a read apparatus for reading digital data stored on a magnetic or optical record carrier. Such a signal may also be obtained from a transmitting station of a communication system for the transmission of digital data. Such a transmission signal comprises a plurality of bit cells which are transmitted in synchronism with a channel clock, and which represent the transmitted digital data. For the recovery of the digital data from the series of samples is necessary to have information on the phase position of the channel clock at the sampling instants. This information can be derived from the positions of the crossings of a detection level Vref by the transmission signal. These crossings represent fixed phase positions of the channel clock. Hereinafter it will be described how the positions of the sampling instants are determined relative to the rising edges of a virtual reference-clock signal which is phase-locked to the channel clock. As a result of this phase locking these positions are correct measures of the phase positions of the channel clock at the sampling instants. In Fig. 1 this reference-clock signal bears the reference Cref. The arrows R indicate the positions of the sampling instants relative to the rising edges of the reference-clock signal. The arrows N indicate the positions of the sampling instants situated just before a detection-level crossing relative to this detection-level crossing. When ignoring a minor error the value of N can be determined by linear interpolation in conformity with the following relationship: where J (n) is the value of the sample just before the detection-level crossing and J (n+1) is the value of the sample just after the detection-level crossing. As is apparent from Fig. 2, the value for N defined by this relationship deviates only slightly from the actual value for the interval N′ between the level crossing and the sampling instant just before the level crossing. P indicates the interval between a detection-level crossing and the nearest rising edge of the reference clock signal. P, N and R are related as follows: P = N - R if - 1/2 L (N - R) + 1/2 L (2a) P = N - R + L if (N-R) < - 1/2 L (2b) P = N - R - L if (N-R) > + 1/2 L (2c) where L = T + Q. Relationships (2b) and (2c) apply to the situation in which a sampling instant is situated between a rising edge of the reference-clock signal Cref and a detection-level crossing (see Fig. 3). This results in a large difference between N and R, whilst in fact the actual interval between the rising edge and the level crossing is only small. Applying a correction by a value ± L corresponding to the period of the reference-clock signal yields a correct value for the interval between the rising edge and the detection-level crossing. The value for R(k+1) at a sampling instant can be derived as follows from the value for R(k) at the preceding sampling instant, the sampling interval T and a value Q representing the difference between the period L and the sampling interval T: R(k+1) = R(k) + Q if R(k) < T R(k+1) = R(k) - T if R(k) > T (3) Fig. 4a shows an example of the variation of R for the value of Q smaller than T and Fig. 4b for a value of Q larger than T. If the period L of the reference-clock signal does not correspond to the period of the channel clock this results in an increasing difference between N and R at the detection-level crossings. The difference between N and R is employed for correcting the value of Q after every detection-level crossing so as to reduce the difference between the period L of the reference-clock signal and the period of the channel clock. A satisfactory correction of Q is obtained by the set of equations (4): IN(m+1) = IN(m) + P(m) Q(m+1) = IN(m+1) + G. P(m) (4) In these equations m represents the successive detection-level crossing IN(k) is the sum of all the values of P determined previously and G is a constant. By iteratively correcting the value of Q the deviation P will be minimized, which means that the virtual reference clock is phase-locked to the channel clock. The rising and falling edges of the virtual reference-clock signal Cref then represent the boundaries between the bit cells and the centres of the bit cells respectively. The intervals R between the sampling instants and the next rising edges of the reference-clock signal Vref therefore always provide a correct indication of the phase position of the channel clock at the sampling instants. The data represented by the transmission signal Vt can be recovered simply from the variation of R and the values of the samples J. This may be effected, for example, by determining the number of bit cells between successive detection-level crossings and the associated sign. Alternatively, this may be effected, for example, by determining which samples are situated nearest the centres of the bit cells and by subsequently detecting the presence of bits having signs corresponding to the signs of specific samples. The samples situated nearest the centres of the bit cells can be selected simply from the values of R by determining for which samples the associated value of R is situated between the bounds B1(= ½ Q) and B2 (T +½ Q). These bounds B1 and B2 are situated symmetrically with respect to the value ½(T+Q), which value corresponds to the interval between the falling edge and the next rising edge of the reference-clock signal Cref. These falling edges indicatethe centres of the bit cells of the transmission signal V t . The number of bit cells between successive detection-level crossings can be determined simply by counting the number of samples for the associated value of R is situated between ½Q and ½Q + T. However, for counting the number of bit cells it is not necessary that the bounds B1 and B2 are equal to ½Q and ½Q + T respectively. It is satisfactory if the interval between the bounds B1 and B2 corresponds to T and the bounds are situated with the range of R, i.e. if the bounds are situated between the values 0 and the period L (=T + Q) of the virtual reference-clock signal Cref. If the bounds B1 and B2 are selected to be equal to Q and (T + Q) respectively the number of bit cells between the successive detection-level crossings can be determined by counting a number of times that R is incremented by the value Q between the successive detection-level crossings. Fig. 5 shows a device 1 embodying the invention for the regeneration of clock information in the form of the intervals R between the sampling instants and the rising edges of the reference clock,which is phase-locked to the channel clock. This Figure shows an interpolation circuit 2 to which the series of samples L in the form of digital codes is applied in synchronism with a system clock signal Cs. From the successive codes the interpolation circuit 2 detects whether the detection level Vref is crossed between the sampling instants corresponding to the successive codes. In the case of such a crossing the interpolation circuit 2 derives a measure of the interval N from the successive codes in conformity with relationship (1). Moreover, the interpolation circuit 2 then generates a detection signal Cd, which indicates detection of a level crossing. The interpolation circuit further generates a logic signal C t representing the sign of the penultimate sample applied. The output signal N in the form of a digital code is applied to first inputs of a difference circuit 3. The value R also in the form of a digital code is applied to the second inputs of the difference circuit 3. A code for the value of Q is applied to third inputs of the difference circuit 3. The difference circuit 3 computes the difference P from N, R and Q in conformity with the relationships (2) and via its output it supplies the value P in the form of a digital code to a sequential filter circuit 4, which in response to the simultaneous occurrence of the detection signal Cd and a pulse of the clock signal Cs derives a new value for Q from the code P in conformity with relationship (4) and applies a code for Q to a computing circuit 5, which in response to a pulse of the clock signal computes the next value for R in conformity with the relationships (3) and supplies this to the difference circuit 3. Fig. 6 shows an interpolation circuit in more detail. The interpolation circuit 2 comprises a first parallel-in parallel-out register 10 to whose data inputs the codes for the samples J are applied and to whose clock input the clock signal Cs is applied. The data outputs of the register 10 are coupled to address inputs 12 of a read-only memory 13 (ROM) and to the data inputs of a second parallel-in parallel-out register 14 which is also controlled by the clock signal Cs. The data outputs of the register 14 are coupled to the address outputs 15 of the memory 13. In response to pulses of the clock signal Cs the codes for the successive samples J are loaded into the register 10 and are subsequently loaded into the register 14 with a delay corresponding to one clock pulse, so that always the codes of two successive samples J are available. The codes of the two successive samples determine the address of the memory 13, which memory stores the corresponding value for N in a code for reach combination of codes representing two samples situated on opposite sides of the detection level Vref, said code being available via output 16. The most significant bits of the codes stores in the registers 10 and 14 indicate the sign of the value of the samples J. The most significant bits of the two codes are applied to an exclusive-OR gate 17 which supplies a signal Cd which indicates whether the applied most significant bits are of different signs, which means that the transmission signal Vt has crossed the detection level between the sampling instants corresponding to the codes.Moreover, a signal C t is supplied, which signal represents the most significant bit of the sample stored in the register 14 and, consequently, the sign of the penultimate sample applied. Fig. 7 shows an example of the difference circuit 3 in detail. The difference circuit 3 comprises a digital subtractor circuit 20 for determining the difference P′ between N and R. The output signal of the subtractor circuit 20 is applied to a first comparison circuit 22, a second comparison circuit 23, a subtractor circuit 24, an adder circuit 25, and a multiplex circuit 21. The comparison circuit 22 compares the code for P′ on the first inputs with a code for ½L = (T+Q)/2 and generates a detection signal Dp if P′ is larger than the value (T+Q)/2 of the code applied to the second input. The code for (T+Q)/2 together with the codes for -(T+Q)/2 and (T+Q) is derived from the code for Q and T by means of customary digital circuits (not shown). The comparison circuit 23 generates a detection signal Dm if P′ is smaller than -½L = -(T+Q)/2. The subtractor circuit 24 derives a code for the value P″ (= P′- (T+Q)) from the codes for (T+Q) and P′. In a corresponding manner the adder circuit derives a code for the value P> (= P′ + (T+Q)) from the codes for (T+Q) and P′. The codes for P″ and P> are also applied to the multiplex circuit 21. Depending on the detection signals Dp and Dm the multiplex circuit 21 always transfers that code of the codes P′ P″ and P> applied to the inputs which represent a value situated between (T+Q)/2 and -(T+Q)/2. The circuit shown in Fig. 7 detects whether the difference between N and R lies between the limits ½(T+Q) = ½L and -½(T+Q) = -½L. In most cases, the difference will be within these limits. However, in the sporadic cases that R indicates that the detection-level crossing is situated just before a sampling instant, while N indicates that the actual level crossing is situated just after a sampling instant, or vice versa, the detected difference P′ is not correct. If such an incorrect different P′ is detected, this value is corrected by the value (T+Q) or -(T+Q), so that no incorrect values for P are transferred to the filter circuit 4. In order to prevent incorrect values for P from being applied to the filter circuit 4 however, it is also possible to transfer, for example, only those values of P′ which are within said limits ± ½L and to reject all value of P′ which are not within these limits. Fig. 8 shows an example of a sequential filter circuit 4. The filter circuit 4 comprises a summing circuit 30 and a parallel-in parallel-out register 31, whose input receives the code of the value of P. The summing circuit is of a customary type comprising an adder circuit 38 and a parallel-in parallel-out register 39. The circuits 30 and 31 are controlled by a control signal Cf which by means of an AND-gate 32 and a delay circuit 33 is derived from the system clock signal Cs and the signal Cd which indicates detection of a detection level crossing, so that in response to a detection-level crossing the summing circuit 30 adds the value of P to the sum value IN already present in the summing circuit. Moreover, the code for the new value of P is loaded into register 31. The code of the value for P stored in register 31 is applied to an adder circuit 35 via a multiplier circuit 34. The code for the sum value IN is also applied to an adder circuit 35. The output of the adder circuit 35 provides a code for the corrected value of Q, determined in conformity with relationship (4). Fig. 9 shows in detail an example of a computing circuit 5. The computing circuit 5 comprises a multiplex circuit 40 to which the code for Q from the filter circuit 4 and a code for the value -T are applied. The outputs of the multiplex circuit 40 are coupled to the input of a summing circuit 41, which in response to a pulse of the system-clock signal Cs adds the value represented by the code on the inputs to a sum value R and applied a code for the value R to a comparison circuit 42. The summing circuit 41 is of a customary type comprising an adder circuit 43 and a parallel-in parallel-out register 44. The comparison circuit 42 generates a detection signal Cr if R is larger than T. The multiplex circuit 40 is controlled by the detection signal Cr in such a way that multiplex circuit 40 transfers the code for -T if Cr indicates that R is larger than T and the multiplex circuit 40 transfers the code for Q if Cr indicates that R is smaller than T. In this way the computing circuit 5 generates a code for the value of R in synchronism with the system-clock signal and hence in synchronism with the applied samples. Fig. 10 shows an example of an arrangement 50 which recovers the data represented by the samples J on the basis of the successive values of the intervals R. The arrangement 50 comprises a first comparison circuit 51 and a second comparison circuit 52 having an input to which the code for the intervals R are applied from the computing circuit 5. The codes for the bounds B1 and B2 are applied to the other inputs of the comparison circuits 51 and 52 respectively. As already described, ½Q is a suitable value for B1 and ½Q+T is a suitable value for B2. The codes for the bounds are derived from the codes for T and Q in a customary manner (not shown). The comparison circuit 51 is constructed in such a way that it exclusively generates a logic "1" signal if R is larger than B1. The comparison circuit 52 is constructed in such a way that it exclusively generates a logic "1" signal if R is smaller than B2. The signals generated by the circuits 51 and 52 are applied to an AND-gate 53 together with a system-clock signal Cs. The output of the AND-gate 53 is applied to the clock input of a counting circuit 54. Through a delay circuit 55 the signal Cd is applied to the reset input of the counting circuit 54 and to a control input of a memory 56 of the first-in first-out type, whose data input and data output are controlled independently from one another. The parallel outputs of the counting circuit 54, which represent the count of the counter, are applied to the data inputs of the memory 56. The signal CT generated by the interpolation circuit 2 and representing the sign of the, penultimately applied sample J is also applied to a data input of the memory 56. The count of the counting circuit 54 is incremented by one each time that a pulse is generated on the output of the AND-gate 54, which pulse indicates that the value of R corresponding to an applied sample is situated within the bounds B1 and B2. In response to the pulse of the signal Cd, which pulse indicates a detection-level crossing, the count is loaded into the memory 56 and the counting circuit 54 is set to zero. Moreover, together with the count the sign of the penultimate sample applied to the interpolation circuit 2 is loaded into the memory 56, so that the memory 56 is successively loaded with counts representing the number of bit cells between successive detection-level crossings and with the associated signs. Under control of a signal C u the counts and these associated signs can be read out of the memory 56 in the same sequence in which they have been loaded into the memory. The device in accordance with the present invention can be constructed entirely by means of digital elements, thus enabling the device together with the circuits for processing the recovered digital data to be incorporated simply in one integrated circuit. It is obvious that several modifications of the embodiments described are possible. For example, it is possible to construct the device by means of a programmable computing circuit, such as microcomputer. Obviously, the present invention is suitable for determining the phase positions of the channel clock at the sampling instants. However, the device in accordance with the invention also furnishes information on the time difference Q between the sampling instant and the period of the channel clock. Therefore, the value of Q may also be utilized for controlling the channel-clock frequency.

Claims: A device for the regeneration of channel-clock information from a series of samples which represent the signal values of a band-limited transmission signal (Vt) at equidistant sampling instants, which transmission signal (Vt) is synchronous with the channel clock, comprising means (5) for determining, in dependence on an input value (Q), reference phase positions (R) indicative for the phase positions of the sampling instants with respect to the phase of a virtual clock (C ref ), the differences (P) between two subsequent reference phase positions (R) corresponding to the input value (Q), detection means (10, 14, 17) for determining crossings of a detection level by the transmission signal (Vt) from the samples (J), interpolation means (12) responsive to level cross detections for determining the phase positions (N) of the sampling instants with respect to the phase of the channel clock from the samples (J) and means for determining the difference between the phase positions (N) and the corresponding reference phase positions (R), characterized by means (4) for adapting the input value (Q) in dependence on the differences (P) determined, such that the differences between the phase positions and the corresponding reference phase positions are substantially kept at a constant value. A device as claimed in claim 1, characterized in that the means (4) for adapting the input value comprise summing means (30) for forming the sum of the differences (P) and means (35) for deriving the the input value (Q) from at least the sum of the differences. A device as claimed in Claim 2, characterized in that the means (3) for determining the difference (8) comprise correction means (22, 23, 24, 25) for correcting the difference by a value (T+Q) corresponding to the period of the virtual reference clock in response to a detection of a difference larger than a value ((T+0)/2) corresponding to half the period of the virtual reference clock. A device as claimed in any one of the preceding claims, characterized in that the means (5) for determining the reference phase positions (R) are provided with comparing means (42) for determining the difference between the reference phase position (R(k)) determined and a value (T) corresponding to the sampling interval, the means (5) for determining the reference phase position (R) being adapted to determine the next phase position (R(k+1)) by modifying it by the input-value (Q) or a value (-T) corresponding with the sampling interval with a sign, a sign opposite to the sign of the input value (Q) in dependence on whether the difference determined by the said comparing means (42) are negative or positive respectively. An arrangement for the recovery of data represented by a sampled band-limited transmission signal which is synchronous with a channel clock, comprising a device as claimed in any one of the preceding claims. An arrangement for the recovery of data as claimed in claim 5, characterized in that the data-recovery arrangement comprises comparison means (51, 52) for determining whether the values of the reference phase positions are situated within bounds (1/2 Q; 1/2 Q+T) which are situated at an interval corresponding to the sampling interval (T) from each other and counting means (54) for counting the number of times that the reference phase positions (R) between two successive detection level crossings are situated within said bounds.

Inventors: KAHLMAN, JOSEPHUS ARNOLDUS HENRICUS MARIA, SCHOUHAMER IMMINK, KORNELIS ANTONIE
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: H04L7
IPC codes: G11B20, H04L7