MAC FORMAT WITH ALTERNATING DC LEVEL AND CLOCK RECOVERY SIGNALS

Abstract: Multiplexed analog component television signal where the clock recovery signal and the DC restoration signal alternate in different lines during the horizontal blanking interval (21). The clock recovery signal and the DC restoration signal could alternate line by line or the clock recovery signal could be sent every Nth line with the DC restoration signal transmitted on lines therebetween.

Description: MAC FORMAT WITH ALTERNATING DC LEVEL AND CLOCK RECOVERY SIGNALS BACKGROUND OF THE INVENTION Technical Field The present invention is directed to improving immunity to channel dis¬ tortions of multiplexed analog component television signals by independently transmitting a clock recovery signal and a DC restoration signal during the hori¬ zontal blanking interval of a video line. More particularly, the clock recovery signal and the DC restoration signal are transmitted on independent lines. Background Information Time division multiplexed analog component (MAC) television signals, a typical line of which is shown with reference of Figure 1, includes a horizontal blanking interval (HBI) 12, in which no picture information is transmitted, fol¬ lowed by a chrominance signal 14 and a luminance signal 16, either of which may be time-compressed. Between the chrominance and luminance signals is a guard band 18 to assist in preventing interference between the two signals. The MAC color television signal of Figure 1 is obtained by generating con¬ ventional luminance and chrominance signals (as would be done to obtain a con¬ ventional NTSC or other composite color television signals) and then sampling and storing them separately. Luminance is sampled at a luminance sampling fre¬ quency and stored in a luminance store, while chrominance is sampled at a chrominance sampling, frequency and stored in a chrominance store. The luminance or chrominance samples may then be compressed in time by writing them into a store at their individual sampling frequency and reading them from the store at a higher frequency. A multiplexer selects either the luminance store or the chrominance store, at the appropriate time during the active line period, for reading, thus creating the MAC signal. If desired, audio samples may be transmitted during the HBI; these are multiplexed (and may be compressed) in the same manner as the video samples. The sample rate at which all samples occur in the multiplexed MAC signal is called the MAC sampling frequency. In the transmission of all typical MAC signals, a reference clock fre¬ quency burst is also transmitted during the HBI. The reference burst is typically about ten cycles of a constant amplitude sinusoid at the MAC sampling fre¬ quency and is used at the receiver for both clock recovery and DC restoration (clamping). The frequency of the reference clock burst is used for clock recovery, while the average of the reference clock burst (ideally zero) is used for clamping. It is of great importance to accurately DC restore the video signal after transmission and clamp on the luminance (or pedestal) value upon which these reference clock burst sinusoids are superimposed. The chrominance values obtained for transmission are relative to a given reference brightness level, rep¬ resented by the DC level of the signal. Accordingly, it is necessary that the received signal be referred to that reference level to provide accurate recon¬ struction of the received signal on a display. This reference level is hereinafter referred to as the DC restoration value. Several problems exist with the prior art method of obtaining the DC res¬ toration value by averaging the reference clock burst. For example, if the discriminator at the receiver (Foster Sealy or FM discriminator) is misaligned, the average value of the reference clock burst is not at its ideal zero reference point. Additionally, if a large data spike either before or after the reference clock burst occurs, when low pass ilter the clock burst, the data spike will cause interference and shift the DC level. Furthermore, any other distortion classi¬ cally inherent in FM discriminators will cause an error to occur when the DC restoration value is obtained by averaging the reference clock burst. This error, sometimes referred to as chrominance/luminance intermodulation, is a non-linear distortion particularly likely to be encountered in FM discriminators as a result of misalignment or drift. It may also occur in a wide variety of baseband video amplifiers, especially as a result of di ferences in circuit component value tolerences. A test signal has been developed specifi¬ cally to measure this distortion in an FM demodulator. See Int'l Radio Consulta¬ tive Comm., Recommendations And Reports Of The CCIR, Transmission of Sound Broadcasting and Television Signals Over Long Distances, Vol. xπ, pps. 13, 20 (XVth Plkenary Assembly, Geneva 1982). One solution- to this problem is to provide a separate clock recovery signal and DC restoration signal in each transmitted line. If the reference clock burst and the DC restoration signal were both about 3 us per line, these two intervals would represent approximately 10% of the typical 63.5 us line. This approach is uneconomical; not only will the bandwidth required for transmission be increased, but the signal-to-noise ratio would also be increased, requiring a larger antenna reflector and/or a more costly Low Noise Amplifier. Summary Of The Invention The problems inherent with trying to obtain the DC restoration value rom the reference burst lie from the fact that the two values are not related, as well as from the distortions classically inherent in FM discriminators. Accord¬ ingly, it is an object of the present invention to transmit the clock recovery sig¬ nal and the DC restoration signal independently of each other. It is further an object of the present to transmit these values on separate lines. According to the objects of the present invention, I have found that the integrity of the television receiver's system is not compromised if the clock recovery signal is not transmitted on every line. In fact, a substantial majority of the transmitted lines per frame need not have the clock recovery signal present for proper operation. Accordingly, the problems inherent in the prior art are avoided by independently transmitting the clock recovery signal and the DC restoration signal on separate lines during a portion of the horizontal blanking interval of the respective lines. The clock recovery signal and the DC restoration signal could be transmitted on alternate lines or the clock recovery signal could be sent every Nth line with the DC restoration signal transmitted on lines therebetween. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an amplitude — vs. — time diagram of a single video line of a MAC signal. Figure 2 illustrates a line of a MAC video signal. Figure 3 illustrates a detailed view of the horizontal blanking interval of the line shown in Figure 2. Figure 4 illustrates the block diagram of the circuitry required to recover the clock recovery signal and the DC restoration signal transmitted during the horizontal blanking interval of Figure 2. DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to Figures 2 through 4, the transmission and recovery of the clock recovery signal and DC the restoration signal will now be described. As shown in Figure 2, a line of a MAC video signal comprises a time segment for horizontal blanking interval (HBI) 21, chrominance component 22, guard band 23 and luminance component 24. Turning now to Figure 3, a detailed view of the horizontal blanking interval of the line shown in Figure 2 is now described with reference to the multiplexed analog component transmission system developed by the assignees of the present invention, typically referred to as B-MAC. As shown in Figure 3, the horizontal blanking interval comprises data segments 31, 32 and 33, separated by guard bands 34 and 35. In the preferred embodiment, the HBI comprises 78 symbols divided as 47 4-level data symbols for data segment 31; 20 4-level data symbols for data segment 32; 7 4-level data symbols for data seg¬ ment 33; and 2 symbols for each guard band 34 and 35. Data segment 32 is used to store either the clock recovery signal or the DC restoration signal, depending upon the transmitted line in question. During transmission of the clock recovery signal, data segment 32, which is preferably approximately 2 us in duration, comprises a series of alternating minima and maxima of the 4-level data values and represents a clock recovery signal having constant amplitude and a fre¬ quency of the MAC sampling frequency. During the transmission of the DC res¬ toration signal, data segment 32 preferably comprises twenty symbols of data at 50 IRE (i.e., the exact center of the dynamic range). Data segments 31 and 33 include other data, such as audio and/or scrambling information, a description of which is both known in the art and not necessary for a full understanding of the present invention. Turning now to Figure 4, the block diagram of the circuitry at the receiver required to recovery the clock recovery signal and the DC restoration signal which was transmitted during the horizontal blanking interval as just described is now discussed. In the preferred embodiment, the clock recovery signal is transmitted on every other line, and the received B-MAC signal is input at line 41. Divide-by-N counter 42 is preferably a divide-by-2 counter and is reset according to the field rate reset pulse and is clocked by the line frequency f^. The outputs of counter 42 are arranged such that AND gates 43 and 44 are enabled mutually exclusive of each other by tying one of the two inputs to Q and Q-bar, respectively. The other input to AND gates 43 and 44 is the keying pulse of line 45 which occurs during data segment 32 (of Figure 3) of the horizontal blanking interval and has a duration of the twenty symbol data segment, preferably about 2 us. The keying pulses are generated by a key pulse generator (not shown), the construction of which will be obvious to those skilled in the art. When a irst line is received at input 41, and assuming that the first line contains a clock recovery signal as described above, AND gate 43 is enabled and the clock recovery signal is allowed to pass through transmission gate 46 to the phase-locked loop circuitry (not shown) connected to line 47. During alternately occuring lines, AND gate 44 is enabled, thereby turning on transistor 48 and allowing the 50 IRE signal, pro¬ duced by input sides 49a and 49b of transmission gate 49 to pass through the sys¬ tem at line 50. It is to be noted that the minima and maxima voltage values cou¬ pled to points 49a and 49b, respectively, represent the minima and maxima of the four-way data contained in the transmitted line of Figure 2. Although the preferred embodiment has been described with reference to transmitting the clock recovery signal and the DC restoration signal on alternate lines, it is also possible to transmit the clock recovery signal on every third line, with the DC restoration signal transmitted on lines therebetween. In an embodi¬ ment of this type, divide-by-N counter 42 would be replaced with a divide-by- three counter, and the reset pulse into the counter would become the frame rate reset pulse (i.e., reset on line 1 of each field). It is still further possible to transmit the clock recovery signal on every Nth line with the reset pulse into clock counter 42 preferably being the frame rate reset pulse provided that the number (N+l) is an integer multiple of the number of lines per frame. Additionally, it is also possible to transmit the DC restoration signal every Nth line, with the clock recovery signal transmitted on lines therebetween. Although illustrative embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments. Vari¬ ous changes or modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention.

Claims: CLAIMS What I Claim As My Invention Is: 1. In a time division multiplexed analog component video signal having a line which includes a luminance component, a chrominance component and a horizontal blanking interval which comprises either a clock recovery sig¬ nal or a DC restoration signal, but not both, the method of transmitting multiple lines of the video signal comprising the steps of: transmitting a first line of the video signal where in the horizontal blanking interval comprises the clock recovery signal; and transmitting N subsequent lines of the video signal wherein the horizontal blanking interval comprises the DC restoration signal. 2. The method of claim 1, wherein (N + 1) is an integer multiple of the number of lines per frame of the video system. 3. The method of claim 1, wherein N = 1. 4. The method of claim 1, wherein N = 2. 5. The method of claim 1, wherein the DC restoration signal is a sig¬ nal corresponding to 50 IRE. 6. The method of claim 5 wherein (N + 1) is an integer multiple of the number of lines per frame of the video system. 7. The method of claim 5, wherein N = 1. 8. The method of claim 5 wherein N = 2. 9. In a video signal receiver for receiving multiple lines of a time division multiplexed analog component video signal having either a clock recovery signal or a DC restoration signal transmitted during a predetermined portion of each line's horizontal blanking interval, a device for recapturing the clock recovery signal and the DC restoration signal comprising: first pulse generating means for generating a first enable pulse whose timing and duration correspond substantially to the predetermined portion of each line's horizontal blanking interval; second pulse generating means having first and second output ports for generating a second enable pulse having a duration corresponding to the transmitted line time and alternately outputting said second enabled pulse at said first and second output ports after every N line time durations; first coincidence gate coupled to said first pulse generating means and the first output port of said second pulse generating means to output a first gating signal during the coincidence of said first enable signal and said second enable signal at the first output port; first gating means coupled to said first coincidence gate for receiving the transmitted video lines and outputting a portion of the video line corresponding to said first gating signal; second coincidence gate coupled to said first pulse generating means and the second output port of said second pulse generating means to out¬ put a second gating signal during the coincidence of said first enable signal and said second enable signal at the second output port; and second gating means coupled to said second coincidence gate for outputting a 50 IRE value signal corresponding to the duration of said second gating signal. 10. The device of claim 9, wherein N = 1. 11. The device of claim 9, wherein N = 2. 12. The device of claim 9, wherein (N + 1) is an integer multiple of the number of lines per frame of the video system. 13. The device of claim 9, wherein the transmitted video lines are received at said second gating means. 14. The device of claim 9, wherein said portion of the video line corre¬ sponding to said first gating signal output from said first gating means is the clock recovery signal. * 15. The device of claim 9 wherein said 50 IRE signal corresponding to the duration of said second gating signal output from said second gating means is the DC restoration signal.

Inventors: RHODES CHARLES W, RHODES, CHARLES, W.
Applicants: SCIENTIFIC ATLANTA, SCIENTIFIC ATLANTA, INC.
Application year: 1987
Main classification: H04N11
IPC codes: H04N7, H04N9, H04N11