FLIP-FLOP CIRCUIT

Abstract: Input and output terminals of two inverters (1, 2) connected between corresponding data input terminals (7, 8) and corresponding data output terminals (12, 11) are cross-connected. Latch switches (3, 4) are inserted between the inverters and the corresponding data input terminals. Hold switches (5, 6) are inserted in the cross-connected portion of the two inverters. The latch switches (3, 4) are turned on/off in synchronism with a latch input (9) while the hold switches (5, 6) are turned on/off in synchronism with a hold input (10).

Description: Background of the Invention The present invention relates to a flip-flop circuit and, more particularly, to a flip-flop circuit having a short signal propagation delay time. Conventional flip-flop circuits will now be described with reference to Figs. 1 to 3 of the accompanying drawings in which:- Fig. 1 is a circuit diagram showing a conventional flip-flop circuit; Fig. 2 is a timing chart for explaining the operation of the circuit in Fig. 1; and Fig. 3 is a circuit diagram showing another conventional flip-flop circuit. Fig. 1 shows a static flip-flop circuit according to a conventional technique. In Fig. 1, the flip-flop circuit is constituted by two inverters 21 and 22, and two switches 23 and 24. In this flip-flop circuit, the switch 23 is operated in response to an input to a latch input terminal 26 to read a signal at a data input terminal 25, and the switch 24 is operated in response to an input to a hold input terminal 27 to hold the data. Fig. 2 shows the operation of the circuit shown in Fig. 1. Since the flip-flop circuit in Fig. 1 performs static operation by holding the data using the two inverters 21 and 22, delay times TD1 and TD2 of the two inverters are added to switching operation time, thereby increasing a total delay time, as shown in a timing chart in Fig. 2. Fig. 3 shows a dynamic flip-flop circuit as another conventional example. Referring to Fig. 3, the flip-flop circuit is constituted by an inverter 31 and a switch 32. In the flip-flop circuit, the switch 32 is operated in response to an input to a latch input terminal 35 to read a signal at a data input terminal 34, and information is held by a capacitor 37 connected to the input of the inverter 31. The held information is then held by the next flip-flop circuit by a switch 33 operated in response to an input to an input terminal 36. A total delay time of the flip-flop circuit having the above arrangement is determined by a delay time of the inverter 31. However, a loss of information may occur at a low frequency because the information held by capacitor 37 is discharged at the low frequency. Accordingly, operation at a low frequency cannot be performed. In U.S. Patent Specification No. 4,506,167, which was issued on March 19 1985, there is proposed a high speed logic latching circuit which consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. It is an object of the present invention to provide a static flip-flop circuit in which the above-described conventional drawbacks are eliminated and the operation speed is increased by shortening the delay time. In an embodiment of the invention to be described there is provided a flip-flop circuit comprising, a first pair of input terminals for respectively receiving a first pair of input data signals; a second pair of input terminals for respectively receiving a second pair of input data signals which pair is complement of the first pair of input data signals, first and second output terminals, a NOR gate whose output terminal is connected to said first output terminal, a NAND gate whose output terminal is connected to said second ouput terminal, two pairs of latch switches respectively inserted between said first pair of input terminals and two input terminals of said NOR gate, and between said second pair of input terminals of said NAND gate, said two pairs of latch switches being controlled by a latch signal to be turned on/off, and two pairs of hold switches respectively inserted between said two input terminals of said NOR gate and said output terminal of said NAND gate and between said two input terminals of said NAND gate and said output terminal of said NOR gate, said two pairs of hold switches being controlled by a hold signal to be synchronously turned on/off. An embodiment of the invention will now be described, by way of example, with reference to Fig. 4 of the accompanying drawings in which:- Fig. 4 is a circuit diagram showing a basic arrangement of a flip-flop circuit. The flip-flop circuit in Fig. 4 receives a pair of input data signals S IN-a and S IN-b and a pair of complementary input data signals S IN-a and S IN-b , and outputs output data Q and Q . In Fig. 4, input terminals 7a and 7b serve to receive the input data signals S IN-a and S IN-b , respectively, and are connected to the two input terminals of a NOR gate 13 via switches 3a and 3b. Input terminals 8a and 8b serve to receive the input data signals S IN-a and S IN-b , respectively, and are connected to the two input terminals of a NAND gate 14 via switches 4a and 4b. The switches 3a, 3b, 4a, and 4b are controlled by a latch signal S L to be synchronously turned on/off. The two input terminals of the NOR gate 13 are commonly connected to the output terminal of the NAND gate 14 via the switches 5a and 5b. The two input terminals of the NAND gate are commonly connected to the output terminal of the NOR gate 13 via switches 6a and 6b. The switches 5a, 5b, 6a, and 6b are controlled by a hold signal S H to be synchronously turned on/off. According to the flip-flop circuit, NAND and NOR outputs can be respectively obtained at the output terminals 11 and 12 by applying the input data signals S IN-a and S IN-b to the input terminals 7a and 7b, respectively, and applying the input data signals S IN-a , S IN-b to the input terminals 8a and 8b, respectively. A delay time of the flip-flop circuit according to the present invention is determined by that of a single inverter in spite of its static operation. Therefore, problems such as loss of information can be solved, and operation at a low frequency can be performed while realizing a high-speed, reliable operation.

Claims: A flip-flop circuit comprising: a first pair of input terminals for respectively receiving a first pair of input data signals; a second pair of input terminals for respectively receiving a second pair of input data signals which pair is complement of tile first pair of input data signals; first and second output terminals; a NOR gate whose output terminal is connected to said first output terminal; a NAND gate whose output terminal is connected to said second output terminal; two pairs of latch switches respectively inserted between said first pair of input terminals and two input terminals of said NOR gate, and between said second pair of input terminals and two input terminals of said NAND gate, said two pairs of latch switches being controlled by a latch signal to be turned on/off; and two pairs of hold switches respectively inserted between said two input terminals of said NOR gate and said output terminal of said NAND gate and between said two input terminals of said NAND gate and said output terminal of said NOR gate, said two pairs of hold switches being controlled by a hold signal to be synchronously turned on/off.

Inventors: ASAZAWA, HIROSHI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1987
Main classification: H03K3
IPC codes: H03K3