DIFFERENTIAL IMPEDANCE NEUTRALIZATION CIRCUIT

Abstract: An impedance neutralization circuit produces correction currents to compensate for the effects of parasitic impedance on the output voltage of an amplifier. In the described embodiment, the neutralization circuit includes a pair of emitter followers, one coupled to the collector of each transistor of a common base amplifier for sensing the output voltage at each collector. A pair of transistors are coupled one to each emitter follower for applying the sensed voltage across a neutralizing impedance proportional to the parasitic impedance seen at the collector of the opposite transistor of the common base amplifier. The voltage applied across the neutralizing impedances produces a correction current. The correction current is summed with a distortion current of proportional amount but opposite sign produced by the output voltage applied across the parasitic impedance to produce a substantially error-free output voltage.

Description: FIELD OF THE INVENTION This invention generally relates to differential amplifiers. More particularly, this invention relates to a circuit for neutralizing undesired parasitic impedances which result from using large area devices in such amplifiers. BACKGROUND OF THE INVENTION The area of a transistor device within a differential amplifier circuit is normally minimized to reduce the effect of parasitic impedances such as collector-base capacitance C cb and collector-substrate capacitance C cs on the speed of the device. The larger these capacitances, the lower the bandwidth of the output signal. A smaller device, however, may not be optimally sized for the standing current density in the device. A mismatch of device area to current density lowers the transition frequency f T of the device from its maximum frequency and thus limits the device bandwidth. The standing current also determines the amount of load resistance and voltage swing that can be provided by the circuit. A number of tradeoffs therefore exist in the prior art among speed, bandwidth and maximum load of a device. The present invention avoids these tradeoffs by neutralizing the effects of the parasitic capacitances. The device area can therefore be sized to accept the desired standing current whose density is chosen in response to the load resistance and projected voltage swing. The closest prior art known to the applicants is shown in:- Dr.H. Barkhausen: "Lehrbuch der Elektronen-Röhren", 2. Band: Verstärker, Verlag S. Hirzel/Leipzig 1933, 4. Auflage, pages 214-216 and page 256, Figure 113, which describes a parasitic impedance neutralization circuit for an amplifier using vacuum tubes. The circuit provides sensing means at the input terminal of an amplifier in order to pre-distort the input signal and neutralize parasitic impedances in the amplifier. Further circuits for neutralizing the effects of undesired parasitic impedances in differential devices are known form US-A-3 531 733 and US-A-4 517 524. SUMMARY OF THE INVENTION An object of the invention, therefore, is to neutralize the effects of parasitic impedance on the operation of a transistor device. Another object of the invention is to enable a transistor device to be sized to accept the desired standing current to maximize the transition frequency of the device. Yet another object of the invention is to provide a parasitic impedance and neutralization circuit whose parameters are easily determined. To achieve these objects, a parasitic impedance neutralization circuit according to Claim 1 is provided. The parasitic impedance neutralization circuit includes a means for sensing an output signal at each of the two output terminals of a differential amplifier and reproducing each output signal in isolation from each output terminal. Additional means coupled to the sensing means applies the isolated output signal from each terminal across neutralizing impedances in the form of active devices, the neutralizing impedances being proportional to the parasitic impedances at each output terminal. This applied output signal produces a correction signal proportional but of the opposite sign to the distortion signal produced by the parasitic impedance at the opposite terminal. The correction signal is passed to the opposite terminal to be summed with the distortion signal and provide a substantially error-free output signal. In a preferred embodiment of the invention, the output voltage at each output terminal is sensed and isolated from the output terminal by an emitter follower. The isolated voltage is then applied by another transistor across a neutralizing impedance to produce the correction current. The neutralizing impedance is matched to the parasitic impedance by using a circuit element matched to the element producing the impedance. For example, in a differential amplifier, the neutralizing impedance is produced by using a transistor matched to the transistor of the amplifier from which the output voltage is taken. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a differential amplifier including an impedance neutralization circuit according to the invention. DETAILED DESCRIPTION Fig. 1 shows a common base amplifier 10 that includes a neutralization circuit according to a preferred embodiment of the invention. The differential common base amplifier 10 is merely one example of amplifiers with which the neutralization circuit may be used. The neutralization circuit, which comprises transistor Q₃ through Q₈, may also be used with other differential amplifiers such as variable gain stages as well. To review briefly the operation of a common-base differential amplifier 10 comprising Q₁ and Q₂, the input signal is provided through currents +I in and -I in which each include a standing or bias current portion and an input signal portion. These currents are produced by a differential stage so the increase in current in one source such as +I in is accompanied by a corresponding decrease in current in -I in . A DC biasing voltage V B , negative in this embodiment, is supplied to each transistor base to render Q₁ and Q₂ conductive. These transistors are matched to draw equal amounts of current when no input signal is present on +I in and -I in . The input signal is transmitted through Q₁ and Q₂ to output terminals at the collector of each transistor, where the input signal can be sensed as a differential voltage measured from +V o to -V o , respectively. +V o and -V o are produced by the change in current through equal load resistors R₁ and R₂ connected to each output terminal. V o therefore includes a DC bias portion and a signal portion. The impedance affecting +V o and -V o at each terminal, however, is not only the load resistance R₁ and R₂. At the first output terminal, for example, Q₁ includes a parasitic impedance that is in parallel to R₁. This impedance comprises a collector-base capacitance C cb and a collector-substrate capacitance C cs , capacitances that cause midfrequency defects in the gain of the differential amplifier 10. This effect is especially pronounced in large area devices, where these capacitances are proportionately larger. In a physical sense, these capacitances produce a distortion signal at the output terminal by absorbing and providing current as +V o changes in response to the input signal. The distorting effect of this capacitance is best seen by simulating the circuit on a computer simulation program such as SPICE. The same distortion, but with opposite sign, occurs on -V o at the second output terminal. The neutralization circuit that comprises transistors Q₃ through Q₈ neutralizes the effect of the capacitances on +V o and -V o . Q₃ is an emitter follower that senses the signal voltage +V o at the first output terminal and reproduces +V o in isolation (at a slightly lower DC bias) so that +V o is not affected by the isolated voltage. Q₃ is biased by a standing current source I B1 . The voltage +V o is then transmitted to Q₅, which applies +V o across the collector of Q₇. The parasitic output impedance of Q₇ is proportional to the impedances of Q₁ and Q₂. In this embodiment the impedances can be equal because Q₇ is chosen to match those transistors. Q₇ is biased by a voltage -V cs and a current source I B3 at a level sufficient to provide and absorb currents as required by C cb and C cs . The collector of Q₅ is cross coupled to the second output terminal to pass a correction current to the terminal, the correction current produced by applying +V o across the impedance of Q₇. Similarly, Q₄ is an emitter follower biased by current source I B2 . Q₄ senses -V o at the second output terminal and reproduce -V o in isolation from the terminal. Because Q₈ is matched to Q₂, the parasitic output impedance of Q₈ is proportional to that of Q₁ and Q₂. In this embodiment the impedances can be equal because of the transistor matching. Q₈ is biased by the voltage -V cs and a current source I B4 at a level sufficient to provide and produce currents as required by C cb and C cs . The collector of Q₆ is cross coupled to the first output terminal to pass a correction current to the terminal, the correction current produced by applying -V o across the impedance of Q₈. In the operation of the neutralizing circuit, the correction currents are summed at each terminal with distortion currents that are proportional but of opposite sign. This proportion can be an equal proportion. For example, when a differential signal is applied to amplifier 10, +V o will rise (or fall) and -V o will correspondingly fall (or rise). As +V o rises at the first output terminal, it must charge C cb and C cs which thereby produce a distortion current that affects the rise of +V o . Correspondingly, -V o falls at the second output terminal and causes C cb and C cs to discharge a distortion current that affects the fall of -V o . These distortion currents are proportional but of opposite sign. Correction currents are produced in response. As +V o rises, it is applied across the neutralizing impedance of Q₇ to produce a correction current proportional to the distortion current affecting -V o . The correction current is transmitted via the collector Q₅ to the second output terminal. In this case, the correction current is drawn out of the second terminal to match the current added thereto by C cb and C cs . As -V o drops, on the other hand, it is applied across the proportional neutralizing impedance of Q₈ to produce a correction current for the first terminal. In this case, the current drawn into the collector of Q₆ decreases because -V o has decreased, effectively "pushing" current into the first output terminal proportional to the distortion current drawn off the terminal by the charging of C cb and C cs . The coupling of the neutralizing circuit to the output terminals and amplifier 10 changes the DC bias portion, but this change does not affect the input signal portion. The DC voltage bias portion of +V o at the base of Q₅ is shifted a diode voltage drop below the DC bias portion of -V o at the second terminal to ensure Q₅ is biased properly. Similarly, the DC bias portion of -V o at the base of Q₆ is shifted below the DC bias portion of +V o at the first terminal to ensure proper operation of Q₆. The neutralization circuit 12, of course, is not limited to matching parasitic impedance of a bipolar transistor in a differential amplifier. The circuit could as well be used for matching parasitic impedances produced by other elements such as Darlington pairs, field effect transistors, passive devices, wiring or interconnections.

Claims: A parasitic impedance neutralization circuit for a differential device having a pair of output terminals, each output terminal providing an output signal and having a parasitic impedance that adds a distortion signal to the output signal, the neutralization circuit being characterized by: sensing means (Q3, Q4) for sensing the output signal at each of the output terminals and reproducing each output signal in isolation from the output terminals; neutralizing impedances (Q7, Q8) in the form of active devices, said neutralizing impedances being proportional to the parasitic impedances at each output terminal; and applying and passing means (Q5, Q6) coupled between the neutralizing impedances and the sensing means and to the output terminals for applying the isolated output signal from each terminal across a neutralizing impedance to produce a corresponding correction signal proportional to but opposite in sign to the distortion signal produced by the parasitic impedance at the opposite terminal and for passing each correction signal to the opposite output terminal to be summed with the output signal so that the distortion signal is neutralized to provide a substantially error-free output signal. The neutralization circuit of claim 1 wherein the sensing means (Q3, Q4) comprises a pair of emitter follower configured transistors, each transistor having the base coupled to one of the output terminals to receive the associated output signal and produce the associated isolated output signal at the emitter. The neutralization circuit of claim 1 wherein the neutralizing impedances (Q7, Q8) comprise a pair of common base configured transistors, each transistor having the collector coupled to the sensing means (Q3, Q4) via the applying and passing means (Q5, Q6) to receive the associated isolated output signal and having a bias current applied so that the transistor provides and absorbs currents as required by the parasitic impedance of the associated output terminal. The neutralization circuit of claim 1 wherein the applying and passing means (Q5, Q6) comprises a pair of common base configured transistors each transistor being coupled between the sensing means and one of the neutralizing impedances (Q7, Q8), and having the base coupled to receive the associated isolated output voltage, the emitter coupled to one of the neutralizing impedances (Q7, Q8), and the collector cross-coupled to the opposing output terminal to provide the correction signal for offsetting the distortion signal.

Inventors: QUINN, PATRICK ALLEN
Applicants: TEKTRONIX, INC.
Application year: 1987
Main classification: H03F1
IPC codes: H03F1, H03F3