DIGITAL PULSE CIRCUIT

Abstract: N digital signals are input in parallel and have phases that are different each by about 1/N of the predetermined quantity, so that the difference in phase among the digital signals will be greater than a predetermined phase difference, to enable only two signals that may rise or break with the change in the quantity to be measured to eliminate the effect of noise superposed on these signals. N digital signals are brought into synchronism with one another by a clock pulse having a predetermined period. The N digital signals are alternatively brought into synchronism with one another by clock pulses having a predetermined period, and are brought into synchronism with one another once again using the above clock pulses before they are issued. From among the signals that are once brought into synchronism with one another, only two signals that may rise or break with the change in the quantity to be measured are enabled. When these two signals change simultaneously, a logic circuit holding the output is provided so that the two signals will not be brought into synchronism in the second time until one of these signals returns to the initial state.

Description: The present invention relates to a digital pulse circuit. More particularly, it relates to a digital pulse circuit for maintaining a pulse width and for suppressing noises. The present invention is particularly advantageously used in a high-resolution pulse encoder circuit. Pulse encoders are used for precise position detection in numerical control (NC) apparatus or the like. In general, two types of pulse encoders are known; an incremental type and an absolute type. Recently, incremental type pulse encoders having a simple constitution and functioning substantially as an absolute type, have been proposed. (Cf. JPA No.60-218027, and No.218029) As shown in Fig.1, the pulse encoder as mentioned above has a rotating code disc 111 which is fixed to a rotation axle which rotates in correspondence with a motion of an object and accordingly which rotates with the rotation axle. The pulse encoder is provided with a pair of light-emitting devices 112a,112b and a pair of light-detecting devices 113a,113b, at the both side of the rotating code disc 111. And each of the light-emitting devices 112a,112b and the corresponding light-detecting devices 113a, 113b confront each other with the rotating code disc 111 intervening therebetween. The circumference of the rotating code disc 111 is provided with translucent parts and non-translucent parts, and when the rotating code disc 111 is rotated, light emitted from the light-emitting devices 112a, 112b passes in part through the translucent parts of the rotating code disc 111 and is transformed to A-phase signal and B-phase signals, where the phase of B-phase signal differs by 90 ° from the phase of the A-phase signal. These signals then become sine wave signals D A and D B (as shown in Fig.2A and Fig.2B) at light-detecting device output amplifiers 114a and 114b, respectively. The A-phase signal precedes the B-phase signal by 90 ° in phase when the rotating code disc 111 rotates in the positive direction (as shown in Fig.2A), and the B-phase signal precedes the A-phase signal by 90° in phase when the rotating code disc 111 rotates in the negative direction (as shown in Fig.2B). The above sine wave signals D A and D B enter the rectangular pulse generating circuit 120. The rectangular pulse generating circuit 120, for example, is provided with a comparator for comparing the level of input signals with a predetermined threshold level, and thus, rectangular pulses P A and P B as shown in Fig. 2A and Fig.2B are obtained. The counter in NC apparatus detects the direction of the rotating code disc 111, namely, the counter determines the direction of motion of the object by the sign of the phase-difference between the above pulses P A and P B , and at every timing of leading (rising) edge and trailing (falling) edge of the pulses P A and P B , the count of the counter in NC apparatus is incremented if the positive direction is determined and is decremented if the negative direction is determined. Figures 3A-3H show the manner of counting at the counter in NC apparatus as mentioned above. The counting ( ±1) is made according to a combination of the level of one of the A-phase signal and the B-phase signal, and the direction of the transition of the level (leading edge or trailing edge of the pulses) in the other of the A-phase signal and B-phase signal. To obtain position-measurement information with a high resolution, first, a series of sine waves, each having a different phase and the phase of the succeeding wave being delayed by an constant phase difference from the preceding wave, are obtained from the aforementioned sine waves D A and D B , and the series of sine waves are applied to the aforementioned rectangular pulse generating circuit to obtain rectangular pulses with the abovementioned phase difference. Figure 4 shows a construction of an apparatus used to execute the abovementioned procedure. The apparatus consists of light-detecting devices 113 similar to the aforementioned light-detecting devices 113a, 113b, a light-detecting device output amplifiers 114, a comparator 121 for obtaining rectangular pulses with the aforementioned phase difference, a A/B-phase signal generating circuit 6 which transforms the rectangular pulses to A-phase and B-phase signals, with a 90 ° phase difference between one signal and another. By using the abovementioned apparatus and obtaining ten rectangular pulses, the phase of each pulse of which is delayed by 1/10 2/10, ···9/10 of the half cycle time of the aforementioned signals D A or D B (the pulse width of P A and P B ) from the signals D A and D B , respectively, the inventers formerly obtained a five times greater resolution than the resolution obtained by merely counting the aforementioned rectangular pulses shown in Figs.2A and 2B. Generally, when N is an even number, by obtaining a set of N rectangular pulses the phase of each pulse which is delayed from the aforementioned signals D A and D B by 1/N, 2/N, ··· N-1/N of the half cycle time of the signals D A or D B , an N/2 times greater resolution than obtained by counting the aforementioned rectangular pulses shown in Figs.2A and 2B, can be obtained, using the abovementioned apparatus. Figure 5 shows the set of ten rectangular pulses D₀,··· D₉ mentioned above. For example, obtaining sine waves having phases preceding (or delayed from) the aforementioned signals D A and D B by an arbitrary constant phase, is made possible by the construction shown in Fig.6, i.e., when sin ϑ is applied to one terminal of the series connection of resisters R₁ and R₂, and sin (ϑ + π/2)= cos ϑ is applied to another terminal of the series connection of resisters R₁ and R₂, the level of the connecting point of the resisters R₁ and R₂ becomes (R₁² +R₂²) ½ sin (ϑ+ tan ⁻¹R₁/R₂)/(R₁+R₂). This means that a sine wave with an arbitrary phase difference can be obtained when the resistance values of resistors R₁ and R₂ are suitably selected. The ten pulses D₀,··· D₉ obtained as mentioned above (Fig.5) are transformed to the two rectangular A-phase and B-phase pulses having a phase difference of 90 ° , so that a high resolution reading of a position measurement at the NC apparatus side becomes possible. These two rectangular A-phase and B-phase pulses can be obtained by the construction as shown in Fig.7. The A-phase pulse F A is obtained by applying each of D₀, D₂, D₄, D₆, D₈ to five input terminals of the construction of Fig.7, respectively and the B-phase pulse F B is obtained by applying each of D₁, D₃, D₅, D₇, D₉ to the five input terminals of the construction of Fig. 7, respectively (Fig.5). Figure 5 shows the timing relationship of these signals F A and F B and the abovementioned D₀, ··· D₉. However, in general, the amplitudes of the output sine waves D A and D B are not exactly equal, and these include offset voltages resulting from the light-detecting device or amplifier. In addition, the phase difference between D A and D B is not exactly 90 ° , i. e., there is some error in the phase difference between D A and D B due to an error in the production of each slit, relative position of the light-emitting devices 112a,112b and the light-detecting devices, or delay time of the light-detecting devices or the like. The abovementioned errors in the sine waves D A and D B and the phase difference between D A and D B have a large influence on the result when these two sine waves are transformed to the aforementioned N rectangular pulses. In this case, the above errors cause some changes in the timings of the leading edges or tailing edges among D₀, ··· D₉, and changes in the time intervals between any two of the leading edges and tailing edges. However, the NC apparatus which receives the aforementioned rectangular pulses F A and F B and which should count the leading edges and tailing edges, can not count same when the time interval between any leading edge and tailing edge of the rectangular pulses F A and F B becomes less than the limit (minimum countable time interval) τ ₀ determined by the cycle time of the reading clock in the NC apparatus (about 300nsec). Especially, in case of a high speed rotation, due to fluctuations in the aforementioned time intervals between the leading edges and tailing edges of the rectangular pulses F A and F B , the time intervals may become less than the limit τ ₀. Another problem comes from noise. As mentioned before, in the prior art, the rectangular pulses F A and F B are obtained as an output of the pulse encoder, by applying the set of D₀, D₂, D₄, D₆, D₈ or the set of D₁, D₃, D₅, D₇, D₉ to the logic circuit of Fig.7. Therefore, for example, when noise appears even in only one input signal among D₀, D₁, ··· D₉, the noise causes an influence directly on the output pulse F A or F B . As shown in Fig.8, when a noise appears in the signal D₈, which properly must be zero during the time interval between a leading edge of D₀ and a leading edge of D₂, an abnormal notch appears in the shape of F A , through the construction of Fig.7 as mentioned before. If the timing of the leading edge of F B is in the time interval where F A is low level due to the abovementioned noise, the NC apparatus counts "-1", judging the motion of the objective to be in the negative direction at the timing t₁, because F A rises due to the noise while F B is low level (cf.Fig.3H). Then the NC apparatus counts "-1", judging that the motion of the objective to be in the negative direction again at the timing t₂, because F B rises while F A is low level due to the noise (cf.Fig.3E), and the NC apparatus counts "-1", judging the motion of the objective to be in the negative direction once again at the timing t₃, because F A rises due to the noise while F B is low (cf.Fig.3E). If the noise mentioned above does not appear in the signal D₈, during the interval covering the abovementioned timings t₁, t₂, and t₃, the NC apparatus must count "+1" once, judging the motion of the objective to be in the positive direction at the timing t₂, because F B rises while F A is high level. However, when noise appears, the NC apparatus counts "-3" during the same interval. This means that, in the high-resolution pulse encoders of the prior art, an incorrect result may be output due to the deformation in the output wave from the light-detecting device or noise which is superposed on the digital signals. An object of the present invention is to provide a digital pulse circuit for deriving information by incremental pulses from waves output by a light-detecting device in a high-resolution pulse encoder, relating to an objective quantity to be measured, in which the time intervals between incremental pulses are maintained as equal to or longer than the minimum countable time interval in the apparatus which counts the output of the pulse encoder, and in which noise superposed on digital signals has no influence on the information relating to an objective quantity to be measured. EP-A-0076861, over which the present invention is characterised, discloses a digital signal synchronizer. According to the present invention, there is provided a digital pulse circuit which receives N input digital signals in parallel, where N is an even integer equal to or greater than 4, the circuit comprising: a clock pulse generator (7) which generates a clock pulse having a predetermined cycle time; and, first means for accepting the N input digital signals, synchronising each of the N input digital signals with the clock pulse, and holding the level of each signal until a new signal is accepted, to output N synchronised digital signals; characterised by: second means for enabling only two of said N input digital signals to be accepted by the first means in each clock cycle, said two digital signals being determined based on the immediately preceding levels of the N synchronised digital signals. With the above mentioned construction, the present invention permits the output pulses from a high resolution encoder to be maintained at time intervals of not less than the minimum countable time at the counter, and to suppress noise. BRIEF DISCRIPTION OF DRAWINGS Figure 1 shows the most basic composition of pulse encoder of the prior art; Fig.2A and Fig.2B show the shapes of the output waves of the pulse encoder in Fig.1; Figs.3A-3H show the manner of counting the outputs of the pulse encoder in the counter; Fig.4 shows the construction of the high resolution pulse encoder of the prior art; Fig.5 shows the shapes of the output waves of the comparators in Fig.4 and Fig.9, and the shapes of the output waves of the A/B-phase signal generating circuit; Fig.6 shows the principle of generating the sine wave having an arbitrary phase difference in the comparators in Fig.5 and Fig.8; Fig.7 shows the construction of the A/B-phase signal generating circuit in Fig.5 and Fig.8; Fig.8 shows the influence on the shape of the output by noise in the pulse encoder circuit of the composition of Fig.4; Fig.9 shows the construction for maintaining a pulse width and suppressing noise according to the present invention; Fig.10 shows an example of the construction of the digital pulse circuit for maintaining a pulse width and suppressing noise according to the first aspect of the present invention; Fig.11A and Fig.11B show an example of the construction of the enable signal output portion 2 in Fig.10 and Fig.14; Fig.12 shows the operation of the circuit in Fig. 10; Fig.13 shows an abnormal case which can occurs in the digital pulse circuit for maintaining a pulse width and suppressing noise according to the first aspect of the present invention; Fig.14 shows an example of the construction of the digital pulse circuit for maintaining a pulse width and suppressing noise according to the second aspect of the present invention; Fig.15 shows an example of the construction of the output-maintaining signal output portion 4; and Fig.16 shows the operation of the circuit in Fig. 14. BEST MODE FOR CARRYING OUT THE INVENTION Figure 9 shows the construction of the digital pulse circuit for maintaining a pulse width and suppressing noise according to the present invention, applied to pulse encoder circuit to solve the aforementioned problem in the composition of FIG.4 as mentioned before. In the construction of Fig.9, the digital pulse circuit 8 according to the present invention is inserted between the comparator of Fig.4 and the A/B-phase signal generating circuit 6. Figure 10 shows an example of the construction of the digital pulse circuit for maintaining a pulse width and suppressing noise according to the first aspect of the present invention. The digital pulse circuit in Fig.10 is provided with a clock generator 7 which generates clock pulses having a cycle time longer than the minimum readable time interval in a counter ( 400ns in this embodiment ). In this counter, the output of the pulse encoder in which the digital pulse circuit according to the present invention is used, is counted. In addition, the abovementioned digital pulse circuit has N clock-synchronizing portions 1₀,1₁, ··· 1 N-1 and an enable signal output portion 2. Each of the N clock synchronizing portions synchronizes the corresponding one of the N outputs D₀, D₁, ··· D N-1 from the aforementioned comparator 121 in Fig.9 by the clock pulse mentioned above. The enable signal output portion 2 receives N outputs D₀ ′ , D₁ ′ , ··· D N-1 ′ from the abovementioned N clock-synchronizing portions 1₀,1₁, ··· 1 N-1 , at N input terminals I₀, I₁, ··· I N-1 respectively. At N output terminals 0₀, 0₁, ··· 0 N-1 of the enable signal output portion 2, the corresponding output signal to each of these input signals appears. The enable signal output portion 2 recognizes two signals one of which can change its state ( rise to high level or fall to low level ) in the next operation, among the aforementioned N digital signals D₀, D₁, ··· D N-1 , and the enable signal output portion 2 outputs the enable signals which enable only the above two signals to enter the abovementioned N clock-synchronizing portions 1₀,1₁, ··· 1 N-1 . The N signals D₀ ′ , D₁ ′ , ··· D N-1 ′ are obtained by synchronizing each of the N signals D₀, D₁, ··· D N-1 by the abovementioned clock pulse, where the N signals D₀, D₁, D N-1 , as shown in FIG.5, invert their levels every time a constant quantity of change in the objective quantity to be measured occurs, and phase differences between any successive signals among these N signals D₀, D₁, ··· D N-1 correspond to about (including the aforementioned fluctuation in the output wave from the light-detecting device ) 1/N of the abovementioned constant quantity. The enable signal output portion 2 recognizes the states of the signals D₀ ′, D₁ ′ , ··· D N - 1 ′ at any timing. For example, if D₀ ′ =D₁ ′ = ··· =D i ′ =0, and D i+1 ′ = ··· =D N-1 ′ =1 ( i=0,1, ···N-2 ) the two signals, either of which can change its state in the next operation among the aforementioned N digital signals D₀, D₁, ··· D N-1 , are D i ( 0→1), and D i+1 ( 1 →0). In correspondence with this recognition, the enable signal output portion 2 outputs "1" from the output terminals 0 i and 0 i+1 among the aforementioned N output terminals 0₀, 0₁, ··· 0 N-1 , and outputs "0" from the other terminals except 0 i and 0 i+1 . It will be readily understood that the enable signal output portion 2 in Fig.10 as mentioned above, can be realized by the construction shown in Fig.11A and Fig.11B. Each of the signals P₀, P₁, P₂, ··· shown in Fig.11A, becomes "1" when the outputs ( D₀ ′ , D₁ ′, ··· D N-1 ′) of D-flip-flop circuits 10₀, 10₁, ···10 N-1 , are ( 0,0,0, ···0 ), ( 1,0,0, ···0 ), ( 1,1,0, ···0 ) , · · · respectively, each of the signals P N-1 , P N , P N+1 , ··· shown in Fig. 11A, becomes "1" when the outputs ( D₀ ′, D₁ ′ , ··· D N-1 ′ ) are ( 1,···1,0 ), ( 1, ···1 ), ( 0,1, ··· 1 ), · · · respectively, and each of the signals P 2N-2 , P 2N-1 shown in Fig.11A, becomes "1" when each of the outputs ( D₀ ′ , D₁ ′ ,··· D N-1 ′) is ( 0, ···0,1,1 ), ( 0, ···0,0,1 ), respectively. These signals P₀, P₁, ··· P N-1 , P N , P N+1 , ···P 2N-1 are obtained by the construction consists of N inverters 24₀, 24₁, ···24 N-1 and 2N AND gates 23₀, 23₁,···23 2N-1 , as shown in Fig.11A. In the composition of Fig.11A, when P ₀ ="1" or P N ="1", the signals which can change its state in the next operation among D₀, D₁, ··· D N-1 , are D₀ and D N-1 ; when P ₁ ="1" or P N+1 ="1", the signals which can change its state in the next operation among D₀, D₁,··· D N-1 , are D 0 and D₁; and when P i ="1" or P N+i ="1", the signals which can change its state in the next operation among D₀, D₁, ··· D N-1 , are D i and D i+1 . Therefore, the construction for obtaining output signals 0 i and 0 i+1 , each of which enables the corresponding signal, D i or D i+1 to enter the next stage, respectively, is realized by using 2N OR gates 21₀, 21₁,···21 N-1 and 22₀, 22₁, ···22 N-1 as shown in Fig.11B. In addition, in Fig.11B, a NOR gate 25, which receives all the outputs of the OR gates 22₀, 22₁, ···22 N-1 , outputs all-enable signal ALENB which enables all signals of D₀, D₁, ··· D N-1 in FIG.10 to enter the next stage, when none of P₀, P₁, ··· P N-1 , P N , P N+1 , ···P 2N-1 equals to "1", for example, at the time of "power-on" or the like. Actually, the logical sum ( not shown ) of each of the outputs 0₀, 0₁, ··· 0 N-1 of the enable signal output portion 2 and the output of the NOR gate 25 shown in Fig.11B, instead of 0₀, 0₁,··· 0 N-1 , is applied to the AND gate 11₀, 11₁, ···11 N-1 in Fig. 10, respectively. Each of the clock-synchronizing portions 1₀,1₁, ··· 1 N-1 consists of a D-flip-flop circuit 10 i and AND gate 11 i , and receives the corresponding signal D i (i=1···N-1) at the data input terminal of the corresponding D-flip-flop circuit 10 i . The true output D i ′ of the D-flip-flop circuit 10 i corresponds to the output Q i of the digital pulse circuit 8. The AND gate 11 i receives the clock pulse from the clock generator 7 at one of the input terminals, and another input terminal of the AND gate 11 i is connected to the corresponding output terminal 0 i of the enble signal output portion 2. The output terminal of the AND gate 11 i is connected to the edge-trigger terminal of the correspomding D-flip-flop circuit 10 i , and therefore, the clock pulse from the clock generator 7 is applied to the D-flip-flop circuit 10 i , only when the enable signal from the enable signal output portion 2 is applied to the AND gate 11 i . As the output of the D-flip-flop circuit 10 i does not change state unless receiving the leading edge of the clock pulse, the enable signal can be regarded as the signal which enables the clock pulse to enter the corresponding D-flip-flop 10 i . From the other point of the view, the enable signal can be regarded as the signal which enables the signal D i to enter the corresponding D-flip-flop 10 i , i.e. which enables the D-flip-flop circuit 10 i to respond to the input signal D i so that the D-flip-flop circuit 10 i can output D i ′ corresponding to the input signal D i . Referring now to a timing chart in Fig.12, the operation of the digital pulse circuit in Fig.10 is explained. During the time from t₀ to t₁, the signal D₂ changes from 0 to 1. Therefore, at the time t₁, synchronized by the rising transition of the clock signal, the output signal D₂ ′ of the D-flip-flop circuit 10₂ to which the signal D₂ has been applied, changes from 0 to 1, because just before the time t₁, D₁ ′ = 1, and D₂ ′ =D₃ ′ = ··· =D N-1 ′ =0, so only D₁ ′ and D₂ ′ are enabled to change. Then, during the time from t₁ to t₂, the signals D₃ and D₄ change from 0 to 1. In this case, just before the time t₂, D₁ ′ = D₂ ′ = 1, and D₃ ′ =D₄ ′ = ··· =D N-1 ′ =0, so only D₂ ′ and D₃ ′ are enabled to change. Therefore, at the time t₂, the output D₄ ′ of the D-flip-flop circuit 10₄ does not respond to the input signal D₄, and only the output D₃ ′ of the D-flip-flop circuit 10₃ responds to the input signal D₃, and changes from 0 to 1. At the next rising timing of the clock pulse t₃, the output D₄ ′ of the D-flip-flop circuit 10₄ changes from 0 to 1. Even if a time interval exists between the timings of the transitions in any two signal levels among the N input signals applied to the construction of Fig.10, which is shorter than the cycle time of the clock pulse, the intervals between the timings of the transitions in any two signal levels among the N output signals D₀ ′, D₁ ′, ··· D N-1 ′ (which equals Q₀, Q₁, ··· Q N-1 ) of the construction of Fig.10, are equal to or greater than the cycle time of the clock pulse, that is, the aforementioned minimum readable time interval. Therefore, the time intervals between the timings of the transitions in the output signals F A , F B are equal to or greater than the above cycle time, and consequently, Consequently, these signals can be counted by the counter (for example, in the NC apparatus) without misreading. In addition, because only two input signals are enabled to enter the next stage at the same time among D 0 , D₁,··· D N-1 , the noise which superposes on any input signals except the above two enabled signals has no influence on the output signals D₀ ′, D₁ ′ , ··· D N-1 ′ of the construction of Fig.10. However, in the following special case, the abovementioned digital pulse circuit for maintaining a pulse width and suppressing noise according to the first aspect of the present invention, can not suppress some noise which appears at the timing mentioned below. This case is discussed with referrence to Fig.13. In Fig.13, at the time t₀, only D₂ and D₃ are enabled, as mentioned before. In this situation, if the objective quantity to be measured increases (i.e. the time proceeds towards the right direction in Fig.13), at first, D₃ changes from 1 to 0 (Cf. D₃ in Fig.13). Then, at the timing of the next rising of the clock pulse, D₃ ′ changes from 1 to 0 (Cf. D₃ ′ in Fig.13). However, if a noise is superposed on the signal D₂, which is also enabled together with D₃ at the same timing as the abovementioned next rising time (Cf. D₂ in Fig.13), D₂ ′ also changes from 0 to 1 at this timing (Cf. D₂ ′ in Fig.13). This means that an abnormality appears in the signal due to the influence of the noise. In order to remove the above abnormality, in the second aspect of the present invention; a first means (first kind of clock-synchronizing portion) which receives the aforementioned signals D₀ , D₁, ··· D N-1 and synchronizes each of the N digital signals by the clock pulse having cycle time is greater than the minimum readable time interval at the aforementioned counter; a second means (second kind of clock-synchronizing portion) which synchronizes once again each of the output signals from the first means by the above clock pulse; a third means which enables only two signals which can change states in the next change of the aforementioned objective quantity to be measured, among the input signals to the second means, to enter the second means; and a fourth means for detecting the existence of two signals having changed states (rise to high level or fall to low level) at the same time, among the outputs signals from the first means, and maintaining the output signals from the second means corresponding to the two signals, in the states just before the change, until one of said two signals returns to the state just before the change; are provided. In the following part, the second aspect of the present invention is explained with referrence to Fig.14 which shows the construction of that embodiment. The composition of Fig.14 comprises: a group of the first kind of clock-synchronizing portions 12₀ , 12₁, ···12 N-1 provided for each of input signals D₀ , D₁, ··· D N-1 ; a group of the second kind of clock-syncronizing portions 3₀ , 3₁, ··· 3 N-1 provided for each of output signals D₀′, D₁ ′ , D N-1 ′ of the first kind of clock-syncronizing portions; an enable signal output portion 2 which receives each of the output signals Q₀ , Q₁,··· Q N-1 of the second kind of clock-syncronizing portions 3₀ , 3₁, ··· 3 N-1 at the N input terminals I₀ , I₁, ··· I N-1 , and which outputs enable signals which enable only two signals which can change states (rise to high or fall to low) in the next operation, among the input signals D₀ ′, D₁ ′, ··· D N-1 ′ , to enter the corresponding one of the second kind of clock-synchronizing portions 3₀ , 3₁, ··· 3 N-1 ; leading edge-tailing edge detecting portions 5₀ , 5₁,··· 5 N-1 each of which detects leading edges or tailing edges of the corresponding one of the output signals D₀ ′, D₁ ′ , ··· D N-1 ′ of the first kind of clock-synchronizing portions, by comparing the above corresponding one of the output signals D₀ ′ , D₁ ′ , ··· D N-1 ′ with the corresponding one of the output signals Q₀ , Q₁, ··· Q N-1 of the second kind of clock-synchronizing portions 3₀ , 3₁, ··· 3 N-1 ; an output-maintaining signal output portion 4 which receives the outputs of the leading edge-tailing edge detecting portions 5₀ , 5₁, ··· 5 N-1 , and which detects that two signals D k ′ , D l ′ have changed states (rise to high level or fall to low level) at the same time, among the outputs signals D₀′ , D₁ ′, ··· D N-1 ′, and then outputs the signals which maintain the output signals Q k , Q l of the second kind of clock-synchronizing portions 3 k , 3 l corresponding to the above two signals D k ′, D l ′ , in the states just before the change, until one of the two signals D k ′ , D l ′ returns to the state just before the change; and a clock pulse generator 7 which generates clock pulses having cycle time longer than the minimum readable time interval at the counter which counts the output signals of the pulse encoder. Each of the N first kind of clock-synchronizing portions 12₀ , 12₁, ···12 N-1 is realized by using a D-flip-flop circuit respectively, and each of the N second kind of clock-synchronizing portions 3₀ , 3₁, ··· 3 N-1 is realized by using the corresponding combination of D-flip-flop circuits 30₀, 30₁, ···30 N-1 and AND gates 31₀ , 31₁,···31 N-1 respectively, in the construction of Fig.14. Each of the aforementioned input signals D₀ , D₁, ··· D N-1 is applied to the data input terminals of the corresponding D-flip-flop circuit which realizes the corresponding one of the first kind of clock-synchronizing portions 12₀ , 12₁, ···12 N-1 , respectively, and the clock pulse from the clock pulse generator 7 is applied to the edge-trigger terminal of each of the D-flip-flop circuits. Then, synchronizing with the clock pulse, each of the D-flip-flop circuits outputs the corresponding one of the true output signals D₀ ′ , D₁ ′ , ··· D N-1 ′ . Each of the output signals D₀ ′ , D₁ ′ , ··· D N-1 ′ of the correspondiong one of the first kind of clock-synchronizing portions 12₀ , 12₁, ··· 12 N-1 is applied to the data input terminals of the corresponding D-flip-flop circuit 30₀, 30₁, ··· 30 N-1 , then these D-flip-flop circuits 30₀, 30₁, ··· 30 N-1 output the true output signals D₀ ′ , D₁ ′ , ··· D N-1 ′ , and each output of the AND gates 31₀ , 31₁, ··· 31 N-1 is applied to the edge-trigger terminal of the corresponding one of the D-flip-flop circuits 30₀, 30₁, ··· 30 N-1 . To each of the AND gates 31₀, 31₁, ··· 31 N-1 , the clock pulse from the abovementioned clock pulse generator 7, the output from the corresponding one of the N output terminals 0₀ , 0₁, ··· 0 N-1 in the enable signal output portion 2, and the inverted signal of the output from the corresponding one of the N output terminals 0₀ ′, 0₁ ′ , ··· O N-1 ′ , are applied. In this construction, the clock pulse is applied to each of the D-flip-flop circuits 30₀, 30₁, ··· 30 N-1 only when the corresponding enable signal is active ("1") and the corresponding output-maintaining signal is non-active ("0"), that is, only under this condition is the corresponding signal D i ′ enabled. The enable signal output portion 2 is realized by the construction of Fig.11A and Fig.11B, as in the aforementioned construction of Fig.10. Each of the leading edge-tailing edge detecting portions 5₀ , 5₁, ··· 5 N-1 comprises an EOR gate. To one terminal of each of the EOR gates 5₀ , 5₁,··· 5 N-1 , the corresponding one of the outputs D₀ ′, D₁ ′, ··· D N-1 ′ of the mentioned first kind of clock-synchronizing portions 12₀, 12₁, ··· 12 N-1 is applied, and to another terminal of each of the EOR gates 5₀ , 5₁, ··· 5 N-1 , the corresponding one of the outputs Q₀, Q₁, ··· Q N-1 of the mentioned second kind of clock-synchronizing portions 3₀, 3₁, ··· 3 N-1 is applied. For example, if D i ′ among the above signals D₀ ′, D₁ ′ , ··· D N-1 ′ , changes state, since the corresponding output signal Q i changes state at the timing of the next rising of the clock pulse in the corresponding second kind of clock-synchronizing portions 3 i , until that rising time, D i ′ ≠ Q i , the output of the EOR gates 5 i is "1". Therefore, the leading edge or the tailing edge of D i ′ can be detected. The detailed construction of the output-maintaining signal output portion 4 is shown in Fig.15. Since, owing to the operation of the enable signal output portion 2, only the two signals adjacent to each other in the order of phase progress, for example, D i ′ and D i+1 ′ (including the case of D N-1 ′ and D ₀ ′ ), can become enabled (change states ) at the same time; the output-maintaining signal output portion 4 in Fig. 15 is composed of: a row of AND gates 42₀, 42₁, ··· 42 N- 1 each of which detects the two adjacent outputs having levels "1" at the same time, among the N outputs of the mentioned N leading edge-tailing edge detecting portions 5₀ , 5₁, ··· 5 N-1 ; and a row of the OR gates 41₀, 41₁,··· 41 N-1 which outputs the output-maintaining signals to maintain the outputs Q i , Q i+1 of the second kind of clock-synchronizing portions 3 i , 3 i+1 , to each of which the corresponding one of the two changed signals as mentioned above, D i ′ and D i+1 ′ is applied, where each changed signal makes the corresponding output of the leading edge-tailing edge detecting portions 5 i , 5 i+1 to be "1". Referring to a timing chart of Fig.16, the operation of the digital pulse circuit of the construction as mentioned above, is explained as follows: During the time interval from the timing t₁ and t₂, D₂ changes from 0 to 1. Then, at the time t₂, synchronizing with the rising of the clock pulse, the output D₂ ′ of the corresponding first kind of clock-synchronizing portions 12₂ changes from 0 to 1, and at the next timing of the rising of the clock pulse t₂, the output D₂ ′ of the corresponding second kind of clock-synchronizing portions 3₂ changes from 0 to 1. Since Q₀ = Q₁ = 1, Q₂ =Q₃=···=Q N-1 = 0 at the time of just before t₂, the enable signals having a "1" level are output from the output terminals 0₁ and 0₂ only in the enable signal output portion to enable D₁ ′ and D₂ ′ to enter the next stage, and consequently, only the signals D₁ ′ and D₂ ′ become enabled. During the time interval from the timing t₂ and t₃, the input signals D₃ and D₄ change from 0 to 1. Then, at the time t₃, synchronizing with the rising of the clock pulse, the outputs D₃ ′ and D₄ ′ of the corresponding first kind of clock-syncronizing portions 12₃ and 12₄ change from 0 to 1, and at the next timing of the rising of the clock pulse t₄, the outputs D₃ ′ and D₄ ′ of the corresponding second kind of clock-synchronizing portions 3₃ and 3₄ change from 0 to 1. However, since Q₀=Q₁=Q₂= 1, Q₃ =Q₄=···=Q N-1 =0 at the time of just before t₄,among D₀ ′ , D₁ ′ , ··· D N-1 ′ , the signals which is enabled to enter the corresponding second kind of clock-syncronizing portions, i.e. which can change the output of the corresponding second kind of clock-syncronizing portions, are only D₂ ′ and D₃ ′ . Therefore, at the next timing of rising of the clock pulse t₄, only the output Q₃ of the second kind of clock-synchronizing portions 3₃, which corresponds to the signal D₃ ′ , changes from 0 to 1. After that, the outputs of the second kind of clock-synchronizing portions 3₀, 3₁, ··· 3 N-1 become Q₀=Q₁=Q₂=Q₃=1, Q₄ =Q₅=···=Q N-1 =0, and therefore, D₄ ′ is enabled. Then, at the next timing of the rising of the clock pulse t₅, the output Q₄ of the second kind of clock-synchronizing portions 3₅, also changes from 0 to 1. As mentioned above, also in the construction of Fig.14, even if a time interval exists between any timings of transitions in the N input signals D₀ , D₁, ··· D N-1 , shorter than the cycle time of the aforementioned clock pulse, the time interval between any timings of transitions in the N output signals Q₀ , Q₁, ··· Q N-1 , becomes longer than the cycle time of the clock pulse, that is, the aforementioned minimum readable time interval. Therefore, the time intervals between any timings of transitions in the output signals F A , F B , which are obtained by applying the abovementioned Q₀ , Q₁,··· Q N-1 to the A/B-phase signal generating circuit 6 in Fig,9, become longer than the abovementioned cycle time, so these signals F A , F B are readable at the counter ( for example, in the NC apparatus ). In addition, in the construction of Fig.14, when the two signals which are enabled by the operation of the enable signals from the enable signals output portion 2, for example, D₂ ′ and D₃ ′ , change states at the same time; the corresponding leading edge-tailing edge detecting portion 5₂ and 5₃ detect these changes, and then the output-maintaining signal output portion 4 detects that both the outputs of the leading edge-tailing edge detecting portions 5₂ and 5₃ were changed to "1" at the same time. The output-maintaining signal output portion 4 outputs the output-maintainung signals to the corresponding second kind of clock-synchronizing portions 3₂ and 3₃, so that the outputs Q₂ and Q₃ of these second kind of clock-synchronizing portions 3₂ and 3₃ are maintained. After that, when, for example, in the case of Fig.13, the noise superposed on the input signal D₂, disappears, the output D₂ ′ of the corresponding first kind of clock-synchronizing portion 12₂ returns to the proper level. Accordingly, the output of the corresponding leading edge-tailing edge detecting portion 5₂ becomes zero, and the above outputs of the output-maintaining signal output portion 4 becomes non-active ("0"). After that, the output Q₃ of the second kind of clock-synchronizing portions 3₂ can be changed properly according to the level of D₃ ′ . As stated above, according to the second aspect of the present invention, all anticipated noise can be suppressed. The inventers realized the circuit according to the present invention by using a gate array circuit. INDUSTRIAL APPLICABILITY The digital pulse circuit according to the present invention is, in particular, useful as a means of obtaining incremental timing information with a high resolution from the output wave of the light-detecting portion in a high resolution pulse encoder.

Claims: A digital pulse circuit which receives N input digital signals (D₀, D₁...D N-1 ) in parallel, where N is an even integer equal to or greater than 4, the circuit comprising: a clock pulse generator (7) which generates a clock pulse having a predetermined cycle time; and, first means (1₀, 1₁...1 N-1 ; 3₀, 3₁...3 N-1 ) for accepting the N input digital signals, synchronising each of the N input digital signals with the clock pulse, and holding the level of each signal until a new signal is accepted, to output N synchronised digital signals (Q₀, Q₁ ...Q N-1 ; characterised by: second means (2; 11₀, 11, 11 N-1 ) for enabling only two of said N input digital signals (D₀, D₁...D N-1 ) to be accepted by the first means in each clock cycle, said two digital signals being determined based on the immediately preceding levels of the N synchronised digital signals (D₀′, D₁′...D N-1 ′). A circuit according to claim 1, further comprising: a third means (12₀, 12₁...12 n-1 ) for synchronising the input signals (D₀, D₁...D n-1 ) with digital signals from the clock pulse prior to the input signals entering the first means; and, a fourth means (4) for detecting an existence of two first synchronised digital signals, among the N synchronised digital signals (D₀′, D₁′...D N-1 ′; Fig 14) output from the first means, the levels of which have changed during the same cycle of the clock pulse, the fourth means then controlling the first means to maintain the levels of two second synchronised digital signals among the N synchronised digital corresponding to said two first synchronised digital signals at the levels just before the levels of said two first synchronised digital signals changed, until one of said two first synchronised digital signals returns to a level just before the level of the two first synchronised digital signals changed. A circuit according to claim 1, wherein the first means has a group of N clock-synchronising portions (1₀, 1₁...1 N-1 ) for the N input digital signals (D₀, D₁...D N-1 ) respectively; and each of the N clock-synchronising portions (1₀, 1₁...1 N-1 ) synchronises a respective one of the N input digital signals (D₀, D₁...D N-1 ) with the clock pulse. A circuit according to claim 3, in which each of the N clock-synchronising portions (1₀, 1₁...1 N-1 ; 3₀, 3₁ ...3 N-1 ) comprises a D-flip-flop circuit. A circuit according to claim 3, in which the second means receives N synchronised digital signals (D₀′, D₁′ ...D N-1 ) from each of the group of N clock-synchronising portions (1₀, 1₁...1 N-1 ), and outputs N enable signals to be supplied to the N clock-synchronising portions, where two of the N enable signals are made active corresponding to the two digital signals to be enabled to enter the first means. A circuit according to claim 5, in which each of the N clock-synchronising portions (1₀, 1₁...1 N-1 ) further comprises: a D-flip-flop circuit (10₀, 10₁...10 N-1 ) for receiving one of the N input digital signals corresponding to each of the N clock-synchronising portions, and outputting one of the N synchronised digital signals corresponding to each of the N clock-synchronising portions; and, a gate circuit (11₀, 11₁... 11 N-1 ) for receiving the clock pulse and one of the N enable signals corresponding to the each of the N clock-synchronising portions, and applying an output of the gate circuit to an edge-triggered input terminal of the D-flip-flop circuit in each of the N clock-synchronising portions. A circuit according to claim 5, in which the second means comprises: a first group of 2N gate circuits (23₀, 23₁...23 N-1 ) for receiving the N synchronised digital signals (D₀′, D₁′ ...D N-1 ) from the N clock-synchronising portions (1₀, 1₁ ...1 n-1 ), detecting 2N possible conditions by determining 2N combinations of levels of the N output signals (D₀′, D₁′...D N-1 ′) to output condition signals according to the detected conditions, respectively; and, a second group of 2N gate circuits (21₀, 21₁...21 N-1 ) for receiving the condition signals and generating the N enable signals according to the condition signals. A circuit according to claim 6, wherein the second means further comprises a third gate circuit (25) which receives all of the condition signals; and which outputs an all-enable signal (ALENB) which enables all of the N input digital signals (D₀, D₁...D N-1 ) to enter the first means when the all of the condition signals are non-active. A circuit according to claim 2, in which the first means comprises a second group of N clock-synchronising portions (3₀, 3₁...3 N-1 ), respectively provided corresponding to the N input digital signals, and each of the N clock-synchronising portions (3₀, 3₁...3 N-1 ) in the second group synchronises a corresponding one of the signals (D₀′, D₁′...D N-1 ′) of the third means with the clock pulse. A circuit according to claim 9, in which each of the N clock-synchronising portions (3₀, 3₁...3 N-1 ) in the second group is a D-flip-flop circuit. A circuit according to claim 9, in which the second means receives the N second synchronised digital signals (Q₀, Q₁...Q N-1 ) from the N clock-synchronising portions (3₀, 3₁...3 N-1 ) in the second group, and, when the synchronised signals change state, the second means outputs N enable signals to be supplied to the N clock-synchronised portions of the second group, where two of the N enable signals are made active corresponding to the two first synchronised digital signals to be enabled to be accepted by the first means. A circuit according to claim 11, in which the second means further comprises a third group of 2N gate circuits (23₀, 23₁...23 N-1 ) for receiving the N second synchronised digital signals (Q₀, Q₁...Q N-1 ) from the N clock-synchronising portions (3₀, 3₁...3 N-1 ) in the second group, detecting 2N possible conditions by determining 2N combinations of the levels of the the N second synchronised digital signals (Q₀, Q₁...Q N-1 ) to output condition signals according to the detected conditions, respectively; and, a fourth group of 2N gate circuits (21₀, 21₁...21 N-1 ) for receiving the condition signals and generating the N enable signals according to the condition signals. A circuit according to claim 12, wherein the second means further comprises a third gate circuit (25) which receives all of the condition signals applied to the second group 2N gate circuit (21₀, 21₁...21 N-1 ); and which outputs an all-enable signal (ALENB) which enables all of the N input signals (D₀′, D₁′...D N-1 ′) of the N second type of clock-synchronising portions (3₀, 3₁...3 N-1 ) to be accepted by the next stage, when the all of the condition signals are non-active. A circuit according to claim 9, in which the fourth means comprises: N leading edge/tailing edge detecting means (5₀, 5₁ ...5 N-1 ), respectively provided corresponding to the N input digital signals, each of the N leading edge/tailing edge detecting means comparing one of the first synchronising digital signals (D₀′, D₁′...D N-1 ′) output from a corresponding one of the clock-synchronising portions (12₀, 12₁... 12 N-1 ) in the first group, with one of the second synchronised digital signals (Q₀, Q₁...Q N-1 ) output from a corresponding one of the clock-synchronising portions (3₀, 3₁...3 N-1 ) in the second group to determine whether or not the compared ones of the first and second synchronised digital signals are equal to detect a pair of the compared one of the first and second synchronised digital signals in which one and the other of the pair are not equal; and, an output-maintaining signal output portion (4) for outputting output-maintaining signals to two of the clock-synchronising portions (3₀, 3₁...3 N-1 ) in the second group which corresponds to two of the N leading edge/tailing edge detecting means (5₀, 5₁...5 N-1 ) when the two leading edge/tailing edge detecting means (5₀, 5₁...5 N-1 ) which are adjacent with regard to the order of the phase progress in due operation, and both of the two leading edge-tailing detecting means (5₀, 5₁...5 N-1 ) detect the pair, the output-maintaining signals making the two clock-synchronising portions in the second group maintain levels thereof, at levels just before the two leading edge/tailing edge detecting the pair, until one of the two first synchronised digital signals returns to a level just before the two leading edge/tailing edge detecting means detect the pair. A circuit according to claim 14, in which each of the leading edge/tailing edge detecting means (5₀, 5₁...5 N-1 ) comprises an EOR gate. A circuit according to claim 14, in which the output-maintaining signal output portion (4) comprises: NAND gates (42₀, 42₁...42 N-1 ), provided corresponding to each two of the leading edge-tailing edge detecting means (5₀, 5₁...5 N-1 ), each of the NAND gates (42₀, 42₁ ...42 N-1 ) receives two output signals from the corresponding two of the leading edge-tailing edge detecting means (5₀, 5₁...5 N-1 ); and, NOR gates (41₀, 41₁...41 N-1 ) provided corresponding to each leading edge/tailing edge detecting means (5₀, 5₁ ...5 N-1 ), each of the NOR gates (41₀, 41₁...41 N-1 ) outputs the logical sum of the outputs of two AND gates (42₀, 42₁ ...42 N-1 ) which receive the output of one of the N leading edge/tailing edge detecting means (5₀, 5₁...5 N-1 ).

Inventors: KOBARI KATSUO, TAKEKOSHI YOSHITAKA, TANIGUCHI MITSUYUKI, KOBARI, KATSUO, TAKEKOSHI, YOSHITAKA, TANIGUCHI, MITSUYUKI
Applicants: FANUC LTD, FANUC LTD.
Application year: 1987
Main classification: G01D5
IPC codes: H03M1, G01D5