ELECTRONIC CIRCUIT HAVING COMPLEMENTARY SIGNAL-CARRYING DATA LINES

Abstract: In conventional digital-to-analogue converters one of a number of multi-emitter transistors is driven by means of the select logics the emitters of which are connected selectively to a group of data lines. The output circuits connected to the data lines further receive a reference voltage to be able to detect the condition on the data lines. In the analogue converter according to the invention each data line is constructed so as to be complementary in which the emitters which in the prior art circuit arrangement are connected to the first group of data lines are coupled in the same manner to a first group of data lines while the remaining emitters are now connected to complementary lines from the second group. The output circuits which are connected to the data lines receive a logic signal of a data line and the complementary logic signal of the associated complementary data line. The result is that the voltage step which is presented to the inputs of the output circuits is twice as large. As a result of this the interference sensitivity is reduced because the margin of the voltage difference to be detected has become twice as large. As further advantage of the converter according to the invention is that a reference voltage for detecting the logic condition on the data lines is superfluous.

Description: The invention relates to an electronic circuit arrangement in which selection means select a transistor from a group of (2 n -1) multi-emitter transistors each having n emitters under the control of an input signal and make it conductive, of which emitters a selection is connected to n data lines, which data lines further are each connected on the one hand to a current source and on the other hand to an output circuit for generating at the output of the output circuit a binary output signal belonging to a given input signal. Such a circuit arrangement is known from British GB-PS 1,547,918, in which a completely parallel operating analogue-to-digital converter is described. In this a-d-converter the data on the data lines are compared with a reference voltage by an output circuit to establish whether the data lines carry a logic high or logic low signal. Such a circuit arrangement usually has a logic small stroke (voltage difference between the logic high and low signal) and as a result of this also has a low interference margin. Increasing the logic stroke usually is not possible because only a small voltage range is available in the bipolar very rapidly operating logic often used for this type of circuit arrangements. It is the object of the invention to provide an electronic circuit arrangement in which the interference sensitivity is reduced and in which the use of a reference voltage for detecting the logic levels on the data lines is superfluous. An electronic circuit arrangement according to the invention is characterized in that n pairs of data lines are provided, a first and a second data line within a pair belonging to a first and to a second group of n data lines, respectively, the i th emitter of each transistor being connected either to the i th data line of the first group or to the i th data line of the second group, the i th data lines forming one of the n pairs of data lines with 1 ≦ i ≦ n, so that each pair of data lines always carries complementary logic signals. The invention will be described in greater detail with reference to examples shown in the drawing, in which Figure 1 is a prior art electronic circuit arrangement, and Figure 2 shows an electronic circuit arrangement according to the invention. Figure 1 shows in brief a prior art analogue-to-digital converter circuit arrangement. Figure 1 shows a select logic circuit arrangement 3 with which no or one out of the seven transistors T1 to T7 is selected with reference to a input signal which is applied to input 5. For this purpose, the bases of the transistors T1 to T7 are connected to outputs U1 to U7. The collectors of the transistors T1 to T7 are connected in common to the supply voltage VCC. The emitters of the transistors T1 to T7 are selectively connected to the data lines D1 to D3 which further are connected on the one hand to current sources I1 to I3 and on the other hand to output circuits L1 to L3. The current sources I1 to I3 are further connected to a second supply source VDD which has a lower potential than VCC. The output circuits L1 to L3 are each provided with a further input to which a reference voltage is applied which is generated by the reference voltage generator VR. If the input voltage applied to the input 5 exceeds a first threshold, transistor T1 will become conductive. When a second, third... seventh threshold voltage is exceeded by the input voltage respectively the second transistor T2, third transistor T3... seventh transistor T7 respectively will become conductive. The one out of the seven conductive transistors T1 to T7 activate one or more lines D1, D2, D3. This activation is such that the transistors T1 to T7 bring the binary codes 001 to 111 one the data lines D1 to D3, which binary codes are copied into the output circuit arrangements L1 to L3. The output circuit L1, L2, L3 preferably are latch circuits which retain the data on the data lines D1 to D3 after copying and put them on their outputs 01, 02 and 03. The voltage step on the data lines D1 to D3 between the logic high and logic low signals is rather low in the binary transistor technique used, in which the applied reference voltage which is to be generated by the source VR should be halfway between the logic high and logic low level. The result of this is that the known circuit arrangement has a high interference sensitivity. Figure 2 shows a circuit arrangement according to the invention in which the elements corresponding to Figure 1 are referred to by corresponding reference numerals. A second group of data lines D1 , D2 and D3 are added to the group of data lines D1, D2 and D3, in which the first group of data lines and the second group of data lines always carry complementary logic signals. The emitters of the transistors T1 to T7 are connected to the data lines D1 to D3 in the same manner as in Figure 1. The emitters of the transistor T1 to T7 which are not connected to data lines in Figure 1 are now connected to the second group of data lines D1 to D3 . A first emitter of transistor T1 is connected to the data line D1 and a second and third emitter, respectively, are connected to the second data line D2 and the third data line D3 , respectively, from the second group. Each data line from the first and second group is connected via a current source I₁₁, I₁₂, I₂₁.....I₃₂ to the second supply source point VDD. On the other hand, the data lines D1, D1 , and D2, D2 and D3, D3 are connected to the respective output circuits L21, L22, L23. For example, the output circuit L21 receives the logic signals on the output line D1 and the output line D1 . Since these signals are complementary the output circuit receives the voltage difference between the logic high and logic low level at its input which is twice as large as the voltage difference at the inputs of the output circuit L1 of Figure 1. The result is that the output circuit L21 sees a twice as large voltage step at its input and hence will be less sensitive to interference. The same situation occurs for the output circuits L22 and L23. The output circuits L21 to L23 are preferably latch circuits which, after receiving the logic signals of the data lines store and transmit them to their outputs 01, 02 and 03.

Claims: An electronic circuit arrangement in which selection means select a transistor from a group of (2 n -1) multi-emitter transistors each having n emitters under the control of an input signal and make it conductive, of which emitters a selection is connected to n data lines, which data lines further are each connected on the one hand to a current source and on the other hand to an output circuit for generating at the output of the output circuit a binary output signal belonging to a given input signal, characterized in that n pairs of data lines are provided, a first and a second data line within a pair belonging to a first and to a second group of n data lines, respectively, the i th emitter of each transistor being connected either to the i th data line of the first group or to the i th data line of the second group, the i th data lines forming one of the n pairs of data lines with 1 ≦ i ≦ n, so that each pair of data lines always carries complementary logic signals. An analogue-to-digital converter having an electronic circuit as claimed in Claim 1.

Inventors: VAN DE GRIFT, ROBERT EMILE JOHAN, VAN DER VEEN, MARTIEN
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1987
Main classification: H03M1
IPC codes: H03M7, H03M1