SEMICONDUCTOR MEMORY

Abstract: A p-channel MOS transistor (51, 52) is connected in series to a floating gate n-channel MOS transistor (21) forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes.

Description: The present invention relates to a semiconductor memory and, more particularly, to a programmable read-only memory (PROM) into which data can be written. A floating-gate, n-channel MOS transistor used as a memory cell in a programmable read-only memory (PROM) has the structure as shown in Fig. 1. As is illustrated in this figure, source 12 and drain 13, both constituted by N⁺ diffusion layers, are formed in one major surface region of P-type silicon substrate 11. Insulation film 14 is formed on the major surface of substrate 11. Floating gate 15 is embedded in insulation film 14 and is located above that portion of substrate 11 which is situated between source 12 and drain 13. Floating gate 15 thus floats electrically above substrate 11. Control gate 16 is formed on insulation film 14 and is located above floating gate 15. Source electrode 17 is formed in one of two contact holes cut in insulation film 14, and is thereby electrically connected to source 12. Drain electrode 18 is formed in the other contact hole, and is thereby electrically connected to drain 13. Now, it will be explained how data "0" is written into the n-channel MOS transistor shown in Fig. 1. First, P-type silicon substrate 11 and source 12 are set at the ground potential (GND). Then, a voltage of, for example, 12.5 V is applied to control gate 16, and a voltage of, for example, 7.0 V is applied to drain 13. As a result, the potential of floating gate 15 rises to, for instance, 9.0 V, since 12.5 V, has been applied to control gate 16. Hence, 9.0 V is applied between floating gate 15 and substrate 11, whereby an inversion layer, that is, N-type layer 19, is formed in that surface region of substrate 11 which separates source 12 and drain 13. The electrons within inversion layer 19 are moved toward drain 13 by the voltage applied to drain 13, and collide with those silicon atoms of substrate 11 which are present near drain 13. A so-called "electron avalanche" occurs near drain 13, thereby generating new electrons. Some of these electrons drift to drain 13, and the rest are injected into floating gate 15. As more and more electrons accumulate in floating gate 15, the potential of the gate falls. When the potential falls to a specific value, electrons can no longer be injected into gate 15. At this point, the writing of data "0" is completed. With the large memory capacity PROM comprising a number of memory cells having the structure as shown in Fig. 1, it is generally required that data be written into each memory cell in the shortest time possible; for example, within 1 millisecond, or within 100 microseconds. Fig. 2 shows a circuit consisting of one memory cell 21 of the type shown in Fig. 1, and a circuit for writing data thereinto. Also provided are n-channel MOS transistors 22 and 23, having their current paths connected in series. MOS transistor 22, which is a data-writing transistor, has its drain connected to high-voltage power supply Vpp for supplying 12.5 V, and its gate receives a write signal. MOS transistor 23 is a column-selecting transistor, and its gate receives a column-address signal of voltage Vpp. A row-address signal of voltage Vpp is applied to the control gate of memory cell 21. When the voltage of the column-address signal and that of the row-address signal both rise to 12.5 V and the drain voltage of memory cell 21 rises to about 7 V, electrons are injected from the substrate into the floating gate of memory cell 21, and data "0" is thereby written into memory cell 21. Fig. 3 is a graph illustrating the data-writing characteristic of the semiconductor memory circuit shown in Fig. 2. In this figure, curve I indicates the operation characteristic, i.e., the relationship between the drain current Ids and drain voltage Vds which memory cell 21 exhibits when a voltage of 12.5 V (i.e., voltage Vpp) is applied to its control gate. As curve I reveals, the electron avalanche occurs in memory cell 21, at point T. Curve II represents the way in which the load applied on memory cell 21 changes as current Ids and voltage Vds change. Intersection P of curves I and II denotes the operation point of memory cell 21. Curve II is specific to a load constituted by an n-channel MOS transistor. Data can be written into memory cell 21 even if current Ids is below point T, provided the data does not have to be written at high speed. In order that data can be written in at a sufficiently high speed, drain current Ids should be at the same level as, or above, point T. However, the angle defined by curves I and II is small in the region above point T, with the result that, in this region, drain current Ids varies considerably even if the inclination of curve I varies only a little, thus causing the data-writing speed of memory cell 21 to vary considerably. The inclination of curve I depends on the process parameters of cell 21, such as the size of the transistor, the impurity concentration of the substrate, the threshold voltage of the transistor, and the like. Since each of the process parameters varies from one memory cell to another, the memory cells in the PROM therefore cannot have the same curve I, i.e., the same data-writing characteristic. Hence, in the conventional PROM, the data-writing current varies considerably from one memory cell to another, with the result that the data-writing characteristic of each cell is unstable. Most programmable read-only memories (PROMs) have the structure shown in Fig. 4. As is illustrated in this figure, a PROM has memory-cell matrix 31, which comprises a floating-gate, and n-channel MOS transistors 32 ll to 32 mn which are used as memory cells. The MOS transistors are arranged in rows and columns. The control gates of the n-channel MOS transistors forming each row are coupled to a row-signal line. More specifically, MOS transistors 32 ll to 32 ln of the first row have their control gates connected to the first row-signal line 33 l , MOS transistors 32 2l to 32 2n of the second row have their control gates coupled to the second row line 33₂, and so forth. MOS transistors 32 ml to 32 mn of the last row have their control gates coupled to the last row-signal line 33 m . Further, the drains of the MOS transistors forming each column are coupled to a column-signal line. More precisely, MOS transistors 32 ll to 32 ml of the first column have their drains connected to the first column-signal line 34 l , MOS transistors 32 l2 to 32 m2 of the second column have their drains coupled to the second column-signal line 34₂, and so forth. MOS transistors 32 ln to 32 mn of the last column have their drains connected to the last column-signal line 34 n . The sources of all n-channel MOS transistors 32 ll to 32 mn are connected to the ground. The PROM further comprises row decoder 35 and column-selecting circuit 36. The output of row decoder 35 is coupled to row-signal lines 33 l to 33 m . The column-selecting circuit 36 is connected to column-signal lines 34 l to 34 n . Column-selecting circuit 36 comprises column-selecting n-channel MOS transistors 37 l to 37 n , which are turned on and off by outputs A l to A n of a column decoder (not shown). MOS transistors 37 l to 37 n are connected at one end to column-signal lines 34 l to 34 n , respectively, and at the other end to one another, thus forming a node. Data-reading n-channel MOS transistor 38 and data-writing MOS transistor 39 are each connected at one end to this node. The other end of MOS transistor 38 is connected to the input terminal of sense amplifier circuit 40 and also to resistor 41, which in turn is coupled to power supply potential Vcc. Data-reading MOS transistor 38 is turned on by a read-mode signal. The other end of data-writing MOS transistor 39 is coupled to high-voltage power supply potential Vpp. MOS transistor 39 is turned on by the output of data-writing gate circuit 42. Gate circuit 42 comprises buffer circuit 43 and AND gate 44. Buffer circuit 43 is coupled to power supply potential Vpp, and has an output terminal connected to the gate of data-writing MOS transistor 39. AND gate 44 has an output terminal coupled to the input terminal of buffer circuit 43, and provides a logical sum of a write-mode signal and data Din to be written in the PROM. The operation of the conventional PROM shown in Fig. 4 will now be described. Assume that memory cell 32 ij (i = 1 to m, j = 1 to n) is selected by outputs of row decoder 35 and the column decoder (not shown). Also assume that the read-mode signal and the write-mode signal are at level "1" and level "0", respectively, and, thus, MOS transistor 38 is on, and MOS transistor 39 is off. In this state, sense amplifier circuit 40 detects the data stored in memory cell 32 ij . This data, Dout, appears at the output terminal of sense amplifier circuit 40. Data "0" and data "1" can be written into any desired memory cell. When the write-mode signal and the read-mode signal are at level "1" and level "0", respectively, MOS transistor 38 is off. When data Din is "1", the output of AND gate is at level "1". As a result, MOS transistor 39 is on. A high voltage is therefore applied from high-voltage power supply Vpp to column-signal line 34 j , via MOS transistor 39 and column-selecting MOS transistor 37 j (j = 1 to n), which has been selected by the column decoder. Hence, data "0" is written into memory cell 32 ij coupled to row-signal line 33 i selected by row decoder 35, and to column-signal line 34 j connected to column-selecting MOS transistor 37 j . On the other hand, when data Din is "0" while the write-mode signal and the read-mode signal remain at level "1" and level "0", respectively, the output of AND gate 44 is at level "0". MOS transistor 39 is therefore off. In this case, no high voltage is applied to memory cell 32 ij selected by row decoder 35 and the column decoder. Hence, data "1" is written into memory cell 32 ij . Fig. 5 shows memory cell 32 ij and the circuit for writing data thereinto. In order to write data "0" into memory cell 32ij, the gate potentials of data-writing MOS transistor 39, column-selecting MOS transistor 37 j , and memory cell 32 ij are set at Vpp level (usually 12.5 V), thereby turning these MOS transistors on. Current Iw flows from high-voltage power source Vpp, coupled to the drain of MOS transistor 39, to the source (i.e., ground GND) of floating-gate MOS transistor 32 ij used as memory cell 32 ij . The hot carriers (i.e., electrons) induced by current I are injected into the floating gate of memory cell 32 ij , thereby writing data "0" thereinto. In order to write data "1" into memory cell 32 ij , the gate potential of data-writing MOS transistor 39 is set at the GND level. Although the potentials at the control gates of column-selecting MOS transistor 37 j and memory cell 32 ij are both at the Vpp level, MOS transistor 39 is off. Hence, no current flows to memory cell 32 ij from high-voltage power source Vpp. As a result, no electrons are injected into the floating gate of memory cell 32 ij , and this memory cell stores data "1". As has been described above, memory cell 32 ij is an n-channel MOS transistor. Column-selecting MOS transistor 37 j and data-writing MOS transistor 39 are also n-channel transistors. Fig. 6 is a circuit diagram modified from the diagram of Fig. 5, and explains how data "0" is written into memory cell 32 ij . When high voltage Vpp is applied to the gate and also to the drain of transistor 39, this transistor is thus on. In this condition, the source potential Va of MOS transistor 39 has not reached the Vpp level. Source potential Va is given as follows, provided that MOS transistor 39 is of enhancement type: Va ≦ Vpp - V THN where V THN is the threshold voltage of MOS transistor 39. Source potential Va is not equal to the substrate voltage (GND), and hence, due to the back-gate bias effect, the apparent threshold voltage of MOS transistor 39 rises, and source potential Va is therefore lower than Vpp - V THN . Further, the source potential Vb of column-selecting MOS transistor 37 j is approximately equal to source potential Va of MOS transistor 39. It follows that potential Va is applied to the source of memory cell 32 ij . As long as the Vpp level is sufficiently high, source potential Va of MOS transistor 39 is also high, and there is no problem in programming the PROM. However, the recent trend has been for the power-supply voltage level Vpp to be lowered. This is because an LSI will deteriorate rapidly when a high voltage is applied to the signal lines incorporated therein. In the case of a CMOS-LSI, the high voltage applied to the signal lines causes a latch-up phenomenon to occur. Even when power-supply voltage level Vpp is lowered, it is necessary, in order to write data into memory cell 32 ij , to supply a current large enough to generate hot carriers between the source and drain of memory cell 32 ij . In order to supply such a large current, source potential Vb of column-selecting MOS transistor 37 j must also be raised to as close to the Vpp level as possible. Nevertheless, source potential Vb is inevitably lowered by the threshold voltage V THN of data-writing MOS transistor 39, and hence, when power-supply voltage level Vpp is lowered, the current flowing through the source-drain path of memory cell 32 ij decreases considerably, thus reducing the speed of writing data "0" into memory cell 32 ij . A semiconductor memory having a non volatile cell, and first and second MOS transistors in series, with the first transistor being of different channel type, is shown in US-A-4 387 444. The gates of the cell and the transistors are connected together, and the circuit forms part of a non volatile semiconductor latch. EP-A-0 050 005 shows an EPROM device with a memory cell and two MOS transistors in series, but the cell and the transistors are of the same channel type. JP-A-61 097 976 (abstract) shows improving read-out and write-in efficiency in an EPROM composed of a P-channel write transistor and an N-channel read transistor having a common floating gate. The use of P-channel MOS transistors for addressing and for switching a programming voltage onto a memory cell is shown in pages 106-107 of the 1978 I EEE Solid State Circuit Conference 16th February 1978, but only in conjunction with P-channel memory cells. As has been described above, in the conventional PROM, the data-writing voltage is lowered by the threshold voltage of the data-writing MOS transistor. The current flowing through the source-drain path of each memory cell therefore decreases. Consequently, the efficiency of writing data "0" into the memory cell is inevitably low. Accordingly, it is an object of the present invention to provide a semiconductor memory wherein the data-writing characteristic of each memory cell can be sufficiently stabilized, even if the memory cells have different operation points due to the difference in their process parameters. Another object of the present invention is to provide a semiconductor memory wherein sufficient current can be supplied to each memory cell, even if the data-writing voltage is relatively low, so as to ensure that data "0" can be written into the cell at a sufficiently high speed. According to an aspect of the present invention there is provided a semiconductor memory comprising: means for connecting a data writing potential; means for connecting a reference potential; a PROM cell, a first MOS transistor and a second MOS transistor connected in series between said data writing potential and said reference potential, wherein the PROM cell is of a first channel type, and is electrically programmable to store data therein; the first MOS transistor is of a second channel type; characterized in that a gate of said PROM cell receives a row selection signal; a gate of said first MOS transistor receives a write signal to determine the operation point of said PROM cell when the memory is set in a data-writing mode; and the second MOS transistor is of said second channel type, and a gate of said second MOS transistor receives a column selection signal to decrease time required for writing data into said PROM cell; and further comprising means for generating and supplying said row selection signal to the gate of said PROM cell; means for generating and supplying said write signal to the gate of said first MOS transistor; and means for generating and supplying said column selection signal to the gate of said second MOS transistor. Opposite channel type MOS transistors are connected together, so that the opposite channel type MOS transistor functions as the load of the memory cell. The operational characteristic of the opposite channel type MOS transistor determines the data-writing current of the memory cell. In other words, the opposite channel type MOS transistor determines the operation point of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operational characteristic of the memory cell changes. According to another aspect of the present invention there is provided a semiconductor memory comprising: a plurality of n-channel floating gate MOS transistors arranged in rows and columns, and used as memory cells; a plurality of row lines equal in number to the rows of memory cells, one row line being connected to the gate of each of the memory cells of the corresponding row; a plurality of column lines equal in number to the columns of memory cells, one column line being connected to the drain of each of the memory cells of the corresponding column; a data-writing, column-selecting circuit including a plurality of p-channel MOS transistors each connected at one end to one of said column lines, respectively, and controlled by data-writing, column-decode signals; a data-reading, column-selecting circuit including a plurality of n-channel MOS transistors each connected at one end to one of said column lines, respectively, and controlled by data-reading, column-decode signals; characterized in that a data-writing, p-channel MOS transistor is connected to the other ends of the p-channel MOS transistors of said data-writing, column-selecting circuit, for applying a high voltage to those memory cells selected and turned on when the semiconductor memory is set in level "0" data-writing mode; and the p-channel MOS transistors of said data-writing column-selecting circuit are connected in parallel with the n-channel MOS transistors of said data-reading, column-selecting circuit, respectively, thereby forming transmission gates. According to another aspect of the present invention there is provided a semiconductor memory comprising: a plurality of n-channel floating gate MOS transistors arranged in rows and columns, and used as memory cells; a plurality of row lines equal in number to the rows of memory cells, one row line being connected to the gate of each of the memory cells of the corresponding row; a plurality of column lines equal in number to the columns of memory cells, one column line being connected to the drain of each of the memory cells of the corresponding column; a data-writing, column-selecting circuit including a plurality of p-channel MOS transistors each connected at one end to one of said column lines, respectively, and controlled by data-writing, column-decode signals; a data-reading, column-selecting circuit including a plurality of n-channel MOS transistors each connected at one end to one of said column lines, respectively, and controlled by data-reading, column-decode signals; characterized in that a data-writing, p-channel MOS transistor is connected to the other ends of the p-channel MOS transistors of said data-writing, column-selecting circuit, for applying a high voltage to those memory cells selected and turned on when the semiconductor memory is set in level "0" data-writing mode; and said data-writing, column-selecting circuit and said data-reading, column-selecting circuit are located at opposite sides of a cell matrix comprising said floating gate MOS transistors. Such circuit arrangements prevent the data-writing voltage from being lowered, by the use of two column-selecting circuits which are provided, one for the read mode, and the other for the write mode. The column-selecting circuit for the read mode comprises n-channel MOS transistors, whereas the column-selecting circuit for the write mode comprises p-channel MOS transistors. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross-sectional view of a floating-gate, MOS transistor; Fig. 2 shows a semiconductor memory using the MOS transistor shown in Fig. 1 as a memory cell, and also shows a circuit for writing data into the MOS transistor; Fig. 3 is a graph illustrating the voltage-current characteristic which the circuit of Fig 1 exhibits when it is set in the data-writing mode; Fig. 4 is a circuit diagram showing a conventional semiconductor memory; Fig. 5 is a circuit diagram showing one of the memory cells shown in Fig. 4, and a circuit for writing data into this memory cell; Fig. 6 is a circuit diagram modified from the diagram of Fig. 5; Fig. 7 is a circuit diagram showing a memory cell and a circuit for writing data into the memory cell, according to a first embodiment of the present invention; Fig. 8 is a graph illustrating the voltage-current characteristic which the circuit of Fig. 7 exhibits when it is set in the data-writing mode; Fig. 9 is a circuit diagram of a semiconductor memory according to a second embodiment of the present invention; Fig. 10 is a circuit diagram showing one of the memory cells used in the memory of Fig. 9, and also showing a circuit for writing data into this memory cell; Fig. 11 is a circuit diagram of a semiconductor memory according to a third embodiment of the invention; Fig. 12 is a circuit diagram of a semiconductor memory according to a fourth embodiment of the invention; and Fig. 13 is a diagram showing the pattern in which the elements of the column-selecting circuit used in the memory of Fig. 12 are arranged. Embodiments of the present invention will now be described, with reference to the accompanying drawings. Fig. 7 shows a memory cell and the circuit for writing data thereinto. As is shown in Fig. 7, memory cell 21 is a floating-gate, n-channel MOS transistor having the structure shown in Fig. 1. The source-drain paths of p-channel MOS transistors 51 and 52 are connected in series to memory cell 21. Transistor 51 is provided for writing data into memory cell 21. High voltage Vpp, or the data-writing voltage, is applied to the source of transistor 51. Voltage Vpp is 12.5 V. A write-mode signal is supplied to the gate of transistor 51. Transistor 52 is provided, in order to select the memory cells of the same column, including memory cell 21. The source of transistor 52 being coupled to the drain of transistor 51, the drain of transistor 52 being coupled to the drain of transistor forming memory cell 21. A column address signal is supplied to the gate of transistor 52. The back gates of both p-channel MOS transistors 51 and 52 are connected to high-voltage power supply Vpp, so that variation in the threshold voltage of transistor 51, resulting from the drop in the substrate bias, can be suppressed. The back gate and source of memory cell 21 are connected to the ground. The row-address signal is supplied to the control gate of memory cell 21. When the write-mode signal and the column-address signal both change to 0V-level, and the row-address signal changes to 12.5 V level, the drain voltage of memory cell 21 becomes approximately 7 V, whereupon data is written into memory cell 21. Fig. 8 represents the data-writing characteristic of the circuit shown in Fig. 7. More precisely, curve I denotes the Ids-Vds relation which is observed when 12.5 V is applied to the control gate of memory cell, where Ids is the drain current of cell 21, and Vds is the drain voltage of cell 21. The electron avalanche in memory cell 21 starts at point T. The p-channel MOS channel transistors 51 and 52 are both regarded as the load of memory cell 21. This load varies with Ids and Vds, as is illustrated by curve II in Fig. 8. Obviously, curve II is almost horizontal in the range now to be considered. This indicates that when a load circuit for memory cell 21 is formed of two p-channel MOS transistors, 51 and 52, the operational characteristic of the memory circuit can be improved. Intersection P of curves I and II (Fig. 8) is the operation point of memory cell 21. Drain current Ids, defined by intersection P, is 2 mA, which is sufficient to write data into cell 21 at high speed. As may be understood from Fig. 8, the currents flowing through transistors 51 and 52 change little in the region above point T, at which the electron avalanche occurs in memory cell 21. This means that the data-writing current scarcely changes even if the operational characteristic of memory cell 21 fluctuates. Therefore, the data-writing speed of cell 21 is not affected by the process parameters of cell 21, thereby enabling a high yield of the PROM to be ensured. In the circuit of Fig. 7, p-channel MOS transistors 51 and 52 both are used as loads on memory cell 21. However, only one data-writing MOS transistor may be used as a load. If this is the case, it suffices to use a p-channel transistor of a high conductance as column-selecting MOS transistor 52. When the present invention is applied to a one-bit semiconductor memory, transistor 52 shown in Fig. 7 becomes unnecessary. In this case, transistor 51 functions as a load to memory cell 21. In the circuit shown in Fig. 7, memory cell 21 is an n-channel MOS transistor, and the load of cell 21 consists of p-channel MOS transistors 51 and 52. Alternatively, cell 21 can be a p-channel MOS transistor, and its load made of n-channel MOS transistors. Also in this case, the same Ids-Vds relation and the same load characteristic as represented by curve I and II shown in Fig. 8 will be obtained. As has been described above, in the semiconductor memory according to the embodiment, the data-writing characteristic of each memory cell can be sufficiently stable even if the memory cells have different operation points, due to the difference in their process parameters, and data can therefore be written into each cell at high speed. Fig. 9 shows a PROM according to a second embodiment of the invention. In this figure, the same numerals and symbols are used to designate the same elements as are used in the conventional PROM shown in Fig. 4. As is shown in Fig. 9, this PROM has memory-cell matrix 31. Matrix 31 comprises floating gate, and n-channel MOS transistors 32 ll to 32 mn , used as memory cells and arranged in rows and columns. The control gates of the MOS transistors forming each row are coupled to a row-signal line. More precisely, MOS transistors 32 ll to 32 ln of the first row have their control gates coupled to the first row-signal line 33 l , MOS transistors 32 2l to 32 2n of the second row have their control gates coupled to the second row-signal line 33₂, and so forth. MOS transistors 32 ml to 32 mn of the last row have their control gates connected to the last row-signal line 33 m . Further, the drains of the MOS transistors forming each column are coupled to a column-signal line. More specifically, MOS transistors 32 ll to 32 ml of the first column have their drains connected to the first column-signal line 34 l , MOS transistors 32 l2 to 32 m2 of the second column have their drains coupled to the second column-signal line 34₂, and so forth. MOS transistors 32 ln to 32 mn of the last column have their drains connected to the last column-signal line 34 n . The sources of n-channel MOS transistors 32 ll to 32 mn are connected to the ground. The PROM further comprises row decoder 35 and column-selecting circuits 61 and 62. First column-selecting circuit 61 is used to read data from memory-cell matrix 31, and second column-selecting circuit 62 is used to write data in memory-cell matrix 31. First column-selecting circuit 61 comprises column-selecting MOS transistors 63 l to 63 n . MOS transistors 63 l to 63 n are n-channel transistors and are turned on by output address signals A l to A n of a column decoder (not shown) which is used to read data from memory-cell matrix 31. MOS transistors 63 l to 63 n are connected at one end to column-signal lines 34 l to 34 n , respectively. They are connected at the other end to each other. Second column-selecting circuit 62 comprises column-selecting MOS transistors 64 l to 64 n . MOS transistors 64 l to 64 n are p-channel transistors and are turned on by output address signals B l to B n of another column decoder (not shown), which is provided to write data in memory-cell matrix 31. MOS transistors 64 l to 64 n are connected at one end to column-signal lines 34 l to 34 n , respectively, and are connected to each other at the other end. The node of the other ends of MOS transistors 63 l to 63 n is connected to one end of data-reading, n-channel MOS transistor 38. The node of the other ends of MOS transistors 64 l to 64 n is coupled to one end of data-writing, p-channel MOS transistor 65. The other end of data-reading MOS transistor 38 is coupled to the input terminal of sense amplifier circuit 40 and also to resistor 42 which in turn is coupled to power supply Vcc. Transistor 38 is turned on by a read-mode signal. The other end of data-writing MOS transistor 65 is coupled to high-voltage power supply Vpp. Transistor 65 is turned on by the output signal of buffer circuit 43 which is coupled to power supply Vpp. The input terminal of buffer circuit 43 is connected to the output terminal of NAND gate 66 for providing the logical sum of the write-mode signal and data Din to be written into the PROM. Buffer circuit 43 and NAND gate 66 constitute gate circuit 67 for writing data into the PROM. The operation of the PROM shown in Fig. 9 will now be explained. In order to read data from the PROM, the read-mode signal at level "1" is supplied to data-reading MOS transistor 38, and the write-mode signal at level "0" is supplied to one of the two input terminals of NAND gate 66. Hence, MOS transistor 38 is turned on, and data-writing MOS transistor 65 is turned off. In the read mode, one of outputs A l to A n of data-reading, column decoder (not shown) rises to level "1", thereby selecting one MOS transistor 63 j (j = 1 to n) provided in first column-selecting circuit 61. The selected MOS transistor 63 j is turned on. Also, in the read mode, all outputs B l to B n of the data-writing, column decoder (not shown) are at level "1", and MOS transistors 64 l to 64 n of the second column-selecting circuit are turned off. Hence, the data read from memory cell 32 ij selected by row decoder 35 and the data-reading column decoder is supplied to sense amplifier circuit 40. Sense amplifier circuit 40 amplifies this data, and the amplified data, or output data Dout, is supplied from the output terminal of sense amplifier circuit 40. On the other hand, in order to write data, the write-mode signal at level "1" is supplied to the first input terminal of NAND gate 66, and the read-mode signal at level "0" is supplied to data-reading MOS transistor 38. All outputs of the data-reading, column decoder are set at level "0". Therefore, MOS transistor 38 and all MOS transistors 63 l to 63 n of first column-selecting circuit 61 are turned off. When data Din is "1" in this condition, the output of NAND gate 66 falls to level "0", whereby data-writing MOS transistor 65 is turned on. A high voltage is thereby applied from high-voltage power source Vpp to column-signal line 34 j through MOS transistor 65 and then through column-selecting MOS transistor 64 j selected by the data-writing, column decoder. Data "0" is thus written into memory cell 32 ij connected to row-signal line 33 i selected by row decoder 35 and to column-signal line 34 j selected by the data-writing, column decoder. When data Din is "1" while the write-mode signal and the read-mode signal are at level "1" and level "0", respectively, the output of NAND gate 66 rises to level "1". In this case, data-writing MOS transistor 65 is turned off. Since data-reading MOS transistor 38 is also off at this time, no high voltage Vpp is applied to memory cell 32 ij selected by the data-writing, column decoder and row decoder 35. Hence, data "1" is written into memory cell 32 ij . Fig. 10 shows memory cell 32 ij and the circuit for writing data into this cell 32 ij . In order to write data "0" into memory cell 32 ij , a voltage at GND level i.e., level "0", is applied to the gate of data-writing MOS transistor 65, and also to the gate of column-selecting MOS transistor 64 j used for writing data. High voltage Vpp is applied to the back gates of MOS transistors 65 and 64 j . Both transistors 65 and 64j are of p-channel type, and their drain potentials Vc and Vd are not lowered by the threshold voltage and are thus equal to voltage Vpp applied to the source of transistor 65. Hence, high voltage Vpp is applied between the source and drain of memory cell 32 ij , whereby a current great enough to write data "0" into cell 32 ij is obtained. As has been described above, two column-selecting circuits are provided, that is, first column-selecting circuit 61 comprising n-channel MOS transistors 63 l to 63 n for reading data from memory cells 32 ll to 32 mn , and second column-selecting circuit 62 comprising p-channel MOS transistors 64 l to 64 n for writing data into memory cells 32 ll to 32 mn . Second column-selecting circuit 62 is used to apply voltage Vpp to the drains of memory cells 32 ll to 32 mn . First column-selecting circuit 61 is used to read GND-level or level "0" data since the sources of memory cells 32 ll to 32 mn , which are n-channel transistors, are at GND potential. MOS transistors 63 l to 63 n of first column-selecting circuit 61 must be of n-channel type in order to read GND-level data. Were they p-channel MOS transistors, their drain potential would not be at the GND level. Rather, their drain potential would be at a level higher than the GND level by V THP , i.e., the threshold voltage of the p-channel MOS transistors. Since two column-selecting circuits 61 and 62 are used, high voltage Vpp does not fall when data "0" is written into any memory cell. Hence, not only data "1" but also data "0" can be efficiently written into the memory cells, even if voltage Vpp is set at a relatively low level. Therefore, voltage Vpp is set at a low level, thus preventing a deterioration of the LSI in which the PROM is incorporated, and also preventing a latch-up phenomenon. For the same reason, the Vpp-generating circuit can be fabricated within the LSI, involving no particular technical difficulties. Fig. 11 shows a further PROM, according to a third embodiment of the present invention. In this figure, the same numerals and symbols are used to denote the same elements as used in the PROM shown in Fig. 9. This PROM differs from the PROM of Fig. 9 in that one column-selecting circuit 71 is used in place of two circuits 61 and 62. This column-selecting circuit 71 comprises complementary transmission gates 70 l to 70 n , each consisting of one n-channel MOS transistors and one p-channel MOS transistor. More specifically, as is shown in Fig. 11, first gate 70 l consists of n-channel MOS transistor 68 l and p-channel MOS transistor 69 l , second gate 70₂ consists of n-channel MOS transistors 68₂ and p-channel MOS transistor 69₂, and so forth. And the last gate 70 n consists of n-channel MOS transistor 68 n and p-channel MOS transistor 69 n . In each transmission gate, the n-channel and p-channel MOS transistors are connected in parallel to each other. The n-channel MOS transistors 68 l to 68 n of transmission gates 70 l to 70 n are turned on by decode signals A l to A n output from a column decoder (not shown), thereby to read data from memory cells 32 ll to 32 mn . On the other hand, the p-channel MOS transistors 69 l to 69 n of transmission gates 70 l to 70 n are turned on by decode signals A l to A n output from the decoder (not shown) whose level is inverted to that of signals A l to A n , thereby to write data into memory cells 32 ll to 32 mn . That is, the transmission gates can function in both a data-read mode and a data-write mode, in accordance with decode signals A l to A n output from the column decoder (not shown) and decode signals A1 to An obtained by inverting decode signals A l to A n . In the PROM shown in Fig. 11, the GND-level data is output through the n-channel MOS transistor of a transmission gate, and the Vpp-level data is input through the p-channel MOS transistor of the transmission gate. Therefore, high voltage Vpp does not fall by the threshold voltage V THN of the n-channel MOS transistor when data "0" is written into the selected memory cell. Neither does the GND-level voltage rise by the threshold voltage V THP of the p-channel MOS transistor when data "0" is read from the selected memory cell. Unlike the PROM shown in Fig. 9, the PROM of Fig. 11 has only one column-selecting circuit, i.e., circuit 71. It follows that this PROM needs to have only one column decoder. Decode signals A l to A n , and A₁ to A n are used to control transmission gates 70 l to 70 n . Hence, the PROM of Fig. 11 does not require so large a pattern area as the PROM shown in Fig. 9. Fig. 12 illustrates still another PROM, according to a fourth embodiment of the present invention. In this figure, too, the same numerals and symbols are used to represent the same elements as used in the PROM shown in Fig. 9. This PROM differs from that of Fig. 9 in that first column-selecting circuit 61 for reading data is provided on one side of memory-cell array 31, whereas second column-selecting circuit 62 for writing data is provided on the other side of array 31. This specific arrangement reduces the required area on the semiconductor chip. Column-signal lines 34 l to 34 n are arranged parallel at extremely short intervals, thereby raising the integration density of the PROM. Were column-selecting circuits 61 and 62 both provided on one and the same side of memory-cell array 31, the output lines of the column decoders (not shown) would of necessity be connected on this side of array 31, not only to n-channel MOS transistors 63 l to 63 n but also to p-channel MOS transistors 64 l to 64 n . Forming as many nodes as all these MOS transistors would require a pattern area larger than that needed in the PROM of Fig. 12 in which column-selecting circuits 61 and 62 are provided on the opposite sides of cell array 31. Moreover, this specific arrangement of column-selecting circuits 61 and 62 ensures complete electrical isolation between n-channel MOS transistors 63 l to 63 n , on the one hand, and p-channel MOS transistors 64 l to 64 n , on the other. That is, if n-channel MOS transistors 63 l to 63 n were arranged near p-channel MOS transistors 64 l to 64 n as in the PROM shown in Fig. 9, a latch-up phenomenon would likely occur. This undesired phenomenon should be avoided at all cost, because, in writing data in the PROM, a large current of tens of milliamperes flows through data-writing MOS transistors 64 l to 64 n . As has been described above, in the semiconductor memories according to the embodiments of Figs. 9 - 12, data "0" can be written into each memory cell at a sufficiently high speed, even if the data-writing voltage is relatively low. Fig. 13 shows the pattern in which the elements of column-selecting circuit 62 for writing data are arranged in the PROM illustrated in Fig. 12. In this figure, the same numerals and symbols are used to designate the same elements as shown in Fig. 12. As is shown in Fig. 13, aluminum strips 81 l to 81 l5 are arranged parallel to one another. Contacts holes 82 l to 82 l8 are provided to connect some elements to others. Polycrystalline silicon layers 83 l to 83₇ and diffusion layers 84 l and 84₂ are also provided. Numerals 85 l to 85₄ denote the floating gates of memory cells 32 l to 32₄. MOS transistors 64 l to 64₄ are formed in the hatched regions. As has been described above, the present invention can provide a semiconductor memory wherein, even if the memory cells have different operation points arising from differences in their respective process parameters, the data-writing characteristic of each memory cell can be sufficiently stable, thereby ensuring that data can be written into each cell at high speed, and which can, therefore, be manufactured with a high yield. Furthermore, the present invention can provide a semiconductor memory wherein data "0" can be written into each memory cell at a sufficiently high speed, even if the data-writing voltage is relatively low.

Claims: A semiconductor memory comprising: means for connecting a data writing potential; means for connecting a reference potential; a PROM cell (21), a first MOS transistor (51) and a second MOS transistor (52) connected in series between said data writing potential and said reference potential, wherein the PROM cell (21) is of a first channel type, and is electrically programmable to store data therein; and the first MOS transistor (51) is of a second channel type; characterized in that a gate of said PROM cell receives a row selection signal; a gate of said first MOS transistor (51) receives a write signal to determine the operation point of said PROM cell when the memory is set in a data-writing mode; and the second MOS transistor (52) is of said second channel type, and a gate of said second MOS transistor receives a column selection signal to decrease time required for writing data into said PROM cell; and further comprising means for generating and supplying said row selection signal to the gate of said PROM cell; means for generating and supplying said write signal to the gate of said first MOS transistor; and means for generating and supplying said column selection signal to the gate of said second MOS transistor. A semiconductor memory according to claim 1, characterized in that said PROM is an n-channel MOS transistor, and said first and second MOS transistors (51, 52) are of p-channel. A semiconductor memory according to claim 1, characterized in that said PROM cell (21) is a floating gate MOS transistor. A semiconductor memory comprising: a plurality of n-channel floating gate MOS transistors arranged in rows and columns, and used as memory cells (32 ll to 32 mn ); a plurality of row lines (33 l to 33 m ) equal in number to the rows of memory cells, one row line being connected to the gate of each of the memory cells of the corresponding row; a plurality of column lines (34 l to 34 n ) equal in number to the columns of memory cells, one column line being connected to the drain of each of the memory cells of the corresponding column, a data-writing, column-selecting circuit (62,71) including a plurality of p-channel MOS transistors (64 l to 64 n ) each connected at one end to one of said column lines, respectively, and controlled by data-writing, column-decode signals; a data-reading, column-selecting circuit (61,71) including a plurality of n-channel MOS transistors (63 l to 63 n ; 68 l to 68 n ) each connected at one end to one of said column lines, respectively, and controlled by data-reading, column-decode signals; characterized in that a data-writing, p-channel MOS transistor (65) is connected to the other ends of the p-channel MOS transistors of said data-writing, column-selecting circuit, for applying a high voltage to those memory cells selected and turned on when the semiconductor memory is set in level "0" data-writing mode; and the p-channel MOS transistors (69 l to 69 n ) of said data-writing column-selecting circuit are connected in parallel with the n-channel MOS transistors (68 l to 68 n ) of said data-reading, column-selecting circuit, respectively, thereby forming transmission gates (70 l to 70 n ). A semiconductor memory comprising: a plurality of n-channel floating gate MOS transistors arranged in rows and columns, and used as memory cells (32 ll to 32 mn ); a plurality of row lines (33 l to 33 m ) equal in number to the rows of memory cells, one row line being connected to the gate of each of the memory cells of the corresponding row; a plurality of column lines (34 l to 34 n ) equal in number to the columns of memory cells, one column line being connected to the drain of each of the memory cells of the corresponding column; a data-writing, column-selecting circuit (62, 71) including a plurality of p-channel MOS transistors (64 l to 64 n ) each connected at one end to one of said column lines, respectively, and controlled by data-writing, column-decode signals; a data-reading, column-selecting circuit (61, 71) including a plurality of n-channel MOS transistors (63 l to 63 n ; 68 l to 68 n ) each connected at one end to one of said column lines, respectively, and controlled by data-reading, column-decode signals; characterized in that a data-writing, p-channel MOS transistor (65) is connected to the other ends of the p-channel MOS transistors of said data-writing, column-selecting circuit, for applying a high voltage to those memory cells selected and turned on when the semiconductor memory is set in level "0" data-writing mode; and said data-writing, column-selecting circuit (62, 71) and said data-reading, column-selecting circuit (61, 71) are located at opposite sides of a cell matrix comprising said floating gate MOS transistors.

Inventors: NAKAMURA, TOSHIMASA C/O PATENT DIVISION, SAEKI, YUKIHIRO C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1987
Main classification: G11C16
IPC codes: G11C16