Noise reduction circuit

Abstract: The present noise reduction circuit comprises a first circuit (20, 22) for extracting a relatively high frequency component of an input singal and amplitude-limiting a component of said amplitude-limited high frequency component exceeding a predetermined level, a second circuit (2l) for delaying said input singal such as a video signal by a predetermined time, and a third circuit (24) for adding outputs of said first and second circuits and outputting an added result as an output of said noise reduction circuit.

Description: The present invention generally relates to a noise reduction circuit, and in particular to a noise reduction circuit for effectively reducing noise components of a signal such as a video signal processed in a video tape recorder. FIG.1(A) is a systematic block diagram of a conventional noise reduction circuit (see the United State Patent US-A-4,563,704, for example). Referring to this figure, an input video signal a as shown in FIG.2(A) which is applied to an input terminal 11 is fed to a high-pass filter 12, at which high frequency components b as shown in FIG.2(B) are extracted from the video signal. A limiter 13 amplitude-limits the high frequency components passing through the high-pass filter 12. Then, the limiter 13 provides a subtractor 14 with the amplitude-limited high frequency component signal, or a noise component signal c as shown in FIG.2(C) through a coefficient circuit 16 for giving the output of the limiter 13 a predetermined coefficient k ( k is an arbitrary number). The subtractor 14 subtracts the noise component signal c from the video signal a and provides an output terminal 15 with an output signal d ′ as shown in FIG.2(D) in which the noise components are reduced. However, the conventional noise reduction circuit described above has a disadvantage in that partial signal loss is introduced in a rising part of the output signal d ′ changing from black level to white level, as indicated with P in FIG.2(D). In addition, the conventional circuit has another disadvantage in that the noise components still remain at that rising part of the output signal d ′ as shown in FIG.2(D). FIG.1(B) illustrates another conventional noise reduction circuit (see the above publication, for example). In this figure, the input signal applied to the terminal 11 is supplied to a low-pass filter 17 and a delay circuit 19. The latter delays the received signal by a predetermined time and provides subtractors 14 and 18 with the delayed input signal. The subtractor 18 subtractors an output signal of the low-pass filter 17 from an output signal of the delay circuit 19 and feeds a subtracted result through the limiter 13 to the subtractor 14. Then, the subtractor 14 subtracts the output signal of the limiter 13 from the output signal of the delay circuit 19, and supplies an output signal to the terminal 15. Although the noise reduction circuit in FIG.1(B) effectively reduces the noise components as compared with the circuit in FIG.1(A), it still has a disadvantage in that signal loss is brought about at the rising part of the output signal changing from black level to white level at the terminal 15. This is mainly because subtraction between the output signal of the delay circuit 19 and the output signal of the limiter 13 which have the same phase and time relationship as each other is performed. According to a first aspect of the present invention there is provided a noise reduction circuit as defined in appended Claim 1. According to a second aspect of the present invention there is provided a noise reduction circuit as defined in appended Claim 10. Preferred embodiments of the present invention are defined in the other appended claims. It is thus possible to provide a suitable noise reduction circuit for video recording and/or reproducing apparatus, the circuit comprising first means for extracting a relatively high frequency component of an input signal and amplitude-limiting a component of said extracted high frequency component exceeding a predetermined level; second means for delaying said input signal by a predetermined time; and third means for adding an output signal of said first means and an output signal of said second means, and outputting an added result as an output signal of said noise reduction circuit. The present invention will be further described, by way of example, with reference to the accompanying drawings, in which: FIG.1(A) is a systematic block diagram of a conventional noise reduction circuit; FIG.1(B) is a systematic block diagram of another conventional noise reduction circuit; FIG.2 shows signal waveforms at each part of the block diagram in FIG.1(A); FIG.3(A) is a systematic block diagram of a first embodiment according to the present invention, FIG.3(B) is a circuit diagram of a delay circuit shown in FIG.3(A), FIG.4 shows signal waveforms at each part of the block diagram in FIG.3(A), FIG.5 is an equivalent block diagram with regard to the block diagram of FIG.3(A) when noise components which are not amplitude-limited by a limiter are considered, FIG.6 shows a delay time v. frequency response of the delay circuit in FIG.3(A), FIG.7 shows an amplitude v. frequency response of the configuration in FIG.3(A), FIG.8 is a block diagram for explaining the transfer function of a basic part in the noise reduction circuit according to the present invention, FIG.9 shows transfer function v. frequency characteristics of the basic part in the noise reduction circuit according to the present invention, FIG.10 is a block diagram for explaining the transfer function of the whole configuration of the noise reduction circuit according to the present invention, FIG.11 shows a transfer function characteristic of the whole configuration of the noise reduction circuit according to the present invention, FIG.12 shows another delay response of the delay circuit in FIG.3(A), FIG.13 shows an amplitude v. frequency response of the delay circuit having the delay characteristic shown in FIG.12, FIG.14 shows still another delay characteristic of the delay circuit in FIG.3(A), FIG.15 is a systematic block diagram of a second embodiment according to the present invention, FIG.16 is a systematic block diagram of a third embodiment according to the present invention, FIG.17 shows an amplitude v. frequency response of an output signal of a subtractor shown in FIG.16, FIG.18 shows amplitude v. frequency responses of an output signal of an adder shown in FIG.16, FIG.19 shows signal waveforms at each part of the block diagram in FIG.16, and FIG.20 is a systematic block diagram of a fourth embodiment according to the present invention. Referring to FIG.3(A) which illustrates a configuration of the first embodiment according to the present invention, an input signal a as shown in FIG.4(A) such as a video signal having noise components is applied to both a high-pass filter 20 and a delay circuit 21 via the input terminal 11. The delay circuit 21 made up of an LC filter, for example, delays the input signal a by a predetermined time Δτ. The amount of the delay time τ is determined, taking into consideration not only the period of time during which noise components are being limited at a limiter 22 but also the frequency of noise components to be reduced. The delay circuit 21 can be formed with a concrete circuit as shown in FIG.3(B). The delay circuit of this example is formed by the combination of inductors L1, -L2, L3 and L4 and capacitors C1, C2, C3 and C4. Of course, it is possible to employ other configuration such as a glass delay circuit. The input signal a is delayed by the time Δτ and is then fed to one of terminals of an adder 24 as a signal d shown in FIG.4(D). On the other hand, the video signal a is filtered by the high-pass filter 20, which outputs a signal b of high frequency components shown in FIG.4(B). The signal b is supplied to the limiter 22, which outputs a noise component signal c shown in FIG.4(C). Then, the noise component signal c is applied to the other input terminal of the adder 24 through a coefficient circuit 23 which weighs the signal d with a predetermined coefficient k ( k is an arbitrary number), as will be discussed later. In principle, the use of the coefficient circuit 23 is not necessarily to achieve the generic object of the invention. However, in the practical use of the invention, it is preferably to use the coefficient circuit 23. An attenuator may be utilized as the coefficient circuit 23. The adder 24 provides the output terminal 15 with an output signal e shown in FIG.4(E). It will be apparent from FIG.4(E) that the output signal e at the terminal 15 has no signal loss at the rising part changing from black level to white level. Of course, no noise component exists at the rising part of the signal e as illustrated in FIG.4(E). In this case, although a signal part just prior to the rise part from black level to white level still have noise components, those components do not cause substantial visual problems, because the level of the noise components is near the black level. The description will now be given of reasons why the noise components are reduced without loss of the signal, and the signal e as shown in FIG.4(E) is thus obtained. Consider noise components which are not amplitude-limited by the limiter 22. In this case, the configuration shown in FIG.3(A) equivalently corresponds to a configuration shown in FIG.5. Under this situation, assume that the delay time v. frequency response, or the delay characteristic of the delay circuit 21 is flat as shown in FIG.6 and that the amplitude characteristic thereof is also flat. Under those conditions, the output signal of the delay circuit 17 has an inverted phase relationship with respect to its input signal a at a frequency f1 satisfying f1≒(1/2)(1/Δτ) , while the output signal has the same phase relationship as the input signal a at a frequency f2 satisfying f2≒1/Δτ . Accordingly, the amplitude v. frequency response of the output signal e of the adder 24 has a dip whose amplitude A₁≒20log(1-k) at the frequency f1, and a peak whose amplitude A₂≒20log(1+k) at the frequency f2, as shown in FIG.7. When Δτ≒280ns, for example, f1≒1.8MHz and f2≒3.6MHz. The delay time of this example is selected, taking into consideration the frequency range (1MHz-2MHz) of the noise components within which there exists visually most conspicuous noise components on the video signal. In case of popular home video recording and reproducing apparatus, the luminance signal in the video signal to be frequency-modulated ranges up to 3.0MHz, it is unnecessary to take into consideration the output signal of the frequency f2 as the f2 is normally out of the frequency range of the luminance signal. As a result, it is possible to obtain the output signal e in which the noise components in the vicinity of the frequency f1≒1.8MHz is considerably reduced, as shown in FIG.7 with the higher frequency components above 1.8MHz less attenuated. Now consider the relationship between the frequency and the transfer function in the noise reduction circuit in FIG.3(A). Supposing that the delay time of the delay circuit 21 is represented as Td and its coefficient is e -jωTd and that the transfer function between the input x and the output y is H(ω), the following equations can be obtained: y/x=k+e -jωTd H(ω)={k+cos(ωTd)}-jsin(ωTd) Therefore, the transfer function v. frequency characteristics with coefficients k as parameters, are as shown in FIG.9. It will be understood from this figure that the transfer function of the delay circuit 22 depends on the coefficient k . Further, assume that the delay time of the high-pass filter 20 is represented by Tc and its coefficient is (jωTc)/(1+jωTc) , the following equations can be obtained: y/x=kjωTc/(1+jωTc)+e jωTd =jkωTc/(1+jωTc)+cos(ωTd)-jsin(ωTd) H(ω)=[{cos(ωTd)+ωTcsinωTd}+j{kωTc+ωTccos(wTd)-sin(ωTd)}]/(1+jωTc) Therefore, the transfer function v. frequency characteristic as shown in FIG.11 is obtained. The above equations f1≒(1/2)(1/Δτ) , and f2≒1/Δτ are satisfied when the cut-off frequency f c of the high-pass filter 20 is considerably small as compared with the frequency f1. The relationship between f1 and f2 is a little different from the above relationship when the phase characteristic of the high-pass filter 20 cannot be ignored. In this case, the frequency f min is shifted from the frequency f1 by the amount corresponding to the amount of the phase which is led at the high-pass filter 20. In the configuration shown in FIG.3(A), the delay response of the delay circuit 21 is not limited to be flat as shown in FIG.6, and the delay response shown in FIG.12 in which the amount of the delay time varies as the frequency, may be employed (whereas the amplitude response is flat). In this case, assume that f3=(1/2)(1/Δτ₃) , and f4=1/Δτ₄ , the frequency characteristic of the delay circuit 21 as shown in FIG.13 in which f5≒f3 and f6≒f4, is obtained. It will be apparent from FIG.13 that it is possible to set the frequency f2 higher (3.6MHz, for example) than the frequency f5 (5MHz, for example) shown in FIG.7, and it is therefore possible to further reduce the noise components of the frequency range in which the noise is especially conspicuous, as compared with the case shown in FIG.7. Moreover, it is possible to use an arbitrary delay response as shown in FIG.14 (in this case, the amplitude response is flat). Still further, it is possible to obtain an output signal as shown in FIG.4(F) when the delay time of the delay circuit 21 is set to Δτ/2. In this case, noise components still remain immediately after the rise of the signal changing from black level to white level. However, the noise components do not cause the visual problems, because the levels of those noise components are over the white level. FIG.15 illustrates a configuration of the second embodiment according to the present invention. In this figure, elements indicated by the same numbers as those in FIGS.1(A) and 3(A) are the same elements as those in FIGS.1(A) and 3(A). The second embodiment corresponds to the combination of the configurations shown in FIGS.1(A) and 3(A). In detail, the noise reduction circuit shown in FIG.3(A) follows the configuration shown in FIG.1(A). That is, a first stage of the noise reduction circuit in FIG.15 consists of the input terminal 11, the high-pass filter 12, the limiter 13, the coefficient circuit 16 having a coefficient k1 and the subtractor 14. A second stage consists of the high-pass filter 20, the limiter 22, the coefficient circuit 23 having a coefficient k2, a delay circuit 25, the adder 24 and the output terminal 15. The delay circuit 25, which has a similar configuration as the delay circuit 21, delays the output signal d′ of the subtractor 14 by the time Δτ/2. In the operation, the signal d′ shown in FIG.2(D) is delayed by the time Δτ/2 at the delay circuit 25 and is then processed by the second stage of the noise reduction circuit in a similar way as the first embodiment in FIG.3(A). An output signal obtained at the output terminal 15 is as shown in FIG.4(F). It will be apparent from this figure that the signal loss immediately after the rise from black level to white level is effectively compensated. As a variation of the second embodiment, the connection of the first and second stages may be reversed. That is, the second stage described above receives the input signal via the input terminal 11 and the output of the second stage is received by the first stage, which supplies the output signal to the terminal 15. According to this variation, it is also possible to obtain a similar output signal as the signal illustrated in FIG.4(F). FIG.16 illustrates a configuration of the third embodiments according to the present invention. In this figure, elements indicated by the same numerals as those in FIG.15 are the same elements as those in FIG.15. The feature of the third embodiment is to remove a set of the high-pass filter 20 and the limiter 22 in FIG.15. That is, the signal c from the limiter 13 is directly supplied to the coefficient circuit 23 without passing through the high-pass filter 20 and limiter 22 in FIG.15. In operation, an output signal d ″ from the subtractor 14 shown in FIG.19(C), in which noise components still remain, is delayed by the time Δτ/2=(1/2)T L (T L represents the period of time in which the amplitude is limited at the limiter 13) by the delay circuit 25. Then, a signal f shown in FIG.19(D) derived from the delay circuit 25 is added by the adder 24 to the signal c shown in FIG.19(B) which passes through the coefficient circuit 23. Then the adder 24 outputs a signal g shown in FIG.19(E). As shown in FIG.19(E), although the noise components having a relatively small amplitude remain at the part just prior to the rise of the signal g , and the noise components having a relatively large amplitude also remain at the part immediately after the rise thereof, the noise duration time in the signal g is made half as much as that of the signal d ″shown in FIG19.(D). In addition, the signal loss at the rising part thereof of the signal g is improved as compared with the signal d ″. In the noise reduction circuit in FIG.16, the amplitude v. frequency response of the output signal d ″ from the subtractor 14 is as shown in FIG.17, and the amplitude v. frequency response of the output signal g from the adder 24 is as shown in FIG.18. It will be understood from comparison between those figures that the third embodiment is capable of effectively reducing the noise components in the vicinity of the frequency f1, as compared with the conventional circuit. It is also possible to obtain the amplitude v. frequency response represented by the solid line or the dotted line in FIG.18, by setting an appropriate delay time in the delay circuit 25 (Δτ₁>Δτ₂, in this example). FIG.20 illustrates the fourth embodiment according to the present invention. In this figure, elements indicated by the same numerals as those in the previous figures are the same elements as those in the previous figures. The feature of the fourth embodiment is in that an equalizer 26 is interposed between the limiter 22 and the coefficient circuit 23. The equalizer 26 is directed to reduce high-frequency noise components which are introduced into the amplitude-limiting process at the limiter 22. That is, the equalizer 26 passes noise components of the output signal of the limiter 22 without reducing thereof yet dulls the waveforms of the noise components appropriately. Therefore, the fourth embodiment can reduce high-frequency noise components which are not originally included in the input signal at the terminal 11 and also which is generated in the limiting process at the limiter 22.

Claims: A noise reduction circuit comprising, first means (20, 22) for extracting a high frequency component of an input signal and then amplitude-limiting a component of said extracted high frequency component exceeding a predetermined level, characterised by second means (21) for delaying said input signal by a time Δτ which is dependent on the period of time during which the noise components are amplitude limited and on the frequency of the noise to be reduced, and third means (24) for adding an output signal of said first means and an output signal of said second means and for outputting an added result as an output signal of said noise reduction circuit. A noise reduction circuit as claimed in Claim 1, characterised in that said first means further comprises coefficient means (23) for weighing said output of said first means (20, 22) with a predetermined coefficient. A noise reduction circuit as claimed in Claim 1, characterised in that said predetermined time Δτ is constant as a function of frequency. A noise reduction circuit as claimed in Claim 1, characterised in that an amplitude v. frequency response of said second means (21) is nearly flat. A noise reduction circuit as claimed in Claim 1, characterised in that said delay time Δτ of the second means (21) satisfying (1/2)(1/Δτ)≒f1 is selected where f1 is a representative frequency of predetermined noise component intended to be reduced, said predetermined noise component having said representative frequency being visually conspicuous compared to noise components other than said predetermined noise components. A noise reduction circuit as claimed in Claim 5, characterised in that said delay time Δτ is set to approximately 280ns when said input signal is a video signal. A noise reduction circuit as claimed in Claim 1, characterised in that a delay time v. frequency characteristic of said second means (21) varies as a function of frequency. A noise reduction circuit as claimed in Claim 1, characterised in that said noise reduction circuit further comprises fourth means (12, 13) for extracting a high component of said input signal and amplitude-limiting a component of said extracted high frequency component exceeding a predetermined level, and fifth means (14) for subtracting an output signal of said fourth means (12, 13) from said input signal applied to said first means, so that an output signal of said fifth means (14) is supplied to said first and second means. A noise reduction circuit as claimed in Claim 1, characterised in that said noise reduction circuit further comprises an equalizer (26) for reducing a high frequency noise component which is generated due to the limiting process by said first means (20, 22), and supplying said reduced high frequency component to said third means (24). A noise reduction circuit comprising, first means (12, 13) for extracting a high frequency component of an input signal and amplitude-limiting a component of said extracted high frequency component exceeding a predetermined level, second means (14) for subtracting an output of said first means (12, 13) from said input signal, characterised by third means (25) for delaying an output of said second means (14) by a delay time which is dependent on the period of time during which the noise components are amplitude limited and the frequency of the noise to be reduced, and fourth means (24) for adding an output of said first means (12, 13) and an output of said third means (25) and for outputting an added result as an output signal of said noise reduction circuit. A noise reduction circuit as claimed in Claim 10, characterised in that said predetermined time is set to a half of the period of time during which amplitude-limiting operation of said first means (12, 13) is performing.

Inventors: FUJIHARA HISASHIGE, FUKUDA HISATOSHI, FUJIHARA, HISASHIGE, FUKUDA, HISATOSHI
Applicants: VICTOR COMPANY OF JAPAN, VICTOR COMPANY OF JAPAN, LIMITED
Application year: 1987
Main classification: H04N5
IPC codes: H04N5, H03H7