Data demodulation system

Abstract: Disclosed is a data demodulation system for reproducing data dividedly recorded in a plurality of recording blocks of a recording medium, comprising the steps of adding specified data patterns to the data bits of dividing portions of each recording block and modulating the recording block and specified data patterns, and adding a specified coded pattern to the modulator signal pattern.

Description: This invention relates to a data modulating/ demodulating method and apparatus used in magnetic recording, optical recording, etc. Conventionally, one known sequential coding method of constant ratio data codes of variable word length is the 2-7 modulation/demodulation system as described in United States Patent Specification No. 4115768 (the disclosure of which is included herein by way of reference) is known. In the 2-7 modulation/demodulation system, as shown in Fig. 2, 2-bit codes are used for 1-bit data, and when demodulating, in order to convert 2-bit codes into original 1-bit data, a demodulation clock DMCK is needed. Fig. 3 refers to an example of a conventional demodulation circuit employed in the 2-7 modulation/ demodulation system. In this system the read data RDDT is introduced into a shift register 11 which is operated by a read clock RDCK. The output of the shift register 11 is introduced into a logic gate circuit 12, and this output is synchronized by a demodulation clock DMCK having 1/2 the period of read clock RDCK and introduced into a demodulation clock generator circuit 13, thereby obtaining demodulated data S20. Thus, in the conventional circuit, since the demodulation clock DMCK is obtained by compressing the read clock RDCK to 1/2 period by flip-flop 22 and AND gate 21, if a wrong inversion occurs in the demodulation clock DMCK due to noise or some other cause, all the subsequent demodulated data S20 is wrong. The invention claimed in European patent application 87300832.0 (now granted as European patent 0232144), from which this application is divided, related to the use of two mutually phase-shifted clock signals to provide respective demodulated versions of a predetermined signal pattern in each data block of a signal, these different versions being compared with a demodulation pattern known to be correct, so as to permit selection of the particular demodulating clock signal producing the correct result. In this way if an incorrect inversion occurs in the clock, normal operation can be quickly restored, so that error in the demodulated data is limited to one data block. To enable this system of European patent 0232144 to operate securely, it is important to be able to detect accurately the beginning of each block. The present invention aims to provide a method and apparatus enabling such secure data block detection. IBM TDB Vol. 27, No. 7B, December 1984, pages 4274 to 4277, IEEE Spectrum 21 (1984) Mar., No. 3, New York, USA, and Electronics and Wireless World, 91(1985) May, No. 1591, pages 27 and 28, disclose methods for providing a modulated signal and synchronisation pattern from data signal dividedly recorded in a plurality of recording blocks on a recording medium. The third of these documents discloses the addition of a specified data pattern to a data dividing portion of each recording block, and the second document dislcoses the modulation of each recording block and its specified data pattern to provide a respective coded signal portion separated from adjacent coded signal portions at coded dividing portions. Also, the first of these documents suggests adding a specified coded pattern which cannot be obtained from the coding of the data bits to the coded signal portion at a coded dividing portion. According to the present invention, there is provided a data modulating/demodulating method for reproducing correct data which has been divided and recorded in a plurality of blocks on a recording medium, each of said plurality of blocks being separated from adjacent blocks at identifiably coded dividing portions characterised in that said method comprises, the steps of: (a) adding a specified data pattern to each block at said dividing portion to enable modulation of the block; (b) modulating each block and its specified data pattern to provide a respective coded signal portion separated from adjacent coded signal portions at coded dividing portions; (c) adding a specified coded pattern to said coded signal portion at said coded dividing portion so as to form a coded signal for recording on said recording medium; (d) demodulating said coded signal so as to reproduce said correct data in said plurality of blocks from said recording medium, wherein as a result of said step (c) a combined coded pattern including a first coded pattern and a second coded pattern is obtained at each of said coded dividing portions, said first coded pattern corresponding to a pattern obtained by modulating said specified data pattern, said second pattern being said specified coded pattern, and wherein said combined coded pattern is a resynchronization pattern which is used to detect said dividing portions of said plurality of blocks. According to the present invention, there is also provided a modulating/demodulating apparatus for reproducing correct data which has been divided and recorded in a plurality of blocks on a recording medium, each of said plurality of blocks being separated from adjacent blocks at identifiably coded dividing portions, characterised in that said apparatus comprises; first adding means for adding a specified data pattern to each block at said dividing portion to enable a modulation of the block; modulating means for modulating each block and its specified data pattern to provide a respective coded signal portion separated from adjacent coded signal portions at coded dividing portions; second adding means for adding a specified coded pattern to said coded signal portion at said coded dividing portion so as to form a coded signal for recording on said recording medium; demodulating means for demodulating said coded signal so as to reproduce said correct data in said plurality of blocks from said recording medium, wherein said second adding means is arranged so that a combined coded pattern including a first coded pattern and a second coded pattern is obtained at each of said coded dividing portions, said first coded pattern corresponding to a pattern obtained by modulating said specified data pattern, said second pattern being said specified coded pattern, and wherein said combined coded pattern is a resynchronization pattern which is used to detect said dividing portions of said plurality of blocks. The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: Fig. 1 is a block diagram of a system configuration for performing the demodulation system according to this invention; Fig. 2 is an explanatory diagram to show the coding type of the 2-7 modulation/demodulation system; Fig. 3 is a circuit diagram of a conventional demodulation circuit; Fig. 4 is an explanatory diagram of a recording format in recording medium; and Fig. 5 and Fig. 6 are explanatory diagrams of bit patterns. Referring now to the drawings, this invention is described herein in detail, specifically relating to some of its embodiments. Fig. 4 shows an example of the recording format employed in magnetic recording, optical recording, etc. Fig. 1 is a block diagram of the system configuration for the demodulation system of this invention. The tracks on the recording medium are, for example, divided into n₁ sectors as shown in Fig. 4(a). A drive unit (DU) 100 in Fig. 1 writes data in the units of these sectors. Each sector is composed of, a control signal area comprising ID, SYNC, etc., shown in Fig 4(b), and a user data recording area comprising n₂ blocks. Each block is composed of n₃ bytes as shown in Fig. 4(c). At the beginning or at the end of this block, a resynchronisation signal is added composed of a specified data bit pattern and a code bit pattern. The above specified data bit pattern and code bit pattern are briefly described below. The data bit pattern is a bit pattern before modulation. It comprises a row of consecutive data, for example a data row as shown in Fig. 5(a). When this bit pattern is 2-7 modulated, as shown in Fig. 5(b), as the word length of the 2-7 modulation/demodulation system is variable, a bit pattern that cannot be modulated using the 2-7 conversion rule may occur at the end of a data row or at the dividing portion of block. Accordingly, a specified data bit pattern is added in order to satisfy the 2-7 conversion rule to ensure that the entire data of a block or row can be modulated. One example of a suitable specified data bit pattern for application to the end of a data row or block is shown in Fig. 5(c). The specified code bit pattern is a bit pattern after modulation. It is used in the detection of the beginning of a block during demodulating. In order to enhance the reliability of demodulation, a pattern not produced as a result of modulation using the 2-7 conversion code, such as the code bit pattern shown in Fig. 6(a) is preferable. Part (1) of the pattern of Fig. 6(a) is the same as the pattern after modulation of the specified data bit pattern shown in Fig. 5(c). By adding part (2) of Fig. 6(a) to this data row, a pattern which is not produced by modulation using the 2-7 conversion rule is obtained. When the pattern of Fig. 6(a) is demodulated, the result is always the pattern of Fig. 6(b). In the system shown in Fig. 1, the data being read out by the drive unit (DU) 100 for recording and reproducing data is synchronised by a PLL circuit 200, from which read data RDDT and read clock RDCK are delivered. The RDDT and RDCK signals are fed into a pattern detector circuit 10 composed of a shift register, a pattern discriminator, and a 2-7 demodulation circuit 23. The pattern detector circuit 10 discriminates the RDDT, and detects the specified code bit pattern and SYNC pattern, and delivers a detection signal to the comparator 17. The RDDT fed into the 2-7 demodulation circuit 23 is converted into parallel by the shift register 11, and is assembled by a gate group 12 to be returned to serial data S23. The read clock RDCK is directly divided into RDCK and RDCK through NOT circuit 24, which are respectively fed into demodulation clock generator circuits 15, 16, to generate demodulation clock signals DMCK1, DMCK2. DMCK1 and DMCK2 are respectively fed into flip-flops (FF) 13, 14. In the flip-flops (FF) 13, 14, the serial data S23 is synchronised for conversion back into data before modulation. As the data is demodulated in the flip-flops (FF) 13, 14 by demodulation clocks DMCK1, DMCK2 differing in phase, the data output from the respective flip-flops (FF) is different. Only one of the outputs corresponds to the original data before modulation. The outputs of the flip-flops (FF) 13, 14 are fed into a comparator 17, which receives the detection signal of a specified code bit pattern shown in Fig. 6(a) from the pattern detector circuit 10. The outputs of the flip-flops (FF) 13, 14 are compared with the bit pattern of Fig. 6(b) on receipt of the detection signal, and a judgement signal is delivered to a multiplexer (MPX) 18 depending on which output of the flip-flops (FF) 13, 14 corresponds to the bit pattern of Fig. 6(b). The multiplexer (MPX) 18 receives this judgement signal, and selects which output corresponds to the correctly demodulated data signal each time the signal of Fig. 6(a) is detected to ensure that a signal corresponding to the original data signal is delivered to the shift register 19. The present system can thereby keep the spread of error in the demodulated data to a minimum when an incorrect inversion occurs in the read clock RDCK. Besides, as shown in Fig. 1, having two demodulation clock generator circuits 15, 16 and hence a normal demodulation clock DMCK1 and an inverted demodulation clock DMCK2, if an incorrect inversion occurs in the normal demodulation clock DMCK1, the next time the signal of Figure 6(a) is detected, the multiplexer (MPX) 17 selects the other demodulation clock DMCK2 for demodulation of the signal, so that any error in demodulation is limited to a single block, allowing normal demodulation of subsequent blocks. As is clear from the description above, through the use of two demodulation clocks differing in phase, even if an incorrect inversion occurs in the read demodulation clock due to skipping, overflow or some other cause during the demodulation of any one block, normal operation is restored for demodulation of the next block. The reliability of the demodulated data is thereby enhanced. In order to operate securely, it is important to detect the beginning portion of a block. In this invention, by using a pattern not produced by modulation of a signal using the 2-7 conversion code, that is, by using a pattern which is not produced in the coded data, the beginning of a block can be detected without fail. Incidentally, the pattern of Fig. 6(a) may be also used as the bit pattern of SYNC information.

Claims: A data modulating/demodulating method for reproducing correct data which has been divided and recorded in a plurality of blocks on a recording medium, each of said plurality of blocks being separated from adjacent blocks at identifiably coded dividing portions characterised in that said method comprises, the steps of: (a) adding a specified data pattern to each block at said dividing portion to enable modulation of the block; (b) modulating each block and its specified data pattern to provide a respective coded signal portion separated from adjacent coded signal portions at coded dividing portions; (c) adding a specified coded pattern to said coded signal portion at said coded dividing portion so as to form a coded signal for recording on said recording medium; (d) demodulating said coded signal so as to reproduce said correct data in said plurality of blocks from said recording medium, wherein as a result of said step (c) a combined coded pattern including a first coded pattern and a second coded pattern is obtained at each of said coded dividing portions, said first coded pattern corresponding to a pattern obtained by modulating said specified data pattern, said second pattern being said specified coded pattern, and wherein said combined coded pattern is a resynchronization pattern which is used to detect said dividing portions of said plurality of blocks. A method according to claim 1, wherein said specified data pattern is configured to enable a data signal obtained by adding said specified data pattern to a block to be modulated. A method according to claim 2, wherein said data signal satisfies a 2-7 conversion rule. A method according to any preceding claim, wherein said specified data pattern is added to the end of each block. A method according to any preceding claim, wherein said specified data pattern is "011". A method according to any preceding claim, wherein said step (b) modulates each block and its specified data pattern according to the following table: Data Bits Code Bits 10 0100 010 100100 0010 00100100 11 1000 011 001000 0011 00001000 000 000100. A method according to any preceding claim, wherein said specified coded pattern is configured to enable detection of said dividing portions of said plurality of blocks for resynchronization. A method according to any preceding claim, wherein said specified coded pattern is added to the end of each coded signal portion. A method according to any preceding claim, wherein said specified coded pattern is "0000100100". A method according to claim 1, wherein said combined coded pattern is one which cannot be produced by 2-7 conversion. A modulating/demodulating apparatus for reproducing correct data which has been divided and recorded in a plurality of blocks on a recording medium, each of said plurality of blocks being separated from adjacent blocks at identifiably coded dividing portions, characterised in that said apparatus comprises; first adding means for adding a specified data pattern to each block at said dividing portion to enable a modulation of the block; modulating means for modulating each block and its specified data pattern to provide a respective coded signal portion separated from adjacent coded signal portions at coded dividing portions; second adding means for adding a specified coded pattern to said coded signal portion at said coded dividing portion so as to form a coded signal for recording on said recording medium; demodulating means for demodulating said coded signal so as to reproduce said correct data in said plurality of blocks from said recording medium, wherein said second adding means is arranged so that a combined coded pattern including a first coded pattern and a second coded pattern is obtained at each of said coded dividing portions, said first coded pattern corresponding to a pattern obtained by modulating said specified data pattern, said second pattern being said specified coded pattern, and wherein said combined coded pattern is a resynchronization pattern which is used to detect said dividing portions of said plurality of blocks. An apparatus according to claim 11, wherein said specified data pattern is configured to enable a data signal obtained by adding said specified data pattern to a block to be modulated. An apparatus according to claim 12, wherein said data signal satisfies a 2-7 conversion rule. An apparatus according to any of claims 11 to 13, wherein said first adding means is arranged to add said specified data pattern to the end of each block. An apparatus according to any of claims 11 to 14, wherein said specified data pattern is "011". An apparatus according to any of claims 11 to 15, wherein said modulating means is arranged to modulate each block and its specified data pattern according to the following table: Data Bits Code Bits 10 0100 010 100100 0010 00100100 11 1000 011 001000 0011 00001000 000 000100. An apparatus according to any of claims 11 to 16, wherein said specified coded pattern is configured to enable detection of said dividing portions of said plurality of blocks for resynchronization. An apparatus according to any of claims 11 to 17, wherein said second adding means is arranged to add said specified coded pattern to the end of each coded signal portion. An apparatus according to any of claims 11 to 18, wherein said specified coded pattern is "0000100100". An apparatus according to any of claims 11 to 19, wherein said combined coded pattern is one which cannot be produced by 2-7 conversion.

Inventors: DEGUCHI TOSHIHISA, FUJIWARA TSUNEO, KOBAYASHI SHOZOU, MAEDA SHIGEMI, TSUJI KENTAROH, YAMAGUCHI TAKESHI, DEGUCHI, TOSHIHISA, FUJIWARA., TSUNEO, KOBAYASHI, SHOZOU, MAEDA, SHIGEMI, TSUJI, KENTAROH, YAMAGUCHI, TAKESHI, Deguchi, Toshihisa, Daiya-Heights Gakuenmae C-722
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1987
Main classification: G11B20
IPC codes: G11B20, G11B27