Calibrated automatic test system

Abstract: A calibrated automatic test system includes a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under test. Each I/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places cali­ brated function codes which are then supplied to the pin electronics circuits.

Description: The following invention relates to an automatic test system for testing electronic devices and a method for calibrating the system. The designing of a test system for very large scale integration (VLSI) devices presents special engineering problems. To test VLSI devices what is needed are testers with as many as 256 I/O channels, 50 MHz clock and data rates, subnano-second timing resolution and large test pattern memories associated with each of the 256 I/O channels. Currently test systems that satisfy these criteria are extremely expensive. This is due to the fact that the best architecture for such testers requires redundant sets of tester electronics, one for each output pin of the tester. This is referred to as tester-per-pin architecture. This duplication of circuitry is desirable because with it the problems of multiplexing and cabling, that would otherwise arise with shared test circuitry, are avoided and the test circuits can be located physically adjacent each input/output pin in close proximity with the device under test. Moreover, complex test patterns may be generated since each of the input/output pin circuits is independent and has independent timing generation and output pattern acquisition. The problem with tester-per-pin architecture is that the redundancy of the pin circuits makes the test instrument very expensive. The pin electronics circuits must include precision components which ensure accuracy of all relevant electrical parameters. Duplicating these types of circuits results in a considerable increase in the overall cost of the system. Publication No. EP-A-0 165 865 discloses a method and apparatus for testing integrated circuits. In accordance with the disclosure of that publication, a control processor provides test vectors to multiple pin electronic circuits. Each pin electronic circuit responds to a test vector by selecting either a high voltage, provided by a first sample and hold, or a low voltage, provided by a second sample and hold, and applies this voltage to its pin through a driver and an output switch. A comparator is connected to the pin and in a calibration operation compares the voltage measured at the pin with a standard high voltage and a standard low voltage. The result of the comparison is used to adjust the voltages stored by the sample and holds. In this manner, the voltage stored in each sample and hold is compensated for any shift between the output of the sample and hold and the pin. J. Healy and G. Ure, A Method of Reducing ATE System Error Components and Guaranteeing Sub-Nanosecond Measurement Accuracies, IEEE-International Test Conference 1985 Proceedings, 19-21 November 1985, pages 191-202, discloses an automatic test system in which independent timing generators are provided for each pin. The independent timing generators are separately adjustable. The signal delay in the path to each pin is measured by use of time domain reflectrometry techniques, and a calibration value is derived for each pin. The calibration values are added to the programmed timing value for each pulse edge during operation of the test system. R. Dunaway, Status of the Calibration Support of Navy ATE, International Automatic Testing Conference, Orlando, 19-21 October 1981, pages 450-454, discloses an automatic test system in which portable calibration equipment is employed to automate calibration. This document discloses that a calibration module may be attached to the test system in lieu of a unit under test to carry out calibration. It is an object of this invention to provide an automatic test system for electronic devices having the advantages of tester-per-pin architecture, including the requisite accuracy, while avoiding the cost usually associated with such architecture. It is a further object to provide a method of calibrating such an automatic test system. Starting out from a system known for example from EP-A-0 165 865, the automatic test system according to the invention is characterized by the features of claim 1 while the calibration method according to the invention is defined in claim 6. The calibrated automatic test system for testing electronic devices comprises a programmable test station which includes a test head having a plurality of input/output pins (I/O pins) for connection to a device under test. CMOS integrated output circuits are provided for each of the I/O pins for generating output signals needed to stimulate the device under test. An external calibration circuit or unit which is selectively connectable to the test head receives test output signals from the CMOS integrated electronic output circuits and derives from those test output signals calibrated signals which may be used to calibrate the CMOS IC's in each of the individual electronic output circuits. Although tester-per-pin architecture is utilized in the present system, it is less expensive because of the incorporation of monolithic CMOS integrated circuits for each of the pin electronics circuits. The use of CMOS IC's would ordinarily subject the tester to a host of inaccuracies due to the variations in circuit parameters that result from the manufacturing processes used to make the IC's. However, the external calibration unit solves this problem by measuring the test output signals generated by each of the electronic output circuits, stores those signals in a memory, and utilizes the signals in the memory to provide for calibration of the IC's. The test station or unit, which may be under the control of a host computer, generates digital test code signals, forming test functions which are provided to each of the electronic output circuits. The electronic output circuits are responsive to error correction memory circuits which provide calibrated test code signals to be substituted for the test code signals provided by the test station thereby producing calibrated test signals at the output of each electronic output circuit. The external calibration unit may be portable and thus may be used with several test stations, and may include an X-Y positioning apparatus for making selective connection with each I/O pin of the test head for calibrating each pin electronics circuit in turn. The foregoing and other objectives, features and advantages of the present invention will be more readily understood upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawings. In the drawings: FIG. 1 is a perspective drawing of an automatic test station under control of a host computer and including a test head for connection to a device under test. FIG. 2 is a perspective drawing of the test station of FIG. 1 with an external calibration unit positioned to make electrical contact with the test head. FIG. 2B is a block schematic diagram of the external calibration unit of FIG. 2. FIG. 3 is a block schematic diagram of one of the pin electronics circuits located in the test head of FIG. 1. FIG. 4 is a block schematic diagram of the driver block of FIG. 3. FIG. 5 is a block schematic diagram of one of the pulse placement circuit blocks of FIG. 4. FIG. 6 is a block schematic diagram of an error correction memory for use with the pin electronics circuit shown in FIG. 3. An automatic test unit 10 includes a test station 12 which includes programmable test circuitry under the control of a host computer (not shown) for generating digital test code signals (digital test function codes) over a connecting cable 14 to a test head 16. The test head 16 may be loaded with a device under test (not shown) such as a VLSI chip which may have as many as 256 input/output lines. Each I/O line is connected to the device under test by a pin (not shown) and each of the pins includes an electronic output circuit or electronic circuit 38 (refer to FIG. 3) to provide test output signals to the device under test in response to digital test function codes generated by the test station 12. In order to calibrate the electronic circuits 38 in the test head 16, the automatic test system includes an external calibration unit 18 which may include an X-Y positioning device 19 which may be positioned to connect to various pins of the test head 16. The positioning device may include a probe head 36 which may move in two dimensions as shown by the arrows in FIG. 2B. The external calibration unit 18 is shown in more detail in FIG. 2B, and comprises several modules including a time measurement circuit 20, pulse generator 22, programmable counter 24, volt meters and ammeters 26, precision resistances 28, and precision voltage sources 30. These are connectable to the X-Y positioning device 19, by way of coaxial cable 32. A series of relays 34 selectively connects the modules of the external calibration unit 18 to the coaxial cable 32 except a memory unit 31 which is internally connected to the other circuits. The external calibration unit 18, with its associated X-Y positioning device 19, may be portable and may be mounted in a cart or rack having wheels (not shown) so that it can be moved about from one test unit 10 to another. This provides for additional economy of the system because only one external calibration unit 18 may be needed for a plurality of test units 10. A block schematic diagram of the electronic circuit 38 for one of the I/O pins of test head 16 is shown in FIG. 3. The circuits represented by the block diagram of FIG. 3 may be contained on two monolithic CMOS integrated circuit chips. These must be small-geometry CMOS chips to fit within test head 16 adjacent each of the I/O pins, and, as a consequence, exhibit large variations in performance characteristics at the speeds at which test signals must be transmitted and acquired for VLSI testing. These speeds typically approach 50 MHz. Thus, while the electronic circuits 38 may be placed adjacent the pins of the test head 16, they must be calibrated if the system is to remain accurate. The CMOS electronic circuit 38 includes driver pulse generators 40 which provide pulses for a driver circuit 42. The driver circuit 42 provides timed output pulses which stimulate the device under test. Signals from the device under test are acquired by a dual comparator 44 and an active load circuit 46. The dual comparator 44 is controlled by comparator clock generators 48. The driver circuit 42, the dual comparator 44 and the active load circuit 46 are controlled by digital test function codes from incoming serial data line 50. Serial data line 50 is connected to the output of a correction memory circuit 76 as will be explained below. A pair of relays 52a and 52b connect either the electronic circuit 38 or a parametric measurement unit (not shown) to one of the input/output pins of test head 16. The parametric measurement unit is a DC measuring device which may be shared among a plurality of electronic circuits 38 and which may be used to measure various DC characteristics of a device under test, A more detailed schematic diagram of the driver circuit 42 is shown in FIG. 4. The driver pulse generators 40 include four output lines which are seen in FIG. 4 as input lines labelled 'driver high pulse," "driver low pulse," "driver off pulse," and "driver on pulse." These lines are connected to pulse placement circuits 54, 56, 58 and 60, respectively. Pulse placement circuits 54 and 56 provide inputs to flip flop 62, and pulse placement circuits 58 and 60 provide inputs to flip flop 64. The outputs of flip flops 62 and 64 are provided to AND gates 66 and 68. The output of AND gates 66 and 68 are connected to transmission gates 70 and 72 respectively, which gate either a driver high voltage rail 71 or a driver low voltage rail 73 through relay 52a. The driver circuit 42 may thus have three states: it may provide a logical high signal, a logical low signal or it may be turned off. For testing purposes, the timing of the leading edges of the driver circuits 42 in all of the electronic circuits 38 may be critical. For example, it may be desirable to time all of the leading edges of pulses produced by the driver circuits 42 so that they all occur within a certain number of nanoseconds relative to a reference determined by a master clock located in test station 12 or in the host computer. This process is known as deskewing the input drivers and makes it possible to generate test pulses that arrive simultaneously on all input pins of interest in the test head 16. In order to adjust the timing of the leading edges of pulses produced by the driver circuit 42, the pulse placement circuits 54, 56, 58 and 60 are arranged so as to provide variable delays which may be adjusted by an 8-bit digital signal. The circuit for implementing driver pulse timing adjustability is shown in FIG. 5. The pulse placement circuit shown in FIG. 5 includes a plurality of multiplexers 74a through 74h. Each one of the multiplexers 74a-74h is connected to one of the lines of an 8-bit shift register 75. The lines from shift register 75 are connected to the SET inputs of multiplexers 74a-74h and choose, depending upon the state of the line, that is, whether a logical high or a logical low, either input A or B. The B input on each of the multiplexers 74a-74h is generally configured to provide more delay to the signal input. For example, in multiplexers 74a, 74b and 74c, a capacitor connected in parallel with the B input provides additional delay. In multiplexers 74d-74h pluralities of buffer amplifiers provide increased delay for the B input as opposed to the A input. The digital code loaded into shift register 75 controls the choice at each of the multiplexers 74a-74h of the A or B input and thereby chooses the amount of delay through the pulse placement circuit 54. The "serial data in" line connected to the shift register 75 is from the output of an error correction circuit 76 which is shown in FIG. 6. The error correction circuit 76 such as the circuit shown in block diagram form in FIG. 6, includes an output for each of the electronic circuits such as circuit 38 shown in FIG. 3. Referring to FIG. 6, the error correction memory circuit 76 includes a random access memory (RAM) 77 which is configured, by way of example only, as a 32k x 8 random access memory. For test heads having 256 input/out pins, the memory 77 would be configured as a 32k x 256 RAM. Each data I/O line of RAM 77 is connected to a data output circuit 78. There will be as many data output circuits 78 as there are pins for the test head 16 and, consequently, there will be the same number of electronic circuits 38. Each data output circuit 78 includes a multiplexer 70 having its b input connected to the data I/O port of RAM 77 and its A input line connected to a serial data input line 80. The serial data line 80 is also connected to an 8-bit shift register 81 which has an output leading to a tristateable buffer amplifier 82. The tristateable buffer amplifier 82 is also connected to the SET input of multiplexer 79 and to a node between the data I/O outputs of RAM 77 and the B input of multiplexer 79. Connected to the address lines of RAM 77 are a 3-bit counter 83, an 8-bit shift/count register, and a 4-bit shift register 85. The 4-bit shift register 85 has an input which provides a serial function code, and the 8-bit shift/count register has a shift/count input line controlling the function of the register 84, that is, whether it functions as a shift register or as a counter. The purpose of the RAM 77 is to store calibrated test code signals i.e. corrected test function codes in address locations that may be accessed by nominal test function codes (nominal test code signals) generated by the test modules included at test station 12. The test function codes may instruct the electronic circuits 38 to perform various test functions such as, for example, generating a test pulse at a time relative to some standard. Because of the variations in performance of the CMOS integrated circuits which contain the electronic circuits 38, the actual timing of such a pulse called for by a specific test function code, may not occur at the desired time. The correction memory circuit 76 provides correct test function codes which may be substituted for the nominal test function codes generated from the test station 12 so that the performance of the electronic circuits 38 corresponds to the actual desired performance. In order to provide the corrected test function codes that are stored in RAM 77, the external calibration unit 18 is positioned over the test head 16 as shown in FIG. 2. The X-Y positioning unit 19 is connected to each I/O pin of the test head 16 in turn, and measurements are taken which record the actual performance of each of the electronic circuits 38 in response to test function codes generated from the test station 12. For example, the timing of the driver pulses from driver circuit 42 is controlled by the pulse placement circuit 54. This circuit is controlled in turn by an 8-bit shift register 75 which receives a test function code from test station 12. Since shift register 75 is an 8-bit register, there may be as many as 256 possible values for the timing of the leading edge of drive pulses for drive circuit 42. The host computer connected to each test station 12 may determine which test functions are to be implemented and analyzes the test data that is received, and may control the operation of the external calibration unit 18. Thus, under control of the host computer, the test station 12 initiates a test of the driver leading edge timing and proceeds to provide the electronic circuit 38 with each of the 256 possible values for the timing of the output of the driver circuit 42. When this occurs, the RAM 77 in the correction memory circuit 76 is turned off and the output of the circuits 78 comprises serial data from the serial data input line 80. The calibration unit 18 records the actual timing data resulting from the 256 test function codes in its memory 31. Next, the host computer determines a desired data value which may, for example, be the timing of a pulse relative to a reference standard. It searches the memory 31 for the data entry that most closely approximates the desired performance of the circuit. Once this data entry has been looked up in the memory 31, its test function code is determined and that code is transferred to a location in RAM 77 which has an address which may be accessed by the nominal test function codes produced by the test station 12. For example, the memory 31 may store all 256 possible values for the timing of the leading edge of a driver pulse relative to a reference. If the driver circuits 42 were to be deskewed so that all driver circuits 42 timed the leading edges of their output pulses to occur 10 nanoseconds after a predetermined clock or reference, the host computer would perform a table lookup in the memory 31 for a data value that represented most closely the desired 10 nanosecond timing relationship. The test function code that produced this data value would then be stored in the(error correction)RAM 77. This data is written into the RAM 77 by turning off the data I/O lines and loading the data into 8-bit shift register 81. The data is placed in the memory on one of the data I/O lines through tristateable buffer 82. At the same time, the "memory write" line of RAM 77 is enabled, and the "use corrected data" line on input OE is turned off which inhibits the output of the data I/O lines. The test function code that produced the 10 nanosecond timing is placed in an address location in the RAM 77 where it will be accessed by the test function code from test station 12 that nominally produces the 10 nanosecond timing relationship. When this has been done for all test functions of interest, RAM 77 will contain calibrated test function codes which may be substituted for incoming nominal test function codes. Once the system has been calibrated, the external calibration unit 18 may be removed from the test head 16. A test function code entering on serial data line 80 will enter 8-bit shift/count register 84. At the same time, a serial function code determines which one of 16 possible test function types is being called up out of memory. The output of the shift/count register 84 will be an address location which contains the calibrated test function code which, in the present example, will cause the electronic circuits 38 to provide the desired pulse timing for the driver circuits 42. The corrected or calibrated test function code will therefore be substituted for the nominal test function code entering on serial data line 80. The corrected test function code will be serially loaded into multipexer 79 one bit at a time by 3-bit counter 83. At the same time, the data I/O lines of RAM 77 are turned on by the "use corrected data" input, which also turns off tristateable buffers 82 and selects line B of multiplexers 79. The substituted 8-bit test function code on the serial data output line forms the serial data input to the 8-bit shift register 75 (refer to FIG. 5) which, as explained above, sets the timing for the pulses of driver circuit 42 in each of the electronic circuits 38 (refer to FIG. 3). The invention has thus been explained by reference to an example in the pin electronic circuits 38 involving the timing of the leading edge of output pulses from driver circuits 42. It should be understood, however, that the other circuits in the electronic circuits 38, such as the dual comparators 44 and the active loads 46, also require calibration and thus have inputs from the serial data line 50 from the correction memory circuit 76 shown in FIG. 6. For example, there are offset and linearity errors that are introduced by digital to analog (DAC) circuits in dual comparator 44. The voltage produced by the DACs also depends upon digital test function codes generated in the test station 12. Similarly, the active load circuits 46 are used to sink or source current to a device under test and depend upon other DAC voltages in their respective circuits which in turn depend upon digital codes at the input of the DACs. The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.

Claims: An automatic test system for testing an electronic device comprising: a) a programmable test station (12) for generating digital test code signals representing test functions, and including: a test head (16) having a plurality of output pins for connection to the electronic device under test, b) a plurality of electronic output circuits (38) each of which is associated with one of the output pins and provides test output signals to the device under test in response to the digital test code signals, c) calibration means (18) for measuring, in a calibration mode, test output signals provided to each of the output pins in response to the digital test code signals by the electronic output circuit (38) associated with the output pin, d) correction memory means (76), in the calibration mode, being responsive to the calibration means (18) for determining and storing in a correction memory (77) calibration signals providing predetermined performance characteristics of each of the electronic output circuits (38), the electronic output circuits (38), in a test mode, being responsive to the calibration signals stored in the correction memory (77) to provide the test output signals in accordance with said predetermined performance characteristics, characterized in that the output circuits (38) are CMOS integrated circuits and the calibration means (18) are external to the test head (16) and are selectively connectable to each of the output pins, in that, in the calibration mode, the calibration means (18) record actual performance characteristics of each electronic output circuit (38) in response to the digital test code signals generated by the programmable test station (12) and the correction memory means (76) determine from the actual performance characteristics and store in the correction memory (77) calibration signals in the form of calibrated digital test code signals which cause the electronic output circuits (38) to provide the test output signals in accordance with the predetermined performance characteristics and in that, in the test mode, the correction memory means (76) selectively substitute calibrated digital test code signals for nominal test code signals generated by the test station (12) when testing the device under test. A system according to claim 1, characterized in that the calibration means (18) comprise a memory (31) and means (20 - 30) for measuring and storing in the memory (31) values of a parameter of the test output signals provided by each electronic output circuit (38) in response to digital test code signals generated by the test station (12). A system according to claim 2, characterized by computer means for searching the memory (31) of the calibration means (18) for the value of the parameter being closest to a desired value of the parameter and for determining the digital test code signal providing the closest value to form the calibrated digital test code signal and for loading the calibrated digital test code signal in the correction memory (77) at a memory location having an address to be accessed, in the test mode, by the nominal digital test code signal generated by the test station (12). A system according to claim 3, characterized in that the correction memory means (76) comprise multiplexing means (78) for permitting selection between providing to the electronic output circuits (38) calibrated digital test code signals from the correction memory (77) or digital test code signals generated by the test station (12). A system according to any one of claims 1 to 4, characterized in that the calibration means (18) include X-Y positioning means (19) for selectively connecting the calibration means (18) to selected ones of the output pins. A method of calibrating an automatic test system for testing an electronic device wherein the test system comprises: a programmable test station (12) for generating digital test code signals representing test functions and including a test head (16) having a plurality of output pins for connecting to the electronic device under test and a plurality of electronic output circuits (38) each of which is associated with one of the output pins and provides test output signals to the device under test in response to the digital test code signals and a calibration circuit (18) for measuring test output signals provided to each output pin in response to the digital test code signals by the electronic output circuit (38) associated with the output pin, the method comprising the steps of: a) connecting the calibration circuit (18) to a selected one of the output pins, b) applying a plurality of digital test code signals to the electronic output circuit (38) associated with the selected output pin, c) measuring with the calibration circuit (18) the values of a parameter of the test output signals produced at the selected output pin in response to each of the digital test code signals applied in step b), d) determining a desired value of the parameter, e) looking up which value measured in step c) comes closest to the desired value and f) determining a calibration signal that produced the value coming closest to the desired value of the parameter when being applied to the electronic output circuit (38) associated with the selected output pin and g) using the calibration signal when testing the device under test, characterized in that for calibrating a programmable test station (12) having electronic output circuits (38) in the form of CMOS integrated circuits step a) comprises using a calibration circuit (18) being external of the test head (16) and having a memory (31), step c) comprises storing the measured values of the parameter in the memory (31), step e) comprises searching the contents of the memory (31) for the value coming closest to the desired value, step f) comprises determining the calibration signal in the form of a calibrated digital test code signal which, when applied to the electronic output circuit (38) of the selected output pin, produces the value of the parameter coming closest to the desired value, and in that step g) comprises substituting the calibrated digital test code signal for a nominal digital test code signal generated by the test station (12) when testing the device under test. A method according to claim 6, characterized by a step h) of loading the calibrated digital test code signals determined in step f) into a correction memory (77) at an address to be accessed by the nominal digital test code signal and the step g) comprising the step of applying the nominal digital test code signal to the correction memory (77) to access the calibrated digital test code signal and applying the calibrated digital test code signal read from the correction memory (77) to the electronic output circuit (38). A method according to claim 7, characterized by serially repeating steps a) to f) and h) for each output pin.

Inventors: MURRAY DONALD F, SULLIVAN STEVEN K, MURRAY, DONALD F., SULLIVAN, STEVEN K.
Applicants: CREDENCE SYSTEMS CORP, CREDENCE SYSTEMS CORPORATION
Application year: 1987
Main classification: G01R31
IPC codes: G01R35, G01R31