ARRANGEMENT FOR CONTROLLING MEMORY OPERATIONS IN A PIPELINE PROCESSOR

Abstract: An arrangement for controlling memory store operations in a memory of a computer system wherein virtual addresses are translated to real addresses includes a processor having a pipeline (16) for processing commands in multiple stages, the commands including a plurality of instructions including store instructions. When the processor processes a store instruction, the pipeline (16) is normally blocked until the associated virtual address is translated by a translation device to a real address. However, if a selected store operation is processed, a check is made to see if the associated virtual address has previously been translated, and if it has, the pipeline (16) is unblocked, thus enhancing the processing of store operations.

Description: ARRANGEMENT FOR CONTROLLING MEMORY OPERATIONS IN A PIPELINE PROCESSOR Technical Field This invention relates to computer systems of the kind including pipeline processing means having a plurality of pipeline stages and adapted to process commands each of which includes a plurality of instructions. Background Art Known pipeline processing systems have an advantage, as compared with processing devices without a pipeline facility, in that pipelining enables the execution of several instructions to be overlapped. However, problems may arise in achieving efficient pipeline operation with high speed processing. Disclosure of the Invention It is an object of the present invention to provide a computer system of the kind specified, which achieves high speed processing and efficient pipeline control. Therefore, according to the present invention, there is provided a computer system of the kind specified, characterized in that said instructions utilize virtual memory addresses, by pipeline control means adapted to control the operation of said pipeline processing means, by first decoding means adapted to generate a first control signal if said commands contain a predetermined instruction in a irst selected stage of said pipeline processing means, by translation control means adapted to receive virtual addresses of instructions in said pipeline processing means and to generate a second control signal if a virtual address of an instruction in a second selected stage of said pipeline processing means has previously translated to a real address, and by second decoding means adapted to generate a third control signal in response to store instructions in said first selected stage of pipeline processing means, whereby said pipeline control means is adapted to provide a blocking signal which blocks said pipeline processing means in response to said third control signal except when said first and second control signals are generated. A computer system according to the invention has the advantage that the time taken for the execution of store instructions is minimized. This is achieved since the time utilized for the address translation of virtual addresses is reduced, resulting from the pipeline not being blocked for selected store operations for which a virtual address has been previously translated. This resuits in an overall higher performance of the computer system. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which: Figs. 1A, IB, and 1C arranged as shown in Fig. 1, form a schematic diagram of the store control circuit of the present invention; Fig. 2 is a schematic diagram of a portion of the page boundary detect circuit of the store control circuit of Figs. lA r IB and 1C; Fig. 3 is a timing diagram of a store operation in a control circuit of an alternative system; Fig. 4 is a timing diagram of a store operation in the control circuit of the present invention; Fig. 5 is an illustration of the cycles of a " fetch and store operation of the pipeline of an alternative system; and Fig. 6 is an illustration of the cycles of a fetch and store operation of the pipeline of a system using the present invention. Best Mode for Carrying Out the Invention Figs. 1A, IB and 1C, arranged as shown in Fig. 1, form a schematic diagram of the store control circuit of the present invention. The circuit includes a central processing unit (CPU) 10, a memory assist register set (MARS) 12 shown in Fig. 1A, and a dynamic address translations circuit (DAT) 14 shown in Figs. IB and 1C. The CPU 10 includes a microprocessor such as the NCR/32-000 central processing chip having a three stage pipeline represented by block 16. In the execution of various computer commands made up of a number of microinstructions, it is necessary to store data in the computer's main memory in a process well understood by those skilled in the art. In a virtual system, the virtual address of data to be stored in the memory must be translated to a real address before the data is actually stored. During this translation, the pipeline 16 must be blocked to give sufficient time to the translation hardware to finish its task. In the present invention, the disclosed circuit determines if the virtual address of data to be stored by certain commands at a later stage in the pipeline 16 has previously been translated. This predetermination is made before a store instruction of the desired commands is actually issued to the memory, such that when a store instruction is issued, the disclosed circuit already knows if a translation has occurred. If the translation has previously occurred, the pipeline is not blocked. At this point, it is appropriate to distinguish between commands and instructions, as used herein. Commands, as used herein, are commands in a programming language which are each composed of a series of instructions. In this instance, the computer is executing NCR NEAT commands, each of which is broken down into a series of instructions. There are certain NEAT commands, identified herein as FAKESTORE commands, for which one cycle stores of data to memory are desired to enhance the operation of the computer. These NEAT commands are: Add Binary, Subtract Binary, Move Effective B-Address, Move B Right to Left, Move A Left to Right, and Move A Right to Left. Each of these FAKESTORE commands contain a special STORE-NO CHECK instruction having function bits 1011 which can be detected to initiate one cycle stores if the associated virtual address has been previously translated. In addition, the pipeline 16 remains unblocked for all store instructions in the NEAT command following the STORE-NO CHECK instruction until an interrupt occurs, a page boundary is about to be crossed, or the FAKESTORE command is terminated. The CPU 10 includes an instruction decode circuit 18 which decodes the NEAT command being issued to detect a FAKESTORE command and the function bits of the associated instructions to detect a STORE-NO CHECK instruction. The CPU 10 transmits all command instructions over a bus 20 to a register pair 22 in the MARS 12, in the usual way. An address register 24 also contains the virtual address at which data is to be stored in the computer's main memory (not shown). The virtual address is transmitted by the CPU 10 from the address register 24 to the register pair 22 over a bus 26. The MARS 12 consists of paired registers in a register storage unit (not shown) for use by the CPU 10 in memory operations, as is well understood. The function bits of the instruction on bus 20 are passed to a store decoder circuit 28 over bus extension 30 for decoding. An output of the store decoder 28 is connected to one input of an AND gate 32 and is enabled high when any store in any command is detected. Thus, the pipeline 16 is blocked in the normal way for all store instructions except those in the FAKESTORE commands, as will be explained. When the instruction decode circuit 18 of the CPU 10 detects a STORE-NO CHECK instruction in a FAKESTORE command, an output connected to conductor 34 issues a high FAKESTORE signal. An inverter 36 has its input connected to a conductor 38, which is connected to the FAKESTORE conductor 34, and has its output connected to one input of the AND gate 32. Other inputs of the AND gate 32 receive a DAT receive store (DATRCVS/) signal over a conductor 78, and a one cycle store (ONECYCLESTORE/) signal over a conductor 88, to be discussed. It will be understood that when the FAKESTORE signal is inverted from a high to a low by inverter 36, the output of the AND gate 32 will go low, unblocking the pipeline 16 by a low PIPELINE BLOCK signal on a conductor 21 connected between the output of the .AND gate 32 to the pipeline 16 of the CP.U 10. As previously mentioned, store instructions from commands other than FAKESTORE commands cause the output of the store decoder circuit 28 to go high, blocking the pipeline 16 in the normal manner. Referring to Fig. IB, the FAKESTORE conductor 34 is connected to a logic buffer device 64, whose output is wire ORed, with the output of an AND gate 54, to a conductor 59. Referring to Fig. 1C, the conductor 59 is connected to the D terminal of a D- type flip-flop 58. The non-inverted output of the flip-flop 58 is connected to a DFAKESTORE conductor 60, which is in turn is connected to a conductor 62 for feeding back the DFAKESTORE signal to an input of the AND gate 54 of Fig. IB. Thus, a high on the conductor 59 will set the non-inverted output of the flip-flop 58 high, which will cause the output of the AND gate 54 to go high, assuming its other inputs are also high. A bus 40 is connected from the register 22 of the MARS 12 to the inputs of a content addressable memory (CAM) 42 in the DAT 14. At this point, it must be remembered that the virtual address being presented from the MARS 12 to the CAM 42 over bus 40, is the virtual address which was issued earlier from the pipeline 16. Thus, when the FAKESTORE signal goes high, the previous virtual address is being checked by the CAM 42. The CAM 42 has a DATMISS output connected to a conductor 44 which is normally low and goes high when the virtual address from bus 40 does not match data in the CAM 42, and a DATHIT output connected to a conductor 46 which is normally low and goes high when the virtual address from bus 40 matches data in the CAM 42. A function bit decoder 72 is included which decodes the instruction function bits for all commands on the bus 40 from the MARS 12. The decoder 72 has a STORE output connected to conductor 74 which is normally low and which goes high when a store instruction is detected, and a STORE-NO CHECK output connected to conductor 75 which is normally low and which goes h gh when a STORE-NO CHECK instruction is detected. The STORE-NO CHECK line 75 is connected to the respective inputs of NAND gates 48 and 52. The other input of NAND gate 48 is connected to the DATMISS conductor 44, and the other input of NAND gate 52 is connected to the DATHIT conductor 46. Outputs of the NAND gates 48 and 52 are connected to inputs of AND gate 54 by conductors 55 and 56, respectively. It will thus be understood that the flip-flop 58 of Fig. 1C will be set when a high FAKESTORE signal is issued, and the flip-flop 58 will remain set until the function bit decoder 72 detects a STORE-NO CHECK instruction before either a DATHIT or a DATMISS is issued by the CAM 42. The NAND gates 48 and 52 are used to achieve the correct timing. The output of one of the NAND gates 48 or 52 will not go low until after either one of the DATHIT or the DATMISS signal goes high while the STORE-NO CHECK signal is also high. When the output of either of the NAND gates 48 or 52 goes low, the output of the AND gate 54 will go low, resetting the flip-flop 58, which will remain reset until it is again set by a high FAKESTORE signal on conductor 34. It will be noted that the STORE-NO CHECK instruction in the CPU stages of the pipeline will set the flip-flop 58 as explained, and that the same STORE-NO CHECK instruction in the DAT stages of the pipeline will reset the flip-flop 58. Referring to Fig. 1C, the inverted output of flip-flop 58 labeled DFAKESTORE/, is connected via a conductor 66 to the respective inputs of AND gates 68 and 69. The other input of the AND gate 68 is connected to the DATMISS conductor 44, and its output is connected to an INTERRUPT conductor 70. Thus, when the flip-flop 58 is reset, a DATMISS causes a high INTERRUPT signal on conductor 70. A second input of the AND gate 69 is connected to the DATHIT conductor 46 via a conductor 80, and a third input is connected to the STORE conductor 74. The output of the AND gate 69 is connected to a MEMSTORE conductor 82. It will thus be seen that when the flip-flop 58 is reset and a DATHIT occurs while the STORE signal is high, that a high MEMSTORE signal will be placed on the MEMSTORE conductor 82. The use of INTERRUPT and MEMSTORE signals in the control of computer memories are well understood, and will not be discussed further. The DFAKESTORE signal on the conductor 62 from the non-inverted output of the flip-flop 58 is connected to one input of an AND gate 84. A second input is connected to the STORE conductor 74, and a third input is connected to the DATHIT conductor 46. The output of the AND gate 84 is connected to the set input S of a set-reset flip-flop 86. The inverted output of the flip-flop 86 is connected to the ONECYCLESTORE/ signal conductor 88, which is connected to one input of the AND gate 32 of Fig. 1A. It will thus be understood that the flip-flop 86 is set when the flip-flop 58 is set and a DATHIT has occurred as the result of a STORE. When the flip-flop 86 is set, the ONECYCLESTORE/ signal on conductor 88 goes low, thus making the output of the AND gate 32 low and unblocking the pipeline 16. An inverter 76 has its input connected to the DATHIT conductor 46, and its output provides the DATRCVS/ signal over conductor 78 to the AND gate 32. Thus, the DATRCVS/ signal will unblock the pipeline for all DATHIT's, but the ONECYCLESTORE/ signal will hold the pipeline unblocked only if the flip-flop 86 is set by a FAKESTORE command, as explained. The reset input R of the flip-flop 86 is connected by a line 90 to the output of an OR gate 92 whose inputs are connected to a TOT1 signal conductor 93, an INTERRUPT signal conductor 70A and a PAGE BOUNDARY signal conductor 94. The TOT1 signal on conductor 93 is a status bit which is used to reset the flip-flop 86 at the beginning of each NEAT command. Thus, when the CPU 10 starts processing a new command, the TOT1 signal is enabled such that the flip-flop 86 is reset. The flip-flop 86 is also reset upon the receipt of an INTERRUPT signal over line 70A, which is the same INTERRUPT signal outputted by the AND gate 68 over line 70. Also, the flip-flop 86 is reset whenever a page boundary is about to be passed as indicated by a PAGE BOUNDARY signal transmitted over line 94, as will be explained. A virtual address register 95 of Fig. IB is connected to bus 96, which is in turn connected to bus 40 from the MARS 12 for receiving a virtual address. The virtual address register 95 receives virtual address bits 3 through 24 for transmission to a translation circuit and storage in a cache, as appropriate. The translation of a virtual address and its storage in a cache is well understood in the art, and does not form a part of this invention, and will not be explained further. The page boundary protection circuit shown in Figs. IB, 1C and Fig. 2 will now be explained. Virtual address register bits VA9 through VA13 from the address register 24 of the CPU are transmitted over a bus (not shown) to the input of a NAND logic array 100 for comparison with page size bits PS1 through PS4. The page size bits PS1-PS4 are coded to indicate the page size of the virtual address pages into which the main memory (not shown) is divided. If the page size is 256 bytes, bits PS1-PS4 are turned on to their 4 one states. If the page size is 1,024 bytes, bits PS2-PS4 are turned on to their one states, and PS1 is turned off to its zero states. If the page size is 2,048 bytes, PS3 and PS4 are turned on to their one states, and PS1 and PS2 are turned off to their zero states. If the page size is 4,096 bytes, PS4 is turned on and PS1-PS3 are turned off. If the page size is 8,192 bytes, the bits PS1-PS4 are turned off to their zero states. A decode circuit 102 receives the function bits over bus 104 from the CPU 10 of Fig. la. The function bits are those which are transmitted over bus 20 from the CPU 10 to the MARS 12. The decode circuit 102 may be incorporated into the instruction decode circuit 18 of the CPU 10, and a direction bit transmitted to the DAT 14, or a separate decode circuit 102 may be incorporated in the DAT as shown. The decode circuit 102 decodes the NCR NEAT command Move A Left to Right (command D54) to determine the direction that the virtual address from the CPU 10 will be incremented during the execution of the command. The output on conductor 105 is high when the direction is from right to left, and is low when the direction is left to right. The output on conductor 106 is high when the direction is from left to right and low when the direction is from right to left. Thus, it will be understood that when the direction is left to right, the NAND gates of the NAND gate array 100 will be enabled by a low on conductor 105. The outputs of the NAND gate array 100 are wire ORed together at a node 108. It will thus be understood that if any one or more of the outputs of the NAND gates of the NAND gate array 100 go high, then the signal at 108 will also go high. The node 108 is connected to conductor 110 for providing a left to right compare signal (LRCMP/) signal to a one input of a comparator 112 of Fig. 1C. The inputs A1-A6 of the comparator 112 are connected to address bits 3-8 of the virtual address transmitted over address bus 114 f om the address bus 96 of Fig. IB. The STORE signal outputted by the function bit decoder 72 of Fig. IB is inputted to comparator input A7 over conductor 115 which is connected to conductor 74, a right to left compare (RLCMP/) signal, which is high when the LTOR signal on conductor 106 is high (as will be explained in connection with Fig. 2), is inputted to input A8 of the comparator 112, and the LRCMP/ signal on conductor 110 is inputted to input A9 of comparator 112. A low is inputted into input B9 of comparator 112, the LTOR signal on conductor 106 is inputted into input B8, a high is inputted into input B7, and the LTOR signal on conductor 106 is also inputted into each of the inputs Bl through B6 of comparator 112. It will be noted that virtual address bits VA9-VA13 presented to the NAND gate array 100 comes from the virtual address register 24 of the CPU 10 of Fig. 1A, while the virtual address bits 3-8 presented to inputs A1-A6 of the comparator 112 come from the virtual address from the MARS 12 of Fig. 1A. Thus, the NAND gate array 100 is comparing the page number of the virtual address from the CPU to determine if a page boundary has been crossed by the virtual address in the CPU stages of the pipeline, while the address bits compared by the comparator 112 are for the previous address in the MARS stages of the pipeline. Since the addresses are being incremented up when the operation is from left to right, the signal on the LTOR conductor 106, which is high when the operation is from left to right, are inputted into B1-B6 of the comparator 112. Thus the comparator 112 is able to determine if a page boundary is about to be crossed before the boundary is actually crossed. This will be indicated when all of the address ' bits 3-8 on bus 114 are high and the LRCMP/ signal from the NAND array 100 is low. As previously explained, an equal compare by comparator 112 will cause the PAGE BOUNDARY signal on conductor 94 to go high enabling the OR gate 92 and resetting the flip-flop 86. Turning to Fig. 2, a NAND gate array 120 is provided whose outputs are wire ORed at node 121. The negative virtual address bits VA9/-VA13/ are presented to the NAND gates of array 120 with the page size bits PS1-PS4 to perform a subtraction function to determine if the page size portion of the virtual address from the CPU 10 has decreased to below the present page. The LTOR signal is transmitted via conductor 123 from the conductor 106 of Fig. IB to one input of an OR gate 122. Thus when the LTOR signal on conductors 106 and 123 is low, the OR gate 122 is partially enabled. When all of the NAND gate outputs of the NAND gate array 120 goes low, the right to left compare signal (RLCMP/) also goes low to indicate that a page boundary in the right to left operation is about to be crossed. The LTOR signal on conductor 106 will be low when the direction is right to left such that the inputs B1-B6 of comparator 112 of Fig. 1C is also low. It will thus be understood that the circuit of Fig. 2 determines when a page boundary is about to change in the negative direction, and the comparator 112 looks to see if all of the bits of the address from the MARS 12 are all zeros indicating that a page boundary is about to change. As previously explained, the OR gate 92 (Fig. 1C) may be enabled to reset the flip-flop 86 whenever the NCR NEAT command is about to change, as indicated by a high TOT1 signal on conductor 93, or if a high INTERRUPT signal is received over conductor 70A, or if a page boundary changes indicated by a high PAGE BOUNDARY signal over conductor 94. Any of these conditions, alone or in combination, will cause the ONECYCLESTORE/ signal on conductor 88 to go high, causing the output on AND gate 32 (Fig. 1A) to go high thereby blocking the three stage pipeline 16. Fig. 3 is a timing diagram of a memory store operation wherein the store takes three cycles. The operation of Fig. 3 shows the operation of a memory store without the present invention. In this operation, a store command 130 causes a pipeline block at 131 until a DATRCVS/ signal is received at 132 to indicate that the STORE command has been received by the DAT, and that the virtual address also received in the DAT produces a DATHIT by the CAM. This operation takes three cycles as shown at 130, 133 and 134. Three cycle stores thus are performed for each memory store operation performed by the MARS. Fig. 4 is a timing diagram showing a STORE operation with the present invention. When a STORE-NO CHECK instruction for a FAKESTORE command is decoded by the instruction decode circuit 18 of the CPU 10 of Fig. 1A, a FAKESTORE signal is issued over conductor 34. This FAKESTORE signal is shown in Fig. 4 at 140. The CAM 42 of the DAT 14 of Fig. IB compares the virtual address on conductor 40 from the MARS 12 of Fig. 1A with its contents, resulting in a DATHIT on conductor 46 when the virtual address has been previously translated. A high STORE signal from the function bit decoder 72 of the DAT 14 (shown at 142 of Fig. 4) which is concurrent with a DATHIT signal on conductor 46 and a DFAKESTORE signal on conductor 62 (caused by the FAKESTORE signal on conductor 34 as previously explained) results in a ONECYCLESTORE/ signal at 143 of Fig. 4. The ONECYCLESTORE/ signal on conductor 88 of Fig. 1C inhibits the AND gate 32 of Fig. 1A thereby disabling the PIPELINE BLOCK signal on conductor 21. The PIPELINE BLOCK signal (see 144 of Fig. 4) stays low until the flip-flop 86 is "reset. The STORE, cycle is shown in phantom at 145 of Fig. 4. One cycle store operations are performed for as long as the ONECYCLESTORE/ signal remains low. As previously discussed, one cycle stores will continue throughout the present NCR NEAT command until a page boundary is crossed, a DATMISS occurs causing an interrupt, or until the NCR NEAT command is ' terminated. Fig. 5 is a timing diagram showing the cycles of the CPU, MARS, and DAT pipeline wherein a store operation takes NMCC cycles. In Fig. 5, a fetch instruction is issued by the CPU in cycle 1, the fetch instruction moves down the pipeline to the MARS in cycle 2 while the CPU performs a no-operation. The fetch instruction then moves to the DAT in cycle 3 while the CPU continues in a no-operation mode. In cycle 4, the CPU again performs a no-operation waiting for the instruction to be completed. In cycle 5, the CPU issues a store instruction. In cycle 6, the store instruction moves from the CPU to the MARS and the CPU stays blocked in the store mode. In cycle 7, the store instruction moves to the DAT and the CPU remains in the store mode. Now that the store has been completed, the CPU may issue a second fetch instruction which moves to the MARS in cycle 9, and the DAT in cycle 10. The three cycle store is then repeated in cycles 11, 12 and 13. The fetch and store sequence is then repeated in a loop until the T-count is expired indicating that the NEAT command has been completed, as is known in the art. Fig. 6 shows the fetch and store sequence using the present invention. In cycle 1 of Fig. 6, the CPU issues a fetch instruction. In cycle 2, the fetch instruction moves to the MARS, and the CPU performs a no-operation. In cycle 3, a FAKESTORE signal is issued by the instruction decoder 18 of the CPU 10, and the fetch instruction moves to the DAT. In cycle 4, the CPU performs a no-operation and a DFAKESTORE signal is issued by the flip-flop 58 of the DAT 14. If the address from the MARS to the CAM 42 of the DAT 14 produces a DATHIT signal, a ONECYCLESTORE/ signal is issued by the DAT 14 unblocking the pipeline such that the CPU 10 may complete the STORE in one cycle. The CPU 10 then issues a fetch instruction in cycle 6 and the ONECYCLESTORE/ signal remains enabled as previously discussed. It will be noted in Fig. 6 that three cycles are needed to complete a fetch operation but only one cycle is needed to complete a store operation, thus shortening the time needed to complete a fetch and store operation. The fetch and store loop continues until the T-count is expired, but the number of cycles to complete a fetch and store operation is shortened from six cycles to four. The execution of store operations in only a single cycle is particularly advantageous in improving the performance of move-type commands. This improvement can be from about twelve percent to about fifty percent, depending on the length of the field being moved. Since move-type commands are among the most frequently used commands, the optimization of these commands result in higher performance of the computer system.

Claims: CLAIMS : 1. A computer system including pipeline processing means (16) having a plurality of pipeline stages and adapted to process commands each of which includes a plurality of instructions, characterized in that said instructions utilize virtual memory addresses, by pipeline control means (32) adapted to control the operation of said pipeline processing means (16), by first decoding means (18) adapted to generate a first control signal if said commands contain a predetermined instruction (STORE-NO CHECK) in a first selected stage of said pipeline processing means (16), by translation control means (14) adapted to receive virtual addresses of instructions in said pipeline processing means (16) and to generate a second control signal (DATAHIT) if a virtual address of an instruction in a second selected stage of said pipeline processing means (16) has been previously translated to a real address, and by second decoding means (28) adapted to generate a third control signal in response to store instructions in said first selected stage of said pipeline processing means (16), whereby said pipeline control means (32) is adapted to provide a blocking signal which blocks said pipeline processing means (16) in response to said third control signal except when said first and second control signals are generated. 2. A computer system according to claim 1, characterized in that said translation control means (14) includes third decoding means (72) adapted to generate a fourth control signal in response to a store instruction in said second selected stage of said pipeline processing means (16), and first gating means (84) having a first input responsive to the provision of said first control signal, a second input adapted to receive said second control signal (DATAHIT) and a third input adapted to receive said fourth control signal. 3. A computer system according to claim 2, characterized in that said translation control means (14) includes first bistable means (58) adapted to be set in response to said first control signal and having a set output coupled to said first gating means (84), said first gating means having an output coupled to a second bistable means (86) adapted when in a first state to provide a fifth control signal (ONECYCLESTORE/) applied in operation to said pipeline control means (32). 4. A computer system according to claim 3, characterized in that said translation control means (14) includes memory controlling means (69) adapted to issue memory store control signals to the memory of said computer system, said memory controlling means (69) having a first input connected to a reset output of said first bistable means (58), a second input adapted to receive said second control signal (DATAHIT) and a third input adapted to receive said fourth control signal. 5. A computer system according to claim 4, characterized by page boundary indicating means (100, 112, 120) adapted to generate a page boundary signal when the virtual address of an instruction in said pipeline processing means (16) is about to cross a page boundary, said page boundary signal being adapted to cause said pipeline control means (32) to provide said blocking signal. 6. A computer system according to claim 5, characterized in that said translation control means (14) includes second gating means (92) having a first input (94) adapted to receive said page boundary signal, a second input (70A) adapted to receive an interrupt signal indicating that a virtual address of an instruction in said pipeline processing means (16) has not been previously translated to a real address, a third input (93) adapted to receive a signal that a command being executed by said pipeline processing means (16) has been terminated, and an output adapted to reset said second bistable means (86) to a second state.

Inventors: FLICEK CHARLES ALBERT, NGUYEN CHINH KIM, FLICEK, CHARLES, ALBERT, NGUYEN, CHINH, KIM
Applicants: NCR CO, NCR CORPORATION
Application year: 1987
Main classification: G06F9
IPC codes: G06F9, G06F12