APPARATUS FOR RECORDING AND REPRODUCING DIGITAL SIGNALS

Abstract: A digital signal recording and reproducing apparatus comprising a dynamic range compression/­ expansion apparatus. The compression/expansion apparatus (l6) receives a digital signal from, for example, an analog-to-digital converter (ll) and compresses the dynamic range of the digital signal and the so com­ pressed digital signal is supplied to a recording signal processing circuit (27) in the recording operation mode, while the apparatus receives a digital signal reproduction output from a recording/reproducing head (29, 30) and expands the dynamic range of the reproduced digital signal and the so expanded digital signal is supplied to, for example, a digital-to-analog converter (l2) in the reproducing operation mode. The compression/­ expansion apparatus includes a circuit for controlling the transient response of the apparatus, that is, for controlling the operation of the compression/expansion of the dynamic range of the digital signal during transient of the digital signal so that recording of the digital signal is performed at a high density with a high quality, without suffering breathing effect, overflow, etc.

Description: BACKGROUND OF THE INVENTION The present invention relates to an apparatus for recording and reproducing digital signals. In a home-use video signal magnetic recording/reproducing apparatus (hereafter abbreviated as VCR) represented by a cassette VTR which is generally used now, the video signal is subject to frequency modulation (FM) and recorded as slant recording tracks on magnetic tape by rotary heads. The audio signal is recorded as longitudinal tracks on an edge portion of the magnetic tape with high frequency bias by a fixed head. In recent years, the magnetic tape, head and signal recording technique have significantly advanced. Accordingly, the recording density has been largely increased. High density recording amounting to l7 times as compared with the VTR produced approximately l0 years ago. These high density recording techniques use reduced tape traveling speed and/or narrowed recording track width. The tape traveling speed is ll mm/s, for example. And the track width is 20 µm, for example. In the audio signal recording system using a fixed head, such a low tape traveling speed deteriorates the wow flutter characteristics, the signal-to-noise ratio at the reproduction, reproduction frequency characteristics, or the like, resulting in an insufficient sound quality. Thus, it is difficult to simultaneously satisfy needs of reduction in size, weight and cost and needs of improvement in picture quality and sound quality. In accordance with one method for making both needs compatible, the audio signal is also converted into an FM signal and recorded onto a video signal recording track by a rotary head. By using this method, the deterioration in the sound quality such as the wow flutter characteristics, signal-to-noise ratio at reproduction and reproduction frequency characteristics is eliminated, and the audio signal is reproduced with high sound quality. In this system, however, the audio signal and the video signal are recorded on an identical part of an identical track. This results in a problem that the after-recording of the audio signal (recording of the audio/video signal onto tape having the information already recorded thereon) is impossible in the editing operation or the like. Therefore, another method for making the above described needs compatible is described in JP-A-55-32296 (laid open on March 4, l980). In accordance with this method, the magnetic tape is wound around a rotary cylinder with an angle larger than in the prior art by ϑ, and one track is divided into a video signal recording track and an audio signal recording track (corresponding to the ϑ part). On this audio signal recording track, the time-compressed audio signal is recorded. As a result, it becomes possible to improve the sound quality compatible with the audio dubbing function. As the application of this method, a VCR having a mode for recording the video signal plus the audio signal and a mode for recording only the audio signal has been proposed in JP-A-58-222402 (laid open on December 24, l983). In this VCR, the video signal recording track is divided into a plurality of parts. The time-compressed audio signal is recorded onto each of the tracks thus divided. A similar technique is disclosed in U.S. Patent 4,558,378. In the home-use VCR, it is necessary to prolong the recordable time of the magnetic tape as far as possible and raise the tape usage efficiency. Therefore, it is desirable that the area for recording the above described time-compressed audio signal is small as far as possible. However, there is a limit in wavelength which can be recorded on the magnetic tape. In high density home-use recording VCRs now in use, the recordable wavelength is approximately 7 to 8 MHz at most. On the other hand, the requisites for attaining the high sound quality are as follows: Dynamic range: 80 dB or more Frequency band: l5 KHz or more Assuming that the pulse code modulation (PCM) is used to obtain this sound quality, even audio signal data needs: 32 (KHz) x 16 (bit) x 2 (ch) ≒ 1.024 Mbits/s Assuming that the time base is compressed to one-sixth (audio signal recording area corresponding to approximately 30° of tape wrap angle; and video signal recording area corresponding to 180° of tape wrap angle), the transmission rate of the audio data required for the recording operation is represented as: 1.024 (Mbit/s) x 6 = 6.144 (Mbits/s) Besides this, it is necessary to record the address data, the error correction data, and the like. The required transmission bit rate of the recording signal depends upon the modulation scheme and is 10 to 15 Mbits/s. In order to attain the above described improvement of sound quality, after-recording function of the audio signal and high density recording operation, it is indispensable to use a signal recording method facilitating reduction in transmission bit rate and assuring a high sound quality. The above described prior art does not pay attention to these points. The document GB-A-2 147 165 discloses a dynamic range controller for digital audio signals. It comprises a level detector for generating a control signal for the gain function of the main signal path in a feed forward manner. The detector compares the digital input signal with a stored signal. Upon a positive result the difference between the compared signals is multiplied by an attack response coefficient and the resultant signal is output from the detector. Upon a negative result the stored value is multiplied with a recovery coefficient and the resultant signal is output from the detector. The article "A Satellite Communications, Broadcast-Quality Amplitude Compander" published in the Journal of Audio Engineering, Vol.29, 1981, pp. 690-698 mentions that frequency response pre-emphasis and de-emphasis is used in its compander in order to make "pumping or breezing" side effects inaudible. Pre- and de-emphasis yield an immediate improvement in SNR and can also be measured. SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal recording/reproducing apparatus having an ability of high sound quality for recording, high density recording and after-recording of sound or picture. In accordance with one aspect of the present invention, the dynamic range of a digital signal (obtained by converting an input audio signal into a digital signal of, say, l6 bits by an analog-to-digital converter) is compressed (to, say, logarithmically half) by compression means, and thereby the information bits of the digital signal are compressed (into, say, l0 bits). The resultant signal undergoes processing such as time-base compression and modulation to be recorded on a recording medium such as a magnetic tape. During the reproduction operation, a digital signal having, say, l0 bits derived by applying the demodulation and time-base expansion to the reproduced signal is expanded (to a l6-bit digital signal, for example) to have the original dynamic range by expansion means having characteristics opposite to the above described dynamic range compression characteristics. The digital signal thus expanded is supplied to a digital-to-analog converter, for example, to produce a reproduced audio signal. It is thus possible to compress the number of bits of the recorded digital signal at least to half while maintaining a high sound quality dynamic range not less than 80 dB and a frequency band not narrower than l5 KHz. In accordance with another aspect of the present invention, each of the above described means for compressing the dynamic range of the digital signal and means for expanding it comprises a second emphasis circuit and a first emphasis circuit respectively including IIR (infinite impluse response) digital filters, a weighting circuit, an amplitude level detection circuit and a division/multiplication circuit. Therefore, the compression means and the expansion means may be provided individually so as to fulfil the operation described below. Alternately, a single compression/expansion means fulfilling the operation described below may be provided. The latter case will now be described. The operation in the compression mode (i.e., in the recording mode) is as follows. A digital signal composed of, say, l6 bits supplied from an input signal source including a DA converter, for example, is divided by the output signal (compression control signal) of the amplitude level detection circuit supplied with a signal which has been emphasized in its high frequency region by the second emphasis circuit, the first emphasis circuit and the weighting circuit. The dynamic range is thus logarithmically compressed to half. The compressed digital signal composed of, say, l0 bits is obtained as the compressed output signal from the first emphasis circuit. In the recording mode, the above described first emphasis circuit and weighting circuit have identical high-frequency emphasis characteristics. During the normal state (i.e., the operation period of the detection circuit), a compressed digital signal supplied with only characteristics of the second emphasis circuit is obtained. Under the state corresponding to the insensitive period of the detection circuit (i.e., the state where a small high-frequency signal is superimposed over a large-amplitude low-frequency signal), a compressed digital signal supplied with characteristics of both the second emphasis circuit and the first emphasis circuit is obtained. This reduces noises generated by the compression of the dynamic range for the reduction of the transmission bit rate. That is to say, the breathing phenomenon of noises caused by the changing noise level is reduced. Further, the transition response modifying signal is generated in the amplitude level detection circuit. The transition response modifying signal provides short attack time characteristics in order to prevent the overflow caused by the emphasis when a large signal level has been suddenly inputted instead of a small signal level. When a large signal level has been suddenly replaced by a small signal level, the transient response modifying signal provides recovery time characteristics after compression operation ceases for a predetermined time (i.e., hold time characteristics) in order to lessen the breathing phenomenon during the small signal period. The operation in the expansion mode (i.e., in the reproduction mode) will now be described. A reproduced digital signal (composed of l0 bits, for example) is de-emphasized in high frequency region by the second emphasis circuit and the first emphasis circuit. And the reproduced digital signal composed of l0 bits is emphasized in the high frequency region by the weighting circuit and amplitude-detected in the amplitude level detection circuit to produce an output signal (i.e., expansion control signal). The above described de-emphasized signal is multiplied with the expansion control signal to expand the dynamic range to the original range. The above described first emphasis circuit and second emphasis circuit are so controlled by a mode switching signal as to have high-frequency de-emphasis characteristics during the reproduction operation opposite to characteristics provided during the recording operation. Further, the detection circuit has attack time characteristics, hold time characteristics and recovery time characteristics similar to those of the recording operation. In the above described compression/expansion apparatus, the second emphasis circuit may be omitted as occasion demands. In this way, the transmission bit rate is reduced by the compression of the dynamic range while preventing the sound quality deterioration such as the breathing phenomenon or overflow caused by the compression of the dynamic range. Since the above described compression and expansion are carried out by using digital signal processing, non-uniformity in characteristics such as attack time characteristics, hold time characteristics, recovery time characteristics and emphasis characteristics due to non-uniformity in devices is prevented. Since it is not necessary to adjust the time constant, level, and the like and use peripheral components for the time constant or the like, a small-sized, light-weight digital signal recording/reproducing apparatus suitable for the implementation as IC may be provided. Several other aspects of the present invention yield effects as described below. (l) The transmission bit rate is reduced by compressing; the dynamic range of the digital signal. In addition, the sound quality deterioration such as the breathing phenomenon and overflow caused by the compression/expansion of the dynamic range is prevented by providing two circuit paths of the emphasis circuit and the weighting circuit and by establishing transient response characteristics including the attack time characteristics, hold time characteristics and recovery time characteristics. The low transmission bit rate and high sound quality can thus be attained. (2) Since the compression/expansion of the dynamic range is carried out by digital processing, advantages as described below are obtained. (i) There is no change in characteristics (such as emphasis, attack, hold, or recovery) from device to device. (ii) Since the time constant circuits of the above described emphasis circuit and the like determine the coefficient data, peripheral components and adjustment positions are not required. (iii) The IC implementation and high-density integration are easy. (3) The compression/expansion operation of the compression/expansion apparatus may be commonly used both for recording and reproduction operation by means of coefficient data switching. (4) As a synthetic result of the above described items (l) to (3), it is possible to construct a digital signal recording/reproducing system having a very small size and a light weight. The object of the present invention is obtained by a compressing apparatus and a compressing/expanding apparatus as defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. l is a block diagram for illustrating an embodiment of the present invention. Figs. 2 and 3 are flow charts used for explaining the operation of the apparatus of Fig. l. Figs. 4 and 5 are block diagrams for illustrating an example of a concrete configuration of a compression/expansion apparatus used in an embodiment shown in Fig. l. Figs. 6 and 7 are block diagrams for illustrating an example of a concrete configuration of a main part of the compression/expansion apparatus shown in Fig. 5. Figs. 8a to 8c are waveform diagrams used for explaining an example of the transition characteristics of Fig. l, 4 and 5. Fig. 9 is a block diagram for illustrating another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. l is a block diagram for illustrating an embodiment of a digital signal recording/reproducing apparatus. The left (L) and right (R) audio signals to be recorded are inputted to input terminals l and 2. The input audio signal is supplied to band restriction filters (LPF) 7 and 8 via PB contacts of switches 5 and 6, respectively. The input audio signal is band-limited to below, say, half of the sampling frequency (64 KHZ, for example) in order to prevent the aliasing noise. Output signals of the LPF 7 and LPF 8 are converted into a digital signal of L - R series comprising, say, l6 bits by a switch circuit 9 and an AD conversion circuit (ADC) ll. The output signal of the ADC ll is supplied to a digital LPF l4 via the PB contact of a switch l3. Only the frequency components belonging to the recordedd audio signal band (up to, say, l5 KHz) are thus passed and undergo the sampling frequency conversion (from 64 KHz to 32 KHz, for example). Thereafter, the dynamic range of the input audio signal is logarithmically compressed at a ratio of, say, 2/3 to l/2 in a compression/expansion apparatus l6. In this case, data compression from l6-bit data to l0-bit data is carried out. The output signal of the compression/expansion apparatus l6 is supplied to a l0 to 8 bit signal converter, where segment compression is applied to l0-bit data to produce 8-bit data. In a recorded signal processing circuit 27 including a PCM modulation circuit, the error correction data, address and the like are added to the 8-bit data and the resultant data undergoes the time-base compression and modulation. The resultant data is recorded onto magnetic tape 3l by a rotary head 29. A signal reproduced from the magnetic tape 3l by a rotary head 30 undergoes waveform equalizing processing and thereafter undergoes data reproduction in a data strobe circuit 32 to produce a reproduced digital signal. This reproduced digital signal undergoes demodulation, time-base expansion and the like in a reproduced signal processing circuit including a PCM demodulation circuit to produce 8-bit reproduced data. The output signal of the PCM demodulation circuit 28 undergoes data expansion from 8-bit data to l0-bit data in an 8 to l0 bit signal converter, and then expanded to the original dynamic range in the compression/expansion apparatus l6, resulting in l6-bit data. The first emphasis circuit 2l and the second emphasis circuit 22 are so controlled by a coefficient switching control signal as to have characteristics which are different from those obtained during the recorded signal processing. The output signal of the compression/expansion apparatus l6 is supplied to the digital LPF l4 having characteristics altered by the coefficient switching control signal. In the digital LPF l4, unnecessary band components are eliminated and the sampling frequency is converted (from 32 KHz to 64 KHz). The output signal of the digital LPF l4 is converted into an analog audio signal by a DA conversion circuit (DAC) l2. The analog audio signal is alternately assigned to two channel signals L and R by a switch circuit l0. After unnecessary components have been eliminated by SW 5, SW 6, LPF 7 and LPF 8, the reproduced audio signal is outputted from output terminals 3 and 4. The compression/expansion apparatus l6 comprises a second emphasis circuit 2l, a first emphasis circuit 22, a weighting circuit 23, an amplitude detecting circuit l9, a dividing circuit l8, a multiplying circuit l7, and switches 20 and 24. Each of the second emphasis circuit 2l, the first emphasis circuit 22, the weighting circuit 23 and the amplitude detecting circuit l9 may be constructed of an IIR (infinite impulse response) digital filter. Further, switching between contacts PB and PB in the switches 5, 6, l3, 20 and 24 may be effected by the use of a coefficient control signal supplied to input terminal l5 (which will be later described), though this is not particularly shown. The operation of the compression/expansion apparatus l6 will now be described by referring to flow charts shown in Figs. 2 and 3. At first, the recording operation mode will now be described by referring to Figs. l and 2. The output signal X of the digital LPF l4 (step c) is divided by the output signal (compression/expansion control signal) Y of the amplitude detecting circuit l9 in the dividing circuit l8 (step d). The output signal of the dividing circuit l8 is supplied to the second emphasis circuit 2l and the first emphasis circuit 22 via the PB contact of the switch 20 to be emphasized at its high frequency region (steps e and f). The signal thus emphasized is outputted to the l0 to 8 bit signal converter 25 as the compressed output. Further, a part of the output of the emphasis circuit 22 is supplied to a combination of the weighting circuit 23 and the detecting circuit l9, which contributes to the generation of the compression/expansion control signal for controlling the compression/expansion characteristics of the compression/expansion apparatus, via the PB contact of the switch 24. The weighting circuit 23 has characteristics identical with the emphasis circuit 22 during the compression operation. The output signal of the emphasis circuit 22 is further emphasized in its high frequency region by the circuit 23 (step g) and thereafter supplied to the amplitude detecting circuit l9. In the detecting circuit l9, the output of the weighting circuit 23 is at first converted into an absolute Value (step h). This output absolute value W is compared with the output signal Y of the detecting circuit l9 which is the compression/expansion signal of the compression/expansion apparatus l6. On the basis of the comparison result, the transient response modifying signal is issued. The detecting circuit l9 operates in one of the three operation modes, i.e., hold, recovery and attack modes which define the transient response characteristics of the compression/expansion apparatus l6 (steps j, k and m). The attack mode is assumed when the detection output signal Y does not exceed the output signal W of the absolute value conversion (W ≧ Y) at step j. In the attack mode, the attack coefficient (m of Fig. 4) is established as the detecting circuit constant of the detecting circuit l9. (For example, attack time 3 ms is set.) In the attack mode, the input signal level to the compression/expansion apparatus l6 is also detected, and the compression/expansion control signal Y is outputted (steps n and p). The hold mode and the recovery mode are assumed when W < Y at the step j. At first, the hold mode is assumed. (The detection operation is stopped and the detected output is held, namely, the previous value holding is effected.) After a predetermined time has elapsed (step m), the recovery mode is assumed. Accordingly, K represents the duration during which the previous value holding is effected and L represents the predetermined time. In the hold mode, the operation of the compression/expansion apparatus l6 is held for a predetermined time (l5 ms, for example) in order to lighten the breathing effect caused by the compression/expansion. At first, the calculation of the amplitude detecting circuit l9 is stopped during the hold period. During that hold period, the compression/expansion control signal derived before the stopping of calculation is held (steps s and t). The recovery mode is assumed after the hold period (lasting for l5 ms, for example) has been finished. During the recovery period (lasting for 40 ms, for example), the input signal level to the amplitude detecting circuit l9 is nullified. After the recovery coefficient (n of Fig. 4) has been set as the detecting circuit constant of the circuit l9, the output calculation result of the control signal of the detecting circuit l9 is outputted (steps o, q and r). Since the weighting circuit 23 has characteristics identical with the emphasis circuit 22 during the compression operation of the apparatus l6, only the characteristics of the emphasis circuit 2l is added during the normal state (i.e., during the operation period of the detecting circuit l9). During the transition state (i.e., during the insensitivity state of the detecting circuit l9), characteristics of both the emphasis circuit 2l and the emphasis circuit 22 are added. In this way, the breathing phenomenon is lessened or suppressed and the sound quality deterioration caused by the dynamic range compression/expansion is prevented. The reproducing operation mode will now be described by referring to Figs. l and 3. The output signal of the 8 to l0 bit signal converter 26 is supplied to the weighting circuit 23 and the second emphasis circuit 2l via the PB contacts of the switches 20 and 24 (steps h′ and a′). Here, the coefficients of the emphasis circuits 2l and 22 are switched on the basis of the coefficient control signal inputted from an input terminal l5 and have de-emphasis characteristics (high frequency de-emphasis characteristics). The output of the second emphasis circuit is inputted to the first emphasis circuit 22 (step b′). On the other hand, the output signal of the weighting circuit 23 is inputted to the amplitude detecting circuit l9 (steps j′ to t′). De-emphasis characteristics of the circuits 2l and 22 cancel (or form inverse characteristics to) the respective emphasis characteristics of the apparatus l6 during the compression operation. The output signal of the emphasis circuit 22 is supplied to the multiplying circuit l7. On the other hand, the output signal (compression/expansion control signal) of the detecting circuit l9 is also supplied to the multiplying circuit l7. Each multiplication result (step c′) is passed through the PB contact of the switch l3, digital LPF l4, DAC l2, switch circuit l0, switches 5 and 6, and LPFs 7 and 8 to be outputted from the output terminals 3 and 4 as the expanded output (steps d′, e′, f′ and g′). Since the operation of the amplitude detecting circuit l9 is the same as that of Fig. 2, it will not be described. In the embodiment heretofore described, l6-bit data are compressed to 8-bit data. That is to say, the audio data are compressed to half. Accordingly, the transmission bit rate of the recorded signal can be reduced at least to half. As for the sound quality, (l) sampling frequency: 32 KHz (2) the number of quantization bits: l6 bits yield (l) audio frequency band: l5 KHz or more (2) dynamic range: 90 dB or more. An example of a concrete circuit configuration of the compression/expansion apparatus l6 is shown in Fig. 4. In Fig. 4, blocks 2l and 22 surrounded by broken lines represent the second emphasis circuit and the first emphasis circuit, respectively. Block 23 represents the weighting circuit and block l9 represents the amplitude detector. The emphasis circuit 2l, the emphasis circuit 22 and the weighting circuit 23 are constructed of IIR digital filters having similar structures. And respective circuits are so controlled by changeover switches as to correspond to the R signal and L signal alternately sent out. The emphasis circuit 2l includes adders 42 and 43, multipliers 44, 49 and 50, latch circuits 46 and 47 for delay, switches 45 and 48 for switching L and R signals, coefficient memories 53, 54, l47 and l48, switches 5l, 52 and l45 for switching coefficients, and a negative converter 55. The emphasis circuit 22 includes adders 56 and 57, multipliers 58, 63 and 64, latch circuits 60 and 6l for delay, switches 59 and 62 for switching L and R signals, coefficient memories 67, 68, l49 and l50, switches 65, 66 and l46 for switching coefficients, and a negative converter 69. The weighting circuit 23 includes adders 70 and 7l, multipliers 72, 77 and 78, latch circuits 74 and 75 for delay, switches 73 and 76 for switching L and R signals, and coefficient memories 79, 80 and 8l. The amplitude detecting circuit l9 includes a detecting circuit portion 38, an absolute value converting circuit portion 82, a hold circuit portion 39, transition response modifying signal generating circuit portions 40 and 4l. The detecting circuit portion 38 includes adders 84 and 85, a multiplier 92, latch circuits 89 and 90 for delay, switches 86 and 9l for switching L and R signals, coefficient memories 94 and 95, a switch 93 for switching coefficients, and switches 83, 87 and 88 for attack, recovery and hold control. The detecting circuit portion 38 has a large time constant (a low cut-off frequency) as compared with that of the circuit portion 82. The hold circuit portion 39 includes latch circuits 99 and l00 for delay, switches 96 and l0l for switching L and R signals, and switches 97 and 98 for holding. The transition response modifying signal generating circuit portions 40 and 4l include comparator circuits l02 and l05, monostable multivibrators (MMV) l03, l04, l06 and l07, and switches l08 and l09 for switching L and R signals. The circuit portion 40 is provided for controlling the L signal, and the circuit portion 4l is provided for controlling the R signal. Examples of coefficients of the emphasis circuit 2l, the emphasis circuit 22, the weighting circuit 23 and the detecting portion 38 are shown in Table l. Coefficients of the emphasis circuit 2l and the amphasis circuit 22 are switched between the recording period ( PB ) and the reproducing period (PB). Since it is only necessary that the characteristics during the recording operation are opposite to those during the reproducing operation, only switches for switching coefficients and sign converters are required. In Fig. 4, respective blocks primarily consist of IIR digital filters having identical structures. In the integrated circuit (IC) implementation, therefore, an embodiment as shown in Fig. 5 may be adopted. In Fig. 5, an IIR operation unit l26 serves as IIR digital filters forming one basic structure of the compression/expansion apparatus l6. An example of the contifiguration of the IIR operation unit is shown in Fig. 6. In Fig. 5, a multiplying/dividing unit ll6 serves as the dividing circuit l8 and the multiplying circuit l7. Therefore, multiplexers l24 and l28, latch circuits ll5, ll7, l25 and l27, and changeover switches ll8 and ll9 are used. The multiplexers (MPX) l24 and l28 are controlled by selection signals Sl and S2 inputted from input terminals ll2 and ll3. Their control modes are shown in Table 2. The IIR operation unit l26 may include multipliers l55, l57 and l58, adders l53 and l54, a delay circuit l56, and coefficient circuits l59, l60 and l6l as shown in Fig. 6 to carry out the operation. Respective coefficients are controlled by a coefficient control circuit l62 on the basis of selection signals Sl and S2 inputted from the input terminals ll2 and ll3 and a coefficient control signal ( PB /PB) inputted from the input terminal as shown in Table 3. The delay circuit in the IIR operation unit l26 is so configured that respective data of signals R and L may be memorized and signals R and L may be alternately processed in the same way as Fig. 4. The delay circuit is also controlled by a hold control signal inputted from an input terminal l52. Numerals l5l and l63 denote an input terminal and an output terminal of the unit l26, respectively. An example of the concrete configuration of the multiplying/dividing unit ll6 illustrated in Fig. 5 is shown in Fig. 7. In Fig. 7, the multiplying/dividing unit ll6 includes logarithmic conversion circuits l35 and l39 for converting natural numbers into logarithms having bases 2, an adder l36, an inverse logarithmic conversion circuit l37 for converting logarithms into natural numbers, and a sign inverting circuit l38. On the basis of the PB/ PB control signal inputted from the input terminal l5, the above described sign inverting circuit l38 controls the adder l36 so that the output of the adder l36 may not be inverted during the PB operation and may be inverted during the PB operation. Assuming that X is inputted from an input terminal l33 and Y is inputted from an input terminal l40 during the PB operation, log₂X - log₂Y = log₂X/Y (l) is inputted to the inverse logarithmic converting circuit l37. From an output terminal l4l, log₂⁻¹ (log₂X/Y) = X/Y (2) is outputted, resulting in division. Here, log₂⁻¹ represents inverse logarithmic conversion. If X is inputted from the input terminal l33 and Y is inputted from the input terminal l40 during the PB operation, log₂X + log₂Y = log₂ X·Y (3) is inputted to the inverse logarithmic conversion circuit l37. From the output terminal l4l, therefore, log₂⁻¹ (log₂ X·Y) = X·Y (4) is outputted, resulting in multiplication. Accordingly, multiplication/division is carried out simply by inverting/noninverting the sign. By using the configuration shown in Fig. 5, the IC implementation with a small-sized circuit thus becomes possible. An example of transition response characteristics of the compression/expansion apparatus derived in the embodiment of the present invention which has heretofore been described by referring to Figs. 4 and 5 is shown in Figs. 8a to 8c. These transition response characteristics include attack time characteristics, hold time characteristics, and recovery time characteristics. In this way, the reduction of transmission bit rate using dynamic range compression/expansion is attained concurrently with the prevention of sound quality deterioration such as breathing or overflow caused by the dynamic range compression/expansion. In addition, the processing of the emphasis characteristics, attack time characteristics, hold time characteristics, recovery time characteristics and the like attendant upon the dynamic range compression/expansion can be easily carried out simply by changing the coefficient data. Not only the characteristics variation due to the non-uniformity in devices but also peripheral components such as the time constant circuit are eliminated, IC implementation being facilitated. Further, the compression means and expansion means in the recording/reproducing operation can be realized by a common circuit. In cooperation with the above described merit of IC implementation, therefore, a digital signal recording/reproducing system having an extremely small size and a light weight can be constructed. Another embodiment of the present invention will now be described by referring to Fig. 9. A block having the same function as Fig. l is denoted by the identical numeral. During the recording operation (i.e., during the PB period), the signals L and R inputted from the input terminals l and 2 are supplied to LPFs 7 and 8 via the PB contacts of switches 5 and 6, respectively. Each of the signals L and R is limited to a frequency band below, say, half of the sampling frequency (which is, say, 64 KHz) in order to prevent the aliasing noise. Output signals of the LPF 7 and LPF 8 are converted into a digital signal of L-R series comprising, say, l6 bits by a switch circuit 9 and an ADC ll. The output signal of the ADC ll is supplied to a digital LPF l4 via the PB contact of a switch l3. Only the audio band (up to, say, l5 KHz) is passed and the sampling frequency is converted from 64 KHz to 32 KHz in the digital LPF l4. The output signal of the digital LPF l4 is supplied to a compression/expansion apparatus l6′. Within the compression/expansion apparatus l6′, the input signal is supplied to the second emphasis circuit 2l′ via the PB contact of a switch l42 to be emphasized at its high frequency region and supplied to a dividing circuit l8. The dividing circuit l8 operates so as to compress the dynamic range of the input audio signal to, say, logarithmically half on the basis of the output signal level (compression/expansion control signal) of an amplitude detecting circuit l9. The output signal of the dividing circuit l8 is supplied to the first emphasis circuit 22 via the PB contact of a switch l43 to be further emphasized at its high frequency region. After the resultant signal has been converted into 8-bit data by a l0 to 8 bit conversion circuit 25, it is supplied to a rotary head 29 via a recorded signal processing circuit 27 including a PCM modulation circuit and recorded on a tape. A part of the output signal of the emphasis circuit 22 is supplied to a weighting circuit 23 to be emphasized at its high frequency region. The signal thus emphasized is supplied to the amplitude detecting circuit l9 for detecting the amplitude level. Thus the compression/expansion control signal to be inputted to the dividing circuit l8 for compressing the dynamic range is thus obtained. In the reproducing mode, operation which is completely inverse with respect to that of the recording mode is carried out and the dynamic range is expanded to, say, twice in the compression/expansion apparatus l6′. That is to say, the output signal (l0 bits) of the 8 to l0 bit signal converter is supplied to the first emphasis circuit 22 and the weighting circuit 23 via switches l43 and l44. Coefficients of the two emphasis circuits 2l′ and 22 are switched to exhibit the characteristics inverse to those of the recording operation ( PB operation) by the coefficient control signal supplied from an input terminal l5. The signal emphasized at its high frequency region in the weighting circuit 23 is supplied to the detecting circuit l9. Its amplitude level detected by the detecting circuit l9 to produce the detected output as the compression/expansion control signal. The output signal of the emphasis circuit 22 is multiplied with the compression/expansion control signal in a multiplying circuit l7. The dynamic range is thus expanded to its original level. The output of the multiplying circuit l7 is de-emphasized at its high frequency region in the second emphasis circuit 2l′ during the PB operation. The resultant signal is supplied to a DAC l2 via a switch l3 and a digital LPF l4 to be converted into an analog signal. The output signal of the DAC l2 is supplied to LPFs 7 and 8 for unnecessary signal components to be removed. The reproduced audio signal is thus outputted from output terminals 3 and 4. Further, switching between contacts PB and PB in the switches 5, 6, l3 and l42-l44 may be effected by the use of the coefficient control signal supplied to the input terminal l5, though this is not particularly shown. Operation of each block is similar to that of Figs. l, 4 and 5 and hence will not be further described. In this way, it is possible to reduce the recorded data transmission rate at least by half without causing the breathing or overflow, by compressing/expanding the dynamic range in the compression/expansion apparatus l6.

Claims: An apparatus for compressing the dynamic range of a digital signal with a controlled transient response for use in a signal recording and reproducing apparatus, comprising: (A) means for receiving an input digital signal; (B) means (18) for dividing said input digital signal (X) by a compression control signal (Y) for dynamic range-compression of said input digital signal (X); (C) emphasis means (22, 21) connected with said dividing means (18) for emphasizing the output of said dividing means (18) to provide an emphasized, dynamic range-compressed digital signal corresponding to said input digital signal, said emphasis means (22, 21) being connectable with said recording and reproducing apparatus (27-32) for recording said emphasized, dynamic range-compressed digital signal, and said emphasis means including first and second emphasis circuits (22, 21) and (D) means (19, 23) responsive to said emphasized, dynamic range-compressed digital signal from said emphasis means (22, 21) for generating said compression control signal (Y) to be supplied to said dividing means (18), said compression control signal generating means (19, 23) including: (a) a weighting circuit (23) connected between said first emphasis circuit (22) and a detector (38, 39) and generating an emphasis signal (W), said weighting circuit (23) and said first emphasis circuit (22) having identical characteristics; (c) said detector (38, 39) having a controllable response and detecting the amplitude of said emphasis signal (W) and delivering an amplitude detection signal as said compression control signal (Y) to said dividing means (18); and (c) a comparator (102, 105) for comparing said emphasis signal (W) from said wighting circuit (23) and said compression control signal (Y) for producing a detector control signal in accordance with a result of the comparison, said detector control signal being supplied to said detector (38, 39) to control the response of said detector (38, 39), said detector (38, 39) including means (87-95) responsive to said detector control signal from said comparator (102, 105) for establishing a hold time followed by a recovery time when said result of the comparison is such that said emphasis signal (W) is less than said amplitude detection signal (Y), during the transition time both the first emphasis circuit (22) and the second emphasis circuit (21) being operative, and during the normal state of said detector (38, 39) only the second emphasis circuit (21) being operative. Apparatus according to claim 1, characterized in that said first and second emphasizing circuits (22, 21) are connected in series such that said second emphasizing circuit (21) is connected between said dividing means (18) and said first emphasizing circuit (22). Apparatus according to claim 2, characterized in that said generator (82) includes a circuit for converting the output of said weighting circuit (23) to a corresponding absolute value. Apparatus according to claim 1, characterized in that said detector (38, 39) includes means (93, 94) responsive to said detector control signal from said comparator for establishing an attack time when said result of the comparison is such that said emphasized signal (W) from said generator is not less than said amplitude detection signal (Y). An apparatus for compressing/expanding the dynamic range of a digital signal with a controlled transient response for use in a signal recording/reproducing apparatus, comprising: (A) means (1, 2, 5-9, 11, 13, 14) for receiving a first input digital signal to be recorded by said recording/reproducing apparatus; (B) means for receiving a second input digital signal reproduced by said recording/reproducing apparatus; (C) means (18) for dividing said first input digital signal (X) by a compression/expansion control signal (Y) for dynamic range-compression of said first input digital signal; (D) emphasis means (22, 21) for emphasizing said compressed first input digital signal and de-emphasizing said second input digital signal, and including first and second emphasis circuits (22, 21) and being connectable with said dividing means (18), the emphasis characteristics of said emphasis means (22, 21) being controllable by a mode switching signal; (E) means (17) being connected with said emphasis means (22, 21) for multiplying said de-emphasized second input digital signal with a compression/expansion control signal (Y); (F) means (19, 23) for generating said compression/expansion control signal (Y) said compression/expansion control signal generating means (19, 23) including: (a) a weighting circuit (23) connected between said first emphasis circuit (22) and a detector (38, 39), said weighting circuit (23) receiving said compressed, emphasized first input digital signal or said second input digital signal for generating an emphasis signal (W); said weighting circuit (23) and said first emphasis circuit (22) having identical characteristics; (b) said detector (38, 39) having a controllable response detecting the amplitude of said emphasis signal (W) and delivering an amplitude detection signal as said compression/expansion control signal (Y) to one of said dividing means (18) and said multiplying means (17); and (c) a comparator (102, 105) for comparing said emphasis signal (W) from said weighting circuit (23) and said amplitude detection signal (Y) for producing a detector control signal in accordance with a result of the comparison, said detector control signal being supplied to said detector (38, 39) to control the response of said detector (38, 39), said detector (38, 39) including means (87-95) responsive to said detector control signal from said comparator for establishing a hold time followed by a recovery time when said result of the comparison is such that said emphasis signal (W) is less than said amplitude detection signal (Y), during this transition time both the first emphasis circuit (22) and the second transition circuit (21) being operative, and during the normal state of said detector (38, 39) only the second emphasis circuit (21) being operative. A compressing/expanding apparatus according to claim 5, characterized in that said first and second emphasizing circuits (22, 21) are connected in series such that said second emphasizing circuit (21) is connected between said dividing means (18) and said first emphasizing circuit (22). A compressing/expanding apparatus according to claim 6, characterized in that said generator (82) includes a circuit for converting the output of said weighting circuit (23) to a corresponding absolute value. A compressing/expanding apparatus according to claim 6, characterized in that said detector (38) includes means (93, 94) responsive to said detector control signal from said comparator for establishing the attack time when said result of the comparison is such that said emphasized signal (W) from said generator is not less than said amplitude detection signal (Y).

Inventors: ITOH, SHIGEYUKI, TSUNOKA, AKITOSHI, WATATANI, YOSHIZUMI
Applicants: HITACHI VIDEO ENGINEERING, INC., HITACHI, LTD.
Application year: 1987
Main classification: G11B20
IPC codes: G11B27, G11B20