NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING MEANS FOR DETECTING COMPLETION OF WRITING OPERATION

Abstract: A semiconductor memory includes memory transistors each having a floating gate is disclosed. This memory is equipped with a detection circuit for detecting a change in the threshold voltage of a selected memory transistor caused by the application of a programming voltage thereto and means responsive to an output of the detection circuit for stopping the application of the programming voltage to the selected memory transistor. A power consumption is thereby reduced in a data writing mode.

Description: The present invention relates to a semiconductor memory and more particularly to a nonvolatile semiconductor memory in which each memory cell includes a memory transistor having a floating gate. In a semiconductor memory of this type, data-writing is carried out by applying a high programming voltage between a control gate and a drain of a selected memory cell to inject carriers of holes or electrons to the floating gate thereof. A time period for completing carrier injection into the floating gate (called hereinafter "injection period") is determined by a device structure of the memory transistor such as a thickness of a gate insulating film, a transistor size, etc. The semiconductor memory according to prior art does not have means for detecting completion of the carrier injection. For this reason, a programming time period during which the high programming voltage is applied between the control gate and drain of the memory cell is designed to be considerably long as compared to the injection period in order to ensure the data writing. An unnecessary power is thereby consumed during the programming time period after the undetected completion of injection. Moreover, an address cannot be changed until the programming time period elapses, so that a large time is required in total to write data into all of the memory transistors. A semiconductor memory according to the preamble of claim 1 is disclosed in US-A-4 357 685. In this memory the floating gate of the memory transistor is progressively charged in a succession of steps separated by reading-operations to check on the conduction threshold of the cell; charging ends when that threshold reaches a predetermined storage level. Although programming time may be controlled by this means it has to be noted that additional steps for the reading operations are necessary. It is an object of the present invention to provide a semiconductor memory in which power consumption in a data writing period is reduced. Another object of the present invention is to provide a semiconductor memory in which the programming time period is shortened. These objects are achieved by a semiconductor memory as defined in claim 1; the dependent claims are related to further developments of the invention. When the memory transistor is injected at its floating gate with the carriers by the programming voltage, the threshold voltage thereof is changed and this change can be detected at a source thereof. The detection circuit monitors the source potential of the selected memory transistor to thereby produce the detection signal representative of the completion of carrier injection into the memory transistor. The programming voltage is thereby removed to reduce a power consumption. The detection signal can be supplied to a data programming equipment which is provided outside of the memory. The programming equipment responds to the detection signal to supply a new address and a new data to the memory. The programming time periods for each selected memory cell and for the memory in total are both thereby shortened. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and advantages and the features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a block diagram showing an embodiment of the present invention; Fig. 2 is a circuit diagram representing a source potential control circuit, a source potential detection circuit, a memory cell array and a column selection switch circuit shown in Fig. 1; Fig. 3 is a circuit diagram representing a control signal generator shown in Fig. 1; Fig. 4 is a cross-section view of a memory transistor which is employed in the embodiment; and Fig. 5 is a graph showing a drain current I D to a control gate-source voltage V GS of a programmed memory transistor and an erased memory transistor. DETAILED DESCRIPTION OF THE EMBODIMENT Referring to Fig. 1, a semiconductor memory according to an embodiment of the present invention is shown as an integrated circuit device 1. Three operation modes of data-writing, data-reading and data-erasing are controlled by the combination of logic levels of two control signal WE and OE supplied respectively to terminals 19 and 20 from an externally provided controller (not shown). In the data-writing operation mode, the control signals WE and OE take a high level and a low level, respectively. A control signal generator 10 responds to these levels of the signals WE and OE to generate a high level writing-signal WR, a low level reading-signal RE and a low level erasing-signal ER. A signal WR takes an inverted level of the writing-signal WR, i.e. the low level. A sense amplifier/output data buffer 13 is inactivated by the low-level reading-signal RE. On the other hand, an input buffer/writing-circuit 14 is activated by the high level signal WR to introduce data signal DI₁ to DI₈ to be written, which are supplied respectively to data input/output terminals 15-1 to 15-8. A booster 12 is activated by the high level writing-signal WR to boost a power voltage V cc of 5V applied to a first power supply terminal 16, so that a high voltage V pp of about 20V is generated. The power voltage V cc is supplied to the respective circuit blocks. A second power supply terminal 17 is grounded. The high voltage V pp is supplied to the input data buffer/writing-circuit which in turn supplies the V pp level or ground level to data lines D₁ to D₈ in accordance with logic levels of the data signals DI₁ to DI₈, respectively. Row address signals RA₁ to RA i and column address signals CA₁ to CA j are supplied to address terminals 2-1 to 2-i and 3-1 to 3-j, respectively. A row decoder 4 receives the row address signals RA₁ to RA i and the high level writing-signal WR and changes one of decoded signals X₁ to X n to the V pp level. Similarly, a column decoder 5 changes one of decoded signals Y₁ to Y m to the V pp level. A control-gate voltage generator 11 responds to the high level writing signal WR and generates a ground level (0V) control-gate voltage V CG which is in turn supplied via a column selection switch circuit to a memory cell array 7. Thus, selected memory cells within the cell array 7 are connected to the data lines D₁ to D₈ through the switch circuit 6 and written with the data DI₁ to DI₈. In a data-reading operation mode, the control signals WE and OE take the low level and the high level, respectively. The control signal generator 10 generates a high level reading-signal RE. The writing signal WE and erasing signal ER both take the low level. The sense amplifier/output data buffer 13 is thereby activated, while the input data buffer/writing-circuit 14 and the booster l2 are inactivated. Since the signals WR and ER are the low level, one of the decoded signals X₁ to X n and one of the decoded signals Y₁ to Y m take the V cc level. The circuit 11 supplies. a reading-voltage as a control-gate voltage V CG to the memory cell array 7 through the switch circuit 6. Thus, the data programmed in the selected memory cells appear on the data lines D₁ to D₈ and are then outputted to the data input/output terminals DO₁ to DO₈ via the sense amplifier/data output buffer as output data signals DO₁ to DO₈. In the data-erasing operation mode, both of the control signals WE and OE take the high level. The control signal generator 10 generates a high level erasing-signal ER, a low level writing-signal RE and a low level reading-signal RE. The sense amplifier/data output buffer 13 and the data input buffer/writing circuit 14 are both inactivated. The booster 12 generates the high voltage V pp in response to the high level erasing-signal ER. The control-gate voltage generator 11 generates an erasing voltage of the V pp level as the control-gate voltage. The row decoder 4 changes one of the decoded signals X₁ to X n to the V pp level and the column decode 5 changes one of the decoded signals Y₁ to Y m to the V pp level. Thus, the data of the selected memory cells are erased. The memory cell array 7 has a plurality of memory cells arranged in a matrix form, each of which includes a known memory transistor shown in Fig. 4. Formed in a silicon substrate 400 of one conductivity type (a P-type in this embodiment) are drain and source regions 401 and 402 of the opposite conductivity type (i.e., an N-type). A silicon oxide film 403 is formed in the surfaces of the substrate 400 and the drain and source regions 401 and 402. A floating gate electrode 404 is buried in the oxide film 403 and a portion thereof is very close to the drain region 401. A control gate electrode 405 is formed on the oxide film 403. In the data writing operation, the drain region 401 is applied with the V pp voltage and the control gate 405 is applied with the ground voltage generated from the control-gate voltage generator 11 (Fig. 1). As a result, a strong electric field occurs in a direction from the drain region 401 to the control gate 405. Electrons in the floating gate 404 are thereby released toward the substrate 400 through a very thin oxide film (so-called tunnel oxide film) between the drain region 401 and the floating gate 404, whereas holes are catched in the floating gate 404. Thus, the floating gate 404 is charged positively and a channel region is formed in the substrate 400 to connect the drain region 401 and the source region 402 with each other. Even if the control-gate voltage and the drain voltage are removed, the positive charging of the floating gate is maintained and the channel region does not disappear. That is, the memory transistor is changed from an enhancement type to a depletion type by the data programming. The characteristic of a drain current I 0 to a control gate-source voltage V GS of the programmed memory transistor is shown in Fig. 5 by a line 500. Since the programmed memory transistor is a depletion type, a drain current I D flows therethrough even when V GS = 0V. A threshold voltage of the programmed memory transistor is denoted by V TD and takes about -5V. In the data erasing mode, the V pp voltage is supplied to the control gate 405 from the control-gate voltage generator 11 and the ground voltage is supplied to the drain region 401. The strong electric field occurs from the control gate 405 to the drain region 401. Electrons are thereby injected through the tunnel oxide film to the floating gate 404. Thus, the channel region disappears and the erased memory transistor returns to an enhancement type transistor. The V DS - I D characteristic of the erased memory transistor is shown by a line 501 in Fig. 5. A threshold voltage of the erased memory transistor is denoted by V TE and takes about 5V. In the data reading operation, an intermediate voltage between the threshold voltages V TD and V TE , 1V for example, is generated by the control-gate voltage generator 11 and then supplied to the control gate 405 of the selected memory transistor. When the programmed memory transistor is selected, its drain current flows. The present invention utilizes the above-mentioned fact that the threshold voltage of the memory transistor is changed from the V TE value (+5V) to the V TD value (-5V) by the date programming. The source of the memory transistor is usually grounded directly. Since the source potential of the memory transistor is thus clamped at the ground level, it has been impossible to detect the threshold change. In the semiconductor memory circuit according to the present invention, the change in the threshold voltage appears as a change of the source potential of the memory transistor and the source potential change is monitored to detect the completion of the data programming. More specifically, the semiconductor memory 1 shown in Fig. 1 further comprises a source potential control circuit 8 and a source potential detection circuit 9 in accordance with the present invention. The source potential control circuit 8 connects the source of each memory transistor in the cell array 7 to the ground only the data-reading and data-erasing operation modes and disconnects it therefrom in the data-writing operation mode. The source potential detection circuit 9 monitors the change in the source potential of the memory cell and produces a high level writing-end signal PE when the source potential exceeds a predetermined level. This signal PE is supplied to the control signal generator 10 and further outputted to a terminal 18 to which an externally provided programming controller (not shown) is connected. Fig. 2 shows a detailed circuit diagram of the source potential control circuit 8 and the source potential detection circuit 9. The column selection switch 6 and the memory cell array 7 are also shown therein. All the transistors shown are of an N-channel type. When the row and column decoders 4 and 5 change respectively the decoded signals X₁ and Y₁ to a selection level in response to the row and column address signals RA₁ to RA i and CA₁ to CA j , transistors Q₈₁ to Q₈₈, Q₁₁₁ to Q₁₁₈ and Q₂₁ to Q₂₈ are turned ON. Accordingly, eight memory transistors Q M11 to Q M18 are selected and connected to the data lines D₁ to D₈, respectively. Since transistors Q₁ and Q₇ are turned ON by the decoded signals X₁ and Y₁, the voltage V CG generated by the control-gate voltage generator 11 is applied to the control gates of the selected memory transistors Q M11 to Q M18 . The voltage V CG is the ground level in the data-writing mode. The data lines D₁ to D₈ are supplied with the V pp level or the ground level in accordance with the input data signal DI₁ to DI₈. The sources of the memory transistors Q M11 to Q M18 are connected to nodes N₁ to N₈, respectively, in the source potential control circuit 8 which includes transistors Q₁₀₁ to Q₁₀₈ each connected between each of the nodes N₁ to N₈ and the power terminal V cc and transistors Q₁₁₁ to Q₁₁₈ each connected between each of the nodes N₁ to N₈ and the ground terminal. The writing-signal WR is supplied in common to gates of the transistors Q₁₀₁ to Q₁₀₈ and its inverted signal WR is supplied in common to gates of the transistors Q₁₁₁ to Q₁₁₈. In the data-writing mode, the signal WR takes the high level and the inverted signal WR takes the low level. The transistors Q₁₁₁ to Q₁₁₈ are thereby turned OFF to disconnect the nodes N₁ to N₈, that is, the sources of the memory transistors Q M , from the ground. The transistors Q₁₀₁ to Q₁₀₈ are turned ON, so that a potential that is lower than the high level (5V) of the signal WR by the threshold voltage (2V) of each of the transistors Q₁₀₁ to Q₁₀₈, i.e. 3V, appears at each of the nodes N₁ to N₈. Assuming that the V pp level is applied only to the first data line D₁, the floating gate of the memory transistor Q M11 releases electrons (or is injected with holes), so that a channel region is formed between the drain and source thereof. The memory transistor Q M11 is thus programmed and changed to a depletion type. A drain current flows through the memory transistor Q M11 to charge the node N₁. The potential at the node N₁ is thereby raised. Since the potential raising of the node N₁ makes the source-gate voltage of the transistor Q₁₀₁ smaller than the threshold voltage thereof, the transistor Q₁₀₁ is turned OFF to disconnect the node N₁ from the power terminal V cc as well. When the node N₁ is charged up to such a potential that is higher than the gate potential (0V) of the memory transistor Q M11 by the absolute value of the threshold voltage V TD (-5V) of the programmed memory transistor, the drain current stops to flow through the transistor Q M11 . That is, the source potential of the memory transistor Q M11 is raised to 5 V by the data writing. Thus, the threshold voltage change of the memory transistor caused by the data writing appears as the source potential change thereof. The nodes N₁ to N₈ are connected respectively to non-inverting input terminals of comparators 91 to 98 in the source potential detection circuit 9, inverting input terminals thereof being supplied with a reference voltage V REF from a reference voltage source 90. The reference voltage V REF is designed to be an intermediate level of a potential before data-writing and a potential after data-writing at each node N. In this embodiment, the reference voltage V REF is 4V. Accordingly, each of the comparators 91 to 98 produce a low level output before data-writing, and the comparator 91 produces a high level output after data-writing. The outputs of the comparators 91 to 98 are supplied to an OR gate 99. Thus, a high level signal PE is generated as a data-writing end signal from the source potential detection circuit 9 when the data-writing completes. Instead of the comparators 91 - 98, inverters having a threshold voltage of 4V may be used. The data-writing end signal PE is supplied to the control signal generator 10 which includes five inverters 101 to 104 and three NOR gates 105 to 107 as shown in Fig. 3. It will be understood from this drawing that only one of the writing-signal WE, the reading-signal RE and the erasing-signal ER takes the high level in accordance with the operation mode. The NOR gate 106 producing the writing-signal WR receives the data-writing end signal PE as its third input. Accordingly, the writing-signal WR is changed to the low level irrespective of the control signals WE and OE when the data-writing end signal PE is generated. As a result, the booster 12 and the input data buffer/writing circuit 14 are both inactivated and the row and column decoders 4 and 5 change the selection levels of the decoded signals X₁ and Y₁ to the V cc level. Thus, the programming high voltage is stopped to generate and an unnecessary power consumption is prevented. The data-writing end signal PE is further supplied through the terminal 18 to the programming controller (not shown). This controller thereby changes the row and column address signals RA₁ to RA i and CA₁ to CA j and supplies new input data signals DI₁ to DI₈ to the terminals 15-1 to 15-8, respectively. The data programming time period is thereby shortened. The present invention is not limited to the above embodiment, but may be applied to a nonvolatile semiconductor memory of a type in which the threshold voltage of a memory transistor is changed by data-programming. In a case where the externally provided programming controller supplies a V pp voltage to the semiconductor memory 1 shown in Fig. 1 in order to omit the booster 12, a switching circuit is provided between a V pp receiving terminal and each of the circuit blocks 4, 5, 11 and 14 and is controlled to be off-state by the data-writing end signal PE.

Claims: A semiconductor memory comprising a plurality of memory transistors (QM11-QM78) each having a control gate (405), a floating gate (404), a drain (401) and a source (402), means (4-6) responsive to a set of address signals (RA1-RAi, CA1-CAj) for selecting at least one of said memory transistors, means (11, 12, 14) for applying a programming voltage (Vpp, VcG) between said control gate and said drain of said at least one memory transistor to charge said floating gate thereof at a predetermined value, and means (10) responsive to a detection signal (PE) for preventing said programming voltage from being applied to said at least one memory transistor, characterized by further comprising means (9) coupled to said source of said at least one memory transistor for detecting a potential change at said source caused by a change in a threshold voltage of said at least one memory transistor and thereby producing said detection signal (PE). The memory as claimed in claim 1 , characterized by further comprising a source potential control circuit (8) including means (Q111-Q118) activated in a data reading mode for connecting said source of said at least one memory transistor to a reference terminal (7) to clamp said source to the reference potential at said reference terminal. The memory as claimed in claim 2 , characterized in that said means (Q111-Q118) included in said source potential control circuit (8) is deactivated in a data-writing mode to disconnect said source from said reference terminal. The memory as claimed in claim 3 , characterized in that said means included in said source potential control circuit (8) comprises a first transistor (Q111-Q118) connected between said reference terminal and said source and turned ON in said data-reading mode and OFF in said data-writing mode, and that said source potential control circuit (8) further includes a second transistor (Q101-Q108) connected between said source and a voltage terminal (Vcc) and turned OFF in said data-reading mode and ON in said data-writing mode. The memory as claimed in claim 4 , characterized in that said second transistor (Q101-Q108) is changed to the OFF state irrespective of said data-writing mode when the potential at said source is changed.

Inventors: WATANABE, TAKESHI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1987
Main classification: G11C16
IPC codes: G11C16, H01L29, G11C17, H01L21, H01L27