MULTIPLEX DIVIDING APPARATUS IN A SYNCHRONOUS MULTIPLEXING SYSTEM

Abstract: The system comprises a shift register (21), a control latch unit (22), a channel number identification unit (24), a timing control unit (25) and a demultiplexing latch unit (26). Serial input data (1) are converted into parallel data (SR1, SR2, SRn) and an output of a certain channel (SRn) is latched, in response to a fixed timing signal (PH1). According to the difference (k-n) between the identified channel number (k); and that at the transmitter (n), the timing of the demultiplexing latch unit is controlled so that the outputs (CH1, CH2, ---CHn) correspond to the transmitted signals.

Description: TECHNICAL FIELD The present invention relates to a multiplexing system of PCM signal and particularly to a synchronous multiplexing system to multiplex the basic signal in the relation of integer time of the basic signal rate. BACKGROUND ART In the conventional multiplexing system based on the asynchronous PCM hierarchy, it has been very difficult to directly extract the desired signal from the multiplexed group signal and output it for transmitting and exchanging a broad band signal such as a video signal, because the time slot of each signal in the multiplexed group signal is not fixed. With spreading of the broadband service network, it is now discussed to construct the synchronous network by the high order PCM hierarchy to reduce the influence of jitter, etc. Under such condition, it is also discussed to employ the synchronous multiplexing system in which the basic signal rate of broadband ISDN (Integrated Services Digital Network) is selected to several tens of M bps and the multiplexing PCM hierarchy is set to its integer time. Since the multiplexing hierarchy is set to an integer time of the basic signal rate in this synchronous multiplexing system, an extra signal (such as frame synchronization signal, control signal, etc.) is not inserted in the unit of multiplexing and therefore the control signal, etc. which is required for multiplexing is prepared on the basic signal frame and the multiplexing is carried out by using such control signal region. Thereby, structure of multiplexing part which is required to have high speed characteristic is very much simplified (can be formed only by the parallel-to-serial (P/S) convertion, serial-to-parallel (S/P) conversion), and it is possible to employ the structure which is just suited to high speed processing because it is enough to execute the frame synchronizing processing and control processing of channel switching part for multiplexing channel correspondence at the basic signal rate. Here, the channel switching is carried out to set the correspondence of channels through the channel switching because the channel number at the time of multiplexing does not always match the channel number after multiplexing since the high speed multiplexing part has the function of only the P/S conversion, S/P conversion. However, this structure does not result in any problem in case the service is provided at the rate under the basic signal rate, namely such strtucture is used as a pipe-line, but it probably generates phase difference on the basic signal frame after the demultiplexing in the wide area service where a plurality of basic signal frames must be used in concatenation. Therefore, it has been requested to develop the synchronized multiplexing system which does not generate phase difference. In the synchronous multiplexing system of the prior art, channel correspondence has been established by discriminating the multiplexing control signal written on the basic signal frame after demultiplexing and controlling the channel switching part located immediately after the latch circuit for demultiplexing based on such discrimination result. Fig. 1 is a frame structure of the basic signal. As indicated in this figure, the frame structure is composed of a control signal and information signal (D) and the control signal is formed by the frame synchronization signal (F), multiplexing control signal (ID) and maintenance supervisory signal, etc. Fig. 2 is an example of the structure of synchronized multiplexing device of the prior art. In the sending side, the particular multiplexing channel numbers are respectively written to the multiplexing control signal ID for the basic signal FB of respective channels CH1, CH2, ....., CHn in the discrimination signal writing parts 1₁, 1₂,...., 1 n of each channel at the multiplexing part. In the P/S converting part 2, the basic signal of each channel to which the multiplexing channel numbers are written is converted to serial signal from parallel signal to generate the multiplexing signal nFB. The control part (CONT) 3 controls the operation timings of respective portions in this time. The multiplexing signal nFB in the output of the P/S converting part 2 is sent to the receiving side through the transmission line 4. In the receiving side, the input multiplexing signal is converted to parallel signal from serial signal by the S/P converting part 5 in the demultiplexing part. Thereby, such signal is isolated to the signals SR1, SR2,.....,SRn having different timings, these are latched in accordance with the timing signal of the counter 7 to generate the basic signals CH1', CH2',.... CHn' through the speed conversion. In this timing, multiplexing channel numbers of the basic signals of each channel do not always correspond to those in the sending side. In the frame synchronization, multiplexing channel number discriminating part (FSYNC, ID DET) 8, the frame synchroniztion is set for the basic signal, for example, CHn' of particular channel and the multiplexing channel number is also discriminated. The switch part 9 is then controlled and the sequence of basic signals of respective channels are replaced so that the discriminatd multiplexing channel numbers match the the intrinsic multiplexing channel numbers of the pertaining channel. Thereby, the output signal having the channel numbers CH1, CH2, ...., CHn corresponding to the channel number at the time of multiplexing in the sending side can be obtained. Since the structure of synchronized multiplexing device indicated in Fig. 2 is intended to use the basic signal as the pipe, in case a plurality of basic signal frames are used in concatenation, phase adjustment is necessary among a plurality of channels because the phase relation of respective channels does not always match the phase relation before multiplexing. Namely, in case three basic signals in the basic signal rate of 50 Mbps are used in concatenation, for example, and the signal of 150 Mbps is transmitted, following cases occur depending on the structure of network. 1. Three coupled basic signals are transmitted respectively by different routes and frame phase differences are generated among three basic signals due to path delay time differences. 2. Even when three basic signals are transmitted by the same multiplexing transmission line, frame phase difference is generated between the coupled basic signals depending on the method of multiplex isolation. The problem 1 can be solved by controlling the network so that basic three signals are sent on the same transmission line. However, the problem 2 cannot be solved by the conventional demultiplexing method. Fig. 3 is a time chart of demultiplexing in the conventional synchronous multiplexing device. An input data multiplexed in Fig. 3 generates the outputs sequentially with delay of a bit at the outputs SR1, SR2,....., SRn of the S/P converter 5. The latch part 6 latches said signals in accordance with the fixed timing signal PH1 of a counter 7 to change the speed and isolates the signals to the basic signals CH1', CH2',..., CH'. Since this basic signal outputs do not correspond to the sending side in the channel number, the channels are replaced at the switch part 9 by discriminating the multiplexed channel numbers in order to set again the channel number correspondence. In this case, it is probable, as indicated in Fig. 7, that phase difference of one bit is generated in each channel output. Therefore, phase control is necessary among respective channels coupled by inserting a function to give or eliminate delay of one bit to the output of switch part. Otherwise, in case a video signal is transmitted as the sending signal, it is also probable that MSB (Most Significant Bit) and LSB (Least Significant Bit) in the one byte of output signal may be replaced due to the difference of one bit. However, in this case, the reproduced information of image data becomes useless. The Article from Electronics Letters, Vol. 9, No. 4, February 22, 1973, pp. 73-75 entitled "Distributed frame synchronisation by non-linear-shift-register sequences", by P.T. Nielsen, describes a simple frame synchroniser. Instead of switching between M outputs of a demultiplexer, it is preferred to inhibit a clock pulse to a counter, thereby effectively moving the search one bit position. When correct synchronisation has been established, the synchronisation word is always present at a particular output. The acquisition is initiated by loading the first "L" bits from the particular output into a shift register. Next, a feedback loop is closed and the sequence generated by the register is compared bit by bit with the received sequence. If a discrepancy is detected, the control logic inhibits the next clock pulse to the counter and interrupts the feedback loop, so that "L" bits from the new position may be loaded into the register as before. If, however, "L - 1" bits have been successfully verified upon closure of the loop, and therefore one complete cycle of the synchronisation word has been observed, the synchroniser decides that the position is correct and as soon as the phase has been determined, for instance by noting when the register contains all zeroes, the counter is reset and a message is put out that synchronisation is correct. After this, the feedback loop remains closed and the control logic continuously checks that the number of discrepancies between the received and the locally generated synchronisation word is tolerably low. Japanese Patent JP-60-261 236 describes a frame synchronising circuit in which output signals from a serial/parallel converter are supplied to respective fixed frame synchronising pattern detection circuits and predetermined frame patters are determined separately. A one shift bit is issued until complete synchronisation on all output channels is achieved. DISCLOSURE OF THE INVENTION It is an object of the present invention to provide a demultiplexing device which does not require phase difference adjustment of data among the channels and channel replacement at the demultiplexing part in the receiving side, in case a certain data is transmitted using a plurality of basic signal channels in the multiplexing system for multiplexing the basic signal frame in the signal rate equal to an integer time of the speed of basic signals. It is another object of the present invention to simplify the processings with the structure which realizes synchronization and channel discrimination at the rate of respective basic signals on the occasion of isolating and latching the signal into the basic signals in the receiving side. The objects of the invention are solved by the devices as specified in claims 1 and 5. Basically, the present invention discloses that in the system, the basic signals are generated by inserting the control signal required for multiplexing on the frame structure of basic signal rate and the high level multiplexing signal is formed by multiplexing such basic signals and a circuit operates at the fixed timing and discriminates the control signal is provided and the timing pulse for demultiplexing is controlled in accordance with the discriminated control signal in the receiving part of the synchronous multiplexing system. Thereby stable correspondence between the channel at the time of multiplexing in the sending side and the channel after the demultiplexing in the receiving side can be ensured. As the other modification of the present invention, the channel synchronization is set between the basic signal during multiplexing in the sending side and the basic signal after demultiplexing in the receiving side by discriminating the multiplexing channel number of particular channel and shifting the phase of timing signal for demultiplex so that such multiplexing channel number matches the multiplexing channel number predetermined for the particular channel. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a frame structure of the basic signals as the background of the present invention, Fig. 2 is a structure of synchronized multiplexing system of the prior art, Fig. 3 is a timechart for the demultiplexing device of the synchronized multiplexing system of the prior art, Fig. 4 is a principle structure of a first embodiment of the demultiplexing device of the present invention, Fig. 5 is a detail structure of a first embodiment of the present invention, Fig. 6 is a timechart for multiplex isolation in the embodiment of Fig. 5, Fig. 7 is a structure of an embodiment of the timing control part of Fig. 5, Fig. 8 is a principle structure of a second embodiment of the demultiplexing device of the present invention, Fig. 9 is a detail structure of a second embodiment of the present invention, Fig. 10A is an operation flowchart of multiplex isolation in the embodiment of Fig. 9, Fig. 10B is another embodiment of a part of processings in the flowchart of Fig. 10A. First Embodiment: Fig. 4 is a principle structure of a first embodiment of the demultiplexing device of the present invention. Disclosed herein is a demultiplexing device in the synchronized multiplexing system in which a control signal including the multiplex channel numbers exists on the basic signal frame and the synchronized basic signals are multiplexed into the signal rates equal to an integer time of the rate of said basic signals, comprising a serial/parallel converting means 11, a control latch means 12, a control signal discriminating means 14, a timing control means 15 and a latch means 16 for demultiplexed signals. The serial/parallel converting means 11 converts the input multiplexing signal into the parallel signal from the serial signal and sequentially generates parallel signal outputs in such a number of multiplexing channels having different timings. The control latch means 12 latches the signal of particular channel at the output of serial/parallel converting means 11. The control signal discriminating means 14 discriminats the multiplexing channel numbers of signals of particular channel latched by the control latch means 12 and detects difference from the multiplex channel number to which the control latch means 12 is connected. The timing control means 15 generates the timing signal having timing difference corresponding to difference of said multiplexing channel number for the latch timing in the control latch means 12. The latch means 16 for demultiplexed signals generates the basic signal output in the number of multiplexing channels by latching an output of the serial/parallel converting means 11 with the timing signal of timing control means 15. In the demultiplexing system of the present invention, control is carried out so that the channel number during multiplexing corresponds to the channel number after demultiplexing by discriminating the channel number on the basic signal frame of particular channel with an output obtained by latching a particular channel with the fixed timing in the control latch means, comparing it with the particular channel number to which the control latch means for control is connected and controlling the latch circuit for demultiplexed signals in accordance with difference between said channel numbers. The first embodiment of the present invention is explained further with reference to the detail structure of Fig. 5. In Fig. 5, 21 is a shift register; 22 is a control latch part; 23 is a counter circuit; 24 is a frame synchronization, multiplex channel number discriminating part; 25 is a timing control part; 26 is a latch part for demultiplexed signals. Fig. 6 is a timechart of multiplex isolation in the embodiment of Fig. 5. A multiplexed input data is read into the shift register 21 in accordance with the clock and thereby the outputs SR1, SR2, ....., SRn which are shifted each other by one bit sequentially, are generated in parallel. The control latch part 22 latches an output of a particular channel, for instance, SRn in accordance with the fixed timing signal PH1 of the counter circuit 23 which counts up the clocks and generates an output. The frame synchronization, multiplexing channel number discriminating part 24 establishes the frame synchronization for the output of control latch part 22 and discriminates its multiplexing channel number. If the discrimination result is a multiplexing channel number k, it is shifted by k-n bits for the multiplexing channel number in the sending side. Therefore, the timing control part 25 generates the demultiplex timing signal PHC which is shifted by k-n bits from the write clock in the shift register 21 for channel synchronization and applies it to the latch part 26 for demultiplexed signals. The latch part 26 for demultiplexed signals generates the output basic signals CH1, CH2,....,CHn having the channel numbers corresponding to the channel number at the time of multiplexing in the sending side by executing the speed conversion after latching an output of the shift register 21 in this timing. Fig. 7 indicates an example of the structure of timing control part 25. The decoder 25₁ decodes a counted value sent from the counter circuit 23, while the selector 252 generates the channel synchronization timing signal PHC by selecting an output of the decoder 25₁ in accordance with the multiplexing channel number discriminated in the frame synchronization, multiplexing channel number discrimination part 24. Second embodiment: The principle structure of the demultiplexing device of the second embodiment of the present invention is indicated in Fig. 8. In Fig. 8, a demultipexing device in the synchronized multiplexing system in which a control signal including the multiplex channel numbers exists on the basic signal frame and the synchronized basic signals are multiplexed into the signal rates equal to an integer time of the rate of said basic signals, comprising a serial/parallel converting means 111, a timing signal generating means 112, a latch means 113 for demultiplexed signals and a control signal discriminating means 114. The serial/parallel converting means 111 converts the input multiplexing signal into the parallel signal from the serial signal and sequentially generates parallel signal outputs in such a number of multiplexing channels having different timings. The timing signal generating means 112 generates a timing signal having any phase of the sequentially different timings in the number of multiplexing channels and repeats in the period of input multiplexing signal. The latch means 113 for demultiplexed signals generates the basic signal outputs of the number of multiplexing channels by latching outputs of the serial/parallel converting means 111 with the timing signal of timing signal generating means 112. The control signal discriminating means 114 discriminates the multiplexing channel number of the basic signal outputs of particular channel of the latch means 113 for demultiplexed signals and detects difference between the discriminated multiplexing channel number and the multiplexing channel number corresponding to said particular channel. Correspondence between the channel number at multiplexing and the channel number after demultiplex-can be established by controlling the phase of timing signal in the timing signal generating means 112 in accordance with difference of such detected multiplexing channel numbers. In the demultiplexing system of the present invention, control is carried out so that the channel number at multiplexing in the sending side corresponds to the channel number after demultiplexing by discriminating the multiplex channel of the particular channel after checking the basic signal of said particular channel after demultiplexing and establishing the frame synchronization of such basic signal and then shifting the phase of timing signal in the timing signal generating means for channel synchronization so that such channel number match the multiplexing channel predetermined corresponding to such particular channel as a result of comparison. The second embodiment of the present invention is further explained with reference to the detail structure of demultiplexing device of Fig. 9. In Fig. 9, 121 is a shift register, 122 is a counter circuit for demultiplexing, 123 is a latch part for channel synchronization, 124 is a frame synchronization part, 125 is a multiplexing channel number discriminating part, and 126 is a shift pulse generating part. Fig. 10A is an operation flowchart for demultiplexing in the embodiment of Fig. 9. The multiplexed input data is read into the shift register 121 in accordance with clock and sequentially generates in parallel the outputs SR1, SR2,...., SRn with the shift of one bit. The counter circuit 22 for demultiplexing counts up the clocks and generates the timing signal which has any phase among the sequentially different timings equal to the number of multiplexing channels and repeats with the period of the input multiplexing signal. The latch part 123 for channel synchronization generates the basic signal outputs CH1, CH2, ...., CHn in the number of multitplexing channels through speed conversion by latching outputs of shift register 121 with the timing signal of the counter circuit 122 for demultiplexing. The frame synchronizing part 124 watches the basic signal outputs of particular channel, for instance, the channel CHn in the outputs of the channel synchronization latch part 123, executes frame synchronization processing for frame synchronization using the frame synchronizing signal F indicated in Fig. 4 (step S2 in Fig. 10A) and repeats the processing until frame synchronization is established by checking whether the frame synchronization is set or not (step S3 in Fig. 10A). When frame synchronization is set, the multiplexing channel number discriminating part 125 discriminates the multiplexing channel number of particular channel CHn (step S4 in Fig. 10A) and checks whether the discriminated multiplexing channel number is n or not (step S5 in Fig. 10A). When the discriminated multiplexing channel number is n, it means the channel synchronization is set (step S6 in Fig. 10A) and the processing in the circuit of Fig. 9 is completed. On the other hand, if the discriminated multiplexing channel number is not n, the shift pulse generating part 126 generates the shift pulse to shift, for one bit, the phase of timing signal in the demultiplexing counter circuit 122 (step 7 in Fig. 10A). Next, the frame synchronization part 124 and multiplexing channel discriminating part 125 are initialized, the frame synchronization process and multiplexing channel number discriminating process are repeated, it is checked whether the multiplexing channel number discriminated again is n or not (step S5 in Fig. 10A), when it is not n, the phase of timing signal is shifted for another one bit (step 7 in Fig. 10A), the same process is repeated until the discriminated multiplexing channel number becomes n, and thereby channel synchronization is completed. If the discriminated multiplexing channel number in the multiplexing channel discriminating part 125 is not n, the shift pulse generating part 126 obtains difference between the discriminated multiplexing channel number and n, and the phase of timing signal in the counter circuit 122 for demultiplexing is shifted as much as the number of bits equal to such difference (step S7' in Fig. 10B), thereby the channel synchronization may also be established. As explained previously, the present invention ensures channel synchronizing the output basic signals having no phase deviation among the basic signals of respective channels always multiplexed correctly in the sending side. Accordingly, demultiplexing can be realized stably even for the broadband service in which a plurality of basic signals are used in comcatenation and in this case, the structure of device used can be simplified and also be reduced in size.

Claims: A demultiplexing device of synchronous multiplexing system which has a control signal including a multiplexing channel number in a basic signal frame and multiplexes the synchronised said basic signal into the signal rate equal to integer time of the rate of said basic signal, comprising; serial/parallel converting means (11) which converts an input multiplexed signal into parallel signal outputs via a plurality of multiplexing channel outputs having sequentially different time slots; control latch means (12) which latches the parallel signal of a particular channel output of said multiplexing channel outputs of said serial/parallel converting means (111) at a predetermined timing; characterized by control signal discriminating means (14) which discriminates a multiplexing channel output number corresponding to said particular multiplexing channel output and determines a difference between the multiplexing channel number of said control signal and the multiplexing channel output number; and timing control means (15) which generates a timing signal depending upon a difference being determined; said timing control means (15) generating the timing signal to correspond to the determined difference; and demultiplexed signal latch means (16) which latches the outputs of said serial/parallel converting means (11) based on the timing signal of said timing control means (15) and generates outputs corresponding to the number of multiplexed channel outputs. A demultiplexing device of synchronous multiplexing system according to claim 1, wherein said serial/parallel converting means (11) is composed of a shift register (21) which sequentially holds said input multiplexed signal with the specified clock in the receiving side and shifts such signal. A demultiplexing device of synchronous multiplexing system according to claim 2, wherein said control latch means (12) latches said control signal with a predetermined timing signal generated by a specified clock in the receiving side. A demultiplexing device of synchronous multiplexing system according to claim 1, wherein said timing control means (15) is composed of a decoder and a selector (252), said selector (252) selecting an output of said decoder in accordance with the multiplexing channel output number discriminated by said control signal discriminating means (14) and applying such output to said demultiplexed signals latch means. A demultiplexing device of synchronous multiplexing system which has a control signal including a multiplexing channel number in a basic signal frame and multiplexes the synchronised said basic signal into the signal rate equal to integer time of the rate of said basic signal, comprising; serial/parallel converting means (111) which converts the input multiplexed signal into parallel signal outputs via a plurality of multiplexing channel outputs having sequentially different time slots; timing signal generating means (112) having sequentially different timings, the number of different timings being equal to the number of multiplexing channels; characterized by control signal discriminating means (114) which discriminates a multiplexing channel number of a particular channel of said demultiplexed signals latch means (113) and detects a difference between said discriminated multiplexing channel number and the multiplexing channel number corresponding to said particular channel; said timing signal generating means generating a timing signal which repeats with the period of the input multiplexing signal, and demultiplexing signals latch means (113) which latches the output of said serial/parallel converting means (111) with the timing signal of said timing signal generating means (112) and generates outputs corresponding to the number of multiplexing channel outputs; whereby a phase of said timing signal is determined in accordance with said difference so that the multiplexing channel number corresponding to said particular channel and said discriminated multiplexing channel number become the same. A demultiplexing device of synchronous multiplexing system according to claim 5, wherein said serial/parallel converting means (111) is composed of a shift register (121) which sequentially holds and shifts said input multiplexed signal with the specified clock in the receiving side. A demultiplexing device of synchronous multiplexing system according to claim 6, wherein said control signal discriminating means (114) is composed of a frame synchronising part (124) and a multiplexing channel number discriminating part (125), and discriminates the channel number among said basic signals after establishing synchronisation of basic signal of a particular channel. A demultiplexing device of synchronous multiplexing system according to claim 6, wherein said timing signal generating means (112) is composed of a counter circuit means (122) which counts clock pulses using said specified clock signal supplied to said serial/parallel converting means (111) and generates a latch pulse supplied to said demultiplexed signals latch means (113) with a specified interval and shift pulse generating means (126) which shifts a counting value of said counter circuit depending on the discrimination performed by said control signal discriminating means (114). A demultiplexing device of synchronous multiplexing system according to claim 8, wherein a pulse generated by said shift pulse generating means corresponds to one clock pulse to be supplied to the shift register of said serial/parallel converting means. A demultiplexing device of synchronous multiplexing system according to claim 8, wherein a pulse generated by said shift pulse generating means corresponds to a number of pulses equal to said difference of channel numbers discriminated by said multiplexing channel number discriminating part.

Inventors: AMEMIYA, SHIGEO, IGUCHI, KAZUO, SOEJIMA, TETSUO, WATANABE, TOSHIAKI NISHIMURA-APATO
Applicants: FUJITSU LIMITED
Application year: 1987
Main classification: H04J3
IPC codes: H04J3