RESISTOR STRUCTURE FOR SUPERCONDUCTING CIRCUITS

Abstract: A method for fabricating resistor structures for superconducting integrated circuits. The method comprises forming a superconducting strip (60) and then altering a region on that strip (78) to depress its critical temperature to below the operating temperature. The alteration may be accomplished mechanically, chemically or physically. The order parameter of the material may be depressed by bombarding the material with ions at a sufficient energy level and dosage, and for sufficient duration. The order parameter may also be reduced by placing a magnetic material in contact with or in close proximity with the region (78).

Description: - I- RESISTOR STRUCTURE FOR SUPERCONDUCTING CIRCUITS BACKGROUND 1. Field of the Invention This invention relates to superconducting integrated circuit technologies and, more particularly, to resistors for use in such technologies. 2. Description of Related Art The unrelenting drive for faster and more densely packed electronic circuits has raised problems which are not easily solvable with today's non-superconducting technologies. For example, transmission line propagation delays become important as desired operating speeds increase, rendering the desire for denser packaging more of a necessity. But as circuit densities increase, it becomes more difficult to distribute power to the numerous devices on the chip. Additionally, as more devices are packed into smaller chip areas, it becomes more difficult to dissipate the power needed to operate them. Furthermore, device switching speeds are quickly approaching their theoretical maximums, beyond which they cannot be increased. Superconducting technologies, background information on which may be found in Faris, "VLSI Superconducting Technologies," in Hardware and Software Concepts in VLSI- at 177-238 (1983), hold the promise for overcoming these obstacles. Since superconducting inter-device transmission lines have zero resistance, they can be made much narrower and be packed much more densely than can transmission lines in non-superconducting technologies. The Jbsephson junction, which is a standard switching device for superconducting circuits, has already been demonstrated to operate with a gate delay of less than 2 pS, a figure ultimately reducible to about 0.1 pS. The power dissipation of Josephson junction circuits is less than 1 uW/gate, which is significantly below that of any other known fast- switching technology. As the Faris reference shows, numerous types of circuits have been developed which take advantage of superconducting phenomena. Most of these circuits, to be practical, must make generous use of resistors both for current limiting and for transmission line termination. Past methods for fabricating resistors, however, leave much to be desired. Resistors are usually fabricated in superconducting circuits by depositing on the substrate or other underlying layer a rectangular thin film of resistor material, such as InAu. An insulating material was placed over this and superconducting transmission lines, made for example of PblnAu, were fabricated at the two ends of the rectangle. The transmission lines had oversized contact areas overlapping the ends of the resistor rectangle, and holes in the insulating material permitted the contact areas to ohmically contact the resistor material. A plan view of this type of resistor is shown in Fig. 1, in which the resistor rectangle is shown as 10 and the superconducting contacts are shown as 12. Other examples of such a resistor structure may be found in the Faris reference at page 189, specifically Figure 9-7, or in Lahiri, "A Thin Film Resistor for Josephson Tunneling Circuits", Thin Solid Films, Volume 41, pages 209-215 (1977). One deficiency with this technique is that the superconducting contacts 12 in Fig. 1 must be made much larger than the actual contact area because fabrication is essentially a photolithographic process and allowances must be made to accommodate inaccuracies in mask alignment. This wastes much valuable space which could otherwise be used for circuit structures and device interconnection lines. The large contact area also unnecessarily increases the parasitic capacitance of the circuit as a whole. Additionally, the ohmic contact area between the superconducting material and the resistor material must be extremely clean in order to clearly define the length and width of the resistor rectangle. This requires finding a cleaner which will be highly effective, but will not damage the resistor material or any underlying layer. Moreover, since the resistor and superconducting materials are different, unwanted stresses are induced during the inevitable cycling between room temperatures and cryogenic temperatures. Another difficulty with modern resistor fabrication techniques derives from the manufacturing process itself. Fabrication of the resistor rectangle may be accomplished by the "liftoff" method, which involves several steps. First, the substrate or other underlying layer is coated with a photoresist. The photoresist is then exposed through a mask at the desired resistor location and developed. This leaves a sharply defined rectangular hole at the desired resistor location. The resistor material is then deposited over the entire wafer and the remaining photoresist is dissolved and washed away. The latter step effectively "lifts off" all the resistor material which ' was deposited on top of the photoresist, leaving the rectangular resistor structure in place. If practiced exactly as- described above, the resistor material, when deposited over the entire wafer, will adhere to the photoresist walls defining the rectangle as well as to the horizontal surfaces. This would cause difficulties in the "liftoff" step because no clean and reproducible break can be expected when the resistor material on top of the photoresist separates from the resistor material in the rectangular hole. To avoid this difficulty, the walls of the photoresist are slightly undercut during developing so little or no resistor material will adhere to them. The liftoff technique has a number of problems. First, it is difficult to achieve sub-micron circuit structures with high reproducibility if undercutting is used. Control of the undercutting process is simply too imprecise. Second, the technique limits the choices for resistor material to those with low deposition temperatures because the photoresist will polymerize if too high a temperature is used when the resistor material is being deposited. For example, to be compatible with the use of niobium as the superconducting material, workers generally used molybdenum for a resistor material. The deposition temperature for molybdenum, however, is too high for use of the liftoff process. Resistor fabrication using a subtractive method is also known. In this method, the entire wafer is first coated with the resistor material and then with photoresist. The photoresist is exposed thrpugh a mask and developed so that photoresist remains only above the desired rectangular resistor location. All other resistor material is then etched away and the remaining photoresist removed, leaving only the rectangular resistor. Subtractive methods, too, are difficult to use because, among other things, the etching step must be controlled very carefully in order to avoid damaging any underlying layer which may be sensitive to the etchant. Yet another problem with modern resistor fabrication techniques exists because res ' istors in superconducting circuits fall generally into two ranges: larger values (approximately 50 ohms) for terminating strip lines and smaller values (approximately 0.2 ohms) for limiting current. If a material having low resistivity is used to make resistors in the larger value range, very long resistor lengths would be required. This results in reduced system performance due to increased inductance and capacitance to ground. If on the other hand a material having high resistivity is used to make resistors in the smaller value range, then the resistors must be made very small. This places a costly premium on accurate control of film composition and dimensions. Thus, at least two different materials are typically required to fabricate a practical superconducting circuit, in addition to the at least two materials used for superconduction and for insulation. Since each material requires separate process steps to fabricate, this need for at least four different materials can significantly reduce yield. This, together with the fact that each different material used may require different deposition equipment, renders device manufacturing extremely expensive. It has been suggested that entire microcircuits, including resistors, be fabricated using proximity effect weak link Josephson junctions as the switching element. Notarys and Mercereau, "Proximity Effect Bridge and Superconducting Microcircuitry," J. Appl. -6- Phvs.- Vol. 44 (April 1973), 1821-1830, at 1829. An extensive review of the subject of weak links is given in Likharev, "Superconducting Weak Links," Reviews of Modern Physics, Vol. 51. (January 1979), 101-159. 5 Notarys* icrocircuit would be constructed by depositing first a layer of a normal conductor, such as W, and then several layers of superconducting film strips in order of increasing T . A proximity effect bridge would then be created by selectively anodizing a small region on 10 the strip down to the appropriate depth. A resistor would be created by anodizing such a region down to a superconductor layer which is normal at the operating temperature and exhibits the desired resistivity. Other ideas were suggested for different circuit elements. 15 Resistors made according to Notarys' method, however, would have many of the deficiencies described above with respect to other types of resistors for superconducting integrated circuits. For example, circuit density is limited because the process is still essentially 20 photolithographic, and accommodation must still be made for imperfect mask alignment. Additionally, Notarys' use of many layers of different materials aggravates the problems of cleanliness and of temperature induced mechanical stress. 25 In other related art, it is known that superconductivity can be inhibited or "poisoned" by implanting ions into the superconductor lattice. This occurs by any of the three mechanisms discussed below: Mechanical. If sufficient numbers of ions are implanted 30 with sufficient energy for a long enough period of time, the lattice structure of the superconducting material will be upset and its order parameter thereby reduced. The order parameter is a basic measure of the ability of a material to exhibit superconducting properties. Chemical. For some materials, such as V 3 Si, the ratio of the elements must be relatively precise in order for superconductivity to obtain. In these materials it is possible to reduce the order parameter by implanting ions which will upset this ratio. For V 3 Si, oxygen may be implanted which will react with, and thereby "steal," vanadium. Physical. Several other phenomena have been discovered which will upset the delicate physics of superconductivity. For example, merely placing a magnetic material nearby, such as Ni or Fe, will reduce the order parameter. Implanting these ions directly into the superconductor will certainly have the same effect. As another example, a concentration of b 2 0 5 in a Nb superconductor will reduce the order parameter. Such a concentration can be created by implanting 0 2 into the Nb and allowing it to react. Superconductor inhibition has so far been used only for research into the physics of superconductivity and for experimentation with bridge junctions. For an example of the former, see Meyer, "Ion Implantation in Superconducting Thin Films", published in Application of Ion Beams to Metals (Plenum, New York, 1974) [Proc. of Int. Conf. on Appl. of Ion Beams to Metals, Oct. 2-4, 1973] at 15-26. For an example of the latter, see Kirschman, "Comparative Studies of Ion-Implant Josephson-Effect Structures," IEEE Trans, on Magnetics, Vol. MAG-13 (January 1977), 731-734. Neither article suggests use of the technique to fabricate resistors in microcircuits. SUMMARY OF THE INVENTION It is an object of the present invention to propose a resistor structure not subject to the foregoing -8- difficulties. It is another object of the present invention to propose a resistor structure which is small and not subject to the contact area problem described above. It is another object of the present invention to propose a resistor structure which does not require the use of a multiplicity of materials. It is another object of the present invention to propose a new method for fabricating resistors for superconducting circuits. These and other objects are accomplished according to the present invention by depositing superconducting material on a substrate and then selectively inhibiting the superconductivity of such material wherever a resistive path is desired. Such inhibition can be accomplished by any known, method, but implantation of an ion which reduces the order parameter of the superconductor chemically or physically is preferred. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with respect to specific embodiments thereof. Reference will be made to the drawings, in which like members are given like designations, and in which: Fig. 1 depicts a prior art resistor structure in plan view? Figs. 2 and 11 show graphically the resistivity of a superconductor as a function of temperature before and after treatment; Figs. 3 and 6 are schematic diagrams of superconducting circuits; Fig. 4 is an unsealed cross sectional view of the circuit of Fig. 3, fabricated according to the prior art; Fig. 5 is an unsealed cross sectional view of the circuit of Fig. 3, fabricated according to the invention; Fig. 7 is an unsealed plan view of the circuit of Fig. 6, fabricated according to the prior art; Fig. 8 is an unsealed plan view of the circuit of Fig. 6, fabricated according to the invention; and Figs. 9 and 10 are plan views of resistor structures fabricated according to the invention. DETAILED DESCRIPTION Reduction of the order parameter of a superconducting material by any of the means described previously manifests itself as a decrease in its critical temperature T . Fig. 2 shows how this phenomenon can be used to convert a superconducting material into a resistor. Curve A of Fig. 2 shows the resistivity of a superconducting material, prior to treatment, as a function of the temperature. It can be seen that the resistivity of the material is relatively flat and non- zero above the critical temperature T and then drops off to zero at temperatures below T . The material is used as a superconducter by cooling it to a temperature of operation T which is below T . If the material is niobium, for example, T is approximately 9oK and T might be 4.2 K. After the order parameter of the material has been reduced as described above, the curve effectively moves to the left by several degrees K as shown in curve B, such that a new critical temperature, T ', obtains. Since T -* is below the temperature of operation T, the resistivity of the material has effectively increased from zero to a predictible non¬ zero value. By choosing appropriate dimensions for a strip of superconducting material and -then altering it as described above, any desired resistance value may be obtained. In Fig. 3 there is shown a simple Josephson circuit having a termination resistor 20 which may be fabricated according to the present invention. The circuit consists of a Josephson junction 22 connected at one end to ground 54 and at the other end to a source (not shown) of bias current I via a line 24. A transmission line 26 is connected between the line 24 and the resistor 20. The opposite end of the resistor 20 is connected to ground at 56. The circuit has a voltage output 28 at the point where the resistor 20.is connected to the transmission line 26. A control line 30 for carrying a control current I passes near the Josephson junction 22. The value of the resistor 20 is chosen to be approximately equal to the impedance of the transmission line 26. In operation, a constant bias current Ig is applied which is below the maximum Josephson current I . The junction 22 is therefore in its no-voltage state, and the voltage output at 28 is zero. When a control current I is sent through the control line 30 a magnetic field is induced around the junction 22 which depresses I to a value below the bias current I . The junction 22 therefore switches to its g voltage state and the voltage output at 28 becomes a non-zero value which can be calculated using well known techniques. -11- Using past methods of resistor fabrication, the circuit of Fig. 3 is fabricated as follows. Referring to Fig. 4, a silicon substrate 40 is provided, over which an insulating layer 42 of Si0 2 is grown by anodization. A film 44 of Nb is then deposited over the entire surface to act as a ground plane. Insulating layers 46 and 48 of Nb-O- and SiO, respectively, are then deposited on top of the Nb film 44. Windows 50 and 52 are opened in both insulating layers for the ground connections 54 and 56, respectively, shown in Fig. 3. The resistor rectangle 58 of InAu is next deposited to act as the resistor 20 shown in Fig. 3. A metallization layer 60 is then deposited to form the transmission line 26 between the junction 22 and the resistor 20. This metallization layer 60 is made of superconducting material PblnAu and has an oversized contact which overlaps one end of the resistor rectangle 58, making electrical connection therewith. A layer 62 of SiO insulator having a window 64 is deposited next at the opposite end of the metallization layer 60 to define the boundries of the Josephson -junction 22, and a thin 50A layer (not shown) of barrier material is formed inside the window 64. Another superconducting metallization layer 66, made of PbBi, is deposited in the window 64 to complete the Josephson junction and connect it to ground through the window 50. Another portion of the metallization layer 66 is at the same time deposited partly in the window 52 and partly on the end of the resistor rectangle 58 opposite the metallization layer 60. Like the metallization layer 60, this portion of the metallization layer 66 overlaps the end of resistor rectangle 58 with an oversized contact area. Finally, another insulating layer 70 of SiO is formed over the Josephson junction area defined by the window 64, and a superconducting layer 72 made of PblnAu is deposited on top of the insulating layer 70 to act as the control line 30 of Fig. 3. -12- A cleaning step must be performed before each step m the above process in which a film is deposited which is intended to make electrical contact with a previously deposited layer. Thus .the circuit must be cleaned 5 before the metallization layer 66 is applied in order to be certain that it makes a low-loss connection with the resistor rectangle 58. The circuit must also be cleaned before the layer 66 is applied in order to ensure a low-loss connection between the resistor and ground, and 1C. between the Josephson junction and ground. The choice of cleaners is limited at the earlier step, and is even more limited at the later step because the structure now contains more different materials which might be harmed by the cleaner. In addition, it can be seen that a 15 large number of materials are used in the process, all of which change differently with temperature, thereby creating unwanted mechanical stresses. In Fig. 5 there is shown a cross sectional diagram of another implementation of the circuit of Fig. 3, this 20 time fabricated using the present invention. Although not intended to demonstrate the best mode for using the invention. Fig. 5 does illustrate a contrast between the invention and the prior art. All the steps of the process are the same as those described with respect to 25 Fig. 4, except that no resistor rectangle 58 (see Fig. 4) is ever deposited. Instead, the metallization layer 60 which acts as the transmission line 26 (see Fig. 3) continues through the former location of the resistor rectangle 58 and extends all the way into the window 52 30 to contact the ground plane 44. The portion of the superconducting layer 66 which would have connected the resistor rectangle 58 to ground is also omitted. "* The resistor does nevertheless appear in Fig. 5 as a region 78 of inhibited superconductivity in the layer 35 60. At some time after the layer 60 is put down, the -13- entire circuit is coated with a photoresist which is opaque to ions chosen for implantation. The photoresist is then exposed through a mask and developed so that photoresist remains on the circuit everywhere except the rectangular region 78 on the metallization layer 60. The entire surface is then bombarded with ions at 10 ions/cm , for 30 minutes, with an energy in excess of 50 keV, and the remaining photoresist is washed away. The ions penetrate the metallization layer 60 in the region 78, upsetting the order parameter of the superconductor and rendering it resistive. The steps remaining in the fabrication process are then performed as described with respect to Fig. 4. It can be seen that the same circuit has been built by the inventive method, but using one less film material (InAu) and one less cleaning step. In addition, there are no large contact areas adjoining the resistor to increase parasitic capacitance and unnecessarily occupy space. It will now be shown even more dramatically how the present invention can be used to reduce the size of an integrated superconducting circuit. In Fig. 6 there is shown a schematic diagram of a Josephson junction based, direct coupled, three input "or" gate. It comprises three inputs A, B and C, connected through series resistors R., R- and R_, respectively, to a common input node N.. Input node N. is connected through a Josephson junction J 1 to a node N-, and also through a resistor R^ to ground G. The node N, is connected through a split resistor R 2 to another node N 2 , and also through a Josephson junction J 2 to ground G. The node N 2 is connected through a resistor R- to the output Q, and also through a Josephson junction J- to ground G. The center of the split resistor R- is connected through a resistor R_ to a bias voltage V. Fig. 7 shows a plan view of the circuit of Fig. 6 as it might have been implemented in the past. For convenience, the circuit components in Fig. 7 are given the same designations as their corresponding components in Fig. 6. The resistors are made of Mo and the interconnects are made of Nb. It is apparent that a large amount of area is devoted to oversized contacts which are needed to accomodate imperfect mask alignment. Fig. 8 shows a plan view of the same circuit as'it might be implemented using the present invention. Again, like circuit components are given like designations. The entire circuit is fabricated with Nb and Nb-O-. and the resistive regions, shown by slashes, are made so by implantation of oxygen ions at 10 15 ions/cm2, with an energy in excess of 50 keV, for 30 minutes. The resistive regions have a sheet resistance of about 1-5 ohms/square. Although the drawings are not to scale and their relative dimensions should not be taken as an indication of the actual savings in chip area, the drawings do demonstrate that a significant amount of space can be saved through the elimination of the oversized contact areas which were needed in the past to connect superconducting layers with resistors made from a different material. In the above example, oxygen ions were used to supress the superconductivity of the superconductor at the selected locations. Oxygen was chosen because it reacts with Nb to form b 2 0 5 , the effect on the order parameter of which is physical rather than mechanical. It therefore need not be applied in large dosages. Even mechanical methods of reducing the order parameter, however, are feasible and within the scope of the invention. For example, a niobium superconductor may be bombarded with ions of argon, or may even be heated in appropriate regions with a laser. Care must be taken. however , to ensure that this does not overheat the structure and cause unwanted damage to other parts of the circuit . Fig. 9 shows another embodiment of the present invention which takes advantage of solely physical properties to reduce the order parameter of a superconductor. A superconducting strip 100 of Nb is covered in a region slightly larger than the desired resistor region with an insulator 102, such as Si0 2 . By any known method, a magnetic material 104, such as nickel, is deposited on top of the insulating layer 102 over the desired resistor region. The proximity of the nickel film 104 effectively reduces the order parameter of the niobium film 100, such that its critical temperature T is depressed to a point below the temperature of operation T. It thus has a sheet resistance within the region of approximately 1 ohm/square. It should be noted that while this embodiment does avoid the excessive parasitic capacitance inherent in the contact area problem, it does not reduce the space which must be alloted for the resistor. The nickel layer 104 must be made larger than the width of the superconductor 100 in order to accommodate imperfect mask alignment, and the insulating layer 102 must be made larger still. The embodiment of Fig. 9 can be taken one step further be eliminating the insulating layer 102 and depositing the nickel layer 104 directly on top of the superconductor 100. Such an embodiment is shown in Fig. 10. The proximity of the nickel layer 104 suppresses the superconductivity of the niobium film 100 ia the region underneath the nickel, as in Fig. 9, but the sheet resistance of the resulting structure is now equal to the parallel combination of the sheet resistance of non-superconducting niobium and the sheet resistance of the nickel film. The latter is subject to precise -16- control during the deposition process, thereby providing a method of fine tuning the resistance of the resulting structure. Additionally, chip area is no longer devoted solely to an insulating- layer of Si0 2 . In the embodiments described up to now, a means was employed to reduce the order parameter of a superconductor within a specified region such that the critical temperature T of the superconductor in that region would be reduced to a point which is below the intended temperature of operation of the circuit. Referring to Fig. 2, it can be seen that this results in a region of material which has a constant, predictable resistivity. While many deficiencies in the pre¬ existing technology are overcome by using the embodiments described above, the fact that only one resistivity value is obtainable for a given suppressed superconductor could render manufacture of widely disparate resistor values difficult, as described previously. This can be remedied according to the invention by using a superconductor material whose resistivity as a function of temperature varies only gradually. Fig. 11 shows a resistivity profile for such a material, which could be niobium, modified by a known means. Curve A in Fig. 11 shows the resistivity as a function of temperature for the superconducting material prior to treatment. Curve B shows the same relationship after the order parameter has been reduced by a certain first amount. Curve C shows the same relationship after the order parameter has been reduced by a second, greater amount. It can be seen that, if the temperature of operation T is chosen to be below the temperature at which the unaltered superconductor (Curve A) has resistance, but above the point where the altered superconductors (Curves B and C) have resistance, then - 17- resistors having values in disparate ranges can be fabricated by reducing the order parameter of some of them by the first amount, and reducing the order parameter of the others- by the second amount. A circuit structure which takes advantage of this aspect of the invention could be fabricated by the following method. After superconducting niobium is deposited on the substrate or other underlying layer, the entire circuit is covered with photoresist. The photoresist is exposed through a mask and developed so that openings are made at the desired locations for all the resistors. A first dosage of oxygen ions is then implanted through the openings so as to move the curve of Fig. 11 to the left until it coincides with Curve B. The remaining photoresist is then washed away and the entire circuit is again coated with photoresist. This new layer is then exposed through a different mask and developed so that openings are formed only at the locations where large value resistors are desired. Sufficient oxygen ions are then implanted to move the curve of Fig. 11 to the left in those regions until it coincides with Curve C. This second layer of photoresist is washed away and the remainder of the circuit is fabricated using previously described methods. Upon completion of these steps, those regions which have been bombarded with oxygen ions once will have a resistivity appropriate for the low value resistors, and those regions which have been bombarded twice will have a resistivity appropriate for the higher value resistors. The invention has been described with respect to specific embodiments thereof, and a person of ordinary skill in the art can now ascertain its essential characteristics. Many variations not described above are possible, all within the scope of the invention.

Claims: -18- What Is Claimed Is I. A method for fabricating a resistor for a superconducting circuit operable at a temperature T, comprising the steps of: providing a strip of material which is superconducting at the temperature T; and reducing the critical temperature of a desired region on the strip to render it non- . superconducting at the temperature T. 2. A method according to claim 1, wherein the step of reducing the critical temperature comprises the step of altering the superconducting material chemically. 3. A method according to claim 1, wherein the step of reducing the critical temperature comprises the step of altering the superconducting material physically. 4. Apparatus according to claim 1, wherein the step of reducing the critical temperature comprises the step of placing a magnetic material in close proximity with the region. 5. A method according to claim 1, wherein the step of reducing the critical temperature comprises the step of placing a magnetic material in contact with the region. 6. A method according to claim 1, wherein the step of reducing the critical temperature comprises the step of implanting ions into the region with an effective energy level, dosage level and duration. -19- ' 7. A method according to claim 2, wherein the step of altering the superconducting material chemically comprises the step of implanting ions into the region with an effective energy level, dosage level and duration. 8. A method according to claim 3, wherein the step of altering the superconducting material physically comprises the step of implanting ions into the region with an effective energy level, dosage level and duration. 9. A method according to claim 8, wherein the superconducting material is niobium and the ion is oxygen. 10. A product made by the method of claim 1-. 11. A product made by the method of claim 2. 12. A product made by the method of claim 3. 13. A product made by the method of claim 6-. 14. A product made by the method of claim 8. 15. A method for fabricating a first resistor and a second resistor for a superconducting circuit operable at a temperature T, comprising the steps of: providing a first strip and a second strip of a material which is superconducting at the temperature T and which material has a gradually increasing resistivity as a function of temperature for temperatures above T; -20- reducing the order parameter of a desired first region on the first strip by an amount necessary to give the first region a non-zero first resistivity at the temperature T; and reducing the order parameter of a desired second region on the second strip by an amount necessary to give the second region a non-zero second resistivity at the temperature T different from the first resistivity. 16. A method according to claim 15, wherein the step of reducing the order parameter of the first region comprises the step of altering the superconducting material chemically. 17. A method according to claim 15, wherein the step of reducing the order parameter of the first region comprises the step of altering the supercoducting material physically. 18. A method according to claim 17, wherein the step of altering the superconducting material physically comprises the step of implanting ions into the first region with an effective energy level, dosage level and duration. 19. A method according to claim 18, wherein the superconducting material is niobium and the ion is oxygen. 20. A superconducting integrated circuit operable at a temperature T comprising a strip of superconducting material and a region thereon smaller than the strip, the region having inhibited superconductivity. -2 1- 21. A superconducting integrated circuit according to claim 20, wherein the superconducting material is essentially Nb and the region having inhibited superconductivity further comprises an effective amount of Nb 2 O g . 22. A superconducting integrated circuit according to claim 20, wherein the region having inhibited superconductivity comprises the superconducting material altered chemically to reduce the order parameter by an effective amount. 23. A superconducting integrated circuit according to claim 20, wherein the region having inhibited superconductivity compries the superconducting material altered physically to reduce the order parameter by an effective amount. 24. A superconducting integrated circuit according to claim 20, wherein the region having inhibited superconductivity comprises the superconducting material after having been bombarded with ions at such an energy level, dosage level and for such a duration as to reduce the order parameter by an effective amount.

Inventors: FARIS SADEG MUSTAFA, FARIS, SADEG, MUSTAFA
Applicants: HYPRES INC, HYPRES, INCORPORATED
Application year: 1987
Main classification: H01L39
IPC codes: H01L27, H01L39