A high switching speed low power logic circuit

Abstract: Disclosed is a Complementary Cascoded Logic (C²L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors (T1, T2, T3) and the invert function is implemented with a first NPN transistor (T4). An inverted NPN transistor (T5) serves as a current source for the first NPN. A first low voltage Schottky diode (D3) is serially connected between the emitter of the first NPN transistor (T4) and the emitter of the inverted NPN current source transistor (T5). The first Schottky diode (D3) precludes, under certain conditions, simultaneous conduction of the first NPN transistor (T4) and the inverted transistor (T5). Oppositely poled second and third low voltage Schottky diodes (D1, D2) are utilized via an emitter follower output (T6) to provide an output voltage swing of V R ± V F , where V R is a reference voltage and V F is the potential drop across a Schottky diode. The low power high speed logic circuit (C²L) has particular utility in redundant circuit applications.

Description: Field of the Invention The invention relates to high speed logic circuits of low power consumption suitable for very large scale integration (VLSI) in which a sizable number of circuits are integrated on a single semiconductor chip. Electronic devices continue to show a trend to be smaller by the use of integrated circuits, and such trend is very important to lower the cost and to increase the operating speed of such devices by reducing the signal propagation delay time. However, when the apparatus is made smaller, the packing density of the circuit will increase and the method of dissipating the heat generated in the circuit will become a problem. Usually the power dissipation per unit circuit is larger in a high speed logic circuit than in a low speed logic circuit. It is all the more difficult in the high speed logic circuit to make the apparatus small. Particularly, it is very difficult to produce VLSI in which several thousand logic gates are integrated on a semiconductor chip of several mm², from the conventional high speed logic circuits. As a technique of reducing the power dissipation in a logic circuit without affecting the operating speed, the variation of the stored energy required for logic operation has been minimized by reducing the stored energy in the circuit and to make the source voltage as low as possible. Among already extensively used logic circuits are, for example, saturation mode logic using a common emitter transistor as an inverter, direct coupled transistor logic (DCTL), resistor transistor logic (RTL), diode transistor logic (DTL) or transistor transistor logic (TTL) and non-saturation mode logic such as emitter coupled logic (ECL) and complementary transistor logic (CTL). In saturation mode logic, as the saturated condition and cut-off condition of the inverter transistor, that is, the maximum condition and minimum condition of the stored energy correspond to the ON and OFF conditions of the gate, the operating speed is inherently low. On the other hand, in ECL circuits, as the current switch transistors having the function of logic gates operate in non-saturated condition, the operating speed is very high. However, ECL circuitry has a deficiency in that the power consumption is high. First, the constant current circuit requires a relatively large voltage and consumes unnecessary electric power. Further, whether the gate is ON or OFF, the total current of the gate will be the same and the power consumption will be high. Background Art There is a very sizable number of logic circuits known to the art. It is to be appreciated with reference to the subject invention, that the following art is not submitted to be the only prior art, the best prior art, or the most pertinent prior art. US-A 3,450,896 entitled "Transistor Switching Circuit Having Compensated Circuit" granted June 17, 1980 to Kenji Tanguchi et al. US-A 3,522,446 entitled "Current Switching Logic Circuit" granted August 26, 1968 to Koji Kodama. US-A 3,579,272 entitled "Logic Circuits" granted May 18, 1971 to Richard Foss et al. US-A 3,656,004 entitled "Bipolar Capacitor Driver" granted April 11, 1972 to Douglas W. Kemerer et al. US-A 3.787.737 entitled "High Speed/Logic Circuit" granted January 22, 1974 to Hisakazu Mukai. US-A 4,039,867 entitled "Current Switch Circuit Having An Active Load" granted August 2, 1977 to Richard Jay Blumberg et al. US-A 4,112,314 entitled "Logical Current Switch" granted September 5, 1978 to Venkappa L. Gani et al. US-A 4,321,490 entitled "Transistor Logic Output For Reduced Power Consumption And Increased Speed During Low to High Transition" granted March 23, 1982 to Robert W. Bechdolt. US-A 4,339,676 entitled "Logic Circuit Having A Selectable Output Mode" granted July 13, 1982 to Richard A. Ramsey. Publication: "Voltage Booster" by A. H. Dansky et al, IBM Technical Disclosure Bulletin, Vol. 26, No. 7B, December 1983, pages 3618-19. US-A-3 836 792 discloses a logic circuit according to the preamble of claim 1 comprising a four stage circuit which utilizes storage in a transistor together with its inverse beta to obtain fast switching. A diode anti-saturation clamp is also used in one of the stages in order to enhance rapid switching. Summary of the Invention The primary object of the invention is to provide an improved logic circuit having high switching speed and low power consumption. An object of the invention is to provide a high speed low power logic circuit having a self-contained power supply regulator. An object of the invention is to provide a high speed low power logic circuit having a high input impedance and a low output impedance. An object of the invention is to provide a high speed low power logic circuit particularly suitable for redundant circuit applications. An object of the invention is to provide a high speed low power logic circuit having power supply noise immunity. These and other objects are provided by means of the Complementary Cascoded Logic (C²L) circuit as claimed in the claim 1. The invention may be summarized as a Complementary Cascoded Logic (C²L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors and the invert function is implemented with a first NPN transistor. An inverted NPN transistor serves as a current source for the first NPN. A first low voltage Schottky diode is serially connected between the emitter of the first NPN transistor and the emitter of the inverted NPN current source transistor. The first Schottky diode precludes, under certain conditions, simultaneous conduction of the first NPN transistor and the inverted transistor. Oppositely poled second and third low voltage Schottky diodes are utilized via an emitter follower output to provide an output voltage swing of V R ± V F , where V R is a reference voltage and V F is the potential drop across a Schottky diode. A low power high speed logic circuit having particular utility in redundant circuit applications is disclosed. Alternatively, the invention provides a circuit employing active redundancy based on the C2L circuit summarized above. A circuit using active redundancy is disclosed in US-A-2 942 193. Brief Description of the Drawings The foregoing and objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings. Figure 1 is a schematic circuit diagram of an embodiment of a complementary cascoded logic circuit in accordance with the invention. Figure 2 discloses idealized waveforms to be viewed in conjunction with explanation of the operation of the logic circuit of Figure 1. Figure 3A illustrates a known three gate logic chain. Figure 3B illustrates a redundant circuit (active redundancy) employing logic circuits in accordance with the invention. Figure 1 discloses a Complementary Cascoded Logic (C²L) circuit in accordance with the invention, which performs a logical AND-INVERT (AI) function. If input A, B, or C to one or more of the input transistors, T1, T2, or T3 is at a low logic level, the output of the circuit will be at a high logic level. A low logic level input will establish the voltage at the emitters of the PNP transistors T1, T2, and T3. The resulting voltage at the base of T4 will not forward bias the base-emitter junction of T4 and low barrier Schottky diode D3, forcing them into a non-conductive state. The current flow through resistor R2 will result in two alternate conductive paths. The first conductive path is from the positive supply VP through R2 and the base-emitter junction of T6. As in ECL circuits, output transistor T6 is always on establishing the output voltage level as a forward biased base-emitter junction voltage below its base voltage. Typically, the base current of T6 through R2 determines the base voltage of T6. This conductive path would directly reflect variations in the value of the positive supply to the output of the circuit. The second conductive path eliminates the direct dependency of the output level on positive supply voltage. This conductive path consists of resistor R2, low barrier Schottky diode D1 and reference voltage V R . When T4 and D3 become non-conductive, the voltage at the base of T6 will begin to rise until the level attains a forward biased low barrier Schottky diode voltage (V F ) above reference supply V R . Diode D1 will conduct current and clamp the voltage at the base of T6 to a forward biased low barrier Schottky diode voltage above reference supply V R . Variations in the positive supply are absorbed by this clamping action, eliminating the direct dependency of the circuits high output voltage level on the positive supply. For the opposite state of operation, transistor T4 and diode D3 will conduct current only when all of the inputs to the circuit are at a high logic level and once again two alternate conductive paths exist. The first conductive path is from the positive supply VP through resistor R2. Typically, the current requirement of T4 and D3 through R2 determines the base voltage of T6. This conductive path would directly reflect variations in the value of the positive supply to the output of the circuit. The second conductive path again eliminates the direct dependency of this output level on positive supply voltage. This conductive path consists of low barrier Schottky diode D2 and the reference voltage V R . When T4 and D3 become conductive, the voltage at the base of T6 will begin to fall until the level attains a forward biased low barrier Schottky diode voltage (V F ) below reference supply V R . Diode D2 will conduct current and clamp the voltage at the base of T6 to a forward biased low barrier Schottky diode voltage below reference supply V R . Variations in the positive supply are absorbed by this clamping action, eliminating the direct dependency of the circuits low output voltage level on the positive supply. The generation (not shown) of the reference supply voltage V R would be implemented on the chip utilizing this circuit family. The design of this supply voltage would include the capability to track the operation of the circuit with power supply, process, and temperature variations. As described, this reference voltage in association with low barrier Schottky diodes D1 and D2 clamp the low and high output logic levels of the circuit: (high output) V H = V R + V F (D1) - V BE (T6) (low Output) V L = V R - V F (D2) - V BE (T6) This clamping action establishes a controlled environment for the output voltage swing of the circuit, V R ± V F , in addition to providing the circuit with power supply noise immunity. The minimum output voltage swing maximizes the performance of the circuit. A significant aspect of this circuit is the use of PNP transistors (as emitter followers) to implement the AND function at the input of the circuit. Typical bipolar logic circuits, ECL, TTL, SCS, use NPN transistors as inputs to the circuits. The inherent internal capacitances, collector to base (CCB) and collector to substrate (CCS), of these devices directly affects their performance. The performance impact related to CCB can be directly attributed to the MILLER effect theorem. The voltage at the collector of a NPN transistor is out of phase with the voltage at its base, resulting in twice the voltage change across CCB. The effect of this voltage is to double the CCB capacitance effect, reducing circuit performance. The collectors of input NPN transistors are common. The total capacitance at the collector node is the summation of the individual CCS capacitances. The CCB and CCS capacitance of an NPN transitor reduces the performance of these circuits by adding capacitance to the switching path of the circuit. The use of the PNP as an emitter follower at the input to the circuit reduces the amount of capacitance in the switching path, thereby improving the performance of the circuit. The internal emitter-base capacitance of the PNP device provides an in phase AC path to charge and discharge the base of transistor T4. Typical bipolar AI circuits, such as TTL, require large amounts of current to perform the logic function. The operation of these circuits are susceptible to the voltage drops that occur as a result of this current flow. The physical distance between these circuits must be minimized to reduce the effects of the voltage drop. This distance between circuits and the amount of current required to maintain functionality, at worst case conditions, are two of the factors which determine the drive capability of a circuit. The inherent operation of the PNP input maximizes the drive capability of the C²L circuit by reducing the current flow required to sustain functionallity. The current that flows between circuits is the base current of the PNP. This current would be a function of the gain of the PNP and the PNP emitter current established within the circuit. The PNP input emitter follower allows the circuit to achieve high input impedance, a desired trait of V L SI circuits. Minimization of the PNP base current results in an increase of the input impedance of the circuit, further improving the performance of the C²L circuit. The C²L circuit is a high performance, low power, bipolar logic circuit. The use of PNP transistors reduces the total capacitance in the switching path thereby allowing maximum performance. The use of low barrier Schottky diodes minimizes circuit power dissipation and establishes a minimum symmetrical voltage swing which reduces the circuit delay. Still referring to Figure 1, the following illustrative circuit parameters are set-forth. CIRCUIT OPERATION The AND function at the emitters of the input PNP transistors establishes the base of T4 as a forward biased PNP emitter-base junction voltage above the input level of the circuit. LOW LOGIC LEVEL INPUT A low logic level, 0.1 volts, at either of the input transistors sets the voltage at the base of T4 to 0.85 volts. This voltage level will not forward bias the base-emitter junction of T4 and low barrier Schottky diode D3, forcing them into a non-conductive state. Resistor R1 will provide the emitter current, 0.35 mA, for the input PNP transistors. The resulting PNP base current will be determined by the PNP device characteristics and the number of inputs at the low logic level. The maximum base current will occur when one input is at a low logic level. For a beta of 49, the maximum base current will be 0.007 mA. This current level establishes the input as a high DC impedance, minimizing load effects on the circuit providing the low logic level input. Minimization of the loading effects increases the fan out capabilities of the logic circuit. In addition, the common collector configuration of the input PNP transistors minimizes the AC effects of CCB maximizing AC impedance. When T4 and D3 are not conducting current, the switchable current source transistor T5 saturates and the current flow through resistor R2 will result in two alternate conductive paths. Resistor R3 will provide transistor T5 with continuous base current. The effective base-collector capacitance of a normal operating NPN transistor increases when the device is saturated. This increase in capacitance reduces the AC performance of a saturated NPN during normal operation. The AC effects of saturating T5 are minimized by use of the inverse operation characteristics of the NPN transistor. When T4 and D3 are off, the base-emitter junction of T5 will forward bias, charging the internal device capacitance of this junction. Minimization of the charge stored within this device improves the AC performance of T5 as a switchable current source. ( Note: The schematic shows V R as the voltage source of resistor R3. This is not a requirement for circuit operation. The positive supply, VP, may be used in conjunction with an increase in the value of resistor R3.) The conductive paths clamp the base of T6 to a forward biased low barrier Schottky diode voltage (0.25 volts) above reference supply V R (1.1 volts), or 1.35 volts. Transistor T6 is used as an emitter follower to set the output voltage level as a forward biased base-emitter junction voltage below its base. Variations in the positive supply are absorbed by the clamping action of diode D1, eliminating the direct dependency of the circuits high output voltage level (0.60 volts) on the positive supply. LOW - HIGH INPUT TRANSITION The emitter follower action of the PNP input transistors provides an in phase path to establish the voltage at the base of T4. As the input approaches a high logic level, the voltage at the base of T4 also increases. The increase in voltage at the base of T4 will cause T4 to conduct current when the base attains the cut-in voltage level of the base-emitter junction (0.7 volts), above the return supply. At this voltage, by-pass capacitor C1 provides a low impedance AC path to the return supply allowing T4 to turn on rapidly. The base of T4 will continue to rise forward biasing diode D3. The previously dormant switchable current source, transistor T5, will now provide a conductive path for the DC current flow of T4 and D3. When T4 and D3 become conductive, two alternate conductive paths also exist. The voltage at the base of T6 will begin to fall, as a result of the current flow through resistor R2, until the level attains a forward biased low barrier Schottky diode voltage (0.25 volts) below reference supply V R (1.1 volts) or 0.85 volts. Diode D2 will conduct current and clamp the voltage at the base of T6 to a forward biased low barrier Schottky diode voltage below reference supply V R . Variations in the positive supply are absorbed by the clamping action of diode D2, eliminating the direct dependency of the circuits low output voltage level (0.10 volts) on the positive supply. The increase in voltage at the base of T4 also reduces the current flow through resistor R1 ( 0.15 mA). This reduction in current reduces the PNP emitter and base currents forcing them into a higher impedance state further improving the load requirements of the circuit. HIGH - LOW INPUT TRANSITION The emitter follower action of the PNP input transistors once again provides an in phase path to establish the voltage at the base of T4. As the input approaches a low logic level, the voltage at the base of T4 also decreases. Due to the action of capacitor C1, the decrease in voltage at the base of T4 will reduce the current flow through T4 and D3. The voltage at the base of T6 will begin to rise, as a result of the reduction of current flow through resistor R2 and diode D2, until the level attains a forward biased low barrier Schottky diode voltage (0.25 volts) above reference supply V R (1.1 volts) or 1.35 volts. Diode D1 will conduct current and clamp the voltage at the base of T6 to a forward biased low barrier Schottky diode voltage below reference supply V R . Variations in the positive supply are absorbed by the clamping action of diode D2, eliminating the direct dependency of the circuits low output voltage level (0.10 volts) on the positive supply. The C²L circuit is particularly suited for redundancy applications used to implement Wafer Scale Integration (WSI). A primary goal of redundancy design is to insure logic functionality in the presence of random process defects. Redundant logic designs eliminate the effects of process defects by providing multiple paths for logic "continuity". Active redundancy will be used as an illustrative embodiment of the application of the C²L circuit. Active redundancy is a method of design that requires multiple hardware and wiring. This method is tolerant of defects that result in faults which cause the input or output of a circuit to be in a non-controlling state. The controlling state of a circuit is defined as the logical input level that governs the logic level of the output. The non-controlling state is defined as the logic input level that sets the logic level of the output only when all inputs to the circuit are at the non-controlling state. The word "Active" means that the corrections occur instantaneously and require no checking or diagnostic programming. Active redundancy is implemented by doubling the fan in and fan out of the non-redundant circuit, in addition to the requirement of duplicating the circuit. Figure 3a illustrates a non-redundant, three gate logic chain, for a single fan in and fan out gate. Figure 3b illustrates the same logic chain implemented with Active redundancy. The duplicate gates of A, B, AND C are A′, B′ and C′, respectively. The output of each gate is fed to the subsequent gate in the chain and its duplicate. The doubling of the fan in and fan out provides an alternate path of logic flow. If a gate has a defect which causes its input or output to be in a non-controlling state, logic will flow through the duplicate gate. This allows the logic to instantaneously correct itself by absorbing the defect through the alternate path. Defects that cause controlling states on any gates input or output will not be absorbed. The functionality of this form of redundancy is determined by the circuits susceptibility to process defects which result in controlling state defects. Typical high speed logic circuits have the same logic capability, OR, at both the input and output of the circuit. These circuit types have a high logic level as the controlling state. Unfortunately, the predominate state caused by typical process defects is a high logic level, making these circuits unsuitable for Active redundancy WSI. As previously described, the controlling and non-controlling states of the C²L circuit are the low and high logic level, respectively. The logic functions at the input and output of C²L are AND and OR, respectively. The complementary logic functions at the input and output allows C²L to absorb defects that result in a high logic level. Typical defects, such as transistor pipes and opens or shorts within the intercircuit metal do not force the output or input of C²L to a controlling state.

Claims: A high switching speed low power Complementary Cascoded Logic (C2L) circuit for performing a logical function, said logic circuit comprising: input circuit means (T1, T2, T3), said input circuit means having at least two input terminals (A, B) and a reduced capacitance and being connected to a second potential source (0V); a first transistor (T4) having a collector, base and emitter, said base of said first transistor connected to said input circuit means; a first resistor (R1) connected between said base of said first transistor (T4) and a first source of potential (Vp); a second resistor (R2) connected between said collector of said first transistor (T4) and said first source of potential (VP); a third transistor (T6) having a collector, base and emitter, said collector of said third transistor being connected to said first source of potential (Vp), said base of said third transistor (T6) being connected to said collector of said first transistor (T4); a third resistor (R4) serially connected between the emitter of said third transistor (T6) and said second potential (0 V); and an output terminal connected to said emitter of said third transistor (T6); characterized in that it further comprises: active current source means (D3, T5) connected between said emitter of said first transistor (T4) and said second source of potential (0V), said active current source means (D3, T5) including the serial interconnection of a diode (D3) and a second transistor (T5) being an inversely operated transistor, said inversely operated transistor having a collector, base and emitter, said collector of said inversely operated transistor (T5) being connected to said second potential source (0 V); circuit means including a source of reference potential (VR), first (D1) and second (D2) low voltage Schottky diodes, the anode of said first Schottky diode (D1) being connected to said collector of said first transistor (T4), the cathode of said second Schottky diode being connected to said collector of said first transistor (T4), and a resistor (R3) connected between said base of said inversely operated transistor (T5) and a common connection of the cathode of said first Schottky diode (D1) and the anode of said second Schottky diode (D2), said common connection being connected to said source of reference potential (VR). A logic circuit according to claim 1 wherein said input circuit means includes at least first and second PNP type transistors (T1, T2) each of said PNP type transistors having a collector, base and emitter, the collectors of first and second PNP type transistors (T1, T2) being connected in common to said collector of said inversely operated transistor (T5), said bases of said first and second PNP transistors respectively connected to said first and second input terminals, and wherein said first transistor (T4), said inversely operated transistor (T5) and said third transistor (T6) are respectively NPN type transistors. A logic circuit according to claim 2 wherein said active current source means includes a low voltage Schottky diode (D3) having an anode and a cathode as said diode (D3) and an inversely operated NPN type transistor (T5) as said inversely operated transistor (T5), said anode of said Schottky diode (D3) being connected to said emitter of said first transistor (T4), said cathode of said Schottky diode (D3) being connected to said emitter of said inversely operated transistor (T5). A logic circuit according to claims 3 wherein said active current source means includes a speed-up capacitor (C1) connected between said emitter of said first transistor (T4) and said collector of said inversely operated transistor (T5). A high switching speed circuit employing active redundancy, said circuit comprising: at least first (A), second (A'), third (B), fourth (B') complementary cascoded logic circuits as defined in any preceding claims; said first (A) and said second (A') circuits each having at least two inputs and an output; said third logic circuit (B) having a first input, a second input and an output, said first input of said third logic circuit (B) connected to said output of said first logic circuit (A), said second input of said third logic circuit (B) being connected to said output of said second logic circuit (A'); said fourth logic circuit (B') having a first input, a second input and an output, said first input of said fourth logic circuit (B') being connected to said output of said first logic circuit (A), said second input of said fourth logic circuit (B') being connected to said output of said second logic circuit (A'); whereby said circuit is capable of obviating at least certain defects of faults in at least one of said first through fourth complementary cascoded logic circuits. A high switching speed circuit according to claim 5 further comprising: fifth (C), and sixth (C') complementary cascoded logic circuits as defined in anyone of claims 1-4; and said fifth logic circuit (C) having a first input, a second input and an output, said first input of said fifth logic circuit (C) being connected to said output of said third logic circuit (B), said second input of said fifth logic circuit (C) being connected to said output of said fourth logic circuit (B'); said sixth logic circuit (C') having a first input, a second input and an output, said first input of said sixth logic circuit (C') being connected to said output of said third logic circuit (B), said second input of said sixth logic circuit (C') being connected to said output of said fourth logic circuit (B'), and whereby said circuit is capable of obviating at least certain defects or faults in at least one of said first through sixth complementary cascoded logic circuits.

Inventors: BANKER DENNIS CLARK, DORLER JACK ARTHUR, HRYCKOWIAN JOHN NICHOLAS, BANKER, DENNIS CLARK, DORLER, JACK ARTHUR, HRYCKOWIAN, JOHN NICHOLAS
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: H03K19
IPC codes: G06F11, H03K19