MULTIPLE DISPLAY SYSTEM

Abstract: A multiple display system is adapted to display data in the VIDEOTEX standard on a display formed of a plurality of display devices. The system comprises an encoder (l,2) for generating a code on the basis of internal or external data supplied thereto, a plurality of decoders (3A to 3I), each of which includes a central processing unit, successively arranged in series with respect to the encoder, and a plurality of display devices (4A to 4I) provided respectively corresponding to the plurality of decoders to thereby display a large image by the plurality of display devices. The encoder inserts an identification number in a predetermined portion of a data sequence. The plurality of decoders respectively select data with corresponding identification number, convert the selected data into a video signal, and supply respective display devices with the video signal.

Description: This invention relates generally to a multiple display system, and more particularly to a multiple display system for displaying a VIDEOTEX information. A multiple display system to display data on a display formed of a plurality of display devices as a single picture screen is known from EP-A 0 074 696. The known system comprises: encoder means for generating a code on the basis of internal or external data supplied thereto; a plurality of decoding means arranged in parallel with said encoder means; a plurality of display devices provided respectively corresponding to said plurality of decoding means, and means for setting an identification number in the form of address data to each of said decoding means which respectively respond to corresponding address data supplied thereto, process the video signals received and supply said display devices with said video signals. Since said plurality of decoding means with related display means is connected in parallel to the encoder means, it is required to provide a plurality of transmission lines which results in a complicated control program, complicated circuit construction and high production cost. It is an object of the present invention to provide a simpler multiple display system. The multiple display system according to the present invention is defined in claim 1. In this system, only the first and the last of the serially connected decoding means have to be connected via transmission lines with the central encoder means. The transmission lines between the successive decoding means can be very short, as these decoding means are arranged very close to each other by being allocated to the displays which form a single picture screen. Extraction of data allocated to a respective decoding means is made possible by an identification number inserted by said encoder means into a data sequence transmitted to said serially connected decoding means. To prevent an uncontrollable brakedown of the system due to data overflow in one of the decoding means, each decoding means has the feature to generate a transmission stop signal to the preceding decoding means or to said central encoding means respectively, when it detects an overflow state. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiment taken in conjunction with the accompanying drawings, throughout which like reference numerals designate like elements and parts. Fig. l is a systematic block diagram showing a construction of an embodiment of the present invention; Fig. 2 is a block diagram showing a construction of a controller appearing in Fig. l; Fig. 3 is a block diagram showing a construction of a decoder appearing in Fig. l; Figs. 4 and 5 are respectively a flow chart and a diagram used to explain how an enlargement or reduction of an image is effected; Figs. 6 and 7 are respectively a flow chart and a diagram used to explain how a data conversion for enlargement of an image is effected; Figs. 8 and 9 are respectively a flow chart and a diagram served for explaining how a bezel correction is effected; Figs. l0 and ll are respectively a flow chart and a diagram employed for explaining how an ID number is assigned to a data sequence; Figs. l2 and l3 are flow charts used to explain how decoders are synchronously operated by an external control; and Figs. l4 and l5 are respectively a diagram and a flow chart used for explaining how a flow control is effected. An embodiment of a multiple display system according to the invention will hereinafter be described with reference to Figs. l to l5. Fig. l shows a whole arrangement of an embodiment of the multiple display system according to the invention. In Fig. l, reference numeral l designates a controller or information generating means for generating information on the basis of data internally or externally supplied thereto which includes a keyboard 2 connected thereto and a printer and so on though not shown. The controller l has a communication (hereinafter simply referred to as a "COM") port and an auxiliary (hereinafter simply referred to as an "AUX") port. The controller l receives the internal and/or external information data through the COM port, carries out the processing thereof, and then transmits the same through the AUX port. A plurality of decoders, for example, nine decoders 3A to 3I are arranged in series with respect to the controller l, each of which has a COM port and an AUX port. The COM port of the decoder 3A is connected with the AUX port of the controller l, and the AUX port of the decoder 3A with the COM port of the decoder 3B. The AUX port of the decoder 3B is connected with the COM port of the decoder 3C, and the AUX port of the decoder 3C with the COM port of the decoder 3D. The rest of the decoders are connected in the same manner as mentioned above. Therefore, the controller l and the decoders 3A to 3I are substantially connected in series in this order and the data can be bi-directionally transmitted through the respective COM and AUX ports. Provided with the respective decoders 3A to 3I are display devices 4A to 4I which are respectively supplied with output signals from the decoder 3A to 3I. In this case, display devices (3 × 3 = 9) are used as an example of a picture screens (m × n). As the controller l, there may be considered such as constructed e.g. as shown in Fig. 2. In Fig. 2, reference numeral l0 designates a central processing unit (hereinafter simply referred to as a "CPU") which is provided with a system ROM ll, a work RAM l2, a video RAM l3, a color palette memory l4, an I/O (input/output) interface l5 and a floppy disk interface l6. The I/O interface l5 is provided with the above mentioned COM port and AUX port and generates a synchronizing control signal to establish the synchronization among the respective decoders 3A to 3I, as will be described later. Arranged in the output sides of the video RAM l3 and the color palette memory l4, both for display, is a D/A converter l7. Further provided with the CPU l0 is a CRT controller 30 which supplies the D/A converter with a picture drawing instruction on the basis of a picture drawing command outputted from the CPU l0. The analog signal converted from the digital signal by the D/A converter l7 is processed by a video signal processing circit l8 to be transformed into R, G, and B chromatic or color signals which are then supplied to a display device l9. Incidentally, each pixel or picture element on the screen of the display device l9 corresponds one by one to the address in the video RAM l3. As each of the decoders 3A to 3I, there may be considered such one as constructed e.g. as shown in Fig. 3. In Fig. 3, reference numeral 20 is a CPU which is provided with a system ROM 2l, a work RAM 22, a video RAM 23, a color palette memory 24, and an I/O interface 25. The I/O interface 25 is provided with the aforementioned COM port and AUX port and supplied with the aforementioned syncronizing control signal. Arranged at the output sides of the video RAM 23 and the color palette memory 24, both for display, is a D/A converter 26. Further provided with the CPU 20 is a CRT controller 40 which supplies the D/A converter 26 with a picture drawing instruction on the basis of a picture drawing command outputted from the CPU 20. The analog signal converted from the digital signal by the D/A converter 26 is processed by a video signal processing circit, not shown, to be transformed into R, G, and B color signals which are supplied to one of the display devices 4A to 4I corresponding to the decoder. In other words, the decoder may be constructed in the same manner as the cntroller l, except that the decoder does not comprise the floppy disk interface and the display device. It is without saying that a keyboard, a printer and so on may be provided with the I/O interface 25. Next, the function of enlargement or reduction of a picture will be hereinafter described with reference to Figs. 4 and 5. First, the procedure of this function is explained, referring to Fig. 4. When an enlargement or reduction program is started at step 40l, the CPU l0 reads out a picture drawing command written on a disk, not shown, in the form of a bit sequence, through the floppy disk interface l6 and stores the picture drawing command in the work RAM l2. Then, at step 402, the CPU l0 analyzes the operand of the picture drawing command, calculates logical X - Y coordinates (on the unit screen), and obtains coordinates of a certain point P (x, y) on the screen, as shown in Fig. 5A. Next, at step 403, the coordinates P (x, y) is multiplied by α (α represents an enlarging or reducing scaling ratio being α ≧ 0) to obtain a point P′ (X, Y) in the enlarged or reduced coordinates by X = αx and Y = αy. The program then proceeds to step 404 whereat it is judged whether or not the value X obtained at step 403 satisfies 0 < X < l. If the answer at step 404 is no, the program proceeds to step 407 to be terminated, since the picture drawing cannot be effected unless X satisfies the above condition, 0 X l. On the other hand, if the answer at step 404 is yes (0 < X < l is satisfied), the program proceeds to step 405 whereat it is judged whether or not the value Y obtained at step 403 satisfies 0 < Y < l. If the answer at step 405 is no, the program proceeds to step 407 to be terminated, since the picture drawing cannot be effected unless Y satisfies the above condition, 0 Y l. If the answer at step 405 is yes (0 < Y < l is satisfied), then the program proceeds to step 406 wherein the values of the coordinates of the point P is stored at a predetermined address in the video RAM l3. An address V-RAMadd at a predetermined position in the video RAM l3 is determined by the following equation as shown in Fig. 5B. V-RAMadd = α y X max + α x Fig. 5B shows the screen of the display device l9, each pixel of which corresponds to each address in the video RAM l3. X max and Y max respectively represent, for example, 256 and 200 pixels. The point P of the enlarged or reduced coordinates is drawn at the point P′ expressed by (αx, αy) in Fig. 5B. The information indicative of the enlarged or reduced coordinates thus stored in the video RAM l3 is read out therefrom under the control of the CRT controller 30. The information is added with the information representative of the intensity of color generated by the color palette memory l4, converted into analog signals by the D/A converter l7, supplied to the video signal processing circuit l8 to be transformed into R, G, and B color signals, and then displayed on the screen of the display device l9. The information indicative of enlargement or reduction information read from the video RAM l3 is added with an ID (identification) number corresponding to each of the decoders, and then supplied to the decoders 3A to 3I through the AUX port of the I/O interface l5. Each of the decoders 3A to 3I fetches the information having the ID number corresponding thereto, decodes the information, and supplies the decoded information to the corresponding one of the display devices 4A to 4I to display the information on the screen of the corresponding display device. In this way, it is possible to display a large single image or picture by using all the display devices 4A to 4I if information supplied to the decoders 3A to 3I are enlargement information. And also the same single image can be displayed on each of the display devices 4A to 4I if information supplied to the decoders 3A to 3I are reduction information. It will be understood that there is no limitation on display manners. Therefore, it is possible to display a medium sized image by simultaneously using e.g. the display devices 4A, 4B, 4D, and 4E and the same image is displayed by each of the other display devices, i.e. a combination of the medium sized image and the small images. It is also possible that a small image is inserted after a large single image is displayed by using all the display devices. It is further possible that while a large single image is displayed on the display devices 4A to 4I, a single image is monitored by the display device l9 arranged in the controller l. A manner for converting an original data to data for an enlarged display in response to each decoder will be hereinafter explained with reference to Figs. 6 and 7. The data conversion program is started at step 60l, whereat a picture drawing command written on the floppy-disk in the form of a bit sequence is read out by the CPU l0 through the floppy disk interface l6 and stored in the work RAM l2. Then, the CPU l0 analyzes the operand of the picture drawing command, calculates logical X - Y coordinates, and obtain values of a point P (x, y) on the X - Y coordinates at step 602. Next, at step 603, enlarged coordinates are obtained on the basis of a point P′ (nx-i, my-j), wherein the coordinates are those of a (i, j) decoder for one of display devices arranged in n (in the horizontal or row direction) x m (in the vertical or column direction) matrix. The value i ranges from 0 to n-l, and the value j from 0 to m-l. At step 604, the picture drawing command is encoded by the use of P′ (nx-i, my-j). That is, the enlarged X - Y coordinates are generated as an ordinary picture drawing command, so that it is not necessary that the decoders are operated without consideration of the enlargement. An enlarged display can be obtained if the decoders are normally operated. Next, at step 605, it is judged whether or not the calculation is made for all the (i, j), that is, whether or not data to be supplied to all the decoders are converted to data for enlarged display. If the answer is no, the program proceeds to step 606 wherein the values i and j are changed and then, the above described procedure from step 603 to step 604 is repeated. If the answer at step 605 is yes, that is, when the calculation is made for all the (i, j), the program proceeds to step 607 to be terminated. Let it now assumed that data is converted for the case where an image is to be enlarged 3 times with the values m and n both being 3. Referring to Fig. 7, reference numerals D0 to D8 correspond to the decoders 3A to 3I. The values i and j respectively represent units of muximum number of pixels in the horizontal and vertical directions. For example, a unit of the muximum number of pixels in the horizontal direction may consists of 256 pixels, and that in the vertical direction 200 pixels. These values range from 0 to 2, respectively. Therefore, the decoder corresponding to D0 is represented by (0, 0); the decoder corresponding to Dl by (l, 0); the decoder corresponding to D2 by (2, 0); the decoder corresponding to D3 by (0, l); the decoder corresponding to D4 by (l, l); the decoder corresponding to D5 by (2, l); the decoder corresponding to D6 by (0, 2); the decoder corresponding to D7 by (1, 2); and the decoder corresponding to D8 by (2, 2). The coordinates of the original data P (x, y) are converted to P′ (nx-i, my-j) for the respective decoders as follows: Decoder corresponding to D0 ... P′ (3x, 3y) Decoder corresponding to Dl ... P′ (3x-l, 3y) Decoder corresponding to D2 ... P′ (3x-2, 3y) Decoder corresponding to D3 ... P′ (3x, 3y-l) Decoder corresponding to D4 ... P′ (3x-l, 3y-l) Decoder corresponding to D5 ... P′ (3x-2, 3y-l) Decoder corresponding to D6 ... P′ (3x, 3y-2) Decoder corresponding to D7 ... P′ (3x-l, 3y-2) Decoder corresponding to D8 ... P′ (3x-2, 3y-2) Therefore, the command for drawing a line from a point (x₁, y₁) to a point (x₂, y₂) corresponds to those for drawing a line from a point (3x₁, 3y₁) to a point (3x₂, 3y₂) for the decoder corresponding to D0; a line from a point (3x-l, 3y) to a point (3x₂-l, 3y₂) for the decoder corresponding to Dl; a line from a point (3x₁-2, 3y₁-2) to a point (3x₂-2, 3y₂-2) for the decoder corresponding to D8. The relationship between the ID number and the decoder (i, j) is expressed by ID = jn + i. For example, the ID number of the decoder (0, 0) is 0, that of the decoder (l, 0) is l, ... and that of the decoder (2,2) is 8. When an image is to be displayed on a plurality of display devices, bezels of the display devices propose a problem. It is desirable that even if there are bezels, an image can be displayed on a plurality of the display devices as if there are no bezels, that is, the bezels are not conspicuous. When a single image is displayed over a plurality of display devices, discrepancies or steps inevitably occur at bezels between adjacent display devices. Therefore, the image, as a whole, is unnaturally displayed. A method to solve or remove this problem will now be explained with reference to Figs. 8 and 9. The bezel correction program is started at step 80l, whereat certain coordinates written on the disk in the form of a bit sequence are read by the CPU l0 through the floppy disk interface l6 and stored in the work RAM l2. The CPU l0 analyzes the picture drawing command, calculates the logical X - Y coordinates, and obtains the coordinates of a point P (x, y) at step 802. Next, at step 803, the enlarged X - Y coordinates of a point are calculated, where a display ratio satisfies 0 ≦ α ≦ 1. The X - Y coordinates are data for a decoder (i, j) corresponding to one of the display devices formed into an n x m matrix. Then, the coordinates obtained at step 803 are shifted by in the direction of the origin to obtain coordinates at step 804. Next, at step 805 it is judged whether or not the calculation is made for all the (i, j), that is, whether or not the shifted coordinates P″ as mentioned above are calculated for all the decoders. If the answer at step 805 is no, the program proceeds to step 806 wherein the values of i and j are changed. Then, the procedure from step 802 to step 804 is repeated. On the other hand, if the answer at step 805 is yes (the above calculaiton is carried out for all the (i, j)), the program proceeds to step 807 to be terminated. In relation to the operation shown in Fig. 8, how the bezel correction is effected when an image is displayed over e.g. two adjacent display devices is explained with reference to Figs 9A and 9B. In Figs. 9A and 9B, reference numeral a designates a physical display area of a display device, b a frame including a border and bezel portions, and c a line drawn over two adjacent display devices. When the X - Y coordinates of the point P (x, y) is obtained at step 802 in Fig. 8, the point P (x, y) is displayed in the display area a of a certain display device. The point P′ on the enlarged X - Y coordinates obtained at step 803 in Fig. 8, though not shown, is displayed in a virtual enlarged display area expressed by a broken line d in Fig. 9A. Then, the virtual enlarged display area is shifted by in the direction to the origin (0, 0), as shown in Fig. 9B. The coordinates at that time are those obtained at step 804 in Fig. 8. As will be clear from Fig. 9B, the virtual display area d and the actual display area b substantially overlap with each other. In the corrected display, i.e. in Fig. 9B, the line c is displayed in a lower portion than that in Fig. 9A. However, the line c in the left display area a and that in the right display area a maintain linearity, that is, the disprepancy or step between the two adjacent display areas by the frames thereof can be prevented. Next, a procedure of assigning an ID number to each of the decoders will be explained with reference to Figs. l0 and ll. An assignment program is started at step l0l. At step l02, the decoder 3A checks whether or not a data sequence for an ID number assignment as shown in Fig. ll is transmitted from the controller l. Next, it is judged at step l03 whether or not information transmitted from the controller l is a data sequence for ID number assignment. If the answer at step l03 is no, the program proceeds to step l06 to be terminated. On the contrary, if the answer at step l03 is yes, the program proceeds to step l04 whereat the decoder 3A stores therein an ID number included in the data sequence as its own ID number and is set at its initial value. Next, at step l05, the decoder 3A increments its own ID number by l and transmits from its AUX port the incremented ID number as the ID number assigned to the next decoder, i.e. the decoder 3B. Then, the program is terminated at step l06. In the same manner as described above, the decoder 3B stores therein the ID number transmitted from the decoder 3A as its own ID number and is set at its initial value. Then, the decoder 3B increments its own ID number by l and transmits from its AUX port the incremented ID number as the ID number assigned to the next decoder 3C. The same procedure is repeated for the decoders 3D to 3I, and thereby the assignment of the ID number to all the decoders 3A to 3I is completed. Next, the method of operating the decoders in synchonism with each other, that is, the method of symultaneously operating all the decoders 3A to 3I by the synchronizing control signal generated by the controller l, will be explained with reference to Figs. l2 and l3 respectively showing the operation of the controller l and that of the decoders 3A to 3I. First, referring to Fig. l2, the operation of the controller l will be described in detail. The synchronization program for the controller l is started at step 20l. The controller l sets the synchronizing control signal outputted from the I/O interface l5 at one of the two levels, e.g. Low level at step 202. Next, at step 203, the controller l transmits all data to the decoders 3A to 3I. Then, at step 204, the controller l sets the synchronizing control signal outputted from the I/O interface l5 at the other level, e.g. High level after all the data are completely transmitted to the decoders. The program is terminated at step 205. Now, the operation of the decoders 3A to 3I is explained with reference to Fig. l3. The synchronization program for all the decoders 3A to 3I is started at step 30l. Then, each decoder receives data through its COM port at step 302 and delivers the received data through its AUX port at step 303. It is judged at step 304 whether or not the synchronizing control signal supplied from the I/O interface l5 of the controller l to the I/O interface 25 of each of the decoders is at High level. If the answer at step 304 is no, that is, the synchronizing control signal is not in High level, the program returns to step 302. On the other hand, if the answer is yes, that is, if the synchronizing control signal is at High level, the program proceeds to step 305 whereat the received data is decoded by each decoder. Next, at step 306, it is judged whether or not the data transmission is terminated. If the answer is no, the program returns to step 304. On the contrary, if the answer is yes, the program proceeds to step 307 to be terminated. It can therefore be noted that the decoders 3A to 3I receive data but do not decode them while the synchronizing control signal is at Low level and that when the synchronizing control signal becomes High level, all the decoders 3A to 3I start at the same time the decoding of the data received. When data overflow is detected by one of serially connected decoders, the decoder commands the preceding decoder to stop the outputting of the data. The procedure of this function or flow control will now be explained with reference to Figs. l4 and l5. Referring first to Fig. l4, the controller l is provided with a buffer TC for data tansmission and a buffer TR for data reception for the COM port and a buffer TA for data transmission and a buffer RA for data reception for the AUX port. The buffers TC, TR, TA, and RA are allocated on the work RAM l2, and only the transmission buffer TA and the reception buffer RA for the AUX port appear in Fig. l4. In the same manner, each decoder is provided with a transmission buffer TC and a reception buffer RC for the COM port and a transmission buffer TA and a reception buffer RA for the AUX port, all of which are allocated on the work RAM 22. The data in the transmission buffer TA for the AUX port of the controller l is transmitted to the reception buffer RC for the COM port of the decoder 3A. The data in the transmission buffer TC for the COM port of the decoder 3A is transmitted to the reception buffer RA for the AUX port of the controller l. Namely, the data are bi-directionally transmitted between the controller l and the decoder 3A. In the same manner, the data in the transmission port TA for the AUX port of the decoder 3A is transmitted to the reception buffer RC for the COM port of the decoder 3B, and the data in the transmission buffer TC for the COM port of the decoder 3B is transmitted to the reception buffer RA for the AUX port of the decoder 3A, that is, the bi-directional transmission of the data is effected also between the decoders 3A and 3B. The other decoders are constructed such that the bi-directional data transmission can be effected between respective adjacent decoders. In the construction described as above, an operation among the decoders 3A - 3C will be explained, as an example, with reference to the flow chart of Fig. l5. First, a transmission program is started at step 50l. Next, it is judged at step 502 whether or not the reception buffer RC for the COM port of the decoder 3B is full, that is, whether or not the reception buffer RC is overflowed with transmitted data. If the answer is yes at step 502, the program proceeds to step 503 whereat a transmission stop singal X off outputted to the transmission buffer TC for the COM port of the decoder 3B. The transmission stop signal X off is then received by the reception buffer RA for the AUX port of the preceding decoder 3A, so that the decoder 3A stops the transmitting of the data to the decoder 3B. If the answer at step 502 is no, that is the reception buffer RC of the decoder 3B is not full, the program jumps to step 504. Then, it is judged at step 504 whether or not the reception buffer RA for the AUX port of the decoder 3B is full. If the answer is yes, the program proceeds to step 505 whereat a transmission stop signal X off is outputted to the transmission buffer TA for the AUX port of the decoder 3B. The signal X off is then transmitted to the transmission buffer RC for the COM port of the next decoder 3C, whereby the decoder 3C stops the transmitting of the data to the decoder 3B. If the answer at the step 504 is no, that is, if the buffer RA is not full, the program jumps to step 506. At step 506, it is judged whether or not the transmission stop signal x off is outputted to the transmission buffer TC for the COM port of the decoder 3B. If the answer is yes, the program proceeds to step 507 whereat it is judged whether or not the transmission buffer RC for the COM port of the decoder 3B has a free or vacant area. If the answer at step 507 is yes, that is, if the transmission buffer RC has a vacant area, the transmission buffer TC for the COM port of the decoder 3B is supplied with a transmission resuming signal X on at step 508. The signal X on is then received by the reception buffer RA for the AUX port of the preceding decoder 3A, and thereby the decoder 3A resumes the data transmission to the decoder 3B. If the answer at step 506 or 507 is no, that is, if the transmission signal X off is not outputted or if the reception buffer RC does not have free area, the program jumps to step 509. Next, it is judged at step 509 whether or not the transmission stop signal X off is outputted to the transmission buffer TA for the AUX port of the decoder 3B. If the answer is yes, the program proceeds to step 5l0 whereat it is judged whether or not the reception buffer RA for the AUX port of the decoder 3B has free area. If the answer at step 5l0 is yes, the transmission resuming signal X on is outputted to the transmission buffer TA for the AUX port of the decoder 3B at step 5ll. The signal X on is then received by the reception buffer RC for the COM port of the next decoder 3C, whereby the decoder 3C resumes the data transmission to the decoder 3B. Now, the program proceeds to step 5l2 to be terminated. If the answer at step 509 or 5l0 is no, that is, if the transmission stop signal X off is not outputted or if the reception buffer RA does not have free area, the program jumps to step 5l2 to be terminated. The above described operation can be similarly carried out between the controller l and the decoder 3A as well as between respective two adjacent decoders. As described above, according to the present invention, the identification number is inserted in a predetermined portion of the data sequence generated by the information generating means, and the first terminal of a plurality of serially connected terminals is set at the initial value by the identification number supplied from the information generating means and produces and transmits a new identification number for the terminal at the next stage, so that each of a plurality of the serially connected terminals can be set at its initial value by the assigned identification number through substantially one transmission line, whereby the circuit construction of the system can be simplified. Also, it is not necessary to provide the information generating means with ransmission ports for every terminal but only one transmission port for the first terminal, so that it is possible to simplify the circuit configuration of the information generating means.

Claims: A multiple display system adapted to display data in a VIDEOTEX standard on a display formed of a plurality of display devices as a single picture screen, said multiple display system comprising: encoder means (1) for generating a code on the basis of internal or external data supplied thereto; a plurality of decoding means (3A - 3I); a plurality of display devices (4A - 41) provided respectively corresponding to said plurality of decoding means; and means for setting an identification number to each of said decoding means which respectively respond to corresponding identification numbers supplied thereto, process the video data received and supply said display devices with said video signals; characterized in that said encoder means (1) inserts an identification number in a predetermined portion of the data sequence transmitted to said decoding means; and each decoding means (3A - 3I) is successively arranged with the other decoding means and said encoder means; respectively extracts data with a corresponding identification number from said data sequence to convert the extracted data into said video signals which are then supplied to said display devices, and generates a transmission stop signal to the preceding decoding means, or the encoder means, respectively, when detecting an overflow state of its data receiving means.

Inventors: NAKAGAWA, YUTAKA, SUGA, RYOICHI, WATANABE, YOSHIMI
Applicants: SONY CORPORATION
Application year: 1987
Main classification: H04N5
IPC codes: H04N5, G09G5, G09G1, H04M11, G06F3