METHOD OF ASSIGNING A BOARD SLOT NUMBER

Abstract: The control system has a software prepared for a maximum system (10), where an access to a number of boards (13-18) of different junctions is made by designating the physical (11) or logical (12) slot number. The same software can be used for a lower system (20), where an access is made by the logical slot number (22) which is defined for the corresponding board in the maximum system (10). For this purpose, a conversion table is made between the physical slot number (21) and the module discrimination number (13-18) for the lower system (20), which is compared with a conversion table between the logical slot number (12) and the module discrimination number (13-18) for the maximum system (10).

Description: Technical Field The present invention relates to a method of allocating board slot numbers, and more particularly to a method of allocating board slot numbers without altering software in a computer control system which is subject to system structure variations. Background Art Generally, a computer control system uses a number of boards and may be subject to a system structure variation dependent on an object to be controlled. When the address map is required to vary by a system structure, the compatibility of software is lost even if the system structure is subordinate, and new software should be formed or software should be converted. However, the development of software requires the expenditure of considerable time and cost, and the conversion of software is not easy to perform. It is therefore necessary to have the address map unchanged even if the system structure varies. This requires an addressing process for each board when the device is assemled, but such a process is troublesome. It is customary to give board slot numbers from a back panel connector so that addressing can automatically be effected dependent on a slot position on a back panel. One solution to keep the same address map for all system structures is to use the same back panel for maximum and minimum systems. Each board is mounted on the slot corresponding to its address. However, when the difference between maximum and minimum systems is large, it would be quite wasteful if the same back panel were employed. It is an object of the present invention to provide a method of allocating board slot numbers, which will solve the aforesaid problems, does not require manual board addressing procedure, and allows a subordinate system to use the software of a maximum system without altering the software. According to the present invention, there is provided a method of allocating logical board slot numbers in a control system composed of a plurality of boards as claimed in Claim 1 According to the above method, the module of each of the boards is automatically identified and converted to a slot number in the maximum system. Therefore, the software of the maximum system can be used for a different system which has a different number of modules and a different module type. In the drawings:- FIG. 1 is a diagram showing the relationship between slot numbers and boards on back panels according to an embodiment of the present invention; FIG. 2 is a block diagram of boards in a subordinate system; FIG. 3 is a detailed block diagram of a slot number control unit 40; FIG. 4 is a timing chart of operation of a slot number loader; and FIG. 5 is a diagram showing an address map according to the embodiment of the present invention. An embodiment of the present invention will hereinafter be described in specific detail with reference to the drawings. FIG. 1 shows the relationship between slot numbers and boards on back panels according to an embodiment of the present invention. In FIG. 1, 10 show how the slot numbers and boards of a maximum system are arranged. Physical slot numbers are denoted at 11. Boards having various functions are designated by 13 through 18 and defined as follows: 13...B Basic board 14...CPU CPU boards 15...MEM Memory boards 16...AXC Axis control boards 17...VS Vision sensing board 18...NET Network board Denoted at 20 is a particular subordinate system having eight slot numbers represented by 21 as physical slot numbers. Denoted at 13 through 18 are boards having various functions like those of the maximum system. 22 indicate logical slot numbers. The logical slot numbers in the subordinate system are converted so that they will coincide with the physical slot numbers and logical slot numbers in the maximum system. Software prepared for the maximum system can operate the hardware of the subordinate system as it has the same board arrangement on the back panel as that of the hardware of the maximum system. In the subordinate system, however, the software should be designed in advance such that the CPU will not access boards which are not actually mounted. Conversion from the physical slot numbers to the logical slot numbers will be described below. FIG. 2 shows in block form the boards in the subordinate system. Denoted at 13 through 16 in FIG. 2 are the same boards as shown in FIG. 1. The basic board 13 contains a slot number loader 31 which, when the power supply is switched on, gives the physical slot numbers to the boards at respective slots. The boards 14, 15, 16 have slot number control units 40, respectively. Each slot number control unit serves to send a module identification number (described later) to the slot number loader 31 and also to convert an address accessed by a logical slot number to an actual address. The boards 14, 15, 16 also contain module identification numbers 33, 34, 35, respectively. The boards 13, 14, 15, 16 are interconnected by a bus 50. To the boards 14, 15, 16, there are connected the respective bits of data lines *D1-54, *D2-55, *D3-55, ... in corresponding relation to the physical slot numbers. More specifically, the data line *D1 is connected for the physical slot number 1, the data line *D2 is connected for the physical slot number 2, and so on. These signals are used to read out the module identification numbers of the respective boards when the power supply is turned on. The slot number control unit 40 will be described below in detail. FIG. 3 shows in detailed block form the slot number control unit 40. An address decoder 41 has an input line A0-23 supplied with 0 to 23 bits from an address bus and produces an output signal which becomes a logic "1" when a corresponding address is applied. For example, 8XXXXXH indicates a hexadecimal notation of address 24 bits, the high-order position being 8 and other positions being any desired numbers. H in the low-order position indicates the hexadecimal representation. Likewise, F0000XH indicates that five high-order digits represent a hexadecimal F0000 and the low-order digit may be any number. A slot number storage register 42 first stores a physical slot number and then a logical slot number. Comparators 43, 44 produce conincidence signals when signal data items applied thereto are the same. Denoted at 45, 46, 47 are AND gates, 48 a bus driver for issuing a module identification number to a data bus, 51 an address bus which is of 24 bits according to the embodiment, 52 a data bus which is 16 bits according to the embodiment, and 53 a control signal line for writing in and reading out data with a write signal *WR and a read signal *RD. Operation of the slot number loader 31 shown in FIG. 2 will be described with reference to the timing chart shown in FIG. 4. A clear signal *CLR in FIG. 4 serves to initially clear the entire circuit for a certain period of time when the power supply is switched on. An address bus A4-23 indicates signals from 4 to 23 bits on the address bus and controls the address bus so that its output will be FFFFFXH during a timing interval from T0 to T15. As a result, the signal FFFFFXH is of "1" from timing T0 to timing T15. An address bus A0-3 indicates signals from 0 to 3 bits on the address bus and controls the bits so that the bit will be 0 at the timing T0, 1 at the timing T1, and 2 at the timing T2. A data bus D0-15 is controlled such that the low-order bit will be 0 at the timing T0, the bit next to the low-order bit will be 0 at the timing T1, and the second bit from the low-order bit will be 0 at the timing T2. Data D1 is connected to the first slot, and data D2 is connected to the second slot. The data are given as timing signals to the 1st through 15th slots from the timing T1 through the timing T15. Since the back panel in the subordinate system has 15 or less slots, not all data up to the timing T15 may be needed in some cases. *WR indicates a control signal for writing in data. Waiting a physical slot for the board connected to the first slot on the back panel will be described below. In FIG. 3, at the timing T1, the input FFFFFXH to the gate 46 is "1" and the write signal *WR is "0". Since the data D1 is connected to the first slot, a signal *IDS is also "0". Therefore, the output from the gate 46 is "1", and the contents of the addresses A0-3 are written in the slot number register 42. At the timing T1, since the contents of the addresses A0-3 are "1", "1" is written in the slot number register 42. For the other boards, likewise, the physical slot numbers of the slots in which the boards are inserted are written in the slot number register 42. Conversion from the physical slot numbers to the logical slot numbers will now be described. After the writing of the physical slot number into the slot number register of each board has been completed, control is transferred from the basic board 13 to a predetermined CPU. The CPU reads out the module identification numbers of the respective boards, and forms tables of the physical slot numbers and the module identification numbers in a local memory in the CPU. At this time, as shown in FIG. 3, the input signal F0000XH applied to the gate 47 is "1". When the output from the slot number register 42 and the signal of the address bus A0-3 are in agreement with each other as compared by the comparator 44, the comparator 44 issues a signal "1". At the same time, the read signal *RD becomes "0", so that the module identification number is read out to the data bus through the bus driver 48. FIG. 5 shows an address map according to the present invention. The address map contains addresses 000000 through FFFFFF, and addresses 800000 through 900000 are allocated to the slots. The tables of the physical slot numbers and the module identification numbers are preset at addresses F00000 through F0000F. Correspondence tables of the logical slot numbers and the module identification numbers in the maximum system are present at addresses F00010 through F0001F. The CPU compares the tables of the subordinate system and those of the maximum system, and allocates the slot numbers, i.e., the logical slot numbers of the maximum system to the same modules of the subordinate system. Specifically, as shown in FIG. 3, when the input signal FFFFXH applied to the gate 46 becomes "1", the write signal *WR becomes "0", and the signal *IDS becomes "0", the logical slot numbers are stored in the slot number register 42 and also in the slot number registers 40 on the respective boards. Operation when the boards are acessed will be described. As shown in FIG. 5, the slots are allotted to the addresses 800000 through 900000. When the address 800000 is selected, i.e., when the input signal 8XXXXXH to the gate 45 becomes "1" and the output from the comparator 43 becomes "1" at the time the logical slot number stored in the slot number register 42 and addresses A16-19 coincide with each other in FIG. 3, the output from the gate 45 becomes "1" and a module selecting signal becomes "1" to access the units in the boards. Thus, the boards which are actually accessed are not fixed boards, but the boards corresponding to the modules which coincide with the prescribed modules in the maximum system are selectively accessed. In the above description, the physical slot numbers are converted to the logical slot numbers by a fixed CPU. However, where there are a plurality of CPUs available, such conversion may be effected after a host CPU is determined among the available CPUs. Heretofore, the selection signal *IDS for the resepctive boards has been a 4-bit signal. In the embodiment, the selection signal *IDS is a 1-bit signal. With the present invention, as described above, the modules of the respective boards are converted so that they can be accessed by the slot numbers of the modules in software of the maximum system. Consequently, the software of the maximum system can be used without being altered or converted. The present invention is therefore highly useful in promoting the development of software in a system that is subject to system structure variations. The device can be assembled simply by inserting boards which are even of one type into a back panel without having to involve a tedious manual addressing procedure or the like. This is advantageous since a board replacement process is facilitated upon maintenance.

Claims: A method of allocating logical board slot numbers in a control system composed of a plurality of boards, the system including a basic board (13) comprising a slot number loader (31) and at least one other board (14,15,16) including a slot number control unit (40) and a module identification number (33,34,35), the method comprising the steps of: assigning by said slot number loader (31) a physical slot number to each of said other boards (14,15,16); reading out the module identification number of each of said other boards (14,15,16) and forming a table of physical slot numbers and the corresponding module identification numbers; assigning a logical slot number to each of said other boards (14,15,16) according to the module identification number of said board on the basis of a logical slot number pre-assigned to that module identification number in a maximal system; and, storing the respective logical board slot number to the slot number control unit (40) of each of said other boards (14,15,16) in stead of the physical slot number. A method according to claim 1 including the step of: generating timing and data signals by the slot number loader (31) to assign said physical slot number to each of said other boards (14,15,16) in sequence. A method according to claim 1 or claim 2, wherein a host CPU is determined from a plurality of CPUs, the logical slot number being determined in said host CPU.

Inventors: KINOSHITA JIRO, YONEKURA MIKIO, KINOSHITA, JIRO, YONEKURA, MIKIO
Applicants: FANUC LTD, FANUC LTD.
Application year: 1987
Main classification: G06F13
IPC codes: G06F12, G06F13