INTEGRATED LIGHT-TRIGGERED AND LIGHT-QUENCHED STATIC INDUCTION THYRISTOR AND MAKING METHOD THEREOF

Abstract: An integrated light-triggered and light-quenched static induction thyristor and fabrication process thereof adapted in such a manner that an integrated SIPT operates in the normal mode in order to enhance current gain, tail current generated at the light-quenching time is reduced in order to enhance turn-off gain, and an buried-gate type of light-triggered static induction thyristor and a photo­ darlington circuit composed of a first and second static induction phototransistors are integrated on a high-­ resistivity substrate in order to permit manufacturing said thyristor compact as a whole in facilitated processes.

Description: The present invention relates to a formation and making method of an integrated light-triggered and light-quenched static induction thyristor (hereinafter abbreviated as LTQSI thyristor) composed by integrating a light-triggered static induction thyristor (hereinafter abbreviated as LTSI thyristor) and static induction phototransistors (hereinafter abbreviated as SIPTs) or a photodarlington circuit including a light-triggered static induction thyristor and static induction phototransistors. Formational examples of LTQSI thyristors have already been proposed in EP-A-0 158 186 (by Japanese Patent Preliminary Publication Nos. Sho 60-198779 and Sho 61-54668 whereas and a making method thereof has been disclosed by Japanese Patent Preliminary Publication No. Sho 62-11470). The LTQSI thyristors proposed by these patents, however, have a drawback that the SIPT thereof has a current gain level lower than that obtainable by the SIPT operated in the normal mode since the former is operated in the inverse mode when quenched by light. A primary object of the present invention is therefore to provide an integrated light-triggered and light-quenched static induction thyristor including integrated SIPTs so adapted as to operate in the normal mode for enhancing the current gain level, and a making method thereof. Another object of the present invention is to provide an integrated light-triggered and light-quenched static induction thyristor so adapted as to have a favorable light-quenched characteristic and reduce the tail current at the time of light quenching for the purpose of enhancing the turn-off gain, and a making method thereof. A third object of the present invention is to provide an integrated light-triggered and light-quenched static induction thyristor manufacturable relatively easily and having very high performance regardless of its compact design, and a making method thereof. According to the present invention, these objects can be accomplished by adopting a formation electrically isolating with a high breakdown voltage the buried-gate regions of the LTSI thyristor from the buried layer region (drain region) to be used as one of the main electrodes of the SIPTs, finding a formation to integrate a photodarlington circuit using the SIPT and adopting an anode shortening composition. The object of the invention is obtained by an integrated light-triggered and light-quenched static induction thyristor as characterised in claim 1 and by its fabrication process as characterised in claim 18. The integrated LTQSI thyristor according to the present invention is utilized effectively for converters and similar devices not only of medium and low electric power but also of high electric power since said thyristor is capable of performing DC-AC conversion of high power at high speed and with high efficiency simply by light triggering pulses and light quenching pulses, and isolating the control circuit completely from high-power circuit. These and other objects as well as the features and the advantages of the present invention will be apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. Figs. 1A and 1B are a sectional view and a top view illustrating a first embodiment of the integrated LTQSI thyristor according to the present invention: Figs. 1C through 1H are sectional views illustrating other embodiments different from one another of the integrated LTQSI thyristor according to the present invention: Fig. 1I is a circuit diagram of the integrated LTQSI thyristor according to the present invention; Figs. 2A through 2H are schematic diagrams illustrating an example of manufacturing processes of the integrated LTQSI thyristor according to the present invention; Fig. 3A is a photograph of an oscillogram illustrating the forward blocking characteristic of the LTSI thyristor portion of the integrated LTQSI thyristor manufactured according to the present invention; Figs. 3B and 3C are photographs of oscillograms illustrating the static characteristics of the integrated main SIPT; Figs. 3D and 3E are photographs of oscillograms illustrating the static characteristics of the integrated SIPT for amplification (auxiliary SIPT); Fig. 3F is a photograph of an oscillogram illustrating optical switching waveform of the fabricated 1000 V - 10 A class integrated LTQSI thyristor according to the present invention; Fig. 4 is a diagram illustrating relationship among turn-off time, turn-off gate current, turn-off gain and anode current of the fabricated 1000 V - 10 A class integrated LTQSI thyristor according to the present invention; Fig. 5 is a diagram illustrating spectral response characteristics of portions of the fabricated integrated LTQSI thyristor according to the present invention; and Figs. 6A and 6B are a sectional view and top view illustrating another embodiment of the integrated LTQSI thyristor according to the present invention. Now, referring to the accompanying drawings, the preferred embodiments of the present invention will be described in details below: A structure of the integrated LTQSI thyristor according to the present invention is illustrated as the Embodiment 1 in Figs. 1A and 1B: the former being a sectional view and the latter being a surface structural view. The integrated LTQSI thyristor according to the present invention consists of a buried-gate type of LTSI thyristor having anode-emitter shorted structure and a planar gate type of the p channel SIPT having a photodarlington structure: said LTSI thyristor and SIPT being electrically isolated by n⁺ high impurity concentration region 131 between a first groove 991 surrounding along the circumference of said LTSI thyristor and second groove 992 surrounding along the circumference of said SIPT, and mutually connected by the two-layered aluminum wiring technique. The LTSI thyristor is composed of n⁺ cathode regions 101, n⁻ high-resistivity regions 102 and 103, p⁺ anode regions 104, n⁺ emitter regions 105, p⁺ gate regions 106, cathode electrodes 107, anode electrodes 108 and gate electrodes 109. The p⁺ gate region is formed in a stripe or mesh-like structure and connected on the circumference thereof to the gate electrode 109 at the bottom of said first groove 991. The n⁻ high-resistivity region located between the p⁺ gate regions is a channel region into which electrons are to be injected from the n⁺ cathode region, and is kept in depletion state due to the diffusion potential between the p⁺ gate region and the n⁻ high-resistivity region or the reverse bias voltage applied to the gate electrode 109. Potential in the channel region is controlled by the potential of the p⁺ gate region in the capacitive-coupled mode. Width, length and impurity concentration of the channel are the important factors for determining the forward blocking characteristic, light-triggering and light-quenching characteristics of the LTSI thyristor. The p⁺ anode regions 104 and the n⁺ emitter regions 105 are arranged alternately, the n⁺ emitter region 105 being shallower than the p⁺ anode region 104, the latter being formed right under the p⁺ gate regions 106, whereas the former being right under the channel regions. In the LTSI thyristor of this structure, the electrons disappear from the front surface of the p⁺ anode region at the time of the turn-off operation since they flow to the n⁺ emitter region. Therefore, the device structure makes it possible to reduce the tailing time and realize high speed turn-off operation. Said structure makes it possible also to enhance the turn-off current gain (ratio between the anode current and turn-off peak gate current). Further, the adoption of the n⁺ emitter structure results in reduction of hole injection efficiency from the anode region 104, however, such adoption causes no substantial reduction of the light triggering sensitivity since the gate electrode 109 has the SIT structure and electron injection efficiency from the cathode region 101 is very high in the LTSI thyristor. Though layout of the p⁺ anode regions and n⁺ emitter regions is not limited to the manner described above, distance as measured from one n⁺ emitter region to another n⁺ emitter region nearest thereto should preferably be not longer than twice the diffusion length of the stored electrons (2L n ). Furthermore, in order to increase the value of the forward blocking voltage of the LTSI thyristor, a mesa region is provided around the gate electrode 109, an n⁺ diffused high impurity concentration region for isolation 131 is formed and a metal electrode 132 is arranged. Distance between the gate electrode 109 and said mesa region should be at least equal to the distance between the p⁺ gate region 106 and the p⁺ anode region 104. In this formation, potential in the n⁺ high impurity concentration region 131 is nearly equal to that in the p⁺ anode region 104, and a depletion layer is formed from the p⁺ gate region 106 toward the mesa region. As a result, concentration of electric field on the device surface can be moderated and forward blocking voltage can be increased. Formed in the cathode electrode 107 is a window for enhancing aperture efficiency for the triggering light. The p channel SIPT consists of the main SIPT including p⁺ source regions 111, n⁻ high-resistivity regions 112, a p⁺ drain region 113, n⁺ gate regions 114, a p⁺ source polysilicon layer 115, source electrodes 116, drain electrodes 117 at the bottom of said second groove 992 and gate electrodes 118, and of an auxiliary SIPT including p⁺ source regions 121, n⁻ high-resistivity regions 122, a p⁺ drain region 113 used commonly for the main SIPT, n⁺ gate regions 124, a p⁺ source polysilicon layer 125, source electrodes 126, drain electrodes 117 in said second groove 992 and gate electrodes 128, an aperture formed between said second gate electrode 128 and said second source electrode 126, and said p channel SIPTS being connected each other through two wires; the source electrodes 126 of the auxiliary SIPT and gate electrodes 118 of the main SIPT are connected through the first electrode wiring (142), source electrodes 116 of the main SIPT and gate electrodes 109 of the LTSI thyristor are connected through the second electrode wiring (143). In Fig. 1A, the reference numeral 141 represents an intermediate insulating layer, whereas the reference numerals 142 and 143 designate metal wires in the second layer. Formed right under the p⁺ drain region 113 are n⁺ regions 151. By designing the photosensitive element for light quenching as a photodarlington type of the SIPTs, it is possible to turn off a high current by light. The quenching light is used for irradiating the auxiliary SIPT and may penetrate deeper than the p⁺ drain region depending on wavelength thereof. In case where the p⁺ regions are formed right under the p⁺ drain region, electrons, among the electron-hole pairs generated by the quenching light penetrating deeper than the p⁺ drain region, are accumulated on the front surface of the p⁺ anode region 104, thereby causing injection of the holes from the anode regions 104 and turning on the pip photodiode consisting of the p⁺ drain region 113, n⁻ high-resistance regions 103 and p⁺ anode regions. In order to prevent this condition, the n⁺ regions 151 are arranged right under the p⁺ drain region to form a p⁺ in⁺ diode and optical gain is limited below 1 accordingly. Arranged around the p⁺ drain region 113 is the groove 992 and high impurity concentration region 131 for electrically isolating the p⁺ gate regions 106 of the LTSI thyristor from the p⁺ drain region 113 of the p channel SIPT. In Fig. 1B illustrating the surface structure of the device according to the present invention, the reference numeral 107 represents cathode electrodes of the LTSI thyristor, the reference numeral 109 designates gate electrodes of the LTSI thyristor in a bottom of a first groove 991, the reference numeral 116 denotes source electrodes of the main SIPT, the reference numeral 118 represents gate electrodes of the main SIPT, the reference numeral 117 designates drain electrodes of the SIPT in a second groove 992, the reference numeral 126 denotes source electrodes of the auxiliary SIPT, the reference numeral 128 represents gate electrodes of the auxiliary SIPT, the reference numeral 142 designates a metal wire in the second layer for connecting the source electrodes of the auxiliary SIPT to the gate electrodes 118 of the main SIPT and the reference numeral 143 denotes a metal wire in the second layer for connecting the source electrodes of the main SIPT to the gate electrodes 109 of the LTSI thyristor. Now, referring to Fig. 1C, descriptions will be made on the structure of the Embodiment 2 of the integrated LTQSI thyristor. In Fig. 1C wherein the parts similar to those shown in Fig. 1A are represented by the same reference numerals as those used in Fig. 1A, the integrated LTQSI thyristor consists of an integrated LTSI thyristor having no anode-emitter shortening structure and an integrated planar-gate type of p channel SIPT of the photodarlington structure for quenching. As shown in Fig. 1C, a p⁺ diffused layer 104' common to the anode regions of said LTSI thyristor is formed also right under the p⁺ drain region of the SIPT. Then, referring to Fig. 1D, the structure of the Embodiment 3 of the integrated LTQSI thyristor according to the present invention will be described. In Fig. 1D wherein the parts similar to those shown in Fig. 1A are designated by the same reference numerals as those used in Fig. 1A, the integrated LTQSI thyristor consists of an LTSI thyristor adopting an n buffer layer 181 and a planar type of p channel SIPT of the darlington structure for quenching. This formation enables to enhance the forward blocking voltage of the LTSI thyristor by adopting the n buffer layer 181. Referring to Fig. 1E the structure of the Embodiment 4 of the integrated LTQSI thyristor according to the present invention will be explained below. In Fig. 1E wherein the parts similar to those shown in Fig. 1A are denoted by the same reference numerals as those used in Fig. 1A, the structure on the first main surface or the anode side of the LTSI thyristor has the n⁺ emitter regions 105 right under the n⁺ cathode regions 101 and the p⁺ anode regions 152 in the other area, and is characterized in that the n⁺ regions 151 are formed right under the p⁺ drain region 113 of the SIPT. This structure allows attemps to enhance the turn-off speed and turn-off gain. With reference to Fig. 1F, the structure will be described on the Embodiment 5 of the integrated LTQSI thyristor according to the present invention. In Fig. 1F wherein the parts similar to those shown in Fig. 1A are represented by the same reference numerals used in Fig. 1A, the formation is characterized in that uniform p⁺ anode regions are formed right under the LTSI thyristor and that n⁺ regions 182 having a diffusion junction depth of the similar degree to that of the p⁺ anode regions 104 are provided in the other area. This structure has advantages to enable to reduce (minimize) the forward voltage drop in the LTSI thyristor portion and to simplify composition of the LTQSI thyristor having the anode shortening structure. Referring to Fig. 1G, the formation of the Embodiment 6 of the integrated LTQSI thyristor according to the present invention will be explained below. In Fig 1G wherein the parts similar to those shown in Fig. 1A are designated by the same reference numerals used in Fig. 1A, and n buffer layer 181 is adopted in the formation illustrated in Fig. 1F. The adoption of this n buffer layer 181 enables the LTQSI thyristor to have a higher blocking voltage and serves to prevent erroneous operation of the SIPT the n⁺ anode layer 182 allows the underside anode surface of the SIPT group to be of the p-i-n structure. With reference to Fig. 1H, description will be made below on the structure of the Embodiment 7 of the integrated LTQSI thyristor according to the present invention. In Fig. 1H wherein the parts equivalent to those shown in Fig. 1A are denoted by the same reference numerals as those used in Fig. 1A, the structure is characterized in that a two-layer structure of p⁺ anode regions 183 and n emitter regions 184 are formed on the anode side of the LTSI thyristor, and that n regions 151 are provided right under the p⁺ drain region 113 of the SIPT. In this case, hole injection efficiency from the anode p⁺ layer 183 is controllable depending on diffused junction depth of the n emitter regions 184 and the tailing current can be reduced. Fig. 1I shows a schematic circuit diagram of the integrated LTQSI thyristor having the formations illustrated in Figs. 1A through 1H. In Fig. 1I, the reference symbols A and K represent the anode and cathode of the LTSI thyristor respectively, the reference symbols G1 and S1 designate the gate and source of the main SIPT, the reference symbols G2 and S2 denote the gate and source of the auxiliary SIPT for amplification, and the reference symbol D represents the drain used commonly for the main SIPT and auxiliary SIPT for amplification. The integrated LTQSI thyristor according to the present invention consists of the LTSI thyristor and the photodarlington type of SIPT. The gate of the LTSI thyristor is connected to the source S1 of the main SIPT composing the photodarlington type of SIPT. The photodarlington type of SIPT consists of the main SIPT and the auxiliary SIPT for amplification; the source of the auxiliary SIPT being connected to the gate of the main SIPT whereas the drain D being used commonly for the main SIPT and the auxiliary SIPT. Now, description will be made on the operations of the Embodiment 1 illustrated as the Embodiment 1 of the integrated LTQSI thyristor according to the present invention. When the surface of the LTSI thyristor is irradiated with the triggering light pulse LT in a state where both the LTSI thryristor and the SIPT are turned off, electron-hole pairs are generated in the n⁻ high-resistivity layer mainly between the p⁺ buried-gate region 106 and the p⁺ anode region 104 by the light penetrating into the LTSI thyristor. Electrons among the generated electron-hole pairs are accumulated in the second base formed in the junction between the p⁺ anode region 104 and the n⁻ high-resistivity layer 103 (or n buffer layer 181), whereas the holes are accumulated into the p⁺ gate regions 106. By the holes accumulated in the p⁺ gate regions 106 as described above, potential of the p⁺ gate regions relative to the electrons in the cathode region 101 is lowered, and along with the lowering, potential at the intrinsic gate point as the saddle point of the potential generated in the n⁻ channel between the p⁺ gate regions 106 and 106 relative to the electrons in the cathode region 101 is lowered, thereby increasing injection of electrons from the n⁺ cathode regions 101. In the similar way, by the electrons accumulated in the second base, potential of the second base relative to the holes in the anode region 104 is lowered and injection of holes from the anode region 104 is increased. The injected electrons and holes are accumulated into the second base and the p⁺ gate regions 106, respectively, the potential barrier in the second base for holes and the potential barrier at the intrinsic gate point for electrons are lowered, and injection of the carriers is increased, finally turning on the LTSI thyristor. Once turned on, the LTSI thyristor is kept in the turned-on condition even after the triggering light pulses are turned off. When the auxiliary SIPT in the darlington type of SIPT is irradiated with the quenching light pulses LQ at the next step, the auxiliary SIPT is turned on by the light penetrating thereinto to drive the main SIPT. When the main SIPT is turned on, the holes so far accumulated in the p⁺ gate regions 106 of the LTSI thyristor and the holes injected from the p⁺ anode region 104 are flown out through the main SIPT. Accordingly, the potential of the p⁺ gate region 106 relative to the electrons in the cathode region 101 and that at the intrinsic gate point relative to the electrons in the cathode region 101 are increased, thereby shutting off the injection of electrons from the n⁺ cathode region 101. The electrons accumulated in the second base are also reduced due to the recombination with holes or the diffusion into the p⁺ anode region 104, thereby shutting off the injection of holes from the p⁺ anode region 104 and turning off the LTSI thyristor. The light triggering and light quenching are performed through the processes described above. Now, a fabrication process of the integrated LTQSI thyristor according to the present invention will be described below. Figs. 2A through 2H show sectional views visualizing the fabrication process of the integrated LTQSI thyristor having the formation illustrated in Fig. 1A. As shown in Fig. 2A, used as the substrate is an n⁻ silicon wafer 103 having, for example, resistivity p≃250 to 500 Ω·cm, thickness on the order of 350 µm and orientation of crystal face (111). Resistivity and thickness of the silicon wafer are determined depending on the blocking voltage of the LTSI thyristor to be manufactured. After oxidation of the n⁻ silicon wafer, boron B is thermally diffused selectively for forming the p⁺ anode region 104 of the LTSI thyristor, p⁺ region 152 right under the n⁺ isolation region, p⁺ gate region 106 of the LTSI thyristor and drain region 113 of the SIPTS. Impurity concentration N s and diffusion depth X j in the surface of the p⁺ gate region of the LTSI thyristor which are the factors, together with the pitch between two neighboring p⁺ gate regions 106, to determine characteristics of the LTSI thyristor are controlled, for example, so as to be N s = 1 x 10²⁰ to 10²¹ atm/cm³ and X j = 10 to 15 µm. Formation of the p⁺ anode regions 104 and the p⁺ regions 152 of the LTSI thyristor may be performed simultaneously, with or separately from the formation of the p⁺ gate regins 106 of the LTSI thyristor and the p⁺ drain region 113 of the SIPT. Then, an n⁻ epitaxial growth layer 207 corresponding to the n⁻ channel region of the SIPT are formed between the p⁺ gate regions and n⁺ cathode region of the LTSI thyristor as shown in Fig. 2B. Since the epitaxial growth of silicon is performed at a temperature around 1100°C, impurities are automatically doped into the epitaxial growth layer 207 from the p⁺ gate regions 106 of the LTSI thyristor and the p⁺ drain region 113 of the SIPT. If an n⁻ layer having low impurity density is grown due to this phenomenon, the epitaxial growth layer will be of the p type and the gates of the p⁺ gate regions will be connected to one another through the p type of areas, thereby hindering an n⁻ channel from being formed. In order to solve this problem, a thin n layer having a relatively high impurity concentration of n type is grown first, and then an n⁻ layer is grown. For example, leaving an oxide film 206 on the anode side of the substrate, an n layer having an impurity density ≃2 x 10¹⁶ cm⁻³ and thickness ≃1 µm is formed by growing for 1.5 minutes with SiCl₄ + POCl₃ + H₂ at 1100°C using tetrachlorosilane SiCl₄, hydrogen H₂ as the carrier gas and POCl₃ as an impurity source, and thereafter H₂ is flowed for five minutes to purge POCl₃ from the reaction tube. Then, growth is performed for 27 minutes with SiCl₄ + H₂ to form an n⁻ layer having an impurity density ≃1 to 3 x 10¹⁴ cm⁻³ and thickness ≃10 to 20 µm. After oxidizing this layer once again, phosphorus (P) is thermally diffused selectively to form the n⁺ cathode regions 101 and n⁺ emitter regions 105 of the LTSI thyristor, the n⁺ gate regions 114 and n⁺ high impurity concentration regions 131 of the SIPT, and the n⁺ regions 151 right under the p⁺ drain region 113 of the SIPT by the known processes using the oxide film 206 as a mask as shown in Fig. 2C. Pitch between two neighboring n⁺ gate regions of the SIPT and diffusion depth X j are determined depending on characteristics of the SIPT. Diffusion depth X j is, for example, on the order of 3 to 7 µm. Then, the p⁺ source regions 111, 121 of the SIPT are formed. From viewpoint of characteristics of the SIPT, the p⁺ source regions 111, 121 should preferably have a shallow diffusion depth X j and high doping concentration. If aluminium is evaporation coated as an electrode directly to this thin diffusion layer, aluminium will pierce through the diffusion layer with high possibility, constituting a cause of degradation in yield rate. In order to solve this problem, the p⁺ source regions 111, 121 should be formed by using a CVD polysilicon doped with boron B as a diffusion source or thermally diffusing boron B over the non-doped CVD polysilicon, and the polysilicon layer 115, 125 should be used as a buffer layer for the metal electrodes and p⁺ source region 111, 121. For example, a non-doped polysilicon layer about 3500 Å can be formed by growth for 17 minutes by using the system of SiCl₄ + H₂. Thereafter, thin p⁺ regions can be formed by deposition of boron B at 1000°C for 20 minutes and then a diffusion process at 1100°C for 15 minutes. Then, after carrying out the known masking process, the CVD polysilicon layer 115, 125 is subjected to patterning by plasma etching. Then, after opening the contact holes for connecting the n⁺ cathode regions 101 of the LTSI thyristor, and the n⁺ gate regions 114, 124 and the n⁺ high impurity concentration regions 131 of the SIPT to the metal electrodes as shown in Fig. 2E, a silicon nitride film 215 is deposited. This silicon nitride film 215 is used as a masking material for silicon etching to make grooves 991 and 992 and to provide electrodes to the p⁺ gate regions 106 of the LTSI thyristor and the p⁺ drain region 113 of the SIPT; this groove isolates the n⁻ layer 216, the p⁺ gate regions 106 and the n⁺ cathode regions 101 of the LTSI thyristor from the n⁻ layer 112, 122 between the p⁺ source regions 111, 121 and the p⁺ drain region 113 of the SIPT. The silicon nitride film 215 can be deposited to a thickness of about 1300 Å by growth, for example, at 780°C for 15 minutes. Requirements as characteristics of the masking material for this process step are a property to permit low enough temperature not to change the impurity profile in the preceding process steps and a high etching selection ratio relative to silicon, and CVDSnO₂, CVDSiO₂ or another similar material is utilizable as the masking material. After the masking process, the silicon nitride film 215 is subjected to patterning by plasma etching. Then, silicon is etched by using the silicon nitride film as a mask, and the p⁺ gate regions 106 of the LTSI thyristor and portion of the p⁺ drain region 113 of the SIPT are exposed at the bottom of etched grooves as shown in Fig. 2E. The silicon etching is performed by the plasma etching method or chemical wet etching method. Whether or not the p⁺ gate regions 106 and p⁺ drain region 113 have been exposed can be monitored through measurement by the four probes method, electrical conduction type of judgment with hot probe or the similar technique. Silicon is etched at a rate of about 10 µm/min by using, for example, an etching solution of HF: NHO₃: CH₃COOH = 15: 100: 5. Impurity density in the surfaces of the p⁺ regions 106 and 113 may be lowered depending on controllability of the etching, etching depth in the wafer surface, etc., thereby resulting in increase of resistance due to contact with the metal electrodes, and resistance of the exposed portions of the p⁺ regions 106 and 113. Such increase of resistance will cause degradation of switching characteristic of the LTSI thyristor. In order to solve the above-mentioned problem, boron B is diffused by ion implantation into the exposed portions on the surfaces of the p⁺ regions 106 and 113 after the silicon etching. For example, aluminium is used as a masking material. A sheet resistance of several ohms/□ is obtainable by the ion implantation of B having a dosage of 3 x 10¹⁵ ions/cm² under an accelerating voltage of 50 kV, removing the maksing aluminium and silicon nitride film 215, and annealing at 950°C for 20 minutes. This process step can also be carried out by thermal diffusion using a CVD nitride film, CVDSnO₂ or CVDSiO₂ as the masking material (see Fig. 2F). Then, both the surfaces of the semiconductor substrate are evaporation coated with aluminium as the electrodes shown in Fig. 2G and subjected to patterning. The aluminium electrode masking process step need not be repeated so far as the n⁻ layer 216 between the p⁺ gate regions 106 and n⁺ cathode regions 101 of the LTSI thyristor as well as the n⁻ layer 112, 122 between the p⁺ source regions 111, 121 and p⁺ drain region 113 of the SIPT is relatively thin, and the pitch between the two neighboring aluminium electrode patterns of the SIPT is relatively wide. However, when said layer 112, 122 is thick or the aluminium electrode patterns are thin and arranged at a narrow pitch, the patterning of the cathode electrodes 107 of the LTSI thyristor, the source electrodes 116, 126 and gate electrodes 118, 128 of the SIPTs, and the electrodes 113 on the n⁺ isolation regions should be carried out separately from the patterning of the gate electrodes 109 of the LTSI thyristor and the drain electrodes 117 of the SIPTs. Further, there is available a method for thickening the electrodes of the LTSI thyristor, allowing a high current and thinning the electrodes of the SIPTs having very thin patterns. For this purpose, evaporation coating of aluminium should be performed twice separately. Futhermore, finer electrodes of the SIPTs can be patterned by flattening or filling the silicon-etched groove portions with a resisting material such as CVDSiO₂ film or polyimide type of resin before the second layer aluminium electrode masking process. Then, wiring 142, 143 to the first layer electrodes for the second layer is carried out on the upper side of the films 141 for insulation between the layers as shown in Fig. 2H. CVDSiO₂ or a polyimide type of resin is used as the intermediate insulation films 141. After depositing or coating the intermediate insulation film 141, patterning is carried out to expose a contact hole portion of each electrode contact hole opening and then aluminium is evaporation coated for the second layer. Patterning of the second layer aluminium is carried out for wiring the source electrodes of the auxiliary SIPT to the gate electrodes of the main SIPT, and the source electrodes of the main SIPT to the gate electrodes of the LTSI thyristor respectively through said contact hole portions. By the fabrication process step described above, it is possible to obtain the integrated LTQSI thyristor having the structure shown in Fig. 1A through 12 masking processes and with relatively easy process techniques. Next, fabrication process step for the integrated LTQSI thyristor having the structure shown in Fig. 1C will be described in the following. Since it is, sufficient to perform uniform p⁺ diffusion on the anode side for this formation, the masking process is unnecessary on the anode side before diffusion of boron B for forming the p⁺ anode regions 104' and p⁺ gate regions 106 of the LTSI thyristor as well as the p⁺ drain region of the SIPT. Since the n⁺ emitter regions 105 shown in Fig. 1A need not be formed either, it is unnecessary to carry out the masking processes for forming the n⁺ cathode regions 101 of the LTSI thyristor, and the n⁺ gate regions 114, 124 and n⁺ isolation regions 131 of the SIPT before diffusion of phosphorus P. The other processes are similar to those described with reference to Figs. 2A through 2H. This formation allows to omit two masking processes. Then, descriptions will be made on the fabrication process of the integrated LTQSI thyristor according to the present invention having the structure illustrated in Fig. 1D. Before diffusing p⁺ on the anode side, for forming the n buffer layer 181, deposition, ion implantation or diffusion of boron B is carried out. The subsequent process steps are similar to those for the manufacturing processes for the structure shown in Fig. 1C. In addition, after forming the n buffer layer 181 on the n⁻ substrate, the p⁺ anode regions 104 can be formed by bringing the p⁺ substrate into close contact with the n buffer layer 181, cementing said substrate through heat treatment and mechanically cutting the substrate into a thin plate. The integrated LTQSI thyristor according to the present invention having the structure shown in Fig. 1E is manufactured by the method described below. The manufacturing processes of this formation are the same as those described with reference to Figs. 2A through 2H, except for the shapes of the masks used for forming the anode regions and the n⁺ emitter regions. The integrated LTQSI thyristor according to the present invention having the structure shown in Fig. 1F can be fabricated by the processes explained below. Since the n⁺ region 182 has a diffusion depth is larger than those of the n⁺ cathode regions 101 of the LTSI and n⁺ gate regions 114 and 124 of the SIPT in this case, it is necessary to carry out the diffusion for the n⁺ region 182 separately from that for the n⁺ cathode regions 101 of the LTSI and the n⁺ gate regions 114, 124 of the SIPT. When boron B and phosphorus P are used as the p type of impurity and n type of impurity respectively, diffusion of boron B should be carried out first for forming the p⁺ anode regions 104, p⁺ gate regions 106 and p⁺ drain region 113, and then phosphorus P should be diffused for forming the n⁺ region 182, taking into consideration the fact that the diffusion coefficient of boron B is smaller than that of phosphorus P. The processes on and after the epitaxial growth of the n⁻ layer are the same as those for the LTQSI thyristor having the structure shown in Fig. 1C. Explanation will be made on the fabrication process of the integrated LTQSI thyristor having the formation illustrated in Fig. 1G. In this case, diffusion of phosphorus P is carried out first to form the n buffer layer 181. The subsequent processes are quite the same as those for the integrated LTQSI thyristor having the formation shown in Fig. 1F. Finally, fabrication process for the integrated LTQSI thyristor according to the present invention illustrated in Fig. 1H will be described. The fabrication processes of the integrated LTQSI thyristor having the structure shown in Fig. 1H are the same as those explained with reference to Figs. 2A through 2H, except for the shape of the mask for forming the anode regions and that of the mask for forming the n emitter regions. In the fabrication processes of the integrated LTQSI thyristor according to the present invention, it is effective, for reducing the tailing current at the turn-off time and increasing the turn-off gain, to diffuse a heavy metal such as gold or platinum into the second base region of the LTSI thyristor and/or irradiate said LTQSI thyristor with a radiation such as electron beam, gamma ray, beta ray or proton etc. under a condition that powerloss of the LTQSI thyristor is not increased so much as a suitable operating frequency used. The integrated light-triggered and light-quenched static induction thyristor according to the present invention enables to increase the value of the turn-off gain G off since said thyristor permits reducing the tail current at the light-quenching time. Accordingly, it is possible to limit the area occupied by the light-quenched SIPT or SIPT darlington circuit portion to about 1/G off relative to the entire chip area. In a case where 100 A is to be quenched by light, for example, on an assumption of and G off = 10, the area occupied by the photodarlington circuit portion composed of the main SIPT and auxiliary SIPT may be about 11% of the area of the light-triggered SI thyristor. For an element on the order of 100A, the entire chip has an area of about 18 mm⊘. Needless to say, higher speed operations can be realized by setting turn-off gain at 2 to 3 and designing the SIPT portion so as to have a larger area. It is therefore possible to design in such a manner that the area occupied by the light-quenched SIPT or SIPT darlington circuit portion is smaller than the light-triggered SI thyristor. As for the light triggered pulse (LT) and light quenching pulse (LQ), it is desirable to select light sources having wavelengths in the vicinity of wavelengths λ T and λ Q which give the peaks of the spectral response of the light-triggered SI thyristor and SIPT respectively. For example, λ Q and λ T will be selected on the order of 780 nm and 950 nm respectively. Alternately, it is possible to mount an infrared filter having a cut-off band between λ Q and λ T over SIPT portion as shown in Fig. 1A. Now, an example of the characteristics will be described on the Embodiment 1 shown in Figs. 1A and 1B which has the most fundamental structure among the embodiments explained above. An element having a forward blocking voltage of 1000 V and a rated forward current of 10 A was fabricated. The LTSI thyristor has an area of 5.34 x 3.92 mm², length of unit channel on the mask of 304 µm, number of channels of 777, pitch between two neighboring gate regions of 29 µm, width of the diffusion window of the p⁺ gate region of 5 µm, and aperture efficiency for incident light of 33.2%. On the other hand, the main SIPT in the quenching photodarlington type of SIPT had an area of 2.16 x 3.56 mm², length of the unit source region of 1219 µm, number of the source regions of 174, pitch between two neighboring n⁺ gate regions of 10 µm, width of the diffusion window for the n⁺ gate region of 15 µm and aperture efficiency for incident light of 19.8%. Further, the SIPT for amplification had an area of 0.53 x 1.68 mm², length of the unit source region of 1281.5 µm, number of the source regions of 21, pitch between two neighboring n⁺ gate regions of 10 µm, width of the diffusion window for the n⁺ gate region of 15 µm, and aperture efficiency for incident light of 39.5%. Figs. 3A through 3F present photographs of oscillograms illustrating the static characteristics of the integrated LTQSI thyristor fabricated by the fabrication process according to the present invention. Fig. 3A shows the forward blocking characteristic of the LTSI thyristor. Speaking concretely, the LTSI thyristor has the normally-on type of characteristic and blocks an anode voltage V AK = 1000 V at a gate bias voltage V GK = -3 V. Voltage amplification factor is µ ≒ 330. Figs. 3B and 3C illustrate the drain current I DS - drain voltage V DS characteristic of the main SIPT in the quenching photodarlington type of p channel SIPT. This element has an area of 2.16 x 1.78 mm². Fig. 3B shows the I DS - V DS characteristic in the low current region. Fig. 3C shows the I DS - V DS characteristic in the high current region. The LTQSI thyristor blocks about 50 V at a gate bias voltage V GS = 0 V. Further, said LTQSI thyristor is capable of flowing a drain current I DS = -600 mA at a gate current I GS = -50 mA. Figs. 3D and 3E show the drain current I D - drain voltage V D characteristic of the auxiliary SIPT (for amplification) in the quenching photodarlington type of p channel SIPT. Fig. 3D illustrates the I DS - V DS characteristic in a low current region, whereas Fig. 3E illustrates the I DS - V DS characteristic in the high current region. That is to say, the SIPT can block a drain voltage V DS = -20 V at a gate bias voltage V GS = 0 V and V DS = -120 V at V GS = +5.0 V respectively as apparent from Fig. 3D. Further, as is clear from Fig. 3E, said SIPT is capable of flowing I DS = -300 mA at a gate current I GS = -50 mA. Fig. 3F is a photograph of an oscillogram illustrating the light switching waveform of an integrated LTQSI thyristor of the 1000 V - 10 A class fabricated by the process according to the present invention. Used as a light source was an LED composed of GaAs having a central wavelength of 780 nm and a rise time of 12 ns. In Fig. 3F, the reference symbol V AK represents an anode voltage waveform, the reference symbol I AK designates an anode current waveform, the reference symbol LT denotes a waveform of triggering light pulse and the reference symbol LQ represents a waveform of quenching light pulse: said triggering light being used for irradiating the LTSI thyristor and said quenching light being used for irradiating the auxiliary SIPT. Fig. 4 shows dependencies of turn-off time t off , turn-off gate current I Goff and turn-off gain G off on anode current I AK at the light quenching operation time. V AK = 500 V and I AK = 8.8 A are turned off within 20 µsec. Turn-off gain is 9 in this case. Fig. 5 shows spectral response characteristics of the SIPT, LTSI thyristor, and diode between the gate and anode. The SIPT has the maximum sensitivity at a wavelength of 775 nm and the LTSI thyristor has the maximum sensitivity at 950 nm. Accordingly, it is effective to select a triggering light source having wavelength in the vicinity of 775 nm and a quenching light source having a wavelength in the vicinity of 950 nm. It is possible to suppress the influence on the SIPT due to the triggering light and the effect of the quenching light acting as the triggering light for the LTSI thyristor by mounting wavelength cut-off filters over the LTSI thyristor and SIPT. Figs. 6A and 6B show an embodiment so adapted as to turn on and off the integrated light-triggered and light-quenched static induction thyristor by light while leading light triggering pulse LT and light quenching pulse LQ through a single light transmission medium 300. This embodiment has a sectional formation which is substantially the same as that of the embodiment shown in Fig. 1C, and is so adapted as to be capable of leading light triggering pulses and light quenching pulses having peak wavelengths close to the optimum triggering wavelength λ T and optimum quenching wavelength λ Q through a suitable light transmission medium 300. In this case, switching between the light triggering pulse LT and light quenching pulse LQ may be performed by emitting and extinguishing two independent light sources while switching mechanically or electrically. Further, this embodiment uses a single light transmission medium and therefore has a characteristic to simplify actual fabrication processes as compared with the embodiments employing plural light transmission means. Optical fibers, bundle fibers, lenses, rod lenses, etc. can be used as the light transmission means. In Fig. 6B, the reference numeral 301 represents the position or range irradiated on the element surface of the auxiliary SIPT (for application) with the light to be led through the light transmission medium 300. In case where a single light transmission medium is used as in this embodiment, it is desirable to select a formation where the p⁺ regions exist in the projected area, on the anode surface, of the drain regions of the SIPT group as shown in Figs. 1C and 1D. Though this formation allows the elections among the pair generated electronhole pairs in the n⁻ layer by the light triggering pulses to be accumulated in the vicinity of the anode and induces hole injection from the anode p⁺ regions, a higher injection efficiency is more desirable. In cases where the light penetration depth and electron diffusion length L n are long, required operations are sufficiently possible with the single light transmission medium in the embodiments having formations other than those shown in Figs. 1C and 1D. The integrated LTQSI thyristor according to the present invention can easily be designed as an element having an element area smaller than 20 mm in diameter, a blocking voltage of 1600 V - rated forward current on the order of 100 A.

Claims: An integrated light-triggered and light-quenched static induction thyristor comprising: a) an buried-gate type of light-triggered static induction thyristor comprising first conductivity type anode regions (104, 152, 104') formed on a first main surface of a high-resistivity substrate of first conductivity type (103), gate regions (106, 113) having a first conductivity type each and high impurity concentration which are partially buried into said substrate in the vicinity of a second main surface of said high-resistivity substrate, a second conductivity type high-resistivity epitaxial layer (112, 122) formed so as to bury said gate regions, a cathode region (101) having a second conductivity type and high impurity concentration which is formed by diffusion into said epitaxial layer, cathode electrodes (107) formed on said cathode region and having windows for penetrating triggering light pulses, gate electrodes (109) formed on said gate regions, and anode electrodes (108) formed on said first main surface, and b) first and second static induction phototransistors forming a darlington circuit comprising a common drain region (113) having said first conductivity type and high impurity concentration and partially buried into said substrate in the vicinity of said second main surface of said substrate, first and second high-resistivity channel regions (112, 122) so formed as to bury said drain region and having said second conductivity type which are isolated from each other, first and second gate regions (114, 124) arranged with a space therebetween, formed in said first and second channel regions respectively and having said second conductivity type and high impurity concentration, first and second source regions (111, 121) formed shallowly in said first and second channel regions respectively between said first and second gate region, and having said first conductivity type and high impurity concentration, drain electrodes (117) formed on said common drain region, first and second gate electrodes (118, 128) formed on said first and second gate regions respectively, and first and second source electrodes (116, 126) formed on said first and second source regions respectively, an aperture for penetrating quenching light pulses formed between said second gate electrode (128) and said second source electrode (126), and c) isolation regions comprising a first groove (991) surrounding along the circumference of said cathode regions, a second groove (992) surrounding along the circumference of said darlington circuit, and a high impurity concentration region (131) of second conductivity type between said first and second grooves, thereby electrically isolating said buried-gate type of light-triggered static induction thyristor from said darlington circuit, and d) wiring comprising a first metal wire (142) connecting said first gate electrode (118) of said first phototransistor, and said second source electrode (126) of said second phototransistor, and a second metal wire (143) connecting said gate electrode (109) of said buried-gate type of light-triggered static induction thyristor and said first source electrode (116) of said first phototransistor. An integrated light-triggered and light-quenched static induction thyristor according to claim 1, characterized in that said gate electrodes (109) are arranged at the bottom of said first groove and said drain electrodes (117) are arranged at the bottom of said second groove. An integrated light-triggered and light-quenched static induction thyristor according to claim 1, characterized in that said anode regions form a diffused layer (104'). An integrated light-triggered and light-quenched static induction thyristor according to claim 1, characterized in that said anode regions (104, 152, 104') are formed in the parts of the first main surface on which said buried-gate regions (106) and said isolation regions (131) are to be projected. An integrated light-triggered and light-quenched static induction thyristor according to claim 4, characterized in that said anode regions (104) and the high impurity concentration emitter regions (105) having said second conductivity type and shallower than said anode regions are arranged alternately in said parts of the said first main surface. An integrated light-triggered and light-quenched static induction thyristor according to claim 5, characterized in that high impurity concentration regions having the second conductivity type (151) are further formed in the part just under said common drain region (113) on said first main surface. An integrated light-triggered and light-quenched static induction thyristor according to claim 5 or 6, characterized In that the pitch between the two neighboring anode regions (104) is shorter than the twice the length of the diffusion length of electrons in the vicinity of said anode regions. An integrated light-triggered and light-quenched static induction thyristor according to claim 3, characterized in that said thyristor further comprises a buffer layer having said second conductivity type and an impurity concentration of 10¹⁵ to 10¹⁸ cm⁻³ between said anode regions and said high-resistivity substrate. An integrated light-triggered and light-quenched static induction thyristor according to claim 1, characterized in that said thyristor further comprises high impurity concentration regions (105, 151) having said second conductivity type, shallower than said anode regions (152) and formed on the first main surface on which said cathode regions (101) and said common drain region (113) are projected, and said anode regions are formed in the rest area of said first main surface. An integrated light-triggered and light-quenched static induction thyristor according to claim 1, characterized in that said anode regions (104) are formed on the first main surface on which said cathode region (101) is projected and said thyristor further comprises high impurity concentration regions having said second conductivity type (182) formed in the rest area of said first surface and having a depth similar to that of said anode regions. An integrated light-triggered and light-quenched static induction thyristor according to claim 10, characterized in that a buffer layer (181) having said second conductivity and uniform thickness is formed between said high resistivity substrate (103) and both said anode regions (104) and said high impurity concentration regions (182) having said second conductivity type. An integrated light-triggered and light-quenched static induction thyristor according to claim 1, characterized in that said thyristor further comprises anode regions (183) formed on the first main surface on which said cathode region (101) and said isolation regions (131) are projected; high impurity concentration regions having the second conductivity type and shallower depth than said anode regions (151) which are formed on the first main surface on which said drain region (113) is projected; and high impurity concentration regions having the second conductivity type and shallower depth than said anode regions (184) which are formed on the first main surface on which said cathode region and said buried-gate regions are projected. An integrated light-triggered and light-quenched static induction thyristor according to any of the claims 1 through 12, characterized in that impurity concentration of said anode regions is lower than 10¹⁷ cm⁻³. An integrated light-triggered and light-quenched static induction thyristor according to any of claims 1 through 13, characterized in that said high-resistivity substrate (103) includes a heavy metal diffused part or a electron beam, gamma ray or proton beam irradiated part. An integrated light-triggered and light-quenched static induction thyristor according to any of claims 1 through 14, characterized in that said thyristor further comprises wavelength cut-off filters mounted on the surface of said static induction transistors for receiving the light quenching pulses and having a cut-off band between the spectral response peak wavelength of said light-triggered static induction thyristor and the spectral response peak wavelength of said static induction phototransistor. An integrated light-triggered and light-quenched static induction thyristor according to any of claims 1 through 15, characterized in that the triggering light and quenching light are transmitted to said static induction phototransistor through a single light transmission medium, and lights having wavelengths in the vicinity of the spectral response peak wavelengths are used for irridiation at turn-on and turn-off times, respectively. An integrated light-triggered and light-quenched static induction thyristor according to any of claims 1 through 16, characterized in that said photodarlington circuit portion formed by said static induction phototransistor has an area smaller than that of said light-triggered buried-gate type of static induction thyristor. A fabrication process of the integrated light-triggered and light-quenched static induction thyristor according to claim 5, characterized in that said fabrication process comprises a first step to form the anode regions (104, 152), buried-gate regions (106) and drain region (113) of the static induction phototransistor by diffusing an impurity of a first conductivity type into semiconductor substrate (103) containing an impurity of a second conductivity type at a low density, a second step to form an epitaxial layer (207) of the second conductivity type with a high-resistivity on said buried-gate regions (106) and said drain region (113), a third step to form the cathode regions (101) and emitter regions (105, 151) of said light-triggered static induction thyristor as well as said isolation region (131) and said first (114) and second (124) gate regions of said static induction phototransistor simultaneously by diffusing an impurity of the second conductivity type, a fourth step to form diffusion windows for forming said first (111) and second (121) source regions of said first and second static induction phototransistors, deposit a polycrystalline silicon layer (115, 125) having low impurity density, form said first and second source regions by diffusing an impurity of the first conductivity type through said polycrystalline silicon layer and etch said polycrystalline silicon for forming polycrystalline silicon electrodes (115, 125), a fifth step to apply a masking material such as a silicon nitride film (215) on said epitaxial layer and using this masking material to etch said epitaxial layer and said substrate (103) for partially exposing said buried-gate regions (106) of said light-triggered static induction thyristor and said drain region (113), a sixth step to perform ion implantation and annealing of the impurity of the first conductivity type into the portions exposed on the surfaces of the buried-gate regions of said light-triggered static induction thyristor and the drain region of said static induction phototransistor, a seventh step to form the cathode electrodes (107), gate electrodes (109) and anode electrodes (108) of said light-triggered static induction thyristor, and first (116) and second (126) source electrodes, the first (118) and second (128) gate electrodes and the drain electrodes (117) of said static induction phototransistor, and an eighth step to form an intermediate insulating film (141) on the surface of said cathode, gate, first and second gate and source electrodes, to open the contact holes on said intermediate insulating film and to form a first electrode wiring (142) for connecting the gate electrodes (118) of said light-triggered static induction phototransistor to the second source electrodes (126) of said second static induction phototransistor and a second electrode wiring (143) for connecting the gate electrodes (109) of said static induction thyristor to the first source electrodes (116) of said first static induction phototransistor through said contact holes.

Inventors: NISHIZAWA, JUN-ICHI, NONAKA, KEN-ICHI, TAMAMUSHI, TAKASHIGE
Applicants: ZAIDAN HOJIN HANDOTAI KENKYU SHINKOKAI
Application year: 1987
Main classification: H01L31
IPC codes: H01L31, H01L29, H01L27, H01L21, H03K17