Photoelectric converter

Abstract: A photoelectric converter comprises a semi­ conductor transistor having a main electrode region of one conductivity type semiconductor and a control electrode region of an opposite conductivity type semiconductor, and a capacitor for controlling a potential of the floating control electorde region. Carriers generated by a light are stored in the control electrode region by controlling the potential of the control electrode area through the capacitor. The stored voltage is read and stored carriers are refreshed. On an unnucleation surface (S NDS ) of said light transmissive substrate, a nucleation surface (S NDL ) of a heterogeneous material having a sufficiently higher nucleation density than that of the material of unnucleation surface and a sufficiently small area to permit growth of single nuclear of the deposite surface is formed. A single crystal region is grown around the single nuclear formed in the nucleation surface (S NDL ). And a photoelectric conversion cell is formed is the single crystal region.

Description: The present invention relates to a method for manufacturing a photoelectric converter in general, and especially one having a photoelectric charge storage area the potential of which can be controlled through a capacitor. A photoelectric converter having a photoelectric charge storage area having a potential thereof controlled through a capacitor has been known, for example, by European Patent Publication No. 132076. It is briefly explained below. Fig. 1(A) shows a plan view of the photoelectric converter and Fig. 1(B) shows a I-I sectional view thereof. Photoelectric conversion cells are arranged on an n-type silicon substrate 101 and each photoelectric conversion cell is electrically insulated from adjacent photoelectric conversion cells by a device isolation area 102 made of SiO₂, Si₃N₄ or polysilicon. Each photoelectric conversion cell is constructed as follows. A p region 104 is formed on a low impurity density n⁻ region 103 formed by epitaxial technique by doping p-type impurity (for example, boron), and an n⁺ region 105 is formed in the p region 104 by impurity diffusion technique or ion injection technique. The p region 104 and the n⁺ region 105 are base and emitter of an NPN bipolar transistor, respectively. An oxidation film 106 is formed on the n⁻ region 103 having the respective regions formed thereon, and a capacitor electrode 107 having a predetermined area is formed on the oxidation film 106. The capacitor electrode 107 faces the p region 104 with the oxidation film 106 being interleaved therebetween, and a potential of the floating p region 104 is controlled by applying a pulse voltage to the capacitor electrode 107. An emitter electrode 108 connected to the n⁺ region 105, a wiring 109 for externally reading a signal from the emitter electrode 108, a wiring 110 connected to the capacitor electrode 107, a high impurity concentration n⁺ region 111 on the rear side of the substrate 101, and an electrode 112 for applying a potential to the collector of the bipolar transistor are formed. A basic operation is now explained. It is assumed that the p region 104 which is the base of the bipolar transistor is initially at a negative potential. A light is applied to the p region 104 and holes of electron-hole pairs generated by the incident light are stored in the p region 104 so that the potential of the p region 104 rise toward a positive level (store operation). Then, a read positive voltage pulse is applied to the capacitor electrode 107 while the emitter electrode 108 floats. When the positive voltage is applied to the capacitor electrode 107, the potential of the p region 104 which is the base rises so that the base-emitter is forward biased and a current flows between the collector and the emitter in accordance with the increment of the base potential at the storage operation. Accordingly, an electrical signal corresponding to the incident light intensity appears at the floating emitter electrode 108 (read operation). Since the charge stored in the p region 104 (base) does not substantially decrease, the same optical information can be repetitively read. In order to remove the holes stored in the p region 104, the emitter electrode 108 is grounded and a refresh positive voltage pulse is applied to the capacitor electrode 107 so that the p region 104 is forward biased relative to the n⁺ region 105 and the stored holes are removed through the grounded emitter electrode 108. When the refresh positive voltage pulse falls, the base potential of the p region 104 resets to the initial negative potential (refresh operation). Thereafter, the store, read and refresh operations are repeated. In the proposed system, the charge generated by the light irradiation is stored in the base p region 104 and the current flowing between the emitter electrode 108 and the collector electrode 112 is controlled by the stored charge. Accordingly, the stored charge is read after amplification by the amplification functions of the cells and hence high output, high sensitivity and low noise are attained. However, this photoelectric converter has a problem described below. When areas of highly density integrated photoelectric conversion cells are very small, an aperture factor is very low and a wiring capacitance increases. In other words, a potential V p generated by the holes stored in the base by the light excitation decreases. The increase of the wiring capacitance may be prevented by increasing a thickness of the insulative layer between the photoelectric conversion cell and the wiring material or using a low dielectric constant material, but the reduction of the aperture factor cannot be essentially prevented because the wiring electrode and the device isolation area exist on the photoelectric conversion cell. As a result, the larger the circuit scale is and the higher the integration density is, the lower is the output level. In the prior art method, the die or pigment used for an on-chip color filter is deposited directly on the cell. As a result, contamination materials in the die or pigment easily go into the cell. This causes a problem in reliability. European Patent Application EP-A-0244081 is relevant prior art under Article 54(3) only. This document discloses Sentaxial growth of a single crystal, e.g. of silicon, on a substrate of either silicon or gallium arsenide (column 13, line 45 to column 14, line 25). The nucleation region is formed on an insulator layer of silicon oxide and is of, for example, silicon nitride. Transistors, other semiconductor devices or optical devices are formed on the surface of the single crystal material. This document also describes growth in a recess. It is an object of the present invention to provide a method for manufacturing a photoelectric converter which method comprises: providing a light transmissive substrate having a recess in a front surface thereof; growing in said recess single crystal material to fill said recess; and forming at the front surface of said single crystal material a transistor including dopant regions and wiring; which method is characterised in that: a nucleation region is provided at the surface of the substrate at the base of the recess, said nucleation region having a nucleation density greater than the adjacent surface and being of such small area as to support the formation of only a single nucleus of said single crystal material; and said single nucleus of said single crystal material is formed on said nucleation region to precede the growth of said single crystal material therefrom. In accordance with the present invention, the single crystal region is formed in the deposit on the recess formed in the light transmissive substrate, and the photoelectric conversion cells are formed in the single crystal region so that the light may be applied to a back side. The single crystal region may be formed by a semiconductor process described as follows. There is no restriction on a substrate material such as that in the SOS (silicon-on-saphire) technique, and no diffusion of aluminum to the cell occurs. Accordingly, the aperture factor is improved, high integration density is attained and the reliability of the cell is improved because comtamination material does not go into the cell. Fig. 1(A) shows a plan view of a photoelectric converter, Fig. 1(B) shows a I-I sectional view thereof, Figs. 2(A) - 2(E) show longitudinal sectional views for illustrating a manufacturing step of one embodiment of the photoelectric converter of the present invention, Figs. 3(A) and 3(B) show longitudinal sectional views for illustrating a manufacturing process of a photoelectric converter having an improved characteristic, Fig. 4 shows a longitudinal sectional view of a second embodiment of the photoelectric converter of the present invention, Fig. 5 shows a longitudinal sectional view of a third embodiment of the photoelectric converter of the present invention, Fig. 6 shows a longitudinal sectional view for illustrating a manufacturing process of a fourth embodiment of the photoelectric converter of the present invention, Figs. 7(A) and 7(B) illustrate a selective deposition method, Fig. 8 shows a graph of nucleus formation densities on a SiO₂ deposit and a silicon nitride deposit, Figs. 9(A) - 9(D) show steps of a single crystal formation method, Figs. 10(A) and 10(B) show perspective views of a substrate in Figs. 7(A) - 7(D), Fig. 11 shows a graph of flow rates of SiH₄ and NH₃ and a composition of Si and N of the silicon nitride film, Fig. 12 shows a graph of the Si/N composition and the nucleus formation density, and Fig. 13 shows a graph of a Si ion injection rate and the nucleus formation density. Figs. 2(A) - 2(E) show longitudinal sectional views for illustrating a manufacturing process of a first embodiment of the photoelectric converter of the present invention. As shown in Fig. 2(A), a recess of necessary size and shape is formed in a light transmissive substrate 1, a heterogeneous material having a high nucleus formation density different from concave structure material of light transmissive substrate is thinly deposit thereon and it is patterned by lithography to form a very fine nucleation deposition surface (S NDL ) formed of heterogeneous material 2. The heterogeneous material 2 may be formed of a modified region having excess Si or Ni formed by ion-injection of Si or Ni into the thin film. Then, a single nucleus of the thin film material is formed only in the heterogeneous deposition surface (S NDL ) 2. The heterogeneous deposition surface (S NDL ) 2 must be fine enough to permit the formation of only one nucleus. The size of the heterogeneous deposition surface (S NDL ) 2 may be less than several microns, although it may vary with the material. As shown in Fig. 2(B), the nucleus is grown while it maintains the single crystal structure to form an island-shaped single crystal grain 3. The island single crystal grain 3 is further grown around the heterogeneous deposition surface (S NDL ) 2 while it maintains the single crystal structure, until the single crystal grain 3 fills out the recess. Thus, a single crystal region 4 shown in Fig. 2(C) is formed. A portion of the region 4 serves as a collector region 4-A of resulted photoelectric conversion device. As shown in Fig. 2(D), a base region 5 is formed in a portion of the collector region 4 by using ion implant method or thermal diffusion method. Then, a gate oxidation film 6 is formed on a surface of the single crystal region 4 by dry oxidation method or wet oxidation method by pyrogenic. A polysilicon electrode 8 is formed on a portion of the base region 5 by a low pressure chemical vapour deposition (LPCVD) method. The polysilicon electrode 8 may be a high melting point metal such as W or Mo or silicide or polysilicide thereof. When the polysilicon is used by the LPCVD method, a film is formed at a temperature of 600 - 650°C, a pressure of 2.7x10¹ - 1.3x10² Pa (0.2-1.0 Torr) and a SiH₄ flow rate of 3.3x10⁻⁷-1.3x10⁻⁶ m³/s (20-100 sccm), and P is highly doped to a vicinity of solid solution limit at 950°C by deposition by POCℓ₃ or ion implantation. Then, ions are implanted to an emitter region 7 and a collector contact region 9 by using a mask pattern formed by photoresist. As shown in Fig. 2(E), an interlayer insulation layer 10 is deposited by CVD method or bias sputter method. Contact holes are formed by photo-etching, and electrodes 11 and 12 of the emitter region 7 and the collector contact region 9 are formed by Aℓ, Aℓ-Si, W, Mo, W silicide , Mo silicide , Ti or Ti silicide. In the present embodiment, since the substrate is made of a light transmissive material, the light may be irradiated to a back side of the substrate opposite to the recess. As a result, in the present embodiment, the light is not blocked by the electrodes and Aℓ wiring which were the causes of light blocking in the prior art converter. Accordingly, the characteristic of the photo-conversion cell can be improved without paying attention to the aperture factor of the cell. Figs. 3(A) and 3(B) show longitudinal sectional views for illustrating a manufacturing process of the photoelectric converter having the improved characteristic. The process is identical to that of Fig. 2 until the gate oxidation film 6 is formed in Fig. 2(D). To compare with Fig. 2(E), a refresh PMOS transistor is added to the base region. It may be formed in the following manner. After the gate oxidation film 6 has been formed, the base capacitor electrode 8 and the PMOS transistor gate electrode 13 are simultaneously formed by photo-etching by using polysilicon, or Mo or W as shown in Fig. 3(A). The collector contact region 9 and the emitter region 7 are then formed by the ion implantation, and a PMOS source region 14 and a drain region 15 are formed by the ion implantation by using a self-alignment method. As shown in Fig. 3(B), the interlayer insulation film 10 is deposited by the CVD method or the bias sputter method. Then, the collector electrode 12, emitter electrode 11 and PMOS source electrode 16 are formed. The PMOS is turned on in the refresh operation. As a result, the base potential is kept constant irrespective of the stored charge and high speed refresh operation is attained and a residual image is prevented. Since the light is irradiated to the back side of the converter, the formation of the PMOS on the front surface of the converter does not affect to the aperture factor. A second embodiment of the photoelectric converter of the present invention is now explained. Fig. 4 shows a longitudinal sectional view of the second embodiment. It is manufactured in the same process as that of the first embodiment until the step of Fig. 2(E). In the present embodiment, a V-shaped groove 17 is formed by photo-etching in the back side of the light transmissive substrate 1. Preferably, the etching is done as isotropically as possible, and either dry etching or wet etching may be used. In accordance with the present embodiment, the V-shaped groove may be formed in the isolation region between the adjacent photoelectric conversion cells so that a light irradiated to the isolation region is refracted to the single crystal region to effectively irradiate it. Further, a cross-talk is reduced. The back side process may be done after the photoelectric conversion cells have been formed or may be done prior to the formation of the photoelectric conversion cells and then the single crystal region and the photoelectric conversion cells may be formed. In the present invention, the back side process for efficiently collecting the light is not limited to the V-shaped groove but it may be done by a lens having a curved surface. A third embodiment of the photoelectric converter of the present invention is now explained. Fig. 5 shows a longitudinal sectional view of the third embodiment. It is manufactured by the same process as that of the first embodiment until the step of Fig. 2(E). In the present embodiment, the light transmissive substrate 1 has a light transmissive layer 18 of a different optical property added thereto, the layer 18 may be a non-reflection layer for suppressing diffused reflection of the incident light on the substrate surface, or a color filter layer. The non-reflection layer may be a single layer (MgF₂) of MgF₂, ZrO₂, and Aℓ₂O₃ or laminated plural layers of them. The color filter layer may be formed by appropriately combining yellow, cyan and magenta dies or blue, red and green filter films by using photo-etching or lift-off technique. The filter film may be formed by a single layer of perylene pigment or a laminated layer of perylene pigment and isoindolinone pigment for a red filter, a single layer of starocyanine pigment or a laminated layer of starocyanine pigment and isoindolynone pigment for a green filter, and a single layer of starocyanine for a blue filter. A fourth embodiment of the photoelectric converter of the present invention is explained. Fig. 6 shows a longitudinal sectional view of a manufacturing step of the fourth embodiment. The photoelectric converter of the present embodiment produces a reference output in a dark state and is used with a photo-sensing photoelectric conversion cell. A recess is formed in the light transmissive substrate 1, and a polysilicon film 19 is deposited by the LPCVD method. The polysilicon film 19 is formed to block the light. It is removed except for the cell area. The polysilicon is then thermally oxidized to form a SiO₂ layer 20, and a heterogeneous deposition surface (S NDL ) 2 for nucleation is formed of material different from SiO₂. The subsequent steps are identical to those of Figs. 2(B) - 2(E). In the present embodiment, since the entire single crystal region is covered by the polysilicon film 19 and the light is blocked, the effect of light radiation on the photoelectric conversion cell is substantially eliminated. The output of such a dark cell corresponds to a dark signal of other photoelectric conversion cell. Accordingly, by subtracting the output of the dark cell from the output of the other photoelectric conversion cell, an electrical signal which exactly represents the incident light is produced. A method for forming the single crystal region 4 on the light transmissive substrate 1 is explained in detail concretely. In order to make complete the understanding of the present invention a selective deposition method for selectively forming a deposition film on the deposit is first explained. In the selective deposition method, the thin film is selectively formed on the substrate by utilizing a difference between factors of materials which are influential to the nucleation in the thin film formation process such as surface energy, deposition coefficient, separation coefficient and surface diffusion rate. Figs. 7(A) and 7(B) illustrate the selective deposition method. As shown in Fig. 7(A), a thin film 22 of a material having the above factor different from that of the substrate 21 is formed on the substrate 21. If the thin film of an appropriate material is deposited under an appropriate deposition condition, the thin film 23 grows only on the thin film 22 and does not grow on the substrate 21. By utilizing the phenomenon, the thin film 23 formed in self-alignment can be grown and the resist or lithography process used in the prior art process is not necessary. The materials for such selective deposition method are SiO₂ for the substrate 21, and Si, GaAs or silicon nitride for the thin film 22 and Si, W, GaAs and Inp for the thin film 23 to be deposited. Fig. 8 shows a graph of nucleation densities on the deposit of SiO₂ and the deposit of silicon nitride. As shown, the nuclearization density on SiO₂ saturates at less than 10³ cm⁻² soon after the start of deposition, and the value does not significantly change 20 minutes later. On the other hand, the nucleation density on the silicon nitride (Si₃N₄) saturates at 4 x 10⁵ cm⁻² and does not change for ten minutes, but it abruptly increases thereafter. In this example, the SiCℓ₄ gas is diluted by the H₂ gas and deposition is made at a pressure of 2.33x10²Pa (175 Torr) and a temperature of 1000°C by the CVD method. The same action may be attained by using reaction gas of SiH₄, SiH₂Cℓ₂, SiHCℓ₃ or SiF₄ and adjusting the pressure and temperature. Vacuum deposition may be used. The nucleation on the SiO₂ raises no substantial problem. By adding the HCℓ gas to the reaction gas, the nucleation on the SiO₂ can be further suppressed so that the deposition of Si on the SiO₂ is completely blocked. Such phenomenon is largely due to the difference between the SiO₂ and the silicon nitride of absorption coefficient, separation coefficient and surface diffusion coefficient to Si but it is also the cause of the selective deposition that SiO₂ reacts by the Si atoms themselves, SiO₂ is etched by the generation of silicon monoxide having a high vapor pressure while the etching does not occur on the silicon nitride. (Journal of Applied Physics, 53, 6839, 1982, by T. Yonehara, S. Yoshioka and S. Miyazawa). By selecting SiO₂ and silicon nitride as the materials for the deposit surface and silicon as the deposit material, a sufficiently large nucleation density difference (Δ ND ) is attained as shown in Fig. 8. Those materials are not restrictive but any other materials may be used so long as one nucleation density difference (Δ ND ) is at least 10³ times as high as that of the other. The materials described hereinafter can also be used for the selective deposition. Another method to attain the nucleation density difference (Δ ND ) is to locally implant Si or N ions to SiO₂ to form a region which includes excess Si or N. According to the present invention, by using the selective deposition method on the basis of the nucleation density difference (Δ ND ), and forming the deposition surface of the heterogeneous material having a sufficiently larger nucleation density than that of the material of the deposit surface into a sufficiently fine are to permit the formation of only one nucleus, the single crystal can be selectively grown at the area where the fine heterogeneous material is present. Since the selective growth of the single crystal is determined by the electron state of the deposit surface, particularly by a dangling bond state, a material having a low nucleation density (for example, SiO₂) need not be bulk material and it may be formed on only material or substrate. Figs. 9(A) - 9(D) show a manufacturing process of the single crystal according to the present invention. Figs. 10(A) and 10(B) show perspective views of substrate in Figs. 9(A) and 9(D). As shown in Figs. 9(A) and 10(A), the thin film 25 having a low nucleation density to allow selective deposition is formed on the substrate 24, the heterogeneous material having a high nucleation density is thinly deposited thereon, and it is patterned by lithography to form the sufficiently fine deposition surface (S NDL ) 26. The size, crystal structure and composition of the substrate 24 may be arbitrary and the substrate may include a functional device of conventional semiconductor material. The deposition surface (S NDL ) 26 of heterogeneous material includes a modified area having excess Si or N formed by ion-implanting Si or N into the thin film 25. The single nucleus of the thin film material is formed only on the deposition surface (S NDL ) 26 of the heterogeneous material under an appropriate deposition condition. The deposition surface (S NDL ) 26 of the heterogeneous material must be formed sufficiently finely to permit the formation of the single nucleus. The size of the deposition surface (S NDL ) 26 may be less than several microns although it may vary with the material. The nucleus grows while it maintains the single crystal structure into the island-like single crystal grain 27 as shown in Fig. 9(B). As described above, it is necessary to establish a condition such that the nucleation does not take place on the thin film 25. The island-like single crystal grain 27 further grows around the deposition surface (S NDL ) 26 while it maintains the single crystal structure and finally covers the entire thin film 25 as shown in Fig. 9(C). Then, the single crystal grain 27 is flattened by etching or polishing so that the single crystal layer 28 in which a desired device may be formed is formed on the thin film 25 as shown in Figs. 9(D) and 10(B). Since the thin film 25 is formed on the substrate 24, the material of the supporting substrate 24 may be arbitrary, and even if the substrate 24 has a functional device formed thereon, the single crystal layer can be readily formed thereon. In the above embodiments, the surface of substrate 24 comprises the thin film 25. Alternatively, the single crystal layer may be formed by using a substrate made of low nucleation density material to allow selective deposition. Example A specific example of forming the single crystal layer is explained. SiO₂ is used as a deposit surface forming material for the thin film 25. A quartz substrate may be used as the substrate, or an SiO₂ layer may be found on a substrate such as metal, semiconductor, magnetic material, piezoelectric material or insulative material by sputtering, CVD or vacuum deposition. The thin film 25 forming material is preferably SiO₂ although SiOx may also be used. A silicon nitride (Si₃N₄) layer or polycrystalline silicon layer is deposited as the deposition surface (S NDL ) forming material on the SiO₂ layer 25 by a depressured vapor deposition method, and the silicon nitride layer or polycrystalline silicon layer is patterned by a conventional lithography technique or a lithography technique which uses X ray, electron beam or ion beam, to form the fine deposition surface (S NDL ) 26 of less than several µm (microns), preferably less than 1 µm (micron). Size of the surface (S NDL ) may be several microns preferably smaller than 1 micron. Then Si is selectively grown on the substrate by using gas mixture of HCℓ, H₂ and SiH₂Cℓ₂, SiCℓ₄, SiHCℓ₃, SiF₄ or SiH₄. The substrate temperature is 700-1100°C and the pressure is approximately 1.33x10⁴ Pa (100 Torr). The single crystal Si grain 27 is grown around the fine deposition surface (S NDL ) 26 of heterogeneous material of the silicon nitride or polycrystalline silicon on the SiO₂ in several tens minutes. It grows to more than several tens of µm (microns) in size under an optimum growth condition. Then, only the Si is etched and flattened by reactive ion etching (RIE) having an etching rate difference between Si and SiO₂ so that the polycrystalline silicon layer having a controlled grain size is formed. A grain boundary is removed and the island-like single crystal silicon layer 28 is formed. When the surface roughness of the single crystal grain 27 is high, the surface is first mechanically ground and then etched. A field effect transistor is formed in the single crystal silicon layer 28 of more than several tens microns in size and having no grain boundary. The field effect transistor exhibited a no inferior property to a field effect transistor formed on a single crystal silicon wafer. Since the device is electrically isolated from the adjacent single crystal silicon layer 28 by SiO₂, there is no mutual interference even if complementary field effect transistors (C-MOS) are fabricated. Since an activation layer of the device is thinner than that when the Si wafer is used, a malfunction due to charge in the wafer created when a radiation beam is emitted is eliminated. Since a stray capacitance is reduced, an operation speed of the device is improved. Since any substrate material may be used, the single crystal layer may be formed on a large substrate with a lower cost than that required when the Si wafer is used. Since the single crystal layer may be formed even on other semiconductor, piezoelectric material or dielectric substrate, a multifunction three-dimensional integrated circuit can be attained. Composition of Silicon Nitride In order to attain a sufficient nucleation density difference between the deposit surface (crystal growth surface) and the deposition surface (S NDL ) of material different from the former surface, the composition of silicon nitride is not limited to Si₃N₄ but other composition may be used. In the plasma CVD method which forms the silicon nitride film at a low temperature by decomposing SiH₄ gas and NH₃ gas in an RF plasma, flow rates of SiH₄ gas and NH₃ gas are changed to control the composition of Si and N of the deposited silicon nitride. Fig. 11 shows a relation between a flow rate ratio of SiH₄ and NH₃ and a composition of Si and N in the silicon nitride film. The deposition condition is an RF output of 175 Watts and a substrate temperature of 380°C. The SiH₄ gas flow rate is fixed to 5.0x10⁻⁶ m³/s (300 cc/min) and the NH₃ gas flow rate is changed. When the flow rate ratio of NH₃ and SiH₄ gases is changed between 4 and 10, the Si/N ratio in the silicon nitride changes between 1.1 and 0.58 as proved by an electron spectrography. When SiH₂Cℓ₂ gas and NH₃ gas are introduced by the depressured CVD method and the silicon nitride is formed at 4.0x10 Pa (0.3 Torr) and 800°C, the composition of the silicon nitride is close to stoichiometric composition of Si₃N₄ (Si/N = 0.75). When the silicon nitride film is formed by heat treatment of Si at 1200°C in ammonium or N₂ gas (thermal nitration), the composition is closer to the stoichiometric composition because the formation is under thermal balance. By growing the nucleus of Si by using the silicon nitride thus formed as the deposit surface having higher nucleation density than that of SiO₂, the nucleation density difference is attained in accordance with the composition. Fig. 12 shows a relation between the Si/N composition and the nucleation density. As shown, as the composition of the silicon nitride changes, the nucleation density of Si grown thereon significantly changes. The Si is grown at a SiCℓ₄ gas pressure of 2.30x10⁴Pa (175 Torr), and a H₂ reaction temperature of 1000°C. The phenomenon of change of the nucleation density by the composition of the silicon nitride influences to the size of the silicon nitride which is the heterogeneous material formed sufficiently finely to permit the growth of single nucleus That is, the silicon nitride having a large nucleation density cannot form a single nucleus unless it is very finely formed. Accordingly, it is necessary to select the nucleation density and an optimum size of the silicon nitride to permit the growth of single nucleus. For example, under the deposition condition which attains the nucleation density of approximately 10⁵ cm⁻², a single nucleus may be formed if the size of the silicon nitride is less than 4 µm (microns). Formation of deposition surface (S NDL ) by ion implantation. In order to attain the nucleation density difference to Si, ions of Si, N, P, B, F, Ar, He, C, As, Ga or Ge may be locally implanted to the SiO₂ which is a material for forming the deposit surface having a low nucleation density to form a modified area in the deposit surface of SiO₂, and the modified area may be used as a material for forming the deposit surface (S NDL ) having a high nucleation density. For example, the surface of SiO₂ is covered by a resist and desired areas are exposed to light, developed and dissolved to partially expose the SiO₂ surface. Then, the SiF 4' gas is used as a source gas and Si ions are implanted to the SiO₂ surface at 10 KeV at a density of 1 x 10¹⁶ - 1 x 10¹⁸ cm⁻². A projection fly path is 1.14 x 10 nm (114Å)and the Si density on the SiO₂ surface is approximately 10²² cm⁻³. Since SiO₂ is inherently amorphous, the Si ion-implanted area is also amorphous. In order to form the modified area, ions may be implanted by using the resist as a mask but the focused Si ions may be implanted to the SiO₂ surface by focused ion beam technique without using the resist mask. After the ion implantation, the resist is removed and the modified area including excess Si is formed on the SiO₂ surface. Then, Si is vapor grown on the SiO₂ deposit surface having the modified area formed therein. Fig. 13 shows a relation of Si ion implantation quantity and the nucleation density. As shown, the larger the Si⁺ implantation quantity, the more does the nucleation density increase. Accordingly, if the modified area is formed sufficiently finely, single Si nucleus can be grown by using the modified area as the heterogeneous material and the single crystal can be grown as described before. The formation of the modified area in a sufficiently fine area to permit the growth of single nucleus may be readily attained by patterning the resist or focusing the ion beam. Method for Depositing Si Other Than CVD In order to grow the single crystal by the selective nucleation of Si, a method for evaporating Si in vacuum (<10⁻⁴Pa (10⁻⁶ Torr))by an electron gun and depositing it on a heated substrate, in place of the CVD method. In a molecular beam epitaxy MBE method which vapor-deposits in high vacuum (<10⁻⁷Pa (10⁻⁹ Torr)), Si beam and SiO₂ start reaction at a substrate temperature of higher than 900°C and the nucleation of Si on the SiO₂ is stopped. (Journal of Applied Physics, 53, 10, p 6839, 1983, by T. Yonehara, S. Yoshioka and S. Miyazawa). By using this phenomenon, the single Si nucleus is selectively formed on the fine silicon nitride area on the SiO₂ and the single crystal Si is grown thereon. The deposition condition is vacuum of 10⁻⁶Pa (10⁻⁸ Torr), an Si beam intensity of 9.7 x 10¹⁴ atoms/cm²·sec and a substrate temperature of 900 - 1000°C. A reaction product SiO₂ having a very high vapor pressure is produced by a reaction of SiO₂ + Si → 2SiO ↑ and etching of SiO₂ by Si occurs by the evaporation. On the other hand, no such etching occurs on the silicon nitride but the nucleation and deposition occur. As a material for forming the deposition surface (S NDL ) having the high nucleation density, tantalum oxide (Ta₂O₅) or silicon nitride oxide (SiON) may be used in place of silicon nitride attain the same effect. This material is formed finely as the deposition surface (S NDL ) and the single crystal may be grown thereon in the same manner. The single crystal area is formed on the light transmissive substrate by the single crystal formation method described above. The photoelectric converter of the present embodiment offers the following advantages. (1) Since the light transmissive substrate is used, the incident light to the back side can be used, and the aperture area is equal to the cell area. Accordingly, the photoelectric conversion efficiency is improved, the output is increased and the high integration density is attained. (2) By machining the light transmissive substrate into the lens, the light applied to the device isolation area can be directed into the photoelectric conversion cell. Thus, a light collection efficiency is improved and a cross-talk is reduced. (3) By forming the anti-reflection coating or color filter on the light transmissive substrate, the substrate may be used as a protective film to protect from the contamination material which has been a defect in a conventional on-chip filter. (4) By covering the entire single crystal area by the polysilicon film 19 to block the light, the effect by the light irradiation can be substantially eliminated and a reference output is produced in a dark state.

Claims: A method for manufacturing a photoelectric converter which method comprises: providing a light transmissive substrate (1) having a recess in a front surface thereof; growing in said recess single crystal material (4) to fill said recess; and forming at the front surface of said single crystal material (4) a transistor (5-12) including dopant regions (5,7,9) and wiring (11,12); which method is characterised in that: a nucleation region (2) is provided at the surface of the substrate (1) at the base of the recess, said nucleation region (2) having a nucleation density greater than the adjacent surface and being of such small area as to support the formation of only a single nucleus (3) of said single crystal material; and said single nucleus (3) of said single crystal material (4) is formed on said nucleation region (2) to precede the growth of said single crystal material (4) therefrom. A method as claimed in claim 1 wherein said nucleation region (2) is of an amorphous material. A method as claimed in claim 2 wherein said nucleation region (2) is produced in the substrate surface by ion-implantation. A method as claimed in claim 3 wherein said adjacent surface of the substrate (1) is of silicon oxide (SiO₂) and the nucleation region (2) is produced by implanting the substrate surface, which is also of silicon oxide (SiO₂), with ions of silicon, nitrogen, phosphorus, boron, fluorine, argon, helium, carbon, arsenic, gallium, germanium, or nickel. A method as claimed in claim 1 wherein said nucleation region (2) is produced on said surface of the substrate (1) at the base of the recess using a deposition technique. A method as claimed in claim 5 wherein said deposition technique is one of low pressure chemical vapour deposition. A method as claimed in claims 5 or 6 wherein said nucleation region (2) produced by deposition technique is patterned by lithography to define said small area thereof. A method as claimed in any of claims 5 to 7 wherein the substrate surface is of silicon oxide (SiO₂) and the nucleation region (2) produced by said deposition technique is of silicon nitride (Si₃N₄) or polycrystalline silicon. A method as claimed in any of claims 1 to 8, wherein either preceding or following the forming of said transistor (5-12) the light transmissive substrate (1) is shaped so as to refract light incident upon the back surface thereof towards said transistor (5-12). A method as claimed in any of claims 1 to 8 wherein a single layer or a multi-layer light transmissive layer (18) is produced on the back surface of said light transmissive substrate (1), said light transmissive layer (18) differing in its optical properties from those of said light transmissive substrate (1). A method as claimed in claim 10 wherein the light transmissive layer (18) produced is either anti-reflective or colour selective. A method as claimed in any of claims 1-8 wherein preceding the growing of said single crystal material (4) an opaque layer is formed about said recess of the light transmissive substrate (1). A method as claimed in any one of the preceding claims and which includes arranging said substrate (1) in a path of light such that said light shall enter said substrate (1) from the direction of the rear surface thereof.

Inventors: ARIKAWA SHIRO, YONEHARA TAKAO, ARIKAWA, SHIRO, YONEHARA, TAKAO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1987
Main classification: H01L31
IPC codes: H01L31, H04N5, H01L27, H01L21