PRINTER ENERGY CONTROL CIRCUIT

Abstract: A control circuit for a dot matrix printer having a plurality of impact print elements includes a latch (48) adapted to receive data to be printed over a data bus (102). The latch (48) provides control signals to drive the print elements, the operating time of the latch (48) being selectively controllable in accordance with an input signal (FORMS) on a lead (20), the level of which is dependent on the thickness of the print record media. The input signal selectively enables a first or second RC network (60, 62, 34, 36) to be operative thereby determining the time at which an associated one of first and second comparators (66, 38) switches to reset the latch (48). The comparators (66, 38) have reference inputs coupled to a reference potential level set by a zener diode (86).

Description: Printer Energy Control Circuit Technical Field This invention relates to a control circuit for a printer which has a plurality of impact print elements utilized in printing on first and second type record media, wherein the required printing energy is different for said first and second type record media. The invention has a particular application to the field of dot matrix printers. Background Art In the field of dot matrix printers, it is known to provide a print head which has included therein a plurality of print wire actuators or solenoids arranged or grouped in a manner to drive the respective print wires a very short, precise distance from the rest or non-printing position to an impact or printing position. The print wires are generally either secured to or engaged by the solenoid plunger or armature which is caused to be moved such precise distance when the solenoid coil is energized and wherein the plunger or armature normally operates against the action of a return spring. It has been found that where impact printers are used with record media of different thicknesses, for example for printing receipts or single thickness items and for printing on forms or multiple thickness items then undesirable image density variations tend to occur. U.S. Patent No. 3,866,533 discloses an impression control arrangement for an impact printer wherein the width of the pulse applied to the print hammers varies in accordance with the sensed thickness of the forms on which printing is being performed and in accordance with the voltage of the source energizing the printing hammers so as to tend to maintain a constant impact force to provide uniform print density for different form thicknesses. However, the known impression control arrangement has the disadvantage of a complex construction. Disclosure of the Invention It is an object of the present invention to provide a control circuit for a printer of the kind specified, which is of simple construction and is adapted for selectively controllable operation. Therefore according to present invention, there is provided a control circuit of the kind specified, characterized by: selection signal means selectively settable to first or second signal levels thereof; latch means adapted to receive data in accordance with information to be printed and having outputs connected to print hammer drives means; a first RC network coupled to said latch means and responsive to said selection signal means at said first level thereof; first comparator means coupled to said first RC network and to said latch means; a second RC network coupled to said latch means and responsive to said selection signal means at said second level thereof; second comparator means coupled to said second RC network and to said latch means; inverter means coupled to said selection signal means and to said first and second RC networks; and precision reference means coupled to said first and second comparator means, said first RC network being operated at said first level of said selection signal means to provide a first pulse width to said latch means for printing of said first type record media by operation of said latch means by said first comparator means when the value of the said precision reference means is reached, and said second RC network being operated at said second level of said selection signal means to provide a second pulse width to said latch means for printing of said second type record media by operation of said latch means by said second * comparator means when the value of said precision reference means is reached. It will be appreciated that by using a control circuit according to the invention, each individual print element is energized with a supply voltage of precise limits and the print head energy control means simultaneously provides modulated pulse width energizing pulses to each and every solenoid or print wire actuator in the print head. The control circuit is effectively incorporated into circuitry utilized in a manner to compensate for the difference in thickness of several types of record media being used in the printer. The record media may be a single layer sheet or a variety of mutlilayer forms. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which: Pig. 1 is a schematic diagram of circuitry incorporating the subject matter of the present • invention; Pig. 2 is a curve illustrating the operating region pulse width for receipt printing when utilizing one source voltage; Fig. 3 is a curve illustrating the operating region pulse width for forms printing when utilizing said one source voltage; Pig. 4 is an illustration of wave forms utilized in the present invention; ' Fig. 5 is a curve illustrating the operating region pulse width for receipt printing when utilizing another source voltage; and Pig. 6 is a curve illustrating the operating region pulse width for forms printing when utilizing said another source voltage. Best Mode for Carrying Out the Invention Referring now to Fig. 1, there is shown a schematic diagram of circuitry which is designed to control and electronically provide constant impact energy to each print wire drive element of a dot matrix print head independent or regardless of variations in the supply voltage. The print head control circuitry is made up of two pulse width modulating circuits, one being for printing of receipts or like relatively thin record media such as single sheet record media and the other being for printing on forms or like relatively thick record media such as multiple sheet record media. The control circuitry also includes a data latch or like apparatus, and associated power drive circuitry. Either of the pulse width modulation circuits is available to be used in printing operations, and selection of which of the circuits to be utilized is by the FORMS signal under microprocessor control. The entire circuit can be disabled by the RESET/ signal. Print head data involving information to be printed is latched into a data latch 48 from the microprocessor via WRITE (WR/) and DATA BUS signals and the pulse width modulators are triggered by writing signals simultaneously with the print head data. A FORMS signal on a lead 20 is input to an open collector inverting TTL gate 22, the output 24 thereof being connected as an-input to an open collector inverting TTL gate 26. The condition of the FORMS signal 20 controls which of the pulse width modulators is utilized. The output 28 of gate 26 is coupled to a resistor 30 which is connected by lead 32 to an RC network comprised of resistor 34 and capacitor 36, the junction of such RC network being an input (RAMP 2 signal) to a comparator 38. The RC network (resistor 34-capacitor 36) extends between potential source Vp and logic ground. It should be here noted that Vcc is +5 volts, V& is +10.2 volts and Vp is +24 volts, all of such voltages being maintained within plus or minus five percent, and that logic ground (LG) is 0 volts and power ground (PG) is 0 volts. A RESET/ signal 40 is input to an open collector non-inverting TTL gate 42, the output 44 of which is coupled as an input 46 to the reset terminal of a TTL clocked-latch type apparatus 48. The RESET/ signal resets the clocked latch 48 and also can be used to disable the entire circuit. The output of gate 42 is also coupled by lead 50 to the output 52 of comparator 38 and to a resistor 54, the other end of which is coupled to voltage source Vcc * The output 24 of gate 22 is also coupled by lead 56 through a resistor 58 to an RC network comprised of resistor 60 and capacitor 62. The RC network (resistor 60-capacitor 62) extends between potential source Vp and logic ground. The junction of such last-mentioned RC network is connected as an input 64 (RAMP 1 signal) to a comparator 66. The junction of leads 50 and 52 is connected to the output 68 of comparator 66. The RESET/ signal 40 is active low and is wired in OR manner with the outputs of comparators 38 and 66. The respective inputs 70 and 72 directed to comparators 38 and 66 are coupled to RC networks forming low pass filters, one comprising resistor 74 and capacitor 76 and the other comprising resistor 78 and capacitor 80, such networks being connected to lead 82. The lead 82 is coupled through a resistor 84 to a potential source Vp and is also coupled through a zener diode 86 to power ground. The zener diode 86 operates as a precision reference device to power ground. An output 90 of the latch 48 is connected as an input to an open collector non-inverting TTL gate 92 and also to an open collector non-inverting TTL gate 94. The output 96 of gate 92 is connected to lead 56 and the output 98 of gate 94 is connected to lead 28. The gates 92 and 94 permit the TRIG signal on output 90 to go to either the R4-C2 network or to the R3-C1 network. The output 96 of gate 92 is wired OR with the output 56 of gate 22, and the output 98 of gate 94 is wired OR with the output of gate 26. The inputs to the data latch 48 are derived through an interface with a microprocessor (not shown) and include a R/ signal 100 as an input clock signal and a plurality of DATA signals input through a DATA BUS 102. The outputs of the data latch 48 are directed in the form of seven signals or pulses HMR2 to HMR8 as power drives to the print head (not shown). It is noted that the print head utilizing the circuitry of the present invention is a seven wire dot matrix type, whose source voltage is 24 volts and ground reference is power ground (PG) . Fig. 2 is a print head compensation curve for use in printing of receipts or like record media and illustrates a valid operating region wherein a desirable pulse width of 340 microseconds is compatible with a print head voltage of 24 volts. Fig. 3 is a print head compensation curve for use in printing of forms or like record media and illustrates a valid operating region wherein a desirable pulse width of 380 microseconds is compatible with a print head voltage of 24 volts. Fig. 4 illustrates a series of wave forms with the WRITE input signal WR/, a plurality of DATA signals D0-D7 of valid data, a HAMMER BUS signal HMRBUS, relating to valid HMR2-HMR8 data signals showing a typical pulse width for printing a line of dots of a seven dot character in the print head energized condition, a TRIGGER signal TRIG which is an output signal of the data latch 48, and an END PULSE/ signal utilized to reset the input of the data latch. A REFERENCE signal REF and a RAMP 1 (2) wave form are illustrated for receipt or form operation. Some of the devices and elements utilized in the illustrated embodiment of the present invention are further identified as follows: the gates 22 and 26 are Texas Instrument type number 7406, the gates 42, 92 and 94 are Texas Instrument type number 7407, the comparators 38 and 66 are National Semiconductor LM 339, and the latch 48 is Texas Instrument type number 74LS273 which comprises clocked latch means in the form of octal D-type flip flops. The resistors 30 and 58 are carbon composition one-quarter watt, 200 ohms; and the resistors 34 and 60 are metal film, low drift, one percent precision, one-quarter watt, resistor 34 being 348K ohms and resistor 60 being 309K ohms. The resistors 74 and 78 are carbon composition one-quarter watt, 47K ohms; the resistor 84 is a metal film, low drift, one-quarter watt, 8.2K ohms; and the resistor 54 is a carbon composition, one-quarter watt, 4.7K ohms. The capacitors 36 and 62 are polypropylene, one percent precision, 0.0047 microfarads and the capacitors 76 and 80 are ceramic, 0.1 microfarads. The zener diode 86 is a one percent precision type, operating at 5.1 volts as a reference device to power ground. In the operation of the present invention, the circuit is powered up with the FORMS signal 20 being inactive (OV) which is the proper state for normal printing of receipts. Also during the power up, the RESET/ signal 40 is active (OV) , the effect being to reset, or the resetting of, the clocked latch 48. Under this condition, all outputs 01-08 of latch 48 (HMR2-HMR8 signals) are inactive. The FORMS signal 20, at one or another signal level thereof, provides the means for selecting the desired RC network. The 01 output signal TRIG of latch 48, on lead 90 through the gates 92, 94, holds the outputs of RC network R3-C1 (resistor 34-capacitor 36) and RC network R4-C2 (resistor 60-capacitor 62), along with the comparators 38 and 66, in an inactive state (OV) . When the print head is to be energized, the WR/ signal 100 turns the circuit on and the 01 output signal TRIG of latch 48 is brought active (+5V) along with the desired HMR signals. The TRIG signal on lead 90 is directed through gate 92 to the R4-C2 network and RAMP 1 to the comparator 66. Since the output of open collector inverting gate 26 is low because the output of gate 22 is high, the RC network of R3-C1 is kept discharged; however the high logic level signal on lead 24 is directed by lead 56 through the resistor 58, and C2 charges up through R4 until it reaches the value of the precision zener diode 86. The time of this action requires approximately 340 microseconds when utilizing the selected values. At this point in time, the output of comparator 66 goes inactive and, over leads 68, 50 and 46, resets the outputs of latch 48 to the inactive state, thereby turning off the print head drive circuitry (HMR2-HMR8) and discharging the R4-C2 network by way of R2, thereby setting the state for the next firing sequence. In the second mode of operation when the FORMS signal 20 is active (+5V), and therefore the output of the gate 26 is high, the RC network of resistor 34 and capacitor 36 (R3-C1) along with comparator 38 are introduced into the firing sequence to increase the pulse width to 380 microseconds for printing on forms. In this case the high output of the gate 26 together with the TRIG signal directed through gate 94 renders the R3-C1 network operative to apply RAMP 2 to the comparator 38. The charging time in this situation is approximately 380 microseconds. During this mode of operation, since the output of gate 22 is low, the R-C network of R4-C2 is kept discharged. It should be noted that the source voltage for RC networks R3-C1 and R4-C2 is V p (24 volts). The networks reach V z (the zener voltage of 5.1 volts) within one RC time constant value, thus making a substantially linear ramp. The slope of this ramp varies linearly with V to create the pulse width compensation curves, as illustrated in Pigs. 2 and 3. It is seen that the slope of the ramp is a linear function between voltage and time and that the region of operation covers a print head voltage that is compensated for an amount on either side of 24 volts. If Vp is up or high, the curve of the ramp is steeper or faster and the duration of the pulse is shorter. If Vp is down or low, the slope of the curve is not as steep and the duration of the pulse is longer. It should also be noted that the precision zener diode 86 is referenced to power ground to additionally compensate for significant drops in power ground printed circuit board runs or in cabling runs. The R5-C3 network and the R6-C4 network operate as low pass filters to reduce noise energy to the respective plus inputs of comparators 38 and 66. A modification of the control circuit of the present invention includes utilization of a source voltage of +28 volts and appearing as Vp on the schematic diagram of Fig. 1. The control circuit for 28 volt operation is identical as described above for 24 volts with the exception that resistor 34 of the R3-C1 network is 365K ohms and resistor 60 of the R4- C2 network is 324K ohms. Fig. 5 is a print head compensation curve for use in printing of receipts or like record media and illustrates a valid operating region wherein a desirable pulse width of 300 microseconds is compatible with a print head voltage of 28 volts. Fig. 6 is a print head compensation curve for use in printing of forms or like record media and illustrates a valid operating region wherein a desirable pulse width of 340 microseconds is compatible with a print head voltage of 28 volts. It is thus seen that herein shown and described is a print hammer energy control circuit that compensates for variations in source voltage and provides pulse width modulation for different types of record media. The circuitry promotes the use of one RC network for receipt printing, another RC network for printing of forms, and the precision reference means to power ground arrangement for compensation of variations in the applied voltage or potential.

Claims: CLAIMS: 1. A control circuit for a printer which has a plurality of impact print elements utilized in printing on first and second type record media, wherein the required printing energy is different for said first and second type record media, characterized by: selection signal means (20) selectively settable to first or second signal levels thereof; latch means (48) adapted to receive data in accordance with the information to be printed and having outputs (HMR2- HMR8) connected to print hammer drives means; a first RC network (60, 62) coupled to said latch means (48) and responsive to said selection signal means (20) at said first level thereof; first comparator means (66) coupled to said RC network (60, 62) and to said latch means (48); a second RC network (34, 36) coupled to said latch means (48) and responsive to said selection signal means (20) at said second level thereof; second comparator means (38) coupled to said second RC network (34, 36) and to said latch means (48); inverter means (22, 26) coupled to said selection signal means (29) and to said first and second RC networks (60, 62, 34, 36); and precision reference means (86) coupled to said first and second comparator means (66, 38), said first RC network (60, 62) being operated at said first level of said selection signal means (20) to provide a first pulse width to said latch means (48) for printing of said first type record media by operation of said latch means (48) by said first comparator means (66) when the value, of the said precision reference means (86) is reached, and said second RC network (34, 36) being operated at said second level of said selection signal means (20) to provide a second pulse width to said latch means (48) for printing of said second type record media by operation of said latch means (48) by said second comparator means when the value of said precision reference means (86) is reached. 2. A control circuit according to claim 1, characterized in that said inverter means includes a first inverter gate (22) having an input coupled to said selection means (20) and an output coupled to said first RC network (60, 62) and to an input of a second inverter gate (26) having an output coupled to said second RC network (34, 36). 3. A control circuit according to claim 2, characterized in that said first and second inverter gates (26) are of open collector type. 4. A control circuit according to claim 1, characterized by non-inverting gate means (92, 94) coupled between said latch means (48) and said first and second RC networks (60, 62, 34, 36). 5. A control circuit according to claim 4, characterized in that said non-inverting gate means includes first and second open collector non-inverting gates (92, 94) coupled respectively to said first and second RC networks (60, 62, 34, 36). 6. A control circuit according to claim 1, characterized by low pass filter means (78, 80, 74, 76) coupled to an input of each of said first and second comparator means (38, 66). 7. A control circuit according to claim 1, characterized in that said precision reference means comprises a zener diode (86). 8. A control circuit according to claim 1, characterized in that said first pulse width is of approximately 340 microseconds for printing on relatively thin record media and said second pulse width is of approximately 380 microseconds for printing on relatively thick record media at an applied voltage of approximately 24 volts.

Inventors: DEL SIGNORE JAMES RICHARD III, DEL SIGNORE, JAMES, RICHARD, III
Applicants: NCR CO, NCR CORPORATION
Application year: 1987
Main classification: B41J9
IPC codes: B41J2, B41J9