Dynamic RAM cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes

Abstract: A one-device shared trench memory cell, in which the polysilicon (22,24) and dielectric layers (26,26A) within the trench (20) extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder (36). The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide a bridge contact (30) that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode (34) to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.

Description: Technical Field The present invention relates to dynamic random access memory (DRAM) cells incorporating a trench storage capacitor contacted by a sidewall-defined bridge contact and it relates to DRAM arrays constructed with these memory cells. The invention relates also to methods of making, such memory cells and such memory arrays. Cross-Reference to Related Applications Reference is made to commonly-assigned U.S. Patent Application S.N. 626,512, entitled "Dynamic RAM Cell with MOS Trench Capacitor in CMOS," filed 29 June 1984 by Lu et al (European Patent Application EP-A-0 167 764. This application relates to a trench cell in which a polysilicon-filled trench extends through a well region formed on an epitaxial region, into the underlying substrate. The resulting poly-to-substrate storage capacitance is considerably enhanced. Reference is made to commonly-assigned U.S. Patent Application S.N. 858,787, entitled "High Density Vertically Structured Memory," filed May 2, 1986 by Fitzgerald et al (European Patent Application EP-A-0 248 993 as well as to "Patent Abstracts of Japan", Vol. 10, No. 259, (E-434) (2315) and JP-A-61 87 359. . These applications relate to dynamic memory cells incorporating a shared trench capacitor. Reference is made to commonly-assigned U.S. Patent Application S.N. 793,401, entitled "High Density Memory," filed October 31, 1985 by the present inventor (European Patent Application EP-A-0 221 380). This application relates to a DRAM trench cell in which a polycrystalline silicon (polysilicon) capacitor electrode is disposed on the bottom of the trench and the gate electrode of the transfer gate field effect transistor (FET) is disposed on the sidewall of the trench so as to define a vertical channel region between the diffused capacitor electrode and the diffused bit line formed on a portion of silicon defined by adjacent trenches. Reference is made to commonly-assigned U.S. Patent Application S.N. 885,618, entitled "Two Square Memory Cells," filed July 15, 1986 by Garnache et al. (European Patent Application EP-A-0 254 046. This application relates to a DRAM trench cell in which the bottom portion of the trench is filled with polysilicon to define separate storage capacitors on each side of the trench, and the upper portion of the trench has gate electrodes so that a conductive channel is formed along the sidewalls of the trench. Background Art Dynamic random access memory "one-device" cells, consisting of a storage capacitor and a single transistor controlling the charge/discharge of the capacitor, were first disclosed in commonly-assigned U.S.P. 3,387,286, to Dennard. Since then, a host of related designs have proliferated in the memory art. In general, these designs have been directed to increasing the storage capacitance of the capacitor, or decreasing the amount of chip area that is taken up by each memory cell. A combination of these trends in the art has led to the development of the so-called "trench storage cell." A trench or groove is defined in a silicon substrate, and is filled with a conductive material such as polysilicon. Since the size of the capacitor electrode has increased without taking up chip surface area, a greater amount of charge can be stored in a smaller area. Among the first disclosures of this general idea were an article by Clarke et al, entitled "Capacitor For Single FET Memory Cell," IBM Technical Disclosure Bulletin , Vol. 17, No. 9, February 1975, pp. 2579-2580 (in Figure 2, polysilicon 22 is formed within an insulated groove to provide an enhanced storage capacitance), and an article by Dockerty, entitled "High-Capacitance, One-Device Cell," IBM Technical Disclosure Bulletin , Vol. 19, No. 2, July 1976, p. 506 (in Figure 3, a 5 micrometer trench is filled with "porus silicon" to enhance storage capacitance). Other teachings in the art have "shared" the capacitance produced by a filled trench between two adjacent FETs. This has further reduced the amount of chip space utilized per memory cell. See the above-cited Clarke article, in which either side of the V-groove trench forms the storage capacitor for adjacent memory cells. Japanese Published Patent Application JP 61-068,647 (published April 19, 1985, based on Japanese Patent Application JP 58-177,231, filed September 26, 1983) apparently discloses a trench cell in which the poly-filled trench is etched such that two separate polysilicon structures are formed on each sidewall of the trench. The structures are separated by air. Each structure appears to form a plate electrode for a capacitor associated with an adjacent FET. The capacitor appears to provide an inversion region which provides charge to a drain region when a channel is induced in the FET. See U.S.P. 4,329,704 (issued May 11, 1982 to Sakurai et al) for a teaching of a "buried" storage capacitor. In some cases, the use of the word "trench" may be a misnomer. Many of the so-called "trenches" are actually discrete apertures that are formed in the substrate. See e.g. an article by Nakajima et al, "An Isolation-Merged Vertical Capacitor Cell For Large Capacity DRAM," IEDM Digest of Technical Papers 1984 , Paper 9.4, pp. 240-243. In Figure 2 the "trench" that is filled with discrete layers of poly is shown as being a square aperture. More recently, trench cells have been proposed in which an elongated aperture (i.e., a true "trench") is filled with polysilicon to define a plurality of sidewall capacitors. See Furuyama et al, "A Vertical Capacitor Cell For Large Capacity DRAM," VLSI Symposium on Integrated Circuits , September 1984, Paper 1-7, pp. 16-17, in which an elongated trench is filled with polysilicon to form a series of memory cells. Adjacent cells are isolated by orthogonal trenches that are filled with silicon dioxide. See also U.S.P. 4,369,564 (issued January 25, 1983 to Hiltpold), wherein a single V-groove is shared by two adjacent memory cells, the midpoint of the groove having a thicker layer of oxide in order to separate the adjacent cells from each other; U.S.P. Re. 32,090 (issued March 4, 1986 to Jaccodine), wherein parallel polysilicon-filled trenches have FETs disposed between them, one side of each trench providing a storage capacitor for the FET and the other side of each trench being isolated from the next FET by a channel stop region; and European Patent Application EP-A-0 150 597 (published August 7, 1985, based on Japanese Patent Application 59-004,364), wherein parallel trenches are alternatively filled with capacitor-defining polysilicon layers and an isolating layer, such that every other trench isolates adjacent poly-filled trenches from one another. The general idea of the so-called "sidewall structures" is also known in the art. As disclosed in commonly-assigned U.S.P. 4,256,514 (issued March 17, 1981 to Pogge et al), a conformal film of material is coated on a "block" or "mandrel structure" that has an upper horizontal surface and vertical surfaces. The film is directionally etched such that it is removed from the horizontal surface of the mandrel. The remaining conformal material forms a sidewall-defined structure that has a horizontal width which is controlled as a function of the original film thickness of the material. In U.S.P. 4,322,883 (issued April 6, 1982 to Abbas et al and assigned to the assignee of the present invention), this general idea is used to define polysilicon sidewall-defined structures 28, which are then oxidized to form sidewalls 30 for isolating adjacent bipolar contacts from one another. A residual portion of the original sidewall may be left in place (it is not critical to the operation of the device). See also U.S.P. 4,378,627 (issued April 5, 1983 to Jambotkar and assigned to the assignee of the present invention), wherein sidewall regions 26 are defined in N+ silicon regions 18 to provide isolation from an overlaying N+ layer 30 that is subsequently etched to define a gate electrode; and U.S.P. 4,419,809 (issued December 13, 1983 to Riseman et al and assigned to the assignee of the present invention), wherein conductive sidewall structures 26 form the gate electrodes of FETs. Note that in Figure 11 of the Riseman patent, the mandrel structure that is used to define the sidewall structures is formed over a semi-recessed oxidation region 12, such that the gate electrodes are spaced from either side of region 12. Finally, note that in the above-cited pending U.S. Patent Application S.N. 885,618 (European Patent Application EP-A-0 254 046), sidewall structures are formed within a partially-filled trench to define the gate electrodes of the FETs associated with the storage capacitors defined by the lower portions of each side of the trench. Further, from EP-A-0 083 816 a semiconductor device having an interconnection pattern is known. According to the teaching of this document there is provided a rim in an opening of the interconnection pattern forming a contacting zone. Heretofore, the present inventor is unaware of any known teachings that relate to utilizing sidewall structures to efficiently define bridge contacts and gate electrodes on either side of a completely filled trench, in which the conductive materials coated within the trench extend above the surface of the substrate to define a mandrel structure. Summary of the Invention It is therefore an object of the present invention to provide a dense dynamic random access memory cell and to provide a method for constructing such a cell. It is another object of the present invention to provide a dense dynamic random access memory array having memory cells with a high capacitance trench storage capacitor and to provide a method for constructing such arrays. It is yet another object of the present invention to produce a trench storage capacitor that has an efficient means for coupling the filled trench to an associated FET device. These objects of the invention are realized by the features laid down in the independent claims. These objects of the present invention are realized by a novel random access memory cell in which a trench has a layer of polysilicon that extends above the surface of the substrate, a sidewall-defined bridge contact being defined on the sidewall of the polysilicon fill for coupling to the source electrode of an associated FET device. In another aspect of the invention, the elongated trench is filled with a first dielectric layer, a thin doped polysilicon layer, a second dielectric layer, and a thick doped polysilicon layer. The trench extends through a well region formed on an epitaxial region grown on the substrate, and also extends through the epitaxial region into the substrate. Portions of the thin polysilicon layer, the second dielectric layer, and the thick polysilicon layer extend above the surface of the substrate. The sidewall-defined bridge contact couples the thin doped polysilicon layer to the source diffusion. The thick doped polysilicon layer, the second dielectric layer, and the thin doped polysilicon layer cooperate to provide a "poly-to-poly" storage capacitance, and the thin polysilicon layer, the first dielectric layer, and the substrate cooperate to form a "poly-to-substrate" storage capacitance. In combination, the two storage capacitances greatly increase the ability of the one device memory cell to store charge. In a further aspect of the invention, the sides of the elongated trench provide independent storage capacitances for a plurality of FET devices formed in a spaced relationship along either side of the trench. The elongated trench is filled with at least one doped polysilicon layer and at least one dielectric layer. The polysilicon layer extends above the surface of the substrate to define a mandrel structure. The sidewall-defined contacts are provided on either side of the trench to couple each side portion of the polysilicon fill to an adjacent source diffusion of a respective FET. A sidewall-defined insulating layer protects the sidewall contact from a sidewall-defined gate electrode for the respective FET. The resulting structure presents a particularly dense random access memory cell that utilizes a shared trench storage capacitor. Brief Description of the Drawings The foregoing and other aspects of the invention will become more apparent upon a description of an embodiment for carrying out the invention, as rendered below. In the description to follow, reference will be made to the accompanying drawings, in which: Figure 1 is a top view of an array of random access memory cells constructed in accordance with the teachings of the present invention; Figure 2 is a cross-sectional view taken along line 2-2 of Figure 1; Figure 3 is a cross-sectional view taken along line 3-3 of Figure 1; and Figures 4-9 present cross-sectional and top views of the random access memory cell of the present invention at various stages of production. Description of an Embodiment the Invention With reference to Figures 1 and 2, the structure of the random access memory cell of the present invention will now be described. The cell is based on a CMOS processing technology. The cell is formed on a wafer 100. The wafer 100 has three components. The first component is a P+ type, 〈100〉 oriented monocrystalline silicon substrate 10. The monocrystalline substrate 10 has a boron dopant concentration in the order of 10¹⁹ ions/cm³. A P- type epitaxial layer 12 overlays monocrystalline substrate 10. The epitaxial layer has a boron dopant concentration in the order of 10¹⁵ ions/cm³. An N+ type well region 14 is formed in portions of the epitaxial layer 12 where memory cells are to be formed. The n-well region 14 has an arsenic dopant concentration in the order of 10¹⁷ ions/cm³. A trench 20 extends through n-well 14 and epitaxial layer 12 to monocrystalline substrate 10. As shown in Figure 1, the trench 20 is elongated (i.e., it runs along the surface of wafer 100). A series of these trenches are formed in parallel. The trench 20 is filled with two layers of doped polysilicon. The first layer of polysilicon 22 is formed along the sidewalls of the trench. The second layer of polysilicon 24 fills the trench. Note that both layers of polysilicon 22, 24 extend from the trench 20 to a point above the surface of wafer 100. The processing method for forming this "overfill" structure will be described below. There are also two dielectric layers disposed along the sidewalls of the trench. A first dielectric layer 26 insulates the first layer of polysilicon 22 from substrate 100. The second dielectric layer 26A insulates the second polysilicon layer 24 from the first polysilicon layer 22. A layer of silicon oxide 28 is formed over the upper surface of the trench fill. Note that the silicon oxide region 28 has lateral portions 28A that extend beyond the sides of the trench fill. A field effect transistor (FET) is formed on either side of the trench 20. Each FET includes a sidewall-defined gate electrode 34 insulated from wafer 100 by a gate insulator 34A, a diffused source electrode 36 and a diffused drain electrode 38. The gate electrode is part of a continuous word line that is disposed on either side of the trench 20 so that all of the FETs on one side of the trench can be accessed at the same time (see Figure 1). The diffusion region 38 serves as a shared drain electrode for adjacent FETs that access adjacent trench capacitors. The drain electrode 38 is coupled at a contact area 44 to a bit line conductor 42, which is disposed in a direction orthogonal to that of the trench 20 to couple a plurality of the drain electrodes 38 together to form a memory array (see Figure 1). The source diffusion 36 is coupled by a sidewall-defined bridge contact 30 to the portion of the first polysilicon layer 22 that extends above the surface of the epitaxial region 12. The bridge 30 is insulated from the gate electrode 34 by a sidewall-defined insulating layer 32. In operation, voltages on bit line 42 are coupled from the drain diffusion 38 to the source diffusion 36 when the gate electrode 34 is at a high voltage. The bridge contact 30 insures that the voltage of polysilicon layer 22 is the same as that of source diffusion 36. Thick polysilicon layer 24, the second dielectric layer 26A and the thin polysilicon layer 22 form a "poly-to-poly" storage capacitance. The thin polysilicon layer 22, the first dielectric layer 26 and the wafer 100 form a "poly-to-substrate" storage capacitance. That is, since both the second polysilicon layer 24 and the substrate 10 are at ground, the dielectric layers 26, 26A provide a dual poly-to-poly and poly-to-substrate storage capacitance whose charge/discharge is controlled by the voltage state of the thin polysilicon layer 22 coupled to the source diffusions 36 on each side of the trench. By controlling the thickness of the two dielectric layers, the charge storage capacity of one of the capacitors can be greater than that of the other. It has been found that oxide formed on polysilicon may have surface discontinuities that may promote hot carrier injection. The effect of these injected carriers may be minimized by increasing the thickness of the dielectric layer. Accordingly, the second dielectric 26A is thicker than the first dielectric 26, such that the poly-to-poly storage capacitance is enhanced. Moreover, in accordance with the teachings of the above-cited U.S. Patent Application, S.N. 626,512 (European Patent Application EP-A-0 167 764); by extending the filled trench through the n-well 14 to the heavily-doped substrate 10, the poly-to-substrate capacitance is also enhanced. In combination, the enhanced poly-to-poly and enhanced poly-to-substrate capacitances greatly increase the composite storage capacitance at each side of the trench, such that a greater amount of charge may be stored in a smaller lithographic space. The ability to store more charge in less space is essential as the dynamic random access memory chips of the future reach densities of one million storage cells per chip and beyond. Figure 1 shows a top view of a section of an array of memory cells of the present invention. The word lines 34 forming the gate electrodes of the FETs run parallel to the trench 20. Note that the FETs are disposed in a spaced relationship along each side of the trench 20. The spaces between the cells are defined by thick isolation layer 28 that are disposed orthogonally with respect to trench 20 to isolate adjacent cells that access the same side of the same trench from each other. As shown in the hatched box labelled "cell," each memory cell takes up a chip surface area in the order of four lithographic squares, a "square" being defined as the minimum image size that can be printed using a given photolithographic exposure system. That is, going from left to right within the hatched box, each cell uses one-half the width of the lithographically-defined drain diffusion 38 (that is, because the drain diffusion 38 is shared by two adjacent cells that access adjacent trenches, the lithographic space is divided between the cells), the entire width of the sidewall-defined gate electrode 34 (which, due to its self-aligned properties, may have a width that is less than the photolithographic limits), and one-half the width of the lithographically-defined trench 20; going from bottom to top within the hatched box, each memory cell uses one-half the width of a first lithographically-defined isolation region 28, the full width of the lithographically-defined bit line 42, and one-half the width of a second lithographically-defined isolation region 28. Since each side of the box is approximately (1/2+1+1/2), the total area of each cell in the order of four lithographic squares or less. Figure 3 shows a cross-sectional view of the isolation region between memory cells. Trench 20 is filled with only a single layer of polysilicon 24. Note that insulating layer 26A (and possibly a residual portion of insulating layer 26, not shown) separates polysilicon 24 from the monocrystalline silicon in the isolation regions. An insulating layer 28 is formed uniformly over the substrate in the isolation regions. Note that gate electrodes 34 are formed over the insulating layer 28 (see Figure 1). The method of forming the memory cell of the invention will now be described with reference to Figures 4-9. An epitaxial layer 12 is first grown on a substrate 10. Both the epitaxial layer 12 and the substrate 10 are doped with boron. The dopant concentrations are controlled such that the substrate 10 has a much greater concentration than does the epitaxial layer 12. The higher P concentration in substrate 10 tends to promote recombination of any majority carriers that may be injected through epitaxial layer 12. Moreover, the difference in dopant concentration produces an electric field that will tend to oppose the injection of minority carriers (i.e., electrons) from the active devices into the substrate. Such injection would materially alter the threshold voltages of the transistors, to thus seriously degrade the reliability of the various circuits formed on the chip. A layer of silicon dioxide 50 is grown on the substrate. The silicon dioxide is grown using conventional techniques, such as exposing the substrate to an oxidizing atmosphere (e.g., wet O₂) at a temperature of approximately 800°C. The silicon dioxide layer should be of sufficient thickness (e.g., 30 nm) to retard crystal dislocations in the substrate that may be imparted by film stresses induced by overlaying layers. A layer of silicon nitride 52 is then deposited on the silicon oxide layer. The silicon nitride layer is formed using low pressure chemical vapor deposition (LPCVD) techniques, using NH₃ and SiH₂Cl₂ as the deposition gasses. Typically, this nitride layer is grown to 40 nm in thickness. A layer of N+ type polycrystalline silicon 54 is then formed on the nitride layer 32 using conventional chemical vapor deposition techniques. The silicon layer is typically in the order of one micron in thickness. As the silicon layer is deposited, arsenic or phosphorus based gases are introduced at a sufficient concentration such that the layer 54 is N+ doped. One or more layers are then deposited on the upper surface of the N+ silicon layer. These layers protect the N+ silicon layer during subsequent processing. As will be described in more detail below, these layers also serve as an etch-stop when the trench fill is replanarized. For example, if chemical-mechanical polishing techniques are used, these layers should have a much slower polish rate than silicon such that the trench fill etch substantially stops when these layers are exposed. If a reactive ion etch (RIE) is used to etch back the trench fill, these layers should be substantially etch resistant in the gas ambient used to etch silicon. In the invention, layers of silicon dioxide 56 (50-75 nm) and silicon nitride 58 (100 nm) are deposited on top of the N+ silicon layer to form the etch-stop. A photosensitive polymer 60 is then applied on top of the upper nitride layer, and a RIE etch sequence is then used to etch through all of the overlaying layers to form trench 20 at least 5.0 µm deep into epi layer 12 and substrate 10. The resulting structure is shown in Figure 4. The polymer 60 (which may be any commercially available photoresist) is exposed and developed in the conventional manner. Then a sequence of etch ambients are introduced to anisotropically etch the stack of layers formed on substrate 10. For example, the upper and lower silicon oxide layers 56 and 50, respectively, and the upper and lower silicon nitride layers 58 and 52 can be etched in a CF₄ plasma. The N+ silicon layer 54 and the silicon substrate 10 may be etched in any plasma (e.g. a chlorine-based RIE) that produces an anisotropic profile in silicon. After the trench 20 is defined, any remaining photoresist 60 may be removed using wet etch (n-methyl pyrrolidone) or dry etch (0₂ plasma) techniques. A series of conformal layers are then formed and etched to coat the trench sidewalls as shown in Figure 5. The first conformal layer 26 is made of a composite structure of silicon oxide (4 nm) - silicon nitride (4-7 nm) - silicon oxide (2 nm) that is formed by oxidizing the trench sidewalls, then depositing the silicon nitride using CVD techniques, and then oxidizing the nitride. While other dielectrics (e.g. silicon oxynitride) could be used, it has been found that the above composite structure provides the combination of low D.C. leakage, high dielectric constant, and high breakdown voltage that is needed for high density dynamic RAM applications as in the present invention. The second conformal layer 22 is a 50 nm layer of undoped polysilicon, formed by conventional techniques. The third conformal layer 62 is a layer of CVD silicon oxide that is doped with boron ions. These layers are then reactive ion etched so that layers 62 and 22 are removed from the surface of silicon nitride 58 and from the trench bottom. Note that the etch is terminated after polysilicon layer 22 is completely removed from silicon nitride layer 58, such that dielectric layer 26 remains on the bottom of the trench to isolate the remaining portions of polysilicon layer 22 on each side of the trench. Due to the anisotropic nature of the RIE, all three layers remain on the sidewalls of trench 20. The upper portions of the layers are tapered due to partial attack during the RIE. Next, as shown in Figures 6A-6B, a process sequence is utilized to define adjacent storage nodes along the sides of the trench. In general, Figures 6A-6B show a top view of the substrate at two discrete points in this process sequence. First, masking structure 64 is applied to the substrate. The masking structure 64 is used to expose lateral portions of the doped oxide layer 62 formed on the sidewalls of trench 20. Using a conventional single-layer photoresist technique, providing such a deep pattern would be difficult. Accordingly, in the present invention the use of multiple patterned layers is preferred. The masking structure is formed of upper and lower patterned layers. The lower layer must be formed of a flowable material (e.g. photoresist or polyimide) that can fill portions of the trench 20. After the upper layer is patterned through a photoresist, the upper layer forms a mask through which exposed portions of the lower layer are removed. Note that the compositions of the upper and lower layers must be chosen so that the upper layer is not etched while the lower layer is being patterned. Numerous layers (e.g. two photoresist layers having different etch characteristics, two polyimide layers at different levels of curing, or an upper layer of silicon oxide or nitride or silicon combined with a lower layer of polyimide or photoresist) could be used to form the upper and lower layers of the multi-layered masking structure 64. Portions of trench 20 exposed by mask 64 are then plasma etched to remove doped oxide layer 62 from the trench sidewalls. Note that the use of a plasma etch (isotropic), as opposed to a RIE (anisotropic), attacks both the horizontal and vertical surfaces of the exposed trench. Note also that the portions of trench 20 that are exposed by mask 64 will ultimately provide isolation between adjacent nodes defined along the trench. The mask 64 protects those areas of trench 20 where storage nodes are to be formed. After the mask 64 is removed by an appropriate etch step, an anneal is carried out to drive the boron dopant ions from the remaining doped oxide 62 into the undoped polysilicon 22. The anneal may be carried out in an inert atmosphere such as N₂. However, since the doped oxide layer 62 is to be subsequently removed, the anneal step may be carried out in an oxidizing atmosphere. Any oxide formed thereby is removed along with oxide layers 62 and 56 by buffered HF etching. Since the doped oxide was heavily doped, a large amount of dopant ions pass from the doped glass into the thin polysilicon layer. Then, the undoped portions of polysilicon layer 22 are selectively removed, resulting in the structure shown in Figure 6B. An important attribute of this process sequence is that during the anneal step boron diffuses laterally such that the spacing between adjacent boron-diffused nodes is below the photolithographic capabilities of the exposure system. That is with reference to Figure 6B, note that the thin polysilicon layer 22 laterally extends beyond the photolithographically defined image 64A, such that the spacing 22B between adjacent poly lines 22 is less than the photolithographically defined space 64B. Therefore, using this lateral diffusion technique a minimum spacing is obtained independent of the particular photolithographic method utilized. Note that any known etchant that exhibits a high undoped silicon-to-doped silicon etch ratio (e.g. KOH in alcohol) could be used to define the boron-diffused nodes. Note that the order of etch steps (i.e., removing doped oxide and then removing the undoped polysilicon) could be reversed as long as the anneal is carried out in a non-oxidizing ambient. After the above process sequence is completed, a second insulating layer 26A is applied to the structure. The insulating layer 26A forms a dielectric that covers the doped polysilicon layer 22 and the exposed first insulating layer 26. Preferably, the second insulating layer 26A is formed of a composite oxide-nitride-oxide structure, as was the first insulating layer 26. Then, a layer of P+ doped polysilicon 24 is applied to the structure to over-fill the trench 20. The doped polysilicon 24 may be formed using conventional techniques (e.g., CVD using silane as the source gas). The polysilicon 24 is then etched back so that it is planar with etch-stop layer 58. As previously discussed, any one of a number of known planarization techniques (RIE etchback by deposition of a planar layer having the same etch rate as polysilicon 24, chemical-mechanical polishing) can be used to planarize the polysilicon fill to etch-stop layer 58. In the invention, chemical-mechanical polishing is preferred. Then, using the nitride layer 58 as a mask, the exposed surface of the polysilicon fill 24 is oxidized by exposure to an oxidizing atmosphere, forming a 200 nm silicon oxide cap 66. See Figure 7. Using the oxide cap 66 as a mask, the nitride layer 58 and underlaying oxide layer 56 is removed by exposure to a CF₄ RIE. Then, the N+ layer 54 is removed by exposure to a wet nitric/HF - based etchant that does not appreciably attack the oxide cap 66 or the underlying nitride layer 52. The resulting "mandrel structure" (i.e., portions of poly layers 22 and 24 and dielectric layers 26 and 26A which form a trench overfill that vertically extends above the silicon surface) is shown in Figure 7. A conventional N-well photolithographic mask is then formed by deposition, exposure and development of a photoresist layer. Note that in the CMOS technology of the present invention, all of the memory cells are formed in the N-well. Although CMOS is preferred for the low power consumption it provides for the memory support circuits such as the data buffers, decoders, drivers, etc., it is to be understood that (with minor modifications) the memory cells of the invention could be formed directly in a P-type region. In the present invention, the N-well 14 is formed by phosphorus implantation at 10¹⁷ ions/cm³ into the memory cell regions, so that it extends through a substantial portion (e.g. two-thirds) of the thickness of the epitaxial layer. Then a 20 nm layer of nitride is deposited on the substrate, to help define those regions in which oxide isolation is to be formed. The 20 nm nitride is then RIE etched to remove it from horizontal surfaces, leaving it on the mandrel sidewalls. It is necessary to stop this etch step in time to leave intact > 50% of the underlying 30 nm nitride layer 52. The remaining nitride 52 is anisotropically etched through a photolithographic mask to define those areas of the surface where isolation regions are to be formed. Then, the surface regions of the wafer exposed by the patterned nitride are subjected to an oxidizing ambient for a sufficient length of time to form a semi-recessed oxidation (S-ROX) pattern 28 as shown in Figure 1. Note that during this oxidation step the silicon beneath the oxide cap 66 is further oxidized so as to form an S-ROX structure 28 on top of the filled trench 20. As this S-ROX structure is formed, it will deform the nitride on the sidewalls of the mandrel structure trench, producing lateral ends 28A that overhang the sidewalls of the trench 20. The importance of this structural feature will become more apparent below. After the S-ROX pattern is defined, the nitride layer (including the portions thereof on the sidewalls of the trench overfill) is etched by wet etching techniques (e.g. hot H₃PO₄). Note that nitride layer 52 is also removed during this step. Then, a brief plasma etch sequence is completed to remove the remaining nitride and oxide components of dielectric layer 26 as well as oxide layer so, such that the polysilicon layer 22 is exposed. The resulting structure is shown in Figure 8. As shown in Figure 9A, a conformal layer of polysilicon 30A is then deposited on the structure, using the same techniques that were utilized to form polysilicon layer 22. The conformal layer is anisotropically etched in a RIE mode, such that portions 30B remain only on the sidewalls of the trench fill and isolation region 28. Because of the lateral portion 28A of the oxide isolation region 28, a small horizontal portion of the conformal layer is protected (and hence not removed) during the anisotropic etch. Using the same drive-in technique that was used to dope polysilicon layer 22, an anneal is carried out in an inert ambient at approximately 800°C so that boron diffuses from the polysilicon layer 22 into the vertical portion of the conformal layer of polysilicon, and through the horizontal portion of the polysilicon layer 22 into a portion of the n-well 14 thereunder to form a diffusion region 36 self-aligned to the conformal layer. In this manner, the conductivity of the conformal layer may be controlled without resorting to doping the layer through conventional photolithographic techniques. Note that, similarly to the initial doping of polysilicon 22, the boron diffuses laterally so that the spacing between adjacent boron doped regions is less than the photolithographic limits (see Figure 9B). Then, the polysilicon layer is exposed to an etchant (KOH in alcohol for example) that has a high undoped polysilicon-to-doped polysilicon selectivity, such that (as shown in Figure 9B) undoped portions of polysilicon region 30B are removed, leaving doped polysilicon region 30 to form a conductive bridge that establishes contact between the polysilicon layer 22 and the P+ diffusion 36 formed thereunder by boron outdiffusion. Note also that by use of this method, the polysilicon bridge contact 30 is totally self-aligned with respect to both the polysilicon 22 and the contacted P+ diffusion 36. Again, this eliminates several costly mask-and-etch steps. After the bridge contact 30 is formed, a conformal layer of silicon oxide is applied using conventional CVD techniques. Similarly to the polysilicon layer 30A, this layer of oxide is then anisotropically etched (preferably in an 0₂ RIE) to form a sidewall insulator 32 (see Figure 1) that isolates the conductive bridge 30 from other conductors. After the sidewall insulator is defined, a gate insulator 34A is formed on the exposed silicon substrate. See Figure 2. Preferably, this gate insulator is formed by thermal oxidation of the exposed silicon. Then a thick layer of conformal polysilicon is deposited over the entire structure, and similarly to previous steps the polysilicon is anisotropically etched in a RIE mode to form sidewall-defined gate electrodes 34. Forming the gate electrode by sidewall techniques reduces the achievable channel length, in that the lateral length of the gate electrode is now a function of the thickness of the polysilicon as-deposited rather than being a function of the limits of the photolithographic exposure system. After the gate electrode is formed and covered by a thin layer of protective oxide, boron ions are implanted into areas of the substrate exposed by the gate electrode, and an anneal cycle is carried out to diffuse these dopant ions into the substrate to produce the drain diffusion 38. During this anneal cycle, boron dopant ions will continue to diffuse from the portion of conductive bridge 30 overlaying the substrate, expanding the self-aligned P-type source diffusion 36 to underlap the poly silicon gate electrode. Note that concentration of the sequence of P+ diffusions is not critical except that it must be above about 7X10¹⁹/cm³ to produce the preferential etching selectivity. The manufacturing process is then completed by depositing a thick layer of doped glass (PSG or BPSG) 40, lithographically defining openings through the glass, and depositing a layer of metal 42 to contact the drain diffusions 38 at a juncture 44. In the above-described manufacturing process, a sequence of sidewall-defined structures (contact bridge 30, insulating layer 32, and gate electrode 34) are all formed relative to the trench overfill, to establish the electrical and physical coupling of the filled trench 20 to the transfer gate FET. Moreover, by providing a combination of poly-to-poly and poly-to-substrate storage capacitance, the resulting memory cell has a sufficient charge storage capability to be useful in a highly dense dynamic RAM chip design. There are two rather important components of the processing sequence described above. One is the ability to form a thin storage node dielectric that provides the necessary charge storage capabilities, particularly between the two polysilicon layers. It has been found that the oxide-nitride-oxide combination provides such a capability. A particularly good way of forming this stack includes the following steps. The exposed silicon is first oxidized by introducing an HCl/0₂ gas flow at 800°C for 13 minutes, and annealing the structure at 800°C for 10 minutes in an inert atmosphere. The resulting oxide layer is on the order of 4 nm thick. Then the wafer is exposed to a gas combination of N₂ (nominal), NH₃ (130 sccm), and SiH₂Cl₂ (10 sccm) for a sufficient time to create a 7 nm nitride layer having an index of refraction of 1.95-2.05. Then the wafer is subjected to a dry 0₂ (15 minutes at 1000°C) dry 0₂ - wet 0₂ - dry 0₂ oxidation sequence (all at 1000°C for a time sufficient to form a 2 nm thick layer of silicon oxide on the nitride. The second important component of the processing sequence is the ability to diffuse boron dopant from the highly doped oxide 62 to poly 22, from poly 22 to the conducting bridge 30, and from the conducting bridge 30 to the substrate surface to form a P+ source region 36 in an N-well 14. At the high minimum concentration of 7X10¹⁹ ions/cm³, this diffusion is reasonably forgiving, (i.e. it does not require control tighter than about ± 50%).

Claims: A one-device dynamic random access memory cell, comprising a trench (20) formed in an exposed surface of a semiconductor substrate, said trench being filled with a trench fill (22, 24, 26A) comprising at least a first conductive layer (22), a first dielectric layer (26) isolating said trench fill from said substrate, said first conductive layer and said first dielectric layer forming a storage capacitor with said substrate, a transistor device disposed on a portion of said substrate adjacent one side of said trench, said transistor having source and drain electrodes formed by first (36) and second (38) doped regions provided within said surface of said substrate to define a channel region therebetween and a gate electrode (34) disposed above and insulated (34A) from said channel region; wherein said trench fill extends above the surface of the substrate, and wherein said first conductive layer is contacted by a sidewall-defined bridge contact (30), said bridge contact having a vertical portion in contact with a portion of said first conductive layer (22) extending above said surface of said substrate, and a horizontal portion in contact with said first doped region (36) of said transistor device, characterized in that said bridge contact (30) is insulated from the gate electrode (34) by a sidewall-defined insulating layer (32) and said gate electrode is formed as a sidewall-defined conductive layer coated on said sidewall-defined insulating layer, and in that the trench fill has a thick insulating layer (28) of silicon oxide on its upper surface, having lateral ends (28A) that overhang the sidewalls of said fill, and said bridge contact (30) is substantially aligned with the edge of said lateral ends (28A). The one-device dynamic random access memory cell of claim 1, wherein said first conductive layer is provided on said first dielectric layer along the sidewalls of said trench, a second conductive layer (24) completely fills said trench and is insulated from said first conductive layer by a second dielectric layer (26A), said first conductive layer and said first dielectric layer forming a storage capacitor with said substrate, and said second conductive layer and said second dielectric layer forming a storage capacitor with said first conductive layer. The one-device dynamic random access memory cell of claim 1 or 2, wherein each of said first and second dielectric layer material is selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. The one-device dynamic random access memory cell of any one of the preceding claims, wherein said second doped region (38) is shared with a second laterally adjacent transistor device, said shared second doped region being coupled to a metal line (42). A dynamic random access memory array of one-device dynamic random access memory cells according to any one of claims 2 to 4, characterized in that the one-device memory cells are arranged in a spaced relationship along each side of a plurality of elongated parallel trenches, opposite parts of the two sides of each trench belonging to different memory cells. A method of forming a dynamic random access memory cell in an exposed surface of a semiconductor substrate, comprising the steps of: coating the semiconductor substrate with a layered structure; forming an elongated trench (20) in the surface of said coated substrate, said trench extending into the semiconductor substrate and having substantially vertical sidewalls and a bottom; coating said sidewalls and said bottom of said trench with a first dielectric layer (26); providing a first polysilicon layer (22) on said first dielectric layer along the sidewalls of said trench, said first polysilicon layer being undoped and said first polysilicon layer, said first dielectric layer, and the semiconductor substrate combining to provide a storage capacitor on each of said sidewalls of said trench, coating said first polysilicon layer (22) with a layer of doped silicon oxide (62) having dopant ions of a first conductivity type; selectively removing portions of said doped silicon oxide to define the lateral extension of the storage node along said trench; annealing the coated substrate to drive said dopant ions from said layer of doped silicon oxide into said first polysilicon layer, said dopant ions laterally diffusing along said first polysilicon layer; removing the remainder of said layer of doped silicon oxide (62); and exposing (64) said first polysilicon layer to an etchant that removes undoped portions of said first layer of polysilicon without appreciably attacking doped portions of said first polysilicon layer; forming a second dielelectric layer (26A) on said doped portions of said first polysilicon layer; forming a second layer of polysilicon (24) on said second dielectric layer, said second layer of polysilicon filling said trench; etching the coated substrate, thereby exposing the surface of the semiconductor substrate and etching said first dielectric layer projecting above the surface of said semiconductor substrate, so that said first polysilicon layer is exposed to form a conductive structure that projects above the surface of the semiconductor substrate and includes the second dielectric and polysilicon layers, said conductive structure having an upper surface and sidewalls; forming an insulating structure (28) on said upper surface of said conductive structure, said insulating structure having sidewalls (28A) that laterally extend over said sidewalls of said conductive structure; coating the assembly conformally with a third polysilicon layer (30A) of undoped polysilicon; anisotropically etching said third polysilicon layer so that it remains on the sidewalls of said conductive structure and of said insulating structure, and is removed from all exposed horizontal surfaces, horizontal portions of said conformal material beneath said sidewalls of said insulating structure being protected during said etch by said sidewalls and thus remaining; heating said substrate so that dopant ions diffuse from said first polysilicon layer of said conductive structure into portions of said remaining third polysilicon layer on said vertical sidewalls of said conductive structure, and at least some of said diffused dopant ions also diffusing from said horizontal portion of said remaining third polysilicon layer into a portion of said semiconductor substrate thereunder to form a diffused region therein (36); and etching the remaining third polysilicon layer such that portions (30B) thereof that remained undoped are removed, the resulting bridge contact (30) contacting said first polysilicon layer of said conductive structure (22) and said diffused region (36); forming a conformal insulating layer on the assembly and anisotropically etching said conformal insulating layer, thereby leaving sidewall-defined insulating portions (32), covering said bridge contact (30), forming a conformal fourth polysilicon layer on the assembly and anisotropically etching said fourth polysilicon layer, thereby leaving a sidewall-defined portion on said sidewall-defined insulating portion (32) forming a sidewall-defined gate electrode (34), implanting ions into a portion of said substrate adjacent said gate electrode to form a second diffused region (38) in the substrate, said gate electrode overlaying a portion of the substrate between said first (36) and second (38) diffused regions so as to form a transistor device adjacent to said trench. The method of forming a memory cell as recited in claim 6, wherein said first dielectric layer comprises a composite of silicon oxide - silicon nitride - silicon oxide. The method of forming a memory cell according to claim 6 or 7, wherein the step of filling said trench with said second polysilicon layer consists of overfilling said trench with said second polysilicon layer and plaranizing said second polysilicon layer so that it is co-planar with said surface of said coated substrate. The method of forming a memory cell as recited in any one of claims 6 to 8, further comprising the step of forming an insulating layer (40) on top of said insulating structure and of said sidewall-defined gate-electrode (34). A method of forming a dynamic random access memory array of one-device memory cells formed according to any one of claims 6 to 9, further comprising the steps of: providing a plurality of said sidewall-defined bridge contacts (30) on each side of said conductive structure, said bridge contacts being disposed in a spaced relationship along each side of said trench, providing a plurality of said sidewall-defined gate electrodes (34), each of said sidewall-defined gate electrodes overlaying a respective one of said sidewall-defined bridge contacts; and forming a plurality of said second doped regions (38) in said substrate, said plurality of sidewall-defined gate electrodes overlaying portions of said semiconductor substrate between said plurality of first (36) and second (38) doped regions to provide a plurality of transistor devices disposed in a spaced relationship along each side of said trench, said trench providing respective storage capacitors to each of said transistor devices.

Inventors: KENNEY DONALD MCALPINE, KENNEY, DONALD MCALPINE
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1987
Main classification: H01L27
IPC codes: H01L27, H01L21