Improved programmable logic device

Abstract: A programmable logic device comprises a plurality of input lines (103-105), a plurality of product terms (111,113) and an array of programmable cells at the intersections of the input lines and product terms. Sensing amplifiers (112,114) are coupled respectively to the product terms and provide logical sense signals. These are applied through a shift register latch (112,122) to output logic macro-circuits (124,138) each of which receives the logical sense signals associated with eight product terms. The output logic macro-circuits can perform predetermined logical functions on at least selected ones of the logical sense signals, and provide outputs to device terminals dependent thereon.

Description: BACKGROUND OF THE INVENTION The present invention relates to programmable logic devices, and more particularly to techniques for providing high speed programming and verification of device array programming data and logic paths. Digital systems such as computers typically are fabricated from many logic and memory integrated circuits or chips. A goal of microelectronic integration is to fit the memory and logic circuits of a system onto the fewest possible integrated circuits, to minimize the cost and increase the system speed and reliability. To meet these requirements, various types of hardware have evolved. Between the extremes of general purpose VLSI devices such as microprocessors on the one hand, and custom and semi-custom gate arrays on the other, are programmable logic devices (PLDs), also termed programmable logic arrays (PLAs). PLDs provide a flexible architecture, user-programmed through on-chip fuses or switches, to perform specific functions for a given application. PLDs can be purchased "off the shelf" like standard logic gates, but can be custom tailored like gate arrays in a matter of minutes. To use PLDs, system designers draft equations describing how the hardware is to perform, and enter the equations into a PLD programming machine. The unprogrammed PLDs are inserted into the machine, which interprets the equations and provides appropriate signals to the device to blow the PLD which will perform the desired logic function in the user's system. The PLD typically includes hundreds or thousands of the fuses or switches, arranged in a matrix to facilitate their manufacture and programming. Recently, PLDs based on erasable-programmable-read-only memory cells (EPROMs) fabricated with CMOS (complimentary-metal-oxide-semiconductor) technology have been introduced. Such devices employ floating gate transistors as the PLD switches, which are programmed by hot electron effects. The EPROM cells are erased by exposure to ultraviolet light. A problem of known PLDs relates to verification of output logic paths. The typical PLD comprises a programmable array, followed by sense amplifiers, logic gates and output drivers eventually arriving at the device output. (The exact configuration will depend on the particular device). A typical PLD output structure comprises an array, sense amplifiers, an OR gate, and an output register, coupled to the device output pin. The output data at the output pin does not have a one-to-one correlation to data on a specific product term or column of the array, as is the case for a memory. The typical way to determine if the output devices are working properly is to program the array with a bit pattern and test to see if the output logic is working. Because bipolar fuses are destructively programmed, it is not possible to verify operation of all the output devices. It is also known to provide a test input to an OR gate to test its functionality, but this does not verify operation of the sense amplifiers or other OR gate inputs. Programmable logic devices with output logic circuits as indicated in the preamble of claim 1 are known e.g. from NEW ELECTRONICS vol. 18, no. 4, February 1985, LONDON, GB pages 72 - 73 D. J. BRAIN: 'EPROM Technology enhances CMOS PAL Performance'. It is known to provide the capability of high speed fuse verification, but insofar as applicant is aware, the known techniques employ separate verification sense amplifiers, thereby providing a somewhat different verification signal path from the normal user signal path through the normal use sense amplifier. Thus, the known techniques do not verify operation of the normal use sense amplifiers, which may be inoperative due to manufacturing defects. Moreover, the use of separate sense amplifiers, with possibly different sense thresholds can lead to different results, i.e., the fuse-verify sense amplifier may sense an open cell, but the normal logic sense amplifier may sense a closed cell. SUMMARY OF THE INVENTION The invention in its various aspects is defined in the appended claims to which reference should now be made. A preferred PLD described in more detail below employs electrically erasable memory cells which can be programmed or erased at high speed. The described PLD memory cells comprise floating gate transistors as the sense elements, which are programmed and erased by Fowler-Norheim tunnelling. The PLD comprises a serial register latch (SRL) which is coupled to the product term lines of the logic array to be programmed, in accordance with our European Patent Application EP-A-0 196 771 (86301336.3). The preferred programmable logic device may -be programmed at very high speed and has both the capability of high speed verification of the programmed data using the normal sense amplifiers and the capability of verifying the operation of the device output logic devices. The preferred PLD requires low power consumption and is reprogrammable by the manufacturer and the user. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages of the present invention will become more apparent from the following detailed description of an exemplary embodiment thereof, as illustrated in the accompanying drawings, in which: Figure 1 is a simplified block diagram illustrative of the preferred embodiment. Figure 2 is a simplified cross-sectional diagram illustrating the electrically erasable memory cell employed in the preferred embodiment of the invention. Figure 3 is a block diagram of the programmable logic device in its normal user mode. Figure 4(a), 4(b) and 4(c) depict, respectively, the functional pin layout of the 20 pin package employed with the PLD of the preferred embodiment in the normal mode, the edit mode, and the logic test mode. Figure 5 is a simplified schematic drawing of an output logic macro cell as employed in the PLD. Figure 6 is an illustration of the array configuration employed in the preferred embodiment. Figure 7 is a simplified schematic illustrative of four cells of a product term or column of the AND array and programming and verification circuits of the preferred embodiment. Figure 8 is a simplified block diagram of a programmable logic device employing the invention when in the edit mode. Figure 9 is a timing diagram illustrative of the loading of programming data into the shift register latch. Figure 10 is a timing diagram illustrating the programming and verification of data in the matrix. Figure 11 is a signal timing diagram illustrating the logic test mode of the preferred embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention comprises a novel programmable logic device employing electrically erasable, programmable memory cells, and adapted for high speed programming and verification. The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. In the following description, numerous specific details are set forth, such as circuit configurations, array cell circuits, signal timing diagrams and the like, in order to provide a thorough understanding of the invention. It will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuit details and steps are not described in detail so as not to obscure the invention. Referring now to Figure 1, a simplified block diagram illustrative of some of the principal features of the invention is disclosed. Exemplary array 10 comprises a 32 row by 64 column (or product term) array of programmable cells. The cells are individually programmable, in dependence upon the state of a programming bit presented to the cell during a programming mode. A 64 stage serial shift register latch (SRL) 30 is coupled to the array 10, such that individual stages 1-64 of the SRL are respectively coupled to corresponding columns 1-64 of the array 10. A 1-of-32 row decoder 20 is provided to select a particular row of the array during the programming cycle. The SRL 30 comprises a clock port 32, a serial data input port 34, a "logic test enable" port 36 and a serial data output port 38. The individual 64 stages of the SRL are respectively coupled to the respective 64 product terms of the array 10. The 32 row lines of the array 10 are respectively coupled to the output of the 1-of-32 row decoder 20. The address of the row to be programmed during a particular program cycle is selected by the state of the row address gate (RAG) bus 22. The clock rate of the clock signal applied to the SRL is nominally 1 Mhz. Thus, programming data may be serially shifted into the SRL from a programming machine or test head external to the logic device at the clock rate; to load the SRL with 64 bits of data requires less than one millisecond at the 1 Mhz clock rate. Once the SRL is loaded with programming instructions or data, then the SRL contents are programmed into the 64 cells of the selected row of the array 10 during a nominal ten millisecond programming cycle. The programming process is then repeated for each row of array 10 until the entire array has been programmed. The arrangement thus allows the programming of the array 10 to be performed very quickly; the entire 32 by 64 cell array may be programmed in less than one-half second, as compared with over 20 seconds required for "single bit" programming of EPROM-based PLDs. The preferred embodiment of the invention is implemented in CMOS technology, wherein the storage elements of each cell comprise electrically erasable programmable floating gate field effect transistors employing Fowler-Nordheim tunneling. The technique is extendable to any arbitrary number of columns, since these floating gate transistors require essentially zero current to program. Thus, programming time can be greatly reduced for PLDs employing the invention. The arrangement provides the capability for high speed verification of the contents of the array 10. The SRL may be employed to verify the state of each of the array cells in a particular, selected row. This data is loaded into the SRL and can be serially shifted out of the SRL via the "serial data out" port 38. As will be apparent to those skilled in the art, the programming equipment may be readily adapted to compare the output data contents of the selected row with the desired data. A further aspect of the array is illustrated in Figure 1. During a logic test mode, data is serially loaded into the SRL. Under the control of a special test input ("Logic test enable"), the data in the SRL is forced onto the sense amplifier inputs. This "apparent array pattern" is then sensed through the normal output logic and read out of the device output pin. Data can then be serially clocked out of the SRL and verified against the logical output that was received on the device output pins. This technique allows the output logic to be validated using the normal sense amplifers without having to program the array pattern into the device. This is a very powerful feature, as it allows the manufacturer to test virtually 100% of the output logic circuitry for each chip. Figure 2 is a cross-sectional view of the electrically erasable memory cell employed in the preferred embodiment. The cell comprises a select transistor and a floating gate transistor as the sense or memory transistor. The floating gate device is adapted to employ the Fowler-Nordheim tunneling effect to remove or augment the charge stored on the floating gate to place the sense transistor in either the enhancement or depletion mode. To allow Fowler-Nordheim tunneling to take place, the floating gate region 5 is separated from the drain region, N + region 3, by a very thin (100 Angstrom) layer of oxide. The select transistor is formed by a polysilicon region 1, separated from the N + regions 3,4 by an oxide layer. The polysilicon region 1 comprises the gate electrode of the select transistor, with the source and drain comprising the N + regions 3,4 formed by N-type dopant implanted in the active area. Programmable Logic Device - Normal Mode Referring now to Figure 3, a logic block diagram illustrative of a PLD employing the invention and in a normal user mode is disclosed. The preferred embodiment comprises an integrated circuit implemented in a CMOS technology. The physical layout of the circuit logic blocks of the PLD is generally indicated in Figure 3. Thus, the 32 by 64 cell array of Figure 1 is shown in Figure 3 as two 32 by 32 subarrays 102,104. To achieve higher performance, the AND gate array has been split into two halves with row drivers driving both directions. This effectively reduces by a factor of four the polysilicon row line delay. Figures 4(a), 4(b) and 4(c) illustrate the device functional pin layout in the normal mode (Figure 4(a)) the edit mode (Figure 4(b)) and the logic test mode (Figure 4(c)). The preferred embodiment is housed in a 20-pin package with eight dedicated inputs (P2-P9) and eight user-programmable bi-directional pins (P12-P19). Pins P1 and P11 provide clock and output enable (CLK/OE) signals to the logic. While the size of the AND matrix available to the user for normal operation is 32 rows by 64 columns, the actual size of the matrix is larger to accommodate several other features of the device. Thus, Figure 6 shows the actual array configuration employed in the preferred embodiment. Rows 0-32 comprise the user portion of the array. Rows 33-59 and 62 constitute reserved array space. Row 60 is 82 bits in length and defines the output logic architecture of the PLD. During the normal user mode, pins P2-P9 are input ports and are coupled via bus 106 to row driver 101. In Figure 3, the respective rows of arrays 102,104 are coupled to the row driver 101 by busses 103,105. One side of the respective columns of cells (or product terms) in the arrays is coupled to the current limiter and column pull-up circuits 108,110. The other side of the array columns are coupled to sense amplifiers 112,114 via busses 111,113, respectively. The sense amplifiers 112,114 are in turn coupled to 32 bit wide SRLs 120,122 via busses 115,117. To accommodate row 60 of the array which is 18 bits wider than the other rows of the array, 9 bit SRLs 120a,122a are selectively serially coupled to SRLs 120,122, and in a parallel fashion to sense amplifiers 116,118. The SRLs 120,122 are in turn coupled to the output logic macrocells ("OLMC") 124,126,128,130,132,134,136,138. The respective OLMC outputs are coupled to respective output drivers 142,144,146,148,150,152,154,156. The 9 bit SRLs 120a,122a are coupled to multiplexor 140. Eight bit buss 160 couples the outputs of the output drivers to multiplexer 140, in turn coupled to the row driver 101. The output drivers are also coupled to output ports P12-P19. Although not active during the normal user mode, the programming row decoder 109 is also illustrated in Figure 3. Figure 5 is a simplified schematic of a typical OLMC 124. In the normal user mode, eight bit buss 125 couples the outputs of eight sense amplifiers associated with eight product terms to the OLMC. One of the sense amplifier outputs (product terms) is applied to one of two inputs to a multiplexer (MUX) 124b. The other input to multiplexer 124b is connected to ground, or logic zero. The output of multiplexer 124b is input to an OR gate 124a, along with the seven other outputs from the sense amplifiers, thus performing the OR logic function on the product terms. The product term that is input to MUX 124b can thus be selectively excluded from the OR logic function. The OLMC allows each device output signal to be individually set to active high or active low, with either combinational (asynchronous) or registered (synchronous) configurations. The signal output from OR gate 124a via XOR gate 124h is input as a combinational input to input 0 of multiplexer (OMUX) 124f and may be registered in flip-flop 124g, the Q output of which is applied to input 1 of multiplexer 124f. Multiplexer (OMUX) 124f selects between the combinational and registered inputs, and provides the selected input signal to an output driver 142 (see also Figure 3). The inverted or Q output from flip-flop 124g is provided to one of four inputs to a multiplexer (FMUX) 124i. A common output enable OE can be connected to all outputs, or separate inputs or product terms can be used to provide individual output enable controls. The common output enable is provided to one of four inputs to a multiplexer (TSMUX) 124d. The other inputs to TSMUX are Vcc; ground; and the product term from buss 125 that is input to MUX 124b. The output of multiplexer 124d is connected to the control input to output driver 142. Thus, when the output of multiplexer 124d is high, output driver 142 is enabled, and it provides a logic signal at bidirectional pin or device terminal P19 which is the output of multiplexer 124f, inverted. When the output of multiplexer 124d is low or a logic zero, output driver 142 is in an "off" or high impedence state. The various configurations of the PLD are controlled by programming bits within the 82-bit architecture control word. Architecture control bit AC0 and the eight AC1 bits direct the output to be wired always-on, by selecting the Vcc input to TSMUX 124d to control output driver 142, always-off (as an input), by selecting the grounded input to TSMUX to control output driver 142, have a common OE term (pin 11), by selecting the OE input to TSMUX to control output driver 142, or to be controlled separately from a product term, by selecting the product term line in buss 125 that is input to MUX 124b to control output driver 142. The architecture control bits also determine the source of the array feedback term output to row driver 124j through multiplexer 124i, and select through multiplexer 124f either combinational or registered outputs. Multiplexer 124i selects one of four inputs and provides the selected signal as a feedback signal to driver 124j. An input signal taken from the device terminal P19 is provided via input line 160 to one of the inputs of multiplexer 124i. Another input to multiplexer 124i is a signal from the previous stage output terminal. Multiplexer 124i is controlled by architecture control bits AC0 and AC1. When the output of multiplexer 124d is low, and therefore output driver 142 is off, data present at pin P19 is available for feedback via line 160 and FMUX 124i. Multiplexer 124i can thus selectively provide, as its output, any one of a signal from P19, a signal from a neighbouring OLMC, or the Q clocked or synchronous output of register 124g, or none of the above by selecting the grounded input. The output of FMUX 124i is provided to row driver 124j for use as a logical input to the associated programmable AND array 102, as shown in Figure 3. The eight XOR bits determine individually each device output polarity, by selectively inverting the signal output from OR gate 124a in XOR gate 124h. The OLMC operation will be apparent to those skilled in the art, and need not be described in additional detail. The PLD illustrated in Figures 3 and 5 is employed in a normal user mode wherein data input/output to the device I/O ports is passed through the device logic paths and operated upon by the particular logic devices which are active, to obtain the desired logic operations on the input signals. PLD AND Array The AND gate array is implemented in a non-volatile reprogrammable EEPROM type technology, which replaces the bipolar type "fuse". The basic cell of the user AND array comprises two transistors, the select and sense transistors; the cell is repeated 2048 times to make up the user programmable "AND" matrix organized as 32 input lines and 64 product terms. Referring now to Figure 7, a simplified schematic of four cells of a product term comprising the subarrays 102,104 is disclosed. Line 233 comprises one of 64 product terms, and line 235 the product term ground line for the product term 233. During the normal user mode, line 235 is the grounded side of the device. In the preferred embodiment, each product term comprises 32 cells coupled in parallel between the product term 233 and the product term ground line 235. Transistors 205,210 comprise one cell 200 coupled to product term 233. Transistor 210 comprises the "select" transistor or gate of the cell. In the normal user mode, the respective select transistors are gated by the input data, and selectively couple the respective sense transistor to the product term ground line. Input driver 215, for example, is gated by an input signal 218, and its true and complement row driver signals on lines 217,216, respectively, drive the gates of select transistors 221,210. Thus, for example, if the input signal on line 218 is high, select transistor 221 will be turned on and select transistor 210 will be turned off. In the device edit mode, the function of the "select" gates in a product term is to isolate predetermined ones of the sense transistors from the high programming voltage. For example, during the edit mode, only one of the 32 cells in a column is to be selected at any given time (except for "bulk" erasing or programming described below, in which the entire array is set to the same state). The selection is accomplished by row decoders 202, one of which is coupled to the gate of each select transistor of each cell. Pins 3-7 and 18 comprise the inputs to the row decoders, and select 1 of the 32 rows to be edited during a particular edit cycle. The second transistor in each cell comprises the data storage (or sense) element for the cell. The transistor comprises an electrically erasable floating gate field effect transistor. The gate threshold turn-on voltage is about +8 volts when the device is in the enhancement mode, and about -5 volts when the device is in the depletion mode. Thus, for cell 200 shown in Figure 7, during normal user operation, with a nominal interrogation voltage (+2.5 vols) on the matrix control gate ("MCG"), the floating gate transistor 205 will conduct when it has been programmed to the depletion mode; when the transistor is operating in the enhancement mode it does not conduct. Thus, during the normal user mode of the PLDs, the state of the sense transistors for each cell determines whether the corresponding input line for that row is coupled to the product term. During the PLD edit mode, the input drivers 215 are disconnected from the array (by switches not shown) by the EDT signal and the row decoders are enabled. On the other hand, during normal PLD operation the row decoders 202 are disabled and have no effect on device operation. The product term 233 is coupled to the input of sense amplifier 250. Amplifier 250 comprises inverters 251,252 and transistors 253-255. Load 256 provides a dc leakage path for the input node 257 of the sense amplifier to ground. The output 258 of sense amplifier 250 is coupled to node 268 of SRL stage 260 by transistor 240, which is gated to the conductive state by the "VERIFY" signal. The product term ground line 235 is coupled to node 271 of SRL stage 260 by transistor 225, which is gated to the conductive state by the "PGM" signal. The SRL stage 260 comprises inverters 263,264,266,267, and transistors 262,265 which are gated to the conductive state by the clock signal "SCLK" and inverted clock signal " SCLK ". Thus, data at the input 261 to the stage 260 will be inverted and propagated to node 269 when SCLK is high; SCLK is low during this time, and transistor 265 is nonconductive. When SCLK goes low, transistor 262 is turned off and SCLK goes high, turning on transistor 265. The input of the stage 260 is then isolated, and the inverted data is propagated through and inverted by inverter 266, so that the data present at node 261 during the clock signal is present at the output node 271. The data is latched at this node, through the operation of inverter 267, so long as transistor 262 is nonconductive. Shift register latches are known in the art; an exemplary reference is the paper entitled "A survey of Design for Testability Scan Techniques," by E.J. McCluskey, in VLSI Design, December, 1984. The product term ground line 235 is also coupled to the column pull-up circuit 280 by transistor 275, which is gated to the conductive state by the "PROGRAM" signal. The pull-up circuit 280 is a high impedance voltage source adapted to generate a programming voltage (nominally +20 volts) high enough to program the floating gate transistors comprising the matrix cells. Such pull-up circuits are known in the art. PLD Device Edit Mode Figure 8 is a simplified block diagram of the PLD when configured in the edit mode. When a super voltage, nominally 20 volts, is applied to pin 2 of the device, a super voltage sense circuit comprising comparator 302 senses the super voltage and issues logic signal "EDT." The pin 2 signal is also coupled to high voltage transfer gate 304, which gates "on" or "off" the programming voltage V PP (20 volts) in dependence on the state of the signals "P/ V " (pin 19) and " STR " (pin 11). As is conventional, pump clock signals ⊘ and ⊘ are internal oscillator outputs which are coupled to diode-capacitor pump circuits to generate high voltages which are used as gate signals to control gate 304 for passing high voltages. The active "EDT" signal also is coupled to the drivers 215, which are tristated by an active "EDT" signal. Thus, application of the super voltage to pin 2 reconfigures the PLD from the normal user mode to the edit mode, with different functions on all pins as shown in Figure 4(b). The inputs to pins 3-7 and 18 serve as the selection bits for the row decoders 109 during the edit mode. In addition V PP is applied to the column pull-up, row decoders and to the matrix control gate generator 306, in dependence on the control bits to gate 304. Like reference numerals are employed in Figure 8 indicate corresponding elements to those shown in Figure 3. Thus, the individual sense amplifiers for each product term are represented by amplifier sections 114,118,116a and 112. The stages of the SRL are grouped in 32 stage SRL section 122, 18 stage SRL section 121 and 32 stage SRL 120. Multiplexers 140a and 140b selectively couple serial data to or around 18 bit SRL section 121, in dependence on architecture logic circuit 310. Thus, the SRL section 121 is bypassed except when row 60 is to be accessed. A "bulk erase" cycle is performed in the edit mode, whereby each of the floating gate transistors of the array cells is programmed into the enhancement mode. To bulk "erase" (or bulk program) the user array cells, a logical "CLR" signal is generated by selecting row 63. Logic circuit 318 is gated by the "CLR" signal and the data at the SDIN port and generates either the bulk erase control signal "BE" or the bulk program control signal "BP,"in dependence on the data at the SDIN port. The CLR signal forces SCLK and SCLK both high, opening up the SRL registers to immediately propagate the data at the SDIN port through all stages of the SRL. This eliminates the need to clock the data through the registers, since the appropriate data of the same logic level are loaded into the SRL. To bulk erase the cells, the appropriate data are loaded into the SRL, and the "MCG" line is raised to +20 volts. The logic signal BE is coupled to the MCG generator 306 to force the MCG signal to +20 volts when BE goes low. A normal programming cycle is then carried out to program all the memory cells to the erased state (enhancement mode). Once the bulk erase cycle is completed, a programming cycle may be carried out. A particular row is enabled, and appropriate data are loaded into the SRL to either enable programming the particular sense transistors to the depletion mode or to inhibit such programming, leaving the particular sense transistor in the enhanced mode. After the SRL has been loaded with data, the "PGM" signal at the gate of transistor 225 may be activated, gating transistor 225 to the conductive state, "PROGRAM" is taken high (+20 volts) to connect the column pull-up to the product term ground. If the data signal at node 271 is low, then the product term ground line 235 is clamped to ground, because the "column pull-up circuit" comprises a high impedance voltage source and cannot supply enough current to raise the voltage level above ground. During the programming cycle, the MCG signal is grounded.. Thus, the selected row cell has a ground potential applied to both the gate and the drain, and no potential is created across the gate/drain to cause tunneling of electrons from the floating gate. As a result, the floating gate transistor of the cell will remain in the enhancement mode. If a "high" data signal is present at node 271 during the edit mode, the product term ground line will not be clamped to ground, and the high (20 volts -V T ) programming voltage from the column pull-up source will be applied to the drain of the selected floating gate transistor. Electrons will tunnel from the floating gate to the drain, programming the transistor to the depletion mode. This program voltage is nominally applied for ten milliseconds, a conventional programming pulse length. To summarize the operation of the array during the programming cycle of the edit mode, the "MCG" signal is grounded, and transistor 225 turned on by a "PGM" signal applied to its gate. Only one of the 32 cells in the product term side has been activated, by application of a select signal to the select transistor to the cell to cause the select transistor to conduct. The data in the SRL is applied to the product term ground line. If the data signal is low, the product term ground line is grounded and the transistor remains in the enhancement mode, requiring an elevated gate voltage level to cause the transistor to conduct. During normal circuit operation, the normal cell interrogation voltage is low enough such that the floating gate transistor will not conduct when in the enhancement mode. On the other hand, if the data signal at node 271 of the SRL stage is "high," then a sufficient field will be impressed across the gate and drain to cause electrons to tunnel from the floating gate to the drain via the 100 Angstrom tunnel oxide, thereby programming the cell to the depletion mode. Programmed Data Verification Another novel aspect of the disclosed PLD is the capability of performing high speed verification of the data stored on the matrix cells. In this verification cycle, the same sense amplifiers used during normal user operation of the device are employed to sense the state of the array cells and to perform a parallel load of the SRL. During this mode, the "VERIFY" signal applied to the gate of transistor 240 (Figure 7) is activated, so that transistor 240 conducts, coupling the output 258 of the sense amplifier 250 to node 268 of the corresponding stage of the SRL. At the same time, the "PGM" and "SCLK" signals are low, so that the stages of the SRL are isolated from each other and from the respective product term ground lines. With the SCLK signal high, the data signal at node 268 is propagated to the output node 271 of the SRL stage. As with the programming cycle, only one cell in each column or product term line of the array is selected at any given time during the verification cycle. Thus, the data contents of an entire selected row of the matrix may be loaded in parallel into the respective SRL stages during the verification cycle. The "VERIFY" signal is then brought low to turn transistor 240 off and isolate the sense amplifiers from the SRL. The contents of the SRL may then be shifted serially out of the SDOUT port (pin 12) of the device for verification, by activation of the SRL clock signal SCLK. The PLD test head is adapted to perform the comparison between the outputted data and the desired data. Logic Verification Another novel feature of the PLD is its logic verification capability, allowing virtually 100% testing capability of the output logic circuits on the device in a non-destructive manner. To carry out the verification, at least one cell in each product term must be conductive. A "bulk program" operation may be employed placing all the floating gate transistors into the depletion mode. This is done by loading appropriate data into the device SDIN port in a manner analogous to that described for the bulk erase cycle. In the disclosed embodiment, row 63 is selected, and all row decoder outputs go high (in a user clear mode) to 20 volts to select all rows; the "MCG" signal is dropped to the ground potential. A normal programming cycle is then carried out. Once the array has been bulk programmed to the conductive or "programmed" state, then "apparent array patterns" are serially loaded into the SRL, by selection of the edit mode as described above for the programming cycle. This desired pattern may be developed to verify a particular logic path through the sense amplifiers and output circuitry. To verify all the logic paths, it will normally be necessary to employ a plurality of apparent array patterns. The device edit mode is then exited by removing the super voltage signal from pin 2, and the logic verification mode is entered. Application of a super voltage to pin 3 of the PLD selects the logic verification mode, and results in activation of the "PGM" signal applied to the gate of transistor 225, such that the transistor becomes conductive, and node 271 of the SRL stage is coupled to the product term ground line 235. To verify the logic paths, it is not necessary to program the array cells with the test bit pattern. Since at least one of the data storage transistors of the cells in a particular product term is in the conductive state, the logic state at node 270 of the SRL will, with transistor 225 in the conductive state, be forced onto the input of the sense amplifier 250. Transistor 240 is turned off in this mode. Thus, by comparing the "apparent array pattern" with the data at the PLD output pin, verification may be obtained of the logic paths. To summarize the sequence of steps for the logic verification, at least one of the sense transistors per product term is programmed to the depletion mode. Then the PLD edit mode is entered, and the SRL is loaded with the desired pattern. Next, the PLD edit mode is exited, and the logic test mode is entered by applying a super voltage to a super voltage pin 3 of the PLD. The logic verification capability also allows functional testing to be conducted after the device has been programmed, and without altering the user data which has been programmed into the array. At least one cell will have been programmed to the depletion mode for each usable product term during the programming cycle. Thus, the apparent bit pattern loaded into the SRL will be propagated through the conductive cell during the logic verification mode, and forced onto the input of the product term sense amplifier. Thus, the ouput logic may be tested, e.g., in the field, without reprogramming the device. Device Waveform Timing Referring now to Figures 9-11, waveform timing diagrams are provided which are illustrative of the signal sequence for loading the SRL programming/verifying the array contents and verifying the operation of the output logic. To load the SRL with data, signal VCC (pin 20) is raised to VCCP, nominally 5 volts (Figure 9(a)). After a time delay T DD to allow the VCC supply to settle, typically 20 microseconds, the device edit mode is entered by raising the EDIT signal applied to pin 2 from zero to VE, the edit/verify supply level, nominally 20 volts (Figure 9(b)). The VCC and EDIT signals are held high during the SRL loading sequence (and during the array program/verify sequence as well.) After the EDIT signal has settled, SDIN data is applied to, the serial data input port for the device in the edit mode (pin 9). The SDIN signal is illustrated in Figure 9(c), and is loaded into the SRL at the clock rate determined by the SCLK clock signal shown in Figure 9(d). The time intervals TD and PWV represent the pulse sequence delay and the verify pulse width ranging from 1 to 10 microseconds, nominally 5 microseconds. Thus, for each clock pulse, one bit of data is loaded into the SRL; Figure 9(c) illustrates the loading of bits N through N+M. Figure 9(e) illustrates the SRL contents being serially unloaded from the device through the serial data output port, pin 12. The data is serially unloaded, with valid data present on the leading edge of the SCLK clock signal as illustrated in Figures 9(d) and 9(e). Serial data bits (N-64) through (N+M-64) are shown in Figure 9(e). Once the SRL has been loaded with the desired data, a selected device array row may then be programmed in accordance with the SRL contents; as illustrated in Figure 10. VCC and EDIT are at their elevated levels, VCCP and VE, respectively (Figures 10(a),(b)). Next, a valid row address RAG0-RAG5 is presented to the row address gate ("RAG") ports (pins 18 and 3-7), to select the row of the matrix to be programmed with the SRL contents. In the edit mode, the matrix may be programmed with data from the SRL (the program cycle) and/or the matrix contents loaded into the SRL for verification (the data verification cycle), in dependence on the state of the "P/ V " control signal presented to pin 19. Figure 10(d) illustrated the P/ V signal in the "program" or high state, and in the inverted "verify" -state, during different time intervals. Once the valid row address has been provided, and the program/verify state determined, then the matrix program step is executed by bringing the STR signal (Figure 10(e)) low for a program pulse width PWp, nominally 10 milliseconds. If the verify state is selected, STR need only be brought to the low state for a nominal verify pulse width of 5 microseconds to load the matrix data onto the SRL stages. Figures 10(d) and 10(c) illustrate the inter-relationship of P/ V and STR for both the data programming and verification sequences. Once the matrix data has been loaded into the SRL, the SRL contents may then be unloaded, after STR is brought to its normal high state to isolate the SRL from the product term sense amplifier. The clocking of data out of the SDOUT port of the device is illustrated in Figures 10(f) and 10(g). The VCC and EDIT signals remain in their high states during this operation. Figure 11 illustrates the signal waveforms during the logic test mode. As shown in Figure 11(a), this mode is selected by raising the LTE signal at pin 3 to +15 volts. The PGM signal goes high (Figure 11(b)), coupling the SRL to the product term ground line 235 though transistor 225. The PROGRAM and VERIFY signals are both low so that the SRL data is forced onto the sense amplifier and the output logic. It is noted that logic circuitry internal to the PLD is adapted to generate the "VERIFY," "PGM" and "PROGRAM" gate control signals applied to the gate of transistors 225,240, and 275 of Figure 7. These signals are determined by the STR , P/ V , RAG signals, VCC and EDIT signals. Thus, for example, to obtain high "PROGRAM" and "PGM" signals requires P/ V to be high and STR to be low. Circuitry to develop the appropriate "VERIFY," "PROGRAM," and "PGM" signals is omitted, for purposes of clarity, as those skilled in the art are readily able to design such circuitry.

Claims: A programmable logic device comprising a plurality of input lines (216,217), a plurality of product terms (233), an array of programmable cells (200) each selectively coupling the respective ones of the input lines to respective ones of the product terms, output logic circuits (124) coupling the product terms to device terminals (P19), a plurality of sensing means (250), one each coupled to a respective one of the product terms for sensing the logic state of the product term (233) and providing to output logic circuits a logical sense signal indicative of said logic state; and the output logic circuits (124) being responsive to the respective sense signals for providing device logic output signals at one or more device terminals (P19), in which the output logic circuits each include: an output driver (142) having an input coupled to a subset of the product term lines and an output coupled to the device terminal, the output driver being responsive to a control logic signal for operating in one of a first mode in which the output driver provides an output logic signal to the device terminal and a second mode in which the output driver presents a high impedance to the device terminal for configuring the logic device to receive data externally applied at the device terminal; characterized in that the output logic circuit further includes: a first multiplexer (124d) having at least two input terminals, including a first input terminal coupled to a predetermined one of the product term lines to receive a product term signal and a second input terminal coupled to receive a predetermined logic signal, and having an output terminal coupled to provide the control logic signal to the output driver; and means (60) for controlling the first multiplexer to selectively provide one of the product term signal and the predetermined logic signal to the output driver as the control logic signal. A device according to claim 1, including: a combinatorial logic means (124a) having a plurality of input terminals coupled to a subset of the product term lines to receive a corresponding subset of the product term signals and having an output terminal for providing a combined logic signal that is a predetermined logical function of the subset of product term signals; a second multiplexer (124b) having at least two input terminals, including a first input terminal coupled to a predetermined one of the subset of product term lines to receive a corresponding one of the product term signals and a second input terminal coupled to receive a second predetermined logic signal, and having an output terminal coupled to one of the input terminals of the combinatorial logic means; and means (60) for controlling the second multiplexer to select one of the predetermined product term signal and second predetermined logic signal for input to the logic means so that the predetermined product term signal can be selectively included among the signals input to the logic means. A device according to claim 2, wherein the combinatorial logic means includes a logic OR gate and the predetermined logic signal is a logical zero signal. A device according to claim 2 or 3, in which: the output terminal of the first multiplexer (124d) provides a first control signal; and the output terminal of the second multiplexer (124b) provides a second control signal. A device according to any of claims 1 to 4, in which: the combinatorial logic means (124a) is coupled to receive as input signals all except the predetermined one of the product term logic signals for providing a logic signal that is a predetermined logical combination of the input signals. A device according to claim 5, including means for programming an output architecture control bit (ACO) and wherein the second multiplexer is responsive to the output architecture control bit. A device according to any of claims 1 to 6, in which the output logic circuits include: an additional multiplexer (124i) having at least two inputs, including a first input coupled to a first one of the device terminals to receive a first logic signal present at the first device terminal and a second input coupled to a second one of the device terminals to receive a second logic signal present at the second device terminal, and having an output terminal; means (60) for controlling the additional multiplexer to present at its output terminal a selected one of the first and second logic signals as a feedback logic signal; and means (124j) for coupling the feedback logic signal to at least one of the input lines of the logic device. A device according to claim 7, further including means for programming an output architecture control bit; and wherein the means for controlling the additional multiplexer is responsive to the output architecture control bit. A device according to claim 7 or 8, in which the said additional multiplexer has an input providing feedback from a previous output logic circuit stage. A device according to claim 7, 8 or 9, in which the said additional multiplexer also has a hard-wired zero input. A device according to any of claims 1 to 10, including a further multiplexer (124f) having an output coupled to the output driver (142) and two signal inputs, the output driver taking the form of a tristate circuit for controlling the polarity of the signal at the said device terminal.

Inventors: RUTLEDGE DAVID L, TURNER JOHN E, RUTLEDGE, DAVID L., TURNER, JOHN E.
Applicants: LATTICE SEMICONDUCTOR CORP, LATTICE SEMICONDUCTOR CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H03K19, G01R31