SYSTEM FOR CONTROLLING THE SPEED OF AN ELECTRIC MOTOR

Abstract: The system comprises two counters (1 and 2) which rece­ ive counting pulses from an oscillator (5) and control pulses from a tachogenerator (11). The first counter (1) is reset by a tacho-pulse and counts to a predetermined maximum value. The counting direction of the second counter (2) is reversed both when a tacho-pulse appears and when the pred­ etermined fixed value is reached by the first counter (1). The control signal for the motor is obtained by comparing the count of the second counter (2) with a reference value (R) in a comparator (14) to derive an on-off signal.

Description: The invention relates to a system for controlling the speed of an electric motor which is controlled by a control signal via an energising circuit, comprising an oscillator which supplies a first pulse train whose frequency depends on the desired speed, a first counter whose clock-pulse input is connected to the oscillator output, which counter counts up to a predetermined value and stops counting when said value is reached, a second counter whose clock-pulse input is connected to the oscillator output and which starts counting as soon as the first counter supplies a signal when said predetermined value is reached, means for producing a second pulse train whose frequency depends on the motor speed, which second pulse train is applied to the first counter to restart said counter, when a pulse appears, to count from a specific initial count to said predetermined value and which pulse train is applied to the second counter to stop the counting process in said second counter when a pulse appears, decoding means to which the output signals of the second counter are applied to generate a control signal for the energising circuit. Such a system is described in British Patent Specification 1,366,971. In fact this known system measures the entire interval between the successive pulses of the second pulse train, the tachometer-pulse train, by allowing the first counter to count up to a fixed value and subsequently starting the second counter, which then counts for the remainder of the interval. The count reached by the second counter is subsequently compared with the count of the first counter. If the count of the second counter is too low or too high a corresponding signal is applied to the motor energising circuit. In this known system a complex decoding circuit is required for deriving the control signal from the counts of the two counters. It is an object of the invention to provide a system of this type such that the generation of the control signal can be realized simply. Further, the known circuit is comparatively insensitive to slight variations in motor speed. The decoding means do not respond until the count of the second counter differs at least one bit from the count of the first counter which is used for this comparison. Therefore, it is another object of the invention to obtain a steep control characteristic in such a way that the system also responds rapidly to small deviations. According to the invention, in order to achieve these goals, a system of the type defined in the opening paragraph is characterized in that the second counter is a bidirectional counter which counts in one direction in the interval between the instant at which the first counter reaches the predetermined value and the occurrence of a pulse in the second pulse train and which counts in the other direction in the intervening intervals, and in that the decoding means are constructed as a comparator for continuously comparing the count of the bidirectional counter with a reference value and which comparator supplies a signal of a first level during the time intervals the refervence value exceeds the count of the second counter and a signal of a second level during the time intervals the reference value is smaller than the count of the second counter. Embodiments of the invention will now be described in more detail, by way of example, with reference to the accompanying drawings. Fig. 1 is a block diagram of a system in accordance with the invention. Fig. 2 shows signal waveforms and curves to explain the operation of the system shown in Fig. 1 in the situation in which the motor speed is within the control range. Fig. 3 shows signal waveforms and curves to explain the operation of the system shown in Fig. 1 in the situation in which the motor speed is much too high. Fig. 4 shows signal waveforms and curves to explain the operation of the system of Fig. 1 in the situation in which the motor speed is much too low. Fig. 5 shows the control characteristic of the system in accordance with the invention. Fig. 1 shows a system embodying the invention. The system comprises a counter 1 which receives clock pulses from an oscillator 5 via a line 4. The frequency of these clock pulses governs the nominal speed of the motor 12. Further, it comprises a counter 2 which also receives clock pulses from the oscillator 5 via a line 6. The counter 1 counts up to a predetermined count and when this count is reached it supplies a signal to a control unit 3 via a line 16. In response thereto the control unit supplies a signal to the counter 1 via a line 7 to stop and, when necessary, reset this counter, and it also supplies a signal to the counter 2 via a line 9 to change the counting direction of this counter. The control unit 3 further receives a signal from a tachogenerator 11 via a line 10, which signal has a frequency which is proportional to the speed of the motor 12. Every time that an edge occurs in the tachogenerator signal the control unit 3 supplies a signal to the counter 1 to start a new counting cycle and a signal to the counter 2 to reverse the counting direction. In a comparator 14, the instantaneous count of the counter 2 is continuously compared with a reference value (R) stored in a register or memory 15. If the reference value exceeds the count, the comparator supplies a signal of a first level and if the reference value is smaller than the count the comparator supplies a signal of a second level. This output signal of the comparator is applied to the energizing circuit 13, which in its turn supplies the motor control signal to the motor 12. Hereinafter the operation of the arrangement will be described with reference to the diagrams in Figs. 2, 3 and 4. Fig. 2 serves to illustrate the operation of the circuit in the case that the motor speed is within the control range. At a the signal from the tachometer 11 is shown, whose frequency is proportional to the speed of the motor 12. At b the variation of the count of the counter 1 is represented schematically. At each edge in the tachometer signal the counter 1 is started from a fixed initial value and counts until a predetermined final value is reached. When this final value is reached the counting process is stopped. The counter 2 is also started to count in one direction at every edge of the tachometer signal, as is illustrated at c in Fig. 2. As soon as the counter 1 has reached its predetermined final count the control unit 3 reverses the counting direction of the counter 2 and the counter 2 counts in the other direction until the next edge in the tachometer signal occurs. When the final count is reached the counter 1 may remain at this count to be reset at the next edge of the tachometer signal or it may be reset directly when its predetermined final count is reached. The broken line (R) in Fig. 2c schematically represents the reference value stored in the register 5. As is shown in Fig. 2d the comparator 14 supplies a squarewave signal resulting from the comparison between this reference value and the count of the counter 2, which squarewave signal may be used directly for controlling the motor. The motor is energized during the positive or high portions (h) of this squarewave signal and is not energized during the negative or low portion (L) of this squarewave signal. If the speed of the motor increases the distance between the edges of the tachometer signal will decrease. Since the interval in which the counter 2 counts up remains the same the interval in which the counter 2 counts down becomes smaller, with the result that, as will be evident from Fig. 2, the count of the counter 2 increases gradually relative to the reference value. A consequence of this is that the comparator supplies a squarewave signal whose positive or high portions become increasingly shorter and whose negative or low portions become increasingly longer. As a result of this, the energisation of the motor 12 is reduced to compensate for the increase in speed. Conversely, if the speed of the motor decreases the distance between the edges of the tachometer signal will increase. Since the interval in which the counter 2 counts up remains the same the interval in which the counter 2 counts down becomes longer with the result that, as will be evident from Fig. 2c, the count of the counter 2 now gradually decreases relative to the reference value. As a result of this, the comparator supplies a squarewave signal whose positive or high portions become gradually longer. As a result of this, the motor 12 receives a more powerful energisation to compensate for the decrease in speed of the motor 12. Fig. 3 shows some signal waveforms and curves to illustrate the situation in which the motor speed is too high, which situation occurs for example after a variation of the frequency of the oscillator 5. The tachometer signal is again shown at a and the count of the counter 1 at b . Since the interval in which the counter 1 counts and the counter 2 counts up is longer than the interval in which the counter does not count and the counter 2 counts down, the count of the counter 2 will increase comparatively rapidly until the maximum count of the counter 2 is reached. Now a situation occurs in which, as is shown at line c , the counter 2 counts down and subsequently, together with the counter 1, counts up until the maximum count is reached. However, in all cases the count of the counter 2 remains higher than the reference value in the register 15, so that the comparator 14 will constantly supply a low signal. Therefore, the motor 12 is not energised so that the speed will decrease until the system has come within the control range and operates as described with reference to Fig. 2. Fig. 4 shows some signal waveforms and curves illustrating the situation in which the motor speed is too low, which situation occurs for example after a variation of the frequency of the oscillator 5. Again the tachometer signal is represented at a and the count of the counter 1 at b . Since the interval in which the counter 1 counts and the counter 2 counts up is shorter than the interval in which the counter 1 does not count and the counter 2 counts down, the count of the counter 2 will decrease comparatively rapidly until the minimum count of the counter 2 is reached. Then a situation is obtained in which, as is illustrated at line c , the counter 2 each time counts up together with the counter 1 and subsequently counts down until the minimum count is reached again. However, the count of the counter 2 remains below the reference value in all cases so that again the comparator 14 constantly supplies a high signal. Therefore, the motor 12 is constantly energised so that the speed increases until the system has come within the control range and operates as described with reference to Fig. 2. Fig. 5 shows the control characteristic of the system in accordance with the invention. The speed is plotted along the horizontal axis and the pulse width (B) of the comparator output signal along the vertical axis. If the speed is too low the pulse widthis 100%, inother words the motor is energised continuously. If the speed is too high the pulse width of the comparator output signal is 0%, in other words the motor is not energised. In the control range the pulse width varies depending on speed variations relative to the desired speed S in a manner as described with reference to Fig. 2. It will be evident that even a very small deviation of the speed will lead to a gradual increase or decrease of the count of the counter 2 after one or more counting cycles , to which the comparator responds by varying the on/off ratio of the motor control signal, to compensate for these variations. Suitably, the predetermined value up to which the counter 1 counts is selected in such a way that this value is reached at least approximately halfway between two edges in the tachometer signal. In that case the intervals in which the counter 2 counts up and counts down are equally long and the counter 2 will not reach one of its limit values. Also if another choice is made for said predetermined values and the reference value in the register 15 is adapted thereto the system will operate in the manner described, as will be evident to those skilled in the art. Further it will be evident from the foregoing that the output signal of the comparator can be used directly for controlling the motor 12. This means that the energising circuit 13 need only comprise an amplifier circuit which is capable of delivering enough energy to energise the motor 12. The waveform of the input signal of the energising circuit 13 is identical to the waveform of its output signal. If the comparator 14 itself is capable of delivering enough power, the energising circuit 13 may be constituted merely by a direct connection from the output of the comparator 14 may be coupled directly to the motor 12. A broken line 16 in Fig. 1 represents a possible connection between the input terminal of the motor 12 and the clock pulse generator 5. Depending on the practical construction of the circuit it is possible that the amplitude of the output signal of the energising circuit 13 or the comparator 14 varies, for example as a result of supply-voltage variations. Such amplitude variations directly influence the speed of the motor 12. In order to eliminate such variations the control signal for the motor 12 (if necessary after rectification) may be fed back to the clock-pulse generator 5. The clock-pulse generator 5 may be of a known voltage-controlled type and respond to the (rectified) control signal from the energising means 13 or the comparator 14 in such a way that a decrease in amplitude of the control signal results in a decrease of the clock-pulse frequency of the generator 5 and an increase in amplitude of the control signal results in an increase of the clock-pulse frequency so as to compensate for amplitude variations by frequency variations. The above-description should allow those skilled in the art to realise the system in practice, for which reason no further details of the circuit are given. It is to be noted that the present system can be formed almost wholly by means of digital components and is therefore very suitable to be integrated. The functions of the counter 1, the counter 2, the control unit 3, the comparator 14 and the register 15 can also be realised readily by means of a suitably programmed processor. If the internal clock-pulse generator of the selected processor is stable enough this generator may be used as the generator 5.

Claims: A system for controlling the speed of an electric motor (12) which is controlled by a control signal via an energising circuit (13), comprising an oscillator (5) which supplies a first pulse train whose frequency depends on the desired speed, a first counter (1) whose clock-pulse input is connected to the oscillator output and which counts up to a predetermined value and stops counting when said value is reached, a second counter (2) whose clock-pulse input is connected to the oscillator output and which starts counting as soon as the first counter (1) supplies a signal when said predetermined value is reached, means (11) for producing a second pulse train whose frequency depends on the motor speed, which second pulse train is applied to the first counter (1) to restart said counter, when a pulse appears, to count from a specific initial count up to said predetermined value and which pulse train is applied to the second counter to stop the counting process in said second counter (2) when a pulse appears, decoding means (14) to which the output signals of the second counter are applied to generate a control signal for the energising circuit (13), characterized in that the second counter (2) is a bidirectional counter which counts in one direction in the interval between the instant at which the first counter reaches the predetermined value and the occurrence of a pulse in the second pulse train and which counts in the other direction in the intervening intervals and in that the decoding means (14) are constructed as a comparator (14) for continuously comparing the count of the bidirectional counter (2) with a reference value, which comparator supplies a signal of a first level during the time intervals the reference value exceeds the count of the second counter (2) and a signal of a second level during the time intervals the reference value is smaller than the count of the second counter (2). A system as claimed in Claim 1, characterized in that the predetermined count is selected in such a way that the interval in which the first counter (1) counts is at least substantially equal to the following interval until the appearance of the next pulse in the first pulse train. A system as claimed in Claim 1 or 2, characterized in that the counting range of the second counter (2) lies between predetermined maximum and minimum values and when these values are reached the counting process is reversed, said values being selected in such a way that they are not reached if the instantaneous speed is fully or almost fully in conformity with the desired speed. A system as claimed in any one of the preceding Claims, characterized in that a signal (16) corresponding to the amplitude of the output signal of the comparator (14) is applied to the oscillator (5) to increase or reduce the frequency of this oscillator (5) when the amplitude decreases or increases respectively. A system as claimed in any one of the preceding Claims, characterized in that the reference value is selected halfway between said maximum and minimum value of the second counter (2). A system as claimed in any one of the preceding Claims, characterized in that the functions of the first counter (1), the second counter (2) and the comparator (14) are realised by means of a suitably programmed processor.

Inventors: GEVEN, WILLEM JOHANNES ANTONIA
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1986
Main classification: G05D13
IPC codes: H02P29, H02P23