GATE ARRAY

Abstract: An integrated circuit device having a chip com­ prises : cell arrays consisting of a plurality of cells, the cells comprising impurity introduction regions (l5, l7) respectively, and conductive lines (V SS , V DD ) selec­ tively formed between the cell arrays and embedded in the substrate together with the cell array ; the embedded conductive lines (V SS , V DD ) being selectively connected to the impurity introduction regions (l5, l7), and an insulating layer being formed on the embedded conductive lines, and wiring (l8) selectively connecting a plurality of cells being formed on the insulating layer.

Description: 1. Field of the Invention The present invention relates to a gate array integrated circuit device, more particularly to a gate array in which a plurality of cell arrays having a plurality of cells formed therein in an array are arranged. 2. Description of the Related Art In a conventional LSI chip such as a gate array, etc., for example, in the case of a complementary LSI such as a complementary MOS (CMOS), etc., pairs of a p-channel device formation region and an n-channel device formation region are repeatedly formed on the same chip, and a wiring region (WR) is provided between the pairs regions. In the p-channel device formation region, for example, a p-channel MOS transistor is formed, and in the n-channel device formation region, an n-channel MOS transistor is formed. An active layer, etc., is not formed on the semiconductor substrate at the wiring region but the wiring is covered by an insulating layer. Further, the power source lines of the chips are usually provided in an upper wiring layer. In the prior art, however, a power source line is provided in such a manner that it spans a device formation region and a wiring region, and thus the wiring efficiency is lowered and an improvement of the miniaturization of device can not be realized. An object of the present invention is to provide an integrated circuit device having a chip wherein the layout efficiency on a semiconductor substrate can be improved. Another object of the present invention is to provide an integrated circuit device having a chip wherein the electromigration effect of a power source line can be suppressed, resulting in an improvement of the responsitivity of a gate array. According to the present invention there is provided a gate array on a semiconductor substrate comprising: cell arrays consisting of a plurality of cells, the cells comprising impurity doped regions respectively; conductive power source lines of a metal material selectively formed between the cell arrays and embedded in the substrate together with the cell arrays, the embedded conductive lines being selectively connected to the doped regions; and an insulating layer formed on the embedded conductive lines and on wiring embedded in the substrate and selectively connecting the plurality of cells. Further advantages and details of the present invention will be explained with reference to the accompanying drawings in which: Fig. 1 is a schematic view of a conventional complementary LSI cell array; Fig. 2 is a schematic view of another example of a conventional cell array; Fig. 3 is a schematic view of still another example of a conventional cell array; Fig. 4 is a schematic view of a complementary LSI cell array and wiring region (WR) pattern according to the present invention; Fig. 5A is a cross-sectional view of a main portion of an LSI chip according to the present invention; Fig. 5B is a top plan view of Fig. 5A; Fig. 6A is a detailed plan view of another example of the present invention; Fig. 6B is a cross-sectional view taken along the line AA′ in Fig. 6A; Fig. 6C is a cross-sectional view taken along the line BB′ in Fig. 6A; Fig. 7A is a cross-sectional view of a main portion of another LSI chip according to the present invention; and, Fig. 7B shows the equivalent circuit of the chip portion of Fig. 7A. To enable a better understanding of the present invention, a description of the prior art will be first given. Figure 1 is a schematic view of a conventional complementary LSI cell. In Fig. 1, pairs of a p-channel (p-ch) device formation region and an n-channel (n-ch) device formation region are repeatedly formed on a chip 1. A wiring region (WR) in which a gate-forming wiring is formed is provided between the p-ch device formation region and the n-ch device formation region. Further, a wiring layer connecting gates is formed in the WR. Although not shown in the figure, an active layer is not formed on the semiconductor substrate of the chip 1, and only an insulating layer is formed on the WR. Further, a power source line for the chip 1 is usually provided on the upper portion of the WR. This power source line is connected to the lower portion of the WR, through a through hole, or to devices. Since, as described above, the power source line spans the device formation region and the WR, the wiring efficiency and the degree of the integration of the LSI chip are lowered. Japanese Unexamined Patent Publication (Kokai) No. 59-163837 discloses a semiconductor integrated circuit comprising a plurality of cell arrays with electric elements and power source lines positioned between the cell arrays but not embedded in a chip. Figure 2 is a schematic view of the cell arrays and the pattern of the power source lines disclosed in Japanese Unexamined Patent Publication No. 59-163837. In Fig. 2 n-ch denotes an element region including a plurality of n-channel MOS, and p-ch denotes an element region including a plurality of p-channel MOS; V SS and V DD are power source lines. Pairs of n-ch and p-ch are formed on each side of the V SS or V DD respectively, but the power source line is not used as a connecting layer which connects the same type of channels to each other. Japanese Unexamined Patent Publication (Kokai) No. 60-233838 discloses a semiconductor integrated circuit device comprising a plurality.of cell arrays and a power source line and wiring region positioned between the cell arrays, as shown in Fig. 3, but the power source lines, V DD , GND) are not embedded in a substrate and do not create a contact between the cells (p-ch, n-ch). Figure 4 is a schematic view of complementary cell arrays and wiring channel region (WR) patterns according to the present invention. In Fig. 4, on a chip 1 of a semiconductor substrate, pairs of a p-channel (p-ch) device formation region and an n-channel (n-ch) device formation region are formed each side of the wiring channel region (WR). An isolation region (ISO) is formed between the n-channel and p-channel device formation regions. The V SS and V DD lines (not shown) are embedded in the WR in the chip 1, and at the same time, are connected to the n-channel and p-channel device formation regions. Figure 5A is a cross-sectional view of a main portion of a LSI chip and Figure 5B is an upper plan view thereof. In Fig. 5A, an n-ch MOS transistor 26 is formed on an n-ch device region in a p type semiconductor substrate 21, and p-ch MOS transistors 24 and 25 are formed on a p-ch device region. Further, a groove H1 is formed between the n-ch MOS transistor 26 and another n-ch MOS transistor (not shown) adjacent thereto. In the groove H1, a power source line V SS is formed, which is embedded in an insulating layer 27. Further, on the insulating layer 27, an insulating film INS is formed so that a wiring channel region WR1 (Fig. 5B) is constituted. A groove H2 is formed between the p-ch MOS transistors 24 and 25. In the groove H2, a power source line V DD is formed, which is embedded in an insulating layer 29. Further, on the insulating layer 29, an insulating film INS is also formed so that a wiring channel region WR2 is constituted. These power source lines V DD V SS and are made of A1, etc. The conductive line may be substantially flattly embedded in the groove. Further an n⁺ layer 22 is provided beneath the power source line V DD so that any leakage of current to the p type semiconductor 21 is prevented. Furthermore, grooves h1 and h2, having a width narrower than that of the above grooves H1 and H2, are formed between the n-ch MOS transistor 26 and the p-ch MOS transistor. Insulating films 28 and 30 are embedded in the grooves h1 and h2, to form an element isolation region ISO. In the structure of the present invention, a wiring channel region is formed to a width of, for example, 100 µm. Accordingly, the power source line formed under the wiring channel region can be widely formed, and thus defects such as electromigration, etc., can be prevented. In Fig. 5A, when the gate 26G of the n-ch MOS transistor 26 is connected to the gate 25G of the p-ch MOS transistor, to form an input terminal IN therebetween, and a drain of the n-ch MOS transistor 26 is mutually connected to the drain of the p-ch MOS transistor 25 by an electrode 31 to form an output terminal OUT, a CMOS inverter is constituted. Figure 6A is a detailed plan view of another example of the present invention, Figure 6B is a cross-sectional view taken along a line AA' of Fig. 6A, and Figure 6C is a cross-sectional view taken along a line BB' of Fig. 6A. In the plan view of Fig. 6A, for clarity, the impurity doped region and the conductive line portions, and the insulating layers formed thereon, are omitted. As shown in Figs. 6B and 6C, power source lines V SS and V DD are embedded in a substrate together with the cell array. The V SS and V DD lines are selectively connected to an n-type impurity region in the substrate, and the V SS and V DD lines are covered by an insulating layer. Further, above the insulating layer, a wiring (WR3) for connecting cells is formed. In Fig. 6A, reference numerals 12, 13 and 14 denote a p⁺ impurity doped region to be connected to V SS , an n⁺ impurity doped region to be connected to V SS , and an insulating layer, respectively. In Fig. 6B, reference numerals 15, 16, 17 and 18 denote a p⁺ type silicon substrate, an insulating layer, an n⁺ impurity doped region (buried layer), and a wiring layer, respectively. The structure shown in Figs. 6A, 6B, and 6C can be formed by the following method. First, an n⁺ type buried layer 17 is formed in an intended p-ch transistor formation region, and a wiring channel formation region adjacent thereto, in a p⁺ type semiconductor substrate 15. Then an n-type epitaxial growth layer is formed on the substrate 15. Next, a groove for forming an insulation region 16 isolating an intended p-ch transistor formation region and an intended n-ch transistor formation region, a groove for forming a power source line V SS which reaches the p⁺ type semiconductor substrate, and a groove for forming a power source line V DD which reaches the n⁺ buried layer 17, are formed. Afterwards the power source lines V SS and V DD are embedded in the desired grooves, the V SS and V DD being flatly covered by an insulating or conductive polycrystalline silicon film. In this case, an insulating polycrystalline silicon film may be flatly embedded in the groove for forming the insulation region at the same time or other. Then a p type impurity is partially introduced to the intended n-ch transistor formation region to form a p type region, and n type impurities are introduced to the surface of the p type region to form n⁺ type impurity doped regions, which become source and drain regions of the n-ch transistor and are formed in such a manner that they are selectively connected to the embedded power source line V SS . A p type impurity is partially introduced into a surface of the n type epitaxial growth layer in an intended p-ch transistor formation region to form p⁺ type impurity doped regions, which become source and drain regions of the p-ch transistor and are formed in such a manner that they are selectively connected to the embedded source line V DD . Then, an insulating film is formed on the surface of regions wherein power source lines V SS and V DD are formed, so that a gate insulating film is formed on the intended n-ch transistor formation region and the intended p-ch transistor formation region. Subsequently, a gate electrode of polycrystalline silicon is formed on the gate insulating film so that a basic cell consisting of a n-ch transistor and a p-ch transistor is realized. Then, to obtain desired logic circuit, multilayer wiring 18 of, for example, A1, in the basic cell or between a plurality of basic cells is formed in an insulating layer provided therebetween. Then, wiring connecting a plurality of basic cells is provided in the wiring region (WR) in which the power source lines V SS and V DD are embedded. Figure 7A is another example of the present invention, wherein the present invention is applied to a Bi-MOS-LSI. Figure 7A is different from Fig. 5A in that a structure in an n-ch, p-ch device region forms a Bi-MOS structure, an n-ch MOS transistor designated by QMOS 1 and a pnp transistor designated QBi 1 are formed on an n-ch device region, and a p-ch MOS transistor designated by QMOS 2 and an npn transistor designated by QBi 2 are formed on a p-ch device region. The arrangement of the wiring channel region WR, n-ch device region, p-ch device region, and isolation region ISO between the n-ch device region and the p-ch device region is the same as in the case of Figs. 5A and 5B. Figure 7B is a view of an equivalent circuit of the wiring portion of Figure 7A. As described above, according to a constitution of the complementary LSI chip of the present invention, the power source line of the LSI chip is embedded in a groove provided in a semiconductor substrate, below a wiring channel region, whereby a channel wiring alone can be provided on the substrate. Therefore, the layout efficiency on a chip surface can be improved, which greatly contributes to an improvement of the degree of integration of the LSI. Additionally, in the present invention, the width of the power source line is widely formed, and thus wiring defects such as electromigration can be prevented.

Claims: A gate array on a semiconductor substrate comprising : cell arrays consisting of a plurality of cells, said cells comprising impurity doped regions (12, 13, 17) respectively; conductive power source lines (V SS , V DD ) of a metal material, selectively formed between the cell arrays and embedded in the substrate (15) together with the cell arrays, said embedded conductive lines being sclectively connected to said doped regions; an insulating layer (INS) formed on the embedded conductive lines; and wiring (WR) selectively connecting a plurality of cells formed on the insulating layer. A gate array according to claim 1, wherein said cell arrays are formed along said conductive lines. A gate array according to claim 1, wherein said substrate (15), having one conductive type, has an opposite conductive type buried layer (17) selectively provided therein, first and second cells arrays respectively consisting of MOS transistors of said one conductive type are provided in parallel to each other in the buried layer (17), one (V DD ) of said conductive lines extending along the first cell array and the second cell array therebetween, said conductive line being connected to said buried layer (17) and a reverse bias being supplied to the pn junction formed by said buried layer (17) and substrate (15), the latter being connected to the other conductive line (V SS ). A gate array according to claim 1, wherein it constitutes a MOS LSI. A gate array according to claim 1, wherein it constitutes a complementary MOS LSI. A gate array according to claim 1, wherein it constitues a complementary MOS or Bipolar MOS LSI.

Inventors: TANIZAWA, TETSU
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H01L27
IPC codes: H01L23, H01L21, H01L27