SEMICONDUCTOR NON-VOLATILE MEMORY

Abstract: A semiconductor non-volatile memory comprises a semiconductor substrate (1) of a first conductivity type, source and drain regions (2,3) of a second conductivity type formed on a surface of the semiconductor substrate in such a manner as to be spaced apart from each other and a floating gate electrode (5) formed on the surface of a portion of the semiconductor substrate between the source and drain regions through a gate insulator film (4). An erasing electrode (8) is provided in opposing relation to the floating gate electrode through a first tunnel insulator film (7). A writing electrode (10) is provided in opposing relation to the floating gate electrode through a second tunnel insulator film (9).

Description: This invention relates to semiconductor non-volatile memories, for example, for use in computers and office automation machines, etc. The present invention seeks to provide a semiconductor non-volatile memory for use in computers etc., wherein an erasing electrode and a writing electrode are provided around a floating gate electrode through respective tunnel insulator films, thereby improving the reliability of the semiconductor non-volatile memory. Semiconductor non-volatile memories are widely used in computers etc. since they are smaller in size than other types of memory and enable high-speed reading. Figure 2 is a sectional view of a general electrically erasable and programmable non-volatile memory (hereinafter referred to as an "EEPROM"). On the surface of a P-type semiconductor substrate 11, N⁺-type source and drain regions 13 are formed, and a floating gate electrode 15 is provided thereon through a gate insulator film 14. A control gate electrode 16 is provided for controlling the potential of the floating gate electrode 15 through an insulator film 102. The transfer of electric charge in relation to the floating gate electrode 15 is effected through a tunnel oxide film 17 provided on the drain region 13. For example, in the case where the thickness of the tunnel oxide film 17 is about 200Å (1nm = 10Å), when a voltage which is 20V higher than the potential of the drain region 13 is applied to the control gate electrode 16, a strong electric field is applied to the tunnel oxide film 17, causing electrons to flow from the drain region 13 into the floating gate electrode 15. To make electrons flow out of the floating electrode 15 into the drain region 13 in the reverse direction, it suffices to apply a voltage to the drain region 13 which voltage is 20V higher than the potential of the control gate electrode 16. Since the channel conductance between the source and drain regions under the floating gate electrode 15, which serves as a gate electrode, changes in accordance with the amount of electric charge accummulated in the floating gate electrode 15, it is possible to read out data. An example of this kind of semiconductor non-volatile memory is disclosed in US-A-4,203,158. Non-volatile memories with separated erasing and writing electrodes are known from EP-A-0 035 160 and US-A-4 099 196. In EP-A-0 052 982 erasing electrode arrangement as used in the present invention is disclosed. In the case of an EEPROM such as shown in Figure 2 in which a strong electric field is applied to a tunnel oxide film to write data, the strong electric field leads to wear and deterioration of the tunnel oxide film, so that repetitive rewriting results in breakdown of the EEPROM. The deterioration of a tunnel oxide film due to wear has been examined carefully, and it has been found that wear is dependent upon direction of the applied electric field. The results of the examination are given in Figure 3 which shows tunnel current with respect to the electric field E ox applied to a tunnel oxide film. Breakdown takes place at a smaller current value when electrons are made to flow out of a floating gate electrode (when +20V is applied to the drain region; +V D ). In other words, it may be considered that breakdown occurs in an EEPROM such as that shown in Figure 2 when it is in an erasing mode (when electrons are made to flow out of the floating gate electrode). On the basis of this fact, the occurrence of breakdown of a semi conductor non-volatile memory according to the present invention due to rewriting is reduced or prevented by providing erasing and writing electrodes separately from each other. By providing the erasing and writing electrodes separately from each other, the direction in which electrons flow through each of two tunnel insulator films is limited to only one direction. According to one aspect of the present invention there is provided a semiconductor non-volatile memory comprising: a semi-conductor substrate of a first conductivity type; source and drain regions of a second conductivity type formed in the surface of said semiconductor substrate in such a manner as to be spaced apart from each other; a floating gate electrode formed on the surface of a portion of said semiconductor substrate between said source and drain regions through a gate insulator film; an erasing electrode provided in opposing relation to said floating gate electrode through a first tunnel insulator film; and a writing electrode provided in opposing relation to said floating gate electrode through a second tunnel insulator film, characterised in that the portion of the floating gate electrode opposing the erasing electrode through the first tunnel film is provided above the erasing electrode The positional relationship between said erasing electrode, said writing electrode and said floating gate electrode may be arranged in order to maximise the breakdown current value of each of said first and second tunnel insulator films. In one embodiment the writing electrode is provided above the floating gate electrode through the second tunnel insulator film. According to another aspect of the present invention there is provided a semi-conducdtor non-volatile memory comprising: a semiconductor substrate of a first conductivity type; a writing electrode of a second conductivity type formed in the surface of said semiconductor substrate; and a floating gate electrode formed on the surface of a portion of said semiconductor substrate which is located between source and drain regions through a gate insulator film, and provided in opposing relation to said drain region through a first tunnel insulator film, characterised by an erasing electrode provided in opposing relation to said floating gate electrode through a second tunnel insulator film. The invention is illustrated, merely by way of example, in the accompanying drawings, in which:- Figure 1 is a sectional view of one embodiment of a semi-conductor non-volatile memory according to the present invention; Figure 2 is a sectional view of a conventional semiconductor non-volatile memory; Figure 3 is a chart showing electric characteristics of a tunnel oxide film on N⁺-type single crystal silicon; Figure 4 is a chart showing electric characteristics of a tunnel oxide film on polysilicon employed in a semiconductor non-volatile memory according to the present invention; and Figure 5 is a sectional view of a second embodiment of a semiconductor non-volatile memory according to the present invention. Referring first to Figure 1, a semiconductor non-volatile memory according to the present invention has, on the surface of a P-type semiconductor substrate 1,N⁺-type source and drain regions 2,3. A floating gate electrode 5 is provided through a gate insulator film 4 on a channel region between the source and drain regions. In addition, a control gate electrode 156 is provided above the floating gate electrode 5 through an insulator film 101. An erasing electrode 8 for causing electrons to flow out of the floating gate electrode 5 is provided below the floating gate electrode through a tunnel oxide film 7. A writing electrode 10 is provided above the floating gate electrode 5 through a tunnel oxide film 9. To effect writing (i.e. to inject electrons into the floating gate electrode 5), a writing voltage is applied to the control gate electrode 6 and the erasing electrode 8 with respect to the writing electrode 10. To effect erasing, an erasing voltage is applied to the erasing electrode 8 with respect to the writing electrode 10 and the control gate electrode 6. Rewriting is effected by moving electrons from a polysilicon third-level layer which constitutes the writing electrode 10 to a polysilicon second-level layer which constitutes the floating gate electrode 5 and from the electrode 5 to the erasing electrode 8 which constitutes a polysilicon first-level layer. Figure 4 is a timing chart showing the characteristics of the tunnel oxidefilms employed in a semiconductor non-volatile memory according to the present invention. Figure 4 shows tunnel current with respect to the applied electric field. It is more difficult for the tunnel oxide film to break down in the case where a positive voltage is applied to the polysilicon first-level layer than in the case of the polysilicon second-level layer. Accordingly, the structure shown in Figure 1 enables realisation of an EEPROM in which the occurrence of breakdown due to rewriting is suppressed. Figure 5 shows a second embodiment of the semiconductor non-volatile memory according to the present invention. The semiconductor non-volatile memory has a P-type silicon substrate 1, N⁺-type source and drain regions 22,23, a gate insulator film 24, a control gate electrode 26 and an insulating film 103. Rewriting is effected by moving electrons from the drain region 23 to a floating gate electrode 25 and from the floating gate electrode 25 to an erasing electrode 29. Thus, the second embodiment has a structure in which rewriting is carried out by applying a strong electric field to each tunnel oxide film 27,28 only in the direction in which it is difficult for the tunnel oxide film to break down. The semiconductor non-volatile memories according to the present invention and described above have a structure in which two tunnel oxide films are provided so that rewriting is effected by applying a strong electric field to each of the tunnel oxide films in only one direction in which it is difficult for the tunnel oxide film to become worn due to the application of the electric field. It is therefore possible to realise semiconductor non-volatile memories which can endure many more rewriting operations than conventional semiconductor non-volatile memories.

Claims: A semiconductor non-volatile memory comprising: a semi-conductor substrate (1;21) of a first conductivity type; source and drain regions (2,3; 22,23) of a second conductivity type formed in the surface of said semiconductor substrate in such a manner as to be spaced apart from each other; a floating gate electrode (5;25) formed on the surface of a portion of said semiconductor substrate between said source and drain regions through a gate insulator film (4;24); an erasing electrode (8;29) provided in opposing relation to said floating gate electrode through a first tunnel insulator film (7;28) and a writing electrode (10;23) provided in opposing relation to said floating gate electrode through a second tunnel insulator film (9;27) characterised in that the portion of the floating gate electrode (5;25) opposing the erasing electrode (8;29) through the first tunnel insulator film (7;28) is provided above the erasing electrode (8;29). A semiconductor non-volatile memory as claimed in claim 1, characterised in that the portion of the floating gate electrode (5;25) opposing the writing electrode (10;23) through the second tunnel insulator film (9;27) is provided below the writing electrode (10;23). A semiconductor non-volatile memory as claimed in claim 1 characterised in that the writing electrode (10,23) is formed in a surface portion of the semiconductor substrate (21) under the floating gate electrode (25). A method of using a semiconductor non-volatile memory as claimed in any preceding claim characterised in that the breakdown current through the first and second tunnel insulator films (7,9; 28,27) is maximized.

Inventors: HIRAI, YOSHIO C/O SEIKO INSTR. & ELECTRONICS LTD., Hirai, Yoshio c/o Seiko Instr. &amp; Electronics Ltd.
Applicants: SEIKO INSTRUMENTS INC.
Application year: 1986
Main classification: H01L29
IPC codes: H01L29, G11C14, H01L21