GUARD SYSTEM FOR INVERTER APPARATUS

Abstract: An inverter using gate turn-off thyristors (GTOs) (5 to 10) is controlled by means of pulse width modulation (PWM) to control the speed of an induction motor (14). If the current flowing through the induction motor becomes an overcurrent which can still be cut off by the GTOs, a gate off signal is sup­ plied to respective GTOs to interrupt the overcurrent. If any one of arms respectively corresponding to phases is short-cir­ cuited, a gate on signal is supplied to all GTOs to distribute the short circuit current among the arms, and the main circuit is in­ terrupted by a high-speed breaker (2). At this time, a simul­ taneous gate on signal (h; k) is given priority. if the simulta­ neous gate on signal is present, a simultaneous gate off signal (g; m) is disabled. Owing to this configuration, destruction of the GTOs due to consecutive guard operation can be pre­ vented.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a guard system for a main switching device of an inverter apparatus, and in particular to a guard system for inverter apparatus having self-cutoff function devices. DESCRIPTION OF THE RELATED ART With the advance of development of various power semiconductor devices in recent years, relatively large-capacity inverter apparatus using so-called self-cutoff switching devices such as GTO's (Gate Turn-Off Thyristors) or power transistors have been brought into use. In general, there is a strict region of voltages or currents with which such a self-cutoff switching device can be switched safely. Switching operation beyond this region immediately results in permanent destruction of the device. In an inverter apparatus using such self-cutoff switching devices, therefore, various guard devices are provided. A conventional method is disclosed in EP-A-0 105 510, for example. If the voltage or current of the main circuit of the inverter becomes abnormal condition and such condition remains in a range recoverable by bringing the condition of the switching devices into the cutoff state, the switching devices of the main circuit of the inverter are simultaneously cutoff to carry out guard function. That is to say, the so-called simultaneous cutoff guard function is operated in the conventional method. If the failure state exceeds the range in which the state can be controlled by means of switching devices, the so-called simultaneous turn-on guard function is operated. That is to say, the switching devices of the main circuit of the inverter are simultaneously turned on to prevent the destruction of the switching devices. And the entire circuit is guarded by cutting off the circuit using a fuse or a breaker. However, it has been found that consecutive guard operation attempts of these guard functions destroy the switching devices contrary to expectation. An inverter having an overcurrent protection circuitry is further disclosed in EP-A-0 010 980. This document describes a protection circuitry for switching the power transistors of the inverter off in case an overcurrent flows through the input line or the phase outputs of the inverter. When the motor is overloaded, the motor current is limited and in case a momentary surge of the input current to the inverter occurs, the driving circuit is closed down to prevent damage. This document does not provide any means for protecting the inverter against a failure resulting in a short circuit of two power transistors forming an inverter branch. The protection circuit described in US-P-39 16 287 comprises overload detectors in each inverter branch. In case an overcurrent occurs in one of the branches, all of the inverter thyristors are excited simultaneously. Then all thyristors are quenched by an additional current supplied by a capacitor, and/or the input current of the inverter is switched off by a circuit breaker. This circuit alway reacts with a sudden interruption of the motor current also in case of a minor overload of the motor. SUMMARY OF THE INVENTION It is therefore the object of the invention to provide a reliable guard system for an inverter which adapts itself flexibly to different sources of failure and surely prevents the switching devices of the inverter from being destroyed. According to claim 1, this object is solved by providing a cutoff as well as a turn-on guard function. The turn-on guard function is given priority over the cutoff function to prevent the switching devices from being destroyed in case of a failure in which one of the switching devices does not switch off properly. When the turn-on function has been activated, a breaker interrupts the input current of the inverter to protect the entire circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram for illustrating an embodiment of a guard system for inverter apparatus according to the present invention when it is applied to an electric car. Fig. 2 is a time chart for illustrating the operation of the guard system shown in Fig. 1. Fig. 3 is a configuration diagram for illustrating a principal part of another embodiment according to the present invention. Fig. 4 is a time chart for illustrating the operation of the part shown in Fig. 3. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 schematically shows a main circuit and a control circuit of a bridge type inverter unit for electric car using GTO's as switching devices. The main circuit includes a switch 1, a high-speed breaker 2, a filter reactor 3, a filter capacitor 4, GTOs 5 to 10 for constituting the main circuit of the inverter, current detectors 11 to 13, and an induction motor (hereafter referred to as IM) 14 constituting the load. The main circuit of the inverter is a circuit of so-called bridge type. Among GTOs 5 to 10, pairs of GTOs 5 and 6, GTOs 7 and 8, and GTOs 9 and 10 are connected between DC power sources respectively in series. The respective pairs of GTOs constitute so-called arms. AC outputs are taken out at middle points of respective arms. The GTOs 5 to 10 are alternately turned on to effect the inverter operation. That is to say, one of the upper GTO 5, 7 or 9 and the lower GTO 6, 8, or 10 belonging to a pair is alternately turned on, while the other GTO belonging to the same arm is turned off. A PWM modulator circuit 15 and ON-OFF signal generator circuits 161 to 166 produce ON-OFF signals. Gate drive circuits 171 to 176 produce ON gate signals when the above described ON-OFF signal turns on and produce OFF gate signals when the ON-OFF signal turns off. Reference numerals 18, 19 and 201 to 212 denote a simultaneous gate off signal generator circuit, a simultaneous gate on signal generator circuit, and NAND circuits, respectively. Load overcurrent detector circuits 221 to 223 produce outputs when outputs of the current detectors 11 to 13 exceed predetermined values, respectively. Outputs of the load overcurrent detector circuits 221 to 223 triggers the simultaneous gate off signal generator circuit 18 by way of an OR gate 23. The simultaneous gate off signal generator circuit 18 functions to produce a simultaneous gate off signal g which assumes "1" under normal conditions and which changes to "0" when the load overcurrent has been detected. Arm short circuit detector circuits 241 to 243 are connected in parallel to series circuits of GTO 5 and GTO 6, GTO 7 and GTO 8, and GTO 9 and GTO 10 representing respective phases, respectively. Each of the arm short circuit detector circuits 241 to 243 detects arm short circuit when the voltage across its corresponding series circuit is lowered than the predetermined value. When the arm short circuit is detected, the simultaneous gate on signal generator circuit 19 is triggered to operate by way of an OR gate 25. The simultaneous gate on signal generator circuit 19 functions to produce a simultaneous gate on signal h which assumes "1" under normal conditions and which changes to "0" when the arm short circuit has been detected. Operation of this embodiment will now be described by referring to the time chart of Fig. 2. When neither load current abnormality nor arm short circuit is detected, both the simultaneous gate off signal g and the simultaneous gate on signal h remain "1". At this time, therefore, ON-OFF signals a and b are inverted by the NAND gates 201 and 202, respectively. The resultant signals are inverted again by the NAND gates 207 and 208, respectively. Signals i and j are thus obtained. At this time, therefore, the ON-OFF signals a and b are applied to gate drive circuits 171 and 172 as the signals i and j , resulting in the normal operation as the inverter. Thus the three-phase AC power is applied to the IM 14 to run the electric car. It is now assumed that the current flowing through the IM 14 has exceeded a predetermined value at time t₁. It is also assumed that the current magnitude does not exceed the current value of the GTOs 5 to 10 which can be cut off. At the time t₁, the simultaneous gate off signal g thus changes from "1" to "0". As a result, outputs of the NAND gates 201 to 206 are fixed to "1" irrespective of the ON-OFF signals a to f . Accordingly, outputs of the NAND gates 207 to 212 are fixed to "0". At this time, therefore, all GTOs of respective arms included in the main circuit of the inverter are simultaneously turned off, the simultaneous cutoff guard function being effected. The overcurrent detector circuits 221 to 223 do not produce outputs when an overcurrent exceeding the current of the GTO which can be cut off has been detected. As described above, the GTOs 5 to 10 constituting the arms of the main circuit of the inverter are alternately turned on and off in the pairs of GTOs 5 and 6, GTOs 7 and 8, and GTOs 9 and 10. If two GTOs paired to form an arm simultaneously assumes the ON state due to some cause such as omission of the OFF signal, that arm forms a short circuit between the DC power sources. Accordingly, an excessively large current (as large as several ten thousand amperes in some case) from the aerial conductor and the filter capacitor concentrates into that arm. If this state is left as it is, there is a fear that a GTO of that arm will be destroyed before the blocking of the circuit current caused by the operation of the high-speed breaker 2. By way of precaution against such a case, therefore, detector means are provided to detect the arm short circuit quickly. If the arm short circuit occurs in any arm, GTOs 5 to 10 of all arms are simultaneously controlled to be turned on immediately thereafter. The above described surge current is thus distributed among all arms to prevent destruction of the GTOs. Thereafter the circuit breaking is effected by the high-speed breaker 2. It is now assumed that the simultaneous gate on signal generator circuit 19 has been triggered at time t₂ due to the detection of the arm short circuit. At the time t₂, therefore, the simultaneous gate on signal h changes from "1" to "0". As a result, the outputs of the NAND gates 207 to 212 are fixed to "1" irrespective of the outputs of the NAND gates 201 to 206 of the preceding stage. At this time, therefore, all GTOs of arms included in the main circuit of the inverter are simultaneously turned on, the simultaneous turn-on guard function being attained. As a result, a large current flows from the aerial conductor into the main circuit through the switch 1 and the high-speed breaker 2. The main circuit is opened by the operation of the high-speed breaker 2 and succeeding operation of the switch 1. As evident from Fig. 2, transition of the simultaneous gate on signal h from "1" to "0" disables the simultaneous gate off control of the GTOs by means of the simultaneous gate off signal g . Thereby the simultaneous gate on control is always given priority. In the foregoing description, the simultaneous gate off control is effected at the time t₁ and the simultaneous gate on control is subsequently effected at the time t₂. In this embodiment, the simultaneous gate on signal h is supplied to the NAND gates 207 to 212 which are placed in a stage subsequent to the NAND gates 201 to 206 supplied with the simultaneous gate off signal g as evident from Fig. 1. Therefore, these NAND gates 207 to 212 serve as means for inhibiting the simultaneous gate off signal g by means of the simultaneous gate on signal h . Once the simultaneous turn-on guard function is effected by means of the simultaneous gate on signal h , the simultaneous cut-off function is not effected however often the simultaneous gate off signal g is changed to "0" so long as the simultaneous gate on signal h is not restored from "0" to "1". Accordingly, the fear of destruction of the GTOs can be sufficiently eliminated. Fig. 3 is a circuit configuration diagram showing another embodiment of the present invention. A principal part of a circuit corresponding to only one phase is illustrated in Fig. 3. Under normal conditions, ON-OFF signal generator circuits 25 and 26 produce ON-OFF signals required for running the inverter. And the ON-OFF signal generator circuits 25 and 26 are configured to produce a signal fixed to the ON state when a signal k is applied thereto and produce a signal fixed to the OFF state when a signal l is applied thereto. A NAND gate 27 serves as inhibition means for disabling a simultaneous gate off signal m by the simultaneous gate on signal k . An inverter gate 28 compensates the signal inversion effected in the NAND gate 27. Remaining parts of Fig. 3 are the same as those of embodiment illustrated in Fig. 1. Fig. 4 is a time chart for illustrating the relation among signals appearing in Fig. 3, i.e., the relation among the simultaneous gate off signal m , the simultaneous gate on signal k , and the output signal l of the NAND gate 27. While the simultaneous gate on signal k assumes "1", the simultaneous gate off signal m is supplied to the ON-OFF signal generator circuits 25 and 26 as the signal l to allow the activation of the simultaneous cutoff guard function. Once the simultaneous gate on signal k changes from "1" to "0", however, transmission of the simultaneous gate off signal m is inhibited to give priority over the simultaneous cutoff guard function to the simultaneous turn-on guard function. As a result, the GTOs can be sufficiently prevented from destruction. In the above described embodiments, GTOs were used as switching devices of the main circuit of the inverter. However, it is a matter of course that application of the present invention is not limited to such a case. For example, the present invention can be applied to any inverter using self-cutoff switching devices such as power transistors. Owing to the present invention as described above, the simultaneous turn-on guard function can be activated with priority over the simultaneous cutoff guard function only by adding the simple logic circuit. Therefore, it is possible to realize a highly reliable guard system for inverter apparatus which surely guards an inverter apparatus at all times and which precludes the possibility of destruction of switching devices.

Claims: A guard system for an inverter having semiconductor switching devices (5 to 10) in a plurality of inverter arms to convert DC power into multiple-phase AC power supplied to a load (14), comprising first guard means (19) for simultaneously turning on all switching devices (5 to 10) in immediate response to detection of a short-circuit in an inverter arm caused by simultaneous conduction of the switching devices connected in series in that inverter arm, and a breaker (2) actuated by said first guard means (19) for interrupting the overall current flowing into said inverter, characterized by second guard means (18) for simultaneously cutting off all switching devices (5 to 10) when an overcurrent flowing to said load (14) is below a maximum cut-off current, and means (201-212; 27) giving the turning-on action of the first guard means (19) priority over the cutting-off action of the second guard means (18). A guard system according to claim 1, wherein said short-circuit is detected by detecting means (241 to 243) which responds to a drop in voltage across said switching devices connected in series. A guard system according to claim 1, wherein said semiconductor switching devices (5 to 10) comprise gate turn-off thyristors. A guard system according to claim 1, wherein said priority means comprises two NAND gates (201 to 206, 207 to 212) connected in series as a first stage and a second stage in an ON-OFF signal transmission path and wherein the NAND gate (201 to 206) of the first stage is supplied with the output signal (g) of said second guard means (18) and the NAND gate (207 to 212) of the second stage is supplied with the output signal (h) of said first guard means (19). A guard system according to claim 1, wherein a three-phase inverter is supplied with DC power from an aerial conductor through a switch (1) and a high-speed breaker (2), said three-phase inverter comprising six sets of GTOs (5 to 10) connected in gate wiring; a three-phase induction motor (14) is supplied with power by said three-phase inverter; an electric car is driven by said induction motor; a pulse width modulator means (15) is provided; gate drive circuits (171 to 176) for turning on and turning off said GTOs on the basis of an ON-OFF signal sent out from said modulator means are provided; said second guard means (18) simultaneously turns off said GTOs in response to a current of said induction motor larger than the maximum current at normal conditions and not larger than the interruptible current of the GTOs; and wherein said first guard means (19) simultaneously turns on said GTOs in response to simultaneous conduction of two sets of GTOs connected in series in said inverter.

Inventors: HORIE, AKIRA, OKAMATSU, SHIGETOSHI
Applicants: HITACHI, LTD.
Application year: 1986
Main classification: H02M7
IPC codes: H02M7