PATTERN RECOGNITION AND LEARNING APPARATUS

Abstract: Disclosed is a pattern recognition and learning apparatus which compares an input pattern with a reference patterns to recognize a category of the input pattern, and learns a refer­ ence pattern from input patterns of a specific category. Learn­ ing of input patterns for obtaining a reference pattern is per­ formed by means of Karhunen-Loeve expansion of a covari­ ance matric of input patterns using a power method.

Description: The present invention relates to a pattern recognition and learning apparatus for obtaining a reference pattern used for recognition processing from input patterns of a specific category. A pattern recognition apparatus for recognizing input patterns, such as voices or characters, has been developed. In the pattern recognition apparatus, an input pattern is compared with recorded reference or standard patterns, and the category of a reference pattern which has a highest similarity with the input pattern is obtained as a recognition result. In order to improve recognition capabilities, learning of reference patterns is necessary. New recording or registration of reference patterns in a dictionary memory is normally called learning of the reference patterns. A plurality of patterns of a known category, which are input for learning, are recorded or stored in a memory as reference patterns of the category in the same form as input patterns to be recognized. In such a reference pattern recording method, since recognition processing is performed by a comparison (matching) between recorded or registered patterns and an input pattern, patterns uttered by the same talker at substantially the same time can be referred to as needed. However, in the case of the reference patterns registered in this method, a statistical distribution in patterns to be recognized is not taken into consideration. Therefore, the recognition method of this type is normally adopted for recognition of input patterns whose variation is small. Recognition methods in consideration of the statistical distribution in patterns, such as Mahalanobis's recognition method using generalized distance system or a multiple similarity method, are known. In these methods, since reference patterns are made in consideration of the statistical distribution of patterns, a large number of sample patterns must be collected. In this case, statistical analysis of sample patterns is significantly difficult to achieve. In the pattern recognition method of this type, since it is difficult to learn reference patterns, learning of patterns is performed in advance using a computer, and reference patterns thus prepared are recorded in a recognition apparatus. In the multiple similarity method, the statistical distribution of patterns to be recognized is taken into consideration for preparing reference patterns. Therefore, recognition performance of this method is considerably superior to the recognition method wherein learning patterns are simply registered as the reference patterns. However, in order to prepare reference patterns in consideration of the statistical distribution, a method such as Karhunen-Loeve expansion (to be referred to as KL expansion hereinafter) is necessary, and this is not easy (cf. ICASSP 85, 26-29/3/85, vol, pp. 21-24). As methods of the KL expansion, the Jacobi method and Householder & Sturm method are known. The former method is relatively simple in computation procedure but requires a large volume of computation. The latter method requires a complex computation procedure and is difficult to apply to an apparatus. Therefore, in a conventional apparatus, a high-performance computer separate from the pattern recognition apparatus is used to obtain reference patterns. It is an object of the present invention to provide a pattern recognition and learning apparatus which can efficiently obtain reference patterns for high recognition performance. According to the present invention, there is provided a method of obtaining a reference pattern and an apparatus for obtaining a reference pattern as claimed in claims 1 and 6, respectively. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic block diagram of a pattern recognition apparatus according to an embodiment of the present invention; Figs. 2A and 2B show, in combination, a detailed block diagram of a pattern learning apparatus of the present invention; and Figs. 3A, 3B and 3C show, in combination, a flow chart for explaining KL expansion in the pattern learning apparatus shown in Figs. 2A and 2B. Fig. 1 shows the schematic arrangement of a voice recognition apparatus according to an embodiment of the present invention. An input voice signal is converted to, e.g., a 12-bit digital voice signal by voice input circuit 1. The digital voice signal is supplied to feature extractor 2 to extract voice-recognition acoustic parameters. Feature extractor 2 comprises 16 bandpass filters for dividing a frequency band, e.g., from 200 Hz to 5.4 kHz into 16 channels. The output signals of the 16 bandpass filters are used as vowel-recognition acoustic parameters. The output signals of eight pairs of bandpass filters are used as consonant-recognition acoustic parameters. Each pair of bandpass filters consists of two bandpass filters for adjacent frequency bands. Each acoustic parameter is expressed by 8 bits. Feature extractor 2 may be arranged to obtain, as acoustic parameters, cepstrum coefficients or part of various parameters obtained through correlation analysis. The acoustic parameters of the input voice pattern obtained by extractor 2 are supplied to segmentation circuit 3, and are segmented for each mono syllable. Segmentation of the acoustic parameters is performed based on variations in the input voice power level. In the case of vowels, one frame (e.g., 10 msec) of a vowel portion of the input voice pattern is segmented to provide a recognition and learning vowel pattern consisting of the output signals of the 16-channel bandpass filters, and expressed by a 16-dimensional vector consisting of the following 16 elements: In the case of consonants, eight frames including a transition portion from a vowel to a consonant are segmented to provide a consonant recognition and learning pattern. In the consonant recognition pattern, the output signals of the 8-channel bandpass filters are each sampled at eight points on the time axis, thereby providing the consonant recognition pattern represented by a 64-dimensional vector consisting of the following 64 elements: Recognition processing of the thus obtained vowel and consonant patterns is performed by recognition circuit 4 using reference patterns stored in reference pattern memory 5. Assuming that a vector of the input pattern is given by f and a reference pattern of category ℓ is given by {n (ℓ) }, the recognition processing is executed based on the following calculation according to the compound similarity method: This calculation is made by dividing a product of scalar product (f,n) of vector f of the input pattern and each reference pattern n of a set {n (ℓ) (n = 1 to N) of N reference patterns belonging to an identical category, and coefficient an (ℓ) determined by an eigen value of reference pattern n, with the second power of the norm ∥f∥ of vector f of the input pattern. Coefficient an (ℓ) can take positive and negative values, and if it is negative, a difference from another category is emphasized. If coefficient an (ℓ) takes only a positive value, the similarity method in equation (3) is the same as the multiple similarity method. The similarity calculation is executed between the input pattern and the reference patterns of all the categories, and the category ℓ of a reference pattern having the maximum similarity S (ℓ) [f] is obtained as the recognition result. The recognition result is displayed in an appropriate form on display 8. The similarity is calculated in accordance with the following relation in practical hardware: where fj indicates each element of the input voice pattern, and ij indicates each element of the reference pattern. The input voice pattern to be subjected to recognition processing is stored in learning pattern memory 6 as a learning pattern. A voice pattern of a known category, which is input for learning, is also stored in memory 6. When a predetermined number of learning patterns of the identical category are stored in memory 6, pattern learning is performed. Standard patterns in memory 5 are updated by learning the patterns of the known category. Pattern learning of the present invention is performed at high speed by special-purpose hardware (to be described later). Pattern learning processing of the present invention can be divided into (1) processing for obtaining covariance matrix K (in the present invention, this is slightly different from each of the mathematical definition of the term) from each of vowel and consonant patterns, and (2) processing for obtaining proper values or eigen values λ and eigen vectors ξ from covariance matrix K. Processing for obtaining N eigen values and N eigen vectors in the descendant order of the eigen values is generally called KL expansion. Pattern learning processing of the present invention will be described in detail hereinafter. Covariance matrix K of input voice patterns (learning patterns) is obtained as follows when the learning pattern is given by a column vector Sm: where M is the number of learning patterns and Sm T is a transposed vector or row vector of Sm. Learning pattern Sm is given by a column vector of 64 elements in the case of a consonant pattern, and is given by a column vector of 16 elements in the case of a vowel pattern. The covariance matrix K is obtained by averaging the respective elements of a matrix prepared by a multiplication of the column and row vectors of the learning patterns for M learning patterns. Therefore, the number of elements of covariance matrix K equals the square of the number of elements of the above vectors. Covariance matrix K can be rewritten as follows: The KL expansion of covariance matrix K is given by K = λ1ξ1ξ1 T + λ2ξ2ξ2 T +.......λnξnξn T (7) According to equation (7), covariance matrix K is expanded into n axes or components. As described above, the KL expansion of covariance matrix K is processing for obtaining eigen values λ and eigen vectors ξ in the descendant order of eigen values λ (λ1 > λ2 >...> λn). In order to obtain covariance matrix K reflecting a distribution in patterns of a certain category, a considerable number of learning patterns are necessary. For this purpose, a predetermined number of learning patterns must be prestored in memory 6. Even if a small number of learning patterns are stored, covariance matrix K can be updated to reflect the pattern distribution in accordance with sequentially input learning patterns. Calculation processing therefor is performed as follows: K = (1 - w)K' + ΣwSn·Sn T (8) where w is a weighting coefficient for updating the covariance matrix, Sn is a newly input learning pattern, and K' is a covariance matrix before learning the learning pattern Sn. Weighting coefficient w can be either a positive or negative value. If coefficient w is positive, the similarity of the covariance matrix for the input pattern is increased; otherwise, the similarity is decreased. The covariance matrix of the patterns can also be prevented from being greatly influenced by newly input patterns. Processing for obtaining the eigen values and eigen vectors from the covariance matrix thus obtained is then performed. A standard pattern used for the above-mentioned compound similarity calculation is prepared based on the eigen values and the eigen vectors. The standard pattern is obtained by KL expansion of covariance matrix K, more specifically, in the present invention, it is obtained by KL expansion using a power method. Assume that covariance matrix K has eigen values λ1, λ2,..., λn, and eigen vectors ξ1, ξ2,..., ξn corresponding to these eigen values, as shown in equation (7). Arbitrary vector u0 is defined as a linear combination of eigen vectors ξ1, ξ2,..., ξn as follows: Covariance matrix K, eigen vectors ξ and eigen values λ are related as follows: Kξi = λiξi (10) In terms of K s u0, K s u0 is rewritten as follows: Eigen values have the following relationship: |λ1| > |λ2| > ... > |λr| > ... > |λn| (12) Equation (11) is rewritten as: Since |λi/λ1| < 1 (i = 2, 3,..., n), if s becomes sufficiently large, the second term of equation (13) is converged to 0. Therefore, K s+1 u0/K s u0 = λ1 (14) In addition, it will be understood that K s u0 is proportional to eigen vector ξ1. When the above-mentioned calculation is executed, scale-out may occur during calculation. For this reason, vector u0 is given by the unit vector as follows: The following calculations are repetitively executed. vs+1 = Kus (16) us+1 = vs+1/bs+1 (s = 0, 1, 2,...) (17) where bs+1 is an element having a maximum absolute value among elements of vector vs+1, and equation (17) means normalization of vector vs+1. By substituting equation (16), equation (17) is rewritten as follows: When equations (16) and (17) are repeatedly calculated, the following result can be obtained: λ1 ≈ bs+1 ξ1 ≈ us+1 (19) After eigen value λ1 having the largest absolute value and eigen vector ξ1 corresponding thereto are obtained in this manner, eigen value λ2 having the next largest absolute value and eigen vector ξ2 corresponding thereto are obtained. In order to obtain λ2 and ξ2, already obtained λ1 and ξ1 must be eliminated from covariance matrix K. This can be achieved by: K' = K - λ1ξ1ξ1 T (20) Since ξ1 T ξi = 0 (i = 2, 3,..., n), equation (20) will be modified as follows: K'ξ1 = Kξ1 - λ1ξ1ξ1 T ξ1 = λ1ξ1 - λ1ξ1 = 0 This means that eigen value λ1 and eigen vector ξ1 are eliminated from K' in equation (20). In general, K'ξi = Kξi - λ1ξ1ξ1 T ξi = λiξi (i ≠ 1) (21) Therefore, as can be seen from equation (21), K' has eigen values satisfying |λ2| > |λ3| > ... > |λn|. In this case, ξi is normalized. If the conversion of the covariance matrix, indicated by equation (20), is performed each time an eigen value and an eigen vector are obtained, eigen values and eigen vectors corresponding thereto can be sequentially obtained in the descendant order of the eigen values. Figs. 2A and 2B show a hardware arrangement of the present invention for performing the above-mentioned KL expansion processing, i.e., pattern learning processing (requiring sum-of-products calculation processing) at high speed. This hardware arrangement is also applied to various sum-of-products calculation processing necessary for calculating the similarity. For KL expansion, there is a very large volume of multiplications of covariance matrix K and eigen vector ξ. For example, if vector ξ has 64 dimensions, the repetitive number of calculations is 50 times, and the number of eigen values and eigen vectors (the number of axes or components in KL expansion) is 7, 64 x 64 x 50 x 7 of multiplications and additions are necessary. The hardware arrangement shown in Figs. 2A and 2B can execute a large number of sum-of-products calculations necessary for similarity calculation and KL expansion processing at high speed. Referring to Figs. 2A and 2B, memories 11 to 15 for pattern recognition and learning are provided, and memories 11 to 14 are coupled to multi-bus 16 (e.g., IEEE-796). Microprocessor 45 is also coupled to bus 16 and, hence, can access memories 11 to 14 through bus 16. To bus 16 are coupled to learning pattern memory 47 storing a plurality of learning patterns for the same category and display 48 for displaying the recognition result. Microprocessor 45 executes segmentation of input voice patterns, learning processing, and recognition processing. Microprocessor 45 loads a program for operating entire hardware into program memory 30. Memory 30 loads program data into program register 33. Sequence controller 31 controls the sequence of hardware in response to an instruction and a jump address from register 33. Controller 31 supplies address data to program memory 30, and the corresponding data is read out from memory 30 in response thereto and is stored in register 33. Register 33 supplies instruction data to ALU (arithmetic logic unit) 41 and decoders 37, 38, and 39. Decoder 37 generates input control signals #2 for controlling data entry of various circuits. Decoder 38 generates output control signals #3 for controlling data output of the various circuits. Decoder 39 generates command control signals #4 for controlling the various circuits. Control signals #2, #3, and #4 are each a 1-bit signal. Memories 11 to 15 receive a 16-bit address signal #1 from register 36 and input control signal #2, output control signal #3, and command control signal #4. An address of memories 11 to 15 are designated by an address signal #1, and the read/write operations thereof are governed by control signals #2 and #3. Command control signal #4 supplied to each of memories 11 to 15 is used for clearing the memory address designated by the address signal #1. Memories 11, 13, and 14 are each coupled to 16-bit data buses, memory 12 is coupled to an 8-bit data bus, and memory 15 is coupled to a 35-bit data bus. Selectors 18 and 19 select one of a plurality of inputs under the control of sum-of-products control circuit 29 responsive to an instruction supplied from ALU 41 through bus 42, and supply the selected inputs to input terminals A and B of sum-of-products circuit 21, respectively. Circuit 21 calculates sum-of-products of data received at terminals A and B under the control of control circuit 29. The outputs of selectors 18 and 19 each have 16 bit, and the output of sum-of-products circuit 21 has 32-bit. The output of circuit 21 is connected to shifter 23. Shifter 23 is a barrel shifter which is arranged to shift a 32-bit output of circuit 21 from 5-bit right shift to 2-bit left shift. Selector 25 selects one of the output data of circuit 21, 5-bit right-shifted data of circuit 21, and upper 16-bit output data of shifter 23 under the control of control circuit 29. Selector 26 selects one of the output data of circuit 21, 5-bit right-shifted data of circuit 21, and data registered in register 22 (in this embodiment, 1) under the control of control circuit 29. The outputs of selectors 25 and 26 are respectively connected to input terminals A and B of sum-of-products circuit 32, and the sum of products of the input data is calculated under the control of control circuit 29. Lower and upper 16-bit data of circuit 32 are coupled to input buses 34 and 35 of ALU 41. Buses 34 and 35 are respectively connected to input terminals A and B of ALU 41. The output of ALU 41 is connected to output bus 42. Upper 16-bit output data of shifter 23 is coupled to bus 35 through buffer 27 responsive to input control signal #2, and lower 16-bit output data thereof is coupled to bus 34 through buffer 28 responsive to input control signal #2. Bidirectional buffer 43 is connected between memory 13 and output bus 42 of ALU 41. Buffer 43 controls a data-flow direction in response to input control signal #2 and output control signal #3. Bidirectional buffer 17, responsive to input control signal #2 and output control signal #3, is connected between memory 11 and bus 42. Bidirectional buffer 20, responsive to input control signal #2 and output control signal #3, is connected between microprocessor 45 and bus 42. Buffer 24 for storing a command from microprocessor 45 in response to input control signal #2 is connected between microprocessor 45 and bus 34. The command from microprocessor 45 is read by ALU 41 through bus 34, thereby determining the next operation of ALU 41. The buffer and the bidirectional buffers each have a tri-state output. ALU 41 has, for example, 16 internal registers to execute arithmetic and logical operations, such as: subtraction, addition, multiplication, division, Exclusive OR, AND, OR, NAND, NOR, and comparison between registers; subtraction, addition, comparison, AND, OR, Exclusive OR, NOR, and NAND with a constant; 1-bit logical left rotate and logical right rotate, arithmetic left shift, arithmetic right shift, and so on. Voice data including 16-channel vowel data for one frame, 8-channel consonant data, and data indicating voice power is extracted from feature extractor 46 to be stored in memory 44. The voice data is read out from memory 44 in response to input control signal #2 to be loaded to ALU 41 through bus 34. Execution of various basic calculations necessary for the similarity calculation shown by equation (4) in the hardware arrangement shown in Figs. 2A and 2B will be explained below. Input voice data is fetched by ALU 41 from extractor 46 through memory 44 and bus 34. The voice data fetched by ALU 41 is input to microprocessor 45 through output bus 42 and buffer 20. Microprocessor 45 segments the voice data based on voice power. Microprocessor 45 writes voice pattern data in memory 11 through multi-bus 16. In the first step, is calculated. For this purpose, fj is read out from memory 11 to be supplied to sum-of-products circuit 21 through selectors 18 and 19. Circuit 21 calculates fj². A calculation is executed for respective elements of vector f stored in memory 11 while sequentially updating designation addresses of memory 11, in other words, while incrementing parameter j . The calculation result is supplied to sum-of-products circuit 32 through selector 25 without being shifted. In this step, circuit 32 does not perform an addition. In the case of a vowel, the above calculation is made for 16 elements of the vector to calculate The 32-bit calculation result is stored in one register of ALU 41 through input buses 34 and 35. N in equation (4) corresponds to 16 in the case of a vowel. In the second step, is calculated. For this purpose, data fj is supplied to input terminal A of circuit 21 through selector 18. In this step, "1" stored in memory 13 is read out therefrom, and is supplied to circuit 21 through selector 19. As a result, is calculated by circuit 21 while updating addresses of memory 11. 5-bit right-shifted data of the output data of circuit 21 (this means rounding off of lower 5 bits) is supplied to input terminals A and B of sum-of-products circuit 32 through selectors 25 and 26. As a result, is calculated by circuit 32. The 32-bit calculation result is supplied to ALU 41 through input buses 34 and 35, and ALU 41 executes a division to store it in one register thereof. In this calculation, rounding off of the output data of circuit 21 is performed so that the output data of circuit 32 does not exceed 32 bits. In the next step, is calculated. For this purpose, vector elements ij of a reference pattern are supplied from reference pattern memory 12 storing reference patterns to circuit 21 through selector 19, and vector elements fj of a sample pattern in memory 11 are supplied to circuit 21 through selector 18. Circuit 21 calculates while updating addresses of memories 11 and 12, in other words, while incrementing j . The calculation result is supplied to circuit 32 through selectors 25 and 26. is calculated by circuit 32, and is calculated by incrementing parameter i from 0 to M-1. The calculation result is stored in a register of ALU 41. ALU 41 calculates similarity S (ℓ) [f] of sample pattern f in accordance with equation (4) using the calculated results described above. The calculated similarity is stored at a predetermined location in memory 14 from ALU 41 through output bus 42 and bidirectional buffer 20. ALU 41 instructs the end of similarity calculation to microprocessor 45. Thus, microprocessor 45 accesses memory 14 to write the similarity in the internal memory, and performs recognition of the category of sample pattern f . Pattern learning is to prepare a reference pattern from a plurality of voice sample patterns for a given category. The prepared reference pattern is registered in reference pattern memory or dictionary memory 12. For the purpose of pattern learning, microprocessor 45 stores an appropriate number of sample patterns for each category in learning pattern memory 47. The number M of learning patterns of a given category is preferably 10 to 20. In the present invention, pattern learning is performed by KL expansion using a power method. Pattern learning processing by means of KL expansion using a power method according to the present invention will be described with reference to the flow chart shown in Figs. 3A, 3B and 3C. In step S1, the initial value of the number of axes or components, AXIS No. of KL expansion of covariance matrix K is set to 1. This value is loaded to one register of ALU 41 from microprocessor 45. The number of axes or components of KL expansion corresponds to n in equation (7). Setting the initial value to 1 means to calculate maximum eigen value λ1 and eigen vector ξ1. In step S1, the maximum number of axes or components to be calculated is also set in another register of ALU 41. In equation (7), the maximum number of components is indicated by n . In the case of a vowel, the number of components to be obtained is preferably 4, and in the case of a consonant, 7. Accumulation magnification coefficient MISCAL "1" used for KL expansion of covariance matrix K is set in a register of ALU 41. Covariance matrix K is loaded to memory 13 from covariance matrix memory 47 through bus 16. Matrix K is expressed by equation (6). n elements Sm1Sm1 to SmnSm1 of the first column of matrix K stored in memory 13 are copied into memory 14 through bus 16. This amounts to loading of a result obtained by multiplying unit vector u0 represented by equation (15) with matrix K in memory 14. In step S2, value B0 of the maximum element of vector ξ2 (to be calculated later) is set to 0. This value is set in one register of ALU 41. The value of one register of ALU 41 indicating the number of calculation times (CAL.TIME) is set to an initial value 0. The maximum number of the calculation times is set to e.g., 200. This value is also set in the register of ALU 41. The number of calculation times corresponds to s in equation (11). In step S3, ξ2 = Kξ1 is calculated. Matrix K stored in memory 13 is supplied to input terminal A of circuit 21 through selector 18, and ξ1 stored in memory 14 is supplied to input terminal B of circuit 21 through selector 19, so that circuit 21 calculates ξ2 = Kξ1. Each element of matrix K is written 15 bits and each element of vector ξ1 has 16 bits. And, each element of Kξ1 has not more than 35 bits. Each element of vector ξ2 is transferred from circuit 21 to memory 15. Vector ξ2 calculated is used for the next calculation as vector ξ1. For this purpose, each element of vector ξ2 must have less than 16 bits. Each element of vector ξ2 is fetched by ALU 41 from memory 15 through shifter 23 (at this time, a shift amount is 0) and upper 16-bit buffer 27. ALU 41 compares the respective elements of vector ξ2 in magnitude in terms of upper 16 bits. Then, an element having a maximum absolute value of vector ξ2 is detected and is given by B1. The absolute value of B1 is given by ABS(B1). ALU 41 sets the shift amount of shifter 23 with reference to maximum absolute value ABS(B1) so that the maximum value of absolute value of each element of vector ξ2 is below 536870912 (= 2²⁹-1). In other words, the shift amount is determined so that the maximum value has not more than 30 bits. The maximum element of vector ξ2 is fetched by ALU 41 through shifter 23 and upper and lower 16-bit buffers 27 and 28. Next, each element of vector ξ2 is fetched by ALU 41 from memory 15 through shifter 23 and buffers 27 and 28. ALU 41 divides each element of vector ξ2 with the maximum element so that the maximum value of elements of vector ξ2 yields 32767 (= 2¹⁵-1) or -32767. In other words, each element of vector ξ2 is divided to have not more than 16 bits. This means normalization represented by equation (17). Calculation ξ2 = Kξ1 corresponds to that of equation (16). ALU 41 stores each element of vector ξ2 converted into 16 bits as described above in memories 11 and 14 through buffers 17 and 20, respectively. The value (CAL.TIME) of the register of ALU 41 indicating the number of calculation times is incremented by 1. In step S4, the same calculation as in step S3 is executed. More specifically, ξ2 = Kξ1 is calculated using vector ξ1 stored in memory 14. Next, element B2 having the maximum absolute value of vector ξ2 is calculated, and its absolute value is set to ABS(B2). As in step S3, the shift amount of shifter 23 is set and each element of vector ξ2 is processed not to exceed 16 bits. New vector ξ2 calculated in step S4 is stored in memory 14. The number of calculation times (CAL.TIME) is incremented by 1. With the above processing, calculations of equations (16) and (17) have been performed twice. Convergence is checked next. Convergence check is performed in two steps, e.g., coarse check and fine check steps. The first coarse check step is performed in step S5. Difference ABS(B2-B0) between maximum absolute value ABS(B2) obtained in step S4 and maximum absolute value B0 set in step S2 (corresponding to the maximum absolute value obtained in the second previous step from step S4) is compared with a 1/β multiple of ABS(B2) (e.g., β = 2³) obtained in step S4. If ABS(B2-BO) ≧ ABS(B2)/2³, it is determined that the maximum absolute value (maximum eigen value) is not yet converged, and checking of step S8 is performed. It is checked in step S8 if calculations are made a predetermined maximum number of times (in this embodiment, 200 times). This means that a maximum of 200 calculations is allowed. If 200 calculations are not yet performed, the maximum absolute value detected in step S4 is loaded to the register of ALU 41 in step S9. Until the first-stage check in step S5 is cleared, steps S3, S4, S8, and S9 are repeated. This means the calculation of equation (18). If it is determined in step S5 that ABS(B2-B0) < ABS(B2)/2³, the operation advances to the second-stage check step. In step S6, sum SA of differences between respective elements of vector ξ2 obtained in step S3 and stored in memory 11 (to be referred to as vector f hereinafter) and vector ξ2 obtained in step S4 and stored in memory 14 (to be referred to as vector ξ1 hereinafter) is obtained. This calculation can be performed such that the contents of memories 11 and 14 are fetched by ALU 41 through bidirectional buffers 17 and 20. Subsequently, in step S7, SA is compared with ABS(B2)/γ (for example, γ = 2³ × n, and n is the number of dimensions of the vector and 16 in the case of a vowel). If SA < ABS(B2)/(2³ × n), it is determined that the maximum value is converged. If convergence is not detected, the calculation times are checked. If the number of calculation times has not reached 200, steps S9, S3 and S4 are repeated. If it is determined in step S8 that the number of calculation times has reached 200, the flow is forcibly ended. If convergence of vector ξ1 is confirmed, the norm of vector ξ1 is calculated in step S10. For this purpose, vector ξ1 stored in memory 14 in step S4 is fetched by ALU 41 through bidirectional buffer 20. In ALU 41, each 16-bit element of vector ξ1 is multiplied with 1/2 through a 1-bit right shift operation. This is to prevent overflow in the calculation of the sum of squares. Thereafter, ξ1 × 1/2 is stored in memory 11(f) from ALU 41 through bidirectional buffer 17. ξ1 × 1/2 is transferred from memory 11 to a location in memory 14 different from that at which vector ξ1 is stored. ξ1 × 1/2 stored in memory 14 is referred to as vector ξ1' hereinafter. Vector f(ξ1 × 1/2) in memory 11 and vector ξ1' stored in memory 14 are supplied to sum-of-products circuit 21 respectively through selectors 18 and 19, so that the square of norm WW = f T ξ1' is calculated. fTξ1' corresponds to 1/16 × f T ξ1 using vector ξ1 obtained in step S4. f T ξ1' obtained by circuit 21 is 2-bit right-shifted by shifter 23 to yield W = WW/4. This result is fetched by ALU 41 through buffers 27 and 28. ALU 41 sets coefficient DIVW = 4 depending on the shift amount of shifter 23 in its register. In step S11, in ALU 41 W = WW/4 is compared with 1073610756 (= 32766²). This corresponds to check as to whether the square root of W exceeds 16 bits or not. If W < 1073610756, since the square root of W does not exceed 16 bits, the operation advances to step S13. However, if W ≧ 1073610756, since the square root of W exceeds 16 bits, step S12 is executed. ALU 41 right-shifts W by 2 bits in accordance with its shift command so that W = W/4 is obtained. Coefficient DIVW is set to 8. This value corresponds to the shift amount of W in shifter 23 and ALU 41. In step S13, square root RW = SQRT(W) of W is calculated by ALU 41. Square root RW must not exceed 16 bits, in other words, must be equal to or less than 32766. W1 = 640000000/DIVW is calculated, and then W1' = W1/RW is calculated. In ALU 41, VAL1 = B2 × 2 SHIFT is calculated for maximum value B2 of vector ξ2 obtained in step S4. SHIFT indicates a value set in register 30 by ALU 41. The shift amount of shifter 23 is determined in accordance with the value of SHIFT. SHIFT 0, 1, 2, 3, 4, 5, 6, and 7 indicate 5-bit right shift, 4-bit right shift, 3-bit right shift, 2-bit right shift, 1-bit right shift, no shift, 1-bit left shift, and 2-bit left shift, respectively. Shifter 23 performs shift corresponding to an amount depending on value SHIFT set in register 30. If the number of axes is 1, eigen value VAL11 of first axis in KL expansion is set to VAL1. VAL11 is stored in ALU 41. ALU 41 performs the following calculation. This calculation is made for normalizing vector ξ1 by the norm so that the sum of squares of each element is constant for each category and axis. In this embodiment, the sum of squares of each element, i.e., the norm, is normalized to 64000. ALU 41 sends thus calculated vector to microprocessor 45 through buffer 20, and microprocessor 45 stores it in dictionary memory 12. In step S14, ALU 41 sets WSIFT in accordance with W = WW/4 obtained in step S12. Then, EDIV = W × 2 WSIFT is calculated, and the following calculation of vector f is made in accordance with its upper 16 bits UEDIV = EDIV/2¹⁶. (f) = -VAL1 × (ξ1)/UEDIV (23) Vector f is stored in memory 11 from ALU 41 through bidirectional buffer 17. A calculation for eliminating the eigen value and the eigen vector of the first axis from covariance matrix K is performed as follows: (K) = (K) + (ξ1)(f) × 2 3+WSIFT-SIFT /2¹⁹ (24) More specifically, vector f stored in memory 11 and vector ξ1 stored in memory 14 are supplied to circuit 21 respectively through selectors 18 and 19, thereby calculating ξ1f. At this time, the shift amount of shifter 23 is set to 3+WSIFT-SIFT, and ξ1f × 2 3+WSIFT-SIFT can be obtained from shifter 23, which is a 35-bit output. Upper 16 bits are coupled to selector 35. This amounts to multiplication of the second term of the above equation with 1/2¹⁹. Covariance matrix K is preloaded to input terminal B of circuit 32. As a result, equation (24) is calculated by circuit 32, and the calculation result is returned to memory 13. This calculation corresponds to equation (19). In step S15, new covariance matrix K obtained by equation (24) is supplied from memory 13 to ALU 41 through buffer 43. ALU 41 calculates maximum absolute value MAXA from elements of matrix K. Subsequently, ISCAL = 16383/MAXA (integer) is calculated. If ISCAL ≠ 1 or 0, the following calculation is made of each element of matrix K: K = K × ISCAL (25) If ISCAL = 0, this is considered as ISCAL = 1. K = K × ISCAL is stored in memory 13 through buffer 43. Coefficient MISCAL is multiplied with ISCAL. Step S15 is executed for the following purpose. More specifically, each time an eigen value and an eigen vector are obtained during KL expansion processing of matrix K, a subtraction of matrix K is executed in step S14. For this reason, the elements of matrix K are gradually decreased. This degrades precision of the following calculations. In order to obtain the eigen value and the eigen vector of each axis of KL expansion with high precision, it is required that each element of matrix K do not become too small. For this purpose, the elements of matrix K is multiplied with ISCAL in step S15. As indicated by equation (22), each element of vector ξ1 is multiplied with 1/MISCAL in step S13, thereby correcting a magnification. In step S16, the number of axes set in ALU 41 is incremented by 1. In step S17, if eigen value VAL1 obtained in step S13 is a negative value, the number of axes is decremented by one. It is then checked in step S18 if the number of axes has reached the prescribed number of axes (in the case of a vowel, 4; in the case of a consonant, 7). If the prescribed number of axes is reached, KL expansion is ended. If the eigen values and eigen vectors up to the prescribed number of axes are not yet obtained, the operation returns to step S2, and the calculation of the eigen value and eigen vector of the next axis is executed. The eigen value and the eigen vector for each axis obtained described above are stored in dictionary memory 12.

Claims: A method of obtaining a reference pattern from a plurality of n input patterns of a specific category so that further input patterns can be recognised using the reference patterns, the method comprising the steps of: obtaining a covariance matrix K having elements in n columns and n rows, each element representing a recognition parameter of said input patterns; transforming said covariance matrix K to eigen values and eigen vectors of a predetermined number of axes in accordance with a Karhunen-Loeve expansion; and obtaining a new covariance matrix K' for obtaining eigen vectors and eigen values of axes subsequent to the first axis by subtracting the eigen vector and eigen value of the first axis from said covariance matrix K, characterised in that said Karhunen-Loeve expansion includes a power method comprising: multiplying said covariance matrix K by a first vector ξ1 consisting of elements of a first column of said covariance matrix to obtain a second vector ξ2; obtaining a first maximum element of absolute value ABS(B1) in said second vector ξ2; multiplying said covariance matrix by said second vector ξ2 to obtain a third vector ξ3; obtaining a second maximum element of absolute value ABS(B2) of said third vector ξ3; determining convergence of said second vector and said third vector by comparing ABS(B1) and ABS(B2); and storing said third vector ξ3 as the eigen vector of a first axis and said second maximum element in absolute value ABS (B2) of said third vector ξ3 as the eigen value of said first axis in a dictionary memory, when the convergence of the second and third vector is determined. A method as claimed in claim 1, in which determining convergence of said second and third vectors, comprises: obtaining the difference of the second maximum element of absolute value ABS(B2) with an initial maximum element BO; comparing the difference with a first value based on the second maximum element; if the difference is greater than the first value, then the second maximum element is set as the initial maximum element and the transformation of the covariance matrix R is repeated until the difference is smaller than the first value, obtaining the difference of the second and third vectors; and comparing the vector difference with a second value based on the second maximum element; if the vector difference is greater than the second value then repeating the transformation of the covariance matrix until the vector difference is smaller. A method according to claim 1 or 2, further comprising: normalizing each element of the third vector ξ3 with the norm of the third vector before storing said third vector as the eigen vector. A method according to any one of claims 1 to 3, further comprising: normalizing each element of the second vector ξ2 and the third vector ξ3 in accordance with the first maximum element of absolute value ABS(B1) and the second maximum element of absolute value ABS(B2) when obtaining the first and second maximum elements, respectively. A method according to any one of claims 1 to 4 further comprising: obtaining a new maximum element of absolute value of the new covariance matrix K'; and normalizing each element of the new covariance matrix K' with the new maximum element. An apparatus for obtaining a reference pattern from a plurality of n input patterns of a specific category so that further input patterns can be recognised using the reference patterns, the apparatus comprising: means (1-6) for obtaining a covariance matrix K having elements in n columns and n rows, each element representing a recognition parameter of said input patterns; means (11, 41, 45, 21) for transforming said covariance matrix K to eigen values and eigen vectors of a predetermined number of axes in accordance with a Karhunen-Loeve expansion; means (41, 45) for obtaining a new covariance matrix K' for obtaining eigen vectors and eigen values of axes subsequent to the first axis by subtracting the eigen vector and eigen value of the first axis from said covariance matrix K, characterised in that said Karhunen-Loeve expansion includes means for performing a power method which comprises; means (13, 14, 16) for multiplying said covariance matrix K by a first vector ξ1 consisting of elements of a first column of said covariance matrix to obtain a second vector ξ2; means (41) for obtaining a first maximum element of absolute value ABS(B1) in said second vector ξ2; means (21) for multiplying said covariance matrix by said second vector ξ2 to obtain a third vector ξ3; means (41) for obtaining a second maximum element of absolute value ABS(B2) of said third vector ξ3; means (11, 14, 41) for determining convergence of said second vector and said third vector by comparing ABS(B1) and ABS(B2); and means (5) for storing said third vector ξ3 as the eigen vector of a first axis and said second maximum element in absolute value ABS (B2) of said third vector ξ3 as the eigen value of said first axis in a dictionary memory, when the convergence of the second and third vector is determined. An apparatus as claimed in claim 6, in which said means for determining convergence comprises: means for obtaining the difference of the second maximum element of absolute value ABS(B2) with an initial maximum element BO; means for comparing the difference with a first value based on the second maximum element; if the difference is greater than the first value, then the second maximum element is set as the initial maximum element and the transformation of the covariance matrix R is repeated until the difference is smaller than the first value; means for obtaining the difference of the second and third vectors; and means for comparing the vector difference with a second value based on the second maximum element; if the vector difference is greater than the second value then repeating the transformation of the covariance matrix until the vector difference is smaller.

Inventors: HIRAI, SHOICHI C/O PATENT DIV. TOSHIBA K.K., MATSUURA, HIROSHI C/O PATENT DIV. TOSHIBA K.K.
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: G10L5
IPC codes: G10L15, G10L11, G06T7