INTERFRAME ADAPTIVE VECTOR QUANTIZATION ENCODING APPARATUS

Abstract: In an interframe adaptive quantization encoding appar­ atus to perform efficient encoding of video signals using vector quantization method, analog signals raster-scanned from the left to the right on the screen and from the upper side to the lower side are converted into digital signals, the digital signals per every m picture elements x n lines are made a block and the block data is subjected to mean value separation (12) in a vector quantization encoder thereby input vector is formed, inner product between the input vector and output vector read from a code book ROM (16) is estimated by an inner product operation circuit (14), and maximum value of the inner product is estimated by a maximum inner product detection circuit (15) and made amplitude coefficient, thereby efficient encoding is per­ formed. The efficient encoding data is transmitted to the transmission path by a transmission data buffer and at the same time threshold value of movement detection in the vector quantization encoding is controlled by a movement detection control circuit (13), and the encoding data supplied from the vector quantizer is decoded by a vector quantization decoder and the block data is reproduced, thereby the apparatus can be constituted without increasing the circuit scale.

Description: The present invention relates to an interframe adaptive vector quantization encoding apparatus which performs encoding of video signals at high efficiency using vector quantization, and also to a video encoding transmission apparatus which transmits the encoding signals. First, the principles of vector quantization will be described briefly. The input signal series of K in number are brought together into input vector X = {x₁, x₂, ... x K }. Then, the K-dimensional Euclidean signal space R k ( X ∈R k ) has the representative points of N in number (i.e., output vector) y i = {y i1 , y i2 , ... y ik }, and set of the representative points is made Y = [ y ₁, y ₂, ... y N ]. The vector quantizer determines output vector y i as hereinafter described from the set of output vectors, and retrieves it. The output vector y i is in the minimum distance (minimum distortion to the input vector, and it follows that: if, d( X , y i )<d( X , y i ) for all j X → y i wherein, d( X , y i ) represents distance (distorsion) between input/output vectors. Then, the input vector X is transmitted or recorded in index i of the output vector. At reproduction, set Y of the output vector y i can be determined by clustering using the video signal series being the training model (repetition of the selection of the representative points and the quantization of the training model into each representative point until the total distorsion becoming minimum). Furthermore, in order to improve efficiency of the vector quantization and versatility of the output vector set, the vector quantization may be performed at separation of the mean value of vectors and the normalization in amplitude. An interframe adaptive vector quantization apparatus in the prior art, as is in principle known from Fig. 23 and 26 of EP-A-0 097 858, will be described. Fig. 2 is a block diagram illustrating a constitution example of an encoding member of an interframe adaptive vector quantization apparatus. In Fig. 2, numeral 1 designates an A/D converter, numeral 2 a raster/block scan conversion circuit where digital video signals in raster form by the A/D conversion are made a block per every m picture elements x n lines (m, n: integer), numeral 3 a vector quantization encoder which encodes the block data at high efficiency by means of vector quantization, numeral 4 a transmission data buffer where the encoded data at high efficiency is stored and transmitted to the transmission path at constant speed, numeral 5 a movement detection control circuit which controls threshold value of movement detection in the vector quantization encoder corresponding to the data amount stored in the transmission data buffer, numeral 6 a vector quantization decoder which decodes the encoded data supplied from the vector quantization encoder and reproduces the block data, numeral 7 a variable delay circuit, and numeral 8 a frame memory. Fig. 3 is a block diagram illustrating a constitution example of a decoding member of the interframe adaptive quantization encoding apparatus. In Fig. 3, numeral 9 designates a receiving data buffer where the encoded data supplied from the transmission path is received and stored and then outputted at speed corresponding to the decoding action, numeral 10 a block/raster scan conversion circuit where the block data decoded and reproduced is converted into data in raster form, and numeral 11 a D/A converter. Encoding and decoding operation of the apparatus will now be described referring to Fig. 2 and Fig. 3. Input video signals (101) are analog signals which are raster-scanned from the left to the right on the screen and from the upper side to the lower side. The analog signals in raster form are converted into digital signals (102) by the A/D converter 1, and then the digital signals in raster form are made a block per every m picture elements x n lines (m, n: integer) by the raster/block conversion circuit 2, and further the picture element sample within the block is arranged in one-dimensional arrangement so as to obtain vector data S (103). Difference signal between the vector data S (103) and frame memory vector data P (104) based on the same position block within the frame memory 8 becomes interframe difference vector ε (105), which is inputted to the vector quantization encoder 3. The vector quantization encoder 3 applies processing of mean value separation and normalization to the interframe difference vector ε (105), and performs movement detecting using mean value and amplitude coefficient obtained by the processing and using threshold value (106), and performs vector quantization of only vector of significant block based on the movement. And then the vector quantization encoder 3 encodes the significance/insignificance block information, the mean value, the amplitude coefficient and the vector quantization index information each using variable length encoding or the like, and outputs the encoded data (107). The transmission data buffer 4 stores the encoded data (107) and transmits it to the transmission path at constant speed according to prescribed transmission speed, and estimates data storage amount (108) and supplies it to the movement detection control circuit 5. The movement detection circuit 5 controls the threshold value (106) for the movement detection depending on variation of the data storage amount (108). The encoded data outputted from the vector quantization encoder 3 is decoded according to reverse processing of the encoding in the vector quantization decoder 6, thereby interframe difference reproduction vector ε and (109) is reproduced. The interframe difference reproduction vector ε and (109) obtained in the processing and the frame vector data P (104) delayed by prescribed time by means of the variable delay circuit 7 are added, thereby reproduction vector data S and (110) is restored and the block data at corresponding position of the frame memory is updated. Above process is shown in following expressions. ε = S - P ε = ε + ϑ ( ϑ represents operation error in vector quantization encoding.) S = P + ε P = S ·Z -f (Z -f represents one frame delay.) On the other hand, the encoded data (107) after received and speed-changed in the receiving data buffer 9 is decoded by the vector quantization decoder 6, thereby interframe difference reproduction vector ε and (109) is reproduced (Fig.3). The interframe difference reproduction vector ε and and the frame vector data P (104) passing through the variable delay circuit 7 are added, and reproduction vector data S and (110) is restored in similar manner to the processing in the encoding member. That is, vector operation S = P + ε = S + ϑ is executed. The reproduction vector data S and (110) is converted into data (111) of raster form by the block/raster scan conversion circuit 10, and the data (111) is converted in D/A conversion by the D/A converter 11 so as to obtain analog reproduction video signal (112). Next, constitution and operation of the vector quantization encoder and the vector quantization decoder of the arrangement of Fig.2 will be described in detail. Fig. 5 shows a constitution example of a vector quantization encoder in the prior art. In Fig. 5, numeral 19 designates a mean value separation and normalization circuit, numeral 13 a movement detection circuit, numeral 23 a distortion operation circuit, numeral 20 a minimum distortion detection circuit, numeral 16 a code book ROM, numeral 17 an address counter, and numeral 18 an index latch. Operation of the vector quantization encoder will be described. The mean value separation and normalization circuit 19 performs operation as hereinafter described to interframe difference vector ε (113) being input signal thereof, and converts it into normalization vector x . Assuming that intrablock mean value of ε = [ε₁, ε₂, ....., ε k ] (k = m x n) be m and amplitude factor thereof be σ, it follows that: Approximate expression of σ such that or the like may be used. Assuming that x j =(ε j -m)/σ x =[x₁,x₂,··· ···,x k ] the mean value m, the amplitude factor σ, the normalization vector x can be obtained. The mean value m (114) and the amplitude factor σ (118) obtained are inputted to the movement detection circuit 13, and compared with the threshold values T₀, T₁, thereby the significance/insignificance block discrimination, i.e., the movement detection processing is performed according to following conditions and the block discrimination information ν (121) is outputted. The block discrimination information ν is transmitted per each block. Only in the case that ν is 1, following processing is performed. The normalization vector x (122) is transmitted to the distorsion operation circuit 23 and subjected to following vector quantization processing. Set of a plurality of output vectors y i (116) (i = 1, 2, ..., N) is produced using clustering method based on statistical property of the normalization vector x , and written in the code book ROM 16. When the normalization vector x (122) is inputted to the distortion operation circuit 23, the address counter 17 performs count-up in sequence of i = 1, 2, ..., N, and reads the output vector y i (116) corresponding to the address information i in sequence of y ₁, y ₂, ..., y N from the code book ROM 16 of the output vector. Distortions d ( x , y i ) between the normalization vector x and N output vectors y i read in sequence are calculated sequentially in the distortion operation circuit 23. The distortion calculation is executed according to following formula. Otherwise, approximate expression such that may be used. In the minimum distortion detection circuit 20, the minimum distortion among the N distortions estimated by the above calculation is detected, and the output vector address information i in the code book ROM indicated by the address counter is taken in the index latch 18 and outputted as the output vector index i (120). The intrablock mean value m (114), the amplitude factor (118), the block discrimination information ν (121) and the output vector index i (120), all obtained in the above process, are converted into codes being suitable as the vector quantization encoding information (107) and then outputted. In this case, if ν is 0, codes in other information are not outputted. A vector quantization decoder shown in Fig. 4 will now be described. In Fig. 4, numeral 21 designates an amplitude coefficient multiplier, and numeral 22 a mean value adder. Among the vector quantization encoded information (107) transmitted from the receiving data buffer 9, the block discrimination information ν (121) is first decoded. If ν = 1, i.e., if the block is significant, the decoded output vector index i (120) is taken in the index latch 18. In the code book ROM 16 where the same content as that of the code book ROM of the vector quantization encoder is written, the output vector y i (119) indicated by the index i (120) is read. The amplitude factor σ* (118) is multiplied to the output vector y i in the amplitude coefficient multiplier 21 and the mean value m (114) is added to the product in the mean value adder 22, thereby the interframe difference reproduction vector ε and (109) is decoded. That is, following processing is executed. ε =[ε₁,ε₂,···,ε k ] ε j =σ·y ij +m (j = 1, 2, ···, k ) If ν = 0, i.e., if the block is insignificant, ε is decoded and reproduced assuming that m = 0, σ = 0. ε = [0, 0, ..., 0] The invention will now be described in detail. Next, constitution and operation of the vector quantization encoder and the vector quantization decoder will be described in detail. In Fig. 1, numeral 12 designates a mean value separation circuit which estimates intrablock mean value of interframe difference vector and separates the mean value, numeral 14 an inner product operation circuit which estimates inner product between input vector by the mean value separation and output vector read from a code book ROM, numeral 15 a maximum inner product detection circuit which detects the optimum output vector by estimating maximum value of inner products between input and output vectors obtained with respect to a plurality of output vectors and determines amplitude factor at the vector quantization decoding, numeral 13 a movement detection circuit which performs movement detection using obtained mean value, amplitude factor and threshold value and outputs significance/insignificance block discrimination information, numeral 16 a code book ROM, numeral 17 an address counter, and numeral 18 an index latch. The operation will be described. The mean value separation circuit 12 performs operation as hereinafter described to interframe difference vector ε (113) being input vector, and converts it into input vector x *. Assuming that intrablock mean value of ε = [ε₁,ε₂,···,ε k ] be m, execution of produces the mean value m and the input vector x *. The inner product operation circuit 14 estimates the inner product between the obtained input vector x * and output vector in the code book ROM 16 where set of output vectors y i (116) (i = 1, 2, ..., N) optimized by clustering or the like are written using normalization vector subjected to mean value separation and normalization by x = [x₁, x₂, ..., x k ]. The inner product F (x, y i ) is estimated according to following formula. Among the obtained inner products of N in number, the maximum value is detected by the maximum inner product detection circuit 15 and at the same time the maximum inner product is outputted as amplitude factor σ* to the movement detecting circuit 13. Assuming that the output vector index to provide the maximum inner product be 0 and the input/output vector be two-dimensional vector (k = 2), y ₀ becomes the optimum output vector and the maximum inner product is obtained as amplitude factor. This will be explained referring to Fig. 6. Since y i is subject to mean value separation and normalization, it follows that | y i | = 1 Assuming that angle between x and y i be ϑ, it follows that Consequently, when ϑ = 0, x and y i become vectors in the same direction and the distance within two-dimensional plane becomes minimum. Since condition of cos ϑ is that -1 ≦ cos ϑ ≦ 1, when ϑ = 0, cos ϑ = 1 and F ( x , y i ) becomes maximum. Hence, y₀ to maximize the F ( x , y i ) is obtained as the optimum output vector. Since max F ( x , y i ) may be used as the amplitude factor σ*. The obtained amplitude factor σ* and the mean value m are inputted together to the movement detection circuit 13, and compared with the threshold values T₀, T₁ (106), thereby the significance/insignificance block discrimination, i.e., the movement detection processing is performed according to following conditions and the block discrimination information ν (121) is outputted. The block discrimination information ν is transmitted per each block. The intrablock mean value m (114), the amplitude factor (118), the block discrimination information ν (121) and the output vector index i (120), all obtained in the above process, are converted into codes being suitable as the vector quantization encoding information (107) and then outputted. In this case, if ν = 0, codes in other information are not outputted. Fig. 7 and Fig. 8 show another embodiment of the invention. In this embodiment, an amplitude normalization circuit is removed, and a DPCM encoding circuit and a DPCM decoding circuit are inserted in vector quantization encoding member and decoding member respectively for mean value component and amplitude factor so that introduction of the DPCM encoding removes redundancy for the mean value component and the amplitude factor. Description of this embodiment is performed regarding the case that threshold control is not performed. Fig. 7 shows a constitution example of the vector quantization encoding member. In Fig. 7, numeral 12 designates a mean value separation circuit, numeral 14 an inner product operation circuit, numeral 15 a maximum inner product detection circuit, numeral 16 a waveform code book ROM, numeral 17 an address counter, numeral 18 an index latch, numeral 25 a DPCM encoding circuit, and numeral 26 an encoding circuit. Also, Fig. 8 shows a constitution example of the vector quantization decoding member. In Fig. 8, numeral 27 designates a DPCM decoding circuit, numeral 21 an amplitude factor multiplier, numeral 22 a mean value adder, and numeral 3 a decoding circuit. In the vector quantization encoding member constituted as above described, the mean value component m (114) is processed in similar manner to the preceeding embodiment, and its redundant component is deleted by the DPCM encoding circuit 25 and the difference signal dµ (123) is outputted. On the other hand, the mean value separation vector x * (115) is processed in similar manner to the preceeding embodiment, and the maximum inner product Fmax (118) is detected by the maximum inner product operation circuit 15, and normalization address information i is taken in the index latch 18 and outputted as the normalization output vector index i (120). The detected maximum inner product Fmax (118) is inputted as the amplitude factor g directly to the DPCM encoding circuit 25, and its redundant component is deleted and then the difference signal dg (124) is outputted. The DPCM encoding circuit output dµ (123) for the mean value component m (114), the DPCM encoding circuit dg (124) for the amplitude factor g (118), and the normalization output vector index i (120) are subjected to variable length encoding in the encoding circuit 26. Next, the vector quantization decoding operation will be described. The difference signal dµ (123) of the mean value component m, the difference signal dg (124) of the amplitude factor g, and the normalization output vector index i (120) are decoded in sequence in the decoding circuit 3. The mean value m (114) is decoded and reproduced in the DPCM decoding circuit 27, and the amplitude factor gi (118) is decoded and reproduced in the DPCM encoding circuit 27. The normalization output vector index i (120) is taken in the index latch 18, and the normalization output vector y i (116) with address indicated by the normalization output vector index i (120) is read and decoded within the waveform code book ROM 16 where the same content as that of the waveform code book ROM 16 in the vector quantization encoding member is written. The normalization output vector y i (116) is multiplied by the decoded amplitude factor g j (123) in the amplitude factor multiplier 21, and the decoded mean value component µ (114) is added to the product thereby the encoding reproduction vector S and (109) is obtained.

Claims: An interframe prediction videocoder comprising a circuit (4, 26 in Fig. 7) outputting the output signal (107, 125 in fig.7) of the videocoder a DPCM-loop having a subtractor outputting interframe difference vectors (105, 113 in Fig.1,5 and 7) a vector quantization encoder (3) processing the interframe difference vectors (105, 113) in blocks, a vector quantization decoder (6), an adder, a delay circuit (7) and a frame memory (8), a code book ROM (16) containing a set of output vectors (116) an index latch (18) for storing an address of the code book ROM (16) and for providing an output vector index (120), characterized in that the vector quantization encoder (3) comprises a mean value separation circuit (12) calculating an intrablock mean value (114) of the interframe difference vectors (113) and converting the actual interframe difference vector (113) into an input vector (115) by subtracting the mean value (114) from the actual interframe difference vector (113) an inner product operation circuit (14) calculating the inner products (117) of the input vector (115) and the output vectors (116) of the code book ROM (16) a maximum inner product detection circuit (15) detecting and outputting the maximum inner product used as an amplitude factor (118) the index latch (18) storing the address of the code book ROM (16) location which holds the optimum output vector producing the maximum inner product, and providing the output vector index (120) indicating the optimum output vector the mean value (114), the amplitude factor (118) and the output vector index (120) being contained in the encoded output signal (107) of the vector quantization encoder (3). A videocoder as claimed in claim 1, characterized in that the circuit (4) is a transmission data buffer (4), the videocoder further contains a movement detection control circuit (5) controlling a threshold value (106) for the movement detection depending on variation of the data storage amount (108) of the transmission data buffer (4), the vector quantization encoder (3) further contains a movement detection circuit (13) outputting a block discrimination information (121) dependent on the mean value (114), the amplitude factor (118) and the threshold value (106), the encoded output signal (107) further includes the block discrimination information (121) and, in case the block discrimination information (121) equals zero, only the block discrimination information (121) is contained in the encoded output signal (107). A videocoder as claimed in claim 1, characterized in that the circuit (26) is a variable length encoder (26), the vector quantization encoder (3) further contains at least one DPCM encoding circuit (25) for removing redundancy in the mean value (114) and the amplitude factor (118) and outputting a mean value component (123) and an amplitude factor component (124) which are encoded in a variable length encoder (26) together with the output vector index (120).

Inventors: ASAI, KOHTARO MITSUBISHI DENKI K.K., ITOH, ATSUSHI MITSUBISHI DENKI K.K., KAMIZAWA, KOH MITSUBISHI DENKI K.K., MURAKAMI, TOKUMICHI MITSUBISHI DENKI K.K., NISHIDA, MASAMI MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1986
Main classification: H04N7
IPC codes: H04N11, H04N7, G06T9