PROXIMITY DIFFUSION METHOD FOR GROUP III-V SEMICONDUCTORS

Abstract: A proximity diffusion method for diffusing a dopant into a group III-V substrate includes depositing a dopant on at least a portion of a first substrate. A second substrate which is a group III-V substrate is positioned so that it is substantially in contact with the dopant deposited on the first substrate. Then, the firstr and second substrates are heated while they are positioned substantially in contact so as to perform thermal diffusion to diffuse the dopant into the second substrate. A cap layer may be selectively formed on portions of the second substrate prior to the positioning step, so that the diffusion regions formed by the heating step will be defined by the selectively formed cap layer. The method allows for thermal diffusion into group III-V substrates which normally dissociate at temperatures at which thermal diffusion takes place. In addition, since the dopant does not need to be positioned directly on the group III-V substrate, problems relating to the thermal mismatch of the dopant layer and the substrate, which can lead to enhanced lateral diffusion, can be avoided.

Description: PROXI ITY DIFFUSION METHOD FOR GROUP III-V SEMICONDUCTORS BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of diffusing a dopant into a group III-V semiconductor, and particularly to a method in which thermal diffusion is employed. 2. Description of the Related Art The use of group III-V semiconductors, such as gallium arsenide (GaAs) and indium phosphide (InP), in the fabrication of a variety of semiconductor devices is known. However, when subjected to a heating process such as thermal diffusion, the group III-V semiconductors tend to dissociate at relatively low temperatures. For example, GaAs decomposes at 550°C. That is, the arsenic dissociates at that temperature. Similarly, InP has a phosphorous dissociation temperature of 350°C. As a result of these low dissociation temperatures the use of thermal diffusion is limited, since diffusion temperatures are generally required to be higher than the dissociation temperatures of GaAs and InP. An alternative to thermal diffusion is an ion implantation process. However, when a deep diffusion is required, it is necessary to employ thermal diffusion. Thus, ion implantation is not a completely acceptable substitute for thermal diffusion. Several methods have been developed in an effort to overcome the low temperature dissociation characteristic of group III-V semiconductors. A sealed tube diffusion method has been developed, 5 wherein a substrate and dopant are placed in a tube which is then sealed. The substrate (e.g., GaAs or InP) is placed in a boat and a dopant or source is also placed in the boat. The p-type dopants include zinc (Zn), cadmium (Cd) , beryllium (Be) and magnesium -*- 0 (mg) . The n-type dopants include tin (Sn) , silicon (Si) and selenium (Se) . Sealed tube diffusion is generally carried out at a temperature of at least 650°C with arsenic or phosphorous overpressure. The overpressure is employed to prevent the dissociation 15 of the arsenic or phosphorous from the substrate. The sealed tube method is disadvantageous in that tight control of vapor pressure is required to obtain a desired surface concentration and junction depth. In addition, the use of the sealed tube complicates 20 the commercial device fabrication process and slows down fabrication considerably. Several open tube diffusion techniques have been developed to avoid the disadvantages of the sealed tube technique. A first type of open tube 2 ^ diffusion technique involves placing a group III-V substrate in a boat in an open tube and pumping a gas (e.g., diethyl-zinc and triethyl-arsine) into the tube as described in "GaAs J-FET Formed by Localized Zn Diffusion", Dohsen et al., IEEE ELECTRON DEVICE 30 LETTERS, Vol. EDL-2, No. 7, July 1981, pps. 157- 158. The arsine gas source is used to deter the decomposition or dissociation of the arsenic from the GaAs substrate. That is, the arsine gas is an overpressure for preventing dissociation. If an InP 35 substrate is used, then a phosphine gas is used as the overpressure source. The disadvantage of this type of open tube diffusion technique is that it requires the use of toxic gas sources, and the arsenic vapor pressure is essential to controlling 5 the diffusion and protecting the surface of the substrate. A second type of open tube diffusion technique is described in "An Open-Tube Method for Diffusion of Zinc into GaAs", Field et al., J. i° Electrochem. Soc. : Solid-state Science and Technology, July 1982, pp. 1567-1570; "Precisely Controlled Shallow p+ Diffusions in GaAs", Ghandi et al., Appl. Phys. Lett. 38(4), 15 February 1981, pps. 267-269; and "Planar Diffusion in Gallium Arsenide i5 from Tin-Doped Oxides", Baliga et al., J. Electrochem. Soc: Solid-state Science and Technology, January 1979, pp. 135-138. In this technique, phosphosilicate glass (PSG) is used as a cap and mask for preventing dissociation of arsenic 20 from a GaAs substrate. For example, a tin-doped silicon dioxide layer is formed on a GaAs substrate and a PSG mask is formed over the tin-doped silicon dioxide and the GaAs substrate. Then, thermal diffusion takes place, with the PSG mask preventing 5 the dissociation of arsenic from the GaAs substrate. As described in "Lateral Diffusion of Zinc and Tin in Gallium Arsenide", Baliga et al., IEEE Transactions on Electron Devices, Vol. ED-21, No. 7, July 1974, pp. 410-415, lateral diffusion is 0 ideally limited to the diffusion depth. However, when a thermal mismatch occurs, the lateral diffusion can be as much as 10 times greater than the diffusion depth. In particular, stresses occur at the interface of the substrate and the PSG mask, thereby 5 leading to enhanced lateral diffusion. The lateral diffusion is reduced by matching the thermal coefficient of expansion of the interfaced materials. The 1979 Baliga et al. publication recognizes that enhanced lateral diffusion will occur because of the mismatch in the thermal expansion coefficients of the PSG mask and the GaAs substrate. The 1979 Baliga et al. publication seeks to overcome this problem by adjusting the phosphorous content of the PSG mask in order to achieve a thermal expansion coefficient matching the thermal expansion coefficient of the GaAs substrate. However, this technique has disadvantages in that the doped oxide still has a different thermal coefficient (higher) than the undoped oxide, because silicon dioxide has a very low thermal expansion coefficient (0.3 x 10 —6cm/°C) . This thermal mismatch will increase lateral diffusion due to the interfacial stress between the substrate (e.g., GaAs with a coefficient —6 of 5.9 x 10 cm/°C) and the doped oxide. As a result, arsenic vapor pressure is often required to suppress the lateral diffusion (e.g., when a tin diffusion is employed) . A further disadvantage is that the percentage of dopant (e.g., tin or zinc) in the doped oxide is critical because the SiO_ cannot be doped too much or there will be a problem in controlling growth. Finally, the diffusion constant of Ga in Si0 2 is five orders of magnitude larger than that for As. Therefore, the surface of the GaAs substrate will be depleted of Ga. A third type of open tube diffusion technique is referred to as a spin-on source technique which is described in "Thermal Diffusion of Tin in GaAs From a Spin-On SnO_/Si0 2 Source", Nissim et al., Appl. Phys. Lett. 37(1), 1 July 1980, pp. 89-91. In this technique, a spin-on source (e.g., Sn0 2 /Si0 2 ) and a silicon dioxide cap are used for diffusion of tin in GaAs. The use of the spin-on source is a quick way of depositing a layer of dopant on a substrate. In particular, this is much quicker than using chemical vapor deposition or sputtering, although it also provides a much lower grade of film. The disadvantages of using the spin-on source are that thicknesses (particularly the capping layer thickness) are critical, and any abrupt change in temperature will result in film peeling. Lateral diffusion is enhanced because there are numerous thermal mismatches between the substrate, the insulator (e.g., Si^N.) and the spin-on source. Finally, the diffusion profile depends on the rate of the thermal ramp (to avoid the above-described abrupt changes in temperature) . There remains a need in the art for a simple thermal diffusion method which will provide acceptable thermal diffusion characteristics, without the disadvantages of enhanced lateral diffusion. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of diffusing a dopant into a group III-V semiconductor by employing a thermal diffusion technique. In particular, it is an object of the present invention to provide a thermal diffusion method which prevents the dissociation of an element from the group III-V semiconductor and avoids the enhanced lateral diffusion which is prevalent in prior art methods. The present invention is directed to a method of diffusing a dopant into a group III-V semiconductor. In the method of the invention, a dopant is deposited on at least a portion of a first substrate, and a second substrate, which is a group III-V substrate, is positioned so that it is substantially in contact with the dopant deposited on 5 the first substrate. Then, the first and second substrates are heated while positioned substantially in contact to perform thermal diffusion, thereby diffusing the dopant into the second substrate. A second embodiment of the method of the 10 invention also includes a step of selectively forming a cap layer on portions of the second substrate (i.e., a cap layer with windows formed therein) prior to positioning the second substrate substantially in contact with the dopant deposited on the first 15 substrate. As a result, when the heating step takes place, the diffusion regions in the second substrate will be defined by the selectively formed cap layer. In a third embodiment of the method of the invention, a cap layer is selectively formed on 2.0 portions of a first group III-V substrate and a dopant is deposited on the cap layer and in the windows of the first group III-V substrate. Then, a second group III-V substrate is positioned so that it is substantially in contact with the dopant deposited 25 on the cap layer of the first group III-V substrate. The substrates are heated to thermally diffuse the dopant deposited in the windows of the first group III-V substrate into the first group III- V substrate, while also diffusing the dopant into the 30 second group III-V substrate. The proximity diffusion method of the present invention offers significant advantages over the prior art. The diffusion method of the invention has all the simplicity of prior open tube diffusion 35 methods, while avoiding the enhanced lateral diffusion problems which are inherent in those methods. Since the dopant is not required to be deposited on the III-V substrate, there is no thermal mismatch problem (with respect to the dopant and the substrate). Further, the low stresses at the interface of the substrate and the mask will not cause enhanced lateral diffusion and redistribution of the dopant will not occur. These together with other objects and advantages which will be subsequently apparent reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings, forming a part hereof, wherein like numerals refer to like parts throughout. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an open tube diffusion apparatus which can be employed for performing the diffusion method of the present invention; FIG. 2A is an exploded cross-sectional view of the arrangement of substrates in accordance with a first embodiment of the method of the present invention; FIG. 2B is a cross-sectional view of the group III-V substrate 32 after diffusion has been carried out in accordance with the first embodiment of the method of the present invention; FIG. 3A is an exploded cross-sectional view of the arrangement of the substrates in accordance with a second embodiment of the method of the present invention; FIG. 3B is a cross-sectional view of the group III-V substrate 36 after diffusion has been carried out in accordance with the second embodiment of the method of the present invention; FIG. 4A is an exploded cross-sectional view of the arrangement of the substrates in accordance with a variation of the first embodiment of the method of the present invention; FIG. 4B is a cross-sectional view of the group III-V substrate 46 the diffusion has been carried out in accordance with the variation of the first embodiment of the method of the present invention; FIG. 5A is an exploded cross-sectional view of the arrangement of the substrates in accordance with a third embodiment of the method of the present invention; FIG. 5B is a cross-sectional view of the group III-V substrate 54 after diffusion has been carried out in accordance with the third embodiment of the method of the present invention; FIG. 5C is a cross-sectional view of the group III-V substrate 28a after diffusion has been carried out in accordance with the third embodiment of the method of the present invention; FIG. 6 is a SIMS profile showing the dopant profile of zinc in GaAs; FIG. 7 is a graph of the IV characteristic of a diode fabricated in accordance with the method of the present invention; and FIG. 8 is an exploded cross-sectional view of the arrangement of substrates within a boat for providing a controlled diffusion process in accordance with a fourth embodiment of the method of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of the present invention includes a heating step which may be carried out in an open tube furnace 20 of the type illustrated in FIG. 1. The open tube furnace 20 includes a tube 22 and a base 24 on which substrates may be placed. A heat source 26 which may be, for example, radiant heating coils, is positioned around the tube 22. The open tube furance 20 also has gas inlets and outlets (not shown) through which appropriate diffusion gases are pumped. The first embodiment of the method of the present invention will be described with respect to FIGS. 2A and 2B. Referring to FIG. 2A, a source substrate 28 has a dopant 30 deposited thereon. In the preferred embodiment, the dopants for the diffusion of n or p-type layers are deposited in the form of oxides, such as zinc oxide (ZnO) and tin oxide (SnO,) , which may be deposited to a thickness β of 300 to 1000 A using plasma chemical vapor deposition or sputtering techniques. The surface damage due to electron bombardment can be annealed out during the high temperature diffusion cycle. The source substrate 28 may be a group III-V substrate or it may be fused quartz. The present invention takes advantage of the property that if GaAs substrates are placed on top of each other, dissociation of As will not occur at the contacting surfaces. This is also true for silicon substrates and quartz substrates. Thus, according to the method of the present invention, a group III-V substrate 32 (e.g., GaAs or InP) is positioned substantially in contact with the dopant 30 on the source substrate 28. FIG. 2A shows the arrangement of group III-V substrate 32 and source substrate 28 in exploded form to make it clear that the dopant is formed on the source substrate 28 and not on the group III-V substrate 32. Of course, in reality, the source substrate 28 rests on the base 24 and the group III-V substrate 32 is positioned to be substantially in contact with the dopant 30. If desired, some pressure can be placed on the group III-V substrate 32 to press it into contact with the dopant 30. After the substrates 28 and 32 have been arranged as illustrated in FIG. 2A, they are subjected to a heating step so as to perform thermal diffusion to diffuse the dopant into the group III-V substrate 32. This diffusion is carried out in the open tube furnace 20 (FIG. 1) , and the temperature and time of diffusion are set in accordance with the required diffusion depths. In the method of the invention diffusion is carried out at a temperature of from 550 β C to 1000 β C, with lower temperatures (e.g., 650 β C) being employed for certain substrates (e.g., InP). After diffusion, the group III-V substrate 32 will have a diffusion region 34 formed therein (FIG. 2B) . It should be noted that the dopant 30 will also diffuse into the source substrate 28. The source substrate 28 may be reused as long as a sufficient amount of dopant 30 is deposited on the source substrate 28. For convenience, .the group III-V semiconductor 32 is referred to as a substrate. However, the method of the invention may be used to form diffusion regions in any group III-V semiconductor (including ternaries and quaternaries of the group III-V semiconductors) wherever they are formed. For example, the method of the invention can be used to form a diffusion region in a group III-V semiconductor layer on which a contact is to be formed. Thus, the term group III-V substrate is intended to include any group III-V semiconductor layer carried by a substrate. FIG. 3A is a cross-sectional view illustrating the arrangement of substrates in accordance with a second embodiment of the method of the present invention. In this embodiment, a group III-V substrate 36 has a cap layer 38 formed thereon, with windows 40 etched in the cap layer. The cap layer be any suitable type of masking material, for example, aluminum nitride (A1N) . A1N is a desirable capping or masking material because of its close thermal match to GaAs. In particular, the thermal coefficient of A1N is 6.1 x 10 "β cm/ β C, while the thermal coefficient for GaAs is 5.9 x lθ "δ cm/ β C. The cap layer 38 is deposited by sputtering techniques or plasma chemical vapor deposition techniques, and the windows 40 are cut into the cap layer 38 by reactive ion etching to obtain straight walls. If straight walls are not required, chemical etching or plasma etching may be employed. The group III-V substrate 36 is positioned in contact with the source substrate 28, so that the cap layer 38 is substantially in contact with the dopant 30, and the substrates 28 and 36 are placed in the open tube furnace 20 to perform thermal diffusion of the dopant into the portions of the group III-V substrate exposed by the windows 40. In view of the close thermal match between A1N and GaAs, no enhanced lateral diffusion will occur in the group III-V substrate 36. FIG. 3B is a cross- sectional view of. the group III-V substrate 36 after thermal diffusion has taken place. Diffusion regions 42 are formed in the group III-V substrate 36 through the windows 40. FIG. 4A is a cross-sectional view of an arrangement of substrates in accordance with a variation of the first embodiment of the method of the present invention. In this embodiment, dopant 44 is selectively deposited on the source substrate 28 to form the desired diffusion pattern. Then, a group III-V substrate 46 is positioned in contact with the dopant 44 and thermal diffusion is carried out in the open tube furnace 20. After diffusion, the group III-V substrate 46 will have diffusion regions 43 formed therein (FIG. 4B) . In practice, the embodiment described with respect to FIGS. 4A and 4B will not provide diffusion regions which are as precisely defined as the diffusion regions 42 of FIG. 3B. That is, more lateral diffusion will occur. FIG. 5A is a cross-sectional view of an arrangement of substrates in accordance with a third embodiment of the method of the present invention, in which a cap layer 50 is selectively formed on source substrate 28a which is a group III-V substrate. Then, a dopant 52 is formed on the cap layer 50 and the exposed portions of the source substrate 28a. A group III-V substrate 54 is positioned substantially in contact with the dopant 52 on the source substrate 28a, and diffusion is carried out in the open tube furnace 20. After diffusion has taken place, the group III-V substrate 54 will have a diffusion region 56 formed therein (FIG. 5B) , while the source substrate 28a will have diffusion regions 58 formed therein (FIG. 5C) . Thus, in this embodiment, the cap layer 50 is used to form windows in the source substrate 28a. In this embodiment, the thermal coefficient at the edges of the substrate, mask and dopant are 5.9 x 10 *β cm/ β C (GaAs), 6.1 x lθ "β cm/ β C (A1N) and 5.0 x 10 "6 cm/ e C (ZnO) . If tin oxide is used as the dopant, the thermal coefficient for Snθ2 is 3.5 x 10 "6 cm/ e C. A SIMS (secondary ion mask spectroscopy) profile of Zn in GaAs was obtained using the technique of the method of the present invention, and is illustrated in FIG. 6. The substrate was n-doped GaAs with a carrier concentration of 10 16cm—_. The diffusion temperature was 650 e C (10 minutes) . As illustrated, by using the method of the present invention, Zn diffuses into a GaAs substrate without dissociation of As. FIG. 7 is a graph of the IV characteristic of a pn diode which was fabricated in accordance with the method of the present invention, and which shows that the diode exhibits the appropriate IV characteristic. It has been shown that arsenic vapor pressure in the ambient reduces the diffusion coefficient of zinc in GaAs. Thus, the substrates may be arranged as described with respect to FIG. 3A and then placed in a boat with a lid on it. FIG. 8 discloses an embodiment in which the arrangement of FIG. 3A is placed in a boat 60 having a lid 62 and partitions 64. The substrates 28 and 36 are placed in a central compartment 66 of the boat 60, while a source material 68 (e.g., GaAs or InAs powder) is placed in side compartments 70 of the boat 60. If the group III-V substrate 36 is InP, then InP power may be used as the source material 68. As the arsenic decomposes into the atmosphere with heating, the diffusion is slowed down in order to provide critical control of the diffusion process. For a shallow diffusion the type of control provided is similar to the results achieved by a shallow ion implantation for a p-type dopant. The method of the present invention provides significant advantages over prior art open tube diffusion techniques. The method of the present invention can be modified to fabricate a variety of devices including MISFET's, MESFET's, J-FET's, bipolar transistors, avalanche photodiodes, impatt devices, and other electronic and optoelectronic devices. By using the method of the present invention, a cap layer (e.g., cap layer 38) can be selected so that it has a good thermal match with respect to the particular group III-V substrate to be employed. For example, A1N is a good thermal match for a GaAs substrate. As a result, the stresses induced by heating will be low and lateral diffusion will be reduced. The proximity diffusion method of the present invention is simple and has all the advantages of other open tube diffusion methods, while overcoming some of the disadvantages inherent in those methods. This is done primarily by placing the dopant on the source substrate 28 (e.g., FIG. 3A, to avoid thermal mismatch between the group III-V substrate and the dopant) instead of on the group III-V substrate on which devices are to be formed. Enhanced lateral diffusion and redistribution of the dopant will not occur because of the low stress at the interface of the substrate and the mask (e.g., an- A1N cap) . Thus, by employing the method of the present invention, the low stresses observed for ion implantation can be obtained, while at the same time allowing use of a thermal diffusion method. By employing the method of the present invention, diffusion depths can be readily controlled since the vapor pressure of the dopant source is lower than that of the element, so that shallow diffusion can be achieved. For example, the vapor pressure of zinc oxide is 10 —6 at 950 β C. Additional control of diffusion can be obtained by performing the diffusion process through a thin layer of A1N film. The many features and advantages of the invention as apparent from the detailed specification, and thus it is intended by the appended claims to cover all such features and advantages of the method which fall within the true spirit and scope of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation shown and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

Claims: WHAT IS CLAIMED IS; 1. A method of diffusing a dopant into a group III-V semiconductor comprising the steps of: (a) providing a first substrate; (b) depositing a dopant on at least a portion of the first substrate; (c) positioning a second substrate which is a group III-V substrate, so that it is substantially in contact with the dopant deposited on the first substrate; and (d) heating the first and second substrates while they are positioned substantially in contact to perform thermal diffusion, thereby diffusing the dopant into the second substrate. 2. A method as set forth in claim 1, further comprising the step of selectively forming a cap on portions of the second substrate prior to said positioning step (c) , wherein said positioning step (c) comprises positioning the second substrate so that the cap is in contact with the dopant on the first substrate, wherein the diffusion region formed by said heating step (d) is defined by the selectively formed cap. 3. A method as set forth in claim 2, wherein said step of selectively forming a cap comprises depositing a cap layer on the second substrate and forming windows in the cap layer by reactive ion etching. 4. A method as set forth in claim 3, wherein said step of depositing the cap layer comprises depositing the cap layer by sputtering. 5. A method as set forth in claim 3, wherein said step of depositing the cap layer comprises depositing the cap layer by plasma chemical vapor deposition. 6. A method as set forth in claim 3, wherein said step (b) comprises depositing a dopant selected from the group consisting of zinc oxide and tin oxide, and wherein said step (c) comprises positioning a second substrate selected from the group consisting of GaAs and InP. 7. A method as set forth in claim 6, wherein said step of selectively forming a cap comprises selectively forming A1N on portions of the second substrate. 8. A method as set forth in claim 1, wherein said step (b) comprises depositing a dopant selected from the group consisting of zinc oxide and tin oxide, and wherein said step (c) comprises positioning a second substrate selected from the group consisting of GaAs and InP. 9. A method as set forth in claim 8, wherein said step (d) comprises heating the first and second substrates to a temperature greater than 550 β C. 10. A method as set forth in claim 9, wherein said step (d) comprises heating the first and second substrates to a temperature of from 550°C to 1000 β C. 11. A method of forming diffusion regions in a group III-V semiconductor, comprising the steps of: (a) providing a first group III-V substrate; (b) selectively forming a cap layer on portions of the first group III-V substrate so as to 5 ' define windows exposing portions of the first group III-V substrate; (c) depositing a dopant on the cap layer and on the exposed portions of the first group III-V substrate; 10. (d) positioning a second group III-V substrate so that it is substantially in contact with the dopant deposited on the cap layer; and (e) heating the first and second substrates to thermally diffuse the dopant deposited 15 in the windows of the first substrate into the first substrate. 12. A method as set forth in claim 11, wherein said step (b) comprises depositing a cap layer on the first group III-V substrate and forming 20 windows in the cap layer by reactive ion etching. 13. A method as set forth in claim 12, wherein said step (b) further ' comprises depositing the cap layer by sputtering. 14. A method as set forth in claim 12, 25 wherein said step (b) further comprises depositing the cap layer by plasma chemical vapor deposition. 15. A method as set forth in claim 12, wherein said step (c) comprises depositing a dopant selected from the group consisting of zinc oxide and 30 tin oxide, and wherein said step (d) comprises positioning a second group III-V substrate selected from the group consisting of GaAs and InP. 16. A method as set forth in claim 15, wherein said step (b) comprises selectively forming 35 A1N on portions of the first group III-V substrate. 17. A method as set forth in claim 11, wherein the first and second group III-V substrates are selected from the group consisting of GaAs and InP, and wherein said step (c) comprises depositing a dopant selected from the group consisting of zinc oxide and tin oxide. 18. A method as set forth in claim 17, wherein said step (e) comprises heating the first and second group III-V substrates to a temperature greater than 550 β C. 19. A method as set forth claim 18, wherein said step (e) comprises heating the first and second group III-V substrates to a temperature of from 550 β C to 1000°C. 20. A method of diffusing a dopant into a group III-V semiconductor, comprising the steps of: (a) providing a first substrate; (b) depositing a dopant on at least a portion of the first substrate; (c) positioning a second substrate which is a group III-V substrate, so that it is substantially in contact with the dopant deposited on the first substrate; (d) placing the positioned first and second substrates in an enclosure with a source material for controlling diffusion; and (e) heating the enclosure including the first and second substrates which are positioned substantially in contact to perform thermal diffusion, thereby diffusing the dopant into the second substrate, said heating step decomposing the source material to slow down the thermal diffusion so as to provide control of the diffusion process. 21. A method as set forth in claim 20, further comprising the step of selectively forming a cap on portions of the second substrate prior to said positioning step (c) , wherein said positioning step (c) comprises positioning the second substrate so that the cap is in contact with the dopant on the first substrate, wherein the diffusion region formed by said heating step (e) is defined by the selectively formed cap. 22. A method as set forth in claim 21, wherein said step (c) comprises positioning a second substrate selected from the group consisting of GaAs and InP, and wherein said step (d) comprises placing a source material selected from the group consisting of GaAs, InAs and InP in the enclosure.

Inventors: FATHIMULLA MOHAMMED AYUB, FATHIMULLA, MOHAMMED, AYUB
Applicants: ALLIED CORP, ALLIED CORPORATION
Application year: 1986
Main classification: H01L21
IPC codes: H01L21