A MICROPROGRAM CONTROL SYSTEM

Abstract: Micro instructions having a predetermined relation are modified so that an original micro instruction and address assigned thereto can be restored by combining one or more modified micro instructions and address assigned thereto. A microprogram memory (8) stores the micro instructions in such modified form and at the modified address. When an original address is designated, one or more term lines are activated in a decoder (86, 88) of the microprogram memory (8), and modified micro instructions corresponding to the activated term lines are led from a memory array (82, 84) of the microprogram memory (8). The read modified micro instruc­ tions are logically combined to restore the original micro in­ struction. Thereby, the number of micro instructions to be ac­ tually stored in the microprogram memory (8) can be reduced.

Description: BACKGROUND OF THE INVENTION Field of The Invention The present invention relates to a microprogram control system having a microprogram memory which comprises decoding means for decoding addresses of a microprogram and memory means connected with the decoding means through micro instruction selecting lines for storing micro instructions of the microprogram, wherein the execution of macro instruction read from a main memory is completed by successively executing a set of micro instructions prepared for the macro instruction in the memory means. Particularly, the invention relates to a microprogram control system having a microprogram memory which can be constructed of a reduced quantity of hardware or can utilize its storage capacity effectively, while having a compatibility or flexibility for a general purpose use, and further which is suited for application of LSI technology. Description of The Related Art With the recent remarkable progress in the MOS (Metal Oxide Semiconductor) technology, a high density of integration in integrated circuits has been achieved, resulting in the appearance of microcomputers of higher performance and improved functions. The higher density of integration is accompanied by the more complicated logic, and thus the main concerns and efforts are now concentrated on methods of constructing an integrated circuit by means of logic circuits which have regular structures. As one of them, a microprogram control system is well known. In such a system, there is usually provided a memory called a microprogram memory or a control memory for its exclusive use, which comprises a ROM (Read Only Memo). There are stored in the ROM a lot of micro instruction sets, each of which corresponds to a specific macro instruction. Namely, one of the macro instructions is composed of a plurality of micro instructions which are prepared suitably for execution of the macro instruction. Although a lot of micro instructions for various kinds of macro instructions are stored in the ROM, it is rarely that micro instructions for completing the execution of a certain macro instruction are all different from those for some other maro instructions. On the contrary, there are many cases where some of micro instructions for a certain macro instruction are common to those for many other macro instructions. In some cases, a micro instruction for one macro instruction has quite the same function as that for the other macro instruction except the difference in a next address included in both micro instructions. In a conventional system, all the micro instructions have been assigned particular addresses in the address space of the ROM, respectively, whether the content of the micro instuctions is the same as or similar to that of other micro instructions or not. Consequently, in the ROM, there exist a plurality of micro instructions which have a common bit pattern in the considerable part thereof, so that the ROM is inefficiently used. This results in increase in the necessary storage capacity of the ROM. In order to improve this, Japanese Patent Laid-Open No. 57-203141 is known, for example. According thereto, there are provided a first microprogram memory for storing micro instructions of the long word length which are capable of being used for the general purpose, a second microprogram memory for storing micro instructions of the shortened word length which are used often but for the limited purpose and a bit pattern generator which produces a signal having a predetermined bit pattern and adds the produced signal to the shortened word length micro instruction to restore the long word length micro instruction when the shortened word length micro instruction is read out from the memory. In this way, micro instructions used frequently are described and stored in the shortened word length so as to increase the working efficiency of the capacity of the ROM. Although this system is effective as a means to reduce the capacity of the ROM, it lacks compatibility in the general purpose use, since the processing content capable of being expressed by the micro instructions of the shortened word length is limited and not all micro instructions can be expressd, when the ROM storing the micro instructions of the shortened word length is employed for storing other micro instructions. This is because a group of micro instructions of the shortened word length for use of the limited purpose is formed therein. Also, when micro instructions for processing macro instructions of a different instruction system are formed, not all the micro instructions can be expressed by the micro instructions already stored in the ROM for those of the shortened word length in which the group of the exclusively-used micro instructions is formed. Consequently, for such an alteration, it is necessitated to construct other bit pattern generators generating many kinds of such a bit pattern as is generated by the aforesaid bit pattern generator. Thus, the ROM storing the micro instructions of the shortened word length lacks compatibility and flexibility for the general purpose employment. Furthermore, EP-A-0 089 469 discloses an instruction control word decoder which allows to encode additional microinstructions by means of unused bits in microinstruction words which are shorter than the normal word length of m bits. Particularly, the known system utilizes X unused decoding values from an m-bit control word to obtain together with n bits of the control word additional X·2 n command signals. For this purpose, an additional logic circuit is provided in the microinstruction decoder. This system has the disadvantage that it depends on X decoded values which are not used for other purposes. SUMMARY OF THE INVENTION It is therefore an object of the invention to provide a microprogram control system being able to utilize the storage capacity of the microprogram memory efficiently, i.e. which can store a large number of micro instructions in a comparably small microprogram memory. The solution of this object is achieved by the invention characterized in claim 1. The invention is based on the idea that it is not necessary to store each micro instruction in the memory array if a group micro instructions has a common bit pattern. In the present invention, micro instructions having a predetermined relation are modified so that an original micro instruction and address assigned thereto can be restored by combining one or more modified micro instructions and modified addresses assigned thereto. The microprogram memory according to the present invention stores micro instructions in such a modified form and at locations corresponding to the modified addresses. When an original address is applied to the decoding means, for at least one of the micro instructions, two selecting lines are activated and the modified micro instructions corresponding to the activated micro instruction selecting lines are read from the memory means. The read modified micro instructions are logically combined to restore the original micro instruction. According to an example in the present invention, the above mentioned modification of micro instructions are achieved among micro instructions which have a common bit pattern, i.e a common code, in considerable fields (a common field) of the micro instruction except a certain specific field arbitrarily noted. To those micro instructions are assigned particular original addresses, and the aforesaid specific field of each micro instruction is coded with a predetermined relation to the original address assigned thereto. The original addresses and the codes of the specific fields are modified so that an original address can be restored by combining one or more modified addresses and a code of a specific field can be also restored by logically combining the modified codes of the specific fields corresponding to the combined modified addresses. In another example, the modification of micro instructions is made for micro instructions each consisting of the common fields and the specific field which has the bit pattern capable of being realized by logically combining the specific fields of some of the micro instructions. A certain one among such micro instructions is assigned an address having a bit pattern which can be restored by logically combining addresses assigned to the micro instructions which are combined for realizing the specific field of the certain micro instruction. According to the present invention, the number of micro instructions to be stored in a microprogram memory is compressed, since a micro instruction can be realized by logically combining one or more other micro instructions actually stored in the memory. Such a compression of micro instructions enables the reduction of the necessary storage capacity of the memory for attaining the same performance. This results in the reduction of the area the microprogram memory occupies on an LSI chip. On the contrary, in case the storage capacity of the memory is fixed, more micro instructions can be realized in accordance with the present invention. This causes the high performance of the microprogram control system. Further, according to the present invention, the effect or advantage as mentioned above can be achieved without shortening the word length of micro instructions. Therefore, the compatibililty or flexibility, which is greatly limited by the shortened word length micro instructions, is not injured at all. Also, any additional elements or parts, such as a bit pattern generator as used in the conventional microprogram system, are not required. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram schematically showing a whole construction of a microprogram control system according to an embodiment of the present invention ; Fig. 1a is an explanatory diagram showing an example of typical micro instructions ; Fig. 2 is a time chart for explaining the operation of the micro instruction control system shown in Fig. 1 ; Fig. 3 schematically shows a structure of a microprogram memory used in the microprogram control system shown in Fig. 1 ; Figs. 4a to 4f are an explanatory diagram and tables for explaining an example of the modification for compression of micro instructions ; Figs. 5a and 5b show an example of a set of compressed micro instructions and the related portion of the microprogram memory in which the compressed micro instructions are allocated ; Figs. 6a to 6d are tables for explaining another example to the modification for compression of micro instructions ; Figs. 7a to 7c are tables for explaining still another example of the modification for compression of micro instructions ; Figs. 8a and 8b show another example of a set of micro instructions and the related portion of the microprogram memory in which the micro instructions are allocated ; and Fig. 9 is a block diagram schematically showing a whole construction of a microprogram control system according to another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 1, a whole construction of a microprogram control system according to an embodiment of the present invention will be explained. In the figure, a reference numeral 2 denotes an instruction register which temporarily stores a macro instruction read out from a main memory (not shown) storing a user program. In this case, it is assumed that the macro instruction is composed of 8 bits. The macro instruction stored in the register 2 are led to an address selector 4, to which also a part of a micro instruction described later is applied. The selector 4 selects either one of an output signal 2R of the register 2 and a part 10Y of the micro instruction in response to a signal 10Z which is also a part of the micro instruction and will be described in detail later. A selected signal 4S is led to a microprogram address register 6 and temporarily stored therein. Although the reason becomes apparent later, the register 6 has the number of bits which is by at least one bit more than that of the instruction register 2. In this case, therefore, the register 6 consists of 9 bits, as the instruction register 2 has 8 bits. A content 6T of the microprogram address register 6 is inputted to a microprogram memory 8. In correspondence to the content 6T, a micro instruction is read out from the memory 8, which is taken into a micro instruction register 10 through lines 8W and temporarily stored therein. A part 10X of the micro instruction is applied to a micro instruction decoder (not shown), in which the signal 10X is decoded and various kinds of control signals are generated in accordance with the result of decoding. These signals control various elements of a processing system, such as a main memory, an operating unit, peripheral devices and so on. Therefore, the so-called operation code is included in this part 10X. The remaining parts 10Y and 10Z of the micro instruction are led to the address selector 4, as described before. It is noted that, in this case, the part 10Y consists of 8 bits and the part 10Z has one bit. Accordingly, the register 6 needs 9 bits, as described before. Usually, a microprogram memory compries a decoder part and a microprogram memory part which is made of ROM. In the microprogram memory 8 used in the present embodiment, the microprogram memory part is divided into two parts, one of which is called a primary microprogram memory array 82 and the other a secondary microprogram memory array 84. The respective memory arrays 82, 84 have separate decoders 86, 88. The signal 6T given from the register 6 is decoded in the decoders 86, 88, and access to the memory arrays 82, 84 is made in accordance with the result of decoding through micro instruction selecting lines 86U, 88V, respectively. A typical example of the micro instruction read out from the microprogram memory 8 is as shown in Fig. 1a. In this example, the micro instruction is made up by plural fields which are functionally distinguished from one another. A first field is a next address field. As stated before, the execution of a macro instruction is completed by successively executing a set of micro instructions one after another. Therefore, each micro instruction includes an address of the next micro instruction to be executed. The content of this field indicates such an address. A second field is a mode field, the function of which is control of the address selector 4. If this field takes a certain value, e.g. a logical "1", the selector 4 selects the signal 2R from the instruction register 2, so that the microprogram address register 6 takes the content of the register 6, i.e. the macro instruction thereinto. The remaining five fields include operation codes. Briefly speaking, their functions are as follows ; Memory Control : Initiation control of read/write operation in a main memory or input/output devices ; Temporary Register Control : Control of registers in which the results of the arithmetic logic operation are temporarily stored ; ALU Control : Control of the operation in an arithmetic logic unit ; Condition Code Control : Control of information to be stored in a status register or a condition code register ; and RAM Control : Control of read/write mode of registers constructed in a RAM (Random Access Memory). These operation code fields as a whole correspond to the signal 10X as shown in Fig. 1. Further, the first field corresponds to the signal 10Y and the second field to the signal 10Z. Next, the brief description will be made of the operation of the system shown in Fig. 1, referring to a time chart of Fig. 2. The system of Fig. 1 is activated by two system clocks CK1 and CK2 as shown in Figs. 2(a) and (b). These clocks CK1 and CK2 have the same frequency and the difference of 180 degree in the phase. However there is no overlapping duration in the pulse width between both clocks CK1 and CK2. Now assuming that the execution of a certain macro instruction has been completed, and that the next macro instruction has been just read out from the main memory to the instruction register 2 (cf. Fig. 2(c)). The register 2 holds the read macro instruction thereafter until the subsequent one is read out, as shown in Fig. 2(d). Usually, the last one of a set of micro instructions for executing a macro instructions has the logical value "1" in its mode field. Therefore, by means of completion of the execution of the certain macro instruction, the logical value "1" is applied to the address selector 4 as the signal 10Z, so that the selector 4 selects the signal 2R, as mentioned before. Accordingly, the content of the instruction register 2 is taken into the microprogram address register 6 at timing of the clock CK1, as shown in Fig. 2(e), and further it is led to the decoders 86, 88 at timing of the clock CK2, as shown in Fig. 2(f). Within the same clock, the micro instruction is read out from the memory arrays 82, 84 and led to the micro instruction register 10, as shown in Fig. 2(g). The micro instruction register 10 holds the read micro instruction until the next micro instruction is inputted, as shown in Fig. 2(h). As shown in Fig. 1a, the micro instruction includes an address indicating the location within the memory 8 where the micro instruction to be executed next is stored. Such a next address is transferred to the address selector 4 as the signal 10Y. Further, the micro instruction, except the last one, has the logical value "0" in its mode field. In the case mentioned above, therefore, the signal "0" is applied to the selector 4 as the signal 10Z, so that the selector 4 selects the signal 10Y. The next address included in the previous micro instruction is stored in the microprogram address register 6 at timing of the clock CK1, as shown in Fig. 2(e). After that, the same operation as described above continues in response to the clocks CK1, CK2 until the execution of the last one of a set of micro instructions for the macro instruction is perfected, as show in Figs. 2(e) to (h). As is apparent from the above description, one entry of a set of micro instructions for a macro instruction is directly designated by the macro instruction itself, not through an instruction decoder as usually utilized, which decodes a macro instruction to produce an address of an entry micro instruction. Namely, the macro instruction itself has information of an address of an entry micro instuction. As a so-called mapping ROM system is known the system in which, in such a way as mentioned above, a macro instruction read out from a main memory, or an operation code included therein; can directly designate an address indicating the location of an entry micro instruction of a microprogram stored in a ROM. Fig. 1 shows an example in which the present invention is embodied in a microporogram control system of the mapping ROM type as mentioned above. However, it should be understood that the application of the present invention is not limted to the mapping ROM type system, but the invention can be applied to every types of the microprogram control system. This will be apparent from the explanation later. Referring now to Fig. 3, the detailed structure of the microprogram memory 8 used in this embodiment will be explained hereinafter. In the following description, the references used for the expression of signals in Fig. 1 are also utilized for indicating lines which carry the corresponding signals. Now, the output signal from the microprogram address register 6 is led to a mode line and address lines of the decoders 86, 88 of the microprogram memory 8. As described before, the output signal 6T consists of 9 bits, one bit of which corresponds to the mode signal supplied through the line 10Z and the remaining eight bits to the next address signal led through the line 10Y. In Fig. 3, a line No. 0 is a mode line and line Nos. 1 to 8 are address lines. The mode line and the address lines are extended through both the decoders 86, 88, each of which consists of a pair of lines, one of them being directly connected with a corresponding bit of the address register 6 and the other being connected therewith through an inverter. The former is called a positive line, e.g. a positive address line, and the latter a negative line, e.g. a negative address line. Micro instruction selecting lines called product term lines (simply called a term line, hereinafter) 86U, 88V are crossed with all the mode and address lines. In the figure, however, only six term lines are shown as examples. At selected cross points of the term lines and the mode or address lines, NMOS transistors are so provided that a source and a drain electrodes thereof are connected with the term line and a gate electrode is supplied with a signal through the mode or address line, as shown within a broken-line circle I in the figure. The cross points provided with the transistors are determined in dependence on the bit patterns, i.e. the codes, of the addresses assigned to the micro instructions. Namely, a transistor is provided in accordance with the following rule. If a certain bit of the code is "1", a transistor is provided at a cross point of the term line and the possitive mode/address line corresponding to the certain bit. On the contrary, if "0" is set at another bit of the code, a transistor is provided at a cross point of the term line and the negative mode/address line corresponding to the another bit. Further, if there is provided no transistors at cross points of the term line and both the positive and negative mode/address lines corresponding to a certain bit, it means that the certain bit is treated as a don't care bit which has neither "0" nor "1". The term lines are further crossed with a clock lines CK2, and at all cross points thereof, NMOS transistors are provided in the same way as described above. In the figure, the cross points provided with the transistors are indicated by small circles. One ends of all the term lines are grounded and the other ends are extended into the memory arrays 82, 84 through PMOS transisters driven by the clock CK1 and inverters. The term lines extended from the decoders 86, 88 are crossed with a plurality of data lines which are extended through the memory arrays 82, 84. The number of the data lines corresponds to the number of bits constructing the micro instruction. At selected cross poins of the term lines and the data lines, there are provided NMOS transistors in such a manner as shown within the broken-line circle II in the figure. Namely, a drain electrode of the transistor is connected with the data line and a source electrode thereof is grounded. The transistor is driven by a signal applied to a gate electrode through the term line to ground the data line. Although the cross points to be provided with the transistors are determined in accordance with the bit pattern, i.e. the code, of the micro instructions to be stored in the memory arrays 82, 84, the indication of such cross points are omitted in the figure. One ends of the data lines are connected to the voltage source V cc through corresponding PMOS transistors which are driven by the clock CK1 . The other ends thereof are led to clocked inverters which form the micro instruction register 10. These clocked inverters are controlled by the clock CK2. Next, referring to Fig. 4, the explanation is done of the principle in accordance with which the construction of the above described microprogram memory 8 is achieved. Now suppose that there exist macro instructions A, B, C and D which are schematically represented by respective flow charts of micro steps as shown in Fig. 4a. Namely, the macro instruction A consists of micro steps A1, P and A2. Similarly, the macro instruction B consists of micro steps B1, P and B2, the macro instruction C of micro steps C1, P and C2, and the macro instruction D of micro steps D1, P and D2. Accordingly, the macro instructions A, B, C and D all include the common micro step P. Fig. 4b illustratively shows the manner in which such micro instructions are stored in a conventional microprogram memory. In this figure, the micro instructions are indicated, devided into three parts, for simpler explanation. The first part is a mode field as shown in Fig. 1a. Similarly, the second part is a next address field and the third part consists of all the remaining fields including operation codes. Although the mode field and the next address field in this figure are reversed in the order of their position, compared with those in Fig. 1a, this is only for convenience sake of explanation and there is nothing to do with the essentials of the invention. Characters a, b, c and d appearing in assigned addresses and the next adddress fields represent particular bit pattern composed of 6 bits, e.g. a: "010100", b: "010101", c: "010110" and d: "011000". Therefore, the next address "a01" means "01010001" and the address "b00" means "01010100". The same is applied to other cases. Symbols [A], [B], [C] and [D] appearing in the assigned addresses indicate that these have address values directly designated by the macro instructions A, B, C and D. In other words, the macro instructions A, B, C and D have bit patterns indicating these addresses, respectively. Further, a symbol [-] included in the next address field represents that an arbitrary bit pattern can be taken for this field. Usually, all 8 bits are filled with "0". It is to be noted that there exists this symbol only in the last one of a set of micro nstructions for each macro instruction. Namely, the specific value is not necessary in the next address field of the last micro instruction, because an address of a micro instruction to be executed next is given by a subsequent macro instruction. In the third part of the micro instructions, and operation code and remaining codes are as a whole indicated by the same reference characters as those of the micro steps. Taking an example of the macro instruction A, the explanation is briefly made of the execution of the macro instruction. At first, the macro instruction A read out from the main memory is stored in the instruction register 2, and the address [A] is designated by the macro instruction A. The micro instruction stored at the address [A] is read out. The operation code etc. A1 included in the read micro instruction is decoded and executed. Simultaneously, the mode "0" and the next address "a00" are applied to the address selector 4, which selects the next address "a00" because of the mode "0". Thereby, the micro instruction at the address "a00" is read out, and the operation is executed in accordance with the operation code etc. P. The mode "0" and the next address "a01" are sent to the address selector 4. Also this time the selector 4 selects the next address included in the micro instruction, i.e. "a01", because of the mode "0" Accordingly, the micro instruction at the address "a01" is read out, and the operation is executed in accordance with the operation code etc. A2. At the same time, the mode "1" and the next address [-] are led to the address selector 4. The execution of the macro instruction A is completed by finishing the execution of this micro instruction. In response to the mode "1", the selector 4 selects a new macro instruction which has been read into the instruction register 2 from the main memory subsequently to the macro instruction A. In cases of the macro instructions B, C and D, the execution thereof is done in the same way. As is seen from Fig. 4b, the micro instructions including the operation code P have almost the same bit pattern and the difference only in the next address field. In this way, in the conventional memory, there exist a plurality of micro instruction which have the common bit pattern in the considerable part of fields except certain specific fields, and those micro instructions each occupy a particular address within the address space of the memory. This results in the ineffectual use of the memory, which, in some cases, is accompanied with the unnecessary increase of the capacity of the memory. In order to preventing this, according to the present invention, micro instructions are compressed to the reduced number of micro instructions by the assignment of address to micro instructions and the modification for allocation thereof on a microprogram memory which are made as follows. First of all, from among all micro instructions to be considered for compression, micro instructions the micro code (i.e. bit pattern) of which is common to one another in the fields except specific fields arbitrarily noted in the micro instructions are all gathered. The field which has the common micro code is called a common field, hereinafter. The result of having gathered such micro instructions is as shown in Fig. 4c. In this case, the specific field mentioned above is the next address field. Here, the gathered micro instructions of the addresses "a00", "b00", c00", and "d00" are named micro instructions Pa, Pb, Pc and Pd, respectively, for convenience of the following explanation. Next, the gathered micro instructions are assigned particular addresses which are used when the respective micro instructions are read out from the microprogram memory. These assigned addresses are called an original address, hereinafter. In the example shown in Fig. 4d, the micro instructions Pa, Pb, Pc and Pd are assigned original addresses "J00", "J01", "J10" and "J11", respectively, whrein J indicates the given bit pattern of 6 bits, similarly to a, b, c and d in Fig. 4b. As is apparent from Fig. 4d, the assigned original address comprises a part having the common bit pattern J and a part having a particular bit pattern for each original address. For convenience of the following explanation, the former is called common bits and the latter distinguishing bits hereinafter. The distinguishing bits have the number of bits which is sufficient to express the distinction in the addresses of all the gathered micro instructions. In the case of Fig. 4d, since the number of the gathered micro instructions is four, two bits, such as "00", "01", "10" and "11" are used for this purpose. The codes of the specific fields of those micro instructions, i.e. the next address field in this case, are determined in accordance with the predetermined relation with the original address assigned to the respective micro instructions. In the case shown in the figure, with respect to the micro instructions Pa, Pb, Pc and Pd are assigned the original addresses "J00", "J01","J10" and "J11", respectively, the codes "K00", "K01", "K10" and "K11" are given to the respective next address fields, wherein K also indicates the given bit pattern consisting of 6 bits. The above mentioned predetermined relation is explained as follows, with the aid of the well known Hamming's distance. Namely, when the micro instructions are arranged in the order of the original addresses assigned thereto, the Hamming's distance between the assigned original addresses of the micro instructions adjacent to each other is equal to that between the micro codes of the specific fields included in the two micro instructions, and further assuming that the number of the gathered micro instructions is m and the maximum value of the allowable Hamming's distance is n, the following relation is satisfied ; 2 n-1 < m ≦ 2 n (1) Fig. 4e is a table showing the result of having reviewed the above mentioned relation with respect to the assignment of address shown in Fig. 4d. As is apparent from this table, the Hamming's distance between the assigned addresses of the micro instructions Pa and Pb, for example, is equal to that between the next addresses included therein. Further, since the number m of the gathered micro instructions is four, the maximum value n of the Hamming's distance is two as those between the micro distances Pb, Pc and Pd, Pa. In other words, more generally speaking about the predetermined relation mentioned above, with respect to two micro instructions which satisfy the aforesaid relation (1), the codes of the specific fields of these micro instructions are so determined that the Hamming's distance between the codes of the specific fields is equal to that between the original addresses of those micro instructions. Now, it should be noted from Fig. 4d that the bit pattern of the micro instruction Pd can be realized by taking a logical add of the remaining three micro instructions. Taking this fact into consideration, the micro instructions are modified for allocation on the microprogram memory. Referring to Fig. 4f, the method of this modification is explained. First of all, there is provided a modified micro instruction (called a primary micro instruction, hereinafter) which has certain micro codes in both the common field and the specific field. In Fig. 4f, the micro instuction which has the code "P" in the operation code field and the code "K00" in the next address field corresponds to the primary micro instruction. The distinguishing bits of the address code assigned to the primary micro instruction are all made the don't care bits which carry neither "0" nor "1". In the figure, the address expressed by the code "J**" is assigned to the primary micro instruction, whrein the asterisk * indicates the don't care bit. As described before, such a don't care bit can be realized by providing no transistor at both points at which a pair of address lines of the bit marked with the asterisk crosses the term line. Next, there are prepared a plurality of address codes, one of the distinguishing bits of which is the care bit of "0" or "1" and the remaining bits are made the don't care bit, and by the logical add of the given combination of the prepared address codes the original addresses of all the gathered micro instructions can be restored. In the example of Fig. 4f, the address codes "J*1" and "J1*" are prepared. These address "J*1" and "J1*", including the address "J**", are called a modified address, hereinafter. The common field of each of the modified micro instructions assigned to the thus prepared address codes is made either "0" in all bits thereof or the same bit pattern as that of the common field of the primary micro instruction. In Fig. 4f, a symbol ϑ indicates that bits in question are all "0". The specific field of each of the secondary micro instructions is modified as follows. Namely, the portion corresponding to the common bits are made either "0" in all bits thereof or the same bit pattern as that of the common bits of the specific field in the primary micro instruction. The distinguishing bits of the specific field are so coded that they have "1" in at least one bit thereof and the bit pattern of the distinguishing bits in the micro instruction of the original address restored by the combination of the modified addresses can be generated by the logical add of the combination of the secondary micro instructions corresponding to the combined modified addresses. For example, assuming that the micro instruction Pc is read out which has the code "P" in the operation code field and the code "K10" in the next address field. In order to read out this, the original address "J10" must be designated (cf. Fig. 4c). Now, in Fig. 4f, suppose the operation code field and the common bits of the next address field in the secondary micro instructions are made "0" in all bits thereof. At this time, if the modified addresses "J**" and "J1*" are combined by the logical add, the original address "J10" can be restored, because the don't care bit can be regarded as being functionally equal to "0". By combining in the logical add the modified micro instructions corresponding to these addresses "J**" and "J1*", the operation code "P" can be obtained and the code of the next address field becomes "K10". Allocation of the micro instructions on the memory is conducted in accordance with the modification as shown in Fig. 4f. Feferring to Fig. 5, the explanation is made of the concrete structure when the modified micro instructions as shown in Fig. 4f are allocated in the microprogram memory 8 shown in Fig. 3. In this case, it is assumed that the bit patterns J and K are "011000" and "011001", respectively. Therefore, the original micro instructions Pa, Pb, Pc and Pd are shown as in Fig. 5a. In accordance with the modified micro instructions shown in Fig. 4f, every lines in the decoders 86,88 and the memory arrays 82, 84 are wired as shown in Fig. 5b. This figure shows only the related portion of the microprogram memory 8 as shown in Fig. 3. If the code "01100000" (the assigned address of the micro instruction Pa) is applied to the address lines 1 to 8 (here assuming that the mode field is "0"), only the term line 86U1 which is precharged by the clock CK1 is grounded in synchronism with the clock CK2, so that the term line 86U1 in the memory array 82 is kept at high level. This state of the term line in the memory arrays 82, 84 is called "activated" hereinafter. As a result, the data lines in the memory arrays 82, 84 which have a transistor at a point where the term line 86U1 crosses are grounded, so that the code "01100100" appears at the lines 10Y. Accordingly, the micro instruction Pa with the code " 01100100" in the next address field can be read out by designating the original address "01100000". Although the operation code "P" of the read micro instruction Pa appears at the lines 10X, the data lines corresponding the lines 10X are omitted in the figure. Further, if the code "01100001" (the assigned address of the micro instruction Pb) is applied to the address lines 1 to 8, the term lines 86U1 and 88V1 are activated, so that the data lines which have a transistor at a point where the term lines 86U1 and 88V1 cross therewith are grounded, and hence the code "01100101" appears at the lines 10Y. Of course, in this case, the operation code "P" read out by the term line 86U1 appears at the lines 10X. By designating the original address "01100001", the micro instruction Pb can be read out. Moreover, if the code "01100011" (the assigned address of the micro instruction Pd) is applied to the address lines 1 to 8, the term lines 86U1, 88V1 and 88V2 are activated, so that the data lines which have a transistor at a point where the term lines 86U1, 88V1 and 88V2 cross therewith are grounded. As a result, the code "01100111" appears at the lines 10Y. Also in this case, the operation code "P" read out by the term line 86U1 appears at the lines 10X. The micro instruction Pd can be read out by designating the address code "01100011". As is apparent from Fig. 5b, the primary one of the modified micro instructions is stored in the primary microprogram memory array 82, and the decoder 86 associated therewith is wired in accordance with the bit pattern of the modified address assigned to the primary micro instruction. Similarly, the secondary one of the modified micro instructions is stored in the secondary microprogram memory array 84, and the decoder 88 associated therewith is wired in accordance with the bit pattern of the modified address assigned to the secondary micro instructions. In this embodiment, as described above, four necessary micro instructions are realized by one primary and two secondary micro instructions, i.e. three modified micro instructions actually stored in the microprogram memory. In other words, it can be said that, according to this embodiment, four original micro instructions are compressed to three micro instructions. The more the micro instructions having the common field are gathered, the more effect can be gained. Fig. 6a shows another example in which eight micro instructions Pa to Ph having the common bit pattern P are collected. Similarly to the case of Fig. 4c, codes "a00" to "h00" indicate addresses assigned to the micro instructions Pa to Ph, respectively, and codes "a01" to "h01" are next address codes included in the respective micro instructions Pa to Ph. With respect to these micro instructions, the assignment of the original address and the coding of the specific field are conducted in accordance with the method described above. The result thereof is shown in Fig. 6b. In this case, the distinguishing bits of 3 bits must be prepared in the address code in order to express the distinction in the addresses of eight micro instructions. Therefore, the common bits J' of the original addresses assigned to the micro instructions and the common bits K' of the next address fields have the given bit patterns consisting of 5 bits, respectively, if, similarly to the case of Fig. 4, the address code is composed of total 8 bits. Further, the result of the modification is as shown in Fig. 6c. The primary one of the modified micro instructions which has the code "P" in the operation code field and the code "K'000" in the next address field is assignd the modified address "J'***". In this example, the operation code fields in three secondary ones of the modified micro instructions are made "0" in all bits thereof. One of the three secondary micro instructions is assigned the modified address "J'**1" and has the code "ϑ001" in the next address field, and another one is assigned the modified address "J'*1*" and has the code "ϑ010" in the next address field. The last secondary micro instruction which has the code "ϑ100" in the next address field is assigned the modified address "J'1**". In the same manner as shown in Fig. 5b, the decoders 86, 88 are wired in accordance with the modified codes "J'***", J'**1", "J'*1*" and "J'1**". In the memory arrays, the operation code "P" and the code "K'000" of the next address field are stored at the location corresponding to the modified address "J'***" in the primary microprogram memory array 82, and one of modified micro instructions of the operation code "ϑ" and the next address code "ϑ001", another one of the operation code "ϑ" and the next address code "ϑ010" and the last one of the operation code "ϑ" and the next address code "O100" are stored at the respective corresponding addresses in the secondary microprogram memory array 84. In this way, in this example, eight micro instructions can be compressed to four modified micro instructions actually stored in the microprogram memory 8. Referring again to Fig. 6b, the distinguishing bits of the next address field contained in a certain micro instruction have the same bit pattern as that of the original address assigned to the certain micro instruction. The same also applied to the case of Fig. 4d. However, it is not always necessary to make the bit pattern of the distinguishing bits agree with each other between the assigned original address and the next address field. In a table framed by the broken line in Fig. 6b, there is shown an example in which the bit patterns of the distinguishing bits of the next address fields are not always the same as those of the assigned original addresses. Even in such a case, the compression of the micro instructions is possible, if the assignment of the original address and the coding of the next address field are conducted in accordance with the principle described before. Fig. 6d shows the result of having reviewed the Hamming's distance with respect to the example shown in the broken-line table in Fig. 6b. It will be understood that the result is the same as that of the case shown in the solid-line table. In a broken-line table of Fig. 6c, there is shown the result of coding of the next address field in the modified micro instruction which is achieved on the basis of the example as shown in the broken-line table of Fig. 6b. Fig. 7 shows still another example of the compression of the micro instructions. As is apparent from gathered micro instructions Pa to Qh as shown in Fig. 7a, in this example the different opoeration codes "P" and "Q" are included therein. Further, with respect to every operation codes, four micro instructions are gathered which have the different bit patterns in the next address fields, respectively. Namely in this example, the compression of the micro instructions is tried over the groups of micro instructions, each group having the particular operation code. First of all, through the micro instruction groups, the assignment of the original address and the coding of the next address field are executed in accordance with the principle mentioned before, the result of which is shown in Fig. 7b. Although the number of micro instruction belonging to each group is four, three bits are provided for the distinguishing bits in the original address code and the next address field, because the total number of micro instructions gathered as an object of the compression is eight and the code of three bits is necessary for expressing the distinction of eight addresses. The modification for allocation on the microprogram memory is done as follow. Concerning the micro instructions of the group having the operation code "P", the following modification is possible in the same manner as shown in Fig. 4; In the same way, with respect to the micro instructions of the gorup having the operation code "Q" : From two tables above, it is noted that two sets of the secondary micro instructions are common to each other except the first bit of the distinguishing bits of the respective assigned addresses. Then, if this bit is made the don't care bit, that is to say, if the distinguishing bits of the assigned addresses in both sets of secondary micro instructions are made "J'**1" and "J'*1*", those two sets of the secondary micro instructions become quite common so that they can be used for both combinations with the primary micro instruction having the operation code "P" and with the primary micro instruction having the operation code "Q". Finally therefore, the modified micro instructions as shwon in Fig. 7c can be abtained. In this example, the eight micro instructions which have the different operation codes are compressed to the four modified micro instructions which comprise two primary micro instructions and two secondary micro instructions. Generally speaking on the effect of the compression according to the present method, it can be said as follows. Namely, if the number of gathered micro instructions which have the same micro code, i.e. the same bit pattern, is 2 n (n = 0,1,2, . . . . .), such micro instructions can be compressed to modified micro instructions of n + 1. Further, if there are m groups of the so gathered micro instructions and hence the total number of micro instructions is 2 n X m (m = 1, 2, 3, .....), those micro instructions can be compressed to modified micro instructons of n + m. In the examples as described hitherto, the specific field arbitrarily noted for compression was the next address field. However, the specific field is not limited thereto. The compression of the micro instructions is possible even when other fields are noted as the specific field mentioned above. Fig. 8 shows such a case wherein the operation code field is taken note of as the specific field. As shown in Fig. 8a, assuming that there exist three micro instructions u, v and w, which are assigned addresses "01010010", "01010100" and "01010110" and have codes "000101", "011000" and "011101" in their operation code fields, respectively. In the case of this example, the bit patterns of the assigned address and the operation code field in the micro instruction w can be obtained by the logical add of those of the micro instructions u and v. Fig. 8b illustrates the concrete structure, but the related portion, of the microprogram memory 8 when the micro instructions shown in Fig. 8a are allocated therein. It is to be noted that 6 bits of each operation code are not realized in the successive data lines of the memory array 82, but are dispersedly allocated. Namely, the first three bits are allocated to the data lines X₂, X₃, X₄ and the remaining bits to the data lines X j-1 , X j , X j+1 . Then, if the code "01010010" is applied to the address lines 1 to 8 (at this time, assumed that the mode is "0"), the term line 86U2 is activated, so that the operation code "000101" appears at the corresponding bits of the lines 10X. Therefore, the micro instruction u can be read out by designating the address "01010010" assigned thereto. Similarly, when the code "01010100" is applied to the address lines 1 to 8, the term line 86U3 is activated, so that the operation code "011000" appears at the corresponding bits of the lines 10X. Accordingly, the micro instruction v can be read out by designating the address "01010100" assigned thereto. If the code "01010110" is applied to the address lines 1 to 8, the term lines 86U2 and 86U3 are activated simultaneously, so that the code "000101" read by the activated line 86U2 and the code "011000" read by the activated term line 86U3 appear at the corresponding data lines. This is equivalent to that the two codes read out are added logically. As a result, the operation code "011101" is outputted on the corresponding bits of the lines 10X. Namely, the micro instruction w is read out as the logical add of the micro instructions u and v actually stored in the memory array 82. Referring now to Fig. 9, there is shown a whole construction of the microprogram control system according to another embodiment of the present invention. In the figure, the same reference numerals or characters indicate the same elements as those shown in Fig. 1. The feature different from the embodiment of Fig. 1 is in that decoding of a macro instruction supplied from a main memory (not shown) and that of a part (a next address field) of a micro instruction read from a microprogram memory 8 are conducted by two separate sets of decoders 861, 881 and 862, 882. Namely, the macro instruction, which is read out from the main memory and stored in an instruction register 2, is decoded by a set of the decoders 861 and 881, and access to a primary and a secondary microprogram memory arrays 82 and 84 is made through lines 861U and 881V. A part of the micro instruction led from a micro instruction register 10 is temporarily stored in a microprogram address register 6 and decoded by another set of the decoders 862 and 882. Thereby the access to the primary and the secondary microprogram memory arrays 82 and 84 is made through lines 862U and 882V. When the memory arrays 82 and 84 are made access from the decoders 861 and 881, that is, in the case of the access by the macro instruction, the micro instruction read from the memory arrays 82 and 84 is led to a multiplexer 12 through a line 8W1, and when the memory arrays 82 and 84 are made access from the decoders 862 and 882, the read micro instruction is led to the multiplexer 12 through a line 8W2. The multiplexer 12 selects eigher one of the micro instructions led through the lines 8W1 and 8W2 in response to a signal 6L applied from the microprogam address register 6, and outputs the selected micro instruction to the micro instruction register 10. The signal 6L from the address register 6 also controls the switchover of the operations of two sets of the decoders 861, 881 and 862, 882. Namely, the signal 6L is led to the decoders 861, 881 directly and to the decoders 862, 882 through an inverter 14. The signal 6L is produced in correspondence with the mode field, which is included in the micro instruction and, as described before, supplied to the address register 6 through a line 10Z. If the mode field is "0", the signal 6L of low level is produced. The low level signal 6L is inverted in the inverter 14 to allow the decoders 862, 882 access to the memory arrays 82, 84, and inhibits the decoders 861, 862 from making access to the memory arrays 82, 84. Simultaneously, the low level signal 6L has the multiplexer 12 select the micro instruction led through the line 8W2. To the contrary, if the mode field is "1", the signal 6L is made high level. The high level signal 6L is led to the decoders 861, 881 to enable them, so that the access to the memory arrays 861, 881 caused by the macro instruction is allowed. At this time, the multiplexer 12 selects the micro instruction read out through the line 8W1 in response to the high level signal 6L. The micro instruction selected in the multiplexer 12 is temporarily stored in the micro instruction register 10. A part of the stored micro instruction, which includes the operation code field, is led to a micro instruction decoder (not shown) through a line 10X, in which it is decoded and various kinds of control signals are generated to execute the micro instruction. The remaining part of the micro instruction stored in the register 10, which includes the next address field and the mode field, is led to the microprogram address register 6 through the lines 10Y and 10Z. The operation after that is as described above. In the system mentioned above, the microprogram memory 8 is constructed in almost the same manner as that of Fig. 1, except that the outputs of the decoders 861, 881 and 862, 882 are gated in response to the signal 6L. Accordingly, the allocation of micro instructions on the memory arrays 82, 84 and the wiring of the decoders 861, 881, 862, 882 are also achieved in the same manner as those described in connection with the embodiment of Fig. 1. The effect of this embodiment which is superior to that of fig. 1 is in the reduction of duration from time when a certain micro instruction has been read out to time when the successive micro instruction is read, because the address selector 4 used in Fig. 1 is omitted. Actually, this time duration seriously affects the performance of the microprogram control system. Therefore, its reduction results in the much improved performance of the system.

Claims: A microprogram control system, in which the execution of a macroinstruction stored in a main memory is effected by successively executing a plurality of microinstructions read out from a microprogram memory (8) in accordance with the macro instruction; said microprogram memory (8) comprising a memory array (82, 84) for storing the micro instructions; and a decoder (86, 88) for decoding an address of a microinstruction and activating a microinstruction selecting line (86U, 88V) coupled to said memory array (82, 84) in accordance with the decoded address, characterized in that a plurality of microinstructions (Pa...Pd) having a field of a common bit pattern (P) and a field of a bit pattern (K00...K11) specific to each microinstruction is grouped in the microprogram memory (8) so that the Hamming distance between their addresses (J00...J11) is equal to the Hamming distance between their specific bit patterns (K00...K11), that said plurality of microinstructions (Pa...Pd) is stored in the memory array (82, 84) in a modified form, that, for at least one (Pb, Pc, Pd) of said plurality of microinstructions (Pa...Pd) having a common bit pattern (P), the decoder activates at least two selecting lines (86U,88V), when the address of said at least one microinstruction (Pb, Pc, Pd) is applied to the decoder (86, 88), and that said at least one microinstruction (Pb, Pc, Pd) is obtained from the microprogram memory (8) by logically combining said modified microinstructions stored in the memory array (82, 84) at locations corresponding to said at least two selecting lines (86U, 88V). The system of claim 1, wherein the address of an entry of a set of micro instructions prepared for a macro instruction can be directly designated by the macro instruction read from the main memory. The system of claim 2, wherein there are provided a first decoder (861, 881) for decoding a macro instruction read from the main memory to activate at least one of the micro instruction selecting lines (861U, 881V) and a second decoder (862 , 882) for decoding a micro instruction read from the microprogram memory (82, 84) to activate at least one of the micro instruction selecting lines (862U, 882V). The system of any of claims 1 to 3, wherein at least one (Pa) of the modified micro instructions (primary micro instruction Pa) includes the bit pattern (P) of the common field, and a micro instruction selecting line (86U, 88V) wired in accordance with the primary micro instruction (Pa) is activated every time when one of the addresses of the original micro instructions (Pa ... Pd) is designated. The system of any one of claims 1 to 3, wherein said plurality of micro instructions (Pa...Pd) having a common bit pattern (P), wherein the bit pattern in the specific field of some of them can be formed by logically combining the specific fields of some others of them, are assigned addresses the bit pattern of which can be restored by logically combining addresses of the micro instructions contributing to form the bit pattern of the specific field, and the decoder (86, 88) is wired in accordance with the thus assigned addresses.

Inventors: KIDA, HIROYUKI, MAEJIMA, HIDEO
Applicants: HITACHI, LTD.
Application year: 1986
Main classification: G06F9
IPC codes: G06F9