CHIP INTERFACE MESA

Abstract: Apparatus for providing microelectronic, intra-chip and chip-to-chip interconnections in an ultra-dense integrated circuit configuration. A chip interface mesa and chip assembly (10) includes a mesa member (12) which has a top planar mesa surface (14) and side walls (16). The perimeter of mesa (12) has a plurality of notches (18) which are each coated with a conductive layer. The notches (18) are electrically coupled to a mesa interface conductive terminals (22) via conductive pathways (20). A semiconductor chip (24) having a top surface (25) bearing active circuitry may be bonded to the bottom of mesa member (12) with an epoxy adhesive. Each notch (18) is aligned with a corresponding conductive interface pad (28) on the top surface (25) of the chip (24). Droplets of solder (26) are placed upon the chip interface pads (28) and are mechanically and electrically coupled to mesa (12) through a conductive layer on each notch (18). The present invention totally eliminates undesirable and wasteful looped wirebonds and provides substantial increases in volume available for active circuitry per planar die area.

Description: CHIP INTERFACE MESA BACKGROUND OF THE INVENTION 1. Cross Reference to Related Patent Applications. The present patent application is related to a pending patent application entitled "Inverted Chip Carrier", also invented by Nils E. Patra and assigned to the Hughes Aircraft Company. Field of the Invention. The present invention pertains to Ultra—Dense, Extremely Large Scale Integration and wafer scale synthesis of microelectronic components residing on a large number of integrated circuits. The specific focus of the preferred embodiment is the planar and orthogonal space optimization of active Microelectronic circuit elements which Makes possible Multi-chip VHSZC hybrids having extraordinarily high signal processing capabilities and enormous memory capacity. 3. Background Information. Over the past four decades, the electronics industry has witnessed vast improvements in the perfoTMance of electronic components. The transition froM thermo-ionic devices to solid state diodes and transistors was the first phase of intense efforts to miniaturize circuitry in order to construct powerful digital computers. The second great phase of innovation involved the consolidation of discrete solid state devices into a compact, unitary circuit which shared a single housing. Before the advent of integrated circuits, components like transistors were individually encapsulated in plastic cases or resided separately in metal cans. These single elements were generally Mounted on circuit boards and each had a number of leads connected together by soldered wires. The first generation of integrated circuits combined many discrete active elements together on several alternating layers of metallic and dielectric films which were deposited on an insulating substrate. These early integrated circuits, called thin-film hybrids, were the precursors of current integrated circuits which contain a solitary, but extremely powerful and densely packed, semiconductor chip or die. This semiconductor chip comprises a base or substrate of material, upon which many thin layers are formed that are, in turn, coupled together by tiny, metallic interconnects or vias which pass vertically through the several horizontal layers. A semiconductive material such as silicon, germanium, or gallium arsenide can be chemically altered in order to form carefully selected, minute regions having different electrical properties. These distinct regions are now fabricated with great precision, and each region may measure less than one millionth of an inch. A few regions which exhibit different degrees of electrical conductivity can be grouped together in order to form a device that can help perform a mathematical calculation or store information. These groups of microscopically small regions or zones within one of the many layers of one monolithic chip are the modern analogs to the discretely packaged components which preceded them twenty and thirty years ago. As each phase of electronic components produced improvements in calculation speed and memory capacity, the packaging of these components became more and more important. Technological advancements that solve problems concerning the fabrication or further miniaturization of semiconductor materials and devices simultaneously create a concomitant packaging problem. As circuit components shrink to increasingly smaller dimensions, the problem of accessing each component grows worse. When integrated circuits become so densely packed that a million of separate active devices occupy a space smaller than the diameter of the eraser on a common pencil, the difficulties involved in exchanging information in the form of electrical signals between that vast network of tiny circuit elements and the outside world become enormous. Another level of complication is reached when designers attempt to connect many integrated circuits together in a unitary system. Semiconductor chips which are shorter than the width of the eraser at the end of the pencil and less than two one hundreths of and inch thich are manufacturer simultaneously by the hundreds on thin circular wafers of semiconducti e material that are typically about four inches wide. Recent attempts to couple all the separate chips on the wafer gave rise to the term wafer scale integration. An electronic device which could incorporate tens, hundreds, or perhaps even thousands or millions of already immensely powerful separate chips, each comprising roughly a million active components, together on one wafer would constitute a tremendous technological leap forward in the electronics arts. Among the most serious problems encountered in designing and manufacturing integrated circuits and multiple integrated circuit arrays are the deleterious consequences of using fine filaments of wire to connect the miniscule terminals or pads which are the access ( o points to the outside world from the internal circuitry of the integrated circuit. These fragile, very light gauge connecting wires are typically one oπe-thousanth of an inch in diameter. One common technique for attaching these wires or leads to the conductive external terminals of the chip is thermocompression bonding. This process combines the application of heat and stress on an integrated circuit die. A very small wedge—shaped probe or tool called a bonding wedge must be viewed through a microscope and guided over a w re which is to bonded onto a conductive pad. The pad is usually located at the periphery of the semiconductor chip or die, which is placed on a heating device in order to soften the metallic material comprising the pad. A refinement of the bonding wedge is called a nailhead or ball bonder, in which the pressure bonding tool consists of a glass capillary tube that feeds the wire through its center to the pad. A flame melts the end of the wire that protrudes out of the open end of the capillary tube and forms a ball having a diameter about twice the thickness of the wire. The wire is then retracted in the tube and the ball is held snugly against the orifice while the tube is moved over the pad and impressed upon it with considerable force. The compression deforms the ball into a flattened thermoco pression bond shaped like the head of a nail. The tube is then pulled back from the pad, and the flame is employed again to melt the wire which is now attached to a pad on the die. The wires and the contact pads are typically made of gold or aluminum. Although thermocompression bonding has proven useful over many years of manuf cturing, this method suffers from many shortcomings. Aside from the great expense incurred in either bonding wires and pads manually or with the aid of costly automated equipment, any mechanical connection like a pressure bond is susceptible to failure caused by a multitude of environmental factors. Since any fabrication process will be less than perfect, some wirebonds will be faulty after manufacturing. Even if only one percent of the connections are inadequate, the entire electronic system which includes the chip with the bad connection may be rendered completely inoperative as a consequence. Different rates of expansion and contraction of the connected materials due to changes in temperature will tend to destroy bonds over time. The ambient environment may contain compounds which will initiate chemical processes such as oxidation that may corrode and destroy metallic connections. The installation of subcomponents, handling, or vibration encountered during use may detach these wire bridges in time. In addition to the nettlesome problems of keeping a wire bond intact over the life of an electronic device, this mode of connecting portions of one chip or an array of many chips is beset by problems even if all the bonds are perfectly made and are never broken. The vast number of wire bonds needed to connect large numbers of chips result in an enormous total length of conductive pathways in the system circuit. These conductors consume electrical power since they are resistive components. Increased ambient temperature caused by this thermal heating may impair the operation of the associated integrated circuits. The wires inject unwanted inductance and capacitance into otherwise precisely balanced circuits. Crosstalk between conductors may severely impair the performance of the entire system. Time delays inherent in the long pathways reduce computation capability. Perhaps the worst problem is the enormous space which is wasted when wires are used to connect together portions of a chip or an array of many chips. Each span of wire that connects two points which reside substantially in the same plane requires a looped, generally parabolic length of bent wire. The amount by which the wire can be bent is limited by the fragility and susceptibility of the wire to fracture. In addition, the size of the wire bonding tool mandates a minimum spacing between contact points which- receive thermocompression bonds. These loops of wire impose limits on the horizontal density of the chip deployment, since a minimum space for each loop must be provided between each adjacent chip. Conventional wire bonding techniques impose die interspacing contraints of no less than twice the thickness of the die. If the die is on the order of twenty mils of an inch in height, as much as fifty mils will be wasted in order to provide adequate separation for the making the wire bonds. The pads which receive the wire bonds also consume precious space on the die. Each pad must be large and sturdy enough to tolerate the great pressure transmitted by the wire bond tool. The wire bonds not only consume valuable horizontal surface area on the face of the die, but also take up space above the plane of the die. The looped portions of the connecting wires can extend far above the die face and preclude the stacking of several levels of chip array planes. When connecting wires consume space above or below the active die surface, the vertical or orthogonal space that extends perpendicular to the active circuitry must be reserved for protruding wires. These exposed wires are vulnerable to a host of environmental hazards including physical shock, vibration, extremes of temperature and damage during the assembly process. Previous microcircuit connection and wafer scale integration inventions have attempted to solve the I I deployment and packaging problems inherent in combining and connecting millions of active circuit components using a variety of approaches. In United States Patent Number 2,050,681, Horton discloses a subminiature structure for electrical apparatus which includes a combination of a plurality αf wafers made of rigid insulating material, conductors fixed to each wafer, and connections between the electrical components on these wafers. Vizzer describes a modular component printed circuit connector in United States Patent Number 3,107,319. This invention uses a modular component base block which is attached to printed circuit boards having end slots for the insertion αf circuit connector elements that are retained by spring loaded terminals. A flat package for sem conductors which includes an insulating ceramic substrate having a channel that « receives a semiconductor wafer that is bonded to a gold tt surface is disclosed in United States Patent Number 3,271,507— Elliott. In United States Patent Number 4,288,841, Gogal describes a semiconductor device including a double cavity chip carrier which comprises a multi—layer ceramic sandwich structure that has a pair of chip cavities. The inventor claims that this structure is useful for connecting two integrated circuits which have different terminal patterns. Minetti reveals a method of forming circuit packages using solid solder to bond a substrate and contact members in United States Patent Number 4,332,341. Minetti's ceramic chip carrier includes a ceramic body with castellations formed at the edges of the carrier surfaces. Multi—layer contact members are coupled to contact pads which are, in turn, connected to leads from an integrated circuit chip. ι3 Hall et al. explain a method of fabricating circuit packages which employ macro—components mounted on supporting substrates in United States Patent Number 4,352,449. In order to maintain sufficient clearance between components and the substrate and to achieve high reliability bonds, Hall employs massive solder preforms which are applied to contact pads on either the components or the substrate. This invention also involves the bonding of lead-tin solder spheres having a diameter of twenty to forty mils to contact pads on a chip carrier. In United States Patent Number 3,811,186, Larnerd et al. describe a method for aligning and supporting micro ircuit devices on substrate conductors when the conductors are attached to the substrate. A shaped, flexible, insulative material placed between the devices and their corresponding conductors supports terminals which can be fused together with heat in order to attach conductors after they have been properly aligned. Beavitt et al. disclose an integrated circuit package including a number of conductors bonded between a cover and a cavity formed within a base that holds a chip in United States Patent Number 3,825,801. This cavity serves as a carrier for the chip, which is held in place between conductive strips of resilient material that are secured between a base and cover of insulating material. A process for producing sets of small ceramic devices such as lea less inverted chip carriers that have solderable external connections is disclosed by Hargis in United States Patent Number 3,864,810. After firing several layers of ceramic material on a base sheet, Hargis mounts a chip on the ceramic carrier by embedding or encapsulating it in an epoxy resin in order to provide leads for the chip which are more easily connected to external devices than the chip terminals themselves. \ 5 In United States Patent Number 3,868,724, Perrino reveals connecting structures for integrated circuit chips which are fabricated by forming many sets of leads on a flexible tape. These leads penetrate through holes formed in the tape and terminate in contacts which are arranged in a pattern that corresponds to a pattern of contacts on an integrated circuit chip. The chips are enclosed by an epoxy encapsulant after they are bonded to the contacts. Hartleroad et al. explain a method and apparatus for positioning semiconductor flip chips onto one end of a transfer probe which automatically and magnetically aligns the chips and bonds them to an overlying lead frame structure. Their method for placing flip chips into one end αf an elongated, groove αf a positioning apparatus and conveying them on guide rails using a magnetic force to properly locate the chips before bonding is the subject of United States Patent Number 3,937,386. i t An electrical package for Large Scale Integrated devices which utilizes solder technology to interconnect a carrier, a circuit transposer and LSI devices is described by Honn et al. in United States Patent 4,074,342. The Honn electrical package includes a carrier which has a thermal expansion coefficient similar to semiconductive material, a standard array of terminal pins, and the transposer, which they claim eliminates mechanical stress on solder joints that is caused by dissimilar thermal expansion of the various packaging materials. Inoue discloses a semi onductor device insulation method in United States Patent Number 4,143,456. This invention employs a protective covering for a semiconductor device which includes a circuit board bearing a conductive pattern and a chip. Inoue fixes his chip with a eutectic or electrically connected adhesive to a die bonded portion of the circuit board pattern with aluminum wire. 1 7 United States Patent Number 4,147,889— Andrews et al. describe a thin, dielectric, dish-shaped chip carrier which has flexible mounting flanges having plated or bonded solderable conductive traces and paths. These traces and paths are coupled with plated or bonded heat sinks which are electrically grounded and provide structural integrity. A flat package for an integrated circuit device that has output pads comprising a supporting member for the integrated circuit device, external output terminals, and array of output conductors, and an electrically insulating encapsulation cover is illustrated in Ugon's United States Patent Number 4,264,917. This invention includes contact islands arranged on a supporting wafer to provide a package for one or more integrated circuit devices having a reduced thickness and surface area. None of the inventions described above solves the problem of wasted planar and orthogonal space that ι3 results from the high portion of chip assemblies that are devoted to chip interconnections such as wirebonds. None of these prior methods or apparatus provides an effective and comprehensive solution which addresses all of the complex aspects of achieving ultra-high density of active semiconductor components. Such a solution to this problem would satisfy a long felt need experience by the semiconductor and integrated circuit industries for over three decades. A truly practical and reliable means for producing efficacious intra-chip and chip-to-chip interconnections without squandering a substantial portion of the die's planar and orthogonal space would constitute a flia or advancement in the microelectroni s field. Manufacturers αf semiconductor dies could employ such an innovative design to produce integrated circuits capable of processing information at speeds greatly exceeding the current state of the art and and capable of storing vast quantities of data far beyond today's most densely packed designs. Such an invention would ideally be suited to operate in cooperation with rt a wide variety of computing systems and would perform consistently and reliably over a wide range of operating conditions and system applications. Extremely Large Scale Integration microcircuitry would also satisfy the rigorous demands of supercomputers and orbital defense systems. An invention which enables aerospace microelectronic designers to deploy enormously powerful yet extremely compact integrated circuits in orbit for space defense systems would most certainly constitute a major technological advancement in the electronics arts. 3.0 SUMMARY OF THE INVENTION The aim of the present invention is to help accomplish this major technological advancement. The Patraw Chip Interface Mesa enables designers of integrated circuits to connect the integrated circuits together in order to form unitary, on—wafer chip arrays which have signal processing and memory capacities that dwarf previous previous discretely connected, multiple integrated circuit systems. The present invention extends the current state of the art beyond Very Large Scale Integration (VLSI) capabilities to the higher range of Ultra—Dense, Extremely Large Scale Integration (ELSI) using the wafer scale synthesis techniques described and claimed below. The chip interface mesa is fabricated from an dielectric material and has a generally rectangular shape having dimensions that are generally slightly smaller than the semiconductor die upon which it resides. The mesa has a rectangular cross-section and may be epoxied to the tap of the die which bears the uppermost level of active circuitry. The perimeter of the mesa is populated by vertical channels or notches which are coated with a layer of conductive material. The top face of the mesa contains an array of conductive regions or external interface pads which are much larger than conventional bond pads. These external interface pads are electrically coupled to a notch on the side wall of the mesa by a thin conductive pathway. Each notch in the mesa is aligned with a conductive chip interface pad on the semiconductor chip. The chip interface pads are deployed on the periphery of the top surface of the chip which is bonded to the mesa. A drop of heated solder or other easily deformable conductive material is placed in each notch from above the mesa and forms an electrical link between the mesa and a chip interface pad, since the solder joins with both the pad and the vertical walls of the notch. 2.Z This microelectronic packaging configuration constitutes an important improvement and refinement of the Patraw Inverted Chip Carrier, which substantially eliminates long looped wirebonds by redirecting iπtra—chip and chip—to-chip interconnections to orthogonal space over the active circuitry of the chip. The present invention eliminates wirebonds completely. All undesirable wire couplers are supplanted by durable and easily formed solder droplet connections inside a notch which is in registry with a corresponding chip pad. The repositioning of intra-chip and chip-to-chip interconnections into space over the active circuitry optimizes packaging space for integrated circuit assemblies and enables designers to approach the theoretical density limit for semiconductor devices due to the enormous saving of space which was once wasted by wirebonds between adjacent chips. The present invention reserves nearly all of the planar space of a multi—chip array for active semiconductor circuitry, and banishes inefficient interconnection space to a volume over or orthogonal to the plane of the active circuitry. This important new integrated circuit assembly design not only optimizes packaging criteria, but also permits the stacking of many parallel levels of contiguous chips with a minimum of costly inter—chip spacing. By connecting many chips together, many semiconductor dies on a wafer can be combined in order to realize full, wafer—scale reconstruction. It is, therefore, an object of the present invention to provide an apparatus for microelectronic interconnection which completely eliminates undesirable and unreliable wirebonds. Another object of the present invention is to provide apparatus for micro—miniature electronic interconnection which maximizes the density of active, integrated circuit devices in a given volume. 2.H Another object of this invention is to provide a simple and reliable means of connecting circuits within a chip or connecting circuits within many different chips in order to make previously impossible wafer—scale synthesis designs practical and cost—effective. Still another object of the present invention is to provide a means of connecting large numbers of semiconductor dies using currently commercially available dies and existing packaging technology. Yet another object of the invention is to provide chip arrays having increased system speeds due to drastic reductions in propagation delay times which results from the total elimination of interconnecting wires. It is also an object αf this invention to provide a chip carrier which enables designers to take advantage of enormous reductions in power consumption, since the elimination of a multitude of long wirebonds dispenses with a primary source of wasteful, capacitive loading. Another object of the present invention is to provide a method of installing many chips together on a chip carri er which may be easily tested, inspected, burned—in, and repaired. Still another object of this invention is to provide a chip deployment scheme which minimizes chip—to—chip input/output requirements. It is a further object of this invention to provide a technique for coupling integrated circuits that inherently protects interconnections from physical damage by placing solder droplets in sheltered notches in the sidewalls αf a chip interface mesa. 2fc Yet another object of the invention claimed below is to provide apparatus for microelectronic interconnection which avoids the deleterious additional capacitance and inductance that are introduced by prior devices which incorporate many long wire connectors within integrated circuit assemblies. It is also an object of the present invention to cut down the mass of integrated circuit systems in order to fabricate systems which can be economically placed in an orbital environment. An appreciation of other aims and objects αf the present invention and a more complete and comprehensive understanding of the this invention may be achieved by studying the following description of a preferred embodiment and by referring to the accompanying drawings. 3.1 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a side elevational perspective view of the present invention showing a mesa atop a semiconductor die. The mesa has conductive mesa interface pads on its top face and has notches cut in its sidewalls that are aligned with chip interface pads on the boundaries αf the top surface of the chip. FIG. 2 is a cross-sectional view of the present invention that illustrates solder droplets connecting the coated conductive walls of the mesa notches with chip interface pads. FIG. 3 is a tap view of the present invention depicting an array of oversized mesa interface pads *8 which are each connected to a notch in a sidewall of the mesa by conductive pathways. J9 DESCRIPTION OF A PREFERRED EMBODIMENT FIG. 1 depicts a chip interface mesa and chip assembly 10 in a perspective view. Mesa 12 is made from undoped silicon and has a top surface 14 and sidewalls 16. The mesa 12 has first and second planar axes that are respectively parallel to the length and width dimensions of the mesa. The transverse axis of the mesa runs perpendicular to the two planar axes and spans the height of the mesa. The sidewalls 16 contain notches 18 which are vertical channels that have been abrasively ground, chemically etched, or laser drilled into mesa 12. In the preferred embodiment, these vertical conductor means, which implement chip interconnections in space which is orthogonal to rather than coplanar with the active circuitry of the chip, are V—shaped grooves extending transversely across the narrowest dimension of the mesa 12. The faces of the notches 18 are coated with a layer of conductive material such as copper. The best mode of the present invention employs vapor deposition techniques that are well known in the art to coat the notches 18. The top of the mesa 12 contains an array of conductive mesa interface pads 22 that are joined to the conductive coating of the notches 18 by conductive pathways 20. These pads are oversized compared to size of conventional wirebond pads in order to provide a convenient means of external connection to the mesa—chip assembly 10. FIG. 2 reveals a semiconductor die or chip 24 after it has been brought into alignment two to four mils below mesa 12. The chip 24 and mesa 12 are aligned so that the two planar axes of each, which extend parallel to the length and width dimensions of both the mesa and chip, are substantially parallel. Each notch 18 is substantially centered over a chip interface pad 28 which is, in turn, connected to the active circuitry 25 on the semiconductor substrate via conductive pathways 27 that is hidden from view by the mesa 12. Conventional epoxies may be used to permanently attach mesa 12 to chip 24. Both the mechanical support and electrical couplings between chip 24 and mesa 12 are provided by solder drops 26. Conventional heated lead—tin solder is wicked into the notches 18 by dipping mesa 12 in molten solder after the faces of the notches 18 have been treated with CrCuAu or CuAu in order to make them solder—wettable. The chip interface pads 28 are also pretreated with wetting material. The soldering process is performed in a heated nitrogen atmosphere in order to achieve the tea—drop shape shown in FIG. 2. The notches 18 may be shaped in any con iguration which will receive a mass or drop 28 of conductive material which will electrically couple the mesa 12 to chip 24 through pads 28. Automated fabrication processes can be employed to form hundreds or thousands of these solder drop connections simultaneously. Any alloy or conductive substance which can form the electrical coupling between conductive surfaces of the notches 18 and the chip interface pads 28 may be utilized without departing from the essence of the present invention. 3Z FIG. 3 illustrates a complete mesa—chip assembly 10 in a top view. This drawing shows a typical arrangement for an actual 188 mil by 220 mil random access memory chip. The contact pads 22 are twenty to twenty—five mils square. These pads are enormous compared to conventional four mil square chip pads encountered in prior designs. The increased surface area provided by the present invention makes it easier to connect a chip to external devices and also greatly enhances the testability of the chip and inspectability of the input and output pad connections. The ductility of the solder joints also inherently compensates for mechanical stress resulting from thermal dissimilarities that are caused by varying amounts of heat which are generated during operation of the electrical components on the chip. Another great advantage of this design is that the solder droplets 26 are also completely visible, in comparison to previous "flipped-chip" packaging designs. In an alternative embodiment of the invention, the notches 18 need not be disposed perpendicular to the top planar mesa surface 14. The notches may be sloped, curved upward, or generally formed in any useful configuration, so long as they provide adequate mechanical support and electrical coupling for the mesa 12. Another great advantage of the solder droplets 26 is that complex and expensive internal interconnections within chip carriers, such as those employed in the Patraw Inverted Chip Carrier, are completely avoided in the Patraw Chip Interface Mesa. The Patraw Inverted Chip Carrier, which is described in detail in a related copending patent application, enables a designer ordinarily skilled in the art to take a current, commercially available chip, place that chip in this new carrier, and realize an enormous increase in volume available for active circuitry of 65JJ for only a tiny ZV. increase in planar area compared to the bare die dimensions. The Patraw Chip Interface Mesa provides even greater volume to surface area ratios by completely eliminating all wirebonds. Nearly all the inter—chip spacing required in conventional manufacturing techniques is avoided by employing solder droplets in mesa receptacles that extend perpendicular to the plane of the chip's active circuitry to form the electrical interconnections between the chip and the outside world. Although the present invention has been described in detail with reference to a particular preferred embodiment, persons possessing ordinary skill in the art to which this invention pertains will appreciate that various modifications and enhancements may be made without departing from the spirit and scope of the invention.

Claims: CLAIMS What is claimed is: 1. Apparatus for M croelectronic interconnection comprising: a mesa Member made from a dielectric material having: a first planar axis extending parallel to the longest planar dimension of said mesa member, a second planar axis extending parallel to au the second longest planar dimension of said mesa member, a transverse axis extending perpendicular to both said first and second planar axes, a top planar Mesa surface extending substanti lly perpendi ular to said transverse axis and bounded by said longest and said shortest planar dimensions of said mesa Member, a plurality of planar perimeter walls disposed generally parallel to said transverse axis, a plurality of vertical electrical coupler means located substantially near said planar perimeter walls, said plurality of vertical electrical coupler means each having a vertical dimension which is substantially parallel to said transverse axis of said mesa member, said plurality of vertical electrical coupler means each further having a conductive coating extending along said vertical dimension of said coupler means, a plurality of Mesa interface conductive terminals disposed upon said top planar mesa surface, said plurality of mesa interface conductive terminals disposed upon said top planar mesa surface being electrically coupled to a plurality of conductive pathways which mr Mechanically coupled to said top planar Mesa surface, said plurality of conductive pathways being further selectively and electrically coupled to said vertical electrical coupler means, 2>3 a semi onductor chip having two planar dimensions corresponding to said chip's two longest dimensions of length and wi th; said semiconductor chip further having a top chip surface bounded by said two planar dimensions which contains an uppermost layer of active circuitry ? said chip further having a plurality of chip interface means deployed upon said top chip surface and generally surrounding said uppermost layer of active circuitry; said plurality of chip interface means also being selectively connected to said active circuitry and disposed generally at the periphery of said top chip surface; lid semiconductor chip being mechanically coupled to said mesa member so that said top chip surface is substantially adjacent to said mesa member; and 3* said plurality of chip interface means also be ng iβlactively and electrically coupled to said vertical ilMetrical coupler Means by a plurality of mesa-chip electrical contact Means. 2. Apparatus as claimed in Claim 1 in which said mesa member is made from undoped sil con. 3. Apparatus as claimed in Claim 1 in which said vertical electrical coupler means arm V-shaped notches cut in said planar perimeter walls of said mesa member and arm also pretinned with solder and precoated with a solder-wetting agent. 4. Apparatus as claimed in Claim 1 in which said mesa interface conductive terminals are metallized pads which have been placed on said top planar mesa surface by a chemical vapor deposition process. 5. Apparatus as claimed in Claim 1 in which said conductive pathways are metallized strips which have been placed on said top planar Mesa surface by a chemical vapor deposition process. 6. Apparatus as claimed in Claim 1 in which said chip interface Means are conductive bond pads. 7. Apparatus as claimed in Claim 1 in which each of said vertical electrical coupler means arm each electrically coupled to only one mesa—chip electrical contact means. 8. Apparatus as claimed in Claim 1 in which each of said vertical electrical coupler means is substantially aligned in registry with only one of said chip interface means. V 9. Apparatus as claiMβd in Claim 1 in which said mesa-chip electrical contact Means are drops of solder placed in electrical coMMunication with said chip interface Means and with said vertical electrical coupler Means. 10. Apparatus as claimed in Claim 1 in which said Mesa eeeber end said chip are mechanically coupled by a layer of epoxy adhesive. 11. Apparatus as claimed in Claim 1 in which said mesa member has said first and second planar dimensions which arm slightly smaller than said two planar dimensions of said chip.

Inventors: PATRAW NILS E, PATRAW, NILS, E.
Applicants: HUGHES AIRCRAFT CO, HUGHES AIRCRAFT COMPANY
Application year: 1986
Main classification: H01L23
IPC codes: H01L21, H01L23