SEMICONDUCTOR DEVICE HAVING A CONTACT AREA

Abstract: A semiconductor device has a semiconductor substrate (11), a first insulating layer (12) formed on the substrate (11), a conductive body (13 and 14) formed on the first insulating layer (12), a second insulating layer (15) formed on the first insulating layer (12) and the conductive body (13 and 14) and having a contact hole formed at a contact area to reach the conductive body (13 and 14), and a first conductive layer (16) formed on the second insulating layer (15) and the conductive body (13 and 14). The conductive body has a conductive member (13) formed on the first insulating layer (12) in the contact area, and a second conductive layer (14) formed on the first insulating layer (12) and the conductive member (13).

Description: The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a contact area for connecting upper and lower conductive layers and a method of connecting these. Fig. 1 shows a conventional semiconductor device having a contact area for connecting upper and lower conductive layers. This semiconductor device has semiconductor substrate 1, insulating layer 2 formed on substrate 1 and having a thickness of, e.g., 4,000 Å (= 0.4 µm), lower conductive layer 3 formed on insulating layer 2 and having a thickness of, e.g., 3,000 to 4,000 Å=(0.3-0.4 µm), thick insulating layer 4 formed on layers 2 and 3 to expose part of layer 3 and having a thickness of, e.g., 7,000 Å=(0.7 µm), and upper conductive layer 5 formed on layer 4 and the exposed portion of lower conductive lay­ er 3. The contact portion of lower and upper conductive layers 3 and 5 constitutes contact area 6. Layers 2 and 4 are made of the same insulating material such as SiO₂. Conventionally, when part of layer 3 is exposed, i.e., when a contact hole is formed in layer 4, an anisotropic etching method, e.g., a reactive ion etching method (RIE), is used to partially etch layer 4, so that the integrated circuit can be micropatterned. Along with the micronization of the integrated circuit pattern, the width and thickness of layer 3 must be reduced. Furthermore, in a static RAM, a polycrystal­ line silicon layer for forming lower conductive layer 3 must be selectively made very thin in order to make the selected part highly resistive and form a high­ resistance element of the polycrystalline silicon layer as the load element of each memory cell. In this manner, as the integrated circuit is micropatterned and highly integrated, the thickness of layer 3 tends to be further reduced. This is also applied to an active element formed in part of the polycrystalline silicon layer. When a contact hole is formed in layer 4 by the RIE method, the ratio of the etching rate of layer 4 to the etching rate of layer 3 (etching selectivity) is not very large, but usually less than 10. Accordingly, when lower conductive layer 3A having a very small thickness of, e.g., 500 Å (0.05 µm),is formed, if part of insulating layer 4 is etched at a small etching selectivity and an etching time 1.5 times a normal etching time in consid­ eration of an allowable error or processing margin, not only the part of layer 4 but also the corresponding portion of layer 3A is etched. In addition, part of insulating layer 2 is etched to partially expose substrate 1. In this state, when upper conductive layer 5A is formed, it is in direct contact with the exposed portion of substrate 1. EP-A-0 00 21 85 discloses a method of producing a connection between two wiring layers which cross at right angles. A first metal wiring is formed on an insulating layer above a semiconductor substrate. An etch stop layer is then formed on the top of the wiring which is typically chromium. An insulation layer is applied over the surface. Both wiring layer and etch stop layer are narrower than a contact hole subsequently formed in the insulation layer. To prevent overetching on the sides of the wiring layer and etch stop layer it is recommended to use an etchant for patterning the second wiring layer which does not significantly etch the insulating layer. In this way, contact with the substrate can be prevented. It is an object of the present invention to provide a semiconductor device wherein upper and lower conductive layers are formed in a contact area to sufficiently contact with each other without contacting a substrate The above object is achieved by a semiconductor device having a semiconductor substrate; a first insulating layer formed on said substrate; conductive means formed on said first insulating layer and including a first conductive layer; a second insulating layer formed on said first insulating layer and said conductive means and having a contact hole formed at a contact area to reach said conductive means; and a second conductive layer formed on said second insulating layer and said conductive means characterized in that said conductive means also includes a conductive member formed on said first insulating layer in said contact area and that said first conductive layer is formed on said first insulating layer and said conductive member, said conductive member being wider than said contact hole. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a sectional view of a conventional semiconductor device wherein upper and lower conductive layers are connected at the contact area; Fig. 2 shows a sectional view of a semiconductor device wherein, when the lower conductive layer in the device shown in Fig. 1 is made thin, a defect occurs in the contact area; and Fig. 3 shows a sectional view of a semiconductor device according to an embodiment of the present invention. Fig. 3 shows a semiconductor device according to an embodiment of the present invention. This device is formed in accordance with the following manufacturing steps. First, SiO₂ insulating layer 12 having a thickness of 4,000 Å (0.4 µm) is formed on semiconductor substrate 11. Polycrystalline silicon conductive layer 13 having a thickness of 1,000 Å (0.1 µm) is formed on a local area of layer 12. Subsequently, a polycrystalline silicon conductive layer having a thickness of 500 Å (0.05 µm) is formed on layers 12 and 13 and is selec­ tively etched to form thin conductive layer 14 on a predetermined region of layer 12 and on layer 13. SiO₂ insulating layer 15 having a thickness of 7,000 Å (0.7 µm) is formed on layers 12 and 14. Part of layer 15 is then selectively etched by, e.g., the RIE method, in order to form a contact hole and thus expose part of layer 13 or 14. Etching is performed so that the bottom of the contact hole reaches the upper surface region of layer 13. In this case, the ratio of the etching rate of layer 15 to the etching rate of layers 13 and 14, i.e., the etching selectively is as small as about 5, and the etching time is set, taking the processing margin into consideration, to be 1.5 times the standard etching time usually required for etching layer 15 to form a contact hole. Since the total thickness of layers 13 and 14 is as large as about 1,500 Å (0.15 µm), layers 13 and 14 are not completely etched in the direction of thickness upon etching. In etching, for example, only selected part of layer 14 is etched in the direction of thickness to expose the upper surface of layer 13, and layer 12 is not etched. Therefore, the contact hole is not formed to extend through layers 13, 14 and 12. After etching, Al wiring layer 16 is formed on layer 15 and the exposed portion of layer 13, thus completing the semiconductor device shown in Fig. 3. As shown in Fig. 3, even when part of layer 13 is exposed during etching, layer 16 sufficiently contacts the upper surface of layer 13 which is in reliable electrical contact with layer 14, and also directly contacts the side wall of layer 14. Therefore, layer 16 is formed in electrically good contact with layer 14. The thickness of layer 13 can be set in advance to an appropriate value by calculation in accordance with the thickness of layers 14 and 15, the etching selectivity and processing margin. In the embodiment, layer 14 is formed of polycrystalline silicon. However, layer 14 can be formed of a refractory metal such as W or Mo; a silicide such as MoSi; a double layered polycide such as polisilicon/MoSi2; single crystalline silicon crystal­ lized by layer annealing technique, or amorphous silicon. Polycrystalline silicon is used to form layer 13 in the embodiment. However, layer 13 can be preferrably formed of any material described above which can be made in good ohmic contact with layer 14. Further, layer 16 can be formed of not only Aℓ, but also any material described above which can be made in good ohmic contact with layer 13. In a case where at least two of layers 13, 14 and 16 are formed of silicon, it is desirable that impuri­ ties of the same type are doped in the silicon layers. As described above, according to the present inven­ tion, layer 13 having an appropriately selected thick­ ness is formed under layer 14 at the contact area. Therefore, even if layer 14 is thin, layer 12 is not etched during etching, and thus layer 16 is not short-­ circuited with substrate 11, thereby improving the manufacturing yield and reliability. Although an embodiment of the present invention has been described above, the present invention is not limited to this. For example, conductive layer 14 can be formed to cover the upper surface and all sidesurfaces of conductive layer 13 in the contact area.

Claims: 1. A semiconductor device having a semiconductor substrate (11); a first insulating layer (12) formed on said substrate (11); conductive means (13, 14) formed on said first insulating layer (12) and including a first conductive layer (14); a second insulating layer (15) formed on said first insulating layer (12) and said conductive means (13, 14) and having a contact hole formed at a contact area to reach said conductive means (13, 14); and a second conductive layer (16) formed on said second insulating layer (15) and said conductive means (13, 14) characterized in that said conductive means (13, 14) also includes a conductive member (13) formed on said first insulating layer (12) in said contact area and that said first conductive layer (14) is formed on said first insulating layer (12) and said conductive member (13), said conductive member (13) being wider than said contact hole. 2. A device according to claim 1, characterized in that each of said conductive member (13), first and second conductive layers (14) and (16) includes a material selected from the group consisting of silicon, polycrystalline silicon, amorphous silicon, single crystalline silicon, tungsten, molybdenum, molydenum silicide and a double layer structure of polysilicon/MoSi₂. 3. A device according to claim 2, characterized in that said conductive member (13) includes a material which can be made in good ohmic contact with said first and second conductive layers (14) and (16). 4. A device according to claim 2, characterized in that said first conductive layer (14) includes a material which can be made in good ohmic contact with said second conductive layer (16). 5. A device according to claim 1, characterized in that at least two of said conductive member (13) and first and second conductive layers (14) and (16) are formed of silicon layers having the same type of impurities doped therein. 6. Method of producing a connection between upper and lower conductive layers separated by an insulating layer in a semiconductor device, comprising: forming a first insulating layer (12) on a semiconductor substrate (11); forming a conductive member (13) at discrete positions on said first insulating layer (12); forming a first conductive layer (14) on said first insulating layer (12) and said conductive member (13); forming a second insulating layer (15) on said first insulating layer (12), said first conductive layer (14) and said conductive member (13); forming a contact hole through said second insulating layer (15) to reach said conductive member (13) and said first conductive layer (14), said contact hole being narrower than said conductive member (13); and forming a second conductive layer (16) on said second insulating layer (15), said first conductive layer (14) and said conductive member (13).

Inventors: MOMOSE, HIROSHI C/O PATENT DIVISION, NOZAWA, HIROSHI C/O PATENT DIVISION, SHIBATA, HIDEKI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L23
IPC codes: H01L21, H01L23