DEGLITCHING NETWORK FOR DIGITAL LOGIC CIRCUITS

Abstract: A deglitching network for digital logic circuits includes a voltage actuated current source coupled to a linear track­ ing, constant voltage column clamp circuit. The deglitching network threshold level tracks closely with the predeter­ mined voltage of the column clamp, which also acts as a current sink. When heavy current loads are switched from the column clamp and its voltage falls briefly, the deglitching network is actuated to inject current into the column clamp circuit and restore the preset voltage.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to electronic circuits and particularly to a low level clamping circuit for stabilizing current flow through a circuit node connected to a high level voltage clamping network. The invention is particularly applicable to programmable logic arrays. Description of the Prior Art In a digital logic network such as a programmable logic array, a plurality of word lines are connected to a plurality of bit lines through logic gates. The product terms of the logic gates are delivered to the bit lines, which are connected by OR gates to sense amplifiers. Because all the output sense nodes are virtually independent of each other, significant variations in their output voltage levels may occur in ordinary operation. To eliminate unwanted swings in the levels of the bit lines, it is a common design practice to provide a linear tracking, constant voltage column clamp which is diode connected to all the bit lines. The column clamp establishes a generally constant high level voltage for the sense nodes, and prevents radical excursions of the sense node voltages. Therefore, the sense amplifiers are provided with a constant high level reference voltage basis for reducing the digital signal swings of the product terms. The state-of-the-art column clamp circuit, however, introduces into the logic array its own inherent deficiencies and limitations. For example, in a large programmable logic array, there may be 64 product terms, each presented at an individual sense node. The product terms are mutually independent so that any one or all of the bit lines may be on at a given time. When most or all of the bit lines are off, a large current load is sunk to ground through the column clamp. Conversely, actuation of many or all of the bit lines will shunt the current load to ground through the word lines, and the column clamp will experience a sudden load drop. This load drop, which is a function of the programming of the logic device, will cause the voltage of the sense nodes to drop briefly but precipitously. The column clamp circuit is intended to prevent such fluctuations, but in reality its response is undesirably slow in responding to large load shifts. During large load changes, the diode connections of the sense nodes to the column clamp act to defeat the intended purpose of the column clamp. That is, the 64 diodes each exert an intrinsic capacitance, and the aggregate of these capacitances creates a significant RC network connected to the reference node of the column clamp. The column clamp may require two or three nanoseconds to overcome the resulting RC rise time effect, which in a system having a 10 nanosecond access time, is, of course, quite significant. While the column clamp voltage is rising to return to its preset value, the sense node high level reference node voltage drop indicative of a logic level shift may fall below the noise margin of the sense amplifiers, causing the sense amplifiers to switch prematurely, or to read incorrect bit line conditions. This condition causes a glitch in which the system fails to operate. Document US-A-3,937,988 discloses a deglitching network for reducing fluctuations in the high or low level of a circuit node due to noise or the like.The network comprises a first branch consisting of series connected emitter-collector-paths of a npn-transistor and a pnp-transistor connected between a voltage source and ground. The transistors alternatingly clamp the node connected to the connected emitters respectively to a high or low potential. For this purpose, the circuit further comprises a bias branch connected in parallel to the emitter-collector-paths of the transistor pair and consisting of a first diode, a second diode and an impedance match resistor. The bases of the transistors are respectively connected to the cathodes of the first and second diodes. It is the object of the invention to provide a deglitching network to prevent voltage excursions in a column clamp network so as to minimize access time. Patent claim 1 defines the means which, according to the invention, are provided for this purpose. SUMMARY OF THE INVENTION The present invention provides a deglitching network for digital logic circuits to prevent voltage excursions in the column clamp network or similar circuits. In a preferred embodiment, the deglitching network comprises a voltage actuated current source coupled to a constant voltage column clamp circuit. The deglitching network threshold level tracks closely with the predetermined voltage of the reference node of the column clamp, which also acts as a current sink. When heavy current loads are switched from the column clamp and the voltage level of the high level reference node falls briefly, the deglitching network is actuated to inject current into the column clamp circuit and restore the preset voltage. The deglitching network includes a pair of transistors connected between V cc and the voltage reference node of the column clamp. One of the transistors is connected in a voltage divided feedback loop which establishes a reference voltage level slightly below the level set by the column clamp. When the column clamped node voltage falls, the other transistor is switched on to form a low impedance path to V cc and deliver a large amount of current to the clamped node. The voltage divider feedback loop is similar to that of the column clamp, so that both networks track closely over temperature variations. The typical column clamp is designed to act as a sink for large amounts of current, whereas the deglitching network of the present invention is adapted to provide a virtually instantaneous source of large amounts of current. The current injected by the deglitching network is sufficient to overcome the parasitic RC rise time effects in a programmable logic array or the like in which diodes connect the voltage reference node to a large plurality of bit lines. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic drawing of the deglitching network shown in exemplary use in a typical programmable logic array network; Figure 2 is a schematic representation of a prior art linear tracking clamp circuit with which the present invention may be employed; Figures 3a-3c are graphic representations of the load and output variations of the linear tracking clamp circuit of Figure 2, operated with and without the deglitching network of the present invention; and Figure 4 is a schematic drawing of the preferred embodiment of the deglitching network of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention generally comprises a deglitching network adapted to stabilize a high level voltage clamped reference node in a logic circuit or the like. In the description of the preferred embodiment the deglitching network will be described with reference to its use in a programmable logic array. Of course, the deglitching network may be employed in any voltage-clamped node arrangement in which the node undergoes large and sudden drops in current load conditions. With reference to Figure 1, a typical programmable logic array (PLA) includes a plurality of word lines 21a-21k, each connected to a respective word line driver 22a-22k. The array also includes a plurality of bit lines 23a-23n, each connected to the operating voltage V cc through a respective controlled voltage source 24a-24n. Each of the intersections of the word lines 21 and the bit lines 23 is connected by one or an array of transistors 26aa-26an, 26ka-26kn. The transistors 26 comprise functional logic gates connecting each bit line to all the word lines. Thus, the logic levels of the bit lines comprise the product terms of the word lines, as is known in the prior art. Each bit line 23 includes a bit sense node 27a-27n. One of a plurality of sense amplifiers 29a-29n is connected to all the sense nodes 27 through OR gates 28a-28n, respectively. To prevent large variations in the relative signal levels of the bit lines, and to establish a common high level reference voltage for the sense amplifiers 29, the sense nodes are clamped to a predetermined high level reference voltage. This is accomplished by connecting the bit lines 23a-23n through diodes 31a-31n, respectively, to a voltage reference node 32. Also connected to the node 32 is a linear tracking, constant voltage column clamp network 30. Figure 2 is a schematic diagram of a typical column clamp network 30 known in the prior art. A transistor 37 has its base connected through resistor 38 to V cc , and the collector is also connected to V cc . The emitter of transistor 37 is coupled through a resistor 39 to the collector of transistor 41. The base of transistor 41 is connected to a fixed bandgap reference voltage (e.g., 1.3v), and the emitter is connected through resistor 42 to ground. The bandgap reference voltage is translated through the base-emitter drop of transistor 41, establishing a current through resistor 42 to ground. This current is mirrored by the collector of transistor 41 to create a voltage across resistor 39. The voltage drop across resistor 39 is applied across the base-emitter junction of transistor 37, establishing a reference voltage at node 43. Node 43 is connected through diode 44 to the array reference node 32. Transistors 46 and 47 are connected between the collector of transistor 41 and node 32 and ground in a high level driver configuration to provide a current sinking path directly to ground. The voltage drop across diode 44 sets the clamp voltage level at node 32 at 2V be plus the voltage drop across resistor 39. It is desirable to maintain the clamp level constant, because any change in output may surpass the noise level margin of the bit sense nodes 27. A negative feedback loop comprising transistor 37, diode 44, and resistor 39 maintains the voltage level by reducing base drive to transistor 37 when the output falls below the predetermined value, and increasing the base drive at elevated voltages. The reference node 32 is also connected to all of the diodes 31a-31n. Each of these diodes has an intrinsic capacitance, and their sum comprises a substantial capacitance, represented schematically by capacitor 50 connected to the node 32. A large current drop, for example, as shown in Figure 3a, may occur at node 32 if an appropriate AC data pattern is fused into the array such that many or all of the product terms are sunk by a single word driver at the same time. At the instant the large load switches out, the high level clamp driver composed of transistors 46 and 47 will momentarily continue to draw a large collector load, although the word driver is now sinking this current. As a result, a negative voltage spike will occur at node 32. The duration of the negative voltage spike is determined by the RC rise time of the node 32, which in turn is established by the resistor 38 and the large parasitic capacitance 50. The resulting RC rise time is depicted in Figure 3b. A substantial portion of that rise time represents a period in which the sense amplifiers cannot acquire a single or low number of rising bit line signals, and thus limits the operating speed of the logic array. The deglitching network of the present invention, shown in Figures 1 and 4, reduces the magnitude and duration of the negative voltage spike to tolerable levels. The deglitching network is connected in parallel with the column clamp, and is designed to provide a transient current spike into reference node 32 when the voltage level of node 32 drops below a predetermined noise margin. As shown in Figures 1 and 4, a transistor 51 has its base connected through resistor 52 to V cc , and its collector also connected to V cc . The emitter of transistor 51 is coupled through a resistor 53 to the collector of transistor 54. The base of transistor 54 is connected to a fixed bandgap reference voltage (e.g., 1.3v), or similar voltage reference and the emitter is connected through resistor 55 to ground. The bandgap reference voltage is translated through the base-emitter drop of transistor 54, establishing a current through resistor 55 to ground. This current is mirrored by the collector of transistor 54, establishing a voltage across resistor 53. The voltage drop across resistor 53 is applied across the base-emitter junction of transistor 51, establishing a reference voltage at node 56 equal to 3V be plus the voltage drop across resistor 53. A feedback loop similar to the feedback loop described in the column clamp network varies the base drive to transistor 51 to maintain a constant voltage at node 56. The deglitching network also includes a transistor 59 having a collector connected directly to V cc , and the emitter connected directly to reference node 32. The base of transistor 59 is connected through capacitor 61 to ground, and also to node 56. Transistor 59, when actuated, forms a low impedance path directly from V cc to the reference node 32, so that a large amount of current may be delivered to the reference node 32 when that node voltage falls suddenly, as described above. Capacitor 61 is provided for added base drive should the transistor 59 be required to deliver an extraordinary amount of current without consuming DC power. The circuit configuration of the deglitching network is intentionally similar to that of the column clamp so both networks will track closely over the operating temperature range. The deglitching circuit, however, includes a transistor 57 having the collector connected to node 56 and the emitter coupled through diode 58 to ground. The base of transistor 57 is connected directly to the collector of transistor 55. In one embodiment, the component values are chosen so that the node 56 of the deglitching network is maintained, for example, 120mv lower than the voltage at node 43 of the column clamp network. In this configuration transistor 59 requires greater than 120mv forward bias to switch on and conduct. Therefore, in this example any negative excursion of node 32 with respect to node 56 exceeding -120mv will forward bias and actuate transistor 59 and initiate a low level clamping action approximately equal to the high level clamp voltage. Once the negative excursion falls below the exemplary 120mv level, transistor 59 is reverse biased to turn off, and no further low level clamping action will occur. The overall result, depicted in Figure 3c, is that the magnitude and rise time of the negative excursion is substantially reduced or even eliminated, and the access time of the logic array is likewise reduced. The deglitching network of the present invention has been described in use specifically to stabilize the bit sense nodes of a logic array in conjunction with a column voltage clamp network. The deglitching network may be viewed as a low level clamping network connected in parallel with a high level clamping network and adapted to correct the inherent tracking error of the high level clamping network under severe load shifting conditions. In one example, the high level voltage clamping network may be required to sink 40 milliamps at maximum load conditions, yet the load may drop to 400 microamps within an extremely brief period, in the nanosecond range. It is only in this circumstance that the deglitching network is actuated to inject current into the voltage reference node, and only until the high level driver transistors restabilize the voltage. The deglitching network may be applied to any voltage clamped node situation in which large load variations cause large voltage fluctuations of the clamped node.

Claims: A deglitching network for stabilizing the current through a circuit node (32), comprising: a first transistor (54) having a base connected to a reference voltage, an emitter coupled to ground and a collector connected to a first node, a second transistor (57) having a base connected to the first node, a collector connected to a second node (56), and an emitter coupled to ground through a diode (58), a third transistor (59) having a base connected to the second node (56), an emitter connected to the circuit node (32) and a collector connected to a potential source (V cc ), the second node (56) also being coupled to the potential source (V cc ) via a resistor (52), and a fourth transistor (51) having a collector connected to the potential source (V cc ), a base connected to the second node (56) and an emitter coupled to the first node. The network of claim 1 comprising further a capacitor (61) connected between the second node (56) and ground.

Inventors: LUICH, THOMAS M.
Applicants: FAIRCHILD SEMICONDUCTOR CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H03K19, H03K5