WRITE CIRCUIT FOR AN ERASABLE PROGRAMMABLE READ ONLY MEMORY DEVICE OF A MICROCOMPUTER

Abstract: A write circuit for an EPROM device of a microcomputer comprises a first circuit (28) responsive to an external clock signal (WCLK) and machine clock signals (Ø₁, Ø₂) for sup­ plying a clock signal (CLK) to a program counter (23) of the microcomputer so as to successively increment an address produced in the program counter, where the external clock signal (WCLK) has a frequency lower than those of the ma­ chine clock signals (Ø₁, Ø₂) and the clock signal (CLK) has different frequencies during normal and write-in operation modes so that the address produced in the program counter (23) is successively incremented in synchronism with the machine clock signals (Ø₁, Ø₂) during the normal operation mode and is successively incremented in synchronism with the external clock signal (WCLK) during the write operation mode, and a second circuit responsive to the machine clock signals and the bit data of a LSB (least significant bit) of the address from the program counter for generating a bit line clock signal (BCLK) for inhibiting a write-in data from being written into the EPROM device during a time period in which the address changes.

Description: The present invention generally relates to write circuits for erasable programmable read only memory devices of microcomputers, and more particularly to a write circuit for an erasable programmable read only memory device of a microcomputer in which write-in addresses of the erasable programmable read only memory device can be generated by applying a low-frequency external clock signal to the write circuit. Conventionally, when writing information into an erasable programmable read only memory (hereinafter simply referred to as an EPROM) of a microcomputer, there is a need to supply addresses of the EPROM from outside of the microcomputer. The conventional microcomputer comprises a program counter, a plurality of multiplexers, a word line driver, the EPROM and the like. Because the program counter operates in synchronism with a machine clock signal having a period of 2 to 3 microseconds during a normal operation mode such as a read operation mode, it is impossible to obtain a sufficiently long write cycle in the order of 50 milliseconds from outputs of the program counter. For this reason, the microcomputer is provided with address terminals for receiving a write-in address during the write (program) operation mode. Thus, the multiplexers couple the outputs of the program counter to the word line driver during the normal operation mode, and switch over to couple the address terminals to the word line driver during the write operation mode. However, especially in the case of a one-chip microcomputer, there is a limit to the number of terminals that can be provided. Accordingly, it is disadvantageous to reserve terminals for the address terminals described before. In addition, the conventional write circuit for the EPROM of the microcomputer suffers a problem in that the circuit construction is complex because of the need to provide the multiplexers for multiplexing the outputs of the program counter and the write-in address from the address terminals. An embodiment of the present invention can provide a write circuit for an EPROM device of a microcomputer in which the problems described heretofore are mitigated or eliminated. An embodiment of the present invention can provide a write circuit for an EPROM device of a microcomputer comprising a clock generating circuit responsive to an external clock signal and machine clock signals for supplying a clock signal to a program counter of the microcomputer so as to successively increment an address produced in the program counter, where the external clock signal has a frequency lower than those of the machine clock signals and the clock signal has different frequencies during normal and write-in operation modes so that the address produced in the program counter is successively incremented in synchronism with the machine clock signals during the normal operation mode and is successively incremented in synchronism with the external clock signal during the write operation mode, and a bit line clock generating circuit responsive to the machine clock signals and the bit data of a least significant bit of the address from the program counter for generating a bit line clock signal for inhibiting write-in data from being written into the EPROM device during a time period in which the address changes. With the write circuit of this embodiment of the present invention, it is possible to generate a write-in address of the EPROM device during the write operation mode by simply applying the external clock signal to the first circuit. Hence, it is unnecessary to provide a plurality of address terminals on the microcomputer and it is sufficient to provide a terminal for receiving the external clock signal. For this reason, it is possible to more effectively utilize the limited number of terminals of the microcomputer. Furthermore, it is possible to positively prevent an erroneous write operation such as the writing of the write-in data into an erroneous address, because the bit line clock signal inhibits the write-in data from being written into the EPROM device during the time period in which the write-in address changes. Reference is made, by way of example, to the accompanying drawings, in which:- FIG.1 is a system block diagram showing an example of a microcomputer comprising a program counter and an EPROM; FIG. 2 is a system block diagram showing an example of a write circuit for an EPROM device of a microcomputer according to an embodiment of the present invention, together with related parts of the microcomputer; FIGS. 3(A) through 3(C) are timing charts for explaining the operation of the block system shown in FIG. 2; FIG. 4 is a circuit diagram showing an example of a part of the write circuit of an embodiment of the present invention; FIGS.5(A) through 5(I) are timing charts for explaining the operation of the circuit shown in FIG.4; FIG.6 is a diagram for explaining the incrementing of a write-in address in correspondence with a clock signal WCLK; FIG. 7 is a circuit diagram showing an example of another part of the write circuit of an embodiment of the present invention, together with related circuit parts of the microcomputer; and FIGS.8(A) through 8(D) are timing charts for explaining the operation of the circuit shown in FIG.7. First, description will be given with respect to an example of a microcomputer comprising the EPROM by referring to FIG.1. The microcomputer generally comprises an EPROM 11, a word line driver 12, multiplexers 13₁ through 13 n , and a program counter 14. In FIG.1, the illustration of a bit line driver and the like is omitted for convenience' sake. The multiplexers 13₁ through 13 n respectively comprise an N-channel transistor coupled to a terminal 16 and an N-channel transistor coupled to the terminal 16 via an inverter 17. When writing information into the EPROM 11, there is a need to supply addresses of the EPROM 11 from outside of the microcomputer. Because the program counter 14 operates in synchronism with a machine clock signal having a period of 2 to 3 microseconds during a normal operation mode such as a read operation mode, it is impossible to obtain a sufficiently long write cycle in the order of 50 milliseconds from outputs a₁ through a n of the program counter 14. For this reason, the microcomputer is provided with address terminals 15₁ through 15 n for receiving a write-in address during the write operation mode. Thus, the multiplexers 13₁ through 13 n couple the output address bits a₁ through a n of the program counter 14 to the word line driver 12 responsive to a low-level switching control signal CNTL1 applied to the terminal 16 during the normal operation mode, for example, and switch over to couple the address terminals 15₁ through 15 n to the word line driver 12 responsive to a high-level switching control signal CNTL1 applied to the terminal 16 during the write operation mode. However, especially in the case of a one-chip microcomputer, there is a limit to the number of terminals that can be provided. Accordingly, it is disadvantageous to reserve terminals for the address terminals 15₁ through 15 n . In addition, the write circuit for the EPROM of the microcomputer of FIG.1 suffers a problem in that the circuit construction is complex because of the need to provide the multiplexers 13₁ through 13 n for multiplexing the output address bits a₁ through a n of the program counter 14 and the write-in address from the address terminals 15₁ through 15 n . FIG. 2 shows an example of a write circuit for an EPROM device of a microcomputer according to an embodiment of the present invention, together with related parts of the microcomputer. The microcomputer generally comprises an EPROM 21, a word line driver 22, a program counter 23, and a bit line driver 24. The write circuit according to the embodiment of the present invention comprises a write timing control circuit 25. The write timing control circuit 25 comprises a clock generating circuit 28 and a bit line clock generating circuit 29. An external low-frequency clock signal WCLK is supplied to the clock generating circuit 28 from a terminal 26, and a control signal CNTL2 is supplied to the clock generating circuit 20 and the bit line clock generating circuit 29 from a terminal 27. For example, the control signal CNTL2 has a high level during the normal operation mode and has a low level during the write operation mode. Machine clock signals ₁ and ₂ (and inverted signals  ₁ and  ₂ thereof) having mutually different phases so that pulses thereof do not overlap each other are also supplied to the clock generating circuit 28 and the bit line clock generating circuit 29. The machine clock signals ₁ and ₂ have a period in the order of several microseconds. The clock generating circuit 28 generates from the external clock signal WCLK shown in FIG.3(A) and the control signal CNTL2 such a clock signal CLK during the write operation mode that the program counter 23 generates a write-in address ADDR shown in FIG.3(B) represented by address bits A0 through An responsive to trailing edges of the external clock signal WCLK. The bit line clock generating circuit 29 generates from a least significant bit (LSB) A0 of the write-in address ADDR, the machine clock signals ₁ and ₂ and the control signal CNTL2 a bit line clock signal BCLK for inhibiting write-in data DA shown in FIG.3(C) represented by data bits D0 through Dm from being supplied to the EPROM 21 from the bit line driver 24 when the write-in address ADDR changes. For example, the write-in data DA is inhibited from being written into the EPROM 21 when the bit line clock signal BCLK has a low level. According to the embodiment, it is possible to generate the write-in address of the EPROM 21 by simply applying the external clock signal WCLK to the clock generating circuit 28 and applying the output clock signal CLK of the clock generating circuit 28 to the program counter 23. Hence, it is unnecessary to provide a plurality of address terminals on the microcomputer and it is sufficient to provide the terminal 26 for receiving the external clock signal WCLK. For this reason, it is possible to more effectively utilize the limited number of terminals of the microcomputer. Furthermore, it is possible to positively prevent an erroneous write operation such as the writing of the write-in data into an erroneous address, because the bit line clock signal BCLK inhibits the write-in data from being written into the EPROM 21 during the time period in which the write-in address changes. FIG.4 shows an example of a part of the write circuit together with a related part of the microcomputer. In FIG. 4, those parts which are the same as those corresponding parts in FIG.2 are designated by the same reference numerals, and description thereof will be omitted. The clock generating circuit 28 comprises a first transfer gate 31 comprising P-channel transistors Q1 and Q2 and N-channel transistors Q3 and Q4, a second transfer gate 32 comprising P-channel transistors Q5 and Q6 and N-channel transistors Q7 and Q8, an AND circuit 33, a NOR circuit 34, a gate circuit 35 comprising P-channel transistors Q9 and Q10 and an N-channel transistor Q11, and an inverter 36. The first transfer gate 31 is supplied with the clock signal WCLK from the terminal 26 and the machine clock signals ₂ and  ₂. The second transfer gate 32 is supplied with an output signal of the first transfer gate 31 and the machine clock signals ₁ and  ₁. The AND circuit 33 is supplied with the output signals of the first and second transfer gates 31 and 32. The NOR circuit 34 is supplied with an output signal of the AND circuit 33 and the control signal CNTL2 from the terminal 27. The gate circuit 35 is supplied with an output signal of the NOR circuit 34 and the machine clock signals ₁ and  ₂. An output signal of the gate circuit 35 is supplied to the program counter 23 as an output clock signal CLK of the clock generating circuit 28. During the normal operation mode, the control signal CNTL2 applied to the terminal 27 has a high level. Hence, a low-level output is obtained from the NOR circuit 34, and as shown in FIG.5(G), an output signal CLK of the inverter 36 rises with a rise in the machine clock signal ₁ shown in FIG.5(A) and falls with a rise in the machine clock signal ₂ shown in FIG.5(B). As a result, the address produced in the program counter 23 is incremented responsive to the output signal of the inverter 36 in synchronism with the machine clock signals ₁ and ₂, and access is made to the EPROM 21 shown in FIG.2 in synchronism with the output signal of the inverter 36. FIGS.5(H) and 5(I) show the periods with which the address bits A0 and A1 change, respectively. On the other hand, during the write (program) operation mode, the control signal CNTL2 applied to the terminal 27 has a low level. Hence, a high-level output is obtained from the NOR circuit 34 when a low-level signal is supplied to the other input terminal of the NOR circuit 34. In other words, the source of the clock signal supplied to the program counter 23 is changed from the machine clock signals ₁ and ₂ of the microcomputer to the external low-frequency clock signal WCLK having a period T of 50 msec, for example. When the external clock signal WCLK from the terminal 26 falls as shown in FIG.5(C), a signal b shown in FIG.5(D) which falls with a rise in the machine clock signal ₂ shown in FIG.5(B) and rises with a rise in the machine clock signal ₁ shown in FIG.5(A) is obtained from the NOR circuit 34. As a result, a signal CLK shown in FIG.5(E) is obtained from the inverter 36 and is supplied to the program counter 23. The address produced in the program counter 23 is incremented responsive to a fall in the output signal CLK of the inverter 36. FIG.6 shows the incrementing of the write-in address produced in the program counter 23 with reference to the external clock signal WCLK for a case where the address comprises three bits, for example. It may be seen from FIG.6 that the address is incremented responsive to each fall in the external clock signal WCLK. Therefore, the selection of the write-in address of the EPROM 21 is performed in synchronism with the external clock signal WCLK. FIG.7 shows an example of another part of the write circuit,together with a related part of the microcomputer. In FIG. 7, those parts which are the same as those corresponding parts in FIG.2 are designated by the same reference numerals, and description thereof will be omitted. The LSB A0 of the address from the program counter 23 is applied to a terminal 40 and is supplied to the bit line clock generating circuit 29. The bit line clock generating circuit 29 comprises a first transfer gate 41 comprising P-channel transistors Q21 and Q22 and N-channel transistors Q23 and Q24, a second transfer gate 42 comprising P-channel transistors Q25 and Q26 and N-channel transistors Q27 and Q28, a third transfer gate 43 comprising P-channel transistors Q29 and Q30 and N-channel transistors Q31 and Q32, an exclusive-OR circuit 44, and a NOR circuit 45. The first transfer gate 41 is supplied with the LSB A0 of the address and the machine clock signals ₁ and  ₂. The second transfer gate 42 is supplied with an output signal of the first transfer gate 41 and the machine clock signals ₂ and  ₂. The third transfer gate 43 is supplied with an output signal of the second transfer gate 42 and the machine clock signals ₁ and  ₁. The exclusive-OR circuit 44 is supplied with the output signals of the second and third transfer gates 42 and 43, and an output signal of the exclusive-OR circuit 44 is supplied to one input terminal of the NOR circuit 45. The control signal CNTL2 from the terminal 27 is supplied to the other input terminal of the NOR circuit 45. An output signal of the NOR circuit 45 is supplied to one input terminal of a NAND circuit 46 of the bit line driver 24 as an output bit line clock signal BCLK of the bit line clock generating circuit 29. The word line driver 22 comprises an address decoder 47 and a driving circuit 48 comprising an inverter and N-channel and P-channel transistors. The output signal of the second transfer gate 42, that is, the delayed word address bit A0 which has been delayed by the first and second transfer gates 41 and 42 under the control of the machine clock signals ₁ and ₂, is decoded in the address decoder 47, and the driving circuit 48 drives a selected word line, WLs for example. As a result, an information is written into a selected memory cell Ms of the EPROM 21 when the word line WLs and a bit line BLs coupled to the selected memory cell Ms are driven. Since other word lines WL are not driven, no information is written into other memory cells M coupled to the bit line BLs. The memory cells of the EPROM 21 are arranged in a matrix arrangement and are coupled to respective word lines WL and bit lines BL, but only a portion of the EPROM 21 is shown in FIG.7 for convenience' sake. The bit line driver 24 comprises the NAND circuit 46 and a driving circuit 49 comprising N-channel and P-channel transistors. For example, the data bit D0 of the write-in data DA is applied to a terminal 50 and is supplied to the other input terminal of the NAND circuit 46. Hence, the driving circuit 49 drives the selected bit line BLs only when the bit line clock signal BCLK has a high level, and the driving of the bit line BLs is inhibited during a low-level period of the bit line clock signal BCLK. In other words, the write-in operation to the EPROM 21 is inhibited during the low-level period of the bit line clock signal BCLK. The low-level period of the bit line clock signal BCLK is in the order of several microseconds, that is, one machine cycle clock. FIGS.8(A) through 8(D) are time charts showing the relationships of the LSB A0 of the address, the machine clock signals ₁ and ₂ and the bit line clock signal BCLK. It may be seen from FIGS.8(A) and 8(D) that the bit line clock signal BCLK inhibits the write-in to the EPROM 21 during a time period in which the address change takes place.

Claims: Microcomputer comprising an erasable programmable read only memory device (21) and a write circuit for said erasable programmable read only memory device (21), said microcomputer comprising a program counter (23) which operates in synchronism with machine clock signals (₁,₂), said write circuit being characterized by comprising: a clock generating circuit (28) responsive to an external clock signal (WCLK) and said machine clock signals for supplying a clock signal (CLK) to said program counter so as to successively increment an address produced in said program counter, said external clock signal (WCLK) having a frequency lower than frequencies of said machine clock signals, said clock signal (CLK) having different frequencies during a normal operation mode and a write-in operation mode so that said address produced in said program counter (23) is successively incremented in synchronism with said machine clock signals during the normal operation mode and is successively incremented in synchronism with said external clock signal (WCLK) during the write operation mode; and a bit line clock generating circuit (29) responsive to said machine clock signals and a bit data A0 of a least significant bit of said address from said program counter (23) for generating a bit line clock signal (BCLK) for inhibiting a write-in data D0,...,Dm from being written into said erasable programmable read only memory device (21) during a time period in which said address changes. Microcomputer as claimed in claim 1 in which said machine clock signals comprise first and second machine clock signals (₁ and ₂) having mutually different phases so that pulses thereof do not overlap each other, said clock generating circuit (28) being supplied with a control signal (CNTL2) indicative of whether the operation mode of said erasable programmable read only memory device is the normal operation mode or the write-in operation mode, said clock generating circuit generating said clock signal (CLK) which rises and falls responsive to transitions of said first and second machine clock signals (₁ and ₂) when said control signal (CNTL2) indicates the normal operation mode, and generating said clock signal (CLK) which undergoes a first transition in response to a transition of said second machine clock signal (₂) and undergoes a second transition in response to a transition of said first machine clock signal (₁) only subsequent to a transition of said external clock signal (WCLK). Microcomputer as claimed in claim 2 in which said clock generating circuit generates said clock signal (CLK) which rises with a rise in said first machine clock signal (₁) and falls with a rise in said second machine clock signal (₂) when said control signal (CNTL2) indicates the normal operation mode, and generates said clock signal (CLK) which falls with a rise in said second machine clock signal (₂) and rises with a rise in said first machine clock signal (₁) only subsequent to a falling of said external clock signal (WCLK). Microcomputer as claimed in claim 2 or 3 in which said first and second machine clock signals(₁ and ₂) have a period in the order of several microseconds and said clock signal (CLK) has a period in the order of fifty milliseconds. Microcomputer as claimed in any preceding claim in which said machine clock signals comprise first and second machine clock signals (₁ and ₂) having mutually different phases so that pulses thereof do not overlap each other, said bit line clock generating circuit (29) comprising a delay circuit for delaying the bit data of the least significant bit (A0) of said address by use of said first and second machine clock signals (₁ and ₂) so as to produce a delayed bit data, an exclusive-OR circuit (44) supplied with the bit data and the delayed bit data of the least significant bit of said address and a NOR circuit (45) supplied with an output signal of said exclusive-OR circuit and a control signal (CNTL2) indicative of whether the operation mode of said erasable programmable read only memory device is the normal operation mode or the write-in operation mode, said NOR circuit producing said bit line clock signal (BCLK). Microcomputer as claimed in claim 1 in which said clock signal (CLK) has a period which is sufficiently long for writing an information into said erasable programmable read only memory device during the write operation mode. Microcomputer as claimed in claim 1 which further comprises a word line driver (22) supplied with said address from said program counter for driving a word line of said erasable programmable read only memory device and a bit line driver (24) supplied with said write-in data (D0) and said bit line clock signal (BCLK) from said bit line clock generating circuit for driving a bit line of said erasable programmable read only memory device excluding said time period in which said address changes.

Inventors: YAMAGUCHI, SATORU FUJITSU LIMITED PATENT DPT.
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G11C17
IPC codes: G06F15, G11C16, G11C17, G11C7