BIPOLAR TRANSISTOR

Abstract: A bipolar transistor suitable for high speed operation and having base (11), collector (9) and emitter (12) semicon­ ductor regions is provided. The base region (11) is provided with two contacts (13, 14) on either side of the base region one of which (14) is connected to and preferably integral with the emitter contact (15). The resulting current flow (17) beneath the emitter debiasses all but a portion of the emitter adjacent the base contact thus giving shorter transit times, increased speed of operation and enabling use of reduced device area with reduced collector-substrate and collector-­ base capacitance.

Description: BIPOLAR TRMISISTOR This invention relates to a bipolar transistor suitable for high speed operation and which comprises semiconductor regions of a first conductivity type each having a contact and forming collector and emitter regions and an intermediate semiconductor region of a second conductivity type forming a base region having two contacts each connected to opposed sides of the base region. Bipolar transistors of this type are known in the art for example that disclosed in gA Junction Transistor Tetrode for high frequency use" Proc. IRE 40 (1952) pp 1395-1400. This discloses an n-p-n transistor having a base contact on each of two opposed edges of the base region. Currently bipolar transistors are mainly used for high speed memory and logic devices. "High speed" in this context means capable of sub nanosecond switching times; that is, operable at clock rates in excess of 1 GHz. A major factor inhibiting the speed of operation of such devices is the base-spreading resistance of- - the transistor. It is known to limit the effect of this to a certain extent by shorting contacts connected to each of two opposed edges of the base region to form a single base connection. Such an arrangement is shown in Fig#ure 1. In Figure 1 a bipolar transistor is shown in cross section in which a collector semiconductor region 1 covered by a silicon dioxide layer 2, surrounds a base region 3 which surrounds an emitter region 4. Metal contact layers (5,6) are provided for the base regions on either side of the emitter region and are connected together to form a common base connection 7. A separate metal contact layer 8 is also provided for the emitter region 4. However such an arrangement still has a considerable base resistance which limits the speed of operation of such transistors. This is made worse when the width of the base region is decreased in order tcr try to achieve shorter transit times and higher speeds of operation since -^ sheet resistivity of the base region increases as the base width decreases. Thus whilst a high value of (the frequency at unity common emitter current gain) may be obtained with such an arrangement the improvement in wjlue of fiax (the frequency at unity power gain) is v less significant. The connection of part of the base region to the emitter contact is also known in the context of bipolar power transistors from US patent number 4,225,874 and ##291,324. However in US 4,225,874 the reason for providing the connection is to provide a diode which acts to prevent damage to the basecol lector p-n junction when it is reverse biased with a high voltage. In US 4,291,324 q high resistance pillar extends from the base region through the annular emitter region to contact the centre of the emitter contact to provide a shunt ballasting structure which gives protection against forward and reverse second breakdown. According to the present invention there is provided a bipolar transistor suitable for high speed operation, comprising semiconductor regions of a first conductivity type each having a contact and forming collector and regions and an intermediate semiconductor region {, a second conductivity type forming a base region having < conwac-s each connected to opposed sides of the base #,-#?. the contacts connected to an edge of , sç region is connected to the contact connected to d'+or region Preferably the transistor is a planar transistor formed by diffusion or deposition of said semiconductor regions and contacts in or onto a substrate. More preferably the contact for the emitter and that connected to one edge of the base region to which the emitter contact is connected are integral. The transistor is preferably of n-p-n construction though p-n-p construction may be used. The transistor according to the present invention by effectively shorting the emitter to one edge of the base region enables the creation of a lateral current flow beneath the emitter which causes a voltage drop across the width of the emitter. This enables only the edge of the emitter closest to the base contact itself to be biassed on so that all the base current enters the emitter there. The route travelled by the base current is thus considerably shorter and the base resistance consequently less than for prior art arrangements. The current flowing laterally in the base region thus de-biases most of the base-emitter junction giving an effective submicron emitter stripe-width. This reduces the need for reducing the emitter width to submicron levels (which would be necessary in conventional devices with base widths of less than about 0.2cm) which would involve difficulties with the lithography required. The lateral electric field thus created in the base region gives rise to the name of devices according to the present invention - Base Field Transistor (BFT). The creation of such a field in a BFT would be expected to give the device an undesirably low forward current gain due to the bias current flowing from the base contact beneath the emitter. However, in the BFT whilst the intrinsic base resistance can remain small due to both the small effective emitter width and the high degree of current crowding the high resistivity of the intrinsic base region acts as an advantage instead of a disadvantage since it reduces the de-biassing current flowing beneath the emitter thus improving the forward current gain. A further advantage of the BFT arises in integration of such devices as significant savings in overall device area may be made. The overall dimensions are dictated by metal pitches and aligrunent tolerances and in the BFT some of these tolerances lay be eliminated resulting in a smaller total device area. Such a reduction in overall area also brings the advantage that the collector substrate and collector base capacitances are reduced. Embodiments of devices according. to the present invention will now be described in more detail with reference to the accompanying drawings in which Figure 1 shows a diagrammatic cross section of a bipolar transistor according to the prior art having common base connections. Figure 2 shows a diagrammatic cross section of a bipolar transistor according to a first embodiment of the present invention. Figure 3 shows a diagramsatic cross-section of a bipolar transistor according to a further embodiment of the present invention. In Figure 2 a cross section of a bipolar transistor according to an embodiment of the present invention is shown waving a plantar constructior. A collector region 9 #overed by a silicon dioxide layer 10 and surrounds a ¯,236 region 11 (of width 41) which surrounds an emitter region 12. Metal contact layers (13,14) are provided for the base regions on either side of the emitter region (of width 42). A metal contact 15 is provided for the emitter, region 12. The emitter region contact 15 and one of the opposed base contacts 14 are connected together to form an emitter contact 16. The connection of these two contacts results in the flow of a debiassing current 17 beneath the emitter region and between the two base contacts. This current is rendered small by the high resistlvi,ty of the intrinsic base region and thus the forward current gain of the transistor need not be adversely affected. Commonly a forward current gain of about a factor of 40 is required for bipolar transistors used in digital circuits and such a gain figure can still be obtained using transistors, according to the present invention. The effect of the debiassing current though is to debias all but a portion of the emitter region 12 adjacent the base contact 13. It is thus only at this point that the base current 18 flows to the emitter. The route taken by the base current 18 is thus considerably shorter than that taken by the base current 19 in transistors according to the prior art as shown in Figure 1. This short base current route, effectively very thin emitter width and high degree of current crowding all result in a considerably lower intrinsic base resistance and thus higher operating speed. This is achieved despite the high resistivity of the intrinsic base region which in fact serves as an advantage in reducing the debiassing current and thus preserving a useful forward current gain. Transistors according to the present invention preferably have base widths of less than O.Sum, and more preferably of less than 0.2m. Because of the effective reduction in emitter width with transistors according to the present-invention, it is no longer the' actual printed size of the emitter which determines the ininlit- acceptable base width. It is therefore possible1 for a given emitter width, to use snaller base width than is feasible with conventional constructions. Hence, even with 'çasily' printed 1 to 2 t printed emitter widths, it is possible to have base widths of less than 0.21. Furthenore the achievement of these effects by connecting the emitter contact to one of the base contacts enables the device to be fabricated using any existing bipolar process or construction without amy additional processing steps. The device though is particularly suitable for fabrication processes involving a polysilicon coated emitter process. Whilst the presence of the debiassing current reduces the forward current gain this reduction is not as great as might be expected due to the high resistivity of the intrinsic base region. The use of a polysil icpn emitter electrode is advantageous in that it increases the gain of what is inherently a low gain device. A thin interfacial layer is formed between the polysil icon and the material of the base. Because electrons tunnel through this interfacial layer better than do holes, injection of electrons from the emitter to the base is more efficient than is injection of holes from base to emitter. Hence the device still gives a useful gain and also has greatly enhanced emitter efficiency. The connection of the emitter contact to one of the base contacts also enables substantial advantages in the reduction of the device area to be achieved. One particular way of increasing such savings is to amalgamate the emitter contact and the base contact to which it is connected thus using a single integral emitter contact which also contacts one side of the base region. Such an arrangement is shown in Figure 3 where a collector region 20 is covered by a silicon dioxide layer 21 and surrounds a base region 22 which surrounds an emitter region 23. The base region is provided with a contact '25 which contacts not only the emitter region 23 but also one side of the base region 26 on the opposite side of the emitter to that on which the side of the base region carrying the base contact is located. The integral contact thus overlies the exposed emitter base junction. Using this manner of construction the overall area occupied by the device is considerably reduced. By such reductions in the metal pitches and alignment tolerances required, the device can be reduced in size without any adverse affects. In fact considerable advantages arise since the reduction in device area results in a¯ reduction in the collector substrate and collector base capacitances of the device with consequently improved performance. The increased speed of operation, reduction in size and capacitance renders devices according' to the present invention particularly suited to use in high speed digital integrated circuit applications.

Claims: CLAIMS 1. A bipolar transistor suitable for high speed operation, comprising semiconductor #regions of a first conductivity type each having a contact and forming collector (9,20) and emitter (12,23'I regions and an intermediate semiconductor region of aNFecond conductivity type forming a base region (11,22) having two contacts (13,14; 23,26) each connected to opposed sides of the base region wherein one (14,26) of the contacts connected to an edge of said base region is connected to the contact (15,25) connected to said emitter region. 2. A transistor according to clalm 1 wherein the transistor is of planar construction. 3. A transistor according to clati 1 or 2 wherein the emitter contact and the base contact to which it is connected are integral. 4. A transistor according to ciala 3 wherein said integral contact overlies the Junctfonz between said emitter and said side of the base region to which said Integral contact Is connected where said junction Is exposed at a surface of the device. 5. A transistor according to any one of the preceding claims wherein said first conductivity type of semiconductor is n-type and said second conductivity type of semiconductor is p-type. 6. A transistor as claimed in any one of claims 2 to 5 wherein said emitter region is provided with a polysilicon emitter electrode. 7. An integrated circuit comprising a plurality of transistors as claimed in any one of claims 1 to 6 integrated on a common substrate.

Inventors: CHANDLER, TIMOTHY JOHN, HOLMES, PHILLIP EDWARD, WELBOURN, ANTHONY DAVID
Applicants: BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY
Application year: 1986
Main classification: H01L29
IPC codes: H01L29