Data randomization equipment

Abstract: Input data (R) is split by a splitting part (21) into a plurality of block data having an equal data length to be processed through respective channels (25 to 28). Each channel data is subjected in a function operation part (22) to a function operation in direct or indirect relation to all the other channel data to produce new channel data. Each channel data is subjected in a transform operation part (23) to a transform operation to produce new channel data. All final channel data obtained after function and transform operations are combined by a combining part (24) to obtain randomized data.

Description: This invention relates to a data randomization equipment for randomizing digital data and to be used for random number generators for generating random numbers of digital data and for encrypting and decrypting processes of cryptographic equipment. The data randomization equipment will first be briefly described. As shown in Fig. 1, data randomization equipment receives digital input data and digital parameter data and provides randomized data as output data. High class data randomization equipment features that nearly one half of the output data bits are changed with a slight change in the input data or parameter data. The prior art will be described as an example of data randomization equipment which is employed in the DES encrypter as a typical cryptographic equipment. Fig. 2 shows this data randomization equipment. The size of 32-bit input data is expanded by data expanding means 12 into 48-bit data. In this data expansion, the 32-bit input data is split into eight blocks each of 4 bits, and the bits on both sides of each 4-bit block are each branched into two bits. Exclusive OR part 13 takes exclusive OR between each bit of the expanded 48-bit data and a corresponding bit of 48-bit parameter data. The resultant 48-bit data is split into 8 blocks each of 6 bits, and these data blocks are fed to respective ROMs 14₁ to 14₈ which are commonly termed S boxes. The S boxes 14₁ to 14₈ each provide 4-bit data using the 6-bit input data as an address. The 32-bit data as the outputs of all the S boxes 14₁ to 14₈ is fed to a permutation part 15 constituted by a wired circuit. The permutation part 15 effects bit position re-arrangement of the 32-bit input data and yields the resultant output as a randomized output. In this prior art equipment, with a change in the input to each of the S boxes 14₁ to 14₈, only one bit at the least to 4 bits at the most of the output undergo a change from "0" to "1" or from "1" to "0", that is, 2.5 bits, in average, of the output are changed. This means that with the occurrence of the change of one bit in the input data to the prior art data randomization equipment, only one bit in the least to 8 bits at the most, i.e., only 4 bits in average, of the 32-bit output data are changed. Further, with a change of one bit of the parameter data to this equipment only 2.5 bits of the output data are changed. A data randomization equipment and method according to the precharacterizing portions of claims 1 and 5 is disclosed in the document COMPUTER, Vol.10, No. 6, June 1977, LONG BEACH US, p.74-84; DIFFIE et al.: "Exhaustive cryptanalysis of the NBS Data Encryption Standard". In this prior art the first function operation means in each randomization stage performs function operation between the right data input to said randomization stage and 48 key bits selected from a 64 bit key according to a specific key scheduling algorithm. SUMMARY OF THE INVENTION An object of the invention is to provide a data randomization equipment, in which nearly one half of the output data bits are changed with change of one bit or a very small number of bits of the input data. This object is achieved with a data randomization equipment and method as claimed in claims 1 and 5, respectively. Preferred embodiments of the invention are subjectmatter of the dependent claims. According to the invention, a plurality of randomization stages are provided in cascade connection, each stage including randomizing means. Input data is fed to the first one of the cascade connected randomization stages for randomization through the consecutive randomization stages. In all or some of randomization stages subsequent to an N-th (N being 2 or a greater integer) one, the input data to the randomizing means in the preceding randomization stage is fed as parameter data to the randomizing means of the pertinent stage. According to the invention, each of a plurality of channel data is subjected to function operation in direct or indirect relation to all the other channel data, so that each final channel data is influenced by all the channel data. Therefore, a one-bit change in the input data leads to a change in a large number of bits of the output data. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a concept of data randomization equipment; Fig. 2 is a view showing data randomization equipment used for a prior art DES encryption equipment; Fig. 3 is a block diagram showing an example of arrangement of a data randomization equipment ; Fig. 4 is a block diagram showing one embodiment of the data randomization equipment ; Fig. 5 is a block diagram showing a different embodiment of the data randomization equipment ; Fig. 6 is a block diagram showing a further embodiment, in which transform and function operations are changed over dynamically; Fig. 7 is a block diagram showing a further embodiment applied to a data randomization equipment dealing with 16-bit input data; Fig. 8 is a block diagram showing a further embodiment of the data randomization equipment, in which similar randomization operation is performed in a plurality of stages; Fig. 9 is a block diagram showing an embodiment of the data randomization equipment according to the invention, in which similar randomization operation is performed in a plurality of stages without use of any parameter data; Fig. 10 is a block diagram showing a further embodiment applied to a data randomization equipment in case where 224-bit parameter data is used; and Fig. 11 is a block diagram showing a further embodiment of the randomization equipment according to the invention, in which 128-bit input data is randomized to obtain 224-bit output data. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 3 shows an example of the arrangement of a data randomization equipment. Input data R is split by a splitting part 21 into a plurality of blocks each with a data length of n bits. The individual block data obtained from the splitting part 21 are processed as channel data through respective processing channels 25 to 28. In each of the processing channels, the channel data is processed through at least one function operation part 22 and, upon request, a transform part 23. The outputs of the individual channels 25 to 28 are combined by combining part 24 to be yielded as an output data. Each function operation part 22 performs a function operation on the input channel data of the pertinent channel with a channel data of a different channel or with parameter data to produce a renewed channel data. Or it performs a function operation on the channel data and parameter data to produce a new parameter data. Each transform part 23 performs bit circulation or bit permutation operation on the input channel data of the pertinent channel to produce a new channel data. Fig. 4 shows an embodiment in which 32-bit input data is processed to obtain 32-bit randomized output data using 16 bits of parameter data. The 32-bit input data R is split by splitting part 21 into 8-bit blocks R0 to R3. The block data R0 to R3 are input to as channel data and processed through respective processing channels 25 to 28 provided between the splitting part 21 and the combining part 24. In channel 25, addition/modulo operation circuit 29 and bit circulation circuit 30 are provided in the mentioned order. In channel 26, exclusive OR circuits (hereinafter referred to as EOR circuits) 31 and 32, addition/modulo operation circuit 33 and bit circulation circuit 34 are provided in the mentioned order. In channel 27, EOR circuits 35 and 36, addition/modulo operation circuit 37 and bit circulation circuit 38 are provided. In channel 28, addition/modulo operation circuit 39 and bit circulation circuit 41 are provided. Parameter data P0 and P1 are fed to the respective EOR circuits 31 and 35, and the block data R0 and R3 are fed to the respective EOR circuits 32 and 36. A constant +1 and outputs of the EOR circuits 32 and 36 are fed to the addition/modulo operation circuit 33. The output of the addition/modulo operation circuit 33 is supplied to the bit circulation circuit 34. The output of the bit circulation circuit 34 is fed to the addition/modulo operation circuit 29. The outputs of the bit circulation circuit 34 and the EOR circuit 36 are fed to the addition/modulo operation circuit 37. A constant +1, block data R3 and output of the bit circulation circuit 38 are fed to the addition/modulo operation circuit 39. The EOR circuits 31, 32, 35 and 36 each perform a bit-by-bit exclusive OR operation on the two input data. The addition/modulo operation circuits 29, 33, 37 and 39 each perform addition of the input data and then perform modulo 256 operation on the resultant sum data. Modulo operation x mod y means an operation of obtaining the remainder of division of x by y. The bit circulation circuits 30, 34, 38 and 41 each perform a 2-bit leftward circular shift of their input data. The EOR circuits 31, 32, 35 and 36 and addition/modulo operation circuits 29, 33, 37 and 39 each constitute the function operation part 22, while the bit circulation circuits 30, 34, 38 and 41 each constitute the transform part 23 in Fig. 3. With this equipment, the input data is subjected to the following randomization process, where variables R0, R1, R2 and R3 represent the channel data of the respective channels 25, 26, 27 and 28, P0 and P1 represent the parameter data, notation "cir" represents an operation of 2-bit leftward circular shift of data, and a symbol of leftward arrow "←"signifies the substitution of the result of the operation on the right side for the variable on the left side. 1st step: R1 ← R1 ⊕ P0 ⊕ R0 in circuits 31 and 32 R2 ← R2 ⊕ P1 ⊕ R3 in circuits 35 and 36 2nd step: R1 ← (R1 + 1 + R2) mod 256 in circuit 33 3rd step: R1 ← cir R1 in circuit 34 4th step: R2 ← (R1 + R2) mod 256 in circuit 37 5th step: R2 ← cir R2 in circuit 38 6th step: R0 ← (R0 + R1) mod 256 in circuit 29 R3 ← (R3 + R2 + 1) mod 256 in circuit 39 7th step: R0 ← cir R0 in circuit 30 R3 ← cir R3 in circuit 41 The final channel data R0 to R3 of the individual channels 25 to 28, which have been obtained through the above randomization process, are combined in the combining part 24 to obtain output data. The final data of each channel has been influenced either directly or indirectly by the block data inputs to all the channels 25 to 28. For example, with respect to the channel data R0 it will be seen that the channel data R2 and R3 are influenced by each other in the EOR circuit 36, the output of which in turn influences channel data R1 in the addition/modulo operation circuit 33, which is coupled through the bit circulation circuit 34 to the addition/modulo operation circuit 29. That is, the channel data R0 is influenced by all the other channel data R1 to R3. In this manner, all the channel data are each influenced by the other. Consequently, when a change occurs in one bit of the input data, the other channel data than the one having the changed bit are also influenced by this one-bit change. in each of the EOR circuits 32 and 36, a change of one bit of the channel data input thereto leads to a change in one bit of the output data therefrom. In each of the addition/modulo operation circuits 29, 33, 37 and 39, a change of one bit of the channel data input thereto leads to a change of at least one bit and at most all the bits, in this embodiment 8 bits, of the output data therefrom. In each of the bit circulation circuits 30, 34, 38 and 41, a one-bit change in the channel data input thereto leads to a 2-bit change in the output data therefrom. Thus, a one-bit change in the input data R leads to a change of 11 bits in average of the output data. This effect is a pronounced improvement over the prior art technique shown in Fig. 2, in which one-bit change in the input leads to a change of only about 4 bits of the output. In the embodiment shown in Fig. 4, the parameter data P0 and P1 are operated directly on the channel data immediately from the splitting part 21. Thus, one-bit change in the parameter data influences all the channel data, so that a great randomization effect can be achieved. In the above embodiment, the bit circulation circuits 30, 34, 38 and 41 have been explained as to perform bit circulation by 2 bits, but they may perform other extents of bit circulation. In the above embodiment of Fig. 4, the parameter data are operated on the channel data to produce renewed channel data. However, it is also possible to use the operation result as new parameter data in the equipment. Fig. 5 shows a different embodiment, in which new parameter data is produced from the aforesaid operation. In Fig. 5, parts corresponding to those in Fig. 4 are designated by like reference numerals. In this example, those corresponding to the EOR circuits 31 and 35 in the processing channels 26 and 27 of Fig. 4, to which the parameter data are fed, have been omitted. Instead, EOR circuits 42, 43, 44 and 45 are connected to foreign channel data input sides of the addition/modulo operation circuits 29, 33, 37 and 39 in channels 25, 26, 27 and 28. Parameter data P2, P0, P1 and P3 are fed to the respective EOR circuits 42, 43, 44 and 45 and operated on the channel data inputs thereto, whereby new parameter data are produced to be fed to the corresponding addition/modulo operation circuits 29, 33, 37 and 39. Again in this case, a one-bit change in the input data R leads to a 11-bit change in average in the output data. It is possible to cause dynamic changeover of the types of processings according to the values of channel data and/or parameter data. Fig. 6 shows a further embodiment which permits such changeover. In the Figure, parts corresponding to those in Fig. 4 are designated by like reference numerals. In this embodiment, processing channel 25 includes cascade connection of EOR circuit 46, multiplexer 47, permutation circuit 48, EOR circuit 49, addition/modulo operation circuit 29 and transform memory 51 in the mentioned order. One output of the multiplexer 47 is connected to the output of the permutation circuit 48 to form a bypass. In channel 26, EOR circuits 31 and 32, addition/modulo operation circuit 33, EOR circuit 52, bit circulation circuit 34 and addition/modulo operation circuit 53 are provided in cascade in the mentioned order. In channel 27, EOR circuits 35, 36 and 54 and addition/modulo operation circuit 37 are provided in cascade in the mentioned order. In channel 28, addition/modulo operation circuit 55, multiplexer 56, a parallel combination of addition/modulo operation circuit 57 and transform memory 58, multiplexer 59 and a parallel combination of addition/modulo operation circuit 61 and permutation circuit 62 are provided in cascade in the mentioned order. Two outputs of the multiplexer 56 are fed to the respective addition/modulo operation circuit 57 and the transform memory 58, the outputs of which are both connected to the same input of the multiplexer 59. Two outputs of the multiplexer 59 are fed to the addition/modulo operation circuit 61 and the permutation circuit 62, the outputs of which are connected to each other. Parameter data P2 and P3 are fed to the respective EOR circuits 46 and 52. The output of the bit circulation circuit 34 is fed to the EOR circuit 49. The output of the addition/modulo operation circuit 37 is fed to the addition/modulo operation circuits 53, 57 and 61. The output of the addition/modulo operation circuit 33 is fed to the addition/modulo operation circuit 55. The multiplexers 47, 56 and 59 each provide its input as either one of its two outputs according to a one-bit control data. The multiplexers 47 and 56 are controlled by respective one-bit parameter data P4 and P5. The multiplexer 59 is controlled by a particular one bit of the output of the addition/modulo operation circuit 37. The permutation circuits 48 and 62 each operate permutation of bit positions on the input data through mere wired circuits. The transform memories 51 and 58 each may consist of a ROM. Their input data are used as addresses to read out transformed data. In this arrangement, the multiplexer 47 supplies the output of the EOR circuit 46 to the EOR circuit 49 either directly or after transform through the permutation circuit 48 in dependence on the value of parameter data P4. In this way the operation on the channel data is changed over dynamically according to the parameter data. The combination of the states selectable through the multiplexers 56 and 59 allows variety of dynamic change in operation processing on the channel data. In the above embodiment, 32-bit input data R was split into 4 one-byte blocks. Fig. 7 shows a further embodiment of the equipment which effects randomization on 16-bit input data. 16-bit input data is split by splitting part 21 into 8-bit block data R0 and R1 for processing through respective channels 25 and 26. The channel 25 includes addition/modulo operation circuit 29 and bit circulation circuit 30, these parts being provided in cascade in the mentioned order. The channel 26 includes addition/modulo operation circuit 33 and bit circulation circuit 34, these parts being provided in cascade in the mentioned order. EOR circuit 63 performs exclusive OR operation on the block data, i.e. channel data R0 and parameter data P0, and its output data is fed to the addition/modulo operation circuit 33. The addition/modulo operation circuit 33 is also supplied with the channel data R1 and a constant +1, and provide its output to the bit circulation circuit 34. EOR circuit 64 performs exclusive OR operation on the output of the bit circulation circuit 34 and parameter data P1, and its output data is fed to the addition/modulo operation circuit 29. This equipment performs the following randomization process. 1st step: R1 ← ((R0 ⊕ P0) + R1 + 1) mod 256 in circuits 33 and 63 2nd step: R1 ← cir R1 in circuit 34 3rd step: R0 ← ((R0 + (R1 ⊕ P1)) mod 256 in circuits 29 and 64 4th step: R0 ← cir R0 in circuit 30 Processed channel data outputs R0 and R1 from the processing channels 25 and 26 are combined in combining means 24 to obtain 16-bit output data. Data randomization equipment which uses the various arrangements of data randomization equipment described heretofore in each of cascaded plural randomization stages will now be described with reference to Fig. 8. EOR circuit 66 performs exclusive OR operation on 64-bit input data and 64-bit parameter data P4, P5, P6, P7, and its output is split in splitting part 67 into left and right block data each of 32 bits. The left block data is fed as such to first randomization stage 68. EOR circuit 69 performs exclusive OR operation on the left and right block data, and its output data is fed as right block data to the first randomization stage 68. In each randomization stage 68, the right data input is directly fed as left data input to the subsequent randomization stage 68, while it is also fed to randomizing part 71 for randomization with 16-bit parameter data. The randomized data output of the randomizing part 71 and left data are exclusively ORed in EOR circuit 72, the output of which is fed as right data to the next randomization stage 68. In this instance, four randomization stages 68 are provided in cascade connection, and each randomization stage 68 performs like process. The left data output of last randomization stage 68 is directly fed to combining part 73. It is also fed to EOR circuit 74 for exclusive ORing with right data. The output of the EOR 74 is fed as right data to the combining part 73. The combining part 73 combines the left and right data to provide 64-bit combined data. EOR circuit 75 performs exclusive OR operation on the 64-bit combined data and 64-bit parameter data to obtain randomized data output. Randomizing part 71 in each randomization stage 68 may be any one of the various arrangements shown in Figs. 3 to 6. Fig. 9 shows an arrangement for randomizing input data without use of any external parameter data. In this instance, 64-bit input data is split by splitting part 67 into left and right block data each of 32 bits. The block data are fed to a first one of a plurality of cascade-connected randomization stages 76. In each randomization stage, right data is fed as left data input to the next randomization stage 76, and it is also fed to EOR circuit 77. Randomizing part 78 randomizes left data with the output of the EOR circuit 77 used as internal parameter data. The output of the randomizing part 78 is fed as right data to the next randomization stage 76. Suitable constant D₀ is fed to the EOR circuit 77 in the first randomization stage 76, while in each of the following randomization stages, left data input to the immediately preceding randomization stage is fed to the EOR 77. The randomizing part 78 of each randomization stage 76 provides 32-bit data as part of 192-bit output data. This means that the 64-bit input data is expanded into 192 bits while it is randomized. The randomizing part 78 may be any one of the arrangements of Figs. 3 to 6 described above. A combination of arrangements of Figs. 8 and 9 may be used as cryptographic equipment either for encrypting a plaintext or decrypting a ciphertext. Such equipment has been proposed in the literature entitled "Fast data encipherment algorithm FEAL", IECEJ Technical Report IT 86-33 (1986) by the present inventors. The encription can be implemented as follows: The 64-bit input data shown in Fig. 9 is fed as a secret key. The output data of 32 by 6 bits, i.e. 192 bits, from the six randomization stages 76 is split into twelve intermediate keys P0 to P11 each of 16 bits in the order of the stages. Of these intermediate keys, the intermediate keys P0 to P3 are fed as parameter data to the respective randomization stages 68 in Fig. 8, the intermediate keys P4 to P7 are fed as parameter data to the EOR circuit 66, and the intermediate keys P8 to P11 are fed as parameter data to the EOR circuit 75. By feeding a plaintext as input to the EOR circuit 66, a ciphertext can be obtained from the EOR circuit 75. For decryption, a ciphertext is fed to the EOR circuit 66, intermediate keys P3, P2, P1 and P0 are fed as parameter data to the respective first to last randomization stages 68, while feeding intermediate keys P8 to P11 to the EOR circuit 66 and intermediate keys P4 to P7 to the EOR circuit 75 as shown in parentheses in Fig. 8. By so doing, an original plaintext can be obtained from the EOR circuit 75. The arrangement of Fig. 8 uses four randomization stages, but it of course is possible to provide a different number of randomization stages. Fig. 10 shows a 6-stage arrangement. In Fig. 10, parts corresponding to those in Fig. 8 are designated by like reference numerals, and their description is omitted. Fig. 11 shows an example of data randomization equipment for obtaining intermediate keys corresponding to a secret key in case where the data randomization equipment of Fig. 10 is used for a cryptographic equipment. In this instance, the input secret key is 128-bit data, which is split in splitting part 80 into two block data each of 64 bits. The two block data are further split in splitting parts 81 and 82 into sub-block data each of 32 bits. The two right sub-block data obtained from the two splitting parts 81 and 82 are exclusively ORed in EOR circuit 83, the output of which is fed as left data to the first one of cascade-connected randomization stages 76. The two left sub-block data from the splitting parts 81 and 82 are fed to randomizing parts 84 and 85 for randomization with respective the right sub-block data. The randomized outputs of the randomizing parts 84 and 85 are fed to EOR circuit 86, the output of which is fed as right data to the first randomization stage 76. Randomization stages 76 are of the same arrangement as those shown in Fig. 9 except that EOR circuit 77 in a concerned randomization stage 76 receives left data input to the randomization stage preceded by three stages from the concerned stage 76. However, all "0" data D₀ is fed to EOR circuit 77 of the first randomization stage 76, and the right sub-block data noted above of the splitting parts 81 and 82 are fed to the EOR circuits 77 of the second and third randomization stages 76, respectively. The outputs of the randomizing parts 78 of the respective randomization stages 76 and outputs of randomizing parts 84 and 85 are provided in combination as 244-bit output data. A combination of arrangements of Figs. 10 and 11 may be used as a cryptographic equipment as follows: The arrangement shown in Fig. 11 is used as a secret key processor, where a 128-bit secret key is input thereto and produces a 224-bit output data composed of 14 intermediate keys P0 through P13 each of 16 bits. The intermediate keys P0 to P3 from the randomizing parts 84 and 85 and the intermediate keys P4 and P5 from the first randomization stage 76 are supplied as parameter data to the first to last randomization stages 68 in Fig. 10 and the intermediate keys P6 to P9 from the second and third randomization stages 76 and the intermediate keys P10 to P13 from the fourth and fifth randomization stages 76 are supplied as parameter data to the EOR circuits 66 and 75 in Fig. 10, respectively. As described before, the arrangements of Figs. 9 and 11 may be used as a secret key processor in a cryptographic equipment. In the secret key processing in the prior art DES cryptographic equipment shown in Fig. 2, one bit is removed from each byte of 64-bit key, the remaining 56-bit data is subjected to bit position permutation, the resultant 56-bit data is split into two 28-bit data, these two data are subjected to leftward bit circulation by one bit or two bits 16 times, and a total of 8 bits are removed from two data resulting from each bit circulation operation while subjecting the resultant data to bit position permutation. In this way, 16 different 48-bit intermediate keys are obtained. In this secret key processing, when one of the intermediate key is known, there are only 8 unknown bits for the leftward bit circulation has been made public. Therefore, the two 28-bit block data can be estimated, so that it is possible to estimate the original 64-bit secret key. Where the arrangements shown in Figs. 9 and 11 are employed for secret key processing, however, the estimation of the original secret key is difficult. In each of the randomizing parts 78, 84 and 85, if two data among two input data and one output data are known, the remaining data can be known. In the case of Fig. 9, however, the key data of the input data consists of 64 bits. Therefore, even if 64 bits of the intermediate keys P8 to P11, for example, are known, the output data of the EOR circuit 77 in the last stage 76 can not be known because it is only data P8 and P9 that are known as one input to the EOR circuit 77 in the last randomization stage 76. That is, only output data P10 and P11 are known with respect to the randomizing part 78 of this stage, and two input data are unknown. Therefore, these input data of that randomizing part 78 can not be determined. For this reason, it is possible to employ other data randomization equipment than those shown in Figs. 3 to 6 as randomizing parts 78, 84 and 85 in Figs. 9 and 11. Even in this case, it is difficult with the arrangements of Figs. 9 and 11 to estimate a correct secret key when some of the intermediate keys are known. In other words, the arrangement itself of the data randomization equipment of Fig. 9 or 11 can effectively serve as data randomization equipment. Further, with the data randomization equipment according to the invention, a one-bit change in the input data leads to a change in nearly one half of the output data bits at all time as noted before. Therefore, by feeding suitably varying data as input data, randomly changing output data can be obtained. This output data may be regarded as random number data. This means that the data randomization equipment according to the invention may be used as a random number generator as well. In the cases of Figs. 3 to 6, the input data was split into 8-bit (i.e., one-byte) data. However, it is possible to split the input data into 16-bit data. In this case, the modulo operation is based on mod 65536 instead of mod 256. Further, in the arrangement of Fig. 9, it is possible to combine the left and right data outputs of the last randomization stage 76 and provide the sole resultant 32-bit data as randomized data. The reason for feeding the constant +1 for addition to the addition/modulo operation circuits 33 and 39 in Figs. 4 and 5 is that unless the constant +1 is added, such a deficiency may occur that when the input data R and parameter data are both zero, the output data is also zero, that is, the input and output data coincide. This is undesired where the data randomization equipment is used for a cryptographic equipment. The deficiency is avoided by the addition of the constant. For this reason, the constant need not be +1 and may be a different number. The addition of the constant is unnecessary where the data randomization equipment is not used for any cryptographic equipment but is employed merely for data randomization. The individual circuits, parts and stages described in the foregoing may be implemented by hardware, or their processes may be partly or totally realized using an electronic computer. With the embodiments (Figs. 4 and 5) a one-bit change in the input data leads to a change of 11 bits of the output data in average, whereas with the prior art equipment the same input data change leads to only a change in 4 bits of the output in average. By substituting the data randomization equipment according to the invention for the data randomization equipment of the prior art DES cryptographic equipment, the encryption stages necessary for the saturation of the data randomization may be reduced from five stages to two to three stages.

Claims: A data randomization equipment comprising splitting means (67, 80 - 82) for splitting input data into left and right data having an equal data length, and a cascade connection of a plurality of randomization stages (76), wherein said left and right data are fed to said cascade connection, in each of said randomization stages (76) the right data input is fed as left data input to the next randomization stage (76) while the right data input is subjected in a first function operation means (77) provided in each randomization stage (76) to a function operation to produce parameter data which is used for randomization of the left input data in a randomization means (78) provided in each randomization stage (76) to obtain randomized data to be fed as right data input to the next randomization stage, characterized in that said first function operation means (77) in each randomization stage (76) performs function operation between the right data input to said randomization stage (76) and the left data input to the preceding one of the randomization stages (76), to obtain said parameter data. The data randomization equipment according to claim 1 wherein each data obtained from said randomizing means (78) in each of said randomization stages (76) is provided as randomized output data. The data randomization equipment according to claim 2, which comprises further splitting means (81, 82) for splitting the left and right data from said splitting means (80) into first to fourth data having an equal data length, left and right randomizing means (84, 85) for randomizing said respective first and third data with said respective second and fourth data as parameter data to provide randomized data, respectively, right function operation means (86) for performing a function operation on the output data of said left and right randomizing means (84, 85) to produce data fed as right data input to said first randomization stage (76), and left function operation means (83) for performing a function operation on said second and fourth data to produce data fed as left data input to said first randomization stage (76). The data randomization equipment according to one of claims 1 and 3 wherein said first function operation means (77) performs an exclusive OR operation on two data. A data randomization method comprising the steps of: (a) splitting input data into left and right data having an equal data length, and (b) feeding said left and right data to a cascade connection of a plurality of randomization stages (76), wherein in each of said randomization stages (76) the right data input is fed as left data input to the next randomization stage (76) while the right data input is subjected to a first function operation in each randomization stage (76) to produce parameter data which is used for randomization of the left input data by way of a randomization operation in each randomization stage (76) to obtain randomized data to be fed as right data input to the next randomization stage, characterized in that said first function operation is performed between the right data input to said randomization stage (76) and the left data input to the preceding one of the randomization stages (76) to obtain said parameter data. The data randomization method according to claim 5 wherein each data obtained by the randomization in each said randomization stage (76) is provided as randomized output data. The data randomization method according to claim 6, which comprises the further steps of (c) further splitting the left and right data obtained by step (a) into first to fourth data having an equal data length, (d) randomizing said respective first and third data with said respective second and fourth data as parameter data to provide first and second randomized data, respectively, (e) performing right function operation on the first and second randomized data to produce data fed as right data input to said first randomization stage (76), and (f) performing left function operation on said second and fourth data to produce data fed as left data input to said first randomization stage. The data randomization method according to one of claims 5 and 7 wherein said first function operation performs an exclusive OR operation on two data.

Inventors: MIYAGUCHI SHOJI, SHIMIZU AKIHIRO, MIYAGUCHI, SHOJI, SHIMIZU, AKIHIRO
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1986
Main classification: H04L9
IPC codes: H04L9