APPARATUS FOR INPUT/OUTPUT NOTIFICATION TO A PROCESSOR

Abstract: A method and apparatus for data transfer completion notification to a processor is presented. Input/output (I/O) devices individually or severally have associated with them command linked lists, located in system memory. In each com­ mand linked list a processor or memory controller has placed command elements. A subset of the command elements in­ cludes elements that are specifically to be used to report status of data transfers. Each command element in this subset of command elements includes a pointer which points to a status entry. Status entries, when updated by an I/O device, are placed in a status linked list also located in memory. An I/O device may have its own linked list or may share a single status linked list with several other devices. Status entries contain status information on transfers between an I/O device and memory locations. The insertion of status entries into a status linked list is done by hardware in an indivisible series of opera­ tions. Depending upon implementation, the hardware may then give asynchronous notification to the processor that a new element has been added to the second linked list. This notification will cause an interrupt to the currently running process in the processor.

Description: APPARATUS FOR INPUT/OUTPUT NOTIFICATION TO A PROCESSOR Background of the Invention The present invention concerns data transfer within a computer system. Typically, an Input/Output (I/O) device will notify a processor when the I/O device is ready to be serviced by the processor, for instance, after a data transfer to or from memory. Ordinarily, this notification is done by signals across special hardware lines. For instance an interrupt line may extend from each I/O device to a system processor. When one of the I/O devices is ready to be serviced it sends a signal across the interrupt line. The processor then can engage the appropriate software routines to service the I/O device. Typically, some form of prioritization is employed by the processor. The assignment of which priority level an I/O device has is fixed by hardware. The number of priority levels available is often chosen based on an analysis balancing the hardware expense of providing for each priority level, and the importance of the processor being able to distinguish levels of priority in order to more efficiently perform its tasks. If a processor is servicing an I/O device which has a high priority level, an I/O device with a lower priority level is typically not allowed to interrupt the processor. Therefore the processor must provide for the buffering or vueuing of interrupt fro the I/O devices, or the I/O device needs to contle e to notify the processor of its need fr service. Such a buffer#ro scheme done in hardware can be cuite c#rplex. Summary of the Invention In accordance with the preferred embodiment of the present invention a method and apparatus for data transfer completion notification to a processor is presented. Input/output (I/O) devices indiyidually or severally have associated with them command linked lists, located in system memory. In each a processor has placed command elements. Typically each element specifies the direction, length, and memory address for data transfer between the I/O device and memory locations. A subset of the command elements includes elements that ar specifically to be used to report status of data transfers. Each command element in this subset of command elements include a pointer which points to a status entry. Status entries, when updated by an I/O device, are placed in a status linked list al located in memory. An I/O device may have its own status linke list or may share a single status linked list with several othe devices. Generally I/O devices sharing a status linked list ar are at the same priority level as regards service by a processo Status entries contain status information on transfers between I/O device and memory locations. The insertion of status entry into a status linked list is done by hardware in an indivisible series of operations. Depending on the implementation, the hardware may then gile asynchronous notification to a control program within the processor that a new element has been added the second linked list. This notification will cause an interrupt to the currently running process in the processor. The present invention has various advantages over the prior art. The number of command linked lists and status linked lists is determined by software, and therefore can be easily varied. The I/O devices associated with each status linked list may be chosen on the basis of process association, priority of service, criticality of resources or by some other criterion or combination of criteria. The control program within the processor selects where on the command linked list the command elements used to report status are placed and which information is to be placed into status entries and so may use them to identify waiting processes and to monitor the status of processes on particular status lists. Furthermore, the control program has the option to receive no interrupts when a new status entry is placed into the status linked list, allowing the processor to control the times when I/O service will be done. Regardless, the status information is not lost but remains on the status linked list until the processor accesses them. Brief Description of the Drawings Figure 1 shows a block diagram of a processor and various I/O devices on a bus. Figure 2 shows a command linked list in accordance with the preferred embodiment of the present invention. Figure 3 shows a command element in accordance with the preferred embodiment of the present invention. Figure 4 shows a corz.ard ele:mer.t, a status entry ar. a linked list of status entries in accordance with the preferred erZc-iment of the present invention. Figure 5 shows a linked list of status entries in accordance with the preferred embodiment of the present invention. Figures 6A-6C show a status entry being added to the linked list of status entries in accordance with the preferred embodiment of the present invention. Description of the Preferred Embodiment In Figure 1, a simplified block diagram of a computer system is shown which includes a processor 11, an input/output (I/O) device 12, an I/O device 13, an I/O device 14, and a system memory 15 all coupled to a data transfer bus 16. I/O devices 12, 13, and 14 are all direct memory access (DMA) devices, i.e. they are able to transfer data to and from system memory 15. In Figure 2, a command linked list 20 composed of command elements 21, 22, 23, 24, 25, 26, and 27 is within system memory 15. In the preferred embodiment, each command element is shown to be four 32-bit words, as shown in Figure 3 and Figure 4. Command elements 21, 22, 23, 25, and 27 all have the same format In Figure 3, the format of command element 23 is given as a representative example. Command element 23 contains a 32-bit word 31, a 32-bit word 32, a 32-bit word 33, and a 32-bit word 34. Word 31 is a pointer, containing the memory address of command element 24, the next command element in linked list 20. Word 32 is an encoded command which instructs an I/O device as t which operation to perform, e.g., to write to memory or read frc memory. Word 33 is an address in system memory 15 to or from where data is to be transferred. Word 34 is a byte count wr.ic: tells the number of bytes of data to be transferred. In Figure 4, the format of command element 24 is given. Command element 24 is a special command element used to report status. Command element 24 contains a 32-bit word 41, a 32-bit word 42, a 32-bit word 43, and a 32-bit word 44. Word 41 is a pointer containing the memory address of command element 25, the next command element in linked list 20. Word--42 is an encoded command which instructs an I/O device as to which operation to perform. Word 43 is an address in system memory 15 of a head 60 of a status linked list 69. Status linked list 69 includes status entries 61, 62, and 64. Word 44 is the address of a new status entry 63 into which an I/O device will place status information and which will be inserted into status linked list 69. Processor 11 places command elements, such as command elements 21-27, on command linked list 20. Command elements 2127 control data transfers involving a single I/O device, for example I/O device 12. I/O device 12 proceeds through command linked list 20 performing the transfers designated by the command elements. When I/O device 12 comes to command element 24, it reads data in head 60, and places this and other various status infor-ation into new entry 63. New entry 63 can contain information as to whether I/O device 12 has detected any errors in transmission, and if so what type of errors they were. Also, I/O device 12 could load residual byte count into new entry 63. For example, Figure 5 shows a new entry 63 to include a 32bit wo 1, a 32-bit word 52, a 32-b. word 53 and a 32-b 54. into word 51 may be loaded the data in head 60 which is the address of status entry 62. Into word 52 may be loaded encoded status information. Word 53 may be undefined, unless an error occurs. If an error occurs then an identifier which identifies the command element active when the error occurred is loaded int word 43. Into word 54 maybe loaded amount ofobytes transferred or a residual bytr count. Status information within word 52 may include information regarding error termination. The status information may differentiate between different types of errors. For instance, there may be provision to encode three kinds of errors within word 52. The first kind signals that there was an incomplete data transfer. The number of bytes not transferred is containec in the residual count in word 54. The second kind of error indicates that there was a device error within a particular I/O device making a data transfer. A device error detected by an IX device while executing command elements is reported as a status to processor 11. For instance, if a device error is detected bs an I/O device while executing command elements 21, 22, or 23, t ] device error is reported as status in word 44 of command elemen 24. Detection of a device error causes an I/O device to cease processing executing command elements until a processor intervenes to restart data transactions to the I/O device. The third kind of error indicates there is a faulty electrical connection, for example, a bus across which data is sent may be defective. This is typically detected by parity checkinc. Whe an I/O device detects this type of error, it stops further data transactions in order to avoid further corruption of system memory 15. Processor 11 detects this type of error by polling status registers in each I/O device. Once values are loaded into new entry 63, new entry 63 is placed into status linked list 69. More than one I/O device may use a single status linked list. For example, both I/O device 12 and I/O device 13 may use status linked list 69. Figures 6A, 6B and 6C show one method to add new entry 63 into status linked list 69. Figure 6A shows status entry 63 ready to be entered into status linked list 69. I/O device 12 and I/O device 13 each place their own entries into status linked list 69. In order to avoid two I/O devices simultaneously adding status entries to status linked list 69, a semaphore may be used. For instance, as shown in Figure 7, head 60 may include a word 71 to be used as a semaphore, as well as a word 72 used to point to the next entry (in Figure 4 the next entry is shown to be status entry 62). For example, one method I/O device 12 could use in order to add status entry 63 to status linked list 69 might incorporate the following six steps. 1. I/O device 12 reads word 71 to detect if another entity (e.g., another I/O device or processor 11) is accessing status linked list 69. If another entity is accessing status linked list 69, I/O device 12 waits for a duration and repeats this step. 2. If linked list 69 is unaccessed, I/O device 12 alters the contents of word 71 to indicate that linked list 69 is now being accessed by I/O Device 12 (Steps 1 and 2 ar separate but successive bus transactions). 3. I/O device 12 reads the contents of word 72. 4. I/O device 12 updates status entry 63, updating word 51 with the value of word 72 which points to status entry 62 and loading other status information as is desirable. 5. Update word 72 to point to status entry 63. 6. Re-initialize contents of word 71 indicating links list is again unaccessed. Another method I/O device 12 might use in order to add status entry 63 to linked list 69 incorporates only the follow three steps: 1. I/O device 12 performs a "load and clear semaphore which reads and clears word 71 in a single bus trapsaction The contents of word 71 indicates to I/O device whether another entity (e.g., another I/O device or processor 11) accessing status linked list 69. If another entity is accessing status linked list 69, I/O device 12 waits for a duration and then tries again. Simultaneous to the foregoing, I/O device 12 reads the contents of word 72. 2. I/O device 12 updates status entry 63, updating word 51 with the value of word 72 which points to status entry 62 and loading other status information as is desirable. 3. Update word 72 to point to status entry 63, and simultaneously re-initialize the contents of word 71 indicating linked list is again unaccessed. On a bus which supports burst transfers of four word blocks, the latter method has fewer steps. It reduces the time taken for each I/O device to update status linked list 69, and therefore reduces conflicts between devices simultaneously desiring to access status linked list 69.

Claims: Claims We Claim: 1. A method for notifying a processor of the status of a data transfer, the method comprising: loading status information into a first section of memory; adding the first section of memory to a linked list; and, accessing the linked list with the processor. 2. A method as in claim 1 wherein the step of adding the first section of memory to a linked list comprises: reading and setting in a single computing cycle of the processor a semaphore within the first section of memory; updating a portion of the first section of memory to act as a pointer to a next entry in the linked list; and, updating a head of the linked list to point to the first section of memory and within the same computing cycle of the processor resetting the semaphore. 3. A method as in claim 1 additionally comprising the step of sending an interrupt to the processor after the step of adding the first section of memory to the linked list is completed. 4. An apparatus for notifying a processor of the status of data transfers between an I/O device and a memory comprising: locations in the memory reserved as status entries; means for loading information into status entries, wherein the information pertains to the status of data transfers; and, means for concatenating the status entries onto a first linked list. means for the apparatus to access the first linked list. 5. An apparatus as in claim 4 wherein the information loaded into the status entries includes error information which differentiates between types of errors. 6. An apparatus as in claim 5 wherein the types of errors include: an incomplete data transfer; a defect within the I/O device; and, a defect within a connection used to perform data transfers

Inventors: JAMES, DAVID V., LUIZ. FERNANDO A.
Applicants: HEWLETT-PACKARD COMPANY
Application year: 1986
Main classification: G06F13
IPC codes: G06F13