METHOD OF SMOOTHING THE SURFACE OF A CERAMIC SUBSTRATE

Abstract: A method of planarizing or smoothing the surface (30) of a ceramic substrate (20) by deposition of a silicon nitride layer (32). The silicon nitride in addition to planarizing the surface forms an alpha particle barrier. The substrates suitable for planari­ zation with silicon nitride in accordance with the method of the present invention are sintered oxide particles (22) which are bonded with a silicon bonding phase (24). The silicon content of the silicon bonding phase is greater than the silicon content of the aggre­ gate of the oxide particles. The silicon nitride is pre­ ferably deposited by plasma enhanced chemical vapor de­ position, and the silicon bonding phase is preferably a glass.

Description: This invention relates to a method of smoothing the surface of ceramic substrates, in particular to vapor deposition of silicon nitride onto the surface of ceramic substrates; and to the planarized ceramic substrates re­ sulting from such deposition of silicon nitride. Silicon nitride has been deposited onto semiconductor substrates and connection metallurgy to form conformal in­ sulating layers. For example, U.S. Patent No. 4,423,547 of Farrar et al. describes a method for providing high density multiple level metallurgy for integrated circuit devices by plasma spraying a thin layer of silicon nitride over a layer of interconnection metallurgy. This patent teaches a method for forming a passivating layer of sili­ con nitride. Vias can be etched in the silicon nitride layer and then a thick layer of a polyimide deposited. The deposition process of the patent produces a conformal silicon nitride layer and does not planarize the sub­ strate. Planarizing the surface of ceramic substrates has been done by mechanical methods including grinding, lapping and polishing. These methods are time consuming, expensive, and in addition can not readily be done on selected regions of the substrate. Glazing, which has been used to produce a planarized surface, like the mechanical methods listed above, is suited for planarizing the entire surface. Glasses used for glazing have low melting points and generally have elements added to depress the melting point such as cal­ cium, sodium and potassium. These added elements are re­ quired to bring the melting point of the glaze below the melting point of the substrate. The glasses may also con­ tain impurities such as lead, uranium and thorium. Since uranium and thorium are alpha emitters the glazing materials may be a source of alpha particles. In addition, glazing tends to form a surface with long wavelength vari­ ation and the edges of the glaze tend to round due to surface tension. Thus the usable planarized area re­ sulting from glazing is limited. An additional disadvan­ tage of glazes is that because of the brittle nature of the glasses used for glazing small cracks tend to pro­ pagate readily when the glazed surface is subject to stress such as may be encountered during fabrication. In addition the glazing process is inherently unsuitable for subsequent selective removal of the glaze. The glazing process is also difficult to control and extremely thick, in the order of 1 or more mils. It is an object of this invention to provide a method of planarizing a ceramic surface with silicon nitride. An object of this invention is to planarize the surface of ceramic substrates prior to metal deposition. Another object of the invention is to form an alpha barrier. It is still another object of this invention to pro­ vide a method which allows for selective planarization of a ceramic surface. Still a future object of this invention is to pro­ vide a planarized ceramic surface for subsequent depo­ sition of metal. A further object of the invention is to provide an alpha barrier which preferentially deposits over the glass phase of a ceramic substrate, the glass phase being an alpha particle emitter. The invention as claimed is intended to remedy the drawbacks encountered with hitherto known processes and to meet the objects of the invention. This is accomplished by chemical vapor deposition of silicon nitride onto a ceramic substrate. In a preferred embodiment, the deposi­ tion is by plasma enhanced chemical vapor deposition. Plasma enhanced chemical vapor deposition of silicon nitride can be used to planarize ceramic semiconductor substrates which are composed of oxides bonded with a silicon bearing bonding phase. Typical oxides used for the substrates are metal oxides such as aluminum oxide, beryllium oxide, zirconium oxide and magnesium oxide; and metal silicon oxides such as forsterite (Mg₂SiO₄), mullite (Al₆Si₂O₁₃), cordierite (Al₄Mg₂Si₅O₁₈) and Spinel (MgSi₂O₄) and mixtures thereof. In order to assure pre­ ferential deposition of silicon nitride onto the bonding phase it is preferred that the bonding phase have a sili­ con dioxide content of between about 70 wt/o and 95 wt/o, and in all cases that the silicon content of the bonding phase be greater than the silicon content of the aggregate of the oxide particles. The silicon bearing bonding phase may be a glass. The advantages offered by the invention are mainly that the thin silicon nitride layer provides for sub­ stantial smoothening of the substrate surface allowing finer metallization lines to be employed. At the same time, it serves as an alpha barrier blocking particles emitted by the substrate surface. Also, the silicon nitride can be patterned subsequent to its deposition onto the substrate permitting regional planarization and increased fabrication process flexibility. These and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings, in which Figure 1 is a schematic representation of one embodiment of the present invention and illustrates a pressed and sintered ceramic substrate onto which silicon nitride and connection metallurgy have been deposited. Figure 2 is a schematic representation of a sintered ceramic substrate illustrating the bonding of the oxide particles by a glass bonding phase, and the distribution of silicon nitride which has been deposited by the method of the present invention. Figure 3 is a schematic representation of a ceramic sub­ strate that has embedded therein a metallic conductive channel. Silicon nitride has been deposited in accordance with the method of the present invention and a hole has been etched through the silicon nitride to expose the metallic conductive channel. Figure 1 is a schematic representation of one embodi­ ment of the present invention illustrating a ceramic sub­ strate 2 composed of oxide particles which are bonded with a silicon bearing glass. Since some oxides, for example aluminum oxide, can contain impurities such as uranium which is an alpha emitter, oxides with low levels of alpha emitting contaminants are preferred. A hole 4 is provided which passes through the substrate 2. An I/O pin 6 is placed through the hole 4. Silicon nitride 8 is de­ posited onto the surface 10 of the substrate 2 prior to positioning of the I/O pin 6. Metallurgical structure 12 is deposited on the silicon nitride 8 and connected to the I/O pin 6 by lithographic techniques. Figure 2 is a schematic representation showing details of the structure of a ceramic substrate 20. The ceramic substrate 20 is composed of oxide particles 22 which are bonded by a glass phase 24. The glass phase 24 is preferentially located at junctions 26 of the oxide particles 22. The surface junctions 28 form the low points on the surface 30 of the ceramic substrate 20. The sili­ con bearing glass frequently contains impurities such as lead, uranium and thorium, with uranium and thorium being alpha particle emitters. Thus the surface junctions 28 may be preferential sources of alpha emission. The surface junctions 28 are associated with relatively large exposed surfaces of the oxide particles 22. Thus the surface junctions 28 may be sites of additional alpha emissions if the oxide particles contain alpha emitters. When silicon nitride 32 is deposited onto the ceramic substrate 20 the silicon nitride preferentially deposits onto the silicon bearing glass phase 24 located at the surface junctions 28. It is preferred that the substrate 20 be composed of metal oxide particles such as aluminum oxide, beryllium oxide, magnesium oxide, zirconium oxide and/or mixtures thereof bonded with a silicon bearing glass. It is further preferred that the silicon dioxide content of the silicon bearing glass be approximately 70 wt/o to 95 wt/o and that the silicon be limited to the glass phase. Having silicon only in the glass phase maximizes the preferential deposition of the silicon nitride layer 8 onto the glass phase. It is further preferred that plasma enhanced chemical vapor deposition be employed for depositing the silicon nitride. Plasma enhanced chemical vapor deposition is pre­ ferred since lower deposition temperatures can be employed while assuring enhanced preferential filling of the junction 28 on the surface 30 of the ceramic sub­ strate 20. The preferential filling of the low points adjoining the surface junctions 28 on the surface 30 re­ sults in planarizing the surface. As a result of the preferential filling of the low points of the surface 30 by silicon nitride, portions 34 of the oxide particles 22 on the surface remain exposed. It is preferred that the mean thickness of the silicon nitride deposited on the surface 30 be less than the mean depth d of the low points adjoining the surface junctions 28 since this assures that regions 34 of the particles 22 will remain exposed. The exposed regions 34 of the oxide particles 22 provide sites for the attachment of the conductive metallurgy deposited subsequent to the depo­ sition of the silicon nitride. The deposition of silicon nitride onto the surface 30 of the substrate 20 can be indexed by co-depositing silicon nitride onto a silicon wafer and measuring the thickness of the coating depo­ sited on the silicon wafer. For typical ceramic sub­ strates which have a surface roughness, as indexed by centerline averages, of between about 0.625 microns and 1.25 microns the thickness of the silicon nitride layer on a co-deposited silicon wafer should be between 1 and 4 microns, and it is preferred that the silicon nitride layer be at least 1.5 microns. In one preferred embodiment chromium is used as the first layer of connective metallurgy and a sintered aluminum oxide is employed for the substrate. The de­ posited chromium will form a chromium oxide which in turn reacts with exposed aluminum oxide particles. This reaction bonds the chromium layer to the ceramic sub­ strate. In addition to planarizing the surface, silicon nitride serves as an alpha particle barrier and blocks alpha particles emitted by surface junctions 28. The thickness of the alpha particle barrier will depend on the level of the alpha particle emissions. For typical ceramic substrates a silicon nitride layer having a thick­ ness of between about 1.5 and 4 microns will serve as an effective alpha barrier. Another advantage of using silicon nitride to planarize the ceramic substrate is that the silicon nitride layer can be patterned subsequent to deposition onto the substrate. A mask can be overlayed on the sili­ con nitride leaving regions of the silicon nitride ex­ posed which can be removed by etching and in this manner the substrate can be regionally planarized. Regional planarization can not be readily accomplished by either mechanical techniques or glazing. Furthermore, since glazing materials frequently contain impurities which emit alpha particles, when the surface is planarized by glazing the surface may become an alpha particle emitter. The silicon nitride of the present invention serves as an alpha barrier. Figure 3 shows a schematic representation of ceramic substrate 40 having a metallic conductor 42 which passes through the substrate 40. When the sur­ face 44 of the substrate 40 is planarized with silicon nitride 46 the metallic conductor 42 will have silicon nitride deposited thereon. After deposition of the sili­ con nitride 46 a plasma etch can be used to remove sili­ con nitride from the regions 48 on the metallic conductor 42 before connection metallurgy is deposited. The use of silicon nitride for planarizing provides for a smoother surface and allows finer metallic lines to be employed. The following examples are given to illu­ strate the benefits from planarizing by deposition of silicon nitride onto a ceramic substrate. EXAMPLE 1 Silicon nitride was deposited onto an aluminum oxide substrate having about 4 wt/o of a silicon bearing glass bonding phase. The glass bonding phase was approximately 95 wt/o silicon dioxide. The substrate had an average surface finish of 0.875 microns and an average peak to valley depth of 7.4 microns. The silicon nitride was de­ posited to an average depth of 1.5 microns wich corres­ ponded to a 1.5 micron layer co-deposited onto a silicon wafer. The silicon nitride was applied by plasma en­ hanced chemical vapor deposition. Prior to deposition the substrate was preheated to 375°C in a tube furnace having a 15 cm diameter and a length of 1.5 m. The fur­ nace was maintained at a pressure of between 250 and 500 Pa. Silane and ammonia gases were fed into the chamber at the rates of 350 cm³/min and 3500 cm³/min respectively. An RF power of 125 watts was applied. The deposition time was approximately 90 minutes. After coating the average surface finish was 0.275 microns and the average peak to valley depth was 3.3 microns. This represents a 68% and a 55% reduction, respectively, in surface roughness characteristics. EXAMPLE II A metallic structure was deposited onto an aluminum oxide substrate having about 4 wt/o a silicon bearing glass bonding phase. The glass bonding phase was approximately 95 wt/o silicon dioxide. The substrate was coated with a chromium adhesive layer, a copper and a second chromium layer. The substrate had an average surface finish of 0.625 microns and an average peak to valley depth of 6.075 to 6.2 microns. The three layer metallized structure of chromium, copper and chromium had thicknesses of about 80 nm, 800 nm and 300 to 600 nm respectively. The base pressure in the sputtering chamber was 250 x 10⁻⁶ Pa with an argon pressure of 10 microns at 130 sccm. The substrate was preheated to 300°C for 20 minutes prior to sputtering. The target power for the chromium deposition was 600 Watts DC with a substrate bias of 0 V. The target power for the copper deposition was 11 KW DC with a substrate bias of 0 V. After sputtering the combined thickness of the deposited metal layer was 8.5 microns, the surface finish was 0.6 microns, and the peak to valley depth was 5.725 to 5.975 microns. Example I illustrates the smoothing effect resulting from depositing silicon nitride onto a ceramic substrate, while Example II illustrates that the use of a metallizing structure is ineffective in smoothing a ceramic substrate even when the deposited layer is relatively thick. While the novel features of this invention have been described in terms of preferred embodiments and particu­ lar applications, it will be appreciated that various omissions and substitutions in form of the present in­ vention may be made by those skilled in the art without departing from the spirit of the invention.

Claims: 1. A method of smoothing the surface of a ceramic sub­ strate comprising the steps of: providing a ceramic substrate (2, 20) of oxides bonded with a silicon bearing phase; and chemical vapor depositing silicon nitride (18,32) onto a major surface (10,30) of said ceramic sub­ strate (2,20) thereby preferentially depositing said silicon nitride onto said silicon bearing bonding phase (24). 2. The method of claim 1 wherein said silicon nitride (8,32) is deposited by plasma enhanced chemical vapor de­ position. 3. The method of claim 1 comprising the additional step of patterning the silicon nitride subsequent to deposition onto the substrate. 4. The method of claim 1 wherein said silicon nitride is sufficient to form an alpha barrier. 5. The method of claim 1 comprising the additional step of co-depositing silicon nitride onto a silicon wafer, said deposition being for a time sufficient to deposit a layer onto said silicon wafer of between about 1.5 and 4 microns. 6. The method of claim 1 wherein the ceramic substrate is comprised of oxide particles selected from the group consisting of beryllium oxide, aluminum oxide, magnesium oxide, zirconium oxide, forsterite, spinel, cordierite, mullite and mixtures thereof, such oxide particles being bonded with a silicon bearing bonding phase, said silicon bearing bonding phase having a silicon content greater than the silicon content of said oxide particles. 7. The method of claim 6 wherein said oxide particles are further restricted to the group consisting of beryllium oxide, aluminum oxide, magnesium oxide, zirconium oxide and mixtures thereof; and said silicon bearing bonding phase is a silicon bearing glass, said silicon bearing glass having a silicon dioxide content of between about 70wt/o and 95 wt/o. 8. A ceramic substrate comprising: a ceramic sheet (2,20) containing oxide particles (22) selected from the group consisting of alu­ minum oxide, beryllium oxide, magnesium oxide, zirconium oxide, cordierite, forsterite, mullite, spinel and mixtures thereof; said oxide particles being bonded with a silicon bearing phase (24); and a non-conformal overlay (32) of silicon nitride on said ceramic sheet. 9. The ceramic substrate of claim 8 wherein said silicon nitride covers selected regions of said ceramic sheet. 10. The ceramic substrate of claim 8 wherein the non-con­ formal overlay (32) of silicon nitride leaves portions (34) of said oxide particles (22) exposed. 11. A ceramic substrate of claim 8 wherein: said a ceramic sheet comprises by weigt approximately 96% aluminum oxide and 4% glass bonding phase; and said non-conformal overlay (32) of silicon nitride is applied by chemical vapor depo­ sition.

Inventors: ELIAS, KENNETH LAMBERT, MARTIN, STUART ROBB, SLATTERY, WILLIAM JOHN
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: C04B41
IPC codes: H05K3, C04B41, H05K1