SEMICONDUCTOR SUBSTRATE BIAS GENERATOR

Abstract: A semiconductor substrate bias generator is provided, which includes a charge pump having a series circuit (16) with first and second nodes (A, B) connected between the semiconductor substrate and a point of reference potential. A first voltage having a first phase is coupled to the first node (A) and a second voltage having a second phase is coupled to the second node (B). A field effect transistor (13) is connected between the substrate and the second node (B) and the control electrode of the transistor is connected to the first node (A). The series circuit includes first and second devices (T1, T2), preferably diodes, with the first device (T1) being connected between the first node (A) and the point of reference potential and the second device (T2) being connected between the first and second nodes (A, B).

Description: The invention relates to a semiconductor substrate bias generator comprising to charge pump integrated in the substrate. Substrate bias generators have been used extensively to enhance the performance of circuits employing N channel devices in integrated circuits formed in semiconductor substrates or chips. The substrate bias lowers junction capacitance between the source/drain diffusions and the substrate, reduces threshold variations due to source-to-substrate bias and may permit higher channel mobility due to a reduction in the threshold tailoring implant. More recently substrate bias generators have been used in complementary metal oxide semiconductor (CMOS) technology to minimize the latch-up problem. The desired bias voltage on a substrate can be provided simply by connecting the substrate to an external bias source or, alternatively, by incorporating into the semiconductor chip a circuit capable of generating a bias voltage having a magnitude within a preselected range of voltages derived from the circuit's voltage supply source. This latter approach to biasing the semiconductor substrate or chip is preferable to the use of separate external bias sources because it eliminates not only the need for additional outside or external power supplies but also an additional pad on the substrate or chip. Many circuits for producing a substrate bias voltage have been proposed, such as, e.g., the circuit disclosed in U.S. Patent 4 229 667, filed on August 23, 1978, by G.L. Heimbignor et.al., which includes a two phase system wherein charge is drawn from the substrate through a diode. A single phase generator which also utilizes a diode for transferring charge from the substrate is taught in U.S. Patent 4 378 506, filed on August 22, 1980, by S. Taira. This latter patent suggests that the devices of the generator may be either N channel devices or P channel devices. U.S. Patent 4 450 515, filed on June 14, 1982, also discloses a single phase generator having a diode through which charge is drawn from the substrate but additionally includes a field effect transistor interposed between the substrate and the diode which is controlled by an external or off-chip voltage source. U.S. Patent 4 403 158, filed on May 15, 1981, by W.C. Slemmer, discloses a substrate bias generator wherein charge from the substrate is drawn through a field effect transistor having somewhat complex control circuitry. It is an object of this invention to provide a highly efficient substrate bias generator having a simple circuit with minimal injection of minority carriers into the substrate, particularly for use in the CMOS technology to minimize the latch-up problem encountered therein. In accordance with the teachings of this invention, a substrate bias generator is provided which includes a charge pump having a series circuit with first and second nodes to which first and second out of phase voltages are applied, respectively, and wherein a field effect transistor is connected between the substrate and the first node and the control electrode of the transistor is connected to the second node. In a preferred embodiment, the series circuit further includes first and second diodes, with the first diode being connected between a point of reference potential and the second node and the second diode being connected between the first and second nodes. The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. Fig. 1 illustrates one embodiment of the substrate bias generator of the present invention which utilizes all N channel devices for providing a negative bias on a P type conductivity semiconductor substrate, Fig. 2 is a sectional view of a semiconductor substrate illustrating the formation therein of the generator shown in Fig. 1, Fig. 3 is a pulse program which may be used to operate the generator illustrated in Figs. 1 and 2, Fig. 4 illustrates a second embodiment of the substrate bias generator of the present invention which utilizes two P channel devices and one N channel device for providing a negative bias on a P type conductivity substrate, Fig. 5 is a sectional view of a semiconductor substrate illustrating the formation therein of the generator shown in Fig. 4, Fig. 6 illustrates a third embodiment of the substrate bias generator of the present invention which utilizes three P channel devices for providing a positive bias on an N type conductivity semiconductor substrate, Fig. 7 is a sectional view of a semiconductor substrate illustrating the formation therein of the generator shown in Fig. 6, Fig. 8 illustrates a fourth embodiment of the substrate bias generator of the present invention which utilizes two N channel devices and a P channel device for providing a positive bias on an N type conductivity substrate, and Fig. 9 is a sectional view of a semiconductor substrate illustrating the formation therein of the generator shown in Fig. 8. Referring to the drawings in more detail, there is illustrated in Fig. 1 one embodiment of the substrate bias generator of the present invention which includes an oscillator 10 having its output connected to a driver circuit 12 producing two out-of-phase voltages at terminals Q and for driving a charge pump 14. The charge pump 14 includes a series circuit 16 having field effect transistors T1, T2 and T3, with transistor T2 being connected to transistor T1 at node A and to transistor T3 at node B. The series circuit 16 is connected between a semiconductor substrate having a P type conductivity at a terminal S P and a point of reference potential such as ground. Transistor T1 is arranged as a diode by connecting its control electrode to node A and transistor T2 is also arranged as a diode by connecting its control electrode to node B. Transistor T3 has its control electrode also connected to node A, with its drain connected to terminal S P . Terminal Q of the driver circuit 12 is connected to node A through a first capacitor C1 and terminal of the driver circuit 12 is connected to node B through a second capacitor C2. The driver circuit 12 is controlled by a regulator 18 which is connected to the substrate terminal S P . It should be understood that the oscillator 10, the driver circuit 12 and the regulator 18 may be of any known type, with the driver preferably producing voltages from terminals Q and that are substantially 180° out of phase with each other. The voltage VH of the supply source for these circuits is typically +5 volts. In Fig. 2 of the drawings there is shown a sectional view of the transistors T1, T2 and T3 of the substrate bias generator of Fig. 1 formed in a semiconductor substrate 20 having a P type conductivity and preferably made of silicon. As indicated in Fig. 2, transistor T1 is an N channel transistor having an N+ source diffusion region 22 connected through a metallic film 24 to a point of reference potential such as ground and an N+ drain diffusion region 26 connected to its gate electrode 28 through a metallic film 30 which is at node A. Transistor T2 is also an N channel transistor which uses the N+ diffusion region 26 as its source and N+ diffusion region 32 as its drain, with a metallic film 34, which is at node B, connecting the drain region 32 to its control electrode 36. Transistor T3 likewise is an N channel transistor which uses the N+ diffusion region 32 as its source and N+ diffusion region 38 as its drain with a metallic film 40 connecting its control electrode to node A. A P+ diffusion region 42 having a metallic film 44, as substrate terminal S P contacted thereto and the N+ drain diffusion region 38 having a metallic film 46 contacted thereto are interconnected by any appropriate conductor 48. Insulating regions 50, preferably made of silicon dioxide, are provided to appropriately isolate the various elements of the circuit as is well known. The generator circuit of Figs. 1 and 2 operates to provide a negative bias voltage to the P type substrate 20 by using the pulse program indicated in Fig. 3 of the drawings. Basically, the out-of-phase voltages at terminals Q and alternately charge and discharge capacitors C1 and C2 and transistors T1, T2 and T3 are connected at nodes A and B so as to cause negative voltages to develop at nodes A and B with the resulting negative voltage at node B being completely transferred to the substrate 20 through transistor T3. Referring more specifically to the pulse program in Fig. 3, at time t1, the voltage on node A is driven negative as the voltage at terminal Q is reduced from +5 volts to 0 volts, while the voltage on node B begins to rise as the voltage at terminal goes to +5 volts. Since node B is more than a threshold voltage of transistor T2 higher than the voltage at node A, transistor T2 turns on, transferring negative charge from node A to node B. Transistor T3 remains off at time t1 since the voltage at node A is less than a threshold voltage above the voltage on substrate 20 and on node B. At time t2, i.e., at the beginning of the opposite phase of the cycle, the voltage at node A rises when the voltage at terminal Q goes to +5 volts, while the voltage on node B falls when the voltage at terminal goes to 0 volts. The voltage on node A rises to a threshold voltage above ground, where it is held by transistor T1. Meanwhile, since the voltage at node B is lower than the voltage at node A, transistor T2 turns off, however, with the voltage at node A being above ground, transistor T3 turns on fully to completely transfer charge from node B to the substrate 20 through substrate terminal S P . It can be seen that a similar cycle is repeated at times t3 and t4, and then another cycle starts at time t5. It should be noted that the voltage at node A swings between a maximum positive voltage V MAX of about one volt, i.e., the threshold voltage of transistor T1, except for overshooting effects, and a minimum voltage V MIN of about -4 volts, for a voltage supply source of +5 volts. The voltage at node B swings between a maximum of about -3 volts at time t1 to a minimum of about -8 volts at time t2. It should be noted that the maximum voltage of -3 volts at node B is equal to the minimum voltage at node A, i.e., -4 volts, plus the threshold voltage of transistor T2. Since the transistor T3 is turned on hard by connecting its control electrode to node A and since node B has a minimum or low voltage of -8 volts, it can be seen that the substrate 20 can be charged theoretically to a negative bias of approximately -8 volts. It should be understood that due to charge transfer losses, actual voltages may differ somewhat from the values set forth hereinabove, depending in part on the sizes of the capacitors C1 and C2. In addition, it should be noted that the substrate bias generator or circuit of the present invention is self-regulating due to the interaction of the voltage at node A and the voltage at substrate terminal S P . If the substrate voltage at terminal S P becomes lower, i.e., more negative, than a threshold voltage below the minimum voltage V MIN at node A, transistor T3 will remain on when node B is high, thus charge from the substrate 20 will leak back into node B to raise or make more positive the voltage on the substrate 20. Accordingly, the output of the substrate bias generator of the present invention is limited to V SX MIN = V A MIN - V t , where V SX MIN is the minimum or most negative voltage on the substrate 20, V A MIN is the most negative voltage at node A and V t is the threshold voltage of transistor T3. If a substrate bias voltage of a more positive magnitude is desired, a regulator 18 of any known type may be connected between the substrate terminal S P and the driver circuit 12. It can also be seen that since the transistor T3 is turned on hard by the voltage on node A all the charge on node B is transferred to terminal S P which prevents minority carrier injection from occurring into the substrate 20 from a forward biased P-N junction at the N+ diffusion region 32 of Fig. 2 or node B. While minority carrier injection has been eliminated at node B, injection may still occur on node A, i.e., diffusion region 26, though to a lesser extent. To eliminate the injection problem completely, the transistors T1 and T2 of the P channel type are used in the generator of Fig. 4 of the drawings. The generator or circuit of Fig. 4 is similar to that of Fig. 1 but differs therefrom primarily in that the charge pump 14' has the P channel transistors T1 and T2 formed in an N well 52, as shown in Fig. 5, which is biased to the supply voltage VH, e.g., to +5 volts. As in Fig. 1, node A will not rise to a voltage higher than the threshold voltage of transistor T1 due to its diode action and transistor T2 will turn on when node A goes more than a threshold voltage below the voltage at node B. Transistor T3 functions in the same manner as discussed hereinabove in connection with the circuit of Fig. 1. Since the voltage VH applied to the N well 52 is significantly more positive than any of the voltages applied to the P+ diffusion regions 56, 58 and 60 of the transistors T1 and T2, there is little or no likelihood of the P-N junctions between P+ regions 56, 58 and 60 and N well 52 being forward biased to produce minority carrier injection. Although the generators discussed hereinabove in connection with this invention have been described as providing a negative bias voltage to a P type conductivity semiconductor substrate, it should be understood that the generator or circuit of this invention may be modified to provide a positive bias voltage to an N type conductivity substrate. Referring to Figs. 6 and 7 of the drawings, the generator illustrated therein provides a positive bias voltage to the substrate terminal S N of an N type conductivity semiconductor substrate 20' having a magnitude greater than +VH. The charge pump 14" includes a series circuit 16 connected between the substrate terminal S N and the supply voltage +VH, with a sectional view of the transistors T1, T2 and T3 of the series circuit 16 being illustrated in Fig. 7 of the drawings, with transistors T1, T2 and T3 being of the P channel type. In the operation of the circuit illustrated in Figs. 6 and 7, a two phase pulse program similar to that in Fig. 3 still applies for the nodes Q and . Due to the arrangement of transistor T1 as a diode, the minimum voltage on node A is limited to a magnitude equal to VH minus the threshold voltage of transistor T1 during a first phase of the cycle, or about +4 volts. During a second phase of the cycle, the voltage on node A obtains a positive value equal to the magnitude at the minimum voltage plus the magnitude of the voltage swing on node Q, or about +9 volts. The maximum magnitude of node A is transferred through transistor T2 to node B on this second phase, causing node B to obtain a minimum value equal to the maximum value on node A minus the threshold voltage of transistor T2, or about +8 volts. The maximum voltage on node B of about 13 volts is transferred to the terminal S N on the first phase of the cycle, due to transistor T3 being driven fully on by the minimum voltage of Node A applied to the control node of transistor T3. Due to self regulation of this circuit, the voltage obtained on the N type conductivity substrate 20' will be somewhat less than the theoretical value of 13 volts, i.e., the maximum value of node A plus the threshold voltage of transistor T3. In the embodiment of Figs. 6 and 7, minority carrier injection may still occur on node A. To eliminate injection completely, a similar technique as was used in going from Fig. 1 to Fig. 4 is employed in the embodiment of Figs. 8 and 9. In the embodiment of the substrate bias generator of the present invention illustrated in Figs. 8 and 9, N channel devices T1 and T2 are formed in a P well 52' held at ground potential with a P channel transistor T3 formed in the N substrate 20', in order to provide a positive voltage on the N type conductivity substrate. Transistors T1, T2 and T3 function in the same manner as discussed hereinabove in connection with the circuit of Fig. 6. Since the voltage applied to the P well 52' is significantly less positive than voltages applied to N+ diffusion regions 56', 58' and 60' of the transistors T1 and T2, there is little or no likelihood of the P-N junctions between N+ regions 56', 58' and 60' and P well 52' being forward biased to produce minority carrier injection. It can be seen that in accordance with the teachings of this invention a self regulating, highly efficient substrate bias generator has been provided which utilizes a very simple circuit. The generator of this invention significantly reduces the minority carrier injection into the substrate which minimizes latch up concerns in CMOS circuits.

Claims: 1. A semiconductor substrate bias generator comprising a charge pump integrated in the substrate (20), characterized by a series circuit (16) having first and second nodes (A, B) connected between a point of reference potential and said substrate, a first source of potential (Q) having a first phase coupled to said first node (A), a second source of potential () having a second phase out of phase with said first phase coupled to said second node (B), and a field effect transistor (T3) having a source, a drain and a gate electrode, said transistor being connected at its source and drain between said substrate and said second node (B) and said gate electrode being connected to said first node (A). 2. The substrate bias generator as claimed in claim 1, characterized in that said series circuit includes a diode (T2) connected between said first and second nodes (A, B). 3. The substrate bias generator as claimed in claim 1 or 2, characterized in that the magnitude of the potential of said first phase being greater than that of said given potential during a given period of time, and the potential of said second phase having a magnitude sufficient to turn on said transistor (T3) during said given period of time. 4. The substrate bias generator as claimed in claims 1 to 3, characterized by comprising a first and second diodes, said first diode (T1) being disposed between said first node (A) and said point of reference potential and said second diode (T2) being disposed between said first and second nodes (A, B). 5. The substrate bias generator as set forth in claim 4, characterized in that said first diode (T1) includes a second field effect transistor and said second diode (T2) includes a third field effect transistor. 6. The substrate bias generator as claimed in claims 1 to 5, characterized in that a first capacitor (C1) is connected between said first source (Q) and said first node (A) and a second capacitor (C2) is connected between said second source and said second node (B).

Inventors: PIRO, RONALD ALAN
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: G05F3
IPC codes: H01L21, H03K19, H01L27, G05F3, G11C11