PLANAR HETEROJUNCTION AVALANCHE PHOTODIODE

Abstract: The planar heterojunction avalanche photodiode (APD) includes a first semiconductor layer of a first conductivity type for generating carriers by absorbing light and a second semiconductor layer of the first conductivity type for avalanche-multiplying the carrier injected from said first semiconductor layer, wherein the impurity concentration decreases with the distance from said first semiconductor layer and whose bandgap is greater than that of said first semiconductor layer. A first semiconductor region of a second conductivity type is diffused in said second semiconductor layer at a prescribed depth from the upper face of said second semiconductor layer and forms a stepwise p-n junction on the interface with said second semiconductor layer. A guard-ring of the second conductivity type is formed in said second semiconductor layer by ion implantation from the upper face of said second semiconductor layer to overlap the circumferential part of said first semiconductor region and forms a linearly graded p-n junction with said second semiconductor layer in a position closer to said first semiconductor layer than said stepwise p-n junction. This heterojunction APD with a guard-ring is effectively protected from edge breakdown and permits further noise reduction.

Description: BACKGROUND OF THE INVENTION The present invention relates to a planar heterojunction avalanche photodiode having a guard ring. The development of an avalanche photodiode (APD) using an In 0.53 Ga 0.47 As semiconductor is under way for optical communications in the 1 to 1.6 micron wavelength region, where the transmission loss of optical fibers is relatively small. Such a heterojunction APD uses a heterojunction of In 0.53 Ga 0.47 As and InP, which permit lattice matching to each other. The InGaAs layer, whose bandgap is smaller, is used for light absorption, and either the electron or the positive hole carriers, generated therein by optical excitation, are transported to the p-n junction in the InP for avalanche multiplication. For this kind of APD, usually a planar structure is used, wherein a p⁺ region is selectively diffused in n-InP to form a stepwise p-n junction. However, there is the problem that, when a reverse bias is applied to the p-n junction, the electric field will most readily concentrate in the circumferential part of the diffused region, resulting in an earlier breakdown than in the p-n junction of the flat part of the diffused region, which is closer to the light receiving area. This phenomenon is known as edge breakdown; in order to prevent it there is proposed an arrangement in which the circumference of the diffused region is surrounded by a guard-ring of a linearly graded p-n junction, whose breakdown voltage is relatively high. T. Shirai et al. attempted to prevent edge breakdown by so forming a guard-ring that its linearly graded p-n junction front reaches the same depth as a stepwise p-n junction (T. Shirai et al., "InGaAs Avalanche Photodiodes for 1 µm Wavelength Region", ELECTRONIC LETTERS,7th July 1983, Vol. 19, No. 14, pp. 534 -535). However, while the depletion layer in a stepwise p-n junction, upon application of a reverse bias, grows unidirectionally into an n-conductivity region, that in a linearly graded p-n junction grows into both p- and n-conductive regions. In consequence, there arises the problem that a contour having a positive curvature emerges in the depletion layer resulting from the two p-n junctions, and an electric field concentrates on the positive curvature region to invite edge breakdown. T. Torikai et al. tried to prevent edge breakdown by forming the linearly graded p-n junction front of a guard ring in an even deeper position than the stepwise p-n junction (T. Torikai et al., "Low Noise and High Speed InP/InGaAsP/InGaAs Avalanche Photodiodes with Planar Structure Grown by Vapor Phase Epitaxy", 10th European Conference on Optical Communication, Stuttgart, Sept, 3-6, 1984, Conference Proceedings, pp. 220-221). However, since the guard ring of the linearly graded p-n junction in this structure is positioned close to the InGaAsP layer whose bandgap is smaller, it is susceptible to edge breakdown from the depletion layer's edge of the guard-ring's p-n junction, so that the front position of the linearly graded p-n junction requires critical control. The first semiconductor region made of InP has two layers with different impurity concentration. In the EP-A-159 544 (EPC Application No. 85103299.5) jointly filed with the present inventor, there is proposed an APD in which edge breakdown is prevented by providing two linearly graded p-n junctions and easing the curvature of the p-n junction depletion layer jointly formed by a stepwise p-n junction and the two linearly graded p-n junctions. This structure, however, requires a process to produce two guard-rings. Moreover, since it demands a highly precise exposure alignment of the outer guard-ring to the inner one, there are problems of difficult processing and lower element yield. Furthermore, in every one of the aforementioned prior art examples, the stepwise p⁺-n junction front is arranged in a high-concentration n-InP layer or at the interface between low-concentration n-InP and high-concentration n-InP layers, so that noise reduction is restricted. Electronics Letters, Vol. 17, No 22 (Oct,1981), pages 826 and 827 concerns an avalanche photodiode comprising a Be-implanted guard-ring which forms a linearly graded junction, whereas the active junction is an abrupt junction formed by a Cd diffused region. SUMMARY OF THE INVENTION An object of the present invention, therefore, is to provide a heterojunction APD with guard-ring, which is free from the disadvantages mentioned above and yet effectively protected from edge breakdown. Another object of the invention is to provide a heterojunction APD permitting further noise reduction. These objects are solved by the features of the claims. Thus according to the invention, the impurity distribution in the first semiconductor region decreases with distance from the first semiconductor layer (light absorbing layer) in a stepwise manner or alternatively continuously. According to the invention, the impurity concentration in the avalanche-multiplying layer gradually decreases with the distance from the light absorption layer. Therefore, the positive curvature of the guard-ring, formed by ion implanation followed by heat treatment, can be eased, so that a single guard-ring can raise the breakdown voltage of the guard-ring itself. Furthermore, since the stepwise p⁺-n junction front can be formed in a position of a medium impurity concentration region in the avalanche layer, the difference between the ionization rate of electrons and that of positive holes can be enlarged, resulting in a low-noise APD. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a cross-sectional view of a first preferred embodiment of the present invention; FIG. 2 is a chart showing the spatial gain distribution in the APD illustrated in FIG. 1; and FIG. 3 shows a cross-sectional view of a second preferred embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to FIG. 1, an APD comprises an n-InP buffer layer 2 (about 1 µm thick), an n⁻-In 0.53 Ga 0.47 As layer 3 (3.5 to 4.0 µm thick) of 3 to 5 x 10¹⁵ cm⁻³ in carrier concentration, and an InGaAsP layer 3' (about 1 µm thick) having a bandgap corresponding to a wavelength of 1.3 µm, successively grown over a sulphur-doped n⁺-InP substrate 1. An n-InP region 4 consists of an n-InP layer 41 (0.7 to 1.0 µm thick) of 3 to 4 x 10¹⁶ cm⁻³ in carrier concentration, an n⁻-InP layer 42 (about 1 µm thick) of 3 to 7 x 10¹⁵ cm⁻³ in carrier concentration, and an n⁻⁻-InP layer 43 (1 to 1.5 µm thick) of 1 to 2 x 10¹⁵ cm⁻³ in carrier concentration. Here the nInP buffer layer 2 is intended to prevent any defect or dislocation in the InP substrate 1 from reaching the layers 3 to 43 during the process of layer growth; the n⁻-InGaAs layer 3, to absorb light of 1 to 1.7 µm in wavelength and generate positive hole and electron carriers; the n-InGaAsP layer 3', to prevent the travelling delay of the positive hole carriers due to the valence electron band discontinuity between the InP layer 4 and the InGaAs layer 3; and the n-InP layers 41 and 42 are avalanche multiplying layers. In the central part of the n⁻⁻-InP layer 43 are a p⁺ type conductive region 5 (about 80 µm in diameter) selectively provided in a round or an oval shape as viewed from above and a guard-ring 5' (about 100 µm in outer diameter) provided in a ring shape around the circumference of the p⁺ region 5. A p-electrode 7 is provided in a ring shape through a surface-protective film 6 with a selectively opened window in the p⁺ type conductivity region 5, and an n-electrode 8 is formed all over the lower face of the substrate 1. The layers 2, 3, 3', 41, 42 and 43 were grown over the InP substrate 1, etched with a mixture of H₂SO₄, H₂O and H₂O₂ in a 3:1:1 ratio, by the hydride vapor phase epitaxial method in a reactor (not shown) combining an InP growth chamber, an InGaAsP growth chamber and an InGaAs growth chamber at a substrate temperature of 700°C. After the epitaxial layer growth, the guard-ring was formed by implanting beryllium ions in the following process. Beryllium was used because it lends itself to the formation of a p-n junction closest to linear grading. An SiO₂ film was formed to a thickness of about 1 µm over the layer 43 by the pyrolitic chemical vapor phase deposition method (thermal CVD method) at 370°C, and a window was selectively opened into said SiO₂ film with buffered fluoric acid solution by the use of an exposure mask for forming the guard-ring 5', on which a ring-shaped pattern was drawn by a usual light-exposure technique. After that, beryllium ions were implanted within an accelerating voltage range of 100 to 140 KV and at a dose of 5 x 10¹³ cm⁻². At this time, the beryllium ions were implanted into the InP crystals, exposed by the opening selectively bored into the SiO₂ film. In this stage, they were substantially evenly distributed within the window in the exposure mask and at a depth about 0.3 micron from the surface of the n⁻-InP layer 43. The SiO₂ film was removed by etching with the fluoric acid solution; then a phosphorated silica glass (PSG) layer was formed to a thickness of about 100 nm at 370°C by the thermal CVD method, and thermal treatment for activation and drive-in diffusion of the beryllium ions was conducted for about 20 minutes at 700°C, resulting in the formation of the guard-ring 5' in the illustrated shape. The lower the impurity concentration in the n-InP, the more extensive the diffusion of beryllium. Since the impurity concentration in the n-InP layer increases with the distance from the surface, the overall guard-ring shape had an eased positive curvature as illustrated. After that, cadmium was thermally diffused within the guard-ring 5' for 20 to 30 minutes at a temperature of 570°C through the PSG film, into which a circular window had been selectively opened by the use of an exposure mask, to so form the p⁺ type conductivity region 5 that the stepwise p⁺-n junction be positioned at the interface between the n⁻-InP layer 43 and the n⁻InP layer 42 or within the n⁻InP layer 42. Next, after said PSG film used for thermal diffusion was removed by etching with fluoric acid solution, the SiN surface-protective film 6 was plasma-deposited at 300°C to a thickness of 150 to 200 nm. After that, a window was opened over the p⁺ type conductive region 5 by the use of an exposure mask, on which a ring-shaped pattern had been drawn by a light-exposure technique, and the p-electrode 7 was formed by successively laying titanim, platinum and gold by the electron-bombardment evaporation method to thicknesses of 100 nm, 100 nm and 300 nm, respectively. Further, the n-electrode 8 of AuGe/Ni alloy was formed all over the lower face of the substrate by the resistive heating evaporation method to finish the APD. To check the breakdown voltage of the guard-ring, a wafer having the same epitaxial structure was used to separately form a linearly graded p-n junction by beryllium ion implantation simultaneously with the aforementioned process. The breakdown voltage of this linearly graded p-n junction ranged from 120 to 150 V. That of the finished APD element was within the range of 100 to 110 V, lower than the 120 to 150 V range of the guard-ring section. Accordingly, avalanche multiplication of carriers was sufficiently achieved at the stepwise p⁺-n junction corresponding to the light receiving region surrounded by the ring-shaped p-electrode 7. This condition is illustrated in FIG. 2, where reference numeral 10 represents a typical multiplication sensitivity distribution, revealing that the carrier multiplication is greater in the stepwise p⁺-n junction corresponding to the light receiving region than in the guard-ring section. Furthermore, the APD according to the present invention is much less susceptible to noise than any prior art APD. A low-noise APD can be realized by increasing the difference between electrons' ionization rate α and positive holes'β. In the avalanche multiplying layer InP, β is greater than α, so that noise can be reduced by enlarging the β/α ratio. Since the β/α ratio is a function of the electric field, and the lower the electric field, the greater the β/α ratio, noise can be reduced by lowering the electric field in the avalanche multiplying layer InP. The electric field is a function of the impurity concentration, and the lower the impurity concentration in the avalanche region, the lower the electric field, resulting in noise reduction. As the stepwise p⁺-n junction is positioned in the n-InP layer 42, having a medium impurity concentration, according to the invention, the excess noise factor (x-value) is expected to be somewhere between 0.5 and 0.6, representing a substantial improvement over the 0.7 to 0.8 of the prior art structure where the p⁺-n junction is positioned in a high impurity concentration layer. FIG. 3 shows a cross-sectional view of a second preferred embodiment of the present invention. The APD illustrated herein differs from the structure of FIG. 1 in that the impurity concentration of the n-InP layer 4 gradually decreases with the distance from the InGaAs light absorbing layer 3 and, consequently, in the shape of the guard-ring 5'. Since the two embodiments are alike in other respects, only these differences will be described in detail below. The n-InP layer 4 has an impurity concentration of about 5 x 10¹⁶ cm⁻³ on its interface with the InGaAsP intermediate layer and an impurity concentration of approximately 1 x 10¹⁵ cm⁻³ at the uppermost level of the epitaxial structure, and the impurity concentration in-between gradually and continuously decreases toward the upper surface. Beryllium ion implantation in the n-InP layer 4, which has this distribution of carrier concentration, in the same process as that for the first preferred embodiment, illustrated in FIG. 1, followed by heat treatment, results in the formation of a guard-ring, whose positive curvature is also eased according to the distribution of impurity concentration in the n-InP layer 4. The formation of the p⁺ type conductivity region 5 is also achieved under the same conditions as those for the first preferred embodiment, the stepwise p⁺-n junction being positioned in an InP region whose impurity concentration is 3 to 5 x 10¹⁵ cm⁻³. This preferred embodiment can be expected to give the same benefits as the first.

Claims: A planar heterojunction avalanche photodiode (APD) including: a first semiconductor layer (3) of a first conductivity type (n̅) for generating carriers by absorbing light; a first semiconductor region (4) of the first conductivity type overlying said first semiconductor layer (3) for avalanche-multiplying the carriers injected from said first semiconductor layer (3), the bandgap of said first semiconductor region (4) being greater than that of said first semiconductor layer (3); a second semiconductor region (5) of a second conductivity type, diffused in said first semiconductor region (4) at a prescribed depth from the upper face of said first semiconductor region (4) and forming a stepwise p-n junction on the interface with said first semiconductor layer region (4); and a guard-ring (5') of said second conductivity type, formed in said first semiconductor region (4) by ion implantation from the upper face of said first semiconductor region (4) and forming a linearly graded p-n junction with said first semiconductor region (4), characterized in that said first semiconductor region (4) has at least a lower semiconductor layer (41) overlying the first semiconductor layer (3), an intermediate layer (42) formed on said lower semiconductor layer (41) and an upper semiconductor layer (43) formed on said intermediate semiconductor layer (42), the impurity concentration of said upper semiconductor layer (43) is lower than that of said intermediate semiconductor layer (42) whose impurity concentration is lower than that of said lower semiconductor layer (41); and in that the stepwise p-n junction is located at the interface between the upper semiconductor layer (43) and the intermediate layer (42) or within this intermediate layer (42), the guard-ring (5') overlaps the circumferential part of the second semiconductor region (5), and the guard-ring (5') reaches said lower semiconductor layer (41) by extending through said upper and intermediate semiconductor layers (43 and 42, respectively). A planar heterojunction avalanche photodiode (APD) according to claim 1, characterized in that the impurity distribution in said first semiconductor region (4) decreases continuously with distance from said first semiconductor layer (3).

Inventors: TORIKAI, TOSHITAKA
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H01L31
IPC codes: H01L31