SAMPLE AND HOLD CIRCUIT

Abstract: A sample and hold circuit comprises a series circuit comprising an input switching element (17) an output switching element (19), and a hold circuit (22) connected between the connecting point of both switch­ ing elements (17, 19) and a reference potential, with floating capacitance. A switching element (25)which is made to conduct only for a short time immediately before conduction of said output switching element (19) is connected between the output of the output switching element (19) and the reference potential in order to discharge any charge in an amplifier (21) of a following circuit.

Description: This invention relates to a sample and hold circuit which may be used as a liquid crystal panel driving circuit or the like of a television receiver. Liquid crystal television receivers employing liquid crystal panels as display elements have been developed recently. To begin with, the outline of operation of such a liquid crystal television receiver is described below. Fig. 4 shows a general construction of a liquid crystal television receiver. Television signals sent from a broadcasting station are received by an antenna 1, and are converted in frequency by a tuner 2 to an intermediate frequency. The intermediate frequency signals are amplified and detected in signal processing circuit 3, and audio signals and video signals are obtained. The audio signals are delivered to a speaker 5 by way of an audio output circuit 4, while video signals are applied to a chroma stage 6 and a control unit 7. The chroma stage 6 comprises a chroma processing unit and chroma output unit, and the video signals are demodulated into R, G, B signals in the chroma processing unit, and are converted into signals inverted in the polarity in every field by the chroma output unit to be applied to a Y driver IC 9. The video signals applied to the Y driver IC 9 are sample-held, and are applied to the source line of an active matrix liquid crystal panel 8. At the same time, the video signals fed to the control unit 7, in which various control pulses are obtained, are applied to the control signal input terminals of X driver IC 10 and Y driver IC 9. The X driver IC 10 is intended to scan in the vertical direction, and its output is applied to the gate line of active matrix liquid crystal panel 8. Thus, by the vertical direction scanning pulses from the X driver IC 10 and video signals from the Y driver IC 9, a television picture is obtained on the active matrix liquid crystal panel 8. Referring now to the outline of operation of Y driver IC 9 shown in Fig. 4, an example of composition of Y driver IC is shown in Fig. 5. The R, G, B signals from the chroma stage are applied to R, G, B terminals, and are changed over in every horizontal period by an analog multiplexer 11 to be led into three video signal lines 12. The analog multiplexer 11 changes over according to the R, G, B picture element arrangement on the liquid crystal panel. Numeral 13 denotes a shift register, which receives clock ø Y and start pulse S, and delivers sampling pulses Q₁, Q₂ and so forth sequentially. Numeral 14 denotes a sample and hold circuit and operational amplifier, which are designed to sample the video signals from the video signal line 12 according to the sample pulses Q₁, Q₂ and so forth from the shift register, and hold them according to the pulses G₁, G₂ applied from outside. The outputs of the sample and hold circuit and operational amplifier 14 are connected to output terminals Y₀₁, Y₀₂, ..... of the Y driver IC and these output terminals are connected to the source line of the active matrix liquid crystal panel. The sample and hold circuit and one (the n-th) of the operational amplifiers in Fig. 5 are shown in Fig. 6, in which numeral 15 denotes a video signal line, and 16 to 20 are switching circuits which operate to turn on when the pulse of the signal indicated by each arrow is high level, and turn off when it is low level. Numeral 16 is a switching circuit for video signal sampling, and its output is applied to two input switching circuits 17, 18, and hold capacitors 22, 23 are connected to output switching circuits 19, 20 are connected to the output terminals of input switching circuit, while output terminals of hold capacitors. Output terminals of these two output switching circuits are mutually coupled together, and are connected to the input terminal of operational amplifier 21 having an input capacitance 24, and the output of operational amplifier becomes output Y 0n of Y driver IC, and is connected to the source line of liquid crystal panel. In thus composed sample and hold circuit, the operation is as described below. Waveforms of the sample and hold circuit and individual parts of operational amplifiers in Fig. 6 are shown in Fig. 7, in which V is a video signal applied to the video signal line 15, and one horizontal period is represented by H. G₁, G₂ are control pulses applied to switching circuits 17 to 20 of sample hold, and the period of both G₁ and G₂ is 2H, and their phases are mutually deviated by π. In order to perform the sample hold securely, there is a period t in which both G₁ and G₂ are off. The period in which either G₁ or G₂ is on is indicated by t₁, t₂, ..... Q n is an n-th output pulse of shift register 13, and it is a video signal sampling pulse to open or close the switching circuit 16. V na and V nb are voltage waveforms applied to hold capacitors 22, 23 and Y 0n is an n-th output waveform of Y driver IC. In the period t₁, G₂ is on and G₁ is off, so that the information V na of hold capacitor 22 is transmitted to the output Y 0n of Y driver IC, and video information V nb is sampled in the hold capacitor 23 by the sampling pulse of Q n . Next, in the period of t₂, when G₁ is on and G₂ is off, the information of V nb which has been sampled in t₁ period is transmitted to the output Y 0n of Y driver IC, while the video information V na is sampled in the hold capacitor 22 by the sampling pulse of Q n . Thereafter, in the period of t₃, t₄ and so forth, the operations in the period of t₁, t₂ are similarly repeated. This arrangement, however, has the following problem. That is, the input capacitance 24 is always present at the input side of operational amplifier 21, and when the operational amplifier is composed of CMOS, in particular, the value of input capacitance is considerably large. As compared with the valued of hold capacitors 22, 23, the value of input capacitance 24 of operational amplifier is generally too great to be ignored, and, therefore, when the output side switching circuits 19, 20 are turned on, the voltage being held by the hold capacitors 22, 23 is influenced by the electric charge 1H before as being accumulated in the input capacitance 24 of the operational amplifier 21 in the output Y 0n of Y driver IC, so that the input voltage may not be delivered at high fidelity. In the example shown in Fig. 7, the value of Y 0n in t₂ period, which should be the voltage of the same level as in period t₁ as indicated by dot-dash line, is actually an upward shifted output voltage due to the effect of the operational amplifier input voltage in period t₁. The above operation is explained in relation to a two branch construction of a sample and hold circuit, but the same holds true in a series connected one branch construction of a sample and hold circuit. Hence, the problem is, when the conventional sample and hold circuit and operational amplifier as shown in Fig. 6 are used, for example, in a liquid crystal televison, brightness changes occur where the brightness should be the same. In the light of the above-discussed problem, this invention is intended to present a sample and hold circuit which is capable of eliminating the adverse effects of the capacitance component if a capacitance component is present at the output side. US patent no. 4366456 (Ueno et al) describes a signal convertor adapted to output so-called 100% sample and hold signals, VS₁₀₀, to a switched capacitor filter. This signal converter may comprise an input switching element having an input terminal for receiving the input signal VS" in , a hold capacitor connected between an output terminal of said input switching element and a reference potential, and an output switching element connected to the output terminal of the input switching element (see Fig. 8 and Fig. 10). The signal converter of the Ueno et al patent is adapted to eliminate the gaps (non-holding terms) which occur in the input signal thereof by the provision of additional sets of input switching element-hold capacitor-output switching element assemblies, connected in parallel with the first, and adapted so that the hold capacitors thereof successively discharge to the output during the gaps in the input signal. The present invention provides a sample and hold circuit comprising: an input switching element for sampling an input signal; a hold capacitor connected between an output terminal of the input switching element and a reference potential; and an output switching element connected to an output terminal of said input switching element; said input switching element and said output switching element being adapted to conduct alternatively, characterized in that: a discharge switching element is connected between the output terminal of said output switching element and said reference potential; and said discharge switching element is adapted to conduct for a short period immediately before said output switching element conducts whereby to discharge the capacitance of an output element connected, in use, to the output terminal of the output switching element so as to return its output potential to said reference potential. This invention, having the above construction, can discharge the electric charge of the capacity component accumulated so far, by means of the switching element for discharge, immediately before the output from the hold capacity is applied to the capacity component of the output side, and can return the output potential to the reference potential so that the next hold voltage may be accurately delivered regardless of the previous output signal value. Features and advantages of the present invention will become more readily apparent from the following description of an embodiment thereof given by way of example with reference to the accompanying drawings in which:- Fig. 1 is a circuit diagram of the sample and hold circuit in accordance with one embodiment of this invention; Fig. 2 is a waveform diagram showing the waveforms of parts of the circuit shown in Fig. 1; Fig. 3 is a circuit diagram showing a practical example of the circuit shown in Fig. 1; Fig. 4 is a block diagram showing a general construction of a liquid crystal television receiver; Fig. 5 is a block diagram showing an example of Y driver IC construction; Fig. 6 is a circuit diagram of a conventional example of a sample and hold circuit; and Fig. 7 is a waveform diagram showing waveforms of parts of the same circuit. One of the embodiments of a sample and hold circuit of this invention is described below while referring to the accompanying drawings. Fig. 1 shows the construction of a sample and hold circuit in the embodiment of this invention, in which numerals 15 to 24 corresponds to the parts of the conventional construction shown in Fig. 6. In this invention, a switching circuit 25 which is turned on and off by P pulse is installed between the output side of the sample and hold circuit and reference potential. The operation of such a sample and hold circuit is explained below by referring to Fig. 1 and Fig. 2. Fig. 2 shows the waveforms of various parts of the sample hold circuit in Fig. 1, in which a P pulse which is applied immediately before G₁ or G₂ is turned on so as to discharge the electric charge accumulated in the capacity component 24. That is, since the output Y 0n of the Y driver IC is returned to the reference potential when the P pulse is turned on, the voltage is always proportional to the sampled video signal regardless of the effect of the hold voltage 1H before. Therefore, as shown in Fig. 7 there is no step difference in the Y 0n value between t₂ period and t₃ period, and the voltage of same level is obtained. Thus, in this embodiment, by installing a switching element which conducts immediately before the switching element for output conducts, between the output circuit side of sample hold circuit and the reference potential, a sample and hold circuit capable of delivering outputs always correctly corresponding to the input video signals without being influenced by the video signal level 1H before may be realized. The embodiment of this invention is shown in Fig. 3, in which each switching element is composed of parallel circuits of p-channel MOS and n-channel MOS. Q n , G ₁, G ₂, P represent the polarity inverted pulses of Q n , G₁, G₂, P respectively. When the operational amplifier 21 is composed of aluminium bate CMOS, its input capacity 24 is about 0.4 to 1pF. On the other hand, since the value of hold capacitors 22, 23 are several pF, effects of video signal level 1H before may be present about 10 to 20% if there is no switching element 25. The above explanation relates to two-branch construction of sample and hold circuit, but the same holds true with one-branch series connected construction. When this embodiment is applied in a liquid crystal television, it will be very effective. Thus, by this invention, by installing a switching element which conducts immediately before the switching element for output conducts between the output circuit side of a sample and hold circuit and reference potential, a sample and hold circuit capable of delivering outputs always correctly corresponding to the input video signal without being influenced by the video signal level 1H before may be realized.

Claims: A sample and hold circuit comprising: an input switching element (17) for sampling an input signal; a hold capacitor (22) connected between an output terminal of the input switching element (17) and a reference potential; and an output switching element (19) connected to an output terminal of said input switching element; said input switching element (17) and said output switching element (19) being adapted to conduct alternatively, characterized in that: a discharge switching element (25) is connected between the output terminal of said output switching element (19) and said reference potential; and said discharge switching element (25) is adapted to conduct for a short period immediately before said output switching element (19) conducts whereby to discharge the capacitance of an output element connected, in use, to the output terminal of the output switching element (19) so as to return its output potential to said reference potential. A sample and hold circuit as set forth in claim 1, wherein pairs of said input switching elements (17, 18) and output switching elements (19, 20) and said hold capacitors (22, 23) are provided, and wherein said pairs of input switching elements (17, 18) and output switching elements (19, 20) are alternatively switched. A sample and hold circuit as set forth in claim 1 or 2, wherein said input signal is a video signal, and said input (17, 18) and output (19, 20) switching elements are switched during one horizontal period of said video signal, Apparatus comprising: a sample and hold circuit comprising an input switching element (17) for sampling an input signal, a hold capacitor (22) connected between an output terminal of the input switching element (17) and a reference potential, an output switching element (19) connected to an output terminal of said input switching element (17), and an amplifier circuit (21) having an input capacitance; wherein the amplifier circuit is connected to the output terminal of said output switching element (19) of the sample and hold circuit such that the input capacitance of said amplifier circuit (21) is present at the output side of said output switching element (19); said input switching element (17) and said output switching element (19) of the sample and hold circuit being adapted to conduct alternatively, characterized in that: a discharge switching element (25) is connected between an output terminal of said output switching element (19) and said reference potential; and said discharge switching element (25) of the sample and hold circuit is adapted to conduct for a short period immediately before said output switching element (19) conducts whereby to discharge said capacitance so as to return its output potential to said reference potential. Apparatus as set forth in claim 4, wherein the amplifier circuit is a MOS-type operational amplifier. Apparatus as set forth in claim 5, wherein pairs of said input switching elements (17, 18) and output switching elements (19, 20) and said hold capacitors (22, 23) are provided, and wherein said pairs of input switching elements (17, 18) and output switching elements (19, 20) are alternatively switched. Apparatus as set forth in claim 5, wherein said input signal is a video signal, and said input (17, 18) and output (19, 20) switching elements are switched during one horizontal period of said video signal.

Inventors: TAKAHASHI, KOUSHIRO
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1986
Main classification: G11C27
IPC codes: H03K7, G11C27, H04N5, G09G3