SEMICONDUCTOR MEMORY DEVICE HAVING A CIRCUIT FOR COMPENSATING FOR DISCRIMINATING VOLTAGE VARIATIONS OF A MEMORY CELL

Abstract: A semiconductor memory device capable of compensa­ ting for variation in a discriminating voltage of a me­ mory cell comprising a memory cell (MC) and a gate cir­ cuit (Qs) for coupling the memory cell to a bit line (WL). The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit (Q5, Q6, Q4, Cps, Q7) precharges a bit line pair with the resultant precharge voltage (Vcc/2 + α) obtained by adding a compensating vol­ tage to a precharge voltage in the reset state. The compen­ sating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discrimina­ ting voltage when it is assumed that the parasitic capa­ citance is not present.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device having a circuit for compensating for variations in a discriminating voltage of a memory cell caused by a parasitic capacitance of a gate transistor of the memory cell upon activation thereof. 2. Description of the Related Art In a so-called dynamic semiconductor memory device having memory cells consisting of a capacitor and a gate transistor, the memory capacitor of each memory cell is connected to a bit line through the gate transistor, and a charging state of the capacitor is detected by a sense amplifier connected to the bit line to discriminate logic "0" or "1" of the memory cell. The ON/OFF operation of the gate transistor is performed via a word line. In this case, the word line may be capacitively coupled to the memory capacitor because of the parasitic capacitance of the gate transistor. If a word line voltage rises to enable the memory cell, the memory cell voltage is influenced by noise through the aforementioned parasitic capacitance and undesirably varies. As a result, the memory cell discriminating voltage i.e., threshold voltage for discriminating the logic "0" or "1" of the memory cell content, is deviated from an accurate intermediate value between logic "0" and logic "1" voltages. The margin for noise is reduced and a read error of the memory cell tends to occur. In order to solve this problem, in a conventional dynamic semiconductor memory device, a dummy transistor is formed in each memory cell to cancel the parasitic capacitance of the gate transistor by its own parasitic capacitance, hereby variations in discriminating voltage are prevented. However, if the dummy transistors are arranged in units of memory cells, the total number of dummy transistors is increased, and a large area is occupied by the dummy transistors in the memory device as a whole. As a result, the memory capacity of the semiconductor memory device per unit area is reduced. SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a semiconductor memory device having a compensating circuit for compensating for variations in a discriminating voltage of a memory cell caused by noise generated upon activation of a memory cell via a word line, without using a dummy transistor. In accordance with the present invention, there is provided a semiconductor memory device having a circuit for offsetting a variation in a discriminating voltage of a memory cell, due to a capacitive coupling Cc, comprising : a bit line pair consisting of first and second bit lines; a memory cell comprising a memory capacitor for storing data and a gate circuit capable of coupling the memory capacitor to the first bit line of the bit line pair; a word line, connected to the gate circuit, for energizing and deenergizing the gate circuit to control coupling and decoupling of the memory cell to and from the first bit line; a sense amplifier connected to said bit line pair, which sense amplifier being adapted to sense and amplify a voltage at the first bit line by using a precharge voltage of the second bit line as a reference voltage in an active state of the semiconductor memory device; and a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state of the semiconductor memory device. The precharge circuit precharges the bit line pair with a resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The resultant precharge voltage is raised to a value Vcc/2 + (Cc/Cs).Vwl, where Vcc is the power source voltage, Cs is the capacitance of the memory capacitor; and Vwl is the voltage change of the word line when it is switched from its inactive to its active state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by said capacitive coupling which exists between the word line and the storage node of the memory capacitor due to a parasitic capacitance Cc of the gate circuit in the active state. The precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the semiconductor memory device according to the present invention will now be described in detail with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a conventional memory device; Fig. 2 is a graph showing the relationship between a memory cell voltage and a signal level in the device of Fig. 1; Fig. 3 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention; Fig. 4 is a graph showing the relationship between a cell voltage Vcℓ of a memory cell and output signal magnitudes ΔV of the memory cell as a function of the cell voltage Vcℓ; Fig. 5 is a time chart for explaining the operation of the device in Fig. 4; and Fig. 6 is a circuit diagram of a semiconductor memory device according to another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS For easy and better understanding of the preferred embodiments, the problems in the prior art will first be explained in detail with reference to Figs. 1 and 2. Figure 1 is a circuit diagram showing conventional semiconductor memory device. Referring to Fig. 1, reference symbols BL and BL(b) denote bit lines; WL, a real word line; MC, a real memory cell; SA, a sense amplifier; Qd, a dummy transistor; and DWL, a dummy word line. The memory cell MC comprises a cell capacitor Cs for storing data and a gate transistor Qs for coupling the cell capacitor Cs to the bit line BL. Reference symbol PC denotes a cell plate of the cell capacitor Cs, which generates a constant voltage (Vcc/2). The sense amplifier SA is a known circuit consisting of transistors Q1, Q2, and Q3. Reference symbol Cc denotes a parasitic capacitance existing between the node and the corresponding word line in the memory cell so as to capacitively couple the node to the word line; and Cb, parasitic capacitances of the bit lines BL and BL(b). In the memory device of Fig. 1, the charged and discharged states of the capacitor Cs in the memory cell MC correspond to logic "1" and logic "0", respectively. If the memory cell is set at logic "1", a memory cell voltage Vcℓ is set to be a power source voltage Vcc. However, if the memory cell is set at logic "0", the memory cell voltage Vcℓ is set to be zero volt. The charging state of the cell capacitor Cs is detected by the sense amplifier SA, thereby reading out data from the memory cell. The above operation will be described in more detail below. When the memory device is reset, the bit lines BL and BL(b) are precharged at a voltage of Vcc/2, i.e., the accurately intermediate value between the logic "1" and "0" voltages. In the active mode wherein data is read out from the memory cell MC, a clock ₀ is supplied to the sense amplifier SA so that the sense amplifier SA is enabled. At the same time, the voltage at the word line WL rises to turn on the gate transistor Qs so that the cell capacitor Cs is connected to the bit line BL. The voltage at the bit line BL is slightly charged up or down with respect to Vcc/2 according to whether the cell capacitor Cs is charged or discharged. The change is detected and amplified by the sense amplifier SA, thereby reading out data from the memory cell. The sense amplifier SA uses the precharge voltage of Vcc/2 of the bit line BL(b) as a reference voltage Vrf and detects the change in voltage at the bit line BL. More specifically, if the memory cell MC is set at logic "1", the cell capacitor Cs is discharged to apply a discharge voltage to the bit line BL. In this case, the voltage at the bit line BL is slightly increased from Vcc/2. However, if the memory cell MC is set at logic "0", a charge is supplied from the bit line BL to the cell capacitor Cs so that a voltage at the bit line BL is slightly reduced. This change is detected by the sense amplifier SA using the reference voltage Vrf of Vcc/2. The relationship between the memory cell voltage Vcℓ of the memory cell MC when the data is stored and an output signal magnitude ΔV (i.e., a change in voltage at the bit line BL) of the memory cell MC when the data is read out will be described hereinafter. First, assuming that the memory cell MC does not have the parasitic capacitance Cc, the above relationship will be described. The output signal magnitude ΔV of the memory cell MC is calculated by equation (1) based on the rule of charge conservation indicating the fact that the charge before read access of the memory cell MC is equal to that after read access thereof: (Vcℓ - Vpc)Cs + Vb·Cb = (Vb + ΔV)Cb + (Vb + ΔV - Vpc)Cs (1) for Vb = Vcc/2 and Vpc = Vcc/2 where Cs: the capacitance of the memory capacitor Cs Cb: the capacitance of the bit lines BL and BL(b) Vcℓ: the memory cell voltage Vb: the precharge voltage on the bit lines BL and BL(b) Vpc: the cell plate voltage Vcc: the power source voltage Substitution of Vb = Vpc = Vcc/2 into equation (1) yields the following equation: Figure 2 is a graph showing the characteristics of equation (2) when the precharge voltage V b (i.e., the reference voltage for causing the sense amplifier SA to discriminate the logic "0" of the memory cell from the logic "1") on the bit lines BL and BL(b) is set to be Vcc/2. In the graph, the memory cell voltage Vcℓ is plotted along the abscissa, and the signal magnitude ΔV is plotted along the ordinate. A solid characteristic curve (a) represents the characteristics of equation (2). That is, a straight line with the following slope, x-intercept, and y-intercept is obtained: Slope: The y-intercept is a value of ΔV when the memory cell voltage Vcℓ is 0, that is, Y-intercept: The x-intercept is a value of the memory cell voltage Vcℓ when the signal magnitude ΔV is zero, that is, X-intercept: Vdsl = Vcℓ(ΔV = 0) = Vcc/2 (5) The x-intercept of the ΔV characteristic curve is the memory cell voltage Vcℓ as a threshold voltage for discriminating whether the content of the memory cell MC is logic "0" or "1" and is referred to as a discriminating voltage Vds of the memory cell MC. The voltage Vcc/2 as a half of a difference (normally Vcc) between the logic "0" and "1" voltages of the memory cell MC is used as the discriminating voltage Vds. If a memory cell voltage Vcℓ is higher than the discriminating voltage Vds, the corresponding cell is discriminated by the sense amplifier SA to be logic "1". Otherwise, the memory cell is discriminated to be logic "0", if the memory cell voltage Vcℓ is lower than the Vds. In this way, a maximum noise margin can be provided to reduce read errors of the memory cell MC. On the other hand, the parasitic capacitance Cc for capacitively coupling the memory capacitor Cs and the word line WL is present in the memory cell. Therefore, in practice, the characteristic curve of the signal magnitude ΔV is changed as follows. If a potential at the word line WL rises to read out the content of the memory cell, it is transmitted to the memory capacitor Cs through the parasitic capacitance Cc, whereby the memory cell voltage Vcℓ rises. Assuming that the voltage at the word line WL is increased from 0 V to Vwℓ, an increase in memory cell voltage Vcℓ is given as follows: Increase in Vcℓ = (Cc/Cs)Vwℓ (6) Therefore, an output signal magnitude ΔV appearing at the bit line BL under the presence of the coupling parasitic capacitance Cc is given by: since the memory cell voltage in the read mode is given as: Vcℓ + (Cc/Cs)Vwℓ Equation (7) is represented by a broken characteristic curve (b) in Fig. 2 i.e., a straight line with the following slope, and x- and y-intercepts: Y-intercept: X-intercept: Vds2 = Vcc/2 - (Cc/Cs)Vwℓ (9) Slope: The line (b) is obtained by simply parallel displacing the line (a). As is apparent from the characteristic curve (b) in Fig. 2, the discriminating voltage Vds of the memory cell MC is represented by equation (9) when the parasitic capacitance Cc is present. This discriminating voltage is lower by Cc·Vwℓ/Cs than the discriminating voltage Vds1 = Vcc/2 given no parasitic capacitance Cc. More specifically, since the memory cell voltage Vcℓ is increased, the discriminating voltage Vds is comparatively lower than the intermediate level to be biased. As a result, the operation margin is reduced and thus read errors tend to occur. In order to solve this problem, the dummy cell Qd is connected to the bit line BL to which the memory cell MC is connected, as shown in Fig. 1. When the word line is enabled, a voltage having a polarity opposite to that of the enabling voltage of the word line WL is applied to the dummy cell Qd through the dummy word line D, whereby the potential at the bit line BL is decreased by an increase caused by the parasitic capacitance Cc of the bit line BL, thereby cancelling the influence of the parasitic capacitance Cc. Since the dummy transistor Qd, however, must be arranged in units of memory cells, the total number of dummy transistors in the semiconductor memory device is increased and utilization efficiency of the area of the semiconductor memory cell as a whole is degraded. A preferred embodiment of the present invention will now be explained with reference to Figs. 3 through 5. The same reference numerals as in Fig. 1 denote the same parts in Fig. 3. Reference symbol Cps denotes a capacitor for supplying a compensating voltage to bit lines BL and BL(b); Q4, a gate transistor for charging the capacitor Cps in the active state; Q5 and Q6, gate transistors for shunting between the bit lines BL and BL(b) in the reset mode; and Q7, a gate transistor for supplying a charge of the capacitor Cps to the bit lines BL and BL(b) in the reset mode. Resistors R1 and R2 serve as voltage dividers for supplying a very-small current to the bit lines so as to prevent the precharge voltage on the bit lines BL and BL(b) from being decreased when the semiconductor memory device is reset for a long period of time, thereby maintaining the bit lines at a predetermined potential (Vcc/2 + α). The resistors R1 and R2 comprise high-impedance resistors. For better understanding of the preferred embodiment, the principle of operation of the present invention will be described with reference to Fig. 4. Figure 4 is a graph wherein the memory cell voltage Vcℓ of the memory cell MC is plotted along the abscissa and a precharged bit line voltage Vb is plotted along the ordinate. The characteristic curves in Fig. 4 represent the memory cell output signal magnitudes ΔV as a function of the memory cell voltages Vcℓ of the memory cell MC when the precharge voltage on the bit lines BL and BL(b) is set at 0, Vcc/2, and Vcc/2 + α. Solid lines (a)₁ , (a)₂ , and (a)₃ are memory cell signal magnitudes ΔV when the bit line precharge voltage Vb is set at 0, Vcc/2, and Vcc/2 + α under the condition that the parasitic capacitance Cc is not present. On the other hand, broken lines (b)₂ and (b)₃ are memory cell signal magnitudes ΔV when the bit line precharge voltage Vb is set at Vcc/2 and Vcc/2 + α under the condition that the parasitic capacitance Cc is actually present. A characteristic curve (c) is plotted along bit line voltage points where the signal magnitude ΔV becomes 0 for the memory cell voltage Vc, and is represented by a straight line with a slope m of 1. Assuming the characteristic curves (a)₂ and (b)₂ , they have the same characteristics as obtained in Fig. 2. Accordingly, although the discriminating voltage Vds is Vcc/2 when the parasitic capacitance Cc is not present, the voltage Vds is lower by x = (Cc/Cs)Vwℓ from Vcc/2 when the parasitic capacitance Cc is present. This implies the following fact. In order to set the discriminating voltage Vds to be Vcc/2 as an intermediate value between the logic "0" and "1" voltages when the parasitic capacitance Cc is present, the discriminating voltage Vds obtained without the parasitic capacitance Cc is set to be Vcc/2 + x. Then, if the parasitic capacitance Cc is present, the discriminating voltage Vds is lowered by x, i.e., is set to be Vcc/2. The value of the bit line precharge voltage Vb for setting the discriminating voltage Vds obtained without the parasitic capacitance Cc to be Vcc/2 + x is the value of the bit line precharge voltage Vb corresponding to the memory cell voltage Vcℓ = Vcc/2 + x in the characteristic curve (c). As a result, since the slope of the line (c) is 1 so that x = α, the bit line voltage Vb should be set to be If the parasitic capacitance Cc is present, the output signal magnitude ΔV is obtained according to the characteristic curve (b)₃. In this case, the discriminating voltage Vds of the memory cell MC is properly maintained at Vcc/2, thereby obtaining a maximum operating margin. According to the present invention, the reference voltage Vrf for discrimination by the sense amplifier is increased or decreased from the normal value (Vcc/2) by a value for compensating a variation α as an increase or decrease in memory cell voltage Vcℓ caused by the influence of the parasitic capacitance Cc upon activation of the bit and word lines. Therefore, the discriminating voltage Vds can be maintained at an optimal value. Referring back to Fig. 3, the operation of the circuit will be described. If the bit lines BL and BL(b) are active, one is set at logic "1" (Vcc), and the other is set at logic "0" (0 V). The capacitances Cb of the bit lines BL and BL(b) with respect to the ground are the same. In the reset mode wherein the data is not read out from the memory device, if the gate transistors Q5 and Q6 are turned on to short-circuit the bit lines BL and BL(b), the bit lines BL and BL(b) are precharged at Vcc/2. Upon the ON operation of the gate transistor Q7 in the reset mode, the capacitor Cps having charged by rising the active clock  a in the active state of the memory device is discharged to the bit lines BL and BL(b), whereby the precharge voltages of the bit lines can be set Vcc/2 + α higher than Vcc/2. An increment α can be adjusted by the capacitance of the capacitor Cps. The value of the capacitor Cps for setting the voltage increment to be α is given by the following equation according to the rule of charge conservation: 2(Cb·Vcc/2) + Vcc·Cps = (Vcc/2 + α)·(2Cb + Cps) (11) The capacitor Cps comprises a MOS capacitor so that all capacitors for all bits can be simultaneously formed. The occupying area of the MOS capacitors is smaller than that of the dummy cells described with reference to Fig. 1, and the MOS capacitors pose little fabrication problems. Figure 5 is a time chart for explaining the operation of the embodiment (Fig. 3) of the present invention. The same reference numerals as in Fig. 3 denote the same parts in Fig. 5. Referring to Fig. 5, reference symbol SA denotes a timing at which the sense amplifier SA is activated; and AP, an active pull-up timing. In Fig. 5, waveforms at the timing SA are denoted by an enlarged view, wherein BL and BL(b) are waveforms when the cell voltage is high and BL* and BL(b)* when the cell voltage is low. As is apparent from Fig. 5, an active clock signal  a is enabled in the active period to charge up the capacitor Cps to Vcc and is disabled in the reset time. After the active clock signal  a is enabled, a clock signal BC2 is enabled to shunt the bit lines so that the bit lines BL and BL(b) and the capacitor Cps are shunted to precharge the bit lines to Vcc/2 + α. As described before, the cell plate voltage Vps at the common junction between the resistors R1 and R2 in Fig. 3 is used to set the bit lines BL and BL(b) to the voltage Vcc/2 + α obtained by voltage division by means of the resistors when the reset time is prolonged. Although a preferred embodiment has been described hereinbefore, various modifications and alterations are possible within the scope of the present invention. The above embodiment is described with reference to a case wherein the bit line voltage is increased by the influence of the parasitic capacitance Cc at the data read mode. However, a bit line voltage may be decreased. In this case, the memory cell discriminating voltage must also be maintained at about Vcc/2. The main part of another embodiment for this purpose will be described in Fig. 6. The same reference numerals as in Fig. 3 denote the same parts in Fig. 6. Referring to Fig. 6, reference symbol Q8 denotes a transistor; and  r , a reset clock signal. In the embodiment described with reference to Fig. 3, the reference voltage Vrf is increased to compensate the discriminating voltage Vds decreased by coupling between the word line WL and the node of the memory cell. On the contrary, the circuit of Fig. 6 corrects an increase in discriminating voltage. In the circuit of Fig. 6, the active clock signal  a and the charge reset signal  r of the capacitor which has the opposite phase as that of the clock signal  a are enabled to turn on the transistor Q₈ so as to discharge the capacitor Cps during the active period. The charge of the capacitor Cps is extracted from the bit lines BL and BL(b) to decrease the reference voltage Vrf. Note that when the transistor Q₈ is turned on, the transistor Q₄ is turned off. In addition, if one of the electrodes of the capacitor Cps is commonly used as the cell plate of the memory capacitor, a thin-film memory cell can be prepared. The reset clock signal  r in Fig. 6 resets the charged capacitor Cps. The reset clock signal  r is enabled at the same timing as that of the active clock signal  a and disabled at the reset timing. In this case, the active clock signal  a is set at low level, and the transistor Q₈ is kept off. In the two embodiments described above, the bit line precharge voltage is derived from the cell plate voltage Vpc. However, the bit line precharge voltage may be provided separately from the cell plate voltage Vpc. The cell plate voltage Vpc is preferably set to be about Vcc/2 to reduce a maximum electric field applied to the dielectric members of the capacitor and is not limited to Vcc/2.

Claims: A semiconductor memory device having a circuit for offsetting a variation in a discriminating voltage (Vds) of a memory cell due to a capacitive coupling (Cc), comprising: a bit line pair consisting of first and second bit lines [respectively (BL) and (BL(b))]; a memory cell comprising a memory capacitor (Cs) for storing data and a gate circuit (Qs) capable of coupling the memory capacitor to the first bit line (BL) of the bit line pair; a word line (WL), connected to the gate circuit, for energizing and deenergizing the gate circuit to control coupling and decoupling of the memory cell to and from the first bit line; a sense amplifier (SA) connected to the bit line pair, which sense amplifier being adapted to sense and amplify a voltage at the first bit line by using a precharge voltage (Vb) of the second bit line (BL(b)) as a reference voltage in an active state of the semiconductor memory device; and a precharge circuit (Q4-Q8, Cps) for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state of the semiconductor memory device, characterized in that the precharge circuit precharges the bit line pair with the resultant precharge voltage obtained by adding a compensating voltage (α) to a precharge voltage in the reset state, the compensating voltage being adapted to compensate for variation in a memory cell discriminating voltage (Vds) based on variation in a memory cell voltage caused by said capacitive coupling which exists between the word line and the storage node of the memory capacitor due to a parasitic capacitance Cc of the gate circuit in the active state, and the resultant precharge voltage being raised to a value Vcc/2 + (Cc/Cs).Vwl, where : Vcc is the power source voltage; Cs is the capacitance of the memory capacitor; and Vwl is the voltage change of the word line when it is switched from its inactive to its active state. A semiconductor memory device according to claim 1, wherein the precharge circuit comprises: a second gate circuit (Q5, Q6) for short-circuiting between the first and second bit lines (BL, BL(b)) in the reset state to supply to the bit line pair the precharge voltage for raising the memory cell discriminating voltage to a value Vcc/2 + (Cc/Cs). Vwl when it is assumed that the parasitic capacitance is not present; and a compensating circuit (Q4, Cps) for adding, to the precharge voltage obtained by the second gate circuit, the compensating voltage. A semiconductor memory device according to claim 2, wherein the compensating circuit comprises: a compensating capacitor (Cps) for storing a charge corresponding to the variation in the compensating voltage for compensating the memory cell discriminating voltage based on the variation in the memory cell voltage caused by the capacitive coupling (Cc) of the word line (WL) to the memory capacitor (Cs) due to the parasitic capacitance of the gate circuit (Qs) upon activation of the memory cell by means of the word line; a second gate circuit (Q4) for supplying the charge corresponding to the compensating voltage to the compensating capacitor in the active state; and a third gate circuit (Q7) for supplying the charge corresponding to the compensating voltage from the compensating capacitor to the bit line pair (BL, BL(b)) in the reset state, thereby compensating for variation in the memory cell discriminating voltage based on the parasitic capacitance and thereby optimizing the discriminating voltage. A semiconductor memory device according to claim 3, wherein the compensating circuit (Cps, Q4) is constituted to be capable of compensating for a decrease in the memory cell discriminating voltage based on the parasitic capacitance (Cc). A semiconductor memory device according to claim 3, wherein the compensating circuit (Cps, Q4) is constituted to be capable of compensating for an increase in the memory cell discriminating voltage based on the parasitic capacitance (Cc). A semiconductor memory device according to claim 3, wherein the compensating circuit further comprises a fourth gate circuit (Q8) for charging the compensating capacitor in the active state, which is alternatively operated with the second gate circuit, the compensating circuit being capable of compensating for both a decrease and increase in the memory cell discriminating voltage based on the parasitic capacitance. A semiconductor memory device according to any one of claims 1 to 6, wherein the precharge circuit further comprises a high-impedance resistance voltage divider (R1, R2) for supplying the resultant precharge voltage to the bit line pair in the reset state for a provision of a long period of reset time.

Inventors: KODAMA, NOBUMI, NAKANO, MASAO, NAKANO, TOMIO, NOZAKI, SHIGEKI, SATO, KIMIAKI, TAKEMAE, YOSHIHIRO
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G11C11
IPC codes: G11C11