CMOS DECODER/DRIVER CIRCUIT FOR A MEMORY

Abstract: A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and to (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A ø PC line is included for receiving a ø PC precharge clock signal thereon and a ø R line is provided for receiving a ø R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices 41...44 connected to A1 to AN-1 or to of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node 14 depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices 24, 28 connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line WLi and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line WLi+1.

Description: The present invention relates to decoder/driver circuits for semiconductor memories, and more particularly to a circuit that can be used as a word-line decoder/driver or a bit-line decoder driver in a CMOS random access memory. A variety of decoder circuits for semiconductor memories are available in the art. In U.S. Patent 4,309,629 issued January 5, 1982 to Kamuro, entitled MOS TRANSISTOR DECODER CIRCUIT, an MOS transistor decoder circuit is disclosed including a plurality of MOS transistors and at least one load element. At least one additional MOS transistor connected to the plurality of MOS transistors and the load element for selecting either of two output terminals for the plurality of MOS transistors, through which decoded output signals are developed. The two additional MOS transistors connected to the two output terminals have normal and complement bit signals, respectively. In U.S. Patent 4,264,828 issued April 28, 1981 to Perlegos et al, entitled MOS STATIC DECODING CIRCUIT, a metal-oxide-semiconductor static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit is laid-out along array lines where the lines have a given pitch. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder. In U.S. Patent 4,259,731 issued March 31, 1981 to Moench, entitled QUIET ROW SELECTION CIRCUITRY, there is provided a quiet row select circuit for holding unselected word lines or row select lines in a memory array at a predetermined voltage potential. Transistors are used to couple each row select line to the predetermined voltage potential. The adjacent row select lines of at least one of the adjacent select lines is always coupled to the predetermined voltage when in an unselected state. A transistor is also used to couple each of the adjacent row select lines together and this transistor is enabled whenever the adjacent row select lines are non-selected so that both row select lines are coupled together to the predetermined voltage level. In another reference of Moench, U.S. Patent 4,200,917 issued April 29, 1980, entitled QUIET COLUMN DECODER, a decoder is provided for semiconductor memory systems which prevents glitches from being coupled into the silicon substrate during the period of time that the sense amplifiers are sensing data on the bit sense lines. The quiet column decoder has double clock NOR gates which allows the address lines to be continuous non-multiplexed lines. The double clocked NOR gate has two transistors for precharging a first and a second node within the NOR gate. Another transistor is coupled between the second node and a voltage reference terminal to serve as an enabling device for the NOR gate. The first node of the NOR gate serves as an output for the column decoder. In U.S. Patent 4,429,374 issued January 31, 1984 to Tanimura, entitled MEMORY ARRAY ADDRESSING, an address decoder for one memory axis is disclosed which comprises NAND circuits while the address decoder for the other axis comprises NOR circuits. A semiconductor memory circuit device comprises at least first and second decoder circuits. The first decoder circuit is so constructed as to receive at least partial address signals among address signals of a plurality of bits and to provide decoded signals of the partial address signals as intermediate signals. The second decoder circuit is so constructed as to receive the intermediate signals, to thereby provide signals for selecting from among a plurality of memory circuits a memory circuit determined by the address signals of the plurality of bits. A publication entitled "CMOS Decoder Circuit" by L M Terman, at page 2135 of Vol 25, No 4, September 1982 of the IBM Technical Disclosure Bulletin relates to improvements in CMOS decoder circuits, and particularly to a decoder circuit which does not dissipate DC power. The decoder is followed with two branches with CMOS drivers for word lines. In Vol 18, No 12, May 1976 of the IBM Technical Disclosure Bulletin, G H Parikh in a publication entitled "High Speed FET Decoder", on page 3955 describes a field-effect transistor decoder circuit which allows improved speed of decoding FET random-access memories, by reducing the capacitance required to be discharged in an unselected decoder. The speed is further increased by reducing the capacitance of the nodes to be discharged wherein isolation transistor devices are provided to isolate the capacitance on word-line voltage nodes to allow bootstrapping to occur if a node has not been discharged. European Patent application EP 0,056 187 discloses a complementary metal-insulated semiconductor (CMIS) memory decoder which is useful for a highly integrated large-capacity ROM or RAM. It describes circuits in which NOR and NAND decoders are used and in which transistors, directly connected to the output node of the decoder, are used as switches to select word lines for driving. Such direct connection loads the output node of the decoder with a high capacitance and hence incurs a loss in speed of response. Other related prior art includes the following references: US Patent 4,194,130 to Moench issued March 18, 1980, entitled DIGITAL PREDECODING SYSTEM; US Patent 4,433,257 to Kinoshita issued February 21, 1984, entitled VOLTAGE SUPPLY FOR OPERATING A PLURALITY OF CHANGING TRANSISTORS IN A MANNER WHICH REDUCES MINORITY CARRIER DISRUPTION OF ADJACENT MEMORY CELLS; US Patent 4,156,938 to Proebsting et al issued May 29, 1979, entitled MOSFET MEMORY CHIP WITH SINGLE DECODER AND BI-LEVEL INTERCONNECT LINES; US patent 4,344,005 to Stewart issued August 10, 1982, entitled POWER GATED DECODING. SUMMARY OF THE INVENTION An object of the present invention is to provide a high-performance decoder/driver that can be used as a word-line decoder/driver or a bit-line decoder/driver in high performance CMOS RAMs. There are many advantages of the decoder compared to other decoder/driver circuits including the use of a relatively small number of devices. In addition, other objects of the present invention is to provide decoder/driver circuits for CMOS memories which have a smaller line pitch thereby permitting a denser array. A further object of the present invention is to provide a memory decoder/driver circuit that exhibits no dc power dissipation. Still other objects of the present invention are to provide decoder/driver circuits for CMOS memories which demonstrate high performance with no clocking after the address lines have switched, while requiring no long chain of series connected devices, minimizing the stages of delay to select a word line, and minimizing the loading on address lines. Accordingly, the invention provides a decoder/driver circuit for a semiconductor memory comprising: a NOR decoder means connected to true and complement lines of a plurality of A1 to AN-1 memory address bits for receiving said memory address bit signals thereon, said NOR decoder means further including an output node having a high signal condition thereon when all said plurality of designated address bit signals A1 to AN-1 connected thereto are at a low signal condition and having a low signal condition thereon when any of said plurality of designated address bit signals A1 to AN-1 have a high signal condition, an output word line driver means connected to a first memory word line and a second memory word line, characterised by: a first field effect transistor (FET) having a gate connected to the true line of an AN memory address bit signal and a second field effect transistor (FET) having a gate connected to the complement line of said AN memory address bit signal, said first and second FETs each being connected with one electrode to the input of said word line driver means, a third field effect transistor (FET) having a gate connected to said output node of said NOR decoder means and an electrode connected to a predetermined potential, said third FET being connected with its other electrode to the other electrodes of said first and second FETs and forming a conduction path isolated from said NOR decoder output node for said first and second FETs when said third FET is switched on in response to a high signal condition on said NOR decoder output node, whereby a high signal condition on said true line connected to said first FET switches said conductive path to enable said word line driver means to drive said first word line, and whereby a high signal condition on said complement line connected to said second FET switches said conductive path to enable said word line driver means to drive said second word line. The invention will now be more particularly described with reference to the accompanying drawings in which:- Fig 1 is a schematic diagram of a decoder/driver circuit according to the principles of the present invention. Figs 2, 3, 4 and 5 are illustrations of waveforms of signals at various points in the circuit shown in Fig 1. Fig 6 is a schematic diagram of a circuit including a decoder and two driver outputs. Fig 7 is a schematic diagram of a circuit which is a modified version of the circuit of Fig 6 which employs fewer devices. A schematic diagram of a decoder/driver circuit is shown in Fig 1. Signal  PC applied on gate lead 10 of p-channel device 22 is a precharge clock signal and signal  R applied on gate lead 12 of n-channel device 41 is a reset clock signal. in Figs 1, 6 and 7, a MOSFET device having a diagonal line, as shown in device 22, is a p-channel device whereas a MOSFET without a diagonal line, as shown in device 41, is an n-channel device. Devices 41, 42, 43...44 are connected in a conventional NOR circuit configuration, well-known to those skilled in the art. Lines A1 through AN are internal address lines from the address buffers, and the first A1 - AN-1 are connected to the inputs of the NOR circuit in the conventional manner. That is, the gate of each device in the NOR circuit is connected to either the true or complement address line for the corresponding address bit from the address buffers. The N-1 address bits are connected to 2 N-1 decoders with the circuit drawn in FIG. 1 being an example of just one of such 2 N-1 decoders, each of which is selected (high output) by a different unique address while the remainder of the decoders will remain unselected (low output). The true and complement lines for address bit AN are both connected to the decoder/driver circuit in the 1 of 2 selection stage, and are shown explicitly in FIG. 1. The 1 of 2 selection stage output is the input to the output driver stage. The functional operation of the proposed circuit will now be described. At the start of a cycle, the address lines A1 , A1, A2 , A2... AN , AN are low as shown in FIG. 3. The precharge signal ø PC applied to the gate of p-channel device 22 on line 10 is low as shown in FIG. 2 and reset signal ø R applied to line 12 is also low as shown in FIG. 5. Node 14 is at V DD and nodes 16 and 18 were charged to V DD when reset clock signal ø R on line 12 went high at the end of the previous cycle. At the beginning of the cycle, precharge clock signal ø PC goes up (see FIG. 2) turning transistor 22 (T1) off. It is assumed for purposes of explanation that driver output WLi+1 is to be selected. For this case, address lines A1 through AN are low and A1 through AN are high. Since all inputs to the NOR remain low, node 14 remains high, device 26 remains on, and node 20 remains low. Now as soon as signal AN goes high, the node 18 is discharged through transistors 24 and 26. As a result, the driver output WLi+1 is selected and goes high. All other driver outputs including WLi remain low and thus are de-selected. If, on the other hand, signal AN is low and signal AN is high, then node 16 is discharged to ground through transistors 28 and 26, selecting driver output WLi; all other driver outputs remain deselected. If any one of the address inputs A1 through AN-1 goes high, node 14 of the NOR circuit will be discharged, turning off device 26 and preventing the discharge of nodes 16 and 18, keeping both word lines WLi and WLi+1 low or deselected regardless of whether AN or AN goes high. Thus, only one of the 2 N-1 NOR circuits will have a node 14 that is high, allowing a selected word line to rise when either AN or AN goes high. The decoding function of the circuit is summarized in Table 1, where the state of decoder node 14 will be high in precharge and remains high if the NOR is selected; it goes low if the decoder is deselected. If the NOR is deselected (node 14 low), neither word line WLi or WLi+1 can be selected, while if it is selected (node 14 high) either WLi or WLi+1 will be selected, depending on whether AN or AN goes high. Only one word line WL will be selected for a given address bit pattern. DECODER NODE 14 AN AN WLi WLi+1 CONDITION High Low Low Low Low Precharge High Low High Low High Select WLi+1 High High Low High Low Select WLi Low Low High Low Low Deselected Low High Low Low Low Deselected Towards the end of the cycle, the clock signal  R goes up and all address line signals A1 through AN as well as A1 through AN go low. The nodes 16 and 18 charge up to V DD , pulling the selected driver output low. At the end of the cycle, reset clock signal  R and precharge clock signal  PC go down as shown in FIGS. 2-5. As a result, node 14 is charged to V DD , turning off devices 30 and 32, leaving nodes 16 and 18 charged high, but floating. To avoid discharge of the nodes 16 and 18 over a long cycle time, p-channel pull-up devices with gates connected to  PC similar to transistor 22 (T1) can be connected between node 16 and V DD and 18 and V DD . Alternatively, the gate of the pull-up device connected to node 16 can be connected to AN, and the gate of the pull-up device connected to node 18 can be connected to AN . In this case, the  R input signal and device 12 may be eliminated. It is necessary to have the least significant internal address bit signal AN/ AN not arrive too early with respect to the other address bit signals A1 through AN-1. If the address bit signal AN/ AN arrives too early, it can lead to an erroneous discharge of nodes 16 and 18. For example, if node 14 will discharge when addresses A1 through AN-1 arrive, and if line AN goes high before node 14 has discharged, then node 18 can at least partially discharge erroneously through devices 24 and 26 and this can bring the associated word line WLi+1 up in error. This erroneous signal is transient, and the circuit will eventually settle into the correct output condition. On the other hand, it is desirable to have the address signal AN or AN arrive as early as possible to minimize delay through the entire circuit. Thus, there is a trade off in the early arrival of address bit AN/ AN between minimizing the delay through the circuit without causing an erroneous transient discharge. The circuit can be readily optimized for minimum delay without significant erroneous transient without substantial impact on overall performance. The circuit in FIG. 6 is an alternative embodiment of the invention which selects two driver outputs running in opposite directions for each associated selecting address input. A modified version of FIG. 6 which uses less devices is shown in FIG. 7. A physical layout of the schematic shown in FIG. 7 may be simpler than that of FIG. 6. The circuit has a number of advantageous features. There is only one NOR circuit per pair of word lines (or per two pairs of word lines as shown in FIGS. 6 and 7). After the address lines switch, no clocking is required before the selected word line rises. This and the low number of delay stages results in high performance. There is no dc power consumed, and dynamic charge storage is required only for a short well-defined portion of the cycle. It will be appreciated by those skilled in the art that alternative embodiments of the invention may be provided wherein the n type devices may be replaced by p type devices, and vice versa. Also, another inverter may be provided at the output to change the polarity of each output and inverted input signals may be used.

Claims: A decoder/driver circuit for a semiconductor memory comprising: a NOR decoder means (NOR DECODER - Fig. 1) connected to true and complement lines of a plurality of A1 to AN-1 memory address bits for receiving said memory address bit signals thereon, said NOR decoder means further including an output node (14) having a high signal condition thereon when all said plurality of designated address bit signals A1 to AN-1 connected thereto are at a low signal condition and having a low signal condition thereon when any of said plurality of designated address bit signals A1 to AN-1 have a high signal condition, an output word line driver means (OUTPUT DRIVER) connected at the output to a first memory word line (WLi) and a second memory word line (WLi+1), characterised by: a first FET (28) having a gate connected to the true line of an AN memory address bit signal and a second FET (24) having a gate connected to the complement line of said AN memory address bit signal, said first and second FETs (28, 24) each being connected with one electrode to the input of said word line driver means, a third FET (26) having a gate connected to said output node (14) of said NOR decoder means and an electrode connected to a predetermined potential, said third FET (26) being connected with its other electrode to the other electrodes of said first and second FETs and forming a conduction path isolated from said NOR decoder output node for said first and second FETs (28, 24) when said third FET (26) is switched on in response to a high signal condition on said NOR decoder output node (14), whereby a high signal condition on said true line connected to said first FET (28) switches said conductive path to enable said word line driver means (OUTPUT DRIVER) to drive said first word line (WLi), and whereby a high signal condition on said complement line connected to said second FET (24) switches said conductive path to enable said word line driver means (OUTPUT DRIVER) to drive said second word line (WLi+1). A circuit as claimed in Claim 1 wherein said NOR decoder means includes a plurality of switching transistors (42, 43...44) connected to said true and complement lines of said plurality of A1 to AN-1 memory address bits and wherein a high signal condition on any of the lines connected to said NOR decoder produces a discharge of said NOR decoder output node (14) and switches off said third FET (26), thus breaking said conduction path and preventing said first and second word lines from being driven by said word line driver means. A circuit as claimed in Claim 2 wherein said NOR decoder means further includes a precharge transistor device (22) connected between a potential voltage supply source (V DD ) and said NOR decoder output node (14), and which switches off in response to a precharge clock signal ( PC) applied to the gate thereof. A circuit as claimed in Claim 2 or Claim 3 wherein said NOR decoder means further includes a reset transistor device (41) connected to said decoder output node (14) and responsive to a reset signal ( R) applied to the gate thereof for discharging said NOR decoder output node (14). A circuit as claimed in Claim 3 or Claim 4 wherein said first FET (28) connected to said third FET (26) and responsive to said AN address bit signal, is further switchably connected to said voltage supply source (V DD ) via a second node (16), and said second FET (24) connected to said third FET (26) and responsive to said AN address bit signal is further switchably connected to said voltage supply source (V DD ) via a third node (18), wherein said first memory word line (WLi) is driven in response to a low signal at said second node (16) and said second memory word line (WLi+1) is driven in response to a low signal at said third node (18), and wherein said first FET (28) switches in response to said AN bit address signal and discharges said second node through said first FET (28) and said third FET (26) device along said conduction path, thereby providing an output signal on said first memory word line (WLi). A circuit as claimed in Claim 5 wherein said second FET (24) switches in response to said AN address bit signal and discharges said third node through said second FET (24) and said third FET (26) along said conduction path, thereby providing an output signal on said second memory word line (WLi+1). Operation of a circuit as claimed in Claim 5 or Claim 6 wherein initially said  PC signal and said  R signal are at a low voltage state, said NOR decoder output node (14) is at a high voltage state, said second (16) and third (18) nodes are at a high voltage state, said true and complement address lines are at a low voltage state and said first (WLi) and second (WLi+1) memory word lines are at a low voltage state, and wherein said  PC signal goes to a higher voltage state, said precharge transistor device (22) switches off, said address lines of said NOR decoder remain at a low state, said NOR decoder output node (14) remains at a high voltage state, and said second node (16) discharges through said first (28) and third (26) FETs, thereby raising the voltage on said first memory word line (WLi) to a higher voltage state. Operation of a circuit as claimed in Claim 5 or Claim 6 wherein initially said  PC signal and said  R signal are at a low voltage state, said NOR decoder output node (14) is at a high voltage state, said second (16) and third (18) nodes are at a high voltage state, said true and complement address lines are at a low voltage state and said first (WLi) arid second (WLi+1) memory word lines are at a low voltage state, and wherein said  PC signal goes to a higher voltage state, said precharge transistor device (22) switches off, said address lines of said NOR decoder remain at a low state, said NOR decoder output node (14) remains at a high voltage state, and said third node (18) discharges through said second (24) and third (26) FETs, thereby raising the voltage on said second memory word line (WLi+1) to a higher voltage state. Operation of a circuit as claimed in Claim 7 or Claim 8 wherein said  R signal goes to a higher voltage state after the voltage on either of said memory word lines has gone to a higher state, resulting in said address lines going to a lower voltage state, and said second (16) and third (18) nodes charging up to a higher voltage state thereby discharging said memory word line signal to a lower voltage state. A circuit as claimed in any of Claims 4 to 6 wherein said  R and said  PC clock signals return to lower voltage states, thereby charging said NOR decoder output node (14) to a higher voltage state.

Inventors: CHAPPELL, BARBARA ALANE, RAJEEVAKUMAR, THEKKEMADATHIL VELAYUDAN, SCHUSTER, STANLEY EVERETT, TERMAN, LEWIS MADISON
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: G11C8
IPC codes: G11C8, G11C11, H03K19