A METHOD OF DRIVING A TWO-DIMENSIONAL CCD IMAGE SENSOR

Abstract: An image sensor comprises rows 2-1, 2-2 of light sensing elements accumulating electrical charges in response to irradiation. The charges are transferred via gates 4-1, 4-2 to first transfer registers 3-1, 3-2. The charges are transferred from these registers into shift registers 5-1, 5-2 and out of the shift registers into a further transfer register 6 from which a serial output video signal is obtained via an output amplifier 8. In order to shorten the effective exposure time transfers from the rows of elements 2-1, 2-2 to the registers 3-1, 3-2 are effected at any time when the stored charges are being trans­ ferred from the shift registers 5-1, 5-2 to the further transfer register 6. The transfers from the first transfer registers 3-1, 3-2 to the shift registers occur in synchronism with the trans­ fers from the shift registers to the further transfer register 6. A discard drain region 30 is provided for sweeping out the first transfer registers and shift registers. In an alternative emb­ odiment a discard drain region is positioned alongside the further transfer register 6.

Description: The present invention relates to a two-dimensional charge-coupled device (CCD) image sensor which is used in an image-picking-up apparatus such as a TV camera and a VTR camera, and more specifically, to a method of driving an interline-transfer type CCD image sensor. The two-dimensional CCD image sensor, which is now finding applications in TV cameras and in VTR cameras, includes an imaging area (photosensitive area) having a plurality of rows of light-sensing elements which accumulate electrical charges of amounts corresponding to intensity of irradiated lights for a predetermined period of time, a storage area (memory area) having a plurality of shift registers each receiving the accumulated charges from each row of the imaging area and storing them, and a readout register receiving the stored charges from each shift register and outputting a video signal. Such a CCD image sensor is disclosed in our United States Patent No. US-A 4,322,753. In operation of such CCD image sensor, the period of time of the charge accumulation in each light-sensing row in the imaging area is fixed to one television field time, which corresponds to 1/60 second exposure time in a mechanical shutter of a camera. When a quickly moving object is picked-up, therefore, a fuzzy video signal is produced to deteriorate the resolution. In order to remove such defect, it is necessary that the CCD image sensor has a shutter function of more than 1/60 second and up to 1/2000 second exposure time. For this purpose, it has been attempted to provide a mechanical shutter in front of the CCD image sensor. However, the camera becomes bulky and the manufacturing cost increases. EP-A-0 083 376 describes a solid state image pickup device in which signal charges obtained by a plurality of photodetectors arranged in horizontal and vertical rows are read by a vertical transfer unit extending along a vertical row of the photodetectors, and are transferred at high speed from the vertical transfer unit to a storage unit. Then they are transferred horizontal line by horizontal line to a horizontal transfer unit. Before the signal charges are read out by the vertical transfer unit, unnecessary charges in the vertical transfer unit are swept out and transferred, in the same direction as the signal charges move, to a charge absorption unit. This is done to reduce "smear" and "blooming" in the sensed image. The invention in its various aspects is defined in the independent claims, to which reference should now be made. In one preferred embodiment of the invention, described in more detail below, an image sensor comprises rows of light sensing elements accumulating electric charges in response to irradiation. The charges are transferred via gates to first transfer registers. The charges are transferred from these registers into shift registers which store the charges, and out of the shift registers into a further transfer register from which a serial output video signal is obtained. Transfers from the rows of light sensing elements to the first transfer registers are effected during the time that the stored charges are being transferred from the shift registers to the further transfer register. One or more discard drain regions are provided for sweeping out the first transfer registers and shift registers during a vertical blanking period. The electric charges accumulated in the light sensing elements are transferred into the first transfer registers during the vertical blanking period and after the sweeping away operation. The charges in the first transfer registers are transferred to the shift registers during the vertical blanking period, and the charges in the shift registers are transferred to the further transfer register during an active video period. Additionally, the electric charges accumulated in the light sensing elements are transferred into the first transfer registers at a selected point during the active video period while the charges in the shift registers are being transferred to the further transfer register. This enables the charge-accumulation time in the imaging area to be shortened without using a mechanical shutter. For example this may give the sensor a shutter function of more than 1/60 second and up to 1/2000 second exposure time without changing the structure of the sensor. A first high speed pulse train (sweeping pulse train) is used for the sweeping out operation in the vertical blanking interval and a second high-speed pulse train having a number of pulses equal to the number of light-sensing elements in each row is used to transfer the charges quickly from the first transfer registers to the shift registers. A first gate pulse takes the accumulated charges out of each row of light-sensing elements at a time point after the first high-speed pulse train is generated and before the second high-speed pulse train is generated, and a second gate pulse takes out non-signal charges accumulated in each row of the light-sensing elements at an arbitrary time point after the generation of the second high-speed pulse train and before the generation of the first high-speed pulse train, during the field period (active video period). The imaging area may have twice the number of light-sensing elements. In this case, each row is arrayed with alternatively arranged light-sensing elements for odd field and even field, and in the odd field period the accumulated charges are taken out of the half of the elements in each row, while in the even field period out of the other half. The second high-speed pulse train has pulses of a number equal to a half of the number of the elements in each row and the second gate pulse is generated only once in any one of the odd and even field period, that is, once in the frame period. Fig. 1(a) is a schematic diagram illustrating a structure of a CCD image sensor to which the present invention is adapted; Fig. 1(b) is a schematic diagram of another structure of a CCD image sensor; Fig. 2(a) is a diagram showing driving pulses for driving the CCD image sensor shown in Fig. 1 according to a prior art; Fig. 2(b) is a diagram showing driving pulses for the CCD image sensor of Fig. 1 according to the present invention; Figs. 3(a) to 3(i) are diagrams showing the transfer of electric charges for explaining operation of the present invention; Fig. 4 is a block diagram of a driving circuit which produces pulses to drive the CCD image sensor according to the present invention; Fig. 5(a) is a diagram showing a video signal of one frame obtained by picking up a quickly moving object relying upon respective accumulations in the odd and even fields; Fig. 5(b) is a diagram showing a video signal of one frame obtained according to a second embodiment of the present invention; Fig. 6 is a diagram showing driving pulses according to the second embodiment of the present invention; Fig. 7 is a block diagram showing a driving circuit which generates the driving pulses shown in Fig. 6; Fig. 8 is a block diagram of a video camera when the driving method of the present invention is adapted to adjusting the sensitivity; Fig. 9 is a block diagram showing a partial portion of the driving circuit of Fig. 8; and Fig. 10 is a block diagram of a video camera which employs the driving method of the present invention. Referring to Figs 1(a) and 1(b), a CCD image sensor, to which the present invention is adapted, comprises an imaging area 1, a storage area 5 and a readout register 6. The imaging area 1 includes a plurality of rows of photodiodes 2-1, 2-2, ..., a plurality of transfer registers 3-1, 3-2, ... each provided along each row of photodiodes (hereinafter referred to as vertical transfer registors because they extend vertically on the driving), and a plurality of transfer gates 4-1, 4-2, ... each provided between each row of the photodiodes and each associated vertical transfer register and electrically connected in common to a terminal 7. When a gate pulse is applied to the terminal 7, electrical charges accumulated in the photodiodes are transferred from each row of the photodiodes to the associated vertical transfer register simultaneously. The storage area 5 includes a plurality of shift registers 5-1, 5-2, .... coupled at their one ends to one ends of the vertical transfer registers, respectively, and has a capacity (total storages of the shift registers) corresponding to a number of picture elements constituting one television field. The readout register, or horizontal transfer register, 6 is provided at the other ends of the shift registers 5-1, 5-2, ..., extending horizontally on the drawing. The accumulated changes are transferred through the vertical registers and the shift registers into the readout register 6, travelled via the readout register 6 to an output amplifier 8, and derived from an output terminal 9 as a video signal. In Fig. 1(a), a discard drain region 30 is provided in common at the other ends of the vertical transfer registers 3-1, 3-2, .... Unnecessary (non-signal) charges are swept away from the vertical transfer registers and from the shift registers into the drain region 30 to vanish. In Fig. 1(b), a discard drain region 31 is positioned along the readout register 6 and coupled to the register 6 via a transfer gate (not shown) which transfers unnecessary (non-signal) charges from the shift registers 5-1, 5-2, .... to the drain region 31 where they vanish. In Fig. 1, the number of the photodiodes 2 in each row or array is, for example, 512 to meet the NTSC system and the number of stages in each vertical transfer register 3 is 256. The 512 photodiodes are classfied into 256 photodiodes for the odd field (odd field photodiodes) and the other 256 photodiodes for the even field (even field photodiodes), and each odd field photodiode and each even field photodiode are alternatively arranged in each row. Accumulated electric charges are transferred from the 256 odd field photodiodes to the 256-stages vertical transfer register 3 in the odd field period and from the 256 even field photodiodes to the same 256-stages vertical transfer register in the even field period. In this case, an accumulation period of the charges in the photodiodes corresponds to one television frame period in the prior art. On the other hand, it is possible that the electric charges accumulated in both of the odd field photodiodes and the even field photodiodes are simultaneously transferred to the vertical transfer register 3 in each of the odd and even fields. In this case, a video signal of one picture element is produced by combining two electric charges of the odd field photodiode and the even field photodiode, and the combination of the odd field photodiode and the even field photodiode in changed dependent on the odd television field and the even television field. Therefore, the accumulation period in this case corresponds to one television field period Operation of the CCD image sensor shown in Figs. 1(a) and 1(b) according to a conventional driving method will now be described in conjunction with Fig. 2(a). Fig. 2(a) shows a vertical driving pulse VD, a vertical branking signal VB, two transfer pulses øV1 and øV2 of two phases for the vertical transfer registers 3 and the memory section 5, and a transfer gate pulse TP for transferring the accumulated electric charge from the photodiodes 2 to the vertical transfer registers 3. In the vertical blanking period at the start of a field period, the electric charges stayed in the vertical transfer registers 3 and/or stored in the memory section 5 are swept away by excess charge sweeping pulses P1. These pulses P1 are applied to both the vertical transfer registers 3 and the shift registers 5. In case of Fig. 1(a) their phase is opposite to a normal phase, that is, the phase transferring the charges to a reverse direction (upwards in the drawing). In case of Fig. 1(b) their phase is normal. The number of the sweeping pulses P1 is greater than a total number of stages contained in both the registers 3 and 5 in each row. Since the number of stages in the register 3 is favorably equal to that in the register 5, the number of pulses P1 is larger than twice of the number of stages in the vertical transfer register 3. For example, if the number of effective scanning lines is set to be 256 in one television field for the NTSC system, the number of pulses P1 is selected to be greater than 512. For sweeping, in the case of Fig. 1(a), the electric charges stages in the vertical transfer registers 3 and/or stored in the memory section 5 are transferred upward to the drain 30. In the case of Fig. 1(b), the electric charges are transferred downward to the drain 31. In this case, a gate (not shown) is practically provided between the horizontal transfer register 6 and the overflow drain region 31 and a gate pulse is applied to this gate to pass the electric charges to the drain region 31 when the sweeping operation is performed. After the sweeping operation, the electric charges accumulated in the photodiodes 2 are transferred to the vertical transfer register 3 by a pulse P4 of the transfer gate pulse TP. The amount of the electric charges accumulated in the photodiodes 2 is dependent upon the quantity of light irradiating during a previous one television field. The electric charges transferred to the vertical transfer registers 3 are then quickly transferred to the shift register having 256 vertical stages in the memory section 5 in response to high-speed transfer pulses P2. Therefore, the high-speed transfer pulses P2 includes 256 pulses. Thereafter, the electric charges transferred to the memory section 5 are shifted to the horizontal transfer register 6 in response to transfer pulses P3 synchronized with a horizontal scanning timing. In each horizontal scanning period, the horizontal transfer register 6 transfers the electric charges in the horizontal direction by a clock of, for example, 7.2 MHz to deliver a video signal at the output terminal 9. In Fig. 2(a), therefore, a period t₁ denotes the excess charge sweeping period, a period t₂ denotes the transfer period from the photodiodes 2 to the vertical transfer register 3, a period t₃ denotes the high-speed transfer period from the vertical transfer register 3 to the memory section 5, and a period t₄ denotes the transfer period from the memory register 5 to the horizontal register 6 determined by the horizontal scanning timing (active video period). The accumulation period in the photodiodes 2 is denoted by a period t₅, and the electric charges accumulated in the photodiodes 2 for the period t₅ are transferred to the vertical transfer register 3 in the next television field. In the conventional driving method, the accumulation period t₅ remains contant and cannot be changed. Next, a driving method according to the present invention will be explained with reference to Fig. 2(b), wherein the same pulses and the same periods as those shown in Fig. 2(a) are indicated by the same reference letters. The feature of the invention resides in addition of a charge transfer pulse P5 which is applied to the transfer gate terminal 7 as a transfer gate pulse TP during the active video period t₄, that is, after the application of the high-speed transfer pulses P2 and before the application of the sweeping pulses P1. According to the present invention, there is no need of modifying the structure of the CCD image sensor. This transfer pulse P5 transfers the charges accumulated for a period t₆ from the application of the normal transfer pulse P4 up to the application thereof from the photodiodes 2 to the vertical transfer registers 3, which charges are to the swept away as mentioned below. Therefor, these charges are non-signal charges, and charges accumulated for a period t₇ which is equal to t₅ (Fig. 2(a)) minus t₆ are effective to become a video signal. Thus, t₆ denotes a needless accumulation period and the period t₇ denotes an effective accumulation period. As shown in Figs. 2(a) and 2(b), the effective accumulation period t₇ can be arbitrarily shortened, as compared with t₅, by t₆ with changing the timing of the charge transfer pulse P5. Operation of the present invention will now be described with reference also to Figs. 3(a) to 3(i) in which the upper halves represent the vertical transfer register 3 and the lower halves represent the memory section 5. In these Figures, the width corresponds to one picture element. Fig. 3(a) shows the condition where the electric charges have been swept away by the excess charge sweeping pulse P1 (Fig. 2(b)), and no electric charge is left in the register 3 and in the memory section 5. Fig. 3(b) shows the condition where the electric charges accumulated in the photodiodes 2 are transferred to the vertical transfer register 3 in response to the transfer gate pulse P4, and the electric charges denoted by C1 are stored in the register 3. Fig. 3(c) shows the next step where the electric charges C1 are transferred to the memory section 5 in response to the high-speed transfer pulses P2. Thereafter, the electric charges C1 stored in the memory section 5 are shifted to the horizontal transfer register 6 in response to the transfer pulses P3 as shown in Fig. 3(d), and the video signal is delivered from the horizontal transfer registe 6. It is assumed that the additional charge sweeping pulse P5 is applied when the electric charges of n lines (n horizontal scanning periods) have been transferred to the horizontal transfer register 6. The electric charges accumulated in the photodiodes 2 up to this timing are transferred to the vertical transfer register 3 as shown in Fig. 3(e). In Fig. 3(e), C2 represents the non-signal electric charges transferred into the register 3. The non-signal electric charges C2 are the charges accumulated in the photodiode 2 during the period t₆ of Fig. 2(b). After the condition of Fig. 3(e), the electric charges C1 in the memory section 5 are successively shifted to the horizontal transfer register 6 in response to the transfer pulses P3, and at the same time the non-signal charges C2 are downwardly shifted forwards the memory section 5. As a result, a condition shown in Fig. 3(f) is obtained at the end of one television field. After the step of Fig. 3(f), excess charge sweeping pulses P1' of the next field are applied as shown in Fig. 2(b), and whereby the non-signal electric charges C2 in the vertical transfer register 3 and the memory section 5 are all swept away. As a result the condition of Fig. 3(g) is obtained. Then, a transfer gate pulse P4' of the next field is applied, and the electric charges accumulated in the photodiodes 2 is transferred to the vertical transfer register 3 as shown in Fig. 3(h). This electric charges are denoted by C3 in Fig. 3(h) and are accumulated during the period t₇ (Fig. 2(b)) after the charge sweeping pulse P5 is applied. The electric charges C3 are then transferred to the memory section 5 in response to a next high-speed transfer pulses P2' as shown in Fig. 3(i) and are delivered from the horizontal transfer register 6 as a video signal during the next television field. Thus, the electric charges C3 accumulated only after the application of the pulse P5 are used as effective charges to produce a video signal. Thereafter, the effective exposure time corresponds to t₇ which can be designated by changing the time point of the application of the pulse P5 which in turn corresponds to an electronic shutter signal. Even in this embodiment, other unnecessary electric charges such as a dark current component and a smear component are swept away by the excess charge sweeping pulses P1, P1', as a matter of course. It is also allowable to add a plurality of charge transfer pulses P5. In this case, a period from the last charge transfer pulse P5 serves as an effective accumulation time t₇, i.e., serves as an exposure time. Fig. 4 is a block diagram showing a driving circuit for obtaining the driving pulses shown in Fig. 2(b). In Fig. 4, a flip-flop 10 which receives a vertical driving pulse VD is set at the front edge thereof, and enables a high-speed pulse generating circuit 11 so as to produce high-speed pulses of a frequency of, for example, 1.5 MHz. A high-speed pulse counter 12 counts the high-speed pulses, and produces two outputs when it has counted 256 and 512 pulses. Responsive to a control signal from the flip-flop 10, first, a timing of 512 pulses is detected by a gate 13, and whereby the flip-flop is reset via a gate 14. The flip-flop 10 is set again by the rear edge of the vertical driving pulse VD, and the high-speed pulse generating circuit 11 produces high-speed pulses. The other output produced by the high-speed pulse counter 12 when it has counted 256 pulses is detected by a gate 15 under a control signal from the flip-flop 10, and the flip-flop 10 is reset via the gate 14. The two control signals supplied from the flip-flop 10 to the gates 13 and 15 change their states so that the above-mentioned sequence can be carried out. Upon receipt of a horizontal driving signal HD, a transfer pulse generating circuit 16 produces the transfer pulse P3 based upon the timing thereof. A mixing circuit 17 mixes the excess charge sweeping pulses P1, the high-speed transfer pulses P2 from the high-speed pulse generating circuit 11, and the transfer pulses from the transfer pulse generating circuit 16 together, and produces transfer pulses øV1 and øV2. In order to drive a CCD image sensor, transfer pulses of two phases, three phases, or four phases are selectively used depending upon the structure of the CCD image sensor or function to be derived from the CCD image sensor. The mixing circuit 17 produces transfer pulses having desired number of phases and desired relationship of phases. A transfer gate pulse generating circuit 18 which receives the vertical driving signal VD generates the transfer gate pulse P4 having a predetermined phase difference as shown in Fig. 2(b). The transfer gate pulse generating circuit 18 also generates the needless charge transfer pulse P5 in response to a delayed vertical driving signal VD' delivered from an accumulation time selecting circuit 19. In the accumulation time selecting circuit 19, the delay time of the delayed vertical driving signal VD' is selected by a selector 20. In this embodiment, one of five different times of seconds is selected by the selector 20. The delay time may be continuous varied in the accumulation time selecting circuit 19, as a matter of course. The circuit 19 can be very easily realized by using a multi-vibrator or a counter. In this embodiment, the circuit 19 is constituted by the counter which receives the horizontal driving signal HD as a clock signal and the vertical driving VD as a clear signal, and produces a carry output as the delayed vertical driving signal VD' while changing an initial load value depending upon the selecting signals A, B, C, D and E. In the first embodiment, as described above, the video signal of one picture element is formed from two outputs of two photodiodes, and these two photodiodes to form the video signal of one picture element are differently selected depending upon the odd field and the even field. In the CCD image sensor, furthermore, it can be also attempted to take out a video signal having high resolution in which an odd field video signal and an even field video signal are delivered from the individual odd field and even field photodiodes instead of combining two photodiodes. This method (defined as a frame mode, hereinafter) can increase the resolution in the vertical direction, and is desirable to take out the video signal corresponding to one fixed picture of the television frame. However, in the frame mode, there exists a time difference in the accumulation time between the odd and even fields. This time difference corresponds to movement of about 46 cm when a moving object moves at a speed of 100 km per hour. In this case, the fixed picture of the television frame becomes as shown in Fig. 3(a), in which a split image is disadvantageously obtained. According to a second embodiment of the present invention, the operation for sweeping away an needless electric charges is effected not for every fields but once for one frame period to remove the defect of Fig. 5(a). Fib 5(b) shows one fixed picture of the television frame obtained according to the second embodiment of the present invention. In Fig. 5(b), there is no difference between the odd and even fields. Fig. 6 shows driving pulses for explaining the driving method according to the second embodiment of the present invention, wherein the vertical driving signal VD, the vertical blanking signal VB, and transfer pulses øV1, øV2 are the same as those of Fig. 2(b). In this embodiment, the needless charge transfer pulse P5 is added once for one frame to provide a coincident effective accumulation time in the odd field and in the even field. That is, as shown in Fig. 6, the needless charges in the vertical transfer register 3, and the memory section 5 are swept by the sweeping pulses P1 and, then, the electric charges accumulated in the photodiodes for the odd field (the odd field photodiodes) are transferred into the vertical transfer register 3 in response to a transfer gate pulse P4₀. Sequentially, the electric charges transferred into the register 3 are transferred to the memory section 5 responsive to high-speed transfer pulses P2. Then, the electric charges accumulated in the photodiodes for the even field (the even field photodiodes) 2 are transferred into the empty vertical transfer register 3 in response to a transfer gate pulse P4 e . Thereafter, responsive to transfer pulses P3 contained two successive fields, a video signal of one television frame is obtained by delivering the electric charges of the odd field and the even field which are stored in the vertical transfer register 3 and the memory section 5, from the horizontal transfer register 6. In the second embodiment, both the needless charge sweeping pulses P1 and the high-speed transfer pulses P2 are not present during a blanking period between the odd field and the even field. In order to realize such operation, the transfer gate pulse P4 e for the even field is designated to appear after the high-speed transfer pulses P2 so as to transfer the accumulated charges corresponding to the even field into the vertical transfer register 3. Furthermore, needless charge transfer pulses P5 o and P5 e are located before the transfer gate pulses P4 o and P4 e , and the effective accumulation times are determined by the period t₇ between the pulses P5 o and P4 o , and between pulses P5 e and P4 e . As shown,in Fig. 6, since the accumulation times for the odd field and the even field are almost in agreement, a perfect fixed picture of the television frames having high vertical resolution is obtained even when the object moves quickly. Fig. 7 shows a block diagram of a driving circuit for the second driving method according to the second embodiment of the present invention. Circuit elements of Fig. 7 are the same as of the driving circuit of Fig. 4 except for a flip-flop 10' and a transfer gate pulse generating circuit 18' which are served with a field index pulse FIP. In Fig. 7, the needless charge sweeping pulses P1 and the high-speed transfer pulse P2 are generated responsive to the field index pulse FIP only during the odd field. Upon receipt of the field index pulse FIP, the transfer gate pulse generating circuit 18' generates a transfer pulse P4 o during the blanking period from the even field to the odd field. Further, the needless charge transfer pulse P5 o is also generated once during the frame period. With respect to transfer pulses TP o and TP e for respective odd and even fields, the transfer pulse TP e for transferring the accumulated charges for the even field is delayed by about 120 µS behind the transfer pulse TP o . Therefore, the transfer pulse TP e can be generated by utilizing this relationship. According to the second embodiment as described above, the needless electric charges are swept away once during each frame, so that the electric charges can be accumulated for nearly a coincident period of time for the two fields. Namely, a video signal having good resolution is obtained in the frame mode while providing the variable shutter function. The foregoing description has dealt with the shutter function of the present invention by changing the accumulation time. The present invention, however, can also be adapted to adjusting the sensitivity of a TV camera. That is, in Fig. 2(b), the sensitivity increases if the effective accumulation time t₇ is extended and decreases if the effective accumulation time t₇ is shortened. The present invention is very advantageous since it involves no modification for the structure of the CCD image sensor. Fig. 8 shows a TV camera apparatus according to a third embodiment of the present invention. In Fig. 8, an image passed through a lens unit 21 is supplied to a CCD image sensor 22 which sends a video signal to a video processing circuit 23. The video signal produced by the video processing circuit 23 is supplied to a level detecting circuit 24 which detects whether the video signal has a level that is greater than a predetermined level or not. The detected result is sent to a timing control circuit 25 which so determines the effective accumulation period t₇ (Fig, 2(b)) that the level difference detected by the level detecting circuit 24 becomes zero, and which sends a control signal to a driving circuit 26. The driving circuit 26 corresponds to the circuit shown in Fig. 4. In the driving circuit 26 of Fig. 8, the accumulation time selecting circuit 19 and the selector 20 of Fig. 4 are modified as shown in Fig. 9, where the control signal is load data defined for each field, and the time when a carry output is delivered from a counter 19' is changed depending upon the load data. According to a fourth embodiment shown in Fig. 10, since a shutter speed is specified for a controller 27, the effective accumulation time of the CCD image sensor 22 is primarily determined depending upon the shutter speed, whereas an iris control circuit 28 coupled to the lens unit 21 and/or a video gain of a video processing circuit 23' are controlled secondarily to compensate the level change of the video signal depending upon the shutter speed. These control operations can be determined in variety manners in accordance with imaging conditions. In one example of the controller 27, various sets of a iris value of the lens unit 21 and again of the video processing circuit 23' are previously prepared in accordance with the shutter speed and the video signal level, and stored in a read-only memory. Therefore, the iris value and the gain are automatically determined in response to the designated shutter speed and the detected video signal level through the read-only memory. The invention was described in the foregoing by using an interline-transfer CCD image sensor. However, it needs not be pointed out that the invention can also be adapted to an image sensor of a MOS structure. Furthermore, it is possible to add the needless charge transfer pulse to the transfer pulses.

Claims: An image sensor comprising a plurality of rows of photodiodes (2-1, 2-2), said photodiodes in each row defining a vertical direction, a plurality of vertical transfer register means (3-1, 3-2) respectively coupled to said plurality of rows of photodiodes (2-1, 2-2) for receiving electric charges accumulated in said photodiodes (2-1, 2-2) and transferring said charges therethrough, storage means (5-1, 5-2) coupled to the outputs of said vertical transfer register means (3-1, 3-2) for receiving electric charges delivered thereto from said vertical transfer register means (3-1, 3-2) and for storing the delivered charges, horizontal transfer register means (6) coupled to said storage means (5-1, 5-2) for transferring electric charges delivered thereto from said storage means (5-1, 5-2) in a horizontal direction to produce a video signal, means for sweeping away electric charges stored in said vertical transfer register means (3-1, 3-2) and said storage means (5) during a vertical blanking period, means for transferring electric charges accumulated in said photodiodes (2-1, 2-2) into said vertical transfer register means (3-1, 3-2) during said vertical blanking period and after said charges are swept away, means for transferring the electric charges delivered to said vertical transfer register means (3-1, 3-2) into said storage means (5-1, 5-2) during said vertical blanking period, and means for transferring the electric charges from said storage means (5-1, 5-2) to said horizontal transfer register means (6) during an active video period, characterized by means for transferring electric charges accumulated in said photodiodes (2-1, 2-2) into said vertical transfer register means (3-1, 3-2) during said active video period while the charges stored in said storage means (5-1, 5-2) are being transferred from said storage means (5-1, 5-2) to said horizontal transfer register means (6). An image sensor according to claim 1, in which the means for transferring electric charges accumulated in said photodiodes into said vertical transfer register means during said active video period is adjustable to adjust the effective accumulation period. An image sensor comprising a plurality of photodiode arrays (2-1, 2-2), each of said photodiode arrays containing first photodiodes designated for an odd television field and second photodiodes designated for an even television field, said first photodiode and said second photodiode being alternatively arranged, a plurality of vertical transfer register means (3-1, 3-2) respectively coupled to the plurality of said photodiode arrays (2-1, 2-2) for receiving electric charges from said first photodiodes and said second photodiodes and defining a vertical direction, storage means (5-1, 5-2) coupled to the plurality of said vertical transfer register means (3-1, 3-2) for receiving the electric charges from the plurality of said vertical transfer register means (3-1, 3-2), horizontal transfer register means (6) coupled to said storage means (5-1, 5-2) for transferring the electric charges delivered from said storage means (5-1, 5-2) in a horizontal direction to output a video signal, means for generating first high-speed pulses (P1) to sweep away electric charges contained in said vertical transfer register means (3-1, 3-2) and said storage means (5-1, 5-2) in the vertical direction during one vertical blanking period in one frame period, means for generating a first transfer pulse (P4o) after generation of said first high-speed pulses (P1) to transfer electric charges accumulated in said first photodiodes to said vertical transfer register means (3-1, 3-2) during said vertical blanking period, means for generating second high-speed pulses (P2) after generation of said first transfer pulse (P4o) to transfer the electric charges stored in said vertical transfer register means (3-1, 3-2) to said storage means (5-1, 5-2) during said vertical blanking period, means for generating a second transfer pulse (P4e) to transfer the electric charges accumulated in said second photodiodes to said vertical transfer register means (3-1, 3-2), and means for generating third transfer pulses (P3) to shift the electric charges stored in said storage means (5-1, 5-2) and in said vertical transfer register means (3-1, 3-2) into said horizontal transfer register means (6) continuously during a television frame period, characterized in that said second transfer pulse (P4e) is generated after generation of said second high-speed pulses (P2), and said image sensor further comprises means for generating a fourth transfer pulse (P5o) to transfer electric charges accumulated in said first photodiodes to said vertical transfer register means (3-1, 3-2) at a selected time point in said television frame period, and means for generating a fifth transfer pulse (P5e) a predetermined period after said fourth transfer pulse (P5o) to transfer electric charges accumulated in said second photodiodes to said vertical transfer register means (3-1, 3-2), whereby the effective accumulation period in said first and second photodiodes can be controlled by selecting said time point in generating said fourth transfer pulse (P5o). A method of shortening the effective exposure time of an image sensor which includes a plurality of rows of light-sensing elements (2-1, 2-2) accumulating electrical charges in response to irradiated light thereon, a plurality of first transfer registers (3-1, 3-2) each coupled to each row of said light-sensing elements (2-1, 2-2) and receiving accumulated charges transferred thereto from said light sensing elements (2-1, 2-2), a plurality of shift registers (5-1, 5-2) each coupled to each said first transfer registers (3-1, 3-2) and storing the accumulated charges transferred thereto from said first transfer registers (3-1, 3-2), and a second transfer register (6) coupled to said plurality of shift registers (5-1, 5-2) and transferring therethrough the stored charges transferred thereto from said shift registers (5-1, 5-2) to output a video signal, said method comprising: a first step of sweeping away accumulated charges stored in said first transfer registers (3-1, 3-2) and said shift registers (5-1, 5-2) during a vertical blanking period, a second step subsequent to said first step of transferring accumulated charges in said light-sensing elements (2-1, 2-2) into said first transfer registers (3-1, 3-2) during said vertical blanking period, a third step subsequent to said second step of transferring the accumulated charges in said first transfer registers (3-1, 3-2) into said shift registers (5-1, 5-2) during said vertical blanking period, and a fourth step subsequent to said third step of transferring the accumulated charges in said shift registers (5-1, 5-2) into said second transfer register (6) during an active video period; characterized by: a fifth step of transferring accumulated charges in said light-sensing elements (2-1, 2-2) into said first transfer registers (3-1, 3-2) during said active video period. A method according to claim 4, in which in the fifth step the time of transfer of the accumulated charges into said first transfer registers is adjustable. A method of driving an image sensor which includes a plurality of photodiode arrays (2-1, 2-2), each of said photodiode arrays including first photodiodes designated for an odd television field and second photodiodes designated for an even television field, said first photodiodes and each of said second photodiodes being alternately arranged, a plurality of vertical transfer register means (3-1, 3-2) respectively coupled to the plurality of said photodiode arrays (2-1, 2-2) for receiving electric charges accumulated in said first and second photodiodes and defining a vertical direction, storage means (5-1, 5-2) coupled to the plurality of said vertical transfer register means (3-1, 3-2) for receiving electric charges delivered from the plurality of said vertical transfer register means (3-1, 3-2), and horizontal transfer register means (6) coupled to said storage means (5-1, 5-2) for transferring electric charges delivered from said storage means (5-1, 5-2) in a horizontal direction to produce a video signal, said method comprising: a sweeping step of sweeping away electric charges stored in said vertical transfer register means (3-1, 3-2) and said storage means (5-1, 5-2) during one vertical blanking period for a television frame; a first transfer step subsequent to said sweeping step of transferring the electric charges accumulated in said first photodiodes into said vertical transfer register means (3-1, 3-2) during said vertical blanking period; a second transfer step subsequent to said first transfer step of transferring the electric charges delivered from said vertical transfer register means (3-1, 3-2) into said storage means (5-1, 5-2) during said vertical blanking period; a third transfer step of transferring electric charges accumulated in said second photodiodes into said vertical transfer register means (3-1, 3-2); and a fourth transfer step of transferring the electric charges stored in said storage means (5-1, 5-2) and in said vertical transfer register means into said horizontal transfer register means (6) continuously for one television frame period to deliver a video signal of one television frame from said horizontal transfer register means (6), characterized in that: said third transfer step is performed subsequent to said second transfer step, said fourth transfer step is performed subsequent to said third transfer step, and said method further comprises a fifth transfer step of transferring electric charges accumulated in said first photodiodes into said vertical transfer register means (3-1, 3-2) at an optional timing during said one television frame period; and a sixth transfer step subsequent to said fifth transfer step of transferring electric charges accumulated in said second photodiodes into said vertical transfer register means (3-1, 3-2).

Inventors: IKEDA, SADAYUKI C/O NEC CORPORATION, INOUE, HIDEHIKO C/O NEC CORPORATION, NAGAI, KIYOTAKE C/O NEC CORPORATION, NAKAJIMA, HIROSHI C/O NEC CORPORATION, USHIYAMA, YASUICHI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H04N3
IPC codes: H04N3