ELECTRONICALLY TUNABLE FM RECEIVER

Abstract: An electronically tunable FM receiver comprising an h-f amplifier circuit RA equipped with tuning circuits (2) and (4), a frequency converter circuit (5), and i-f signal amplifier circuit (8), a demodulator circuit (9), and a first control voltage gener­ ating circuit (11) for controlling the oscillation frequency of a local oscillator (7) of the frequency converter circuit (5). The tuning control voltage from the first tuning control generating circuit (11) is changed depending upon the detected output of the demodulating circuit (9) and is fed to the tuning circuits (2) and (4) of the h-f amplifier circuit RA. Further, provision is made of a second tuning control voltage generating circuit (25) which so controls the tuning frequency that it nearly fol­ lows the h-f received signals. Therefore, distortion of the h-f received signals decreases in the h-f amplifier circuit RA.

Description: TECHNICAL FIELD The present invention relates to an electronic tuning type FM receiver which comprises a tuning control voltage generating circuit for controlling the oscillation frequency of a local oscillator for a high frequency amplifying circuit having a tuning circuit, a frequency converting circuit, an intermediate frequency amplifying circuit, a demodulating circuit, and the frequency converting circuit. BACKGROUND ART A prior art electronic tuning type FM radio receiver will be described with reference to Fig. 7. A signal received by an antenna 1 is supplied to a high frequency amplifying circuit RA. This high frequency amplifying circuit RA is formed of high frequency tuning circuits 2 and 4 that are provided before and after a high frequency amplifier 3. Each of the high frequency tuning circuits 2 and 4 constructs, for example, a multiple tuning circuit and is formed of a pair of electromagnetically-coupled windings L1 and L2, a capacitor C connected in parallel thereto and a series circuit formed of a pair of voltage-controlled type variable capacity elements (varactor diodes) VC and connected in parallel to the winding. The high frequency signal from the high frequency amplifying circuit RA is supplied to a mixing circuit 6 which constructs a frequency converting circuit 5. The intermediate frequency signal obtained from the mixing circuit 6 is supplied through an intermediate frequency signal amplifying circuit, that is, an intermediate frequency amplifying circuit 8 to a demodulating circuit, that is, a frequency detecting circuit 9. Reference numeral 10 designates an output terminal at which a frequency-detected output is developed. Reference numeral 7 designates a local oscillator which constructs the frequency converting circuit 5 and which includes a resonance circuit 7A which is formed of a winding L, a capacitor C connected in parallel thereto and a series circuit formed of a pair of voltage-controlled type variable capacitor elements (varactor diodes) VC and connected in parallel to the winding. Reference numeral 11 designates a PLL (phase locked loop) employed as the tuning control voltage generating circuit and which comprises a reference oscillator 12, a phase comparator 13, a programmable frequency divider 14 and a low pass filter 15. The oscillation signal from the local oscillator 7 is supplied to the programmable frequency divider 14 and thereby divided by N. The signal thus frequency-divided and the reference signal from the reference oscillator 12 are supplied to the phase comparator 13 and thereby phase-compared. Then, the compared output is supplied to the low pass filter 15. The tuning control voltage obtained from the low pass filter 15 is supplied to the cathodes of the respective voltage-controlled type variable capacity elements VC in the resonance circuit 7A of the local oscillator 7. Further, this tuning control voltage is supplied to the respective cathodes of the respective voltage-controlled type variable capacity elements VC of the respective high frequency tuning circuits 2 and 4 in the high frequency amplifying circuit RA. In such electronic tuning type FM radio receiver, a channel selection frequency is determined by selecting the frequency-dividing ratio of the programmable frequency divider 14 in the PLL 11. In other words, when the frequency-dividing ratio of the programmable frequency divider 14 is altered, the oscillation frequency of the local oscillator 7 is altered and the center band pass frequencies of the high frequency tuning circuits 2 and 4 in the high frequency amplifying circuit RA are altered to become substantially coincident with the channel selection frequency. In the above mentioned prior art electronic tuning type FM radio receiver, the center pass band frequencies of the high frequency tuning circuits 2 and 4 in the high frequency amplifying circuit RA are altered so as to become substantially coincident with the channel selection frequency, that is, the carrier frequency of the high frequency receiving signal. That is, with respect to the frequency characteristics of the high frequency amplifying circuits 2 and 4 as shown by a curve in Fig. 8, a carrier frequency fO is coincident with the center band pass frequency thereof. Since this carrier signal is frequency-modulated by a modulation signal (audio signal), the high frequency receiving signal supplied to the high frequency amplifying circuit RA is changed around the frequency fO from hour to hour. For example, when a momentary frequency thereof is fO - Δf, as illustrated in the figure, the frequency response in the high frequency amplifying circuit RA is lowered as compared with a case where the frequency is fO also, on the basis of the value Df, the phase of the high frequency receiving signal is changed variously so that the high frequency receiving signal is destorted. In another prior art electronic tuning type FM radio receiver (FR-A-2 304 213) in order to obtain a stable local oscillation signal even when the received frequency is valid, the loop gain of the PLL circuit in a local oscillator is changed. Thus, the local oscillation signal itself is changed, which is disadvantageous for the signal/noise ratio. Accordingly, it is an object of this invention to provide an electronic tuning type FM receiver in which a high frequency receiving signal is difficult from being distorted in the high frequency amplifying and has a good signal/noise ratio. In an electronic tuning type receiver comprising a high frequency amplifying circuit having a tuning circuit, a frequency converting circuit forming a mixer for receiving an output signal from said high frequency amplifying circuit and an output signal from a local oscillator, an intermediate frequency signal amplifying circuit and a demodulating circuit, and a phase locked loop circuit formed of a reference oscillator, a phase comparator, a programmable frequency divider and a low pass filter controlling said local oscillator in which phase locked loop circuit an oscillator frequency of said frequency converting circuit is controlled by said programmable frequency divider, characterized by correcting voltage generating means for correcting an non-linearity of a tuning control voltage versus capacity characteristic in a voltage-controlled type variable capacity element provided in said tuning circuit in response to an output voltage of the low pass filter in said phase locked loop circuit, and first adding means for adding a low frequency signal of said demodulating circuit and an output of said correcting voltage generating means to and for supplying an added signal to the voltage-controlled type variable capacity element in said tuning circuit. According to the present invention as described above, since the center pass band frequency of the tuning circuit in the high frequency amplifying circuit substantially follows the frequency of the high frequency receiving signal, the amplitude characteristic of the output from the high frequency amplifying circuit becomes substantially flat and the phase characteristic thereof becomes substantially flat so that the distortion of the high frequency receiving signal in the high frequency amplifying circuit is reduced. BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a circuit diagram showing an embodiments of the present invention, Fig. 2 is a graph graphing the relationship between the frequency characteristic of a high frequency tuning circuit and a frequency of a high frequency receiving signal, Fig. 3 is a graph graphing an amplitude frequency characteristic and a phase frequency characteristic in the high frequency tuning circuit, Fig. 4 is a graph graphing frequency chracteristic of an output voltage from an operational amplifier 21, Fig. 5 is a graph graphing frequency characteristic of a tuning control voltage supplied to each voltage-controlled type variable capacity element in the high frequency tuning circuit, Fig. 6 is a circuit diagram showing one portion of another embodiment of the present invention, Fig. 7 is a circuit diagram of a prior art example and Fig. 8 is a graph graphing a relationship between a frequency characteristic of a high frequency tuning circuit and a high frequency receiving frequency in the prior art example. BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will hereinafter be described with reference to Fig. 1. Fig. 1 shows an electronic tuning type FM radio receiver. A high frequency receiving signal from an antenna 1 is supplied to a high frequency amplifying circuit RA. This high frequency amplifying circuit RA is formed of a high frequency amplifier 3 and high frequency tuning circuits 2 and 4 that are provided in the preceding and later stages thereof. The high frequency tuning circuits 2 and 4 are each formed of, for example, a multiple tuning circuit which comprises electromagnetically-coupled windings L1 and L2, a capacitor C connected in parallel thereto and a series circuit formed of a pair of voltage-controlled type variable capacity elements (varactor diodes) VC connected in parallel to the winding. The output from the high frequency amplifying circuit RA is supplied to a mixing circuit 6 which constructs a frequency converting circuit 5. The intermediate frequency signal therefrom is supplied through an intermediate frequency signal amplifying circuit, that is, an intermediate frequency amplifying circuit 8 to a demodulating circuit 9 and thereby a detection output is developed at an output terminal 10. Reference numeral 7 designates a local oscillator which constructs the frequency converting circuit 5 and which includes a resonance circuit 7A formed of a winding L, a capacitor C connected in parallel thereto and a series circuit formed of a pair of voltage-controlled type variable capacity elements (varactor diodes) VC connected in parallel to the winding. Reference numeral 11 designates a PLL (phase locked loop) employed as a first tuning control voltage generating circuit and which includes a reference oscillator 12, a phase comparator 13, a programmble frequency divider 14 and a low pass filter 15. The local oscillation signal from the local oscillator 7 is supplied to the frequency divider 14 and thereby frequency-divided by N. The frequency-divided output and the reference oscillation signal from the reference oscillator 12 is supplied to the phase comparator 13 and thereby phase-compared and the compared output is supplied to the low pass filter 15. The tuning control voltage from this low pass filter 15 is supplied to the cathodes of the respective voltage-controlled type variable capacity elements VC in the resonance circuit 7A of the local oscillator 7. Reference numeral 25 designates a tuning control voltage generating circuit which will be described hereinafter. The first tuning control voltage from the PLL 11 is applied through a buffer amplifier 17 to both ends of a series circuit formed of resistors 18 and 19. The voltage obtained at the junction between the resistors 18 and 19 is supplied to a non-inverting input terminal of an operational amplifier 16. A resistor 20 is connected between the output terminal and the inverting input terminal of the operational amplifier 16. The detection output of the frequency detecting circuit 9, that is, the audio signal is supplied to a non-inverting input terminal of an operational amplifier 21. A resistor 22 is connected between the output terminal and the inverting input terminal of the operational amplifier 21. The output terminal of the operational amplifier 21 is connected through a resistor 23 to the inverting input terminal of the operational amplifier 16. The output from the buffer amplifier 17 is supplied to a window comparator 24 in which it is compared with, for example, 5 reference voltages. Then, the window comparator generates four kinds of compared outputs on the basis of the region of 5 reference voltages to which the above mentioned output belongs. The inverting input terminal of the operational amplifier 21 is grounded through respective series circuits formed of on-off switches S1 to S4, resistors R1 to R4 and DC power sources E1 to E4. The tuning control voltage from the operational amplifier 16 is supplied to the cathodes of the respective voltage-controlled type variable capacity elements VC of the respective high frequency tuning circuits 2 and 4 in the high frequency amplifying circuit RA. Next, the operation of this electronic tuning type FM radio receiver will be described. It is possible to select the channel by varying the frequency-dividing ratio of the programmable frequency divider 14 in the PLL circuit 11. That is, when the frequency-dividing ratio of the programmable frequency divider 14 is altered, the local oscillation frequency of the local oscillator 7 is altered and the tracking is carried out such that the center band pass frequencies of the respective high frequency tuning circuits 2 and 4 in the high frequency amplifying circuit RA becomes substantially coincident with the channel selection frequency, that is, the carrier frequency of the high frequency receiving signal. By the way, since the relationship between the capacity and the control voltage of the voltage-controlled type variable capacity element (varactor diode) is non-linear, in the case of the tuning circuit using this voltage-controlled type variable capacity element, as the tuning frequency becomes high, the control voltage deviation for obtaining the same frequency deviation becomes large. In other words, the control voltage is proportional to square to cubic of the tuning frequency. Therefore, in view of such aspect, the gain of the operational amplifier 21 will be altered by a step-by-step line approximately as follows. Specially, the tuning control voltage from the buffer amplifier 17 is supplied to the window comparator 24 in wich it is compared with, for example, five reference voltages Va, Vb, Vc, Vd and Ve (where Va < Vb < Vc < Vd < Ve). Then, on the basis of one of four regions of these reference voltages Va to Ve to which the tuning control voltage belongs, the switches S1 to S4 are turned on selectively and then the gain of the operational amplifier 21 is altered on the basis of the resistance values of the resistors R1 to R4. Thus, the detection output voltage of the detecting circuit 9 is corrected thereby so as to match the relationship between the tuning frequencies of the tuning circuits 2 and 4 and the control voltage with the above mentioned characteristic. Further, in order that the center band pass frequencies (tuning frequencies) of the high frequency tuning circuits 2 and 4 may become substantially coincident with the channel selection frequency (the frequency of the carrier signal for the high frequency signal) within the reception frequency band (for example, 76 MHz to 90 MHz), the tuning control voltage from the buffer amplifier 17 is corrected bv switching the DC voltage sources E1 to E4 in response to the corresponding voltage so as to alter the offset voltage of the operational amplifier 21. In this case, V4 assumes the frequency-detected output voltage supplied to the non-inverting input terminal of the operational amplifier 21, V3 assumes the output voltage of the operational amplifier 21, V1 assumes the output voltage of the buffer amplifier 17 and V2 assumes the output voltage of the operational amplifier 16. Then, the gain of the operational amplifier 16 is controlled such that when V3 = 0, the equality V2 = V1 is established. If the frequency characteristic of the tracking error presented when the tuning control voltage from the PLL 11 is supplied directly to the respective voltage-controlled type variable capacity elements VC of the respective high frequency tuning circuits 2 and 4 contains a characteristic having, for example, a downward convexity as shown by a broken line in Fig. 4, it is sufficient that a control voltage supplied to each of the respective voltage-controlled type variable capacity elements VC of the tuning circuits 2 and 4 may have a characteristic opposite thereto. Therefore, the high frequency receiving frequency range is selected as a range from frequencies fa to fe, the range is equally divided to four ranges, reference frequencies fa, fd, fc, fd and fe, which contains both ends of such divided range, are selected and substantially average control voltages Vα, Vβ, Vγ and Vδ in the respective regions are obtained by the above mentioned DC voltage sources E1 to E4. That is, a voltage having a frequency characteristic shown by a solid line in Fig. 4 becomes the voltage V3 developed at the output side of the operational amplifier 21. The gain of the operational amplifier 21 is made different by the resistors R1 to R4 in the respective regions from the respective frequencies fa to fe, whereby the inclinations of the control voltages supplied to the respective voltage-controlled type variable capacity elements VC of the tuning circuits 2 and 4 are made different. Accordingly, the tuning control voltage V2 having a frequency characteristic shown in Fig. 5 is developed at the output terminal of the operational amplifier 16 and then supplied to the respective cathodes of the respective voltage-controlled type variable capacity elements VC of the respective tuning circuits 2 and 4. Alternatively, it may be possible that the respective switches are omitted, a single variable resistance element such as an FET and the like is employed instead of the respective resistors, a single variable DC voltage source is employed instead of the respective DC voltage sources, and the gain and the offset of the operational amplifier 21 are respectively varied continuously. Accordingly, as shown in Fig. 2, in response to the receiving frequency fO - Δf of the high frequency receiving signal supplied to the high frequency amplifying circuit RA, the center pass band frequencies (tuning frequencies) of the tuning circuits 2 and 4 are altered so as to become substantially coincident with this frequency fO - Δf. As a result, as shown in Fig. 3A, the amplitude characteristic relative to the high frequency receiving freguency becomes substantially flat in a range between fO - Δf and fO + Δf where the maximum frequency deviation is selected as ± Δf. Further, as shown in Fig. 3B, the phase characteristic of the high frequency receiving signal becomes substantially flat in the range between fO - Δf and fO + Δf. Thus, the distortion of the high frequency receiving signal in the high frequency amplifying circuit RA is reduced considerably. Furthermore, since the offset voltage of the operational amplifier 21 is altered in response to the value of the tuning control voltage from the above mentioned PLL 11, the high frequency tuning circuits 2 and 4 in the high frequency amplifying circuit RA can achieve the tracking positively. While in the above example, 4 series circuits formed of the on-off switches, the resistors and the DC power sources are connected in parallel between the inverting input terminal of the operational amplifier 21 and the ground so as to simultaneously switch both the offset voltage and the gain of the operational amplifier 21 as described above, it may be possible that as shown in Fig. 6, there are provided two stages of operational amplifiers 21A and 21B, resistors 22A and 22B are connected respectively between the output terminals and the inverting input terminals thereof, respective series circuits formed of on-off switches S11 to S14 and resistors R1 to R4 are connected in parallel between the inverting input terminal of one operational amplifier 21A and the ground while the respective series circuits of on-off switches S21 to S24 and DC power sources E1 to E4 are connected through a resistor RO between the inverting input terminal of the other operational amplifier 21B and the ground. Also in this case, this circuit can be operated similarly to Fig. 1. According to the present invention as described above, since the tuning frequency of the high frequency tuning circuit in the high frequency amplifying circuit substantially follows up the high frequency receiving frequency, the distortion of the high frequency receiving signal in the high frequency amplifying circuit can be reduced.

Claims: 1. An electronic tuning type receiver comprising a high frequency amplifying circuit (RA) having a tuning circuit (2, 4), a frequency converting circuit (5) formed by a mixer (6) for receiving an output signal from said high frequency amplifying circuit (RA) and an output signal from a local oscillator (7), an intermediate frequency signal amplifying circuit (8) and a demodulating circuit (9), and a phase locked loop circuit (11) formed of a reference oscillator (12), a phase comparator (13), a programmable frequency divider (14) and a low pass filter (15) controlling said local oscillator (7), in which phase locked loop circuit (11) an oscillator frequency of said frequency converting circuit (5) is controlled by said programmable frequency divider (14), characterized by correcting voltage generating means (24; S1 to S4; R1 to R4; E1 to E4) for correcting a non-linearity of a tuning control voltage versus capacity characteristic in a voltage-controlled type variable capacity element (VC) provided in said tuning circuit (2, 4) in response to an output voltage of the low pass filter (15) in said phase locked loop circuit (11), and first adding means (21) for adding a low frequency signal of said demodulating circuit (9) and an output of said correcting voltage generating means (24; S1 to S4; R1 to R4; E1 to E4) and for supplying an added signal to the voltage-controlled type variable capacity element (VC) in said tuning circuit (2, 4). 2. An electronic tuning type receiver according to claim 1, characterized in that said correcting voltage generating means includes a plurality of reference voltage sources (E1 to E4), a window comparator (24) connected to the output side of said low pass filter (15) and switching means (S1 to S4) for selectively supplying an output voltage of anyone of said plurality of reference voltage sources (E1 to E4) to said first adding means (21) in response to an output of said window comparator (24). 3. An electronic tuning type receiver according to claim 2, characterized in that a gain of said adding means (21) is switched in response to the output of said window comparator (24). 4. An electronic tuning type receiver according to claim 2, characterized by second adding means (16) for adding and supplying an output voltage of said low pass filter (15) in said phase locked loop circuit (11) and the output of said first adding means (21) to the voltage-controlled type variable capacity element (VC) in said tuning circuit (2, 4). 5. An electronic tuning type receiver according to claim 4, being characterized in that said first (21) and second (16) adding means are respectively formed of operational amplifiers.

Inventors: SATO KAZUHIRO, SATO, KAZUHIRO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1986
Main classification: H03J7
IPC codes: H04B1, H03J7