LASER DISPLAY SYSTEM

Abstract: A laser control system comprising a computer (10), an output buffer (11, 12) and a laser control circuit (13, 14, 15, 16, 17, 18, 21, 22). The laser control circuit includes laser deflection mirrors (17, 18) for controlling X and Y coordinates of the laser beam, the mirrors being rotated by precision galvanometers (21, 22), which are in turn driven by analogue to digital converters (ADCs) (13, 14). Data for the ADCs is stored in First-In-First-Out buffers (FIFOS) (11, 12) until required, the FIFO buffers being periodically refilled by an output routine running in the computer (10). When the FIFO buffers are full, an interrupt stops the output routine, allowing the processor to continue with other tasks until another interrupt is generated, signalling that the buffers have reached a predetermined degree of emptyness, at which time the output routine is recommenced.

Description: LASER DISPLAY SYSTEM The present invention relates generally to a laser display system and in particular the invention is directed to an interface between a computer and a laser, which enables the laser to be computer driven in real-time and to achieve special effects hereto before not possible with conventional laser display systems. Known computer control laser display systems comprise a pair of mirrors mounted on precision galvanometers which deflect the beam in an x-y plane, in response to X, Y co-ordinates provided by the computer. By suitable manipulation of the mirrors, the laser beam can be made to trace a desired pattern on a screen. If the pattern is swept by the beam at a sufficiently high rate, the traced pattern will appear to be continuously illuminated to the human eye. The laser can then be used in applications such as advertising, light shows and the production of special effects. In producing a laser image, the co-ordinates of the points of the image must first be calculated by the computer, converted to analogue voltages and fed to respective precision galvanometer/mirror assemblies. Moreover, the co-ordinate values must be fed to the galvanometer/mirrors at least at a sufficiently high rate. Known systems cannot achieve real time creation and alteration of laser display patterns since the computers used cannot calculate display co-ordinates from input instructions at a high enough rate to allow the supply of co-ordinate data to the mirrors in real-time. Thus, the presently available laser display systems require the co-ordinates of the desired image to be first calculated, then stored in memory from which they are read out at a predetermined rate. The known systems are generally inflexible and allow little interaction by the operator. Further, the large amounts of memory required to store co-ordinates of even simple images increases the costs and complexity of the laser display system. The present invention consists in a laser display system comprising a computer adapted to receive and store data relating to the definition of images to be displayed by the laser and to generate co-ordinate data as an output to be fed to laser control circuits for controlling the direction in which the laser beam is projected to thereby trace an image on a screen, a data buffer being disposed between said computer output and said control circuits such that data is supplied from the data buffer to the control circuits at a rate determined by the requirements of the control circuits and data is supplied from the computer to the data buffer at a rate determined by the capabilities of the computer, said data being supplied from the data buffer to the control circuits in the same order that it is supplied from the computer to the data buffer. In a preferred form of the invention, the computer is able to supply data to the data buffer at a rate which is sufficiently high that from time to time the data buffer is unable to accept any further information. In order to deal with data at this rate, the data buffer is provided with a first signal output indicating that the buffer is no longer capable of accepting data and a second signal output indicating that the data buffer has attained or exceeded a predetermined degree of emptiness. These first and second signals produced by the data buffer are used to interrupt the operation of the computer to switch between first and second programmes running in the computer, the first programme being a programme to calculate and output data co-ordinates to the buffer this programme being initiated or resumed upon the occurrence of the second signal from the data buffer and being halted by the occurrence of the first signal from the data buffer, while the second programme is a programme which provides a user interface and allows generation storage and retrieval of images to be displayed, the second programme being initiated or recommenced by the occurrence of " the first signal and being halted by the occurrence of the second signal from the data buffer. In the preferred embodiment the data buffer comprises a First In First Out (FIFO) buffer having a Buffer Full signal as its first signal and a Buffer Half Empty signal as its second signal, such that when the Half Empty signal is active, the computer is interrupted and switches to the output programme which then proceeds to calculate co-ordinate data and output that data to the FIFO buffer, until such time as the full signal once again interrupts the processor causing the output programme to be terminated and the user interface programme to be recommenced. In this way, a significant portion of the total processing time of the computer is available to the user for tasks such as defining and storing images. This "spare" processor time is also used to perform housekeeping functions and to queue images to the output programme. According to another aspect, the present invention consists in an interface circuit for interfacing between a computer and the laser beam position control device comprising addressing means for addressing a plurality of programme modes of said computer and a first-in-first-out (FIFO) memory with two interrupt signals for interrupting programmes running in the computer, said memory adapted to receive laser beam position data from said computer, a first of said interrupts being generated when the FIFO memory is "nearly empty" and the other of said interrupts being generated when the FIFO memory is "full" and the interrupts being fed to the computer to cause the computer to switch between two programmes running to the computer. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Fig. 1 schematically illustrates a laser -display system in accordance with the present invention; Fig. 2 schematically illustrates part of a first embodiment of the buffer circuit connecting the computer and digital to analogue converters of Fig. 1; Fig. 3 schematically illustrates a second embodiment of part of the buffer connecting the computer and digital to analogue converters of Fig. 1; Fig. 4 is a circuit diagram of the interface circuit of the preferred embodiment; and Fig. 5 is a flow chart of a programme scheduling routine associated with interrupts generated by an output buffer in accordance with the present invention. Referring to Figs. 1 and 2, the laser beam produced by laser 19 is directed by laser control means 5. The laser control means 5 comprises mirrors 17, 18 mounted on precision galvanometer mechanisms 21, 22. A shutter 20 can also be induced to interrupt the beam. Typically, two mirrors 17, 18 oscillating in orthogonal directions are provided to direct the beam in an X-Y plane. The galvanometers 21, .22 are driven by analog voltage deflection signals 23, 24 which are amplified by amplifiers 15, 16. These analog deflection signals are obtained from two eight-bit digital to analog convertors 13, 14 which form part of the interface between a computer 10 and the laser control system 5. The digital to analog convertors 13, 14, in turn, obtain the digital values from a first-in-first-out (FIFO) memory configured as two parallel FIFO buffers, which preferably also provides two extra bits, one for shutter control and the other for clock selection, such that the FIFO memory is in effect 18 bits wide. The clock selection bit allows different channels on a programmable timer to be selected. These control the output clocking of the FIFO memory and hence the rate at which the galvanometers are updated with new position/co-ordinate values. Thus, different -parts of a complex image can be written at different rates giving an increased flexibility. Since the required deflector update rate (up to 20,000 times per second) approaches the fundamental limitations of the computer's calculating capacity, it is necessary to smooth irregularities in the computer's rate of generating data and to optimize the manner in which programmes provide the data. This is achieved by generating computer interrupts on two different conditions. Referring to Fig. 2, a first interrupt 34 when the FIFO memory is "nearly empty" (in the preferred embodiment, this is implemented when the FIFO memory becomes less than approximately half full) , and a second interrupt 35 when the FIFO memory is full. These interrupts are communicated to the computer to cause the computer to switch between two programmes running in the computer, an application programme 43 typically written is BASIC (a language in which many programmers are fluent) , and a computation programme 42 written in machine language and used to calculate the data for the FIFO memory. When the FIFO memory is full, interrupt 34 causes the computer to switch to the application programme 43, for example to receive keyboard instructions from the operator or to accept preprogrammed instructions. When the data in the FIFO memory 13 (31, 32 of Fig. 2) falls below the "nearly empty" threshold, computer interrupt 34 causes the computer to switch to the computation programme to calculate more co-ordinate data for the laser control device. The computation programme is written in machine language for rapid execution. The use of the "full" interrupt 35 allows the machine language routine to execute without the normal practice of continually testing an interface to determine if it can accept data, a time consuming requirement of known laser display systems. As well as providing the data for the FIF-O memory 13 (and 14), the machine language programme 42 performs some computations, adding offsets to various parts of images and performing the interpolations between images. It is relatively simple to add new computational functions to this programme. The machine language programme is driven by tables held in memory and by images referenced by the tables. An additional suite of functions can be included in machine language programmes to interface between the BASIC language application programme and the machine language programme described above. These interface programmes convert data from the formats used by BASIC to formats that are much more efficient for the programmes that are updating the FIFO memory 13, 14, and make it much easier for the BASIC application programme to manipulate images in a form suited thereto. Referring to Figure 1 the illustrated embodiment of a laser display system comprises a computer 10 in which is stored representations of images to be displayed by the laser display system, the computer including an output programme designed to output co-ordinate data, in the form of X co-ordinates and Y co-ordinates, defining the trajectory of the laser beam to be produced by the display system. The X co-ordinates and Y co-ordinates produced by the computer 10 are respectively fed to an X co-ordinate buffer 11 and a Y co-ordinate buffer 12 which are parallel First In First Out buffers and which effectively form a single eighteen bit wide FIFO buffer. The outputs of the FIFO buffer 11, 12 are fed to respective digital to analogue converters 13 and 14 which in turn produce signals to drive the X and Y galvanometer and mirror assemblies 17 and 18 respectively, the signal being amplified by amplifiers 15 and 16 before being applied to the galvanometers. The laser 19 produces a beam which is directed at the mirror of the X co-ordinate mirror and galvanometer assembly 17 which generates a horizontal deflection of the beam. From the "X mirror" , the beam is deflected onto the mirror of the Y mirror and galvanometer assembly 18 which in turn produces a vertical deflection of the laser beam. The laser beam may be interrupted by a gate 20 which is controlled by one bit of the co-ordinates generated at the output of the FIFO buffer, this gate being used to generate blank spots in the laser display. By simply providing buffers between the computer 10 and the digital analogue converters 13. and 14, it is possible to partition the computer's processing time into two portions, the first of which is used to rapidly output co-ordinate data to the buffer and the second of which is used for non real-time tasks such as providing a user interface. If such a buffer is not incorporated in the system, as was the case in prior art laser display systems, the computer is forced to output data at the rate at which it is required by the laser control circuitry. When the computer is operated in this way, without an output buffer, non real-time tasks are continuously interrupted each time the output of a new co-ordinate is required and the resulting processing time overheads relating to interrupt processing and other housekeeping tasks effectively preclude any significant amount of time being allocated to the non real-time task, nor did such prior art systems have sufficient capacity to perform the significant recalculation of each new image position, size or shape in real-time, as would be required if the system were to display moving or animated images. In a system made in accordance with the present invention, on the other hand, the use of output buffers enables the processor to output data at its own rate, independent of the rate at which the data is required by the laser control electronics and therefore overheads relating to interrupt processing are significantly reduced, leaving more time for tasks such as real-time recalculation of co-ordinates when moving an animated display for example, as well as allowing time for the processing of user inputs. Therefore, while the processor is outputing one display pattern, the user can be creating a new pattern on a video terminal and this new pattern can be displayed as soon as the creation is completed. Further, sufficient processing time is available to allow interpolation from one image to another, whereby the real-time programme takes the initial and final images and sequentially recalculates the co-ordinates for intermediate images in order to provide a smooth transition from the initial to the final image, allowing the creation of various effects such as animation, zooming and expanding of images. Referring now to Figure 2, a more detailed schematic illustration of one half of the data buffer of the preferred embodiment is shown. In the embodiment of Figure 2, the X buffer 11 of Figure 1 is realised using a pair of FIFO buffers 31 and 32 connected in series, each of the FIFO buffers having a status output which indicates when the buffer is full. These status outputs are used to generate interrupts to the process 10, the status line from buffer 31 being used to indicate when the combined buffer is full and the status line from buffer 32 being inverted by a gate 33 to generate an interrupt when the combined buffer is less than half full. Each of the interrupts causes the processor 10 to enter an interrupt service routine which is effectively a programme scheduling routine 41. ' This scheduling routine saves the current stack pointer for the programme that was running in the computer immediately prior to the interrupt, loads a new stack pointer relating to the programme that is to be resumed as a result of the interrupt and then executes a return from interrupt instruction. In the preferred embodiment the microprocessor used in the computer 10 is a Motorola 6809 (registered trade mark) , in which the programme counter is stored on the stack together with the remainder of the machine registers upon the occurrence of an interrupt and therefore by replacing the stack pointer and executing a return from interrupt instruction, the programme scheduling routine effectively switches operation of the computer from one programme to another. When the display system is first turned on, the computer is initialized and commences executing the real-time programme 42 which calculates and outputs the co-ordinates for the first image to be displayed. This programme simply calculates each co-ordinate set and outputs the co-ordinates, one at a time, to a peripheral interface adaptor (PIA) which loads the data into the X and Y buffers respectively, while the programme goes on to calculate the next co-ordinate and in turn writes this new co-ordinate into the PIA. The programme always assumes that data previously written to the PIA will have been loaded into the X and Y buffers by the time the next co- ordinate is written and therefore the programme is able to rapidly output a block of data which will fill the combined X buffers 31, 32 and the respective Y buffers, without the need to continuously check the status of the PIA. When the output buffers are full, the Buffer Full signal from the X buffer 31 will generate an interrupt which causes the programme scheduling routine 41 to run and this routine in turn halts operation of the real-time programme 42 and transfers operation to the user interface routine 43, thereby allowing the user to enter new images. edit old images or define sequences of images to be displayed. The user interface routine 43 also queues images to be displayed such that the next image required by the output routine 42 is always available to it. Meanwhile, the FIFO buffers output their contents to the digital to analogue converters 13 and 14 at a relatively constant rate, as required by the display electronics, until shortly after the first part of the X buffer 31 empties, when the full signal of the second part of the X buffer 32 will change state, causing a Less Than Half Full interrupt to be generated. This interrupt once again causes the programme scheduling routine 41 to run in the computer 10 and this routine in turn switches control back to the co-ordinate calculating and output routine 42 which then commences to calculate the next sequence of output co-ordinates and output these to the FIFO buffers. A flow chart for the programme scheduling routine 41 is illustrated in Fig. 5. When either the first or second ' interrupt is detected by the processor an automatic interrupt sequence is initiated which pushes the current instruction register (return address) data register and status register contents onto the stack and then passes control to the routine described by the Fig. 5 flow chart. This routine pops the various register contents saved by the processors interrupt sequence and saves these in a temporary storage reserved for the interrupted programme for this purpose. The interrupt routine then pushes the instruction register valve and other saved register contents relating to a programme to be commenced as a result of the interrupt. This data is retrieved from a second temporary register storage area associated with the second programme. In this manner, control is transferred from one programme to another, alternately, as the buffer empties and fills. Referring now to Figure 3, one half of a second embodiment of the FIFO buffer is illustrated schematically. In this embodiment the computer output data is fed to one of a pair of buffers 52 and 53 via a demultiplexing device 51 while at the same time data from the other of the pair of buffers 52 and 53 is being fed from the buffer to the digital to analogue converter 13 via a multiplexer 54. The data transfer to and from the buffers 52 and 53 is under the control of a buffer control circuit 55. In the circuit of Fig. 3, the buffers 52 and 53 could be simple shift registers, as one buffer will • always be filling while the other is emptying. Otherwise, the circuit interfaces with the computer 10 in the same manner as that of Figure 2, there being two interrupt signals generated by the buffer control circuit 55, an empty signal which generates an interrupt whenever one of the buffers 52 or 53 is empty, to initiate the output of data from the computer by the co-ordinate calculating and output routine 42 and a full signal which generates an interrupt when either of the buffers 52 and 53 is full, to switch control in the computer 10 from the co-ordinate calculating and output routine 42 to the user interface routine 43. In order to determine when each shift register of the pair becomes full or empty, each shift register can be made one bit wider than required, the serial input for the additional bit being set when the register is being loaded and reset when the register is being unloaded such that transitions of this bit at the serial output indicate the empty and full state respectively. It will be recognised that the software required in computer 10 to operate with the buffer of Figure 3 is essentially the same as that previously described with reference to the buffer of Figure 2. The interface circuit shown in Fig. 4 is embodied in a "laser control card" designed to be installed in any one of the explanation slots of the Hitachi MB6890 personal computer. The card interfaces to the computer address, data and control buses via a 56 pin connector. The interface circuit consists basically of a MC6840 timer chip (ICI), a MC6821 peripheral interface adaptor (PIA) chip (IC2), four AM2813 first-in-first-out (FIFO) memory chips (IC3-IC6) , and two DAC0800 digital to analog convertors (IC7 and IC8) which operate in conjunction with amplifiers, together with their associated circuitry (IC19a and b) . Address decoding is carried out by IC10 a, b; ICll a, b; IC12 a, b, c, d and e. Addresses FF74 to FF77 are used in controlling and setting up the PIA (IC2) as shown in Table 1. TABLE 1 ADDRESS REGISTER FF74 Peripheral Register A - Data Direction Register A FF75 Peripheral Register B - Data Direction Register B FF76 Control Register A FF77 Control Register B The timer chip (ICI) is controlled and set up (in conjunction with the R/W control line ) by addresses in the range FF78 - FF7F as shown in Table 2. TABLE 2 ADDRESS REGISTER R/W = Write R/W = Read FF78 Control Register N/A #3 or #1 FF79 Control Register #2 Status Register FF7A MSB Buffer Register Timer #1 Counter FF7B Timer #1 Latches LSB Buffer Register ADDRESS REGISTER R/W = Write R/W = Read FF7C MSB Buffer Register Timer #2 Counter FF7D Timer #1 Latches LBS Buffer Register FF7E MSB Buffer Register Timer #3 Counter FF7F Timer #3 Latches LSB Buffer Register The PIA (IC2) data direction registers A and B are set so that both peripheral interface ports A (PAO-7) and B (PBO-7) are used as output ports. The control registers are set such that interrupt line CAl detects (with IC14 a and b) when the FIFO buffer (IC3, 4, 5 and 6) is full and interrupt CBl detects when the FIFO buffer (IC3, 4, 5 and 6) is "nearly empty". The nearly empty state is indicated in this embodiment when the buffer is less than half empty, CB2 is set as a control signal and strobes the data when available into FIFO's IC3 and 5. CA2 is set to control the *D' type flip-flop IC15 which via the FIFO data bit D8 controls: a) the FIFO output clock (IC3 and 4) , and b) the operation of a shutter (not shown) to control the laser output (IC5 and 6) . The timer chip (ICI) is set to produce two frequencies one of which is selected by IC16 to control the output from the FIFO's (IC3, 4, 5 and 6). The frequency selected is controlled by FIFO data bit 8 (IC3 and 4) and the 2:1 MUX chip IC16. The output from the Timer No 2 output is used to control the FIFO .output when displaying images, with control being changed to the timer No 1 output for character display. Both the timer output frequencies have been selected to be less than the input strobe so that interrupt control can be achieved. The FIFO memory chips (IC3, 4, 5 and 6) are connected as two serially connected pairs to provide two parallel 64 x 9 bit buffer memories. The 9 bit consisting of 8 data bits + 1 bit (D8) used as a control function. The control function associated with the second of the parallel buffer memory is used to control the speed at which the data bits are removed from the FIFO' s. The control bit associated with the second of the parallel buffer memory can be used to control the laser output. IC7 and IC8 are 8 bit high speed digital-to-analog convertors. IC7 controls the 'X' axis of the laser image whilst IC8 controls the 'Y' axis. Operational amplifiers IC9 a and b convert the current output of the D/A convertors to + 8 volts output to drive the laser "X" and "Y" amplifier circuits respectively. A reference voltage required by the D/A convertors is supplied by an 8 volt regulator IC17. The D/A and amplifier circuits IC7 with IC9a and IC8 with IC9b are arranged to give + 8 volts when the input data are all ' 1' s and -8 volts when this data are all 'O's. TABLE 3 DIGITAL CODE Deflection DO Dl D2 D3 D4 D5 D6 D7 D8 Volts Output Positive Full 1 1 1 1 1 1 1 1 1 +8.0 Scale + Zero 1 0 0 0 0 0 0 0 0 +0 . 04 - Zero 0 1 1 1 1 1 1 1 1 -0 .0 4 Negative Full 0 0 0 0 0 0 0 0 0 -8 . 0 Scale The output from the laser card is taken via a 9 pin "D" type connector to the laser unit. The interface is designed for operation with a Hitachi Peach computer, with disk drives and digitiser. The foregoing describes only one embodiment of the present invention however, and modifications which are obvious to those skilled in the art may be made thereto without departing from the scope of the invention. For example, in the event that deflectors of higher speeds are used and/or multiple laser systems are driven, the interface circuit can be repackaged to suit an Hitachi Si computer (a compatible upgrade of the MB 6890 computer) , or the interface circuit can be implemented by "black box" units containing their own micro processors, but co-ordinated by a central computer.

Claims: THE CLAIMS 1. A laser display system comprising a computer adapted to receive and store data relating to the definition of images to be displayed by the laser and to generate co-ordinate data as an output to be fed to laser control circuits for controlling the direction in which the laser beam is projected to thereby trace an image on a screen, a data buffer being disposed between said computer output and said control circuits such that data is supplied from the data buffer to the control circuits at a rate determined by the requirements of the control circuits and data is supplied from the computer to the data buffer at a rate determined by the capabilities of the computer, said data being supplied from the data buffer to the control circuits in the same order that it is supplied from the computer to the data buffer. 2. The laser display system of claim 1, wherein a computer is able to supply data to the data buffer at a rate which is greater than the rate at which the data buffer supplies data to the laser. 3. The laser display system as claimed in claim 2, wherein the data buffer is provided with a first signal output indicating that the buffer is no longer capable of accepting data and a second signal output indicating that the data buffer has attained or exceeded a predetermined degree of emptiness. 4. The laser display system of claim 3, wherein the first and second signals produced by the data buffer are used to interrupt the operation of the computer to switch between first and second programmes running in the computer, the first programme being a programme to calculate and output data co-ordinates to the buffer, this programme beinq initiated or resumed upon the occurrence of the second signal from the data buffer and being halted by the occurrence of the first signal from the data buffer, while the second programme is a programme which provides a user interface and allows generation, storage and retrieval of images to be displayed, the second programme being initiated or recommenced by the occurrence of .the first signal and being halted by the occurrence of the second signal from the data buffer. 5. The laser system as claimed in any one of claims 1-4, wherein the data buffer comprises a First In First Out (FIFO) buffer having a Buffer Full signal as its first signal and a Buffer Half Empty signal as its second signal, such that when the Half Empty signal is active, the computer is interrupted and switches to an output programme which then proceeds to calculate co-ordinate data and output that data to the FIFO buffer, until such time as the full signal once again interrupts the processor causing the output programme to be terminated and a user interface programme to be recommenced. 6. An interface circuit for interfacing between a computer and the laser beam position control device comprising addressing means for addressing a plurality of programme modes of said computer and a first-in-first-out (FIFO) memory with two interrupt signals for interrupting programmes running in the computer, said memory adapted to receive laser beam position data from said computer, a first of said interrupts being generated when the FIFO memory is "nearly empty" and the other of said interrupts being generated when the FIFO memory is "full" and the interrupts being fed to the computer to cause the computer to switch between two programmes running to the computer. 7. The interface circuit of claim 6, wherein a first of said programmes is a programme for outputing data to the FIFO memory and the second of the programmes is a programme for receiving input from an operator, the first programme being halted and the second initiated or recommended by the second interrupt and the second programme being halted and the first programme being initiated or recommenced by the first interrupt. 8. The interface circuit of claim 6 or 7, wherein the first interrupt signal is generated when the FIFO buffer falls below half full. 9. The interface circuit as claimed in any one of claims 6 to 8, wherein two clock rates are provided for clocking data out of the FIFO buffer to drive a laser display, one or other of the clock rates being selected by one bit of the data which is clocked out of the FIFO buffer.

Inventors: LANGDOWN CECIL WILLIAM GEORGE, MCCLOSKEY PAUL STEPHEN, WILLIAMS BRUCE GILBERT, LANGDOWN, CECIL, WILLIAM, GEORGE, MCCLOSKEY, PAUL, STEPHEN, WILLIAMS, BRUCE, GILBERT
Applicants: LUSHER MARK EDWIN FENN, MCCLOSKEY PAUL STEPHEN, SAMREIN PTY LTD, LUSHER, MARK, EDWIN, FENN, MCCLOSKEY, PAUL, STEPHEN, SAMREIN PTY. LIMITED
Application year: 1986
Main classification: G02B26
IPC codes: G09G3