Latch circuit tolerant of undefined control signals

Abstract: A master slave latch circuit wherein the output impedances (Z₁-Z₄) of the input and latching gates (G₁-G₄) in both the master and slave sections are adjusted to prevent the two input gates (G₁, G₃) from turning an simultaneously.

Description: This invention relates to a latch circuit used for a semiconductor integrated circuit device or the like. Figure 12 shows a conventional master/slave latch circuit belonging to the prior art. In Fig. 12 is shown an input A to a master latch circuit M. An input B to a slave latch circuit S is the output of the master latch circuit M. Also shown are an output C of the slave latch circuit S and a control signal . A master input gate G 5 and a slave latching gate G 8 have enable state and disable states controlled by a control signal  and have respective outputs O 5 and O 6 . A master latching gate G 6 and a slave input gate G 7 have their enable states and disable states controlled by a control signal  and have respective outputs O 7 and O 8 . The control signal  is the complement of the control signal . The master latch circuit M contains a buffer B 3 and in the slave latch circuit S contains a buffer B 4 . Figure 13 is a table indicating the states of the gates G 5 through G 8 and of the latch circuit outputs B and C with the states of the control signal . The operation of the conventional master/slave latch circuit will be described. When the master input gate G 5 and the slave latching gate G 8 are enabled by the control signal , the gates G 6 and G 7 are disabled. As a result, the signal of the input A is applied to the output O 5 of the gate G 5 . Simultaneously, in the slave latch circuit S the signal of the output C existing before the change of the control signal  is latched by the gate G 8 and the buffer B 4 . When the control signal  is inverted, the gates G 5 and G 8 are disabled while the gates G 6 and G 7 are placed in an enabled state. Under this condition, in the master latch circuit M, the signal of the output B existing before the control signal  is inverted is latched by the gate G 6 and the buffer B 3 . At the same time, the signal of the output B latched by the master latch circuit M is transmitted through the gate G 7 in the slave latch circuit S and thus transmitted to the output C. The conventional master/slave latch circuit suffers from a difficulty that, when the potential of the control signal  becomes unstable between the "H (high)" potential and the "L (low)" potential (for instance the potential of the control signal  changes slowly from "L" to "H"), the signal of the input A read into the master latch circuit M is directly transmitted to the output C of the slave latch circuit S. The signal provided at the output B (described later) is determined by which one of the outputs of the master input gate G 5 and the slave latching gate G 8 has the smaller output impedance. Similarly, the signal provided at the output C is determined by which one of the outputs of the master latching gate G 6 and the slave input gate G 7 has the smaller output impedance. These output impedances are determined depending upon performances of transistors used therein. On the other hand, in the conventional master/slave latch circuit, in order to decrease the delay time of signal transmission from the input A to the output B and from the input B to the output C, the input gate G 5 in the master latch circuit and the input gate G 7 in the slave latch circuit are made large in transistor size. Also, in order to reduce the chip size of the semiconductor integrated circuit device or the like the master latching gate G 6 and the slave latching gate G 8 are made small in transistor size. Accordingly, in the above-described case, when the potential of the control signal  is  3 (O <  3 <  0 ), the output impedance Z 5 of the master input gate G 5 becomes equal to the output impedance Z 6 of the master latching gate G 6 . Furthermore, when the potential of the control signal  is  4 ( 0 <  4 < V cc ), the output impedance Z 7 of the slave input gate G 7 becomes equal to the output impedance Z 8 of the slave latching gate G 8 . Therefore, when  3 <  <  4 , the output impedance Z 5 of the master input gate G 5 is lower than the output impedance Z 6 of the master latching gate G 6 , and the output impedance Z 7 of the slave input gate G 7 is lower than the output impedance Z 8 of the slave latching gate G 8 . As a result of this, at the output B the output O 5 of the master input gate G 5 is provided as a "master" output while the output O 6 of the master latching gate G 6 is provided as a "slave" output. Also, at the output C the output O 7 of the gate slave input G 7 is provided as a "master" output while the output O 8 of the slave latching gate G 8 is provided as a "slave" output. That is, both of the outputs O 5 and O 7 from the input gates G 5 and G 7 are provided as "master " outputs, and the signal of the input A read into the master latch circuit M is transmitted directly to the slave latch circuit output C with the result that the function of the master/slave latch circuit is not correctly performed. That is, the master/slave latch circuit operates erroneously. In WO-A-8 403 012 a further master/slave latching circuit is described which also consists of a master latch circuit having a reading gate and a latching gate and a slave latch circuit with the same components. The operation of the circuit is controlled by a control signal applied to the gates. The operation of the known latching circuit is similar to that of the circuit shown in Fig. 12. Accordingly, an object of this invention is to eliminate the above-described difficulties accompanying a conventional master/slave latch circuit. More specifically, an object of the invention is to provide a master/slave latch circuit in which its original master/slave latch function is correctly performed and the erroneous operation is prevented. Reference is also made to JP-A-57 64394 which discloses master-and-slave circuits, each having an input data receiving gate, a logic circuit in series and a positive feedback gate. Errors in the high level data in the memory circuits resulting from a time delay in application of clock pulses  and  to the slave circuit with respect to application of the clock pulses  and  to the master circuit are avoided by connecting a resistance in series to the input side of each input data receiving gate. The objects of the present invention are solved by a latch circuit including: a master latch circuit (M) including a first reading gate (G 1 ) for receiving an input signal (A) and for providing an output signal (0 1 ) to a first connection point and a first latching gate (G 2 ) for receiving an input derived from said first connection point and for providing an output (0 2 ) to said first connection point; first means for controlling said master latch circuit (M) by a control signal () alternately to enable said first reading gate (G 1 ) and disable said first latching gate (G 2 ) and to disable said first reading gate (G 1 ) and enable said first latching gate (G 2 ) to thereby enable a first latching output (O 2 ) at said first connection point; a slave latch circuit (S) including a second reading gate (G 3 ) for receiving an input from said first connection point and for providing an output signal (0 3 ) to a second connection point and a second latching gate (G 4 ) for receiving an input derived from said second connection point and for providing an output signal (0 4 ) to said second connection point; second means for controlling said slave latch circuit (S) by said control signal () alternately to enable said second latching gate (G 4 ) and disable said second reading gate (G 3 ) and to disable said second latching gate (G 4 ) and enable said second reading gate (G 3 ) to thereby enable a second latched output (0 4 ) at said second connection point; characterized in that the output impedances (Z 1 to Z 4 ) of said gates (G 1 to G 4 ) satisfy the following condition when the magnitude of the voltage of said control signal () lies within a predetermined range, , <  <  2 , of which the lower end value ( 1 ) is the control signal voltage at which the output impedances (Z 3 , Z 4 ) of the second reading and latching gates (G 3 , G 4 ) transiently become equal and the upper end value ( 2 ) is the control signal voltage at which the output impedances (Z 1 , Z 2 ) of the first reading and latching gates (G 1 , G 2 ) transiently become equal, said condition being: Z 1 > Z 2 and Z 3 > Z 4 , whereby for any voltage value of said control signal (), said first reading gate (G 1 ) provides an output signal (0 1 ) to said first connection point at times other than when said second reading gate (G 3 ) provides said output signal (0 3 ) to said second connection point. A master/slave latch circuit according to the invention is so designed that, irrespective of the magnitude of voltage of a gate control signal, the output of a reading gate in the master latch circuit and the output of a reading gate in the slave latch circuit are not provided as "master" outputs simultaneously. In the master/slave latch of the invention, there is provided a means for preventing, irrespective of the value of voltage of the gate control signal, the simultaneous output of the input gate in the master latch circuit and the output of the input gate in the slave latch circuit. Thus, the outputting of the input signal of the master latch circuit directly from the slave latch circuit is prevented. Fig. 1 is a circuit diagram showing a master/slave latch circuit which is a first embodiment of this invention. Fig. 2 is a diagram indicating the states of various gates with the states of a control signal . Fig. 3 is a diagram showing equivalent circuits of the master latch circuit and the slave latch circuit with  =  =  0 . Figs. 4, 5, 7, 8, 10, and 11 are circuit diagrams showing master/slave latch circuits which are other embodiments of the invention. Fig. 6 is a diagram showing examples of clocked gates employed in the circuits of Figs. 7 and 8. Fig. 9 is a diagram showing examples of transmission gates used in the circuits of Figs. 10 and 11. Fig. 12 is a circuit diagram showing a conventional ordinary master/slave latch circuit. Fig. 13 is a diagram indicating the states of various gates with the states of a control signal . In these figures, like parts are designated by like reference numerals or characters. A first embodiment of this invention will be described with reference to Fig. 1. The outward form of this circuit is the same as that of Fig. 12, although the elements have been renumbered. Most importantly, the output impedances of the gates are restricted. However, the associated logic table is different. Fig. 2 indicates the states of outputs O 1 through O 4 of gates G 1 through G 4 and the latch circuit outputs B and C as a function of the voltages of the control signal . Figure 3 shows equivalent circuits of the master and the slave latch circuits in the case when  =  =  0 , showing the variation in potential of the output B. In Fig. 3, reference characters Z 1 through Z 4 designate respectively the output impedances of the master input gate G 1 , the master latching gate G 2 , the slave input gate G 3 and the slave latching gate G 4 . It is required that Z 1 is equal to or greater than Z 2 and Z 3 is greater than Z 4 and these output impedances are selected from the range of 100 ohms to 1,000 ohms so as to meet the characteristics of transistors used therein. B 1 and B 2 respectively represent the buffers in the master latch circuit and the slave latch circuit. The enabled and disabled states of the gates G 1 and G 4 are controlled by the control signal  while the enabled and disabled states of the gates G 2 and G 3 are controlled by the complemented control signal  . When the gates G 1 and G 4 are in the enabled state and the gate G 2 and G 3 are in the disabled state, in the master latch circuit the signal of the input A is transmitted to the output O 1 of the master input gate G 1 while in the slave latch circuit the signal of the output C provided before the change of the control signal  is latched by the slave latching gate G 4 and the buffer B 2 . Upon the inversion of the control signal , the gates G 1 and G 4 are disabled while the gates G 2 and G 3 are enabled. In this operation, in the master latch circuit, the signal of the output B provided before inversion of the control signal  is latched by the master latching gate G 2 and the buffer B 1 , while in the slave latch circuit the signal of the output B thus latched is read by the slave input gate G 3 and transmitted to the output C. In the above-described embodiment, as shown in Fig. 3, when  =  =  0 , in the master latch circuit, the output impedance Z 2 of the latching gate G 2 is less than output the impedance Z 1 of the input gate G 1 . Therefore, at the master output B, the potential of the output O 2 of the master latching gate G 2 is provided as a "master" potential while the potential of the output O 1 of the master input gate G 1 is provided as a "slave" potential (cf. the parts (a) and (b) of Fig. 3). In the slave latch circuit, the output impedance Z 4 of the latching gate G 4 is less than the output impedance Z 3 of the input gate G 3 . Therefore, at the slave output C, the potential of the output O 4 of the slave latching gate G 4 is provided as a "master" potential while the potential of the output O 3 of the slave input gate G 3 is provided as a "slave" potential (cf. parts (c) and (d) of Fig. 3). Accordingly, in the above-described embodiment, as shown in Fig. 2, when the potential of the control signal  is  1 (O - <  1 <  0 ), the output impedance Z 3 of the slave input gate G 3 becomes equal to the output impedance Z 4 of the slave latching gate G 4 . Also, when the potential of the control signal  is  2 ( 0 <  2 < V cc ), the output impedance Z 1 of the master input gate G 1 becomes equal to the output impedance Z 2 of the master input gate G 2 . Therefore, at the output B, when 0 ≦  <  2 , the output O 2 of the master latching gate G 2 is provided as a "master" output while the output O 1 of the gate G 1 is provided as a "slave" output. Also, when  2 <  ≦ V cc , the output O 1 of the master input gate G 1 is provided provided as a "master" output while the output O 2 of the master latching gate G 2 is provided as a "slave" output. And at the output C, when O ≦  <  1 , the output O 3 of the slave input gate G 3 is provided as a "master" output while the output O 4 of the slave latching gate G 4 is provided as a "slave" output. Also, when  1 <  ≦ V cc the output O 4 of the slave latching gate G 4 is provided as a "master" output while the output O 3 of the slave input gate G 3 is provided as a "slave" output. Therefore, there is no case in which both of the outputs O 1 and O 3 are provided as "master" outputs. That is, the difficulty that the signal of the input A read by the master latch circuit is transmitted directly to the slave latch circuit output C will never occur. Thus, the above described master/slave latch circuit will never operate erroneously. In the above-described embodiment, the buffers B 1 and B 2 are employed. However, in the case where the output of the gates G 1 through G 4 are sufficiently large, a circuit as shown in Fig. 4 in which the buffers B 1 and B 2 are not employed may be used with the same effect as the above-described embodiment. In the above-described first embodiment, the output B of the master latch circuit is the connecting point of the output O 1 of the master input gate G 1 and the output O 2 of the master latching gate G 2 . Also, the output C of the slave latch circuit S is the connecting point of the output O 3 of the slave input gate G 3 and the output O 4 of the slave latching gate G 4 . However, the circuit may be so modified that, as shown in Fig. 5, the input of the master latching gate G 2 is the output B of the master latch circuit M, and the input of the slave latching gate G 4 is the output C of the slave latch circuit S. The first embodiment has been described with reference to the ordinary master/slave latch circuit. However, it may be modified as follows. The gates are replaced by clocked gates as shown in Figs. 6(a) and 6(b) to form a circuit as shown in Fig. 7 or 8, and the output impedance Z 1 through Z 4 of the clocked gates G 1 through G 4 are determined similarly as in the case of the above-described embodiment. The modification can provide the same effect as the above-described embodiment. Furthermore, transmission gates as shown in the Figs. 9(a) and 9(b) may be employed to form a circuit as shown in Fig. 10 or 11, and the output impedance Z 1 through Z 4 of the transmission gates G 1 through G 4 are determined similarly as in the case of the above-described embodiment. This modification also can provide the same effect as the above-described embodiment. In Figs. 6 and 9, reference characters P 1 through P 6 designate P-channel MOS transistors, and N 1 through N 6 N-channel MOS transistors. As is apparent from the above description, the master/slave latch circuit according to the invention is so designed that, when the voltage of the control signal  or  changes slowly in the range of 0V to V cc , the output of the reading gate in the master latch circuit and the output of the reading gate in the slave latch circuit may not be provided as "master" outputs simultaneously. Therefore, the master/slave latch circuit of the invention is free from the erroneous operation that the signal of the input A is transmitted through the output B of the master latch circuit directly to the slave latch circuit output C.

Claims: A latch circuit including: a master latch circuit (M) including a first reading gate (G 1 ) for receiving an input signal (A) and for providing an output signal (0 1 ) to a first connection point and a first latching gate (G 2 ) for receiving an input derived from said first connection point and for providing an output (0 2 ) to said first connection point; first means for controlling said master latch circuit (M) by a control signal () alternately to enable said first reading gate (G 1 ) and disable said first latching gate (G 2 ) and to disable said first reading gate (G 1 ) and enable said first latching gate (G 2 ) to thereby enable a first latching output (O 2 ) at said first connection point; a slave latch circuit (S) including a second reading gate (G 3 ) for receiving an input from said first connection point and for providing an output signal (0 3 ) to a second connection point and a second latching gate (G 4 ) for receiving an input derived from said second connection point and for providing an output signal (0 4 ) to said second connection point; second means for controlling said slave latch circuit (S) by said control signal () alternately to enable said second latching gate (G 4 ) and disable said second reading gate (G 3 ) and to disable said second latching gate (G 4 ) and enable said second reading gate (G 3 ) to thereby enable a second latched output (0 4 ) at said second connection point; characterized in that the output impedances (Z 1 to Z 4 ) of said gates (G 1 to G 4 ) satisfy the following condition when the magnitude of the voltage of said control signal () lies within a predetermined range,  <  <  2 , of which the lower end value ( 1 ) is the control signal voltage at which the output impedances (Z 3 , Z 4 ) of the second reading and latching gates (G 3 , G 4 ) transiently become equal and the upper end value ( 2 ) is the control signal voltage at which the output impedances (Z 1 , Z 2 ) of the first reading and latching gates (G 1 , G 2 ) transiently become equal, said condition being: Z 1 > Z 2 and Z 3 > Z 4 , whereby for any voltage value of said control signal (), said first reading gate (G 1 ) provides an output signal (0 1 ) to said first connection point at times other than when said second reading gate (G 3 ) provides said output signal (0 3 ) to said second connection point. A latch circuit as recited in claim 1, characterized in that when the magnitude of the voltage of the control signal () lies outside said range ( 1 -  2 ), the output impedances satisfy either the condition: Z 3 < Z 4 , Z 1 > Z 2 ( less than  1 ); or the condition Z 1 < Z 2 , Z 3 > Z 4 ( greater than  2 ). A latch circuit as recited in claim 1 or 2, characterized in that said first and second reading and latching cates (G 1 - G 4 ) are all clocked gates. A latch circuit as recited in claim 1 or 2, characterized in that said first and second reading and latching gates (G 1 - G 4 ) are all transmission gates.

Inventors: OKITAKA TAKENORI, SASADA TATSUYOSHI, OKITAKA, TAKENORI, SASADA, TATSUYOSHI, OKITAKA, TAKENORI MITSUBISHI DENKI K.K., SASADA, TATSUYOSHI MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1986
Main classification: H03K3
IPC codes: H03K3, G11C11