INTEGRATED INJECTION LOGIC OUTPUT CIRCUIT

Abstract: An I²L output circuit is described for supplying current (I D ′) to an output node (8) of a plurality of I²L blocks (7) in order to ascertain the logic condition at the output node. The output circuit includes a standard I²L gate (11) with an input connection (12) to the semiconductor region comprising both the lateral injector transistor collector electrode and the vertical switching transistor base electrode, and an output connection (13) from the semiconductor region comprising one of the collectors electrodes of the switching transistor. The gate output being used to control two identical current sources (T₁₁, T₁₂) one of which (T₁₁) supplies current to the input of a simple current mirror (T₁₃, T₁₄) having its output connected to the gate input. The other current source (T₁₂) being connected to the output node of the logic blocks. The provision of a current feedback loop around the I²L gate in this way ensures that, upon stabilisation, the current (I D ′) from the current source into the output node is very close in value to the internal injector current (I J ) of the I²L gate.

Description: Integrated injection logic (I²L) circuits are now well established in the art and widely publicised in the technical literature. Attention is drawn for example to articles in the IEE Journal of Solid-State Circuits, Vol SC-7, No 5 Oct 1972, at page 340 and page 346 and further to IBM Technical Disclosure Bulletin, vol. 19, no. 12, May 1977, p. 4635.The I²L concept is essentially based on inverting single or multiple collector transistors which are powered by direct minority carrier injection close to their emitter-base junctions (order of magnitude, one diffusion length). This bipolar logic concept has very short switching times. In addition it is suitable for the manufacture of extremely highly integrated large-scale logical circuits. Figure 1 shows a schematic diagram of a portion of a large scale integrated (LSI) circuit structure which contains an array of I²L cells 1, each bounded by isolation regions 2. A sectional view along line A-A is included as part of Figure 1. The equivalent circuit of one of the cells is shown in Figure 2. Briefly, layer 3 of highly doped N⁺ type material provides the substrate for the LSI structure. Each cell 1 is provided by a layer N1 of N⁻ type material epitaxially grown in the N⁺ substrate 3. Regions P1 and P2 of P type material are diffused into the layer N1 and several, in this case four, regions N2.1, N2.2, N2.3 and N2.4 of N⁺ type material are diffused into the region P2. A diffusion of highly doped N⁺ type material through the body of the cell into the underlying substrate 3 provides the ladder-like isolation structure 2 effectively isolating one cell from its neighbours. This cell structure provides a lateral semiconductor sequence P1/N1/P2 merged with a vertical semiconductor sequence N2/P2/N1. A silicon dioxide protection layer 4 overlays the surface of the LSI and is provided with apertures through which connections can be made to the two P type diffusions P1 and P2 and the four N type diffusions N2.1,N2.2, N2.3 and N2.4. The equivalent circuit of the basic cell is shown in Figure 2 with appropriate potentials applied so that it functions as an I²L four output gate. In this configuration, the lateral injector PNP transistor T1 supplies injector current I J to the four-collector vertical inverting NPN multiple transistor T2. The input to the gate is applied via input conductor 5 connected to the P2 region and the outputs taken from any or all of the four collector electrodes of the multiple transistor T2 via output conductors 6.1, 6.2, 6.3 and 6.4 connected respectively to the N2.1, N2.2, N2.3 and N2.4 regions. In operation, an effective short circuit at the input conductor 5, for example from the low level output (0.1 volts) of a preceding gate, causes the injector current I J through injector transistor T1 to be diverted to ground. The multiple electrode inverting transistor T2 consequently remains OFF and the potential on the output conductors (assuming that they are connected to appropriate loads) remain high (0.7 volts if connected as input to a succeeding gate). An effective open circuit at the input terminal 5, for example from the high level output (0.7 volts) of a preceding gate, diverts the injector current I J through injector transistor T1 into the base region of the inverter transistor T2 causing it to conduct. Consequently, the potential on the output conductors drop to the low level (0.1 volts if the loads are provided by further identical gates). This is the normal operation of I²L devices, with the output collectors being pulled from some voltage, generally the device Vbe, to ground, or vice-versa. Combinations of such gates are interconnected to provide logic functions at an output node in known manner. A difficulty with I²L circuits is that the inverting devices have a low breakdown voltage and thus cannot be used directly to drive other circuits which operate at comparatively higher voltages. There is a need therefore for an output circuit which is operable to supply the necessary current to an output node of an I²L circuit combination in order to generate an output signal indicative of the logic condition of the output node. A typical circuit which converts internal (on chip) I²L signal levels to external signal levels such as VTL is shown included as part of the circuit in Figure 3. In the figure a number of I²L logic blocks 7 are shown connected to an output node 8. In order to interrogate the logic condition of the I²L combination a current I D is required to be supplied to output node 8 being of a value close to that of the internal injection current I J of an I²L gate. Depending upon the logic state of the I²L combination, this current I D will either be diverted to ground, in which case output transistor T₃ with its base connected to node 8 will remain or be turned OFF, or alternatively diverted into the base of transistor T₃ in which case the transistor T3 will remain or be turned ON. The output transistor is a real on-chip transistor (ie not inverted) with a high beta and high collector/base, collector/emitter breakdown voltage. An output terminal 9 is connected to the collector of transistor T3 which may be operating from a relatively high supply voltage such as, in the case of VTL, 5 volts. This prior art circuit incorporates an I²L gate 10 comprising injector transistor T4 and multicollector inverting transistor T5 arrangement as described previously with reference to Figure 2. The gate 10 is not standard in that is has been modified by the provision of an additional connection shorting the base of the inverting transistor T5 to its collectors. There is no input connection to the gate which as a result of the modification functions as a rudimentary current mirror and approximately mirrors the injector current I J supplied by injector transistor T4 into the collectors of the inverting transistor T5. This current is further mirrored by conventional current mirror combination of transistors T6, T7 and T8 to provide the interrogation current I D at node 8. In practice, this circuit has several disadvantages which lead to a poorly defined current I D . First the NPN transistors comprising the inverting combination in the I²L gate providing the mirror function have very poor matching characteristics. The I²L gate has a large base drive current to the merged NPN transistors which is NPN Beta - inverse dependent. The PNP current mirror has collector voltages that are different and referenced to different power supplies. Thus the V ce for transistor T6 is 2V be ′s whereas the V ce for transistor T8 is the supply V-V be where V is the supply voltage. As the collector slope resistance of PNP transistors in typical technologies is low and temperature dependent, this reduces the accuracy of definition of the current I D . In practice with this circuit, the cumulative effect of these three disadvantages results in the value of I D being about 30% less than the value of the injector current I J . Finally, referencing to different power supplies reduces noise immunity of the circuit which is an additional disadvantage. According to the invention, a conversion circuit operable to supply interrogation current to an output node of a plurality of I²L blocks connected thereto in order to ascertain the logic condition of the blocks, includes an I²L gate having an input terminal and an output terminal, the output terminal being applied as control input to two substantially identical current sources, the resulting current from one of said sources being applied as input to a current mirror, the output of which is connected to the input of the I²L gate, and the current from the other of said sources being supplied as said interrogation current to said output node. The prior art as known to the Applicant has been described hereinbefore with reference to Figures 1 to 3 of the accompanying drawings, in which: Figure 1 shows schematically in plan view and in section a portion of an LSI circuit structure containing an array of I²L cells; Figure 2 shows the equivalent circuit of one of the cells contained in Figure 1; and Figure 3 shows a typical output circuit for converting internal I²L signal levels to external signal levels for driving circuits operating at higher voltages and currents such as for example VTL. Having therefore described the prior art and its disadvantages, a preferred embodiment of the present invention will now be described with reference to Figure 4 of the accompanying drawings. In this figure, an output converter circuit is required to supply as before an interrogation current to the output node 8 of logic combination 7. An output transistor T₃ is again shown connected to node 8 as in the prior art circuit described with reference to Figure 3, operable to supply output signals to output terminal 9 representing the logic state of the logic combination 7. The requirement of the output converter circuit of the present invention is that it should supply an interrogation current I D ′ much closer in value to the internal injector current I J of an I²L gate than the corresponding interrogation current I D of the prior art circuit. The converter circuit of Figure 4 includes a conventional I²L gate 11 consisting of a lateral injector transistor T₉ and a multicollector vertical inverting transistor T₁₀ as previously described herein. The input to the gate 11 is via conductor 12 connected to the common injector collector and inverter base region (corresponding to region P2 in Figure 2). The output is via conductor 13 connected to one of the collectors of multiple transistor T₁₀. It should be pointed out that a multi-conductor inverting transistor is not essential and that an I²L gate constructed so as to provide a single inverter transistor with only one collector output is all that is required. However since it is more likely that the available gates on an LSI layout will incorporate multi-collector devices it is felt that this structure is more representative of actuality. The output conductor 13 from the I²L gate is connected to the base electrodes of two identical, or substantially identical PNP transistors T₁₁ and T₁₂. The emitters of the two transistors are connected to a common supply rail V. The collector of transistor T₁₁ is connected as input to a conventional current mirror consisting of NPN transistors T₁₃ and T₁₄, the output of which is directly connected to the conductor 12, the input to the I²L gate 11. The collector of transistor T₁₂ is directly connected to the logic output node 8. In order to understand the operation of this circuit it is helpful to consider the situation where all the devices are in the process of turning on. Thus with injector current I J from injector transistor T₉ increasing, inverter transistor T₁₀ starts to turn ON. The fall in voltage on the gate output 13 causes current supply PNP transistors T₁₁ and T₁₂ to turn on equally to develop the current I D ′ in their respective collectors. The collector current I D ′ from transistor T₁₁ into the mirror input turns on NPN transistors T₁₃ and T₁₄ equally. The turning on of mirror transistor T₁₄ has the effect of robbing the injector current I J from the base of inverter transistor T₁₀ of the I²L gate 11 by an amount equal to the input current I D ′ to the mirror. The feed back loop thus described stabilises when substantially all the injector current is flowing into the mirror transistor T₁₄ and consequently with very little base current into inverting transistor T₁₀. Assuming a value for the beta of the PNP transistors T₁₁ and T₁₂ of 10 then the value of their combined base currents and the collector current of the inverter transistor is 2 I D ′/10. Assuming also a value for the beta of the NPN inverting transistor T₁₀ of 6 then the base current required to sustain the circuit is only I D ′/30. Accordingly at stability the value of the interrogation current I D ′ into the output node 8 is only about 3% less than the injector current I J . This represents a substantial improvement in accuracy over the value of the corresponding interrogation current I D of the prior art circuit which is about 30% less than the injector current I J . It should be noted that the collector voltages of the two current supply transistors T₁₁ and T₁₂ are to all intents and purposes identical. Thus the V ce of transistor T₁₁ is V-V be (T₁₃) whereas the V CE of transistor T₁₂ is V-V be (T₃). The circuit can be improved by including emitter resistors for the PNP transistors T₁₁ and T₁₂ and by using Darlington outputs. Although the conversion circuit according to the present invention has one more active device, in practice it takes up only as much or even less space since it has one less PNP transistor which take up twice or three times the area as a NPN depending upon the technology employed. Finally, the injector current of the present circuit can be changed by up to two decades as may be required for various applications without affecting its operation. In summary therefore, the conversion circuit has the following features: 1. the circuit tends to be independent of injector current value; 2. the circuit provides more drive than the described prior art conversion circuit; 3. the circuit is smaller than the prior art circuit; and 4. the circuit requires about half the power supply voltage of the prior art circuit.

Claims: 1. An I²L output circuit operable to supply interrogation current to an output node (8) of a plurality of I²L blocks (7) connected thereto in order to ascertain the logic condition of the blocks, said circuit including an I²L gate (11) having an input terminal (12) and an output terminal (13), the output terminal being connected as control input to two substantially identical current sources (T₁₁, T₁₂), characterised in that, in operation, the resulting current (I D ′) from one of said sources (T₁₁) is applied as input to a current mirror (T₁₃, T₁₄), the output of which is connected to the input of the I₂L gate and the current from the other of said sources (T₁₂) is supplied as said interrogation current (I D ′) to said output node. 2. An I²L output circuit as claimed in claim 1, in which said output node is further connected to the control input of an output device (T₃) operable in response to application of said interrogation current to said output node to generate at its output (9) a signal, indicative by its level of the prevailing logic condition at said output node. 3. An I²L output circuit as claimed in claim 1 or claim 2, in which said two current sources comprise first and second PNP transistors, the emitter electrodes of which are connected to a common supply voltage, the base connections of which are directly connected together and to said output terminal of said I²L gate and in which the collector of the first PNP transistor is connected to the input to the current mirror and the collector of the second PNP transistor is connected to the output node. 4. An I²L output circuit as claimed in claim 3, in which the current mirror comprises first and second NPN transistors connected in common emitter mode to a reference potential, the first transistor having its collector electrode shorted to its base electrode and to the base electrode of the second transistor, the collector of said first PNP transistor being connected to the collector of said first NPN transistor and the collector of the second NPN transistor being connected to the input terminal of said I²L gate. 5. An I²L output circuit as claimed in claim 4, in which the emitter electrodes of the first and second PNP transistors are directly connected to the common supply voltage and the emitter electrodes of the first and second NPN transistors are directly connected to the reference potential. 6. An I²L output circuit as claimed in any preceding claim, in which said I²L gate comprises merged complementary transistors providing a PNP lateral injector transistor and an NPN vertical switching transistor having one or more collectors, an injector pad connected to the emitter of the injector transistor, a voltage reference pad connected to the common base of the injector transistor and emitter of the switching transistor, an input pad connected to the common collector of the injector transistor and base of the switching transistor and one or more output pads connected respectively to said one or more collectors of the switching transistor.

Inventors: NEWMAN, ERIC LEWIS
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H03K19