PROGRAMMABLE READ ONLY MEMORY OPERABLE WITH REDUCED PROGRAMMING POWER CONSUMPTION

Abstract: A programmable read only memory having an improved writing circuit is disclosed. The writing circuit includes a first field effect transistor of a conductivity type opposite to the conductivity type of a second field effect transistor constituting a memory cell. A programming current is supplied via the first transistor to the second transistor. The first transistor represents its load characteristic having a constant current region. A programming power consumption is thereby reduced.

Description: BACKGROUND OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory or a programmable read only memory in which each of memory cells is composed of an insulated gate field effect transistor having a floating gate, and more particularly to a writing or programming circuit in such a memory). A writing circuit in a semiconductor memory of the above-mentioned type includes a writing transistor connected in series to selected one of memory cells to supply a programming voltage and current thereto. Such a device which is a memory device according to the preamble of claim 1 is disclosed in EP-A-112 078. In this prior art, the writing transistor and the memory cell transistor are of the same conductivity or channel type. Therefore, the source of the writing transistor is connected to the memory cell transistor. The memory cell transistor is supplied with the programming voltage and current, so that electrons or holes are injected into the floating gate of the memory cell transistor. A programmed memory cell is thus obtained. The programmed memory cell continues to be supplied with a relatively high voltage responsive to the programming voltage for a programming period. For this reason, a channel breakdown occurs in the memory cell transistor to lower the potential at the connection point of the writing transistor and the memory cell transistor. In other words, the programmed memory cell has a negative resistance characteristic. The source potential of the writing transistor is thereby decreased to increase the current flowing through the writing transistor and the memory cell transistor. Thus, the semiconductor memory including prior art writing circuit consumes a considerably large programming power. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide a semiconductor memory including an improved writing circuit. Another object of the present invention is to provide a semiconductor memory in which a programming power consumption is reduced. These objects are achieved by a semiconductor memory as claimed in claim 1; the dependent claims are related to further embodiments of the invention. In the present invention, the selected memory cell is thus supplied with the programming current through the second (i.e., writing) transistor of the opposite conductivity type to that of the memory cell transistor. Such a writing transistor represents a load characteristic having a constant current region. Therefore, even if the channel breakdown occurs in the programmed memory cell, the current flowing through the memory cell is limited. The programming power consumption is thereby reduced remarkably. In a preferred embodiment, the writing transistor is driven by a signal having an amplitude that is approximately equal to a potential difference between a programming voltage and a gate selection voltage of the selected memory cell in a data read operation. The constant current region in the load characteristic of the writing transistor is thereby broadened. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a circuit diagram representing a prior art programming operation; Fig. 2 is a graph showing a voltage-current characteristic of the circuit shown in Fig. 1; Fig. 3 is a circuit diagram representing a programming operation of the present invention; Fig. 4 is a graph showing a voltage-current characteristic of the circuit shown in Fig. 3; Fig. 5 is a diagram showing a preferred embodiment of the present invention; Fig. 6 is a circuit diagram of a writing signal producing circuit shown in Fig. 5; and Fig. 7 is a circuit diagram of a read-out circuit shown in Fig. 5. DETAILED DESCRIPTION OF THE PRIOR ART Referring to Figs. 1 and 2, a programming operation according to prior art will be described in order to facilitate the understanding of the present invention. A memory cell MC is composed of a transistor Q₁ of an N-channel type having a floating gate 1-4. When this memory cell is selected or designated, a transistor Q₂ of the same channel (N-channel) type as the transistor Q₁ is connected in series to Q₁. A writing signal W is supplied to the gate 2-3 of the transistor Q₂, the drain 2-2 of which is connected to a terminal 3 supplied with a programming voltage V pp . The writing signal W depends on the data to be programmed and thus takes Vpp level when the data is "1" for example and a zero volt when it is "0". The source 1-1 of the memory cell transistor Q₁ is grounded and the control gate 1-3 thereof is supplied with a selection signal X from a decoder (not shown). The drain 1-2 of the transistor Q₁ is connected to the source 2-1 of the transistor Q₂, this connection point being represented by "a". When the programming is carried out with respect to the memory cell MC, the programming voltage Vpp is applied to the terminal 3 and the writing signal W assumes the Vpp level to turn the transistor Q₂ ON. The voltage V a at the point a takes a high voltage responsive to the Vpp voltage in consequence. The selection signal X is in the Vpp level. Thus, the drain 1-1 and the control gate 1-3 of the memory cell transistor Q₁ receives the high voltage, so that electrons are injected into the floating gate 1-4 of Q₁. The floating gate 1-4 is thereby charged to a negative potential to increase the threshold voltage of the transistor Q₁. Since the transistor Q₂ is of an N-channel type, it has a linear load characteristic represented by line 30 in Fig. 2. In the graph of Fig. 2, the abscissa is the voltage V a at the point a and the ordinate is the current I₁ flowing through the transistors Q₁ and Q₂. On the other hand, the voltage-current characteristic of the memory cell transistor Q₁ before programming is represented by line 10 in Fig. 2. Accordingly, when the voltage V a at the point a becomes larger than the voltage V w1 represented as an intersection of the lines 10 and 30, the transistor Q₁ is supplied with a current I W1 to inject electrons into the floating gate 1-4 of Q₁. A programmed memory cell is thus obtained. When the memory cell transistor Q₁ is brought into the programmed condition, its voltage-current characteristic is changed to line 20 shown in Fig. 2. That is, since the floating gate assumes a negative potential and the drain 1-2 is applied with a high voltage, a high electric field occurs near the drain 1-2 to cause a channel breakdown in the transistor Q₁. In other words, the programmed memory cell transistor Q₁ represents a negative resistance at a voltage RV. As a result, the voltage V a at the point a is lowered to a value V w2 and the current I₁ is increased to a value I W2 . The current value I W2 is considerably larger than the value I W1 . The power consumption (I W2 x V pp ) at this time is a part of the programming power consumption. Thus, a semiconductor memory including a prior art writing circuit consumes a large programming power. DETAILED DESCRIPTION OF THE INVENTION Fig. 3 shows a circuit diagram representing a programming operation of the present invention. The same constituents as those shown in Fig. 1 are denoted by like references. In the present invention, the memory cell transistor Q₁ is supplied with a programming current through a transistor Q₃ that is of an opposite conductivity type to the transistor Q₁, i.e., a P-channel type. Therefore, the source 3-1 of Q₃ is connected to the terminal 3 along with its substrate electrode, and the drain 3-2 thereof is connected to the drain 1-2 of Q₁. The connection point of the drains of the transistors Q₁ and Q₃ is represented by "b". Moreover, the transistor Q₃ is driven by a writing signal W' which has an amplitude that is approximately equal to the potential difference between the programming voltage V pp and a selection voltage supplied to the memory cell in a read-out operation. For this purpose, a P-channel transistor Q₅ and an N-channel transistor Q₄ are connected in series between terminals 3 and 4, and the connection point therebetween is connected to the gate 3-3 of the transistor Q₃. A writing control signal Wc responsive to an input data is supplied in common to the gates of Q₄ and Q₅. The terminal 4 is supplied with a voltage of a V cc level. This voltage level is substantially equal to the selection level supplied to the memory cell in the read-out operation. Since the transistor Q₃ is of a P-channel type and the source 3-1 thereof is connected to the terminal 3, Q₃ represents a constant current characteristic when its gate-source voltage V GS is smaller in absolute value than its source-drain voltage V DS and a resistive characteristic when V GS is larger in absolute value than V DS . Therefore, the load characteristic of the transistor Q₃ is completely different from that of the transistor Q₂ (Fig. 1) and is shown by a line 40 in Fig. 4. The abcissa of the graphs in Fig. 4 is the voltage V b at the point b and the ordinate thereof is the current I₂ flowing through the transistors Q₁ and Q₃. The voltage-current characteristics of the memory cell transistor Q₁ before programming and after it are not changed, as represented by lines 10 and 20 in Fig. 4, respectively. In the programming, the point b therefore assumes a voltage V W3 which is represented as an intersection of the lines 10 and 40 and the programming current I₂ having a value I W3 flows through the transistor Q₁. It should be noted that the transistor Q₃ is supplied at its gate 3-3 with the V cc level, not with the ground level. Therefore, the constant current characteristic region of the transistor Q₃ is broadened, the current value I W3 required for the programming is supplied surely to the transistor Q₁. The programmed memory cell transistor Q₁ represents the negative resistance as mentioned hereinbefore, so that the voltage V b is lowered from the value V W3 to a value V W4 . However, the constant current characteristic of the transistor Q₃ maintains the current I₂ flowing through the transistors Q₁ and Q₃ at the value I W3 . The programming power consumption is thereby reduced remarkably. The writing control signal WC takes OV as its low level and V pp level as its high level, and the writing signal W' takes V cc level as its low level and the V pp level as its high level. Therefore, the transistors Q₄ and Q₅ operate as a level conversion circuit. Fig. 5 shows a semiconductor memory according to one embodiment of the present invention, in which the same constitutents as those shown in Fig. 3 are denoted by like references. Each of a plurality of N-channel transistors Q₁₁ to Q NM has a floating gate and constitutes a memory cell. These transistors Q₁₁ to Q NM are arranged in rows and columns to form a memory cell array 62. The drains of the memory cell transistors disposed in the same column are connected in common to one of digit lines D₁ to D M , and the control gates of the memory cell transistors disposed in the same row are connected in common to one of word lines W₁ to W N . The sources of the transistors Q₁₁ to Q NM are connected to a reference potential (a ground potential, in this embodiment). The digit lines D₁ to D M are connected to a circuit node N through N-channel switching transistors Q₂₀₁ to Q 20M , respectively. Row address signals RA₀ to RA i are supplied through row address terminals 61-0 to 61-i to a row decoder 63, and column address signals CA₀ to CA j are supplied through column address terminals 60-0 to 60-j to a column decoder 64. The row decoder 63 applies a selection level to one of row selection signal X₁ to X N . One of the word lines W₁ to W N is thereby energized. The column decoder 64 raises one of column selection signal Y₁ to Y M to the selection level. As a result, the associated one of the transistors Q₂₀₁ to Q 20M is turned ON to energized one of the digit lines D₁ to D M . The memory cell corresponding to the row and column address signals CA and RA is thus selected. A transistor Q₃ of an opposite conductivity type as the memory cell transistor (i.e., a P-channel type) is provided between the circuit node N and a terminal 3 in accordance with the present invention. The transistor Q₃ is driven by transistors Q₄ and Q₅ connected in series between the terminals 3 and 4. The writing control signal WC supplied to the gates of Q₄ and Q₅ is produced by a writing signal producing circuit 66. As shown in Fig. 6, in the circuit 66, a write-enable signal WE supplied thereto is inverted by an inverter 661 and the inverted signal is supplied through an N-channel transistor Q₆₆₁ to the gates of a P-channel transistor Q₆₆₃ and an N-channel transistor Q₆₆₄. The transistors Q₆₆₃ and Q₆₆₄ are connected in series between the terminal 3 and the ground, and the signal WC is produced the connection point thereof. The signal WC is fed back to a P-channel transistor Q₆₆₂. Accordingly, the writing signal producing circuit 66 determines the level of the writing control signal WC in response to the level of the write-enable signal WE. The signal WC takes either one of OV and V pp . This signal is converted into the signal W' taking either one of V cc and V pp by the transistors Q₅ and Q₄. V pp is larger in absolute value than V cc . The write-enable signal WE is produced by a writing control circuit 65. This circuit 65 responds to a programming control signal PC supplied to a terminal 50 and carries out a programming operation or a read-out operation. In the programming operation, the terminal 3 is applied with the V pp level and the terminal 50 is supplied with the programming signal having a high level, for example. As a result, the writing control circuit 65 determines the level of the signal WE in response to an input data supplied to a terminal 69. The circuit 65 further supplies a signal RE having a level that inactivates a read-out circuit 67. When the signal WE responsive to the input data assumes the high level, the transistor Q₃ is supplied with V cc level and thus turned ON. On the other hand, in response to the row and column address signals CA and RA, the row and column decoder raise ones of the row and column selection signals X and Y to the selection level. This selection level takes the V pp level in the programming operation. The programming voltage and current are thus supplied through the transistor Q₃ to the selected memory cell to carry out the programming thereto. The programming power consumption in this operation is remarkably small as explained with reference to Figs. 3 and 4. In the read-out operation, the terminal 3 is connected to the terminal 4 to receive the V cc level, and the low level signal PC is supplied to the terminal 50. The writing control circuit 65 changes the signal WE to a level that maintains the transistor Q₃ in an off-state and produces a read-enable signal RE to the read-out circuit 67. One of the row selection signals X and one of column selection signals Y are raised to a selection level in response to address signals PA and CA. The selection level at this time assumes about V cc level since the terminal 3 receives the V cc level. When the programmed memory cell is selected, this cell is maintained in the off-state, since its threshold voltage is higher than the selection level of the signal X. To the contrary, when the unprogrammed memory cell is selected, it is turned ON to lower the potential at the node N. The potential at the node N is supplied to the read-out circuit 67 as a cell data. As shown in Fig. 7, the read-out circuit 67 includes N-channel transistors Q₆₇₃ and Q₆₇₄ connected in a differential form. The gate of the transistor Q₆₇₃ is connected to the circuit node N through an N-channel transistor Q₆₇₁, and the gate of the transistor Q₆₇₄ is supplied with a reference voltage V REF . An N-channel transistor Q₆₇₅ operating as a current source is connected to the source connection point of Q₆₇₃ and Q₆₇₄. P-channel transistors Q₆₇₆ and Q₆₇₇ constitute a current mirror load, and from the connection point of the transistors Q₆₇₇ and Q₆₇₄ a read-out data DO supplied to a data output circuit 68 (Fig. 5) is derived. The transistors Q₆₇₁ and Q₆₇₅ are supplied at their gates with the read-enable signal RE. The signal RE takes the low level in the programming operation to inactivate the read-out circuit 67 and assumes the high level in the read-out operation to turn the transistors Q₆₇₁ and Q₆₇₅ ON. The circuit 67 is thereby activated. When the programmed memory cell is selected, the circuit node N is disconnected from the ground. However, a P-channel transistor Q₆₇₂ is provided, and therefore the gate of the transistor Q₆₇₃ receives a high voltage. When the unprogrammed memory cell is selected, the potential at the node, i.e. the potential at the gate of the transistor Q₆₇₃, takes a resistance divided voltage determined by the transistor Q₆₇₂, the switching transistor Q 20h (h = l to M) and the memory cell transistor. The reference voltage V REF supplied to the transistor Q₆₇₄ is selected to an intermediate level between the above-mentioned high voltage and the resistance divided voltage. As a result, the read-out data DO takes the high level or the low level in response to the programmed cell or the unprogrammed cell, respectively. The read-out data DO is supplied to the data output circuit 68, so that an output data D OUT is derived from the terminal 69. The terminal 69 is thus used as a data input/output terminal. The semiconductor memory may be modified, for example, in that a plurality of terminals 69 can be provided.

Claims: A semiconductor memory comprising a plurality of memory cells (Q11-QNM) each including a first field effect transistor (Q1) of a first conductivity type having a floating gate (1-4), means (64, 64, Q201-Q20M) for selecting at least one of said memory cells in response to address information (PA, CA), and means activated in a programming operation for supplying a programming current to the selected memory cell to write data into said first field effect transistor (Q1) of the selected memory cell, said supplying means including a second field effect transistor through which said programming current flows, characterized in that said second field effect transistor (Q3) included in said supplying means is of a second conductivity type opposite to said first conductivity type. The memory as claimed in claim 1 , characterized in that said second field effect transistor (Q3) is driven by a signal (W') having a voltage amplitude that is approximately equal to the voltage difference between a programming voltage (Vpp) and a gate voltage (Vcc) supplied to the selected memory cell in a read-out operation. The memory as claimed in claim 2 , characterized in that said supplying means further includes a first terminal (3) supplied with said programming voltage (Vpp), a second terminal (4) supplied with said gate voltage (Vcc), and means (Q4, Q5) coupled between said first and second terminals (3, 4) and responsive to a writing signal (WC) for driving said second field effect transistor (Q3) with said signal (W') having a voltage amplitude changing between said programming voltage (Vpp) and said gate voltage (Vcc), and that said second field effect transistor (Q3) having a source coupled to said first terminal (3). The memory as claimed in claim 3 , characterized in that said driving means comprises a third field effect transistor (Q4) of said first conductivity type connected between said second terminal (4) and the gate of said second field effect transistor (Q3) and a fourth field effect transistor (Q5) of said second conductivity type connected between said first terminal (3) and the gate of said second field effect transistor (Q3), said writing signal (WC) being supplied in common to gates of said third and fourth field effect transistors (Q4, Q5). The memory as claimed in claim 1, 2, 3 or 4, further comprising a plurality of word lines (X1-XN) and a plurality of digit lines (D1-DM), each of said first field effect transistors (Q1) further having a control gate (1-3) connected one of said word lines (W) and a source-drain current path connected between one of said digit lines (D) and a reference potential point, and said selecting means including a first decoder (63) energizing one of said word lines (W) in response to a first set of address signals (RAO-RAj), a circuit node (N), a plurality of gate transistors (Q201-Q20M), each of which is connected between said circuit node (N) and an associated one of said digit lines (D), and a second decoder (64) turning ON one of said gate transistors (Q201-Q20M) in response to a second set of address signals (CAO-CAj).

Inventors: WATANABE, TAKESHI
Applicants: NEC CORPORATION
Application year: 1986
Main classification: G11C16
IPC codes: G11C16, G11C17