MOSFET AC SWITCH

Abstract: A solid state relay is responsive to a control signal and is used with an impedance load and a source of alternating electrical power. The solid state relay is used to connect and disconnect the load from the source of alternating electrical power. The solid state relay turns on in response to a control signal and to a substantially zero voltage crossing of the alternating electrical power of the source. The solid state relay turns off in response to the control signal and to a substantially zero current crossing of the alternating electric­ al power of the source.

Description: The present invention relates in general to solid state relays and has particular application to solid state relays and AC switches using MOSFET devices. Compared to electromechanical relays, solid state relays have several advantages. These advantages include a longer lifetime, the elimination of contact bounce, and low voltage turn on that reduces both the electromagnetic interference and stress on the attached load. Typical prior art solid state relays utilize triac and SCR components for the switching device. These components when used in a solid state relay have a number of disadvantages. These solid state relays usually are very costly to manufacture, have high leakage current, and are prone to false triggering. Also prior art solid state relays are not readily compatible for use with high impedance logic circuits and CMOS logic. One prior art relay using a triac as a switching device and having the features of the preamble of claim 1 is shown in US-A-4334184. The triac is arranged to connect and disconnect a load and a source of power in response to a control signal provided by a touch switch. The load is switched on (connected) at the zero crossing of the voltage passing through the load and switched off (disconnected) at zero crossing of the current. It is a primary object of the present invention to provide a novel solid state relay especially for low power AC applications. It is another object of the present invention to provide a solid state relay which prevents false triggering and minimizes switch dissipation. It is yet another object of the present invention to provide a solid state relay which is readily compatible with high impedance logic circuit and CMOS logic. It is another object of the present invention to provide a solid state relay which turns on only at a zero voltage crossing point of the alternating source voltage. It is a further object of the present invention to provide a solid state relay which turns off only at a zero current crossing point of the alternating source current. The present invention provides a solid state relay responsive to a control signal (D) and for use with an impedance load and a source of alternating electrical power, said solid state relay comprising: switch means in series with the load for connecting and disconnecting the source and the load said source being operatively connected across the series connection of the switch means and the load means for controlling the switch means, said control means being operatively connected to the switch means and being responsive to the control signal and to zero voltage crossing of said alternating electrical power of said source, whereby to connect the load to the source; and current sensing means for sensing current through said switch means and for outputting a signal indicative of zero-crossing of current flow through said switch means for causing said switch means to disconnect the source from the load; characterised in that: said switch means comprises a first field effect transistor operatively connected in a source-to-source configuration with a second field effect transistor, the drain of said first field effect transistor being connected to said source and the drain of said second field effect transistor being connected to said load; said current sensing means comprises: a third field effect transistor having its drain and gate connected, respectively, to the drain and gate of the first field effect transistor and having its source connected through a first resistance (RS1) to the source of the first field effect transistor, for sensing current through said first field effect transistor and a first differential amplifier (Q1) having its input connected across said first resistance (RS1) for outputting a first current sensing signal indicative of zero-crossing of current flow through said first field effect transistor; a fourth field effect transistor having its drain and gate connected, respectively, to the drain and gate of the second field effect transistor and having its source connected through a second resistance (RS2) to the source of the second field effect transistor, for sensing current through said second field effect transistor and a second differential amplifier (Q2) having its input connected across said second resistance (RS2) for outputting a second current sensing signal indicative of zero-crossing of current flow through said second field effect transistor; and said control means is arranged to receive the first and second current sensing signals and operates to turn off the first and second field effect transistors when the control means receives said first and second current sensing signals indicating zero-crossing of current flow in said first and second field effect transistors and when the control signal indicates turn off, said turning off of said first and second field effect transistors causing the load to be disconnected from the source. The switching means preferably comprise two MOSFET devices wired in series in a source to source configuration. The load is connected in series with the MOSFET devices and the total series circuit is connected across the AC source. A portion of the circuitry in the solid state relay operates to turn on the solid state relay in response to the control signal and to a zero voltage crossing of the alternating electrical power of the source. Another portion of the circuitry of the solid state relay provides for turning off the solid state relay responsive to the control signal and to a zero current crossing of the alternating electrical current flowing through the load. Brief Description of the Drawings The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention together with further objects and advantages may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which: Figure 1 is a general block diagram of the solid state relay. Figure 2 is a graph comparing the timing of various signals inthe solid state relay. Figure 3 is a more specific block diagram with circuit elements of the Figure 1 diagram. Figure 4A and 4B are graphs of signals in the Figure 3 circuit. Description of Preferred Embodiment The novel solid state relay of the present invention is shown in general block diagram form in Figure 1. An alternating power source 10 is connected between a hot node A and a neutral node N. An impedance load 12 is connected between node B and node N. A first switch 14 is connected in series with a second switch 16 at common node C and the combination is connected between nodes A and B and in series with the load 12. Thus, when the first and second switches 14 and 16 are closed the load 12 is connected across the alternating power source 10. A floating power supply 18 is referenced to node C and provides a voltage to power she control circuit 20. The control circuit 20 controls the first and second switches 14 and 16 on output line 22. The control circuit 20 receives a control signal on input line 24 from terminal D. This control signal typically may be of the type from CMOS logic circuitry. The control circuit 20 monitors the voltage across switches 14 and 16 through lines 26 and 28 which are connected to nodes A and B respectively. Also the control circuit 20 monitors the current through switch 14 by lines 30 and 32 and monitors the current through switch 16 by lines 34 and 32. The control means 20 turns on switches 14 and 16 thereby connecting the load to the alternating source 10 in response to the control signal received at terminal D and to a substantially zero voltage crossing of the alternating electrical power of the source 10. The control means 20 turns off switches 14 and 16 in response to the control signal received on terminal D and to a substantially zero current crossing of the alternating electrical power source 10. This operation of the circuit is shown diagrammatically in Figure 2. Data signal 36 may be a typical logic signal operating between two low voltage levels. For one voltage level the signal indicates an off state for the solid state relay and for a second voltage level the signal indicates an on state for the solid state relay. Curve 38 illustrates the varying voltage of the power source 10. At time point 40 the solid state relay receives a data signal 36 indicating that the solid state relay is to turn on. However, the solid state relay does not turn on until time point 41 where the voltage 38 of the power source 10 crosses the zero axis. At time point 41 the solid state relay turns on connecting the load 12 to the source 10. Curves 42 and 44 show the voltage across the load 12 and the current through the load 12, respectively. To illustrate the operation of the present invention the load 12 has been chosen to have a current which is out of phase with the voltage. At time point 46 the data signal 36 instructs the solid state relay to turn off. However, the solid state relay does not turn off until time point 48 when the current through the load 44 crosses the zero point. Figure 3 is a more detailed block diagram of the present invention including circuit elements within each of the blocks. In the preferred embodiment the first switch 14 and the second switch 16 are field effect transistors (FET) connected in a source to source configuration. The sources of FETs 14 and 16 are connected to node C, the drain of FET 14 is connected to node A and the drain of FET 16 is connected to node B. The gate of FET 14 is connected to the gate of FET 16. First and second current sensing circuits 50 and 52 are provided. In current sensing circuit 50 FET 54 has its drain connected to the drain of FET 14 and its gate connected to the gate of FET 14. The source of FET 54 is connected to the source of FET 14 through series resistor RS1. When the solid state switch is closed, FET 14 is conducting and the voltage drop across FET 14 is approximately one-half volt for an alternating power source of 110 volts due to the internal resistance of FET 14. Therefore, the voltage drop across RS1 is also approximately one-half volt. Amplifier Q1 measures the voltage across RS1 thereby measuring the current flowing through FET 14. An output signal from amplifier Q1 appears at the output 56 of the current sensing circuit 50 during the positive half cycle of the AC signal from the source 10 when the solid state relay is on. Operation of the second current sensing circuit 52 is similar to the operation described for the first current sensing circuit 50 and the output signal from Q2 which measures the voltage across RS2 and, therefore the current through FET 16, provides an output signal on the output 58 of the second current sensing circuit 52 during the negative half cycle of the AC signal from the source 10. FETs 54 and 60 provide high voltage protection for amplifiers Q1 and Q2. Voltage sensing circuit 62 is provided and has first and second resistors R1 and R2 connected between node A and node X, and between node B and node X, respectively. The floating power supply 18 provides a reference voltage to node X through R3. Node X is also connected to the gate of FET 64 which has its source connected to the floating power supply 18 and has its drain connected to an output terminal 66. Logic circuit 68 is provided and in the preferred embodiment has an OR gate 70 which has its inputs connected to terminals 56 and 58 of the first and second current sensing circuits 50 and 52, respectively. The output of the OR gate 70 is connected to one input of an AND gate 72 and the output of AND gate 72 is connected one input of an OR gate 76. The other input of OR gate 76 is connected to an optical isolator 77 which receives the control signal from terminal D. The output of OR gate 76 is connected to one input of AND gate 78. The other input of AND gate 78 is connected to the output of OR gate 80. One input of OR gate 80 is connected to terminal 66 of the voltage sensing circuit 62 for receiving a voltage sensing signal and the other input of OR gate 80 is connected to the output AND gate 78. Similarly, the other input of AND gate 72 is connected to the output of AND gate 78. The output of AND gate 78 is also connected to the gates of FET 54 and 60 and in the first and second current sensing circuits 50 and 52, as well as, to the gates of the first and second FET switches 14 and 16. The overall operation of the circuit will now be described. When the solid state relay is off, FETs 14, 16, 54 and 60 are all also in the off state. The AC signal from the source 10 across FETs 14 and 16 is blocked because of internal diodes D1 and D2. When the relay is on all four FET devices 14, 16, 54 and 60 are on and FETs 14 and 16 therefore create a short circuit connecting the load 22 to the source 10 across nodes A and N. The relay turns on only at substantially zero voltage crossing of the source 10 and the relay turns off only at substantially zero current crossings of the source 10. When the relay is in the on state amplifier Q1 outputs a signal during the positive half cycle of the AC signal of the source 10 and amplifier Q2 outputs a signal during the negative half cycle of the source 10. Amplifier Q1 turns off only when the voltage drop across RS1 approaches zero, that is when the current flow through FET 14 approaches zero. Similarly, amplifier Q2 turns off only at the same time as amplifier Q1, that is when the voltage across RS2 approaches zero which is when the current through FET 16 approaches zero. FET 54 and 60 can be turned on only when the output of AND gate 78 is high. When the outputs of amplifiers Q1 and Q2 drop to a low the input to AND gate 72 through OR gate 70 becomes low thereby providing an output from AND gate 72 which is low if the input to OR gate 76 from the optical coupler 77 is low, in addition to the signal from the output from AND gate 72 being low. In this case the output of OR gate 76 will be low. If the input to AND gate 78 is low from OR gate 76 then the output of AND gate 78 will be low, thereby causing FET 54, 60, 14 and 16 to turn off. The input to OR gate 76 from the optical coupler 77 is low only when the data input on terminal D to the control circuit 20 is low, thereby indicating that the relay should turn off. When the relay is off it can be turned on only at the zero voltage crossing. The voltage appearing at node X in the voltage sensing circuit 62 is a full wave rectification of the AC signal from the source 10. This is formed by the voltage divider network R1 and R2 connected across nodes A and B. Thus, the voltage at node X is a sign wave of whose amplitude is about one-fifth the value of the AC signal in phase with the AC signal. The voltage across the gate and source of FET 64 is a whole wave rectified sign wave which is positive going. See Figures 4a and 4b. The voltage across the gate and source of FET 64 (V xc in Figure 4b) is viewed by comparing the voltage at node C to Node X (v c in Figure 4a) and the voltage at node X to node N (v x in Figure 4a). FET 64 is turned on except for the brief period (in the preferred embodiment approximately 200 microseconds) when the voltage from the gate to source of FET 64 drops to substantially the zero crossing point (V zc in Figure 4b). At this time the input to OR gate 80 connected to the terminal 66 goes high. At all other times the input to OR gate 80 from terminal 66 remains low. When the relay is initially off the output of AND gate 78 is at a low and therefore the only time that the output of OR gate 80 can go high is when the input to OR gate 80 from FET 64 goes high. This time is when FET 64 turns off at the substantially zero voltage crossing point of the source 10. When FET 64 is turned off one input to AND gate 78 is high. And gate 78 must receive not only the signal from or gate 80 as a high at the zero voltage crossing point but also must receive a signal through OR gate 76 from the optical coupler 77. The signal from the optical coupler 77 is received only when the control signal from terminal D is received indicating for the relay to turn on. When both inputs to AND gate 78 are high the relay turns on. Once the switch is turned on the output of AND gate 78 is coupled back to the inputs of OR gate 80 and AND gate 72 to hold the relay on until the data input on terminal D goes low and the outputs of amplifiers Q1 and Q2 go low at the substantially zero current crossing point.

Claims: A solid state relay responsive to a control signal (D) and for use with an impedance load (12; 22) and a source (10) of alternating electrical power, said solid state relay comprising: switch means (14,16) in series with the load (12; 22) for connecting and disconnecting the source (10) and the load (12; 22) said source being operatively connected across the series connection of the switch means (14,16) and the load (12; 22); means (20) for controlling the switch means, said control means being operatively connected to the switch means (14,16) and being responsive to the control signal and to zero voltage crossing of said alternating electrical power of said source (10), whereby to connect the load (12; 22) to the source (10); and current sensing means (50,52) for sensing current through said switch means (14,16) and for outputting a signal indicative of zero-crossing of current flow through said switch means (14,16) for causing said switch means to disconnect the source from the load; characterised in that: said switch means comprises a first field effect transistor (14) operatively connected in a source-to-source configuration with a second field effect transistor (16), the drain of said first field effect transistor (14) being connected to said source (10) and the drain of said second field effect transistor (16) being connected to said load (12; 22); said current sensing means comprises: a third field effect transistor (54) having its drain and gate connected, respectively, to the drain and gate of the first field effect transistor (14) and having its source connected through a first resistance (RS1) to the source of the first field effect transistor (14), for sensing current through said first field effect transistor (14) and a first differential amplifier (Q1) having its input connected across said first resistance (RS1) for outputting a first current sensing signal indicative of zero-crossing of current flow through said first field effect transistor (14); a fourth field effect transistor (60) having its drain and gate connected, respectively, to the drain and gate of the second field effect transistor (16) and having its source connected through a second resistance (RS2) to the source of the second field effect transistor (16), for sensing current through said second field effect transistor (16) and a second differential amplifier (Q2) having its input connected across said second resistance (RS2) for outputting a second current sensing signal indicative of zero-crossing of current flow through said second field effect transistor (16); and said control means is arranged to receive the first and second current sensing signals and operates to turn off the first and second field effect transistors when the control means receives said first and second current sensing signals indicating zero-crossing of current flow in said first and second field effect transistors (14,16) and when the control signal indicates turn off, said turning off of said first and second field effect transistors causing the load to be disconnected from the source. The relay of claim 1, further comprising means (62) for sensing voltage of the source (10) and operatively connected across said first and second field effect transistors (14,16) and to a common node (C) of the first and second field effect transistors (14,16), said voltage sensing means comprising a resistive divider network connected across said first and second field effect transistors, a common node (X) of said resistive divider network operatively connected to the common node (C) of said first and second field effect transistors (14,16) such that said common node (X) of said resistive divider network thereby produces a series of positive sine wave pulses, said common node (X) of said resistive divider network operatively connected to a field effect transistor (64) having its gate operatively connected to common node (X) of said resistive divider network and its source operatively connected to the common node (C) of said first and second field effect transistors and its drain having a voltage sensing signal appearing thereon, the field effect transistor (64) outputting said voltage sensing signal when the voltage level of said positive sine wave pulses occurs at substantially a zero level. The relay of claim 2, wherein said solid state relay further comprises a floating power source means (18) for providing a floating voltage operatively connected to the common node (C) of said first and second field effect transistors (14, 16) and also operatively connected to said voltage sensing means (62), said floating power source means (18) comprising a first resistor (R X ) operatively connected to the neutral side (N) of the source in series with a first diode in series with a parallel circuit comprising a capacitor (C X ) and a zener diode which is operatively connected to said common node (C) of said first and second field effect transistors (14, 16). The relay of claim 2 or 3, wherein said control means (20) comprises a first OR gate (70) for receiving said first and second current sensing signals on first and second inputs, an output of said first OR gate, operatively connected to a first input of a first AND gate (72), an output of said first AND gate (72) operatively connected to a first input of a second OR gate (76) and a second input of said second OR gate (76) receiving the control signal (D), an output of said second OR gate (76) operatively connected to a first input of a second AND gate (78) and a second input of said second AND gate (78) operatively connected to an output of a third OR gate (80), a first input of said third OR gate (80) operatively receiving said voltage sensing signal, and an output of said second AND gate (78) operatively connected to a second input of said first AND gate (72) and a second input of said third OR gate (80), said output of said second AND gate (78) operatively connected to said first and second field effect transistors (14, 16). The relay of claim 4, wherein said output of said second AND gate (78) of said controlling means is operatively connected to the gate of said first, second, third and fourth field effect transistors.

Inventors: BAKER, RICHARD H., MADDOX, EDWARD L.
Applicants: MODICON, INC.
Application year: 1986
Main classification: H03K17
IPC codes: H03K17