PROCEDURE AND DEVICE FOR CROSSPOINT-SWITCHING OF SYNCHRONOUS OR ASYNCHRONOUS DATA TRANSMISSION LINES, PARTICULARLY FOR SERIAL DATA TRANSMISSION

Abstract: In the course of the procedure it should be first decided, which one of the data transmission lines being present should be connected to which other. Then a definite time slot is assigned to every connection path to be established. Thereafter, every transmit line is sampled in the time slot assigned to a specific interconnection, and sampled values are given onto the corresponding line, and after sampling all selected lines the whole process will be repeated. Data lines should be sampled at the very moment signal changes on the line, then sampled data and a time value corresponding to relative moment of signal change should be stored. On sampling all the lines, corresponding sampled and stored values will successively be given onto predetermined interim lines in corresponding assigned time slots, while possible new values of line signals and time values characterizing signal changes are concurrently stored for the next periodical sequence of time slots. The invented device comprises a control unit (11), signal encoder and signal decoder circuits (13a-13n), which are one by one connected to a group of central lines (A) and to a group of internal lines (B). A group of input lines (C1-Cn) are connected individually to inputs of signal encoder and time slot assigner circuits (12a-12n), and a group of output lines (D1-Dn) are connected one after the other to the outputs of said time slot selector and signal decoder circuits (13a-13n).

Description: PROCEDURE AND DEVICE FOR CROSSPOIN -S ITCHING OF SYNCRONOUS OR ASYNCHRONOUS DATA TRA SMISSION LINES, PARTICULARLY FOR SERIAL DATA TRANSMISSION BACKGROUND AND FIELD OF THE INVENTION The subject of the invention is a procedure and a device for orosspoint-switching of asynchronous and/or • ' sjmc ronous data transmission lines, particularly for . serial data transmission. As is well-known, typical of our times is the enormou and sudden growth of amount of information. There is a need for transmitting vast amount of information which requires a great number of data communication paths to be establishe and which are generally established througii crosspoint connection nodes. In order to realize such crosspoint connection nodes (first of all for serial data tra smission) the- following three essential methods have been worked out so far: - Simple Time Division Multiplex (TDM) Systems, (examp Dataswitch terminal switching system of Develcon Electronics Corporation). Characteristic of the TDM systems is that the input data lines are sequentially ' sampled, and the switche 57892-541 \ . output signals are regenerated from these data samples. •In the case of said Dataswitch System, each of the data lines is sampled four times per one bit time, that means, 25 % system distortion arises on the re- ' generated output data. Another feature of this concept • is that the highest number of lines that may be switched is considerably limited by the sampling rate. However, in contrast to said disadvantageous characteristi a great advantage of these switching systems is undoubted- . ly the fact that due to the bit oriented sampling method dataswitching itself does not require the exact ' anticipation of all of the bit, byte, protocol etc. characteristics (with the exception of the maximum data rate) of the data to be switched and transmitted (fully transparent data- transmission), respectively,* - Byte (or rather character-) oriented Time Division Multiplex Systems. A system operating on this principle is for example the EDXS line switching system SIEMENS. The EDXS system is basically, a .character- oriented TDM multiplexer. According to this method the serial input characters are first transferred in bit-parallel format, then the parallel-format characters are sampled. This solution in¬ creases total data transmission speed and capacity. However, devices realizing this principle are relatively complicated and data transmission is not transparent any more at byte (or character) level. - Statistical Multiplexers (Statistical Time Division Multiplexer, or in a shortened form, STDM Systems). Develnet, an improved product of Develcon Electronics- Corporation, can practically be regarded as a-distributed data communication network operating as a statistical multiplexer. " The operation principle of STDM systems is that data (arriving from one or more appropriate inputs) . are interpreted and temporarily stored in an input memory. Stored data are ' transferred via a statistically allocated' data transmission medium to an output memory, from .here data is given to one or more .appropriate outputs. In the aforementioned device every subscriber module being able to serve for eight input channels is controlled by its own Z8000 microprocessor. The advantage of this method is that due to the statistical allocation of the data transmission medium data transmission capacity is extreπ high as compared with traditional TDM systems. However, thi solution is very expensive and complicated. A further dis¬ advantage is that data transmission is not transparent even on the system protocol level, that means, bit and data formats, moreover, all the protocols, being used along with tr_e input channels must be known and fixed in advance, moreover, actively manipulated by the switching equipment itself, although it is merely a transmit medium. By reason of the above difficulties, the aim of the invention is to simultaneously eliminate said 'drawbacks and to develop a line switching system operating on a certa time division basis, which system - allows bit-oriented manipulation of the input data, - as soon as the appropriate connection has been established between the calling and called channels, ensures fully transparent data communication, as " regards the switching system itse ' lf; - increases data transmission capacity as•compared to the traditional, simple TDM systems, - enables the hardware designer to separately realize line multiplexing/demultiplexing circuits channel by channel in order to develop a switching, system being modular in a high degree and with simplified system architecture and increased reliability, - permits basic switching circuits to be realized by a single LSI integrated circuit, - as a consequence of the above features allows • system designers to increase circuit density and system reliability. SUMMARY OF THE INVENTION . The principal object of the invention is consequently to provide a new procedure and a new device which permit system designers to develop circuit realizations being simple but showing suitably high capacity. The basis of the invention is that the task can be easily solved if data signals arriving on input lines and to be switched are sampled at the moment when the logical state of said signal actually changes. The procedure according to the invention is an improve ment of a known procedure on course thereof it is first decided which of the date transmission lines being present should be interconnected to establish one or more connectio slot is assigned to every connection path to be established. Thereafter, every (trans liney s x sampled^ τhe time glot assigned to the respective interconnection path and sampled values are given onto the predetermined line or lines and after every selected line has been sampled, the who'le process should be repeated. The invention lies in the improvement that the input line is sampled at the very moment the logical state thereo changes, then both the signal sample and the value of the time when said signal changes is stored. Every line is successively sampled and subsequently the adequate sampled and stored values are successively given onto the pre¬ determined lines in the appropriate time slot or slots assigned to respective, interconnection or inter¬ connections, while both any possible new value appearing on any of the input lines and corresponding time value characterizing instant of any signal change are simultaneou stored for the next sequence of time slots. According to the invention moments of data changes and those of the time slots are suitably measured and determined in relation to the beginning of the respective sampling period. In particular, the time value of the moment of signal change is transferred concurrently with the value of the sampled data. Moreover, it is suitable that the sample values, given out in the corresponding appropriate assigned time slot, be received and stored at the indicated "channel, and there¬ after, in relation to the beginning of the next sampling period, after a time period determined by the time value previously received has elapsed, output data *be restored withthe logical state. determined by the last data sample. The invented device is an improvement of a known device, which comprises a control unit, signal encoder and time slot assigner circuits, time slot selector and signal decoder circuits, respectively, which are one by one connected to a group of central lines. The improvement lies in that said control unit, said signal encoder and time slot assigner circuits, further said time slot selector and signal decoder circuits are connected (in addition to said group of central lines) also to a group of internal lines. The invented device is provided with a group of input lines representing inputs of said device and connected individually to corresponding inputs of said signa encoder and time slot assigner circuits, furhter with a group of output lines representing outputs of said device and connected one after the other to- outputs of said time slot selector and signal decoder circuits. In an expedient embodiment of the invention said control unit suitably comprises a central processor unit, a synchroni unit and a supervisor unit. Inputs/outputs of said central processor unit are connected to inputs/outputs of said synchronizer unit and to those of said supervisor unit via a bunch of central lines being a subset of said group of central lines. The outputs of said synchronizer unit are applied to a first, a second and a third synchronizer line, said three lines listed above constituting a part of said group of • central lines. Inputs of said supervisor unit are taken from a group of supervisor lines, which form a part of said group of internal lines. In a particular embodiment said signal encoder and time slot assigner circuit comprises a time slot assigner and • enabler circuit, a gating circuit and a signal encoder circuit. Inputs/outputs . of said time slot assigner and enable circuit are connected to said bunch of central lines, re¬ presenting a subset of said group of central lines, one of the inputs of said time slot assigner and enabler circuit is connected(via said first synchronizer line, being part of said group of central lines) to an input of said signal encoder circuit, a further input thereof comes from said third synchronizer line, being a part of said group of centra lines, the outputs of said time slot assigner and-enabler circuit are partly applied to the input of said gating circuit (via a time slog assigner line), partly connected to said group of supervisor lines, constituting a subset of said group of internal lines, respectively. Further inputs of said signal encoder circuit are connected partly to said second synchronizer line, being part of said group of central lines, and- partly to said group of input lines,* respectively. Outputs of the above circuit are applied, via a group of en¬ coded signal lines, to further inputs of said gating circuit. Outputs of said gating circuit are led to said group of internal lines. In a further embodiment said signal encoder circuit comprises a counter, a first storage block, a second storage block, a first bistable-multivibrator, a second bistable multivibrator and a signal change indicator circuit, respectively. Inputs of said counter are one by one connected to said first and said second synchronizer line (both being part * of said group of central " lines), furthermore, via said first synchronizer line to an input of said first and said second storage block, in addition " to an input of said first and s i second bistable multivibrator. Outputs of said counter are connected (via a group of data lines) to data inputs of said first storage block. Further inputs of said second storage block are taken via a first group of stored data lines from outputs of said first storage block while outputs thereof are applied to a second group of stored data lines being a part of said group of encoded signal lines. A further input of said first bistable multivibrator is connected via an input line representing a part of said group of input lines, to an input of said signal change indicator circuit and a further input thereof is connected via a write data line, to one of the inputs of the first storage block and to an output of said signal change indicator circuit. An output of said first bistable multi- vibrator is applied to a further input of said second bi¬ stable multivibrator. An output of said second bistable multivibrator is connected to a stored line which is a part of said group of encoded signal lines. In a further embodiment said signal encoder circuit Includes also a third and a fourth storage block. Inputs of said third storage block are connected to said bunch of input lines (which is a subset of said group of input lines moreover, other inputs thereof are connected to said write data line and to said first synchronizer line. Outputs of . said third storage block are applied (via a third group of stored data lines) to inputs of said fourth storage bloc A further input of said fourth storage block comes from said first synchronizer line, its outputs are .applied, to a fourth, group of stored data lines, which in turn is a subset of the group of encoded agnal lines. In a further embodiment of -the invention said time slot assigner and enabler circuit comprises an address decoder unit, a time slot storage_ register, an enable register, a count register, a first gate circuit and a second gate circuit. Inputs of said address decoder ^ unit are connected via said bunch of central lines being a subset of said group of central lines to inputs of said time slot- storage register and to those of. said enable register. An output of said address decoder unit is connected via a first selector line to an input of said time slot storage register and another output thereof is applied via a second selectro line an input of said enable register. Inputs of sail count register come partly from said first and third synchronizer line, being part of said group of central lines on the one hand .and via a group of time slot lines from outputs of said time slot storage register on the other hand. An output of said count register is connected via a time slot line to an input of said first and to an input of said second gate circuit. A further input of said first gate circuit comes via a first enable line from an output of said enable register, the output of said first gate circuit is connected to said time slot assigner line. A further input of said second gate circuit is connected via a second enable line to a further output of said enable register. Outputs of said second gate circuit are connected to said group of supervisor lines, which represent a subset of ' said group of internal lines. In a preferred embodiment of the invention the time slot selector and signal decoder circuit comprises a signal decoder circuit as well .as a time slot selector and enabler circuit. Inputs of said time slot selector and enabler circuit are connected to said bunch of central lines, being a subset of said group of central lines, a further input thereof is connected via the first synchronizer line to an input of said signal decoder circuit with another input thereof connected to said third synchronizer line, while the output thereof is connected via a sampling line to an input, of said signal decoder circuit. Further inputs of said signal decoder circuit are connected partly to said group of internal lines, partly to said second synchronizer line being a part of said group of central lines while out¬ puts of said signal decoder circuit are applied to said group of output lines. According to a further advantageous embodiment of the invention said signal decoder circuit includes a time code store, a time counter, a first sign storage, a second sign storage and a first gate. Inputs of said first sign storage are connected via said group of internal lines- with inputs of said time code store, a further input is connected via the sampling line with a further input of said time code glare, while the output of said first sign storage is applied to an input of said second sign storage, respectively. Inputs of said time counter are connected to outputs of said time code store, a further input thereof is connected via the first synchronizer line with " further input of said second sign storage and another input thereof to said second synchronizer line, while an output thereof is applied to an input of ' said first gate. A further input of said first gate comes from an output of said ' second sign storage and an output thereof is led to an output line, being part of said group of output lines. It is considered to be a preferred embodiment w_e?ein said signal decoder circuit also includes a first auxiliary store, a second auxiliary store and a secondsp.te. Inputs of said first auxiliary store are connected to said group of internal lines, another input thereof to said sampling line while its outputs are applied to inputs of said second auxiliary store. A further input of said second auxiliary store is taken from said first synchronizer line, while out¬ puts thereof are connected to inputs of said second gate. A further input- of said second gate comes from said output of said time counter. Outputs of said second gate are applied to said bunch of output lines being a subset of said group of output lines. In a preferred embodiment said time slot selector enabler circuit comprises an address decoder circuit, a time slot storage, an enabler unit, a time counter and an output gate. Inputs of said address decoder circuit are • connected to said b.unch of central lines being a subset of said group of central lines, and via said bunch of central lines with inputs of said time slot storage and to those of said enabler unit, res ectively, Outputs of said address decoder circuit are connected via an addressing line to an input of said time slot storage and via the command line to an input of said enabler unit, respectively. Inputs of said time counter are taken partly from outputs of the time slot storage, partly from said first and from said third synchron line, respectively, both being part of said group of central lines. An output of said time counter is applied to an input of said output gate. A further input of said output gate comes from an output of said enabler unit, and an output thereof is connected to the sampling line, respectively. ' BRIEF DESCRIPTION OF THE DRAWING Hereinafter the invention will be explained with refere to the accompanying drawings, which represent some expedient implementation and embodiment of the procedure and device invented. In the drawings: Fig. 1 is a time diagram illustrating the invented procedure, Fig. 2 is a further time diagram, illustrating addition details of the invented procedure, Fig. 3 is a block diagram, illustrating a conventional switching device improved according to the invention, Fig. 4 is a block diagram, illustrating a possible embodiment of the control unit in the invented device, Fig. 5 is a block diagram illustrating a possible ' embodiment of the signal encoder and time slot assigner circuit in the invented device, Fig. 6 is a block diagram illustrating a possible embodiment of the signal encoder circuit in the invented device, Fig. 7 is a block diagram illustrating a possible embodiment of the time slot assigner and enabler circuit in the invented device, Fig. 8 is a block diagram, illustrating a possible embodiment of the time slot selector and signal decoder circuit in the invented device, Fig. 9 is a block diagram illustrating a possible embodiment of the signal decoder circuit in the invented device, Fig. 10 is a block diagram illustrating a possible embodiment of the time slot selector and enabler circuit in the invented device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the figures the same details are designated with the same character symbols, (letters or numbers) ' . If the same or similar details appear repeatedly in one and the same figure, or if a specific detail consists of many further components or particulars, the reference numbers are suppleme ' ed with letters, the reference letters are supplemented with_number.- in order to identify these particulars unam iguously. In the figures, arrows represent uni¬ directional, twofold and oppositely directed arrows symoblize bidirectional relations. The essentials of the invented procedure will be apparent from the time diagrams of Fig. 1 and Fig. 2, Fig. 1 represents the time diagram of the multiplexing, Fig. 2 shows that of the demultiplexing part of the invented procedure. In the course of the invented procedure, signal manipulation (multiplexing and demultiplexing) is synchronize by three basic synchronizing signals. These are the following: frame- synchron signal aa, time slot synchron signal bb and time code synchron signal cc. The time code synchron signal cc is generated by means of said frame synchnron signal aa and time slot synchron signal bb. By the help of the two above signals a time slot signal dd is also generated in a way that as a consequence of a defined, subsequent 0FF-0N transition following a precedi ON-OFF transition of said frame synchron signal aa of said time slot synchron signal said time slot- signal dd goes to ON, and thereafter as a result of the immediately following 0FF-0N transition of said time slot synchron signal bb said time slot signal dd goes to OFF again. A simultaneous 0FF-0N transitions of said frame synchron signal aa said time slot synchron signal bb and said time code synchron signal cc indicate the peculiar moment relatively to which a time distance value should be measured, for example by - using a counter. The least significant bit. of this counter is shown on Fig. 1 as said first time counter signal ff. Counting by the help of said first time counter signal ff continues until a data (that is a signal change) arrives on input channel data signal ee. At -this moment in time counting stops sign of the input data, and in addition a corresponding time value is measured ( ' counted) and stored as first stored sign signal gg and first stored data signal After the subsequent appearance of the frame synchron signal aa the next period of receiving (that is keeping trac a possible new input signal change starts again, and concurrently, as a result of an 0FF-0N transition of said frame synchron signal aa said first stored signsignal gg and said first stored data signal hh will be stored by temporary stores. These stored signals are represented on Fig. 1 as • second stored sign signal- ii and second stored data signal j respectively. The above two signals are gated (during ON state) by the next appearing pulse of said time slot signal dd to the output. These signals appear on Fig. 1 as transit sig signal kk and transit data signal 11, respectively. Inherent in .the invented procedure is the operation of the demultiplexing part .of the preferred device. This will be einlightened with reference to Fig. 2, wherein some signals of Fig. 1 are repeatedly -shown and referred to, respectively. Said transit sign signal kk and transit data signal 11 is sampled and stored by the time slot signal dd, especially as a third stored sign signal mm and a third stored data signal ΏIL. Said third stored sign signal mm will temporarily be stored as a fourth stored sign signal oo and simultaneously a timing is started practically by loading said third stored data signal mm into a counter then letting said counter count down. In this way the moment can be determined which in relation to the previ pulse on the frame synchron signal aa exactly corresponds to th equivalent moment in Fig. 1, with respect to the change on the input channel data signal ee. This timing is represented oh Fig. as a second time counter signal pp, the ON-OFF transition of which causes data according to said fourth stored sign signal o to be gated onto the output as output channel data signal rr. Referring to Fig. 3 , also the operation of presently known crosspoint switching devices will be apparent. The device comprises a control unit 11, severel signal encoder and time slot assigner circuits 12a-12n and several tim slot selector and signal decoder circuits 13a-13n, which are connected one by one to a group A of central lines. Data arrivi on one or any of groups C-, -C of input lines are received and sampled by the corresponding signal encoder and time slot assig circuits 12-12n,that is 3 they generate an appropriate time slot, and in said given, time slot they give sampled data onto the gro A of central lines, if so instructed by a control unit 11 via group A of central lines. The appropriate time slots (that is d≡ta samples in the appropriate time slots) appearing on said group A of central lines are received by corresponding time slo selector and signal decoder circuit 13a-13n, if so instructed b said control unit 11 via said group A of central lines, and output data will regenerated from said data samples and given onto outputs- (D-,- group of output lines). The invented device will also be described with reference to Fig. 3. The invented device differs from the known solution in that a control unit 11, signal encoder an time slot assigner circuit 12a-12n and time slot selector and signal decoder circuits 13a-13n are connected hot only to said group A of centrallines but also to a group B of internal lines. Inputs are represented by group C-,-0 of input lines connected individually to inputs of said signal encoder and time slot assigner circuits 12a-12n. GroupD-,τD of output lines connected one after the other to the outputs of said time slot selector and signal decoder circuits 13a- 13n constitute, however, the outputs of the device. The operation of the device according to the invention differs from that of the known solution in that said signal encoder and time slot assigner circuit 12a-12n instead of immediately generating a time slot pulse (and sampling at the same time ), at first indicates signal change on its input and determines and stores sign and time of this • change. Thereafter, if so instructed by said control ' unit. .11, it gives ' identification (sign) of data onto the group A of central lines and at the same time it gives time code (that is the value of time el a -psed from a relative time base up to the signal change) onto, said group B of internal lines,too. Output data will be regenerated from these two types of data samples by said time slot selector and signal decoder circuits 13a-13n. Output data regenerated in this way will be equivalent to the input data with regard to both sign and phase. Said control unit 11 of the invented device will be described hereinafter with reference to Fig. 4 in detail. Said control unit 11 includes a central processor unit • 14, a synchronizer unit 15 and a supervisoer unit Iβ. Inputs/outputs of said central processor unit 14 are connected via a bunch E of central lines to inputs/outputs of said synchronizer unit 15.and those of said supervisor unit 16 which bunch E is a subset of said group A of central lines. Outputs of said synchronizer unit 15 are applied to first, second and third synchronizer lines b, g and h, respectively, said three lines constituting a part of said group A of central lines. Inputs of said supervisor unit Iβ are taken from a group G of .supervisor lines being part of said group B of internal' lines. Via said bunch E of central lines constituting a general-purpose control bus central processor unit 14 controls the operation of said synchronizer unit 15, supervisor unit Iβ and furthermore that of said signal encoder and time slot assigner circuits 12a-12n and said time slot selectro and signal decoder circuits 13a-13n being connected to said group A of central lines. In a . preferred realization, said central processor unit 14 may expediently be a microprocessor. Said,synchronizer unit 15 generates major synchronizer pulses, appearing on the first b, second g and third h synchronizer lines at a repetition rate (frequency) adjustable by program upon send an appropriate microprocessor command to synchronizer 15 unit via said bunch E of central lines. Said supervisor unit Iβ is practically a programmable data input unit having max, n number .of input lines which are connected to said group G of supervisor lines, comprising n number o separate supervisor lines. At the same time a time slot pulse appears on a time slot assigner line i (see Fig. 5), each of said signal encoder time slot assigner circuits 12a-12n generates a pulse onto appropriate lines of said group G of supervisor lines assigned to a given signal encoder and time slot assigner circuit 12. The supervisor unit 16 recognizes (by supervising the input lines) whether one or more of the signal encoder and time slot assigner circuits 12a-12n give a pulse onto the wires of the group B of internal lines and if more than one pulse is recognized an error message will be sent via said bunch E of central lines ' to said central processor unit 14. Operation of the invented signal encoder and time slot assigner circuits 12 will be explained referring to Fig. 5 in detail. Said signal encoder time slot assigner circuits 12 comprise a time slot assigner enabler circuit 20, a gating circuit 21 and a signal encoder circuit 22. Inputs/outputs of said time slot assigner and enabler circuit 20 are connected to said bunch E of central lines, representing a subset of said group A of central lines, while one of its inputs is connected (via said first synchronizer line b bein part of said group A of central lines) to an input of said signal encoder circuit 22, a further input of the above circuit comes, from said third synchronizer line h, being part of said'group A qf central lines. Outputs of said time slot assigner and enabler circuit 20 are partly applied via the i time slot assigner line tσ ϊ -- input of said gating circuit 21, partly connected to said group G of supervisor lines constituting a subset of said group B of internal lines. Further inputs of said signal encoder circuit 22 are connected partly to said second synchronizer line g bein part of said ' group A of central lines, partly to said group C of input lines. Outputs of the above circuit are applied via group K of encoded signal lines to further inputs of said gating circuit 21. Outputs of said gating circuit 21 are connected to group B of internal lines. Said signal encoder circuit 22 synchronized by the pulses arriving on said first and second synchronizer line b and g, respectively, periodically generates time code and sign of the data signal changes, further status code of auxiliary signals, characterizing data flow appearing on said group C of input lines, and gives these codes onto s group K of encoded signal lines. Said time slot assigner and enabler circuit 20 being programmable- via said bur.ch Ξ of central lines and synchronized by said first and third synchronizer line b and h, respectively, periodical generates time slot assigner pulses corresponding to the logical channel being assigned to the given device and gives these pulses onto said time slot assigner line i. Said gating circuit 21 -gates codes arriving on said group K of encoded signal lines during pulses appearing on time slot assigner line i to said group B of internal lines. C currently with said time slot assigner pulse, appearing on the i time slot assigner line said time slot assigner " ' and enabler circuit 20 gives also a pulse to on appropria wire of said group G of supervisor lines, constituting a subset-of said group B of internal lines. A possible embodiment of said signal encoder circuit ' 22 will be explained with reference to Fig. 6. Said signal encoder circuit 22 includes a counter 23 a first storage block 24, a second storage block 25, a first bistable multivibrator 52, a second bistable multi¬ vibrator 2β and a signal change indicator circuit 27. Inputs of said counter 23 are one by one connected to said first and second synchronizer line b and g, further- more, via the first synchronizer line b to an input of said first and second storage block 24 and 25 and -in addition to one of the inputs of said first and second bistable multivibrator 52 and 26, respectively. Outputs of said counter 23 are connected via a group L of data lines to data inputs of said first storage block 24. Further inputs of said second storage block 25 are taken via a first group M of stored data lines from outputs of said first storage block- 24 while outputs thereof are applied to a second group N of stored data lines, which represent a subset of said group K of encoded signal line A further input of said first bistable multivibrator 52 is connected via an input line c representing a part of the group C of input lines to an input of said signal change indicator circuit 27, and a further input thereof is connected via a ' write data line f to an input of saLd first storage block 24 and to an output of said signal change indicator circuit 27. An output of said first bistable multivibrator 52 is applied to a further input of said second bistable multi- vibrator 2 β . An output of said second bistable multivibrator 2β is connected to said stored line , which is a part of said group K of encoded signal lines. Output values of said counter 23 will be incremented (the counter counts "up") as an effect of every 0FF-0N transition appearing on said second synchronizer line g, however said counter 23 will be cleared as soon as a pulse appears on said first synchronizer line b. Data outputs of said counter 23 appear on group L of data lines. If the logical state of a signal applied to said input line c changes, said signal change indicator circuit 27 generates a- pulse on its output and applies it to said write data line f. This pulse appearing on the write data line f causes the sign of data change occuuing on the input line c (practically the signal state immediately following the transition) enter into said first bistable multivibrator 52. Thus the new signal state will be stored. As an effect of the same pulse on said write data line f actual data on said group L of data lines, will enter said first storage block 24 to be stored there. Data will also be clocked into said -bistable multivibrator 52 and first storage block 24 as soon as a pulse appears on said first synchronizer line b. As an effect of a pulse on first syhcnroni ' zer line b the actual logical state of the output of said first bistable multivibrator 52 (data line x) will be stored by said second bistable multivibrator 26 and data being present on outputs of said first storage block 24 (first group M of stored data lines) will enter said second storage block 25. The output of said second bistable multi¬ vibrator 26 (k stored line) and that of said second storage block 25 (second group N of stored data lines) constitute a subset of said group K of encoded signal lines. A further possible embodiment of the invented signal encoder circuit 22 will also be explained with reference to Fig. 6. This embodiment of said signal encoder circuit 22 differs from that detailed above in that it comprises further third and a fourth storage block 28 and 29, respectively. Inputs of said third storage block 28 are connected to a bu ch R of input lines (which is a subset of said group C of input lines), moreover other inputs thereof are connected to said write data line f and to said first synchronizer line • b. Outputs of said third stora ' ge block 28 are applied (via a third group 0 of stored data lines) to inputs of said fourth storage block 29. A further input of said fourth storage block 29 comes from said first synchronizer line b and outputs thereof are connected to a fourth group P of stored data lines which is in turn a subset.of said group K of encoded signal lines. In this embodiment of said signal encoder circuit 22 data inputs of said third storage block 28 are connected to said bunch R of input lines being a subset of said group C of input lines and carrying auxiliary signals of the input data channel presented on group C of input lines. To an input of said third storage block 28 is connected said write data line f, too. Said third storage block 28 is loaded with actual data being present on its input when, a pulse arrives on said write data line f or on said first synchroniz b being connected to load inputs thereof. That is, said third group 0 of stored data lines carries information being characteristic of the state of auxiliary signals arriving on said group C of input lines and of signalchange on said inpul line c. Said fourth storage'block 29 will be 2 Q loaded with data being present on said third group 0 of stored data lines as soon as a pulse arrives on said first synchronizer line b. Said fourth group P of stored data lines connected to outputs of said fourth storage block 29 constitutes ' a subset of said group K of encoded signal lines. Said time slot assigner and enabler circuit 20 will be explained with reference to Fig. 7. Said time slot assigner and enabler circuit 20 comprises an address decoder unit 30, a time slot storage register 31, an enable register 32, a count register 33, a first gate circuit 34 a'nd a second gate circuit 35. Inputs of said address decoder unit 30 are connected via said bunch E of central lines to inputs of said time slot storage register 31 and to those of said enable register 32. An output of said address decoder unit 30 is connected via a first selector line m to an input,,of said time slot storage register 31 another output thereof is applied via a second .selector-line n to an input of said enable register 32. Inputs of said count register 33 come partly from said first and third synchronizer line b and h, respectively, 'these lines being part of said group A of cent • lines, and partly via group T of time slot lines, ' from out¬ puts of said time slot storage register 31. Outputs of said countregister 33 are connected via a time slot line t to an input of said first and second gate circuit 34 and 35, respectively. A further input of said first gate circuit 34 comes via a first enable line r from an output of said enable register 32, while an output of said first gate circuit 34 is connected to said time slot assigner line i. A further input of said second gate circuit 35 is- connected via a second enable line s to a further output of said enabl register 32, while outputs of this circuit are connected to said group G of supervisor lines, which represent a subset of said group B of inernal lines. Operation of said time slot assigner and enabler circui 20 may be programme-controlled, that is said time slot storage 31 and said enable register 32 can be loaded with data via said bunch E of central lines. Programmed instructio intended to select and load said time slot storage 31 and enable register 32 are recognized by said address decoder unit 30 which generates a select pulse on said first selecto line m or on said second selector line n, respectiveli if one of the above registers is to be loaded. Pulses on said first selector line m load said time slot storage register 31 with data characteristic of the time slot assigned to a specific group C-,-0 of input lines,- while pulses appearing on said second selectro line n loads said enable register 32 with data permitting or inhibiting the codes characterizing the given input data to be periodically gated on* said group B o-f internal lines. Said count register 33 is , periodically loaded ' with data appearing on outputs of said time slot storage register 31 and. carried by said group T of time slot lines and . said count register 33 will be loaded whenever a pulse appears on said first synchronizer line b. Every time a pulse arrives on said third synchronizer line h said count register 33 counts down (its contents will be decremented). Thus on a borrow output of said count register 33 which is connected to said time slot line t a pulse will periodically be generated, inparticular, exactly one pulse after each puls appearing on said first synchronizer line b, and the interval between the first synchronizer pulse and the time slot pulse being determined by data stored in said time slot storage register 31. If enabled by the logical level being present on said output of said enable register 32 and on the first enable line r connected thereto then pulses given onto said time slot line t will appear on the output of said first gate circuit 34 and on said time slot assigner line i, too. If enabled by the logical state of a corresponding bit of said register 32 logical state of said second enable line s enables said second gate circuit 3.5 to generate a pulse on its output, concurrently with a pulse on said time slot line t and to give this pulse on an appropriate line of said group G of supervisor lines being a subset of said group B of internal lines. A possible embodiment of said time selector and signal decoder circuit 13 will be explained with reference to Fig. The time slot selector and signal decoder circuit 13 compris a signal decoder circuit 36 and a time slot selector enabler circuit 37. Inputs of said time slot selector and enabler circuit 37 are connected to said bunch E of central lines, being a subset of said group A of central lines and a furthe input is connected via said first synchronizer line b to an input of said signal decoder circuit 36 and a further input thereof to said-third synchronizer line h. An output of the above circuit is connected to a sampling line n, . and via said sampling line u to an input of said signal decoder circuit 36. Further inputs . of said signal decoder circuit 36 are connected partly to said group B of internal lines and partly to said second synchronizer- line g being part of said group A of central lines. Outputs of said signa decoder circuit 36 ' are applied to said group D of output lines. Said time selector and enabler circuit 37 being program controlled via said bunch E of central lines periodically generates and gives a sampling pulse onto said sampling line n which sampling pulse corresponds to the time slot number assigned to the corresponding input channel. Sampling pulses are. generated synchronously with pulses periodically arriving on said first synchronizer line b. During a pulse given onto said sampling line u said signal decoder circuit 36 samples corresponding signals arriving on said group B of internal lines and regenerates output data signals of the respective channel from these samples using synchronizer pulses periodically arriving on said first and third synchronizer line b and h and t »hese regenerated signals will be given onto said group D of output lines. A possible embodiment of the invented signal decoder circuit 36 will be described with reference to Fig. 9 in detail. Said signal decoder circuit 36 includes a time code store 38, a time counter 39, a first sign storage 40, a second sign storage 41 and a first gate 42. Inputs of said first sign storage 40 are connected via said group ' B of internal lines to the inputs of said time code store 38, a further input is connected via said sampling line u with ' a further input of said time code store 38 while an output of said first sign storage 40 is applied to an in¬ put of said second sign storage 41. Inputs of said time counter 39 are ' connected to outputs of said time code store 38 and a further input thereof is connected via said first synchronizer line b to a further input of said second siga storage 41 and another input to said second synchroniz line g while its output is applied to an input of said first gate 42. A further input of said first gate 42 comes from an output of said second sign storage 42 and its output is led to an output line d being part of said ' group D of output lines. •As an . effect of pulses appearing on ' said sampling line u corresponding lines of group B of internal lines will be periodically sampled and said time code store 38 loaded with data carrying time code, said first sign storage 40 loaded with a data- bit representing the sign of data to be transmitted. A pulse arriving on said synchronizer line b clocks data appearing on said outputs of said time code store 38 into said time counter 39. At the same time said second sign storage 41 will be loaded with a bit value being present on said output of said first sign storage 40. Every time a pulse arrives on said secondsynchronizer line g said time counter 39 counts down, i.e. its value is decremented. When all of the outputs of said time counter 39 reach simultaneously their zero-state a borrow pulse will be generated -on said output of said time counter 39.- This borrow pulse gives the bit value being present on said output of said second sign storage 41 to the output of said first gate 42. Said output of said first gate 42 is connected to said output line d being part of said group D of output lines. A further possible embodiment of the invented signal decoder circuit 39 will also be explained with reference to Fig. 9. This embodiment of said signal decoder circuit 36 differs from the above that it comprises further a first auxiliary store 43, a second auxiliary store 44 and a second gate 45. Inputs of said first auxiliary store 43 are connecte to said group B of internal lines, another input thereof to said sampling line u and its outputs are applied to in- puts of said second auxiliary store 44. A further input of said second auxiliary store 44 is taken from said first • synchronizer line b and outputs thereof are connected to inputs of said second gate 45. A further input of said se.cond gate 45 comes from said output of said time counter " 39. Outputs of said second gate 45 are applied to said bunch Q of output lines being a subset of said group D of output lines, A pulse arriving on said sampling line u loads said ' - first auxiliary store 43 with data appearing on group B of internal lines and carrying sampled values of auxiliary signals of the given channel. Data appearing on said outputs of said first auxiliary store 43 is clocked in said second auxiliary store 44 by a pulse arriving on said first synchronizer line b. Said outputs of said second auxiliary store 44 carrying auxiliary signals of the given (transmitted channel will be clocked in said second gate 45 by a pulse generated by said borrow output of said time counter 39. - The outputs of said second gate 45 are connected directly to said bunch Q of output lines being a subset of said group D of output lines. Ώ. a concrete realization of the device said first gate VJl Ω VJ1 Ω VJl CQ P H ta Hi P CQ H Ω 4 tB !> » P Ω Ω VJl d- •d d- σ 4 μ. d- 4 4 P Hi μ- Φ I- 4 4 o P H μ. P Ω Ω P Ω Ω 4 μ- 4 I- 1 Ω Ω 4 • 3 4 Φ 4 3 μ- P i CQ Ω P d- Hi μ. P φ P <! P - g d- 4 ! •d φ d- CD P Je- 04 oq CO μ- Ω μ- H- Φ C0 a μ- ϋJ Ω d- Ω Ω Φ μ 4 Φ P P o " cr CQ ct Φ P P t H. Ω H) μ. H μ. era 3 O P oq μ- a> Ω P - • P Ω -J P i 3 φ -P- d- 4 ct P i P i Hi § P CQ 00 Φ P oo Ω P P -o Ω P 4 o d- d- P CQ i «-_ σ 4 P 13 P oq P P P d- ta P 4 Φ μ- • ? . • CQ g P i o 4 era CQ Φ H P i Ω P Φ 4 fi μ- ta CQ M Φ P σ 4 P i μ- 4 H td CQ P <Ά P μ 4 Φ P μ- -f^ μ 4 g 4 CQ P i VJl μ 4 P P μ- P 4 μ- μ- 4 p. 00 μ- Φ P μ- - Ω ct μ « P- P i P 4 P Ω CQ μ- Φ P B o σ 4 P P i td Φ g P d- P Φ P 4 ω P i B. •d μ- P Φ •d P d- μ- P CQ P ta ■ d σ 4 Φ P Ω P i •• 4 μ- Φ 3 p. _^ td P i CQ o 4 d- Ω Φ P H Hi p i d- ta φ - . φ P t-> P l» > μ 4 μ- P ta 4 σ 4 Ω P Ω Ω 3 a> Ω *d Ω P o 4 Φ Ω Φ «<J -J P CQ 4 .P Hi Ω t 4 Hi •d Ω Ω era μ- Φ tB VD H Pi P i t-* H Hi IV Φ P CQ ω !d Ω CQ Ω Φ H- CQ μ- φ Ω 4 P 4 d- μ- P μ- P ct P 4 Φ 4 P § P Φ Ω P i P Ω 4 p P ' μ- CQ μ 4 μ. φ P era μ- μ- 4 Φ P oq Pi CQ ta p. Ω ct Ω ct P i P μ- OQ p Φ H P Φ d- Ω 4 μ. Ή d- d- P P μ- <. H P P- Ω Φ B P 4 μ- ■ P- Ω Ω 4 d- μ. ct Φ I- 4 μ. P i Pi Ω 4 P H Ω P VD P P Ω P i 4 μ- P i 4 P P P μ « P Φ d- P H ■ P- P Φ 4 Φ d- oq cr N H μ. P •d P CQ Ω VO Φ φ CQ o Φ I- 1 Φ μ- ct .0 P P μ 4 P P P IB P ω CQ Φ CQ P . P i d- μ- μ- μ- ct ≤i •d ta Φ ta -J 4 φ -*> P P P i •d tr¬ •d μ- Ω Pi P 00 t ω -l P B ■ d Φ P et Φ P H p i μ- g P 4 P ' P ta ct d- P 4 P cr Ω Φ i Ω ^— » 3 d- d- * μ- 4 o Ω Ω P CQ μ- CQ σ 4 Ω Ω Φ 3 Ω P i μ- IV Ω P P d- Φ Φ P P Ω φ Hi P P ta 01. P i •d Pi μ- μ> μ- d- VJl Hi & d- era P φ P Pi i -J P P d- ■ d IV Ω CQ P μ- Ω 4 μ 4 4 O i era Ω p ω Ω Ω P Ω P i Ω CQ Φ P • i 4 d- Ω P • p p μ- d- P 4 p Φ ta i 4 P CQ ' Ω μ- d- p P i P d- 4 p Q p i H Φ d- ■ 3 P i •d d- IV CQ μ- Φ μ- μ- μ- 4 H) CQ CQ μ- P 4 Φ P Φ d- φ P 3 04 ct CQ P Φ CQ P P Φ CQ Ω d- 4 μ. P μ- Φ ■ d era to P μ- σ 4 CQ 4 p 3 P i Ω -F- era ta P P to d- φ Hi d- Ω VJl Φ p ta g 3 3 CQ P -O μ- μ* era Φ 4 Ω 4 ■ d Hi Ω Ω H i « i μ- i μ- d- P Hi Ω Ω Ω μ- Φ P Φ o ct g CQ Ω 3 d- CQ cr t-> 1 d- P P Φ Ω P Ω d- μ « P *<J oq o d- μ- Hi μ- CQ P P • Φ P B μ- ct P 4 P • d Ω <j i 4 i Ω P P i φ P i P i P μ 4 t. 4 Ω d- - Q o d- μ- Ώ Ω g d- P Φ d P Φ μ- 3 P o Φ ■ d P every pulse arriving on said first synchronizer line b. Said time counter 50 counts ' down on every pulse on said third synchronizer line h..Said time counter 50 counts down onevery pulse on said third synchronizer line h. If output value of said time counter 50 reaches zero the borrow output of said time counter 0 generates a pulse and gives it to said input of said output gate 51. If said output of said enabler unit 49 being also connected to an input of said output gate 51 enables operation of said ' gate 51 the output of said output gate 51 will generate a pulse simultaneously with the borrow pulse of said time counter 50 and this pulse appears on said sampling line u. ADVANTAGES OF THE INVENTION The advantages provided by the invented device and procedure can be summarized in the ' following: 1. The invented procedure keeps the advantages of the known simple TDM systems as regards the BIT-LEVEL TRAITSPARENCY of data transmission between channels to be interconnected. Thi's feature may be of a great importanc in such cases, when data have to be treated secretly. This • characteristic is however important in other respects, too, i.e. data transmission and line switching can be carried out with uniform devices and uniform methods even if data formats are known but diverse. 2. As compared with simple, traditional TDM systems the invented procedure has the essential advantage that theoretically data samples should only be transferred between the channels to be Interconnected once per bit time,because the relative time of data changes occuring within a bit time is determined by the time code and embedded in the data samples. (In practice transmission rate of data samples should be chosen as two per bit time,, since even in the case of a negligible signal distortion but greater than zero actually two signal changes may occur within a single bit-time " . This would result in a bit-loss in a device according to the invention, if the sampling rate were chosen as one per bit-time.) In such a way, the maximum number of time slots (practically the number of channels) that may be transmitted by a given number of 5 internal lines can practically be increased by one order of magnitude without any increase of signal distortion as compared with traditional TDM systems. (According to the invented procedure signal distortion caused by the system does not depend on sampling rate, but on resolution 10. of time code embedded in data samples.) 3. In the invented procedure functions of sampling/ /resolving the input serial data and generating/transmittin time slots are separated (see operation of said second and third synchronizer lines g and h, respectively, )and 15 ' this fact provides an opportunity to adapt .the switching system according to the number and transmission speed of the lines to be switched in order to reach best effectivene by merely appropriately selecting repetition rate of the above twosynchronizing signals. 20 4. IΏ. the invented device circuit accomplishing - data sampling and signal regeneration constitute independen -parts per channel, and this allows this circuit parts to be realized by LSI integrated circuits being capable of carry- - . ing out line switching functions of a separate serial 5 data transmission channel. This in turn permits the functio of line switching to be realized by a simple, cheap and compact construction as compared with other known line switching methods. 5. Theoretically εfca samples and time code have only to 0 be transmitted -in cases when a signal change actually occure in the given sampling period. Thus,- .transferring of re¬ dundant information can also be avoided. Supposing a con¬ ventional twofold sampling in a bit time and asynchronous serial input data statistically 50 to 75 % of the time slots are unused even in case of a continuous data transmission, i.e. without regard to the statistical characteristics of the input data stream itself. To take advantage , of this feature, only a single control bit has to be transferred. This -may also result in further advantages, e.g. decrease of bandwidth.

Claims: C L A I M S 1. A procedure for crosspoint-switching of asynchronous and/or synchronous data transmission lines, particularly in case of serial data transmission comprising the steps of first deciding which -specific one of the data trans- mission lines should be connected to which other or which other ones for establishing a specific connection path, • then assigning a definite time slot to every specific connection path to be established, and thereafter samplin every line and giving sampled values onto said specific line or lines during said time slot assigned to a specifi connection path and repeating the above steps afterevery specific line has been sampled, ch a r a c t e r i z e d by the steps; .sampling.-line . signals at the very moment the logical state of said specific line changes, - then storing signal .sample and the value of time of said signal change, and giving corresponding sampled and stored values in said time slot assigned to said specific connection path onto corresponding -lines after every line signal has successively been sampled,and concurrently storing values of possible new signal changes for a next sequence, wherein the above steps are repeated. 2. The procedure claimed in claim 1 comprising the steps of measuring and determining significant moments an time slot values with respectto the beginning of the corresponding sampling period. 3. The procedure claimed in claims 1 or 2 comprising the step of giving out time value of the moment of signal change concurrently with one or more values of sampled data. 4. The procedure claimed in any of claims 1 to 3' comprising the steps of receiving sample value together with time value of the signal change given out during a corresponding time slot and havi sto - ϊ d ' by- the selected channel regenerating data with logical state, on the out- put of the corresponding channel, determined by said signal sample value and accomplishing said regeneration in relation to beginning of the next sampling period, after a time interval determined by the time value of signal change. 5. A device aimed at crosspoint-switching of asynchrono or synchronous or both kind of data transmission lines particularly for serial data transmission, for example to realize the procedure according to any of claims 1 to 4 comprising a control unit, signal encoder and time slot o assigner circuits . and time slot selector and signal decoder circuits, each ' connected - one by one to a group of control lines, c h a r a c t e riz- e d in that said control unit (11), said signal encoder and time slot assigner circuits (13a-13∑ι) are connected both to a group of central lines (A), to a group of internal lines (B), while inputs of the device are constituted by a.group of input lines (-^-C ) connected individually to inputs of said signal encoder and time slot assigner circuits (12a-12n) wherein a group of output lines . (-D 1 --D n ) connected one after the -other to the outputs of said time slot selector and signal decoder circuits (13a-13n) constitute an output of the device. (Fig. 3) 6. The device claimed in claim 5 w h e r e i n said control unit (11) includes a central processor unit (14) a synchronizer unit (15) and a supervisor unit (16), inputs and outputs of said central processor unit (14) are connec¬ ted via a bunch of central lines (E) ."to coiresponding out¬ puts and inputs of said synchronizer unit (15) and to those of said supervisor unit (16) which bunch of central lines (S) is a subset of said group of central lines (A), further outputs of. said synchronizer unit (15) are applied to a • - first, second and third synchronizer line (b,g, h) respect- ively, these three lines (b, g, h) constituting a part of said group of central lines (A), inputs of said supervisor t units (16) are taken from a group of supervisor lines (G) Ω Ω 3 .to an input of said first and second bistable multivibrator (52, 26) on the one hand, outputs of said counter (23) are connected via a group of data lines (L) to data inputs of said first storage block (24), further inputs of said second storage block (25) are taken via a first group of stored data lines (M) from outputs of said first storage • block (24), its outputs are applied . to a second group of stored data lines (N) . representing a subset of said group of encoded signal lines (K) , a further input of said first bistable multivibrator (52) is connected via an input line (c) representing a part of said group of input lines (C) to an- input of said signal change indicator circuit (27), further input thereof via a write data line (f) to an input of said first storage block (24) and to an output of said signal change indicator circuit (27), an output of said first bistable multivibrator (52) Is applied via a data line (x) to a further input of said second bistable multivibrator (26), an output of said second bistable multi¬ vibrator (26) is connected to-a stored line (k), which is a part of said group of encoded signal lines (ϊζ)(Fig. 6) 9. The device claimed in claim S w h e r e i n said signal encoder circuit (22) comrises a third storage block (28) and a fourth storage block (29), inputs of said third storage block (28) are connected to -a bunch of input lines (R) being a subset of said group of input lines (C) and further inputs thereof are .connected to said write data line (f) and to said first synchronizer line (b), outputs " of said ' third storage block (28) are applied via a third group of stored data lines "(0)! to inputs of said fourth storage block (29), a further input of said' fourth storage block (29) comes from said first synchronizer line (b " ), its outputs are connected to a fourth group of stored data lines (P) which is a subset of said group of encoded signal lines (K). (Fig. 6) 10. The device claimed in claims 7 to 9 w h e r e i n said time slot assigner and enabler circuit (20) includes an address decoder unit (30), a time slot storage register (31), an enable register (32), a count register (33), a firs gate circuit (34), and a second gate circuit (35), inputs of. said address decoder unit (30) are connected via said 5 bunch of central lines (E) to inputs of said time slot storage register (31) and to those of said enable register (32), an output of said address decoder unit (30) is connecte via a first selector line (m) to an input of said time slot storage register (31), another output thereof is applied via 10 a second selector line (n) to an input of said ' enable registe (32), inputs of said count register (33) come partly from said first and third synchronizer line (b, h), partly via a group of time slot lines (T) from outputs of said time slot storage register (3D, an output of the count register (33) •15 is connected via a time slot line (t) to an input of said first gate circuit (34) and to that of said second gate circuit (35), a further input of said first gate circuit (34) comes via a first enable line (r) from an output of said enable register (32), the output of said first gate circuit 20 * (34) is connected to a time slot assigner line (i), a furthe input of said second gate circuit (35) is connected via a second enable line (s) to a further output of said enable register (32) and output thereof are connected ' tq said group of supervisor lines (G) representing a subset of said group 25 of internal lines (B) (Fig. 7). 11. The device to any of the claims ' 5-10 w h e r e i n said time slot selector and signal decoder circuit (13) comprises a signal decoder circuit (36) and a time slot selector and enabler circuit (37) and inputs of said time sl 30 selector and enabler circuit (37) are connected to a bunch of central lines (E) . being a subset of said group of central lines (A), a further input thereof is connected via a first synchronizer line (b) to an input of said signal decoder circuit (36), another ' input to a third synchronizer line (h), 35 an output of said time slot selector and enabler circuit (37) is connected to a sampling line (u) and to an input of said signal decoder circuit (36) further inputs of said signal decoder circuit (36) are connected partly to said group of i ternal lines (B), partly to a second synchronizer line (g), 5 being part of said group of central lines (A), outputs of said signal decoder circuit (36) are applied to said group of output lines (D). (Fig. 8) 12. The device claimed in claim 11 w h e r e i n said signal decoder circuit (3 ) includes a time code store (38), 10 a time counter (39), a first sign storage (40), a second sign storage -(41) and a first gate (42)., inputs of said first sign storage (40) are connected via said group of internal lines (B) to inputs of said time code store. (38), a further input is connected via said sampling line .(u) to Tc a further input of said time code store (38), an output of said first sign storage (40) is applied to an input of -said second sign storage (41), inputs of said time counter (39) are connected to outputs of said time code store (38), a further input thereof is connected via said first synchroniz 20 ' line (b) to a further input of sa'id second sign storage (41), another input to said second synchronizer line (g), an output thereof is applied to an input of said first gate (42), a further input of said first gate (42) comes from an output of said second sign storage (41), an output 2 thereof is connected to an output line (d), which is part of said group of output lines (D) -(Fig. 9). 13. The device claimed in claim 12 w h e r e i n said signal decoder circuit (36) includes a first auxiliary store (43), a second auxiliary store (44), and a second gate (45), Q inputs of said first auxiliary store (43) are connected to said group of internal .lines (B), another of its inputs to said sampling line (u), outputs thereof are applied to Input of said second auxiliary store (44), a further input of 5 said second auxiliary store (44) is taken from said first" synchronizer line (b), outputs thereof are connected to inputs of said second gate (45), a further input of said second gate (45) comes from said output of said' time counter (39), outputs of said second gate (45) are applied to a bunc of output lines (Q), which is a subset of said group of output lines (D). (Fig. 9) 14. A device according ' to any of the claims 11 to 13, w h e r e in said time slot selector and enabler .circuit (37) comprises an address decoder circuit (47), a time slot storage (48), an enabler unit (49), a time counter (50) and an output gate (51), inputs of said address decoder circuit (47) are connected to said bunch of central lines (E)- being a subset of said group of central lines (A) and via said bunch of central lines (B) to inputs of said time slot storage (48) and to those of said enabler unit (49), outputs of said address decoder circuit (47) are connected via an addressing line (v) to an input of said time slot storage (48) and via a command line (w) to an input of said enabler unit (49), inputs of said time counter (50) are taken partly from outputs of said time slot- storage (48) and partly from said first and third synchronizer line (b, h), both being part of said group of central lines (A), the Output of said time counter (50) is ' applied to an input of said output gate (51) and a further input of said output gate (51) comes from an output of said enabler unit (49) while its output is connected to said sampling line (u) . (Fig. 10).

Inventors: BANKI FERENC, HUNYADI JOZSEF, KARADI PAL, KOEVESHEGYI LASZLO, MAYER ISTVAN, REE EOERS, SZEBENYI ENDRE, SZEMEREKI ZOLTAN, SZUECS F KAROLY, BANKI, FERENC, HUNYADI, JOZSEF, KARADI, PAL, KOEVESHEGYI, LASZLO, MAYER, ISTVAN, REE, EOERS, SZEBENYI, ENDRE, SZEMEREKI, ZOLTAN, SZUECS, F., KAROLY
Applicants: MTA KOEZPONTI FIZ KUTATO INTEZ, MTA KOEZPONTI FIZIKAI KUTATO INTEZETE
Application year: 1986
Main classification: H04Q11
IPC codes: H04L12, H04Q11