FIELD EFFECT TRANSISTOR

Abstract: A field effect transistor comprising a substrate made of one conductive type or semiinsulator of semiconductor, work­ ing layers formed on the substrate, a source region and drain region provided in the working layer and channel region be­ tween the source and drain region and gate electrode formed on the channel region, said working layers comprising a first semiconductor layer of Ga In As mixed crystal formed on the substrate and a second semiconductor layer formed on the first semiconductor layer and made of AI In As mixed crystal containing n type impurity in such a manner that the density of the impurity is less in the region near the gate electrode and more in the region near the second semiconductor layer.

Description: The present invention relates to a field effect transistor, comprising a substrate made of semiinsulator or semiconductor of one conductivity type; working layers formed on the substrate; a source region and a drain region provided in the working layer and a channel region between the source and drain region; and a gate electrode formed on the channel region, said working layers comprising a first semiconductor layer of mixed crystal formed on the substrate and a second semiconductor layer formed on the first semiconductor layer and made of mixed crystal containing n-type impurity in such a manner that the density of the impurity is lower in the region near the gate electrode than in the region near the first semiconductor layer. Such a transistor is known from EP-A-0 555 968. There has been proposed a field effect transistor (referred to as FET) comprising a first layer made of Gallium, Indium and Arsenide (Ga 0.47 In 0.53 As referred to as Ga In As) mixed crystal and a second layer made of non-doped Aluminium, Indium and Arsenide (Al 0.48 In 0.52 Ao referred to as Al In As) mixed crystal on the first layer and third layer made of n-doped Al In As mixed crystal formed on the second layer. (C.Y. Chen, IEEE, ELECTRON DEVICE LETTERS, vol. EDL 3, No. 6, June 3). In the FET of the above type, a two dimensional electron gas is formed in the Ga In As layer, since the electron affinity of the Al In As layer is smaller than the affinity of Ga In As layer and n-type impurities are selectively doped into the Al In As layer. The mobility of electrons is affected by scattering due to impurities. In the FET of the above type, impurities are doped into the Al In As layer while the two dimensional electron gas is in the Ga In As layer. Thus, the two dimensional electron gas has high mobility since the scattering due to impurities is remarkably suppressed. This two dimensional electron gas acts as a channel between the source and drain, namely the drain current flows through the two dimensional electron gas from the drain to the source. The drain current is varied by the applied voltage to the gate, since the density of the two dimensional electron gas is varied by the applied voltage to the gate. The FET of the above type has a high transconductance, since the two dimensional electron gas which acts as the channel has a high mobility. The electrons in the two dimensional electron gas of the heterojunction interface between Al In As mixed crystal layer and Ga In As mixed crystal layer can have a higher mobility about 13.000 cm²/V.sec under a room temperature than the electron mobility in the hetero junction between the Ga As layer and Al Ga As mixed crystal layer disclosed in the Japanese patent publication 53714/1984 and Japanese Journal of Applied Physics vol.19, 1980 L225. FETs using the hetero junction between Al In As layer and Ga In As layer to which the present invention pertains can provide a higher transconductance and high speed operation than the FET using Al Ga As/Ga As heterojunction. FETs using the hetero junction between Al In As layer and Ga In As layer have been disclosed in IEEE Electron Device Letters EDL Vol. 1-8 page 154, wherein the non-doped Al In As layer is formed on the Ga In As layer doped with n-type impurities and a gate electrode is formed on the Al In As layer. The FETs of the above type are effective to increase the gate break down voltage. However, in these FETs, the two dimensional electron gas is not included because n-type impurities are not doped into the Al In As layer. The electron mobility under the room temperature of the Ga In As layer which acts as the channel is low because of a high density of n-type impurities such as 1.2 x 10¹⁷ cm⁻³ in Ga In As layer which causes the electrons flowing between the source and drain of the FET to be scattered by the ionized n-type impurities. Therefore, in the FETs of the above type, it cannot be expected to increase the transconductance and high speed operation. An object of the present invention is to provide a field effect transistor which is able to operate with a high transconductance and a high speed operation. According to one aspect of the invention, the field effect transistor initially defined is characterized in that the mixed crystal in said first semiconductor layer is GaInAs; the mixed crystal of said second semiconductor layer is Al In As; and said n-type impurity is substantially absent in a region of at least 5 nm depth measured from the surface of the second semiconductor layer. According to another aspect of the invention, there is provided a field effect transistor comprising: a substrate made of semiinsulator or semiconductor of one conductivity type; working layers formed on the substrate; a source region and drain region provided in the working layer and channel region between the source and drain region; and a gate electrode formed on the channel region, said working layers comprising a first semiconductor layer of mixed crystal formed on the substrate, a second semiconductor layer of non-doped mixed crystal formed on the first semiconductor layer, and a third semiconductor layer of mixed crystal containing n-type impurity in such a manner that the density of the impurity in the region near the gate electrode is lower than the density of the n-type impurity in the region near the second semiconductor layer, characterized in that the mixed crystal of said first layer is Ga In As; the mixed crystal of said second and third layers is Al In As; and said n-type impurity is substantially absent in a region of at least 5 nm depth measured from the surface of the second semiconductor layer. For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figs. 1 and 2 are cross-sectional views showing a preferred embodiment of a field effect transistor according to the present invention; Fig. 3 and 4 show respectively distribution of n-type impurity in the Al In As semiconductor layer; Fig. 5 is a graph showing a characteristic curve of the current and voltage in the Schottky junction of Al In As layer to which Si of 1 x 10¹⁷ cm⁻³ is doped; Fig. 6 is a graph showing a characteristic curve of the current and voltage in the Schottky junction of Al In As layer to which no impurity is doped in the region of 12 nm from the upper surface of Al In As layer; Fig. 7 is a graph showing a characteristic curve of the drain current and the drain voltage of a conventional field effect transistor, Fig. 8 is a graph showing a characteristic curve of the drain current and the drain voltage of the FET according to the present invention. In general, in the Schottky junction comprising semiconductor material containing n-type impurities of a density N D , the backward breakdown voltage is proportional to the inverse of the density N D . Decrement of the impurity density in the semiconductor improves the backward breakdown voltage in the Schottky junction. However, decrement of the density of the n-type impurity in Al In As layer decreases the two dimensional electron gas in Ga In As layer, thereby resulting in less FET performance such as a high source resistance, less gate swing amplitude. The electron density of the two dimensional electron gas near the heterojunction in the semiconductor layer near the substrate can be increased to a maximum value defined by the electron affinity in the heterojunction under the thermal equilibrium by enhancing the n-type impurity of the Al In As layer. In the FETs hereinafter described the density of the n-type impurity in Al In As layer is changed so that the density near the substrate is increased, thereby developing two dimensional electron gas of a high electron density and the density of the n-type impurity in the Al In As layer is made low near the gate electrode so as to provide a gate electrode of a high break down voltage. According to an experiment conducted by the inventor, in case a Schottky junction is formed on Al In As layer which is formed by MBE method on the In P substrate of 480 o C, when the density of the n-type impurity which is Si exceeds 1 x 10¹⁷ cm⁻³, the backward break down voltage is abruptly reduced and break down occurs upon application of about 2 volts in the backward direction. Fig. 5 shows current and voltage characteristics at the Schottky junction formed directly on Al In As layer containing Si of 1 x 10¹⁷ cm⁻³. By referring to Fig. 5, it is understood that a high backward break down voltage cannot be obtained so far as the density of the impurity exceeds 1 x 10¹⁷ cm⁻³ . Fig. 6 shows a current voltage characteristic at the Schottky junction of the Schottky metal formed on Al In As layer in which Si is contained more than 1 x 10¹⁸ cm⁻³ near the substrate and Si is not contained in the region of 12 nm (120 A) from the upper surface of the Al In As layer. By Fig. 6, when the Schottky junction is formed on the portion containing low n-type impurity in Al In As layer, the backward break down voltage is higher than 6 volts. As hereinafter described, the backward gate break down voltage of FETs can be increased. Therefore, a high drain voltage can be applied without causing break down in the gate of the FETs, namely the saturation characteristic of the drain voltage and current can be improved. Referring to Fig. 1, Ga In As layer 2 is formed with a thickness of 1 micron by MBE method on a substrate 1 made of In P semiconductor. In order to improve the crystalline quality, a buffer layer (not shown) of Al In As layer may be formed between the substrate 1 and Ga In As layer 2. Subsequently, Al In As layer 3 is formed on the Ga In As layer 2 with a thickness of 40 nm (400 Å.) An n-type impurity such as Si is doped in the Al In As layer 3. The distribution of the n-type impurity in a direction of thickness is in such a manner that the impurity is absent in the range from the upper surface of the Al In As layer 3 to 10 nm (100 A) depth and the density of Si impurity in the range from 10 to 40 nm (100 to 400 A) depth is 10¹⁸/cm³ as shown in Fig. 3. In place of the impurity distribution mentioned above, the density of the impurity may be increased linearly as the depth becomes large to 20 nm (200 Å) deep and the density of the impurity is constant in the range deeper than 20 nm (200 Å.) In any case it is essential that the density of the n-type impurity is minimized at the upper surface of the Al In As layer 3 and the density of the n-type impurity increases as the depth increases. A gate metallized layer 4 is formed on the upper surface of the Al In As layer 3 using metal or metal compound such as Pt, Al, W or Silicide by way of evaporation or sputtering. A source metallized layer 5 and a drain metallized layer 6 are formed on both sides of the gate metallized layer 4 by evaporation so that the metallized layers reach the Ga In As layer 2. Both of the source and drain metallized layers are formed on the Ga In As layer using Au, Ge or Ni which forms an ohmic electrode by evaporation and the semiconductor device with the metallized layers is processed under a temperature of 400 o C for 4 minutes. Referring to Fig. 2 showing another embodiment of the present invention, the substrate 1 and Ga In As layer 2 are formed in the same manner as mentioned in the embodiment shown in Fig. 1. A first Al In As layer 3-1 is formed with 2 nm (20 A) thickness on the Ga In As layer 2 and a second Al In As layer 3-2 is formed on the first Al In As layer 3-1 with 40 nm (400 A) thickness. The second Al In As layer 3-2 is doped by n-type impurity such as Si. The distribution of the density of the impurity in the second layer 3-2 is such that the impurity is substantially 0 near the upper surface of the second layer 3-2 and the density increases as the depth increases in a stepped manner as shown in Fig. 3 or the density may be increased linearly as shown in Fig. 4. In any event it is essential that the density is low near the supper surface of the second layer and increases as the depth increases. In the FETs shown in Fig. 1 or 2, upon application of a positive voltage to the gate electrode 4, electrons are induced in the Ga In As layer 2 and a conduction channel region can be formed near the hetero junction by a potential barrier defined on the interface between Al In As layer 3 (in case of Fig. 3 the first layer 3-1) and Ga In As layer 2. Thus a current can flow between the source metallized layer 5 and drain metallized layer 6 through the channel. The number of the electrons in the channel can be controlled by the voltage applied to the gate electrode 4, so that transconductance between the source electrode 5 drain electrode 6 can be controlled. Fig. 8 shows graphs of drain current and drain voltage characteristics of the FET shown in Fig. 1 made by MBE method with 480 o C of the substrate 1.

Claims: A field effect transistor comprising: a substrate (1) made of semiinsulator or semiconductor of one conductivity type; working layers (2,3) formed on the substrate (1); a source region (5) and a drain region (6) provided in the working layer and a channel region between the source and drain region; and a gate electrode (4) formed on the channel region, said working layers comprising a first semiconductor layer (2) of mixed crystal formed on the substrate (1) and a second semiconductor layer (3) formed on the first semiconductor layer and made of mixed crystal containing n-type impurity in such a manner that the density of the impurity is lower in the region near the gate electrode (4) than in the region near the first semiconductor layer, characterized in that the mixed crystal in said first semiconductor layer (2) is GaInAs; the mixed crystal of said second semiconductor layer (3) is AlInAs; and said n-type impurity is substantially absent in a region of at least 5 nm depth measured from the surface of the second semiconductor layer (3). A field effect transistor according to claim 1, wherein the density of the n-type impurity changes stepwise in the second semiconductor layer. A field effect transistor according to claim 2 wherein the depth at which the density of the n-type impurity changes is in the range of 5 nm to 20 nm from the upper surface of the second semiconductor layer. A field effect transistor according to claim 1, wherein the density of the n-type impurity changes monotonically as the depth increases. A field effect transistor according to claim 4 wherein the density of the n-type impurity is less than 10¹⁷ cm⁻³ in a region from the upper surface of the second semiconductor layer to 10 nm depth. A field effect transistor comprising: a substrate (1) made of semiinsulator or semiconductor of one conductivity type; working layers (2,3) formed on the substrate (1); a source region (5) and drain region (6) provided in the working layer and channel region between the source and drain region; and a gate electrode (4) formed on the channel region, said working layers comprising a first semiconductor layer (2) of mixed crystal formed on the substrate (1), second semiconductor layer (3-1) of non-doped mixed crystal formed on the first semiconductor layer, and a third semiconductor layer (3-1) of mixed crystal containing n-type impurity in such a manner that the density of the impurity in the region near the gate electrode is lower than the density of the n-type impurity in the region near the second semiconductor layer, characterized in that the mixed crystal of said first layer is GaInAs; the mixed crystal of said second and third layers is AlInAs; and said n-type impurity is substantially absent in a region of at least 5 nm depth measured from the surface of the second semiconductor layer (2-2). A field effect transistor according to claim 6, wherein the n-type impurity in the third semiconductor is changed stepwise at a predetermined depth. A field effect transistor according to claim 7, wherein the depth at which the density of the n-type impurity changes is in the range of 5 nm to 20 nm from the upper surface of the third semiconductor layer and the density of the n-type impurity in the region nearest to the gate electrode is less than 10¹⁷ cm⁻³. A field effect transistor according to claim 6, wherein the density of the n-type impurity in the third semiconductor layer changes monotonically. A field effect transistor according to claim 9, wherein the density of the n-type impurity of the third semiconductor layer is less than 10¹⁷ cm⁻³ in a range from the upper surface of the third semiconductor layer to 10 nm depth.

Inventors: SASAKI, GORO OSAKA WORKS, SUMITOMO ELEC.IND.LTD.
Applicants: SUMITOMO ELECTRIC INDUSTRIES LIMITED
Application year: 1986
Main classification: H01L29
IPC codes: H01L29, H01L21