METHOD OF MANUFACTURING AN INSULATED GATE FIELD EFFECT DEVICE

Abstract: A method of manufacturing an insulated gate field effect device comprising the steps of providing on a silicon region (11) of a first conductivity type a gate insulating layer (17) and a doped polysilicon layer (19), providing an anti-oxidation mask (21, 23) on the polysilicon, oxidizing the unmasked polysilicon including laterally oxidized portions (31) under the edge of said mask thereby diffusing the dopant into region (11) to form source and drain regions (27, 29) with lightly doped extensions (45, 46) of the second conductivity type, then (plasma) etching the oxidized polysilicon and the underlying gate insulating layer (17) except said laterally oxidized portions (31) using said mask as an etch mask, and ion implanting highly doped source and drain portions (50, 51) in the export source and drain areas (32, 34).

Description: The present invention relates to a methods manufacturing an insulated gate field effect device comprising the steps of forming an electrically insulating layer of silicon oxide on the surface of a semiconductor region of a first conductivity type, depositing a doped polysilicon layer on said insulating layer, providing a patterned anti-oxidation masking layer on said polysilicon layer leaving a mask over at least the area in which the gate electrode is to he formed, diffusing the dopant from said polysiliconlayer through said insulating layer into said semiconductor region by thermal oxidation of said polysilicon layer where it is not covered by said mask thus forming source and drain regions of the second, opposite conductivity type on both sides of said mask, said diffusion being prevented where said oxidation has been prevented by said mask, the unoxidized portion of said polysilicon layer forming the gate electrode, and subsequently producing highly doped source and drain portions of the second conductivity type. In field effect devices, such as an insulated gate field effect transistor (IGFET), it is desirable that the source and drain zones in the immediate proximity of the gate electrode have a lightly doped extension. This is particularly important in field effect devices having a very small channel length. The lightly doped extension in such devices increases the breakdown voltage of the drain gate junction and prevents the injection of hot charge carriers into the gate dielectric. A method as described above is known from the article by Goto et al. "A new selfaligned source/drain diffusion technology from selectively oxidized polysilicon", IEDM 1979, p.585-588. In this prior art technique, prior to depositing the polysilicon layer source- and drain windows are etched in the insulating layer. Then, after depositing the polysilicon layer, the said masking layer is provided also above said window, and then the oxidation is carried out thus forming weakly doped and highly doped source and drain portions. The method requires a masking step for forming the said windows as well as a rather critical positioning step to provide the masking layer exactly above the windows. Moreover the dopant of the highly doped source/drain portions cannot be chosen independently of the dopant of the weakly doped portions. These are disadvantages in very large scale integration where not only the number of positioning steps should he kept as low as possible in order to increase the reproducibility, but also the dopants should he chosen freely so as to he able to produce source- and drain regions of the required depth and doping concentration. It is an object of the present invention to provide a highly reproducible method for manufacturing an insulated gate field effect transistor with very short lightly doped source and drain extensions, with a high degree of selfalignment. According to the invention a method as described in the introductory part is characterized in that said thermal oxidation is continued so as to form laterally oxidized polysilicon portions under the edges of said mask, said diffusion producing lightly doped source- and drain extensions under said laterally oxidized portions, that the oxidized polysilicon and the underlying portions of said insulating layer are then etched away except for said laterally oxidized portions which are protected from the etching by said mask, thus exposing parts of said source and drain regions, after which ions are implanted into said exposed source- and drain region parts to produce said highly doped source and drain portions, said mask and said laterally oxidized portions shielding said lightly doped extensions during said ion implantation. Other objects, features and advantages of the invention will he apparent from the following description and appended claims when considered in conjunction with the accompanying drawing in which: Figure 1 is a cross-section of a device at an interim stage of its manufacture in accordance with the method of the invention; Figure 2 is a cross-section of the device of Figure 1 at a later stage in its manufacture; Figure 3 is a cross-section of the device of Figures 1 and 2 at a still later stage of its manufacture. Figure 4 is a cross-section of the device of Figure 3 after one type of metallization; and Figure 5 is a cross-section of the device of Figure 3 after another type of metallization. The drawing is purely schematic and not to scale. This is particularly so with respect to the thicknesses of the elements of the device shown. Corresponding parts are designated by the same reference numerals in the various figures. Semiconductor regions of the same conductivity type are cross-hatched in the same direction. Figure 1 shows a device made in accordance with the method of the invention at an interim stage in the practice of the invention. The method starts with a semiconductor body 11 which in this case is chosen to be of p-type silicon. As will he apparent to those skilled in the art, however, the body could be of the n-type conductivity. An approximately one (1) micron (1 micron = 1 micrometre) thick layer 13 of silicon oxide surrounding part of the surface 15 is provided on body 11 by using any known method, for exampple, pyrolitic oxidation and etching, or local oxidation of silicon (LOCOS). Surface 15 of semiconductor body 11 is covered with an electrically insulating layer 17, also of silicon oxide, approximately 200 to 500 angstroms (1 angstrom = 0.1 nanometre) thick. This forms the gate oxide and is obtained, for example, by thermal oxidation. A polycrystalline silicon layer 19 between .15 and .25 microns thick is deposited on insulating layer 17 and on field oxide 13 in a typical manner such as by decomposition of a gaseous silicon compound. Polysilicon layer 19 is doped with an n-type dopant such as phosphorus, although other type dopants may also be used. Oxychloride phosphorus (POCl₃) is presently preferred as a doping source for this purpose. (If the method started with an n-type body obviously a p-type dopant, such as boron, would be used.) In a manner well known in semiconductor technology, a .05 micron thick silicon oxide layer 21 may optionally be provided over layer 19. On top of this by means of low pressure chemical vapor deposition, a .08 to .2 micron thick silicon nitride layer 23 is provided. By way of photolithographic etching methods conventionally used in semiconductor technology, layers 21 and 23 are then given a certain pattern in which a layer of photolacquer (not shown) may be used as a mask. Phosphoric acid may be used as an etchant for the silicon nitride and a hydrofluoric acid containing solution may be used as an etchant for the silicon oxide. At that point in the method, a device such as shown in Figure 1 is obtained. Polysilicon layer 19 is then oxidized by heat treating in an oxidizing atmosphere. This oxidizes the polysilicon to form the oxide layer 25. It also diffuses the n-type dopant from the polysilicon layer through insulating layer 17 into semiconductor body 11 on both sides of the mask formed by nitride layer 23 to form source and drain regions 27 and 29. By properly selecting the resistivity of semiconductor body 11, the oxidation temperature and time and the polysilicon thickness and resistivity, the desired junction depth of source and drain regions 27 and 29 and the lateral oxidation and diffusion under mask 23 is appropriately controlled. For thin gate oxides, for example, a high pressure polyoxidation at low temperatures such as 900⁰C can be used to prevent the formation of junctions that are too deep. This process of forming junctions through polysilicon oxidation is known and provides source and drain regions (27,29) with lightly doped extensions (45,46) as shown in Figure 2. By controlling the amount of lateral oxidation that takes place under mask 23 the size of gate electrode 19 can he predetermined. After oxidation an anisotropic reactive ion etching is performed using the nitride layer 23 as a mask. During etching, the laterally oxidized sections or spacers 31 (Figure 3) are protected from etching by mask 23. As can be seen, insulating layer 17 not protected by mask 23 is also etched away to expose the upper surfaces 32 and 34 of source and drain regions 27 and 29. Arsenic is then ion implanted into the exposed source and drain regions to produce highly doped regions (50,51) of an n-plus type conductivity. As a result, source and drain regions are produced with n-type conductivity extensions (45,46) under spacers 31 and n+type conductivity regions in the prescribed contact areas. (If p-type source and drain regions are formed in an n-type body, a p+type conductivity dopant such as heron, would he used in the ion implantation step). Phosphor silicate glass 33 is deposited on top of the entire device. Contact openings are etched in this glass by the use of oversized masks in any well known manner. Aluminium silicon 35 is then deposited in the contact openings to provide direct electrical contact to the source and drain regions. By using a photolithographic process to etch away the undesired aluminium, the device shown in Figure 4 is produced. If it is desired to add a silicide layer before metallization, a device as that shown in Figure 5 is produced. Starting with the interim device of Figure 3, a thin oxide is grown on the contact areas 32 and 34 of the source and drain. The silicon nitride layer 23 is then etched away. The thin oxide on the source and drain contact areas 32 and 34 and the optional pad oxide 21 (Figure 1), if any, is also etched away. In the preferred embodiment, titanium is then deposited on the source and drain contact areas and on gate 19 to form the silicide layers 37 shown in Figure 5. A thin oxide 41 is then grown over the silicide. Silicon nitride 39 is then deposited on top of the thin oxide layer. With an oversized mask of photoresist, the silicon nitride and the thin oxide layer are both etched away to leave the patterned silicon nitride 39 as shown in Figure 5 and the oxide layers 41 as shown in the same figure. After this etching, phosphor silicate glass 33 is deposited on the device and etched to expose contact areas. Aluminium silicon contacts 35 are then deposited in any well known manner. From the foregoing, it will be apparent to those skilled in the art that both NMOS, PMOS and CMOS devices can be fabricated from the disclosed self-aligned method. It is understood that various modifications to the above-described method and device will became evident to those skilled in the art and that the arrangement described herein is for illustrative purposes and is not to he considered restrictive. In particular the body 11 may consist of a semiconductor material other than silicon.

Claims: A method of manufacturing an insulated gate field effect device comprising the steps of forming an electrically insulating layer (17) of silicon oxide on the surface of a semiconductor region (11) of a first conductivity type, depositing a doped polysilicon layer (19) on said insulating layer (17), providing a patterned anti-oxidation masking layer (23) on said polysilicon layer (19) leaving a mask (23) over at least the area in which a gate electrode is to be formed, diffusing the dopant from said polysilicon layer (19) through said insulating layer (17) into said semiconductor region (11) by thermal oxidation of said polysilicon layer (19) where it is not covered by said mask (23) thus forming source and drain regions (27,29) of the second , opposite conductivity type on both sides of said mask (23), said diffusion being prevented where said oxidation has been prevented by said mask (23), the unoxidized portion of said polysilicon layer (19) forming the gate electrode (19), and subsequently producing highly doped source and drain portions (50,51) of the second conductivity type, characterized in that said thermal oxidation is continued so as to form laterally oxidized polysilicon portions (31) under the edges of said mask (23), said diffusion producing lightly doped source- and drain extensions (45,46) under said laterally oxidized portions (31), that the oxidized polysilicon (25) and the underlying portions of said insulating layer (17) are then etched away except for said laterally oxidized portions (31) which are protected from the etching by said mask (23), thus exposing parts (32,34) of said source and drain regions (27,29), after which ions are implanted into said exposed source- and drain region parts (32,34) to produce said highly doped source and drain portions (50,51), said mask (23) and said laterally oxidized portions (31) shielding said lightly doped extensions (45,46) during said ion implantation. A method as claimed in Claim 1, characterized in that said source and drain regions (27,29) are surrounded and delimited by a field oxide layer (13) which is thicker than said insulating layer (17). A method as claimed in Claim 1 or Claim 2, characterized in that etching step is carried out by plasma-etching. A method as claimed in any one of the preceding claims, characterized in that after said ion implantation step the masking layer (23) is etched away, after which a metal (35) is deposited on the exposed source and drain region parts (32,34) and on the gate electrode (19) and heated so as to form metal silicide layers (37) thereon. A method as claimed in any one of the preceding claims characterized in that said masking layer (23) comprises silicon nitride. A method as claimed in any one of the preceding claims characterized in that said polysilicon layer (19) is phosphorus-doped. A method as claimed in any one of the preceding claims characterized in that said implantation is done with arsenic ions. A method as claimed in any one of Claims 1 to 5 characterized in that said polysilicon layer (19) is boron-doped and that said implantation is done with boron ions.

Inventors: CHEN, TEH-YI JAMES
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1986
Main classification: H01L21
IPC codes: H01L21, H01L29