VIRTUAL MEMORY ADDRESS FETCHING

Abstract: A hybrid hardware/software implementation of a translation look-aside buffer (TLB) is disclosed for improving the efficiency of address translation in a computing system utilizing a virtually addressed memory. Through the use of the present invention, complex hashing routines can be used to address entries in a virtual address translation table (VSTT) within the system's physical memory, without increasing the complexity or significantly reducing the performance of the TLB fetch hardware.

Description: Background of the Invention Modern computers frequently are constructed to permit user programs to execute code and fetch data from virtual memory addresses. However, data and memory modules must still be addressed with physical addresses. Therefore, hardware tables are used to translate virtual addresses into physical addresses. Such a hardware table is called a Virtual Address Translation Table (VATT). In order to improve the efficiency of virtual to physical address translation, the VATT can include a section of high speed register memory of sufficient speed to execute instructions within a single processor cycle. Such a VATT is typically located at or near a high speed memory portion of the computer processor, in which memory is stored the most recently used address translation entries. This high speed memory section is referred to as a Translation Look-aside Buffer (TLB). Frequently, as programs progress, address translations will be found in the TLB, thus speeding up program execution. However, when an address translation is needed which is not in the TLB, a new table entry must be fetched by hardware from the VATT and loaded as an entry into the TLB. Methods have been developed to increase the speed with which the TLB entries can be updated. One such method is the use of a simple organization of the entries within the VATT. For example, the VATT can be a simple table of sequential virtual memory addresses or a simple, hierarchical extension of a sequential table as explained in "Computer structures: Principles and Examples" by D. Siewiorek, C. Bell, and A. Newell, McGraw Hill, 1982, pp. 227-243. Such simple organizations reduce the complexity and cost of the TLB fetch hardware, but significantly limit the structure of addresses within the VATT. More complex VATT formats are desirable because the virtual memory address space may be significantly larger than the actual physical address space implemented in hardware. Thus, the size of the sequential virtual address tables or the hierarchical structures containing such tables can exceed the size of the physical memory. The system must then swap portions of the tables between the physical memory and an alternate slow memory device such as a disc when access to entire table is required. A more scalable approach is the use of hashing functions as described in "Translating a Large Virtual Address" by M. Houdek, G. Mitchell, IBM system 38 Technical Development, IBM GS80-0239, 1978, pp. 22-25 to translate virtual addresses in the TLB to physical addresses in the VATT. A hashing function is a pseudo-random method for efficient searching of the VATT for a translation table entry. Although the use of hashing functions is a flexible method for searching the VATT entries, it typically degrades the speed of the search, or increases the cost of TLB fetch hardware. The IBM Technical Disclosure Bulletin, Vol. 24, No. 9, February 1982, pages 4714-5 discloses a two-level DLAT design to improve cost/performance ratio. Summary of the Invention The present invention discloses a hybrid software and hardware mechanism for updating the TLB. A simple hardware configuration is used to implement the fetching of most TLB entries, which is the critical factor affecting the average speed of address translation. This hardware is then coupled to software which is used to implement the complex, but infrequently used portion of the TLB entry fetch operation. The TLB is segmented into two hardware portions: a high speed primary TLB located at or near the processor, and a slower secondary TLB located within the processor or in physically addressed main memory. Virtual address translation is first attempted by the processor via the primary TLB, and if the virtual address translation is not contained within the primary TLB, hardware is used to fetch a new TLB entry from the secondary TLB. If the virtual address translation is not contained within the secondary TLB, a processor trap occurs to interrupt or halt the operation of the processor and software located within the processor is used to transfer the desired entry from the VATT to the secondary TLB or to both the primary and secondary TLB. Because the transfers from the VATT to the secondary TLB or from the VATT to the primary and secondary TLB are infrequent and occur in software, the complexity of the VATT does not significantly affect overall processor performance or add to system complexity. Therefore, the present invention is capable of supporting complex VATT structures, which reduces the memory storage required for the VATT without increasing the cost and complexity of the TLB fetch hardware. Brief Description of the Drawings Figure 1 shows a block diagram of the hybrid TLB fetch hardware according to a first embodiment of the present invention. Figure 2 shows a two-way associative-mapped table for use according to Figure 1. Figure 3 shows a flow chart for the software according to a preferred embodiment of the present invention. Figure 4 shows a block diagram of the hybrid TLB fetch hardware according to a second embodiment of the present invention. Description of the Preferred Embodiment Figure 1 shows a block diagram of the hardware system 100 for hybrid TLB fetching according to a first embodiment of the present invention. The processor 110 contains a small number of the most recently used virtual to physical address translations in a primary TLB 120. The primary TLB 120 will typically be implemented with high-speed register files or random-access memory chips (RAMs), and will typically contain between four and 64 table entries. The actual size selected for the primary TLB 120 will depend on the number of memory cycles lost when a desired TLB entry is not found in the primary TLB 120. For example, in a system in which only four memory cycles are lost when a desired TLB entry is not found in the primary TLB 120 (i.e., a low "miss" penalty), the primary TLB 120 will typically hold only 4 entries, while in a system in which sixteen memory cycles are lost when a desired TLB entry is not found in the primary TLB 120 (i.e., a high "miss" penalty), the primary TLB 120 will typically hold 16 to 64 entries. Initially, the processor 110 will search for a new address translation directly in the primary TLB 120. If this address translation is found in the primary TLB 120, the processor 110 will use the address translation to generate a physical address and fetch the desired code or data from the physical memory 130 via a main memory bus 140. On the other hand, if the address does not map any of the current entries in the primary TLB 120, conventional state machine fetch hardware 145 within the processor 110 is used to fetch the new translation entry from a secondary TLB 160 via the memory bus 140. The secondary TLB 160 is typically implemented with general purpose RAM. Because access to the secondary TLB 160 is less frequent than access to the primary TLB 120, the secondary TLB 160 can typically be 4 to 16 times slower than the primary TLB 120, and typically can therefore economically contain 16 times the capacity of the primary TLB 120. The secondary TLB 160 can be organized as a direct-mapped table (i.e., each table entry corresponds to one address translation) in order to simplify the complexity of the fetch hardware 145. Alternatively, the secondary TLB 160 may be organized as a two-way associative-mapped table 200 as shown in Figure 2. In the two-way mapped table 200, the virtual address from the processor 110 is processed by Boolean logic 210, which typically consists of exclusive-OR gates, to generate a pair of indexes 220 and 230 to a pair of address sub-tables 240 and 250, each sub-table 240 and 250 containing one-half of the total secondary TLB entries. The VATT table entry fetch proceeds as follows. A VATT table entry 260 at index 220 of table 240 is transferred to the primary TLB 120. If this first entry 260 does not contain the correct virtual address, the correct virtual address at a second table entry 270 at index 230 of table 250 is transferred to the primary TLB 120. Referring again to Figure 1, after the new translation entry from the secondary TLB 160 is transferred via memory bus 140 to the fetch hardware 145, the new entry is used to update the primary TLB 120 so that the processor 110 can use the new entry to fetch the indicated code or data from the memory 130 via the memory bus 140. If the new virtual address translation is not contained in the relatively large secondary TLB 160, a processor trap is generated by the TLB fetch hardware 145 to interrupt the processor 110. During this trap, software as shown in Figure 3 within the processor 110 transfers the desired data from a Virtual Address Translation Table (VATT) 170 to the secondary TLB 160 or to both the primary TLB 120 and the secondary TLB 160. The VATT 170 should be large enough to hold the entire address translation table, as well as a hashing table of desired complexity, and will typically be at least 4 times slower than the secondary TLB 160 because of the complexity involved in using a hash table. Once the new virtual address translation is finally received by the processor 110, the software returns from the trap of the processor 110 and the processor 110 re-executes the instruction which caused the trap. A second embodiment of the hardware system 400 for hybrid TLB fetching is shown in Figure 4. In contrast to the embodiment shown in Figure 1 in which the primary TLB 120 is located in the memory 130, the system 400 utilizes a separate secondary TLB 410 connected to a processor 415 via a separate TLB bus 420. The separate secondary TLB 410 is ordinarily more expensive to implement than that shown in Figure 1 due to the added cost of a separate memory module and the added complexity of the TLB bus 420, but the system 400 is capable of higher performance since the speed of the memory elements within the secondary TLB 410 can be selected independently of the speed of the memory elements within memory 430 and VATT 440, and the speed of the TLB bus 420 can be tailored independently of the speed of the main memory bus 450 and the speed of fetch hardware 460. Further, the secondary TLB 410 can actually be located immediately adjacent to or actually within the processor 415, to further increase performance if desired. As shown in Figure 3, after a secondary TLB trap is encountered, the software calculates a VATT hash table entry to determine a VATT index from the physical memory 130. A VATT entry is then fetched from the physical memory 130 based on the hash table entry. A comparison is made between the virtual address from the processor 110 and the VATT entry. If the comparison is valid, the VATT entry is moved from the physical memory 130 to the secondary TLB 160 (or to both the primary TLB 120 and to the secondary TLB 160) and the software returns from the secondary TLB trap and the processor hardware 110 re-executes the instruction which caused the trap. On the other hand, if the comparison between the virtual address from the processor 110 and the VATT entry is not valid, a test is performed to determine if an alternate hash table entry exits. If one or more such an alternate VATT entries exist, each entry is in turn tested to determine if the virtual address from the processor 110 and the VATT are equal. However, if no alternate VATT entry exits, or after all available alternate VATT entries have been exhausted, a fault trap is made to a page in the memory to execute operating system software to report that the desired address does not exist in the physical memory 130. Because the most recent address translations reside in the high speed primary TLB 120, memory accessing can be done very quickly (typically in a single processor cycle) with a minimum of hardware. In addition, because transfers from the VATT 170 to the secondary TLB 160 are relatively infrequent (typically less than 0.1 percent of the time) and because the VATT-to-secondary TLB transfers occur in software, the complexity and size of the VATT 170 does not significantly effect the performance or complexity of the processor 110.

Claims: A computer system having a virtually addressable memory, said system comprising: a processor having a hardware primary translation look-aside buffer (120) containing a first set of data representative of a first set of recently used virtual-to-physical address translations, said processor first attempting virtual address translation via said primary translation look-aside buffer; and a physical memory (130) coupled to the processor by a first bus (140), said physical memory having a hardware secondary translation look-aside buffer (160) coupled to the first bus for providing a second set of data to the processor, said second set of data representative of a second set of virtual-to-physical address translations, said secondary translation look-aside buffer being fetched if said primary translation look-aside buffer does not contain the desired translation and a virtual address translation table means (VATT) coupled to the secondary translation look-aside buffer for providing a third set of data to the processor, said processor having software for transferring entries from said third set of data to said secondary translation look-aside buffer if said secondary translation look-aside buffer does not contain the desired translation, said third set of data representative of all virtual-to-physical address translations needed to access data located in the physical memory. A computer system as in claim 1, wherein said processor further comprises fetch means (145) coupled to the primary translation look-aside buffer and the first bus, said fetch means for fetching the second set of data from the secondary translation look-aside buffer. A computer system as in claim 1, wherein the virtual address translation table means comprises hashing means for distributing virtual address entries throughout allocated portions of the physical memory. A computer system as in claim 3, wherein the hashing means comprises a hashing function located in software. A computer system as in claim 1, wherein the memory access speed of the primary translation look-aside buffer is greater than the memory access speed of the secondary translation look-aside buffer. A computer system as in claim 5, wherein the memory size of the primary translation look-aside buffer is less than the memory size of the secondary translation look-aside buffer. A computer system as in claim 1, wherein the processor further comprises trap means for interrupting operation of the processor while entries from the third set of data are transferred from the virtual address translation table to the secondary translation look-aside buffer. A computer system as in claim 1, wherein the processor further comprises trap means for interrupting operation of the processor while entries from the third set of data are transferred from the virtual address translation table to both the primary and secondary translation look-aside buffer. A computer system as in claim 1, wherein the third set of data comprises a set of virtual addresses corresponding to a set of physical addresses located in the physical memory. A computer system having a virtually addressable memory, said system comprising: a processor having a hardware primary translation look-aside buffer (425) containing a first set of data representative of a first set of recently used virtual-to-physical address translations, said processors first attempting virtual address translation via said primary translation look-aside buffer; a hardware secondary translation look-aside buffer (410) coupled to the primary translation look-aside buffer by a TLB bus (420) for providing a second set of data to the processor, said second set of data representative of a second set of virtual-to-physical address translations, said secondary translation look-aside buffer being fetched if said primary translation look-aside buffer does not contain the desired translation; and a physical memory coupled to the processor by a first bus (450), said physical memory having a virtual address translation table means (VATT) coupled to the secondary translation look-aside buffer for providing a third set of data to the processor, said processor having software for transferring entries from said third set of data to said secondary translation look-aside buffer if said secondary translation look-aside buffer does not contain the desired translation, said third set of data representative of all virtual-to-physical address translations needed to access data located in the physical memory. A computer system as in claim 10, wherein said processor further comprises fetch means (460) coupled to the primary translation look-aside buffer and the first bus, said fetch means for fetching the second set of data from the secondary translation look-aside buffer. A computer system as in claim 10, wherein the virtual address translation table means comprises hashing means for distributing virtual address entries throughout allocated portions of the physical memory. A computer system as in claim 12, wherein the hashing means comprises a hashing function located in software. A computer system as in claim 10, wherein the memory access speed of the primary translation look-aside buffer is greater than the memory access speed of the secondary translation look-aside buffer. A computer system as in claim 14, wherein the memory size of the primary translation look-aside buffer is less than the memory size of the secondary translation look-aside buffer. A computer system as in claim 10, wherein the processor further comprises trap means for interrupting operation of the processor while entries from the third set of data are transferred from the virtual address translation table to the secondary translation look-aside buffer. A computer system as in claim 10, wherein the processor further comprises trap means for interrupting operation of the processor while entries from the third set of data are transferred from the virtual address translation table to both the primary and secondary translation look-aside buffer. A computer system as in claim 10, wherein the third set of data comprises a set of virtual addresses corresponding to a set of physical addresses located in the physical memory. A method for addressing a physical memory in a virtual addressable computer system, said method comprising the steps of: (a) using hardware to attempt to fetch a virtual-to-physical address translation by a processor from a primary translation look-aside buffer; (b) using hardware to attempt to fetch the address translation from a secondary translation look-aside buffer if the address translation is not in the primary translation look-aside buffer; and (c) using software to fetch the address translation from a virtual address translation table to the secondary translation look-aside buffer if the address translation is not in either of the primary or secondary translation look-aside buffers. A method as in claim 19 further comprising during step (c) the step of (d) interrupting operation of the processor. A method for addressing a physical memory in a virtual addressable computer system, said method comprising the steps of: (a) using hardware to attempt to fetch a virtual-to-physical address translation by a processor from a primary translation look-aside buffer; (b) using hardware to attempt to fetch the address translation from a secondary translation look-aside buffer if the address translation is not in the primary translation look-aside buffer; and (c) using software to fetch the address translation from a virtual address translation table to both the primary translation look-aside buffer and the secondary translation look-aside buffer if the address translation is not in either of the primary or secondary translation look-aside buffers. A method as in claim 21 further comprising during step (c) the step of (d) interrupting operation of the processor.

Inventors: JAMES, DAVID V.
Applicants: HEWLETT-PACKARD COMPANY
Application year: 1986
Main classification: G06F12
IPC codes: G06F12