Self-aligned split gate EPROM

Abstract: A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.

Description: This invention relates to an EPROM array. Nonvolatile EPROMs may have a split gate (i.e., both a floating gate and a control gate) for controlling the writing and reading of each cell. A split gate nonvolatile EPROM with increased efficiency is disclosed in U.S. Patent No. 4,328,565 issued May 4, 1982 on an application of Harari, filed April 7, 1980. As disclosed by Harari, the floating gate in an n channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate then overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the floating gate and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain. A cell is erased either by ultraviolet illumination or by electrons from the floating gate tunneling through a region of thinned oxide. The nonsymmetrical arrangement of the control gate and floating gate with respect to source and drain allows a very dense array implementation. Other split gate structures are disclosed in an article by Barnes, et al. entitled "Operation and Characterization of N-Channel EPROM Cells", published in Solid State Electronics, Vol. 21, pages 521529 (1978) and an article by Guterman, et al. entitled "An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure", published in the IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 2, April 1979. There is also known from the prior art within the meaning of Article 54(3) EPC the document EP-A-0 164 781 which describes a method of fabricating a memory cell having a floating gate self-aligned with the drain region. In addition in US-A-4 297 719 and FR-A-2 468 972 split gate transistors for tunnel programming and erasing are described. In the accompanying drawings: Figure 1 illustrates a prior art EPROM using a single floating gate beneath the control gate; Figure 2 illustrates the split gate structure of the prior art wherein the floating gate is not self-aligned to the drain region and the control gate is formed over part of the channel region; Figure 3 illustrates a split gate structure as described in EP-A-0 164 781, wherein the floating gate is self-aligned to the drain region and overlies but is illustrated from an accurately defined portion L eff of the channel region between the source and drain and the control gate overlies the floating gate and that portion of the channel region not overlain by the floating gate but is insulated therefrom; Figure 4 illustrates the relationship between threshold voltage V tx and drain turn-on voltage V DTO for the structure of Figure 1; Figures 5a and 5b illustrate a process described in EP-A-0 164 781 and used to manufacture the self-aligned split gate structure of the invention; Figures 6a-6d illustrate the effect of the channel length L P1 under the floating gate on programming; Figures 7a and 7b show the tight envelope of operation for the nonself-aligned structure and illustrate graphically the advantages of the self-aligned split gate structure; and Figure 8 shows in schematic form a memory array formed using the self-aligned split gate structure; Figure 9a shows the layout of a portion of a high-speed EPROM of this invention incorporating the self-aligned split gate structure; Figure 9b shows in cross-section two transistors from the structure of Figure 9a; and Figure 9c shows schematically the architecture of one embodiment of the EPROM array portions of which are shown in Figures 9a and 9b. Figure 1 illustrates a typical EPROM of the prior art. In Figure 1 a memory cell comprises n ++ source region 11a and n ++ drain region 11b separated by channel region 16. Channel region 16 has an effective length L eff as shown. Overlying channel region 16 is gate dielectric 12 on which is formed a floating gate 13. Typically floating gate 13 is formed of polycrystalline silicon. Overlying floating gate 13 is insulation 14, typically thermally grown silicon dioxide. Control gate 15 is formed above floating gate 13 on insulation 14. The state of the transistor in Figure 1 is determined by the charge placed on floating gate 13. When electrons are placed on floating gate 13, the threshold voltage V tx required on gate 15 to turn on the transistor (i.e., to form an n channel between source 11a and drain 11b thereby allowing current to flow from one to the other) is much greater than when no electrons are placed on floating gate 13. As shown in Figure 1, regions 13a and 13b of floating gate 13 overlie the source 11a and drain 11b, respectively, by a small amount "Δ". Consequently, a capacitance is formed between the source 11a and floating gate region 13a and between the drain 11b and floating gate region 13b. If the overlap by gate 13 of the source 11a and the drain 11b is the amount "Δ", then the capacitance C pp between the floating gate 13 and the control gate 15 (both made of polycrystalline silicon) is given by the following equation: C pp α A pp α W(L eff + 2Δ FG,D ) In equation 1, C pp is the capacitance between the floating gate 13 and the overlying control gate 15 (this capacitance is proportional to A pp ) and A pp , the area of the floating gate 13, is just the width W of the floating gate 13 (perpendicular to the sheet of the drawing) times the length of the floating gate 13 which is (L eff + 2 Δ FG,D ). The capacitance C PROM between the floating gate 13 and the substrate 10 is proportional to the effective width W eff (i.e. the width perpendicular to the sheet of the paper of the active area underneath the floating gate 13) of the floating gate 13 times L eff . Thus the capacitance C PROM is C PROM α A PROM α W eff (L eff ) The capacitive coupling C FG,D of the floating gate 13 to the drain 11b is given by C FG,D α A FG,D α W eff (Δ FG,D ) The coupling ratio CR FG,D of the capacitive coupling C FG,D of the floating gate 13 to drain 11b to the capacitive coupling C pp of the floating gate 13 to the control gate 15 and the capacitive coupling C PROM of the floating gate 13 to the substrate 10 is CR FG,D α W eff (Δ FG,D )/[W eff (L eff )+W(L eff +2Δ FG,D )] As L eff becomes smaller and smaller the impact of the coupling of the drain on the performance of the PROM cell becomes greater and greater until in the limit, as L eff becomes very, very small, this coupling approaches 0.3 (taking into account different oxide thicknesses and the difference between W and W eff , for example). The overlay "Δ" depends on the process and is substantially fixed. Figure 2 shows the prior art split gate structure as illustrated by Harari in U. S. Patent No. 4,328,565 issued May 4, 1982. The major concern in this structure relates to the length of portion 26b of channel 26 beneath floating gate 23. The structure of Figure 2 is a nonself-aligned split gate structure. The total effective channel length 26 is defined by one mask and therefore is constant. Unfortunately, the length of the portion 26b of channel 26 beneath the floating gate 23 varies with mask alignment tolerances. Thus the effective channel length 26b depends strongly on the alignment process. As a result the best technology available today yields an effective channel length tolerance 26b no better than ±0.5 to ±0.6 µm. For a typical nominal one µm effective channel length 26b the actual channel length will vary, due to manufacturing tolerances, over the range of about 1 ± 0.6 µm. The result is a very wide variation in performance from one transistor memory cell to the next. Programming and read current are both very sensitive to channel length. Good cells will be perfect but bad cells will not work. A good device has an effective channel 26b (in one embodiment 0.8 µm) which lies between a too-short channel length (for example 0.2 microns or less, so that considering manufacturing variations there may not be any overlap at all of floating gate 23 over the channel 26 and thus there will be no programming of the cell) and a too-long channel length (for example greater than 1.4 µm) with unacceptably slow programming. The major issue in this prior art structure thus is the length of channel portion 26b (L eff ) rather than the coupling. Therefore in a structure such as that shown in Figure 2 there can be coupling between drain 21b and floating gate 23 but if the channel length 26b is not carefully controlled, the memory cell is not going to perform as expected. A major problem in the prior art EPROM of Figure 1 relates to the relationship between the program threshold voltage V tx and the drain turn on voltage V DTO of the device. V DTO is the voltage on the drain which, when capacitively coupled to the floating gate 13, turns on the transistor. As shown in Figure 4, for L eff as shown in Figure 1 increasing from about 0.5 to 1.2 µm, the program threshold V tx drops below the acceptance program threshold. On the other hand the drain turn-on voltage V DTO becomes as high as the junction breakdown voltage for L eff greater than about one µm. Below one µm, V DTO is very low and may go as low as three to five volts which causes the array of EPROMs to fail. The crossover point is shown as "A" in Figure 4. In designing a regular EPROM, the crossover point A should be such that V tx is high enough (i.e. greater than give volts) while V DTO is not too low (i.e. not lower than eight volts). However, both V DTO and V tx are quite steep at the crossover point A and thus the characteristics of the device are very sensitive to L eff . So if the tolerance on L eff is even ±0.3 µm, which is very good, then the characteristics of the device are still relatively unpredictable. Obviously the desired solution is to eliminate the effect of V DTO and optimise L eff for V tx . In accordance with the present invention as defined in the claims, the problems of the prior art may be overcome by providing a memory cell using a split gate structure containing both a control gate and a floating gate, in which the floating gate is self-aligned to the drain region. The control gate is not self-aligned. "Self-aligned" means here that the portion of the transistor channel length under the floating gate will be defined by the floating gate itself regardless of any processing mis-alignments thereby insuring a constant channel length under the floating gate. To do this, a special process is employed wherein the floating gate is used to define one edge of the drain region. The source region is defined at the same time as the drain region but the alignment of the source region relative to the floating gate is not critical so long as the source region does not underlie and is spaced from the floating gate. According to the present invention there is provided an EPROM array comprising: a substrate composed of semiconductor material; a plurality of memory cells, each memory cell including a split gate transistor; a metal source contact line running in a first direction across the array; a plurality of source diffusion lines being integrally formed in the substrate and running orthogonal to the metal source contact line; each source diffusion line having 2N portions serving as source regions of adjacent split gate transistors, where N is an integer; a contact between the metal source contact line and each of the underlying source diffusion lines for coupling a potential on the metal source contact line to each of the source regions; a plurality of metal drain lines running across the array substantially parallel to the metal source contact line, each metal drain line contacting a plurality of separate drain regions formed in said substrate, each drain region being located between two of said source regions and serving as a common drain region of a pair of adjacent split gate transistors; and a plurality of control lines formed over the array running orthogonal to the metal source contact line and the plurality of metal drain lines; the control lines having 2N portions serving as control gates of said split gate transistors; wherein each split gate transistor further comprises: a separate floating gate formed over but insulated from a channel region extending in said substrate between said source and drain regions and having a length equal to the sum of a first and a second distance, said floating gate having one edge substantially aligned with the edge of the drain region and spanning substantially the first distance so as to be separated from the edge of the source region by the second distance, and the control gate being formed over but insulated from both the floating gate and the portion of the channel region not covered by the floating gate. Thus, there is also provided a method of fabricating an EPROM array comprising forming on a substrate composed of semiconductor material: a plurality of memory cells, each memory cell including a split gate transistor; a metal source contact line running in a first direction across the array; a plurality of source diffusion lines being integrally formed in the substrate and running orthogonal to the metal source contact line; each source diffusion line having 2N portions serving as source regions of adjacent split gate transistors, where N is an integer; a contact between the metal source contact line and each of the underlying source diffusion lines for coupling a potential on the metal source contact line to each of the source regions; a plurality of metal drain lines running across the array substantially parallel to the metal source contact line, each metal drain line contacting a plurality of separate drain regions formed in said substrate, each drain region being located between two of said source regions and serving as a common drain region of a pair of adjacent split gate transistors; and a plurality of control lines formed over the array running orthogonal to the metal source contact line and the plurality of metal drain lines; the control lines having 2N portions serving as control gates of said split gate transistor; wherein further each split gate transistor is formed with a separate floating gate formed over but insulated from a channel region extending in the substrate between the source and drain regions and having a length equal to the sum of a first and a second distance, said floating gate having one edge self-aligned with the edge of the drain region and spanning substantially the first distance so as to be separated from the edge of the source region by the second distance, and the control gate being formed over but insulated from both the floating gate and the portion of the channel region not covered by the floating gate. In the claimed method, the diffused drain region is formed using the floating gate to define one edge of the drain region. In the preferred embodiment, the drain and source regions are formed by ion implantation and one edge of the floating gate defines the lateral limit of one side of the drain region. A photoresist material partially extends over the floating gate in one direction and beyond the floating gate in the other direction and the source region is defined by an opening in the portion of this photoresist extending beyond the floating gate in the other direction. The result is to form a precisely defined channel portion L eff of the channel region beneath the floating gate and a remaining relatively imprecisely defined portion of the channel region (to be controlled by a to-be-formed control gate electrode which is part of the word line) underneath the photoresist between the other edge of the floating gate and the source region. Any mis-alignment between the floating gate and the source region is covered by a to-be-formed control gate and has little effect on the operation of the memory cell while the floating gate is self-aligned to the drain region. The following detailed description relates to Figure 3 and Figures 5-9 of the accompanying drawings and is meant to be illustrative only and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the following description. In Figures 5a and 5b, only the cross-section of a single memory cell or a portion thereof is shown while in Figure 3 two cells and part of a third are shown in cross-section. It should be understood that a semiconductor integrated circuit memory made in accordance with this invention employs a plurality of such cells together with peripheral circuits for writing data into memory and for accessing the data stored in the memory. For simplicity these circuits are not shown. The starting point for the process of the invention to yield my novel self-aligned split gate structure is the same as in the the nonself-aligned split gate structure of the prior art and in particular of the '565 patent. Thus as shown in Figure 5a a monocrystalline silicon substrate 50 typically having a resistivity of 10-50 ohm-centimeters has formed thereon in a standard manner a layer of gate oxide 51. Gate oxide 51, typically 30 nm (300 angstroms) thick, then has formed on it a first layer of polycrystalline silicon (often called "poly 1") which is patterned as shown in Figure 5a to form a floating gate 52. The oxide 51 beneath the portions of polycrystalline silicon removed to form floating gate 52 is then removed by an etching process (typically a plasma etch) and a photoresist layer 53 is then formed over the top surface of the structure. As shown in Figure 5b, photoresist layer 53 is then patterned so that a particular segment 53-1 of photoresist is formed to partially overlie floating gate 52. Photoresist 53-1 has a right edge 53a which is formed to overlie the floating gate 52 somewhere near its middle and a left edge 53b which is formed to the left of left edge 52b of floating gate 52. The width of floating gate 52 is typically 1.5 to 2 µm and thus it is not difficult to ensure with sufficient certainty given typical tolerances in the manufacturing process that edge 53a is to the left of right edge 52a of floating gate 52 even for a reasonably expected worst case mask misalignment during the manufacturing process. It is also quite simple to insure that left edge 53b is sufficiently to the left of left edge 52b of floating gate 52 so that left edge 52b of floating gate 52 is never exposed, even in a worst case alignment mismatch of masks during manufacture. Thus the to-be-formed source 54a will always be laterally spaced from the left edge 52b of floating gate 52. Following the formation of patterned photoresist segment 53-1 the structure is subjected to an ion implantation at a selected well-known dosage (typically 4 x 10 12 per cm 2 ) to form n ++ drain region 54b and n ++ source region 54a in the top surface of the semiconductor material 50. The region 54b has its left edge 54b' defined by the right edge 52a of floating gate 52 and its right edge 54b" defined by the left edge 53c of patterned photoresist segment 53-2. The source region 54a has its right edge 54a" defined by the left edge 53b of patterned photoresist segment 53-1. Thus, the drain region 54b is self-aligned to the right edge 52a of floating gate 52. However, the right edge 54a" of source region 54a is self-aligned to the left edge 53b of photoresist 53-1. The uncertainty in the location of left edge 53b of patterned photoresist segment 53-1 relative to left edge 52b of floating gate 52 represents an uncertainty in the length of the control gate channel (corresponding to channel portion 36b in Figure 3) and not of the floating gate channel L eff (corresponding to channel portion 36a in the center cell of Figure 3). By placing a proper voltage on the to-be-formed control gate, (corresponding to control gate 35 in Figure 3), the channel length under the control gate becomes irrelevant and the conduction or nonconduction of the total channel is determined by the voltage placed on the floating gate 52 (corresponding to floating gate 33 in Figure 3). Because floating gate 52 is uniformly coupled to drain 54b in all transistors and further because the effective channel length L eff (corresponding to channel 36a in Figure 3) is substantially the same underneath all floating gates 52 in all transistors, the self-aligned structure yields a split gate programmable EPROM capable of being manufactured with much higher yield than the prior art EPROMs. The remaining steps in the process are standard well known steps in the silicon gate EPROM technology. Insulation (not shown) is formed over floating gate 52. A control gate (often called "poly 2") corresponding to control gate 35 in Figure 3 is formed, usually as part of a word line. The resulting structure appears as shown in Figure 3. Figure 3 shows floating gate 33 and floating gates 33L and 33R formed to the left and right of floating gate 33. All three floating gates have their right edges self-aligned to the left edges of the underlying drain regions. The drain region for a given cell doubles as the source region for the cell to the right. The finished structure made by the process as illustrated in Figures 5a and 5b is shown in Figure 3. In Figure 3 the floating gate 33 has been formed prior to the formation of the source and drain regions 31a and 31b. The floating gate 33 is formed on a thin layer of insulation overlying a portion of the to-be-formed channel region between the source and drain. The right edge of the floating gate 33 has been used to define one edge of the drain region 31b. Overlying floating gate 33 is insulation 34 (typically silicon oxide) and overlying oxide 34 is the control gate 35. A portion 35a of control gate 35 overlies a second portion of the channel region between the left end of the floating gate 33 and the source region 31a. As described herein, the channel region 36b beneath portion 35a of control gate 35 can have a length 36b which varies substantially without affecting the performance of the device. The structure shown in the central part of the cross-section in Figure 3 is but one cell of a plurality of such cells. In a typical virtual ground structure the drain 31b for the cell shown in cross-section in Figure 3 serves as the source for another cell located just to the right. Likewise the source 31a serves as the drain for a second cell located just to the left. The portions of the floating gates 33L and 33R associated with these adjacent cells are shown in Figure 3. Note that the floating gate 52 (Figures 5a and 5b) becomes capacitively coupled to drain region 54b by the lateral diffusion of left edge 54b ' beneath floating gate 52 during further processing of the structure. This lateral diffusion is typically around 0.3 µm. However contrary to the prior art, the floating gate 52 is formed before the formation of the drain region 54b, rather than after and is precisely self-aligned to one edge of the drain region 54b. Figure 6a illustrates the variation in threshold voltage versus the drawn channel length (L Pl ) of the floating gate ("poly 1"). In Figure 6a the ordinate is the program threshold and the abscissa is the length of the floating gate channel L Pl in microns. (Of importance, Figures 6a through 6d and 7a and 7b use drawn dimensions. However, the channel lengths 36a and 36b shown in Figure 3 are the effective dimensions after processing. Thus channel length 36a is denoted L eff to represent the effective length of this channel after processing, while before processing this channel length is a drawn dimension and as such is denoted by the symbol L Pl . Accordingly, each of the dimensions L Pi shown in Figures 6a through 6d and 7a and 7b must be corrected (i.e., reduced) by a given amount (approximately 0.5 µm), to reflect the effect of processing. Naturally the amount of the correction will vary with the processing.) The threshold voltage V tx obtained or programmed in a given time for a given drain voltage and gate voltage (corresponding in Figure 6a to a drain voltage of 8 volts and a gate voltage of 12 volts) drops rapidly, as the length of the channel L P1 under the floating gate 52 (Figure 5b) increases, to to a minimum V tx of about 2.5 volts for L P1 of somewhere between 3 to 4 µm and then increases slightly. This minimum V tx corresponds to the initial device threshold before programming. The threshold V tx represents the voltage which must be applied to the control gate (such as gate 35 in Figure 3) to turn on the transistor beneath the control gate as shown in Figure 3 when the cell containing that transistor has been programmed. Thus as the length of the channel 36a underneath the floating gate 33 increases (Figure 3) the threshold voltage necessary to turn on the transistor and create a channel from the source region 31b to the drain 31a decreases. As is shown in Figure 6a, both 1 millisecond and 10 millisecond programming times yield substantially the same shaped curve. Figure 6b illustrates the effect of the length of the channel 36a underneath floating gate 33 on the threshold voltage (ordinate) versus programming time (abscissa). The various curves reflect different lengths L Pl of the channel 36a (Figure 3) beneath floating gate 33 in µm. As these channel lengths increase, the threshold voltage for a given programming time drops. Thus for a programming time of 10 -2 seconds, the threshold voltage for a 1.5 µm channel length L Pl is approximately 7 volts whereas the threshold voltage for a 3.0 µm channel L Pl is about 4 volts. These curves were obtained for a voltage V DS from the drain to the source of 8 volts and a voltage on the control gate 35 of 12 volts. The curves of Figure 6b illustrate that the shorter the floating gate the stronger the field which is formed and therefore the more electrons which are placed on the floating gate thereby resulting in a larger threshold voltage V tx to turn on the transistor. Figure 6c is a plot of threshold voltage V tx (ordinate) versus the voltage on the drain 31b (Figure 3) with the length of channel 36a beneath floating gate 33 as the parameter on the various curves. For a given drain voltage V DS (for example 8 volts) the threshold voltage V tx goes up as the length L Pl of the channel 36a beneath floating gate 33 goes down. The curves of Figure 6c were taken with a control channel L P2 (corresponding to the drawn dimension of channel 36b in Figure 3) beneath the control gate 35 of 2.5 µm, a gate voltage on control gate 35 of 12 volts and a programming time of 10 milliseconds (10 -2 seconds). These curves illustrate that once a given drain voltage difference V DS is achieved between the drain and the source, increasing the drain voltage beyond a given amount has substantially little effect on the threshold voltage V tx of the transistor. In other words, ΔV tx /ΔV DS becomes substantially zero thereby showing that increasing the drain voltage coupled to the floating gate has little effect on the programming of the transistor. Thus after the program threshold voltage V tx is reached, increasing the drain to source voltage V DS does not achieve any significant improvement in performance. As L P1 increases, the threshold voltage V tx at which ΔV tx over ΔV DS becomes very small decreases. So increasing V DS does even less for structures with longer floating gates. In Figure 6c each consecutive point on a given line for a given L Pl represents an additional 10 milliseconds of programming time rather than just 10 milliseconds of programming time. Accordingly the curves for V tx versus V DS in Figure 6c would be even flatter than shown in Figure 6c if a constant programming time was applied to program the cell from different V DS start points. Figure 6d illustrates the very tight predictability of threshold voltage V tx versus V D (min) for the self-aligned structure.V D (min) is defined as the minimum VDS needed to start programming (i.e., to start efficient electron flow onto the floating gate). In Figure 6c V D (min) is the V DS at which the curve shows a break point sharply to the right. This break point or "knee" corresponds to the V D (min) plotted in Figure 6d. The relationship of Figure 6d to Figure 6c illustrates a basic point. In a 256K EPROM the time to program the cells in the EPROM theoretically equals 256K times the time to program each cell divided by 8 (ROMs are programmed one byte at a time). Therefore, if the programming time of each cell can be significantly reduced, the efficiency of programming a large number of EPROMs can be proportionally increased. To program to a given threshold voltage V tx in a given programming time, the key is to control the length of L Pl and in particular to make this length (which is related to the channel 36a in Figure 3) as small as practical without generating punch-through from the source to the drain. As shown by analysis of Figure 6d, the threshold voltage V tx is increased for a given programming time by decreasing V D (min). As shown in Figure 6c V D (min) decreases as L Pl decreases in length. Accordingly, decreasing L Pl is the key to programming to a given threshold voltage V tx in a given time. The self-aligned structure not only allows a small effective channel length L eff to be achieved beneath the floating gate but allows this channel length to be achieved in a controllable and reproducible manner throughout an EPROM array thereby to obtain repeatable and consistent results throughout the array. Figure 7a illustrates change of threshold voltage, ΔV tx for three different L Pl (i.e., three different drawn channel lengths beneath the floating gate) for the structure shown in Figure 2. In a nonself-aligned structure, the proper length of the channel under the floating gate is crucial to achieve maximum threshold voltage V tx . As shown in Figure 7a if the channel length 36a becomes too short (for example, 1.5 µm), then punch-through occurs between the source 31a and drain 31b during programming resulting in a failure to program the device. The proper alignment of a floating gate in the nonself-aligned structure to optimize the length of the channel 36a beneath the floating gate 33 and the overlap of the floating gate to drain is crucial. The very sharp peak in Figure 7a reflects the variation in V tx with channel length L P1 . Figure 7a shows that to optimize the device for the minimum channel length L Pl in terms of programming efficiency results in a lower initial threshold before programming and higher final threshold after programming so as to obtain a higher read current. This means a lower impedance in the circuit which in turn means that during read a capacitor in the sense amplifier in the peripheral circuitry of the memory discharges faster through a programmed transistor than otherwise would be the case resulting in shorter access time. Three effective channels beneath the floating gate (1.5 µm, 2.0 µm and 2.5 µm) are shown in Figure 7a. The parameter ΔV T (representing the change in threshold voltage as a function of different channel length) is illustrated by the curves. This change in voltage is particularly pronounced as one goes from 1.5 to 2 to 2.5 µm length for L Pl . The change in V tx as a function of channel length is similar to that shown in Figure 6a for the self-aligned structure of my invention. However, as one goes from a 2 µm L Pl to 1.5 µm L Pl and shorter, a new phenomenon appears reflecting possible punch through from the source to the drain and V tx thus is lower than would be expected. The nonself-aligned curve shows that a proper L Pl is critical to obtaining a predicted threshold voltage. However, with nonself-aligned floating gate technology L Pl can vary even across a given chip causing a variation in V tx from cell to cell within a given memory. Often this variation is unacceptable. As can be seen by the curves of Figure 7a, a given memory can have L Pl from cell to cell varying for example from 1.5 µm all the way to 2.5 µm or greater because of misalignment in the masking during the processing of the wafer. Accordingly, V tx is unpredictably variable across the wafer often resulting in unacceptable performance. Figure 7b shows the effect of overlap and V D on threshold voltage. For the nonself-aligned device the structure must be aligned so that the 3 sigma worst case of alignment gives a satisfactory channel length 36a beneath floating gate 33. Increasing the coupling between the floating gate and the drain does not improve the threshold voltage of the device for given programming conditions so overlapping the drain with the floating gate does not help. The more overlap of the floating gate to the drain means the more electrons required to charge the floating gate for a given channel length 36a beneath the floating gate. So instead of improving the efficiency of the device, increasing the overlap of the floating gate to the drain actually decreases this efficiency. A minimum overlap of the floating gate to the drain is needed to insure that accelerated electrons hit and lodge in the floating gate rather than in the control gate or the word line. Figure 7b shows that as the overlap of the nonself-aligned structure increases, the αV tx actually declines for a given V D . Again, this shows that the coupling between the drain and the floating gate is not helpful to achieving a desired V tx and indeed can even be harmful. The self-aligned circuit is highly scaleable and retains its self-aligned character as it is scaled. An important effect of the self-aligned structure is that by choosing the correct L Pl the programming time for a memory array can be substantially reduced. For example, a prior art 256K EPROM takes approximately 150 seconds or 2 ½ minutes to program. A 256K EPROM using the self-aligned structure can be programmed in approximately 30 seconds. This is a substantial improvement resulting in lower programming costs and lower test costs. An additional advantage flowing from the use of self-aligned split gate structures is that the uncertainty in the location of the floating gate due to mask alignment tolerances is substantially reduced compared to the uncertainty in the location of the floating gate in the prior art nonself-aligned structure and in the standard prior art EPROM (nonsplit gate but self-aligned). Table 1 illustrates this improvement with respect to the self-aligned split gate structure compared to the standard non-split gate self-aligned structure of the prior art. Standard EPROM (Non-split but self-aligned gate structure) Self-aligned split gate structure STEP 1 Poly 1 (Floating gate) Critical dimension not defined but non-critical dimensions are defined Poly 1 (Floating gate) Critical dimension defined STEP 2 Poly 2 (Control gate) Define critical dimensions of control gate - Accuracy degraded because of rough, non-planar topology associated with two layers of polycrystalline silicon STEP 3 Poly 1 critical dimension defined using Poly 2 as a mask Table I compares only the critical steps in the two processes used to define the floating gate and thus the crucial channel length L eff . L eff is the important channel length in the self-aligned split gate structure and in any EPROM structure. Note that in a standard non-split gate self-aligned structure L eff is the total channel length between the source and drain. As shown in Table I three steps are required to define the critical dimension of the floating gate in the standard non-split gate self-aligned structure. In the first step only the noncritical dimensions corresponding to the width (but not the length) of the channel beneath the floating gate are defined. The critical dimensions of the floating gate corresponding to the channel length beneath the floating gate are not defined. In step 2 the second layer polycrystalline silicon from which the control gate will be fabricated is deposited. The critical dimension of this second layer (known as "poly 2") is defined in step 2. This dimension corresponds to the channel length between the to-be-formed source and drain regions. However, the accuracy with which the critical dimension of the control gate is fabricated is degraded because of the rough nonplanar topology associated with the two layers of polycrystalline silicon deposited on the wafer. In the third step the first layer of polycrystalline silicon (poly 1) has its critical dimension (corresponding to channel length L Pl ) defined using the second layer of polycrystalline silicon as a mask. Again, the accuracy with which the critical dimension of the first layer of polycrystalline silicon is defined is degraded due to the uneven topology of the structure. In contrast, the self-aligned split gate structure defines the critical dimension of the poly l floating gate layer in step 1. As the above comparison shows, the channel length L Pl for the standard nonsplit gate self-aligned structure is equal to the drawn length of the channel plus or minus the uncertainty in the critical dimension associated with the poly 2 definition step plus or minus the uncertainty introduced in the critical dimension of the channel length associated with poly 1 using poly 2 as a mask. Thus the uncertainty in the effective channel length in the standard nonsplit gate self-aligned structure has two components introduced by two critical dimensions. On the other hand, using the self-aligned split gate structure, only one uncertainty in a critical dimension occurs and that occurs in the first step where the poly l critical dimension is defined and the topology is smooth. Accordingly, the self-aligned structure yields a double processing advantage over the process by which, the standard non-split gate self-aligned structure of the prior art is made by eliminating one critical dimension in defining L eff and by introducing a much smoother topology during the formation of the critical channel length L eff . Table 2 compares the critical steps required to define the poly 1 floating gate in the nonself-aligned split gate structure of the prior art compared to the single step required to define the floating gate in the self-aligned split gate structure. Nonself-aligned split gate structure Self-aligned split gate structure STEP 1 Source and Drain Implanted Poly 1 (Floating Gate) Define critical dimension STEP 2 Poly l (Floating Gate) Define critical dimension Step 1 in fabricating the prior art nonself-aligned split gate structure is to implant the source and drain regions in the device. Step 2 is then to deposit the poly 1 layer and then form the floating gate from this layer. The critical dimension L Pl is defined by this step. Unfortunately, uncertainty in the length of L Pl results from the uncertainty in the critical dimension of the poly l plus or minus the misalignment of the mask used to define the critical dimension of the floating gate relative to the underlying drain region. Typically the uncertainty in the critical dimension is ±0.3 µm while the uncertainty due to the mask misalignment is ±0.6 µm. When combined in a statistical sense (root mean square) the total uncertainty in L P1 can be ±0.6 or ±0.7 µm. To the contrary, using the self-aligned split gate structure the critical dimension of the poly 1 floating gate is defined with an uncertainty at most of about ±0.3 µm. Accordingly, a substantial improvement in manufacturing accuracy over the prior art nonself-aligned split gate structure is achieved. Figure 8 illustrates an EPROM array fabricated using the self-aligned split gate structure. For simplicity, an array of nine (9) transistors or cells is shown. The programming and reading of cell or transistor Q5 will be described. Note that the array comprises word line rows m-1, m and m+1 and bit line columns n-2, n-1, n and n+1. Column n-2 is the source of transistors Ql, Q4 and Q7 while column n-1 is the drain of transistors Ql, Q4, and Q7 and the source of transistors Q2, Q5 and Q8. Similarly, column n is the drain of transistors Q2, Q5 and Q8 and the source of transistors Q3, Q6 and Q9. Column n+1 is the drain of transistors Q3, Q6 and Q9. In operation, to read device m, n (i.e. cell Q5) all bit lines except n-1 are set at 2 volts. Bit line n-1 is set at ground. Word line m is set at 5 volts while all other word lines except m are set at ground. To program device m, n (i.e., cell Q5) all bit lines except n are set at ground while bit line n is set at 8 or 9 volts. All word lines except m are set at ground while word line m is set at 12 volts. During programming, device m, n+1 (i.e., cell Q6) is also in a programming condition but in the reverse configuration (i.e., the high voltage is applied away from the floating gate). In this configuration there is no programming of m, n+1. This asymmetry in the split gate EPROM is what enables one to utilize the virtual ground approach. An embodiment of this invention is illustrated in Figures 9a, 9b and 9c. Figure 9a illustrates in top view the layout of an embodiment of this invention which decreases the switching time necessary to read the state of a cell. Naturally, to increase the speed of a memory the time necessary to read the state of each cell in the memory should be decreased. The smaller the cell current or the larger the capacitance associated with the bit line connected to a given cell, the longer it takes to read the state of the cell. In the previously described split-gate structures, the drain region for one cell may serve as the source region for another cell. Thus when a cell is being read the source may serve as virtual ground. To read one cell in a memory and then read a second cell, the drain region of the second cell which has previously served as a virtual ground must be switched to a higher voltage. The time necessary to do this depends upon the capacitance of the drain region. To do this more rapidly, the drain capacitance (also called the bit line capacitance) must be reduced. The structure of Figure 9a does this by using a novel array architecture utilizing the self-aligned split gate EPROM. Instead of a virtual ground which can function as both a source and a drain region and which achieves the high cell density as described above in conjunction with Figures 3, 5a and 5b, the structure of Figure 9a uses a solid, dedicated source line 130-p as in a standard EPROM and dedicated bit lines (such as bit lines 213-m, 113-m and 113-(m+1). The source line is not switched from virtual ground to a high voltage but rather is always kept at a voltage near the level at which the cell is to be switched. By doing this the switching time can be decreased. The source line 130-p comprises a metal line formed on insulation over the array in a direction orthogonal to source regions 142-(s-1) and 142-s. Vias 131-(i-1) and 131-i connect metal source line 130-p to source regions 142-(s-1) and 142-s, respectively. Source regions 142-(s-1) and 142-s are typically formed by ion implantation. Formed orthogonal to source line 130-p are word lines 122-n and 122-(n-1). Word lines 122-n and 122-(n-1) function as control gates and are formed over but separated on insulation from floating gates 121-i and 121-(i-1). Floating gates (of which gates 121-i and 121-(i-1) are shown in top view in their entirety ) are formed of polycrystalline silicon overlying but insulated from the channel region between an underlying drain and source. In accordance with the description given above in conjunction with the structure of Figures 3, 5a and 5b, drain 111-i is formed by ion-implantation using edges 123-a and 124-a of floating gates 121-(i-1) and 121-i, respectively to define the top and bottom edges 111b and 111a, respectively (Figure 9b) of drain 111-i. Sides 111c and 111d of drain 111-i are bounded by oxide isolation. Thus each drain region such as region 111-i is disconnected from the other similar drain regions. As will be shown shortly, the width of the source regions 142-(s-1) and 142-s can be reduced substantially by forming each source region (such as source regions 142-s and 142-(s-1)) by ion implantation using one edge of each word line (such as word line 122-n or 122-(n-1) respectively) as a mask to define the edge of the corresponding source region during the n + ion implantation used to form the n + regions of the peripheral access and logic transistors on the EPROM. The main difference in the structure shown in Figure 9a using the self-aligned split gate concepts shown in Figures 3, 5a and 5b, and prior art EPROM arrays is the location of the bit lines 213-m, 113-m and 113-(m+1) and the word lines 122-(n-1) and 122-n in terms of layout. The advantage of the structure of Figure 9a is that the bit line 113 associated with a given cell 110 does not have to be switched all the way from ground to a voltage necessary to detect the state of this cell but is always held at a voltage close to the read voltage. The selection of the particular cell to be read is done by the word line 122. A second advantage is that a bit line 113-m, 213-m ... as much less capacitance than a typical prior art bit line. The reason for this is that while the bit line (such as bit line 113-m) is connected to a plurality of drain regions (such as drain 111-i of cell 110-i+1) arranged in a column, each drain such as drain 111-i functions as the drain in only two adjacent transistors (transistors 110-(i+1) and 110-i shown in Figure 9a) and each drain is not connected as part of a continuous diffused (or in this case, ion-implanted) region to the other drain regions. Thus the capacitance associated with each drain region 111 is reduced compared to the capacitance associated with a continuous drain diffusion of the prior art. As shown in Figure 9a and in cross-section in Figure 9b, the ion-implanted drain region 111-i serving memory cell 110-i+1 is contacted by a via 112-i formed in insulation 150 over the drain region 111-i. Metal bit line 113-m (also called a metal drain line) electrically contacts drain 111-i through via 112-i. Formed directly adjacent to drain 111-i and self-aligned with drain 111-i as described above in conjunction with Figures 3, 5a and 5b, are two floating gates 121-(i-1) and 121-i formed of a first layer of polycrystalline silicon ("poly 1"). Overlying floating gate 121-i is a control gate 122-n (also called a word line) formed of a second layer of polycrystalline silicon ("poly 2"). The second layer of polycrystalline silicon 122-n extends the length of 2N transistors in the array to form a word line (also called a control gate) and is orthogonal, in the embodiment shown, to both metal drain line 113-m and metal source contact line 130-p. N is an integer which in accordance with this invention is preferrably 2, 4 or 8. The cell 110-(i+1) includes part of a source diffusion denoted as 142-s in Figure 9a. The source diffusion 142-s for cell 110-(i+1) is also the source diffusion for cell 110-(i+2) (not shown in Figure 9a but shown schematically in Figure 9b and 9c) just as the drain diffusion 111-i is the drain diffusion for cell 110-i as well as for cell 110-(i+1). Source diffusion 142-s also serves as the source region for other cells in a given row. Thus each source diffusion except the first actually serves as the source region for 4N memory cells. The polycrystalline silicon word line 122-n is formed with substantial overlap over the source and drain to prevent misalignment from affecting the ability of a given cell to turn on when read. Edges 123a and 124a of the poly-1 floating gates 121-(i-1) and 121-i serve, as described above in conjunction with Figures 3, 5a and 5b, to define the edges 111b and 111a, respectively, of drain region 111-i as Illustrated in Figures 9a and 9b. Figure 9b also illustrates the symmetrical structure memory cells 11--i+1 and 110-i of this invention. These two cells share a common drain region 111-i as shown. Control gate 122-n (typically formed of polycrystalline silicon) has a left edge 144b which extends over source region 142-s. Source 142-s serves as a source not only for cell 110-(i+1) but also for cell 110-(i+2) (adjacent and below cell 110-(i+1) in Figure 9b but not shown in Figure 9a). Overlying source region 142-s is a metal contact layer 130-p (Figure 9a) which is connected to the source line 142-s by a contact 131-i. In fabricating the structure of Figures 9a, 9b and 9c it is clear that the source region 142-s, for example, can be fabricated using left edge 144b of polycrystalline word line 122-n as a guide to define right edge 146b of source region 142-s. When this is done, the width of control line 122-n and all similar control lines can be reduced by the tolerance otherwise placed on this width to insure that it is properly aligned over source region 142-s. Thus a saving in space can be achieved using this technique of at least half a µm in width of control line 122-n. When similar savings are made in conjunction with control line 122-(n-1) ty self-aligning left edge 145b of source 142-(s-1) with the right edge 143b of control line 122-(n-1), a substantially smaller array can be achieved. Advantageously, sources 142 are formed using the n + ion implant used to form the MOS transistors in the logic and access circuitry in the peripheral regions of the memory array. Figure 9c illustrates schematically the layout of an array utilizing the structure shown in Figures 9a and 9b. As shown in Figure 9c, metal source line 130-p is shown extending vertically down the center of the array. Contacts 131-i and 131-(i-1) are shown schematically to illustrate the vias through the underlying insulation through which metal line 130-p electrically contacts the laterally extending source regions 142-s and 142-(s-1). As described above, source regions 142-s and 142-(s-1) are preferably formed by ion implantation. Each lateral source region serves as the source for up to 2N transistors on each side of metal source line 130-p where N typically is an integer and can be 2, 4 or 8. Metal bit lines 113-m, 213-m ... to N13-m are shown to the left of metal source line 130-p and extending parallel to metal source line 130-p while metal bit lines 113-m+1, 213-(m+1), ... to N13-(m+1) are shown to the right of metal source line 130-p but extending parallel thereto. Each metal bit line such as bit line 113-m contacts underlying drain regions such as drain region 111-i through a via and contact region such as 112-i. As explained above, drain region 111-i and comparable drain regions 211-i through N11-i and 115-i through N15-i each serve as the drain regions for two self-aligned transistors such as transistors 110-i and 110-(i+1). Each source line 142 serves as the source for each of the 2N or 4N transistors connected thereto. However, each incremental section of the source line between a given pair of adjacent transistors (such as transistors 110-i and 210-i) has an incremental resistance R associated therewith. Thus, the when read current I r passes through each incremental resistance drop in voltage by the amount I r R with the result that the drain to source voltage difference at transistor N10-i is reduced by the amount NI r R. Accordingly, the voltage drop generated by the read current passing through the source regions to metal contact line 130-p places a practical limit on the maximum size of the number N. As shown schematically in Figure 9c source region 142-s serves as the source not only for transistors 110-i+1 through N10-(i+1) and 114-(i+1) through N14-(i+1), but also for transistors 110-(i+2), 210-(i+2) through N10-(i+2) and transistors 114-(i+2) through N14-(i+2). Thus the second through subsequent rows of source lines 142 each are connected to two lines of transistors. The metal bit lines 113-m through N13-m and 113-(m+1) through N13-(m+1) are each connected in rows to a plurality of pairs of transistor cells in the same manner as shown in conjunction with line 113-m, the contact region 112-i and transistor cells 110-i and 110-(i+1) (Figures 9a and 9b). Typically a row of the array will include 256, 512 or more metal contact regions such as contact region 112-i contacting the drains of 512, 1024 or more transistor cells such as cell 110-i and cell 110-(i+1). Among the advantages of the structure shown in Figures 9a, 9b and 9c is that the capacitance of a typical word line 122 to a typical bit line 113 is substantially reduced. The reason for this can be seen in Figure 9b. In the prior art each time a word line passes over a bit line, in the prior art a fairly high capacitance exists because the bit line has a high donor concentration (typically n + ) and the oxide between the word line and the bit line is thin. However, with this invention, the word line 122-n is separated from the overlying bit line 113 by fairly thick oxide 150a (typically around one µm thick) and thus the capacitance is very low. Moreover, the word line 122-n has very little overlap associated with edge 144a overlying the drain region 111-i. Accordingly, the bit line to word line capacitance is substantially reduced. Another advantage of this invention lies in the fact that the read current I r is quite high because of the use of a split gate. With a split gate the floating gate 121-i can be made shorter but wider because high coupling to the gate is not required. Since the current is proportional to the width of the floating gate over the length of the floating gate, the current is increased by having a short floating gate. Finally, the bit line capacitance itself is smaller than in the prior art because the bit line 113-m contacts 256 discrete drains rather than a continuous drain line. The reduction in size of the drain regions by using unconnected drain regions such as drain 111-i substantially reduces the capacitance associated with the bit line. It should be appreciated that the present invention is not restricted to the details of the foregoing embodiment.

Claims: An EPROM array comprising: a substrate composed of semiconductor material; a plurality of memory cells, each memory cell including a split gate transistor (110-i; 110-(i+1)...) ; a metal source contact line (130-p) running in a first direction across the array; a plurality of source diffusion lines (142-(s-1); 142-s...) being integrally formed in the substrate and running orthogonal to the metal source contact line; each source diffusion line having 2N portions serving as source regions of adjacent split gate transistors (110-(i+1); 110-(i+2)), where N is an integer; a contact (131-(i-1); 131-i...) between the metal source contact line and each of the underlying source diffusion lines for coupling a potential on the metal source contact line to each of the source regions; a plurality of metal drain lines (113-m; 113-(m+1)...) running across the array substantially parallel to the metal source contact line, each metal drain line contacting a plurality of separate drain regions (111-i) formed in said substrate, each drain region being located between two of said source regions and serving as a common drain region of a pair of adjacent split gate transistors (110-i; 110-(i+1)); and a plurality of control lines (122-(n-1); 122-n...) formed over the array running orthogonal to the metal source contact line and the plurality of metal drain lines; the control lines having 2N portions serving as control gates of said split gate transistors; wherein each split gate transistor further comprises: a separate floating gate (121-(i-1); 121-i...) formed over but insulated from a channel region extending in said substrate between said source and drain regions and having a length equal to the sum of a first and a second distance, said floating gate having one edge (123a; 124a) substantially aligned with the edge (111b; 111a) of the drain region (111-i) and spanning substantially the first distance so as to be separated from the edge (145b; 146b) of the source region (142-(s-1); 142-s) by the second distance, and the control gate being formed over, but insulated from, both the floating gate and the portion of the channel region not covered by the floating gate. An EPROM array as claimed in claim 1, wherein the edge (143b) of the control gate furthest from the floating gate (121-(i-1)) is aligned with the edge (145b) of the source region (142-(s-1)) adjacent the channel region. An EPROM array as claimed in claim 1 or 2, wherein the integer N is 2, 4 or 8. A memory device comprising an EPROM array as claimed in any preceding claim replicated M times to form an EPROM device with M times the memory cells of the EPROM array according to any one of claims 1 to 3. A method of fabricating an EPROM array comprising forming on a substrate (50) composed of semiconductor material: a plurality of memory cells, each memory cell including a split gate transistor (110-i; 110-(i+1)...); a metal source contact line (130-p) running in a first direction across the array; a plurality of source diffusion lines (142-(s-1); 142-s...) being integrally formed in the substrate and running orthogonal to the metal source contact line; each source diffusion line having 2N portions serving as source regions of adjacent split gate transistors (110-(i+1); 110-(i+2)), where N is an integer; a contact (131-(i-1); 131-i...) between the metal source contact line and each of the underlying source diffusion lines for coupling a potential on the metal source contact line to each of the source regions; a plurality of metal drain lines (113-m; 113-(m+1)...) running across the array substantially parallel to the metal source contact line, each metal drain line contacting a plurality of separate drain regions (111-i) formed in said substrate, each drain region being located between two of said source regions and serving as a common drain region of a pair of adjacent split gate transistors (110-i; 110(i+1)); and a plurality of control lines (122-(n-1); 122-n...) formed over the array running orthogonal to the metal source contact line and the plurality of metal drain lines; the control lines having 2N portions serving as control gates of said split gate transistor; wherein further each split gate transistor is formed with a separate floating gate (121-(i-1); 121-i...) formed over, but insulated from, a channel region extending in the substrate between the source and drain regions and having a length equal to the sum of a first and a second distance, said floating gate having one edge (123a; 124a) self-aligned with the edge (111b; 111a) of the drain region (111-i) and spanning substantially the first distance so as to be separated from the edge (145b; 146b) of the source region (142-(s-1); 142-s) by the second distance, and the control gate being formed over but insulated from both the floating gate and the portion of the channel region not covered by the floating gate. A method according to claim 5, wherein the edge (143B) of the control gate furthest from the floating gate (121-(i-1)) is self-aligned with the edge (145B) of the source region adjacent the channel region. A method according to claim 5 or 6, wherein the integer N is 2, 4 or 8.

Inventors: EITAN BOAZ, EITAN, BOAZ
Applicants: WAFERSCALE INTEGRATION INC, WAFERSCALE INTEGRATION INC.
Application year: 1986
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29