METHOD FOR FABRICATING ARTICLES HAVING HETEROEPITAXIAL STRUCTURES

Abstract: A rapid thermal anneal (RTA) can substantially improve the quality of heteroepitaxial structures such as dielectrics on semiconductors, semiconductors on metal on semiconductor (e.g., Si/CoSi2/Si), semiconductor on semiconductor (e.g., GaAs/Si, and SixGe1-x/Si), or semiconductor on insulator (e.g., Si/Al2O3). The RTA involves heating a heterostructure, comprising a single crystal first material substrate with a layer of second material thereon, to an absolute temperature Ta2 for a time ta2, where typically 0.75 Tm2 < Ta2 < Tm2 and 1 < ta2 < 60 seconds, Tm2 being the absolute melting temperature of the second material. The method can produce substantial improvement in such indicators of crystalline perfections as RBS ratio chi min or carrier mobility mu .

Description: METHOD FOR FABRICATING ARTICLES HAVING HETEROEPITAXIAL STRUCTURES Field of the Invention This invention pertains to formation or improvement of single crystal heteroepitaxial structures by a method comprising solid-state rapid thermal annealing, and to articles, e.g., semiconductor devices, produced thereby. Background of the Invention From the beginning of semiconductor device technology, scientists have discussed a host of heteroepitaxial structures, i.e., combinations of layers of different materials in a single composite crystal. The fascination in this kind of structure is traceable to the wide selection of electrical properties thus potentially available to the device designers. The early visions of a wide variety of such structures have not yet been realized, however, and it is now recognized that heteroepita ial structures with perfection suitable for state of the art devices are in general extremely difficult to produce. Some types of heteroepita ial semiconductor structures, e.g., combinations of III-V compound se iconductors of varying compositions, are well known to the art and are widely used in optical and electronic devices. Some heterostructures comprising a semiconductor substrate and a metal layer deposited thereon are also known to the art. For instance, U.S. Patent 4,492,971 discloses silicon/metal suicide heterostructures. The patent teaches that such structures can, for instance, be formed by co-deposition of metal and silicon onto the single crystal silicon substrate, with the substrate maintained at a temperature that favors formation of the stoichiometric metal silicide. U.S. Patent 4,477,308 discloses a method for forming an epitaxial layer of multiconstituent material on a substrate, the method 5. comprising deposition of a very thin template layer onto the substrate material, followed by deposition of further material at a higher substrate temperature. And co-assigned U.S. patent application Serial No. 820,581 filed January 17, 1986 in the name of J. C. Hensel et 10 al . teaches, inter alia, that a template method can also be used to form highly perfect epitaxial Si on metal silicide. The above referred to references teach formation of heteroepitaxial structures by adjusting the 15 conditions such that the deposition of overlayer material directly results in growth of the epitaxial and highly perfect overlayer. Although this approach is successful in a number of material combinations, e.g., silicon/metal silicide, there exist many material 20 combinations for which this approach either does not work or is considered not likely to work. The prior art also teaches that some heteroepitaxial structures can be formed by methods comprising transient melting of material. For instance, 25 H. Ishiwara et al , Material Research Society Symposium, Proceedings, Volume 1, pp. 525-531 (1981) , disclose that a-, heteroepitaxial Si/CoSi 2 /Si structure can be formed by depositing a layer of Co onto a Si substrate, heating the substrate to form the cobalt silicide, depositing a 30. layer of amorphous Si atop the silicide, and melting the amorphous Si by means of a high powered laser. Formation of a heteroepitaxial structure by means of transient melting of the top layer is also disclosed in co-assigned U.S. Patent 4,555,301 issued on November 26, 35 1985 to J. M. Gibson et al . Various means for heating wafer-like samples during processing are known to the art. For instance, D. J. Lischner et al , Materials Research Society Symposium, Proceedings, Volume 4, pp. 759-764 (1982) , disclose annealing of ion- implanted Si by means of a battery of tungsten halogen lamps, J. C. C. Fan et al , (ibid, pp. 751-758) , disclose transient heating of wafer-shaped materials (e.g.. Si) by means of a graphite strip heater, and C. Hill, Materials Research Society Symposium, Proceedings, Volume 13 (1983) , pp. 381-392, discusses beam processing in semiconductor technology. As demonstrated by the above discussed references, the prior art knows techniques that can be used to produce some heteroepitaxial structures. However, frequently the crystalline quality of the epitaxial overlayer (or other relevant material parameter of the heterostructure is relatively low, making the material unsuitable, or of marginal utility, for device applications. Examples of heterostructures of technological promise that suffer from low crystalline quality of the epitaxial overlayer are Si/Al 2 o 3 (Si-on-sapphire) and GaAs/Si. An example of a heterostructure in which another material parameter is frequently of a relatively low value is Si Ge-, /Si (0 < x >1) , with the parameter being the room temperature carrier mobility. It has recently been discovered that the crystalline quality of the overlayer of a particular heterostructure (CaF z /si) can be substantially improved by a rapid thermal anneal (RTA) . See, for instance, Pfeiffer et al . , Applied Physics Letters, volume 46, No. 10, pages 947-949, 15 May 1985. In view of the fact that many material combinations, such as Si-on-sapphire, GaAs/Si, and Si χ Ge 1 _ χ /Si, are of potential interest in technology, especially in semiconductor device technology, a broadly applicable processing technique that can result in the transformation of lower quality overlayer material into higher quality material that is epitaxial with its substrate would be of much interest. This application discloses such a technique. Glossary A crystalline layer atop a single crystal substrate herein is considered to be "epitaxial" with the substrate if the overlayer is a single crystal and the crystalline orientation of the overlayer is determined by the crystalline orientation of the substrate. A layer of crystalline material herein is considered to be "polycrystalline" if X-J- (i.e., the room temperature ratio of RBS in an appropriate low- index lattice direction (typically chosen normal to the layer) to that in a random lattice direction) is greater than at least about 20%, for a 1-2 MeV He probe beam of about 1 mm^ cross section. In amorphous material χ . is of course 100%. A crystalline layer is considered herein to be "single crystalline" if its ^ in , determined with a similar probe beam, is less than about 20%, preferably less than 10 or even 5%, along two crystalline directions. ι The x m ^ n of crystals known to be essentially perfect is found to be about 3%, the exact value depending on the material. For X_-i n between about 3 and about 20%, >^ n is a generally accepted measure of crystal perfection. Ho ever, in epitaxial films that - are found to have χ min *> 3% and that are thus considered to be essentially J perfect according to the x.mm. criterion, possible differences of crystalline perfection may be established by other means. One such other measure of crystalline perfection is the observed room temperature carrier mobility (μ) in the material. This measure can be used, for instance, for heteroepitaxial semiconductors, e.g.. Si v Ge- ι Ϋ /Si. Herein the relevant pre-RTA ( iϊapid Thermal Anneal) measure of second mater ial crystal per fection is identi fied by the subscr ipt (e .g . , x i n i ' ^i) ' and the post-RTA measure by the subscr ipt f_ (e .g . , χ min ξ , μ f ) . The " normal i zed change" in the appropr iate measure of second mater ial crystal perfection herein is designate d Δ x min , Δ μ , etc . , w h ere Δ X min - < min , i " * min ,f> / χ min , i , and Δ *» = 0> £ - J / μ f . An epitaxial layer of material atop a single crystal substrate is herein considered to form a "heteroepitaxial" structure if the substrate (the "first material") substantially differs from the overlayer (the M secσnd material") in chemical composition. In particular, at least one chemical element that is a major constituent of the first (second) material is not a major constituent of the second (first) material. For purposes of this definition a constituent is a "major" constituent if it makes up at least 5% by weight of the mate ial. Brief Description of the Drawings FIGS. 1 and 2 schematically depict exemplary heterostructures? FIG. 3 schematically depicts apparatus for rapid thermal annealing; The Invention We have discovered that the crystalline perfection (as expressed by X min , μ, or in other appropriate ways) of a layer of material (the "second" material) deposited onto an appropriate single crystal substrate (the "first" material) can, under appropriate conditions, be substantially improved by means of a apid ^ thermal a_nneal (RTA) . Typically, the inventive method produces a normalized change in the appropriate measure of crystal quality of at least about 0.1. Thus, Δ X--i n >.0.1, or Λ P j> 0.1. For instance, the X min i of as deposited second material frequently is greater than 10%, even 20 or 50%, and the inventive method can produce therefrom high quality epitaxial material having X- IU,-.Lr--. ,_• of less than 10%, even 5%. The method is currently believed to have wide applicability and may, for instance, permit (when applied sequentially) the fabrication of heteroepitaxial structures comprising any desired number of layers of appropriately chosen single crystal material. In such a case, the last layer to be transformed into single crystal material forms the substrate for the next layer to be formed, and the term "substrate" herein is to be understood in this broader sense. Exemplary material combinations to which the invention method can advantageously be applied are CaF 2 /metal silicide/Si, Si χ Ge,-_ x »/Si, with 0 < x 1, BaF 2 /Ge, GaAs/Si, and Si/ l^ j . Typically, the first and second material lattice constants must differ by less than 10% for epitaxy to be possible. The inventive method typically comprises preparation of a major surface of a single crystal substrate, typically a semiconductor wafer that is cut substantially parallel to a low-index (e.g., within about + 5° of a (100), (111), or (1T02)) lattice plane, by known methods, such as to provide a substantially atomically clean and undamaged substrate surface. See, for instance, A. Ishizaka et al , Proceedings, Second International Symposium on Molecular Beam Epitaxy, Tokyo, 1982, pp. 183-186. Onto the thus prepared first material surface all the material needed to yield the desired layer thickness of second material is deposited. In case the second material is a multiconstituent material, deposition is often advantageously co- deposition. During deposition the substrate temperature can be raised to any desired level , so long as the materials neither melt nor chemically-reac . However, it is currently considered to be a significant feature of the instant invention that the substrate can be maintained at a relatively low temperature during deposition, typically below 0.5 T m2 , where T m2 is the absolute melting temperature of the second material, and even below 300 or 200°C. The thus deposited second material, which has the same overall chemical composition as the desired single crystal epitaxial second material but which is typically polycrystalliπe or even amorphous, is then subjected to a RTA by any appropriate means. The RTA involves heating at least the deposited second material to an annealing temperature T a2 , and maintaining the deposited second material at the annealing temperature for an annealing time ta Λ,. By the "annealing temperature" we mean herein a temperature that permits atomic rearrangement of the deposited second material, typically a temperature greater than about 0.75 m2 but less than T m2 , preferably between 0.8 and 0.95 T -. By an "annealing time" we mean herein a time sufficient to result in transformation of the deposited second material into single crystal second material at the annealing temperature. For instance, for Si-on-sapphire (Al 2 o 3 ) , t- a2 typically is in the range 1-60, or frequently 5-40 seconds, and these ranges we consider to be broadly applicable. A further condition on g2 and t a2 is the requirement that the chemical composition of the resulting second material layer be substantially identical to that of the as deposited second material. This obviously requires that substantially no mass transfer across, or chemical reaction at, substrate/deposit interface occurs, and sets upper limits on the allowable combinations of T a« £.. and t α 3 _. A further requirement is that T a 2 be less than the melting temperature of the first material , as well as of any other material in a mul ti-material heterostructure . FIG. 1 schematically depicts the simplest possible epitaxial heterostructure, namely, a first material single crystal substrate 10 and a second material single crystal overlayer 11 that is epitaxial with 10. For instance, 10 could be a Si wafer, and 11 a semiconductor such as Ge or GaAs or a metal such as CaF 2r or a metal such as CoSi 2 . FIG. 2 schematically shows a slightly more complicated epitaxial heterostructure comprising single crystal material 10 (e.g.. Si), epitaxial single crystal material 11 (e.g., CoSi 2 ) thereon, and epitaxial single crystal material 20 (e.g». Si) atop 11. It will be recalled that herein 10 is considered to be the substrate for purposes of formation of 11, whereas 11 is considered to be the substrate for purposes of formation of 20. The scheme is to be extended in the case of more complicated epitaxial heterostructures. In electronic devices according to the invention means for making electrical contact to appropriate layers of the heterostructure would of course be provided. Such means are well known and are not shown. The inventive method comprises a RTA, carried out by any appropriate means. Such means are well known in the art. See, for instance, D. J: Lischner et al (op. cit.) , and J. C. C. Fan et al (op. cit.) . Exemplary apparatus for carrying out a RTA accord ing to the invention is schematically shown in FIG. 3 , wherein sample 30 (e.g . , a Si wafer with a layer of composition Si ^ g Ge thereon) is supported by transparent ( e .g . , fused sil ica) sample holder 31 hav ing sample supporting posts 32. The sample holder is attached to cover plate 33 which can form an airtight seal with transparent chamber 35 by means of 0-ring 34. Means 37 are prov ided for attaching the apparatus to a vacuum system . Not shown are other well known means that may advantageously be present in a RTA apparatus , e .g . , resistive heater means , temperature measur ing means (e.g., thermocouples) , means for admitting inert gas to the chamber, and means for depositing second material onto the substrate (e.g., e-beam, Knudsen, or other evaporators, or sputtering means) . Radiant energy sources 36 are shown placed outside of 35, and such placement is currently preferred for high intensity lamps, e.g., tungsten halogen lamps. However, other heat sources (e.g., a graphite wire heater) could be advantageously placed inside the chamber. In order to achieve substantially uniform heating of 30 during RTA it is desirable that the radiant flux from the sources 36 be substantially homogeneous. This can be achieved, for instance, by interposing a diffusing surface between the lamps and the sample, e.g., by sandblasting or otherwise roughening the outside of 35, or by providing a large area heat source. Particularly advantageous apparatus for practicing the invention comprises means for final in situ preparation of the initial substrate (e.g., by means of oxidation, followed by heating in UHV to remove the oxide, or by sputtering) , means for in situ forming the second material layer atop the initial substrate, and, if desired, means for forming in situ one or more further layers of material. With such apparatus it is in principle possible to form heterostructures comprising any desired number of layers without exposing the incomplete heterostructure to a contaminating atmosphere, and this is currently considered by us to be a preferred approach. In particular, we believe that it is frequently advantageous to carry out the deposition(s) and the RTA(s) under conditions such that the 0_ partial pressure is at most about 10 Pa, preferably less than 10 Pa. We currently believe that the inventive method can at least in some cases, produce single crystal material even from amorphous deposited material, and consequently we believe that there is frequently substantially no lower limit on the deposition temperature. This is considered to be a significant aspect of the instant invention. For instance, deposition onto a cold substrate can avoid the island formation frequently observed when it is attempted to form very thin layers of second material on a hot substrate. As will be appreciated, by those skilled in the art, the appropriate annealing time depends not only on the second material and possibly also on the first material, but is also a strong function of the annealing temperature. No universally valid limits can thus be determined, but we believe that typically ta___. will be in the range 1-60 seconds, with t a2 decreasing as a2 increases. Typically, there exists an upper limit in T a_ __. above which the crystalline qual ity of the annealed mater ial decreases . It will undoubtedly be apprec iated by those skilled in the art that the exact value of the upper l imit depends on the second mater ial , t 2 , and possibly also on the first material . Typically, however , a 2 < 0.95 T m2 , and frequently T a 2 < 0.9 T m2 . In the case of sil icon-on-sapphire , we have found that a 2 is advantageously chosen in the range 1250°C to about 1410°C, and for GaAs/Si in the range 750 to about 900°C For some mater ial combinations , typically when the d ifferential thermal expansion of substrate and overlayer exceeds about 1% between room temperature and a 2 _ cracking or buckl ing of the overlayer may occur during cool-down after the RTA. This can often be prevented by a thermal soak after RTA, i .e . , by maintaining the sample at a soak temperature T , (0 .5 T m2 < T s 2 < 0.75 T m2 ) for a time t s 2 (1 < t g 2 < 60 seconds) . Example I_ The 0.5 πm thick Si layer of a commercially available (Union Carbide, San Diego, California) Si/ l 2 o 3 heterostructure, grown at a substrate temperature of about 500°C, has a X^^ of about 20%. The sample is placed into a furnace, the furnace is sealed, flushed with Ar for about 10 minutes, and thereafter the furnace power is ramped up at about 15% per second until the annealing temperature of about 1200°C is reached. This temperature is held for about 20 seconds, and then the furnace power is decreased at 15% per second. The sample is maintained in the furnace until the sample temperature has dropped to about 100°C. This procedure results in a heteroepita ial structure, with the Si having a )^ in of about 5%. Example II On a n + Si ( 100 ) substrate were sequential l y deposited by MBE ( us ing mul tiple guns) a) 470 nm Si ( p + , 1 « 10 18 cm" 3 ) ; b) 25 nm of undoped Si ; c) 50 nm of undoped Ge 2 si « alloy ; d) 25 nm of undoped Si ; and e) 75 nm of Si ( ρ + , 1 10 18 cm" 3 ) . All layers were deposited at a substrate temperature of 500°C, in a vacuum of at least about 10~ 7 Pa. Further details of the procedure can be found in U.S. Patent No. 4,529,455. The thus produced heterostructure had essentially ideal χ min ( 3%) throughout, the hole mobility in the alloy at 60°K was about 140 cm 2 /volt sec. After a RTA (T _ = 1080°C, t _ =_. n seconds) substantially as described in Example 1, the hole mobility was 210 cm /volt sec, with . remaining about 3%. Example III A Si/ l 2 o 3 heterostructure (orientation (100) and (1X02) , respectively) , made substantially as described in Example I, is subjected to a RTA(T a2 = 1410°C, t &2 =_. 15 seconds) . The resulting combination is heteroepitaxial, with the Si having a χ min of less than 5%. Example VI A single crystal Si substrate (oriented about 3° off (100) towards < 011 >)- was prepared by a known method, and a 2μm GaAs layer grown thereon by MBE, substantially as described by R. Fischer et al , Journal of Applied Physics, Vol. 58, p. 374 (1985). In particular, the final step in the substrate preparation was formation of a thin oxide layer by maintaining the substrate for 5 minutes in a 80°C solution of composition 3HC1.3H 2 0 2 < 5H 2 0. Before starting the MBE growth, the substrate was heated to about 900°C to thermally desorb the oxide layer, and 10 minutes after oxide removal was complete the arsenic cell shutter was opened and the substrate cooled to about 425°C. A thin GaAs layer (about 25nm) was- then deposited at a growth rate of about .2 μm/hour. The substrate temperature and deposition rate were then slowly increased to about 595°C and 1 μm/hour , respectively, to start the normal growth of the GaAs. RTA was performed in a commercially available heat pulse system in a forming gas atmosphere (the GaAs/Si sample placed upside down onto a GaAs substrate. ( a2 about 900°C, t &2 about 10 seconds) the rise and cooling times of the annealer were about 10 and 6 seconds, respectively. The annealed combination had a substantially lower percentage of displaced atoms near the GaAs/Si interface (decreased to 7% from 20%, as estimated by RBS) , decreased width of the (400) peak in the rocking curve (from 400 to 185 arc seconds) , greatly increased photoluminescent intensity, and greatly decreased etch pit density, as compared to a similarly grown GaAs/Si combination that was not subjected to RTA. In the annealed GaAs, avalanche photodiodes were made, and RTA was found to improve the yield significantly. It will be appreciated by those skilled in the art that the above cited conditions are exemplary only. For. instance, the substrate can be oriented differently, including exact (100) orientation, the template layer deposition temperature can be different (e.g., about 150°C) , the GaAs growth temperature is advantageously chosen in the approximate range 580-610°C, and T _ i s advantageously in the approximate range 750-900°C. The improvement in the crystalline quality of the GaAs that is attained by RTA according to the invention typically depends on the quality of the starting material.

Claims: Claims 1. Method for fabricating an article comprising, a composite structure of a single crystal first material substrate and a layer of a single crystal 5 second material overlying the substrate, with the second material layer being epitaxial with the substrate, CHARACTERIZED BY a) providing a composite structure of a first material substrate and a layer of second material on the 0 substrate, the second material having a RBS ratio χ„ mι in n,ιJ and a predetermined chemical composition; and b) heating at least the second material to an annealing temperature T a2 for a time t a2 , with T a2 and t 'a2 cnosen such that, after completion of the heating, 5 the second material still has essentially the predetermined chemical composition and (i) the second material has χ min f such that Δ min >. 0.1, where Δ X min = min,i" x min,f > / min,i OE (ii) if prior to the heating step a room 0 ' temperature carrier mobility μ. is associated with the composite structure, then the heating is conducted such that a room temperature carrier mobility μ f is associated with the composite structure, such that Δ n > 0.1, where μ = (μ f -μ i )/μ f , or 5 (iii) both. 2. Method of claim 1, wherein σ*75 T m2 τ a2 < τ m2' wtlere τ m2 * s tiιe secon °3 material metlaing temperature, with ^ and T a2 being absolute temperatures and 1 t a2 < 60 seconds. ff 3. Method according to claim 1, CHARACTERIZED IN THAT at least step b) is carried out in an atmosphere having an 0 2 partial pressure less than about 1 10 "2 Pa. 5 4. Method according to claim 1, CHARACTERIZED IN THAT X min,! > L0% and min,f i 5% - 5. Method according to claim 1, CHARACTERIZED IN THAT 5 the single crystal first material substrate is formed by a process comprising ■ f i) providing a third material single crystal substrate, the third material composition differing from at least the first material composition; and 10 ii) forming a layer of first material on the third material substrate, the first material layer consisting substantially of first material with min < 10% ' 6. Method according to claim 5, 15 CHARACTERIZED IN THAT step ii) comprises iii) depositing first material on the third material substrate; and iv) heating the deposited first material to 20 an annealing temperature τ al for a time t al , with T al and a ^ chosen such that the first material with m £ n < 10% is produced. 7. method according to claim 1, CHARACTERIZED IN THAT 25 the first material is Al 2 o 3 and the second material is Si. 8. Method according to claim 7, CHARACTERIZED IN THAT T a2 is in the range from about 1250 .OC to about 30 1410°C. 9. Method according to claim 1, CHARACTERIZED IN THAT the first material is Si, and the second material is GaAs. 35 10. Method according to claim 9, CHARACTERIZED IN THAT T a2 is in the range from about 750°C to about 900°C. 11. Method according to claim 1, CHARACTERIZED IN THAT the second material has, prior to step b) ,(ii) , a RBS ratio min i f and after step b) ,(ii) a RBS ratio 12. Method according to claim 11, CHARACTERIZED IN THAT the first material consists substantially of Si, and wherein the second material consists substantially of material of composition Si χ Ge- , 0 < x - 13. Method according to claim 1, CHARACTERIZED IN THAT after completion of step b) , the temperature of the composite structure is reduced to a soak temperature T g2 , where 0.5 T m2 < T g2 < 0.75 T m2 , and the composite structure maintained at the soak temperature of a time g2r where 1 < t g2 < 60 seconds.

Inventors: CHAND NARESH, PFEIFFER LOREN NEIL, PHILLIPS JULIA MAE, CHAND, NARESH, PFEIFFER, LOREN, NEIL, PHILLIPS, JULIA, MAE
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1986
Main classification: C30B1
IPC codes: C30B1, C30B29, H01L21