SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Abstract: A semiconductor integrated circuit device inhibits the output of programmed data of its built-in memory (ROM) to an external terminal (TO) but outputs the result of compari­ son of the programmed data with an input signal supplied from an external terminal (I, I/O) to the external terminal (TO).

Description: BACKGROUND OF THE INVENTION This invention relates generally to a semiconductor integrated circuit device, and more particularly to technique which is effective when applied to a semiconductor integrated circuit device having a microcomputer function, for example. In a 1-chip microcomputer, for instance, predetermined data processing is made in accordance with a program written into its built-in read-only memory (ROM). If a circuit arrangement is made in such a manner as to output the programmed data of this built-in ROM to an external terminal, there occurs the possibility that the content of the program will be known to a third party, and this is undesirable from the aspect of protection of software. However, the program content must be read out to the external terminal in order to test the memory. As one prior art reference relating to the 1-chip microcomputer, mention can be made of "HITACHI MICROCOMPUTER DATA BOOK, 8-BIT SINGLE CHIP" published by Hitachi, Ltd., September, 1983. GB-A-2 092 338 describes a memory in chip form in which external access to a program stored therein is physically disconnectable within the chip by a signal generated subsequent to the entry and checking of the program. SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a semiconductor integrated circuit device which satisfies both the functions of the security of the programmed data of its built-in memory and the test of the memory. The invention is defined by claim 1. The objects and features of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a 1-chip microcomputer to which the present invention is applied; Fig. 2 is a circuit diagram of a comparison circuit of the microcomputer shown in Fig. 1; and Fig. 3 is a timing chart useful for explaining the test operation of the microcomputer shown in Fig. 1. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 is a block diagram of a 1-chip microcomputer in accordance with the present invention. In the drawing, the portion encompassed by dash lines is one LSI which constitutes as a whole a 1-chip microcomputer. It is formed on one semiconductor substrate such as a silicon substrate by known semiconductor integrated circuit production technique. Symbol CPU represents a microprocessor, and its principal constituent block is shown in the drawing as a representative. Symbol A represents an accumulator, X is an index register, CC is a condition code register, SP is a stack pointer, PCH and PCL are program counters, CPU-CONT is a CPU controller and ALU is an arithmetic logic unit. The construction of the microprocessor CPU described above is well known in the art; hence, its detailed description will be omitted. Symbol I/O represents an input/output port, which includes therein a data transfer bidirectional register. Symbol I represents an input-only port. Symbol OSC represents an ocillator. Though not particularly limitative, the oscillator uses a quartz oscillator Xtal mounted to LSI and generates a high precision reference frequency signal. A clock pulse necessary in the microprocessor CPU is prepared from this reference frequency signal. The reference frequency signal is used as a reference time pulse for a timer, too. This timer consists of a counter COUNT, a prescaler PR and a controller CONT. These circuits OSC, PR, COUNT and COUNT consist of heretofore known circuits, respectively. Symbol RAM represents a random access memory circuit or block which is used primarily as a memory circuit of temporary data. Though not particularly limitative, a known static random access memory is used as this random access memory. Symbol ROM represents a read-only memory circuit or block, into which a program for various data processing is written. Though not particularly limitative, the read-only memory (ROM) of this embodiment consists of a mask ROM. This mask ROM comprises a plurality of word lines, a plurality of data lines crossing the word lines, respectively, and memory cells disposed at the points of intersection between the word lines and the data lines. The circuit block ROM further includes row and column address decoders for selecting the word lines and the data lines in accordance with row and column address signals supplied from the microprocessor CPU through the address bus, respectively. A precharge circuit and a sense amplifier circuit are connected to the data lines. Namely, the mask ROM of this embodiment comprises a known circuit. The output of the sense amplifier circuit is used as the output of the read-only memory ROM, which consists of an 8-bit unit and is outputted to the data bus through an output circuit (not shown in Fig. 1). Each of the circuit blocks described above is connected to each other by the buses BUS with the microprocessor being the center. The buses BUS includes the data bus, the address bus and the control bus. In the microcomputer of this embodiment, the output of the programmed data of the read-only memory ROM to the external terminal or to the outside of LSI is inhibited for the security purpose. In other words, the microcomputer is not equipped with the operational function of delivering the content of the read-only memory ROM to the external terminal. The following comparison circuit CMP is disposed in order to easily test such a read-only memory ROM. This comparison circuit CMP compares the content of the read-only memory ROM, which is read out onto the data bus, with an input signal supplied from the external terminal, judges coincidence and discordance between them and outputs the result of comparison to the external terminal TO. In this embodiment, the result of judgement to be delivered to the external terminal TO is produced once per a plurality of comparing operations in order to enhance the security. Incidentally, the comparison circuit CMP is operative in a test mode and judges the coincidence and discordance between the ROM content and the input signal (expected value) supplied from any of the input/output ports I/O or the input-only port I. Fig. 2 is a circuit diagram of one example of the comparison circuit CMP. In the test mode, the input-only port I becomes operative automatically, though this circuit arrangement is not particularly limitative, so that the input circuit DI transfers the signal supplied from the external terminal Din to the data bus in the bus BUS in synchronism with an inverted clock signal  . Fig. 2 illustrates a typical example of one unit input circuit DI constituting the input-only port I. In the 8-bit single chip microcomputer, eight unit input circuits DI are disposed and 8-bit input signals are supplied to eight data buses, though this circuit arrangement is not particularly limitative. The 8-bit input signal supplied to each data bus is held by a D-type flip-flop circuit F2, which receives the input signal, simultaneously with the inverted clock signal  (or in the low level period of the signal ). This flip-flop circuit F2 consists of eight flip-flop circuits, too. The programmed data of the read-only memory ROM are read out in synchronism with the non-inverted clock signal . In other words, the read signal of the read-only memory ROM is outputted to the data bus through the output circuit DO which is rendered operative by the clock signal . The output circuit DO consists of eight output circuits, too, and delivers the 8-bit read signal read out from the read-only memory ROM to the data bus. The 8-bit read signal supplied to the data bus is held by a D type flip-flop circuit F1, which receives the input signal, in synchronism with the clock signal  (in the high level period of the signal ). This flip-flop circuit F1 consists of eight flip-flop circuits, too. Though not limitative in particular, the flip-flop circuits F1 and F2 may have a set terminal (or a preset terminal and a clear terminal). In such a case, a reset signal is supplied to the set terminal before the test mode, and the flip-flop circuits F1 and F2 can enter the set state, that is, the output can be set to the high level. The signals received by the flip-flop circuits F1 and F2 are supplied to a digital comparator DC. The digital comparator DC consists of eight exclusive NOR circuits (coincidence/discordance circuits) and an eight input AND gate circuit that recives the outputs of the NOR circuits, respectively. The output of the flip-flop circuit F1 is supplied to one input terminal of each of the eight exclusive NOR circuits, and the output of the flip-flop circuit F2 is supplied to the other input terminal. The output of the AND gate circuit is used as the output of the digital comparator DC. In order to further ensure the security, the output signal of the digital comparator DC is not as such delivered to the external terminal TO but is outputted through the next output control circuit in this embodiment, though this circuit arrangement is not particularly limitative. In other words, the output signal of the digital comparator is supplied to the input terminal D of the D type flip-flop circuit F3 through the AND gate G1. The output signal Q of this flip-flop circuit F3 is supplied to the input terminal D of the D type flip-flop circuit F4. The flip-flop circuit F3 receives its input signal by means of the non-inverted clock signal  (in the high level period of the signal ), while the flip-flop circuit F4 receives its input signal by means of the inverted clock signal  (in the low level period of the signal ). These flip-flop circuits F3 and F4 are set by reset signals RES supplied to their set terminals S (or the preset terminal and the clear terminal) before the test mode. In other words, their outputs are at the high level. The output signal of the flip-flop circuit F4 is supplied to the input terminal of the AND gate circuit G1 as its control signal on one hand, and is outputted to the external terminal TO as the result of comparison through the AND gate G2, on the other. The output signal OC of the AND gate circuit G3, that receives the 4-bit address signals a0 - a3, is supplied to the other input of the AND gate circuit G2, though this is not particularly limitative. The lower 4 bits of the row or column address signal for the selection of the read-only memory ROM are used as the address signals a0 - a3. The row or column address signals are sequentially incremented or decremented in order to test the read-only memory ROM. Therefore, the lower 4 bits of the address signal that are incremented or decremented in the test rise to the high level once per 16 incrementation or decrementation. Accordingly, the output signal OC rises to the high level once per 16 accesses to the read-only memory ROM, and the test result is outputted to the external terminal TO at a rate of 1 to 16 test cycles. The test result may be outputted at a rate of once per 2, 4, 8, 32, 64, ... accesses. This can be set by changing the bit number of the input to the gate circuit G3. The test result can be outputted at a rate of 1 to 16 accesses by inputting the output of each stage of a 4-stage ripple counter to the gate circuit G3. The ripple counter is counted up in synchronism with the clock signal  or  . Other counters can be likewise utilized. Thus, the test result can be output once per an arbitrary number of access times by changing the counter construction. In this case, random access can be made to the read-only memory in the test mode. One example of the operation of the comparison circuit CMP will be described with reference to the timing chart shown in Fig. 3. The flip-flop circuits F3 and F4 are set during the high level period of the reset signal RES before the test operation. In other words, their outputs are set to the high level. The AND gate circuit G1 is kept open. Then, the test operation is started. Since the flip-flop circuit F3 operates in synchronism with the clock signal , the test operation is started from the clock signal  having the inverted phase. The expected value EO corresponding to the programmed data of the read-only memory ROM to be read out is supplied to the data bus through the input-only port I in synchronism with the low level of the clock signal  (the high level of the clock signal  ). This signal EO is held by the flip-flop circuit F2. Since the flip-flop circuit F3 is inoperative when the signal  is at the low level, the output of the comparator DC is not taken there-into. Therefore, the output of the flip-flop circuit F4 is kept at the high level. Though not particularly limitative, the row and column address signals are supplied to the read-only memory ROM during the low level period of the clock signal , and the 8-bit output signal of the read-only memory ROM is taken into by the output circuit DO. Next, the programmed data RO of the read-only memory ROM are outputted from the output circuit DO to the data bus in synchronism with the high level of the clock signal . This read signal RO is received by the flip-flop circuit F1 in synchronism with the clock signal . The signal RO of the flip-flop circuit F1 and the expected value EO are compared with each other by the digital comparator DC. The output of this comparator DC is transmitted to the input terminal of the flip-flop circuit F3 through the AND gate circuit G1 and is received in synchronism with the high level of the clock signal . If all the bits (8 bits) of the signal EO coincide with those of the signal RO, the output of the comparator DC is at the high level, so that the output signal of the flip-flop circuit F3 are kept at the high level as represented by solid line in Fig. 3. If any one of the bits of the signal EO is not in agreement with that of the signal RO, the comparator outputs the low level signal, so that the output signal of the flip-flop circuit F3 is inverted to the low level (logic "0") as represented by dotted line in the chart. The output signal of the flip-flop circuit F3 is transmitted to the flip-flop circuit F4 in synchronism with the fall of the clock signal  to the low level. When the discordance signal (logic "0") is transmitted to the flip-flop circuit F4, the output of the flip-flop circuit F4 drops to the low level. As a result, the output of the AND gate circuit G1 is kept fixed at the low level. In other words, the AND gate circuit G1 is closed to inhibit the reception of the subsequent comparator outputs. When the clock signal  drops once again to the low level as described above, the input of the next expected value E1 is effected. Thereafter, the same operation is repeated, and the indirect read operation read-only memory ROM, that is, comparison with the expected value and output of judgement, makes it possible to test the memory. In this embodiment, since only the comparison judgement output signal is delivered, decoding of the ROM content by the third party who does not know the ROM program content cannot be made. The present invention provides the following effects. (1) The programmed data of ROM can be read out indirectly by supplying the expected value from the external terminal and outputting only the result of its comparison judgement. Accordingly, only those who know the content of ROM can test it. (2) The expected value is supplied from the external terminal and is compared with the programmed content of the memory storing the security data, and only the result of comparison judgement is outputted. Therefore, the programmed content of the memory cannot be decoded substantially by those who do not know the content of the memory. (3) Since the comparison judgement outputs of a plurality of times of comparison are outputted, it becomes unknown which expected value is wrong. Therefore, in order to decode the programmed content, the expected values consisting of an extremely large number of combinations must be generated, and decoding of the programmed content by the third party becomes substantially impossible. When one judgement result is outputted per 16 times of comparison operations for the 8-bit expected value as in the foregoing embodiment, the necessary number is as great as 2 8x16 . (4) In comparison with a circuit arrangement wherein the output function to the external terminal of ROM or the like is completely inhibited by fuse means or the like, the present invention makes it possible to test the content of the memory so long as one knows the expected value. Therefore, this is extremely convenient for defect analysis and maintenance on the market. The built-in ROM may be various known programmable ROMs such as EPROM (erasable-programmable ROM), EEPROM (electrically erasable-programmable PROM) to which data are written electrically. It is also possible to employ the arrangement wherein the sequence for establishing the test mode is not laid open or a keyword is required for establishing the test mode. Such an arrangement can further enhance the security of the programmed content. Various forms may be used for the system configuration of the 1-chip microcomputer. For example, a switch which is turned ON only in the test mode may be disposed between each data bus and each of the flip-flop circuits F1 and F2. Signals other than the signal  may be supplied to the circuit DI and DO at times other than the test mode. Additional circuits such as A/D converters and the like may be further incorporated in order to expand the functions of the microcomputer. The built-in ROM may be of such a type into which data are written. The present invention can be widely applied to semiconductor integrated circuits having the microcomputer function such as the 1-chip microcomputer or IC cards, or to semiconductor integrated circuit devices which are equipped with a built-in ROM and which process signals in accordance with the content of ROM, or semiconductor memory device.

Claims: A semiconductor integrated circuit device comprising a memory circuit (ROM) the output of programmed data of which is adapted to be inhibited to an external terminal (TO), characterised by a comparing circuit (CMP) for comparing the programmed data read out from said memory circuit (ROM) with an input signal supplied from an external terminal (I, I/O), and out-putting the resulting coincidence or discordance signal to an external terminal (TO). The device of claim 1, wherein said memory circuit comprises a read-only memory (ROM). The device of claim 1 or 2, wherein the output of said coincidence or discordance signal is effected once after a plurality of said programmed data are compared with a plurality of said input signals corresponding to said programmed data. The device of claim 3, wherein said programmed data is read out in a unit of a plurality of bits. The device of claim 3 or 4, wherein the output of said coincidence or discordance signal is controlled by part of an address signal supplied to said memory circuit (ROM). The device of claim 3 or 4, wherein the output of said coincidence or discordance signal is controlled by a counter circuit (COUNT) in synchronism with said comparison operation. The device of any of claims 3 to 6, wherein said comparing circuit (CMP) includes holding means (F3, F4) for holding said coincidence or discordance signal, and inhibiting means (G1) for inhibiting the reception of subsequent results of comparison after one discordance signal is generated and held by said holding means (F3, F4). The device of any of claims 1 to 7, which further comprises a microprocessor (CPU) which executes calculation on the basis of said programmed data of said memory circuit (ROM), and wherein said memory circuit (ROM) consists of a read-only memory storing therein programs or data for said microprocessor (CPU). The device of any of claims 1 to 8, including output means (G2) controlled by memory address signals (a0...a3) for passing said coincidence or discordance signal to said external terminal (TO). The device of any of claims 1 to 9, and formed on an IC chip. The device of any of claims 1 to 10, wherein said comparing circuit (CMP) includes a digital comparator (DC), a first gate circuit (G1) having a first input coupled to the output of said comparator (DC), a first flip-flop (F3) coupled to the output of said first gate circuit (G1) and supplied with a first clock signal (), and a second flip-flop (F4) coupled to an output of said first flip-flop (F3) and supplied with a second clock signal (  ) opposite in phase to said first clock signal (), the output of the second flip-flop (F4) being coupled to an output stage (G2), wherein said first and second flip-flops (F3, F4) are respectively set to a first set of output levels when said comparator (DC) provides said coincidence signal, and to a second set of output levels when said comparator (DC) provides said discordance signal, and wherein an output of said second flip-flop (F4) is coupled to a second input of said first gate circuit (G1) to fix said first gate circuit (G1) to a predetermined level inhibiting the passage of signals from said comparator (DC) to said first flip-flop (F3) when said first and second flip-flops (F3, F4) are at said second output levels. The device of claim 11, wherein said output stage comprises a second gate circuit (G2) having its output connected to said external terminal (TO), a first input coupled to the output of said second flip-flop (F4) and a second input coupled to receive a control signal (OC) for controlling the timing of the application of said conincidence or discordance signal to said external terminal (TO). The device of claim 12, comprising a third gate circuit (G3) having its output connected to the second input of said second gate circuit (G2) and its inputs coupled to receive address signals (a0...a3) designating a predetermined selection state of said memory circuit (ROM), said third gate circuit (G3) generating said control signal (OC) when said address signals (a0...a3) indicate said predetermined selection state of said memory circuit (ROM).

Inventors: MATSUBARA, KIYOSHI, YAMAURA, TADASHI
Applicants: HITACHI, LTD.
Application year: 1986
Main classification: G11C29
IPC codes: G11C29, G06F21