IMAGE MEMORY

Abstract: A video random access memory (Video RAM) comprises a plurality of RAM and shift register sets, each RAM (7) being randomly accessed and each shift register (3) being serially ac­ cessed, each RAM and corresponding shift register being con­ nected by transfer gates (8) in order to transfer read/write data. Ther Video RAM further comprises an input/output circuit (4) which is operatively connected to the shift registers and is switched from an input side to an output side, or from an output side to an input side, in response to the direction of data trans­ fer between the RAM and the shift register, and a transfer con­ trol circuit (5) for controlling the switching of the input/output circuit and for controlling the direction of data transfer, based on predetermined modes of the input signals.

Description: This invention relates to a semiconductor memory, and more particularly to a video random access memory (Video RAM), made as a large scale integrated circuit (LSI) and used as an image memory. A Video RAM according to the present invention may be advantageously used for high speed serial read/write data transfer in an information processing system. Recently, display apparatus, particularly graphic display apparatus, has been considerably developed in the field of information processing systems. The Video RAM used in this graphic display apparatus is generally constituted by a plurality of RAM (for example dynamic RAM) and shift register sets. The RAM is used for storing the image data and is randomly accessed by a memory controller. The shift register is serially accessed and used for reading/writing the data from/to the RAM. Accordingly, one of the functions required of the Video RAM is a high speed read/write operation. Another requirement is to miniaturise a structure thereof, and thus increase the packaging density of the memory cell array. The Video RAM has many external pins (terminals), for example 24 pins, in order to connect with another device, but the number of terminals that can be provided is limited due to the above-mentioned miniaturisation and increase in package density. Therefore, many functions are required for each terminal, for example as a data or signal input/output terminal. In general, many input terminals and output terminals are used only for one purpose in a Video RAM. However, if the input terminal can be used in common with the output terminal, the number of pins having the input/output function can be reduced by half in the Video RAM. Accordingly, the remaining terminals can be used for other purposes, so that the Video RAM can have many other functions necessary to the graphic display. Three relevant conventional Video RAMs are disclosed in the NIKKEI ELECTRONICS, 1985, 5-20 and 8-12, and IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC85) DIGEST OF TECHNICAL PAPERS, February 1985. In the paper "New 64K memory chip gets the picture", A T & T Bell Laboratories Record, No. 1, Jan. 1985, pages 10-15 a video RAM is disclosed with serial access via a shift register having an input terminal for writing and an output terminal for reading. In EP-A-97778 a RAM is disclosed having a single terminal used for input and output to and from a shift register forming part of it. The device also includes a transfer control means to control the direction of data transfer depending on the direction of data transfer between the RAM and the shift register. In accordance with the present invention, there is provided a video random access memory (Video RAM) comprising a plurality of RAM and shift register sets, each RAM being randomly accessed and each shift register being serially accessed, and each RAM and shift register being connected by transfer gates in order to transfer read/write data, characterised by an input/output circuit operatively connected to the shift register and switchable from an input side to an output side or from an output side to an input side in response to the direction of transfer between the RAM and the shift register, and transfer control means comprising a memory for storing a previous transfer state for controlling the switching of the input/output circuit and for controlling said direction of data transfer based on the previous transfer state stored in the memory. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic block diagram of a conventional Video RAM; Figure 2 is a basic block diagram for explaining the principle of the invention; Figures 3A and 3B are basic block diagrams for explaining the basic operation of the invention; Figures 4A to 4C are basic mode patterns relating to an embodiment of the invention; Figs. 5A and 5B are basic mode patterns relating to another embodiment of the invention; Fig. 6 is a schematic block diagram of one form of Video RAM according to the invention; Fig. 7 is a detailed block diagram of a mode recognition logic and clock circuit forming part of the Fig. 6 circuit; Figs. 8A and 8B show a detailed circuit of a memory forming part of the Fig. 6 circuit; Fig. 9 is a logic diagram of a transfer command circuit forming part of the Fig. 6 circuit, which diagram corresponds to the second embodiment shown in Figs. 5A and 5B; Fig. 10 is a logic diagram of a transfer command circuit forming part of the Fig. 6 circuit, which diagram corresponds to the first embodiment shown in Figs. 4A to 4C; Figs. 11 to 14 are signal timing charts corresponding to various modes; Fig. 15 comprises a top view for explaining a terminal arrangement of the Video RAM according to the present invention, and a table of terminal details; Figs. 16 to 18 are timing charts of a best mode of operation of the present invention; and Fig. 19 is a timing chart of a combination of the various modes shown in Figs. 16 to 18. Before describing the preferred embodiments, a description will be given of a conventional Video RAM. Referring to Fig. 1, a Video RAM chip 1 comprises RAMs 2A to 2D, shift registers (SRs) 3A to 3D, clock generators 4A and 4B, input/output terminals SI01 to SI04 for the SRs 3A to 3D, input/output terminals DQ1 to DQ4 for the RAMS 2A to 2D, a row address strobe terminal RAS , a column address strobe terminal CAS , a write enable terminal WE , a transfer command/output enable terminal TR / OE , a serial clock signal terminal SCLK , and a serial output enable terminal SOE . In the Video RAM, the terminals SI01 to SI04 are used as input/output terminals of the shift registers 3A to 3D for serially accessing the data. Other terminals DQ1 to DQ4 are used as input/output terminals of the RAMs 2A to 2D for randomly accessing the stored data. As explained above, it is possible to reduce the number of pins greatly when some terminals are used as common input/output terminals. There are, however, some problems regarding the switching of the input/output mode of these terminals. Conventionally, the terminal SOE is also used as the terminal for switching the input/output mode. However, it is undesirable to use this terminal in common as the I/O switching terminal because there are large differences in "output data rate" between the RAM and the shift register. A video RAM according to the present invention will be explained in detail hereinafter. In the present invention, each terminal of the shift register is used as the input/output terminal, and it is possible to switch the input/output mode easily without using the terminal SOE as the input/output switching terminal and without newly adding another input/output terminal. A transfer control mode is utilised for switching the input/output mode in the present invention. Referring to Fig. 2, this basic block diagram shows a RAM and SR set, for example a set consisting of the RAM 2A and the shift register 3A in Fig. 1. Accordingly, reference numeral 2 represents a RAM, 3 a shift register (SR), 4 an input/output (I/O) circuit, 5 a transfer command circuit, and SIO an input/output terminal. The serial clock signal is input to the SR3 through the SCLK . The transfer write enable/serial output enable signal is input to the I/O circuit 4 through the TWE / SOE . Moreover, the transfer/output enable signal is also input to the transfer command circuit 5 through the TR / OE . The basic operation of serial read/write data transfer is as follows. That is, when the terminal SIO functions as the input terminal, the data is written in the RAM through the I/O circuit 4 and the SR 3 in response to the clock signal SCLK . In this case, the transfer signal TR is used for opening the gate transistor provided between the RAM and the SR. When the terminal SIO functions as the output terminal, the stored data is read from the RAM through the SR 3 and the I/O circuit 4. These operations will be explained in detail below. Referring to Figs. 3A and 3B, reference numeral 6 represents the data for one line, i.e., the data for one page on the word line in the RAM 2. The read operation is explained by using Fig. 3A and the write operation by using Fig. 3B. In the read operation, the data 6 is simultaneously read out in parallel to the shift register 3 in response to the transfer signal TR . When the transfer from the RAM to the SR is finished, the I/O circuit 4 is switched to the output side and the terminal SIO is switched to the output side. Then, data stored in the shift register 3 is serially read out from the terminal SIO. In the write operation, the I/O circuit 4 is switched to the input side before the transfer signal TR is input to the transfer gate. When the data is serially input to the shift register 3 through the input terminal SIO and fully stored in the shift register 3, the data is transferred and written in parallel in the RAM as the data for one line based on the transfer signal TR . As explained above, the switching of the I/O circuit 4 is performed in correspondence with the transfer and reading of the data from the RAM 2 to the SR 3, or in correspondence with the transfer and writing of the data from the SR 3 to the RAM 2. In these cases, it is necessary for the I/O circuit 4 to be switched from the input to the output after the data is transferred from the RAM 2 to the SR 3 in the read operation, while it is necessary for the I/O circuit 4 to be switched from the output to the input before the data is transferred from the SR 3 to the RAM 2. Regarding the above-mentioned switch, there is sufficient time for switching the I/O circuit 4 between these transfers of the data because the output data rate of the RAM is larger than that of the SR (i.e., the data output speed of the RAM is slower than that of the SR). Accordingly, since the operation of the SR is stopped from after the data transfer until the next transfer, the I/O circuit 4 can be switched during this interval. The principle of the present invention is based on the fact that the input/output mode of the I/O circuit 4 statistically depends on the data transfer direction between the RAM and the SR. That is, when the data is transferred from the RAM to the SR, the data is read out from the SR to the I/O circuit. Accordingly, the terminal SIO becomes an output side. While, when the data is transferred from the SR to the RAM, the data is written to the SR through the I/O circuit. In this case, the terminal SIO becomes an input side. As explained above, there is the sufficient time for switching the I/O circuit between the input and output. Consequently, various basic modes indicating the data transfer direction are set in order to switch the I/O circuit, and then the terminal SIO is switched based on the predetermined mode. These modes will be explained in detail hereinafter. Referring to Figs. 4A to 4C, Fig. 4A shows modes a and b , Fig. 4B mode c , and Fig. 4C modes d and e . The terminal RAS is used for inputting a row address strobe signal, and the CAS for inputting a column address strobe signal. The terminal TR / OE is used for inputting a data transfer signal and an output enable signal for reading, the terminal TRW / WE for inputting a transfer read/write signal and a write enable signal. Thus, it is possible to obtain various modes by combining these modes. 1. mode a The mode a shows an asynchronous operation between the RAM and the SR. The SR 3 is set to an output mode. 2. mode b The mode b also shows an asynchronous operation between the RAM and the SR. The SR 3 is set to an input mode. 3. mode c The mode c shows a read transfer operation in parallel from the RAM 2 to the SR 3. The terminal SIO is switched to the output side. 4. mode d The mode d shows a write transfer operation in parallel, from the SR 3 to the RAM 2. The terminal SIO is switched to the input side. 5. mode e The mode e shows a non-transfer mode and functions only when the terminal SIO switches to the input side. In modes a and b , the asynchronous operation means that the RAM and the SR separate independently from each other, based on the random access. The RAS and the CAS patterns are the same throughout Figs. 4A to 4C. In Fig. 4A, when the RAS is switched from "H" level to "L" level, as shown by a trailing edge arrow, the CAS is "H" level and TR / OE is also "H" level at the time showing a chain dotted line. The terminal TRW / WE is irrelevant to the read/write transfer because the RAM and the SR operate independently and asynchronously from each other. In this case, the distinction between mode a and mode b depends on the previous mode. That is, either mode a or mode b is determined by whether the previous mode is mode c or mode d. In Fig. 4B, the TR / OE is "L" level and the TRW / WE is "H" level. The "L" level of the TR / OE means a synchronous transfer and the "H" level of the TRW / WE means a read transfer. In Fig. 4C, the TR / OE is also "L" level but the TRW / WE is "L" level. The "L" level of the TRW / WE means a write transfer. In this case, the distinction between mode d and mode e also depends on the previous mode. That is, for example, when the previous mode is c , the mode e is selected. When the previous mode is either e or d , the mode d is selected. Referring to Fig.s 5A and 5B, Fig. 5A shows mode d and Fig. 5B shows mode e . As explained above, the same patterns as in Figs. 4B and 4C are provided to the RAS , CAS and TR / OE patterns. TWE / SOE is "L" level when mode d but "H" level when mode e at the time shown by a chain dotted line. The terminal TWE / SOE is used as a transfer write enable and serial output enable terminal. In this case, the non-transfer mode as shown by mode e is always necessary for data transfer. As mentioned above, the mode e is used only for switching the terminal SIO to the input side. This mode e is inserted between the read transfer mode and the write transfer mode in order to prevent an error such as the read data is used again as the write data. Referring to Fig. 6, reference numeral 7 represents a memory cell array corresponding to the RAM, 7A sense amplifiers (SA) each providing bit line, 8 transfer gates, 9 a memory, 10 a read amplifier (RA), 11 a write amplifier (WA), 12 a shift clock generator, 13 a pointer (P) and decoder (D), 14 a word line drive circuit, 15 an input/output amplifier, and 16 a mode recognition and clock generator. BL1 and BL1 to BL256 and BL256 represent a plurality of pairs of bit lines. As shown before, reference numeral 3 represents a plurality of shift registers (SR), 4 the I/O circuit and 5 the transfer command circuit. A transfer control means is constituted by the memory 9, transfer circuit 5, and mode recognition 16. Each transfer gate 8 is provided between each bit line BL and each shift register SR, and is turned ON/OFF by the signal from the transfer gate circuit 5. The memory 9 is provided for storing just before the transfer mode and constituted by flip-flop circuit as shown in detail hereinafter. The shift clock circuit 12 corresponds to the clock generator 4B in Fig. 1 and is used for generating clock signal SCLK . The output clock signal of this circuit 12 is input in parallel to the shift register 3, the I/O circuit 4, and the decoder D (13). The decoder D designates "H" level of the pointer P as a start point based on the input address signal. The designated pointer P outputs an "H" level signal to the transfer gate 8A and a selected transfer gate 8A is turned ON. Accordingly, read data can be read out from the shift register 3 through the transfer gate 8A and the bus line DB, while the write data can be written in the shift register 3 through the bus line DB and the transfer gate 8A. The pointer P sequentially designates the transfer gate 8A based on the clock signal and the transfer signal, the transfer gate 8A is also sequentially turned ON when the gate is high level, and can transfer the data from/to any of the shift registers 3. In the write mode, the I/O circuit 4 is switched to the input side, the data is temporarily stored in the shift register 3 through the write amplifier (WA) 11, the bus line DB, and the transfer gate 8A. Next, the mode d signal, which indicates a write operation, is input to the transfer command circuit 5 and the transfer gate 8 is opened by an output of this command circuit 5. The data stored in the shift register can be written in parallel to the memory cell array 7. In the read operation, the transfer gate 8 is opened by the output signal from the transfer command circuit 5. In this case, the circuit 5 outputs this signal based on the mode c signal which indicates a read operation. When the gate 8 is opened, the data for one line (page) is read out in parallel from the memory cell array 7 to the shift register 3. Next, the stored data in the shift register 3 is output from the terminal SIO through the transfer gate 8A, the bus line DB, the read amplifier 10, and the I/O circuit 4. The operation of each circuit will be explained in detail hereinafter. Referring to Fig. 7, reference letters A1 to A3 represent AND gate circuits, L1 to L3 clocked D-type latch circuits, IV1 to IV5 inverters, OR1 and OR2 OR gate circuits, and CG a clock generator. T1 represents an active pulse, T2 on reset pulse. The output clock signal CLK from the clock generator CG is input to the transfer command circuit 5. The asynchronous signal N0, the read signal R0, and the write signals W0 to W2 are also input to the transfer command circuit 5 and the memory 9. The signal N0 is used only for the asynchronous modes a and b , in order to drive the word line. The signal R0 is used for a read transfer, and the signals W0 to W2 are used for a write transfer. This circuit can be used for the first and second embodiments shown in Figs. 4A to 4C and 5A to 5B. Referring to Fig. 8A, this circuit is constituted by the depletion type MOS transistors Q1, Q2 and the enhancement type MOS transistors Q3 to Q8. The flip-flop circuit is constituted by the transistors Q1 to Q4, and the transistors Q5 to Q8 are used for switching the flip-flop circuit based on the write signal W0 and read signal R0. These W0 and R0 signals are input from the mode recognition circuit 16. The output mode SO (serial out) and SI (serial in) are transferred to the I/O circuit 4. This flip-flop circuit stores the direction of read/write transfer between one transfer mode and the next transfer mode. After the read transfer, the output SO becomes high and SI becomes low based on the read signal R0. These serial output states of "H" and "L" are switched by the read signal R0 and maintained hereinafter. While in the write transfer, the output SO becomes low and SI becomes high based on the write signal W0. These serial input states of "L" and "H" are switched by the write signal W0 and maintained hereinafter. Accordingly, this flip-flop circuit is switched, first, when the write transfer is input during the serial read state, and second, when the read transfer is input during the serial write state. Referring to 8B, this circuit is used for detecting a first write transfer after a continuous read transfer by using a monostable multi-vibrater. The write transfer signal WT having a pulse width t₂ is generated by detecting the leading edge of the signal SI, because the SI is switched to "H" level when a write transfer is carried out. Accordingly, the pulse width t₁ of the SI is not used for generating the WT. One pulse of the signal WT is output to the transfer command circuit 5. The circuit shown in Fig. 8A is used for the first and second embodiments shown in Figs. 4A to 4C and 5A to 5B, but the circuit shown in Fig. 8B is only used for the first embodiment shown in Figs. 4A to 4C. Accordingly, in the first embodiment, the memory circuit 9 is constituted by the flip-flop circuit and the monostable multi-vibrater. Referring to Fig. 9, the mode can be reaiized by the logic diagram of input signals W1, W2, R0, and N0. In this case, the terminal TWE / SOE is set to high level in order to indicate the mode e as shown in Fig. 5B. The mode e means that the write transfer is not activated and only the terminal SIO is switched to the input side. Each delay element DLY is provided in order to invert the drive time between the word line and transfer gate in the read/write transfer. The OR comprises an OR circuit, AMP amplifiers, and BUF buffers. This logic diagram corresponds to the second embodiment shown in Figs. 5A and 5B. Referring to Fig. 10, the mode can be realized by the logic diagram of input signals W1, WT, R0 and N0. In this case, since the terminal TWE / SOE is not concerned, it is necessary to detect the switch point of the SO and SI signal level. Accordingly, the signal WT is input to the AND gate, and by this signal, the first write transfer signal when the transfer mode is switched to the serial input side does not act as the transfer mode, and this transfer signal is used for switching from output to input terminal. Referring to Figs. 11 to 14, these signal timing charts show waveforms at each point of the circuits shown in Figs. 7 to 10. Referring to Fig. 11, this chart shows the mode c . In this case, the mode c is used by, for example, steps of mode d → b → b → c as the first case, and mode d → c as the second case. Each case is selected by the level of the signals SI and SO. Outputs P1 to P3 of the clocked D-type latch circuits are all low level because the input data D1 to D3 are latched by the active pulse T1 and reset by the reset pulse T2. Although, in the mode b or d , the signal SI is "H" and SO is "L" level, because these modes are input, after read transfer the signal SO becomes "H" level and SI becomes "L" level based on the "H" level of the read signal R0. In this case, the I/O circuit is switched to the output side. When the selected word line is turned from "L" to "H" level, the transfer gate is opened after a short delay DLY and the data is transferred from the RAM to the shift register. Referring to Fig. 12, this chart shows the mode d . In this case, the mode d is used by, for example, steps of mode b → b → d . The signal SI is "H" level and SO is "L" level because previous mode b is input mode. These "H" and "L" levels are maintained in this mode d. When the transfer gate is turned from "L" to "H" level, the selected word line is also turned from "L" to "H" level after a short delay DLY and the data is written from the shift register in the RAM. Referring to Fig. 13, this chart shows the mode e . In this case, the mode e is used by, for example, steps of mode a → a → e → b → b → d. The signal SI changes from "L" to "H" level and SO changes from "H" to "L" level. These "L" and "H" levels are maintained in this mode e . The I/O circuit is switched to the input side. The transfer gate is maintained to "L" level so that the data transfer is not performed in this mode, in spite of the fact that the word line is selected to the "H" level. Referring to Fig. 14, this chart shows modes a and b . In the mode a , the signal SI is "L" level and the signal SO is "H" level. In this mode b , the signal SI is "H" level and the signal SO is "L" level. In this case, the transfer gate is maintained at "L" level so that the data transfer between the RAM and the shift register is not performed in these modes. The explanation will be given of the best mode of operation for carrying out the present invention. The best mode for the present invention is employed in the Video RAM model MB81461 made by Fujitsu Limited. This Video RAM is basically constituted by four RAM's, each of which comprises a 256 x 256 bits memory cell array, and four corresponding shift registers (SR) each having 256 bits. Referring to Fig. 15, this Video RAM has 24 pins. Each of the terminals 1 to 24 has a different function, as shown in the list of Fig. 15. The RAM has the same functions as a dynamic RAM (DRAM) constituted by the standard type (64K x 4) except for a data transfer cycle function. This RAM also comprises the functions RAS only·refresh, page·mode, and CAS before RAS refresh. The data transfer between the RAM and the SR is performed by the RAS cycle. Whether this is a transfer cycle or normal RAM cycle is determined by the TR / OE signal in the initial cycle. The data can be transferred both ways and the direction of the data transfer is determined by the TRW / WE signal. In general, the transfer from the RAM to the SR is called a "read transfer", and the transfer from the SR to the RAM is called a "write transfer". The data transfer is always performed by every row per one cycle, as shown in Figs. 3A and 3B. When the data transfer is run, the input/output of the SR is simultaneously switched. That is, when the read transfer cycle is run, the I/O terminal of the SR is switched to the output mode hereinafter and the output data is obtained from the SD terminal in response to th shift clock SCLK . When the write transfer cycle is run, the I/O terminal of the SR is switched to the input mode hereinafter and the input data is written from the SD terminal in response to the SCLK . When the write transfer is not performed and only the I/O terminal is switched to the input mode, a dummy write transfer cycle (or, write mode enable cycle) is used instead of the write transfer cycle. The difference between these write transfer cycles lies in the level of the TWE / SOE . Each shift register SR is constituted by a data register and a pointer. The serial operation of the pointer is performed in response to the leading edge of the SCLK by adding "1" to the selected address. When the pointer reaches the final address, the pointer returns to the first address in response to the next SCLK . After data transfer, the first accessed address can be optionally selected by the transfer cycle. This address is serially accessed as the first address by inputting the SCLK after data transfer. The SR can perform "real time read transfer". This transfer can be performed by synchronizing with TR / OE for a short time in the transfer cycle. That is, it is possible by serializing the data read of the SR before transfer with the data read of the SR after transfer. The input/output terminal of the SR is controlled by the TWE / SOE . That is, this terminal functions as an output enable in the output mode and as a write inhibit in the input mode. Actual timing charts of the operation of the model MB81461 are shown in Figs. 16 to 18. One feature of the operation is that the function decision is performed by the trailing edge of the RAS . When the TR / OE is high level at this trailing edge, the data transfer is not performed, i.e., the RAM and the SR operate independently (i.e., asynchronously as shown in Fig. 4A) to one another. When the TR / OE is low level at this trailing edge, the data transfer is performed. In the transfer mode, when the TRW / WE is "H" level, it denotes a read transfer, and when the TRW / OE is of "L" level, it denotes a write transfer. Referring to Fig. 16, this timing chart shows an independent mode of the RAM and the SR. This chart corresponds to that of Fig. 4A. The TR / OE is used as the output enable of the RAM. The SR is set to the output mode. The output data SD₁ can be obtained after an access time from the leading edge of the SCLK as shown by the arrow. Referring to Fig. 17, this timing chart shows a read transfer from the RAM to the SR. This chart corresponds to that of Fig. 4B. In this case, the row address to be transferred in the RAM is designated by the portion corresponding to the row address, and the head address for reading the SR after transfer is designated by the portion corresponding to the column address. Accordingly, the asterisk mark attached to the ROW denotes the row address of the page to be transferred and the asterisk mark attached to the SR denotes the read start address of the SR after transfer. Actual transfer is performed by the leading edge as shown by arrow in the TR / OE . In the SCLK applied before this leading edge, the SR data (a) just before transfer is read out, while in the SCLK applied after this leading edge, the SR data (b) just transferred is read out. Referring to Fig. 18, this timing chart shows a write transfer from the SR to the RAM. This chart corresponds to that of Figs. 4C and 5A, 5B. The SCLK must stop input during a low level of the RAS . The TWE / SOE is low level in the trailing edge of the RAS when a write transfer is carried out. When the TWE / SOE is high level, it denotes a dummy write transfer cycle. In this case, the I/O mode of the SR is switched to the input mode and the data transfer is not performed. This mode is shown in Fig. 5B as mode e . The asterisk mark attached to the ROW and the SR have the same meanings as that of Fig. 17. Referring to Fig. 19, this chart shows a combination of above-mentioned operation modes. V CC represents a power source voltage. In the transfer mode, DC represents a dummy cycle, RT a read transfer, WT a write transfer, ASYN an asynchronous operation, and DWT a dummy write transfer.

Claims: A video random access memory (Video RAM) comprising a plurality of RAM and shift register sets, each RAM (7) being randomly accessed and each shift register (3) being serially accessed, and each RAM and shift register being connected by transfer gates (8) in order to transfer read/write data, characterised by an input/output circuit (4) operatively connected to the shift register and switchable from an input side to an output side or from an output side to an input side in response to the direction of data transfer between the RAM and the shift register, and transfer control means (5,9,16) comprising a memory (9) for storing a previous transfer state for controlling the switching of the input/output circuit and for controlling said direction of data transfer based on the previous transfer state stored in the memory (9). A Video RAM as claimed in claim 1, in which the transfer control means comprises a transfer command circuit (5) for commanding a transfer signal to the shift register (3) and for controlling ON/OFF switching of the transfer gate (8), and a mode recognition and clock circuit (16) for recognising predetermined modes in order to control the memory and the transfer command circuit. A Video RAM as claimed in claim 2, characterised in that the mode recognition and clock circuit (16) comprises three clocked D-type latch circuits (L1-L3) for inputting four kinds of commands and one OR gate (OR1) and three AND gate (A1-A3) circuits for outputting read/write signals. A Video RAM as claimed in claim 2 or claim 3, characterised in that the memory (9) comprises a flip-flop circuit (Q1-Q4) for latching a serial read/write transfer state. A Video RAM as claimed in claim 4, characterised in that the memory (9) further comprises a monostable multivibrator for switching the input/output mode. A Video RAM as claimed in any one of claims 2 to 5, characterised in that the transfer command circuit (5) comprises a logic circuit for controlling the transfer gate (8), a word driver (14), and a pointer-decoder (13). A Video RAM as claimed in any preceding claim, characterised in that the direction of data transfer is determined by four transfer modes. A Video RAM as claimed in claim 7, characterised in that the four transfer modes comprise an asynchronous mode, a read transfer mode, a write transfer mode, and a non-transfer mode. A Video RAM as claimed in claim 7 or claim 8, characterised in that each of the transfer modes is constituted by combining the four transfer modes. A Video RAM as claimed in claim 9, characterised in that each of the transfer modes is detected by the trailing edge of a row address strobe signal.

Inventors: OGAWA, JUNJI
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G11C8
IPC codes: G11C11, G06F12, G11C7