SEQUENTIAL LOGIC CIRCUIT

Abstract: A sequential logic circuit has a logic memory (2′), a preced­ ing logic circuit (1′), a succeeding logic circuit (3′), and a function defining circuit (10). An input signal (4) is taken by the preceding logic circuit (1′), where a new logic state (6) is produced based on the input signal (4) and a present logic state (5) in the logic memory (2′) executing a defined calculation. The content of the logic memory (2′) is taken over by the new logic state (6). The succeeding logic circuit (3′) produces an output signal (7) based on the logic state (5) of the logic memory (2′) executing a defined calculation. The calculation executed in the succeeding (1′) or preceding (3′) logic circuit is defined by the defining function circuit (10). Thus, the whole circuit operates with a desired function.

Description: BACKGROUND OF THE INVENTION This invention relates to a sequential logic circuit and, more particularly, to a multi-functional sequential logic circuit comprising semiconductor integrated circuits. A block diagram of a typical sequential logic circuit is shown in Fig. 1. This circuit comprises of a preceding logic means 1, a logic memory means 2, and a succeeding logic means 3. A flip-flop circuit is usually utilized for the logic memory means 2, and a logic gate or a ROM is usually utilized for the preceding logic means 1 and the succeeding logic means 3. The preceding logic means 1 is supplied with two input signals, that is, an external INPUT 4 from an external circuit (not shown), and a logic state 5 from the logic memory means 2. With these two input signals, a logic calculation is executed so that the preceding logic means 1 generates a new logic state 6 and the content of the logic memory means 2 is rewritten with the generated new logic state. On the other hand, the logic state 5 is also given to the succeeding logic means 3. Then the succeeding logic means 3 outputs an OUTPUT 7 which is obtained from the logic state signal 5 through a predetermined logic calculation. Thus the sequential logic circuit decides the next logic state always depending on the present logic state and the external INPUT. As each of the preceding logic means 1 and the succeeding logic means 3 is made up of a logic gate or a ROM, a logic calculation executed in each logic means is defined by an arrangement of the logic gate or the content of the ROM. In conclusion, the function of the whole sequential logic circuit is defined unequivocally by them. When a user wants to operate the sequential logic circuit with another function, a rearrangement of the logic gates or a change of the ROM is required. Even if the desired function slightly differs from the present function, the whole circuit need to be changed. The change requires considerable time and labor. In order to give a multi-function to the sequential logic circuit, the whole circuit becomes large and complex because an individual arrangement of logic circuits or an individual ROM have to be provided for each function. Both the Article "PROM Based Fast Logic Systems" M.H. Graff, 1974, IEEE Intercon Technical Program Papers, p.p. 1-5, and the book, "Digital Logic Techniques" T.J. Stonham, 1984, von Nostrand Reinhold (UK) Co. Ltd. p.p. 103-108, describe sequential logic circuits. Both documents describe a memory which operates as a combinational circuit which receives external inputs and outputs the next state as a function of the previous state and the external inputs. The previous state is stored in a series of flip-flops whose outputs are connected to inputs of the memory. A PROM and a RAM memory are recommended respectively for the combinational circuit. The article by T.J. Stonham describes two methods of increasing the function capacity of a sequential logic circuit. In the first method, a Parallel arrangement of memory planes is provided with a single decoder. A separate memory plane is used for each function. In the second method, all the functions are stored in one memory and the particular function required is selected with function address inputs. It is also know from the article to provide a sequential logic circuit in which the memory is initially programmed via data-in terminals by compiling an address/ contents table from the present/next state and output specifications of the sequential logic circuit. A subsequent programming of the memory is not disclosed. From Tietze-Schenk, Halbleiterschaltungstechnik, 1983, pages 286-287, the equivalence between a dual port RAM and a single port RAM in combination with a multiplexer is known. The object of this invention is to provide a further sequential logic circuit whose logic function can be easily altered. The foregoing object is accomplished by providing a sequential logic circuit, comprising a logic memory means which stores a predetermined logic state; a preceding logic means which is supplied with an external input and a logic state stored in said logic memory means as inputs, for generating a new logic state by executing a logic calculation upon these inputs and for rewriting the content of said logic memory means with said new logic state; and a succeeding logic means which is supplied with said logic state stored in said logic memory means as an input for outputting a logic state obtained from a logic calculation with the input, characterized by a function defining means which defines a logic calculation executed in said preceding logic means and/or said succeeding logic means depending on the desired function, said preceding logic means comprising a RAM which outputs a data stored at a selected address as a new logic state, said RAM being a dual-port RAM which has a first address port, a first data port, a second address port and a second data port, the external input and the logic state stored in the logic memory means being given to the first address port of said RAM, the first data port of said RAM being connected to said logic memory means, the second address port and the second data port of said RAM, being connected to the function defining means, said first address and data ports being used for reading data, said second address and data ports being used for writing data, and a selecting gate which is connected between the function defining means and the second data port and allows data to be transferred therebetween dependent upon an open gate signal from the function defining means. The object of the invention is also solved by a sequential logic circuit, comprising a logic memory means which stores a predetermined logic state; and a preceding logic means which is supplied with an external input and a logic state stored in said logic memory means as inputs, for generating a new logic state by executing a first logic calculation upon these inputs and for re-writing the content of said logic memory means with said new logic state; characterized by a succeeding logic means which is supplied with said logic state stored in said logic memory means as an input, for outputting a logic state obtained from a second logic calculation carried out on the input; the succeeding logic means comprising a dual-port RAM which is preprogrammed with data in accordance with the second logic calculation which outputs a data stored at a selective address as the output signal, the logic state stored in said logic memory means is supplied to the first address port of said dual-port RAM, an output signal to be supplied to an external circuit is taken out from the first data port of said dual-port RAM, said first address and data ports (A, D) of said dual port RAM are used for reading data, and said second address and data ports of said dual-port RAM are used for writing data, and a function defining means for defining a third logic calculation executed in said succeeding logic means by re-writing the data in said succeeding logic means with a data signal supplied from said function defining means to the second data port of said dual-port RAM according to an address signal supplied to the second address port of said dual-port RAM from said function defining means. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: Fig. 1 illustrates a block diagram showing a sequential logic circuit according to the prior art; Fig. 2 illustrates a block diagram showing one embodiment of a sequential logic circuit according to this invention; Fig. 3 illustrates a block diagram showing another embodiment of a sequential logic circuit according to this invention; and Fig. 4 illustrates a block diagram showing a further embodiment of a sequential logic circuit according to this invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The sequential logic circuit shown in Fig. 2 illustrates an embodiment of the invention in which a logic calculation executed in a preceding logic means is definable. The preceding logic means comprises a dual-port RAM 1', and the logic memory means comprises a flip-flop circuit 2'. An external INPUT 4 and a logic state 5 outputted from the flip-flop circuit 2' are given to a first address port A1 of the RAM 1', and a corresponding data which is selected based on a given address through the port A1 is outputted as a new logic state 6 through a first data port D1. Ordinarily, the dual-port RAM 1' operates with the first ports A1 and D1. In this ordinary mode, as an R/W signal 8 indicates "read", an output data is read out through the data port D1. A selecting gate 9 is closed so that the data port D1 is connected only to the flip-flop circuit 2'. Therefore, in the above mode, this circuit operates similarly to the circuit shown in Fig. 1, and its function is decided depending on the contents of the RAM 1'. When a user wants to operate this circuit to provide another function, the content of the RAM 1' is rewritten using the second port as follows. An address signal 11 from the function defining means 10 is given to the second address port A2, and a data signal 12 from the function defining means is given to the second data port D2 which is in common with port D1 in this embodiment. Simultaneously, the function defining means 10 gives an open gate signal 13 to the selecting gate 9 and an R/W signal 8 indicating "write" to the RAM 1', respectively, so as to rewrite the RAM 1' with the data signal 12. Thus, the content of the RAM 1' is rewritten with desired data, so that the circuit shown in Fig. 2 operates with a desired function after it has returned to the ordinary mode. The sequential logic circuit shown in Fig. 3 illustrates another embodiment of the invention in which a logic calculation executed in a succeeding logic means is definable. The succeeding logic means comprises a RAM 3' and the logic memory means includes a flip-flop circuit 2'. Though the RAM 3' is a single-port RAM, it operates in the same manner as the dual-port RAM 1' shown in Fig. 2 because of the function of a multiplexer 14. The multiplexer 14 selects either a logic state 5 from the flip-flop circuit 2' or an address signal 11 from the function defining means 10 depending on a selecting signal 15 from the function defining means 10. The signal selected by the multiplexer 14 is given to an address port A of the RAM 3'. Ordinarily, as the multiplexer 14 selects the logic state 5 and as an R/W signal 8 indicates "read", an output data which corresponds to the logic state 5 is read out through a data port D as an OUTPUT signal. In this ordinary mode, a selecting gate 9 is closed and this sequencial logic circuit operates similarly to the circuit shown in Fig. 1. The function of this circuit is decided depending on the content of the RAM 3'. When a user wants to operate this circuit to provide another function, the content of the RAM 3' is rewritten as follows. The selecting signal 15 causes the multiplexer 14 to select the address signal 11 so as to access the RAM 3' with the signal 11. Simultaneously, the function defining means 10 gives an open gate signal 13 to the selecting gate 9 and an R/W signal 8 indicating "write" to the RAM 3', respectively, so as to give a data signal 12 to the data port D thereby effecting a write operation. Thus the content of the RAM 3' is rewritten with desired data, so that this circuit operates with a desired function after it has returned to the ordinary mode. The sequential logic circuit shown in Fig. 4 illustrates still further an embodiment of the invention in which a logic calculations executed in both of the preceding and succeeding logic means are definable. Each of the preceding and succeeding logic means includes a RAM 16. As a consequence, a part of addresses of the RAM 16 is assigned to the preceding logic means and the other part to the succeeding logic means, respectively. The logic memory means is constituted by of a flip-flop circuit 2'. Though the RAM 16 is a single-port RAM, it operates in the same manner as a dual-port RAM because of a function of a multiplexer 14. The multiplexer 14 selects either a logic state 5 from the flip-flop circuit 2' or an address signal 11 from the function defining means 11 depending on a selecting signal 15 from the function defining means 10. The selected signal is given to an address port A of a RAM 16. Ordinarily, as the multiplexer 14 selects the logic state 5 and an R/W signal 8 indicates "read", an output data which corresponds to the logic state 5 is read out through a data port D. This output signal is given to an external circuit as an OUTPUT signal and also given to the flip-flop circuit 2' as a new logic state 6. In the above described ordinary mode, the selecting gate 9 is closed. Thus the logic circuit shown in Fig. 4 operates similarly to the circuit shown in Fig 1, and its function is decided depending on the content of the RAM 16. When a user wants to operate this circuit to provide another function, the content of the RAM 16 is rewritten as follows. The selecting signal 15 causes the multiplexer 14 to select the address signal 11 so as to access the RAM 16 with the signal 11. Simultaneously, the function defining means 10 gives an open gate signal 13 to the selecting gate 9 and an R/W signal 8 indicating "write" to the RAM 16, respectively, so as to give a data signal 12 to the data port D, thus effecting a write operation. Thus, the content of the RAM 16 is rewritten with desired data, so that this circuit operates with a desired function after it has returned to the ordinary mode.

Claims: A sequential logic circuit, comprising a logic memory means (2') which stores a predetermined logic state; and a preceding logic means (1') which is supplied with an external input (4) and a logic state (5) stored in said logic memory means (2') as inputs, for generating a new logic state (6) by executing a first logic calculation upon these inputs (4, 5) and for rewriting the content of said logic memory means with said new logic state (6); said preceding logic means (1') comprising a RAM which is pre-programmed with data in accordance with the first logic calculation and which outputs a data stored at a selective address as the new logic state (6), the external input (4) and the logic state (5) stored in the logic memory means (2') being supplied to the address port (A) of said RAM (1') and the data port (D) of said RAM (1') being connected to said logic memory means (2'); the address and data ports (A, D) of said RAM (1') being used for reading and writing data; characterized by a succeeding logic means (3') which is supplied with said logic state (5) stored in said logic memory means (2') as an input, for outputting a logic state (7) obtained from a second logic calculation carried out on the input; said RAM (1') being a dual-port RAM (1'), the external input (4) and the logic state (5) stored in the logic memory means (2') being supplied to the first address port (A') of said dual-port RAM (1'), and the first data port (D) being connected to said logic memory means (2'); and a function defining means (10) for defining a third logic calculation executed in said preceding logic means (1') by re-writing the data in said preceding logic means (1') with a data signal (12) supplied from said function defining means (10) to the second data port (D2) of said dual-port RAM (1') according to an address signal (11) supplied to the second address port (A2) of said dual-port RAM (1') from said function defining means (10). A sequential logic circuit, comprising a logic memory means (2') which stores a predetermined logic state; and a preceding logic means (1) which is supplied with an external input (4) and a logic state (5) stored in said logic memory means (2') as inputs, for generating a new logic state (6) by executing a first logic calculation upon these inputs (4, 5) and for re-writing the content of said logic memory means with said new logic state (6); characterized by a succeeding logic means (3') which is supplied with said logic state (5) stored in said logic memory means (2')as an input, for outputting a logic state (7) obtained from a second logic calculation carried out on the input; the succeeding logic means (3') comprising a dual-port RAM which is preprogrammed with data in accordance with the second logic calculation which outputs a data stored at a selective address as the output signal (7), the logic state (5) stored in said logic memory means (2') is supplied to the first address port (14, A) of said dual-port RAM (1), said output signal (7) to be supplied to an external circuit is taken out from the first data port (D) of said dual-port RAM (1), said first address and data ports (A, D) of said dual port RAM (1) are used for reading data, and said second address and data ports (A, D) of said dual-port RAM (1) are used for writing data, and a function defining means (10) for defining a third logic calculation executed in said succeeding logic means (3') by re-writing the data in said succeeding logic means (3') with a data signal (12) supplied from said function defining means (10) to the second data port (D) of said dual-port RAM (3') according to an address signal (11) supplied to the second address port (14,A) of said dual-port RAM (3') from said function defining means (10). A sequential logic circuit according to claim 1, characterized in that the succeeding logic means (3') comprises a RAM which outputs a data stored at a selected address as the output signal (7). A sequential logic circuit according to claim 2, characterized in that the preceding logic means (1) comprises a RAM which outputs a data stored at a selected address as a new logic state (6). A sequential logic circuit, comprising a logic memory means (2') which stores a predetermined logic state; and a preceding logic means (16) which is supplied with an external input (4) and a logic state (5) stored in said logic memory means (2') as inputs, for generating a new logic state (6) by executing a first logic calculation upon these inputs (4, 5) and for re-writing the content of said logic memory means (2') with said new logic state (6); said preceding logic means being comprised in a part of a single port RAM (16) which is pre-programmed with data in accordance with the first logic calculation and which outputs a data stored at a selective address as the new logic state (6), the external input (4) and the logic state (5) stored in the logic memory means (2') being supplied to the address port (A) of said RAM (16) and the data port (D) of said RAM (16) being connected to said logic memory means (2'); the address and data ports (A, D) of said RAM (16) being used for reading and writing data; characterized by a multiplexer (14) which is connected to the address port (A) of said single-port RAM (16) and a selecting gate (9) which is connected to the data port (D) of said single-port RAM (16); a succeeding logic means (16) which is supplied with said logic state (5) stored in said logic memory means (2') as an input, for outputting a logic state (7) obtained from a second logic calculation carried out on the input; said succeeding logic means being comprised in another part of said RAM (16), the logic state (5) stored in the logic memory means (2') being supplied to a first input of the multiplexer (14), and the data port (D) being connected to said logic memory means (2'); and a function defining means (10) for defining a third logic calculation executed in said preceding and succeeding logic means (16) by re-writing the data in said preceding and succeeding logic means (16) with a data signal (12) supplied from said function defining means (10) to the data port (D) through said selecting gate (9) and an address signal (11) supplied to the address port (A) through a second input of said multiplexer (14). A sequential logic circuit according to any of claims 1 to 4, characterized in that said RAM is constructed by combining a single port RAM (3'), a multiplexer (14) which is connected to the address port (A) of said single-port RAM and a selecting gate (9) which is connected to the data port (D), of said single-port RAM; said function defining means (10) defining the function of the single-port RAM by providing a selecting signal (15) to the multiplexer (14), a gate signal (13) to the selecting gate (9) and a R/W signal (8) to the single-port RAM (3'). A sequential logic circuit according to claim 5, characterized in that said function defining means (10) defines the function of the single-port RAM (16) by providing a selecting signal (15) to the multiplexer, a gate signal (13) to the selecting gate and a R/W signal (8) to the single-port RAM. A sequential logic circuit according to any of claims 1 to 7, characterized in that the logic memory means (2') comprises a flip-flop circuit.

Inventors: KAIZUKA, MASAO, SHIMIZU, HIROSHI
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H03K19
IPC codes: G05B19, G06F9, H03K19