CLOCK SIGNAL CONTROL CIRCUIT

Abstract: A clock signal circuit receives first and second clock signals (CLOCK 0, CLOCK 1) the pulses of which are non-overlapping with respect to each other. The first and second clock signals (CLOCK 0, CLOCK 1) are applied to the source-drain paths of respective first and second MOS transistors (36, 40), the gate electrodes of which are coupled via the source-drain paths of third and fourth MOS transistors (34, 38) to the outputs of respective first and second NOR gates (31, 32) receiving the second and first clock signals, respectively, and also receiving first and second control signals. The outputs of the NOR gates (31, 32) are further connected to a third NOR gate (42) having an output connected to the gate electrode of a fifth MOS transistor (44) connected to an output line. In operation, selected, booted clock signals are supplied to the output line.

Description: CLOCK SIGNAL CONTROL CIRCUIT Technical Field This invention relates to clock signal circuits of the kind for selecting clock signals for output on a clock output line. Background Art In semiconductor devices, clock generators are employed which have output driver circuits for driving capacitive loads between a low level, usually ground, and high level, usually the supply voltage. In driving towards the high level using MOS devices, there is encountered a voltage drop of one enhancement threshold voltage from the supply voltage which is caused by the electrical characteristics of MOS devices. The clocking signal thereby loses some of its amplitude causing deterioration in the operation of circuits which are activated by the clock signal. Bootstrap circuits can be used to increase and/or restore the full amplitude of the clock signal. In integrated circuit design, the area required for conductors and devices limits the reduction in size of the chip on which the circuit is implemented and in turn increases the cost and generally decreases the speed of the circuit. It is therefore desirable, if possible, to run two signals over the same line, thereby eliminating the need for one line as long as the two signals do not interfere with each other. Such being the case, the area required to implement a - circuit is reduced making for smaller and faster circuits. Disclosure of the Invention It is an object of the present invention to provide a simple and inexpensive circuit for selecting clock signals for output on a clock output line. wherein booted clock signals are provided on the output line. Therefore, according to the present invention, there is provided a clock signal circuit for selecting clock signals for- output on a clock output line, characterized by first and second clock input means adapted to receive non-overlapping clock signals and connected -to said clock output line by respective first and second MOS devices; third and fourth MOS devices coupled to said first and second MOS devices, respectively; and logic means connected to said third and fourth MOS devices and responsive to clock signal control signals and to said clock signals, whereby selected booted clock signals are provided on said clock output line. A further advantage of a clock signal circuit according to the invention is the capability of operating on two clock signals and providing a combination of either the first or the second clock signal on the clock signal output without causing interference between the two clock signals. An additional advantage is that the circuit is suitable for implementation as a small and fast operating circuit. In brief summary of a first embodiment of the invention, there are provided two identical circuit paths for control of the respective clock signals, each circuit path starting with a NOR gate having as inputs the respective control signal and the other clock signal. The output of each NOR gate is directed to a source terminal of a MOS device with the gate of the MOS device connected to the supply voltage. The drain of the MOS device is connected to the gate of a second MOS device with the source of the second MOS device being connected to receive the first clock signal. The drain of the second MOS device is connected to the circuit's output terminal. The similar circuit path for the second clock signal has its output connected to the same output terminal. The output terminal is connected by means of an output MOS device to a reference potential such as ground. A NOR gate connects the output of the first and second NOR gates to the gate of the output MOS device. In a second embodiment of the invention, the turn off and turn on times of the bootstrapping circuit are assured and the conduction path between the two clock signals through two MOS devices when the clock signals are low is eliminated by cross-coupling the output of each of the NOR gates through AND circuits which are clocked by a flip-flop circuit receiving as toggling inputs the first and second clock signals. In a third embodiment of invention there is provided a circuit which is responsive to input signals which are complementary to the input signals for the first and the second embodiments. Brief Description of the Drawings Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating the present invention. Fig. 2 is a logic diagram partly in circuit form of the preferred embodiment of the present inven¬ tion. Fig. 3 is a circuit schematic of the preferred embodiment shown in Fig. 2. Fig. 4 is a logic diagram partially in circuit form of a second embodiment of the present invention. Fig. 5 is a circuit diagram of the second embodiment illustrated in Fig. 4. Fig. 6 is a set of waveforms occurring at like labeled points on the embodiments shown in Figs. 2-5. Fig. 7 is a set of waveforms occurring at like labeled points on the embodiment shown in Figs. 4 and 5. Fig. 8 is a logic diagram partly in circuit form of a third embodiment of the present invention. Fig. 9 is a circuit diagram of the third embodiment illustrated in Fig. 8. Fig. 10 is a set of waveforms occurring at like labeled points on the third embodiment shown in Figs. 8 and 9. Best Mode for Carrying Out the Invention Referring to Fig. 1, the box labeled 20 represents the circuit of the present invention re¬ ceiving as inputs the signal CONTROL FOR CLOCK 0, the signal CONTROL FOR CLOCK 1 and the non-overlapping clock signals, CLOCK 0 and CLOCK 1. It should be understood that the individual pulses of the clock signal CLOCK 0 do not overlap with the individual pulses of the clock signal CLOCK 1. Furthermore, as will be appreciated from the ensuing description, the signal CONTROL FOR CLOCK 0 can change during the CLOCK 1 time, but is stable during the CLOCK 0 time. Similarly, the signal CONTROL FOR CLOCK 1 can change during the CLOCK 0 time but is stable during the CLOCK 1 time. The output is taken from the terminal labeled OUTPUT and consists of a five volt pulse train. In the preferred embodiment of the invention, CLOCK 0 and CLOCK 1 are trains of five volt pulses. In operation, the CLOCK 0 or the CLOCK 1 is passed to the OUTPUT terminal upon the activation of the boot circuit by means of the control for clock signals appearing on the inputs. The first embodiment for accomplishing the function depicted in Fig. 1 is shown in Fig. 2. Referring to Fig. 2, the circuit path of each of the clocking signals is substantially identical. The signal CLOCK 1 is directed to one input of a NOR gate 31. The CONTROL FOR CLOCK 0 signal is applied to the other input of NOR gate 31. The output of NOR gate 31 is directed to the source terminal of a MOS device 34, with the drain terminal of the MOS device connected to the gate terminal of MOS device 36. The drain terminal of MOS device 36 is connected to the OUTPUT terminal. The gate of MOS device 34 is connected to an appropriate source of voltage VQD. The source terminal of MOS device 36 is connected to receive the CLOCK 0 signal. In a like manner, the CLOCK 0 signal is applied to one input of a NOR gate 32. The output of NOR gate 32 is connected to the source terminal of a MOS device 38. The CONTROL FOR CLOCK 1 signal is applied to the other input of the NOR gate 32. The gate terminal of the MOS device 38 is connected to the source of voltage V^Q. The drain of MOS device 38 is connected to the gate of MOS device 40 with the source terminal of MOS device 40 connected to receive the CLOCK 1 signal. The drain of the MOS device 40 is connected to the OUTPUT terminal. A MOS device 44, connects the OUTPUT terminal to a reference potential, which may be ground, in response to signals appearing on its gate input. A NOR device 42 has one input connected to the output of NOR gate 31 and a second input connected to the output of NOR gate 32. The output of the NOR gate 42 drives the gate of MOS device 44 in response to the signal levels on its input. In operation, when the input signal levels to NOR gate 31 are low, generally ground, the output of NOR gate 31 is high and is directed to the input of the NOR gate 42 which effectively grounds the gate of the MOS device 44 preventing its turn on. Referring now to Fig. 3, the logic circuit diagram of Fig. 2 is converted into a physical circuit diagram with the NOR gate 31, shown as a dotted box, comprised of three MOS transistors having gate width- to-length ratios as shown. The dotted boxes 32 and 42 and the MOS devices therein correspond to the NOR gates 32 and 42, respectively. Fig. 4 is an enhanced version of the booted clock circuit of Figs. 2 and 3 configured to prevent the flow of interclock current when both controls for clock signals are on and both clock signals are low. If the low voltage level of the two clock signals is substantially identical, the circuit of Figs. 2 and 3 will be adequate. In those instances where that condition does not exist, the circuit of Figs. 4 and 5 will eliminate the interclock current. In Fig. 4, a NOR gate 50, in a cross coupled fashion, receives the output from a NOR gate 52 via an AND gate 54. The signals CLOCK 0 and CLOCK 1 applied to the S and R inputs, respectively, of a flip-flop 60 provide a signal at the Q output for gating the AND gate 54. The NOR gate 52 receives the output from the NOR gate 50, in a cross coupled fashion, via an AND gate 56 under the gating control of the signal at the Q/ output of flip-flop 60. The enhanced circuit operates to pull down the gate of the boot circuit of the clock signal which has just ended, if the other clock is enabled for booting next. If the second clock boot is not enabled, the enhanced circuit has no effect and the first boot circuit is turned off by the second clock, according to the operation of the circuit of Figs. 2 and 3. Referring now specifically to Fig. 5, the flip-flop circuit 60 is shown implemented with cross- coupled MOS devices having gate inputs labeled S and R and outputs labeled Q and Q/. The flip-flop circuit 60 is implemented using MOS technology with the gate ratios shown in the drawing. The NOR gate 50 and AND gate 54, logic combination of Fig. 4, translate into the circuit hardware combination of the three MOS devices shown in the dotted box 50 and the two MOS devices shown within the dotted box 54. In a like manner the NOR gates, 42 and 52, and the AND gate 56 translate into the circuit combination of the MOS devices shown within the respective dotted boxes. Referring now to the timing waveforms of Fig. 6, in conjunction with the circuit shown in Figs. 2 and 3, for the purpose of running through an operating cycle of the circuit. Each waveform label corresponds to a like labeled physical point on the circuit. The action lines, beginning with a circle and ending with an arrow correspond to cause and effect, i.e., an event occurs at the circled point in time and that event causes a second or more events to occur at a latter point in time, indicated by the arrowed end of the line. Hatched portions of a waveform correspond to "Don't Care" states wherein the event may occur at any time during the hatched portion without affecting the circuit operation. As a starting point for this example both CONTROL FOR CLOCK 0 and CONTROL FOR CLOCK 1 are in their clock blocking state, that is, at a high voltage level. Then during CLOCK 1 the CONTROL FOR CLOCK 0 input is driven low, as indicated by action line 1, thereby enabling the NOR gate 31 and driving the node A high, upon the transition of the signal CLOCK 1 from a high to a low, as indicated by action line 2. In turn, when the node A is high the node B follows and the output of NOR gate 42, node E, goes low (action line 3). When CLOCK 0 goes high it further boosts the potential on node B, (action line 4). Thus, by a booting action, the OUTPUT goes high, to a level corresponding to the.full amplitude of the clock signals. When the CLOCK 0 goes negative (action line 5) node B reduces to its previous voltage level and the OUTPUT drops to. a low level. When the next CLOCK 1 pulse goes high (action line 6) node A drops to a low level and node E rises to the high level. The signal CONTROL FOR CLOCK 0 rises from the low level to the high level. The remaining cycles repeat the operation for the second channel containing nodes C and D. Referring now to the Fig. 6 and Fig. 7 waveforms in conjunction with the circuit shown in Figs. 4 and 5. In Fig. 7 when the CLOCK 0 signal applied to the flip-flop 60 goes from a low to a high level the Q/ output goes from high to low and in turn the Q output goes from low to high. When the signal CLOCK 1 goes from a low to a high level the signal Q goes from high to- low which in turn causes the signal Q/ to go from a low level to a high level. The Q and Q/ signals are input signals for the AND gates 54 and 56, respectively. These AND gates are connected as shown in Fig. 5, to the nodal points A and C and affect the operation of the circuit by causing the high level to low level transition to occur sooner than in the preceding circuit embodiment. This operation is shown in Fig. 6 by the action lines 8, 9 and 10 and the dotted sections of the waveforms appearing at node C and at node D. This operation assures that when nodes A and B are rising to a high level nodes C and D are dropping to a low level and vice versa. Referring now to the third embodiment of the two-clock circuit shown in Fig. 8, the control signals CONTROL FOR CLOCK 0 and CONTROL FOR CLOCK ■ 1, applied as inputs to a NOR gate 90 and to MOS devices 88 and 92, respectively, are not barred as was the case for the preceding embodiments. The signal CLOCK 0 is applied to the source of a MOS device 70, the 'gate of a MOS device 82, and to the gate of MOS device 92 via an inverter 86. The signal CLOCK 1 is applied to the gate of a MOS device 78, the source of a MOS device 76, and to the gate of the MOS device 88, via the inverter 84. MOS devices 72 and 74 are connected between the OUTPUT terminal and circuit ground. The output of NOR gate 90 is connected to the gate of MOS device 74 and an input to a NOR gate 80. The NOR gate 80 has two other inputs, one connected to the nodal point C and the other connected to the nodal point D' . The output of NOR gate 80 is coupled to the gate of MOS device 72. The nodal point C is also connected to the MOS devices 78 and 88 and to the gate of MOS device 70. The nodal point D' is also connected to the MOS devices 82, 92 and to the gate of MOS device 76. Referring to Fig. 9, the two NOR gates 80 and 90, and the two inverters, 84 and 86, are shown translated into the circuit combination of MOS devices shown within the correspondingly labeled dotted boxes. The waveforms of Fig. 10, taken at like labeled physical points on the circuit embodiment of Figs. 8 and 9, illustrate..the various signal timings. Considering Figs. 8, 9 and 10 together, the signal CLOCK 0, (action line 12), in moving from a low level to a high level causes the potential on node A' to drop. With the signals CONTROL FOR CLOCK 0 and CONTROL FOR CLOCK 1 both low, no further transitions occur. When the signal CLOCK 0 goes from high to low, (action line 13), the potential on node A' rises but no further transitions occur. When the signal CLOCK 1 rises it activates the signal CONTROL FOR CLOCK 0 to a high level and drops the potential on node B' to a low level. The rising of the CONTROL FOR CLOCK 0 signal (action line 15), causes node E' to go low which in turn (action line 16), causes node F' to rise. When the signal CLOCK 1 goes toward the low level (action - line 17) the potential on node B' starts to rise, in turn drawing node C along (action line 18). When the signal CLOCK 0 goes towards the high level (action line 19) the potential at node C* is boosted higher causing the signal at the OUTPUT to rise to the full potential of the clock signals. The remaining cycles of the circuit are obvious from an inspection of the waveforms in conjunction with the circuit diagrams.

Claims: CLAIMS 1. A clock signal circuit for selecting clock signals for output on a clock output line, characterized by first and second clock input means adapted to receive non-overlapping clock signals and connected to said clock output line by respective first and second MOS devices (36, 40; 70, 76); third and fourth MOS devices (34, 38; 88, 92) coupled to said first and second MOS devices (36, 40; 70, 76), respectively; and logic means (31, 32; 80, 84, 86, 90) connected to said third and fourth MOS devices (34, 38; 88, 92) and responsive to clock signal control signals and to said clock signals, whereby selected booted clock signals are provided on said clock output line. 2. A clock signal circuit according to claim 1, characterized by output control means (42, 44) connected to said logic means (31, 32) and to said clock output line and adapted to connect said clock output line to a reference potential in the absence of a booted clock signal on said output means. 3. A clock signal circuit according to claim 2 , characterized in that said logic means includes first and second logic devices (31, 32); ..n that said first, second, third and fourth MOS devices include respectively first, second, third and fourth MOS transistors (36, 40, 34, 38), the third and fourth MOS transistors (34, 38) having their gates connected to a supply voltage and their source-drain paths connected between said first logic device (31) and the gate electrode of said first MOS transistor (36), and between said second logic device (32) and the gate electrode of said second MOS transistor (40), respectively. 4. A clock signal circuit according to claim 3, characterized in that said clock signals include a first clock signal (CLOCK 0) and a second clock signal (CLOCK 1), the clock pulses of said first clock signal (CLOCK 0) being non-overlapping with the clock pulses of said second clock signal (CLOCK 1), and in that said first logic device includes a first NOR gate (31) adapted to receive as inputs a first control signal and said second clock signal (CLOCK 1) and said second logic device includes a second NOR gate (32) adapted to receive as inputs a second control signal and said first clock signal (CLOCK 0). 5. A clock signal circuit according to claim 4, characterized in that said output control means includes a fifth MOS transistor (44) and a third NOR gate (42), said" fifth MOS transistor (44) having its source-drain path connected between said output line and said reference potential, and said third NOR gate (42) being adapted to receive as inputs the outputs of said first and second NOR gates (31, 32), and having an output connected to the gate electrode of said fifth MOS transistor (44). 6. A clock signal circuit according to claim 5, characterized by gating means (54, 56) adapted to cross-couple the output from said first and second NOR gates (50,' 52) to the inputs to said second, and first NOR gates (52, 50), respectively and by a bistable circuit (60) receiving as inputs the first and second clock signals (CLOCK 0, CLOCK 1), and having first and second outputs connected to said gating means (54, 56), thereby ensuring non- overlapping actuation of said first and second MOS transistors (36, 40). 7. A clock signal circuit according to claim 6, characterized in that said gating means includes first and second AND gates (54, 56) said first AND gate (54) receiving as inputs the output of said second NOR gate (52) and a first output of said bistable circuit (60) and having an output connected to an input of said first NOR gate (50), and said second AND gate (56) receiving as inputs the output of said first NOR gate (50) and a second output of said bistable circuit (60) and having an output connected to an input of said second NOR gate (52).

Inventors: BOATES ROGER WILLARD, KERBER WILLIAM OSWALD, SANWO IKUO JIMMY, BOATES, ROGER, WILLARD, KERBER, WILLIAM, OSWALD, SANWO, IKUO, JIMMY
Applicants: NCR CO, NCR CORPORATION
Application year: 1986
Main classification: H03K17
IPC codes: H03K17