CHARGED PARTICLE BEAM LITHOGRAPHY SYSTEM

Abstract: A charged particle beam lithography system has a high-throughput and inexpensive system configuration. The system configuration is constituted by a plurality of charged particle optical systems (17, 18, 19) each adapted to focus and deflect a beam of charged particles and irradiate the beam onto a specimen (10) so that the beam draws a desired pattern on the specimen, a plurality of deflection distortion correcting circuits (14, 15, 16) each associated with each of the charged particle optical systems for correcting a deflection distortion of each charged particle optical system, and a common pattern data control circuit (1, 3, 4) for supplying data of a pattern to be drawn to each of the plurality of deflection distortion correcting circuits.

Description: This invention relates to a charged particle beam lithography system as described in the first part of claim 1 for use in a lithography process for manufacture of semiconductor devices and more particularly to a charged particle beam lithography system having a system configuration suitable for achieving cost reduction and high throughput. Such a charged particle beam litography system is known from EP-A-0.064.404 which will be discussed later. The charged particle beam lithography system may be classified into two types of which one uses an electron beam and the other uses an ion beam, and will conveniently be described herein by way of example of the former type. Lithography techniques can not well comply with the recent trend toward high-density, fine semiconductor devices, without resort to an electron beam direct lithography in which an electron beam is finely focused on a wafer coated with resist so as to draw a pattern directly on the wafer. The electron beam direct lithography can fully fulfil itself in the formation of fine patterns but disadvantageously, it has a small throughput and can not therefore be practiced in the device production line on mass production basis. In order to increase the working speed of the electron beam lithography system, many advanced elemental techniques have been developed, including an expedient for speed-up of the control circuit system described in, for example, "a high speed, high precision electron beam lithography system" by K. Nakamura, et al., J. Vac. Sci, Technol., B3(1), p.94, Jan/Feb, 1985, and an approach to a continuous stage movement for variable shaped beam electron optics described in, for example, "An electron beam lithography system for submicron VHSIC device fabrication" by H. J. King, et al., J. Vac. Sci. Technol., B3(1), p. 106 Jan/Feb, 1985. However, even with the best combination of these elemental techniques, of the conventional system configuration in which one control circuit system controls one channel of an electron beam system is sticked to, then the throughout per channel will be technically limited and estimated to be 20 and 30 sheets/hour at the most for a wafer of 10,16 to 12,70 cm (4 to 5 inches). Further, the lithography system is very costly in terms of one channel and can not be manufactured commercially with profitness. The already mentioned document EP-A-0 066 404 describes a charged particle beam lithography system comprising a plurality of charged particle optical systems, a deflection distortion correcting system including at least one deflection distortion correcting circuit for correction deflection distortion of the charged particle optical systems, a pattern data memory for storing data of a pattern to be drawn which is supplied to said deflection distortion correcting system and a common pattern data control circuit for supplying data of a pattern to be drawn to said pattern data memory. In this document all the channels are used for drawing the same pattern in parallel but it does not permit to draw different patterns at the same time. An object of this invention is to provide a charged particle beam lithography system which can eliminate the drawbacks of the conventional lithography system by having a system configuration which can permit the charged particle beam lithography to be performed at high throughput and low cost without impairing the fine working faculty of the charged particle beam lithographic technique. To accomplish the above object, a charged particle beam lithography system comprises all the features according to claim 1. The system comprises a plurality of charged particle optical systems each adapted to focus and deflect a beam of charged particle and irradiate the beam onto a specimen so that the beam draws a desired pattern on the specimen, a plurality of deflection distortion correcting circuits each associated with each of the charged particle optical systems for correcting a deflection distortion of each charged particle optical system, and a common pattern data control circuit for supplying data of a pattern to be drawn to each of the plurality of deflection distortion correcting circuits. The pattern data control circuit comprises a plurality of pattern data memories provided in correspondence to the plurality of charged particle optical systems so that the charged particle optical systems can draw different patterns. The invention is illustrated by way of example, in the accompanying drawings, in which: Fig. 1 is a schematic block diagram showing a system configuration of an electron beam lithography system; Fig. 2 is a block diagram showing an electron beam lithography system according to the invention; and Fig. 3 is a block diagram showing another electron beam lithography system not falling within the scope of the claims. The invention will now be described by way of example with reference to the accompanying drawings. In principle, an electron beam lithography system according to the invention is systemized as will be explained below with reference to Fig. 1. More particularly, a control computer 1 receives pattern data from a magnetic tape 2 and writes the data into a buffer memory 3 after the pattern data has been divided into pieces of drawing data by means of a pattern generator 4. The drawing data is supplied to an electron optical system 6 through a deflection distortion correcting circuit 5 and the electron optical system 6 draws a pattern in accordance with the drawing data on a wafer 10 located within a specimen chamber 7. The deflection distortion correcting circuit 5 corrects a deflection distortion for the electron beam in accordance with the data from the computer 1. The computer 1 also controls a mark detection circuit 8 which detects and processes a signal representative of a reflected electron beam sensed by a sensor 11 so as to control the position of the electron beam and controls a stage controller g which drives a stage 12 carrying the wafer 10. Fig.2 illustrates, in block form, the embodiment of a system configuration according to the present claimed invention. This system configuration is suitable for electron beam lithography for devices such as custom LSI's which abound in variety but are manufactured on relatively small output basis. Pattern data is first divided by a pattern generator 4 into pieces of drawing data representative of an irradiation unit figure which depends on a field, a subfield and a beam shape, these factors being determined by the electron optical system. These pieces of drawing data are in turn stored in buffer memories 20, 21 and 22. It will be appreciated that the buffer memories 20, 21 and 22 are provided in correspondence to respective electron optical systems 17, 18 and 19. The respective buffer memories deliver the drawing data to the respective electron optical systems 17 to 19 through the deflection distortion circuits 14 to 16. With this arrangement, when the buffer memories 20, 21 and 22 have been stored with different types of data for different LSI's, the individual electron optical systems 17, 18 and 19 can draw different patterns to permit simultaneous lithography for a variety of patterns. These deflection distortion correcting circuits 14 to 16 are operable to correct deflection distortions preset for individual electron optical systems, so that a pattern can be drawn on a wafer loaded in each electron optical system. The distortion correction must be different for the individual optical systems because even when all the electron optical systems are constructed under quite the same design, the deflection distortion for the electron beam travelling in the optical system slightly differs from system to system. For simplicity of illustration, three channels of electron optical systems for pattern drawing are shown herein but the number of channels is in no way limited to three. It should be understood that the system configuration of the electron beam lithography system described so far can obviously also be applied to a lithography system, which can be used as a doping apparatus, based on an ion beam. Fig. 3 illustrates, in block form, a system configuration which is different from the claimed system, but which is also advantageous. This system configuration which is not falling within the scope of the claims is suitable for electron beam lithography for devices such as memories required to be manufactured on mass production basis. In this embodiment, one channel comprised of a control computer 1, a buffer memory 3 for storage of pattern data and a pattern generator 4 performs simultaneous control of a plurality of electron optical systems 17 to 19 respectively associated with deflection distortion correcting circuits 14 to 16. In operation, data of a pattern to be drawn supplied from the control computer 1 is stored in the buffer memory 3. Upon issuance of an instruction for commencement of lithography, the pattern data is divided by the pattern generator 4 into pieces of drawing data representative of an irradiation unit figure. The drawing data is delivered to the electron optical systems 17 to 19 through the deflection distortion correcting circuits 14 to 16. Since in the system shown in Fig.3 which is not falling within the scope of claim 1 lithography is performed in accordance with the data stored in the buffer memory 3, all the wafers are simultaneously drawn with the same pattern. The resulting effects may be estimated as below. Assuming that a single electron optical system has a throughput of 30 sheets/hour, the throughput of the lithography system is as large as (30 x n) sheets/hour in total when n channels of the electron optical systems are connected in common. Considering the cost of the overall lithography system, one control circuit system ranging from the control computer 1 to the pattern generator 4 is almost identical in cost with one channel comprised of each of the deflection distortion correcting circuits 14 to 16 and each of the electron optical systems 17 to 19 and, given the same throughput, the cost of the lithography system according to this embodiment can therefore be reduced to approximately half that of the conventional lithography system when the number n of electron optical systems is large, amounting to 5, for example. As described above, in a charged particle beam lithography system according to the present invention, a control circuit system controls a plurality of charged particle optical systems to ensure that the throughput can be improved and at the same time the cost of the lithography system can be reduced. To be specific, when the control circuit system controls n channels of charged particle optical systems, the overall lithography system can have a throughput which is n times as large as that of one channel and the cost required for each channel of charged particle optical system associated with the common control circuit system can be approximately halved as compared to the conventional system configuration, in which one control circuit system controls one channel of a charged particle optical system. This permits charged particle beam lithography to be practiced on actual production line in device factories.

Claims: A charged particle beam lithography system comprising (a) a plurality of charged particle optical systems (17, 18, 19), each adapted to focus and deflect a beam of charged particles and irradiate said beam onto a specimen so that said beam draws a desired pattern on said specimen; (b) a deflection distortion correcting system including at least one deflection distortion correcting circuit (14, 15, 16) for correcting deflection distortion of the charged particle optical systems; (c) a pattern data memory system for storing data of a pattern to be drawn which is supplied to said deflection distortion correcting system; and (d) a common pattern generator (4) for supplying data of a pattern to be drawn to said pattern data memory system, characterized in that; (e) a deflection distortion correcting circuit (14, 15, 16) is associated with each of said charged particle optical systems, respectively, each for correcting a deflection distortion of the associated charged particle optical system; (f) said pattern data memory system includes a plurality of buffer memories (20, 21, 22) associated with said deflection distortion correcting circuits, respectively, each for storing data of a pattern to be drawn which is supplied to the associated deflection distortion correcting circuit; and (g) said common pattern generator (4) is capable of supplying data of different patterns to said pattern data memories so that said buffer memories store data of patterns different from each other whereby said charged particle optical systems are capable of drawing the different patterns at the same time. A charged particle beam lithography system according to Claim 1, wherein said charged particle beam is an electron beam. A charged particle beam lithography system according to Claim 1, wherein said charged particle beam is an ion beam. A charged particle beam lithography system according to Claim 1, wherein said pattern data control circuit comprises a single pattern data memory (3) and a pattern generator (4). A charged particle beam lithography system according to Claim 1, wherein said plurality of charged particle beam optical systems are respectively associated with separate pattern data memories (20, 21, 22).

Inventors: KOMODA, TSUTOMU, OKUMURA, MASAHIDE, OOYAMA, MITSUO, SAITOU, NORIO
Applicants: HITACHI, LTD.
Application year: 1986
Main classification: H01J37
IPC codes: H01J37, H01L21