OSCILLATING CIRCUIT

Abstract: An oscillating circuit using a phase locked loop which includes a voltage controlled oscillator (6), a phase compara­ tor (3), a low pass filter (4) and a phase extractor (8) has a small circuit scale. Every repeat period of a reference pulse signal being provided to one input terminal of the phase comparator (3) and having a frequency of I/N times of an oscillating frequency of the voltage controlled oscillator, one of leading edges of the output pulses of the voltage controlled oscillator (6) near a leading edge of the reference pulse signal is selectively extracting by the phase extractor (8). The extracted leading edge of the output pulse of the voltage controlled oscillator (6) is provided to another input terminal of the phase comparator (3) and phase-compared with the leading edge of the reference pulse signal by the phase comparator (3). A phase error signal generated from the phase comparator (3) is supplied through the low pass filter (4) to the voltage controlled oscillator (6) as a control voltage thereof in order to stable the oscillating frequency.

Description: BACKGROUND OF THE INVENTION This invention relates to an oscillating circuit, especially an oscillating circuit which is suitable to generate an oscillating output having a stable oscillating frequency phase-locked to a reference signal or a constant frequency. In an apparatus dealing with a video signal, it is necessary to use high-frequency pulse signals having predetermined phases to a video signal period, for example, a horizontal scanning period. The high-frequency pulse signals are used as a sampling pulse or a clock pulse of an apparatus for converting the video signal to a digital signal, a delay circuit including a charge coupled device (CCD) for the video signal, so on. In the prior art, a phase locked loop (hereinafter PLL) having a voltage controlled oscillator (hereinafter, VCO) has been popularly used. Basically in this loop, an output of the VCO is divided, the divided output is phase-compared with a reference signal, and the VCO is controlled by an error signal thereof, so that a stable signal having higher frequency than the frequency of the reference signal could be obtained. Generally in the video apparatus, as a frequency of the reference signal, a horizontal scanning frequency (f H ) is used and as an oscillating frequency of the VCO, a frequency equal or lower than 910 times of f H is used. Since f H of the NTSC color television system is 15,734.246 Hz, 910 times of it becomes about 14.3 MHz. As it is possible for digital circuit elements in the market to operate adequately at such a frequency, the above PLL circuit has been used. In the above art, however, since it is necessary to use a divider which divide the output of the VCO into the frequency of the reference signal, there are some problems. That is, the circuit scale becomes large and a noise generated at the VCO is superimposed to the video signal. The European patent application EP-A-0 054 322 discloses a pulse oscillating circuit containing a phase comparator comparing a reference pulse with the voltage circuit oscillator output to generate a control signal which is fed to a voltage controlled oscillator. Both the trailing edge and the leading edge of the reference pulse is used for the phase correction. SUMMARY OF THE INVENTION It is an object of the present invention to provide an oscillating circuit which does not include a divider. It is another object of the invention to provide a PLL type oscillator having a small circuit scale. The objects of the present invention are reached with a circuit as defined in the claims. According to the present invention, an oscillating circuit comprises a voltage controlled oscillating means which oscillates at a frequency being N times of a frequency of a reference signal, means for selectively extracting one of predetermined phases of the oscillating output with the predetermined phase of the reference signal, and a low pass filter (LPF) for passing the output of the phase comparing means, wherein the output of the LPF is used as a frequency control signal of the voltage controlled oscillating means. Further, according to the present invention, as the extracting means and the comparing means, a digital circuit that includes three D-type flip flops (DFFs) or another digital circuit that includes two T-type flip flops (TFFs) and a DFF is provided. In the former circuit, input terminals D of two DFFs receive the reference signal and clock terminals CK of the two DFFs receive the oscillating output of the voltage controlled oscillating means and an inverted pulse of the oscillating output thereof, respectively. Q outputs of the two DFFs are provided to a clock terminal CK and an input terminal D of the third DFF, respectively. Q output of the third DFF is supplied to the LPF to generate the frequency control signal. Also, in the latter circuit, clear terminals CLR of the two TFFs receive an inverted signal of the reference signal and clock terminals CK of the Two TFFs receive an inverted pulse of the oscillating output and the oscillating output, respectively. Q outputs of the two TFFs are provided to a clock terminal CK and an input terminal of the DFF, respectively. Q output of the DFF is supplied to the LPF to generate the frequency control signal. As the predetermined phases of the oscillating output, for example, leading edges or trailing edges of the oscillating output are used. Also, as predetermined phase of the reference signal, a leading edge or a trailing edge every repeat period of the reference signal is used. In this technical area, the integer N is set about several hundreds or several tens. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram of an embodiment of an oscillating circuit of the present invention, Figs. 2A to 2C illustrate waveforms of main parts of the block diagram shown in Fig. 1, Fig. 3 shows a circuit diagram of an example of a voltage controlled oscillator 6 of the embodiment shown in Fig. 1, Fig. 4 shows a block diagram of an embodiment of a phase extractor 8 shown in Fig. 1, Figs. 5A to 5D illustrate waveforms of main parts of the block diagram shown in Fig. 4, Fig. 6 shows a block diagram of an embodiment of the phase extractor 8 and a phase comparator 3 shown in Fig. 1, Figs. 7A to 7G illustrate waveforms of main parts of the block diagram shown in Fig. 6, Fig. 8 shows a circuit diagram of another embodiment of the phase comparator 3 and the phase extractor 8 shown in Fig. 1, Fig. 9 shows a block diagram of another embodiment of the phase comparator 3 and the phase extractor 8 shown in Fig. 1, Figs. 10A to 10E illustrate waveforms of main parts of the block diagram shown in Fig. 9, Fig. 11 shows a block diagram of another embodiment of the oscillating circuit of the present invention, and Figs. 12A to 12I illustrate waveforms of mainparts of the block diagram shown in Fig. 11. DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 shows a block diagram for explaining an essence of the present invention. Referring to Fig. 1, a reference pulse signal 1 and a feedback signal 2 are compared at a phase comparator 3. An output signal of the phase comparator 3 is filtered by a lowpass filter (LPF) 4. A voltage controlled oscillator (VCO) 6 is controlled by a frequency control voltage 5 supplied from the LPF4. In the present invention, in order to generate the feedback signal 2, a phase extractor 8 is used in place of a divider of the prior art. The phase extractor 8 extracts one of leading edges of the output signal 7 of the VCO6, which generates near to a leading edge of the reference pulse signal 1 every repeat period of the reference pulse signal. Fig. 2A illustrates a waveform of the reference pulse signal 1. T designates the repeat period of the reference pulse signal 1. Fig. 2B illustrates the output signal 7 of the VCO6. Every repeat period of the leading edge a of the reference pulse signal 1, the leading edge b of the output signal 7 of the VCO6 is extracted, so that the feedback signal 2 shown in Fig. 2C having a phase information of the pulse edge b is generated. The phase comparator 3 compares the reference pulse signal 1 with the feedback signal 2 and provides the output signal, which has a high level in the case shown in the left side of Fig. 2C and a low level in the case shown in the right side of Fig. 2C. Here, in order to stabilize the oscillating frequency of the VCO6, it is necessary to maintain an interval between the leading edge b shown in the left side and the leading edge b shown in the right side a predetermined cycle number of the output signal 7. Namely, in order to stabilize the oscillating frequency of the VCO6 into Nfo (N: an integer, fo: a repeat frequency of the reference pulse signal 1), the leading edge b shown in the right side must become the Nth pulse edge in the case that the leading edge b shown in the left side is numbered zero-th and the leading edges, each of which varies from a low level to a high level and positions at the right side of the zero-th leading edge, are sequentially numbered from the first. The above condition will be satisfied like below. As the reference pulse signal 1, a signal having frequency stability generated from a crystal oscillator is used. For example, a horizontal scanning frequency pulse transmitted from a broadcasting station or the same kind pulse generated from a television camera is used. The frequency variation of these pulses is generally stabilized ±10 to 20 ppm to the reference value thereof. Further, as the VCO6 in Fig. 1, a crystal oscillating type VCO using a crystal oscillator 9 shown in Fig. 3 is used. Referring to Fig. 3, the numerals 10, 11, 12 and 13 denote an inverter, a resistance, a condenser and a varactor diode, respectively. The VCO shown in Fig. 3 is well known in this technical area. When the value of the frequency control voltage 5 becomes bigger, the capacitance of the varactor diode 13 becomes lower and the output signal 7 of the VCO becomes higher. The frequency variation range of the VCO is designed to be Nfo ±60 ppm. As a result, the maximum deviation of the oscillating frequency of the VCO6 becomes lower than ±100 ppm. Namely, in the case that the frequency of the reference pulse signal 1 is set the horizontal scanning frequency f H and the frequency of the VCO is set 910 x f H , that is, about 14.3 MHz in the NTSC television system, the pulse number of the VCO per one period of the reference pulse signal becomes 910 ±0.091. Therefore, the above condition is satisfied. Fig. 4 shows a block diagram of an embodiment of the phase extractor 8. Figs. 5A to 5D illustrate waveforms of main parts thereof. Referring to Fig. 4, the numerals 15 and 16 designate monostable multivibrators (MMV), and the numeral 18 denotes a D-type flip-flop (DFF). A pulse 17 shown in Fig. 5C is generated by the MMV 16. The pulse 17 has a pulse width, which is narrower than one period of the output signal 7 and contains a timing of the leading edge of the reference pulse signal 7. When the pulse 17 is provided to the input terminal D of the DFF 18 and the output signal 7 is supplied to the clock terminal CK, the DFF 18 produces a pulse 2 having a phase coincident with the leading edge of the reference pulse signal 7 at the output terminal Q. Since the pulse width of the pulse 17 is set narrower than one period of the output signal 7, only one leading edge is extracted every repeat period of the reference pulse signal. In a transient state just after switching on a power supply, there is possibility that the leading edge of the output signal 7 can not be detected or the leading edge of the predetermined number ±1 is detected. However, concerning the former case, if a digital type phase comparator is used as the phase comparator 3, it is possible to generate such a value of the control voltage 5 as to make the oscillating frequency higher in the case of absence of the feedback signal 2. Also, it parameters of the VCO6, for example, the capacitance of the condenser 12, is determined so that the output signal 7 of the VCO6 becomes the predetermined frequency nearly at a center value between the maximum value and the minimum value of the control voltage 5, there is no possibility that the state of being no pulse at the output terminal Q of the DFF 18 is held. Further, concerning the latter case, since the phase deviation of the output signal 7 every repeat period of the reference pulse signal 1 is very little, the predetermined numbered leading edge of the output signal 7 is selectively extracted in a stationary state. In the embodiment shown in Fig. 4, it is necessary to use the MMV 15 and the MMV 16, the phase of the generated pulse of which is stable to an ambient condition, for example, a variation of the supply voltage or the ambient temperature. Next, another embodiment that is not necessary to use such a high-stable MMV will be explained in accordance with Fig. 6 and Figs. 7A to 7E. Referring to Fig. 6, the numerals 19, 20 and 24 denote DFFs. The reference pulse signal 1 is provided to the input terminals D of the DFFs 19 and 20, the output signal of the VCO6 is provided to the clock terminal CK of the DFF 19 and an inverted pulse from an inverter 21 is provided to the clock terminal CK of the DFF 20. In this case, in response to the phase relation between the leading edge a of the reference pulse signal 1 and the leading edge b of the output signal 7, the phase relation between the Q output 23 of the DFF 19 and the Q output 22 of the DFF 20 varies. Figs. 7C and 7D illustrate the Q outputs 22 and 23, respectively. The Q output 22 is supplied to the input terminal D of the DFF 24 and the Q output 23 is supplied to the clock terminal CK of the DFF 24. As a result, the Q output 25 of the DFF 24 which is a phase error signal becomes low level in the case that the leading edge b is preceding to the leading edge a, which is shown at the left side of Figs. 7A and 7B, and the Q output 25 of the DFF 24 becomes high level in the case that the leading edge b is delaying from the leading edge a, which is shown at the right side thereof. Fig. 7E illustrates the waveform of the Q output 25. When the Q output 25 is provided to the LPF4, the control voltage 5 decreases in the former case and increases in the latter case. Therefore, in response to the control voltage 5, the VCO6 generates the output signal 7 having the predetermined frequency, so that it becomes possible that the output signal 7 is phase-locked to the reference pulse signal 1. For example, if the output signal 7 of the VCO6 has the predetermined relation to the frequency of the reference pulse signal 1 at the 70% level of the maximum value of the control voltage 5, the low level period of the Q output 25 and the high level period becomes in the ratio 3:7. Since the phase deviation of the output signal 7 to the reference pulse signal 1 is very little, the leading edge b approximately coincides with the leading edge a. As being apparent from the above explanation, according to the embodiment shown in Fig. 6, the leading edge b of the output signal 7 is effectively extracted and phase-compared with the leading edge a of the reference pulse signal 1 every repeat period of the reference pulse signal so as to get the Q output 25 as the phase error signal. Fig. 8 shows another embodiment of the present invention, where in place of the DFF 24 shown in Fig. 6 a circuit having inverters 26 and 27, a NAND gate 28, an AND gate 29, P-channel MOS transistor 30 and N-channel MOS transistor 31 is used in order to a phase error signal 25'. Figs. 7F and 7G illustrate waveforms of the output 32 of the NAND gate 28 and the output 33 of the AND gate 29, respectively. The P-channel MOS transistor 30 conducts at the low level of the output 32 so as to transmit a high level voltage 34 as the phase error signal 25', and shuts at the high level of the output 32. In contrast, the N-channel MOS transistor 31 conducts at the high level of the output 33 so as to transmit a low level voltage, for example, an earth level in Fig. 8, and shuts at the low level of the output 33. Therefore, when the phase error signal is provided to the LPF 4 shown in Fig. 1, it is possible to get the same control voltage 5 as the embodiment of Fig. 6. Fig. 9 shows another embodiment of the present invention, where in place of the DFFs 19 and 20 shown in Fig. 6 known T-type flip flops (TFFs) 35 and 36 are used. Referring to the TFFs 35 and 36, round marks at the CK terminals means that the TFFs 35 and 36 operate at tailing edges of the input signals, and round marks at clear terminals (CLR) thereof means that the TFFs 35 and 36 stop at the low level of the reference pulse signal 1. Figs. 10A to 10E illustrate waveforms of main parts of the circuit shown in Fig. 9. The reference pulse signal 1 shown in Fig. 10A is delivered to the CLR terminals. The output signal 7 of the VCO6 and the inverted signal thereof are provided to the CK terminals of the TFFs 36 and 35, respectively. When the leading edge b of the output signal 7 precedes the leading edge a of the reference pulse signal 1 as shown in the left side of Fig. 10B, the Q output 37 of the TFF 35 precedes the Q output 38 of the TFF 36 as shown in the right side of Figs. 10C and 10D. On the contrary, when the leading edge b follows the leading edge a as shown in the right side of Fig. 10B, the Q output 38 of the TFF 36 precedes the Q output 37 of the TFF 35 as shown in the right side of Figs. 10C and 10D. Therefore, as a result, the same phase error signal as the embodiment can be produced at the Q output of the DFF 24, as shown in Fig. 10E. By the way, in the embodiment shown in Fig. 9, the TFFs 35 and 36 generates pulses which are two-divided ones of the output signal 7 of the YCO6. For example, when the frequency of the output signal 7 is 14.3 MHz, the frequency of the two divided pulse is about 7.16 MHz. Therefore, in an apparatus dealing with a NTSC television signal, the frequency band of which is about 4 MHz, even if the noise from the TFFs 35 and 36 would superimpose the television signal, the noise could be eliminated by a LPF inserted in a video signal circuit, so on. Also, in this technical area, it is easily possible to make a circuit, where only the first pulses of the Q outputs 37 and 38 after the leading edge a of the reference pulse signal 1 are provided to the DFF 24 and another pulses of the Q outputs 37 and 38 are not provided. Further, in place of the inverter 21, it is possible to use a pulse delay circuit having an appropriate delay time, because it is necessary 15 for the clock pulses provided to the CK terminals of the DFF 20 of Figs. 6 and 8 and the TFF 35 of Fig. 8 only to have a difference phase to the output signal 7. Fig. 11 shows another type of embodiment of the present invention, where in place of the output signal 7 a pulse 45 which is produced by dividing the output signal 7 is used as an input pulse of the phase extractor 8. In Fig. 11, the pulse 45 is produced by three-dividing the output signal 7. Figs. 12A to 12I illustrate waveforms of main parts of the circuit shown in Fig. 11. There is one type of a solid state image device, which uses a clock pulse having a frequency of 910/3 times of the horizontal scanning frequency f H , that is, about 4.8 MHz, for example, a solid state image sensor using Solid State Image Device HE98,225 produced by Hitachi Ltd. The embodiment shown in Fig. 11 is suitable to this device. The output signal 7 is divided by a three-divider 39, which produces three phase pulses 411, 412 and 413, the phase deviation of which is one period of the output signal 7 as shown in Figs. 12C, 12D and 12E. Also, the reference pulse signal 1 is divided by a three-divider 40, which produces three phase pulses 421, 422 and 423 shown in Figs. 12F, 12G and 12H, respectively. In this technical area, it is well known to construct the three-dividers 39 and 40 with a digital circuit technic. AND gates 43 and an OR gate 44 produce the pulse 45 shown in Fig. 12I based on the three phase pulses 411, 412 and 413. The pulse 45 is one of the three phase pulses 411, 412 and 413 which is sequentially selected. In this configulation, it is possible to get the leading edge b of the predetermined pulse of the output signal 7 every repeat period of the reference signal. Therefore, when the pulse 45 is used in place of the output signal 7 of the circuits shown in Figs. 4, 6, 8 and 9, it becomes possible to effectively get the leading edge b of the output pulse 7 every repeat period of the reference pulse signal 1 in order to compare it with the leading edge a of the reference pulse signal. In this embodiment, since the three-dividers 39 and 40, the AND gate 43 and the OR gate 44 are shared with the circuit for generating the clock pulse having the frequency of 910/3 times of f H , it becomes possible to reduce a total circuit scale. As it being detailed above, according to the present invention, when the reference pulse signal having the frequency fo is phase-locked

Claims: A pulse oscillating circuit which includes a voltage controlled oscillator (6) generating an output signal having a frequency Nfo, where N is an integer and fo is a repetition frequency of a reference signal (1), means (3) for comparing the phase of the reference signal with a phase of the output signal of the voltage controlled oscillator (6) to generate a phase error signal, and means (4) for producing a control signal for the voltage controlled oscillator (6) based on said phase error signal, characterized by N being at least several tens, and by means (8) for selectively phase-extracting one of predetermined leading or trailing edges of the output signal of the voltage controlled oscillator (6) respectively near a predetermined leading or trailing edge of the reference signal every repeated period of the reference signal, the extracted edge being input to the phase comparator means (3). An oscillating circuit according to claim 1, characterized in that said phase-extracting means (8) includes two monostable multivibrators(15, 16) in series and a D type flip-flop (18), the first one (15) of said monostable multivibrators receiving the reference signal, an output of the second one (16) of said monostable multivibrators being provided to an input terminal D of said D type flip-flop (18) and the output of the voltage controlled oscillator (6) being supplied to a clock terminal of said D type flip-flop. An oscillating circuit according to claim 1, characterized in that said control signal producing means (4) is a low pass filter . An oscillating circuit according to claim 1, characterized in that said phase-extracting means (8) and said phase-comparing means (3) include three D type flip-flops (19, 20, 24), the first D type flip-flop (19) of which receives the reference signal at an input terminal D and the output of the voltage controlled oscillator (6) at a clock terminal, the second D type flip-flop (20) of which receives the reference signal at an input terminal D and a pulse signal having a phase different from the phase of the output of the voltage controlled oscillator (6) at a clock terminal, and the third D type flip-flop (24) of which receives a Q output of said second D type flip-flop (20) at an input terminal D and a Q output of said first D type flip-flop (19) at a clock terminal and generates said phase error signal as a Q output thereof. An oscillating circuit according to claim 4, characterized in that said pulse signal having a phase different from the phase of the output is produced by inverting the output of the voltage controlled oscillator (6). An oscillating circuit according to claim 1, characterized in that said phase-extracting means (8) and said phase-comparing means (3) include two T type flip-flops (35, 36) and a D type flip-flop (24), the first one (36) of said T type flip-flops receiving an inverted signal of the reference signal at a clear terminal and an inverted signal of the output of the voltage controlled oscillator (6) at a clock terminal, the second one (35) of said T type flip-flops receiving an inverted signal of the reference signal at a clear terminal and the output of the voltage controlled oscillator (6) at a clock terminal, and said D type flip-flop (24) receiving a Q output of said second T type flip-flop (35) at an input terminal D and a Q output of said first T type flip-flop (36) at a clock terminal and produces said phase error signal as a Q output thereof.

Inventors: AIZAWA, IWAO
Applicants: HITACHI, LTD.
Application year: 1986
Main classification: H03L7
IPC codes: H03L7, H04N5, H03K3