HIGH-SPEED CMOS BUFFER WITH CONTROLLED SLEW RATE

Abstract: A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a CMOS output buffer and in particular to a high-speed CMOS output buffer with a controlled slew rate. Prior Art Prior art CMOS output buffers exhibit very fast output voltage transitions. In an integrated circuit, this rapid rate of change of the output voltage (dV o /dt) of a CMOS output buffer causes large power supply current surges, cross talk, i.e., undesired energy appearing in one signal path as a result of coupling from other signal paths, ringing, and other undesirable system effects. These effects are magnified in high pin count packages, i.e., packages with more than 100 output pins. Figure 1 shows a prior art CMOS output buffer circuit comprising inverters 1 and 2. The input voltage signal is supplied to input lead V i connected to inverter 1. The output signal of inverter 1 is applied to the gates G1 and G2 of transistors Q1 and Q2, respectively, of inverter 2. Transistor Q1 is a P channel enhancement mode transistor, and transistor Q2 is an N channel enhancement mode transistor. Source S1 of transistor Q1 is connected to the supply voltage V DD . Drain D1 of transistor Q1 is connected to drain D2 of transistor Q2 and both are connected to output node V o of inverter 2. Source S2 of transistor Q2 is connected to system ground V SS . Capacitor C, shown schematically in Figure 1 connected between V o and system ground, represents the load capacitor. Figs. 2a and 2b show typical input and output voltage curves for the output buffer of Fig. 1. The current I D shown in Fig. 2c is the current supplied to load capacitor C. There is a transient current surge during the period while V o is rising. During this switching interval, power is dissipated in the channel resistance of P channel transistor Q1 and energy is supplied to the load capacitor C. Similarly, there is a transient current surge during the period while the voltage V o is falling. During this period the energy stored in the load capacitor C is dissipated in the channel resistance of N channel transistor Q2. If the capacitance of load capacitor C is increased, the rise time and the fall time increase and the peak values A and B of the transient currents also increase in absolute value. As stated above, these transient current surges are undesirable. Attempts have been made to reduce these transient current surges by using conventional negative feedback techniques to reduce the time rate of change of the output voltage dV o /dt, but unacceptable delays are introduced using this approach. Of course, reducing the size of transistors Q1 and Q2 in inverter 1 reduces the transient currents, but this also reduces DC drive to unacceptable levels. Therefore, one of the objects of this invention is to provide a high-speed CMOS output buffer which substantially reduces transient current surges during switching, but which does not reduce the DC output drive of the buffer. In Japanese patent applications JP-A-58-196725 and JP-A-58-196726, both published on November 16, 1983, CMOS output circuits to reduce power supply noise are disclosed. Both of these circuits use inverters consisting of N and P channel transistors. In U.S. patent US-A-4,103,188, issued on July 25, 1978, to Morton, a complementary-symmetry amplifier is disclosed which includes a CMOS inverter having a MOSFET paralleled by a bipolar transistor. In U.S. patent US-A-3,631,528, issued December 28, 1971, to Green, another CMOS-bipolar inverter is disclosed. In Arthur H. Seidman, "Integrated Circuits Applications Handbook", John Wiley & Sons, 1983, pages 107-110, rules are disclosed which enable one to calculate threshold voltages (i.e., the switching voltages) of a CMOS inverter. The functioning and results obtained with the CMOS output buffer of the present invention distinguish from the prior art because there is no description or suggestion in the prior art of operating a high speed CMOS buffer circuit with partial outputs from a plurality of output stages under control of control inverters having predetermined switching threshold voltages. SUMMARY In accordance with this invention a high-speed CMOS output buffer is provided which includes a first CMOS output stage and a CMOS output inverter having a common output lead. In one embodiment the CMOS output stage is controlled by a first control inverter having a first switching threshold voltage. The CMOS output inverter includes a P channel enhancement mode transistor and an N channel enhancement mode transistor whose gates are controlled separately. The gate of the P channel enhancement mode transistor is controlled by a second control inverter having a second selected switching threshold voltage higher than the first switching threshold voltage. The gate of the N channel enhancement mode transistor is controlled by a third control inverter having a third selected switching threshold voltage lower than the first switching threshold voltage. When the same rising voltage signal is applied to the control inverters, the third control inverter goes low first, turning off the N channel transistor. Next, the first control inverter goes low, causing the output signal of the output stage to go high and a first transient surge in the current I D as energy is stored in the load capacitor. Finally, the second control inverter goes low, turning on the P channel transistor and causing a second surge in the current I D as energy is stored in the load capacitor. The surge currents produced by the switching of the output stage and the output inverter are less than the surge current that would be produced by the switching of a single CMOS output buffer having equivalent DC drive. Similarly, when a falling voltage signal is applied to the control inverters, the second control inverter goes high first, turning off the P channel transistor. Next, the first control inverter goes high, causing the output signal of the output stage to go low and causing a third current surge in I D as the load capacitor is partially discharged. Finally, the third control inverter goes high, turning on the N channel transistor and producing a fourth current surge in I D as the remaining load capacitor is discharged. Again, the surge currents produced by the switching of the output stage and output inverter are less than the surge current that would be produced by the switching of a single CMOS output buffer having equivalent drive. BRIEF DESCRIPTION OF THE DRAWING S Fig. 1 shows a prior art CMOS output buffer; Fig. 2a shows a voltage input curve for the buffer of Fig. 1; Fig. 2b shows a voltage output curve for the buffer of Fig. 1 corresponding to the input curve of Fig. 2a; Fig. 2c shows the current I D corresponding to the curves shown in Fig. 2a and Fig. 2b; Figs. 3a, 3b and 3c show a voltage input curve, a corresponding coltage output curve and an I D curve for specific values of component parameters for the circuit shown in Fig. 1; Fig. 4 shows one embodiment of the present invention; Fig. 5a shows a voltage output curve and Fig. 5b shows corresponding to the same input voltage curve shown in Fig. 3a the curve I D for one embodiment of the invention as shown in Fig. 4; (Note that Fig. 3a is repeated to more clearly show the relationship between the curves.) Fig. 6 shows a tri-state embodiment of the present invention; and Fig. 7 shows a truth table for control logic 10. DETAILED DESCRIPTION Figs. 3a, 3b and 3c show the input voltage waveform V i , the output voltage waveform V o and the current waveform I D , respectively, for the prior art output buffer circuit shown in Fig. 1 under the following assumptions: (1) Transistor Q1 represents 11 transistors connected in parallel, each transistor having a channel width of 66 microns, so that the channel width of Q1 is 11 x 66 microns; the channel length of Q1 is 3 microns; (2) Transistor Q2 represents 8 transistors connected in parallel, each transistor having a channel width of 58 microns, so that the channel width of Q2 is 8 x 58 microns; the channel length of Q2 is 2.5 microns; (3) V DD = 5 volts; and (4) The load capacitance is 20 picofarads. Under the above assumptions, the rise time t r is approximately 5 nanoseconds (See Fig. 3b) and the corresponding current surge in I D reaches a peak of approximately 25 milliamps (See Fig. 3c). The fall time tf is approximately 2.8 nanoseconds and the corresponding current surge in I D reaches a peak of 35 milliamps. Fig. 4 shows one embodiment of the CMOS output buffer of the present invention which has the same total output drive as the CMOS buffer circuit shown in Fig. 1 where P channel transistor Q1 and N channel transistor Q2 satisfy assumptions (1) and (2) above. In the CMOS buffer circuit shown in Fig. 4, the current paths of inverter A and output stage B (hereinafter also referred to as "inverter B") are connected in parallel. Inverter A consists of P channel enhancement mode transistor Q1A and N channel enhancement mode transistor Q2A. Transistor Q1A has a channel width of 5x66 microns and a channel length of 3 microns. Transistor Q2A has a channel width of 2x58 microns and a channel length of 2.5 microns. Inverter B consists of P channel enhancement mode transistor Q1B and N channel enhancement mode transistor Q2B. Transistor Q1B has a channel width of 6x66 microns and a channel length of 3 microns. Transistor Q2B has a channel width of 6x58 microns and a channel length of 2.5 microns. The drains of transistors Q1A, Q2A, Q1B and Q2B are all connected to the output node V o . Thus in view of the channel dimensions given above, inverters A and B connected as shown in Fig. 4 have the same DC drive as inverter 1 which satisfies conditions (1) and (2) above. The sources of transistors Q1A and Q1B are connected to the positive power supply V DD which is 5 volts in this embodiment, and the sources of transistors Q2A and Q2B are connected to ground. The input voltage signal V i is applied to the gates of transistors Q1A and Q2A via CMOS inverter E which has a switching threshold voltage V SE of approximately 2.5 volts with V DD at 5 volts. The term switching threshold voltage of a CMOS inverter as used in this specification means the input voltage of the inverter at which both the N channel and P channel transistors in the inverter are saturated. Holt, Electronic Circuits Digital and Analog , John Wiley & Sons (1978) shows in Fig. 8-15 on page 239, a voltage transfer characteristic for a CMOS inverter wherein both transistors are saturated when the input voltage is .5 V DD . Inverter A also has a switching threshold voltage of approximately 2.5 volts. The output voltage signal of inverters A and B appears on output node V o . The gate of N channel enhancement mode transistor Q2B of inverter B is controlled by the output signal of inverter D. Similarly, and the gate of P channel enhancement mode transistor Q1B of inverter B is controlled by the output signal of inverter C. Inverter D is specially constructed to have a switching threshold voltage of 1.1 volts, which is lower than the switching threshold voltage of inverters A and E. Inverter D comprises P channel enhancement mode transistor Q1D and N channel enhancement mode transistor Q2D. The low switching threshold voltage of inverter D is achieved by making the gate width of N channel enhancement mode transistor Q2D larger than the gate width of P channel enhancement mode transistor Q1D. For example, in one embodiment, the gate width of transistor Q1D is 9 microns (and the gate length is 2.5 microns), and the gate width of transistor Q2D is 78 microns (and gate length is 2 microns), which produces an inverter D having a switching threshold voltage of 1.1 volts. Inverter C, which controls the gate of transistor Q1B, is comprised of transistors Q1C and Q2C. Inverter C is specially constructed so that the switching threshold voltage of inverter C is higher than the switching threshold voltage of inverters E and A. This is achieved by making the gate width of P channel enhancement mode transistor Q1C larger than the gate width of N channel enhancement mode transistor Q2C. For example, in one embodiment, the gate width of transistor Q1C is 78 microns (and gate length is 2.5 microns), and the gate width of transistor Q2C is 6 microns (and the gate length is 2 microns), which produces an inverter C having a switching threshold voltage of 3.7 volts with V DD at 5.0 volts. The operation of the CMOS output buffer shown in Fig. 4 may be understood as follows. Assume as initial conditions that the input voltage V i is 0 volts, that the output voltage V o is 0 volts since both Q2A and Q2B are turned on and Q1A and Q1B are turned off, and that the capacitance of the load capacitor, indicated schematically by capacitor C in Fig. 4, is 20 picofarads. Assume also that the voltage input signal V i follows the curve shown in Fig. 3a. As the voltage V i applied to inverters E, C, and D rises, the output signal of inverter D goes low first since inverter D has the lowest switching threshold voltage, namely 1.1 volts. This causes the voltage on the gate of transistor Q2B of inverter B to fall, turning off transistor Q2B. Next, as the voltage V i continues to rise to 2.5 volts, inverter E goes low, causing the voltage on the gates of transistors Q1A and Q2A to fall which turns on transistor Q1A and turns off transistor Q2A. The transient surge of current through transistor Q1A charges load capacitor C and causes the first surge in the I D current shown in Fig. 5b. The peak of this current surge has a value of approximately 13 milliamps. The absolute value of this peak current is only approximately one-half of the absolute value of the peak surge current shown in Fig. 3c. The lower peak value of the transient current surge is due to the smaller dimensions of transistor Q1A as compared to the dimensions of transistor Q1 and Q2 set forth in conjunction with Figures 3b and 3c. As the voltage V i continues to rise and reaches 3.7 volts, inverter C goes low, causing the voltage applied to the gate of P channel enhancement mode transistor Q1B to fall, thus turning on transistor Q1B. As transistor Q1B turns on, there is a second transient surge in I D , namely a surge in current through transistor Q1B which continues to charge load capacitor C. The second current surge has a duration of approximately 8 nanoseconds and a peak value of approximately 3 milliamps as shown in Fig. 5b. The curve representing the output voltage signal V o is shown in Fig. 5a. The rise time of the output voltage signal V o is approximately 8.2 nanoseconds compared with the rise time of 5 nanoseconds for the circuit corresponding to Fig. 3b. As the voltage signal V i begins to fall (as shown in Fig. 3a), inverter C, having the highest switching threshold voltage (3.7 volts), switches first, causing the voltage applied to the gate of transistor Q1B of inverter B to rise, thus shutting off transistor Q1B. As the voltage signal V i continues to fall to 2.5 volts, inverter E switches, causing the voltage applied to the gate of transistors Q1A and Q2A to rise, which turns on transistor Q2A and turns off transistor Q1A. The turning on of transistor Q2A causes the current surge in I D having a peak value of approximately 12 milliamps as shown in Fig. 5b. This current surge dissipates power as the energy stored in the load capacitor C is dissipated in the channel resistance of N channel enhancement mode transistor Q2A of inverter A. As the input voltage V i falls to 1.1 volts, inverter D switches, causing the voltage applied to the gate of transistor Q2B to rise, turning on transistor Q2B and thus causing a fourth surge of I D current. This current surge has a maximum value of approximately 6 milliamps as shown in Fig. 5b. This current surge dissipates power as the energy remaining in the load capacitor C is discharged through the resistance of N channel enhancement mode transistor Q2B of inverter B. While a specific embodiment of the invention is described above, having selected delays, slew rates and DC drives, other embodiments may also be obtained by controlling the size of the transistors shown in Fig. 4. The size of the transistors may be controlled during the creation of the metal mask for the integrated circuit. In effect, the buffer is "programmed" by the metal mask. This can be done after completion of the entire chip design. In general, the lowest dV o /dt will be programmed consistent with the system requirements for each output buffer in the circuit. Fig. 6 shows a tri-state embodiment of the CMOS output buffer of the present invention. The components in Fig. 6 which are the same as the components in Fig. 4 bear the same labels. Inverters E1 and E2 are identical to inverter E. Control logic 10 of the tri-state CMOS output buffer of Fig. 6 includes input leads EN (enable) and V IN , inverters E3 and E4, NOR gate NOR-1 and NAND gate NAND-1. The input signal on lead EN is provided to NOR gate NOR-1 and the complement is provided to NAND-1 via inverter E3. The input voltage signal V i is provided on lead V IN and the complement V i is provided to NOR gate NOR-1 and to NAND gate NAND-1 via inverter E4. Fig. 7 shows a truth table for control logic 10. When the enable signal EN is high (logical 1), the output signal of NOR gate NOR-1 is a logical 0 and the output signal of NAND gate NAND-1 is a logical 1, regardless of the state of the input voltage signal V i . The logical 0 output signal from NOR gate NOR-1 is inverted by inverters E1 and C so that a logical 1 is applied to the gate of P channel enhancement mode transistor Q1A, and to the gate of P channel enhancement mode transistor Q1B, turning transistors Q1A and Q1B off. The logical 1 output signal from NAND gate NAND-1 is inverted by inverters E2 and D so that a logical 0 is applied to the gates of N channel enhancement mode transistor Q2A and to the gate of N channel enhancement mode transistor Q2B turning transistors Q2A and Q2B off. Thus, when the enable signal EN is high (logical 1), all of the transistors in inverter A and B are off. On the other hand, when the enable signal EN is low (logical 0), the output signal of NOR gate NOR-1 and the output signal of NAND gate NAND-1 follow V i , so that the circuit operates as previously explained in conjunction with Fig. 4. The above embodiments are meant to be explanatory and not limiting. Many substitutions and modifications will be obvious to one of average skill in the art in view of the above disclosure.

Claims: A high speed CMOS output buffer with controlled slew rate, the buffer having a first circuit network having an output stage (B), a first (D) and a second (C) control inverter, said output stage (B) being coupled to the outputs of said first (D) and second control inverters (C), said CMOS output buffer being characterized by: a second circuit network having a third control inverter (E) and an output inverter (A) coupled in parallel to said output stage (B), said output inverter (A) coupled to the output of said third control inverter (E); output means (V o ) including a load capacitor coupled to the output of said output stage (B) and output inverter (A); means (V i ) for applying an input signal having rising and falling portions to said first (D), second (C) and third (E) control inverters, so that during the rising portion of said input signal said load capacitor is first charged slowly by said second circuit network and then by said first circuit network and during the falling portion of said input signal, said capacitor is partially discharged slowly by said second circuit network and then fully discharged by said first circuit network, wherein the switching threshold voltage of said third control inverter (E) is less than the switching threshold voltage of said second control inverter (C) and greater than the switching threshold voltage of said first control inverter (D), the values of said threshold voltages of said control inverters causing each of said output inverters to provide in sequence a partial output of the total output to said load capacitor. A CMOS output buffer as in claim 1 wherein said output stage (B) comprises a P channel enhancement mode transistor (Q1B) having a gate, source, and drain, and an N channel enhancement mode transistor (Q2B) having a gate, source and drain, said drain of said P channel transistor (Q1B) being connected to said drain of said N channel transistor (Q2B). A CMOS output buffer as in claim 2 wherein said second control inverter (C) comprises a P channel enhancement mode transistor (Q1C) and having a gate, a source, and a drain, and an N channel enhancement mode transistor (Q2C) having a gate, a source, and a drain, said drain of said P channel transistor (Q1C) being connected to said drain of said N channel transistor (Q2C). A CMOS output buffer as in Claim 3 wherein said first control inverter (D) comprises a P channel transistor (Q1D) having a gate, a source, and a drain, and an N channel transistor (Q2D) having a gate, a source, and a drain, said drain of said P channel transistor (Q1D) being connected to said source of said N channel transistor (Q2D).

Inventors: WALKER, ROBERT M., III, WONG, ANTHONY Y.
Applicants: LSI LOGIC CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H03K17, H03K5, H03K19