DIELECTRICALLY ISOLATED INTEGRATED CIRCUIT DEVICE AND METHOD OF MAKING

Abstract: A method of fabricating dielectrically isolated integrated circuit devices, comprising the following steps: using a semiconductor substrate with upper and lower portions (14, 12), doping said upper portion (14) of said substrate in accordance with types of devices to be formed, said lower portion (12) of said substrate forming a plurality of sub­ collectors. (i)(a) forming a masking layer (20) over said substrate; (i)(b) etching a plurality of holes (30) in said masking layer; and (i)(c) isotropically etching a plurality of active device regions (40) in said substrate through said holes, (ii) growing an oxide layer (50) over portions of said sub­ strate where said devices are to be formed; (iv) forming said devices by selective epitaxial growth in said regions (40).

Description: The invention relates to a novel method of semiconductor device fabrication employing selective epitaxial growth, in which interdevice isolation is formed as an integral part of the process, rather than as a separate formation step. One aspect of this process is that at least one of the active elements of the resultant structure are formed before the isolation layer, and may exist both inside and outside the selective epitaxial growth regions. Interdevice isolation is an important aspect of integrated circuit fabrication, as it is vitally important to prevent the occurence of such phenomena as parasitic capacitances. Formerly, various approaches to such isolation have been employed. In U.S. Patent No. 4,357,622, recessed oxide isolation (ROI) techniques were employed to provide isolation regions surrounding transistors in a complementary NPN/PNP structure. This technique makes achieving a compact structure difficult. In another approach, isolation trenches were etched in a monocrystalline Si substrate, and lined with oxide. In this instance, the oxide layer formation was a separate process step. Further, the trenches did not constitute active elements of the devices, and the active elements of the devices were not formed in the trenches. Rather, the trenches themselves, and the oxide filling, provided the interdevice isolation. As a result, considerable space was wasted on a substrate. An example of this approach may be found in I. Antipov and C. G. Jambotkar, "Post Emitter Polysilicon Trench Isolation," IBM Tech. Disc. Bull., July 1982, pp. 588-589. In this disclosure, trenches were lined with oxide and nitride, and refilled with polysilicon. This resulted in quite a deep structure, which was necessary to prevent the sideways flow of electric charge between adjacent devices on the substrate. U.S. Patent No. 4,159,915 also exemplifies this approach. In the patent, deep isolation regions were formed surrounding individual transistors in a array. Again, a deep structure resulted. Also, the overall structure occupied considerable space on the substrate. A similar process is known from FR-A-2 547 954. In this process, polycrystalline silicon is deposited in a recess in a silicon substrate whose walls are insulated by a silicon nitride layer except for an opening formed in this nitride layer a the bottom of said recess. Then, the polycrystalline silicon is re-epitaxied so as to become monocrystalline silicon by thermal heating from the "nucleus" formed by the underlying silicon in said opening. Other attempts to provide proper interdevice isolation have included trench isolation alone, without oxide lining or ROI. This solution has been difficult to implement. Selective epitaxial growth, in which active elements of devices are formed within etched regions in an oxide layer, the surrounding oxide providing the required isolation, has been used for a number of years. Attempts have been made to apply this technique to vertical transistor structures, which take up less of the available surface area on a substrate, and also to symmetrical transistor structures. Prior attempts to form such structures, not employing selective epitaxial growth, may be found in Reisman et al., "Methods for Making Symmetrical Transistor Structures," IBM Tech. Disc. Bull., Dec. 1982, pp. 3357-3363, and in U.S. Patent No. 4,214,315 (vertical transistor structures). In the patent, deep, separately-formed isolation regions surrounded individual transistors. In the past, selective epitaxial growth has been employed to form all active elements of a device, including a subcollector, within the etched regions in the oxide layer. U.S. Patent No. 4,400,411 shows such a structure. Similar examples of this approaches are known from JP-A-5 933 846 and JP-A-5 933 847. However, autodoping and other problems arise when the subcollectors are selectively epitaxially grown in this manner. The above deficiencies and problems are overcome by the present invention as defined in the appended claims. The invention will be described in detail below with reference to the accompanying drawings, in which: Figs. 1(a)-(j) illustrate a first type of structure employing the method of the invention, and individual formation steps; Fig. 2 shows an array formed of elements according to the structure and method shown in Fig. 1; Figs. 1(a)-1(f) show formation steps for a first type of structure according to the invention. In Fig. 1(a), a monocrystalline silicon substrate 10 has a lower portion 12 which is doped n+ to a concentration in a range from 5x10¹⁹ - 2x 10²⁰/cm³, and an upper portion 14 which is doped in accordance with the type of device to be formed. For example, if an n-channel MOS structure is to be formed, the portion 14 would be doped p, to a concentration of from 10¹⁴ to 3x10¹⁶/cm³. If an NPN bipolar structure is preferred, the portion 14 would be doped n-, to a particular concentration (for example, in a range from 10¹⁵ to 5x10¹⁶/cm³) in accordance with desired device characteristics. Also, the upper portion may be formed as an epitaxial layer, separate from the lower portion 12. The lower portion forms the subcollector region for the device to be formed. In addition, the lower portion 12 could be a buried subcollector in a more highly resistive Si substrate. At this point, it should be noted that, throughout this specification, preferred ranges of dopant concentrations have been set forth. Further, the ordinarily skilled artisan, being familiar with a wide range of doping techniques, would be able to employ the appropriate technique without undue experimentation, given the concentration ranges. An oxide overlayer 20, which may be from 200 nanometers to two micrometers thick, is grown over the upper portion 14 by conventional methods. An emitter oxide opening 30 also is formed anisotropically by known techniques. When a plurality of devices are to be fabricated, as shown in Fig. 2, multiple openings are formed. These openings will be used to direct a reactive ion etching (RIE) step, to be performed later, for ensuring selfalignment of the vertical transistor structure to be formed. Fig. 1(b) shows a crevice 40, etched out of the upper portion 14 down to the lower portion 12 by plasma or wet etching, preferably by isotropic etching in any event. The crevice 40 may extend into the subcollector region 12, as shown in Figures 1(c)-1(j). Generally, the crevice 40 preferably will have the shape shown in Figs. 1(b)-(j) and Fig. 2, that is, a trapezoidal shape, having a flat lower surface. If plasma etching is used, the sides of the crevice 40 may be curved. A rectangular-shaped crevice also may be etched. The device will be formed within the crevice 40 with the subcollector region 12 outdiffusing into the overall structure, as will be described below, the crevice 40 constituting an active device region. The size of this region may vary, depending on the width of the hole 30, and on the size of the epi growth within. Actually, the desired base width will be the overall determinative factor, as the size of the epi growth will depend on the base width chosen. In Fig. 1(c), an oxide layer 50, which may be thermal SiO₂, is grown on the inner surface of the crevice 40. The desired thickness may vary between 20 and 300 nanometers, in accordance with the desired operating characteristics of the device and the degree of isolation required. The oxide layer may be quite thin, thereby enabling a more compact structure than was possible before. Also, more than one layer may be grown, the additional layer or layers being nitride (yielding an oxide/nitride combination) or other appropriate insulator. The layer or layers are effective in preventing parasitic capacitances. RIE then is performed on the oxide layer 50, as shown in Fig. 1(d), through the emitter opening 30 formed in the oxide overlayer 20, to open a self-aligned collector hole 60 in an anisotropic manner in the oxide layer 50. In this manner, the subcollector region 12 makes contact with the other active elements of the overall device. The collector hole 60 formed in this manner should have the same size as the emitter opening 30. After the RIE step, the crevice 40 is refilled using selective epitaxial techniques. As shown in Fig. 1(e), after the collector hole 60 is opened, a collector 70 is outdiffused from the subcollector 12 by enabling expansion of the subcollector material 12 into the crevice 40. At this point, planar diffusion or ion implantation can be added to augment the doant concentration of the collector 70. If this is needed, preferably it would be performed before the selective epitaxy is carried out. Finally, p-type silicon 80 is grown within the crevice to provide a base for the device. In Fig. 1(f), an n+ emitter 90, having a concentration of 5×10¹⁹ - 2×10²⁰/cm³, is formed within the p-type epi structure 80, either through diffusion or through ion implantation. In the overall device, the width of the base region between the collector-base and base-emitter junctions may be from 0.1 - 0.5 micrometers, again depending on desired device characteristics. It should be noted that the procedure described thus far results in the above-mentioned junctions having equal areas -- an important consideration in device fabrication, in addition to the resulting self-aligned structure. The junction areas are defined, respectively, by the emitter opening and the collector opening, which have equal dimensions. Also, it should be noted that the p-type epi material 80 within the crevice 40 may be selectively epitaxially grown in a single step, and the collector simultaneously formed by outdiffusion expansion of the subcollector during the epitaxial growth process. Alternatively, the collector, base, and emitter may be grown in separate steps, by any appropriate technique, such as ion implantation or diffusion. Fig. 1(g) shows the formation of an n+ subcollector reach-through 100 for the device. The reach-through has the same concentration as the subcollector region 12, in order to facilitate contact on the same major surface of the overall device as the remainder of the contact structure, which will be described in greater detail below. Figs. 1(h)-(j) show alternative base contact structures which the inventive device and formation method enable. Because of the dish-like shape of the crevice 40, base contacts may be made on the surface of the wafer, thereby enabling connection of the device to other active elements in an array on the surface, instead of having buried contacts, as was the case previously. In Fig. 1(h), an extrinsic base contact 174 is formed through the oxide layer 20. Also, an emitter contact 172 is formed, as well as a contact 176 for the subcollector reach-through 100. Alternatively, in Fig. 1(i), an overlapping contact 182 connects the region 80 with a p+ region 184 grown at a prior stage by diffusion or ion implantation under the oxide layer 20 and in the upper portion 14 of the substrate 10. Materials such as polysilicon, polycide, or metal silicide may be used for the contacts 172, 174, 176, and 182. In this manner, bases of adjacent devices may be linked within the device, rather than extrinsically. Fig. 1(j) shows an overlapping contact structure in which polysilicon, polycide, or metal silicide 194 is used as the contact medium. The material 194 is grown over the oxide layer 20, and contacts the base region 80. It should be noted that, while the structure shown in Fig. 1(f) is a bipolar structure, the technique described above may be equally applicable to forming a CMOS or complementary NPN-PNP transistor array. An array with an optional CMOS configuration is shown in Fig. 2. A p-type Si film is epitaxially grown on a n+ Si blanket subcollector 202, whereby, after the process is completed, a plurality of n-type regions 208 are formed, using the above-described selective epitaxial process (Figs. 1(a)-(e)) which form the device regions in PMOS devices. The remaining p regions of the original p epitaxial layer are used to fabricate NMOS devices. Thereafter, the original thick oxide layer overlay (oxide layer in Fig. 1(a)) is stripped. The wafers then are cleaned, and then conventional methods are used to fabricate the PMOS and NMOS devices in their appropriate respective regions to form the CMOS circuitry. The formation of gate contacts 290, 292, and contacts 284, 286, 294, and 296 also may be carried out by known techniques. At the far left of Fig. 2, the additional p+-type region 240 shown may be grown to provide a CMOS structure. Preferred dopant concentration ranges for the various regions shown in Fig. 2 are as follows: n 10¹⁴ - 10¹⁷/cm³ p 10¹⁴ - 10¹⁷/cm³ n+ 5x10¹⁹ - 5x10²⁰/cm³ p+ 5x10¹⁹ - 5x10²⁰/cm³ Again, it should be clear to the ordinarily skilled artisan that, given the desired dopant concentration ranges, and the desired device characteristics, it should be possible to determine how the various doping and growth techniques should be applied, without undue experimentation.

Claims: A method of fabricating dielectically isolated integrated circuit devices, comprising the following steps: (i) forming a plurality of subcollector regions in a monocrystalline silicon substrate (10) having upper and lower portions (14, 12), said step (i) including the step of doping said upper portion (14) of said substrate (10) in accordance with types of devices to be formed, said lower portion (12) of said substrate forming said subcollector regions, said step (i) further including the following steps: (i)(a) forming a masking layer (20) over said substrate (10); (i)(b) etching a plurality of holes (30) in said masking layer (20); and (i)(c) isotropically etching a plurality of active device regions (40) in said substrate (10) through said holes (30); (ii) growing an oxide layer (50) in said active device regions (40) over portions of said substrate where said devices are to be formed; (iii) etching first regions in said oxide layer (50) over said subcollector regions by anisotropically etching a self-aligned hole (60) in said oxide layer (50) in each of said active device regions (40), said self-aligned hole (60) being directly beneath a corresponding one of said holes (30) in said masking layer (20); and (iv) forming said devices by selective epitaxial growth at least in said first regions. A method as claimed in claim 1, wherein said step (iii) comprises the step of etching said first regions (40) through said upper portion (14) of said substrate (10) to contact said lower portion (12) of said substrate. A method as claimed in claim 1, wherein said step (iii) comprises the step of etching said first regions (40) through said upper portion (14) of said substrate (10) and into said lower portion (12) of said substrate. A method as claimed in anyone of the claims 1 to 3, wherein said step (iv) further comprises the following steps: (iv)(a) filling said active device regions (40) by selective epitaxial growth; and (iv)(b) forming remaining active elements (70, 80, 90) of said integrated circuit devices in accordance with a type of device to be formed. A method as claimed in claim 4, wherein said step (iv) further comprises the step of growing said devices in said active device regions (40) and in said first regions, said step (iv) further comprising the step of selectively epitaxially growing a collector (70), a base (80), and an emitter (90) through each of said holes (30) in said masking layer (20), whereby a vertically self-aligned symmetrical transistor structure is achieved, a collector-base junction and a base-emitter junction covering equal areas. A method as claimed in claim 5, wherein said collectors (70) are grown by out-diffusing said subcollectors regions into said active device regions. A method as claimed in claim 4, further comprising the following step: (v) forming complementary devices between said devices formed in said active device regions, said complementary devices being dielectrically isolated from said devices formed in said active device regions by said oxide layers, said upper portion of said substrate being doped in a manner opposite to the doping of said base grown in each of said active device regions. A method as claimed in anyone of the claims 4 to 7, wherein said step (iv)(b) further comprises the step of forming a base region of said devices wider than said self-aligned hole, said method further comprising the step of forming a base contact through said masking layer into said base region, whereby contact to said base region may be established on an upper surface of said devices. A method as claimed in claim 8, further comprising the step of forming an appropriately doped portion in an upper region of said upper portion of said substrate adjacent said oxide layer outside said base region, whereby contact with said base region is established by connecting said appropriately-doped portion with said base contact.

Inventors: SILVESTRI, VICTOR JOSEPH, TSANG, PAUL JAMIN
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: H01L21
IPC codes: H01L27, H01L21, H01L29