STROBO ELECTRON BEAM APPARATUS

Abstract: The present invention is a strobo electron beam device which, in the strobo electron beam apparatus having an energy analyzer (9) and measuring the voltage in the integrated circuit (l0), samples a secondary electron signal (7) by setting a retarding voltage of the energy analyzer and connecting it to the measured phase, obtains the waveform of the secondary electron signal by a once time or several times phase scanning, adds the product of a suitable coefficient and a difference between the secondary electron signal waveform and a slice level to the retarding voltage and corrects the same. A unit (l8) is provided for judging the conversion of the retarding voltage from the value of the dispersion for the slice level of the secondary electron signal waveform, a unit for adding and giving a mean of the retarding voltage for obtaining a measured value of retarding voltage having a desired S/N ratio, and a unit for random phase scanning so that the measured value having a desired S/N ratio can be easily obtained.

Description: The present invention relates to a strobo electron beam apparatus which provides a retarding field type energy analyzer for measuring a voltage and which quantitively observes the waveform of the voltage in the examined integrated circuit operated rapidly, and especially to the strobo electron beam apparatus which quantitizes the voltage waveform by controlling the retarding voltage supplied to the energy analyzer connected to a phase scanning operation. As the method for quantitizing the voltage waveform in the integrated circuit by using strobo beams, the method for obtaining the voltage waveform with a one phase scanning operation (one time phase scanning method) is known. (Unexamined Japanese Patent Publication (Kokai) No. 59-225539 and No. 60-l0739) As the method for measuring the voltage waveform in the integrated circuit via an insulation film, a plurality of times phase scanning method and a precharge (erase) method using a serial scanning are known. (Unexamined Japanese Patent Publication (Kokai) No. ll7640) However, in the one time phase scanning method, a large amount of EB radiation is carried out at a same time and at one phase point, and accordingly, the voltage waveform measurement via the insulation film is difficult because of the charge up phenomena of the insulation film. Further, in the one time phase scanning method, if the metal wiring portion is directly probed, contamination is increased and thus the base line is displaced. Accordingly, a stable measurement of the voltage waveform is difficult when the base line sampling is not carried out. The precharge method (Unexamined Japanese Patent Publication (Kokai) No. 60-ll7640) can quantitize the voltage waveform by cooperating with the one time phase scanning method, but an erase operation is required and thus the measuring time is increased. Further, in the usual serial plurality of time phase scanning method (Todokoro, Fukuhara, Japanese Society for Promotion of Science, Committee l32, (Electron and Ion Beam Science and Technology) 82, Research Document p 20 (l982), unless the radiated amount of EB per one phase scanning is decreased, the voltage waveform of the wiring under the insulation film cannot be obtained without the charge up phenomena occuring. If, in the usual plurality of times phase scanning method, the phase scanning is carried out at a high speed, to remove the effect of the charge up, the frequency response of the energy analyzer must be more than l0 MHz, and therefore the quantitization of the voltage waveform is difficult to realize. Accordingly, it is desirable to provide a strobo electron beam apparatus which provides a means of correcting the retarding voltage in the energy analyzer and a means for randomly changing the phase scanning, so that the measuring time can be shortened and the voltage measurement accuracy can be improved. To achieve the above-mentioned, an embodiment of the present invention can provide a strobo electron beam apparatus comprising: a strobo electron beam means for detecting a voltage in an examined integrated circuit having a high speed operation; a phase scanning means for scanning the phase of a strobo electron beam; an energy analyzing means for analyzing a secondary electron energy obtained at each phase scanning from the examined integrated circuit; a secondary electron detecting means for detecting the secondary electron energy analyzed at each phase scanning; a retarding voltage correcting means for correcting the retarding voltage supplied to the energy analyzing means at each phase scanning from the secondary electron signal obtained from the secondary electron detecting means; a conversion judgment means for calculating an error of the corrected analyzed voltage to judge the conversion thereof; a repeating means for repeating the operations of the phase scanning, secondary electron energy detection, retarding voltage correction, and conversion judgment when the error is judged to be beyond a predetermined value; and a retarding voltage adding means which, when the error is judged to be below a predetermined value by the conversion judging means, repeats the operations of the phase scanning, the secondary electron signal detection, and the retarding voltage correction by a number of times determined by the error and a desired voltage measurement accuracy, and which calculates and outputs the added means of each corrected retarding voltage obtained therefrom at each phase scanning, and further the strobo electron beam apparatus comprises a random phase scanning commanding means for commanding a random phase scanning to the phase scanning means and a commanding order changing means for changing the order of a phase scanning command in said commanding means at every one set of phase scanning commands. According to the above-mentioned means, the retarding voltage can be connected and converged in a short time based on a predetermined relative relationship, the measured retarding voltage having a desired S/N ratio can be obtained from the relationships between the dispersion value of the converged value and the voltage measurement accuracy. On the other hand, by carrying out the random phase scanning, the wiring operated under a low repetition frequency can be measured in the same way as the wiring operated under a high frequency. Accordingly, the voltage waveform of the wiring under the insulation film can be sampled without the attenuation caused by the charge up phenomena. Further, by changing the combination of the order of the phase scanning, the state of the charges on the surface of the insulation layer becomes statistically constant, regardless of the measuring phase. In the conventional precharge method, a preradiation of the beam is effected to obtain such a state, but, according to an embodiment of the present invention, a similar condition can be obtained without the preradiation. Reference will now be made, by way of example, to the accompanying drawings, in which: Figure l is a diagram showing a construction of a signal processing apparatus embodying the present invention; Fig. 2 is a diagram showing a construction of a strobo electron beams apparatus embodying the present invention; Fig. 3 is a diagram showing relationships between an analyzed curve and a conversion coefficient α; Fig. 4 is a timing chart for explaining the operation of the strobo delay circuit; Fig. 5 is a diagram showing a sequence of the operation of the present invention; Fig. 6 is a diagram showing a principle of quantitizing the voltage waveform; Fig. 7 is a diagram showing relationships between the number of times of changing the retarding voltage and the retarding voltage; Fig. 8 is a diagram showing relationships between a retarding voltage V R near a slice level SL and amounts of a secondary electron signal; Fig. 9 is a diagram showing a relationship between a voltage on a surface of an insulation film and a time for injection of an electron beam; Fig. l0 is a diagram explaining a random phase scanning system; Fig. ll is a diagram explaining an effect of the random scanning; Fig. l2 is a diagram showing a measurement of a voltage waveform of an integrated circuit having no insulative film; Fig. l3 is a diagram showing a construction of registers of a secondary electron signal adding circuit; Fig. l4 is a diagram showing a construction of registers of a secondary electron signal processing circuit; Fig. l5 is a diagram showing a construction of registers of an retarding voltage control circuit; Fig. l6 is a diagram showing a construction of registers of a phase control circuit; Fig. l7 is a diagram showing an initialization of Reg. 8; Fig. l8 is a diagram showing a construction of registers of a random address generator circuit; Fig. l9 is a diagram showing a construction of registers of a retarding voltage data processing circuit; Fig. 20 is a diagram showing a construction of registers of a conversion judging circuit; Fig. 2l is a diagram showing a construction of registers of a repeating time setting circuit; Fig. 22 is a diagram showing a construction of registers of a phase feeding counter circuit; Fig. 23 is a diagram showing a construction of registers of a phase scanning counter circuit; Fig. 24 is a diagram showing a construction of registers of a conversion flag setting circuit; Fig. 25 is a diagram showing a construction of registers of a retarding voltage adding counter circuit. Fig. 26 is a block diagram of an internal construction of the secondary electron signal adding circuit ll shown in Fig. l; Fig. 27 is a block diagram of an internal construction of the strobo delay circuit l2 shown in Fig. l; Fig. 28 is a block diagram of an internal construction of the secondary electron signal processing circuit l3 shown in Fig. l; Fig. 29 is a block diagram of an internal construction of the analyzed voltage control circuit l4 shown in in Fig. l; Fig. 30 is a block diagram of an internal construction of the phase control circuit l5 shown in Fig. l; Fig. 3l is a block diagram of an internal construction of the random address generator l6 shown in Fig. l; Fig. 32 is a block diagram of an internal construction of the analyzed voltage data processing circuit l7 shown in Fig . l; Fig. 33 is a block diagram of an internal construction of the conversion judgment circuit l8 shown in Fig. l; Fig. 34 is a block diagram of an internal construction of the repeating times setting circuit l9 shown in Fig. l; Fig. 35 is a block diagram of an internal construction of the phase feeding counter circuit 20 shown in Fig. l; Fig. 36 is a block diagram of an internal construction of the phase scanning counter circuit 2l shown in Fig. l; Fig. 37 is a block diagram of an internal construction of the conversion flag setting circuit 22 shown in Fig. l; and, Fig. 38 is a block diagram of an internal construction of the retarding voltage adding counter circuit 23 shown in Fig. l. Hereinafter, the embodiments of the present invention will be explained in detail. {Construction of a strobo electron beam apparatus (Fig. l and Fig. 2)} A block diagram of the strobo electron beam apparatus as one embodiment of the present invention is shown in Fig. 2. The present invention provides a signal processing apparatus l, a strobo SEM apparatus 2 having a retarding field type energy analyzer 9, a control apparatus 3, and a clock signal generator 4. Further, the SEM apparatus 2 is formed by a blanker 5, which converts a primary electron beam into a pulse form, and an energy analyzer 9, which analyzes an energy of secondary electrons 7 radiated from an examined IC l0 by a strobo electron beam 6, and a secondary electron signal detector 8 which detects a secondary electron signal and converts it to an electric signal. l0l is a start signal of the signal processing apparatus, l56 is an end signal of the signal processing apparatus, l58 is a clock signal, l60 is a blanking pulse, l63 is a retarding voltage, and l64 is a secondary electron signal. The signal processing apparatus l is shown in Fig. l. The signal processing apparatus is formed by a secondary electron signal adding circuit ll, a strobo delay circuit l2, a secondary electron signal processing circuit l3, a retarding voltage control circuit l4, a phase control circuit l5, a random address generator l6, a retarding voltage data processing circuit l7, a conversion judgement circuit l8, a repeating times setting circuit l9, a phase feeding counter circuit 20, a phase scanning counter circuit 2l, a conversion flag setting circuit 22, a retarding voltage adding counter circuit 23, and AND and OR circuits 24 ∼ 34. {Explanation of an operation of the strobe electron beam apparatus (Fig. l)} Referring to the operation of the strobe electron beam apparatus constructed above, first, the summary thereof will be given. [Operation l] At the time that the random address generator l6 generates N points of random address information in order, N counts for reading the random information at that time are generated by a phase feeding counter circuit 20. Then, corresponding phase data is generated by the phase control circuit l5 at every address, and the electron beam 6 corresponding to each phase is irradiated via the strobo delay circuit l2 and the blanker 5 (Fig. 2) to the examined IC l0. Simultaneously, the retarding voltages corresponding to each phase above are read from a register in the retarding voltage control circuit l4, and are applied to the energy analyzer 9 (Fig. 2). At this time, the address pointer for registers equals each address mentioned above generated in the random address generator l6. Next, in each phase mentioned above, the secondary electron signal l64 is detected L times in the secondary electron signal detector 8 (Fig. 2) and is added L times and is averaged by the secondary electron signal adding circuit ll. Then the result of the averaging in each phase is added in to a register of the secondary electron signal processing circuit l3. At this time, the addresses in each register have the value of each address generated in the random address generator l6. By the above-mentioned operation, an added mean value of the detected secondary electron signals of L samples is obtained at every N phase points generated randomly. [Operation 2] The operation l is repeated J times. The repeat of J times is controlled by the phase scanning counter circuit 2l. As a result, at each of the phase points generated at random, the added results of detected secondary electron signals of M = L × J sample are obtained in N registers in the secondary electron signal processing circuit l3. [Operation 3] After the operation 2 is ended, from the result of the added means of the secondary election signals at N phase points, a retarding voltage corresponding to the next N phase points is determined and this retarding voltage value is set in each register in the retarding voltage control circuit l4. At this time, the prior each retarding voltage value and a predetermined conversion coefficient α are used. [Operation 4] After the operation 3 is ended, the conversion judgeing circuit l8 calculates a voltage measurement error V err l at each of the N phase points above for a predetermined slice level. At this time, the conversion coefficient α is used. If V err l is not lower than a predetermined value of first conversion judgement V conv , the above-mentioned operations l ∼ 3 are repeated by correcting the retarding voltage. When V err l becomes lower than V conv , the above-mentioned operations l ∼ 3 are repeated only a predetermined number of times K, and the added mean value of K times the retarding voltage values are calculated at each of the N phase points. At this time, the value of K is determined from the ratio between V err l and a predetermined secondary conversion error V err 2. Further, above addition is carried out by the retarding voltage data processing circuit l7, and the setting and the control of the number of repeating times K are carried out by the repeating times setting circuit l9 and the conversion flag setting circuit 22. [Operation 5] The result of the K times addition of the retarding voltage at every phase point obtained by the operation 4 is output to the control apparatus 3 as a final output. As mentioned above, by the operations l ∼ 5, the result of a measured voltage for N phase points can be obtained with a good accuracy within a predetermined accuracy V err 2. Hereinafter, the operations of each circuit will be explained in detail. {Explanation of the operation of the secondary electron signal adding circuit ll (Fig. l and Fig. l3)} The following is an explanation of the operation of the secondary electron signal adding circuit ll. In the secondary electron signal adding circuit ll, there is a Reg l and Reg 2 each having a l6 Bit depth, and a Reg 3 having a 32 Bit depth. Upon receipt of a strobe from the starting signal l0l, the secondary electron signal adding circuit ll reads the adding times of secondary electron signal L from the control apparatus 3 to Reg l, and when all secondary electron signal adding times M are read in Reg 2, a signal line l02 is made to a high potential and a mask l57 is made to a low potential. When a signal line lll is made to a high potential, the signal line l02 is reset. Data setting means for Reg l, Reg 2 and a reset means for the signal line l02 are omitted. When the secondary electron signal adding circuit ll receives the strobe from the signal line l25, it clears Reg 3, and thereafter, makes the mask l57 to a high potential. Then the sampling strobe l62 synchronized with the blanking pulse l60 is output from the strobo delay circuit l2. The sampling strobe l62 becomes a trigger for AD conversion of the secondary electron signal l64, and the AD converted data is converted to a floating point representation and is added to Reg 3. When the secondary electron signal adding circuit ll receives the sampling strobe l62 L times, it makes the mask l57 to a low potential, and multiplies the content of the Reg 3 by l/M to make the secondary electron signal data l26. After a least significant bit of a final AD converted value is made the LSB data l27, the strobe is generated in the signal line l28. The LSB data l27 is a natural random number having a value of 0 or l, and is used for randomly combining the order of a phase scanning mentioned hereafter. {Explanation of an internal construction of the secondary electron signal adding circuit ll (Fig. 26)} The following is the explanation of the internal construction of the secondary electron signal adding circuit ll. The secondary electron signal adding circuit ll is formed by a Reg l control circuit C00l formed by Reg l and a peripheral circuit, a Reg 2 control circuit C002 formed by Reg 2 and a peripheral circuit, a Reg 3 control circuit C003 formed by Reg 3 and a peripheral circuit, a counter register circuit C004 formed by a temporary counter register having a l6 Bit depth, an AD converter C005, and AND gates, an OR gate and RS flip-­ flop circuits. When the Reg l control circuit C00l receives a strobe from a start signal l0l, it reads a number of times L of adding the secondary electron signals from a control apparatus 3 via a signal line A00l to Reg l, and thereafter, generates a strobe to a signal line A003. The content of Reg l appears in the signal line A0l0. In Fig. l, the signal line A0l0 is omitted. When the Reg 2 control circuit C002 receives a strobe from a start signal l0l, it reads a number of times M of adding all secondary electron signals from a control apparatus 3 via a signal line A002 to Reg 2, and thereafter, generates a strobe to a signal line A005. The content of Reg 2 appears in the signal line A0l8. In Fig. l, the signal line A002 is omitted. A signal line l02 detects the rising in the signal line A003, and when the rising is detected in the signal line A005, it is made to a high electric potential. The signal line l02 is made to a low electric potential when it detects a rising in the start signal l0l or the signal line lll. In Fig. l, the signal line lll is omitted. When the Reg 3 control circuit C003 receives a strobe from the signal line l25, it clears Reg 3, and thereafter, generates a strobe to a signal line A008. When the circuit C003 receives an AD conversion ending strobe from a signal line A0l4, it floats the AD converted data appearing in the signal line A0l5, and thereafter, is added to Reg 3. When the circuit C003 receives a strobe from the signal line A0l6, the circuit C003 writes the result in which the data stored in Reg 3 is divided by the content M of Reg 2 appearing in the signal line A0l8 to the secondary electron signal data l26, and generates a strobe to the signal line l28 after the signal line l26 becomes stable. The counter register circuit C004 is provided therein with a temporary register having a l6 Bit depth, and when the circuit C004 receives a strobe from the signal line l25, circuit C004 transfers the content of Reg l appearing in the signal line A0l0 to the temporary registor, and thereafter, generates a strobe to the signal line A0ll. When the circuit C004 receives a sampling strobe l62, it decrements the content of the temporary register by l. At this time, as a result of the decrement, when the content of the temporary register becomes 0, it generates a strobe to the signal line A0l6 after a suitable waiting time. The waiting time is suitably selected to be somewhat longer than a series of operations so that the circuit C003 writes the result of the AD conversion of the secondary electron signal l64 effected by the AD conversion circuit C005 after the sampling strobe is received. When the signal line A008 detects a strobe, and the signal line A0ll detects a strobe, a mask l57 is made to a high electric potential. When a signal line A007 or a signal line A0l6 detects a strobe, the mask l57 is made to a low electric potential. The AD conversion circuit C005 carries out an AD conversion of the secondary electron signal l64 synchronized with the sampling strobe l62. When the AD conversion is ended, the result thereof is set in the signal line A0l5, and the strobe following is generated to the signal line A0l4. When the AD conversion circuit C005 receives a strobe from the signal line A0l6, it sets the LSB of the final AD converted value to the signal line l27 as LSB data. The setting of the data to the signal line l27 is carried out almost without delay of the strobe to the signal line A0l6. {Explanation of the operation of the strobo delay circuit l2 (Fig. l and Fig. 4)} Hereinafter an explanation of the operation of the strobo delay circuit l2 is given. Figure 4 is a timing chart showing the operation of the strobo delay circuit l2. The strobo delay circuit l2 generates the blanking pulse l60 having a delay of IPH × l00 PS to the clock l59. The sampling strobe l62 has a fixed delay of τ del seconds for the blanking pulse l60. IPH is given by the phase data l6l of an unsigned integer. The phase data l6l is given by l6 Bit data, that is, about 65,000 levels, and accordingly, the delay time of the blanking pulse l60 is about 6.5 µs max. {Explanation of an internal construction of the strobo delay circuit (Fig. 27)} The following is the explanation of the internal construction of the strobo delay circuit l2. The strobo delay circuit is formed by a programmable delay circuit C006, a fixed delay circuit C007, and a decoder C008. As the programmable delay circuit C006, an EH l5l6 with a parallel interface manufactured by EH International Inc. is used. The circuit C006 generates a blanking pulse l60 having a delay amount specified by the signal line A020 for the parallel interface for the clock input from the signal line l59. The fixed delay circuit C007 gives the fixed delay τ del second for the blanking pulse l60 so as to generates a sampling strobe l62. The decoder circuit C008 converts the phase data given to the signal line l6l by a l6 Bit unsigned integer in a packed decimal manner so as to correspond to the parallel interface of the EH l5l6. The result of the conversion is written in the signal line A020. {Explanation of the operation of the secondary electron signal processing circuit l3 (Fig. l and Fig. l4)} Hereafter an explanation of the secondary electron signal processing circuit l3 is given. In the secondary electron signal processing circuit l3, as shown in Fig. l4, there is a register group Reg 4 of 256 having a depth of 32 Bits designated by addresses 0 ∼ 255 for adding the secondary electron signal. The Reg 4 is the register for storing the secondary electron signal data l26 for each phase scanning and the address thereof is supplied by a relative address data l22 from the random address generator l6. When the secondary electron signal processing circuit l3 receives the strobe via the signal line ll2 from the OR circuit 25, it is brought to the adding mode, and after clearing Reg 4, it makes the signal line ll3 to the AND circuit 26 to a high potential. When the signal line ll5 is made to a high potential, it is reset. The reset means for the signal line ll3 is omitted. In above-mentioned adding mode, when the secondary electron signal processing circuit l3 receives a strobe to the signal line l28, the secondary electron signal data l26 is added to each register in Reg 4 specified by the relative address data l22 from the random address generator l6. Further, in the adding mode, the requests l36, l4l for reading the secondary electron signal are masked. Next, the operation for reading the signal will be explained. When the secondary electron signal processing circuit l3 receives the strobe from the signal line l35 from the phase scanning counter circuit 2l, it is made to a signal reading mode. When, it is made to a signal reading made, and the request l36 for reading the secondary electron signal from the retarding voltage control circuit l4 receives the strobe for the first time, the content of the register specified by the address 0 in the Reg 4 appears at the secondary electron signal data l37. Hereinafter, when the strobe is received at the secondary electron signal reading request l36, the data of the register in Reg 4 specified by the address in which a prior address is incremented is sent to the secondary electron signal data l37. The above-mentioned operation is similar to the secondary electron signal reading request l4l between the conversion judgeing circuit l8 and the secondary electron signal data l42. Further, in the signal reading mode, the signal line l28 is masked. {Explanation of an internal construction of the secondary electron signal processing circuit l3 (Fig. 28)} The following is an explanation of the internal construction of the secondary electron signal processing circuit. The secondary electron signal processing circuit is formed by a Reg 4 control circuit C009 including Reg 4 and the peripheral circuit thereof, a decoder circuit C0l0, an address counter C0ll, a data buffer circuit C0l2, AND gates, an OR gate, and flip-flop circuits. When the Reg 4 control circuit C009 receives a strobe from the signal line ll2, it is made to the adding mode, and after clearing the Reg, generates a strobe to the signal line A030. In the adding mode, the signal line A035 is made to a low electric potential, and the secondary electron signal read requests l36, l4l are masked. When the circuit C009, in the adding mode, receives a strobe to the signal line l28, the circuit adds the secondary electron signal data l26 to each register in Reg 4 specified by the address in the signal line A039. When the circuit C009, receives a strobe from the signal line l35, it is made to a data reading mode. When the strobe is generated to the signal line l35, the RS flip-flop is set and the signal line A035 is made to a high potential. Then, the mask for the secondary electron signal read requests l36, l4l is removed. When the circuit C009, in the above-mentioned data reading mode, receives a strobe to the signal line A037, it reads the secondary electron signal data stored in each register of the Reg 4 specified by the address of the signal line A039 to the signal line A040. The decoder circuit C0l0 converts the address given from the signal line l22 or the signal line A038 to match the circuit C009. When the circuit C0l0 receives a strobe from the signal line ll2, it is made to an adding mode, and the circuit C0l0 converts an address data given by the signal line l22 to match the circuit C009, and thereafter, sets the address data to the signal line A039. When the circuit C0l0 receives a strobe from the signal line ll2, it is made to an adding mode, there after it generates a strobe to the signal line A032. When the decorder circuit C0l0 receives a strobe to the signal line l35, it is made to a data reading mode and it converts an address data given by the signal line A038 to match the circuit C009, and, thereafter, sets the address data to the signal line A039. When the address counter C0ll receives a strobe to the signal line l35, it clears the address counter having a 9 Bit depth in the circuit C0ll. The value of the address counter is set to the signal line A038. When the address counter circuit C0ll receives a strobe from the signal line A037, it increments the value of the address counter by l. The timing for incrementing the address counter is immediately after that at which the circuit C009 receives a strobe from the signal line A037 and sets the secondary electron signal data to the signal line A040. The data buffer circuit C0l2 distributes the secondary electron signal data appearing in the signal line A040 to the signal line l37 and the signal line l42. When the signal line ll3 receives a strobe to the signal line A030 and the signal line A032, it is made to a high electric potential, and when it receives a strobe to the signal line ll5, it is made to a low electric potential. The signal line is not shown in Fig. l. {Explanation of the operation of the retarding voltage control circuit l4 (Fig. l, Fig. 3 and Fig. l5)} The following is an explanation of the retarding voltage control circuit l4. In the retarding voltage control circuit l4, as mentioned in Fig. l5, there is a group of registers Reg 5 formed by 256 having a 32 Bit depth by the addresses 0 ∼ 255 for storing retarding voltage data, a 32 Bit Register Reg. 6 for storing the slice level SL, and a 32 Bit Register Reg. 7 for storing a conversion coefficient α. Reg. 5 is a register for storing a next retarding voltage in each phase scanning, and the address is supplied by the relative address data l22 from the random address generator l6. When the retarding voltage control circuit l4 receives a strobe from a starting signal l0l, it makes an initial value of 256 retarding voltage data in Reg. 5 to 0, and it sets the slice level SL from the control apparatus 3 to the read Reg. 6 and similarly, the conversion coefficient α to the read Reg. 7, and then makes the signal line l04 to the AND circuit 24 to a high electric potential. The signal line l04 is reset when the signal line lll is made to a high electric potential. The slice level SL is, as shown in Fig. 3, a mean value of the amounts of the secondary electron signals which the retarding voltage of the energy analyzer 9 (Fig. 2) has sampled by +20 V and -20 V, the conversion coefficient α is a reciprocal of an inclination of an analyze curve at a crosspoint of the slice level and the analyze curve. A data setting means from the control apparatus 3 to Reg. 6, Reg. 7 and a deciding means for deciding the slice level SL and the conversion coefficient α and a means for resetting the signal line l04 are omitted. The retarding voltage control circuit l4 is brought to the retarding voltage setting mode when the signal line l2l from the random address generator l6 receives a strobe, and the content of Reg 5 specified by the relative address data l22 is DA converted to be made to the retarding voltage l63 for the energy analyzer 9 (Fig. 2). When the value of the retarding voltage l63 is set, the signal line l23 for the AND circuit 30 is made to a high electric level. The signal line l23 is reset when the signal line l25 is made to the high electric level. A reset means for the signal line l23 is omitted. Next, the retarding voltage control circuit l4 receives a strobe from the signal line l35 from the phase scanning counter circuit 2l, and is brought to a retarding voltage renewal mode. In the retarding voltage renewal mode, a strobe is generated, in order, to the secondary electron signal read request l36 for the secondary electron signal processing circuit l3, the secondary electron signal data l37 is read, and the content of Reg 5 is renewed according to the following equation. V R (I) = V R (I) - α(S(I) - SL) ... (1) I = 0, ..., 255 V R (I) is the retarding voltage data of Reg 5 specified by the address I, and S(I) is the secondary electron signal data of Reg 4 specified by the address I. When the renewal of the content of Reg 5 is ended, the retarding voltage control circuit l4 makes the signal line l38 for the AND circuits 3l and 33 to a high electric potential, then it becomes the retarding voltage read mode. The signal line l38 is reset when the signal line l50 or the signal line l40 has a high electric potential. A reset means of the signal line l38 is omitted. When the mode is switched to the retarding voltage read mode and the strobe is received for the first time from the retarding voltage data processing circuit l7 to the retarding voltage read request l52, the content of the register specified by the address 0 in Reg 5 appears at the retarding voltage data l53. Hereinafter, when the retarding voltage read request l52 receives the strobe, the data of the register Reg 5 specified by the address incremented by a prior address is sent via the retarding voltage data l53 to the retarding voltage data processing circuit l7. {Explanation of an internal construction of the retarding voltage control circuit l4 (Fig. 29)} The following is an explanation of the internal construction of the retarding voltage control circuit l4. The retarding voltage control circuit l4 is formed by a Reg 5 control circuit C0l3 including the Reg 5 and the peripheral circuit thereof, a Reg 6 control circuit C0l4 including the Reg 6 and the peripheral circuit thereof, a Reg 7 control circuit C0l5 including the Reg 7 and the peripheral circuit thereof, a decoder circuit C0l6, a DA conversion circuit C0l7, a subtracting circuit C0l8, a multiplier circuit C0l9, an address counter C020, an AND gate, an OR gate, and an RS flip-­ flop circuits. When the Reg 5 control circuit C0l3 receives a strobe to the signal line l2l, it makes an initial value of 256 retarding voltage data in Reg 5 0 volt, and thereafter, generates a strobe to the signal line A042. When the circuit C0l3 receives a strobe to the signal line l2l, it is set to a retarding voltage setting mode. In the retarding voltage setting mode, the circuit C0l3 sets the retarding voltage data stored in each register of the Reg 5 specified by the address data A049 to the signal line A050, and after the set value is stabilized, the DA conversion request strobe is generated to the signal line A05l. When the circuit C0l3 receives a strobe to the signal line l35, it is set to a retarding voltage renewing mode. in the retarding voltage renewing mode, the circuit C0l3 generates, in order, the strobe to the signal line l36 and for the strobe, subtracts the value appearing in the signal line A056 from the content in each registers in Reg 5. That is, for the strobe issued at i times to the signal line l36, the value appearing in the signal line A056 is subtracted from the register in Reg 5 specified by an address i-l, so that the retarding voltage data is renewed. When the circuit C0l3 generates strobe 256 times to the signal line l36 and changes the content of 256 registers in Reg 5, it generates a strobe to the signal line A057 so that it is set to the retarding voltaged reading mode. In the retarding voltage reading mode, when the circuit C0l3 receives a strobe from the signal line l52, it sets the retarding voltage data stored in each register in Reg 5 specified by the address data A049 to the signal line l53. When the Reg 6 control circuit C0l4 receives a strobe from a start signal l0l, it receives a slice level from the control apparatus via a signal line A040, stores its value in the Reg 6, and generates a strobe to the signal line A043. The content of Reg 6 appears in the signal line A053. The signal line A040 is not shown in Fig. l. When the Reg 7 control circuit C0l5 receives a strobe from the starting signal l0l, it receives a conversion coefficient α from the control apparatus via the signal line A04l, sets its value to Reg 7, and thereafter, generates a strobe to the signal line A044. The content of Reg 7 appears in the signal line A055. The signal line A04l is not shown in Fig. l. When a signal line l04 receives a strobe to the signal line A042, it receives a strobe to the signal line A043, and receives a strobe to the signal line A044, is made to a high electric potential, and when it receives a strobe to the signal line lll, is made to a low electric potential. The signal line lll is not shown in Fig. l. When the decoder circuit C0l6 receives a strobe from the signal line l2l, it sets a relative address data set in the signal line l22 to a signal line A049. When the circuit C0l6 receives a strobe from the signal line A057, it sets the value of the address counter set in the signal line A059 to a signal line A049. When the DA conversion circuit C0l7 receives a DA conversion request strobe to the signal line A05l, it receives the retarding voltage data from the signal line A050, DA converts the same, and sets it to the signal line l63. The DA conversion circuit generates a strobe to the signal line A052 after the signal line l63 is stabilized. When the signal line l23 receives a strobe from the signal line A052, it is made to a high electric potential, and when it receives a strobe from the signal line l25, it is made to a low electric potential. The signal line l25 is not shown in Fig. l. The subtracting circuit C0l8 subtracts the value of the slice level set in the signal line A053 from the secondary electron signal data l37, and writes the result thereof in the signal line A054. The multiplier circuit C0l9 multiplies the value of the conversion coefficient α set in the signal line A055 with the data received from the signal line A054 and writes the result thereof in the signal line A056. The address counter circuit C020 has an address counter having an 8 Bit depth. When the circuit C020 receives a strobe from the signal line A057, it clears an address counter. When the address counter circuit receives a strobe to the signal line l52, it increments the address counter after a suitable delay. Preferably, the time has a value longer than that required for writing the retarding voltage data in the signal line l53 by the Reg 5 control circuit, for the strobe in the signal line l52. The content of the address counter always appears in the signal line A059. When the signal line l38, receives a strobe to the signal line A057, it is made to a high electric potential, and when it receives a strobe to the signal line l40 or the signal line l50, it is made to a low electric potential. The signal line l40 and the signal line l50 are not shown in Fig. l. {Explanation of the operation of the phase control circuit l5 (Fig. l, Fig. l6, and Fig. l7)} Hereinafter, the operation of the phase control circuit l5 will be explained. In the phase control circuit l5, as shown in Fig. l6, there is a group of registers Reg 8 of 256 specified by the address 0 ∼ 255 having a l6 Bit depth. When the phase control circuit l5 receives the strobe from the starting signal l0l, Reg 8 is initialized in the form shown in Fig. l7.  ini ,  stp are an initial phase and a phase step of the measured waveform specified by l00 ps units, respectively. When the initialization of Reg 8 is ended, the signal line l06 for the AND circuit 24 is made to a high electric potential. The signal line l06 is reset when the signal line lll is made to a high electric potential. The initializing means for Reg 8 and the reset means for the signal line l06 are omitted. When the phase control circuit l5 receives the strobe from the signal line l2l, the content of Reg 8 shown by a relative address data l22 from the random address generator l6 is sent to the phase data l6l, and thereafter, the signal line l24 for the AND circuit 30 is made to a high electric potential. The signal line l24 is reset when the signal line l25 is made to the high electric potential. The reset means for the signal line l24 is omitted. {Explanation of the internal construction of the phase control circuit l5 (Fig. 30)} The following is an explanation of the internal construction of the phase control circuit l5. The phase control circuit l5 is formed by a Reg 8 control circuit C02l including the Reg 8 and a peripheral circuit thereof, a decoder circuit C022 and flip-flop circuits. When the Reg 8 control circuit C02l receives a strobe from the signal line l0l, it initializes Reg 8 to a form shown in fig. l7, and thereafter, generates a strobe to the signal line A062. An initial phase  ini is read via a signal line A060 from the control apparatus 3, and a phase step  stp is read via a signal line A06l from the control apparatus. The signal line A060 and the signal line A06l are not shown in Fig. l. When the signal line l06 receives a strobe from the signal A062, it is made to a high electric potential, and when it receives a strobe from the signal line lll, it is made to a low electric potential. The signal line lll is not shown in Fig. l. When the Reg 8 control circuit C02l receives a strobe from the signal line l2l, it reads the phase data stored in each register of the Reg 8 specified by the address of the signal line A063 to the signal line l6l. After the phase data is stabilized, the circuit C02l generates a strobe to the signal line A064. When the signal line l24 receives a strobe from the signal line A064, it is made to a high electric potential, and when it receives a strobe from the signal line l25, it is made to a low electric potential. The signal line l25 is not shown in Fig. l. The decoder circuit C022 converts the address data of the signal line l22 to match the Reg 8 and writes the result thereof in the signal line A063. {Explanation of the operation of the random address generator l6 (Fig. l and Fig. l8)} Hereinafter, the operation of the random address generator l6 will be explained. In the random address generator l6, as shown in Fig. l8, there is a group of registers Reg 9 of 5l2 specified by the address 0 ∼ 5ll having a 8 Bit depth, and pointer registers Reg l0, Reg ll, Reg l2 having a 9 Bit depth. When the random address generator l6 receives a strobe from the starting signal l0l, the random address generator l6 writes a data in which the values 0 ∼ 255 previously generated at the control apparatus 3 is randomly combined with the portion which is specified by the addresses 0 ∼ 255 of Reg 9, and after that Reg l0 is set 0, Reg ll is set at 256, Reg l2 is set at 5ll, and the signal line l05 for the AND circuit 24 is made to a high electric potential. When the signal line lll is made to the high electric potential, the signal line l05 is reset. The data setting means for Reg 9 and the resetting means for the signal line l05 are omitted. When the signal line ll6 receives a strobe from the OR circuit 27, the random address generator l6 makes the signal line ll7 to the AND circuit 28 is made to a high electric potential. The signal line ll7 is reset when the signal line ll9 is brought to the high electric potential. The resetting means for the signal line ll7 is omitted. When the signal line l33 from the phase scanning counter circuit 2l receives the strobe, the random address generator l6 makes, if the value of Reg l0 at this time is 256, Reg l0 = 256, Reg ll = 0, and Reg l2 = 255, and if the value of Reg l0 at this time is 256, Reg l0 = 0, Reg ll = 256, and Reg l2 = 5ll, and thereafter, generates the strobe to the signal line l34 for the OR circuit 27. When the random address generator l6 receives a strobe at the signal line l20 from the OR circuit 29, the random address generator l6 sets the data read from Reg 9 to the relative address data l22 by using the added content of the address data l3l and the content of Reg l0 as an address, and thereafter, generates a strobe to the signal line l2l. When the random address generator l6 receives a strobe from the secondary electron signal adding circuit ll to the signal line l28, if the LSB data l27 is l, the random address generator l6 writes the address data l22 in a register in the Reg 9 specified by Reg ll as an address so as to increment Reg ll, and if the LSB data l27 is 0, the random address generator l6 writes the relative address data l22 in a register in the Reg 9 specified by Reg l2 as an address so as to decrement the Reg l2, and generates the strobe to the signal line l29 for the phase feeding counter circuit 20. {Explanation of an internal construction of the random address generator l6 (Fig. 3l)} The following is an explanation of the internal construction of the random address generator l6. The random address generator l6 is formed by a Reg 9 control circuit C023 including a Reg 9 and a peripheral circuit thereof, a Reg l0 control circuit C024 including a Reg l0 and a peripheral circuit thereof, a Reg ll control circuit C025 including a Reg ll and a peripheral circuit thereof, a Reg l2 control circuit C026 including a Reg l2 and a peripheral circuit thereof, a decoder circuit C027, a strobe generator circuit C028, AND gates, an OR gate, and flip-flop circuits. When the Reg 9 control circuit C023 receives a strobe from the start signal l0l, it requests a write of random data, via the signal line A070, from the control apparatus 3. The circuit C023 reads the data which the control apparatus 3 sends to the signal line A07l for the strobe in the signal line A070 to the address data Reg 9 as push up. When 256 registers from the top of Reg 9 are filled with the data of the signal line A07l, the circuit C023 generates a strobe to the signal line A072, and when 256 registers are not full, generates a strobe to the signal line A070 again. When the circuit C023 receives a strobe to the signal line A090, it sets the data read from the Reg 9 to a relative address data l22 by using the data from the signal line A089 as an address, and thereafter, generates a strobe to the signal line l2l. When the circuit C023 receives a strobe to the signal line A096, it sets the relative address of the signal line l22 to a register in Reg 9 specified by the data received from the signal line A095 as the address. When the circuit C023 receives a strobe to the signal line A098, it writes a relative address of the signal line l22 to a register in Reg 9 specified by using the data received from the signal line A097 as an address. The signal lines A074, A070 are not shown in Fig. l. When the Reg l0 control circuit C024 receives a strobe from the signal line l0l, it clears a base address pointer Reg l0, and thereafter, generates a strobe to a signal line A074. When the circuit C024 receives a strobe from the signal line l20, it writes a content of Reg l0 to the signal line A087, and thereafter, generates a strobe to a signal line A088. When the circuit C024 receives a strobe from the signal line l33, if the content of Reg l0 is zero, it makes a content of Reg l0 256, and thereafter, generates a strobe to the signal line A08l. When the circuit C024 receives a strobe from the signal line l33, if the content of Reg l0 is 256, it makes a content of Reg l0 zero, and thereafter generates a strobe to the signal line A082. When the Reg ll control circuit C025 receives a strobe from the signal line l0l, it makes the content of Reg ll 256, and thereafter, generates a strobe to the signal line A076. When the circuit C025 receives a strobe from the signal line A08l, it makes the content of Reg ll 0, and thereafter, generates a strobe to the signal line A083. When the circuit C025 receives a strobe from the signal line A082, it makes the content of Reg ll 256, and thereafter, generates a strobe to the signal line A083. When the circuit C025 receives a strobe from the signal line A09l, it writes the content of Reg ll in the signal line A095, generates a strobe to the signal line A096, and thereafter, increments the content of Reg ll by l. When the Reg l2 control circuit C026 receives a strobe from the signal line l0l, it makes the content of Reg l2 5ll, and thereafter, generates a strobe to the signal line A076. When the circuit C026 receives a strobe from the signal line A08l, it makes the content of Reg l2 255, and thereafter, generates a strobe to the signal line A085. When the circuit C026 receives a strobe from the signal line A082, it makes the content of Reg l2 5ll, and thereafter, generates a strobe to the signal line A085. When the circuit C026 receives a strobe from the signal line A092, it writes the content of Reg l2 in the signal line A097, generates a strobe to the signal line A098, and thereafter, increments the content of Reg l2 by l. When the signal line l05 receives a strobe to the signal line A072, it also receives a strobe to the signal line A074, a strobe to the signal line A076, and a strobe to the signal line A078, it is made to a high electric potential, and when it receives a strobe to the signal line lll, it is made to a low electric potential. The signal line lll is not shown in Fig. l. When the Reg ll control circuit C025 generates a strobe to the signal line A083, and the Reg l2 control circuit C026 generates a strobe to the signal line A085, the strobe is generated to the signal line 134. When the decoder circuit C027 receives a strobe from the signal line A088, it adds the content of Reg 10 appearing in the signal line A087 and an address data of a signal line 131, writes the value thereof in the signal line A089, and thereafter, generates a strobe to the signal line A090. If LSB data of the signal line 127 is zero, when the strobe generator circuit C028 receives a strobe from the signal line 128, it generates a strobe to the signal line A092. If LSB data of the signal line 127 is 1, when the circuit C028 receives a strobe from the signal line 128, it generates a strobe to a signal line A091. When the signal line 117 receives a strobe to the signal line 116, it is made to a high electric potential, and when it receives a strobe to the signal line 119, it is made to a low electric potential. The signal line 119 is not shown in Fig. 1. {Explanation of the operation of the retarding voltage data processing circuit 17 (Fig. 1 and Fig. 19)} The following is an operation of the retarding voltage data processing circuit 17. In the retarding voltage data processing circuit 17, as shown in Fig. 19, there is a group of registers Reg 13 of 256 specified by the addresses 0 ∼ 255 having a 32 Bit depth, and Reg 14 having an 8 Bit depth. Reg 13 is a register for integrating and storing the retarding voltage in every each phase scanning. The retarding voltage data processing circuit 17 clears Reg 13, Reg 14 when the starting signal 101 receives the strobe, and makes the signal line 107 for the AND circuit 24 to a high electric potential. The signal line 107 is reset when the signal 111 is at a high electric potential. The reset means for the signal line 107 is omitted. When the strobe is received from the signal line 151 from the OR circuit 32, the retarding voltage data processing circuit 17 generates in order the strobe to the retarding voltage read request 152, reads each retarding voltage data 153 from the Reg 5 in the retarding voltage control circuit 14, and renews the content of Reg 13 in accordance with the following equation. V R sum(I) = V R sum(I) + V R (I) ... (2) I = 0, ..., 255 V R sum is a content of each Reg l3 of 256 (the added value of the retarding voltage data), V R is a content of each Reg 5 of 256, and I is an address for specifying the data of 256 of Reg 5, Reg l3. When the renewal of the Reg l3 ends, the retarding voltage data processing circuit l7 increments Reg l4, and generates a strobe to the signal line l54 for the analyzed voltage adding counter circuit 23. The content of the Reg l3 becomes a final measured value of the retarding voltage and can be read from the control apparatus 3, here, however, this means is omitted. {Explanation of an internal construction of the retarding voltage data processing circuit l7 (Fig. 32)} The following is an explanation of the internal construction of the retarding voltage data processing circuit l7. The retarding voltage processing circuit l7 is formed by a Reg l3 control circuit C029 including Reg l3 and the peripheral circuit thereof, a Reg l4 control circuit C030 including Reg l4 and a peripheral circuit thereof, an AND gate, and a flip-flop circuits. When the Reg l3 control circuit C029 receives a strobe from the start signal l0l, it clears the added value Reg l3 of the retarding voltage data, and thereafter, generates a strobe to the signal line Al00. When the circuit C029 receives a strobe to the signal line l5l, it generates a strobe to the retarding voltage data read request l52, in order, reads the retarding voltage data l53, in order, from the Reg 5 in the retarding voltage control circuit l4, and changes the content of Reg l3 according to the equation (2) already mentioned. When the change of the content of Reg l3 is completed, a strobe is generated to the signal line l54. When the circuit C029 receives a strobe from the control apparatus 3 to the signal line Al05, it sends the retarding voltage data added value of Reg l3 to the signal line Al06 for the control apparatus 3, in order. The signal line Al05 and the signal line Al06 is not shown in Fig. l. When the Reg l4 control circuit C030 receives a strobe from the start signal l0l, it clears the adding times counter Reg l4, and thereafter, generates a strobe to the signal line Al02. When the circuit C030 receives a strobe to the signal line l54, it increments the adding times counter Reg l4 by l. When the signal line l07 receives a strobe to the signal line Al00, and receives a strobe to the signal line Al02, it is made to a high electric potential, and when it receives a strobe to the signal line lll, is made to a low electric potential. The signal line lll is not shown in Fig. l. {Explanation of the conversion judgment circuit l8 (Fig. l and Fig. 20)} The following is an explanation of the conversion judgment circuit l8. In the conversion judgment circuit l8, as shown in Fig. 20, there is a register Reg l5 having a 32 Bit depth for storing the value of a first conversion judgment value V conv of the retarding voltage, a 32 Bit Register Reg l6 for storing the conversion coefficient α, and a 32 Bit Register Reg l7 for storing a slice level SL. When the starting signal l0l receives a strobe, the conversion judgment circuit l8 reads the first conversion judged values V conv of the retarding voltage from the control apparatus 3 to Reg l5, the conversion coefficient α to Reg. l6, the slice level SL to Reg l7, and thereafter makes the signal line l09 for the AND circuit 24 to a high electric potential. The signal line l09 is reset when the signal line lll is made to the high electric potential. The reset means for the signal line l09 and the data setting means for the Reg l5 ∼ Reg l7 are omitted. When the conversion judgment circuit l8 receives the strobe from the signal line l40 from the AND circuit 33, the conversion judgment circuit l8 generates a strobe, in order, to the signal line l4l for the secondary electric signal processing circuit l3, reads the secondary electron signal data l42 of 256 from Reg 4, and calculates a primary conversion error V err l of the retarding voltage in accordance with the following equation. here, S(I) is a content of the register in Reg 4 specified by the address I. When V err l ≦ V conv , the conversion judgment circuit l8 writes the value of V err l to a retarding voltage precision data l45 for the repeating times setting circuit l9, and thereafter, generates a strobe to a conversion flag set request l44 for the conversion flag setting circuit 22. When V err l > V conv , it generates a strobe to the signal line l43 for the OR circuit 25. {Explanation of an internal construction of the conversion judgment circuit l8 (Fig. 33)} The following is an explanation of the internal construction of the conversion judgment circuit l8. The conversion judgment circuit is formed by a Reg l5 control circuit C03l including Reg l5 and a peripheral circuit thereof, a Reg l6 control circuit C032 including Reg l6 and the peripheral circuit thereof, a Reg l7 control circuit C033 including Reg l7 and a peripheral circuit thereof, a subtracting circuit C034, a multiplier circuit C035, a square law circuit C036, a temporary register control circuit C037, a comparator circuit C038, an AND gate, and RS flip-flop circuits. When the Reg l5 control circuit C03l receives a strobe from the start signal l0l, it sets a first conversion judgment value to Reg l5 via the signal line All0 from the control apparatus 3, writes V conv in the signal line Al27, and thereafter, generates a strobe to the signal line All3. The signal line All0 is not shown in Fig. l. When the Reg l6 control circuit C032 receives a strobe from the start signal l0l, it sets a conversion coefficient α V conv to Reg l6 via the signal line Alll from the control apparatus 3, writes α in the signal line Al22, and thereafter, generates a strobe to the signal line All4. The signal line Alll is not shown in Fig. l. When the Reg l7 control circuit C033 receives a strobe from the start signal l0l, it sets a slice level SL to Reg l7 via the signal line All2 from the control apparatus 3, writes SL in the signal line Al20, and thereafter, generates a strobe to the signal line All5. The signal line All2 is not shown in Fig. l. When the signal line l09 receives a strobe to the signal line All3, it receives a strobe to the signal line All4 and receives a strobe to the signal line All5, it is made to a high electric potential, and when it receives a strobe to the signal line lll, it is made to a low electric potential. The signal line lll is not shown in Fig. l. When the subtracting circuit C034 receives a secondary electron signal data l42 from the secondary electron signal processing circuit l3, it subtracts the slice level SL appearing in the signal line Al20 from the secondary electron signal data and writes the result of the operation in the signal line Al2l. When the multiplier circuit C035 receives a result of the operation Al2l from the subtracting circuit C034, it multiplies the conversion coefficient α appearing in the signal line Al22 to the result of the operation and writes the same in the signal line Al23 as the new result thereof. When the square law circuit C036 receives a result of the operation Al23 from the multiplier circuit C035, it makes square the result of the operation and writes the same in the signal line Al24 as the new result thereof. When the temporary register control circuit C037 receives a strobe from the signal line l40, it clears the temporary register which stores the temporary data for determining the first conversion error V errl , and thereafter, generates a strobe to the signal line l4l, and requests a write operation of the secondary electron signal data l42 for the secondary electron signal processing circuit l3. The circuit C037 adds the operated result from the signal line Al24, and thereafter, again generates a strobe to the signal line l4l. The circuit C037 receives a strobe from the signal line l40, adds 256 times the result received from the signal line Al24 to the temporary register, and thereafter writes the content of the temporary register in the signal line Al26. After the signal line Al26 is stabilized, the circuit C037 generates a compare request strobe to the signal line Al25. When the comparator circuit C038 receives the compare request strobe at the signal line Al25, it calculates, from the data of the signal line Al26, in the equation (3) already shown. Next, the circuit C038 compares V errl with the value of the first conversion judgment value V conv set in the signal line Al27. At this time, when V errl ≦ V conv , the circuit C038 writes V errl in the signal line l45, and after the signal line l45 is stabilized, generates a strobe to the signal line l44. When V errl > V conv , the circuit C038 generates a strobe to the signal line l43. {Explanation of the repeating times setting circuit l9 (Fig. l and Fig. 2l)} The following is an explanation of the operation of the repeating times setting circuit l9. In the repeating times setting circuit l9, as shown in Fig. 2l, there is a 32 Bit register Reg l8 for storing the secondary conversion error V err 2 for the voltage measurement accuracy which is necessary in the measurement of the voltage waveform. When the repeated setting circuit l9 receives a strobe from the starting signal l0l, the repeating times setting circuit l9 reads V err 2 from the control apparatus 3 to Reg l8, and thereafter, makes the signal line ll0 for the AND circuit 24 to a high electric potential. The signal line ll0 is reset when the signal line lll is made to the high electric potential. The reset means for the signal line ll0 and the data setting means for Reg l8 are omitted. When receiving the strobe to the signal line l46 from the conversion flag setting circuit 22, the repeating times setting circuit l9 reads a primary conversion error V err l from a retarding voltage precision data l45 from the conversion judgment circuit l8, determines the number of times K is repeated in accordance with the following equation (4), K = (V err l/V err 2)² ...(4). And thereafter, makes, K an integer by raising fractions. Next, K is written in the repeated data l47 for the retarding voltage adding counter circuit 23 and the strobe is generated to the signal line l48. At this time, K is also sent to the control apparatus 3, but here the means thereof are omitted. {Explanation of an internal construction of the repeat times setting circuit l9 (Fig. 34)} The following is an explanation of the repeat time setting circuit l9. The repeat time setting circuit l9 is formed by a Reg l8 control circuit C039 including a Reg l8 and a peripheral circuit thereof, a temporary register control circuit C040 including a temporary register for storing the first conversion error V errl from the conversion judgment circuit l8, and a peripheral circuit thereof, a divider circuit C04l, a square-law circuit C042, an integer circuit C043, and a flip-flop circuit. When the Reg l8 control circuit C039 receives a strobe at the signal line l0l, it reads the secondary conversion error V err2 to the Reg l8 via the signal line Al30 from the control apparatus 3, and generates a strobe to the signal line Al3l. The signal line Al30 is not shown in Fig. l. When the circuit C039 receives a strobe to the signal line Al32, it writes the secondary conversion error V eer2 to the signal line Al34 from Reg l8. When the signal line ll0 receives a strobe to the signal line Al3l, it is made to a high electric potential, and when it receives a strobe from the signal line lll, it is made to a low electric potential. The signal line lll is not shown in Fig. l. When the temporary register control circuit C040 receives a strobe at the signal line l46, it reads the primary conversion error V errl to the temporary register via the signal line l45 from the conversion judgment circuit l8. Thereafter, the temporary register control circuit C040 writes the data in the temporary register to the signal line Al33, and thereafter, generates a strobe to the signal line Al32. When the divider circuit C04l reads the primary conversion error V errl from the signal line Al33 and the secondary conversion error V err2 from the signal line l34, it divides V eer2 by V errl and generates the result thereof to the signal line Al35. When the square-law circuit C042 receives the operation result of the divider circuit C04l from the signal line Al35, it determines the squared value thereof, and writes the same in the signal line Al36 as a new operation result. When the integer circuit C043 receives the operation result of the square-law circuit C042 from the signal line Al36, it converts the value thereof to an integer by raising the fractions, and writes the same in the signal line l47 and the signal line Al37 for the control apparatus 3 as a new operation result, and thereafter, generates a strobe to the signal line l48. The signal line l37 is not shown in Fig. l. {Explanation of operation of the phase feeding counter circuit 20 (Fig. l and Fig. 22)} The following is an explanation of the operation of the phase feeding counter circuit 20. In the phase feeding counter circuit 20, as shown in Fig. 22, there is an 8 Bit counter register Reg l9 and a l Bit overflow flag register Reg 20 for representing the overflow of the counter register Reg l9. When the phase feeding counter circuit 20 receives a strobe from a signal line ll5 from the AND circuit 26, the phase feeding counter circuit 20 clears Reg l9, Reg 20, and thereafter, makes the signal line ll8 for the AND circuit 28 to a high electric potential. The signal line ll8 is reset when the signal line ll9 is made to the high electric potential. The reset means for the signal line ll8 is omitted. When receiving the strobe to the signal line l29 from the random address generator l6, if the overflow flag Reg 20 is set, the phase feeding counter circuit 20 generates a strobe to the signal line l32 for the phase scanning counter circuit 2l, and if the overflow flag Reg 20 is not set, the phase feeding counter circuit 20 sets the content of Reg l9 to the address data l3l for the random address generator circuit l6, and thereafter, generates a strobe to the signal line l30 for the OR circuit 29 and increments Reg l9, and if an overflow occurs in Reg l9, sets the overflow flag to Reg 20. {Explanation of an internal construction of the phase feeding counter circuit 20 (Fig. 35)} The following is an explanation of the internal construction of the phase feeding counter circuit 20. The phase feeding counter circuit 20 is formed by a Reg l9 control circuit C044 including a Reg l9 and a peripheral circuit thereof, a Reg 20 control circuit C045 including a Reg 20 and a peripheral circuit thereof, an AND gate, and flip-flop circuits. When the Reg l9 control circuit C044 receives a strobe at the signal line ll5, it clears the phase feeding counter Reg l9, and thereafter, generates a strobe to the signal line Al40. When the circuit C044 receives a strobe to the signal line Al45, it sets the content of the phase feeding counter Reg l9 to the signal line l3l, and subsequently, generates a strobe to the signal line l30. After generating a strobe to the signal line, the circuit C044 increments the content of Reg l9 by l. At this time, when Reg l9 overflows, the circuit C044 generates a strobe to the signal line Al46. When the Reg 20 control circuit C045 receives a strobe to the signal line ll5, it clears the overflow flag Reg 20, and thereafter, generates a strobe to the signal line Al42. When the circuit C045 receives a strobe at the signal line l29, and if the overflow flag is set, generates a strobe to the signal line l32, and when it receives a strobe to the signal line l29 and if the overflow flag is not set, generates a strobe to the signal line Al45. The overflow flag Reg 20 is set when the strobe is received from the signal line Al46. When the signal line ll8 receives a strobe to the signal line Al40 and receives a strobe to the signal line Al42, it is made to a high electric potential, and when it receives a strobe to the signal line ll9, it is made to a low electric potential. The signal line ll9 is not shown in Fig. l. {Explanation of operation of the phase scanning counter circuit 2l (Fig. l and Fig. 23)} The following is an explanation of the phase scanning counter circuit 2l. In the phase scanning counter circuit 2l, as shown in Fig. 23, there is a l6 Bit register 2l for setting the number of scannings of the phase J and a counter Reg 22 for scanning the phase. When the phase scanning counter circuit 2l receives a strobe from the starting signal l0l, it sets the number of the times for scanning the phase J from the control apparatus 3 to Reg 2l, and thereafter, makes the signal line l03 for the AND circuit 24 to a high electric potential. The signal line l03 is reset when the signal line lll is made to a high electric potential. The reset means for the signal line l03 is omitted. When the phase scanning counter circuit 2l receives a strobe from the signal line ll2 from the OR circuit 25, the circuit 2l transfers the content of Reg 2l to Reg 22, and makes the signal line ll4 for the AND circuit 26 to a high potential. The signal line ll4 is reset when the signal line ll5 is made to the high electric potential. The resetting means for the signal ll4 is omitted. When the phase scanning counter circuit 2l receives a strobe from the signal line l32, the circuit 2l decrements the content of Reg 22. As a result, when the content of Reg 22 becomes 0, the strobe is generated to the signal line l33 to the random address generator l6, and in the other case, the strobe is generated to the signal line l35 for the secondary electron signal processing circuit l3 and the retarding voltage control circuit l4. The relationships between the number J of times of scanning the phase, the number L of times for adding the secondary electron signal in the content of Reg l, and the number M of times for adding all secondary electron signals in the content of Reg 2 is shown by following equation (5). M = L × J (5) {Explanation of an internal construction of the phase scanning counter circuit 2l (Fig. 36)} The following is an explanation of the internal construction of the phase scanning counter circuit 2l. The phase scanning counter circuit 2l is formed by a Reg 2l control circuit C046 including a Reg 2l and a peripheral circuit thereof, a Reg 22 control circuit C047 including a Reg 22 and a peripheral circuit thereof, and flip-flop circuits. When the Reg 2l control circuit C046 receives a strobe from the start signal l0l, it reads the number of the phase scanning times J to Reg 2l via the signal line Al50 from the control apparatus 3, and thereafter, generates a strobe to the signal line Al5l. When the circuit C046 receives a strobe from the signal line ll2, it writes the content of the Reg 2l in the signal line Al52, and thereafter, generates a strobe to the signal line Al53. When the signal line l03 receives a strobe to the signal line Al5l, it is made to a high electric potential, and when it receives a strobe to the signal line lll, it is made to a low electric potential. The signal line lll and the signal line Al50 are not shown in Fig. l. When the Reg 22 control circuit C047 receives a strobe to the signal line Al53, it receives the content of the Reg 2l, that is the number of scanning times J from the signal line Al52, sets the same to the phase scanning counter Reg 22, and thereafter, generates a strobe to the signal line Al54. When the circuit C047 receives a strobe at the signal line l32, it decrements the phase scanning counter Reg 22, and if the content of the Reg 22 becomes 0, generates a strobe to the signal line l33, or in another case, generates a strobe to the signal line l35. When the signal line ll4 receives a strobe at the signal line Al54, it is made to a high electric potential, and when it receives a strobe to the signal line ll5, it is made to a low electric potential. The signal line ll5 is not shown in Fig. l. {Explanation of operation of the conversion flag setting circuit 22 (Fig. l, Fig. 24)} The following is an explanation of the conversion flag setting circuit 22. In the conversion flag setting circuit 22, as shown in Fig. 24, there is a l Bit register Reg 23 for storing a conversion flag. The conversion flag setting circuit 22 receives a strobe from the starting signal l0l, and the circuit 22 clears Reg 23 and makes the signal line l08 for the AND circuit 24 to a high electric potential. The signal line l08 is reset when the signal line lll is made to a high electric potential. The reset means for the signal line l08 is omitted. The content of Reg 23 appears in the conversion flag l39 for the AND circuit 33 and AND circuit 3l. The conversion flag setting circuit 22 receives the strobe from the conversion flag setting request l44 from the conversion judgment circuit l8, and the circuit 22 sets the conversion flag to Reg 23, and when the value of the conversion flag l39 is determined, the circuit 22 generates a strobe to the signal line l46 for the repeating times setting circuit l9. {Explanation of an internal construction of the conversion flag setting circuit 22 (Fig. 37)} The following is an explanation of the internal construction of the conversion flag setting circuit 22. The conversion flag setting circuit 22 is formed by delay circuits C048, C049, AND gates, and an RS flip-flip circuit. The conversion flag Reg 23 is formed by one flip-flop circuit. The delay time of the delay circuits C048, C049 is suitable for determining a time slightly larger than that for stabilizing the value of the signal line l39, from when the signal line l0l or the signal line l44 receives the strobe. When the signal line l08 receives a strobe from the signal line Al6l, it is made to a high electric potential, and when it receives a strobe from the signal line lll, it is made to a low electric potential. The signal line lll is not shown in Fig. l. {Explanation of operation of the retarding voltage adding counter circuit 23 (Fig. l and Fig. 25)} The following is an explanation for the retarding voltage adding counter circuit 23. In the retarding voltage adding counter circuit 23, as shown in Fig. 25, there is a l0 Bit register Reg 24 for storing the number of times of adding of the retarding voltage. When the retarding voltage adding counter circuit 23 receives a strobe pulse from the signal line l48 from the repeating times setting circuit l9, the counter circuit 23 stores the repeated data l47 in Reg 24, and thereafter, the counter circuit 23 generates a strobe to the signal line l49 for the OR circuit 32. When the retarding voltage adding counter circuit 23 receives a strobe from the signal line l54 from the retarding voltage data processing circuit l7, the counter circuit 23 decrements the content of Reg 24, and when Reg 24 is 0, generates a strobe to the end signal l56, and when Reg is not 0, generates a strobe to the signal line l55 for the OR circuit 25. The operation of present invention mentioned above follows the operation sequence as shown in Fig. 5. In Fig. 5, loops l, 2, 3, 4, and 4', 5 correspond to the operations l, 2, 3, 4, 5 already mentioned. {Explanation of the principle of the invention (Fig. 6 ∼ Fig. l0) Hereinafter, the principle of the present invention will be explained. Figure 6 shows the principle for quantifying the voltage waveform. In Fig. 6, V R is the retarding voltage in the voltage measurement energy analyzer and is the data of Reg 5 in the embodiment of the invention, S is an amount of the secondary electron signal which corresponds to the data of Reg 4 of the present invention. The suffix at the top right shows the renewed number of times the retarding voltage. N is the number of the measured phase points, and N = 256 in the embodiment. A phase  is a data of Reg 8 in the embodiment of the present invention. When the sampling of the secondary electron signal is carried out by the phase (i), and the measured voltage V R ℓ (i), S ℓ (i) is obtained. When S ℓ is obtained at all phases measured by the phase scanning, the retarding voltage V R ℓ is renewed by the equation (l) already mentioned. By repeating the above-mentioned renewal operation, the retarding voltage goes from the initial value V R ⁰ (0 V in the embodiment) to a converged value and the amount of the secondary electron signal coincides with the slice level SL except for the noise component. Next an explanation is given of the reason why the conversion coefficient α is given by the reciprocal of the inclination of the analyze curve at the crosspoint of the slice level and the analyze curve, and the reason why a primary convergence in which the convergence of the retarding voltage is carried out by renewing the retarding voltage in accordance with the already mentioned equation (l) and the reason why the adding of the mean times K of the retarding voltage which carries out the adding of the retarding voltage data renewed after the primary convergence and which obtains the analyzed voltage having an accuracy of the secondary convergence error V err 2 is given by the equation (3), (4). Figure 7 shows a relationship between the times of renewal of the retarding voltage and the retarding voltage for five conversion coefficients α. In Fig. 7, the initial value of the retarding voltage is set to 0 V, and the retarding voltage is renewed in accordance with the already mentioned equation (l). In Fig. 7, it can be understood that, when the conversion coefficient α is selected to be the reciprocal of the inclination of the analyze curve at a the crosspoint of the slice level and the analyze curve, i.e., it most rapidly converges on the final convergence value 4.l8 V. The second reason for which the convergence coefficient α is set to the value shown by the equation (6) will be given hereinafter. As shown in Fig. 8, the relationships between the retarding voltage V R near the slice level SL and the amount of the secondary electron signal S is shown by the equation (7). In equations (7) ∼ (9), the suffix ℓ showing the number of times of the correction of the retarding voltage is placed in right under portion, to distinguish it from the number of times of multiplying. n ℓ designating a white noise. S ℓ = SL + β (V Rℓ - V Rconv ) + n ℓ To ensure that the generality is not lost if it is set as SL = 0, V ncon = 0, the following equation (7)' is used. S ℓ = βV Rℓ + n ℓ (7)' When the retarding voltage is corrected in accordance with the equation (l), V R is given by the equation (8). In the equation (l0), when it is set as V Rℓ is shown by the multiplication of α and the white noise n ℓ . As shown in the equation (9). V Rℓ = -αn ℓ-l (9) There is a well known characteristic feature concerning the white noise wherein the dispersion is decreased in proportion to K -l/2 by carrying out a K times adding. By using this characteristic feature, by carrying out a K times correction of the retarding voltage and the adding after the retarding voltage converges near to the slice level, the S/N of the measured value of the retarding voltage can be improved by √K times. Further, in the condition in which the relation­ ships between the secondary electron signal amount S and the retarding voltage V R is linear so as to form the equation (7), the error V err l of the analyzed voltage can be determined from the equation (3). Therefore, to obtain a desired voltage measurement error V err 2, the analyzed voltage may be added and for the number of times determined by the equation (4). Next, an explanation will be given of the effect of the random phase scanning method against the usual serial phase scanning method and the method for realizing the random phase scanning method. When the electron beam is continuously exposed to the insulation film, in a simple model for explaining the charge up phenomena of an insulation film, regardless of the initial value V ini of the surface voltage of the insulation film V suf , the insulation film surface voltage V suf becomes an equillibrium surface voltage V eq in a certain relaxation time τ as shown in Fig. 9. Here, τ is a relaxation time for a continuous electron beam. When it is assumed that the pulse width of the strobo electron beam is t ω ·l0⁻⁹s and the repetition frequency is f × l0⁶ Hz, the relaxation time τ stb in the case of the strobo election beam can be shown as follows. As a typical example, when τ = 5 µsec, the pulse width of the strobo electron beam is l ns, the repetition frequency is l MHz, τ stb becomes 5 msec. When the voltage waveform having a repetition frequency of l MHz is measured at 256 phase points, when the number of the electron beam pulses at one phase point is L, the time τ scan required for scanning one phase becomes as follows: τ scan = 256·L·l0⁻⁶ sec (ll) In the serial phase scanning usually used, if the condition of equation (l2) is satisfied, an almost faithful measurement of the voltage wave is possible, wherein τ scan « τ stb (l2) For example, if it is assumed that 10 τ scan = τ stb , it becomes about L = 2. However, in this case, when the voltage waveform is quantitized in the embodiment of the present invention, the retarding voltage of the energy analyzer must be switched at 2 µsec, therefore, the portion which supplies the retarding voltage to the energy analyzer of the energy analyzing means and the phase scanning means requires a frequency response of about l0 MHz. Further, when the number of measuring points increases, the frequency response must be further increased, and thus the realization becomes difficult. On the other hand, by using the technique of a so-called precharge method, the sampling in which 2¹⁰ electron beams pulses are injected to one phase point at one precharge operation becomes possible. Further, the number of electron beam pulses does not depend on the number of measuring phase points. However, the electron beam pulse having an amount l0 times that needed when the sampling is carried out for the precharge is neces­ sary, and therefore, the measuring time becomes long. Conventionally, the precharge method is carried out by using the electron beam with a special phase, however, a similar effect can be obtained by exposing the electron beam and randomly changing the phase. Therefore, if the secondary electron signal is sampled by randomly scanning the phase, the sampling and the precharge are carried out at the same time, and the electron beam pulse of 2¹⁰ per one phase point can be used regardless of the number of phase measuring points. Further, the response speed of the energy analyzer may be about 20 KHz, and this is easily realized. Further, by carrying out the random phase scanning, the voltage waveform having a low frequency component can be measured in the same way as the voltage waveform having a high frequency component. This is very advantageous when the measurement is carried out via an insulation film. Next, the method for realizing the random phase scanning will be explained. In the random phase scanning by the electron beam, all the measuring phases must be set accurately at one time by one phase scanning and the phase scanning is carried out with a different order at each phase scanning. Such a method for realizing the phase scanning is shown in Fig. l0. In the 0 ∼ 255 addresses of the address data in Reg 9, the values combined randomly with the numbers 0 ∼ 255 are stored. When the value Il obtained by adding the content 0 of the base address pointer of Reg l0 and the content Il of the phase feeding counter of Reg l9 is used as the address and the data is read from the address data of Reg 9, the value I2 is obtained. The value read from the phase data of Reg 8 by using I2 as the address is set to the phase data l6l, the value read from the retarding voltage data of Reg 5 using I2 as the address is DA converted and sets the retarding voltage l63, and the secondary electron signal is then sampled and the sampled value is written in the portion of the address I2 of the secondary electron signal data of Reg 4. If the LSB data l27 is l, I2 is written in the Reg 9 by using a value Pl of Reg ll as the address, to increment Reg ll and increment Reg l9. If the LSB data l27 is 0, I2 is written in Reg 9 as the content of the address pointer of Reg l2 to decrement Reg l2 and increment Reg l9. When the Reg l9 overflows, if Reg l0 is 0, it is set as Reg l0 = 256, Reg ll = 0, Reg l2 = 255, Reg l9 = 0, and if Reg l0 = 256, it is set as Reg l0 = 0, Reg ll = 256, Reg l2 = 5ll, Reg l9 = 0, then the phase scanning can be effected by a new random sequence generated by a natural random LSB data l27. {Result of experiments according to the present invention (Fig. ll and Fig. l2) } Figure ll shows the result of experiments with the present invention. The measurement is carried out by supplying a rectangular pulse wave having an amplitude of 5 V and a frequency of l MHz to a 5 µm electrode under the insulation protecting film (PSG) having a l µm thickness. The EB acceleration voltage is l kV, the EB pulse width l ns, and the number of pulses exposed per one phase point per one phase scanning is 2¹⁰. The phase transferred width is 8 ns. Figure l2 shows the case when the waveform in the IC excluding the PSG film is measured under a similar condition to that shown in Fig. ll. The wave distortion seen in the serial phase scanning (Fig. llB) is removed by carrying out the random phase scanning (Fig. llA). The attenuation of the amplitude when the voltage waveform is measured via the insulation film is due to the voltage drop by the electric field occurring inside the insulation film. Thus, by using an embodiment of the present invention, the voltage waveform of the electrode under the insulation film can be quantitatively measured. According to an embodiment of the present invention, the retarding voltage can be corrected and converged in a short time, and an analyzed measured voltage having a high S/N ratio can be obtained. Further, by randomly scanning the phase, if the electrode is placed under the insulation film a measurement having a high accuracy can be possible in a short time.

Claims: 1. A strobo electron beam apparatus comprising: a strobo electron beam means (2) for detecting a voltage in an examined integrated circuit (l0) having a high speed operation, a phase scanning means (l5) for scanning a phase of a strobo electron beam (6), an energy analyzing means (9) for analyzing an energy spectrum of secondary electrons obtained at each phase scanning from said examined integrated circuit (l0), a secondary electron signal detecting means (8, ll, l3) for detecting secondary electron signal analyzed at said each phase scanning, a retarding voltage correcting means (l4) for correcting the retarding voltage supplied to said energy analyzing means at said each phase scanning from said secondary electron signal obtained from said secondary electron signal detecting means, a conversion judgment means (l8) for calculating an error of said corrected retarding voltage so as to judge the conversion; a repeating means for repeating the operations of said phase scanning, said secondary electron signal detection, said retarding voltage correction and said conversion judgment when said error is judged to be beyond a predetermined value, and retarding voltage adding means (l7, l9) which, when said error is judged to be below a predetermined value by said conversion judging means (l8), repeats the operations of said phase scanning, said secondary electron signal detection and said retarding voltage correction by a number of times determined by said error and a desired voltage measurement accuracy, and which calculates and outputs the addition of said each corrected retarding voltage obtained therefrom at said each phase scanning. 2. A strobo electron beam apparatus according to claim l, wherein said apparatus comprises a random phase scanning commanding means (l6) for commanding the random phase scanning to said phase scanning means (l5) and a command order changing means (20, 2l) for changing the order of a phase scanning command in said commanding means at every one set of said phase scanning commands. 3. A strobo electron beam apparatus according to claim l, wherein, in said retarding voltage correcting means (l4), when, for a number of measuring phase points N, a measuring phase (I), I = l, ..., N, the retarding voltage Vn(I), I = l, ..., N, secondary electron signal S(I), I = l, ..., N are obtained, the correction of said analyzed voltage is carried out by a following equation. VRℓ+l(I) = VRℓ(I) - α(Sℓ(I) - SL) ... (l) α > 0, I = l, ....., N wherein a suffixes at the top right ℓ or ℓ+l are a number of times of the correction of the retarding voltage, α is a conversion coefficient, and SL is a slice level. 4. A strobo electron beam apparatus according to claim 3, wherein said conversion coefficient α is an inverse value of a slope of an analyzed curve at a cross point of said slice level and said analyzed curve obtained as a relationship between said secondary electron S and said retarding voltage VR as shown by a following equation. 5. A strobo electron beam apparatus according to claim 3, wherein a value (Verr l) of said error is given by a following equation. 6. A strobo electron beam apparatus according to claim l or 5, wherein the relationships between the number of added and mean times (K) of said retarding voltage, said error(Verr l) and said desired voltage measurement accuracy (Verr 2) is given by a following equation. K = (Verrl/Verr 2)² (4) 7. A strobo electron beam apparatus comprising: a strobo electron beam means (2) for detecting a voltage in an examined integrated circuit (l0) having a high speed operation, a phase scanning means (l5) for scanning the phase of a strobo electron beam (6), an energy analyzing means (9) for analyzing an energy spectrum of secondary electrons obtained at each phase scanning from said examined integrated circuit (l0), a secondary electron signal detecting means (8, ll, l3) for detecting said secondary electron signal analyzed at said each phase scanning, an retarding voltage correcting means (l4) for correcting the retarding voltage supplied to said energy analyzing means at said each phase scanning from said secondary electron signal obtained from said secondary electron signal detecting means, a random phase scanning commanding means (l6) for commanding the random phase scanning to said phase scanning means (l5) and a command order changing means (20, 2l) for changing the order of a phase scanning command in said command means at every one set of said phase scanning commands.

Inventors: GOTO, YOSHIRO, ISHIZUKA, TOSHIHIRO, ITO, AKIO, OOKUBO, KAZUO, OZAKI, KAZUYUKI
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G01R31
IPC codes: G01R31, H01L21, H01J37, G01Q30