INTEGRATED DIGITAL CIRCUIT FOR PROCESSING SPEECH SIGNAL

Abstract: In an integrated circuit (10) for transcoder, a subtractor (28) generates a signal representing a difference between an input speech signal (Di) and a prediction signal (Sf). This signal is transferred to a quantizing unit (30). The unit (30) quantizes an output signal from the subtractor (28), and generates a predictive encoded signal (S1). An inverse quantizing unit (42) generates a difference signal (S2). A predictor filter (46) generates the prediction signal (Sf) to be supplied to the subtractor (28). A signal path changing unit made up of electronic switches (26, 32, 34, 36, 38) responds to a mode select signal (M1, M2) to suitably change an electric connection among the subtractor (28), the quantizing unit (30) and the reverse quantizing unit (42), whereby the integrataed circuit device can function as an ADPCM encoder or an ADPCM decoder.

Description: The present invention relates to a digital communication network, and more particularly to an integrated circuit used for a high efficiency encoding system such as adaptive differential pulse code modulation. Recently, due to remarkable developments in digital communication networks, it is possible for various types of analog information to be converted into digital form and transferred among subscribers. A communication system using a predictive encoding system such as adaptive differential pulse code modulation (ADPCM) is widely employed at present. The ADPCM system is advantageous in 1) that speech signals in a telephone network, for example, can be compressed to approximately 16 to 32 K-bit/s, which is advantageous considering signal transmission, and 2) that the reproduced signal on the receiving side is high quality. Advances in semiconductor device manufacturing technology with higher integration, such as LSIs, further facilitates wider application of ADPCM systems. Recent digital communication systems have included transcoder units for performing data compression/expansion. A transcoder unit contains an encoding unit which is provided in the transmitting side for converting a PCM signal into a compressed digital signal, and a decoding system which is provided in the receiving side for decoding the compressed digital signal. By the way, the PCM technique has been widely used in digital communication systems. Particularly, a µ-low PCM system or A-law PCM system according to the CCITT recommendation is most popular. When signal processing units, such as the encoding and decoding units, are packed in an LSI chip, it is necessary that the integrated circuit be designed so as to adapt to the above PCM system. Although the encoding and decoding circuits have many common components, these circuits have been integrated separately and an exclusive encoder LSI and decoder LSI are manufactured independently. Therefore, in the prior art, two types of LSIs are required for the encoder and decoder units. According to an improved example, a circuit arrangement is so designed as to include all the components necessary for the both encoding and decoding circuits and is integrated in an LSI chip. This LSI thus may serve as either an encoder or a decoder. When assembled in the communication system, the LSI is preset so as to perform a selected function, that is, either an encoding or decoding function. In this case, since only one type of LSI can be used as the encoder and decoder units in the communication system, it is possible to reduce the types of LSIs to be manufactured for the encoder and decoder. However, the preset LSI assembled in the system can perform only a selected function, and the function thereof cannot be changed during the system operation. For this reason, the same number of LSIs as the total number of encoder and decoder units, as needed in a digital communication system, must be prepared. Particularly, in the case of a l:n signal transmission system, such as a telephone conference system wherein one party receives a plurality of speech signals of other parties who are participating in the same conference or meeting, an increased number of LSIs must be used according to the number of signal transmission channels. This causes the configuration of the hardware of the transcoder units included in the digital communication system to be undesirably complicated. It is known from "A 32 kb/s Toll Quality ADPCM Codec using a Single Chip Signal Processor", IEEE International Conference on Acoustics, Speech and Signal Processing 1982, T. Nishitani et al, to provide an integrated circuit device which is applied to a digital communication system and has input terminals and output terminals, said device comprising: input signal selector means for receiving digital input signals supplied through the input terminals and for generating selected input signals in a time-division multiplexing manner; subtractor means for receiving a prediction signal and each of the selected input signals time-divisionally supplied thereto from said signal selector means and for generating a difference signal representing a difference between the prediction signal and each of the selected input signals; quantizer means for quantizing the difference signal output from said subtractor means to generate a digitally compressed signal including an adaptive differential pulse code modulation signal; inverse quantizer means for inverse-quantizing the digitally compressed signal to generate an inverse-quantized signal; and predictor means for generating said prediction signal to be supplied to said subtractor means based on said inverse-quantized signal. It is an object of the present invention to provide a new and improved integrated circuit which can be integrated in an LSI chip of decreased size, and can be used effectively for a digital communication system, and hence simplify the circuit arrangement of the system. The integrated circuit device of this invention additionally comprises: signal path changing means for receiving a mode select signal, for changing an electrical connection among said subtractor means, said quantizer means, said inverse quantizer means and said output terminals in response the mode select signal in such a manner that, in a first operation mode, said subtractor means, said quantizer means and said inverse quantizer means are electrically connected with each other so as to form an encoder configuration for each of the selected input signals wherein the input signals are encoded to be supplied to the output terminals in a time-division multiplexing manner, said signal path changing means causing, in a second operation mode, said subtractor means and said quantizer means to be electrically disconnected so as to form a decoder configuration for each of the selected input signals wherein the input signals are decoded to be supplied to the output terminals in a time-division multiplexing manner. An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating the internal construction of an integrated circuit device for transcoder (used in digital speech communication system based on the ADPCM system) which is one preferred embodiment according to the present invention; Fig. 2 shows in block form an equivalent circuit of the IC device when it is switched to a encoding circuit; Figs. 3A to 3I show waveforms of signals as supplied to or generated in the key portions of the IC device of Fig. 1 when it is switched to the encoding circuit; Fig. 4 shows in block form an equivalent circuit of the IC device when it is switched to a decoding circuit; and Figs. 5A to 5H show waveforms of signals as supplied to or generated in the key portions of the IC device of Fig. 1 when it is switched to the decoding circuit. Referring now to Fig. 1, an integrated circuit (IC) for a speech transcoder, which is one embodiment of the present invention, is indicated by block 10. IC circuit 10 is packed in one chip LSI. Circuit 10 includes two input terminals 12 and 14, two output terminals 16 and 18, one clock input terminal 20, and two mode select terminals 22 and 24. First input terminal 12 is connected through electronic switch 26 to subtractor 28, which is further connected to quantizing circuit 30. Circuit 30 quantizes difference signal output from subtractor 28, and generates ADPCM signal S1 of the predetermined number of bits. Electronic switch 26 has input terminals connected to first and second input terminals 12 and 14. Switch 26 serves to selectively transfer to subtractor 28 signals from input terminals 12 and 14. The output terminal of quantizing circuit 30 is connected to first and second output terminals 16 and 18 by way of mode select switches 32 and 34, as electronic switches connected in parallel with each other, and latch circuits 60 and 62. The output terminal of circuit 30 is further connected to the inputs of other electronic switches 36 and 38 connected in parallel with each other. Switches 36 and 38 are connected through succeeding stage electronic switch 40 to reverse quantizing circuit 42, which locally decodes the ADPCM signal S1 sent from quantizing circuit 30. Switch 40 has two inputs connected to the outputs of switches 36 and 38, and an output connected to inverse quantizing circuit 42. The output signal of circuit 42 is fed back to subtractor 28, by way of adder 44 and predictor filter 46. The output signal of adder 44 is also fed back to the adder itself, via predictor filter 46. The output signal of adder 44 is further connected to the second inputs of mode select switches 32 and 34 connected to output terminals 16 and 18 of IC circuit 10. Predictor filter 46 includes arithmetic unit 48 and parallel-connected memories 50 and 52. These memories are each constructed using delay circuits such as digital filter in a known manner. The output signal from adder 44 is supplied to either of memories 50 and 52 by electronic switch 54 provided in predictor 46. The outputs of memories 50 and 52 are connected to unit 48 via another electronic switch 56 in predictor 46. Thus, the output signal from adder 44 is selectively supplied to memories 50 and 52 by means of switches 54 and 56, and processed by unit 48, and then transferred to subtractor 28. The remaining inputs of switches 36 and 38 located at the output stage of quantizing circuit 30 are respectively connected to input terminals 12 and 14. Input terminal 12 is connected through to quantizing circuit 30 through subtractor 28, as mentioned above, and also to the second input terminal of electronic switch 38. With this connection, switch 38 performs a switching operation, and may selectively transfer either ADPCM signal S1 from quantizing circuit 30 or the signal from first input terminal 12 to the succeeding stage electronic switch 40. Input terminal 14 is connected to electronic switch 26 at the preceding stage of subtractor 28, and directly connected to the second input of switch 36. Accordingly, electronic switch 36 performs a switching operation, and may selectively transfer to the succeeding stage electronic switch 40 either of signal S1 from quantizing circuit 30 or the signal from second input terminal 14. The two mode select switches 32 and 34 provided in IC circuit 10 respond to the first mode select signal M1 from mode select terminal 22, to perform an appropriate mode select operation. The switching operation of select switches 34 and 36 is controlled by the second mode select signal M2 from mode select terminal 24. In IC circuit 10 is provided controller 58 which generates control signals C1 to C4 for controlling the switching operations of switches 26 and 40, and the switches 54 and 56 contained in predictor 46. Controller 58 also generates control signals for controlling latch circuits 60 and 62 in response to mode select signals M1 and M2. Further, controller 58 responds to clock signal CK as supplied thereto through clock input terminal 20, and generates reference clock signal FCK to be supplied to subtractor 28, quantizing circuit 30, inverse quantizing circuit 42, adder 44, and predictor 46. According to the IC circuit as the first embodiment of the present invention, when it is assembled into a digital communication system based on the ADPCM system, such as the IC circuit for speech transcoder, responsive to mode select signals M1 and M2 supplied from an external circuit, circuit 10 can time-divisionally be switched to an ADPCM encoder circuit or an ADPCM decoder according to a request occurring in the data transfer operation. Specifically, during a time period that mode select signals M1 and M2 supplied to terminals 22 and 24 of IC circuit 10 are logically high, IC circuit 10 functions as the ADPCM encoder. During another time period that these signals are logically low, that circuit serves as the ADPCM decoder. The function changing operation of this IC circuit will now be described in detail referring to Figs. 2 to 5. When mode select signals M1 and M2 are logically high, mode select switches 32 and 34 are switched as shown in Fig. 2. Under this condition of the circuit, the output signal S1 from quantizing circuit 30 is led to the output terminals 16 and 18 of the circuit. At this time, electronic switches 36 and 38 are switched to the first input side under control of controller 58. When the input signal Di1 to the device takes a form as shown in Fig. 3A, one cycle of the operation of the IC device is so defined as to be divided into five periods T1 to T5 by the reference clock signal FCK. In response to pulsative control signal C1 from controller 58 which is high in logic level during the first period T1 as shown in Fig. 3C, input signal select switch 26 transfers to subtractor 28 the first input signal Di1 supplied from first input terminal 12, during only the first period T1 shown in Fig. 3B. During the other periods (T2 to T5), switch 26 supplies to subtractor 28 the second input signal Di2 supplied from the second input terminal 14. Switch 40 responds to pulsative control signal C2 from controller 58, which is logically high during the third period as shown in Fig. 3D, and during only period T3, guides to inverse quantizing circuit 42 signal S1 as supplied thereto from quantizing circuit 30 through switch 38. During the other periods, switch 40 transfers the input signal Di2 from second input terminal 14 to inverse quantizing circuit 42, through switch 36. Through the switching operations of switches 26 and 40, the data signal supplied from one input terminal 12 of IC circuit 10, for example, a linear PCM signal D1 representing speech information is led to subtractor 28 by way of switch 26. Subtractor 28 calculates a difference between signal Di1 and prediction signal Sf1 output from predictor 46 (see Fig. 3E), in synchronism with reference clock signal FCK, and generates difference signal Se. This signal Se is transferred to quantizing circuit 30 during the second period T2, which quantizes difference signal Se to generate a digital speech signal S1 of the predetermined number of bits (e.g. 16 bits) as the prediction signal. Synchronized with reference clock signal FCK and during the third period T3, the prediction signal S1 from quantizing circuit 30 is led to output terminal 16 through mode select switch 32, and supplied to latch circuit 60. Control signal C5 from controller 58 has the logic high level when mode select signal M2 is logically high during the third period T3. Latch circuit 60 receives control signal C5 and holds an input signal, i.e., the ADPCM signal, supplied thereto during the third period T3 for one cycle of sampling period. The output signal from latch circuit 60 is sent to exterior by way of the terminals. At this time, ADPCM signal S1 is supplied to inverse quantizing circuit 42 by way of electronic switches 38 and 40, since during the third period T3, switch 40 has been switched to allow the output of quantizing circuit 30 to the input of inverse quantizing circuit 42. Inverse quantizing circuit 42 locally inverse-quantize this signal S1. Difference signal S2 output from inverse quantizing circuit 42 is added, by adder 44, with signal Sf1 output from predictor 46 during the fourth period T4. The output signal S3 of adder 44 is supplied to predictor 46 as a reconstructed signal representing a new sampling value. At this time, the two switches 54 and 56 provided in predictor filter 46 have been switched as shown in Fig. 2. Accordingly, when supplied to predictor 46, signal S3 is transferred to the first memory 50 in predictor 46. This signal is subjected to digital delay processing by memory 50, and subjected to additional operation by operation circuit 48. In other words, predictor 46 stores the input new sampling value in memory 50, and generates a predicted value signal during the next sampling segment i+l based on this signal. Accordingly, predictor 46 generates a predicted value signal Sf which predicts the present input signal Di on the basis of the past input sampling value to predictor 46. This new signal Sf is supplied as a prediction signal to subtractor 28 and adder 44 during periods T1 and T4 contained in the next sampling segment i+l. In this way, a sequence of processings of first input signal Di1 applied through first input terminal during the ith segment is completed. The signal processing of the second input signal Di2 as input to the second input terminal during the ith segment is performed after one cycle of reference clock signal FCK since the signal processing of first input signal Di1. Predictor 46 must independently operate for first and second input signals Di1 and Di2. For this reason, it has two parallel memories 50 and 52. These memories 50 and 52 respectively store a first reconstructed difference signal output from adder 44 during the fifth period T5, and a second reconstructed difference signal output from adder 44 during period T1. (The signal supply to memories 50 and 52 is appropriately changed by the switches 54 and 56 provided in predictive filter 46, as already described.) When second input signal Di2 is processed, in-filter switches 54 and 56 are switched as indicated by broken lines in Fig. 2, to supply the input signal to predictive filter 46 to second memory 52. The second predictive signal generated corresponding to second input signal Di2 is output during periods T2 and T5, as shown in Fig. 3F. As a result, the second output signal Do2 is supplied to latch circuit 62. The level of control signal C6 from controller 58 is changed to the logic high level during the fourth period T4. Latch circuit 62 receives control signal C6 and holds the ADPCM signal supplied thereto for one cycle of sampling period. The output signal from latch circuit 62 is output from second output terminal 18 during period T4, while delaying one cycle from first output signal Do1. Thus, if the signal as obtained during period T3 is taken out of terminal 16, first ADPCM signal Do1 is obtained. If a signal as obtained during period T4 is taken out, second ADPCM signal Do2 is obtained. When mode select signals M1 and M2 have logical low level, mode select switches 32 and 34 are switched as shown in Fig. 4, and guides the output signal S1 from adder 44 to the output terminals 16 and 18 of the circuit under discussion. At this time, electronic switches 26, 36, and 38 are switched to the second input side under control of controller 58. Therefore, subtractor 28 and quantizing circuit 30 are electrically disconnected from other components in the IC circuit. In this case, the signals applied to the IC circuit device are ADPCM signals Di3 and Di4 with waveforms as shown in Fig. 5A. One cycle of the operation of IC device 10 is segmented into five periods T1 to T5 by reference clock signal FCK. The control signal C2 from controller 58 (see Fig. 1) is logically high during only the period T3, as shown in Fig. 5c. Accordingly, switch 40 is switched during period T3 as shown, so that ADPCM signal Di3 supplied to first input terminal 12 is transferred through electronic switches 38 and 40 to inverse quantizing circuit 42. Circuit 42 inverse-quantizes the input signal during period T3, and supplies a reconstructed difference signal S2' to adder 44 during period T4. Signal S2' is added by adder 44 to prediction signal Sf1 from predictor 46. Signal Sf1 has a waveform as shown in Fig. 5D. It is noted that, since switches 54 and 56 in predictor filter 46 have been switched as indicated by continuous line in Fig. 4, prediction signal Sf1 is generated through the operation of memory 50. The reconstracted signal output from adder 44 is supplied through switch 32 to latch circuit 60 during period T5, while synchronizing with reference clock signal FCK from controller 58 (Fig. 1). Control signal C5 has the logic high level during the fifth period T5 in response to mode select signal M1 with the logic low level. Therefore, signal Do3 output from latch circuit 60 appears the output terminal 16 of the IC device. The reconstructed signal output from adder 44 is supplied as a new sampling value to predictor 46. Although predictor 46 produces first prediction signal Sf1 during periods T1 and T4, the signal Sf1 produced during period T1 is not used in this case. In this way, the decoding processing is performed for first predictive encoded signal Di3. After period T3, switch 40 responds to control signal C2, and is switched to the opposite position as indicated by broken line to connected second input terminal 14 with inverse quantizing circuit 42. ADPCM signal Di4 supplied from second input terminal 14 is transferred to inverse quantizing circuit 42 during the first period T1, with a time delay corresponding to one clock pulse behind a time point that ADPCM signal Di3 is supplied. At this time, the switches 54 and 56 in predictive filter 46 are switched to the opposite positions as indicated by broken lines. By second memory 52, second predictive signal Sf2 is supplied to adder 44. Accordingly, in adder 44, the operation similar to the above-mentioned case is performed to generate second reproduced speech signal Do4, as shown in Fig. 5E. This signal Do4 is supplied to latch circuit 62 through switch 34. Control signal C6 supplied to latch circuit 62 has the logic high level during the first period T1 in response to mode select signal M2 with the logic low level. Therefore, latch circuit 62 holds the ADPCM signal supplied thereto in the first period T1. The output signal of latch circuit 62, that is, reproduced signal Do4 is then output to exterior from output terminal 18. Through the above sequence of operations, reproduced signal Do3 is obtained from output terminal 16, while another reproduced signal Do4 is obtained. According to the above-mentioned embodiment, the input signals supplied to the first and second input terminals 12 and 14 of IC device 10 can be processed independently of each other in a time-division multiplexing manner. When the mode select signal M1 input to first mode select terminal 22 has a logic high level, and the mode select signal M2 input to the second mode select terminal 24 has a logic low level, IC device 10 serves as ADPCM encoding circuit for the input signal supplied to first input terminal 12, and as an ADPCM decoding circuit for the input signal to second input terminal 14. On the other hand, when the mode select signal M1 input to first mode select terminal 22 is low in logic level, and the mode select signal M2 input to second mode select terminal 24 is high, IC device 10 serves as an ADPCM decoding circuit for the input signal to first input terminal 12, and as an ADPCM encoding circuit for the input signal to second input terminal 14. The circuit 10 of the above-mentioned embodiment can independently process two input signals in the time-division multiplexing manner. Specifically, responsive to the mode select signals M1 and M2 applied to mode select terminals 22 and 24, the circuit 10 can select any combination of circuit functions, such as two predictive encoding circuits, two decoders, or an ADPCM encoder circuit and an ADPCM decoder. To realize a transcoder of N channels for input PCM signals into ADPCM signals by using IC 10, the number of ICs shown in Fig. 1 as required is only N/2. With the feature of the time-divisional signal processing of circuit 10, all but the memory included in predictive filter 46 can be used for both the encoding and decoding circuits. Therefore, the number of necessary components may be minimized and the chip size may further be reduced. This can lead to simplification of the transcoder circuit and reduction of cost to manufacture. Although the present invention has been shown and described with reference to particular embodiments, various changes and modifications which are obvious to a person skilled in the art to which the invention pertains are deemed to lie with the scope of the invention, as defined in claim 1. For example, subtractor 28 and adder 44 may be manufactured using almost the same components. Therefore, these may be replaced by an adder/subtractor. In this case, the adder/subtractor is time divisionally operated with slightly different timings for signal processing. If so, the circuit arrangement may be simplified, with reduced chip size containing such circuit. In the above-mentioned embodiment, the predictor filter 46 is designed so as to receive the output signal from the adder 44, assuming that it serves as a pole filter in the decoder. If it is used as a zero filter, however, predictor filter 46 may be modified so as to receive the output signal from the reverse quantizer. Further, if it is used as both the pole and zero filters, the filter may receive both the signals output from adder 44 and inverse quantizer 30. It is natural, however, that these filters are categorized into the predictive filter for generating a predictive signal. The predictor filter may have either fixed or variable type coefficient. In the case of the variable type coefficient, the coefficient may separately be sent. Furthermore, the present invention may be realized by software or modified so as to receive a great number of input signals.

Claims: An integrated circuit device which is applied to a digital communication system and has input terminals (12, 14) and output terminals (16, 18), said device comprising: (a) input signal selector means (26) for receiving digital input signals (Di) supplied through the input terminals and for generating selected input signals (Di) in a time-division multiplexing manner; (b) subtractor means (28) for receiving a prediction signal (Sf) and each of the selected input signals (Di) time-divisionally supplied thereto from said signal selector means (26) and for generating a difference signal representing a difference between the prediction signal and each of the selected input signals; (c) quantizer means (30) for quantizing the difference signal output from said subtractor means to generate a digitally compressed signal (S1) including an adaptive differential pulse code modulation signal; (d) inverse quantizer means (42) for inverse-quantizing the digitally compressed signal (S1) to generate an inverse-quantized signal (S2); and (e) predictor means (46) for generating said prediction signal (Sf) to be supplied to said subtractor means based on said inverse-quantized signal (S2); characterised by (f) signal path changing means (32, 34, 36, 38) for receiving a mode select signal, for changing an electrical connection among said subtractor means (28), said quantizer means (30), said inverse quantizer means (42) and said output terminals (16, 18) in response to the mode select signal in such a manner that, in a first operation mode, said subtractor means (28), said quantizer means (30) and said inverse quantizer means (42) are electrically connected with each other so as to form an encoder configuration for each of the selected input signals (Di) wherein the input signals (Di) are encoded to be supplied to the output terminals (16, 18) in a time-division multiplexing manner, said signal path changing means causing, in a second operation mode, said subtractor means (28) and said quantizer means (30) to be electrically disconnected So as to form a decoder configuration for each of the selected input signals (Di) wherein the input signals (Di) are decoded to be supplied to the output terminals (16, 18) in a time-division multiplexing manner. The integrated circuit device according to claim 1, characterized in that, in the first operation mode, said signal path changing means (32, 34, 36, 38) supplies each of the selected input signals (Di) to said subtractor means, and changes an electrical connection among said subtractor means (28), said quantizer means (30), and said inverse quantizer means (42) so as to transfer the digitally compressed signal (S1) from said quantizer means (30) to said inverse quantizer means (42), and also to said output terminal (16, 18), whereby said integrated circuit device serves as an encoding circuit. The integrated circuit device according to claim 2, characterized in that, in a second operation mode, said signal path changing means (32, 34, 36, 38) prohibits the selected input signals (Di) from being transferred to said quantizer means (30), and directly supplies said input signals (Di) to said inverse quantizer means (42), and changes an electrical connection among said subtractor means (28), said quantizer means (30), and said inverse quantizer means (42) so as to transfer output signals, which correspond to the input signals (Di) and generated sequentially from said inverse quantizing means (42), to said predictor means (46), and also to the output terminals (16, 18) of said integrated circuit device, whereby said integrated circuit device serves as a decoding circuit. The integrated circuit device according to claim 3, characterized in that said signal path changing means includes a plurality of electronic switches (26, 32, 34, 36, 38). The integrated circuit device according to claim 4, characterized in that said integrated circuit has two input terminals (12, 14) and two output terminals (16, 18), and said predictor means (46) has two memories (50, 52) connected in parallel with each other, said memories (50, 52) being alternately operative in response to the signal supplied to the input terminal (12, 14). The integrated circuit according to claim 5, characterized in that said integrated circuit further comprises: adder means (44) having a first input connected to an output of said inverse quantizer means (42) and a second input to which said prediction signal (Sf) is supplied, said adder means (44) adding together the inverse-quantized signal (S2) and the prediction signal (Sf), to generate a signal representing the result of addition which is prohibited from being transferred to the output terminals (16, 18) in the second operation mode.

Inventors: KUROKI, TOSHIHIKO, NAKAMURA, MAKOTO, SUZUKI, HIDEO
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H03M3
IPC codes: H03M7