SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO CARRY OUT A TEST OPERATION

Abstract: A semiconductor integrated circuit device includes a memory cell array, a decoder circuit, a selection circuit, and a plurality of input terminals 3(1 )...3(n) and input/output termi­ nals (4). The selection circuit is connected to one 3(1) of the terminals and includes a high voltage detector circuit (2) for producing a control signal (⊘) only when a predetermined volt­ age higher than a power source voltage is applied to one of the terminals. The selection circuit further includes a latch circuit (5) connected to the terminals other than the one terminal, for latching an input signal in response to a control signal (⊘) pro­ duced from the high voltage detector circuit (2). When a pre­ determined high voltage is applied to the high voltage detector circuit through one of the terminals, the signal input from the other terminals is latched, in response to the control signal. The status of the memory cell array and the decoder circuit is made to a predetermined specific mode, based upon the latched sig­ nal.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit adapted to carry out a test operation. In particular, it relates to a semiconductor integrated circuit having a multiplexed function selection circuit which enables the integrated circuit to be set to a conventional operation mode as well as other operation modes, for example, a test operation mode. 2. Description of the Related Arts In general, the operational efficiency of semiconductor integrated circuits is checked after manufacture, to ensure that the circuits will function properly in normal use, for example, when subjected to conditions of normal user operation. This check is carried out by a test operation, and is applied generally to simple logic circuits. A memory usually contains a combination of many input patterns, and therefore, a long time is needed for carrying out a test of the circuits therein. In some cases, however, whether an internal circuit is operating normally cannot be determined clearly by a conventional input pattern, and a problem arises in that a satisfactory test of the circuit cannot be carried out. SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved semiconductor integrated circuit adapted to carry out a test operation in which various modes of testing the integrated circuit can be selected under the condition that only a small number of input-only terminals are utilized, and by which a reliable test operation of the integrated circuit can be carried out under such a condition. In accordance with the present invention, there is provided a semiconductor integrated circuit device adapted to carry out an test operation, including: a memory cell array; a decoder circuit; a selection circuit; and a plurality of input or output terminals. The selection circuit includes: a high voltage detector circuit connected to one of the input or output terminals, for outputting a control signal only when a predetermined voltage higher than a power source voltage is applied to said one of the input or output terminals. The memory cell array and the decoder circuit carry out an operation of the integrated circuit device in a regular mode by means of a signal input through the terminals, when a normal voltage is applied to the high voltage detector circuit through said one of the terminals, whereby the statuses of the memory cell array and the decoder circuit are brought to a predetermined special mode, when a predetermined high voltage is applied to the high voltage detector circuit through said one of the terminals. The invention is characterized in that said selection circuit further comprises latch circuits each connected to a terminal other than said one input or output terminal for latching an input signal from said other terminals in response to a control signal delivered from the high voltage detector circuit. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a prior art pad outline; Figure 2 is a block diagram of a prior art high voltage detector circuit and address buffer in an integrated circuit; Figure 3 is a block diagram showing the integrated circuit of an embodiment in accordance with the present invention; Figure 4 is a circuit diagram showing a decoder control circuit and decoder circuit in the integrated circuit of the invention; Figure 5 is a block diagram showing a semiconductor memory circuit of an embodiment according to the present invention; Figure 6 is a circuit diagram showing a control signal latch circuit of the memory circuit in Fig. 5; and Figure 7 is a diagram showing the function of the latch circuit in Fig. 6 and the test mode. DESCRIPTION OF THE PREFERRED EMBODIMENTS To enable a clearer understanding of the present invention, the operation of a multiplexed function optional circuit in accordance with a prior art memory will be described hereinafter with reference to Figs. 1 and 2. As shown in Figs. 1 and 2, a high voltage detector circuit is connected as a multiple selection circuit to an input terminal. Connected to the voltage detector circuit is a decoder circuit, which is set to a definite circuit status for a test mode by the output signal of the high voltage detector circuit. When the potential of an output signal from the high voltage detector circuit is LOW, the decoder circuit of a memory operates in a normal state. The input terminal other than that for the high voltage detector circuit is connected to an input buffer circuit, the output of which is directed to an internal circuit of the memory. Recently, there has been a trend toward an increase of width of the output side of the semiconductor integrated circuit, such as the adaptation of 16 bits or the like to a microcomputer, but this means that it becomes necessary to correspondingly enhance the number of input or output terminals in the memory. This increase in the number of terminals, however, leads to an undesirable increase in the size of the elements. Figure 1 shows a prior art pad outline. In this field, the term "pad" is often applied to edge connectors, which are circuit terminals on a printed circuit board. Figure 1 shows the pad configuration of a 1M bit EPROM, which includes, as an example, 18 inputs and 16 outputs. Among these 18 inputs, ten are utilized to carry out a test operation. Thus, a method is adopted wherein an input buffer and an output buffer are connected to the same terminal, to avoid an increase in the number of input and output terminals, and this method can improve the number of input and output terminals necessarily utilized. As described above, in a test mode it is necessary to apply a voltage higher than the power source voltage V cc to an input terminal. Accordingly, an input/output terminal which is connected by an input buffer and an output buffer can not be employed as a test terminal. This is because, with regard to a memory of CMOS structure, when a high voltage is applied to such an input/output terminal, a forward current of a diode which is connected between an output terminal of a data output buffer and the power source V cc flows in the direction of the power source V cc , and thus the application of a high voltage can not be detected by the high voltage detector circuit. Accordingly, an attempt has been made to provide an input terminal for exclusive use in carrying out a test. But, because of the increase in the number of input/output terminal for common use, the number of input terminal for exclusive use must be decreased. Therefore, a problem arises in that a satisfactory test mode can not be set, and thus a positive and reliable test cannot be carried out. An example of the high voltage detector circuit having CMOS transistors used in a prior art semiconductor integrated circuit is shown in Fig. 2. In Fig. 2, a circuit diagram of a high voltage detector circuit 47 utilizing a CMOS is described. In Fig. 2, 51 and 52 denote a pair of P-channel transistors, 53 an N-channel transistor, and 54 a converter. An input terminal is connected to the source of the P-channel transistor 51. The semiconductor integrated circuit adapted to carry out test operation according to an embodiment of the present invention will now be described with reference to Figs. 3 to 6. As shown in Fig. 3, a plurality of input/output terminals 4 and input terminals 3(1)... 3(n) are employed to send the signal from a control input pad to a latch circuit 5 through a high voltage detector circuit 2, and then send the output of the latch circuit to be utilized as a test signal. On the other hand, a signal from an input/output terminal is sent through an input buffer to an internal memory 6 and an output signal from the internal memory is sent through an output buffer to a latch circuit. Said internal memory circuit 6 includes selection circuit controlling logic circuit, row decoder control means, row decoder, column decoder control means, column decoder, memory cell array, column gate, sense amplifier, and write/data output portion. Figs. 5A to 5D are block diagram showing detailed structure of semiconductor integrated circuit shown in Fig. 3. The operation of the prior art multiple selection circuit will now be described. At a normal operation, the voltage applied by the power source V cc is equivalent to a high level voltage applied to the input terminal, for example, 5 Volts. Then, as the transistors 51 and 52 turn OFF and the N-channel transistor 53 turns ON, a high voltage detector signal is made low level through the converter 54. Therefore, the decoder circuit is in a normal operation mode and carries out a normal memory operation. On the contrary, if the voltage applied by the power source V cc is, for example, 5 Volts in a testing mode, the high level voltage applied to the input terminal is higher than the voltage applied by the power source, for example, 12 Volts. Then, the pair of P-channel transistors 51 and 52 and the N-channel transistor 53 all turn ON, but because of a small transconductance value at the N-channel transistor the output is at a high level. Therefore, the decoder circuit 311 is set to a test mode (for example, a selection state of all word lines), and thus a predetermined test can be executed. Accordingly, in a test mode, a voltage higher than the power source voltage V cc must be applied to the input terminal. Figure 6 is a block diagram of a latch circuit for a control signal in accordance with an embodiment of the present invention. In Fig. 6, reference numerals 7, 8, and 9 denote each two-input NAND gate circuit, R denotes an input for a power ON reset signal, which sets the latch circuit in a reset state by a low level signal pulse produced when the power source voltage is input.  is a control signal supplied from the high voltage detector circuit, and S(IN) and S(LATCH) denote an input signal and a latch signal, respectively. Referring to a truth table in Fig. 7, the operation of the circuit according to the embodiment will be described. In the figure, "L" denotes a low signal level and "H" a high signal level, and "H/L" may be used as either "H" or "L". When the power source rises, an "L" pulse is generated on the R terminal, the circuit is reset, and the output S(LATCH) is initialized to an "L" status (Step(a)). This status is latched and remains the same even if the signal level of the R terminal is "H" (Step(b)). When the output is "L", a normal signal is input to the input terminal or input/output terminal to enable an inherent integrated circuit operation to be carried out. Then, a high voltage for a test mode setting is input to a high voltage detector circuit, and thus the control signal  is changed from "L" to "H". When the input terminal (or input/output terminal) is "L", the output S(LATCH) remains as "L" (Step(c)). When the input terminal (or input/output terminal) becomes "H", the output S(LATCH) is "H" (Step(d)). When the output S(LATCH) is "H", a predetermined circuit of the integrated circuit connected thereto is set to a test mode. This status remains the same even if the control signal  is changed from "H" to "L" and does not depend on the level of the input/output terminal (Step(e)). According to a circuit of an embodiment of the invention, when the circuit is once set to a test mode status, as the test mode state is maintained by a latch circuit, it is not necessary to constantly apply a high voltage throughout a test period, as in the prior art. Since a control signal latch circuit is constituted so as to operate at a normal voltage level, the circuit can be connected not only to an input terminal but also to an input/output terminal, to utilize the signal input from these terminals for a test setting. Therefore, the kinds of test setting modes can be enhanced to a great extent to enable a reliable test to be carried out. A normal operation mode and a test mode which is determined by an output S(LATCH) will be concretely described. Figure 4 shows a circuit diagram of decoder control circuits 301 and 302 and decoder circuits 311 and 312 in accordance with an embodiment of the present invention. In Fig. 4, reference numerals 10, 12, 18, and 24 denote N-channel depletion type transistors; 11, 13 to 15, 17, 19 to 21, 23, 25 to 27, and 29 denote N-channel enhancement type transistors, and 16, 22, and 28 denote P-channel enhancement type transistors. The transconductance of the N-channel transistor 11 is assumed to be comparatively large, and a i denotes an address signal and a i is an inverted signal. The operation of the circuit will be now described. When the output S(LATCH) is "L", the transistor 11 in the decoder control circuit 30 turns OFF, and the power source voltage of each NAND circuit in the decoder circuit 31 is V cc , so that the decoder circuit operates in a normal mode. On the contrary, when the output S(LATCH) is "H", the transistor 11 turns ON to make the output voltage of the decoder control circuit 30 V ss . Therefore, as all outputs of each NAND circuit are V ss , all outputs of the decoder circuit also are "H", and set in a test mode, i.e., the so-called selection of all word lines mode. Figure 5 is a block diagram showing a semiconductor memory circuit device of an embodiment in accordance with the present invention. In Fig. 5 reference numeral 32 denotes a memory cell array, 301 a row decoder control circuit, 311 a row decoder circuit, 35 a column gate circuit, 302 a column decoder control circuit, 312 a column decoder circuit, 38 a sense amplifier, 39 a write/data output circuit, 40 a logic circuit, 41 a high voltage detector circuit, 42(1) and 42(2) input buffer circuits, 43(1) and 43(2) control signal latch circuits, 44(1) to 44(6) address buffer circuits, and 45(1) to 45(6) data input/output buffer circuits. In the figure, the Address/Data terminals are those used for both address multiplexing and as input/output terminals. The operation of the memory circuit device will now be outlined. When a normal voltage level is input to each terminal, an inherent functional operation as in known memory circuits, that is, write and read of data, can be carried out. On the one hand, when a test mode setting voltage higher than the power source voltage through a control input terminal is input to the high voltage detector circuit 41, a control signal  is output to one of the control signal latch circuits 43(1) and 43(2) from the high voltage detector circuit 41. When a fixed signal is input also from the input terminal (or input/output terminal) to which the control signal latch circuits 43(1) and 43(2) are connected, the test mode setting signal is produced from the control signal latch circuits 43(1) and 43(2). The test mode setting signal is input, for example, to a row decoder control circuit 301, as shown in Fig. 5, and the row decoder circuit 311, which can not be set by a normal operation mode, is set to the selection of all word lines modes. Thus, the predetermined test operation can be carried out. As in the row decoder circuit, a column decoder circuit 312 also can be set to the selection of all word lines mode. From the foregoing description of the present invention, it can be concluded that, in response to a high voltage detecting signal produced when the high voltage for test setting use is input from one input terminal, an input signal from other input terminals or the input/output terminals is latched to set a semiconductor integrated circuit to the desired test mode. Thus, the present invention is advantageous in that many kinds of test modes can be set and the testing time is shortened, whereby a reliable operation can be ensured.

Claims: A semiconductor integrated circuit device adapted to carry out a test operation, comprising: a memory cell array; a decoder circuit means; a selection circuit means; and a plurality of input or output terminals (3(1),..., 3(n), 4); said selection circuit means comprising: a high voltage detector circuit (2) connected to one (3(1)) of said input or output terminals for outputting a control signal () only when a predetermined voltage higher than a power source voltage is applied to said one (3(1)) of said input or output terminals; said memory cell array and said decoder circuit means carrying out an operation of said integrated circuit device in a regular mode by means of a signal input through said input or output terminals (3(1),..., 3(n), 4) when a normal voltage (V cc , V ss ) is applied to said high voltage detector circuit through said (3(1)) one of terminals; the status of said memory cell array and said decoder circuit means being brought to a predetermined special mode, when a predetermined high voltage higher than said normal voltages (V cc , V ss ) is applied to said high voltage detector circuit (2) through said one (3(1)) of said terminals, characterized in that said selection circuit means further comprises latch circuits (5), each connected to a terminal (4, 3(n)) other than said one (3(1)) input or output terminal for latching an input signal from said other terminals (4, 3(n)), in response to said control signal () delivered from said high voltage detector circuit. An integrated circuit device according to claim 1, wherein a multiplexed functional selection circuit is provided to carry out a selection of all word lines. An integrated circuit device according to claim 1, wherein there is provided an erasable programmable read only memory which includes a plurality of pads having a definite number of input terminals for exclusive use and a plurality of input/ output terminals for dual usage.

Inventors: YOSHIDA, MASANOBU
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G11C29
IPC codes: G06F11, G01R31, G11C11, G11C29, H01L21, H01L27