LOGIC CIRCUIT HAVING A TEST DATA LOADING FUNCTION

Abstract: A logic circuit having a test data loading function, compris­ ing at least one J-K flip-flop (1). Each J-K flip-flop includes a test data latching logic circuit (2). In response to an enable sig­ nal (E), test data (D) is selected in place of the usual J and K in­ put data to be latched. In a complex logic circuit including such flip-flops, a test can be effected in a short time.

Description: The present invention relates to a logic circuit having a test data loading function. J-K flip-flops are widely known in the art. These J-K flip-flops are used, for example, in a semiconductor chip of a gate array with a multi-stage connection to form a counter or a shift register. When the number of stages is large, it is not easy to test the counter or the shift register, especially at the tail stages. For example, to test the m-th bit of an n-bit binary counter, test data can reach the m-bit flip-flop only after 2 m clocks are applied. When m = 10, 2 m = 1024 and thus 1024 clocks must be applied. Therefore, to test a logic circuit having a very complex logic, the necessary number of clock signals becomes large and thus a very long time is needed for testing the logic circuit. If the test data can be loaded at an arbitrary stage of the logic circuit, such an inconvenient long test time will be eliminated. Therefore, to give a flip-flop a data loading function is especially important for flip-flops used in a logic circuit having a complex logic. However, if an attempt is made simply to give the J-K flip-flop a data loading function, this will necessitate the use of a complex switching circuit, as later described in more detail. An article in IBM Technical Disclosure Bulletin, Vol. 27, No. 6, November 1984, by H. C. Burbank et al., entitled "J-K LSSD SRL for use in a Self-testable Logic Circuit", discloses a logic circuit having the features of the preambles of accompanying claims 1 and 3. This logic circuit uses a test clock and a separate system/self-test clock. In Siemens "Digitale Schaltungen, MOS Datenbuch, 1974/75, Band 1", pages 258-9, there is disclosed a J-K flip-flop corresponding to that depicted in the accompanying Fig. 10. According to one aspect of the present invention, there is provided a logic circuit having a test data loading function, comprising at least one J-K flip-flop; said J-K flip flop comprising:- a first-stage logic circuit having a first input terminal for receiving first input data, a second input terminal for receiving second input data, a test data terminal for receiving test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a clock signal input terminal for receiving a clock signal, a noninverted signal output terminal, and an inverted signal output terminal; said first-stage logic circuit being operable to select, in response to said enable signal applied to said enable terminal, either said test data or said first and second input data, the selected data being latched in said second-stage logic circuit in response to said clock signal applied to said clock signal terminal; characterised in that:- said second stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to the input of said pre-stage logic circuit, the outputs of said pre-stage logic circuit being connected to the inputs of said final-stage logic circuit, and the outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; and in that:- said first-stage logic circuit comprises:- a first AND gate having four inputs respectively connected to said noninverted signal output terminal (Q), to said second input terminal through an inverter, to said enable terminal, and to one of the outputs of said pre-stage logic circuit; a second AND gate having four inputs respectively connected to said first input terminal, to said enable terminal, to said inverted signal output terminal, and to said one of the outputs of said pre-stage logic circuit; a third AND gate having three inputs respectively connected to said test data terminal, to said enable terminal through an inverter, and to said one of the outputs of said pre-stage logic circuit; and a NOR gate having three inputs respectively connected to the outputs of said first, second and third AND gates and having an output connected to said input of said second-stage logic circuit. A second aspect of the invention provides a logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising:- a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal for receiving a first clock signal, an output terminal, and an inverted signal output terminal; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal; characterised in that:- said second-stage logic circuit further comprises a second clock signal input terminal for receiving a second clock signal, the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal. Developments of the invention comprise a synchronous and an asynchronous logic circuit comprising a plurality of J-K flip-flops, as defined in claims 7 and 8. An embodiment of the present invention may provide a logic circuit including a J-K flip-flop with a data loading function, without causing the switching circuits to become complex. An embodiment of the present invention may provide a logic circuit having a test data loading function provided in a semiconductor chip and having a test data input function for testing a logic operation, and more particularly to a J-K flip-flop circuit having a data loading function for carrying out an input of test data other than data input for a usual logic operation. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is a block diagram illustrating a logic circuit according to an embodiment of the present invention; Fig.2 is a logic circuit diagram illustrating in detail the logic circuit shown in Fig. 1; Fig. 3 is a block diagram illustrating a symbol marking of the logic circuit shown in Fig. 1 or in Fig. 2; Fig. 4 is a logic circuit diagram illustrating a logic circuit according to another embodiment of the present invention; Fig. 5 is a block diagram illustrating a symbol marking of the logic circuit shown in Fig. 4; Fig. 6 is a logic circuit diagram illustrating a logic circuit according to still another embodiment of the present invention; Figs. 7A through 7H show a time chart explaining the operation of the logic circuit shown in Fig. 6; Fig. 8 is a block diagram illustrating an asynchronous logic unit according to a still further embodiment of the present invention; Fig. 9 is a logic circuit diagram illustrating a logic circuit according to a still further embodiment of the present invention; Fig. 10 is a logic circuit diagram illustrating an example of a conventional J- K flip-flop; Fig. 11 is a block diagram illustrating a symbol marking of the J- K flip-flop shown in Fig. 9; and Fig. 12 is a logic circuit diagram illustrating a proposed logic circuit including a data loading function. Before describing the embodiments of the present invention, conventional and previously proposed logic circuits and the problems therein will first be described with reference to Figs. 10, 11, and 12. Figure 10 shows an example of a conventional J- K flip-flop. In Fig. 10, G₁ to G₅ are NAND gates, G₆ is a NOR gate; G₇ and G₈ are AND gates, J and K are inputs; CLK is a clock; and Q and Q are outputs. The truth table of this circuit is illustrated in the following table 1; and the symbol marking thereof is illustrated in Fig. 11. J K Q n+1 0 0 0 0 1 Q n (hold) 1 0 Q n (inverted) 1 1 1 The value of Q n+1 is that value existing after a clock is input (after a change from a low level (L) to a high level (H)). Q n represents the Q output at n clock (n-th clock pulse). Q n+1 represents the Q output at n+1 clock. Q n represents an inverted state, i.e., if the prior state is "1", Q n becomes "0"; and if the prior state is "0", Q n becomes 1. The output is determined at the time the clock rises from a low (L) level to a high (H) level. Accordingly, this flip-flop is a positive edge trigger type. There is a need for the flip-flop to be given a data loading function, as mentioned before. Fig. 12 is a logic circuit diagram illustrating a proposed logic circuit including the J- K flip-flop shown in Fig. 10 or 11 and a switching circuit. In Fig. 12, 10 is the J- K flip-flop; S₁ to S₃ represent switches; CKA is a clock signal for normal operation as a J- K flip-flop; CKB is a test clock signal for data loading operation; D is a test data; and E is an enable signal. When the enable signal E is at the H level, the inputs J and K and the clock signal CKA are selected by the switch circuits S₁ to S₃ so as to carry out a usual J- K flip-flop operation. When the enable signal E is turned to the L level, the test clock signal CKB and the test data D are selected so as to perform a test operation. Where a logic circuit includes a multi-stage connection of flip-flops, each flip-flop consisting of the switch circuits S₁ to S₃ and the J- K flip-flop 10 shown in Fig. 12, the input data J and K are supplied from outputs Q and Q of a pre-stage flip-flop (not shown in Fig. 12). Since the switches S₁ to S₃ are complex, the logic circuit shown in Fig. 12 has a disadvantage regarding integration, and when a number of flip-flops are to be connected, this disadvantage will become more serious. Further, since the switches S₁ to S₃ are provided externally of the J- K flip-flop 10, the conventional J- K flip-flop 10 itself does not have a data loading function. Embodiments of the present invention will be now described in the following. Figure 1 shows a logic circuit according to an embodiment of the present invention. In Fig. 1, the logic circuit includes a J-K flip-flop 1. The J-K flip-flop includes a first-stage logic circuit 2 and a second-stage logic circuit 3. The first-stage logic circuit 2 has a first input terminal J for receiving a first input data J, a second input terminal K for receiving a second input data K, a test data terminal D for receiving test data D, an enable terminal E for receiving an enable signal E, and an output O₁. The second-stage logic circuit 3 has an input I connected to the output O₁ of the first-stage logic circuit 2. The circuit 3 further has a clock signal input terminal CK, a noninverted signal output terminal Q, and an inverted signal output terminal Q . The first-stage logic circuit 2 operatively selects, in response to the enable signal E applied to the enable terminal E, either the test data D or the first and second input data J and K. The selected data is latched in the second-stage logic circuit in response to the clock signal terminal CK. Figure 2 shows in more detail the logic circuit 1 shown in Fig. 1. In Fig. 2, the second-stage logic circuit 3 includes a pre-stage logic circuit 4 consisting of NAND gates G₃ to G₅ and a final-stage logic circuit 5 consisting of NAND gates G₁ and G₂. These NAND gates G₁ to G₅ are the same as those in the conventional J- K flip-flop shown in Fig. 9. The output O₁ of the first-stage logic circuit 2 is connected to the input I of the pre-stage logic circuit 4. The outputs O₂ and O ₂ of the pre-stage logic circuit 4 are connected to the inputs I₂ and I ₂ of the final-stage logic circuit 5. The outputs of the final-stage logic circuit 5 are respectively connected to the noninverted signal output terminal Q and to the inverted signal output terminal Q . The first-stage logic circuit 2 includes a NOR gate G 6a , a first AND gate G 7a , a second AND gate G 8a , and a third AND gate G₉. The first AND gate G 7a has four inputs respectively connected to the noninverted signal output terminal Q, to the second input terminal K through an inverter G₁₁ , to the enable terminal E, and to one of the outputs O₂ , of the pre-stage logic circuit. The second AND gate G 8a has four inputs respectively connected to the first input terminal J, to the enable terminal E, to the inverted signal output terminal Q, and to the output O ₂ of the pre-stage logic circuit. The third AND gate G₉ has three inputs respectively connected to the test data terminal D, to the enable terminal E through an inverter G₁₀ , and to the output O ₂ of the pre-stage logic circuit 4. The NOR gate G 6a has three inputs respectively, connected to the outputs of the first, second, and third AND gates, G 7a , G 8a and G₉ , and has the output O₁ connected to the input I of the second-stage logic circuit 3. The NAND gates G₁ and G₂ in the final-stage logic circuit 5 are cross-coupled to each other. In the pre-stage logic circuit 4, the NAND gate G₃ has two inputs and an output; the NAND gate G₄ has three inputs and an output; and the NAND gate G₅ has two inputs and an output. The input I is connected to one input of the NAND gate G₄ and to one input of the NAND gate G₅. The output of the NAND gate G₃ is connected to the input I₂ of the NAND gate G₁ , to the other input of the NAND gate G₅ and to the other input of the NAND gate G₄. The output of the NAND gate G₅ is connected to one input of the NAND gate G₃. The clock signal terminal CK is connected to the other input of the NAND gate G₃ and to another input of the NAND gate G₄. The output of the NAND gate G₄ is connected to the other input of the NAND gate G₂. A symbol marking for this J-K flip-flop with the data loading function shown in Fig. 1 or Fig. 2 is illustrated in Fig. 3. To explain the operation of the logic circuit shown in Fig. 2, usual operations as a J-K flip-flop in a counter or a shift register are carried out by raising the potential of the enable signal E to the H level. In this state, the AND gates G 7a and G 8a are opened to pass the first and the second input data J and K and the AND gate G₉ is closed so that input of the test data D is inhibited. Therefore, by the clock signal CK and the input data J and K, the logic circuit operates in the same way as the before-mentioned conventional J K flip-flop. When the test data is to be loaded, it is necessary to turn the enable signal E to the L level. This closes the AND gates G 7a and G 8a so as to inhibit passage of the input data J and K therethrough; and the AND gate G₉ is opened so that the test data D passes through the AND gate G₉ and the NOR gate G 6a to be input to the NAND gates G₄ and G₅ at the input stage of the pre-stage logic circuit 4. Thus, instead of the first and second input data J and K, the test data D is input to the J-K flip-flop. Therefore, the outputs Q and Q of the J-K flip-flop are determined by the test data D. That is, the test data D is loaded into the flip-flop. When a serial shift register or a binary counter is formed by connecting a number of flip-flops each consisting of a J-K flip-flop such as shown in Fig. 2, the test data D is supplied from the output Q or Q of a pre-stage J-K flip-flop not shown in Fig. 2. Below, the term "flip-flop" is used to indicate a flip-flop with data loading function embodying the present invention. Figure 4 shows a logic circuit according to a second embodiment of the present invention. The difference between Fig. 2 and Fig. 4 is that, in place of the single clock signal CK in Fig. 2, two clock signals CKA and CKB are supplied to the J-K flip-flop shown in Fig. 4. Because of this difference, the NAND gate G 3a has three inputs and the NAND gate G 4a has four inputs. The clock signals CKA and CKB are supplied to the NAND gates G 3a and G 4a . The clock signal CKA is used for a usual J-K flip-flop operation, and the clock signal CKB is used for loading the test data D. In a synchronous logic circuit, it will not always be necessary to include two clock signals. However, in an asynchronous logic circuit such as a binary counter, two clock signals are indispensable for loading the test data D. Figure 5 shows a symbol marking for the logic circuit shown in Fig. 4. If the inverter gate G₁₁ is omitted, the logic circuit shown in Fig. 2 or Fig. 4 will become a J- K flip-flop (instead of a J-K flip-flip). Figure 6 shows an example of a four-bit binary counter constructed by J- K flip-flops each consisting of a logic circuit such as shown in Fig. 4 except that the inverter gate G₁₁ is omitted. In Fig. 6, 10A to 10D are the above-mentioned J- K flip-flops with data loading functions. The first input data J of the first stage flip-flop 10A is fixed at the H level and the second input data K is fixed at the L level. The first input terminal J of the second-stage flip-flop 10B is connected to the noninverted output terminal QA of the first-stage slip-flop 10A. The second input terminal K of the flip-flop 10B is connected through an inverter G₁₂ to the first input terminal J. The second input K of the third-stage flip-flop 10C is a NAND of the noninverted output QA of the first-stage flip-flop 10A and the noninverted output QB of the second-stage flip-flop 10B; and the first input terminal J is an inversion thereof. The second input terminal K of the fourth-stage flip-flop 10D is a NAND of the noninverted output QA of the first-stage flip-flop 10A, the noninverted output QB of the second stage 10B and the noninverted output QC of the third stage 10C, and the first input is the inversion thereof. G₁₃ and G₁₅ are NAND gates; and G₁₂ , G₁₄ and G₁₆ are inverters. The test data terminal D of the first-stage flip-flop 10A receives a test signal Sin; and the test data terminals D of the second-stage and the subsequent flip-flops are the inverted outputs of the pre-stage flip-flops. The operation of the binary counter shown in Fig. 6 is explained with reference to a time chart shown in Fig. 7A through 7H. When the enable signal E shown in Fig. 7A is at the H level, J and K inputs are valid so that a usual counter mode is effected in which, since the J input of the first-stage flip-flop 10A is "1" and the K input is "0", the noninverted output QA is inverted every time the clock signal CKA rises as shown in Fig. 7E. In the second-stage flip-flop 10B, the J input is the same as the output QA and the K input is the inversion of the J input. Therefore, when the QA is "1", the output QB is inverted every time the clock signal CKA rises, and when the QA is "0", the output QB is not changed even when the clock signal CKA rises, as shown in Fig. 7E. In the third-stage flip-flop 10C, when the outputs QA and QB are both at the high level H, the J input of the flip-flop 10C becomes "1" so that the noninverted output QC thereof is inverted by the rise of the clock signal CKA as shown in Fig. 7G. In the same way, in the fourth-stage flip-flop 10D, the noninverted output QD becomes as shown in Fig. 7F. As will be apparent from these outputs QA to QD, the flip-flops 10A to 10D constitute a binary counter. Next, when the enable signal E is turned to the L level, the D inputs of these flip-flops 10A to 10C become valid so that a test mode is effected. In the test mode, the test clock signal CKB is supplied to the binary counter. An explanation of this is given with reference to the time chart shown in Figs. 7A to 7H. When the input test data Sin is at the H level, the output QA of the first-stage flip-flop 10A is turned to the H level by the rise of the test clock signal CKB, and is kept in this state from thereon. The outputs QB, QC, ... of the flip-flops of the second-stage, third-stage, ... are made H by the second, the third, ... rises of the test clock signal CKB, and are kept in these states from thereon. When the input test data Sin is turned to the L level, the output QA is turned to the L level by the rise of the test clock signal CKB; the QB is turned to the L level by the next rise of the test clock signal CKB; and so forth, so that the test data Sin(here at the H level) is shifted by one stage of flip-flops each time the test clock signal CKB rises, as illustrated in Figs. 7A to 7H. In operation as a counter, 2 m clocks are necessary to change the output of the m-stage flip-flop (m = 1, 2, 3, ...). By contrast, in the test mode of operation, only m clocks are necessary to change the output of the m-stage flip-flop. Accordingly, the test mode is suitable when data is to be input from the first-stage input to the m-th stage of a number of flip-flops connected in cascade. In the embodiment shown in Fig. 6, the two clock signals CKA and CKB may be replaced by the single clock signal CK, according to an embodiment of the present invention. In this case, the flip-flops 10A to 10D should be replaced by flip-flops which are identical with the J- K flip-flop 1a shown in Fig. 4 except that the inverter G₁₁ is omitted. For general purposes, however, it is convenient to provide the two clock signals CKA and CKB which are independent or each other, because many logic circuits are asynchronous. Figure 8 shows an example of an asynchronous logic unit. In Fig. 8, logic circuits 11A through 11C are operated by clock signals CK a , CK b , and CK c , respectively. These clock signals CK a to CK c are different from each other. The output of the logic circuit 11A is connected to the input of the logic circuit 11B, and the output of the logic circuit 11B is connected to the logic circuit 11C. Thus, the logic circuits 11A through 11C (each, for example, a data loading flip-flop embodying the invention) constitute an asynchronous logic unit. To effect the above-mentioned test mode operation, a common clock signal is necessary. Therefore, the test clock signal CKB is commonly supplied to these logic circuits 11A to 11C. Figure 9 shows a synchronous logic circuit according to a still another embodiment of the present invention. In Fig. 9, each of the flip-flops 10E to 10F is for example the same as the J-K flip-flop with data loading function shown in Fig. 2 having the single clock signal terminal CK. Test data DA to DD are independently supplied to the respective flip-flops 10E to 10F; the enable signal E is commonly supplied to these flip-flops; and the outputs Q of the flip-flops are inspected in parallel in the test mode. Thus, to test each flip-flop, no additional switching circuit is necessary externally of the flip-flop. As described above, according to the present invention, since a J-K flip-flop has a data loading function, a serial shift register circuit can be constructed so that a test of a complex logic circuit can be easily carried out. Accordingly, a fault diagnosis of a logic circuit is easy and thus a highly reliable circuit can be provided. Also, since the switching circuit for the data loading is simple, the flip-flop circuit as a whole can be constructed to be small and the integration degree can be increased. Further, since the number of logic gates is reduced, the delay time of both the usual operation and the test operation is shortened. It should be noted that the difference between the J-K flip-flop and the J- K flip-flop is not important in the present invention. Further, the present invention is not restricted to the edge-trigger type flip-flop. Any type of J-K flip-flop may be applicable to the present invention. Still further, logic circuits embodying the present invention are not restricted to a counter or a shift register. Any logic circuit including J-K flip-flops may be applicable to the present invention.

Claims: A logic circuit having a test data loading function, comprising at least one J-K flip-flop; said J-K flip flop comprising:- a first-stage logic circuit having a first input terminal (J) for receiving first input data, a second input terminal (K) for receiving second input data, a test data terminal (D) for receiving test data, an enable terminal (E) for receiving an enable signal, and an output (O₁); and a second stage logic circuit having an input (I) connected to the output (O₁) of said first-stage logic circuit and further having a clock signal input terminal (CK) for receiving a clock signal, a noninverted signal output terminal (Q), and an inverted signal output terminal ( Q ); said first-stage logic circuit being operable to select, in response to said enable signal applied to said enable terminal, either said test data or said first and second input data, the selected data being latched in said second-stage logic circuit in response to said clock signal applied to said clock signal terminal; characterised in that:- said second-stage logic circuit comprises a pre-stage logic circuit (G₃, G₄ and G₅) and a final-stage logic circuit (G₁ and G₂), the output of said first-stage logic circuit being connected to the input of said pre-stage logic circuit, the outputs of said pre-stage logic circuit being connected to the inputs of said final-stage logic circuit, and the outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal (Q) and to said inverted signal output terminal ( Q ); and in that:- said first-stage logic circuit comprises:- a first AND gate (G 7a ) having four inputs respectively connected to said noninverted signal output terminal (Q), to said second input terminal (K) through an inverter (G₁₁), to said enable terminal (E), and to one of the outputs of said pre-stage logic circuit; a second AND gate (G 8a ) having four inputs respectively connected to said first input terminal (J), to said enable terminal (E), to said inverted signal output terminal ( Q ), and to said one of the outputs of said pre-stage logic circuit; a third AND gate (G₉) having three inputs respectively connected to said test data terminal (D), to said enable terminal (E) through an inverter (G₁₀), and to said one of the outputs of said pre-stage logic circuit; and a NOR gate (G 6a ) having three inputs respectively connected to the outputs of said first, second and third AND gates and having an output connected to said input of said second-stage logic circuit. A logic circuit as set forth in claim 1, wherein said final-stage logic circuit comprises cross-coupled first and second NAND gates (G₁ and G₂), and said pre-stage logic circuit comprises a third NAND gate (G₃) having two inputs and an output, a fourth NAND gate (G₄) having three inputs and an output, and a fifth NAND gate (G₅) having two inputs and an output, said clock signal terminal being connected to one of the inputs of said third NAND gate and to one of the inputs of said fourth NAND gate, the output of said first-stage logic circuit being connected to another one of the inputs of said fifth NAND gate and to another one of the inputs of said fourth NAND gate, the output of said third NAND gate being connected to still another one of the inputs of said fourth NAND gate and to another one of the inputs of said fifth NAND gate. A logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising:- a first-stage logic circuit having a first input terminal (J) for receiving a first input data, a second input terminal (K) for receiving a second input data, a test data terminal (D) for receiving a test data, an enable terminal (E) for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal (CKA) for receiving a first clock signal, an output terminal (Q), and an inverted signal output terminal ( Q ); said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal; characterised in that:- said second-stage logic circuit further comprises a second clock signal input terminal (CKB) for receiving a second clock signal, the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal. A logic circuit as set forth in claim 3, wherein said second-stage logic circuit comprises a pre-stage logic circuit (G₃, G₄ and G₅) and a final-stage logic circuit (G₁ and G₂), the output of said first-stage logic circuit being connected to the input of said pre-stage logic circuit, the outputs of said pre-stage logic circuit being connected to the inputs of said final-stage logic circuit, and the outputs of said final stage logic circuit being respectively connected to said noninverted signal output terminal (Q) and to said inverted signal output terminal ( Q ). A logic circuit as set forth in claim 4, wherein said first-stage logic circuit comprises:- a first AND gate (G 7a ) having four inputs respectively connected to said noninverted signal output terminal (Q), to said second input terminal (K) through an inverter (G₁₁), to said enable terminal (E), and to one of the outputs of said pre-stage logic circuit; a second AND gate (G 8a ) having four inputs respectively connected to said first input terminal (J), to said enable terminal (E), to said inverted signal output terminal ( Q ), and to said one of the outputs of said pre-stage logic circuit; a third AND gate (G₉) having three inputs respectively connected to said test data terminal (D), to said enable terminal (E) through an inverter (G₁₀), and to said one of the outputs of said pre-stage logic circuit; and a NOR gate (G 6a ) having three inputs respectively connected to the outputs of said first, second and third AND gates, and having an output connected to said input of said second-stage logic circuit. A logic circuit as set forth in claim 4 or 5, wherein said final-stage logic circuit comprises cross-coupled first and second NAND gates (G₁ and G₂), and said pre-stage logic circuit comprises a third NAND gate (G₃) having three inputs and an output, a fourth NAND gate (G₄) having four inputs and an output, and a fifth NAND gate (G₅) having two inputs and an output, said first and second clock signal terminals respectively being connected to two of the inputs of said third NAND gate and to two of the inputs of said fourth NAND gate, the output of said first-stage logic circuit being connected to another one of the inputs of said fifth NAND gate and to another one of the inputs of said fourth NAND gate, the output of said third NAND gate being connected to still another one of the inputs of said fourth NAND gate and to another one of the inputs of said fifth NAND gate. A logic circuit as set forth in claim 1 or 2, comprising a synchronous logic unit including a plurality of flip-flops, each of said flip-flops being constituted by a said J-K flip-flop, all of said clock signal terminals being commonly connected, and all of said enable terminals being commonly connected. A logic circuit as set forth in any of claims 3 to 6, comprising an asynchronous logic unit including a plurality of flip-flops, each of said flip-flops being constituted by a said J-K flip-flop, all of said second clock signal terminals being commonly connected, and all of said enable terminals being commonly connected.

Inventors: SUGIHARA, TAKANORI
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H03K3
IPC codes: G01R31, H03K3, H03K19