PHASE DETECTION CIRCUIT

Abstract: A phase detection circuit for detecting the difference in phase between an analog signal having clock components and a reference clock signal, includes an analog-to-digital converter for sampling the analog signal at the frequency of the reference clock signal and providing a k-bit first digital signal, a delay cir­ cuit means for sampling the first digital signal at a frequency equal to one half the frequency of the reference clock signal providing a k-bit digital signal, and a multiplier means for mul­ tiplying the first digital signal by the second digital signals to provide a data representative of the phase difference.

Description: BACKGROUND OF THE INVENTION The present invention relates to a phase detection circuit for use with, for example, a demodulator which is adapted for demodulation of PSK (Phase Shift Keying), QAM (Quadrature Amplitude Modulation) and other digital modulated carrier waves. More particularly, the present invention is concerned with a phase detection circuit for detecting a difference between an analog signal which contains a clock signal component and a reference clock signal. A prior art phase detection circuit of the type described is made up of a reference clock generator, a timing extracting circuit, a set-reset flip-flop (SR FF), a counter, and a high-rate clock generator. The output of the reference clock generator is coupled to a reset input of the SR FF and a reset input of the counter. The timing extracting circuit extracts a timing signal out of an analog signal which contains a clock signal, the timing signal being applied to a set terminal of the SR FF. The SR FF compares the phase of the timing signal with that of the reference clock signal which is fed to the reset input thereof, thereby producing a pulse signal representative of a phase difference between the two signals. Only when the pulse signal outputted by the SR FF is high level, the counter counts up clock pulses from the high-speed clock generator so as to produce the phase difference as a digital value. The above-described type of phase detection circuit is not readily practicable, however, because accuracy of phase difference measurement cannot be enhanced unless the high-rate clock has a sufficiently greater value (usually more than 30) than the modulation rate and, therefore, unless a demodulator and others are operable at considerably high processing rates. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a phase detection circuit capable of operating at a processing speed which is two times higher than the modulation rate of analog signals. A phase detection circuit to which the present invention is applicable, detects the difference in phase between an analog signal including clock components, and a reference clock signal. The phase detection circuit of the present invention comprises an analog-to-digital converter for sampling the analog signal at the frequency of the reference clock signal and providing a k-bit first digital signal, a delay circuit means for sampling the first digital signal at a frequency equal to one half the frequency of the reference clock signal and providing a k-bit digital signal, and a multiplier means for multiplying the first digital signal by the second digital signals to provide a data representative of the phase difference. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following description taken with the accompanying drawings: FIG. 1 is a block diagram of a prior art phase detection circuit; FIGS. 2A to 2E are timing charts demonstrating the operation of the circuit of FIG. 1; FIG. 3 is a block diagram showing a phase detection circuit in accordance with the present invention; FIGS. 4A - 4F are timing charts representative of operation of the circuit shown in FIG. 3; FIG. 5 is a plot showing a phase detection characteristic particular to the circuit of FIG. 3; FIG. 6 is a block diagram of another embodiment of the present invention; FIG. 7 is a plot showing a phase detection characteristic of the circuit shown in FIG. 6; and FIG. 8 is a block diagram representative of an application of the present invention to a demodulator. DESCRIPTION OF THE PREFERRED EMBODIMENTS To better understand the present invention, a brief reference will be made to a prior art phase detection circuit, shown in FIG. 1. The operation of the prior art circuit is shown in FIGS. 2A to 2E. An analog signal A (FIG. 2A) is, for example, a coherent detection output of a demodulator, not shown. A timing extracting circuit 1 extracts a timing signal B (FIG. 2B) which, in this example, is a zero-crossing timing signal associated with the analog signal A. The timing signal B is applied to a set-reset flip-flop (SR FF) 2 which then detects a difference between the timing signal B and a reference clock signal C (FIG. 2C), which is outputted by a reference clock generator, not shown. As a result, the SR FF 2 produces a signal D (FIG. 2D) which is representative of a phase difference between the signals B and C. The phase difference signal D carries phase information in each of its pulse widths and, therefore, each pulse width must be integrated to determine a phase difference. So long as the demodulator is of an analog processing type, the integration may be implemented with an integrator. However, when it comes to a digital processing type demodulator, it is required that digital processing be employed for the integration. In this particular example, a counter 3 is used to effect the integration. The counter 3 is constructed to count up only when the logical level of the signal D is a ONE responsive to a high rate clock signal which is fed thereto from a high-rate clock generator, not shown. The counter 3 is initialized (usually to zero) by the reference clock signal C. In this condition, the counter 3 produces outputs E as shown in FIG. 2E. The high-rate clock adapted to drive the counter 3 as stated above must have a value (usually more than 30) which is sufficiently higher than the modulation rate or the reference clock, otherwise deteriorating phase resolution performance. This in turn requires that the processing rate of the demodulator be increased to an impractical value. Referring to FIG. 3, a phase detection circuit embodying the present invention is shown which constitutes a solution to the above-descussed problem. An analog signal A which has been modulated at a rate fs is applied to an analog-to-digital (A/D) converter 4. Also applied to the A/D converter 4 is a clock signal (fr) B having a two times higher rate than the signal A, i.e. 2fs. The A/D converter 4 quantizes the analog signal A to produce a k-bits (k being a positive integer) digital signal C responsive to the clock signal B. The digital signal C outputted by the A/D converter 4 is sampled and delayed by a k-bit D type flip-flop (D FF) 5 at a rate fs. In this particular embodiment, the clock signal B whose rate is 2fs is phase-locked to a reference clock signal having a rate fs and is halved by a frequency divider 6 to provide a clock signal (fs) D. This clock signal D is applied to a clock input (CK) of the D FF 5. A multiplier 7 multiplies a delayed output E of the D FF 5 and the k-bits quantized signal C, the resultant product F being delivered as a phase difference signal. The multiplier 7 may be implemented with a digital adder or a read only memory (ROM) storing various products of C x E which may be addressed by the signals C and E. The D type flip-flop may be replaced by a shift register. Referring to FIGS. 4A to 4F, the signals A to F appearing in various portions of FIG. 3 as stated above the shown in timing charts. The waveform of the output C of the A/D converter 4 (FIG. 4C) is represented on a PAM (Pulse Amplitude Modulation) basis for simplicity. As shown in FIG. 4E, among the signals sampled by the A/D converter 4 at the rate 2fs, the odd sampled signal, for example, constitute the signal E which is sampled and delayed by the D FF 5 at the rate fs. Assuming that the demodulated analog signal which is synchronous to the reference clock is d(t) = cos(πfst), the even and the odd sampled signals which were sampled by the A/D converter 4 at the rate 2fs are expressed as follows: Event (t) = Feven (nT + t0) = cos{nπ + (π/T)t0} .... Eq. (1) Fodd (t) = Fodd (nT + T/2 + t0) = cos{ nπ + π/2 + (π/T) t0} = - sin {nπ + (π/T) t0} .... Eq. (2) where T is 1/fs, and t0 is a time gap associated with a phase difference ϑ between the reference clock signal and the analog signal A. The multiplier 7 multiplies the even and the odd sampled signals Feven (t) and Fodd (t). Hence, based on the Eqs. (1) and (2), the output F of the multiplier 7 is produced as: F = cos{nπ + (π/T)t0} x (-1) sin{nπ + (π/T)t0} = (-1/2) [sin{2nπ + (2π/T)t0} + sin 0] = (-1/2) sin ϑ .... Eq. (3) where ϑ is 2πt0/T. It will be apparent from the Eq. (3) that the circuitry shown in FIG. 3 is capable of determining a phase difference ϑ between the reference clock signal (fr) and the analog signal A, i.e. clock signal contained in the analog signal A. Such a phase detection characteristic is plotted in FIG. 5. Assume that among the k-bits of output digital signal of the A/D converter 4 the most significant digit (MSD) is the data bit representative of a polarity (±) (e.g. a ONE representing the positive polarity and a ZERO the negative polarity), and the remaining lower (k - 1) digits are rerpesentative of a magnitude of the signal. Then, as shown in Fig. 6, the multiplier 7 of Fig. 1 can simply be implemented with an Exclusive-OR gate 8 only. Specifically, in FIG. 6, the MSD of the k-bits digital signal C is applied to one input of the Exclusive-OR gate 8, and the MSD of the delayed output E of the D FF 5 to the other input of the gate 8. The output of the gate 8 in combination with the output E of the D FF 5 except for the MSD, i.e., remaining lower (k - 1) bits to produce the phase difference signal F. In this condition, while the MSD of the k-bits output F which is the output of the gate 8 is representative of a polarity of the phase difference data, the remaining lower (k - 1) bits are representative of a magnitude of phase difference. Describing the principle of this particular construction, the delayed signal E which has been sampled by the D FF 5 at the rate fs is the odd sampled signal Fodd (t) which is represented by the Eq. (2). The lower (k - 1) bits of the signal E contain data whose magnitude corresponds to the phase difference ϑ = (π/T), which is to be obtained. Meanwhile, the MSD of the k-bits digital signal C is representative of the polarity of the analog signal A0 which has appeared at the instant of sampling. Therefore, at the instant when the gate 8 computes Exclusive-OR, the MSD is representative of a polarity (±) of the even sampled signal Feven (t) which is produced by the Eq. (1). Because the magntidue of the phase difference ϑ is determined in terms of the magnitude of the signal Fodd (t) and the polarity in terms of the product of MSDs of nearby odd sampled signals, the polarity is attainable in terms of the output of the gate 8. The fact discussed above will be presented using numerical expressions. A signal produced by determining a polarity of the signal of the Eq. (1) is expressed as sgn{cos (nπ + πt0/T)} The product of this signal and the signal of the Eq. (2) derives an expression F = sgn{cos (nπ + πt0/T)} x (-1) sin[nπ + (π/T) t0} = - sin (πt0/T) .... Eq. (4) The phase detection characteristic of the circuit shown in Fig. 6 is plotted in FIG. 7. Referring to FIG. 8, the phase detection circuit of FIG. 3 which is applied to a demodulator is shown in a block diagram. As shown, the demodulator includes coherent detectors 101 and 102 to which a modulated carrier wave such as a PSK wave or a QAM wave is applied. The detectors 101 and 102 detect the input carrier wave responsive to a carrier wave which is outputted by a carrier wave generator 104 and then passed through a π/2 phase shifter 103 and to the carrier wave which is not passed through the phase shifter 103, respectively. The demodulated analog signals outputted by the detectors 101 and 102 respectively are applied to A/D converters 105 and 106 to be thereby converted each to a k-bits digital signal. The outputs of the A/D converters 105 and 106 are routed to a calculator 109 to be converted to an m-bits recovered digital signal while being subjected to error correction and other signal processings. A circuit 110 which is constructed as shown in FIG. 3 is adapted to detect a phase difference between the clock signal fc contained in the output analog signal of the detector 102 and the reference clock signal fr (= 2fs) from a reference clock generator 108. The reference clock fr is routed through a variable phase shifter 107 to a frequency divider 6 and sampling terminals of the A/D converters 105 and 106. The frequency divider 6 halves the frequency of the clock signal fr. Each of the converters 105 and 106 converts an analog signal value at a sampling point to a k-bits digital signal. The variable phase shifter 107 is controlled by a multiplier 7 of the circuit 110 such that the phase difference between the clock signals fc and fr converges to zero. In summary, it will be seen that the present invention provides a phase detection circuit which processes a modulated carrier wave by use of a clock signal whose rate is double the modulation rate and, therefore, makes it possible to use a low rate clock, compared to a prior art circuit, thereby increasing the operation rate of a demodulator.

Claims: A phase detection circuit for detecting the difference in phase between an analog signal including clock components, and a reference clock signal, comprising: an analog-to-digital converter (4) for sampling the analog signal at the frequency of the reference clock signal (B) and providing a k-bit first digital signal (C); a delay circuit means (5) for sampling the first digital signal at a frequency equal to one half the frequency of the reference clock signal and providing a k-bit digital signal; and a multiplier means (7) for multiplying the first digital signal by the second digital signal to provide a data representative of the phase difference. A phase detection circuit as claimed in Claim 1, wherein the delay circuit means comprises a D type flip-flop (5). A phase detection circuit as claimed in Claim 1, wherein the multiplier means comprises an Exclusive-OR gate (8) responsive to the most significant digits of the first and second digital signals; the output of the Exclusive-OR gate and the remaining lower (k - 1) digits of the second digital signal constituting the phase difference data. A phase detection circuit as claimed in Claim 1, further comprising a variable phase shifter (107) responsive to the phase difference data, for phase-shifting the reference clock signal and supplying the phase-shifted reference clock signal to the analog-to-digital converter. A phase detection circuit as claimed in Claim 4, further comprising coherent detector means (101 and 102) for demodulating a digital-modulated carrier wave and providing the analog signal. A phase detection circuit as claimed in Claim 5, wherein the digital-modulated carrier wave is a PSK wave. A phase detection circuit as claimed in Claim 5, wherein the digital-modulated carrier wave is a QAM wave.

Inventors: OTANI, SUSUMU
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H04L7
IPC codes: H03D3, H04L27, H03D13, H04L7