UNIVERSAL PACKAGE

Abstract: A memory device comprising a package (10) which has a plurality of terminals (12), at predetermined positions for in­ specting program, and switching means (30) which is arran­ ged in the package (10) and which switches the first and second operations. In the first operation, a rewritable read-­ only memory is connected to the terminals for inspecting pro­ gram. In the second operation, inspection means (8) is con­ nected to the terminals for inspecting program. In the first operation of the piggyback type, a rewritable ROM (EPROM) is connected to the terminals for program inspection of the package. In the second operation of the evaluator type, in­ spection means is connected to the terminals for program in­ spection of the package and is used as switching means, so that the operation can be automatically switched by a multi­ plication select circuit. Therefore the signal lines can be multi­ plexed to a great extent, and the piggyback-type chip and the evaluator-type chip can be used as the same device. Further, the same package can be used to accommodate the chips. This eliminates the need of separately developing the piggy­ back-type chip and the evaluator-type chip, and to separately produce the packages, contributing to shorten the time for development and to reduce the cost of development. More­ over, the piggyback-type chip, the evaluator-type chip and the mask ROM mounted chip can be made of the same pin arran­ gements. Therefore, the program can be evaluated by the evaluator-type chip with the mask ROM mounting board which is a final product, without requiring the traditionally emplloyed interface substrate or the like.

Description: TECHNICAL FIELD This invention relates generally to a data storage apparatus and, more particularly, to a universal package detachably connected to a single-chip microcomputer for use as a development tool. BACKGROUNT ART Japan patent application N° A-57072362 and French patent application N° A-2 498 782 are cited. JP-A-57 07 2362 discloses a semiconductor device wherein to manage parts of the device easily, managing information circuitry and switch controlling means are provided between internal parts of said device and some pins. The problem of connecting an interface to said semiconductor device in order to connect a different external apparatus thereto is not addressed. FR-A-2 498 792 teaches an emulator adapter wherein test memory means and microprocessor means including switching means responsive to a particular instruction, are provided an a same board. Said emulator adapter is not foreseen to be used in common with a piggyback chip. A single-chip microcomputer is typically shipped with a program provided in the final product in the form of a mask-type, read only memory (ROM). The mask-type, read only memory is incapable of being rewritten because the information stored in the ROM is written to the ROM during the manufacturing process using a mask. Therefore, to allow developing and evaluating of a program, an evaluator-type chip can be used with a piggyback-type chip. In general bus which are led out to the outside and connected to a rewritable and erasable EPROM mounted to the upper portion of that chip. The evaluator-type chip requires, in addition to the program address bus, the data bus, and the like, a control signal and the like at the outside for being capable of single-step program evaluation. The evaluator-type chip is used in an early stage of the development of the program to check the operation of the microcomputer, and the piggyback type is used in a later stage to check the actual operation of the program. Fig. 5 schematically illustrates input and output pin configurations of a prior art mask-type ROM chip, a piggyback-type chip, and an evaluator-type chip. Reference numeral 1 designates a package of the mask ROM-type chip, reference numeral 2 designates a package of the piggyback-type chip, and reference numeral 3 designates a package of the evaluator-type chip. On a rear surface of the piggyback-type chip package 2, there are mounted a plurality of program testing terminals 4 that are used to connect the EPROM to the piggyback-type chip package. The evaluator-type chip 3 has more pins than either the mask-type ROM chip package 1 of the piggyback-type chip package 2. The additional pins of the evaluator-type chip 3 are needed to connect pins such as a terminal for an external memory, a terminal for a control signal, and so on to the package of the evaluator chip 3. Accordingly, although package 1 and 2 are the same relative to the physical placement of the pins, that is, pin arrangement, and also in the manner in which they are connected to the internal circuitry, that is, program pin configuration, package 3 is different from packages 1 and 2 in pin arrangement and configuration of package 2 allows the packages 1 and 2 to be loaded on a final product board. However, package 3 cannot be loaded on a final product board. In the prior art, when the evaluation of a microcomputer is made by using the evaluator-type chip, as shown in Fig. 6, an interface board 6 is necessary because of the incompatibility of the terminal of the incompatibility of the terminals of the piggyback-type chip 2 with those of the evaluator-type chip of Fig. 5. Therefore, in the prior art, an interface board is required for use with the product board 5. The product board 5 and the interface board 6 are connected with a flat cable 7 which has connections at either end of the cable, the evaluator-type chip package 3 is mounted using the evaluator chip terminals at a predetermined position on the interface board 6. The evaluator-type chip package 3 and a development tool or insert kit emulator 8, which is a debugger, and the like are connected using a flat cable 9 having connectors at either end of the cable. In the prior art, since the piggyback-type chip and evaluator-type chip require different input and output signals, they are designed independently. Further, since the packages thereof are different as described above, packages of different types must be constructed, respectively. Among the various programs that result from the development of independent designs is that the program development requires much time, and the manufacturing cost is increased. Further, the evaluator-type chip cannot be directly incorporated into the board of the final product which has mounted thereon the microcomputer so that another interfaces board and so on must be provided as described above. In view of this, it is desirable to provide, in accordance with the invention, a universal package which is fully compatible with the final product board and the evaluator-chip to obviate the cumbersome arrangement of using an interface board because of incompatibility of the terminals of the piggyback-type chip and the evaluator-type chip. Therefore, the piggyback-type chip and the evaluator-type chip are not necessarily developed separately. DISCLOSURE OF INVENTION A universal package (10) according to this invention is claimed in claim 1. It comprises a plurality of testing terminals 12 at predetermined positions and a switching circuitry 30 located within this package 10 for switching first and second operations, wherein in the second operation the testing terminals are connected with a rewritable read only memory, while in the first operation the above-mentioned program testing terminals are connected with testing apparatus 8. In the first operation, the testing apparatus, such as a development tool 8, is connected to the testing terminal 12 of the package 10 so as to allow the package to operate as the evaluator type. In the second operation, the rewritable read only memory 11 is connected to the testing terminals 12 of the package 10 so as to allow the package to operate as the piggyback-type chip. Therefore, the same package 10 can be used with both the evaluator-type chip and the piggyback-type chip. BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a construction diagram showing an embodiment of this invention, Fig. 2 is a construction diagram showing one example of a main portion of this invention, Figs. 3 and 4 are diagrams used to explain the operation of Fig. 2, Fig. 5 is a schematic representation illustrating input and output pins of respective conventional chips and Fig. 6 is a diagram showing a connection relationship of a prior art evaluator type chip. BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of this invention will hereinafter be described in detail with reference to Figs. 1 to 4. Fig. 1 shows one embodiment of this invention. Referring to the figure, although at the final shipment stage of the final product board 5, such mask ROM mount-type chip 1 as shown in Fig. 5 is mounted thereon, in the early stage of the development, the piggyback type chip is mounted thereon to thereby check the development. Then, the evaluator type chip is mounted thereon to thereby carry out the evaluation checking. Here, there is shown such a state that the package 10 which is used in common as both the piggyback type chip and the evaluator type chip is detachably mounted on the final product board 5. The package 10 is provided on its rear surface with the plurality of program testing terminals 12 which are connected with an EPROM 11 when it is operated as the piggyback type chip while which are connected with the other end of the flat cable 9 led out from the development tool 8 when it is operated as the evaluator type chip. The switching between the program testing terminals 12 of the package 10 being operated as the piggyback type and the evaluator type is carried out by a signal multiplexing and selecting circuit 30 that is used as switching means shown in Fig. 2. That is, in Fig. 2, reference numeral 20 designates an address terminal, reference numeral 21 designates an address, command, data and bus multiplex terminal, reference numeral 22 designates a command, data and control signal multiplex terminal, reference numeral 23 designates a selector for selecting the command and the data derived from the multiplex terminals 21 and 22, reference numeral 24 designates an input terminal which is supplied with a signal used to switch the piggyback type (PG) and the evaluator type (EV), and reference numeral 25 designates an input terminal which is supplied with a signal used to switch the normal program execution mode and the program stop mode in the single step operation when the package is operated as the evaluator type. The address terminal 20 and the multiplex terminals 21 and 22 correspond to the program testing terminals 12 on the package 10. When a signal of, for example, "0" is supplied to the terminal 24, the multiplex terminals 21 and 22 and the selector 23 are respectively switched so as to operate as the piggyback type. Then, the multiplex terminal 21 delivers a program address from the side of a bus 26 as shown in Fig. 3, the multiplex terminal 22 takes in the command and the data read out of the ROM and the selector 23 is operated so as to allow the command and the data derived from the multiplex terminal 22 to be supplied to the side of a bus 27. The address terminal 20 is served, regardless of the signal applied to the terminal 24, as the address terminal which delivers the program address from the bus 26 in either operation of the piggyback type and the evaluator type. Next, when a signal of, for example, "1" is supplied to the terminal 24, the multiplex terminals 21 and 22 and the selector 23 are switched so as to operate as the evaluator type. Then, the multiplex terminal 22 is served as the input and output terminals of a reference clock, an operation control signal and the like. On the other hand, the multiplex terminal 21 is switched between two operations on the basis of whether or not a hold (HOLD) signal is supplied to the terminal 25. For example, when the hold signal is not supplied to the terminal 25, it is placed in a state to carry out the normal program execution operation. Then, it delivers the program address of the bus 26 during the period of first and third clocks M0 and M2 in one machine cycle formed of clocks M0, M1, M2 and M3, while it takes in the command and the data read out from the ROM during the period of the second and fourth clocks M1 and M3. The thus taken-in command and data are delivered through the selector 23 to the side of the bus 27. When on the other hand the hold signal is supplied to the terminal 25, the multiplex terminal 21 is placed in the program stop operation mode upon the single step operation. Thus, it delivers the content of an accumulator (not shown) through an internal bus 28 during the period of the first clock M0; it delivers the content of a temporary register (not shown) through the internal bus 28 during the period of the second clock M1; it delivers a status flag and the content of a program counter (not shown) through the internal bus 28 during the period of the third clock M2; and during the period of the clock M3 shown in Fig. 4, it delivers the content of the program counter through the internal bus 28. The above cycle is repeated upon the stop mode. Fig. 4 illustrates the data contents of the multiplex terminal 21 when the package is operated as the above mentioned evaluator type. Fig. 4A shows the data content of the multiplex terminal 21 when the program runs in the normal state, that is, when the normal program is executed. While, Fig. 4B illustrates the data content of the multiplex terminal 21 upon the stop modes, such as, the single step operation mode and the like, that is, when the program is stopped in the single step operation. When the package is operated as the piggyback type, the EPROM is connected to the address terminal 20 and the multiplex terminals 21 and 22. While, when the package is operated as the evaluator type, the development tool 8 is connected through the flat cable 9 to the address terminal 20 and the multiplex terminals 21 and 22 so that if the level of the signal supplied to the terminal 24 is switched, the package 10 can be used in common as both the piggyback type and the evaluator type.

Claims: A universal package (10) for a microcomputer chip detachably mounted on a microcomputer chip final product board (5) for selectively and detachably connecting said microcomputer chip to testing means (8) or to a rewritable read only memory (11), said testing means being used at an early stage to check the operation of said microcomputer chip and said rewritable read-only memory being used at a later stage in developing and evaluating a program to be stored in a permanent read-only memory to be permanently connected to said microcomputer chip final product board, said universal package being characterized in that it comprises: a plurality of testing terminals (12) for connection selectively to said testing means and to said rewritable read-only memory during successive stages of checking the operation of the microcomputer chip and the evaluation of said program presently in the microcomputer chip and to be subsequently stored in said permanent read-only memory ; and switching means (30) for establishing a first internal electrical configuration in which a first set of said testing terminals are activated when said rewritable read-only memory is connected to said testing terminals and a second internal electrical configuration in which a second set of said testing terminals are activated when said testing means is connected to said testing terminals, said first and second sets of activated terminals being different ; wherein said switching means comprises an input terminal (24) and means responsive to a signal applied to said input terminal, said responsive means being constructed so that when said signal has a first value said responsive means establishes said first internal electrical configuration and when said signal has a second value said responsive means establishes said second internal electrical configuration. A universal package according to claim 1 wherein said switching means comprises means responsive to a digital signal having a first value for establishing said first internal electrical configuration and a second value for establishing said second internal electrical configuration. A universal package according to claim 2 wherein said means responsive to a digital signal applied to said input terminal comprises a first multiplex terminal means (21) and a second multiplex terminal means (22) and selector means (23) being responsive to a state of said digital signal and further comprising bus means (26) connected to said selector means and to said first and second multiplex terminal means, whereby said first and second multiplex terminal means and said selector means cooperate with said testing means during one state of said digital signal and with said rewritable read-only memory in an other state of said digital signal. A universal package according to claim 3 wherein said first multiplex terminal means comprises an operation switching means for switching between a single step operation when a hold signal is applied to said operation switching means and a program execution operation in absence of said hold signal. A universal package according to claim 4 wherein said single step operation is operative during : a first phase of operation of said microcomputer chip for receiving contents of an accumulator at said first multiplex terminal means and sending said contents of said accumulator to said testing means through internal bus mean (28); a second phase of said operation of said microcomputer chip for receiving a content of a temporary register at said first multiplex terminal means and sending said contents of said temporary register to said testing means through said internal bus means (28); a third phase of said operation of said microcomputer chip for receiving a content of a program counter at said first multiplex terminal means and sending a status flag and said contents of said program counter to said testing means using said internal bus means (28); and a fourth phase said operation of said microcomputer chip for receiving the content of said program counter at said first multiplex terminal means and sending said content of said program counter to said testing means. A universal package according to claim 5 wherein said program execution operation is operative during : said first phase of operation of said microcomputer chip and said third phase of operation of said microcomputer chip for receiving a program address from an address means and sending said address to said testing means through said bus means (26); said second phase of operation of said microcomputer chip and said fourth phase of operation of said microcomputer chip for receiving a command signal and a data signal from said read-only memory and sending said command signal and said data signal to said testing means through further bus means (27), connected to said selector means (23).

Inventors: WATANABE, NOBUHISA
Applicants: SONY CORPORATION
Application year: 1986
Main classification: G06F11
IPC codes: G06F15, G06F11, G06F1