Multilevel modulator comprising a compact error correcting code producing unit

Abstract: In a multilevel modulator for use in modulating an input digital signal (S₁) of N levels into a multilevel modulated signal (S₂, the input digital signal is converted by a code converting unit (15) into a major converted signal (S₁₀) for the input digital signal and a minor converted signal (S₂₀) corresponding to the major converted signal. The major converted signal is rearranged into groups each of which consists of a predetermined number of levels smaller than N and which is produced in a time division fashion together with the minor converted signal. A signal producing unit (17) processes each group to produce a Lee-error correcting code sequence. Alternatively, major and minor converted signals are produced on quadrature-phase amplitude modulation of a circular signal arrangement of N-levels to divide the circular signal arrangement into a square signal arrangement and the remaining signal arrangement. In a counterpart multilevel demodulator, an inverse operation is carried out to reproduce the input digital signal.

Description: This invention relates to a multilevel modulator which has an error correcting code producing unit and to a multilevel demodulator for use as a counterpart of the modulator. For the multilevel modulator of the type described, it is desirable that a modulating signal have an increased number of levels. This is because the increased number of levels makes it possible to effectively utilize a carrier level. Therefore, a large-capacity digital radio communication network ordinarily comprises the multilevel modulator. In such a digital radio communication network, a transmission error, namely, a code error, of transmission information is reduced by an error correcting system which makes use of an error correcting code. As the error correcting code, a Lee-error correcting code is well known in the art. The error correcting system is exemplified in an article contributed by Katsuhiro Nakamura of NEC Corporation, namely, the present assignee, to ICC Conference Record, Vol. 4-3 (June 1979), pages 45.4.1 to 45.4.5, under the title of "A Class of Error Correcting Codes for DPSK Channels." With an increase in the modulating signal levels, the error correcting code requires an increased number of bits. Accordingly, the error correcting code producing unit must carry out a large amount of logical operation on producing the error correcting code. As a result, the error correcting code producing unit becomes bulky and expensive. This applies to the multilevel demodulator. US-A-4 077 021 teaches the conversion of a sequence of binary digits into a sequence of discrete signal values of a modulated carrier signal by introducing additional redundant signal values by a convolutional coding operation. This allows an output signal to be transmitted which is suitable for a Viterbi decoder. EP-A-0 103 866 teaches a digital transmission system for deriving a square signal point arrangement. In this system, an input signal is divided into a first bit stream representative of one of quadrants of a phase plane and a second bit stream representative of a location of a signal point in the quadrant. The first bit stream is encoded by a differential encoder into an encoded data stream. The encoded data stream and the second bit stream are encoded by transparent error-correction into a transparent error-correcting code and then modulated by two dimensional multilevel modulation. It is therefore an object of this invention to provide a multilevel modulator which comprises a compact error correcting code producing unit. It is another object of this invention to provide a multilevel modulator which is suitable for high-speed operation. It is a still further object of this invention to provide a multilevel demodulator for use as a counterpart of the multilevel modulator of the type described. These objects are solved with the features of claims 1 and 5. BRIEF DESCRIPTION OF THE DRAWING: Fig. 1 is a block diagram of a multilevel modulator according to a first embodiment of this invention; Fig. 2 is a diagram for use in describing operation of a code converting unit of the modulator illustrated in Fig. 1; Fig. 3 is a block diagram of a multilevel demodulator for use as a counterpart of the multilevel modulator illustrated in Fig. 1; Fig. 4 is a diagram for use in describing operation of an error correcting unit of the demodulator illustrated in Fig. 3; Fig. 5 is a block diagram of a multilevel quadrature-phase amplitude modulator which is a multilevel modulator according to a second embodiment of this invention; Fig. 6 shows a signal point distribution of a conventional multilevel quadrature-phase amplitude modulated signal; Fig. 7 shows a signal point distribution of a quadrature-phase amplitude modulated signal produced by the multilevel quadrature-phase amplitude modulator illustrated in Fig. 5; Fig. 8 is a block diagram of a multilevel quadrature-phase amplitude demodulator for use as a counterpart of the multilevel quadrature-phase amplitude modulator illustrated in Fig. 5; and Fig. 9 is a diagram for use in describing error correcting operation of an error correcting unit of the demodulator illustrated in Fig. 8. DESCRIPTION OF THE PREFERRED EMBODIMENTS: Referring to Fig. 1, a multilevel modulator according to a first embodiment of this invention is for use in modulating an input digital signal S₁ into a multilevel modulated signal S₂. The multilevel modulator comprises a code converting unit 15 supplied with the input digital signal S₁. The input digital signal S₁ is capable of representing at most N levels where N is represented by ( i·2 n + m ) where, in turn, n is an integer which is not smaller than two, m and i are integers which satisfy 0 ≦ m < 2 n and (m + i) ≧ 2 , respectively. The code converting unit 15 is for converting the input digital signal S₁ to a major converted signal S₁₀ of 2 n levels and a minor converted signal S₂₀ which has (i + k) levels where k is equal to zero and one when m is equal to zero and is greater than zero, respectively. When the input digital signal S₁ is a four-bit binary digital signal, it is capable of representing at most sixteen levels (= 2⁴). The code converting unit 15 converts the input digital signal S₁ to the major converted signal S₁₀ of eight levels (= 2³) and the minor converted signal S₂₀ of two levels (= 2¹). In other words, the code converting unit 15 rearranges the levels of the input digital signal S₁ as will later be described in detail. It is understood under the circumstances that n, m, i, and k are equal to three, zero, two, and zero, respectively. The major converted signal S₁₀ is divided into two parts one of which is delivered to a multiplexer 16. The other part is supplied to a signal producing unit 17. Responsive to the major converted signal S₁₀, the signal producing unit 17 produces a single Lee-error correcting code sequence S₃ in the manner described in the conference record cited hereinabove. The multiplexer 16 multiplexes the error correcting signal S₃ and the major converted signal S₁₀ into a major multiplexed signal S₁₁ and the error correcting signal S₃ and the minor converted signal S₂₀ into a minor multiplexed signal S₂₁. A multilevel modulating unit 18 has a code converting function which is complementary to the code conversion of the code converting unit 15. Accordingly, the modulating unit 18 converts the major multiplexed signal S₁₁ and the minor multiplexed signal S₂₁ to a multilevel signal having sixteen levels. Furthermore, the modulating unit 18 modulates a carrier signal C₁ by the multilevel signal and produces the multilevel modulated signal S₂ of sixteen levels. The multilevel modulated signal S₂ is transmitted to a multilevel demodulator through a transmission medium. Referring to Fig. 2, description will be made as regards the code conversion in the code converting unit 15. In the manner exemplified above, it will be assumed that the input digital signal S₁ is capable of having one of zeroth through fifteenth levels 0 to 15. The major and the minor converted signals have zeroth through seventh levels 0 to 7 and zeroth and first levels 0 and 1, respectively. The code converting unit 15 converts the zeroth to the third levels 0 to 3 and the twelfth to the fifteenth levels 12 to 15 of the input digital signal S₁ into the major converted signal S₁₀ of the fourth to the seventh levels 4 to 7 and the zeroth to the third levels 0 to 3, respectively. The code converting unit 15 further converts the fourth to the eleventh levels 4 to 11 of the input digital signal S₁ into the major converted signal S₁₀ of the zeroth to the seventh levels 0 to 7. In other words, the input digital signal S₁ of sixteen levels 0 to 15 is rearranged in the major converted signal S₁₀ by the code converting unit 15 into first and second groups, each of which consists of eight levels 0 to 7. Alternatively, the code converting unit 15 may convert the zeroth to the seventh levels 0 to 7 of the input digital signal S₁ into the major converted signal S₁₀ of the zeroth to the seventh levels 0 to 7 and the eighth to the fifteenth levels 8 to 15 also to the major converted signal S₁₀ of the zeroth through the seventh levels 0 to 7. As shown in Fig. 2, the first group serves to specify eight levels consisting of zeroth through third levels and twelfth through fifteenth levels while the second group serves to specify eight levels consisting of fourth through eleventh levels. In the example being illustrated, (i + k) is equal to two as mentioned before and can determine the number of groups of the major converted signal S₁₀. Accordingly, the major converted signal S₁₀ exemplified in Fig. 1 is rearranged into two groups. The minor converted signal S₂₀ has two levels in correspondence to the two groups of the major converted signal S₁₀. The code converting unit 15 produces the minor converted signal S₂₀ of the zeroth level "0" together with the major converted signal S₁₀ when the input digital signal S₁ takes one of the fourth to the eleventh levels 4 to 11. The code converting unit 15 produces the minor converted signal S₂₀ of the first level "1" when the input digital signal S₁ takes one of the zeroth to the third levels 0 to 3 and the twelfth to the fifteenth levels 12 to 15. Thus, the input digital signal S₁ of sixteen levels is converted into the major converted signal S₁₀ of eight levels and the minor converted signal S₂₀ which has two levels. Referring back to Fig. 1, the signal producing unit 17 carries out a predetermined operation on the major converted signal S₁₀. The predetermined operation is for producing the single Lee-error correcting code sequence S₃. The exemplified single Lee-error correcting code sequence is suitable for correcting a single Lee-error such that a change of either "+1" or "-1" takes place in a data signal of eight levels. Such a change of either "+1" or "-1" can be corrected by adding either "-1" or "+1" modulo 8 to the data signal. This is similar to a double Lee-error correcting code sequence, if the signal producing unit 17 produces the double Lee-error correcting code sequence. In this event, such a double Lee-error can be corrected by adding either "+2" or "-2" modulo 8 to the data signal. Code correction of the single and the double Lee-error correcting code sequences is described in the conference record cited before and has no direct concern with the present invention. Therefore, no description will be made as regards the Lee-error correcting code sequence and the signal producing unit 17 any longer. It may, however, be pointed out that the signal producing unit 17 processes the major converted signal S₁₀ of eight levels rather than directly the input digital signals S₁ of sixteen levels. Therefore, the signal producing unit 17 is operable with a reduced amount of logical operation. The signal producing unit 17 is compact and can carry out the logical operation at high speed. Referring to Fig. 3, a multilevel demodulator is for use as a counterpart of the multilevel modulator illustrated with reference to Fig. 1. The multilevel demodulator is supplied as a demodulator input signal with a multilevel modulated signal which is identical with that illustrated in Fig. 1 as long as no transmission or code error takes place and which is indicated at S₂'. Responsive to the multilevel modulated signal S₂' and a local carrier signal C₂, a demodulating unit 21 carries out multilevel demodulation of the multilevel modulated signal S₂' and code conversion which is complementary to the code conversion in the modulating unit 18 (Fig. 1). As a result, the demodulating unit 21 delivers a major demodulated signal S₁₁' and a minor demodulated signal S₂₁' to an error correcting unit 22. If the multilevel modulated signal S₂' is free from the transmission error, the major demodulated signal S₁₁' and the minor demodulated signal S₂₁' are reproductions of the major multiplexed signal S₁₁ and the minor multiplexed signal S₂₁, respectively. The major demodulated signal S₁₁' is divided into two parts, one of which is supplied to the error correcting unit 22. The other part is fed to a signal producing unit 23. The signal producing unit 23 successively deals with each major demodulated signal S₁₁' as the data signal of eight levels ("0" to "7") to detect the single Lee-error. The signal producing unit 23 thereby produces an error correcting signal S₄ on detection of the single Lee-error. The error correcting signal S₄ takes either "+1" or "-1" at a position of the major demodulated signal S₁₁' at which such a single Lee-error occurs. The signal producing unit 23 is also described in detail in the above-referenced conference record and will not be described any longer. The illustrated error correcting unit 22 corrects at least the single Lee-error of the major demodulated signal S₁₁' and the minor demodulated signal S₂₁' with reference to the error correcting signal S₄ as will later be described in detail. The error correcting unit 22 produces a major correction result signal S₁₀' and a minor correction result signal S₂₀'. If the major demodulated signal S₁₁' is free from the code error, the error correcting unit 22 produces the major demodulated signal S₁₁' and the minor demodulated signal S₂₁' as they stand. Otherwise, the error correcting unit 22 produces error corrected signals. At any rate, the error correcting unit 22 sends major and minor correction result signals S₁₀' and S₂₀' to a code converting unit 24. The code converting unit 24 carries out code conversion complementary to the code conversion of the code converting unit 15 (Fig. 1) and converts the major correction result signal S₁₀' and the minor correction result signal S₂₀' to produce an output digital signal S₁' of sixteen levels as a reproduction of the input digital signal S₁ (Fig. 1). Referring to Fig. 4, description will be made as regards the error correction in the error correcting unit 22. The major demodulated signal S₁₁' has two rearranged groups, each of which specifies eight levels. The minor demodulated signal S₂₁' has two levels in correspondence to the two groups of the major demodulated signal S₁₁'. The error correcting unit 22, for example, converts the major demodulated signal S₁₁' of the fourth level 4 to the major correction result signal S₁₀' of the fifth level 5 when the error correcting unit 22 is supplied with the error correcting signal S₄ of "+1." Generally speaking, the error correcting unit 22 produces the major correction result signal S₁₀' of a level which is equal to one plus the level of the major demodulated signal S₁₁' whenever the error correcting unit 22 is supplied with the error correcting signal S₄ of "+1." To the contrary, the error correcting unit 22 produces the major correction result signal S₁₀' of another level which is equal to the level of the major demodulated signal S₁₁' minus one whenever the error correcting unit 22 is supplied with the error correcting signal S₄ of "-1." In this manner, the error correcting unit 22 corrects the single Lee-error of the major demodulated signal S₁₁' and the minor demodulated signal S₂₁' as shown in Fig. 4. If the multilevel modulation is carried out either by amplitude modulation or frequency modulation, specific levels of the major and the minor demodulated signals S₁₁' and S₂₁' are excepted from the error correction. Each of the specific level is enclosed with parentheses in Fig. 4. With regard to the minor demodulated signal S₂₁', the error correcting unit 22 inverts the levels of the first minor demodulated signal S₂₁' on error correcting the seventh level of the major demodulated signal S₁₁' whenever the error correcting unit 22 is supplied with the error correcting signal S₄ of "+1." The error correcting unit 22 further inverts the levels of the minor demodulated signal S₂₁' on error correcting the zeroth level of the major demodulated signal S₁₁' whenever the error correcting unit 22 is supplied with the error correcting signal S₄ of "-1." In the meanwhile, the signal producing unit 23 does not discriminate the two rearranged groups of the major demodulated signal S₁₁'. This might bring about occurrence of any error such that the minor multiplexed signal S₂₁ alone is erroneously demodulated into the minor demodulated signal S₂₁' despite the fact that the major multiplexed signal S₁₁ is correctly reproduced into the major demodulated signal S₁₁'. But, such a code error occurs in a very low probability so far as the Lee-error correcting code sequence is used as the multilevel modulated signal. Therefore, the above-exemplified code error can be disregarded. From this fact, it is seen that the signal producing unit 23 may logically process the major demodulated signal S₁₁' of eight levels. Such logical processing may need only three (= log₂8) logical steps which are reduced in number in comparison with four (= log₂16) logical steps necessary for processing the multilevel modulated signal S₂' of sixteen levels. Accordingly, the signal producing unit 23 may be small in size and can carry out logical operation at high speed. Referring to Fig. 5, a modulator according to a second embodiment of this invention is for use in a sixteen-level quadrature-phase amplitude modulation. The modulator modulates a first input digital signal SP₁ of a channel P and a second input digital signal SQ₁ of another channel Q into a quadrature-phase amplitude modulated signal QAM. The modulator comprises a code converting unit 31 supplied with the first and the second input digital signals SP₁ and SQ₁. Each of the first and the second input digital signals SP₁ and SQ₁ is capable of representing at most N levels where N is equal to 2 x where, in turn, x is an integer which is not less than four. The code converting unit 31 is for converting the first input digital signal SP₁ to first major and first minor converted signals SP₁₀ and SP₂₀ and the second input digital signal SQ₁ to second major and second minor converted signals SQ₁₀ and SQ₂₀, respectively. Each of the first and the second major converted signals SP₁₀ and SQ₁₀ has 2 x levels. Each of the first and the second minor converted signals SP₂₀ and SQ₂₀ has 2y levels where y represents a positive integer. Each of the first and the second input digital signals SP₁ and SQ₁ may be a four-bit binary digital signal and capable of representing at most sixteen levels (= 2⁴). Accordingly, each of the first and the second major converted signals SP₁₀ and SQ₁₀ has sixteen levels (= 2⁴). On the other hand, each of the first and the second minor converted signals SP₂₀ and SQ₂₀ has two levels (= 2¹). Under the circumstances, a combination of the first and the second input digital signals SP₁ and SQ₁ can represent 256 different values. The 256 different values are produced as the quadrature-phase amplitude modulated signal QAM. Referring to Fig. 6, the 256 different values are depicted as 256 signal points on a phase plane of the quadrature-phase amplitude modulated signal QAM. When distributed on the phase plane in a usual manner, the 256 signal points form a square on the phase plane. Turning to Fig. 7, the code converting unit 31 (Fig. 5) is for arranging the 256 signal points into a nearly circular shape on the phase plane. In order to derive the nearly circular signal arrangement, twenty-four signal points in first to fourth corners A₁ to A₄ (Fig. 6) of the square are displaced to four sides of the square in the manner which will be described in the following. Comparison of Figs. 5 and 7 will show that the first input digital signal SP₁ is rearranged in the first major converted signal SP₁₀ by the code converting unit 31 into a first and a second rearranged group. The first rearranged group consists of zeroth to fifteenth levels 0 to 15. The second rearranged group consists of zeroth level 0 and fifteenth level 15. Similarly, the second input digital signal SQ₁ is rearranged in the second major converted signal SQ₁₀ into two groups which will again be called a first and a second rearranged group. The first rearranged group consists of zeroth to fifteenth levels 0 to 15. The second rearranged group consists of zeroth level 0 and fifteenth level 15. Such code conversion is exemplified in US-A-4,675,619 and has no direct concern with the present invention. Therefore, no description will be made about the code converting unit 31 any longer. In Fig. 5, the first major converted signal SP₁₀ is divided into two parts one of which is delivered to a first multiplexer 32p. The other part is supplied to a first signal producing unit 33p. Responsive to the first major converted signal SP₁₀, the first signal producing unit 33p produces a first single Lee-error correcting code sequence SP₂ in the manner described in connection with the signal producing unit 17 (Fig. 1). The first multiplexer 32p multiplexes the first single Lee-error correcting code sequence SP₂ and the first major converted signal SP₁₀ into a first major multiplexed signal SP₁₁ and the first single Lee-error correcting code sequence SP₂ and the first minor converted signal SP₂₀ into a first minor multiplexed signal SP₂₁. Similarly, a second multiplexer 32q is supplied with the second major converted signal SQ₁₀ and a second single Lee-error correcting code sequence SQ₂ which is produced by a signal producing unit 33q in response to the second major converted signal SQ₁₀. The second multiplexer 32q multiplexes the second single Lee-error correcting signal SQ₂ and the second major converted signal SQ₁₀ into a second major multiplexed signal SQ₁₁ and the second single Lee-error correcting signal SQ₂ and the second minor converted signal SQ₂₀ into a second minor multiplexed signal SQ₂₁. Responsive to the first major and the first minor multiplexed signals SP₁₁ and SP₂₁ and the second major and the second minor multiplexed signals SQ₁₁ and SQ₂₁, a multilevel modulating unit 34 modulates a pair of quadrature-phase carrier signals C₃ into the multilevel quadrature-phase amplitude modulated signal QAM. The multilevel quadrature-phase amplitude modulated signal QAM is transmitted to a multilevel quadrature-phase amplitude demodulator through a transmission medium. It is readily understood that the first and the second signal producing units 33p and 33q may produce a double Lee-error correcting code sequence as described in Fig. 1. As mentioned above, the first major converted signal SP₁₀ is divided into the first group of sixteen levels and the second group of two levels placed outside of the sixteen levels and is subjected to error correction by the use of the first signal producing unit 33p for carrying out a logical operation of the sixteen levels. This is because the Lee-error correcting code sequence is used as the first major converted signal SP₁₀. A conventional thought is that an error correcting code producing unit for thirty-two levels is indispensable for correcting such a first major converted signal of eighteen levels. From this fact, it is readily understood that the first signal producing unit 33p is small in size and operable at a high speed in comparison with the conventional error correcting code producing unit. This applies to the second signal producing unit 33q, although the above-mentioned description is restricted to the first signal producing unit 33p. Referring to Fig. 8, a multilevel quadrature-phase amplitude demodulator is for use as a counterpart of the sixteen-level quadrature-phase amplitude modulator illustrated with reference to Fig. 5. The demodulator is for demodulating the multilevel modulated signal illustrated with reference to Fig. 7. The demodulator comprises a multilevel demodulating unit 41 supplied with the multilevel quadrature-phase amplitude modulated signal indicated at QAM'. Responsive to a pair of quadrature-phase local carrier signals C₄, the demodulating unit 41 demodulates the multilevel quadrature-phase amplitude modulated signal QAM' into first major and first minor demodulated signals SP₁₁' and SP₂₁' of the channel P and second major and second minor demodulated signals SQ₁₁' and SQ₂₁' of the other channel Q. The first major demodulated signal SP₁₁' is divided into two parts, one of which is delivered to a first error correcting unit 42p. The other part is supplied to a first signal producing unit 43p. Responsive to the first major demodulated signal SP₁₁', the first signal producing unit 43p produces a first error correcting signal SP₃ on detection of the single Lee-error in the manner described in conjunction with the signal producing unit 23 (Fig. 3). The second major demodulated signal SQ₁₁' is divided into two parts, one of which is delivered to a second error correcting unit 42q. The other part is supplied to a second signal producing unit 43q. Responsive to the second major demodulated signal SQ₁₁', the second signal producing unit 43q produces a second error correcting signal SQ₃ on detection of the single Lee-error. The first error correcting unit 42p corrects the single Lee-error of the first major demodulated signal SP₁₁' and the first minor demodulated signal SP₂₁' with reference to the first error correcting signal SP₃ as will later be described in detail. The first error correcting unit 42p produces a first major correction result signal SP₁₀' and a first minor correction result signal SP₂₀' to a code converting unit 44. On the other hand, the second error correcting unit 42q produces a second major correction result signal SQ₁₀' and a second minor correction result signal SQ₂₀' to the code converting unit 44. The code converting unit 44 carries out code conversion which is complementary to the code conversion of the code converting unit 31 (Fig. 5). The code converting unit 44 converts the first major correction result signal SP₁₀' and the first minor correction result signal SP₂₀' to produce a first output digital signal SP₁' of sixteen levels as a reproduction of the first input digital signal SP₁ (Fig. 5). The code converting unit 44 further converts the second major correction result signal SQ₁₀' and the second minor correction result signal SQ₂₀' to produce a second output digital signal SQ₁' of sixteen levels as a reproduction of the second input digital signal SQ₁ (Fig. 5). Referring to Fig. 9, description will be made as regards the error correction in the first error correcting unit 42p. Although restricted to the first error correcting unit 42p, the description applies to the second error correcting unit 42q. The first major demodulated Signal SP₁₁' has first and second rearranged groups. The first rearranged group consists of zeroth to fifteenth levels 0 to 15. The second rearranged group consists of zeroth level 0 and fifteenth level 15. The first error correcting unit 42p produces the first major correction result signal SP₁₀' of a level which is equal to one plus the level of the first major demodulated signal SP₁₁' whenever the first error correcting unit 42p is supplied with the first error correcting signal SP₃ of "+1." To the contrary, the first error correcting unit 42p produces the first major correction result signal SP₁₀' of another level which is equal to the level of the first major demodulated signal SP₁₁' minus one whenever the first error correcting unit 42p is supplied with the first error correcting signal SP₃ of "-1." In this manner, the first error correcting unit 42p corrects the single Lee-error of the first major demodulated signal SP₁₁' as shown in Fig. 9. With regard to the first minor demodulated signal SP₂₁', the first error correcting unit 42p inverts the level of the first minor demodulated signal SP₂₁' on error correcting the fifteenth level of the first major demodulated signal SP₁₁' whenever the first error correcting unit 42p is supplied with the first error correcting signal SP₃ of "+1.". The first error correcting unit 42p inverts the level of the first minor demodulated signal SP₂₁' on error correcting the zeroth level of the first major demodulated signal SP₁₁' whenever the first error correcting unit 42p is supplied with the first error correcting signal SP₃ of "-1." In the meanwhile, the first signal producing unit 43p does not discriminate the two rearranged groups of the first major demodulated signal SP₁₁'. This might bring about occurrence of any error such that the first minor multiplexed signal SP₂₁ alone is erroneously demodulated into the minor demodulated signal SP₂₁' despite the fact that the first major multiplexed signal SP₁₁ is correctly reproduced into the first major demodulated signal SP₁₁'. But, such a code error can be disregarded for the reasons described in conjunction with Figs. 3 and 4. As mentioned above, the first major demodulated signal SP₁₁' is divided into the first rearranged group of sixteen levels and the second rearranged group of two levels placed outside of the sixteen levels. The first signal producing unit 43p carries out a logical operation for detecting the Lee-error of the first major demodulated signal SP₁₁' of the sixteen levels. It is readily understood that the first signal producing unit 43p is small in size and operable at a high speed for the reasons described in connection with the first signal producing unit 33p illustrated in Fig. 5. This applies to the second signal producing unit 43q. While this invention has thus far been described in conjunction with two preferred embodiments thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, the number N may be 32 or 64. The major converted signal may be rearranged into three or more groups. The minor converted signal has three levels in correspondence to the respective groups when the major converted signal is rearranged into three groups.

Claims: A multilevel modulator responsive to an input digital signal having a plurality of levels for modulating a carrier signal into a multilevel modulated signal, said modulator having a code converting means (15, 31) for converting said input digital signal, a signal producing means (17, 33) for producing a Lee-error correcting code sequence and a modulating means (18, 34), characterized in that a) said code converting means (15; 31) converts said input digital signal into a major converted signal (S₁₀) and a minor converted signal (S₂₀), said major converted signal having rearranged groups, each group consisting of a first predetermined number of levels, said minor converted signal having a second predetermined number of levels related to the respective groups; b) said signal producing means (17; 33) is responsive to said major converted signal for producing a Lee-error correcting code sequence (S₃); c) multiplexing means (16; 32) is provided for multiplexing said error correcting code sequence (S₃) and said major converted signal (S₁₀) into a major multiplexed signal (S₁₁) and said error correcting code sequence (S₃) and said minor converted signal (S₂₀) into a minor multiplexed signal (S₂₁); and d) said modulating means (18; 34) modulates said carrier signal by said major and said minor multiplexed signals into said multilevel modulated signal, e) wherein said input digital signal is capable of reproducing at most N levels where N is represented by ( i·2 n + m ) where, in turn, n is an integer which is not smaller than two, m and i being integers which satisfy 0 ≦ m < 2 n and (m + i) ≧ 2 , respectively, said first predetermined number being equal to 2 n , said second predetermined number being equal to (i + k) where k is equal to zero and one when m is equal to zero and is greater than zero, respectively. A multilevel modulator as claimed in Claim 1, wherein said modulating means (18; 34) is for carrying out either an amplitude modulation, a frequency modulation, or a phase modulation. A multilevel modulator according to any one of claims 1 or 2 and being further responsive to a second input digital signal for modulating a pair of quadrature-phase carrier signals into a multilevel quadrature-phase amplitude modulated signal, wherein a) the code converting means (31) further converts said second input digital signal to a second major and a second minor converted signal, each of said first and said second major converted signals having a first rearranged group of a first predetermined number of levels and a second rearranged group or a second predetermined number of levels, each of said first and said second minor converted signals having a third predetermined number of levels related to said first and said second rearranged groups, respectively; b) the signal producing means has first and second signal producing members (33p, 33q) responsive to said first and said second major converted signals for producing a first and a second Lee-error correcting code sequence, respectively; c) a second multiplexing means (32g) is provided for multiplexing said second error correcting code sequence and said second major converted signal into a second major multiplexed signal and said second error correcting code sequence and said second minor converted signal into a second minor multiplexed signal; and d) said modulating means (34) modulates said pair of quadrature-phase carrier signals by said first major and said first minor multiplexed signals and said second major and said second minor multiplexed signals into said multilevel quadrature-phase amplitude modulated signal. A multilevel quadrature-phase amplitude modulator as claimed in Claim 3, wherein said first predetermined number is equal to N, said second predetermined number being equal to 2y where y represents a positive integer, said third predetermined number being equal to (y + 1). A multilevel demodulator for demodulating a multilevel modulated signal into which a modulator carrier signal is modulated by a modulating signal which is converted from an input digital signal and which comprises a Lee-error correcting code sequence, said input digital signal having a plurality of levels, comprising: a) demodulating means (21; 41) responsive to a local carrier signal for demodulating said multilevel modulated signal into a major demodulated signal (S₁₁') and a minor demodulated signal (S₂₁'), said major demodulated signal having rearranged groups, each group consisting of a first predetermined number of levels, said minor demodulated signal having a second predetermined number of levels related to the respective groups; b) signal producing means (23; 43) responsive to said major demodulated signal for producing an error correcting signal (S₄); c) error correcting means (22; 42) for correcting said major demodulated signal (S₁₁') and said minor demodulated signal (S₂₁') with reference to said error correcting signal (S₄) to produce a major correction result signal (S₁₀') and a minor correction result signal (S₂₀'), respectively; and d) code converting means (24; 44) for converting said major correction result signal and said minor correction result signal into a reproduction of said input digital signal, e) wherein said input digital signal is capable of representing at most N levels where N is represented by ( i·2 n + m ) where, in turn, n is an integer which is not smaller than two, m and i being integers which satisfy 0 ≦ m < 2 n and (m + i) ≧ 2 , respectively, said first predetermined number being equal to 2 n , said second predetermined number being equal to (i + k) where k is equal to zero and one when m is equal to zero and is greater than zero, respectively. A multilevel demodulator according to claim 5, for demodulating a multilevel quadrature-phase amplitude modulated signal into which a pair of quadrature-phase modulator carrier signals are modulated by a first and a second modulating signal, with said first and said second modulating signals converted from a first and a second input digital signal, respectively, said first and said second modulating signals comprising a first and a second Lee-error correcting code sequence, respectively, wherein a) the demodulating means (42p, 42g) is responsive to a pair of quadrature-phase local carrier signals for amplitude demodulating said multilevel quadrature-phase amplitude modulated signal into a first major and a first minor demodulated signal and a second major and a second minor demodulated signal, each of said first and said second major demodulated signals having a first rearranged group of a first predetermined number of levels and a second rearranged group of a second predetermined number of levels, each of said first and said second minor demodulated signals having a third predetermined number of levels related to said first and said second rearranged groups, respectively; b) a second signal producing means is provided and is responsive to said second major demodulated signal for producing a second error correcting signal; c) a second error correcting means is provided for correcting said second major and said second minor demodulated signals with reference to said second error correcting signal to produce a second major correction result signal and a second minor correction result signal, respectively; and d) the code converting means wherein (44) converts said first major and said first minor correction result signals and said second major and said second minor correction result signals into a first and a second output digital signal as reproductions of said first and said second input digital signals, respectively. A multilevel quadrature-phase amplitude demodulator as claimed in Claim 6, wherein said first predetermined number is equal to N, said second predetermined number being equal to 2y where y represents a positive integer, said third predetermined number being equal to (y + 1).

Inventors: NODA SEIICHI C O NEC CORPORATI, YOSHIMOTO MAKOTO C O NEC CORPO, NODA, SEIICHI C/O NEC CORPORATION, YOSHIMOTO, MAKOTO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1986
Main classification: H03M13
IPC codes: H03M13, H04L27, H04L1