SEMICONDUCTOR MEMORY DEVICE HAVING SERIALLY ADDRESSING SCHEME

Abstract: A semiconductor memory of the type that a plurality of memory locations (MC) are sequentially addressed in synchronism with a chain of clock pulses without externally applied address signals is disclosed. The memory is provided with a detection circuit (20) for detecting a selection of a predetermined memory location (MC) and thus it is allowed for user to know which memory location has addressed.

Description: Background of the Invention: The present invention relates to a semiconductor memory formed on a semiconductor substrate, and more particularly to a semiconductor memory IC having a serially addressing scheme for serially reading a plurality of bit locations without address information from the outside. Many kinds of memories have been developed and used widely in accordance with purposes and applications. Of those, a memory having a large capacity is used in a system handling large amount of data such as those for voices or images. The memory of this kind is not required to operate at a very high speed, but to be easy to use at low cost. Therefore, a memory of serially addressing type has been proposed, and devices have been made to minimize the number of external pins so as to reduce the cost. As one of approaches to achieve the above, a reduction in the number of address terminals has been proposed and practised. Since such a memory having a large memory capacity has a wide address space which requires a large address bit length. This makes it necessary to use a great number of address terminals if the conventional address access system is adopted. For example, eighteen address terminals are required in case a memory composed of 320 word lines in rows and 700 bit lines (or bit line pairs) in columns to have a capacity of 224 kbits is to be produced. On the other hand, it is a current practice to access the voice or image data not at random but sequentially in a fixed order of columns so that the column addresses are repeatedly renewed. As a result, the column address terminals can be dispensed with if a counter or a shift register is provided inside of a memory and is incremented or decremented to generate a column address. Thus, a plurality bits of data read on bit lines in columns are sequentially addressed one by one by incrementing or decrementing contents of the counter or shift register. Since the memory of this kind need not receive any column address from the outside, it is advantageous in that it can be fabricated at a low cost and used easily. However, the memory is disadvantageous in that which column is being accessed, i.e., which bit line the data being read or written cannot be known from the outside of the memory. In the memory of this kind, generally speaking, after all the data set in an output data register have been read out, the data held in this register have to be written again in the original locations. This operation is generally performed independently of a refreshing operation although it can be conducted together with the latter operation. Moreover, the writing operation is required for maintaining the memory data. Since, however, the user of this memory cannot know from the outside when the read of the data (of 700 bits, for example) of one word is to from the outside to a row decoder for performing a word selecting signal is counted by a counter, which is prepared outside of the memory, to locate the position of the bit being accessed, by which the aforementioned rewrite timing is checked. This raises a serious defect that the number of parts to be added to the outside of the memory is increased to complicate the system design and to necessarily raise the cost. Even if the check is conducted outside, moreover, the timing detected at the outside and the actual timing in the memory are not necessarily coincident, and there is possibility of a discrepancy in the timing due to characteristic dispersions depending upon the different lengths of the signal lines and the fabricating conditions of the memory. This problem is predicted to become the more prominent especially as the number of cells per one word line (or one bit line) becomes the greater. A memory as described above and forming the preamble of claim 1 is disclosed, for example, in US-A-3 930 239. Summary of the Invention: An object of the present invention is to provide a semiconductor memory which can grasp an internal addressing operation timing reliably and easily. This object is achieved by a semiconductor memory device comprising a memory array of memory cells arranged in rows and columns, row selection means for selecting one of the rows of the memory array, column selection means for serially selecting columns consecutively in synchronism with clock signals, and an output means for outputting data on the selected column, and is featured by comprising an external detection terminal and a column address detecting means coupled to a predetermined one of said columns for generating a detection signal at said detection terminal when said predetermined one of said columns is selected by said column selecting means. According to the present invention, it is possible to internally detect the internal address or operation timing of a predetermined bit being accessed inside of the memory so that the timing conforming to a real operation sequence can be recognized reliably and easily outside of the memory without requiring any complicated additional circuits. According to the present invention, more specifically, an address prepared inside of the memory can be known easily and precisely without feeding any address to the memory from the outside thereby to remarkably facilitate the controllability of not only the aforementioned rewrite but also the other memory control requiring the bit access timing. Brief Description of the Drawings: Fig. 1 is a schematic block diagram showing a memory according to a prior art; Fig. 2 is a timing diagram showing operations of the memory of Fig. 1; Fig. 3 is a schematic block diagram of a memory according to a first embodiment of the present invention; Fig. 4 is a timing diagram showing operations of the memory of Fig. 3; Fig. 5 is a schematic circuit diagram showing a major part of the memory according to a second embodiment of the present invention; Fig. 6 is a timing diagram showing operation of the second embodiment; and Fig. 7 is a schematic block diagram of a third embodiment of the present invention. Detailed Description of the Invention: The serially addressing type memory device according to a prior art is shown in Fig. 1. A memory cell array 1 includes a plurality of memory cells MC each composed of a memory cell transistor Q M and a storage capacitor C M . "m" word lines WL₁ to WL n are arranged in rows and "n" pairs of bit lines d₀, d₀ to d n-1 , d n-1 are arranged in columns in the array 1. A plurality of sense amplifiers SA to SA n-1 coupled to the pairs of bit lines. A row decoder 3 selects one or the word lines based on row address information. A data register section 4 is composed of "n" data holding circuits D₀ to D n-1 having input ends coupled to "n" pairs of bit lines d₀, d₀ to d n-1 , d n-1 , respectively. Each data holding circuit e.g. D₀ operatively holds data on the pair of bit lines d₀, d₀ . A pair of output ends of each data holding circuit are coupled to a pair of bus lines I/O and I/O through each pair of transfer gates Q 0A , Q 0B to Q n-1A , Q n-1B . The pair of bus lines I/I and I/O are connected to a pair of input ends of an input/output circuit 6. A shift register 5 has "n" shift stages S₀ to S n-1 and shifts a single selection signal towards rightward one by one in synchronism with a chain of clock pulses  IN . Driver transistors Q t0 to Q tn-1 generate selection signals  T0 to  Tn-1 for conducting the pairs of transfer gates Q 0A , Q 0B to Q n-1A , Q n-1B upon coincidence of a drive pulse  and the outputs of the shift register 5, respectively. The row decoder 3 selects one of the word lines, data are read out in parallel from the n-bit cells connected with the respective word lines and are set in the register 4. The data thus set in the register 4 are read out one bit by one bit to an data input/output terminal DT through the pair of bus lines I/O, I/O and the circuit 6 in response to the shift clock ø CL . Incidentally, the n-bit data inputted in series from the terminal DT circuit 6 are once set in the register 4 and are then written in parallel in the n cells connected with the word lines selected. Operations are shown in the time chart of Fig. 2. The shift register 5 holds its state in response to a low level of ø IN and shifts the contents of the respective stages by one rightwardly in response to a high level of ø IN . The pulse ø assumes a high level during a period that ø IN is at low and a low level at least during a period that ø IN is at high. First, during a period T₁, the stage S₀ generates "1" output while other stages S₁ to S n-1 generate "0" output. Therefore, a signal ø T0 is generated in response to a high level of ø. Accordingly, the transfer gate pair Q 0A and Q 0B are rendered conductive so that data stored in the holding circuit D₀ is outputted to the terminal DT via a pair of bus lines I/O, I/O and the circuit 6. Then, during a period T₂, "1" output is shifted from S₀ to S₁ in the shift register 5 in response to a high level of ø IN . Subsequently, during a period T₃, a selection signal ø T1 is generated in response to a high level of ø so that data stored in D₁ is read out at the terminal DT via Q 1A , B 1B . In this manner, data stored in D₀ to D n-1 in the data register 4 are sequentially outputted one by one in synchronism with repetition of pulses of ø IN and ø. This memory is advantageous in that a plurality bits of memory location are accessed sequentially without any specific column address information. However, on the other hand, it is difficult to know which column is accessed from the outside. Fig. 3 shows a first embodiment of the invention. In Fig. 3, the portions corresponding to those in Fig. 1 are denoted by the similar references. This embodiment comprises a timing detection circuit 20 added to the prior art circuit of Fig. 1. The timing detection circuit 20 has an input end receiving one of the selection signals ø TO to ø Tn-1 and an output end coupled to an external terminal 10 of the memory IC, that is a pad on the semiconductor substrate of the memory IC. In this embodiment, the input end of the circuit 20 is connected to ø Tn-2 . The circuit 20 is composed of a series circuit of field effect transistors (FETs) Q₁₁ and Q₁₂ coupled between Vcc and ground serving as a buffer and a series circuit of a load resistor R and an FET Q₁₃ coupled between ground and a detection terminal AT. A gate of FET Q₁₁ is connected to the next-to-last selection signal ø Tn-2 and a reset signal ø p is applied to a gate of FET Q₁₂. An outside system (not shown) utilizing the memory output data through the output terminal DT or a test system testing the memory IC has a terminal At which is connected to the terminal 10 of the memory IC of the embodiment, and a pull-up resistor R is connected between the terminal AT and a power supply V cc which should be common to that V cc for the memory IC. The terminal 10, or the terminal At, is used to detect that the holding circuit D n-2 is being selected to output the data stored therein. In case when the terminal 10 is used by a testing apparatus, the resistor R is removed from the terminal 10 after testing to reduce a power comsumption when the memory IC is used in a system where the detection is not required. It is also possible to fabricate the resistor R on the same semiconductor chip of the memory. The reset signal ø p assume a high level before read-out data in the respective columns are stored in the data register 4, and a low level during a serial accessing period during which the memory is accessed. The detection circuit 20 generates a "1" level output (ø A ) before the signal ø Tn-2 is energized to a "1" level and a ″0″ level output (ø A ) when the signal ø Tn-2 is energized to a "1" level and thereafter in the same serial addressing cycle. Thus, by monitoring a level of the terminal 10, it can be known that the serial column access has reached the predetermined column (in this case the next-to-last column "n-2"). The above operation is illustrated in Fig. 4. In this embodiment, "n-2"th column is subject to detection of access thereto. However, in place of "n-2"th column, any one (xth) of columns "0"th to "n-1"th can be similarly subjected to the detection of access thereto by connecting the gate of FET Q₁₁ to a desired x-th selection signal ø Tx (x being one of 0 to n-1). Fig. 5 shows another embodiment of the detecting circuit of the present invention. A buffer circuit composed of MOST's Q₂₄ to Q₃₃ has a function to latch the selection signal ø Tx . Since the buffer circuit generates both of V cc and ground level to the pad 10, no pull-up resistor is required. Fig. 6 is a time chart for explaining the detecting circuit of Fig. 5. The voltage at an output node N₄ rises as a result of the transition of the signal ø Tx of x-th column (x being one of 0 to n-1) to the high level and maintains this high level till the rising point of the signal ø p . As a result, effects similar to those of Fig. 3 can be attained. Fig. 7 shows a memory according to a third embodiment of the invention. This embodiment is featured in that a column address counter 12 which is incremented in response to a clock signal ø′ IN and a column decoder 11 for generating column selection signals ø T0 to ø Tn-1 by decoding contents of the counter 12, in place of shift register 5 of Fig. 3. The remaining operations are similar to those of the aforementioned serial access memory such that the individual states of the data register are sequentially selected in response to the selection signal ø TX (wherein x = 0 to n-1) from the column decoder to conduct the reading and writing operations through the data terminal DT. As has been described hereinbefore, according to the present invention, the address information at a predetermined read and write addresses can be obtained without counting the memory control signals at the outside so that the system using the serial access memory can be remarkably simplified. Moreover, an arbitrary selection signal may be fed to the detection circuit or the individual detected signals can be combined to know an arbitrary address by connecting a plurality of detecting circuits in parallel.

Claims: A semiconductor memory device comprising a memory array (1) of memory cells (MC) arranged in rows and columns, row selecting means (3) for selecting one of said rows, column selecting means (4, 5, QOA, QOB - Qn-1A, Qn-1B, Qto - Qtn-1) for serially selecting said columns consecutively in synchronism with clock signals (IN), and output means (6, DT) for outputting data of the selected column, characterized by further comprising an external detection terminal (AT), and a column address detecting means (20) coupled to a predetermined one (n-2) of said columns for generating a detection signal (A) at said detection terminal when said predetermined one of said columns is selected by said column selecting means. The memory according to claim 1 , characterized in that word lines (WL1, WL2 ...) are provided in said rows and a plurality pairs of bit lines (do, do - dn-1, dn-1 ) are provided in said columns, in said memory array. The memory according to claim 1 , characterized in that said column selecting means includes a plurality of data holding circuits (Do-Dn-1) each provided for one of said columns, The memory according to claim 1 , further comprising a bus line (I/O, I/O ) coupled to the input of said output means. The memory according to claim 2 , characterized in that said column selecting means includes a plurality of transfer gates (QOA, QOB - Qn-1A, Qn-1B) each coupled between a bit line and the input of said output means, a shift register (5) enabling one of said transfer gates.

Inventors: TSUJIMOTO, AKIRA NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1986
Main classification: G11C7
IPC codes: G11C11, G11C7