SIGNAL ELECTRODE DRIVE APPARATUS FOR USE IN A LIQUID CRYSTAL DISPLAY

Abstract: In the signal electrode drive apparatus for use in a liquid crystal display, the signal electrode drive circuit (3a) for driving a liquid crystal display panel (LCD) is comprised of a latch circuit (2l) for latching a digitized video signal, a buffer (22), a graduation signal-forming circuit (23), an intensity modulation pulse-generating circuit (25), and an analog multiplexer (24). The latch circuit (2l) holds the video data only once during one horizontal scanning period till the next latch pulse M is generated, thus considerably reducing current dissipation.

Description: This invention relates to improvement of a signal electrode drive apparatus which is contained in the display-drive circuit for use in a liquid crystal display device. A portable television employs a liquid crystal display device to provide its picture. An example of this known type of TV set is disclosed in U.S. Pat. No. US-A-4,58l,654. The display-drive circuit of this prior art TV set is configured as shown in Figs. l through 3. Fig. l shows a configuration of the overall displaydrive circuit. In the figure, reference numeral l designates a simple matrix liquid crystal display panel of, for example, l20 × l60 dots. Numeral 2 designates a scanning electrode drive circuit, and 3a and 3b denotes signal electrode drive circuits. Scanning electrode drive circuit 2 sequentially drives scanning electrodes Xl to Xl20 of display panel l. The sequential drive operation is timed by a timing signal from a controller (not shown). Signal electrode drive circuits 3a and 3b drive groups of signal electrodes Yl to Y80 and Y8l to Yl60, respectively. The drive operation is performed using an n-bit digital signal, passed through an A/D converter, and a timing signal from the controller. More specifically, circuit 3a fetches the data of 80 lines, which comprise the left-hand portion of the input data record during the effective horizontal scanning period. Electrode drive circuit 3b fetches the data of 80 lines in the right-hand portion. On the basis of the fetched data, drive circuits 3a and 3b drive the respective groups of electrodes Yl to Y80 and Y8l to Yl60, in synchronism with the driving of scanning electrodes Xl to Xl20. Fig. 2 shows in block diagraph the details of the prior art signal electrode drive circuit 3a. In the figure, shift register ll is provided in each stage of 80 stages, and which consists of a 4-bit register. The 4-bit video data coming from an A/D converter (not shown) is sequentially stored in the the shift register, in synchronization with sampling clock s. The data loaded is transferred to graduation signal-forming circuit l3, via buffer l2 which consists of 80 stages, each stage including 4-bit buffer registers, and which operates in synchronism with a latch pulse L. Intensity modulation pulse-generating circuit l5 responds to latch pulse L and counts clock pulse 2, to form intensity modulation pulses Pl to P4. These pulses Pl to P4 are input to graduation signal-forming circuit l3. Circuit l5 contains a counter, which is reset by latch pulse L, and which frequency-divides, by 2, the frequency of clock pulse 2, to form intensity modulation pulses Pl to P4. Clock pulse 2 is a fundamental clock signal with a frequency of 3 MHz. Graduation signal-forming circuit l3 appropriately processes the 4-bit video data latched in buffer l2, and the intensity modulation pulses Pl to P4 generated by intensity modulation pulse-generating circuit l5, and forms l6 types of graduation signals Sl to S80 with different time widths. These graduation signals are transferred to 2-channel analog multiplexer l4. Multiplexer l4 also appropriately processes graduation signals Sl to S80 from graduation signal-forming circuit l3 and field-select signal f, and forms signal electrode drive signals Yl to Y80, to drive liquid crystal display panel l. Fig. 3 shows in detail one stage of the signal electrode drive circuit of Fig. 2 which consists of 80 stages, as previously stated. As is shown in shift register ll, each stage is made up of one register lll of 4 bits, which is operated in response to sampling clock pulse s. Data of 4 bits Dl to D4 coming from the A/D converter (not shown) are loaded into register lll, and then transferred to register ll2, at the next stage. Buffer l2 includes a 4-bit buffer register l2l in each stage of 80 stages. The data from register lll is loaded into buffer register l2l in synchronism with latch pulse L. The data is then transferred to graduation signal-forming circuit l3. Graduation signal-forming circuit l3 consists of OR circuits l3l to l34, AND circuit l35, and flip-flops l36 to l38. The data from buffer register l2l, together with intensity-modulation pulses Pl to P4 from modulation pulse-generating circuit 25, is input to AND circuit l35, via OR circuits l3l to l34. The output data from AND circuit l35 is input to flip-flop l36, in synchronism with clock pulse 2. The output data of flip-flop l36 is input to the reset terminal R of flip-flop l37. Flip-flop l37 is set by latch pulse L. Flip-flop l36 is reset by latch pulse L. The output signal of flip-flop l37 is loaded into flip-flop l38, in synchronism with clock pulse 2. The output signal from flip-flop l38 is transferred, as a graduation signal Si, to analog multiplexer l4. Multiplexer l4 is made up of decoder l4l, and transfer gates l42 to l45. Multiplexer l4 receives a graduation signal Si and a frame-select signal f. Transfer gates l42 to l45 are coupled with V5, V2, V3, and V0, respectively. These gates are gate-controlled by the output signal from decoder l4l. By way of this gate control, one of voltages V5, V2, V3, and V0 is selected and output as a signal electrode drive signal Yi. As can be seen from the foregoing, the signal electrode drive circuit is arranged such that each stage of shift register ll is made up of a register lll. Shift register ll in each stage of 80 stages contains register lll, ll2,..., respectively, each of which transfers the video data of 4-bits. Register lll is comprised of, for example, inverter including two transistors, and a clocked inverter including four transistors. The fact that the signal electrode drive circuit requires 80 stages for transferring video data at high speed, for example, 3 MHz which is the frequency of the fundamental clock signal, implies an increase in current dissipation in that drive circuit. GB-A-2155221 discloses an LCD drive circuit including a plurality of latch circuits to latch video signals simultaneously under the control of multi-phase clock signals derived from a counter/decoder circuit. Accordingly, an object of this invention is to provide a signal electrode drive apparatus for use in a liquid crystal display, which requires a relatively small number of circuit elements for its circuit construction, and therefore consumes less current. According to this invention, a signal electrode drive apparatus for use in a liquid crystal display comprises latch circuit means including m stages of shift registers and m buffer registers, one shift register in each stage successively shifting a latch pulse M in synchronism with fundamental clocks, to generate m latch clocks Tl to Tm with different phases, and each of the buffer registers latching in parallel fashion the n-bit video data in synchronism with the latch clocks Tl to Tm output from the shift registers, the buffer registers of each stage being coupled with the video data, and means for generating signal electrode drive signals for a liquid crystal panel, by using the video data, latched in the buffer register at each stage. With such an arrangement, the signal electrode drive apparatus according to this invention uses a latch circuit for transferring the high-speed data as the video data, in place of the shift register as employed by the prior art. The buffer register in this latch circuit latches the 4-bit video data once, in one horizontal scanning period, and holds it until the next latch pulse is generated. This feature reduces the current dissipation remarkably. The shift register, which is used in the latch circuit and which generates m latch clocks Tl to Tm with different phases, by sequentially shifting the latch pulse M in synchronism with the fundamental clock pulse 2, need only be capable of shifting one bit at each stage. This feature also further reduces the power dissipation from that of the prior art. Furthermore, the number of circuit elements used for forming the latch circuit is less than that for the prior art. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. l shows a block diagram of a display drive circuit for use in a prior liquid crystal display, for example, a liquid crystal TV set; Fig. 2 shows a block diagram of a signal electrode drive circuit used in the display drive circuit of Fig. l; Fig. 3 shows a circuit diagram of one stage of the signal electrode drive circuit of Fig. 2; Fig. 4 is a block diagram of a signal electrode drive circuit according to one embodiment of this invention; Fig. 5 is a circuit diagram of a latch circuit and a buffer used in the circuit of Fig. 4; Fig. 6 shows a timing chart for help in explaining the operation of the circuits of Figs. 4 and 5; Figs. 7A and 7B show a symbol of a circuit element used by the signal element drive circuit according to this invention, and its circuit diagram; and Fig. 8 shows a circuit diagram showing how to combine the circuit elements used in the circuit of Fig. 5. An embodiment of a signal electrode drive apparatus for use in a liquid crystal display according to this invention will now be described with reference to the accompanying drawings. Fig. 4 shows a circuit configuration of the signal electrode drive circuit in a display drive circuit of the liquid crystal display. When this signal electrode drive circuit is applied to the display drive circuit shown in Fig. l, it is used as the signal electrode drive circuit 3a. Reference numeral 2l designates a latch circuit made up of 80 stages. Applied to latch circuit 2l are 4-bit video data coming from an A/D converter (not shown) and latch pulse M. Latch circuit 2l includes a shift register, which sequentially shifts latch pulse M from the timing signal-generating circuit. In synchronism with the latch pulse as shifted by the shift register, the latch circuit latches the 4-bit video data, and outputs it to buffer 22. Latch circuit 2l shifts latch pulse M from the right stage to the left stage as shown in the drawing, i.e. from the portion connected to signal electrode drive signal Y80 to the portion connected to signal Yl. Latch circuit 2l will now be described in detail. In the description to follow, graduation signal-forming circuit 23 and analog multiplexer 24, succeeding buffer 22, will not be described in detail, since each of these circuits may have the same construction as those of the Fig. 3 circuit. Referring now to Fig. 5, the circuitry shown in this figure corresponds to latch circuit 2l and buffer 22, which correspond to the signal electrode drive signal Y80. In latch circuit 2l, reference numeral 2ll indicates a 4-bit buffer register, and numeral 2l2 denotes a shift register. The buffer register 2ll provided in each stage of latch circuit 2l is coupled with the 4-bit video data Dl to D4 coming from the A/D converter in parallel fashion. The video data are then loaded into the shift register 2l2 in buffer 22. Shift register 2l2 is also coupled with latch pulse M. As shown in Fig. 6, shift register 2l2 fetches latch pulse M in synchronism with clock pulse 2, and outputs it to the next shift register 2l2. More specifically, shift regis-ter 2l2 first fetches latch pulse M in synchronism with clock pulse 2. Subsequently, the shift registers 2l2 in the subsequent stages successively produce latch clocks T80 to Tl in synchronism with clock pulse 2. By means of these latch clocks, the 4-bit video data are successively latched into the buffer registers 2ll in the respective stages. After these latching operations for the shift registers at all stages, latch pulse L is generated, and the video data held by buffer register 2ll is transferred to buffer 22. The video data is then transferred to analog multiplexer 24 via graduation signal-forming circuit 23. Multiplexer 24 forms signal electrode drive signals Yl to Y80, by using the graduation signal from circuit 23 and frame-select signal f. A typical example of the circuit element of latch circuit 2l is symbolically illustrated in Fig. 7A. This circuit element of Fig. 7A is a NOR gate 70, which can be comprised of, for example, 4 MOS transistors combined, as shown in Fig. 7B. A CMOS inverter, which contains transistors combined, as shown in Fig. 8, may be used as shift register 2l2, buffer register 2ll and shift register 2l2 in buffer 22. Using this arrangement, the number of inverters, particularly in buffer register 2ll, may be l2 for the 4-bit video data, while it is 24 in the prior device. As a result, power dissipation can also be reduced remarkably. Incidentally, latch pulses M and L and clock pulse 2 shown in Figs. 4 and 5, may be generated by the controller, as disclosed in USP No. US-A-4,58l,654.

Claims: A signal electrode drive apparatus for use in a liquid crystal display, characterized by comprising: latch circuit means (2l) including m stages of shift registers and m buffer registers (22), one shift register in each stage successively shifting a latch pulse M in synchronism with fundamental clocks, to generate m latch clocks Tl to Tm with different phases, and each of said buffer registers latching in parallel fashion the n-bit video data in synchronism with the latch clocks Tl to Tm output from said shift registers, the buffer registers of each stage being coupled with said video data; and means (23) for generating signal electrode drive signals for a liquid crystal panel, by using the video data latched in the buffer register at each stage.

Inventors: KAWAMURA, MASAO PATENT DEPT. HAMURA R&D CENTER, USUI, MINORU PATENT DEPT. HAMURA R&D CENTER, Kawamura, Masao Patent Dept. Hamura R&amp;D Center, Usui, Minoru Patent Dept. Hamura R&amp;D Center
Applicants: CASIO COMPUTER COMPANY LIMITED
Application year: 1986
Main classification: H04N3
IPC codes: G02F1, G09G3, H04N3