TELECOMMUNICATION LINE CIRCUIT AND AMPLIFIER CIRCUIT USED THEREIN

Abstract: Telecommunication line circuit with a resistance synthesis circuit coupled between line feed resistances (R0/1) and supply inputs (VEET) of line amplifiers (LOA0/1) and including a line current sensing circuit (SENC) which is coupled with an AC filter (R22, R23, C4) which is directly connected to the plus input of an operational amplifier (OA6) whose minus input is connected to a control circuit wherein a control voltage is converted into a current which is derived from this minus input. The output of this amplifier is coupled with the line amplifiers.

Description: The present invention relates to a telecommunication line circuit including line amplifiers whose outputs are coupled to respective line conductors of a telecommunication line via feed resistances, and a resistance synthesis circuit for synthesizing a wanted resistance from said feed resistances, said synthesis circuit having inputs coupled with said feed resistances and an output coupled to supply inputs of said line amplifiers, said output being constituted by the output of an operational amplifier circuit which is controlled by a control voltage and to which said inputs are coupled through a loop current sensing circuit and an AC filter. Such a circuit is already known from Belgian patent No. 898049. Therein the control voltage is applied to the non-inverting input of the operational amplifier through a resistance, whilst the filter circuit is coupled to the same input through at least a buffer amplifier in order that this filter circuit should not be loaded by the resistance. Drawbacks of this known circuit are that such a buffer amplifier introduces a DC offset and produces noise so that the accuracy of the DC synthesizing circuit is adversely affected and that noise appears on the line. Moreover, such a buffer amplifier occupies a relatively large surface when the line circuit is integrated on a chip. An object of the present invention is to provide a telecommunication line circuit of the above type, but which does not present these drawbacks. According to the invention this object is achieved due to the fact that said AC filter is directly connected to the non-inverting input of said opertional amplifier circuit whose output is coupled through a negative feedback circuit to its inverting input which is connected to a control circuit to which said control voltage is applied and which is able to transform said control voltage into a control current and to derive this current from said inverting input. By transforming the control voltage into a current and deriving it from the inverting input of the operational amplifier, it has been possible to directly connect the filter circuit to the non-inverting input of this amplifier, i.e. without the use of a buffer amplifier. In this way the accuracy of the DC impedance synthesis circuit is increased and the noise performance of the circuit is improved because all unwanted signals are prevented from reaching the line. Also the circuit may be integrated on a smaller chip surface. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of a preferred embodiment taken in conjunction with the accompanying drawings wherein : Fig. 1 shows a telecommunication circuit including a line circuit according to the invention; Figs. 2 and 3 together represent this line circuit in more detail. The telecommunication circuit shown in Fig. 1 includes a line circuit LC which is connected in cascade with a switch circuit HVC between a telecommunication line with conductors LI0 and LI1, connected to a subset TSS, and a switching network SNW. LC, HVC and SNW are located in a telecommunication exchange. Line circuit LC includes the cascade connection of a SLIC, a Digital Signal Processor DSP, a TransCoder and Filter circuit TCF and a Dual Processor Terminal Controller DPTC. Subset TSS includes a normally open hook switch HS connected between the line conductors LI0 and LI1. Switch circuit HVC is for instance of the type disclosed in Belgian patent No. 897 772. It includes 4 pairs of bidirectional switches sw00, sw01 to sw30, sw31 as shown and has line terminals L0 and L1 connected to line conductors LI0 and LI1 respectively, test terminals T0 and T1 connected to a test circuit TC, ringing terminals RG0 and RG1 connected to a ringing circuit RC, tip and ring terminals TP and RG connected to the like named outputs of line amplifiers LOA0 and LOA1 in the SLIC respectively and terminals STA, STB, SRA, SRB connected to like named terminals of a sensing circuit SENC in the SLIC. In HVC the line terminals L0/L1 are connected to TP/RG via the series connection of sw00/01, 50 ohms line feed resistors R0/1 and sw10/11 respectively. The respective junction points STB and SRA of sw00 and R0 and of sw01 and R1 are connected to TC via sw20 and sw21 respectively, whilst the respective junction points STA and SRB of R0 and sw10 and of R1 and sw11 are connected to RC via sw30 and sw31 respectively. As shown for a switched through connection, series switches sw00, sw01, sw10 and sw11 are closed, whereas the other shunt switches are open. All the switches are controlled by the SLIC so that HVC is able to establish either one of the following connections : between TSS and SLIC (LOA0, LOA1 and SENC); TC and TSS; SLIC (LOA0, LOA1) and TC; RC and TSS; RC and SLIC (SENC). The function of TC is to test the connection to TSS and to the SLIC and that of RC is to apply a ringing signal to this line and to SENC in the SLIC. For instance, RC is able to connect ground through sw30 and the negative battery BA of -48 or -60 Volts in series with a ringing source RS of 90 Volts RMS through sw31. The Subscriber Line Interface Circuit SLIC which is integrated on a chip is a two-wire bidirectional circuit on the side of TSS and a four-wire one towards SNW. It has a speech receive input terminal Rx ( with ground return) and a speech transmit output Tx (again with ground return), Rx and Tx being connected to DSP. The SLIC further has a 12 kHz or 16 kHz metering signal input terminal MTCF connected to TCF, data input and output terminals DSP1 and DSP2 connected to DSP and the above mentioned terminals STA, STB, SRA, SRB, TP and RG connected to HVC. The sensing circuit SENC included in the SLIC is of the type disclosed in European published application No. 85200774.9 and provides at its output a composite DC/AC voltage considered with respect to VAG which is for instance equal to ri / 2 wherein r = R0 = R1 and i is the line current comprising a DC component and possibly an AC component constituted by a speech signal and/or a metering signal. The digital signal processor DSP converts a digital speech signal received from TCF into an analog speech signal which is then applied to the speech receive terminal Rx of the SLIC. Conversely it converts an analog speech signal received via the speech transmit terminal Tx of the SLIC into a digital version which is applied to TCF. DSP also includes an echo canceller circuit. The following drive bits are transmitted by DSP to data input terminal DSP1 of the SLIC : BR0 and BR1 : polarity reversal bits indicating that the polarity on RG and on TP has to be made high (1) or low (0) according to the following table : BR0 BR1 TP RG condition 0 0/1 1 0 normal condition 1 0 0 1 reversal condition 1 1 0 0 ground signalling condition This last condition is called ground signalling condition because it allows signalling in TSS on each of the line conductors by applying a ground thereon. Indeed, because TP and RG are at a low voltage current is able to flow from this ground towards the line circuit; FR : a feed characteristic bit to indicate that the synthesized line feed resistance should be high ohmic (0) or low ohmic (1. The meaning of synthesized feed resistance will be explained later; CT0 and CT1 : current limit bits indicating four possible maximum line current conditions; BV : a battery bit indicating that the exchange battery V- is -48 Volts (0) or -60 Volts (1); SMPI : a metering signal bit indicating that a metering signal applied to SLIC by TCF has to be allowed in the SLIC (1) or not (0); RNG : a ringing bit indicating that ringing is to be performed (1) or not (0); BPW : a power bit indicating that the SLIC should be put in the power up mode (1) or not (0); HB : a high bias bit indicating that the SLIC should be put in a high bias mode (1) or not (0); RY0, RY1, RY2 : three relay drive bits indicating that a corresponding one of the relays (not shown) having the above mentioned contacts sw00 to sw31 should be operated (1) or not (0). Finally, the DSP also receives on its data input terminal DSP2 control data bits transmitted by the SLIC. These bits are the same as those transmitted to DSP1 except that the four bits FR, RNG, CT0 and CT1 are respectively replaced by : SHD : a switch hook detection bit indicating that the line loop between SLIC and TSS is open (0) or closed (1); RT : a ring trip indicating that the ringing signal applied to line by the circuit RC has to be switched off (1) or not (0); OC : an overcurrent or overtemperature bit indicating that the temperature of LOA0 and/or LOA1 is above (1) or below (0) a predetermined value; VPB : a bit indicating that ground detection has to be performed on the line conductors (1) or not (0). In the present case VPB is always 0. The TCF performs a transcoding operation on digital signals received from the DSP and the DPTC and is also adapted to supply a metering signal MTCF to the SLIC. These operations are described in the Belgian patents 897 771 and 897 773. Finally, the DPTC performs the general control of the SLIC. Details of this circuit are described in the Belgian patents 898 959 and 898 960. To be noted that whereas HVC, SLIC and DSP are individually associated to the telephone line, the circuits TCF and DSP are provided in common for a number of such lines, e.g. 8 lines, as indicated by the multipling arrows. Reference is now made to Figs. 2 and 3 representing the SLIC of Fig. 1 in more detail. This circuit has some similarities with the one disclosed in Belgian patent no. 898049. This circuit operates with the following voltages : V+ which is at 0 Volts or ground potential; V- which is equal to -48 or -60 Volts e.g. -48 Volts; VAUX which is an auxiliary voltage 15 Volts above V-, e.g. -33 Volts; VAG which is a voltage half-way between V- and VAUX, i.e. substantially equal to 7,5 Volts above V-, e.g. -40,5 Volts; VEET which is a regulating voltage; B1 which is a continuously applied constant voltage equal to about 3 Volts below VAUX; B2 which is a so called bandgap reference voltage, e.g. equal to 2.41 Volts above VAG. As shown in Fig. 2, the output CO1 of the sensing circuit SENC is connected to the inputs VEET of both LOA0 and LOA1, which have respective feedback resistances R2 and R3, through a DC feedback circuit DCFC which together with the amplifiers LOA0 and LOA1, the equal feed resistances R0 an R1 and the sensing circuit SENC constitutes a resistance synthesis circuit, i.e. a circuit to convert the value of each of the feed resistances R0 and R1 into a wanted resistance value. The output CO1 of the sensing circuit SENC is also connected via a DC blocking capacitor C1 in series with an amplifier stage OA3 including an operational amplifier, on the one hand to the inverting input INO of LOA0 via resistance R4 and, on the other hand, to the non-inverting input NI1 of LOA1 through resistance R5 equal to R4. The amplifiers LOA0 and LOA1, the resistances R0 and R1, the sensing circuit SENC, the amplifier stage OA3 and the resistances R4 and R5 constitute an AC impedance synthesis circuit able to convert the resistance value of R0 and R1 into a wanted AC impedance. The non-inverting inputs NIO of LOA0 and NI1 of LOA1 are connected through equal resistances R6 and R7 to the respective outputs VTI and VRI of a polarity reversal circuit PRC of the type disclosed in the copending Belgian patent application of even date entitled "Polarity reversal circuit". As disclosed in this application the circuit PRC has inputs controlled by the above mentioned drive bits SMPI, HB, BPW, BR0 and BR1 and is able to apply a DC supply voltage V+ minus x to VTI and a DC voltage VEET plus x to VRI (normal condition) or vice-versa (reversal condition) or even VEET plus x to both VTI and VRI (ground signalling condition). The voltage x is chosen in function of the magnitudes of the speech signal and the metering signal and/or of one or more of the drive bits SMPI, HB, BPW. The PRC also provides at its output VX a voltage equal to V+ minus 2x which is applied to the DC feedback circuit DCFC. The non-inverting input NI0 of LOA0 and the inverting input IN1 of LOA1 are connected to VAG through respective equal bias resistances R8 and R9. The above mentioned outputs MTCF of TCF and Rx of DSP are coupled to the inverting input IN0 of LOA0 and to the non-inverting input NI1 of LOA1 via not shown means (indicated by dashed lines) and respective resistances R10, R11 and R12, R13. R10 and R12 are equal to R11 and R13 respectively. Finally, the output of the amplifier stage OA3 is also coupled via not shown means (also indicated by a dashed line) to the transmit output Tx. The not shown means are without importance for understanding the invention and are for instance of the type disclosed in the above mentioned European patent application. The above mentioned DC feedback circuit DCFC which will be described in detail hereinafter has the following terminals : an input connected to the output CO1 of the sensing circuit SENC; an input connected to the output VX of the polarity reversal circuit PRC; inputs controlled by the above mentioned drive bits FR, BV, BR0, BR1, CT0 and CT1 and by the complements thereof. The function of the other drive bits and of the control bits is not explained in the present description; an output VEET connected to the polarity reversal circuit PRC and to the like named inputs of both the line amplifiers LOA0 and LOA1. On the last mentioned output the circuit DCFC generates a regulating voltage VEET which is function of the above line current i and drive bits. The current limiting bits CT0 and CT1 more particularly control a current limiting circuit CLC which forms part of the DCFC and which will be considered later with reference to Fig. 3. The output CO1 of the sensing circuit SENC is connected to a circuit controlled by the feed characteristic bit FR and the complement FR thereof. More particularly, this output CO1 is connected to the non-inverting input of an operational amplifierOA4 via the series connection, on the one hand of a low pass filter R14, R15, C2 and a transfer gate PG1 and, on the other hand, of a low pass filter R16, C3 and a transfer gate PG2. The low pass filter R14, R15, C2 comprises the series resistance R14 and a shunt branch constitued by resistance R15 and capacitance C2 in parallel, whereas the low pass filter R16, C3 comprises the series resistance R16 and the shunt capacitance C3. Each of these filters is used to filter the 12 kHz or 16 kHz metering signal from the above mentioned composite AC/DC voltage signal generated at the output CO1 of the sensing circuit SENC. Due to the presence of two resistances R14, R15 the filter R14, R15, C2 provides a higher attenuation than the filter R16, C3, as is required in the low ohmic case. This will become clear later. Moreover, these resistances R14 and R15 are external to the chip constituting the SLIC and can therefore be easily replaced by other ones. The transfer gates PG1 and PG2 are controlled by bits FR and FR in a reverse way. The drive bit FR also controls a PMOS transistor PM1 which is connected in series with a bias resistance R17 between VAG and the inverting input of the amplifier OA4 which has a negative feedback resistance R18. The series connection of R17 and PM1 is shunted by a resistance R19. The circuit just described operates as follows when a low ohmic (FR = 1) or a high ohmic line condition (FR = 0) has to be realised. Low ohmic line condition (FR = 1) In this case transfer gate PG1 is conductive, whereas transfer gate PG2 and transistor PM1 are both blocked. As a consequence the voltage, considered with respect to VAG, and equal to ri / 2 provided at the output of the sensing circuit SENC is attenuated and filtered in the filter circuit R14, R15, C2 and then amplified by a factor equal to In a preferred embodiment R18 = R19 so that this factor is then equal to 2. High ohmic line condition (FR = 0) In this case transfer gate PG1 is blocked, whereas transfer gate PG2 and transistor PM1 are both conductive. As a consequence the last mentioned voltage ri / 2 is filtered in the filter circuit R16, C3 and then amplified by a factor which is larger than in the low ohmic line condition. In a preferred embodiment R18 = R19 = 60 / 14 R17 so that the gain factor is larger than 5. As will become clear later, this will result in a voltage VEET of higher value and hence in a smaller line current. It should be noted that since in the high ohmic line condition the gain has to be increased, the filter R16, C2 does not include a resistance comparable to R15 and which would decrease this gain. The output of amplifier OA4 is connected to a unity gain circuit controlled by the polarity reversal bit BR0 and the complement BRO thereof. More particularly, this output is connected via a common resistance R20 and individual PMOS transistors PM2 and PM3 to the non-inverting and inverting inputs of an operational amplifier OA5 respectively. PM2 and PM3 are controlled by the respective bits BRO and BR0. The latter bit BR0 also controls PMOS transistor PM4 connected between VAG and the non-inverting input of OA5. The latter amplifier OA5 has a negative feedback branch comprising PMOS transistor PM5 and resistance R21 in series, the junction point of PM5 and R31 being connected to the output CL of the current limiting circuit CLC to be considered later. The gate of PM5 which is identical to PM3 is connected to the supply voltage V- and PM5 is therefore continuously conductive. The circuit just described operates as follows in the normal (BR0 = 0) and other (BR0 = 1) polarity conditions mentioned above : Normal condition (BR0 = 0) In this case transistors PM3, PM4 and PM5 are conductive, whereas transistor PM2 is blocked. As a consequence the output voltage, considered with respect to VAG, provided by the amplifier OA5 is amplified by a factor equal to In a preferred embodiment R20 = R21 so that the latter gain factor is equal to -1. Other conditions (BR0 = 1) In these cases transistors PM2 and PM5 are conductive, whereas transistors PM3 and PM4 are blocked. As a consequence the voltage, considered with respect to VAG, generated at the output of the amplifier OA5 is amplified by a factor equal to 1. It should be noted that the continuously conductive transistor PM5 in the negative feedback path of OA5 is provided in order that its impedance Z should compensate the same impedance of PM3 in the forward path i.e. in the path by which resistance R20 is connected to OA5. Indeed, for instance in the case BR0 = 0 the gain factor is in fact equal to instead of From the above it follows that the voltage collected from the line is inverted twice, i.e. in SENC and OA5, in the normal condition (BR0 = 0) and once in the other conditions (BR0 =1). In this way the signal at the output of amplifier OA5 is independent from the direction of the line current. The output of amplifier OA5 is connected to the non-inverting input of an operational amplifier OA6 via a filter circuit which comprises series resistances R22 and R23 and shunt capacitance C4. The resistance R22 is connected in parallel with the emitter-to-base junction diodes of the diode-connected NPN transistor N1 and PNP transistor P1. The purpose of this filter circuit is to filter small residual AC signals, such as speech, as well as to pass to its output large DC signals, such as the one produced when a subscriber goes off hook, substantially without distortion and very rapidly. This is achieved as follows : for a large positively or negatively directed DC voltage variation transistor N1 or P1 becomes conductive and short-circuits the resistance R22 due to which the time constant of the filter R22, R23, C4 is reduced so that this voltage variation is rapidly supplied to OA6. On the contrary, for a smaller voltage variation the resistance R22 is not short-circuited so that this variation is more filtered before being supplied to OA6. The voltage applied to the input of OA6 is called V1 + VAG. The inverting input of amplifier OA6 is controlled from the output VX of the polarity reversal circuit PRC as well as from a circuit controlled by the battery bit BV and the complement BV thereof. The inverting input of OA6 is connected to its output via resistance R24 and the emitter-to-base junction of PNP transistor P2 whose collector is connected to V-. The emitter of P2, which constitutes the output VEET is connected to the PRC and to the inputs VEET of both the line amplifiers LOA0 and LOA1. The circuit controlled by BV and BV includes an operational amplifier OA7 and an associated voltage divider circuit connected between VAUX and VAG and comprising the emitter-to-collector path of PMOS transistor PM6 and resistances R25, R26 and R27 in series. The base of transistor PM6 is continuously biased by the constant voltage B1, so that PM6 continuously supplies a constant current to the last mentioned voltage divider. The non-inverting input of amplifier OA7 is connected to the bandgap reference voltage B2 and the tapping points TP2 and TP3 of the above voltage divider are connected to its inverting input via respective PMOS transistors PM21 and PM22 which are controlled by the battery bits BV and BV respectively. Tapping point TP1 of this voltage divider is connected to the inverting input of amplifier OA6 via resistance R28. The circuit just described operates as follows : in case BV = 0 (battery of -48 Volts) transistors PM21 and PM22 are conductive and blocked respectively so that the reference voltage, say V2 + VAG, applied to the inverting input of amplifier OA6 via resistance R28, is equal to the reference voltage B2, also considered with respect to VAG, multiplied by a gain factor equal to in case BV = 1 (battery of -60 Volts) this gain factor is equal to because transistors PM21 and PM22 are then blocked and conductive respectively. This factor is larger than in the case BV = 0 and gives rise to a smaller VEET, as will become clear later. Thus the supply of a larger line current is ensured since this current is function of V+ - VEET - 2x. In a preferred embodiment and R27 = 4 R26 so that the gain factor is equal to 1.65 for BV = 0 and larger than 2 for BV = 1 respectively. The output VX of the polarity reversal circuit PRC is connected to the junction point of three series connected diode connected NPN transistors N2 to N4 and a resistance R29 via the series connection of a resistance R30, the base-to-emitter junctions of NPN transistors N5 and N6 which form a Darlington pair, a resistance R31 and the base-to-emitter junction of a PNP transistor P3 which forms a Common Emitter - Common Collector pair with NPN transistor N7. The collectors of N5 and N6 are both connected to the supply voltage V+, and the emitter and collector of transistor P3 are joined to the collector and base of transistor N7 respectively. The emitter of the latter transistor N7 is connected to a current source comprising NPN transistors N8, N9 and N10 and resistances R32 and R33. More particularly, this emitter is connected to the supply voltage V- via the collector-to-emitter path of N8 and resistance R32 in series. The emitter of N7 is also connected to the base of transistor N9 whose collector-emitter path is connected between VAUX and the base of transistor N8. Finally, the base of current source transistor N8 is connected to the base of transistor N10 whose emitter is connected to V- via resistance R33 and whose collector is connected to the inverting input of amplifier OA6. Because the voltage at the output VX of the PRC is equal to V+ -2x and when calling V(N) the VBE of a transistor N, the voltage at the upper end of resistance R31 is equal to V+ -2x - V(R30) - V(N5) - V(N6), wherein V(R30) is the voltage drop in protection resistance R30. On the other hand the voltage at the lower end of the resistance R31 is equal to VAG - V(N2) - V(N3) - V(N4) + V(P3). The circuit is now so adjusted, by means of resistance R29 and possibly also by resistance R30, that the VBEs of the transistors are cancelled so that the current I flowing through the resistance R31 is given by This current flows to V- mainly via the collector-emitter paths of NPN transistors N7 and N8 and resistance R32 in series. Because of current mirror transistor N10 this current also flows in the collector of the latter transistor so that it is derived from the inverting input of amplifier OA6. When calling, as already mentioned : V1 + VAG the voltage applied to the non-inverting input of OA6; V2 + VAG the reference voltage applied to the inverting input of OA6 via resistance R28, one may calculate that the output voltage VEET of OA6 is given by the following relation : In a preferred embodiment R24 = R31, so that in this case VEET is independent from VAG, and so that VEET is then given by : VEET = V+ -2x + 13V1 - 12V2 (3) The current limiting circuit CLC shown in Fig. 3 is now considered. The output CLC of filter circuit R16, C3 is also connected, on the one hand to the non-inverting input of operational amplifier OA8 via PMOS transistor PM7 and, on the other hand to the inverting input of OA8 via resistance R34 and PMOS transistor PM8 in series. The non-inverting input of OA8 is connected to VAG through bias resistance R35 and its inverting input is connected to its output via PMOS transistor PM9 and resistance R36 in series. The gates of transistors PM7 and PM8 are controlled by the Boolean functions BRO + FR and BRO + FR respectively, whereas the base of transistor PM9 is connected to V- and is therefore continuously conductive. The circuit just described operates as follows : when FR = 0 (high ohmic line condition) both transistors PM7 and PM8 are blocked and no current limitation is performed; when FR = 1 (low ohmic line condition) the circuit operates either as an inverter (BR0 = 0) or as a follower (BR0 = 1) in order that in all the conditions (BR0 = 1) a signal independent from the direction of the current line should be supplied to the current limiting circuit proper which is connected to the output of amplifier OA8. Indeed : when BR0 = 0, transistors PM7 and PM8 are blocked and conductive respectively so that the signal applied to the circuit is multiplied by a gain factor equal to - or -1 when R34 = R36; when BR0 = 1, transistors PM7 and PM8 are conductive and blocked respectively, so that the gain factor is then equal to 1. Again transistor PM9 is provided in order to compensate the impedance of PM8. The output of amplifier OA8 is connected via a resistance R37 to a first input of a differential amplifier whose other input is connected to tapping points TP4 to TP7 of a voltage divider via the pairs of series connected PMOS transistors PM10, PM11; PM12, PM13; PM14, PM15 and PM16, PM17 controlled by the current limit bits CTO , CT1 ; CTO, CT1 ; CTO , CT1 and CT0, CT1 respectively. The voltage divider comprises resistances R38 to R42 connected in series between bandgap reference voltage B2 and VAG. The inputs of the differential amplifier are constituted by the bases of NPN transistors N11 and N12 whose emitters are connected to a common bias current source comprising PMOS transistor PM18, NPN transistors N13 and N14 and resistances R43 and R44. The supply source VAUX is connected to V- via the source-to-drain path of PM18 which is controlled by bias source B1, the collector-to-emitter path of diode connected transistor N14 and resistance R44 in series. The joined emitters of N11 and N12 are connected to V-via the collector-to-emitter path of current mirror transistor N13 and resistance R43 in series. The base of N13 is connected to both the collector and base of N14. The collector of N12 is connected to VAUX which is connected to the collector of transistor N11 via the diode connected PMOS transistor PM19 which forms part of a current source/current mirror configuration. This configuration further includes PMOS transistor PM20, NPN transistors N15 and N16 and resistances R45 and R46. More particularly, the gate of PM19 is connected to that of PM20 whose source is connected to VAUX and whose drain is connected to V- via the collector-to-emitter path of diode connected transistor N15 and resistance R45 in series. The base of transistor N15 is connected to that of transistor N16 whose emitter is connected V- via resistance R46 and whose collector constitutes the output CL of the current limiting circuit CLC and is connected to the junction point of transistor PM5 and resistance R21. The circuit just described operates as follows. As long as the input signal applied to the base of transistor N11 is smaller than that applied to the base of transistor N12 and which depends on the value of the current limit bits CT0 and CT1, the constant current provided by the current source/current mirror circuit N13, N14, PM18 mainly flows through transistor N12 so that no current flows in the collector-to-emitter path of transistor N16 and that the operation of the circuit including amplifier OA5 is not influenced. On the contrary, when due to an increase of the line current, e.g. by a short-circuit, the input signal applied to the base of transistor N11 becomes larger than that applied to the base of transistor N12, the constant current provided by the circuit N13, N14, PM18 mainly flows through transistor N11. It is mirrored in the collector of transistor N16 via transistors PM19, PM20 and N15. As this current is withdrawn from the inverting input of amplifier OA5 less current flows through the feedback resistance R21 thereof so that the output voltage of OA5 is increased. This means that the above mentioned voltage V1 applied to the non-inverting input of amplifier OA6 is also increased and that consequently, as follows from the relation (3), the regulating voltage VEET is increased too. The effect of such an increase is to limit the line current, as required. It is clear from the above that the start of this line current decrease is function of the bits CT0 and CT1 which together determine the bias of transistor N12. To appreciate the above described circuit the following should be noted. Reference is hereby made to the above mentioned Belgian patent No 898049. In the latter patent the function of the circuit R14, R15, C2 is performed by separate filter and voltage divider circuits which are linked by a buffer amplifier in order that the voltage divider circuit should not constitute a load for the filter circuit. A drawback of the use of such a buffer amplifier is that it introduces a DC offset in the DC impedance synthesizing loop, that it produces noise and that it occupies a relatively large surface on the chip. In the circuit, described above the circuit R14, R15, C2 has a filter as well as a voltage divider function, so that it may be coupled to the high impedance non-inverting input of operational amplifier OA4 without the use of a buffer amplifier. Thus the accuracy of the regulating voltage VEET and therefore of the synthesized DC impedance is increased, the noise factor of the circuit is improved and the required chip surface is decreased. In the last mentioned Belgian patent use is made of a so-called absolute value circuit including two operational amplifiers (not shown in this patent) to make the DC impedance synthesis independent from the direction of the line current. In the present circuit the same result is achieved by the use of a single amplifier OA5 controlled by the bit BRO. Thus again the present circuit has a better performance than the known one. It should also be noted that the present circuit does not affect the DC level of the signals applied to it since these signals are either passed or inverted. This is not the case with the last mentioned absolute value circuit. Finally, in the circuit according to the above mentioned Belgian patent, the current limiting circuit is controlled from the output of the so-called absolute value circuit including two cascaded amplifiers producing a DC offset and to which the output of the sensing circuit is coupled via a filter circuit. On the contrary, in the present circuit the current limiting circuit is directly controlled from the filter circuit output. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims: Telecommunication line circuit including line amplifiers (LOA0/1) whose outputs are coupled to respective line conductors (LI0/1) of a telecommunication line via feed resistances (R0/1), and a resistance synthesis circuit for synthesizing a wanted resistance from said feed resistances, said synthesis circuit having inputs coupled with said feed resistances (R0/1) and an output (VEET) coupled to supply inputs (VEET) of said line amplifiers (LOA0/1), said output being constituted by the output of an operational amplifier circuit (OA6) which is controlled by a control voltage (VX) and to which said inputs are coupled through a line current sensing circuit (SENC) and an AC filter (R22, R23, C4), characterized in that said AC filter (K22, R23, C4) is directly connected to the non-inverting input of said operational amplifier circuit (OA6) whose output is coupled through a negative feedback circuit (P2, R24) to its inverting input which is connected to a control circuit to which said control voltage (VX) is applied and which is able to transform said control voltage (VX) into a control current and to derive this current from said inverting input. Telecommunication line circuit according to claim 1, characterized in that said control voltage (VX) is coupled to a first end of a first resistance (R31) through a series of forwardly biased first transistor junction diodes (N5, N6) of a Darlington first amplifier (N5, N6), whilst a first supply voltage (VAG) is connected to the second end of said first resistance (R31) through a series of forwardly biased second transistor junction diodes (N2, N3, N4, P5) of which the one directly connected to said second end forms part of a common emitter-common collector amplifier (P6, N7) whose output is coupled to said inverting input of said operational amplifier circuit (OA6) through a current source/current mirror configuration, and that the junction point of said series and said one second transistor junction diode is coupled to a second supply voltage (V-) through a compensation second resistance (R29) which has such a value that the voltage drops across said series of first and second transistor junction diodes are equal. Telecommunication line circuit according to claim 1, characterized in that the output (CO1) of said sensing circuit (SENC) is coupled through a second operational amplifier circuit (OA5) to said filter circuit (R22, R23, C4) which comprises a series branch constituted by series connected third (R22) and fourth (R23) resistances and a shunt branch constituted by a first capacitance (C4), said third resistance (R22) being shunted by first (N1) and second (N2) reversely branched diode connected first (N1) and second (N2) transistors whose bases and collectors interconnect the output of said second operational amplifier (OA5) and a negative feedback circuit thereof. Telecommunication line circuit according to claim 1, characterized in that the output (CO1) of said sensing circuit (SENC) is coupled to said filter circuit (R22, R23, C4) through a third operational amplifier circuit (OA5) the gain of which is controlled by a first binary signal (BR0) which is indicative of a first or a second polarity condition of said line and in such a way that a corresponding positive or negative unity gain is realised. Telecommunication line circuit according to claim 4, characterized in that said third operational amplifier circuit (OA5) has a negative feedback path constituted by the series connection of a continuously operated first transistor switch (PM5) and a fifth resistance (R21), as well as a forward path whose input is connected to the non-inverting and inverting inputs of said third operational amplifier circuit (OA5) through a second (PM2) and third (PM3) transistor switch respectively, said non-inverting input being moreover connected to a bias voltage (VAG) via a fourth transistor switch (PM4), and that said third (PM3) and fourth (PM4) transistor switches are controlled by said first binary signal (BR0), whilst said second transistor switch (PM2) is controlled by the complement ( BRO ) of said first binary signal (BR0). Telecommunication line circuit according to claim 5, characterized in that said first (PM5) and third (PM3) transistor switches are identical and the gain of said third amplifier circuit (OA5) is equal to unity. Telecommunication line circuit according to claim 1, characterized in that the output (CO1) of said sensing circuit (SENC) is coupled to said filter circuit (R22, R23, C4) through a fourth operational amplifier circuit (OA4) the gain of which is controlled by a second binary signal (FR) which is indicative of said synthesized resistance and in such a way that the synthesized resistance has a corresponding lower or higher value. Telecommunication line circuit according to claims 3, 5 and 7, characterized in that said second operational amplifier circuit is constituted by said third operational amplifier circuit (OA5), the output of said fourth operational amplifier circuit (OA4) being connected to the input of the forward path of said third amplifier circuit. Telecommunication line circuit according to claim 7, characterized in that the output (CO1) of said sensing circuit (SENC) is coupled to the non-inverting input of said fourth operational amplifier circuit (OA4) through a parallel circuit with first and second branches, said first branch comprising the series connection of a metering signal filter and voltage division network (R14, R15, C2) and a fifth transistor switch (PG1) and said second branch comprising the series connection of a metering signal filter (R10, C2) and a sixth transistor switch (PG2), said fifth (PG1) and sixth (PG2) transistor switches being so controlled by said second binary signal (FR) and the complement ( FR ) thereof in such a way that they are conductive when said synthesized resistance of lower and higher value has to be realised respectively. Telecommunication line circuit according to claim 9, characterized in that a supply voltage (VAG) is coupled to the inverting input of said fourth operational amplifier circuit (OA4) via a second parallel circuit a first branch of which comprises a sixth resistance (R19) and a second branch of which comprises the series connection of a seventh resistance (R17) and a seventh transistor switch (PM1) which is so controlled by said second binary signal (FR) in such a way that it is conductive together with said sixth transistor switch (PG2). Telecommunication line circuit according to claim 2, characterized in that a current limiting circuit which is controlled by current limiting signals (CT0, CT1) is coupled between the output (C01) of said sensing circuit (SENC) and the inverting input of said second operational amplifier circuit (OA5) and is able to derive current from said inverting input. Telecommunication line circuit according to claim 11, characterized in that said current limiting circuit includes a differential amplifier (N11/14, PM8) having a common bias current source (PM18, N13, N14) as well as a first and a second input, the output (C01) of said sensing circuit (SENC) being coupled to said first input through a control circuit which provides an output signal independent from the direction of the line current and said second input being coupled to the output of a reference circuit controlled by said current limiting signals (CT0, CT1) and providing a selectable reference voltage at its output. Telecommunication line circuit according to claims 4, 7 and 12, characterized in that said control circuit includes a fifth operational amplifier circuit (OA8) which is controlled by said first (BR0) and second (FR) binary signals in such a way that in case a higher synthesized resistance of higher value has to be realised a positive or negative unity gain is provided. Telecommunication line circuit according to claims 9 and 13, characterized in that the output (C01) of said sensing circuit (SENC) is connected to the non-inverting and inverting inputs of said fifth operational amplifier circuit (OA8) through said metering signal filter in common and respective first and second individual branches, said first branch comprising an eighth transistor switch (PM7) and said second branch comprising the series connection of an eighth resistance (R34) and a ninth transistor switch (PM8), that the non-inverting input of said fifth operational amplifier circuit (OA8) is connected to a supply source (VAG) through a ninth resistance (R35) whilst the inverting input thereof is connected to its output through are series connection of a continuously operated tenth transistor switch (PM9) and an eleventh resistance (R36), and that said eighth (PM7) and ninth (PM8) transistor switches are controlled by respective Boolean functions BRO + FR and BR0 + FR , wherein BR0 and FR are said first and second binary central signals and BRO and FR are the complements thereof. Telecommunication line circuit according to claim 14, characterized in that said ninth (PM8) and tenth (PM9) transistor switches are identical.

Inventors: MOONS, ELVE DESIDERIUS JOZEF, PIETERS, JOZEF FRANS PHARIDA
Applicants: ALCATEL N.V.
Application year: 1986
Main classification: H04M19
IPC codes: H04M19, H04M3