METHOD OF CONFIGURING N-TH DEGREE SWITCHED CAPACITOR FILTER

Abstract: A n-th degree switched capacitor filter having transfer characteristics expressed by a transfer function H(Z) can be configured by expanding this transfer function to a n-element linear simultaneous state equation of n state voltages inclusive of an output voltage. The coefficients of the transfer function a₁₁ to a n2 , b₁₁ to b nn are determined in a range within which the filter circuit can be configured by hardware and further each state voltage is below a maximum output voltage. In practice, the filter is configured by plural leapfrog type differential operational amplifiers (11, 12) having base capacitors C o , plural transmission gates, and plural electric charge transfer capacitors C T so as to determine each coefficient on the basis of ratios C T /C o .

Description: BACKGROUND OF THE INVENTION Field of the invention The present invention relates to a method of configuring any given n-th degree filter, and more particularly to a method of configuring a n-th degree filter preferably applied to a switched-capacitor filter. Description of the Prior Art Conventionally, LC filters composed of coils and capacitors are well known as filter circuits. However, since these LC filters are large in size and high in cost, it has recently been attempted to configure filters by use of integrated circuits. As methods of configuring such LC filters as described above, the use of gyrators, active filters, digital filters, switched-capacitor filters, have been studied. In particular, switched-capacitor filters have been highlighted owing to various advantages such as a high possibility of realizing the filters by monolithic ICs using MOS transistors, excellent electric characteristics, wide applicable fields, low cost, etc. However, thus far only leapfrog type and bi-quad type have been known as methods of configuring the switched-capacitor filters, and no satisfactory method of configuring a filter which can realize any given n-th degree transfer function has been known. In particular, in the case where a filter for a video signal band is required to be configured, a switching speed as high as 40 times higher than the reproduction band is required for the leapfrog type switched-capacitor filter. Further, in the case of the bi-quad type switched-capacitor filter, the method of determining the coefficients has not yet been well known, so that deviation in coefficients is readily produced, thus causing problems in that the filter is unstable or it is impossible to realize. A method of configuring an n-th degree switched capacitor filter having transfer characteristics expressed by any given n-th degree transfer function, can be derived from EP-A-58 113, in which the n-th degree transfer function is expanded to a state equation expressed by an n-element linear simultaneous equation with respect to n state voltages inclusive of an output voltage to configure a filter corresponding to the above state equation. However, such a method does not permit to determine the optimal filter coefficients implementing the desired filter transfer function within the hardware constraints relative in particular to : the maximum state voltage amplitudes, the minimum value of the desired signal to noise ratio (minimum state voltage amplitude), and on-chip circuit component limitations. SUMMARY OF THE INVENTION With these problems in mind, therefore, it is the object of the present invention to provide a method of configuring an n-th degree switched capacitor filter in which each coefficient of the n-th degree filter can be determined readily and reasonably, capable of yielding a unique and optimal answer in the sense of signal to noise ratio (if implemented on a computer). To achieve the above-mentioned object, it is proposed the method which is defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the method of configuring an n-th degree switched capacitor filter according to the present invention will be more clearly appreciated from the following description of the preferred embodiment of the invention taken in conjunction with the accompanying drawings in which: Fig. 1 is a state diagram corresponding to the one obtained by expanding the transfer function of a quadratic filter to a two-element linear simultaneous state equation; Fig. 2 is a flowchart for determining optimum coefficients of a simultaneous state equation of the quadratic filter; Fig. 3 is a practical circuit diagram of a quadratic switched capacitor filter configured by the two-element linear simultaneous state equation; Fig. 4 is a state diagram corresponding to the one obtained by expanding the transfer function of an n-th degree filter to an n-element linear simultaneous state equation; and Fig. 5 is a state diagram corresponding to a linear filter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to the attached drawings, reference is now made to the method according to the present invention. Basic Principle The basic principle of the method of configuring an n-th degree switched capacitor filter related to the present invention will first be described. In digital filters, in general, configurations for generating an output by linearly-coupling n-piece past inputs have been well known. However, in such a filter as switched capacitor for implementing analog calculations, the method of using a great past data is not appropriate because the signal conserving capacity is not sufficient. To overcome this problem, in the case of filters for realizing an n-th degree transfer function, there has been adopted a so-called linear state method such that each state voltage is changed into V₁(N) to V n (N) according to coming input voltages V₁(N) by use of a group of n-piece inner state voltages V₁ to V n of the filter circuit and an input voltage V I , when each voltage reaches V₁(N-1) to V n (N-1), in correspondence to the present filter state. In this method, the succeeding state can be determined on the basis of only an input voltage V I prior to one unit time and the states of inner state voltages V₁ to V n , and thereby the number of signals to be conserved is that corresponding to one unit time (one clock period). Therefore, this method is suitable for the switched capacitor filters based mainly upon analog calculations. Further, a digital filter can be configured in accordance with this method in such a way that an output voltage V o is generated by selecting any one or more signals from the inner state voltages V₁ to V n . Method of configuring quadratic filter By way of example of such a linear state method as described above, a method of configuring a quadratic filter will be described hereinbelow. When the following equation is given as a quadratic transfer function H(z) and a quadratic filter for realizing the above transfer function (1) is required to be configured it is possible to obtain a two-element linear simultaneous state equation with respect to two inner state voltages V₁(z) and V₂(z) of the quadratic filter as follows: where V I (z) denotes an input voltage The above equation (2) can be rewritten as follows; When the V₁(z), for instance, is determined to be an output voltage V₀(z) in the equation (2) or (2'), the output voltage V₀(z) (=V₁(z)) is obtained by eliminating the inner state voltage V₂(z) as follows: By transforming this equation (3) as H(z) = V₀(z) / V I (z) and by comparing the equation (3) with the equation (1), it is possible to obtain the corresponding relationship between each coefficient α₀ to β₂ and a₁₁ to b₂₂ as follows: Further, the other inner state voltage V₂(z) can be expressed by eliminating V₁(z) as follows: The above V₂(z) may be determined as an output voltage. These equations (3) and (5) indicate that V₁ and V₂ have the same pole. Here, the matrix determined by the first-term coefficients a₁₁ to a₂₂ on the right side of the equation (2) is referred to as A-matrix or an input matrix and the matrix determined by the second-term coefficients b₁₁ to b₂₂ on the right side of the same equation (2) is referred to as B-matrix or a pole matrix. The zero point thereof is determined by coupling of these two A- and B-matrix elements. Here, the equation (2) or (2') is equivalent to a state diagram as shown in Fig. 1, which can be determined as a practical circuit configuration as it is. That is, in Fig. 1, each voltage V₁ or V₂ (one is taken out as an output voltage V₀) is self-attenuated by the coefficients b₁₁ and b₂₂. In a practical circuit, the circuit is configured by operational amplifiers of self-feedback type. The coefficients b₁₂ and b₂₁ indicate the mutual coupling of each voltage V₁ and V₂ and are configured by a so-called leapfrog circuit in which one operational amplifier mutually functions as a feedback circuit to the other operational amplifier. The coefficients a₁₁ to a₂₂ indicate the contribution of an input voltage V I to each voltage V₁ and V₂. The method of determining each coefficient a₁₁ to b₂₂ of the above-mentioned simultaneous state equation expressed by equation (2) or (2') on the basis of each coefficient α₀ to β₂ of the previously-given transfer function expressed by equation (1) will be described hereinbelow. First, it is required that the absolute value of each coefficient a₁₁ to b₂₂ of the state equation should be in a range between the maximum value M a and the minimum value M i because there exists a condition on hardware in order to allow the filter circuit to be realized in practice. Additonally, with respect to the inner state voltage other than the output voltage, for instance, such as V₂, there exists a requirement such that if the maximum absolute value of the output voltage V₀ is P (= | V₀ | max), the maximum absolute value of V₂ should be less than P ( P≧ | V₂ | max). Further, it is desired that the lower limit value Q ( | V₂ | min≧Q) is large enough not to deteriorate the S/N ratio. Further, as understood by the equation (4) , the coefficient a₁₁ is α₀ itself, and if coefficients a₁₂, a₂₁, and a₂₂, are determined, the remaining coefficients b₁₁ to b₂₂ can be determined unconditionally as follows: Therefore, in practice the coefficients a₁₁ to b₂₂ which satisfy the above-mentioned conditions can be obtained by variously changing a group of these coefficients a₁₂, a₂₁, and a₂₂ with the coefficient a₁₂, a₂₁, or a₂₂ as an independent variable, respectively. The determination of each coefficient a₁₁ to b₂₂ as described above can be made automatically by use of a computer, which will be described with reference to a flowchart shown in Fig. 2 by way of example. In Fig. 2, first in step 101, control sets the control variable to N=0 and proceeds to the next step 102 to set the lower limit value Q. In the first process, this lower limit value Q is set to a value (Q=P) equal to the maximum absolute value P (= | Vo | max) of the ouput voltage because a high S/N ratio is required. This Q is reduced as described later only where a group of coefficients a₁₁ to b₂₂ satisfying the condition is not obtained in the subsequent steps. In the succeeding step 103, as described above the coefficients a₁₂, a₂₁, and a₂₂ are changed in a range within which each absolute value | a₁₂ |, | a₂₁ | or | a₂₂ | of these coefficients lies between the upper limit Ma and the lower limit M i . In this step, the form of coefficient change, that is, the kinds of groups of coefficients a₁₂, a₂₁, and a₂₂ are finite when the magnitude of unit change (changed steps) of each coefficient has previously been determined, so that plural kinds of coefficient groups are selected in accordance with a predetermined sequence, proceeding to the next step 104. In step 104, control discriminates whether the above-mentioned finite change form, that is, all the combinations of coefficients a₁₂, a₂₁, and a₂₂ possible have been selected (the change completion). If YES, control proceeds to step 105; if NO, to step 106. In step 106, the remaining coefficients b₁₁ to b₂₂ are calculated and determined on the basis of the selected coefficients a₁₂, a₂₁, and a₂₂ and the coefficients α₀ to β₂ of the above transfer function in accordance with the above equation (6). In step 107, control discriminates whether the absolute values of these coefficients b₁₁ to b₂₂ lie within a range between the above upper limit Ma and the lower limit Mi (Ma ≧ b₁₁ |, |b₁₂ |, |b₂₁ |, |b₂₂ |≧ Mi). If NO, control returns to the step 103 to change the combination of the coefficients a₁₂, a₂₁, and a₂₂; if YES, control proceeds to step 108. In step 108, the inner state voltage V₂ is calculated in accordance with the equation (5) and determines the maximum absolute value |V₂ | max. In the succeeding step 109, control discriminates whether this |V₂ | max is less than the upper limit P (= |Vo| max) but more than the lower limit Q. If NO, control returns to step 103; if YES, control proceeds to the next step 110. In step 110, the control variable N is incremented (N=N+1) and proceeds to the succeeding step 111. In step 111, control determines and stores the maximum coefficient Kmax (N) and the minimum coefficient Kmin (N) from among the determined coefficients a₁₁ to b₂₂, returning to the step 103. As described above, after all the possible combinations of coefficients have been completed (the change completion) by sequentially changing the coefficients a₁₂, a₂₁, and a₂₂, control determines YES in step 104 and proceeds to step 105. In this step 105, control discriminates whether the control variable N is zero or not. If YES (N=0) , this indicates that the combinations of coefficients a₁₁ to b₂₂ which satisfy the above condition have not been obtained. Therefore, control proceeds to the step 112 at which the lower limit value Q is reduced, thereafter returning to the step 103. In this case, in step 103, the change operation of each coefficient a₁₂, a₂₁, or a₂₂ is restarted from the beginning; that is, the operations from step 103 to step 111 are repeatedly executed of all the possible combinations of coefficients. On the other hand, if NO (N≠0) is determined in step 105, this indicates that at least one combination of coefficients a₁₁ to b₂₂ which satisfies the condition has been obtained. In the succeeding step 113, control determines a group of coefficients having a minimum difference between the maximum coefficient value Kmax (N) and the minimum coefficient value Kmin (N) of each group from among the obtained combinations of coefficients, as an optimum combination of filter coefficients. As described above, since the initial value of Q is determined as P (Q=P= |Vo | max) and the Q is reduced gradually by checking all the combinations of coefficients a₁₂, a₂₁, and a₂₂ realizable by hardware, it is possible to determine the filter coefficients with a relatively high Q value, thus it being possible to obtain a filter having a dynamic range of high S/N ratio. The quadratic filter circuit expressed by the two-element linear simultaneous state equation having optimum coefficients a₁₁ to b₂₂ determined as described above can readily be configured by hardware on the basis of the state diagram shown in Fig. 1. By way of example, there will be explained an embodiment where a switched-capacitor filter is configured in practice by a CMOS (complementary metal oxide semiconductor) circuit on the basis of the simultaneous state equation corresponding to the above filter circuit. To realize a switched-capacitor filter, operational amplifiers, transmission gates, and capacitors, etc. are necessary. In the case where the filter is configured independently, although a clock-noise eliminator, an input clamp circuit, a clock forming circuit, a post/pre-filter and an output circuit are additionally required, the description of these circuits are omitted herein because these are not directly related to the gist of the present invention. On the basis of the state diagram shown in Fig. 1, it is possible to configure a switched-capacitor filter as shown in Fig. 3. In Fig. 3, two CMOS operational amplifiers 11 and 12 are configured as a complete differential type to avert the influence of a clock signal. Capacitors C₀ connected in the feedback loops of these operational amplifiers 11 and 12 are so-called base capacitors. The coefficient (a₁₁ or others) is determined on the basis of a ratio (C₁/C₀) of the base capacitor (C₀) to switching-controlled capacitor (C₁ or others) (so-called electric charge transfer capacitor C T ). A non-inversion input voltage V I is supplied to an input terminal 1 and an inversion input voltage V I , is supplied to an input terminal 2 so as to correspond to the complete differential type operational amplifiers. Further, in Fig. 3 the circuit block 13 corresponds to the coefficient matrix (input matrix) of the first term on the right side of the equation (2); the circuit block 14 corresponds to the coefficient matrix (pole matrix) of the second term on the right side of the same equation (2). Here, in order to realize the coefficients a₁₁to b₂₂ in the switched-capacitor filter circuit, transmission gates and electric discharge transfer capacitors C T are necessary. Each coefficient a₁₁ to b₂₂ can be determined on the basis of the ratios C T /C₀ of these capacitors C T to the base capacitor C₀ connected in the feedback loop of the operational amplifiers. In Fig. 3, these electric discharge transfer capacitors C T correspond to capacitors C₁ to C₁₀. However, as in a₁₂Z⁻¹ or a₂₂Z⁻¹ of the input matrix, when a unit time (one clock period) delay is required for the input voltage V I , two electric discharge transfer capacitors C₂, C₃ or C₇, C₈ are connected in sequence, respectively so as to delay the signal electric charge by one clock (one bit) for each two transfer. In this case, since the electric discharge to be transferred is half in practice, C₂/C₀are and C₃/C₀ are allowed to correspond to 2a₁₂ twice as long as coefficient a₁₂; and C₇/C₀ and C₈/C₀ are allowed to correspond to 2a₂₂ twice as long as coefficient a₂₂. Further, although the output of each operational amplifier 11 or 12 corresponds to the inner state voltage V₁ or V₂, since there exists one clock (one bit) delay with respect to the input V I , one capacitor C₄, C₅, C₉ or C₁₀ is used, respectively, as electric discharge transfer capacitors for realizing the coefficient b₁₁Z⁻¹, b₁₂Z⁻¹, b₂₁Z⁻¹, or b₂₂Z⁻¹ of the pole matrix. However, since the inversion output of the operational amplifier is feedbacked to the non-inversion input thereof and the non-inversion output thereof is feedbacked to the inversion input thereof, respectively, (1-b₁₁) corresponds to C₄/C₀ in coefficient b₁₁; (1-b₂₂) corresponds to C₉/C₀ in coefficient b₂₂. Either one of the inner state voltages V₁ or V₂ is taken as an output voltage V₀. In the the example shown in Fig. 3, an output voltage V₂ of the inversion output terminal of the operational amplifier 12 is taken out through an output terminal 3 as a filter output voltage. In the quadratic filter circuit as described above, since self feedback loops are provided for each operational amplifier 11 or 12, it is possible to obtain a stable operation. Method of configuring n-th degree filter The method of configuring any given quadratic filter circuit on the basis of the linear state method has been described above. In the same way, it is possible to configure any given n-th degree filter circuit on the basis of the linear state method. Any given n-th degree transfer function H(Z) can be expressed as Corresponding to this equation (7), an n-element linear simultaneous state equation for n-piece state voltages V₁(Z) to V n (Z) of a circuit including an output voltage V₀(Z) can be obtained as follows: where V I (Z) denotes an input voltage. The above equation can be obtained as follows: if the state voltage V n (Z) is determined as an output voltage V o (Z), for instance, the relationship between the output voltage V₀(Z) (=V n (Z)) and the input voltage V I (Z) is obtained by eliminating V₁(Z) to V n-1 (Z) from equation (8), and then an equation corresponding to equation (6) can be obtained by H(Z) = V₀(Z)/V I (Z). Thereafter, by comparing coefficients of each term, respectively, it is possible to obtain the relationship between α n to α₀, β n to β₀ of equation (7) and a₁₁ to a n2 and b₁₁ to b nn of equation (8). In the same way as in the above-mentioned quadratic filter, the n-element linear simultaneous state equation (8) can be expressed by a state diagram as shown in Fig. 4. As already described, this state diagram can be allowed to correspond to a practical circuit configuration in the same form. Here, in considering the meanings of the simultaneous state equation (8) and the state diagram shown in Fig. 4, if the transfer function H(Z) of any given linear filter is expressed as the state equation is V₀(Z) = [a₁₁a₁₂Z⁻¹] V I (Z) + b₁₁Z⁻¹V₀(Z) (10) where V₀(Z) denotes an output voltage and V I (Z) denotes an input voltage. The state diagram corresponding to this equation (10) becomes as shown in Fig. 5. In Fig. 5, the output voltage V₀ is self-attenuated by the coefficient b₁₁. This indicates an attenuation represented by e -kt . The practical circuit can be configured by operational amplifiers which can effect self-feedback. Further, the input voltage V I is supplied to the operational amplifiers through transmission gates corresponding to a₁₂Z⁻¹ including coefficients a₁₁ or other and delay elements, thus contributing to the output voltage V₀. Further, in the case where an n-th degree filter more than quadratic filter is configured, the output voltage V₀ of the basic configuration shown in Fig. 5 is replaced with n-piece inner state voltages V₁ to V n and the mutual communication is effected between state voltages V₁ to V n , respectively; that is, so-called leapfrog resonance is effected as shown by the dashed lines in Fig. 4. In the practical circuit, this mutual communication can be realized by transferring signals via the transmission gates including delay elements and coefficients between two of the operational amplifiers, respectively. Further, in the same way as in the already-mentioned quadratic filter, each coefficient a₁₁ to a n2 , or b₁₁ to b nn of the simultaneous state equation expressed by equation (8) is determined as follows: the absolute values of the coefficients a₁₂ to a n2 are changed so as to lie within a range between Ma and Mi with these values as variables; it is discriminated whether the absolute values of the coefficients b₁₁ to b nn at that moment lie within a range between Ma and Mi; and it is discriminated whether the inner state voltages V₁ to V n lie within an appropriate range, that is between P (= |V₀ | max) and Q. Further, when a number of combinations of the coefficients a₁₁ to a n2 and b₁₁ to b nn which satisfy these conditions are selected, a combination of the coefficients having a minimum difference between the maximum value and the minimum value in the same group of coefficient is selected as an optimum group of coefficients. Further, without being limited to the above embodiments, it is possible to apply the present invention to various practical filter circuits such as digital filters other than switched-capacitor filters. By the method of configuring n-th degree filters according to the present invention, it is possible to reliably configure filter circuits having any given n-th degree transfer function on the basis of the linear state method. Further, the coefficients of the filter lie within a range realized by hardware and further the inner state voltages lie within an appropriate range, so that it is possible to realize a high S/N ratio and a wide dynamic range. Further, it is possible to resonably and readily select the optimum filter coefficients having the minimum difference between the maximum value and the minimum value.

Claims: A method of configuring an n-th degree switched capacitor filter having transfer characteristics expressed by as any given n-th degree transfer function H(z), in which the above n-th degree transfer function H(z) is expanded in the form of an n-element linear simultaneous state equation of n state voltages V₁ to V n inclusive of a last-stage output voltage as where V I denotes an input voltage; each coefficient a₁₁ to a n2 , b₁₁ to b nn of the above state equation is changed in a range within which the filter circuit can be configured by hardware with each coefficient as variable; a group of coefficients a₁₁ to a n2 and b₁₁ to b nn is so determined that each state voltage V₁ to V n is below a finally-obtained maximum output voltage; and a filter circuit is configured so as to correspond to the above simultaneous state equation having each coefficient determined as recited above, coefficients a₁₁ to b nn are determined in accordance with the following steps of: (a) setting a lower limit Q of inner voltages to a maximum absolute value P of an output voltage V o (Q=P= |V o | max); (b) setting a maximum value M a and a minimum value M i of each coefficient a₁₁ to a n2 , b₁₁ to b nn on the basis of the following hardware limitations: maximum and minimum capacitance values, maximum inner voltage range and switching frequency; (c) steppedly changing each absolute value of each coefficient a₁₁ to a n2 within a range between the maximum value M a and the minimum value M i (M i ≦ |a₁₁ | to |a n2 | ≦ M a ) to obtain all possible combinations of coefficients a₁₁ to a n2 ; (d) discriminating whether all the combinations of coefficients a₁₁ to a n2 , b₁₁ to b nn have been selected; (e) if no, calculating all coefficients b₁₁ to b nn on the basis of the selected coefficient a₁₁ to a n2 and the transfer function coefficients α o to α n , β o to β n in accordance with equations representative of relationship between a₁₁ to a n2 and b₁₁ to b nn through intermediary of α o to α n , β o to β n ; (f) discriminating whether the absolute values of the calculated coefficients b₁₁ to b nn lie between the lower limit M i and the upper limit M a (M i ≦ | b₁₁ | to |b nn | ≦ M a ); (g) if no, returning to the above step (c) to change the combinations of coefficients a₁₁ to a n2 ; (h) if yes, calculating inner state voltages V n in accordance with equations obtained by eliminating inner voltages other than V n on the basis of the simultaneous state equation to determine a maximum absolute value |V n | max; (i) discriminating whether the calculated maximum absolute inner state voltage |V n | max lies between the upper limit P and the lower limit Q(Q ≦ |V n | max ≦ P); (j) if no, returning to the step (c) above; (k) if yes, incrementing control variable N; (l) storing the maximum coefficient Kmax (N) and the minimum coefficient Kmin (N) among the determined coefficients a₁₁ to a n2 , b₁₁ to b nn and returning to the above step (c); (m) if yes in step (d) above indicating all possible combinations of coefficients a₁₁ to a n2 , b₁₁ to b nn have been selected, discriminating whether the control variable N is zero; (n) if yes (N=0), reducing the lower limit Q and returning to the step (c) above; and (o) if no (N≠0), determining an optimum combination of coefficients a₁₁ to a n2 , b₁₁ to b nn having a minimum difference between the maximum coefficient value Kmax (N) and the minimum coefficient value Kmin (N). An n-th degree switched capacitor filter configured in accordance with the method as set comprises: (a) a number n of differential operational amplifiers each including two base capacitors C o in each feedback loop thereof; (b) an input circuit of said differential operational amplifiers having plural transmission gates and plural electric charge transfer capacitors C T for configuring the first term of the right side of the expanded n-element linear simultaneous state equation in such a way that each coefficient a₁₁ to a n2 can be determined on the basis of each capacitance ratio C T /C o of the base capacitor C o to each electric charge transfer capacitor C T and the delay Z⁻¹ can be determined by additionally connecting another capacitor in series with C T ; and (c) an output circuit of said differential operational amplifiers having plural transmission gates and plural electric charge transfer capacitors C T for configuring the second term of the right side of the expanded n-element simultaneous state equation in such a way that each coefficient b₁₁to b nn can be determined on the basis of each capacitance ratio C T /C o of the base capacitor C o to each electric charge transfer capacitor C T and the delay Z⁻¹ can be determined by connecting each inversion output terminal to each non-inversion input terminal or vice versa.

Inventors: KIKUCHI, ATSUSHI, NISHIMURA, TOSHIMICHI
Applicants: SONY CORPORATION
Application year: 1986
Main classification: H03H19
IPC codes: H03H19, H03H17