METHOD AND APPARATUS FOR INTERFACING BETWEEN ANALOG SIGNALS AND A SYSTEM BUS

Abstract: An interface unit between analog signals from a device being monitored and a digital signal data bus includes a multiplexer unit, a sample and hold amplifier, an analog to digital converter, a buffer memory unit, and control circuits. The control circuits are responsive to signals from a central processing unit and can control the operating parameters of the interface unit, including a software programmable clock. The control circuits can also generate interrupt signals.

Description: METHOD AND APPARATUS FOR INTERFACING BETWEEN ANALOG SIGNALS AND A SYSTEM BUS BACKGROUND OF THE INVENTION Field of the Invention 5. ' This invention relates generally to an apparatus providing an interface between devices having analog output signals and a system signal bus for exchanging digital signals with a central processing unit. Discussion of the Related Art 10* It is known in the related art to provide an interface apparatus that can sample and hold selected analog signals produced by monitoring or by control devices. The signals are in turn applied to an analog to digital converter and, in turn, the signals can be transferred to a data bus. The data bus applies the signals to data 15. processing apparatus that can manipulate the data in a predetermined manner. In the past the capability of the apparatus interfacing between a system data bus and the analog signals produced by the devices being monitored has been severely limited. The operating capabilities of 20. the interface unit are fixed, either during the manufacture of the unit or else are controllable by switches. However, the interface unit can receive signals from the monitored devices that are to be processed in a plurality of modes. For example, instead of the normal sampling mode of an analog 25. signal, a transient data capture mode (in which a group of data is acquired for a predetermined period of time) can be desirable. The changing of the inode of operation of the interface unit has in the past required manipulation of the interface unit, an activity that can - - be inconvenient for interface units located at remote or inaccessible sites. If the services require a plurality of operation modes for the monitoring operation, then in the past a plurality of interface units was required. 5. A need has therefore been felt for an interface unit that can provide processing capability to permit control functions to be performed in the interface unit. The control circuits of the interface unit can permit the user to select from a plurality of operating options and modes. 10. ' SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved interface unit coupling analog data signals with a system data bus. It is another object of the present invention to provide an interface unit for coupling analog data signals with a system data bus 15 ^ that can be programmable from a central processing unit. It is yet another object of the present invention to provide an interface unit between analog data signals and a system data bus that includes a software programmable timer. It is still a further object of the present invention to provide 20.an interface unit coupling analog data signals and a system data bus for which a user can control a plurality of modes of operation. It is a more particular object of the present invention to permit one of a plurality of analog signals monitored by apparatus coupled to a system data bus to be selected and to be monitored in a plurality of 25. odes controlled by a central processing unit. The aforementioned and other features are accomplished according to the present invention by providing an interface unit multiplexer capable of receiving a plurality of analog signals, a sample and hold amplifier for storing a quantity related to a selected analog signal 25.at a predetermined time, an analog to digital converter for providing a digital signal related to the amplitude of the sampled analog signal, a data memory unit for storing the digital value of the signal prior to placing the value on the signal data bus for transmission to the central processing unit, and control circuits for determining the mode of operation of the associated interface apparatus and for providing a sufficient programmable timer. " The control circuits include a clock, a control unit for controlling the operation of the remaining units, and an apparatus for 5. providing an interrupt request and related data to the central processing unit. The control circuits permit each analog signal applied to the interface apparatus to be monitored in the most appropriate manner. Interrupt circuits are provided to inform the central processing unit of the availability of data signals in the 10. interface apparatus. These and other features of the present invention will be understood upon reading the following description along with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS 15. Figure 1 is a general block diagram showing the position of the interface unit with respect to the analog input signals and the data bus. Figure 2 is a block diagram showing the principal components of the interface unit. 20. Figure 3a is a diagram showing the location of signals entered in the control registers to control the signal processing. Figure 3b is a diagram showing the location of signals in the interface unit to be transmitted to the central processing unit. Figures 4a-4d, 5a-5d, and 6a-6c together comprise a detailed 25. schematic diagram of the interface unit of the present invention. Figures 7a-7c illustrate the orientation of Figures 4a-4d, 5a-5c, and 6a-6c respectively. DESCRIPTION OF THE PREFERRED EMBODIMENT Detailed Description of the Figures 30. Referring to Figure 1, the general position of the interface unit of the present invention with respect to the remainder of the system is shown. Signals are provided by the devices or apparatus being monitored. These signals are typically signals extracted from or related directly to the signal operation of the monitored apparatus. The signals are typically in analog form and unsuitable for direct 5.application to a system data bus requiring'a digitally formatted signal group. The interface apparatus couples the analog signals to the system data bus 11. The system data bus is coupled to central processing unit 9. Referring to Figure 2, the principal components of the interface 10. apparatus are shown. The multiplexer 21 receives one or more analog input signals at the input terminal of multiplexer 21. A selected one of these analog signals is transmitted to the output terminal of multiplexer 21. A latch circuit can be included to control the operation of the multiplexer without the requirement of continuous 15. application of a control signal. The signal at the output terminal of multiplexer 21 is applied to sample and hold amplifier 22. The sample and hold amplifier 22 applies an output signal to an analog to digital converter 23, and the output signal of the analog to digital converter 23 is applied to data 20. memory unit 24. The data memory unit is coupled to the data register 25. A control logic unit 29 is coupled to the multiplexer 21, the sample and hold amplifier 22, the analog to digital converter 23, the data memory unit 24, and the data register 25. The control logic unit 29 receives signals from a clock 29a and from control registers 28. 25. The control registers 28 receive signals from address and decoder unit 27 and exchange signals with data transceiver 26. The address and decoder unit 27 also applies signals to data register 25 and to interrupt register 41. The interrupt register 41 exchanges signals with data transceiver 26 and applies signals to interrupt request and ' 25. vector unit 41. The interrupt request and vector unit 41 applies signals to the system data bus 11. The address and decoder unit receives signals from the system data bus 11 and determines whether the signals are intended for the selected interface unit and to what location in the selected interface unit the incoming data signals are 30. directed. Referring to Figure 3a, the write date memory configuration is shown. (The base address of the interface unit can be selectable by jumper connections) . The data can occupy four consecutive word locations. The first word location includes the start conversion 5. data, while the second word includes the control register data. The third word includes the number of blocks and the conversion period, while the fourth word includes an enable signal, interrupt level, and an interrupt status/ID information. These signals are stored in the system memory in the central processing unit. 10. Three registers that control the operation of the interface unit are a general register, conversion period/number of blocks register, and an interrupt register. Referring to Figure 3b, the read data memory configuration is shown. The first word includes data register infoπnation, while 15. the second word includes data associated with the status register. The third and fourt words include information identical with the write configuration. This data group is stored in the system memory in the central processing unit. Referring now to Figures 4a-4d, 5a-5d, and 6a-6d, these together 20. form a detailed schematic diagram of the interface unit of the present invention. Figures 4a-4d illustrate the address and address modifier decod¬ ing circuitry (including elements 49-56 and 58), the status register (including element 60), the control register (including element 61), 25. the timer (including elements 63 and 65), the block counter (includ¬ ing elements 64 and 66) , the data latch (including element 84 and 85) the interrupt logic (including the various integrated circuits shown in Figs. 4a to 4d) and the data transceiver (including elements 94 and 95) . - - Figures 5a-5c illustrate the analog inputs (including elements 100) , the multiplexer (including element 74) , the sample-and-hold circuit (including element 87) , the analog-to-digital converter (including element 85) , the memory buffers (including element 5. 97, 98, 101 and 102), and the external trigger circuit (including connector P3 and the integrated circuits shown in Figs. 5a-5d) . Figure 5d illustrates the clock circuit (including elements 140 and 141). Figures 6a-6c illustrate analogue to digital control circuitry 10. the data memory unit and the memory control circuits. The significant circuit elements of the detailed schematic will now be described. First regarding the address and address modifier decoding circuit, this circuit comprises three eight-bit magnitude comparators 50, 52 and 54 (Figure 4a) . These devices monitor address 15. bits A03-A23 and the AS, LWORD and IAC signals. The address bits supply one input to a two-input comparator within comparators 50, 52 and 54, while the other input is switched to either +5 volts or ground through jumpers 51, 53 and 55. When the monitored level of address bits on the address bus matches 20. the corresponding levels set by the switches, the output (P=Q) goes LOW, and this level together with a LOW produced by a correctly decoded address modifier (AM) in PROM 49 is gated through circuit 56 to produce a HIGH on the data input of the board select bistable circuit 58. This HIGH level is also used to enable DSO and DS1 onto 25. the board, and these are used to clock bistable circuit 58 and therefore enable the board for system bus READ or WRITE operations. The address modifier PROM 49 may be mounted in a socket for appropriate user programming in order to provide the desired res- - 7 - ponse to address modifier codes. Regarding now the control/status registers, a preferred embodiment of the invention includes three control/status registers- Data is latched into the control registers by a 5. WRITE operation to the board, whereas data is output from the status registers by a READ operation. The first control/status register is an eight-bit circuit comprising an ectal buffer 60 and an octal latch 61. The second control/status register is a 16-bit circuit comprising two 10. eight-bit latch-readback registers 63 and 64. The conversion period of the board is determined by the latched outputs of register 63. These outputs are connected to the data inputs of an eight-bit counter 65. When enabled, counter 65 counts down from the preloaded value until at zero a signal is produced 15. which begins the A/D conversion process and reloads the counter 65 to its predetermined value. The block size of the memory is determined by the latched outputs of register 64. These outputs are compared to the eight most significant bits of one of the memory address counters 20. (A or B) by an eight-bit comparator 66. The third control/status register is a sixteen-bit circuit comprising two eight-bit latch/raadback registers 67 and 69, and it contains the interrupt information for the board. An interrupt status/ID byte is latched into register 67, and the 25. interrupt request level is latched into register 69. When the board is configured to interrupt, a LOW level is clocked through - 8 - circuit 71 to enable an interrupt request from circuit 70. During the interrupt acknowledge cycle the level of inter¬ rupt being serviced is indicated on address lines A01, A02 and A03. This address information is compared ^ to the generated interrupt 5. level'by comparator 72, and if the request and service levels match the interrupt status/ID byte stored in register 67, it is enabled onto bits D00-D007 of the data bus (connector Pi, Figure 4d). Regarding channel-selection, an eight-channel multiplexer 10. 74 selects the analog input signal to be passed from the P3 connector (Figure 5a) through the buffer amplifier 76 to the smaple-and-hold amplfier 87. -The channel address bits A0,A1 and A2 are provided by a counter 79 that is clocked by the A/D convert command. Thus as the board is converting, the multi- 15. plsx β r 74 and buffer amplifier 76 are tracking the next channel to be converted. A channel select comparator 82 is used to clear the counter 79 each time the selected number of channels have been accessed. With respect now to the sample-and-hold amplifier 87, it 20. tracks the analog signal on its input until a HIGH level on pin 11 puts it into HOLD mode. On receipt of this HIGH level the sample-and-hold circuit 87 holds the analog value steady to enable the analog-to-digital converter to carry out its con¬ version. 25. Regarding the analog-to-digital converter 85, it can be jumpered for a 0 to 10 volt, plus-or-minus 5 volt, or plus- or-minus 10 volt operation by properly arranging jumpers J8 and ' J9. The gain and offset of the A/D 85 are adjustable by - 9 - means of resistors 91-93. The twelve-bit output of the A/D 85 is stored in one of the two swinging buffer memories depending upon which data bus buffers are enabled. If data bus buffers 97 and 98 are enabled, the data is stored in memory B, whereas 5. if data bus buffers 101 and 102 are enabled, the data is stored in memory A. Regarding the data memory, it is arranged as two 16 x 12 bit swinging buffers, memory B comprising circuits 107-109 and memory A comprising circuits 104-106. Data is written to and read from 10. these memories using appropriate control sequences stored in PALS. . PAL A produce a control sequence that inputs data from the A/D converter ' 85 to the memory location addressed by address counters A or B«- 15. PAL B produce a control sequence that outputs data from the memory addressed by address counters A or B to the system data bus. OPERATION-OF THE PREFERRED EMBODIMENT In the inventive interface unit, the multiplexer, sample and hold apparatus, analog to digital converter, and buffer memory 20. unit can be typically implemented by components known in the related art. However, control of the components is performed by means of the control logic unit in response to signals from the central processing unit. The timing and control logic unit is provided with a software programmable timer based on clock 29a 25. that can permit the user to select the conversion period of the interface unit. In addition, the control logic unit permits the user to select between an internal or an external trigger, between normal and event trigger in an internal mode, between a continuous or tran- - 10 - sient data acquisition mode, and .between an interrupt or polling response mode. In the continuous mode of data acquisition signals from the moni¬ tored device are storedr ' -in separate portions of the data memory unit, and the portions of the data memory unit are alternatively applied to the 5- system data bus. In addition, the user can select the number of input channels monitored by the interface unit and the mode of operation when each channel is being monitored. An interrupt signal is generated and applied to the central processing unit when data is available in the 10. interface unit for transfer to the central processing unit. The user can also select between a disable or enable mode for the board. Thus, the mode of the interface unit is controllable, permitting flexibility in operation by the user. This control can be effected, in the present invention by loading the control register 15. with appropriate signals. Based upon these signals, the control logic unit can determine, for example, if a continuous or transient mode of operation is to be employed to monitor output signals. The control apparatus further includes apparatus for signalling the presence of an interrupt event identified by the interface unit. 20. It will be clear that the disclosed apparatus can change the mode of monitoring a device (under control of the central processing unit). This flexibility permits the monitoring of expected transient events by the use of the interface unit. The foregoing description is included to illustrate the operation 25. of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited by the following claims. From the foregoing description many variations will be apparent to one skilled in the art that would yet be encompassed by the spirit and scope of the invention.

Claims: What is Claimed is: 1. An interface unit coupling at least one analog signal and a system data bus comprising: a multiplexer unit for selecting said at least one analog signal; a sample and hold amplifier for storing a signal related to a portion of said selected analog signal; an analog to digital converter for converting said signal portion to digital signals; a data memory unit coupled to said system data bus for storing said digital signals; and data control means coupled to said multiplexer unit, said sample and hold amplifier, said analog to digital converter, and to said data memory unit, said data control means controlling operation of said interface unit components coupled thereto. 2. The interface unit of Claim 1 wherein said data control means comprises: a control register for storing predetermined groups of signals; and a control logic unit for processing said predetermined groups of signals and generating control signals to said multiplexer unit, to said sample and hold amplifier, to said analog to digital converter, and to said data memory unit for controlling the operation of said interface unit. 3. The interface unit of Claim 1 wherein said data control means further comprises a clock. 4. The interface unit of Claim 2 wherein said data control means further includes means for providing interrupt signals indicating the presence of digital signals to be applied to said system data bus. - 12 - 5. The method of interfacing at least one analog signal and a system data bus comprising the steps of: selecting said at least one analog signal; χ selecting a mode of operation for monitoring said at least one analog signal from signals on said system * data bus; storing data related to said at least one analog signal; and transferring said data to said system bus. 6. The method of interfacing of Claim 5 wherein said mode selecting step includes the step of controlling output signals from a local clock. 7. The method of interfacing of Claim 5 wherein said mode selecting step includes the step of selecting between a continuous monitoring mode and a transient data capture mode. 8. The method of interfacing of Claim 5 further including the step of generating an interrupt signal when said data is ready for said transferring step. 9. The method of interfacing of Claim 5 further comprising the step of providing signals for said signal selecting step and for said mode selecting step from a central processing unit. 10. Apparatus for providing an interface between at least one analog signal and a system data bus comprising: multiplexer means for selecting an analog signal; sample and hold means for providing a signal related to a preselected portion of said analog signal; analog to digital converter means for providing digital signals related to said preselected portion; storage means for storing said related digital signals; and control means responsive to signals from said system data bus for controlling said multiplexer means, said sample and hold means, said analog to digital converter means, and said storage means. - 13 " 11. Apparatus for providing an interface of Claim 10 further including interrupt means for pro%'iding a signal indicating the presence of digital signals to be transferred to said system data bus 12. Apparatus for providing an interface of Claim 10 wherein said control means includes a clock, and wherein timing signals from said clock are controlled by signals to said control means from said system data bus. 13. Apparatus for providing an interface of Claim 10 wherein signals from said system data bus to said control means control a data acquisition mode of said apparatus. 14. Apparatus for providing an interface of Claim 13 wherein said control means configures said apparatus for a continuous data acquisition mode or a transient data acquisition mode. 15. Apparatus for providing an interface of Claim 10 further including interrupt means for providing a signal when digital signals are available for transfer to said system data bus. 16. Apparatus for providing an interface of Claim 10 further including address means for identifying control signals to be applied to said control means from said system data bus. 17. Apparatus for providing an interface of Claim 10 further comprising a central processing means for controlling said apparatus. 18. Apparatus for providing an interface of Claim 17 wherein said central processing means provides signals to said control means for determining a mode of operation.

Inventors: HARDIE IAN, HARDIE, IAN
Applicants: BURR BROWN LTD, BURR-BROWN LIMITED
Application year: 1986
Main classification: G06F3
IPC codes: G06F3, H03M1