SEMICONDUCTOR MEMORY DEVICE ADAPTED TO CARRY OUT OPERATION TEST

Abstract: In order to facilitate a test of the operations of a semi­ conductor memory device, the semiconductor memory device includes a line selection checking unit (ALL-SELECTED STATE CHECK CIRCUIT) coupled to a cell array and column gates to form a logic gate circuit unit consisting of a plurality of transistors, the gates of the transistors being connected to word lines (X0, X1, X2) or bit lines (Y0, Y1, Y2). The line selection checking unit has a voltage or current detection portion (NODE OUTPUT) connected to a pad (PM, P1) for detecting an output voltage or current of the line selection checking unit.

Description: The present invention is related to a semiconductor memory device adapted to carry out a test of an operation of the semiconductor memory device. The device according to the present invention is applicable to, for example, an EPROM. In general, the test of a semiconductor memory device upon manufacture is carried out by an IC tester and a probe. Among the test modes used are a mode wherein all of the word lines or bit lines are selected, and a mode wherein a group of the word lines or bit lines is selected. These all-selection mode or group-selection mode tests are adopted to enhance the speed of a test of the semiconductor memory device. The tests according to the above modes are usually carried out according to an all-selection or group-selection operation by the programs stored in the IC tester. However, in prior proposals, in tests according to the all-selection or group-selection modes, usually the confirmation of whether or not the all-selection or group-selection signals are actually supplied to the device to be tested is not carried out, and accordingly, confirmation of whether or not an all-selection or a group-selection actually takes place is not carried out. In another prior proposal, the selection of all of the word or bit lines, or the selection of a group of word or bit lines is confirmed by information obtained from the memory cell array. In this confirmation, however, it is necessary to store special information for the test in the memory cell and to read the stored special information, and such processes are complicated and inconvenient. Thus, a satisfactory method or system has not been established for realizing a reliable test including a complete test of the all-selection or group-selection of lines of a semiconductor memory device. According to one aspect of the present invention there is provided a semiconductor memory device adapted to carry out an operation test of said semiconductor memory device comprising:- a cell matrix having a memory cell array, rows of word lines, and columns of bit lines; row and column decoders for decoding signals for carrying out a selection of all of said word or bit lines or a selection of a group of said word or bit lines; column gates connecting the bit lines to an output buffer and connected with their gates to selection signal lines output from said column decoder; a plurality of pads for providing input or output terminals of said semiconductor memory device; characterised by:- line selection checking means coupled to said word lines and said selection signal lines to form a logic gate circuit means comprising a plurality of transistors, the gates of said transistors being connected to said word lines or selection signal lines; said line selection checking means having a voltage or current detection portion connected to one of said pads for detecting an output voltage or current of said line selection checking means. According to another aspect of the present invention there is provided a semiconductor memory device adapted to carry out an operation test of said semiconductor memory device comprising:- a cell matrix having a memory cell array, rows of word lines, and columns of bit lines; a sense amplifier; row and column decoders for decoding signals for carrying out a selection of all of said word or bit lines or a selection of a group of said word or bit lines; a plurality of pads for providing input or output terminals of said semiconductor memory device, a number of said pads being connected to output terminals of said sense amplifier; characterised by:- transfer gates connected between said columns of bit lines and said sense amplifier; a line selection checking means coupled to said word lines or bit lines to form a logic gate circuit means comprising a plurality of transistors, the gates of said transistors being connected to said word lines or bit lines; said line selection checking means having a voltage or current detection portion for detecting the output voltage of said logic gate circuit means. The logic gate circuit means may consist entirely of a plurality of transistors. An embodiment of the present invention may provide an improved semiconductor memory device adapted to carry out a test of an operation of the semiconductor memory device in which a reliable test including a complete test of all-selection or group-selection of lines of a semiconductor memory device is carried out. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, Fig.1 shows a fundamental structure by which an operation consistent with the present invention may be realised; Fig.2 shows a semiconductor memory device according to an embodiment of the present invention; Fig. 3 shows a semiconductor memory device according to another embodiment of the present invention; and Fig. 4 shows a semiconductor memory device according to still another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a preferred embodiment of the present invention, the fundamental structure of a device by which an operation consistent with the present invention may be realized will be described with reference to Fig. 1. The device of Fig. 1 includes a NOR type memory cell array having word lines X(0), X(1), X(2), ..., bit lines Y(0), Y(1), Y(2), ..., column gates, an output buffer circuit, a NAND circuit consisting of transistors Q(1), Q(2), Q(3), ..., and a depletion type load transistor Q(LOAD) having a diode connection. The output node NODE(OUTPUT) is connected to a specially provided pad P(M). Alternatively, the output node NODE(OUTPUT) is connected through the switching circuit to an existing pad P(1) for delivering the information in the output node NODE(OUTPUT) through the existent pad P(1). In normal operation, the internal circuits are connected through the switching circuit to the pad P(1). In a test, a signal which cannot appear at the pad P(2) in a normal operation, such as a high voltage signal or the like, is applied to the pad P(2) so that the switching circuit switches the internal circuits including the memory cell array, the column gates, and the output buffer circuit to a high impedance state, and switches the information of the output node NODE(OUTPUT) to be delivered from the pad P(1). Instead of the above-described monitoring of the potential of the output node NODE(OUTPUT), it is possible to confirm the all-selected state by monitoring the current passing through the transistors Q(1), Q(2), Q(3), .... It should be noted that this current flows only in the all-selected state. In consequence, in the simultaneous plural word line selection mode or in the simultaneous entire word line selection, if at least one bit or word line is not selected, either the potential of the output node NODE(OUTPUT) of the NAND circuit becomes HIGH, or a current does not pass through the NAND circuit. Thus, the simultaneous plural word line selection or the simultaneous entire word line selection can be easily confirmed by monitoring the potential of the output node of the NAND circuit, or the presence or absence of a current passing through the NAND circuit. A semiconductor memory device according to an embodiment of the present invention is shown in Fig. 2. The device of Fig. 2 includes a cell matrix 11, a row decoder 12, a column decoder 13, column gates 14, word lines 15, bit lines 16, an output buffer 17, a bus line 18, address buffers 27, 28, 29, 210, and 211, high voltage detection circuits 212, 213, 214, 215, and 216, an inverter 217, column address inputting pads 31 and 32, row address inputting pads 33 and 34, an address inputting pad 35, an output pad 38, and an all-selected state check circuit 5. The all-selected state check circuit 5 includes N channel MOS field effect transistors 511, 512, 513, 514 ..., N channel MOS field effect transistors 521, 522, 523, ..., and an N channel MOS field effect transistor 531. The drain of the transistor 531 is connected to the bus line 18 connected to the column gates 14. The source of the transistor 531 is connected to the series connection of the transistors 521, 522, 523, ..., and the gates of the transistors 521, 522, 523, ... are connected to the selection signal lines, that is, the column decoder output lines, of the column gates 14. The source of the transistor 531 is also connected to the series connection of the transistors 511, 512, 513, 514, .... The gates of the transistors 511, 512, 513, 514, ... are connected to the word lines. The current i(C) passing through the transistors 521, 522, 523, ... and the current i(W) passing through the transistors 511, 512, 513, 514, ... is detected by monitoring the output pad 38. Alternatively, it is possible to monitor the potential of the output node 54 of the all-selected state check circuit 5. In the usual operation state, a high voltage is not applied to the pads 31, 32, 33, 34, and 35, and accordingly, the potential of the outputs a (mH), a(lH), a(jH), a(iH), and a(xH) remain HIGH. As usual, address signals are supplied to the column decoder 13 or the row decoder 12 through address buffers, so that data can be written in and read from the cell matrix 11. The operation of the testing device of Fig. 2 will now be described below. First, the operation for checking the all-selected state of the word lines is described, with the use of a probe and an IC tester. (i) It is assumed that the potential of the output a(mH) of the high voltage detection circuit 212 is HIGH. When a high voltage is applied to the pad 31, the potential of the output a(mH) of the high voltage detection circuit 212 becomes LOW, and the potentials of both outputs of the NAND gates 221 and 222 become HIGH. Hence, the output of the column decoder 13 becomes all-LOW. Accordingly, the column gates 14 become all-OFF, and the bit lines become all-unselected. This condition can be confirmed by the absence of current through the bus line 18. Here, it is assumed that a memory cell allows a current to pass therethrough when this memory cell is selected. (ii) A high voltage is also supplied to the pad 34, and accordingly, the potential of the output a(iH) of the high voltage detection circuit 215 becomes LOW. (Here, it is assumed that the potential of the output a(iH) is usually HIGH.) The potentials of both the outputs a(i) and a(i) become LOW, and thus the potentials of the outputs of the row decoder 12 become all HIGH. Accordingly, the word lines 15 are made to the all-selected state. In this case, the bit lines 16 are all in the unselected state, and accordingly a current does not flow through the bus line. (iii) When a high voltage is applied to the pad 35, the potential of the output a(xH) of the high voltage detection circuit 216 becomes LOW. (Here, it is assumed that the potential of the output a(xH) is usually HIGH.) The transistor 531 as a transfer gate becomes ON, and thus the bus line 18 is connected to the all-selected state check circuit 5. When the operation of the all-selection of the word lines is being carried out as usual, all of the transistors 511, 512, 513, 514, ... having the word lines 15 as gate inputs become ON, and thus the current i(W) flows. Therefore, by detecting the current passing through the bus line 18, the actual occurrence of an all-selection state of the work lines is confirmed. Next, the operation for checking the all-selected state of the bit lines is described. (i) Where the column gates 14 are selected, a confirmation of the selection of the bit lines is carried out. Thus, by confirming the selection of all of the column gates 14, it is possible to confirm the selection of all of the bit lines. (ii) A high voltage is supplied to the pad 33, and accordingly, the potential of the output a(jH) of the high voltage detection circuit 14 becomes LOW. (Here, it is assumed that the potential of the output a(jH) is usually HIGH.) The potentials of the outputs a(j) and a(j) become HIGH, and accordingly, all of the word lines 15 are made to the unselected state. This state can be confirmed by detecting an absence of current through each of the bit lines 16. (iii) A high voltage is also supplied to the pad 32, and accordingly the potential of the output a(lH) becomes LOW. (Here, it is assumed that the potential of the output a(lH) is usually HIGH.) Therefore, the potentials of the output a(l) and the output a(l) become LOW. Accordingly, all of the bit lines 16 are made to the selected state, that is, all of the column gates 14 are made to the selected state. In this case, all of the word lines 15 are in the unselected state, and thus a current does not flow through the bus line 18. (iv) Further, a high voltage is supplied to the pad 35, and thus the potential of the output a(xH) of the high voltage detection circuit 216 becomes LOW. Accordingly, the transistor 531 turns ON, and the bus line 18 is connected to the all-selected state check circuit 5. When the operation of the device is as usual and all of the bit lines 16, that is all of the column gates 14, are selected, all of the transistors 521, 522, 523, ... having the input signals for the column gates 14 as the gate input signals thereof turn ON, so that the current i(C) passes through the transistors 521, 522, 523, .... Thus, by detecting the current i(C) passing through the bus line 18, it is possible to confirm the selection of all of the bit lines 16. A semiconductor memory device according to another embodiment of the present invention is shown in Fig. 3. In the device of Fig. 3, the confirmation of a simultaneous selection of a half of all of the word lines or a half of all of the bit lines is carried out. In Fig. 3, a group-selected state check circuit(A) for one half of all of the word lines and one half of all of the bit lines, and a group-selected state check circuit(B) for the other half of all of the word lines and the other half of all of the bit lines are provided. The gate of the transistor 631, which constitutes a load for the transistors 611, 612, ..., and 621, 622, ..., is connected through the inverter 218 to the high voltage detection circuit 216A for the pad 36. The gate of the transistor 731, which constitutes a load for the transistors 711, 712, ..., and 721, 722, ..., is connected through the inverter 219 to the high voltage detection circuit 216B for the pad 37. Under the condition that a high voltage is applied to the pad 36, the confirmation of the selection of one half of all of the bit lines or one half of all of the word lines is carried out by detecting the potential of the node 64. Conversely, under the condition that a high voltage is applied to the pad 37, the confirmation of the selection of the other half of all of the bit lines or the other half of all of the word lines is carried out by detecting the potential of the node 74. A semiconductor memory device according to still another embodiment of the present invention is shown in Fig. 4. Figure 4 shows case wherein the confirmation of the selection of all of the word lines is carried out. The device of Fig. 4 includes a NOR type memory cell array having word lines X(0), X(1), X(2), ..., bit lines Y(0), Y(1), Y(2), ..., transfer gates T(B0), T(B1), T(B2), ..., a NAND circuit consisting of transistors Q(1), Q(2), Q(3), ..., and a depletion type load transistor Q(L) having a diode connection, a sense amplifier, a switching transistor T(G), and nodes P(0), P(1), P(2) .... The device of Fig. 4 carries out the detection of the potential of the output node NODE(OUTPUT). The switching transistor is normally in an OFF state, and the transfer gates T(B0), T(B1), T(B2), ... are normally in an ON state. The operation of the device of Fig. 4 will now be described. First, all of the bit lines Y(0), Y(1), Y(2), ... are made to the unselected state, and all of the transfer gates T(B0), T(B1), T(B2), ... are made to the OFF state. Then, the switching transistor T(G) is made ON, and the output node NODE(OUTPUT) is connected to the sense amplifier. Therefore, for example, the information of the potential of the output node NODE(OUTPUT) appears at the output S(0) of the sense amplifier. Accordingly, it is possible to confirm the selection of all of the word lines by detecting the information appearing at the existing pad P(0) connected to the output S(0). Similarly, it is possible to carry out the confirmation of the selection of all of the bit lines, by providing a NAND circuit for the bit line side, that is the column gate side. In this case, a column gate input signal constitutes a gate input signal. In the device of Fig. 4, the generation of control signals for the transistors T(B0), T(B1), T(B2), ..., and T(G), the selection of all of the word lines and non-selection of all of the bit lines, and the selection of all of the bit lines and non-selection of all of the word lines can be controlled by the application of a high voltage to the existing pads for which additional modes are provided. In this case, high voltage detection circuits are provided for the existing pads concerned.

Claims: A semiconductor memory device adapted to carry out an operation test of said semiconductor memory device comprising:- a cell matrix (11) having a memory cell array, rows of word lines (15), and columns of bit lines (16); row and column decoders (12, 13) for decoding signals for carrying out a selection of all of said word or bit lines or a selection of a group of said word or bit lines; column gates (14) connecting the bit lines to an output buffer (17) and connected with their gates to selection signal lines output from said column decoder (13); a plurality of pads (31, ..., 35, 38) for providing input or output terminals of said semiconductor memory device; characterised by:- line selection checking means (5; 6, 7) coupled to said word lines and said selection signal lines to form a logic gate circuit means comprising a plurality of transistors (511, ..., 514; 521 ... 523), the gates of said transistors being connected to said word lines or selection signal lines; said line selection checking means (5) having a voltage or current detection portion (NODE (OUTPUT)) connected to one of said pads (P(M)) for detecting an output voltage or current of said line selection checking means. A device according to claim 1, wherein said line selection checking means is a line selection checking circuit (5) for checking the selection of all of said word or bit lines. A device according to claim 2, wherein said line selection checking means (5) comprises a first series sequence of transistors (511, 512, ...) for receiving gate signals from all of said word lines, a second series sequence of transistors (521, 522, ...) for receiving gate signals from all of said selection signal lines, and a switching transistor (531), said first and second series sequences of transistors being connected in parallel. A device according to claim 3, wherein one electrode of said switching transistor is connected to one of said pads (38) through a bus line (18) and said output buffer (17). A device according to claim 3 or 4, wherein the gate of said switching transistor (531) is connected to one of said pads (35) through an inverter (217) and a high-voltage detection circuit (216). A device according to claim 1, wherein said line selection checking means comprises a plurality of line selection checking circuits (6, 7), and each of said line selection checking circuits is a line selection circuit for checking the selection of a group of said word or bit lines. A device according to claim 6, wherein each of said line selection checking circuits (6, 7) comprises a first series sequence of transistors (611, 612, ...; 711, 712, ...) for receiving gate signals from a group of said word lines, a second series sequence of transistors (621, 622, ...; 721, 722, ...) for receiving gate signals from a group of said selection signal lines, and a switching transistor (631, 731), said first and second series sequences of transistors being connected in parallel. A device according to claim 7 or 8, wherein one electrode of said switching transistor (631, 731) is connected to one of said pads (38) through a bus line (18) and said output buffer (17). A device according to claim 7, wherein the gate of said switching transistor (631, 731) is connected to one of said pads (36, 37) through an inverter (218, 219) and a high-voltage detection circuit (216A, 216B). A semiconductor memory device adapted to carry out an operation test of said semiconductor memory device comprising:- a cell matrix having a memory cell array, rows of word lines (X(O), ...), and columns of bit lines (Y(O), ...); a sense amplifier (SA); row and column decoders for decoding signals for carrying out a selection of all of said word or bit lines or a selection of a group of said word or bit lines; a plurality of pads (P(O), ...) for providing input or output terminals of said semiconductor memory device, a number of said pads being connected to output terminals (S(O), ...) of said sense amplifier; characterised by:- transfer gates (T(B0), ...) connected between said columns of bit lines (Y(O), ...) and said sense amplifier (SA); a line selection checking means coupled to said word lines or said bit lines to form a logic gate circuit means comprising a plurality of transistors (Q(1), ...), the gates of said transistors being connected to said word lines (X(O), ...) or bit lines (Y(O) ...); said line selection checking means having a voltage or current detection portion (Q(LOAD); NODE (OUTPUT)) for detecting the output voltage of said logic gate circuit means. A device according to claim 10, wherein a switching transistor (T(G)) is connected between the output node (NODE (OUTPUT)) of said logic gate circuit means and said sense amplifier.

Inventors: TAKEGUCHI. TETSUJI
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G11C8
IPC codes: G11C29, G11C16, G11C8, G11C17