SEMICONDUCTOR DEVICE INCLUDING PROTECTING MOS TRANSISTOR

Abstract: A zero-cross thyristor comprises an n-type sub­ strate region (l05) surrounded by a p-type region (l06), a p-type base region (l03) formed in the n-type substrate region and surrounding an n-type inner region (l05′) of the n-type substrate region, and a p-type floating region (ll0) formed in the n-type inner region. An n-channel MOS transistor whose gate is connected to the floating region (ll0) is formed in the p-type base region (l03). A first p⁺-type diffusion region (lll) whose depth is less than that of the p-type base region is continuously formed in the p-type base region and the n-type inner region and a second p⁺-type diffusion region (ll2) whose depth is also less than that of the p-type floating region (ll0). The distance between the first and second diffusion regions is set to a predetermined value for preventing the breakdown of the gate insulating layer of the MOS transistor.

Description: The present invention relates to a semiconductor device, such as a thyristor or a triac, including a protecting MOS transistor. A zero-cross photo thyristor or a zero-cross photo triac, which is turned on only at a zero-cross time point at which an AC voltage applied between a cathode and an anode crosses a zero line or at a time point near the zero-cross time point, has been proposed. The zero-cross photo thyristor is not turned on upon incidence of light when the voltage applied between the anode and cathode is high, but is turned on upon incidence of light when the voltage is low and is near the zero-cross time point. In such a thyristor, noise generated during switching is significantly reduced. An example of a thyristor whose operation is controlled by an incorporated MOS transis­ tor is disclosed in Japanese Patent Disclosure (Kokai) No. 58-l05572. A semiconductor device in which a gate portion of the above MOS transistor is protected from a high voltage so as to allow the above thyristor or the triac to have a high withstand voltage is disclosed in Japanese Patent Disclosure No. 60-74678. Fig. l is a sectional view of a planar type thyristor having such a structure for protecting a gate portion. The thyristor shown in Fig. l has a pnpn four-­ layered structure including n-type cathode region l, n-type region 2, p-type base regions 3 and 4 (which are formed integrally or connected electrically) sur­ rounding cathode region l and n-type region 2, n-type region 5 surrounding base regions 3 and 4, and p-type anode region 6 surrounding n-type region 5. N-type region 2 is short-circuited to base region 3 through wiring 7. Cathode region l, n-type region 2, gate insulating layer 8 provided on cathode region l, n-type region 2 and base region 3 between cathode region l and n-type region 2, and gate electrode 9 provided on gate insulating layer 8 constitute a MOS transistor. Cathode region l and n-type region 2 are electrically connected and disconnected according to an ON-OFF operation of the MOS transistor. P-type floating region l0 is formed in the inner region of n-type region 5 surrounded by base regions 3 and 4, and gate electrode 9 is connected to floating region l0. An operation of the semiconductor device in Fig. l is as follows. Assume that a sine wave voltage is ap­ plied between anode electrode A and cathode electrode K, the anode is positive and the cathode is negative, and a voltage amplitude is high. In this state, the voltage between the anode and cathode is applied to a p-n junc­ tion between n-type region 5 and base region 3. When the voltage is applied in the manner described above and light becomes incident on a surface of the device in Fig. l, a photo current is generated in base region 3. The thyristor is turned on by the photos current if not having a structure to be turned on near the zero-cross time point of the AC voltage. However, in the thyristor shown in Fig. l, a channel is formed in a surface region of base region 3 between cathode region l and n-type region 2 according to the gate voltage. More specifical­ ly, a current path including wiring 7, n-type region 2, the above channel, cathode region l, and cathode elec­ trode K is formed from base region 3, and the photo cur­ rent generated in base region 3 flows to cathode K. Therefore, the thyristor is prevented from being turned on when the AC voltage is high. The thyristor is turned on when the voltage between the anode and cathode is low enough to be near the zero-­ cross time point. More specifically, a potential of anode electrode A is supplied to gate electrode 9 through floating region l0, and a potential of cathode electrode K is supplied to the channel. Accordingly, when the voltage between the anode and cathode is lower than threshold voltage Vth of the MOS transistor, the channel which electrically connects cathode regions l and n-type region 2 is not formed. When the channel is not formed as described above, the thyristor is turned on by the photo current generated in base region 3. Once the thyristor is turned on, the MOS transistor is kept in an off state since the voltage between the anode and cathode does not rise over the forward voltage drop of the thyristor. The semiconductor device (including a thyristor or a triac) shown in Fig. l has the following problems. More specifically, when a thyristor, a triac, or the like has a high withstand voltage, a high voltage is applied between the anode and cathode. Therefore, the MOS tran­ sistor must be prevented from breakdown by the high volt­ age. For this purpose, a structure which limits the voltage applied to the gate electrode below a predeter­ mined value has been proposed. More specifically, a p-type floating region l0 surrounded by base regions 3 and 4 is provided such that a depletion layer which is generated between p-type base regions 3 and 4 and n-type region 5 gradually extends as the voltage between the anode and cathode becomes high and at last reaches float­ ing region l0, thereby limiting the voltage applied to gate electrode 9 at a predetermined value. The voltage between the anode and cathode when the depletion layer reaches floating region l0 is called a punch-through starting voltage. In order to control the above punch-through start­ ing voltage precisely, the following three factors are present. That is, (l) impurity concentration of n-type region 5, (2) distances ℓ between base regions 3 and 4 and floating region l0, and (3) surface impurity concen­ trations of base regions 3 and 4 and floating region l0. Since factor (l) is normally determined by the other conditions, the controls of factors (2) and (3) are im­ portant. Factors (2) and (3) are controlled by the dif­ fusion length in the lateral direction of base regions 3 and 4 and floating region l0. As for a thyristor or a triac with a high withstand voltage, a diffusion depth of base regions 3 and 4 must be about 40 µm. The diffusion depth, i.e., the diffusion length in the longitudinal direction and inpurity can be controlled with relatively high precision. However, it is very difficult to control precisely the diffusion length in the lateral direction, so that the diffusion length in the lateral direction varies largely according to a manufacturing process. More specifically, in the structure of Fig. l, distances ℓ between base regions 3 and 4 and floating region l0 vary largely; so does the punch-through starting voltage. Therefore, control of distances ℓ is important. It is an object of the present invention to provide a semiconductor device incorporating a protecting MOS transistor to be turned on near the zero-cross voltage of a supply AC voltage, and having a structure capable of controlling a voltage applied to the gate electrode of the MOS transistor at a predetermined value with high precision and ease. A semiconductor device including a protecting MOS transistor according to the present invention comprises a first semiconductor region of a first conductivity type connected to a first voltage supply source, a second semiconductor region of a second conductivity type which has a main surface and whose surface except for the main surface contacts the first semiconductor region; a third semiconductor region of the first conductivity type formed in the second semiconductor region and connected to a second voltage supply source, a fourth semicon­ ductor region of the second conductivity type formed in the third semiconductor region and connected to a third voltage supply source; a fifth semiconductor region of the second conductivity type formed in the third semicon­ ductor region and short-circuited to the third semicon­ ductor region, a gate insulating layer continuously pro­ vided on one surface portion of the fourth semiconductor region, one surface portion of the fifth semiconductor region and the surface portion of the third semiconduc­ tor region between the fourth and fifth semiconductor regions, a gate control electrode provided on the gate insulating layer, a sixth semiconductor region of the first conductivity type formed in the inner region of the second semiconductor region surrounded by the third semi­ conductor region and connected to the gate control elec­ trode, a first diffusion region of the first conductivity type having a depth less than that of the third semicon­ ductor region, the first diffusion region being continu­ ously formed in one portion of the inner region and in one portion of the third semiconductor region and con­ tacting at least one portion of the surface junction between the third semiconductor region and the inner region of the second semiconductor region, and a second diffusion region of the first conductivity type having a depth less than that of the sixth semiconductor region and facing the first diffusion region, the second diffu­ sion region being continuously formed in one portion of the inner region and in one portion of the sixth semicon­ ductor region and contacting at least one portion of the surface junction between the sixth semiconductor region and the inner region of tne second semiconductor region. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. l is a sectional view of a conventional zero-­ cross thyristor; Fig. 2 is a sectional view of a zero-cross thyris­ tor according to one embodiment of the present invention taken along the line II - II of Fig. 3; Fig. 3 is a plan view of Fig. 2; and Fig. 4 is a part of a plan view of the zero-cross thyristor according to another embodiment of the present invention. In a thyristor shown in Figs. 2 and 3, p-type first semiconductor region l06 is connected to first voltage (anode voltage) supply source A through anode electrode ll3 provided on a surface opposite to a major surface. N-type second semiconductor region l05 has a main surface and the surface of region l05 except for the main surface contacts the first region l06. P-type third semiconductor region l03 (base region) is formed in sec­ ond region l05 so as to surround inner region l05′ of second region l05. N-type fourth semiconductor region l0l (cathode region) and n-type fifth semiconductor region l02 are provided in third region l03. Fifth region l02 is short-circuited to base region l03 by short circuit wiring l07. Base region l03 is connected to second voltage supply source G (base voltage supply source). The base voltage is not supplied when the thyristor is turned on upon incidence of light. Gate insulating layer l08 is formed on portions of cathode region l0l and fifth region l02 and the upper portion of base region l03 between cathode region l0l and fifth region l02, and gate control electrode l09 is formed on gate insulating layer l08. P-type sixth region ll0 (floating region) is formed in inner region l05′ of n-type second region l05. Floating region ll0 is con­ nected to gate control electrode l09. Over the entire area of surface junction ll4 between base region l03 and inner region l05′, p-type first diffusion region lll is continuously formed in portions of base and inner regions l03 and l05′. Over the entire area of surface junction ll5 between floating and inner regions ll0 and l05′, p-type second diffusion region ll2 is continuously formed in portions of floating and inner regions ll0 and l05′. A distance between diffu­ sion regions lll and ll2 is adjusted to be predetermined distance ℓ. An impurity concentration of diffusion regions lll and ll2 is higher than that of base and floating regions l03 and ll0, and depth of diffusion regions lll and ll2 is less than that of base and float­ ing regions l03 and ll0. In this embodiment, a surface impurity concentration of base and floating regions l03 and ll0 is set to be l × l0¹⁷ cm⁻³, a depth thereof is set to be 40 µm, an impurity concentration of diffusion regions lll and ll2 is set to be 5 × l0²⁰ cm⁻³, a depth thereof is set to be 3 µm, and an impurity concentration of second region l05 is set to be l × l0¹⁴ cm⁻³. An operation of the thyristor shown in Figs. 2 and 3 will now be described. Assume that anode voltage supply source A is positive, cathode voltage supply source K is negative, and the voltage between A and K is high. An anode potential is supplied to gate control electrode l09 through floating region ll0, and a cathode voltage is supplied to the channel region between cathode region l0l and fifth region l02 through a p-n junction (forward p-n junction) between cathode region l0l and base region l03. Therefore, the MOS transistor (including cathode region l0l and fifth region l02, gate insulating layer l08, and gate control electrode l09) is turned on. Accordingly, a current path is formed from base region l03 to cathode voltage supply source K through wiring l07, fifth region l02, the channel region, and cathode region l0l. There­ fore, the thyristor is not turned on because a photo current generated in base region l03 upon incidence of light on the device surface flows to cathode voltage supply source K. However, when a voltage between the anode and cathode is small and a voltage applied between gate control electrode l09 and the channel region is lower than a threshold voltage of the MOS transistor, the MOS transistor is turned off, so that the thyristor is turned on by the photo current. In the embodiment shown in Figs. 2 and 3, in order to set the voltage between the anode and cathode, which turns on the MOS transistor, to be 5 to 6 V, insulating layer (SiO₂ layer) l08 is so formed as to have a thick­ ness of about l,500 Å. A breakdown voltage of the in­ sulating layer with this thickness is normally l20 to l30 V. When the thyristor is prevented from being turned on, the anode-cathode voltage is applied direct­ ly to the insulating layer l08. At this time, when the anode-cathode voltage is increased, the depletion layer extends from base region l03 and first diffusion region lll to floating region ll0 and second diffusion region ll2, so that the punch-through occurs. Thereafter, even when the anode-cathode voltage is increased, the voltage applied to gate control electrode l09 is not appreciably increased. It was found that in order to set the punch-­ through starting voltage below l20 V, a distance between first and second diffusion regions lll and ll2 must be set to be about 30 µm. In the prior art shown in Fig. l, in order to obtain a thyristor with a withstand voltage of 600 V, the depths of base regions 3 and 4 and floating region l0 were set to be 40 µm, surface impurity concentrations thereof were set to be l × l0¹⁷ cm⁻³, and a distance between the base region and the floating region was set to be l00 µm on the mask. However, the punch-through starting voltage was between 60 to 90 V, and variations therein were very large. In the embodiment shown in Figs. 2 and 3, a depth of base region l03 and floating region ll0 is the same as that in Fig. l, a depth of diffusion regions lll and ll2 is set to be 3.2 µm, a concentration thereof is set to be 5 × l0¹⁷ cm⁻³, distance ℓ therebetween is set to be 25 µm on the mask. As a result, the punch-through starting voltage was in a range of 70 ± 5 V, thereby extremely reducing the variations therein. Because of diffusion regions lll and ll2, the punch-through starting voltage could be easily and precisely controlled without changing the withstand voltage and the characteristics of the thyristor. Fig. 4 is a part of a plan view of another embodi­ ment of the present invention. In Fig. 2, first diffu­ sion region lll is provided along the entire surface junction between inner region l05′ and base region l03, and second diffusion region ll2 is provided along the entire surface junction between inner region l05′ and floating region ll0. However, first and second diffusion regions lll and ll2 may be provided along only the por­ tions of both of the above mentioned surface junctions. This is because the punch through starting voltage is determined at a point where distance ℓ is shortest. Although the description has been made with refer­ ence to only a thyristor, it is obvious that the present invention can also be applied to a triac.

Claims: 1. A semiconductor device including a protecting MOS transistor comprising: a first semiconductor region (l06) of a first conductivity type connected to a first voltage supply source (A); a second semiconductor region (l05) of a second conductivity type which has a main surface and whose surface except for said main surface contacts said first semiconductor region; a third semiconductor region (l03) of the first conductivity type formed in said second semiconductor region and connected to a second voltage supply source (G); a fourth semiconductor region (l0l) of the second conductivity type formed in said third semiconductor region and connected to a third voltage supply source (K); a fifth semiconductor region (l02) of the second conductivity type formed in said third semiconductor region and short-circuited to said third semiconductor region; a gate insulating layer (l08) continuously provided on one surface portion of said fourth semiconductor region (l0l), one surface portion of said fifth semiconductor region (l02) and the surface portion of the third semiconductor region (l03) between said fourth and fifth semiconductor regions; a gate control electrode (l09) provided on said gate insulating layer; a sixth semiconductor region (ll0) of the first conductivity type formed in the inner region (l05′) surrounded by said third semiconductor region and connected to said gate control electrode; a first diffusion region (lll) of the first conductivity type having a depth less than that of said third semiconductor region, said first diffusion region being continuously formed in one portion of said inner region (l05′) and in one portion of said third semicon­ ductor region (l03) and contacting at least one portion of the surface junction between said third semiconductor region (l03) and said inner region (l05′) of said second semiconductor region; and a second diffusion region (ll2) of the first conductivity type having a depth less than that of said sixth semiconductor region (ll0) and facing said first diffusion region, said second diffusion region being continuously formed in one portion of said inner region (l05′) and in one portion of said sixth semiconductor region (ll0) and contacting at least one portion of the surface junction between said sixth semiconductor region and said inner region of said second semiconductor region. 2. A semiconductor device according to claim l, characterized in that the impurity concentrations of said first and second diffusion regions (lll, ll2) are higher than those of said third and sixth semiconductor regions (l03, ll0). 3. A semiconductor device according to claim l, characterized in that said first diffusion region (lll) contacts all the surface junction between said third semiconductor region and said inner region of said second semiconductor region and is continuously formed in one portion of said inner region and in one portion of said third semiconductor region; and said second diffusion region (ll2) contacts all the surface junction between said sixth semiconductor region and said inner region of said second semiconductor region and is continuously formed in one portion of said inner region and in one portion of said sixth semicon­ ductor region.

Inventors: JITSUKATA, KOUJI C/O PAT. DIV. TOSHIBA K.K., YAKUSHIJI, SHIGENORI C/O PAT. DIV. TOSHIBA K.K.
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L29
IPC codes: H01L27, H01L31, H01L29