JUNCTION SHORTENING-TYPE SEMICONDUCTOR READ-ONLY MEMORY

Abstract: In a junction-shortening type PROM, between a pair of memory cells (MC), a highly doped region (12) of the same conductivity type as the base is provided. This region (12) is a base contact region leading out the paired bases commonly out to the surface terminal connected to a word line (W₀ W₁,...). This region (12) reaches the substrate (SUB), the collector, so as to reject influence between the paired cells by pre­ venting the minority carriers in each of the paired bases from diffusing into each other base. The base contact region (12) may be isolated from the emitter regions (26) by a narrow groove filled with an insulation material deeper than the emitter but shallower than the substrate (SUB). A cell block composed of the paired cells and the base contact region (12) is isolated at its circumferences by a narrow groove (22) filled with a dielectric insulating material. The narrow isolation grooves and the elimination of the conventional buried base layer reduce stray capacity and increase the current amplification factor of the transistors. Both of them allow the related circuit to require less current load, which means increasing switching speed or less power consumption, and also reduction of occupation area for cells and the peripheral circuit, resulting in in­ creased density of integration.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an improvement of a semiconductor read-only memory (referred to hereinafter as PROM) whose diode is written-in by shortening its junction. More particularly, the present invention relates to a structure of its memory cell achieving increased density of integration and increased speed of the operation. PRIOR ART DOCUMENTS The US-A-4,287,569 discloses a semiconductor device having a plurality of memory cells located at a cross position of a plurality of bit lines and a plurality of word lines, the memory cell comprising a series circuit of an information storing element such as a diode or a fuse and a PNP type transistor. An N type epitaxial layer is used as a word line and the P type semiconductor substrate is used as a collector output line. To improve the integration of a semiconductor memory device the JP-A-59-43566 discloses forming a buried layer of an isolation region, thereby substantially reducing the width of the buried layer to enhance the concentration of a current at the wiring time. An isolating region is formed in a structure that a dielectric material is buried in a deep groove formed on an Si substrate. Reactive ion etching is used, the groove is substantially vertically cut to substantially reduce the width of an N⁺ type buried layer. The inside of the region becomes an element forming region, and two bipolar transistors are formed. Each transistor is formed of an emitter, a base and a collector in this order from the surface in a vertical shape in such a manner that the collector contact is made common. Description of the Related Art The principle of a typical PROM according to the above prior art of junction shorting type is schematically illustrated in FIGs. 1. The PROM of junction shorting type includes word lines W₀, W₁,..., bit lines B₀, B₁,..., and memory cells, each of which is connected to a cross point of one of the word lines and one of the bit lines. Each memory cell MC includes a series connection of a transistor Q and a diode D which is polarized so as to block a current flowing through the transistor. The cathode of the diode is connected to a bit line, and the base of the transistor is connected to a word line. The structure of the memory cell is schematically illustrated by the cross sectional view in FIG. 1(b). The n⁺ region K and the p⁺ region E therebeneath form the cathode and the anode of the diode D respectively. And the same p⁺ region E, the n region B and the substrate SUB form the emitter, the base and the collector of the pnp transistor Q respectively. For writing-in the cell, the pn junction of the diode is shorted by applying a voltage higher than the break down voltage of the reversely connected diode D and a current high enough to short the junction of the diode. The shorted cell MC′ is indicated by a mark M in FIG. l(b). When a word line having a shorted diode connected thereto is selected, namelY addressed, by applying a low level L on the base of the transistor Q, the transistor becomes conductive to pull the connected bit line down to the low level, L. However, when the diode is not written-in, the diode is non-conductive, so the connected bit line is not pulled down keeping the high level H which is given by selecting the bit line connected to this cell, even if the transistor Q becomes conductive. Thus, an addressed bit line, being applied with H, can be readed-out the stored data "l" or "0" of the cell connected thereto, by detecting whether a current flows into the bit line or not. Since the first PROMs of 256 and 5l2 bit are developed in l970, the memory capacity has been enhanced by the pace of four times per three years and now 64K bit integration is on production. And further increase of the integration capacity is still expected. Reviewing the history of the developments, at the early stage of the junction shorting type PROM, the gold diffused TTL technique was employed. Thenafter, the more precise lithography technique for the greater density integration, the washed emitter technique, and the mask self-alignment technique have been employed. In addition to these techniques, a technique for suppressing the parasitic thyristor effect caused by the increased density of the integration has been developed. These are reported by the inventor et al. in "An Advanced SVG Technology for 64K Junction-Shorting PROM's", IEEE Transactions on Electron Devices, Vol.ED-30, No.l2, Dec, l983. The problems of this thyristor effect shall be further described in some detail. When one of the memory cells is already written-in and an adjacent memory cell thereto fabricated on a common epitaxial layer is not written-in yet, there is produced a parasitic pnpn element, namely a thyristor, between these two cells, as shown by the dotted lines in FIG. l(c). If this thyristor turns on, the selected bit line B₁ so being to be of H level is clamped to the unselected bit line B₀ having L level. At this state, any other memory cell on the bit line B₁ can not be written-in, because sufficient voltage to write-in the other cell is not available on the bit line B₁ any more. As widely known, a thyristor is composed of two transistors of npn and pnp, and the breakover voltage V Bo of the thyristor is decided by the following formula, where V CB0 denotes the collector-base break down voltage of the parasitic npn transistor and a n , a p denote the current amplification factors of the npn transistor and pnp transistor respectively, and n is a constant: V B0 = V CB0 (l-a n - a p ) l/n and the thyristor latches up at: a n + a p ≅ l Consequently, in order to prevent the latching up the thyristor,V B0 must be large, in other words, the current amplification factors a n and a p should be small. For this purpose, the p⁺ layer, namely the base, of the parasitic npn transistor is made thick as shown in FIG. l(d), resulting in reduced a n . Further more, this thick region attendantly raises the break down voltage of the transistor Q, at the same time. As another measure, the cells adjacent to each other may be located in staggered position, so as to reduce the facing peripheral length of the emitters to each other resulting in lowered current amplification factor of the parasitic transistor. These techniques have been contributing to increase the density of integration, namely to produce PROM of 256K to 8K bit. The size of the memory cell has shrunk from l820 micro m² to l260 micro m² (or micron ²). However, as long as the gold diffused TTL process is employed, the following problems still remained unsolved: (a) Because of segrigation problem of the gold, as well known, the epitaxial layer is required to be thick (7 micron m) and consequently, the deeply diffused p⁺ thick base layer (2 micron) causes its lateral diffusion expanding wider, resulting in wider surface occupation area. Therefore, increasing the density of integration is limited. (b) Control of gold-doping is difficult, because the larger the wafer size becomes, the larger the uncontrolable heat capacity becomes. So the diameter of the wafer can not be increased for better production efficiency. (c) Gold particles in the diffused layer are easy to cause shorting emitter and collector junctions. Therefore, the base width of transistors can not be reduced, namely increase of the current amplification factor of the transistors is limited (h FE :25 to l00). This means,there are limitations of reducing power consumption in the circuit as well as increasing the operation speed. (d) The logic circuit must be of saturated type, so the switching speed is limited to increase. In order to solve these problems, as widely known, the V-shaped isolation groove, or so-called SVG (a Shallow V-shaped Groove), which provides perfect separation of the elements by a relatively shallow groove, was invented, as shown by V₁ in FIG. l(f). This V-shaped groove reaches the upper side of the buried n⁺ layer BL, namely a buried base lead, from the surface of the epitaxial layer, thus perfectly isolates the epitaxial layer of each memory cell. Some conduction may be existing through the buried n+ layer BL, however the minority carriers in the epitaxial regions can not diffuse into the adjacent cell, because this n⁺ region is highly doped to cause recombination of these carriers. V₂ indicates another isolation groove, which reaches the substrate SUB, thus completely isolating each cell block. Introduction of this SVG technique allows to disuse the gold diffusion having many problems, thus the following advantages are achieved: (a) The parasitic thyristor effect between adjacent cells are completely removed. (b) The thin epitaxial layer (3 µm) as well as thin p⁺ diffused base layer (0.7 µm) can be employed in the npn transistors of the peripheral circuits. Thus, the density of the integration can be increased. (c) A wafer diameter can be increased for increasing production efficiency. (d) The base width of the npn transistor of the peripheral circuit can be thin, so that the current amplification factor of the transistor can be made large (h FE : 70 to 250), resulting in allowing the higher speed operation as well as the lower power consumption in the peripheral circuits. (e) The Schottky diode-clamped TTL technique is employed in the peripheral circuits to increase the operation speed. As described above, owing to the invention of the V-shaped groove, a PROM of 256 to 64K bit with the Schottky diode clamped TTL technique has been materialized. The area of the memory cell is reduced from 864 square micron to 252 square micron . The current status of the art are also reported by the inventor et al. in "A 40ns 64K bit Junction-Shorting PROM", IEEE Journal of Solid Sate Circuits, Vol sc-l9, No. 2, April l984. However, problems are still remaining as hereinafter described. SVG isolation is formed by widely known anisotropic etching using a peculiar characteristics of (l00) crystal of silicon. As widely known, the relation between the width W on the mask of the lithography and the depth D of the groove is shown by the formula: D = (l/2) W tan54° ≅ 0.7 W Therefore, when the epitaxial layer is 3 µm thick and the upward diffusion of the n⁺ buried layer is l micron thick, namely difference 2 µm is required for the depth so 3 µm for the width of the SVG are automatically determined. Thus no more reduction of the isolation width is possible. Further more, as widely known, in the V-shaped isolation, eaves (approximately l micron on each side) of silicon dioxide, so-called a bird beak, expand laterally along the surface. Therefore, margin area between the adjacent patterns is required, so a greater density integration is prevented. The problems about the vertical (depth) direction are as follows. The isolation effect of the SVG becomes sure when the groove reaches the n⁺ buried layer. So, the epitaxial layer is required to be thin, so that the groove width at the surface can be narrow. Therefore, the upward diffusion of the n⁺ buried layer must be sufficiently controlled, but it is difficult. On the other hand, in order to keep reliability of writing-in the cell, the depth of the p+ layer, namely the emitter of the pnp transistor Q, is generally required to be approximately l.2 µm thick. And, in order to secure more than 20V of the break down voltage between the base (n epitaxial layer) and the emitter during writing-in the cell, the width of the depletion is generally required approximately l µm Therefore, if the upward diffusion of the buried layer is l µm, the epitaxial layer is required to be at least 3 µm thick. On the other hand, also in the peripheral circuit, such as X and Y address inverter X-ADD; Y-ADD, decoder/driver D/D, multiplexer MPX, and chip-enable CE, further increase of the operation speed, and increase of the integration density, and/or decrease of the power consumption must be achieved. For solving these problems, stray capacity in the circuits, particularly the stray capacity of the word line, must be reduced and performance of the transistors in the circuits must be graded up in order to ease the current load of the circuits. Explanation regarding the relations between these factors and the effects shall be given related to the later description of the preferred embodiments in detail. SUMMARY OF THE INVENTION It is an object of the invention to provide a junction shorting type PROM having an increased density of integration as well as an increased speed of operation. This object is solved by a junction-shortening type semi-conductor programmable read only memory device as defined in the appended claims. In a structure of the memory cell of the junction shorting type PROM having a diode on a transistor both of which are connected in series and the cell is fabricated by the stack of diffused layers on a substrate, the present invention provides a memory cell which has no buried layer as a word line and is paired with an adjacent cell to form a cell block and the cell block is further isolated by an insulation region surrounding the cell block from an adjacent cell block. The structure in detail is as follows. Between the emitters as well as bases of the transistors of the paired cell but isolated from the emitter, a highly doped region made of an opposite conductivity to the substrate is provided reaching the substrate, so as to separate each base, namely to prevent the minority carriers in each base region from diffusing laterally into each other base region. This highly doped region, also as a base contact region, leads the paired bases commonly out to a corresponding word line fabricated upon the surface of the cells. The base contact region may be separated from each emitter region of the cell by a pair of isolation grooves filled with a dielectric material as deep as not reaching the substrate. The cell block is isolated from an adjacent cell block by a U-shaped isolation groove filled with a dielectric material reaching the substrate. The occupation area reduced by the U-shaped isolation groove reduces stray capacity of the wirings. Elimination of the buried base conductor also reduces stray capacity of the word lines etc., and further reduces the thickness of the epitaxial layer. Reduction of the thickness of the epitaxial layer increases current amplification factor of the transistors and also contributes to decrease the surface area of the periferal circuit. All these factors finally contribute to increase the density of integration, to increase the speed of operation and to decrease the power consumption, not only at the cell area but also at the peripheral circuits. The above-mentioned features and advantages of the present invention, together with other objects and advantages, which will become apparent, will be more fully described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS FIGs. l schematically illustrate the prior art PROM. n FIGs. l, (a) is a principal circuit diagram of a junction shorting type PROM, (b) is a cross sectional view of the memory cells, (c) schematically illustrates the parasitic thyristor between adjacent cells, (d) shows a cross sectional view of a cell to explain the thickness relation, (e) is a birds-eye view of the cells, and (f) schematically illustrates the SVG. FIGs. 2 schematically illustrate the memory cells of the PROM according to the present invention. In FIG. 2, (a) is a birds-eye view of the memory cell, (b) shows a plan view of six cell blocks, and (c) is the circuit diagram of the two pairs of the memory cells. FIG. 3 through 5 illustrate the sequential steps for fabricating the PROM according to the present invention. FIG. 6 schematically illustrates the upward diffusion from the substrate to help the downward diffusiion of the highly doped region reach the substrate. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIGs. 2, the principal structure and the circuit diagram of the invention are shown. The n⁺ region 32 and p⁺ region 26 respectively form the cathode and the anode of the diode D of a cell. The same p⁺ region 26, the n region l2, the highly doped n⁺ region l8, and the substrate SUB respectively forms the emitter, the base, and the collector of the pnp transistor Q of the cell. Two of these cells adjacent to each other compose a pair, namely a cell block. The circumference of this cell block is isolated from its adjacent cell blocks by the U-shaped isolation regions 24. Each base region of paired transistors is separated by a highly doped diffusion region l8 which prevents the diffusion of the minority carriers (holes) into each other base region. This highly doped region l8 also acts as a base contact region which leads both of the base regions to the common base contact 34 provided on the top of the highly doped region l8. Word lines W o ,..W₃ are respectively connected to each corresponding common base contact 34. Bit lines B₀,..B₃ are respectively connected to each corresponding cathode region 32 of the diode D. Referring to FIG. 3 through 5, the fabrication steps of the PROM according to the invention are successively illustrated. As shown in FIG. 3(a), according to a widely known technique used for a general bipolar IC (Integrated Circuit) fabrication process, the n⁺ buried layer l0 is firstly formed on an area of the substrate SUB where the peripheral circuits are to be fabricated, namely excepting the area where the cells are to be fabricated. Next, an n epitaxial layer l2 is grown all over the substrate having the buried layer l0 as shown in FIG. 3(a) by a widely known method used for a general bipolar IC fabrication. Next, a silicon nitride film l4 of approximately l000Å (1Å=0.1nm) thick, for example, is formed upon the epitaxial layer l2 by a widely known method used for a general bipolar IC fabrication. The silicon nitride film is patterned as shown in the figure, by a widely known method used for a general bipolar IC fabrication. Next, the epitaxial layer below the opened window of the nitride film l4 is oxidized by the widely known local oxidization method used for a general bipolar IC fabrication, to form a pair of the isolation regions l6, each top of which is swelling out beyond the nitride film l4 caused by the oxidization. This isolation region l6 is for preventing the lateral expansion of the p⁺ diffusion layer 32 which is to be fabricated later as an emitter of the pnp transistor Q in the cell as well as the lateral expansion of the base contact 34 which is also to be fabricated later. The region l6 can be fabricated by not only the above-described local oxidization but also by the above-described SVG method. The depth of this isolating region l6 is deeper than the emitter region but shallower than the top of the substrate, so that the highly doped region l8 is isolated from the emitters but can contact the base regions. Next, a dopant, such as phosphorous or arsenic, is diffused into a particular part of the epitaxial layer l2 located between the paired isolation regions l6 to form the highly doped region l8, so high as l0¹⁹ cm⁻³ of concentration measured at the surface, for example. The highly doped region l8 must be formed deep enough to reach the substrate SUB, so that the diffusion of the minority carriers (holes) in each paired cell from/to the other cell is completely prevented. The formation of this highly doped region l8 may be carried out not only by a widely known simple diffusion from the surface (downward diffusion) or the ion implantation but also by its combination with an additionally employed upward diffusion 39 (shown in FIG. 6) of an n⁺ buried layer previously prepared on the particular portion where the highly doped region l8 is to reach on the substrate. In the case where the upward diffusion of the buried layer is employed, an attention must be, of cause, paid for the mask alignment of the upward diffusion 39, however, the alignment is easy because the width of the isolation region l6 is 2 µm and the accuracy of the alignment is below 2 µm without difficulty, so the downward diffusion and the upward diffusion will never fully deviate from each other. 20 denotes a highly doped n⁺ region which acts as a collector contact connecting the buried layer l0 for a npn transistor in the peripheral circuit to the collector terminal 38. FIG. 3(c) illustrates the a birds-eye view of FIG. 3(b). The isolation regions l6 and the highly doped n⁺ region l8, 20 are extended laterally along the surface of the epitaxial layer, so that the conduction between the elements are perfectly prevented. Next, in order to isolate each cell block including the pair of the memory cells, an U-shaped groove 22 is formed as narrow as l.4 µm between each cell block by a widely known technique, such as dry etching, as shown in FIG. 4(a) and its birds-eye view FIG. 4(b). On forming the U-shaped groove 22, the delicate control of its depth is generally difficult in contrast with the case to form V-shaped groove where the depth D can be controlled by its width W at the surface by the above-described relation: D = 0.7W. However, in the embodiment of the present invention, the delicate depth control of the U-shaped groove 22 is not required, because the depth can be rather relaxed as long as the U-shaped groove isolates the cell blocks. Therefore, according to the present invention, it is easy to control the fabrication conditions. Into the bottom portion of the U-shaped groove 22, a p⁺ dopant, such as boron, is diffused by an ion implantation method, for example, to cut an undesirable electrical channel formed along the outer surface of the groove, as widely known. And, the side walls in the U-shaped groove is oxidized by the local oxidization method, for example, to form an isolation film of approximately 3000Å. The U-shaped grooves are extended along the surface, crosswisely isolating entire circumference of each cell block. Next, polycrystalline silicon is grown in the U-shaped groove 22, by a widely known method, such as CVD (Chemical Vapor Deposition), to form the isolation wall 24. The excessive polycrystalline silicon grown beyond the surface is removed by polishing to form a flat surface. The silicon nitride film l4 is removed by a widely known method, such as chemical etching. The polished surfaces of the polycrystalline silicon and other portions are oxidized by a widely known method, such as a thermal oxidization. Next, on the specific portion of the n epitaxial layer l2, a p⁺ dopant, such as boron, is diffused as much as l0¹⁴ cm⁻² of concentration, for example, to form an approximately l.2 micron thick p⁺ layer 26, 28 and an approximately 0.3 to 0.5 micron thick p⁺ layer 30, as shown in FIG. 5(a), by a widely known method used for a general bipolar IC fabrication process. These p⁺ layers form the emitter regions of the pnp transistor Q and the base region of the npn transistors of the peripheral circuits. Owing to the existance of the isolation layer l6, self-alignment technique can be employed for diffusing these regions. The self-alignment contributes to achieve greater density of integration without production difficulty. Next, on each specific portion of the p⁺ layer 26, l8, 30, an n⁺ dopant is diffused to form n⁺ layers 32, 34, and 36 respectively, by a widely known method used for a general bipolar IC fabricaion. The layer 32 is the cathode of the diode D. The layer 34 is the base contact to make a good contact with an external aluminum wirings, which is to be fabricated later. The layer 36 is the emitter of npn transistor of the peripheral circuit. Upon the surface having these layers, aluminum wirings for the connections are patterned by a well known technique used for a general bipolar IC fabrication, as shown in FIG. 2(a). Each base contact 34 is connected to the corresponding word line W₀, W₁,..., and each cathode 32 is connected to each corresponding bit line B₀, B₁,..., as mentioned earlier. Now, a pair of memory cell is finally completed. The effects of the embodiment of the present invention shall be hereinafter described. The U-shaped isolation groove reduces the width of the isolation groove to l.4 µm, eliminating the unnecessary width caused by the prior art, such as the bird beak etc., resulting in reduction of the occupation area by the memory cell. The cell area is reduced from 252 µm² to ll7 µm² i.e. approximately 46 percent. This reduced cell size contributes to reduce stray capacity and inductance of the leads in the cell area. The elimination of the buried layer n⁺ for leading out the bases to the outside contributes to the improvement of the PROM in three ways. Firstly, it reduces the stray capacity of the word lines, which was made of a buried layer fully facing the substrate in the prior art. Secondly, it reduces the thickness of the epitaxial layer. Thirdly, the reduced thickness of the epitaxial layer contributes to increase the current amplification factor of the transistors both in the cell and in the peripheral circuits, as well as reduces the surface occupation area of the transistors. These are explained further in detail as follows. Because of the elimination of the buried layer, the upward diffusion of the buried layer is of course nothing, saving l µm in thickness. Accordingly, the thickness of the epitaxial layer l2 can be reduced from 3 µm to 2 µm, which is the sum of l.2 µm of p⁺ layer for the diode and 0.7 or 0.8 µm for the base, without sacrificing the thickness of the base and emitter which is delicately important to keep reliability of the cell for the writing-in process. The thin, only 2 µm thick, epitaxial layer l2 reduces also the thickness of the epitaxial layer l2 from 2 µm to l µm at the peripheral region where the upward diffusion of the buried layer l0 is l micron thick. Namely, the l µm thick epitaxial layer, the 0.3 to 0.5 µm thick base region 30, and 0.2 to 0.3 µm thick emitter 36 can make the width of the lateral diffusion of the emitter narrower than that of the thick epitaxial layer, consequently contributing to the reduction of the occupied surface area of the transistors in the peripheral circuits. In addition to this fact, at the memory cell the elimination of the buried layer increases the facing area of the substrate SUB, namely the collector, to the emitter 32, as well as decreases the length of the path between the emitter and the collector, more than the prior art structure in which the facing area and the shortest path between the emitter and the collector is obstructed by the existance of the buried layer, which is denoted by BL in FIG. l(b). This increased facing area as well as decresed path length increases current amplification factor of the pnp transistor Q of the cell. The h FE of the transistor is raised from l.5 to 30, for example. These increased current amplification factor reduces the required base current of the transistor Q, namely the addressing current on the word iine supplied from the D/D circuit. For a switching operation, the stray capacity must be charged during the transient period from the driver circuit. Therefore, the reduced stray capacity reduces the required charging current supplied from the driver circuit to keep same switching speed. This means that, if the same current is supplied, the charging time is reduced, namely fast switching is achieved. Thus the reduced addressing current and the reduced base current reduce the current load of the peripheral circuit, such as D/D circuit. In other words, this reduced current load contributes to the faster switching operation, and results in a simplified structure of the peripheral circuit as well as in a smaller occupation area of the circuit, namely increased density of integration, and also smaller power consumption and the speed, thus the address time is reduced from 20--25 ns to l0--l5 ns. This simplified small circuit structure reduces the stray capacity again. Needless to say, the Schottky diode-clamped transistor technique is inherited in the peripheral circuit of the present invention for the high speed operation. The description was made referring to the case where the substrate is of p⁺ conduction type, however, n⁺ conduction type is of course applicable to the substrate according to the circuit requirement. The many features and advantages of the invention are apparent from the detailed specification and thus, it is intended by the appended claims to cover all such features and advantages of the system.

Claims: Junction-shortening type semiconductor programmable read only memory device comprising a semiconductor substrate (SUB) of a first conductive type, a plurality of first regions (12) of an opposite conductive type to said first conductive type of said substrate (SUB) formed on said substrate (SUB), a plurality of word lines (W₀, W₁,...) as well as a plurality of bit lines (B₀, B₁,...), and a memory cell (MC) including a transistor and a diode at each cross point of a word line (W₀, W₁,...) and a bit line (B₀, B₁,...), characterized in that the memory cells are arranged in pairs forming cell blocks and in that the structure of each memory cell block comprises: first dielectric isolation means (24) surrounding one of said first regions (12) and reaching said substrate (SUB); a second region (18) doped with a dopant of said opposite conductive type into the central area of said first region (12) so as to divide said first region (12) into two divided first regions (12), whereby said second region (18) connects said divided first regions (12) to the word line (W₁, W₂,....); a third region (26) of said first conductive type formed on each of said divided first regions (12), but apart from said second region (18); a fourth region (32) of said opposite conductive type formed on each of said third regions (26); one of said bit lines (B₀, B₁,....) connected to said fourth region (32); and one of said word lines (W₀, W₁,...) connected to said second region (18); wherein said substrate (SUB), said divided first region (12) and said third region (26) form the transistor (Q) and said third region (26) and said fourth region (32) form the diode (D) of each of said memory cells. A memory device according to claim 1, characterized in that said second region (18) is isolated at its two sides from each of said third regions (26) by second dielectric isolation means (16) which does not reach said substrate (SUB). A memory device according to claim 1 or 2, characterized in that each of said divided first regions (12) is surrounded at three vertical sides by said first dielectric isolation means (24) and is surrounded at its remaining one vertical side facing to the other of the divided first regions by said second dielectric isolation means (16) and said second region (18). A memory device according to claim 3, characterized in that said second region (18) is surrounded at its two vertical sides facing to each other by said second dielectric isolation means (16) and is surrounded at its remaining two vertical sides by said first dielectric isolation means (24). A memory device according to any one of claims 1 to 4, characterized in that said first dielectric isolation means (24) is made of a U-shaped groove (22) filled with a dielectric insulating material. A memory device according to any one of claims 1 to 4, characterized in that said first dielectric isolation means (24) is made of a V-shaped groove filled with a dielectric insulating material. A memory device according to any one of claims 2 to 6, characterized in that said second dielectric isolation means (16) is made by field oxidization. A memory device according to any one of claims 2 to 6, characterized in that said second dielectric isolation means (16) is made of a V-shaped groove filled with a dielectric insulating material. A memory device according to any one of claims 1 to 8, characterized in that said divided first region (12) being a base of said cell transistor (Q), said third region (26) being an emitter of said cell transistor (Q) as well as an anode of said cell diode (D), and said fourth region (32) being a cathode of said cell diode (D). Process for fabricating a junction-shortening type semi-conductor programmable read only memory device according to any one of claims 1 to 9, in which after forming a buried layer (10) for forming peripheral circuits on a substrate (SUB) an epitaxial layer (12) is grown all over said substrate (SUB), next a silicon nitride film (14) is formed on said epitaxial layer (12) and is patterned, next open windows of said silicon nitride film (14) are oxidized or SVG-fabricated to form second isolation means (16), next between said second isolation means a dopant is diffused or ion implantated to form a second region (18), next grooves (22) are formed and filled with an isolation film, next a dopant is diffused on specific portions of said epitaxial layer (12) to form a third region (26), next on said second and third regions (18, 26) a dopant is diffused to form contacts and a fourth region (32), respectively, and next wirings are connected to the latter region.

Inventors: FUKUSHIMA, TOSHITAKA
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H01L27
IPC codes: H01L27, H01L21, G11C17