A METHOD FOR DECODING DATA TRANSMITTED ALONG A DATA CHANNEL, AND AN APPARATUS FOR EXECUTING THE METHOD

Abstract: Method of decoding data making it possible on the one hand to correct certain errors, e.g. in synchronization and transmission, and, on the other, to require only one com­ pact and universal processing unit, where a device for im­ plementing the method consists of a radio receiver (21), a microprocessor (22) for its control and a universal decoder (11) consisting on the one hand of a demodulation (13) and clock regeneration (12) component, the imput of which is connected to the multiplex output of the radio receiver (21) and, on the other, of a broadcast data processing micropro­ cessor (14), the output of which is connected to said micro­ processor (22) for controlling the radio receiver.

Description: The invention relates to a method for decoding data transmitted along a data channel, said data being arranged in groups, each group containing a fixed number of N blocks, each block (J) containing an information word MJ of n1 bits, which by means of information of a linear error protection code has been extended to an error protected block of (n1+n2) bits, and wherein to each protected block in a group a predetermined off-set word WJ has been added by bitwise EXCLUSIVE ORING, which off-set word indicates the position of the block in question within its groups, said method comprising the steps of: a) in an initialization phase receiving a sequence of (n1+n2) data bits from said channel and therefrom generating a first syndrome by means of incremental operations (42), each incremental operation taking into account exactly one most recently received data bit; b) comparing said first syndrome to respective standard syndromes, the latter corresponding to all possible off-set words (44); c) in case of non-correspondence omitting the least recently received data bit from said (n1+n2) data bits and updating said first syndrome while accounting for a still more recently received data bit (40) until either in step b) or in step c) a correspondence occurs with a standard syndrome corresponding with a standard syndrome corresponding to one of said predetermined off-set words; d) in a user phase following step c) generating for each next block of (n1+n2) bits received over said data channel an associated syndrome (52) and comparing it with its position indicating standard syndrome(s) (54), each next block having a presumed next following position in the sequence of groups; e) in case of correspondence outputting the block's information word to a user (48); in case of non-correspondence executing an error protection operation (56) on the error-protected block of n1+n2 bits without its associated off-set word. The invention also relates to a device for executing such a method. Such a method and device are known from the UK patent application No. 2094041. In this publication, this method is applied to a data receiver which receives error protected information words of N=49 bits, comprising n1=36 information bits and n2=13 error correction bits. For these error protected information words, syndromes, that is, characteristic numbers, are determined by means of incremental operations. In case of an error free information word, the syndrome will have a standard value (zero in the published method); hence a non-standard syndrome indicates that the error protected information word contains an error. A similar encoding scheme and a decoder for this scheme is known from a publication by the European Broadcasting Union (EBU), Tech. 3244-F appendix 2 part 2-2 thereof, describing an implementation of a decoder. In this publication, a group contains for blocks (N=4) and each information word contains 16 bits (n1=16) and n2=10 redundant bits for error correction. The redundancy used allows for correcting single bit errors and burst errors up to a maximum length of five bits. It is known by itself to use a particular amount of redundancy to implement various different error protection strategies. For example, one such strategy is to omit the full error correcting capability of a particular code, but to enhance the error detection capability. For example, a code with a bitwise minimum Hamming distance of four may be used either for single bit error correction, double bit error detection, or alternatively, for treble bit error detection. Even in a single application, certain code blocks may be treated differently from other code blocks. The advantage of a linear error protection code is that the sum of two code blocks again constitutes a code block. The code may b either systematic on the bit level or non-systematic on the bit level. In the former case a correct block has the information word contained within n1 specific bit positions. In the latter case, the information word must be retrieved from a larger number of bit positions (up to a maximum number of (n1+n2) bit positions). This method be particularly useful in systems for the radio transmission of data, especially in the FM band. Such systems, like the one known by the name of RDS (Radio Data System) make it possible to insert data, unbeknown to the listener, serving especially to tune the radio receiver and identify the mono or stereophonic sound radio broadcast program. With receivers fitted with a display screen, the data also makes it possible to show the name and type of program to which the receiver is tuned, to identify the decoder, a radio text, etcetera, and other information relating more particularly to motorists with a car radio, like road messages. However, the method may also be used in a one-way point-to-point intercommunication, in other types of modulation, and in completely different application environments. To apply such a method to data transmitted as serial bits along a channel, it is necessary to know the location of information word boundaries in the data. To determine such boundaries, the known method teaches an initialization phase in which syndromes are determined at all possible successive locations, and it is assumed that a boundary has occurred as soon as standard syndrome value has been found. At this moment, the known method enters a user phase in which the information words are inspected for errors and if necessary correct by means of the syndromes. It is a disadvantage of the known method that it does not provide for detecting a complete loss of synchronization, as may occur for example when using a broadcast radio data channel if the signal strength suddenly varies. In particular, it does not provide for such detecting in a flexible manner reducing the number of false alarms about synchronization loss. Moreover, the known method also does not provide for the reduction of false synchronization in the initialization phase, which may occur when the syndrome fortuitously assumes a standard value. It is an object of the method and device according to the invention to provide for handling of synchronization errors in a way which is more flexible and robust than the known method and device. The method according to the invention realizes this object, because it is characterized in that in case of correspondence in the user phase (e) a first controlling signal is output (68), whereas of non-correspondence a second strategy controlling signal is output (7), and in that step a) is restarted if one time-sequence of first and second strategy controlling signals from a specified class of time-sequence occurs (66). In this way, the problem is handled that occurs when after synchronization has been established in certain situations, the amount of error in the user phase increases in such a degree, that synchronization must be considered as lost. In that case, the system returns to the synchronization phase. The errors correctable and/or detectable could occur in particularly in a vehicle, e.g. a car fitted with a car radio, when it passes beneath a bridge. This protection is very effective in that at various predetermined positions in the bit stream (spaced at n1+n2 bits apart) the actual syndrome generated is compared to the appropriate standard syndrome(s). If the comparison yields equality, synchronization is correct and also transmission is considered error-free. If the comparison does not yield equality, an error protection operation is effected. The result of such operation may be detection of one, two or more errors (considered as uncorrectable), correction of one or more bit errors, or a combination thereof. The type of error is stored in an error register means. The system continuously keeps book of those error types and makes a decision after processing of each block as to the expected quality of the transmission. In certain applications the strategy of this decision is adjustable. One particular strategy would be: each block with an error (either correctable or not) increases an error score. If a certain limit is attained, the system is considered out of synchronism. If a correct block is received, the error score is reset to zero. Other strategies are explained hereinafter. The specifications issued by the European Broadcasting Union concerning the RDS system stipulate that the information word of the first block of the group shall remain the same. The invention takes advantage of this special provision in order to detect and correct any slip by ±1 bit which could occur inside a group. This is why, in one embodiment of the invention, with the first block identical along the data channel, the user phase is also intended to comprise a phase of seeking and correcting the bit slip error. After the errorless detection of this first block the possible slip detected is therefore retained while shifting the synchronization instant by 0, +1 or -1 bit cells. In this way the second and further blocks will have a much lower probability for an uncorrectable error. The invention is advantageous in that no large processing means is required. Especially, only a limited memory capacity (less than 4K bytes) is required. Thereby the invention also relates to an apparatus for executing the above-mentioned method. Such apparatus may comprise a universal decoder made up of a demodulation and clock regeneration component. The input thereof is connected to a multiplex output of a radio receiver. Furthermore, the apparatus comprises a microprocessor for processing the broadcast data. The output thereof is connected to a second microprocessor for controlling the radio receiver. The use of the output data from the universal decoder may be effected in various ways, depending on the way the data is applied in an environment, on the content of the data, and of the quality and/or safety levels intended. Further advantageous aspects are recited in the dependent Claims. The following description, given with reference to the attached drawings, showing non-limitative examples, will show of what the invention consists and how it can be produced. Figure 1 shows the basic structure of the data channel. Figure 2 shows how the syndrome of data channel block is calculated. Figure 3 is a flow chart of a decoding process of the invention. Figure 4 illustrates the detection and correction of a slip error. Figure 5 is a diagram of a device for implementing the decoding method of the invention. Figure 6 is a more functional diagram of certain parts of such a device. Figure 1 shows the structure of the data channel. The largest component is a group comprising, for example, N=4 blocks. Each blok J (J=1 to 4) consists of an information word MJ of n1 bits and a control word CJ of n2 bits. The recommendations of the European Broadcasting Union concerning the RDS system specify a 16 bit information word and a 10 bit control word, so that a block has n1+n2=26 bits. Fiugure 2 shows the generation of a syndrome SJ for a block of (n1+n2) bits. The generation is effected by multiplication by a parity check matrix of dimensions (n1+n2)xn2 bits. The resulting syndrome is bit string of n2 bits. Syndrome calculation for a non-systematic code is effected in a corresponding manner. Figure 3 is a flow chart of a decoding process of the invention. This process is made possible in that on the transmitter side to the control word CJ of each block a so-called off-set word is added (bitwise EXCLUSIVE ORED). The content of each off-set word is one-to-one correlated to the position of the control word (and consequently, of the block in question), within the group. For the organization of Figure 1, four different off-set words would suffice. However, for organizational reasons, the cited RDS system has seven different off-set words. Certain of these off-set words, in addition to indicating the block's position within the group, could therefore serve other purposes, such as indicating the type of the block, or the type of the group in question. However, this latter information is not used on the level of the present invention. The flow chart of Figure 3 starts at input 60. Here, the data bits are received, but there is not a priori information of their relative positions within either block or group of blocks. The upper part of the Figure, above the broken line 62 gives the initialization or synchronization phase. That is, as long as the system is in this synchronization process, the decoded data is not yet considered as reliable. Block 42 represents the initialization phase. Herein the syndrome SJ of the block constituted by the first (n1+n2) bits, with the off-set word added thereto, is calculated. In order to limit time and memory capacity for the calculations, the syndrome SJ is calculated incrementally in that for each data bit received a preliminary syndrome bit string is updated by an increment bit string si, that is the contribution of the most recent data bit to the ultimate syndrome bit string SJ. This goes on, until a main counter, that counts the data bits, has reached a position (n1+n2). At that point it would in principle be possible that synchronization had occurred. Thus, the system goes to block 44, which has two exits. Block 44 represents a comparison between the syndrome SJ actually generated and the standard syndromes SW each of which would have been generated on the basis of a particular off-set word WJ alone. Note that the off-set word constitutes a quasi-error word. These quasi-error word syndromes or standard syndromes are present in a comparison register means RC. Thus, in the setup of Figure 1, at least four such standard syndromes would be present. If the comparisons are all negative there are two possibilities: either the block window is mispositioned, or there is an error present in the data received. In case of a negative output (0), the system goes to block 40, which tries to reposition the block window. For each next-following data bit b(n1+n2+k) the syndrome is further updated. This is effected by wiping out the contribution of data bit b(k) and by adding the contribution of the data bit b(n1+n2+k) to the syndrome bit string, which operation has been shown symbolically. If k reaches the value (n1+n2), the window should have been positioned correctly; then the negative comparison result surely has been caused by an error. The system of Figure 3, however, goes on with repositioning the block window, which in principle could go on indefinitely. Higher-level measures, such as a time-out provision (signalling an unusable connection) fall outside the scope of the present invention. Due to the linear character of the code (the sum of two code blocks again represents a code block) bit errors outside the block window do not contribute to the syndrome. The linear character of the code also allows for the incremental generation of the syndrome SJ in block 42. Thus, in case of a reasonably low number of errors, at some time or another, the comparison in block 44 will give a positive result (1) and the system proceeds to block 46. Herein it is presumed that the previous window is correctly positioned; also, the identity of the previous standard syndrome is known. Therefore, the standard syndrome(s) for the next expected off-set word(s) is (are) chosen from the comparison register means. Note that this expectation may be unique (in the case of exactly N different off-set words). In other cases it could be ambiguous. For example, in the case of N=4 and seven off-set words, the number of possiblities for the expected off-set word syndrome could vary between one and four. Furthermore, in block 46 the next syndrome S(J+1) is calculated in exactly the same way as in block 42. After calculation, in block 50, the new syndrome S(J+1) is compared to the (one or more) selected syndromes from the comparison register means. In the same way as in block 44, the result can be positive or negative. If the result is negative, the system assumes that synchronization is absent and it returns to block 42. If the result is positive, the system assumes that synchronization is correct, and it may go to the data processing part proper or user phase under broken line 62. The degree of safety can be increased further in that the process of blocks 46 and 50 can be repeated one or more times, while a secondary counter keeps track of the number of these repetitions. If the number reaches a predetermined level, the line 62 may be transgressed. In certain applications only a single correct comparison in block 44 would be sufficient, its output directly leading to block 48. On the lower side of broken line 62 there is assumed correctness of the two most recently received blocks (or of an even higher number in case the secondary counter cited hereabove had been used). The system can now transmit the data word(s) of one (the most recent) or more of these correct blocks to a user. This operation is illustrated by block 48 "BUS": the actual function of the bus subsystem is illustrated in Figure 5. Next, the operations of blocks 46/50 are repeated in blocks 52/54. In block 54 the same comparison is made as in block 50, each time for the appropriate standard syndrome(s). If the comparison indicates no error, the system proceeds via block 68 to block 48, wherein the information word is made available to the user. The error strategy block 68 is considered later. In principle, the loop of blocks 48, 52, 54, 68 may be executed continually. In contradistinction to block 50, however, now also the error protection feature is taken into account. Thus, if there is a discrepancy (0 in block 54), the system goes to block 56. In block 56, an error protection operation on the error-protected block of (n1+n2) bits without its associated off-set word is effected while making use of the syndrome proper. The off-set word is ignored by subtracting it (which is the same as bit-wise EXCLUSIVE-ORING). In the particular application of the RDS-system, there are various possible signalizations a. single bit error signalled plus corrected data word; b. compound error signalled, possibly in combination with an indication of the error burst length; c. signalization of an incorrectable error (two or more bit errors not in a single burst or a burst error of length greater than five). In block 58 this signalization is analyzed, with respect to correctibility. If the answer is "correctible" (1), the system, via error strategy block 70 goes to block 48, wherein the information word is made available to the user. Also the loop of blocks 48, 54, 52, 58, 70 may, in principle, be executed continually. If in block 58, the error proves incorrectable, the system goes to block 66. In block 66, the actual state of the error protective strategy is evaluated. This actual state is represented by a numerical value. If this value is low (1), the system goes to block 64. Herein, a first message is made available to a user. This first message may signal: information word irretrievable. Next, the system goes to error strategy block 72. Thereupon, the system goes to block 52. Thus, it is presumed that on the one hand, no synchronization error had occurred. On the other hand, the information word could not be made available to the user and block 48 is bypassed. If however, in block 66 the numerical value proves to be high (0), it is assumed that synchronization had been lost. The system goes to block 74. Herein, a second message is made available to a user. This second message may signal: synchronization lost. Thereafter, the synchronization process is restarted. The error strategy blocks 68, 70, 72 are considered hereinafter. A modification of the set-up of Figure 3 is to connect test block 66 directly at the negative output of block 54, block 66's two outputs leading to block 74 and 56, respectively. The negative output of block 58 would then directly lead to block 64. Various other interconnection schemes would yield good results. The error strategy blocks 68, 70, 72 relate to the updating of the numerical value in the error register. A first possibility is to increment the numerical value by one if there is an incorrectable error (block 72) and to reset the numerical value to zero if there is either an errorless situation (block 68) or if there is a correctable error. A second possibility is to increment the numerical value by two if there is an incorrectable error, to increment by one if there is a correctable error, and to reset to zero if there is no error. Other strategies, that take into account the amount of errors in a block could be used, such as increment by one in case of a single bit error, increment by two in case of a correctable burst error, increment by five in case of an incorrectable error, reset in case of a correct block. Still other strategies, that would take into account the recent error history, could also be used. The critical value in block 66 for deciding when synchronization has been lost depends on various criteria. As a general rule, this value is greater if the number of successive blocks to be received errorless in the synchronization phase is higher. For example, if the reception conditions are good, in the synchronization phase two successive blocks must be received error free (as in Figure 2). Then, the critical value would lie between 16 and 64. On the other hand, if the reception conditions are poor, only a single errorless block in the synchronization phase would imply synchronization. Then, however, the critical numerical value could be chosen lower, such as only 4. The reception conditions can be determined dynamically, for example on the basis of the amplitude or so-called field strength of the received broadcast, alone, or in combination with the well-known multi-pass conditions (coexistence of various transmission paths by virtue of reflections by buildings and the like), or, alternatively on the basis of past transitions between the synchronization phase and the user phase. In certain channel organizations the first block of a group contains always the same information word. Therefore, the whole block, incremented by a single off-set word is always identical. In this respect, Figure 4 illustrates the detection and correction of a bit slip error. As soon as the first block (of any arbitrary group) has been decoded errorless (block 54 in Figure 3) once, it is stored in an additional register in the form originally received. Upon reception of the first block of any next-following group it is compared to the stored block. This comparing may be done by bitwise EXCLUSIVE ORING and is effected, once in the presumably correct position in time (80 in Figure 4) and also with one bit off-set in each of the two possible directions (82, 84 in Figure 4). If the correct position yields an erroneous comparison, but either of the other two positions indicates a good comparison, the synchronization window is shifted in the corresponding direction. A different strategy is that the slip detection is effected only after the first block has been found incorrectible: in block 58 also the block number is taken into account. Now, various operations in the flow chart may take such time as to necessitate time sharing of the processing facilities of, for example a microprocessor or microcontroller. This could occur if the error correction operation is not yet ready before the first bit of the next block must be taken into account in block 52. Thus, the calculations for determining the time shift would also take such time as to produce a result only after the processing of the second block has begun already. Thus, in the case of a bit slip present, the second block would almost never lead to an errorless or "correctable error" situation. Now, the cited RDS system is such that the second block of a word is critical: if it is lost, the whole remaining group is considered lost. In Figure 3 this could be effected in that the block 66 also takes into account the block number and in case of "block 2" appears incorrectible, the operation in the block 48 is de-activated for the remaining blocks of the group in question. However, to avoid the incorrectability of block 2 in case of a forward slip, the calculations on block 2 then are delayed by one bit position. This, in one method, may be represented by the omission, of the first bit: the actual first bit received is now the second bit of the block and the calculations are adapted to this slip. In the multiplication by the parity check matrix the first multiplication thus is by the second row, and so on. The slip thus is translated into an "always zero" for the first data bit. If the bit should be zero, no problem is encountered. If the bit should be "one", this implies an (additional) single bit error that most often is correctable. A higher level solution would be to actually advance the syndrome calculation of block 2, in that the last bit of block 1 (slip assumed zero) is taken into account both for block 1 and for block 2, the latter representing a negative slip of block 2 by one bit position. After n1+n2 bits have been taken into account for block 2, the actual slip of block 1 may be known. For a value of this slip of -1, 0, and +1 bits, the system should, for block 2, execute the operations of block 40 in Figure 3 zero, one, or two times. Similar considerations apply for block one. Figure 5 is a diagram of a device for implementing the decoding method of the invention. Element 20 is an antenna for receiving a broadcast signal. Element 21 is a conventional radio receiver or tuner. The radio receiver is bidirectionally connected to its controlling microprocessor or microcomputer 22. Such control is conventional in present day systems. Element 15 represents the low-frequency decoding and amplification of the audio signal. Elements 16 represent the loudspeakers for the left hand and right hand channels, respectively. The remaining part of the apparatus serves for the digital data processing. In the first place a small separate microprocessor or microcomputer 14 is provided. This can be easily integrated in a small component 11, together with clock regenerator 12 and demodulator 13. The latter two are fed by the multiplex output of radio receiver 21. The information words retrieved according to the invention from the broadcast signal and forwarded to microprocessor 22 along an eight bit wide bus 23. Component 11 now operates completely independent from microprocessor 22. The latter's programming may be structured in an arbitrary way with respect to the functioning of component 11. Component 11 thus outputs the user words, block number, error data for each block and, if required, cumulative error data indicating the actual state of the error recovery procedure. The bus data format is not related to the present invention, and may well be one of several well-known universal bus formats. Microprocessor 22 may process the user words, i.e. store them in non-volatile RAM 17, display them on a visible display element not shown, convert them into a speech signal output, or use them as control signals for radio receiver 21. Figure 6 is a more functional diagram of certain parts of a device according to Figure 5. Input 100 is fed by radio receiver 21 in Figure 5. Block 102 is an interrogation device that interrogates input 100 at regularly spaced intervals as signalled by control signals on line 104. Block 106 receives the binarized input values from block 102 and determines the optimum position of the bit cell boundaries and therefrom intended interrogation positions to be signalled on line 104. Furthermore, block 106 provides for demodulation of the channel bits so that a sequence of data bits is outputted on line 108. Block 110 provides for the incremental matrix multiplications specified in blocks 40, 42, 46, 52 of Figure 3, while the increments are summed in an accumulator register. Block 112 represents a store for standard syndromes, each one corresponding with a predetermined off-set word. Block 116 is a selection element, whereby either all standard syndromes or only a selection thereof are activated for comparison to an actual syndrome. Block 114 is the actual comparator, that in the preferred embodiment operates on ten-bit syndromes received in parallel. The result is positive or negative and communicated to result evaluation element 118. The result evaluation element 118 feeds block 110 with a signal for signalling the positive output in block 44, or the negative output in block 44 (calculate next syndrome or update the syndrome, respectively). Block 118 also signals in block 50, 66, whether the next syndrome is to be calculated in the synchronized state, or in the non-synchronized state. Block 118 signals selection element 116 whether to unblock all standard syndromes, or only a particular subgroup of one or more standard syndromes for comparison. Block 118 signals block 122 that the block received on line 108 must be evaluated for error correction. The error correction is thereupon undertaken in block 122, the corrected information word is sent to block 124, and the correction result (single error corrected, burst error corrected, no error, correction impossible) is sent to block 118. Block 118 thereupon consults block 120 that contains the numerical value indicating the past error history. This numerical value is updated and restored. Based upon these results, either the output gate 124 is made transmissive or an appropriate user message is sent on output 126. Bit slip detection is effected by appropriate delay of the various comparison operations.

Claims: Verfahren zum Decodieren über einen Datenkanal übertragener Daten, die in Gruppen geordnet sind, wobeijede Gruppe eine feste Anzahl von N Blöcken umfaßt, jeder Block (j) ein Informationswort (MJ) von n1 Bits enthält und mittels Information eines linearen Fehlerschutzcodes zu einem fehlergeschützten Block von (n1+n2) Bits erweitert wurde, jedem geschützten Block in einer Gruppe ein vorgegebenes Offset-Wort WJ durch bitweises EXKLUSIV-ODERn zugesetzt wurde, und dieses Offset-Wort die Position des betreffenden Blocks innerhalb seiner Gruppen anzeigt, und das Verfahren folgende Schritte umfaßt: a) den Empfang einer Folge von (n1+n2) Datenbits aus dem Kanal in einer Einleitungsphase und die Erzeugung eines ersten Syndroms daraus mittels schrittweisen Operationen (42), wobei jede schrittweise Operation genau ein zuletzt empfangenes Datenbit berücksichtigt; b) den Vergleich des ersten Syndroms mit jeweiligen Standardsyndromen, wobei diese letzten allen möglichen Offset-Wörtern (44) entsprechen; c) das Auslassen des zuletzt empfangenen Datenbits aus den (n1+n2) Datenbits im Falle der Nichtübereinstimmung und das Aktualisieren des ersten Syndroms unter Berücksichtigung eines noch später empfangenen Datenbits (40), bis entweder im Schritt b) oder im Schritt c) eine Übereinstimmung mit einem Standardsyndrom auftritt, das einem Standardsyndrom entsprechend einem der vorgegebenen Offset-Wörtern entspricht; d) die Erzeugung eines zugeordneten Syndroms (52) für jeden folgenden Block von (n1+n2) Bits, die über den Datenkanal empfangen wurden, in einer Benutzerphase nach dem Schritt c) und den Vergleich mit (einem) seine Position anzeigenden Standardsyndrom(en) (54), wobei jeder folgende Block eine vorausgesetzte nächste folgende Position in der Gruppenreihenfolge einnimmt; e) das Ausgeben des Informationsworts des Blocks nach einem Benutzer (48) bei Übereinstimmung; die Durchführung einer Fehlerschutzoperation (56) im fehlergeschützten Block von n1+n2 Bits ohne das zugeordnete Offset-Wort bei Nichtübereinstimmung, dadurch gekennzeichnet , daß bei Übereinstimmung in der Benutzerphase (e) ein erstes Steuersignal ausgegeben wird (68), während bei Nichtübereinstimmung ein zweites Strategiesteuersignal ausgegeben wird (70), und daß der Schritt a) erneut gestartet wird, wenn eine Zeitfolge erster und zweiter Strategiesteuersignale aus einer spezifizierten Klasse von Zeitfolgen auftritt (66). Verfahren nach Anspruch 1, worin zwischen Schritt c) und Schritt d) eine zusätzliche Einleitungsphase eingeführt ist, in der beim Empfang eines Kanaldatenblocks (46) ein Syndrom erzeugt wird, das im Vergleich mit seiner zugeordneten Position, die ein Standardsyndrom (Standardsyndrome) (50) bis zu einer Folge einer vorgegebenen Länge von Vergleichen anzeigt, positive Ergebnisse erreicht hat, bevor zum Schritt d) (48) übergegangen wird, während ein negatives Ergebnis in der Folge unmittelbar den Schritt a) (42) neu startet. Gerät zur Durchführung des Verfahrens nach Anspruch 1 oder 2, wobei dieses Gerät Empfängermittel (102, 106) zum Empfangen eines Datenbitflusses aus dem Datenkanal, Matrixmultiplikationsmittel (110) zum Multiplizieren jedes empfangenen Datenbits mit einer eine Paritätsprüfmatrix erhöhenden Bitkette zum Erzeugen einer Syndrombitkette, Vergleichsregistermittel (114) zum Vergleichen einer Syndrombitkette mit der ihre Position anzeigenden Standardsyndrombitkette (112) unter der Steuerung von eine Position anzeigenden Wählmitteln (116), Einleitungs-/Benutzerphasesteuermittel (118) zum Entaktivieren der Wählmittel (116) in einer Einleitungsphase, aber zum Umschalten nach einer Benutzerphase unter der Steuerung einer Folge mit vorgegebener Länge positiver Vergleichsergebnisse, zum Aktivieren der Wählmittel (116) dabei, wobei das Gerät eine Fehlerauswerteinrichtung (128) mit einem ersten Zustand, um in der Benutzerphase unter der Steuerung eines positiven Vergleichsergebnisses ein Informationswort auszugeben, das in einem zugeordneten Kanalblock enthalten ist, während ein erstes Strategiesteuersignal ausgegeben wird, und mit einem zweiten Zustand zum Aktivieren einer Fehlerschutzanordnung (122) in der Benutzerphase unter der Steuerung eines negativen Vergleichsergebnisses zur Durchführung eines Fehlerschutzvorgangs enthält, während ein zweites Strategiesteuersignal ausgegeben wird, und ein Fehlerregistermittel (120) enthält, das von den ersten und zweiten Strategiesteuersignalen zum Umschalten der Einleitungs-/Benutzerphasesteuermittel (118) in die Einleitungsphase unter der Steuerung einer vorgegebenen Zeitfolge gespeist wird. Gerät nach Anspruch 3, worin die Einleitungs-/Benutzerphasesteuermittel (128) Zählmittel zum Zählen einer vorgegebenen ununterbrochenen Folge wenigstens zwei positiver Vergleiche vor dem Umschalten in die Benutzerphase besitzt, und worin ein negatives Vergleichsergebnis in der Einleitungsphase zum Rückstellen der Einleitungsphase nach ihrem Startpunkt wirksam ist. Gerät nach Anspruch 3 oder 4, worin das zweite Strategiesteuersignal einen Fehlertyp spezifiziert, das momentan für typenabhängige Steuerung der Fehlerregistermittel gefunden ist. Gerät nach Anspruch 3, 4 oder 5, weiter mit Bitgleitdetektionsmitteln zum Vergleichen eines vorgegebenen Kanaldatenblocks, wie er mit verschiedenen verschobenen Positionen eines später eingetroffenen vorgegebenen Kanaldatenblocks gespeichert ist, wobei ein Ausgang der Bitgleitdetektionsmittel die Vergleichsmittel (114) zum Ausgleichen des Bitgleitens steuert. Gerät nach Anspruch 6, worin die Bitgleitdetektionsmittel für einen vorgegebenen Block innerhalb einer Gruppe wirksam ist, und worin ein Bitgleitkorrekturmittel für den folgenden Block in derselben Gruppe vorgesehen ist. Gerät nach einem der Ansprüche 3 bis 7, worin das Fehlerregistermittel (120) einen rückstellbaren Zähler enthält, der durch ein unkorrigierbares Fehlersignal erhöht wird, aber durch ein anderes erstes oder zweites Strategiesteuersignal auf Null zurückgestellt wird, und worin ein vorgegebener Zählstand das Umschalten in die Einleitungsphase steuert. Gerät nach einem der Ansprüche 3 bis 7, worin das Fehlerregistermittel (120) einen rückstellbaren Zähler enthält, der durch ein zweites Strategiesteuersignal erhöht und durch ein erstes Strategiesteuersignal zurückgestellt wird, und worin ein vorgegebener Zählstand das Umschalten in die Einleitungsphase steuert. Gerät nach Anspruch 8 oder 9, worin der vorgegebene Zählerstand einstellbar ist. Gerät nach einem der Ansprüche 3 bis 10, mit einem Rundfunkempfänger (221) zum Empfangen eines Rundfunksignals und zum Ableiten daraus des Datenbitflusses, wobei der Rundfunkempfänger (21) außerdem ein Meßmittel zum Messen eines Qualitätspegels des Rundfunksignals enthält und daraus ein Umschaltsteuersignal ableitet, und worin das Umschaltsteuersignal zum Einstellen der vorgegebenen Länge oder eines kritischen Wertes der vorgegebenen Zeitfolge in der Einleitungs-/Benutzerphasensteuermittel wirksam ist. Gerät nach einem der Ansprüche 3 bis 11, mit einem Radioempfänger (21) und einem ersten Mikrocomputer (22) zum Steuern des Radioempfängers, in dem das Gerät ebenfalls einen Universaldecoder (11) enthält, der aus einem Demodulations-(13) und einem Taktregenerationsbauteil (12) besteht, dessen Eingang mit einem Multiplexausgang des Radioempfängers verbunden ist, und einen zweiten Rundfunkdatenverarbeitungsmikrocomputer (14) enthält, dessen Ausgang mit einem Dateneingang (23) des ersten Mikrocomputers (22) verbunden ist. Gerät nach Anspruch 12, worin der Dateneingang (23) ein Universalbusanschluß ist. Gerät nach Anspruch 11, 12 oder 13, worin der erste Mikrocomputer (22) zusätzlich zum Informationswort eines Blocks wenigstens eine weitere Information bezüglich einer Fehlerschutzsituation oder Blockorganisation ausgibt.

Inventors: MAUGE, JACQUES
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN, PHILIPS ELECTRONIQUE GRAND PUBLIC
Application year: 1986
Main classification: H04L7
IPC codes: H04B7, H03M13, G08G1, H04H60, H04L1, H04L7