A LOW TEMPERATURE METHOD FOR FORMING A GATE INSULATOR LAYER FOR SEMICONDUCTOR DEVICES

Abstract: A low temperature method of controlling the drain current drift and enhancing the channel mobility in InP-MISFETs by saturating an InP substrate surface with phosphorous and subsequently forming a phosphorous rich native oxide. This is followed by in-situ formation of a gate insulator layer on the phosphorous rich native oxide. The phosphorous rich native oxide is formed at a low temperature in the range of 200 DEG C - 300 DEG C using an isolated plasma enhanced chemical vapor deposition.

Description: A LOW TEMPERATURE METHOD FOR FORMING A GATE INSULATOR LAYER FOR SEMICONDUCTOR DEVICES BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing semiconductor devices, and more particularly to a low temperature method for forming a gate insulator for semiconductor devices. 2. Description of Related Art Group III-V semiconductors offer significant potential for high speed digital circuits, optoelectronic devices and high frequency power devices. This potential is particularly evident in devices constructed on InP substrates, because of the high saturation velocity, low ionization coefficients and high carrier mobility of InP. However, as in MOSFETs, the insulator layer in InP devices plays an important role in determining device characteristics. For example, the insulator layer should be fully compatible with the InP substrate to suppress interface state density between the insulator layer and the substrate. Moreover, minimal thermal strain should be produced on the semiconductor surface during gate insulator deposition. This strain causes surface defects such as anti-site defects in InP which tend to c?usø the drain current of InP Metal-Insulator-Semiconductor Field-Effect Transitors (MISFETs) to drift over a period of time, and to reduce the mobility of carriers in the channel of InP-MISFETs. Therefore, development of the full potential of InP devices, such as InP-MISFETS depends upon the formation of a fully compatible insulator layer at low temperatures and upon the control of drain current drift in the. devices. Additionally, typical manufacturing processes for semiconductor devices include process steps requiring temperatures above 300°C. These temperatures cause an InP substrate to decompose due to the loss of phosphorus from the surface of the InP substrate. Thus, in addition to the need for a compatible insulator layer, InP-MISFETs should be manufactured using processes employing temperatures less than 300°C. Prior to our invention, InP-MISFETs exhibited drain current drift and low channel mobilities which limited the application of these devices with practical circuits. Our invention alleviates these drawbacks and enables InP-MISFETs to be used in variety of useful circuits. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for fabricating a gate insulator layer for semiconductor devices which produce high carrier mobility and reduced interface state density. Another object of the present invention is to provide a method for fabricating a gate insulator layer for semiconductor devices which minimizes device drain current drift. A further object of the present invention is to provide an improved method for fabricating III-V semiconductor devices. Another object of the present invention is to provide an improved method for fabricating a gate insulator layer for semiconductor devices. A further object of the present invention is to provide a low temperature method for fabricating a gate insulator layer for semiconductor devices. Still another object of the present invention is to provide a method for fabricating a gate insulator layer for semiconductor devices that minimizes stress and thermal strain to the semiconductor during gate insulator deposition. Still a further object of the present invention is to provide a method for fabricating a gate insulator layer which controls contaminants and out-diffusion of impurities between the insulator layer and an underlying substrate. Still a further object of the present invention is to provide a method for fabricating a MISFET insulator layer with reduced density of interface states between the insulator layer and an underlying substrate. To achieve the above and other objects, the present invention comprises a low temperature method of forming a gate insulator layer on a substrate housed within a chamber, the method comprising the steps of: heating the substrate to a first temperature in an atmosphere of a first gas; ionizing a second gas in the chamber thereby forming energetic species of the second gas; forming a first portion of the gate insulator layer from the first gas and at least one of the energetic species of the second gas; introducing a third gas into the chamber; and forming a second portion of the gate insulator layer from at least one of the energetic species of the second gas and at least one reactant species of the third gas. In a preferred embodiment of the present invention the substrate comprises InP and is heated to a temperature in the range of 200-300°C in an atmosphere of phosporous vapor or phosphine (PH3) . The second gas comprises N2°» and the energetic species are formed in a plasma of the N 2 0. The first portion of the gate insulator layer comprises ^2°x N l-x» where 0.8 is less than x which is less than 0.99. The third gas selectively comprises one of SiH 4 and TEOS ( (C2H5O)4 Si). The second portion of the gate insulator comprises one of Siθ2 or PχN v 0 2 * where x is approximately 0.3, y is approximately 0.54 and z is approximately 0.1. The first portion of the gate insulator layer is formed to a thickness in the range of 25& to 10θϋ. In the preferred embodiment, the second gas is ionized in a region below the substrate so that the substrate is not damaged by the energetic species. Because a first portion of the gate insulator layer in devices fabricated using the present invention comprises a phosphorus rich native oxide, physical strain between an Siθ2 insulator layer and a InP substrate generated during insulator deposition is suppressed, and surface defects such as anti-site defects are suppressed. In addition, due to the low water content in the phosphorous vapor, OH is eliminated from the interface between the substrate and the insulator layer. Channel mobility is improved because surface defects at the surface of the InP substrate are minimized and because interface state density is reduced and dangling bonds at the surface of the InP substrate are minimized, so that carrier scattering is reduced. As a result of the higher channel mobility, InP devices have improved gain, higher power and higher switching speed for example, above 1GHz. Finally, the anti-site defects which act as acceptors are reduced due to saturation of the InP substrate surface with phosphorous. As a result the drain current for InP devices does not drift over time. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings serve to facilitate explanation of the method of the present invention and to illustrate the features and advantages of the present invention. Fig. 1 is a schematic, isometric view of an apparatus for practicing the method of the present invention; Fig. 2 is a cross-sectional view of an InP-MISFET having an insulator layer fabricated using the method of the present invention; Fig. 3 is a graph illustrating the reduced drain current drift of a device having an insulator layer fabricated using the method of the present invention; Fig. 4 is a CV plot of a device having an insulator layer fabricated using the method of the present invention; Fig. 5 is a graph illustrating the DC characteristics of a device having an insulator layer fabricated using the method of the present invention; and Fig. 6 is a graph illustrating the reduced interface density states of a device having an insulating layer fabricated using the method of e present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a schematic, isometric view of an apparatus for practicing the method of the present invention. In Fig. 1, reaction chamber 10 comprises a cylinder 15 hermetically sealed at ends 20. The cylinder 15 can comprise, for example, quartz glass. A pedestal 25 is mounted within the reaction chamber 10 and a substrate 30 is positioned thereon. Positioned below the pedestal 25 are plasma generating electrodes 35 and 40. Each of these electrodes can comprise, for example, an electrically conductive ring. The pedestal 25 can comprise, for example, electrolytically coated graphite or refractory metal coated stainless steel. The pedestal 25 includes a thermocouple (not shown) which senses the pedestal temperature, and therefore the temperature of the substrate 30. A cylinder 45 contains the pedestal 25 and is positioned such that the plasma generating electrodes 35 and 40 are outside the cylinder 45. A vacuum pump 50 connects through tube 55 to port 60 within the cylinder 45. The vacuum pump 50 maintains the pressure within the reaction chamber 10 in the range of 1-1.5 Torr. The vacuum pump 50 can comprise any relatively inexpensive mechanical unit or a turbo pump. An effusion cell 65 provides a gas through a tube 70 to a dispersion head 75 which is positioned close to the substrate 30, e.g. approximately two inches above the substrate 30. The effusion cell 65 comprises a first vessel 80 having housed therein a second vessel 85. The second vessel 85 contains a material 90 to be dispersed within the reaction chamber 10. The material 90 can comprise, for example, phosphorous. Pressure within the first vessel 80 is held within the range of 0.3 - 0.5 Torr. Furnace elements 95 heat the phorphorous 90 to a temperature in the range of 250°C to 400°C to produce gaseous P 4 species, and a tube 100 supplies an inert gas such as hydrogen to the chamber 80. The P 4 species ride on the inert gas molecules through tube 70 to disperson head 75. A heating element 105 wrapped around tube 70 insures that the phosphorous does not condense on the tube 70. Additional effusion cells could be connected to chamber 10, and used to provide dopants for growing various doped layers. As an alternative to providing gaseous phosphorous to chamber 10 via effusion cell 65, phosphine (PH 3 ) with a low water content in the range of 10 parts per million, could be supplied to the tube 70. A tube 110 supplies a reactant gas to dispersion head 115. The dispersion head 115 can comprise, for example, stainless steel, and is connected to a power supply (not shown) so that the tube 115 functions as the plasma electrode 40. A tube 120 supplies a gas through a dispersion head 125 to a region above the substrate 30. The dispersion head 125 comprises quartz diffuser shower head type assembly for dispersing the gas supplied by tube 120. The quartz diffuser comprises a filter tube with a fritted glass disk. The porosity of the fritted glass disk is in the range of 4-5^m. A grid electrode 130 is positioned over the cylinder 45. The grid electrode 130 can comprise, for example, tungsten, molybdeum or stainless steel, and can be connected to a power supply (not shown) to control the flow of charged species to the substrate 30. Alternatively, the grid electrode 130 can be connected to ground to neutralize any charged species as they travel in the direction towards the substrate 30. A similar apparatus is disclosed in copending 8 U.S. patent application having the same inventors as the subject application, having a common assignee. Allied, and entitled: "An Isolated Plasma Enhanced Chemical Vapor Deposition System." In a preferred embodiment of the method of the present invention, an InP substrate 30 is placed on the pedestal 25. The pressure within the effusion cell 65 is maintained in the range of 0.3 - 0.5 Torr, and the furnace elements 95 heat the phosphorous 90 to a temperature in the range of 250 β C - 400°C, so that the phosphorous vaporizes. An inert gas is applied through tube 100 so that the gaseous phosphorous passes through the tube 70 to diffusion head 75. As the gaseous phosphorous passes through the tube 70 toward the diffusion head 75, the substrate is heated to a temperature in the range of 200°C - 300°C, for example 280°C. After the substrate reaches the desired temperature, it is heated at that temperature for approximately 3min. - 5min. to saturate the InP substrate surface and to compensate for any loss (e.g., out-diffusion) of phosphorous from the InP substrate 30. After heating the substrate 30 in the phosphorous atmosphere for 3 min. - 5 min., N2O is passed through tube 110 to diffusion head 115 at a rate in the range of 15 - 50cc/min. Power is applied to the plasma electrodes 35 and 40 (which corresponds to diffusion head 115) to generate a plasma in the N 2 0. The plasma electrodes 30 and 45 are spaced from each other by approximately 1 inch. The plasma power density is in the range of 1.0 - 1.5 /cm 2 . The plasma generates energetic species comprising atomic oxygen and atomic nitrogen. These energetic species react with the gaseous P4 species carried into the reaction chamber 10 from the effusion chamber 65 via tube 70 and dispersion head 75. This reaction forms a phosphorous rich native oxide on the InP substrate. The native oxide comprises ?2°x N l-x' where x is approximately 0.97. The preferred thickness of the phosphorous rich native oxide is in the range of 25& to IOOA. The particular thickness is determined by the charge carrier tunneling range and density of states to be reduced. After growing the phosphorous rich native oxide layer 135 (Fig. 2) to the desired thickness, the flow of P 4 through tube 70 and diffusion head 75 is stopped by turning off the furnace elements 95. This stops the phosphorous vaporization. The inert gas is, however, left flowing to flush out the system. Next, a gas comprising SiH 4 at a rate in the range of 2.5 - 5cc/min., or (C2H5O) 4 Si) (i.e., TEOS) at a rate in the range of 25 - 50cc/min., is supplied to reaction chamber 10 through tube 120 and diffusion head 125. The ratio of the flow rates of N2O and SiH4 is approximately 12:1. The energetic species of atomic oxygen (0) and atomic nitrogen (N) generated by the plasma electrodes 35 and 40 decompose the gas introduced into the reaction chamber 10 via diffusion head 125 to provide atomic Si. (After colliding with molecules of either SiH 4 or (C2H5θ) 4 Si, the species are no longer considered as energetic.) The atomic Si and atomic oxygen adsorb on the substrate 30 which is heated to a temperature in the range of 250 β C - 300 β C; that is, on the phosphorous rich native oxide 135. The atomic Si and atomic 0 then migrate and react to form a Si0 2 insulator layer 140 shown in Fig. 2. A typical thickness of the insulator layer 140 is in the range of 600A - 700A. Alternatively, insulator layer 140 can comprise AI2O3, Gβ3N 4 or phoslon (P x N y O z where x is approximately 0.36, y is approximately 0.54 and z is approximately 0.1). For example phoslon can be formed by supplying gaseous phosphorous to reaction chamber 10 from effusion cell 65 using, for example, N 2 as a carrier gas, and 2O to the plasma electrode 40. After forming the insulator layer 140 to the desired thickness, generation of the plasma between electrodes 35 and 40 is stopped, as is the flow of gases to the reaction chamber 10 except for the inert gas which is used to purge the system. If desired, a device having an insulator layer fabricated using the method of the present invention can then be annealed. Annealing normally takes place at temperature of approximately 300 β C and lasts for approximately 20min. - 30min. Two alternative annealing processes are as follows. In the first alternative, the furnace elements 95 are energized to produce a gaseous phosphorous which is introduced into the reaction chamber via dispersion head 75 and the inert gas supplied to tube 100 is hydrogen (H) . The annealing therefore occurs in a phosphorous vapor in a hydrogen atmosphere. In the second alternative, power can be applied to electrodes 35 and 40 and AsH 3 supplied to the reaction chamber 10 via tube 110 and dispersion head 115. Annealing therefore occurs in an As atmosphere. This in-situ annealing further reduces the interface density to approximately 8 x 10 10 cm" 2 ev _1 . It is presumed that the reduction in interface density when annealing with, for example, AsH 3 results from both the H and As permeating the Si0 2 to minimize any dangling bonds in the phosphorous rich native oxide layer 135 shown in Fig. 2. Fig. 3 illustrates the drain current drift in a MISFET having an insulator layer formed using the method of the present invention. As seen in Fig. 3 the drain current drift is negligible over a test time of 10 5 sec. Fig. 4 is a CV plot of a device having an insulator layer fabricated using the method of the present invention. The data shown in Fig. 4 was obtained from a MIS capacitor having an insulator layer fabricated using the method of the present o invention, and having a 600A Siθ2 layer formed on a 100A layer of phosphorous rich native oxide. The data shown in Fig. 4 is for an unannealed sample, .-or such a sample only an extremely small (i.e., negligible) hysteresis was measured. The dotted waveform in Fig. 4 represents the type of hysteresis normally ocurring in annealed MIS capacitors not fabricated using the method of the present invention. Annealing a MIS device in our invention as described above results in a hysteresis free CV plot. Fig. 5 is a graph illustrating the DC characteristics of a device such as illustrated in Fig. 2 having a 4 urn gate length. The high output current obtained with such a device clearly indicates that the device can be used in a high power MISFET when a larger gate width is employed. MISFETs including an insulator layer fabricated using the method of the present invention have channel mobilities in the range of 3200cm 2 /v-s to 3700cm 2 /V-s. This is considerably higher than the channel mobility of MISFETs without a phosphorous rich native oxide which at best, have a channel mobility of approximately 2600 cm 2 /V-s and which is more typically in the range of 1000 - 2000cm 2 /V-s. The inventors believe that the high channel mobility of devices having an insulator layer fabricated using the method of the present invention results from reduced carrier scattering at the phosphorous rich native oxide/Si0 2 interface due to the reduction in the number of dangling bonds and surface defects. The high channel mobility in MISFET devices including an insulator layer fabricated using the method of the present invention results in high transconductance (e.g., 62mS/mm for 4urn gate length devices) for short gate length devices, and consequently, ultra high speed performance for integrated circuits based upon InP-MISFETs having an insulator layer fabricated using the method of the present invention. The significantly enhanced channel mobility also results in devices having improved gain, higher power and higher switching speeds (above 1GHz). The method of the present invention results in a significant reduction of interface state densities which the inventors believe is due to the phosphorous rich native oxide minimizing any dangling bonds, and results in a very smooth interface between the gate insulator and the InP substrate. Fig. 6 is a graph illustrating the reduced interface state density of a device having an insulator layer fabricated using the method of the present invention. Minimum densities in the range of 9 x 10^°cm"" 2 eV~l were measured for unannealed devices, and for annealed devices densities in the range of 8 x 10^°cm" 2 eV~ 1 were measured. These values are considerably lower than those associated with devices not having an insulator layer fabricated using the method of the present invention which are in the range of 4 x 10 11 cra" 2 eV" 1 . The method of the present invention also significantly reduces drain current drift because anti-site defects (e.g.. In on P site, or P on an In- site) which behave as acceptors are suppressed. The negligibly small drift current resulting from the 13 method of the present invention is a significant improvement over the large drift currents of, for example, greater than 20% of the channel current, which occur in InP-MISFET devices which do not have an insulator layer fabricated using the method of the present invention. Additionally, InP-MISFET devices having an insulator layer fabricated using the method of the present invention exhibit a hysteresis free CV characteristic leading to more reliable devices. It will be apparent to those skilled in the art that modifications and variations can be made in the method of the present invention. Thus, the present invention is not limited to the embodiment described above, and instead, is limited only to the scope of the appended claims and their equivalents.

Claims: - 14 - CLAIMS What is claimed is: 1. A low temperature method of forming a gate insulator layer on a substrate housed within a chamber, comprising the steps of: a) heating the substrate in an atmosphere of a first gas; b) ionizing a second gas in the chamber, to form species of the second gas; c) forming a first portion of the gate insulator layer from the first gas and at least one of the species of the second gas; d) introducing a third gas into the chamber; and e) forming a second portion of the gate insulator layer from at least one of the species of the second gas and at least one reactant species of the third gas. 2. A low temperature method for forming a gate insulator layer according to claim 1, wherein said step d) comprises the substep of i) decomposing the third gas into reactant species using the species of the second gas. - 15 - 3. A low temperature method of forming a gate insulator layer according to claim 2, wherein said substep i) comprises decomposing the third gas in a region above the substrate. 4. A low temperature method for forming a gate insulator layer according to claim 3, wherein said step a) comprises heating the substrate to a temperature in the range of 200 β C - 300 β C. 5. A low temperature method of forming a gate insulator layer according to claim 4, wherein said step a) comprises heating the substrate in an atmosphere comprising one of P 4 and PH3. 6. A low temperature method of forming a gate insulator layer according to claim 5, wherein in said step b) , the second gas comprises N2O. 7. A low temperature method for forming a gate insulator layer according to claim 6 wherein in said step d) , the third gas comprises one of SiH 4 and (C 2 H 5 0) 4 Si. 8. A low temperature method of forming a gate insulator layer according to claim 7, wherein in said step c) , the first portion of the gate insulator layer comprises P2θχ N l-χ* 9. A low temperature method of forming a gate insulator layer according to claim 8, wherein x is in the range of 0.8 to 0.99. 10. A low temperature method of forming a gate insulator layer according to claim 9, wherein said step c) comprises the substep of forming the first portion of the gate insulator layer to a thickness in the range of 25& - 100&. 11. A low temperature method of forming a gate insulator layer according to claim 1, wherein said step b) comprises the substep of generating a plasma in the second gas. 12. A low temperature method of forming a gate insulator layer according to claim 11, wherein said step b) further comprises the substep of generating the plasma in a region below the substrate. 13. A low temperature method of forming a gate insulator layer according to claim 12, wherein said step b) further comprises the substep of generating the plasma with a plasma energy in the range of 0.3W/cm 2 - 1.5W/cm 2 . 14. A low temperature method of forming a gate insulator layer according to claim 13, wherein said step a) comprises heating the substrate to a temperature in the range of 200°C - 300°C. ^ 15. A low temperature method of forming a gate insulator layer according to claim 14, wherein said step a) comprises heating the substrate in an atmoshphere comprising one of P 4 and PH3« 16. A low temperature method of forming a gate 5 insulator layer according to claim 15, wherein in said step b) , the second gas comprises N 2 0. 17. A low temperature method of forming a gate insulator layer according to claim 16, wherein in said step d) , the third gas comprises one of SiH 4 and ( C 2 H 5 0) 4 Si. - 17 - (C 2 H 5 0) 4 Si . 18 * A low temperature method of forming a gate insulator layer according to claim 17, wherein in said step c) , the first portion of the gate insulator layer comprises P2 0 N l-x» 19. A low temperature method of forming a gate insulator layer according to claim 18, wherein x is the range of 0.8 to 0.99. 20. A method of forming an insulator layer on a substrate housed within a chamber, comprising the steps of: a) heating the substrate to a first temperature in a first atmosphere; b) generating a plasma in a first gas to form species of the first gas; c) forming a first portion of the gate insulator layer on the substrate from the first atmosphere and at least one of the species of the first gas; d) introducing a second gas into the chamber such that the species of the first gas decompose the second gas into reactant species; and e) forming a second portion of the gate insulator layer on the first portion of the gate insulator layer, from the species of the first gas and at least one of the reactant species of the second gas. 21. A low temperature method of forming a gate insulator layer according to claim 20, wherein said step a) , the first temperature is in the range of 200 β C - 300 β C, and the first atmosphere comprises one of P 4 and PH 3 . - 18 - 22. A low temperature method of forming a gate insulator layer according to claim 21, wherein said step b) comprises the substep of generating the plasma with a power in the range of 0.3W/cm 2 - 1.5W/cm 2 . 23. A low temperature method of forming a gate insulator layer according to claim 22, wherein in said step d) , the second gas comprises one of SiH 4 24. A low temperature method of forming a gate insulator layer according to claim 23, wherein in said step b) , the first gas comprises N2O. 25. A low temperature method of forming a phosphorous rich native oxide on an InP substrate housed within a chamber, comprising the steps of: a) heating the substrate to a temperature less that 300 β C in an atmosphere of phosphorous; b) generating a plasma in a first gas to form species of the first gas; c) forming a native phosphorous oxide layer including a species of the first gas on the substrate; d) introducing a second gas into the chamber such that the species generated in step b) decompose the second gas into its reactant species; and e) forming an insulator layer on the native phosphorous oxide layer from the species generated in step b) and at least one of the reactant species of the gas introduced in step d) .

Inventors: GUTIERREZ DAVID, PANDE KRISHNA PRASAD, GUTIERREZ, DAVID, PANDE, KRISHNA, PRASAD
Applicants: ALLIED CORP, ALLIED CORPORATION
Application year: 1986
Main classification: H01L21
IPC codes: H01L21, H01L29