DETECTION OF INSTANTANEOUS SPEED VARIATIONS IN A TAPE DRIVE

Abstract: Apparatus and method for detecting short-term speed variations in a reel-to-reel tape drive for use with digital data, comprising counters (132) for generating time windows representing equal numbers of data bits read from the tape, further counters (135) for counting up during one window and down during the next, comparators (136, 137) for comparing the residual count of the up/down counters with preset limits and an error indicator (138, 134) for indicating the condition when the residual count exceeds the permitted bounds. The invention may be practised over a plurality of data tracks, in which case the apparatus includes means (139, 140) for indicating an overall error when an error has been detected on all tracks.

Description: Technical Field of Invention This invention relates to an apparatus and method of detecting unacceptable data recording density variations on a record medium caused by short-term variation of the recording medium past a data detector. The invention is particularly concerned with detecting such variation in a reel-to-reel tape drive. Background Art Reel-to-reel tape drives capable of recording a plurality of high density information tracks on the tape require that the movement of the tape through the recording and reading heads of the drive be tightly controlled. US-A-4,015,799 assigned to the assignee of the present application describes apparatus for controlling the motion of the tape to achieve a high degree of control over the tape movement. However, it has been discovered that, even with the sophisticated control apparatus provided by US-A-4,015,799, undetected instantaneous speed variations (ISV) can be encountered. These ISV's are of extremely short duration and can go undetected in a recording drive which is designed to accommo­ date some speed variation. It is when the ISV goes undetected that problems can subsequently develop. For example, the tape may be loaded into another drive which cannot respond as proficiently as the original recording drive and may, therefore, not be able to read the recorded data. The present invention overcomes this problem by ensuring that ISV's do not go undetected. Various techniques for monitoring tape speed are known. For example, US-S-3,439,354 to Behr et al describes a speed checker for a tape transport where the speed is determined by detecting the interval between recording a bit on the tape and detecting the bit at a read head which is a precise distance from the write head. This approach will detect the average speed of the tape between the write and read heads, however, it would not detect any instantaneous speed variations which may occur during the movement between the heads and which have become a problem with the very high density tape media which is of concern herein. US-A-3,829,893 to Baichtal is another tape speed monitor where the tape speed is determined by measuring the interval between recording and reading data on the tape media. This patent also does not disclose any arrangement for detecting ISV's. US-A-4,409,628 (Frimet et al) discloses a speed control system for a tape transport mechanism where the tape speed is derived via a phase-­ locked-loop from a data track on the tape. It includes the ability to switch over to a second data track in the instance of a drop out (loss of signal) on the first track. Additionally, it includes the use of a background clock if the data signal is lost from both tracks. This approach will detect the speed of the tape past the playback head or heads but does not provide the ability to detect ISVs. US-A-4,007,492 to Rose describes apparatus for monitoring the velocity of a rotating member to ensure that the member is rotating at an acceptable speed. The rotational speed of the member is compared with an asynchronous AC line frequency. This comparison is used to determine whether a recording medium is moving at an acceptable rate so that a magnetic head is positioned in transducing relationship with the medium only when the motion of the medium is adequate for a transducing operation. The patent does not disclose any means for detecting an ISV when recording on the medium. Disclosure of the Invention The present invention provides, in a multiple track digital record­ ing system, apparatus for detecting instantaneous speed variations in the movement of the recording medium. The apparatus consists of means for detecting a change in the recording rate on a preselected number of the recording tracks on the medium and means for recognising that all of the preselected recording tracks have detected an unacceptable change in the recording rate. The invention may be implemented in either an analogue or a digital form. In a preferred analogue form, a buffer means responds to instantaneous memory voltage changes from the pre­ selected recording tracks, the changes in instantaneous voltages from the tracks are then summed together and the resultant compared to a threshold voltage. If the summed voltage exceeds the threshold voltage, an unacceptable data rate variation has been detected and the unsatis­ factorily recorded data is rewritten. In a preferred digital form, the nominal frequency of a voltage controlled oscillator (VCO) is divided into a plurality of intervals. The frequency output of the VCO is controlled by the memory voltage output from a read circuit phase lock loop phase error detector. A high speed clock steps a counter posi­ tively during the first half of the intervals and negatively during the second half of the intervals. The counting is terminated at the end of each interval and if the count from a counter for a preselected record­ ing track is greater than a specified minimum at the time of termination, a signal indicating a possible instantaneous speed variation is provided. The outputs of each preselected recording track detecting circuit are AND'ed so that an output indicating an ISV condition is provided only when all preselected tracks indicate such a condition. The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings. Brief Description of the Drawing Figure 1 is a diagram of a typical tape drive for which the present invention is useful. Figure 1A is an example of the write circuitry which may be used for each of a plurality of typical write heads. Figure 1B is an example of the read circuitry which may be used for each of a plurality of typical read heads. Figure 2 is a block diagram of a digital implementation of an instantaneous speed variation detector circuit. Figures 3A, 3B, 4A, 4B, 4C, 4D, 4E and 5 provide a more detailed representation of a preferred embodiment of the instantaneous speed variation detector circuit. Figures 6A and 6B illustrate some of the timing signals present in the instantaneous speed variation detector circuit. Figure 7 is a block diagram of an analogue implementation of an instantaneous speed variation detector circuit. Description of the Preferred Embodiments It has been discovered that, in at least some reel-to-reel tape drives, the tape path can be subject to instantaneous speed variations (ISV). Such a change in tape speed is manifested to the transducing system as a change in the date rate and can normally be accommodated by the system. However, if the change in data rate is too rapid, the system clock cannot make the required adjustments and data will be erroneously detected. As the speed variation affects the entire tape width, all tracks will simultaneously produce erroneous data. This unique condition can be used to distinguish an ISV condition from other tape error conditions which normally do not impact all tracks simultaneously. When substantial tape speed variations occur during a write operation, the density of the data written on the tape experiences a substantial change. This change in data density creates a stress condition that may be beyond the capacity of the read operation of some tape units and, therefore, be subsequently undetectable as valid data by those units. If the variation in data density is not detected during a write check operation in the drive creating the tape, the drive may consider the data acceptable. Furthermore, the data will often by satisfactorily read on other drives. However, the stress condition may make it impossible for some drives to read the tape. Clearly, it is not acceptable to record data which can be read by some drives and not others. Of course, with severe ISV conditions, no drive will be able to read the data and, therefore, the data recording will be rejected at the outset and no subsequent problem can arise. It is with the less severe ISV conditions that we encounter a problem. The less severe ISV condition may go undetected initially and subsequently be discovered when an attempt is made to read the data on another tape drive. If the data cannot be read at that time, the data may will be totally lost. Consequently, it is essential to detect this less severe condition at the time of occurrence. The present invention provides means for detecting this less severe condition at the time of recording so that any data written during an ISV condition may be subsequently rewritten so that the recording data rate variation is maintained within tolerances acceptable to all compatible tape drives. Figure 1 illustrates schematically a reel-to-reel tape drive of a type which can experience problems with instantaneous speed variations in the tape path. Even though tape 14 is tightly controlled within the tape path between tape reels 10 and 12, sudden changes of speed of very short duration may occur. For example, a sudden jump of the tape caused by non-uniform coiling of the tape on the reel, commonly described as interlayer slip, may be encountered on either reel. As shown in Figure 1, tachometers 18, 24 and 30 detect the linear tape speed in the tape path and the rotational speed of the tape reels. The outputs 34, 32 and 36 of tachometers 18, 24 and 30 are analysed by motion control logic 44 which generates the necessary control signals to drive digital-to-­ analogue converters 46 and 48. The outputs of converters 46 and 48 are fed to drive motors 20 and 26 through compensating filters 50 and 52 and amplifiers 54 and 56. By this means, the relative speeds of drive shafts 22 and 28 are closely controlled so that relatively stable tape motion is provided between reels 10 and 12. A more detailed description of the tape control procedure is provided in previously referenced US-A-4,015,799. As the tape control is not part of the present invention it will not be further described herein. However, as has been emphasised hereinbefore, even with such tightly controlled tape movement as is provided by the control system described in US-A-4,015,799, perturbations of tape motion of very short duration can occur and go undetected. These perturbations must be identified at the time of occurrence if subsequent problems are to be avoided. Detection of these perturbations or instantaneous speed variations (ISV) requires a reading of the recorded signal immediately after writing. Furthermore, it is necessary to obtain a reading from a sufficient number of the recorded parallel tracks such that the error, if detected, can be clearly identified as arising from an ISV rather than some other source. This can be done since errors arising from an ISV will affect will tracks, whereas, all other types of errors which would be of such short duration could only affect some of the tracks. Circuitry suitable for writing and reading a plurality of data tracks simultaneously is also shown schematically in Figures 1A and 1B, respectively. As shown in Fig. 1A, each write head 60 receives a write data signal. The write data is provided to flip-flop 62 which provides a clipped signal to tri-state buffers 64 and 65. Buffers 64 and 65 are enabled by the write enable signal to provide write signals to head 60. A source of voltage 66 is applied to head 60 to provide current flow, thus creating the recording magnetic field in the head. Identical write circuitry is provided for each write head. The read circuitry is shown in Fig. 1B. As with the write circuitry, the read circuitry is replicated for each read head 70. Read head 70 provides a signal to a differential to single ended converter 72 in accordance with flux changes in the recording medium passing under read head 70. Converter 72 provides an output signal to amplifier 74. The amplifier output is provided to data detector 76. Data detector 76 provides an input signal to a phase comparator consisting of phase detector 78 and loop filter 79 which controls the voltage controlled oscillator (VCO) 80. The phase comparator compares the phase of signals received from detector 76 with the frequency signals from oscillator 80 and thereby provides a control voltage to the oscillator 80 to alter the output frequency of the phase lock loop of oscillator 80. Oscillator 80 controls the sampling frequency of data detector 76. The memory voltage output of phase comparator 78 can be used to detect changes in the data velocity as such changes are reflected in the phase variations between the phase of the detected data and the phase of the output of the phase lock loop of the oscillator 80. The inventors have devised two ways of detecting ISV's. The currently preferred approach is to use digital circuitry for detecting the ISV's. Figure 2 shows a block diagram of a digital ISV detector. A gate 130 provides a signal to an alignment flip-flop 131 to ensure that the flip-flop 131 is only active when data is over the head. This prevents any attempt to detect for ISV's in inter block gaps where it is acceptable for the drive to start and stop. A read data clock signal from a voltage controlled oscillator, such as 80 in Fig. 1B, is provided to a first set of counters 132 to establish up/down windows for starting each cycle and ending the previous cycle. The length of the up and down windows is established by the output of the voltage controlled oscillator. The alignment flip-flop 131 provides an output signal to the single shot 133. The single shot 133 provides a load pulse to interrogate an error latch 134 and reset the counters 132 to start another cycle. A high frequency clock signal is provided to a high speed counter 135 during the interval initiated by the load pulse. The counter counts in a positive direction during the up window portion of the cycle and in a negative direction during the down window portion. The output of the counter 135 is provided to positive and negative comparators 136 and 137, respectively, at the end of the cycle. The comparators 136 and 137 determine whether the count held in the counter exceeds a predetermined positive or negative number. If either comparator 136 and 137 indicates that the count is too high or too low then an OR circuit 138 provides a signal to the error latch 134 which provides an error signal to an AND gate 139. The circuit so far described is provided for each selected track. The outputs from the error latches for each circuit are combined in AND gate 139 so that a final error latch 140 is set only when each of the selected tracks identifies an error condition. A positive output from the final error latch 140 indicates that an instantaneous speed variation has been encountered and cannot be reliably overcome by the read circuitry. A more detailed showing of the digital ISV detector is provided in Figs. 3A, 3B, 4A to 4E, and 5. Figures 6A and 6B show the key timing patterns used in the detector. To initiate operation of the detector circuitry an in record signal is generated by the record gating AND gate 82 which responds to a Coast and High Gain signal from the tape subsystem control unit. The output of AND gate 82 correspondingly generates a "not in record" through the NOT gate 84 or an "in record" signal as shown in Fig. 5. Only the "in record" signal is shown in Fig 6A as it is only when the tape subsystem is actively recording that it is necessary for the ISV detector circuit to be in its active state. When the tape head is over an inter-block gap area, the drive may stop and start and an indication of an instantaneous speed variation where the drive has properly stopped and restarted would clearly be erroneous. The "in record" signal resets the count up and count down window counter 86. In the example shown, the counter 86 counts to 128. During the first 64 steps of the counter 86 a set of counters 88 counts up in response to a high speed counter clock signal as described more fully hereinafter. During the last 64 steps of the counter 86, the set of counters 88 counts down. Synchronisation between the up/down window counter 86 and the set of counters 88 is provided through an alignment flip-flop 90 which receives as inputs the high speed counter clock signal and the output of the up/down window counter 86. After the output of the up/down window counter 86 goes up and the next successive upward pulse of the high speed counter clock signal is received, the counting up cycle of the set of counters 88 is initiated when the synchronisation signal from the alignment flip-flop 90 comes up. When the output of the up/down counter 86 comes down and a successive upward pulse of the high speed counter clock signal is received, the counting down cycle of the set of counters 88 is initiated when the synchronisation signal from the alignment flip-flop 90 comes down. The set of counters 88 stop counting when the voltage controlled oscillator signal, the sychronisation signal from the alignment flip-flop 90 and the high speed counter clock signal are all up. At this point, the count in the set of counters 88 is provided to the positive and negative comparators 92 and 94. In the present example, the positive comparator 92 is set to a reference value of +5 and the negative comparator 94 to a reference value of -5. These values have been selected because they are consis­ tent with the requirements of the particular system. Other designs may have higher or lower ISV tolerences and, therefore, more or less precise counting by the set of counters 88 may be required. Accordingly, any acceptable reference value could be placed in the comparators 92 and 94. In fact, in some instances, it may be desirable to put different absolute values in the positive and negative comparators 92 and 94 because, for example, an ISV which decreases the data rate may by more tolerable by the system than one that increases the data rate. Whenever the input from the set of counters 88 exceeds the pre-established threshold, in this example, +5 or -5, the output of the comparator 92 or 94 is high. The output of the positive and negative comparators 92 and 94 are provided through an OR gate 96 to an error latch 98. The error latch 98 is activated by the + load signal and a positive output from an "allow error" latch 100 so that the error latch 98 only provides an output indicating an error if the comparator 92 or 94 output exceeds the threshold at the time a counting cycle is completed. The detector circuitry so far described in Figures 3A, 3B, 4A to 4E and 5 is provided for each track on the tape which is to be sensed for ISV's. Any number of tracks may be selected for ISV sensing; however, there is a trade-off to be made between the cost of providing circuitry for each selected track and the need to select a sufficient number of tracks to ensure that ISV's are isolated from other errors which may be encountered. In the embodiment shown in Fig. 3C, three tracks have been selected. The outputs from the error latches 98 of each track circuit are combined in an AND gate 102. The AND gate 102 provides an output indicative of an error condition only when all three error latches 98 indicate an error condition. The tracks selected on the multiple track tape are sufficiently separate that the only condition that could affect all three tracks would be a condition affecting all of the tracks on the tape. The only case where such a condition would not be sensed by the normal error sensing and correcting circuitry of the tape drive would occur when the condition was created by an instantaneous speed variation or a transitory speed change of extremely short duration, or an oscillatory condition within the drive. Accordingly, the output from the AND gate 102 indicates a condition which may not be detected by the normal error sensing and correcting circuitry and may be unreadable during subsequent operations. The output of the AND gate 102 is provided to a final error latch 104 which, when latched, will provide a signal indicating that the entire record of data should be considered in error and be subsequently rerecorded. An analogue implementation of the ISV detection circuitry is shown schematically in Fig. 7. As with the digital implementation, a predetermined number of tracks across the width of the tape are selected. In the particular design, the data signal from each track is provided to a phase detector 110 which establishes a phase output signal representative of the phase difference between the received data signal and an output of a voltage controlled oscillator (VCO) 112. The phase difference signal is provided through a filter 114 as an input to the VCO 112 to alter the output of the VCO 112 so that it maintains phase with the data. The output of the filter 114 is also provided to a summing amplifier 116 for those tracks which have been selected to provide an indication of an instantaneous speed variation. The phase difference signal between the received data signal and the VCO output signal is a clear indicator of the amount of speed change during the detected data interval. The phase difference signals from each selected track are provided to the summing amplifier 116 which provides an output representative of the sum of the phase deviation detected on all selected tracks. The output of the summing amplifier 116 is fed through a differentiator 118 and filter 120 to a signal comparator 122. The comparator 122 is provided with a preset threshold input which determines the amount of phase deviation which can be accepted without indicating an error condition as a result of an instantaneous speed variation. Whenever the output from the summing amplifier 116 to the comparator 122 exceeds the predetermined threshold the comparator provides an output indicating an error condition caused by an instan­ taneous speed variation and requiring that the recorded data be rewritten. Although the analogue design has some advantages of economy with respect to the digital design it does have some technical disadvantages. For example, it is possible to identify an ISV situation where one track indicates a substantial phase error even though other tracks do not have such an error since the outputs of all selected tracks are summed together. This would only occur in the very unlikely case where the phase deviation in one track is extremely large. With the digital design this is not possible because each track must provide a positive indication of an error condition to the AND circuit. Consequently, the digital design will only provide an error signal when an ISV condition exists whereas the analogue design may respond with an error signal where the condition is created by some source other than an ISV.

Claims: 1. Date recording apparatus in which, in use, data is written in a medium by a recording head as the medium moves at speed past the head, including a monitoring arrangement for detecting unacceptable data recording density variations on said medium caused by short-term speed variations of the recording medium during the writing process of the data, said monitoring arrangement comprising clock means (112) operable during data read mode to generate a clock signal waveform locked to the data rate of the data as it is read from the medium, first counter means (86; 132) for repetitively accumulating successive groups of a predetermined number of clock signals from said waveform, timing means (88; 135) for deriving for each group of clock signals a value representative of the time of duration of that group, comparing means (88, 135) for comparing the time of duration of successive groups, and error means (136, 137, 138) for detecting time differences between successive groups in excess of a predetermined value selected as indicative of said unacceptable data recording density variations and generating an error signal identified with the portion of the recorded data from which the successive groups leading to the error signal were derived. 2. Data recording apparatus as claimed in claim 1, in which said timing means comprises a second counter means arranged during operation to count regularly occurring clock pulses supplied thereto and having a frequency considerably in excess of the nominal repetition rate of said clock signal waveform, means for enabling said second counter means to count said clock pulses, for the period of accumulation of a group of signals by said first counter means, whereby the number of clock signals counted by said second clock means is representative of the time of duration of that group. 3. Data recording apparatus as claimed in claim 2, in which said second counter means comprises a bi-directional counter arranged to count in one direction for the period of accumulation of one group of signals by said first counter means and to count in the other direction for the period of accumulation of the next successive group of signals whereby any residual count value in said bi-directional counter is representative of the difference between the time of duration of the two successive groups. 4. Data recording apparatus as claimed in claim 3, in which said error means includes a comparator for separately comparing any said residual error from said second counter with a positive and a negative version of said predetermined value and to generate on an output thereof an error as aforesaid when the residual count is positive and exceeds the positive predetermined value or is negative and exceeds the negative predetermined value. 5. Data recording apparatus in which, in use, data is written in a plurality of parallel tracks on a medium by an equal plurality of recording heads as the medium moves at speed past the heads, characterised in that an individual monitoring arrangement each as aforesaid is provided simultaneously to monitor the data from each track, the error outputs therefrom being logically combined to produce a further error output signal only when like errors occur simultaneously on all tracks. 6. A method for use in the detection of unacceptable data recording densities on a pre-recorded record medium due to speed variations of the record medium during the recording process, comprising the steps of: reading the pre-recorded data from said moving record medium; generating therefrom a signal waveform locked to the data rate of the pre-recorded data as it is read from the medium; deriving a value representative of the difference between a first average rate of pulses in said signal waveform over a first period and a second average rate of pulses in said signal waveform over a second period; and producing an error signal in the event that the magnitude of said value exceeds a predetermined value.

Inventors: BLANCO, ALFRED WARREN, MCDOWELL, JUDSON ALLEN, YEARY, DAVID ANGELUS
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: G11B15
IPC codes: G11B5, G11B15, G11B20