SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING SAME BY ION IMPLANTATION

Abstract: A method of manufacturing semiconductor devices by ion implantation, comprising the steps of, i) implanting P ions and ions selected from Si or Group II elements to the same region of GaAs or AlGaAs material, ii) performing a heat treat­ ment to said ion implanted region for activation. Also dis­ closed are semiconductor devices manufactured according to this method.

Description: The present invention relates to semiconductor devices and to a manufacturing method of semiconductor devices that makes use of semiconductor compounds of Group III-V elements, such as GaAs, and in particular, to an improvement in the process of forming a p- or n-type ion implanted layer. Because of their large electron mobility, semiconductor compounds of Group III-V elements such as GaAs have been investigated for their application to electronic devices that are operated at high speed. In such devices, there is required an especially high degree of controllability so that the ion implantation method is now being adopted almost exclusively in place of Zn diffusion method that has been used widely in the past. For instance, in the manufacture of HBT (Hetero-junction Bipolar Transistor), ion implantation of p-type impurities is performed in the process of formation of a high concentration external base layer for taking out a base electrode. In this case, as a kind of ion for the p-type impurities, use is made of beryllium (Be) or magnesium (Mg) which possess a relatively large projection range. However, one technical problem associated with this existing technique is that it is difficult to form a high concentration p-type layer by means of the ion implantation method. Fig. 1 illustrates the relationship between the sheet carrier concentration and the amount of ions implanted for a p-type layer which is obtained by implanting Mg in a semi-insulating GaAs substrate with an accelerating energy of 180 KeV, and by applying a heat treatment by irradiation with a halogen lamp, while suppressing dissociation of As by covering the surface with an SiO₂ film obtained by CVD (Chemical Vapor Deposition) method. Starting with the implanted amount that exceeds 2 x 10¹⁴ atoms/cm², the proportionality between the sheet carrier concentration and the implanted amount begins to deteriorate, and the sheet carrier concentration reaches only the low level of 3 x 10¹⁴/cm² at the implanted amount of 2 x 10¹⁵ atoms/cm². This means that only 15% of the implanted Mg is acting as acceptors. Fig. 2 shows the distribution of the carrier concentration (solid line) for the implantation of 2 x 10¹⁵ atoms/cm². According to the curve determined by the LSS theory, which is represented by a broken line, the peak carrier concentration should reach 1 x 10²⁰/cm³. The measured carrier concentration, however, remains at 5 x 10¹⁸/cm³. This figure also shows an enormous diffusion that was occurred during the heat treatment. This diffusion also means that the amount of activated Mg as acceptors is relatively small in quantity. As for the cause of the low rate of activation of Mg, it is necessary to consider the deviation from the stoichiometric composition of GaAs. In order for Mg to act as an acceptor in GaAs, it is necessary to infiltrate into the Ga lattice site and combine with As. In a GaAs crystal, the density of Ga atom is 2. 2 x 10²²/cm³ so that when Mg is implanted to a concentration of about 1x10²⁰/cm³ as shown in Fig. 2, it becomes necessary for all of the Mg atoms to activate as acceptors, either by the shift of about 1% of Ga atoms to interlattice positions or by the diffusion into the SiO₂ film formed on the surface. However, these changes do not occur to a sufficient extent under usual conditions. There are some problems in the implanting of Be or Silicon (Si). Though Si infiltrates into the Ga site in the same way as Mg or Be, it behaves as a donor in the GaAs material. There have also been investigations concerning the implanting of As, which is a compositional element of the GaAs substrate, together with Zn or Si to improve the carrier concentration and/or diffusion. For example, Japanese Journal of Applied Physics, vol. 22, No. 6, Part 2, June 1983, pages L373-L375 describes implantation of Zn and As. This method, however, is not preferable because of the damages caused by As ion implanation. As has the atomic number 33, which is large compared with 4 of Be, 12 of Mg or 14 of Si. Therefore, the energy of implanting As becomes enormous if attempts are made to obtain a project range comparable with that for Be, Mg or Si. The carrier concentration is limited due to the damage. Therefore, ion implanation using As is not suitable. Besides, in United States Patent No. 4,383,869, there is described P or Ar implantation for enhancing the activation of Si decreasing the concentration of Cr in a semi-insulating GaAs. Accordingly, an object of the present invention is to provide an improved method of manufacturing semiconductor devices by ion implantation. Another object of the invention resides in providing such a process which makes it possible to form a p- or n-type region that has a sufficiently high carrier concentration together with a lowered diffusion in a GaAs or AlGaAs material. It is also an object of the invention to provide improved semiconductor devices. In accomplishing the foregoing objects, there is provided according to this invention a method of manufacturing semiconductor devices by ion implantation, comprising the steps of: i) implanting phosphorous ions and ions of Group II elements to the same region of GaAs or AlGaAs material; and ii) performing heat treatment to said ion implanted region for activation. According to another aspect of this invention there is provided an improved semiconductor device, comprising: a structure of an n-type GaAs collector layer, a p-type GaAs base layer and an n-type AlGaAs emitter layer stacked upon each other in the recited order; and a p-type external base region formed in a predetermined region of said structure, and having phosphorous and impurities selected from Group II elements and extending in depth from said n-type AlGaAs emitter layer to said n-type GaAs collector layer. This invention, together with its various features and advantages, will be readily understood from the following more detailed description presented in conjunction with the following drawings, in which :- Fig. 1 is a diagram showing the sheet carrier concentration when Mg is implanted in a GaAs substrate; Fig. 2 is a diagram showing the distribution of the carrier concentration for the same case as in Fig. 1; Fig. 3 is a diagram showing the relationship between the amount of Mg implanted in GaAs substrate and the sheet carrier concentration, Mg being implanted together with P in accordance with the present invention; Fig. 4 is a diagram showing the distribution of carrier concentration corresponding to the Fig. 3; Fig. 5 is a diagram showing the preferable range of the amount of P to the Mg; Fig. 6 is a diagram for showing the case in which an AlGaAs substrate is employed; Figs. 7a through 7e schematically illustrate the manufacturing process for an HBT to which the present invention is applied; Fig. 8a is a diagram showing the relationship between the emitter circumference length/emitter area, and the current amplification factor β for the same device in Fig. 7; and Fig. 8b shows the parts of an HBT. According to the invention phosphorus (P) ions that are inactive but are not the compositional elements of a GaAs or AlGaAs material are implanted together with ions of Group II elements. Prior to the description of the method applied to the actual manufacture of the device, certain experimental results will be considered as follows. Fig. 3 shows the relationship (solid-line) between the implanted amount of Mg and the sheet carrier concentration of the p-type layer obtained, when equal amounts of Mg and P are ion implanted (P ion implantation was followed by Mg implantation) in a semi-insulating GaAs substrate under the implanting energy of 180 KeV. The project range Rp is about 0.18 µm for Mg⁺, and 0.15 µm for P⁺. Also shown in the figure is the result for a prior method (broken line) in which no implantation of P is carried out. The heat treatment of these samples after the ion implantation was carried out by covering the surface with a CVD SiO₂ film and heating them to 85°C for 2 seconds with a halogen lamp. In contrast to the tendency of saturation in the carrier concentration that is seen for the implanted amount of Mg that exceeds 2x10¹⁴ atoms/cm² in the previous method, according to the present method, the impurity activation factor showed a value as high as 70% even for a high implanted amount of 2 x 10¹⁵ atoms/cm². This sheet carrier concentration realizes a value about five times as large compared with the case of the previous method. Further, the distribution of the carrier concentration for the present case is shown in Fig. 4 as a solid line. Due to the simultaneous implantation of P ions, as a result of suppression of abnormal diffusion of Mg caused by the insufficiency of an element of Group V, there is obtained a steep distribution of carrier concentration compared with the previous method, with a peak concentration that reaches 7 x 10¹⁹cm³. Also included in Fig. 4 are the results due to the LSS theory (shown in broken lines) for Mg and P at an implanting energy of 180 KeV. It will be understood that the implanted regions of P and Mg are piled upon each other in the GaAs substrate. It also can be understood that the peak concentration of each impurity was about 1x10²⁰ atoms/cm³ at the implanting step. In the investigated embodiments, the sheet carrier concentration was measured by the Pauw method, which makes use of the hall effect. As for the distribution of carrier concentration, the measurements were performed as follows. After performing the slight etchings for the surface of the ion implanted region and the sheet carrier concentration measurements described above, alternatively, the volume concentration of each of the carriers was caluclated for each etching step by dividing the amount of the change of the sheet carrier concentration by the etching depth as shown in Fig. 4 (solid line). Calculations of the implanted amount were carried out by multiplying the ion current density by ion implanting period according to the conventional method. Fig. 5 shows the relationship between the amount of P implanted into the semi-insulative GaAs and the sheet carrier concentration, at a Mg level of 2 x 10¹⁵ atoms/cm². The broken line shows the case in which Mg only is implanted into the substrate. In each case, the implanting energy was 180 KeV. The maximum carrier concentration was obtained when the implanted amount of P equals the Mg level. At an implanted amount of 2 x 10¹⁵ atoms/cm² for each, the sheet carrier concentration reached 1.4 x 10¹⁵/cm². The preferred ratio of the implanted amount of P to Mg atoms is between about 1:10 and 10:1, especially between about 1:2 and 2:1. Fig. 6 is a diagram showing the effect of implanting Mg and P ions into semi-insulative Al 0.3 Ga 0.7 As substrate with an implanted amount of 2 x 10¹⁵ atoms/cm² for each type of ion, at 180 KeV. As a comparison, the cases of (1) implanting Mg alone and (2) using a GaAs substrate are also shown. According to the experiments, it will be understood that the present method supplies an almost equivalent carrier concentration to the AlGaAs substrate as in the case of GaAs. Fig. 7a to Fig. 7e illustrate cross-sectional structures showing the manufacturing steps for an HBT, to which the present invention is applied. First of all, as shown in Fig. 7a, onto the semi-insulating GaAs substrate 1, an n⁺ -GaAs layer 2 of impurity concentration of 2 x 10¹⁸ atoms/cm³ and thickness of 5 x 10⁻⁷m (5000 Å) was grown. Furthermore, an n-GaAs layer 3 of 5 x 10¹⁶ atoms/cm³ and 5 x 10⁻⁷m (5000 Å), a p⁺-GaAs layer 4 of 1 x 10¹⁹ atoms/cm³ and 1 x 10⁻⁷m (1000 Å), an n-AlGaAs layer 5 of 5 x 10¹⁷ atoms/cm³ and 2 x 15 -7m (2000 Å), and an n⁺-GaAs layer 6 of 5 x 10¹⁸ atoms/cm³ and 1 x 10⁻⁷m (1000 Å) were also grown onto it. As for the method of growth of each layer, MBE (Molecular Beam Epitaxy) was used. During the growth of each layer by means of the MBE method, Be or Si was introduced as acceptor or donor impurities at the predetermined concentration shown above. A 8 x 10⁻⁷m (8000 Å) layer of CVD SiO₂ film 7 was then deposited on the surface, and wet etching to the n⁺-GaAs layer 6 was performed for forming a contact mesa of an emitter using the CVD SiO₂ film 7 as an etching mark. Next, P ion implanation in the amount of 2 x 10¹⁵ atoms/cm² at 190 KeV, and then Mg ion implanation of 2 x 10¹⁵ atoms/cm² at 150 KeV to the region for making an external base region for taking out an electrode were performed. Fig. 7b. After removing the CVD SiO₂ film 7, the sample was covered with a 1.5x10⁻⁷m (1500 Å) film of CVD SiO₂ 8 and was annealed with a halogen lamp at 850°C for 2 seconds. Due to this annealing, the high concentration p-layer 9 was made at the ion implanted region, as shown in Fig. 7c. After that step, Boron (B) ions were implanted with 7 x 10¹² atoms/cm² at 150 KeV. And hydrogen (H) ions were implanted in the amount of 5 x 10¹⁴ atoms/cm² at 190 KeV. By these implantations, as shown in Fig. 7d, isolation regions 10, 11 were formed. Then, predetermined surface portions were removed by wet etching, and on these portions, AuZn alloy electrode 12 and AuGeNi alloy electrodes 13, 14 were formed. Fig. 7e shows a collector region 3, an inner base region 4, an external base region 9, an emitter region 5 and an external emitter region 6. Further, there is shown a base electrode 12, an emitter electrode 13, a collector electrode 14, respectively. According to this embodiment, the external base region 9 is formed at a high carrier concentration so that the sheet resistivity of the base region 9 is lowered. Also, the resistivity of the ohmic contact of the base electrode 12 is also lowered. In the embodiment described above, the emitter region 5 is surrounded by the external base region 9 and is buried in the substrate, and has substantially the same outline compared with that of the inner base region 4. Fig. 8a shows the relationship observed between the ratio of the emitter circumference length/emitter area and the current amplification factor β of the HBT. The solid line shows the device in Fig. 7, and on the other hand, the broken line shows the case of implanting Mg alone. Upon decreasing the emitter size so that the ratio reaches 0.4 (area is 10 x 10 µm²), the current amplification factor β of the previous method drops to 20 rapidly. But for the present method, the decrease is at a much lower rate. An HBT has the feature that the undesirable injection of holes from the base region to the emitter can be effectively prevented because the p-n junction coincides with the hetero junction consisting of GaAs 4 and AlGaAs 5, and this improves the factor β to a high degree. Therefore, the rapid lowering of the β in the previous method is thought to be a shift of the p-n junction from the boundary of the hetero junction, due to the occurrence of an abnormal Mg diffusion at the corner of the bottom of the emitter region 5 toward the center of emitter region 5, this influence becoming remarkable as the device size decreases. (Fig. 8b) In the embodiments described in Fig. 3 to Fig. 8, Mg is used as the acceptor. However, Be can be used instead of Mg. Other acceptors selected from Group II elements (including IIa) such as Zn may be used, if desired. Two types of acceptors also may be used in combination. An AlGaAs substrate can be used with Mg ions implanted into the source and drain regions, for a p-channel MESFET. Heat treatment for activation of implanted ions may be performed before the formation of contact electrodes 12, 29 and 30. Alternatively, this heat treatment may be performed after forming the electrodes. In each of the embodiments, the P ion implantation step was followed by another ion implantation, such as Mg ion implantation, and then the heat treatment was performed. However, it can be done by reversing the order of the two implanting steps. Furthermore, these implanting steps can be done at the same time. For achieving a relatively high carrier concentration, it is preferable to implant ions of Group II elements with the implanted amount being more than 1 x 10¹⁴ atoms/cm², and with the peak concentration in the distribution being more than 1 x 10¹⁹ atoms/cm³ at the ion implanting step. The preferred ratio of the implanted amount of atoms for P ions to the ions of Group II elements is between about 1:10 and 10:1, especially between about 1:2 and 2:1. As for the covering film, CVD SiO₂ film (for example, 8 in Fig, 7) was used. However, this may be replaced by other deposited insulating films such as PSG, SiN, SiON or AlN. And as for the heat treatment, it may be performed at 700 - 1100°C, and heating by firing can also be used instead of the halogen lamp.

Claims: A method of manufacturing semiconductor devices by ion implanation, comprising the steps of: i) implanting phosphorous ions and ions of Group II elements to the same region of a GaAs or AlGaAs material; and ii) performing a heat treatment of said ion implanted region for activation. A method of manufacturing semiconductor devices by ion implanation according to claim 1, wherein phosphorous and Be or Mg are implated for forming a p-type region. A method of manufacturing semiconductor devices by ion implanation according to claim 1, wherein the implanted amount of ions of Group II elements is more than 1 x 10¹⁴ atoms/cm². A method of manufacturing semiconductor devices by ion implanation according to claim 1, wherein the peak concentration of implanted ions of Group II elements in said step i) is more than 1 x 10¹⁹ atoms/cm³. A method of manufacturing semiconductor devices by ion implantation according to claim 1, wherein the ratio of the implanted amount of atoms for phosphorus ions to the ions of Group II elements is between 1:10 and 10:1. A method of manufacturing semiconductor devices by ion implantation according to claim 1, wherein the ratio of the implanted amount of atoms for phosphorous ions to the ions of Group II elements is between 1:2 and 2:1. A method of manufacturing semiconductor devices by ion implantation according to claim 1, further comprising the step of depositing an insulating film on the GaAs or AlGaAs material before said heat treatment is performed. A method of manufacturing semiconductor devices by ion implantation according to claim 7, wherein said insulating film is selected from SiO₂, PSG, SiN, SiON and AlN. A method of manufacturing semiconductor devices by ion implantation according to claim 1, wherein said ion implantation is performed for a region comprising an external base region of a bipolar transistor. A method of manufacturing semiconductor devices by ion implantation according to claim 1, wherein said implantation is performed to source and drain regions of a MESFET. A method of manufacturing semiconductor devices by ion implantation according to claim 10, wherein said ion implantation regions are formed as self-aligned regions to a gate electrode. A method of manufacturing semiconductor devices by ion implantation, comprising the steps of: i) forming a structure of an n-type GaAs collector layer, a p-type GaAs base layer and an n-type AlGaAs emitter layer stacked upon each other in the recited order; ii) implanting phosphorous ions and ions selected from Group II elements to a predetermined region extending in depth from said n-type AlGaAs emitter layer to said n-type GaAs collector layer, to form an external base region; and iii) performing a heat treatment of said ion implanted region for activation. A method of manufacturing semiconductor devices by ion implantation according to claim 12, wherein said ions selected from Group II elements are Mg or Be ions. A method of manufacturing semiconductor devices by ion implantation according to claim 12, further comprising the step of forming said stacked structure in step i) on a semi-insulative GaAs substrate. A method of manufacturing semiconductor devices by ion implantation according to claim 12, further comprising the step of forming a mask on said stacked structure after step i), and wherein said ion implanting step is performed using said mask as an implanting mask. A method of manufaturing semiconductor devices by ion implantation according to claim 15, further comprising the step of forming a high concentration n-type external emitter layer on said stacked structure before forming said mask, and subsequently patterning said external emitter layer using said mask as an etching mask. A method of manufacturing semiconductor devices by ion implantation according to claim 12, wherein said external base region is formed in order to surround said emitter layer. A method of manufacturing semiconductor devices by ion implantation according to claim 12, further comprising the step of forming an ohmic contact electrode on said external base region after step i). A method of manufacturing semiconductor devices by ion implantation according to claim 12, wherein the implanted amount of ions selected from Group II elements is more than 1 x 10¹⁴ atoms/cm². A method of manufacturing semiconductor devices by ion implantation according to claim 12, wherein the peak concentration of implanted ions selected from Group II elements in said step ii) is more than 1 x 10¹⁹ atoms/cm³. A method of manufacturing semiconductor devices by ion implantation according to claim 12, wherein the ratio of the implanted amount of atoms for phosphorous ions to the ions selected from Group II elements is between 1:10 and 10:1. A method of manufacturing semiconductor devices by ion implantation according to claim, 12, wherein the ratio of the implanted amount of atoms for phosphorous ions to the ions selected from Group II elements is between 1:2 and 2:1. A method of manufacturing semiconductor devices by ion implantation according to claim 12, further comprising the step of depositing an insulating film on said stacked structure between steps i) and ii). A method of manufacturing semiconductor devices by ion implantation according to claim 23, wherein said insulating film is selected from SiO₂, PSG, SiON and AlN. A method of manufacturing semiconductor devices by ion implantation according to claim 1 or claims 12, wherein said heat treatment is performed by exposure to a lamp or by firing. A method of manufacturing semiconductor devices by ion implantation according to claim 1 or claim 14, wherein said heat treatment is performed at a temperature of from 700 - 1100°C. A method of manufacturing semiconductor devices by ion implantation according to claim 12, wherein said each layer is formed by the MBE method. A semiconductor device, comprising: a structure of an n-type GaAs collector layer, a p-type GaAs base layer and an n-type AlGaAs emitter layer stacked upon each other in the recited order; and a p-type external base region formed in a predetermined region of said structure, containing phosphorous and impurities selected from Group II elements and extending in depth from said n-type AlGaAs emitter layer to said n-type GaAs collector layer. A semiconductor device according to claim 28, wherein said impurities selected from Group II elements comprise Mg or Be atoms. A semiconductor device according to claim 28, wherein said structure is formed on a semi-insulative GaAs substrate. A semiconductor device according to claim 28, wherein said external base region surrounds said emitter layer. A semiconductor device according to claim 28, further comprising an ohmic contact electrode formed on said external base region. A semiconductor device according to claim 28, wherein the amount of impurities selected from Group II elements is more than 1 x 10¹⁴ atoms/cm². A semiconductor device according to claim 28, wherein the peak concentration of said impurities selected from Group II elements is more than 1 x 10¹⁹ atoms/cm³. A semiconductor device according to claim 28, wherein the ratio of the amount of phosphorous atoms to the impurities selected from Group II elements is between 1:10 and 10:1. A semiconductor device according to claim 28, wherein the ratio of the amount of phosphorous atoms to the impurities selected from Group II elements is between 1:2 and 2:1.

Inventors: MORIZUKA, KOUHEI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L21
IPC codes: H01L29, H01L21