Apparatus for interpolating image signals

Abstract: An apparatus for interpolating image signals in an image processing unit for receiving image data of original pixeles to store the same in image data memory means thereby to output said image data in a designated magnification, said apparatus comprising: clock generating means for generating second clocks by regularly defaulting clocks from an array of periodic first clocks on the basis of a prescribed rule in compliance with said magnification, read means for reading said image data stored in said image data memory means on the basis of said first clocks when said magnification is for enlargement, said reading being performed on the basis of said second clocks; interpolation data generating means for interpolating said image data as read to generate at least one interpolation data; and interpolation data assigning means for selectively assigning said interpolation data to additional pixels added by said default of said clocks on the basis of selection data previously set in correspondence to said prescribed rule.

Description: Field of the Invention The present invention relates to an apparatus for interpolating image signals, and more particularly, it relates to an apparatus for interpolating image signals in processing of input and output images which are different in number of pixels. Description of the Prior Art In order to, for example, enlarge or reduce images, it is necessary to output the images in a different number of pixels from that of input images. Generally well known is technique of varying magnifications of images for an image processing device such as a process scanner, a laser printer, a facsimile or the like which temporarily stores image data in a memory having storage capacity for, e.g., one scanning line while relatively varying pixel clocks (or memory addresses) for writing and reading the image data in and from the memory with target magnifications thereby to increase or decrease the number of pixels. Examples of such technique are as follows: A first system employs a frequency dividing circuit included in a PLL circuit, the frequencey dividing ratio of which is varied to change pixel clock frequencies in writing and reading operations as disclosed in, e.g., Japanese Patent Publication Gazette No. 50561/1977. Although such a method substantially has no problem in a low frequency range, the PLL circuit is complicated in stucture and a high-speed processing circuit (device) is required in order to obtain outputs of a highly enlarged magnification value in an apparatus requiring processing in a high frequencey range, whereby the cost is inevitably increased. In a second system, pixel clocks are employed in such a manner that additional pulses are inserted between ordinary periodic pixel clocks, i.e., synchronous pulse trains, as disclosed in, e.g., Japanese Patent Laying-Open Gazette No. 11601/1978. Such pixel clocks are adapted to designate addresses for writing in a memory while the original pixel clocks are adapted to designate addresses for reading from the memory, whereby reproduced pixels in the pattern of an original are increased in number in comparison with the pixels read or sampled from the original to provide enlarged image outputs. On the other hand, the pixel clocks may be adapted to designate the addresses for reading, thereby to obtain reduced image outputs. In such a system, however, the additional pulses must be inserted between the pulse trains in predetermined periods, whereby designation of magnifications for varying the same is restricted to, e.g., a range of 50 to 200% in the embodiment as disclosed in the Japanese Patent Laying-Open Gazette No. 11601/1978. Further, the magnification settable intervals are restricted to (n + 1)/n x 100% (n: integer), i.e., 1/2, 2/3,... 1,... 3/2 and 2/1. A third system writes image data in a memory at a constant frequency (pixel clock) or sampling pitch to access the same with memory addresses which are partially omitted for reduction or duplicated for enlargement, thereby to decrease or increase the number of outputted pixels, as disclosed in, e.g., Japanese Patent Laying-Open Gazettes Nos. 65601/1979 and 35613/1979. According to such technique, distribution of the omitted or duplicated addresses is averaged to considerably reduce uneveness of outputted images in reduction or enlargement , whereas the circuit structure for such averaging is complicated. Such a tendency is spurred by increase in the range of magnifications. In the conventional magnification varying systems, thus, it has been difficult to obtain images in which additional pixels are evenly distributed in a wide magnification range with relatively simple circuit structure. Further, the output operation is performed only through the pixel data written in the memory in each of the aforementioned systems, and hence continuous pixels in specific gradation are unexpectedly followed by those in different gradation when identical pixel data are repeated in a reproduced image in enlargement, whereby space gradation in the reproduced image cannot be smoothly changed. An apparatus for interpolating image signals according to the preamble of claim 1 is known from US-A-4 153 896. An object of the present invention is to provide an apparatus for interpolating image signals, which apparatus can readily obtain an output image of smooth picture quality with simple structure when input pixels are different in number from output pixels, particularly when the output pixels are larger in number than the input pixels. A second object of the present invention is to provide an apparatus for interpolating image signals, which apparatus can obtain output image data with additional pixels evenly distributed in a wide magnification varying range from input image data picked up at constant sampling pitches regardless of magnification values as well as a natural image with space gradation smoothly changed in a reproduced image in enlargement processing. The invention is as defined in claim 1. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings, in which : Fig. 1 is a schematic diagram showing a first embodiment of the present invention; Fig. 2 is a detailed illustration of a technical example related to the first embodiment; Fig. 3 is a diagram showing the principle of producing data in a clock memory of the related technical example; Fig. 4 is a flow chart showing data producing processing in the clock memory of the related technical example; Fig. 5 is a timing chart showing the operation of the related technical example; Figs. 6 and 7 illustrate image data in enlargement processing; Fig. 8 is a detailed schematic diagram showing the first embodiment; Fig. 9 is a diagram showing the principle of interpolation in the first embodiment; Figs. 10A and 10B are a flow chart showing data producing processing in a clock memory of the first embodiment; and Fig. 11 is a timing chart showing the operation of the first embodiment as shown in Fig. 8. (A) Entire Structure of First Embodiment Description is now made on a first embodiment, in which interpolation processing according to the present invention is applied to image enlargement in an image processing apparatus which receives image data to store the same in memory means thereby to output the image data at a designated magnification value. Fig. 1 is a schematic diagram showing the first embodiment which is applied to a drum scanning type process color scanner 1, while the present invention is not restricted to such application, but is applicable also to a drum scanning type monochrome scanner, a flat bed scanning type process scanner and the like. In Fig. 1, arrows in double lines denote image signals and arrows in solid lines denote control pulses while those in dot lines denote control signals for a vertical scanning driving motor respectively. The color scanner 1 as shown in Fig. 1 is provided with an original drum 3 around which an original 2 is wound and recording drum 5 around which a photosensitive material 4 is wound. Both of the original and recording drums 3 and 5 are fixed to a drum shaft 6, which is synchronously rotated by driving force supplied from a motor 9 through a pulley 7 and a belt 8. In an opposite manner to the original drum 3 and the recording drum 5, a pickup head 10 and an exposure head 11 are arranged to be movable in parallel with the drum shaft 6, to be fed by feed screws 14 and 15 through driving force supplied from driving pulse motors 12 and 13 respectively. The pickup head 10 contains a color separation optical system and a plurality of photoelectric conversion elements etc. to read color tones and optical density of the original 2 thereby to generate color-separated image signals in the three primary colors. The color-separated image signals are subjected to arithmetic processing in a color and gradation correcting circuit 16 for correction of the color tones and gradtion, to be converted to image signals for recording. The converted signals are supplied to an A-D converter 17, which in turn samples the said signals in response to periodic pixel clocks CK1 from a timing control part 23 as hereinafter described, thereby to sequentially perform A-D conversion of the same. The image signals thus A-D converted are supplied to an image memory 18. In the apparatus according to the present invention, a desired reproduced image magnification value is previously designated in a magnification setting part 20, which can be formed by a CPU or combination of digital switches and a decoder. The image data are written in the image memory 18 in such a manner that a memory address generation part 19 generates address signals in response to the signals from the magnification setting part 20 in such modes as herein-after described to write the image data in addresses of the image memory 18. In a similar manner, the image data are read from the addresses of the image memory 18 designated by outputs from the memory address generation part 19, to be supplied to an interpolation arithmetic circuit 21 in a subsequent stage. The interpolation arithmetic circuit 21 is adapted to interpolate the read pixels in a mode as hereinafter described when the magnication is designated in an enlarged size, while supplying the said outputs to a halftone dot generator 22 with no such interpolation when the magnification is designated in an equal or reduced size. The halftone dot generator 22 compares the received image signals and reference halftone dot signals to generate halftone dot outputs, thereby to record or reproduce the image on the photosensitive material 4 through the exposure head 11. In synchronization with input pulses from a pulse generator PG which is synchronous with rotation of the drum shaft 6, the timing control part 23 generates the pixel clocks CK1, main scanning periodic clocks CK2 indicating initiation or completion of one main scanning operation and the control signals for the driving pulse motors 12 and 13, to supply the same to the respective parts as shown in Fig. 1. The remaining mechanical structure and the like are identical to those of a well-known facsimile etc. and deailed deacription thereof is omitted. (B) Related Technical Example In order to facilitate understanding of present invention, description is now made on a technical examle which closely related to the present invention. This technical example (not yet published) has been proposed by the inventor, to attain the aforementioned principal object of the present invention. (B-1) Structure of Related Technical Example The technical example is mainly different from the first embodiment of the present invention as shown in Fig. 1 in that no interpolation circuit 21 is provided and that memory address generation part 19 is in different structure. Fig. 2 is a block diagram showing memory address generation part 19a of the technical example in detail, while other components are shown in numerals identical to those in Fig. 1. The memory address generation part 19a as shown in Fig. 2 includes an address counter (progammable n-ary counter) 31 for receiving pixel clocks CK1 supplied from the timing control part 23 as shown in Fig. 1. The address counter 31 is previously supplied with a prescribed load value through a register 32 from a magnification setting part 20 which is formed by a CPU. Assuming that the magnification is set at n/m (n, m: integers), such a prescribed load value can be set in a number (m - 1) when the address counter 31 is a down counter, or in a number (2 k - m) when the address counter 31 is an up counter, k being the bit number of the address counter 31. Thus, the address counter 31 provides cyclic address outputs which return to the original address every time the pixel clock CK1 generates m pulses. The count outputs from the address counter 31 are supplied as address inputs to a clock memory 33. The clock memory 33 previously stores data of m words x 1 bit which are determined following a prescribed rule corresponding to the magnification as hereinafter described and are supplied from the magnification setting part 20, so that the data are read out word by word from accessed addresses to be supplied to an AND circuit 34. The AND circuit 34 gates the pixel clocks CKI by the outputs from the clock memory 33 thereby to generate clocks (second clocks) CK3 obtained by regularly omitting clock pulses from the clock pulse array of pixel clocks CK1. A selector 35 in a subsequent stage receives the pixel clocks CK1 and the second clocks CK3 to supply either the former or the latter to an address counter 36. Such selection is performed by outputs from an XOR circuit 39 which receives outputs from a flip-flop 37 for selecting writing and reading and outputs from a register 38 for selecting reduction and enlargement. The selector 35 selects the clocks CK3 for reading the image data from the image memory 18 in enlargement and for writing the same thereinto in reduction and the pixel clocks CK1 in other case. In other words, data on the input terminal A of the selector 35 is selected in case of S = 1 while data on the input terminal B is selected in case of S = 2 in Fig. 2 respectively. The flip-flop 37 receives main scanning periodic clocks CK2 while the register 38 receives inputs from the magnification setting part 20. The address counter 36 receives the clocks thus selected and counts the same to supply its address outputs to the image memory 18, which in turn writes or reads the image data in correspondence to the address outputs from the address counter 36. (B-2) Storage Contents of Clock Memory 33 Description is now made on data contents to be stored in the clock memory 33. The magnification setting part 20 operates the clock pulses to be omitted from those of the pixel clocks CK1 in response to the set magnification value as hereinafter described, so that the results of the operation are stored in the clock memory 33. In this technical example, the AND circuit 34 obtains logical products of the pixel clocks CK1 and the outputs from the clock memory 33 to default (m - n) clock pulses from m clock pulses, thereby to produce the clocks CK3. Therefore, it is required for the data to be stored in the clock memory 33 that (m - n) pulses in the interval for m pulses of the pixel clocks CK1 become "0" and the remaining n pulses become "1", and the n pulses of "1" are preferably distributed as averagely as possible. In the technical example, therefore, a plurality of continuous words are sequentially collected to multiply the number of the words by (n/m) to assign "1" to the last word of every value exceeding one word thereby to obtain average distribution. Such an idea is illustrated in Fig. 3. The abscissa in Fig. 3 shows bit order (I = 1, 2,...,m) of the data or the addresses in the clock memory 33 and the ordinate shows (n/m) x I in case of reduction at a ratio of 30% (n = 3, m = 10). As shown in Fig. 3, the value (n/m) x I is linearly increased with respect to I, to exceed the integers 1, 2 and 3 in the ordinate in positions where the value I reaches 4, 7 and 10 as shown by small white circles. Thus, when the value I is sequentially increased in consideration of a set of first to I-th words in this example, words which may become "1" newly appear respectively in points where I is equal to 4, 7 and 10, and hence the word DATA (I) corresponding to the said I values are set at "1". With respect to the whole data from I = 1 to I = m (10 in the shown example), n bits within the m bits are strictly "1" as obvious from the fact that the values (n/m) x I become n at I = m. In other words, the average distribution can be obtained in approximation of extremely high accuracy while strictly maintaining the designated magnification value. Fig. 4 is a flow chart illustrating procedure of producing the data to be stored in the clock memoryy 33 by the magnification setting part 20 in accordance to the said rule. The flow chart as shown in Fig. 4 is now described, also with reference to Fig. 3 illustrating relation between amounts "A" and "A1" in Fig. 4 and the value I. At a step S1, the value I is set as 1 and the amount A is set at zero, and at a subsequent step S2, the integer part of (n/m) x I is operated to be assigned to A1. Then, at a step S3, a determination is made on correspondence between A1 and A. For example, when I = 1 in the example as shown in Fig. 3, A1 = A = 0 and hence the process is advanced to a step S4, at which data DATA(I) to be assigned to an I-th word is set at "0". Then, at a step S6, the value I is increased by 1 and the value A is redefined by the current value A1, and the process is advanced to a step S7. When the value I is smaller than m, the process is returned to the step S2. Such operation is repeated on I = 1, 2 and 3 respectively in the example as shown in Fig. 3, while it is assumed here that the value I becomes 4 thereafter. Then, A1 becomes "1" at the step S2 (refer to A1 corresponding to I = 4 in Fig. 3), and hence A1 ≠ A at the step S3, whereby the process is advanced to the step S5 to set the data DATA(I) at "1". Then, the value A is set at A1 (= 1) at the step S6. In a subsequent processing loop (I = 5), A1 = A (= 1), and hence the data DATA(I) again becomes "0". The data DATA(I) for the respective values I are defined in such a manner, and the. data production is completed when I > m. As illustrated in Fig. 3, through the fact that A1 indicating the integer part of (n/m) x I and A following A1 in delay by 1 word are discrepant only in points where A1 is changed, the data DATA(I) is set at "1" with respect to the value I with the said discrepancy in the processing as shown in Fig. 4. It may be understood from Fig. 3 that such discrepance appears in the positions shown by the small white circles on the graph of (n/m) x I as shown in Fig. 3. Table 1 shows the data to be stored in the clock memory 33 obtained on the basis of the aforementioned rule. For example, the column of the magnification at the ratio of 30% (m = 10, n =3) shows the data as shown in the lower part of Fig. 3 (begins from "1" in Table 1, for convenience of illustration). Although the above description has been made on the case of reduction, such reduction is only different from enlargement as to whether the clocks CK3 obtained on the basis of the data are employed for writing in the image memory 19 or reading from the same, and hence the same data contents may be employed in a corresponding manner. For such reason, the data on reduction at a ratio of n/m are identical to those on enlargement at a ratio of m/n in Table 1. (B-3) Operation of Related Technical Example With reference to a timing chart shown in Fig. 5, the operation of this technical example will be described particularly on portions characterizing this example. In Fig. 5, the operation is performed on the values m = 3 and n = 2, i.e., enlargement at a ratio of 150% in magnification and reduction at a ratio of 66% in magnification. Enlargement at 150% Operation for enlargement at the ratio of 150% is now described. In advance to receiving an image, the magnification value (150%) is set by the magnification setting part 20. Then the magnification setting part 20 performs arithmetic to obtain the data of m (= 3) words x 1 bit to be stored in the clock memory 33 in accordance with the flow chart as shown in Fig. 4, to store the same in the clock memory 33. The magnification setting part 20 simultaneously loads the value of m in the address counter 31 through the register 32 while supplying signals to the register 38 to place the same in a state indicating "enlargement". Upon initiation of reading the original 2, the main scanning periodic clocks CK2 are supplied so that the flip-flop 37 enters a state indicating "writing" and the address counter 36 is cleared. Then, the pixel clocks Ck1 from the timing control part 23 (Fig. 1) are periodically supplied as shown at Fig. 5(a). The address counter 31 counts the pixel clocks CK1 to output address signals which are increased or decreased pulse by pulse and cycle per m pulses of the pixel clocks CK1. The clock memory 33 receives the outputs as address inputs, to sequentially read out the aforementioned data (see Fig. 5(b)) stored therein. The AND circuit 34 receives the data to gate the pixel clocks CK1 by the same thereby to generate the clocks CK3 obtained by regularly omitting the pulses of the pixel clocks CK1, as shown at Fig. 5(c). On the other hand, the output from the register 37 is "1" (writing) and the output from the register 38 is "0" (enlargement) at this time, and hence the XOR circuit 39 outputs "1". As hereinabove described, the selector 35 selects the A inputs with respect to S = 1, and hence the address counter 36 receives the pixel clocks CK1 in this case. Thus, the address counter 36 generates address outputs (see Fig. 5(d)) corresponding to the periodic pixel clocks CK1 to supply the same to the image memory 18. Therefore, the image memory 18 stores all the original pixel data received in this apparatus with no omission for the writing operation. Now considered is the reading operation for the enlargement, which is different from the aforementioned writing operation in the following points: The flip-flop 37 is placed in a "0" (reading) state by the main scanning periodic clocks CK2. Then the XOR circuit 39 outputs "0", whereby the B inputs, i.e., the clocks CK3 are selected by the selector 35. thus, the address counter 36 receives pulses in the form as shown at Fig. 5(c), to continuously access the same addresses in positions the pulses are omitted from the clocks CK3, as shown at Fig. 5(e). In the operation for reading the image data from the image memory 18, a plurality of continuous pixels having the same contents are followed by subsequent pixels, thereby to reproduce the image in enlarged form. Reduction at 66% The operation for reduction is performed in an inverse manner to the above operation for enlargement. In other words, the register 38 indicates "1" (reduction) and hence the selector 35 selects the clocks CK3 for writing and the pixel clocks CK1 for reading respectively. Thus, address signals corresponding to the clocks CK3 are generated in writing as shown at Fig. 5(f), so that the image data are recorded along the main scanning direction on the original with the pixels reduced in processing. The image data are read by the pixel clocks CK1 in reading, thereby to provide a reduced reproduced image. Thus, the clock pulses are so omitted that the pixels are increased in enlargement and decreased in reduction. (B-4) Advantages and Disadvantages of the Related Technical Example According to the aforementioned technical example, the values n and m can be arbitrarily set to enable image processing in a wide variable range of magnifications with simple circuit structure. Further, unevenness of the reproduced image is reduced by the average distribution of the omitted pulses as hereinabove described. Thus, the technical example attains the principal object of the present invention. However,the increase in the pixel data causes problems in the reproduced image in enlargement. For example, image data as shown at Fig. 6(b) are obtained by applying the aforementioned enlargement (250%) to original data as shown at Fig. 6(a), whereas gradation changes are partially inverted as shown at Fig. 6(c) by application of processing for enhancing sharpness. Further, when the enlargement is performed on an original having gradation boundary lines slanted in directions different from both of main and vertical scanning directions as shown at Fig. 7(a), the reproduced gradation boundary lines are inevitably stepped as shown at Fig. 7(b). (c) Details of Structure of First Embodiment Accordingly, the present invention is so structured as to perform interpolation for enlargement in order to overcome the aforementioned problems, while employing the technical idea of the above related example. Fig. 8 is a block diagram showing the first embodiment as shown in Fig. 1 in detail, which is different from the technical example of Fig. 2 in the following points: In comparison with the memory address generation part 19a of the technical example, the memory address generation part 19 of the first embodiment is characterized in that the clock memory 40 is with data inputs/outputs in two-bit structure, and storage contents thereof include new information as hereinafter described, that one input of the AND circuit 41 is in two-bit structure, and that the interpolation arithmetic circuit 21 receives the clocks CK3 and the outputs from the clock memory 40. On the other hand, the outputs from the image memory 18 are supplied to two D type flip-flops or D-FFs 51 and 52 which are connected in series with each other and included in the interpolation arithmetic circuit 21. The D-FFs 51 and 52 receive the clocks CK3 in latch inputs thereof. Respective outputs V₁ and V₂ from the D-FFs 51 and 52 are supplied to three linear interpolation circuits 53a to 53c. The linear interpolation circuits 53a to 53c receive the outputs V₁ and V₂ to operate three linear interpolation values as follows: (V₁ + V₂)/2 (2V₁ + V₂)/3 (V₁ + 2V₂)/3 which are supplied as B to D inputs for a selector 54. The outputs V₁ (original pixel data) from the D-FF 52 are directly supplied as A inputs to the selector 54. One of the four inputs A to D are selected by the two bit outputs from the clock memory 40, to serve as Y outputs. This embodiment is so structured that the D, C, B and A inputs are respectively selected when the selecting inputs respectively indicate "0", "1", "2" and "3". Therefore, in this case, "3" indicates the original pixel data and "2" indicates signals in the expression (1) while "1" indicates signals in the expression (2) and "0" indicates signals in the expression (3). This is shown as "0" to "3" in Table 2 which is inserted few pages after. Further, the outputs from the selector 54 and the outputs V₁ from the D-FF 52 are received by a selector 55, which in turn selects the A inputs for reduction and the B inputs for enlargement respectively to supply the same to the halftone dot generator 22, with the reduction/enlargement indicating inputs supplied from the magnification setting part 20 through the register 38 as selection inputs. (D) Storage Contents of Clock Memory 40 in First Embodiment Description is now made on data contents to be stored in the clock memory 40. The data are supplied in the unit of one bit in the aforementioned case, while the same are in two-bit units this time, to include selection data for selecting interpolation data. In the first embodiment, clock pulses are regularly omitted from the pixel clocks CK1 following the rule employed in the aforementioned related technical example while pixels newly added in correspondence to the omitted pulses are assigned with values obtained by interpolation of data on original pixels adjacent to the same. It is to be noted that the first embodiment is directed to enlargement up to 300%. The interpolation values vary with positional relation between the said added pixels and the original pixels, to assign a value obtained by simply averaging two pixel data V₁ and V2 (e.g., gradation data) on two original pixels with respect to an added pixel P₀ when the said pixel P₀ is between the said two original pixels, and values obtained by weightedly averaging in the ratio of 1:2 and 2:1, when two continuous added pixels P₁ and P₂ are inserted between two original pixels, the two pixel data V₁ and V₂ on the two original pixels with respect to the added pixels P₁ and P₂ respectively. Such interpolation is called linear interpolation. Therefore, it is necessary to find the added pixels in the outputs from the image memory 18 and find positional relation between the said added pixels and the original pixels. In the first embodiment according to the present invention, the former information is indicated by using similar data to that in Table 1 for indicating the pulse omission rule employed in the aforementioned technical example while the latter positional relation is indicated by assigning one of three values as hereinafter described to words indicating omission in the data. Figs. 10A and 10B show processing for assigning such values. A routine S10 in Fig. 10 is identical to the routine as shown in Fig. 4 except for that the process in the case of A1 = A (step S5) is performed as DATA(I) = 3, and detailed description thereof is omitted. Thus, obtained after completion of the routine S10 are data in which "1" is replaced by "3" in the data as shown in Table 1. As a subsequent step S11, a determination is made as to whether or not the designated magnification indicates enlargement, and when the determination is of no, no interpolation is required and the processing is completed. When the determination is of yes, the process is advanced to a step S12, at which I is assigned with 1 while 0-th and (m + 1)th words are defined through use of data on m-th and first words respectively. Such definition is performed in consideration of case where the added pixel is in a position corresponding to the first or m-th word, in order to attain the data on the pixels adjacent to the added pixel, through the fact that the data are repeatedly used in a cyclic manner. At a subsequent step S13, a determination is made as to whether or not the I-th word is in the value "3", and if the determination is of yes, the process is advanced to a step S19. In other words, no interpolation is required in this case since a pixel supplied by a non-omitted clock pulse is an original pixel. On the other hand, when the I-th word is determined as a value other than "3", a further determination is made at a subsequent step S14 as to whether or not a (I - 1)th word indicates "3". When the determination is of no, the word is assigned with "0" at a step S15. In this case, the pulse part corresponding to the I-th word is omitted and a pixel immediately ahead of the added pixel thereby generated is also an added pixel, that is, the added pixel corresponds to P₂ as shown at Fig. 9(b), and hence the value "0" is assigned for indicating assignment of the value (V₁ + 2V₂)/3 in operation as hereinafater described. When the (I - 1)th word indicates "3" at the step S14, a determination is made at a step S16 as to whether or not the (I - 1)th word is "3". If the determination is of no, the I-th word is assigned with "1" at a step S17. In this case, the (I - 1)th and (I + 1)th words adjacent to the I-th word indicate the original and added pixels respectively, the positional relation recognized as that shown by P₁ at Fig. 9(b), and hence (2V₁ + V₂)/3 is assigned by the value "1". When the (I + 1)th word is also determined as "3" at the step S16, the word indicates the added pixel interposed between the original pixels, and the word is assigned with"2" to provide (V₁ + V₂)/2. After the aforementioned data assignment, the value I is increased by 1 at a step S19 and a determination is made at a step S20 as to whether or not I is greater than m. If the value I is smaller than m, the process is returned to the step S12 to repeat the aforementioned processing, while the processing is completed when the value I becomes greater than m. Table 2 shows data obtained by the said processing, in which all of the values "1" in Table 1 are replaced by "3" and the values "0" in Table 1 are changed to any of "0" to "2" depending on the positional relation as shown in Fig. 9. (E) Operation of First Embodiment Description is now made on the operation of the first embodiment in the aforementioned structure with reference to Fig. 8 and a timing chart as shown in Fig. 11. Briefly mentioned in the following description are components operated similarly to those of the related technical example. Further, consideration is made on the case of m = 5 and n =2, i.e., enlargement at a ratio of 250%. Enlargement at 250% In the enlargement at 250%, the magnification setting part 20 setting this magnification value operates data of m(= 5) words x 2 bits (column of "250%" in Table 2)in accordance with the flow chart as shown in Fig. 10, to store the same in the clock memory 40 as shown in Fig. 8. Further, the register 38 is placed in an "enlargement" state. When reading of the original 2 is started, the flip-flop 37 enters a state indicating "writing", and the address counter 36 is cleared. In advance to this, the other address counter 31 is loaded with the value m (= 5), to sequentially supply cyclic address signals with periods for m pulses of the received pixel clocks CK1 (Fig. 11(a)) to the clock memory 40. As shown at Fig. 11(b), the clock memory 40 sequentially outputs the data stored therein in a cyclic manner. The AND circuit 31 gates the pixel clocks CK1 by the outputs from the clock memory 40 to generate the clocks CK3 as shown at Fig. 11(c) from which the pulses are regularly omitted. However, the selector 35 selects the A inputs, i.e., the pixel clocks CK1 in writing for enlargement as hereinafter described, and hence the address counter 36 outputs periodic address signals as shown at Fig. 11(d). Therefore, the image data are written in the image memory 18 in response to the periodic pixel clocks CK1. In such writing operation, since the image memory 18 is in a data input state to make no data output, the interpolation arithmetic circuit 21 is not operated. In reading operation, the flip-frop 37 indicates "reading" and hence the selector 35 selects the B inputs, i.e., the clocks CK3. Therefore, the address outputs from the address counter 36 corresponds in timing to the clocks CK3 as shown at Fig. 11(e) while the reading outputs from the image memory 18 also correspond in timing to the clocks CK3. The image data read in the aforementioned manner are supplied as data inputs to the D-FF 51 in the interpolation arithmetic circuit 21. On the other hand, the D-FF 51 is supplied with clocks CK3 as the latch inputs, whereby the received image data are latched by the pulse intervals of the clocks CK3, to be transferred to the D-FF 52 in the subsequent stage, which in turn performs similar operation. Thus, the outputs V₁ from the D-FF 52 are image data delayed by two pulses of the clpocks CK3 while the outputs V₂ from the D-FF 51 are those delayed by one pulse, as shown at Fig. 11(f) and (g). Symbol D n denotes the image data, which are read in order of ..., D₋₁, D₀, D₁, D₂, ... Linear interpolation circuits 53a to 53c are adapted to operate interpolation values in response to the outputs V₁ and V₂, to supply the same to the selector 54. The selector 54 is also supplied with the outputs V₁ as the A inputs. Selection inputs S of the selector 54 are obtained by the outputs from the clock memory 40, and hence selection of the A to D inputs is determined by the data "0" to "3" outputted from the clock memory 40. The outputs from the selector 54 in such selecting relation are shown at Fig. 11(h). Thus, the selector 55 in the subsequent stage is suppplied as B inputs with signals controlled by values of the data stored in the clock memory 40. The selector 55 is supplied as its A inputs with the outputs V₁ from the D-FF 52, and one of the two inputs A and B are selected by the S inputs from the register 38, which are adapted to select the B inputs of the selector 55 in enlargement. Thus, the selector 55 supplies enlarged image data obtained by assigning the interpolation values to the pixels added by omission of the clock pulses to the halftone dot generator 22. (F) Effects of First Embodiment According to the first embodiment of the present invention, the interpolation values are provided in the aforementioned operation thereby to obtain the image data as shown at Fig. 6(d) by naturally enlarging the original as shown at Fig. 6(a). Further, no inversion in gradation is caused as shown at Fig. 6(e) upon application of processing for enhancing sharpness. Also, when the image as shown at Fig. 7(a) is enlarged, finely stepped gradation boundary lines can be obtained as shown at Fig. 7(c). In addition, the values n and m can be appropriately selected in the magnification at a ratio of (n/m) x 100% or (m/n) x 100%, thereby to arbitrarily reduce serration of the set magnification. (G) Modifications of First Embodiment (G-1) Arbitrary Setting of Enlargement Range As hereinabove described, the data (selection data) for indicating the interpolation values to be assigned in response to the positions of the pixels added in enlargement are employed as composite data composed with the data expressing the rule for omitting the clocks as shown in Table 2 in the aforementioned embodiment. In the sturcture as shown in Fig. 8, calculated are three linear interpolation values for the case where one added pixel is interposed between two original pixels and for the case where two added pixels are interposed between two original pixels, and the data to be stored in the clock memory 40 may be correspondingly formed such that data for selecting the interpolation values are within three types, corresponding to the range of 100 to 300 % in magnification. Required for enlargement exceeding a ratio of 300 % is such an example as hereafter described. When an enlargement range of 100 to (100 x N) % (N: integer), linear interpolation circuits are arranged in parallel for performing the following arithmetic: [LV₁ + (K - L)V₂ ]/K where L = 1, 2, 3,..., (K -1) K = 2, 3, 4,..., N Omittable is one of -these performing substantially identical arithmetic, e.g., (2V₁ + 4V₂)/6 (V₁ + 2V₂)/3 Assuming that the number of the prepared linear interpolation circuits is represented by Q, words in P-bit length corresponding to the minimun integer P providing the following expression (7) are employed as the data to be stored in the clock memory 40: (1 + Q) ≦ 2 P Thus, the information for omitting the clocks as well as that for selecting the interpolation values can be indicated by the values indicated by the said words. Table 3 shows an example of structure according to this principle. Thus, the magnification can be set in an arbitrary range. (G-2) Data Setting Although the data for omitting the clocks and those for selecting the interpolation values are prepared as composite data in the aforementioned embodiment, the present invention is not restricted to such a mode. The said data may be separately prepared to be read in a related mannner so that the omission of the clocks and the selection of the interpolation values are carried out as in the above. (G-3) Interpolation Arithmetic Circuit Although the linear interpolation is performed as interpolation arithmetic in the aforementioned embodiment, interpolation other than the linear interpolation may be employed. Further, the method of fetching the data on the original pixels for the interpolation is not restricted to that employing the aforementioned D-FFs. (G-4) Other Factors Although the above embodiment has been applied to a process color scanner to generate outputs in halftone dots, the present invention is not restricted to such application, but can be applied to any other apparatus such as a process scanner, a facsimile, a copying machine etc. for enlarging images. Since image input/output operation may not be optically performed, the present invention is also appplicable to an apparatus which electrically or magnetically performs input/output operation. Further, significant pixels are substantially increased in number by the interpolation according to the present invention, which is thus applicable to transmission of image data between input and output units in different sampling pitches. According to the first embodiment of the present invention as herein-above described, an even image can be obtained in a wide magnification variable range with an image processor which can obtain a natural image by smoothing space gradation changes of the reproduced image in enlargement.

Claims: An apparatus for interpolating image signals in an image processing unit, said apparatus comprising: image data memory means (18) for storing image data of original pixels, said image data being written into said memory means in synchronism with periodic first clock pulses (CK1), clock pulse generating means (40, 41) for generating second clock pulses (CK3) of a lower frequency than that of the first clock pulses, image data reading means (35, 36) for reading said image data from said image data memory means (18) in synchronism with said second clock pulses, interpolation data generating means (21, 51, 52, 53a - 53c) for interpolating said image data as read to generate interpolation data, characterized by said clock pulse generating means (40, 41) generating said second clock pulses by omitting clock pulses from the first clock pulses according to a prescribed rule, interpolation data assigning means (21, 54, 55) for selectively assigning said interpolation data to additional pixels to be generated at positions corresponding to omitted clock pulses, the selection of assigned data being defined by selection data previously set in correspondence to said prescribed rule. An apparatus for interpolating image signals according to claim 1, wherein said clock pulse generating means includes composite data memory means (40) for commonly storing data representing said prescribed rule and said selection data, said clock pulse generating means and said interpolation data assigning means respectively performing processing on the basis of said composite data read from said composite data memory means (40). An apparatus for interpolating image signals according to claim 2, wherein said interpolation data generating means includes linear interpolation arithmetic means (53a - 53c) for obtaining a plurality of linear interpolation data defined by the positional relation between said additional pixels and said original pixels, said selection data representing said positional relation between said additional pixels and said original pixels.

Inventors: CHO MASAMICHI, KURUSU YASUO, TOMOHISA KUNIO, CHO, MASAMICHI, KURUSU, YASUO, TOMOHISA, KUNIO
Applicants: DAINIPPON SCREEN MFG, DAINIPPON SCREEN MFG. CO., LTD.
Application year: 1986
Main classification: G06T3
IPC codes: G06T3, G06F17