SIGNAL QUALITY STEERED DIVERSITY

Abstract: A circuit and technique for directing an adaptable antenna system. The invention is coupled to the output of an RF receiver (28) configured to provide a data signal output, and evaluates the quality of the receiver data signal. The invention switches antennas (13, 14) when the signal quality deteriorates below a predetermined level.

Description: SIGNAL QUALITY STEERED DIVERSITY Cross-Reference To Related Applications This is a continuation-in-part application based on serial number 06/511431, filed July 6, 1983. Background of the Invention Field of Invention This invention relates to the field of portable communication transceivers and specifically to a portable transceiver circuit which determines che quality of a received signal and directs the tranceiver to select an alternative antenna if the signal quality deteriorates below a predetermined level. Description of che Prior Art Portable radio transceivers are used in several facets of communications technology. Portable trans¬ ceivers can be found in paging systems, cwo-way communica¬ tion systems such as chose used by police and other public servan s, and more recently portable receivers have found use in portable data terminals which are used co communicate wich a hose compucer over a radio link. Portable data cerratnals provide compucer diagnoscics and expanded compucer power in che porcable terminal. Typical portable paging receivers in the past have incorporated loop-type antennas which are typically reβponβive to the magnetic field component of a ' trans¬ mitted RF signal. This type of antenna system provides marginal performance, but is desirable because the loop antenna can be concealed within a radio housing and responds well when the receiver is in close proximity to a human body. However, the overall sensitivity of the antenna/receiver combination is somewhat degraded where the receiver is in close proximity to a human body. In addition, loop-type antennas exhibit certain problems which make chem undesirable for use in a portable device which also utilizes a transmitter. Portable unics which contain both a receiver and transmitter are utilized in public service and private industry where communication between a number of units is desirable. The units typically contain a receiver and transmitter used in combination with an external helical, monopole or dipole antenna. These antennas are respon- sive to the electrical field of an RF signal and provide superior reception and cransmission characceriscics, when che ancenna is locaced excernaliy co che portable device housing. In addicion, helical and monopole ancenna performance is degraded substantially when che ancenna is operaced in close proxi icy co a human body. A paging receiver is normally worn on che body when in use. Unlike che pager, a portable transceiver is utilized in many different environments. It may be handheld in fronc of che face, worn on che hip, or placed on a conducting or non-conducting surface. Wich che advance of data processing and daca communication techniques, it is now desirable co manu¬ facture portable communicacion devices which are capable of crahsmicting and receiving daca in cooperation wich a hose computer. These devices are for inscance useful co servicemen who use ene portable terminal co perform on-site computer testing and diagnostics, and to keep records thereof. It is desirable to manufacture a portable data terminal as small as possible, so the terminal can be transported easily. In addition, it is also desirable to provide a portable data terminal with an antenna system which is completely enclosed within the terminal housing. This feature enhances che portability of the data terminal, as well as providing protection for the terminal antenna system. These terminals may be carried in the hand, worn on the hip, put in a coat pocket, used on a desk, or put into a service cool kic. The orientation of. the unic, as well as ics physical environment is constantly changing as it is utilized from one time to the next. Since che portable data terminal is operated in a number of discincc environments and orientations, ic is necessary co provide an ancenna system which is adaptable to a changing environment. Adaptability is especially useful when che porcable daca terminal is used in close proximity Co a human body. In an adapcable ancenna system, che receiver muse include a means for alternately accivacing antennas in response co che qualicy of a received signal. Prior arc ancenna swicching devices have typically based che ancenna swicching decision on che signal screngch of an incoming RF signal. This technique switches ancennas when che incoming signal drops below a predetermined chreshold. To implement a signal strength based ancenna decision, expensive RF circuicry is required co process signal screngch information. In addicion, signal screngch based ancenna switching is prone co "chattering" when Che signal Level for each ancenna is below a predeceπnined threshold. For the foregoing and ocher shorccomings, chere is a need for an improved adapcable ancenna system control scheme for use with a transceiver in which the ancenna system activates a particular antenna based on the signal quality of the incoming signal. Signal quality information is derived from the receiver output signal and does not require any special RF amplifiers to determine signal quality. Summary of the Invention Accordingly, it is an object of the present inven¬ tion to provide an improved antenna selector device which utilizes a measurement of the audio signal quality to determine whether to switch to an alternate antenna. It is a further object of the present invention to implemenc an antenna hold feature so rapid antenna switching will not occur at low signal levels. It is still another object of che present invention co implemenc an ancenna selector device which effects che ancenna swicch ae a cime optimized for reduced data errors due co swicching cransiencs. Briefly described, che invention contemplates an ancenna switching circuit, and technique which is used co control an adapcable ancenna system in a porcable crans- ceiver. The invencive ancenna switching circuit is coupled co che audio output of a receiver, which is configured co provide a daca output signal. The receiver is coupled Co a bit quality dececcor which samples each incoming daca bic at four times the data rate. Each data cycle is stored in a shift register. The data sample corresponding co che middle of che daca bic is recained as che value of che daca bit and che daca bit together wich boch adjacenc data samples are compared co generace a noise flag bic. If che bic transition itter is less than + 1/4 bit, the noise flag bit is 0 otherwise the noise flag bit is sec co 1. The incoming daca scream and noise flag bit stream is then coupled co a microcompucer which operates in conjunccion wich Che bic qualicy and daca scorage regiscers. When 8 daca bics and che corresponding 8 noise flag bits have been accumulated, the bits are ' read into the microcomputer memory and processed in accordance with the present invention. According co the present invention, the microprocessor retains 14 bytes of previous noise flag bit information. The microcomputer then compares the flag rate being generated by the presently connecced ancenna wich the flag rate which was generated by the previously connected antenna, f che previously connecced ancenna has been disconnected for 14 bytes then its flag rate is set to (a fixed value) K/14, where K is an integer greater than or equal to 0. In che present embodiment, K is sec Co 5. If che ancenna presently connected produces a flag rate higher than the previously connecced ancenna, che microprocessor will pause and swiech ancennas ac a cime which minimizes bic errors due co swicching transients. Brief Description of che Drawings Figure 1 is a perspeccive drawing of a porcable daca receiver such as one which would incorporace che preferred embodimenc of che presenc invencion. Figure 2 is a block diagram of an ancenna syscem which would incorporace an embodimenc of che present invencion. Figure 3 is a illuscracion of che sampling scheme for decermining bic qualicy in accordance wich che presenc invencion. Figure 4 is an electrical schemacic of a circuit which generates bic qualicy informacion oics ucilized by Che present invencion. Figure 5 is a flow diagram which details che operacion of the presenc invencion. Figure 6 is a flow diagram which decails che operacion of anocher embodimenc of che present invencion. Detailed Description of the Drawings Figure 1 shows a perspective drawing of a portable data communication device such as one which would incorporace the preferred eabodiaent of the present invention. The portable transceiver 10 incorporates a display 12 and a keyboard 11 and is used to communicate with a host computer. The portable transceiver 10 transmits and receives modulated data and can be used to provide on-site computer diagnostics. The portable transceiver 10 is constructed of a plastic housing which encases the terminal and radio electronic circuits, as well as an adaptable antenna system including a plurality of antennas which may be optimized for specific environmental conditions, for example, on the body versus off the body use. An exact description of the receiver antenna system is shown in copending patent applicacion serial number 511,430 entitled "Homotropic Ancenna System" by Kneisel et al, filed July 6, 1983, and assigned to the assignee of the present invention. The present invention operates in cooperation with the receiver and deter- mines which antenna 13, 14 is producing a higher quality signal, and selects that antenna. Figure 2 shows an electrical schematic and block diagram of a data receiver which would utilize che pre¬ ferred embodimenc of the present invention. The daca terminal includes cwo ancennas 14, 13 which are coupled co diodes 21, 26. The antennas are selectively activated through induccors 22, 27 by placing a control voltage on terminals "A" or "B". Ancennas 14, 13 are then coupled to a receiver 28 through capacitors 23, 24. The receiver 28 processes the received signal and converts it to a lower frequency signal of che desired form, in chis case binary data at approximately 4800 bics/sec. The receiver daca output is then coupled to a bic qualicy dececcor 30 which generaces a binary signal corresponding co che binary daca signal which provides a flag bic indicating the quality of a received bit. The bit quality detector circuit 30 will be discussed in more detail later. The bit quality detector 30 is coupled co a micro¬ processor 31 which processes che incoming data and bit qualicy information in accordance with the present invention. The microprocessor 31 then selectively activates antenna 14 or 15 depending on the quality of che incoming signal being produced by a particular antenna. The microprocessor 31 can be any suitable conventional microprocessor, such as, for example, a Motorola type MC146805 and ics RAM and other peripheral devices. Figure 3 is an illustration of the sampling scheme for determining bic qualicy in accordance wich che presenc invencion. As shown in Figure 3, each incoming daca bic is sampled four cimes. According co che presenc invencion, a daca bic of accepcable incegricy is defined as having less Chan + 1/4 bic cransicion cime jiccer. Therefore, according co Figure 3, if samples 2, 3 and 4 are Che same, i.e., all ones or zeros, then che noise flag will be sec co zero for chac bic, ocherwise, che noise flag is 1. Figure 4 shows an eleccrical schemacic of a circuit in bic qualicy dececcor 30 in Figure 2 which generates noise flag bic informacion in accordance wich the present invencion. The bic noise flag generacor circuit consists of a series of flip-flops 40, 42, 44 which are configured as a 3 bic shift register. Samples are shifced inco che chree bic shift regiscer ac four cimes che daca race as shown by cerminal 4X coupled co flip-flops 40, 42 and 44. The chree outputs of this shifc regiscer provide che four sample per bit informacion required co recover clock and daca and generate bit noise flags. A separace circuic (noc shown) decodes che daca scream and produces a clock signal ac che clock race, a clock signal ac twice the data rate and a clock signal ac four Cimes che daca rate. The clock recovery circuic could be any conventional digital phase locked loop configured co lock che dececcor clock onto che incoming data βtrean. The four samples occur on the ricing edge of 4X serial daca clock. The IX and 2X clocks are derived from che 4X clock by simple divide by 2 stages. The IX and 2X clocks are used co uniquely identify che position of che four samples as chey are shifced chrough che 3 bit regiscer. The recovered daca signal is derived from che oucpuc of flip-flop 40 and corresponds co sample 3 of Figure 3. The daca sample is ehen shifced co che 8 bic daca regiscer 56 on each falling edge of che IX clock. The bic noise flag informacion is generaced by logic gaeeβ 46, 48 and 50. The bic noise flag bic is shifced inco che 8 bic BNF regiscer 54 on ehe rising edge of che BNF clock (BNFC). This clock (BNFC) is derived by the 3-input NOR gate 52 at the fall of the 4X clock following sample 4 of Figure 3, which fall occurs when samples, 4, 3 and 2 are all present in flip-flops, and 40, 42 and 44 respectively and the bit noise flag BNF has been . decoded in gate 50. This occurs when flip-flop 40 stores sample 3, and flip-flop 44 stores sample 2. The exclusive OR gates 48, 46 and OR gate 50 are coupled so that they generate an output according to the logical relationship. BNF - [2 + 3] + [3 + 4] Afcer eight daca bics and che corresponding BNF bics have been shifced inco che regiscers 54, 56, che informacion is transferred co buffer regiscers (noc shown; which are accessed by che microprocessor 31 of Figure 2. Figure 5 shows a flow diagram which defines che micro¬ processor (31 of Figure 2) operacion in accorαance wich che preferred embodimenc of che presenc invencion. The process of che presenc invencion keeps a running eocal of how many bics are flagged and which ancenna is connected when each byce's worch of daca received. The invencive process decides chac che ancenna is co be switched if and only if there is ac lease one flag bic that is a 1 in the most recencly received byce and the flag rate from the non-accached ancenna (FR2) is less Chan che flag race of che accached ancenna (FR1). Flag rate 2 (FR2) is defined as the numoer of flags received in the last fourteen bytes when che non-accached ancenna 2 was accached divided by che number of byces when che non-accached ancenna was accached. FR2 is equal Co zero if non-accached ancenna was noc accached during che lasc 14 byces. Flag race 1 (FR1 for che accached ancenna FR1 is defined in ehe same manner. When an ancenna swiech is effecced, che number of flags in che byce where che ancenna swiech occurred is sec Co zero and che associaced byce is considered co belong co che ancenna chac was swicched in. The invencive process also causes che swicching accion co occur ac a parcicular cime before che nexc bic enters che ancenna cerminals. For che purposes of che preferred embodimenc che microprocessor (31 in Figure 2) is adjusced co swiech che ancenna abouc 50 microseconds before che bic cransicion encers che ancenna cerminals. This feature allows che ancenna system co switch ancennas ac a Cime which minimizes bic errors due to swicching transients. In accordance wich che presenc invencion, che program shown in Figure 5 is inicaced every cime che BNF and daca regiscers (54, 56 in Figure ) have accumulated eighe bics. Item 70 inscruces che microprocessor co read che concencs of che daca and BNF regiscers inco che micro- processor RAM. For the purposes of che presenc invencion, 14 bytes of previous BNF informacion for che ancennas are also recaineα in RAM. Decision 72 examines che byce counc for Che currently activated ancenna. If che oyce counc K indicaces chac an ancenna switch occured during che lasc BNF byce (i.e. K»1) , decision 72 direccs che program Co icem 76 which sets che BNF count co zero because chis byce has been corrupted by the antenna switching transient. The byte count K is then reset and item 76 exits the routine to wait for the next byte. If an antenna switch did not occur during the last BNF byte (i.e. K-0) , decision 72 selects item 78 which counts and stores the BNF information of the latest byte. The program proceeds to decision 80 which compares the relative flag rates FRt and FR2 of the two antennas. The flag rate FR of a particular ancenna is defined according to the following relationship. number of flag bits fro* ancenna(n) FR(n - nυB ber of ancenna byctβ ancβnna(n) Flag race 2 (FR2) is always associaced wich che decached ancenna. If flag race 1 (FR1) is grβacβr chan che flag race from che decached ancenna FR2, che program proceeds co icem 84 which waicβ approximacβly SO microseconds before che nβxc bic encers che receiver and chen swicches ancennas. Icem 84 Chen resecs che byce counc co 1 and exics che roucine. If flag race 1 (FR1) is less Chan or equal co flag race 2 (FR2) , an ancenna swiech is noc required and decision 80 exics che roucine. ' Figure 6 shows a flow diagram which defines che micro¬ processor (31 of Figure 2) operacion in accordance wich anocher embodimenc of che presenc invencion. The process of che presenc invencion keeps a running coeal of how many bics are flagged and which ancenna is connecced when each byce's worth of data is received. The inventive process decides chac che ancenna is Co be swicched if and only if che flag race from che non-attached antenna (FR2) is less chan ehe flag race of ehe attached antenna (FR1). Flag rate 2 (FR2) is defined as the number of flags received in che lasc fourceen byces when che non-aceached ancenna 2 was accached divided by che number of byces when che non-attached ancenna was accached. FR2 is set equal co X/14 if che previously connecced antenna has been disconnecced for 14 byces then its flag race is sec to (a fixed value) X/ 4, where X is an integer greater than or equal to 0. In the presenc embodimenc, X is sec co 5, if che non-accached ancenna was noc accached during che lasc 14 byces. Flag race 1 (FR1) for che accached ancenna FR1 is defined in che same manner. When an ancenna swiech is effβceβd, che number of flags in the byte where the antenna switch occurred is set to zero and the associated byte is considered to belong to the antenna that was switched in. The inventive process also causes the switching action to occur at a particular time before the next bit enters the antenna terminals. For the purposes of the preferred embodimenc ehe microprocessor (31 in Figure 2) is adjusced co switch the antenna about 50 microseconds before che bic cransicion enters che ancenna cerminals. This feature allows the antenna system co swiech ancennas ae a cime which minimizes bic errors due eo swicching cransienes. In accordance wich che presenc invencion, ehe program shown in Figure 6 is inicaced every cime che BNF and daca regiscers (54, 5b in Figure 4) have accumulacβd eighe bics. Icem 170 inscruces ene microprocessor eo read che concencs of che daca and BNF regiscers inco che micro¬ processor RAM. For che purposes of che presenc invencion, 14 byces of previous BNF informacion for che ancennas are also recained in RAM. Decision 172 examines ehe byce counc for che currencly accivaced ancenna. If che byce counc K indicaces chac an ancenna swiech occured during che lasc BNF byce (i.e. -1) , decision 172 direccs che program co icem 176 which sets the BNF. counc co zero because chis byce has been corrupted by the ancenna swicching cransiene. The byce counc K is then sec co two and icem 176 exics Che roucine co wait for che nexc byce. If an ancenna switch did noc occur during che lasc BNF byce (i.e. K≠ . ) , decision 172 sβleces icem 178 which councβ and scores che BNF informacion of che laeesc byce. If che byce counc K - 14 decision 190 seleccs icem 191 which sets flag rate 2(FR2) - 5/14. If the byte counc K ≠ 14 (i.e. <14) then decision 190 selects item 192 which increments the byte count K. The program proceeds co decision 180 which which compares che relative flag ra t es FR1 and FR2 of the two antennas. The flag rate FR of a particular antenna is defined according to the following relationship. number of flag bits from antenna(n) r ^ number of antenn bytes antenna(n) Flag rate 2 (FR2) is always associated with the detached antenna. If flag rate 1 (FR1) is greater than the flag rate from the detached antenna FR2, the program proceeds to icem 84 which waits approximately 50 microseconds before the next bit enters the receiver and then switches antennas. Item 84 then resets the byte count to 1 and exits che roucine. If flag race 1 (FR1) is less Chan or equal Co flag race.2 (FR2) , an ancenna swiech is noc required and decision 180 exics che routine. In summary, a device capable of directing a swicched ancenna diversicy syseem is described. The ancenna swicching syseem examines bic qualicy informacion generated by an eleccronic circuic and swicches ancennas based on che relacive bic flag race being produced by each ancenna. The invencion effeccs ancenna swicches ac a cime chosen co ' minimize bic error due Co swicching cransiencs. Accordingly, ocher modifications uses and embodiments will be apparent co one skilled in che arc wiehouc deparcing from che spiric and scope of che principles of che present invencion. What is claimed is:

Claims: Claims 1. An antenna control circuit for selecting a particular antenna in an adaptable antenna system, including a presently selected antenna and an alternate antenna, based on the output data signal of a receiver configured to receive a modulated data signal comprising: means for sampling each bit of the received data signal a plurality of times and producing respective noise flag bits indicative of the quality of the data signal receiver output using, respectively, the presently selected antenna or the alternate antenna; and means for processing the respective noise flag bits for the presently selected antenna and alternate antenna and selecting the alternate antenna if data signal quality indicated by the processed noise flag bits for the presently selected antenna is lower than data signal quality for the alternate antenna. 2. A method for selecting a particular antenna in an adaptable antenna system, including a presently selected antenna and an alternate antenna, based on the output signal of a receiver configured to receive a modulated data signal comprising the steps of: sampling each bit of the received data signal a plurality of times; producing respective noise flag bits indicative of the quality of the data signal received using, respectively, the presently selected antenna or the alternate antenna; processing the noise flag bits for the presently selected antenna and the alternate antenna; and selecting the alternate antenna if the data signal quality indicated by the processed noise flag bits for the presently selected antenna is lower than the data signal qualit for the alternate antenna. 3. A method for selecting one of the two antennas in an adaptable antenna system including a presently selected antenna and an alternate antenna for receiving an RF data signal having a plurality of bits comprising the steps of: receiving the RF data signal; converting the received RF data signal to a baseband data signal; sampling each bit of the baseband data signal at least four times; comparing the data samples and generating a noise flag bit based on a predetermined criteria; accumulating multiple bytes of noise flag bits; generating a respective noise flag rate based on at least two noise flag bytes for each of the presently selected antenna and the alternate antenna; and selecting the alternata antenna if the noise flag rate of the presently connected antenna is greater than the noise flag rate of the alternate antenna. - 16 - 4. An antenna control circuit for selecting a particular antenna in an adaptable antenna system including a presently selected antenna and an alternate antenna based on the output signal of a receiver configured to receive a modulated data signal comprising: means for sampling each bit of the baseband data signal a plurality of times; means for comparing the data samples and generating a noise flag bit based on predetermined criteria; means for accumulating multiple bytes of noise flag bits; means for generating a respective noise flag rate based on at least two noise flag bytes for each of the presently selected antenna and the alternate antenna; and means for selecting the alternate antenna if the noise flag rate of the presently connected antenna is greater than the noise flag rate of the alternate antenna. 5. A method for selecting one of two antennas in an adaptable antenna system, including a presently selected antenna and an alternate antenna for receiving an RF data signal having a plurality of bits comprising the steps of: receiving the RF data signal; converting the received RF data signal to a baseband data signal; sampling each bit of the baseband data signal at least four times; storing the four data samples in a register; retaining a data sample as the value of the data bit; comparing the data samples and generating a noise flag bit based on a predetermined criteria; accumulating multiple bytes of noise flag bits and retained data bits; generating a respective noise flag rate based on at least two.noise flag bytes for the presently selected antenna and alternate antenna; comparing the noise flag rate of the presently selected antenna with the noise flag rate of the alternate antenna; generating a delay if the noise flag rate of the presently connected antenna is greater than the noise flag rate of the alternate antenna; and selecting the alternate antenna after the delay has elapsed. - 18 - 6. An antenna control circuit for selecting a particular antenna in an adapatable antenna system including a presently selected antenna and an alternate antenna based on the output signal of a receiver configured to receive a modulated data signal comprising: means for sampling each bit of the baseband data signal at least four times; means for storing the four data samples in a register; means for recovering a data sample as the value of the data bit; means for comparing the data samples and generating a noise flag bit based on predetermined criteria; means for accumulating multiple bytes of noise flag bits and recovered data bits; means for generating a respective noise flag rate based on at least two noise flag bytes for each of the presently selected antenna and the alternate antenna; means for comparing the noise flag rate of the presently selected antenna with the noise flag rate of the alternate antenna; means for generating a delay if the noise flag rate of the presently connected antenna is greater than the noise flag rate of the alternate antenna; and means for selecting the alternate antenna after the delay has elasped. 7. The method of claim- 5 wherein said generating step includes the step of generating noise flag bits according to the relationship [S2 + S3] + [S3 + S4] where S2, S3 and S4 are the second, third and fourth data samples when the first sample occurs on the leading edge of each data bit. - 20 - 8. An antenna control circuit for selecting one of two antennas in an adaptable antenna system, the antenna selection based on the data signal quality of the receiver output signal, said antenna control circuit comprising: a first shift register having at least a first, second and third outputs and being coupled to the receiver output for sampling and storing an incoming data bit; a first exclusive OR logic means with inputs coupled to said second and third shift register outputs for generating a first logic signal; a second exclusive OR logic means with inputs coupled to said second and third shift register outputs for generating a second logic signal; OR logic means with inputs coupled to the outputs of said first and second exclusive OR logic means for generating noise flag bits; means for generating a first, second and third clock signals locked to the incoming data stream for clocking said first shift register with the third clock signal; NOR logic means with inputs ςoupled to said first, second and third clock signals and an output. a second shift register with a clock and data input, said clock input coupled to said NOR logic means output signal, said data input coupled to said OR logic means for accumulating noise flag bits; a third shift register with data and clock input, said clock input coupled to said first clock signal, said data input coupled to the first output of said first shift register for accumulating data bits; processing means coupled to said second and third shift register for receiving noise flag and data bits and selecting one of the two antennas based on the noise flag bits. 9. An antenna control, circuit for selecting a particular antenna in an adaptable antenna system, including a presently selected antenna and an alternate antenna, based on the output signal of a receiver configured to receive a modulated data signal comprising: means for sampling each bit of the received data signal a plurality of times and producing respective noise flag bits indicative of the quality of the data signal receiver using, respectively, the presently selected antenna; and means for processing the respective noise flag bits for the presently selected antenna and selecting the alternate antenna if a predetermined number of noise flag bits are detected within a predetermined number of bytes of the received data signal. 10. A method for selecting a particular antenna in an adaptable antenna system, -including a presently selected antenna and an alternate antenna, based on the output signal of a receiver configured to receive a modulated data signal comprising the steps of: sampling each bit of the received data signal a plurality of times; producing respective noise flag bits indicative of the quality of the data signal received using the presently selected antenna; processing the noise flag bits for the presently selected antenna; selecting the alternate antenna if the number of noise flag bits detected during a predetermined period exceeds a predetermined constant. - 24 - 11. A method for selecting one of two antennas in an adaptable antenna system including a presently selected antenna and an alternate antenna for receiving an RF data signal having a plurality of bits comprising the steps of: receiving the RF data signal; converting the received RF data signal to a baseband data signal; sampling each bit of the baseband data signal at least four times; comparing the data samples and generating a noise flag bit based on a predetermined criteria; accumulating multiple bytes of noise flag bits; generating a respective noise flag rate based on at least two noise flag bytes for each of the presently selected antenna; and selecting the alternate antenna if the noise flag rate of the presently selected antenna exceeds a predetermined threshold. 12. An antenna control circuit for selecting a particular antenna in an adaptable antenna system including a presently selected antenna and an alternate antenna based on the output signal of a receiver configured to receive a modulated data signal, comprising: means for sampling each bit of the baseband data signal a plurality of times; means for comparing the data samples and generating a noise flag bit based on predetermined criteria; means for accumulating multiple bytes of noise flag bits; means for generating a respective noise flag rate based on at least two noise flag bytes of the presently selected antenna; and means for selecting the alternate antenna if the noise flag rate of the presently connected antenna is greater than a predetermined constant. 13. A method for selecting one of two antennas in an adaptable antenna system, including a presently selected antenna and an alternate antenna for receiving an RF data signal having a plurality of bits comprising the steps of: receiving the RF data signal; converting the received RF data signal to a baseband data signal; sampling each bit of the baseband data signal at least four times; storing the four data samples in a register; retaining a data sample as the value of the data bit; comparing the data samples and generating a noise flag bit based on a predetermined criteria; accumulating multiple bytes of noise flag bits and retained data bits; generating a respective noise flag rate based on at least two noise flag bytes for the presently selected antenna; comparing the noise flag rate of the presently selected antenna with a predetermined constant; generating a delay if the noise flag rate of the presently connected antenna is greater than the predetermined; and selecting the alternate antenna after the delay has elapsed. 14. An antenna control circuit for selecting a particular antenna in an adapatable antenna system including a presently selected antenna and an alternate antenna based on the output signal of a receiver configured to receive a modulated data signal comprising: means for sampling each bit of the baseband data signal at least four times; means for storing the four data samples in a register; means for recovering a data sample as the value of the data bit; means for comparing the data samples and generating a noise flag bit based on predetermined criteria; means for accumulating multiple bytes of noise flag bits and recovered data bits; means for generating a respective noise flag rate based on at least two noise flag bytes for the presently selected antenna; means for comparing the noise flag rate of the presently selected antenna with a predetermined constant; means for generating a delay if the noise flag rate of the presently connected antenna is greater than the noise flag rate of the predetermined constant; and means for selecting the alternate antenna after the delay has elasped. - 23 - 15. The method of claim 13 wherein said generating step includes the step of generating noise flag bits according to the relationship [S2 + S3] + [S3 + S4J where S2, S3 and S4 are the second, third and fourth data samples when the first sample occurs on the leading edge of each data bit.

Inventors: BRUCKERT EUGENE JOSEPH, BUTCHER JAMES STEVEN, KNEISEL THOMAS FREDERICK, BRUCKERT, EUGENE, JOSEPH, BUTCHER, JAMES, STEVEN, KNEISEL, THOMAS, FREDERICK
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1986
Main classification: H04B7
IPC codes: H04B7, H04L1