EQUALIZED BIASED ARRAY FOR PROMS AND EPROMS

Abstract: An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V T above V BIAS . Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V T above V BIAS . The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.

Description: BACKGROUND The present invention relates to a method and apparatus for equalizing the biasing of a transistor memory cell during the READ mode across those cells which are non-selected. The invention is applicable to read only memory cells (ROMS), programmable read only memory cells (PROMS) and electrically programmable read only memory cells (EPROMS). Previously, a reference signal was used to drive independent bit line and array source drivers in order to condition the floating gate transistors for a READ cycle in an array of programmable and electrically programmable read only memory cells. The variation of the voltage level on the drain of the floating gate transistor being read due to threshold voltage or V T variations of the above-mentioned drivers rendered more uncertain the correct detection of the cell state. In addition, because the driver of the bit line operated in a mode in which its gate voltage was not more than a V T above its drain, not only was its source voltage V T dependent, but whenever the bit line voltage rose suddenly, the latter bit line driver became non-conducting and resulted in trapping the bit line voltage in a higher than normal state. Accordingly, it is a principal object of this invention to provide an improved biasing arrangement for an array of transistor memory cells. SUMMARY OF THE INVENTION According to the invention there is provided an array of transistor memory cells as set forth in claim 1. A bias voltage line on which there is established a voltage V BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V T above V BIAS . Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V T above V BIAS . The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be non-conducting. BRIEF DESCRIPTION OF THE DRAWINGS The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein: Fig. 1 is a circuit diagram of a prior biasing arrangement for an array of programmable and electrically programmable read only memory cells; Fig. 2 is a circuit diagram of a preferred embodiment of a biasing arrangement for an array of programmable and electrically programmable read only memory cells; and Fig. 3 is a circuit diagram of an array of cells in accordance with the biasing arrangement shown in Figure 2 above. DETAILED DESCRIPTION WITH REFERENCE TO THE DRAWINGS Referring to Figure 1 there is shown a prior arrangement for biasing an array of memory transistors 12. In this case transistors 12 are each coupled to ground through associated ground select transistors 22. The drain of each transistor 12 is coupled by a bit line 24 to the source-drain path of a bit transistor 14. The other end of the source drain path of transistor 14 is connected to a voltage V cc line 16 while its gate is fed by a reference voltage REF. The source of each transistor 12 is coupled to an associated source line 28 which connects to a source-drain path of a transistor 20. The other end of the latter path is coupled to V cc line 16 by the source drain path of a transistor 18. The gate of transistor 18 is driven by the reference voltage REF while that of transistor 20 is driven by the complement VG of the voltage VG that drives the gate of ground select transistor 22. Also coupled to bit line 24 are a pair of series connected select transistors 26 and 30 driven by select lines Y and Z, respectively. The source-drain path of transistor 30 connects to a transistor 32 whose gate is driven by the reference voltage REF and the other end of the path being coupled to a transistor 34 connected as a load to voltage line V cc 16. A sense amplifier (not shown) couples to the junction of transistors 32 and 34 to measure the voltage at that point during a read cycle. The structure, circuit arrangement and operation of the array of memory cells of Figure 1 is similar to that set forth in U.S. Patent No. 4,314,362 issued Feb. 2, 1982 Klaas et al. Operation of the circuit of Figure 1 for a read mode involves selection of a particular transistor 12 by application of decode signals X, Y and Z to sets of transistors 12, 26 and 30, respectively. The application of reference voltage REF which is normally about 2 or 3 volts to the gate of transistor 14 causes the latter to conduct and places a voltage equal to REF -V T on bit line 24. The threshold voltage V T of transistor 14 is introduced as a variable on bit line 24 since transistor 14 is operating with its gate at a lower voltage than its drain (ie. 2-3 volts versus 5 volts). For a selected transistor 12, ground select transistor 22 is turned on by the application of a voltage VG to its gate thereby drawing down source line 28 close to ground. If the selected transistor 12 has not been programmed so that it is in a "1" state then current will flow through transistors 14, 12, and 22 to ground. Similarly, transistor 32 will be made conducting by voltage REF so that current will flow through it and through transistor load device 34 thereby dropping the voltage fed to the sense amplifier (not shown). Since transistor 32 also operates in a V T dependent mode its conductive state will depend on its value of V T as compared to that of transistor 14. For a V T variation of transistor 32 higher than that of transistor 14, it is possible that transistor 32 could be insufficiently conductive. In order to avoid loading of the bit line 24 during a read cycle by other transistors 12 all source lines 28 other than that of the selected transistor 12 are driven up to the same potential as their corresponding bit lines 24 by transistor 18. In this case the complement voltage of VG is applied to the gate of transistor 20 making the latter conduct while reference voltage REF is applied to the gate of transistor 18 also making it conduct. However, since voltage REF is less than the voltage V cc on line 16, the voltage on source line 28 will depend on the value of V T of transistor 18. If V T of transistor 18 were significantly higher than that of transistor 14 then it is possible that with transistor 12 in a "1" state transistor 12 could remain conducting sufficiently to load the bit line to which the selected transistor 12 is connected thereby reducing read access time. It will be appreciated that the circuit of Figure 1 is very dependent on the value of V T of a number of transistors. One way of overcoming the V T dependence in the read mode is exemplified by the circuit of Figure 2. In this case both source line 28 and bit line 24 are coupled through transistors 20 and 14 to a V BIAS line 42. Line 42 is coupled through transistor 44 to V cc line 16 and through transistor 46 to ground. The gate of transistor 44 is connected to REF while that of transistor 46 is connected to V cc line 16. The gate of transistor 14 is also connected to V cc line 16 while that of transistor 20 is driven by the complement voltage of VG, designated VG . In the sensing amplifier circuit non-inverting input 60 of sense amplifier 64 is coupled directly to the drain of transistor 30 while its inverting input is coupled to second reference voltage (not shown) but whose value is approximately half-way between the value on input 60 when associated transistor 12 is non-conducting and the value thereon when transistor 12 is conducting. In operation decode signal X serves to select a particular row of memory cells 12, transistor 22 provides a virtual ground to a particular column of cells or transistors 12 and decode signals Y and Z connect the selected cell 12 to the sense amplifier 64. At the same time the presence of voltage V cc on line 16 causes transistor 14 to turn on and couple voltage V BIAS on line 42 to the bit line 24. Since voltage V cc is more than V T greater than V BIAS the full value of V BIAS will be transmitted to the bit line 24. Moreover, since all of the bit lines 24 are connected to V BIAS there is a high capacitance on line 42 which serves to stabilize it. Even though the value of V BIAS is dependent on the threshold voltage V T of transistor 44, any variation of this value of V T affects the voltage on both bit line 24 and source line 28 the same. The sense amplifier 64 whose non-inverting input 60 is lower than input line 62 when transistor 12 is conducting provides a low output in the latter case. If transistor 12 has been programmed so that it is nonconducting then input 60 will be higher than input 62 and output 66 will go high. The drop in voltage of bit line 24 when transistor 12 is conducting is due to the voltage drop across the channel of transistor 14 when it conducts. Incorporation of the circuit of Figure 2 into an array can be understood from the circuit of Figure 3. In this case only 2 rows of transistors 12 with 16 transistors in each row are shown. The rows are labelled X₀ and X₁. Each cell 12 is connected on its source side to a source line 28 and on its drain side to a bit line 24. The remaining components that correspond to those in Figure 2 are labelled with like reference numerals. It will be observed that there are 8 Y lines, 1 Z line 58 and 9 VG or selection lines for the ground selection transistors 22. Line 16 has a voltage V cc applied to it during a read cycle and is grounded during a program cycle. Eight Y lines are applied to the associated gates of 8 P-channel transistors 52 and result in a high voltage V pp being applied to respective bit lines 24 during a programming mode. While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is, therefore, contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims: An array of semiconductor memory transistors having associated bit and source lines and a biasing network comprising: a bias line (42); biasing means (44) coupled to said bias line for biasing the latter to a preselected voltage; bit means (14) coupled between said bias line and said bit lines for transmitting the voltage on said bias line to said bit lines during a read cycle in response to a control signal V cc (16); and source means (20) coupled between said bias line and source lines for transmitting the voltage on said bias line to non-selected source lines in response to a control signal VG ; wherein the voltage on said bias line is more than 1 V T less than the voltage of control signals V cc and VG . A biasing network according to claim 1, wherein said bit means is a bit transistor (14) whose source-to-drain path is coupled between said bias line and an associated bit line and whose gate is coupled to a V cc line. A biasing network according to claim 2, wherein said source means is a source transistor (20) whose source-to-drain path is coupled between said bias line and an associated source line and whose gate is coupled to a VG line. A biasing network according to claim 3, wherein said biasing means is a supply transistor (44) whose source-to-drain path is coupled between the V cc line and said bias line and whose gate is coupled to a reference voltage REF. A biasing network according to claim 4, wherein said bias line is coupled to ground through a bleed transistor (46) whose gate is coupled to the V cc line and whose channel size is much smaller than that of said supply transistor. A biasing network according to claim 5, wherein the voltages V cc , VG, Y and Z all about equal d.c. voltages greater than 3 volts and the voltage REF is in the range of 2 to V cc volts. A method of biasing an array of semiconductor memory transistors of a type having respective bit and source lines, comprising: establishing a bias voltage; and transmitting said bias voltage onto said bit lines and onto said source lines of non-selected ones of said memory transistors during read modes. A method according to claim 7, wherein said bias voltage is transmitted to said bit lines by a plurality of transistors each having a source-to-drain path connected between said bias line and an associated bit line and a gate coupled to a V cc line and such that the voltage on said bias line is more than about 1 V T less than that on the V cc line. A method according to claim 8, wherein said bias voltage is transmitted to said source lines by a plurality of transistors each having a source-to-drain path connected between said bias line and an associated source line and whose gate is coupled to a VG line such that for non-selected transistors, the voltage on the VG line is more than about 1 V T greater than that on said bias line. A method according to claim 9, wherein said bias voltage is established by coupling the source-to-drain path of a bias transistor between the V cc line and said bias line and its gate to a reference voltage REF whose voltage is below that of V cc . A method according to claim 10, wherein a bleed path for charge from said bias line is provided by connecting a conducting transistor between said bias line and ground whose channel size is much smaller than that of said bias transistor.

Inventors: COFFMAN, TIMMIE M., KASZUBINSKI, JEFFREY K., SCHRECK, JOHN F., WILMOTH, DAVID D.
Applicants: TEXAS INSTRUMENTS INCORPORATED
Application year: 1986
Main classification: G11C16
IPC codes: G11C17, G11C16, H03K5