MAIN STORAGE ACCESS CONTROL SYSTEM FOR VIRTUAL COMPUTING FUNCTION SYSTEM

Abstract: A main storage access control system for a virtual comput­ ing function system includes an address register (14, 16) for registering memory addresses used for accessing a main storage (4) and being operated under a plurality of address modes having different effective bit lengths concerning the memory addresses, a tag register (30) for registering tag bits for individually designating the address registers, and a selec­ tion unit (33) for selecting the designation of address registers designated by the tag bits by means of an operand address of an instruction which is to be executed by the program of the vir­ tual machine monitoring region. The address mode is changed to the address mode used by the virtual computing function system by means of the output signal of the selection means (33). A method concerning the conversion of an access key by the output of a register designation detection unit in a virtual computing function system is also disclosed.

Description: The present invention relates to a main storage access control system for a virtual computing function system. A virtual computing function system is well known in which a main storage has a plurality of virtual machine regions and a virtual machine monitoring region. In such a system, each of the virtual machine regions is under the control of the virtual machine monitoring region. A virtual computing function which is selected by the virtual machine monitoring region is executed by a central processor unit of a real computer. In a virtual computing function system, an operating system for the virtual computing function system carries out a supervision of operations of the virtual computing function system. Where the result of supervision of an operation of a virtual computing function system affects another operation of the virtual computing function system, for example, in the case of a translation look aside buffer (TLB) or the like, a participation of a virtual machine monitoring region or the like takes place. However, the participation of such a virtual machine monitoring region tends to cause an extension of the time required for execution of the programs, and accordingly, tends to lower the ability of the virtual computing function system. When a virtual machine monitoring region carries out an access to a virtual machine region, for the virtual machine monitoring region to represent the function of the virtual machine region, it is necessary to estaglish an address in accordance with an address mode which is designated by the virtual machine region. Hence, when a virtual machine monitoring region carries out an access to a virtual machine region, it is necessary to discriminate the address mode of the virtual machine region and change the mode to the discriminated address mode or to carry out the equivalent address treatment, which causes a lowering of the efficiency of the control of the virtual computing function system because of the resultant undesirable increased processing overhead. The present invention is claimed in claim 1. An embodiment of the invention may provide an improved main storage access control system for a virtual computing function system in which control in relation to the address mode of the virtual machine region is curtailed, and accordingly, the overhead in operation of the virtual computing function system can be reduced. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is a schematic diagram of a proposed main storage access control system for a virtual computing function system; Fig. 2 is a schematic diagram of a main storage access control system for a virtual computing function system according to an embodiment of the present invention; Fig. 3 illustrates the operation of the system of Fig. 2; Fig. 4 illustrates the operation of a proposed system; and Fig. 5 is the schematic diagram of another main storage access control system for a virtual computing function system, useful for understanding the present invention. Before commencing the description of the preferred embodiment, an example of a previously proposed system is described with reference to Fig. 1. The system of Fig. 1 includes a central processor device 1 and a main storage 4 having virtual machine (VM) regions 41 and a virtual machine monitoring (VMM) region 42. The central processor device 1, is provided with groups of general purpose registers 14 and 16, an instruction register 18, a selector 26, an address adder 21, an access control portion 10, program status word (PSW) registers 15 and 25, a selector 28, and a virtual machine (VM) latch 22. The virtual computing function system of Fig. 1 is operated in a manner such that the program stored in the virtual machine monitoring (VM) region 42 is executed by the central processor unit 1, and the control is transferred to the program stored in the virtual machine region 41. The central processor unit has a plurality of address modes, for example, two address modes such as an address mode of 24 bits and an address mode of 31 bits. The information for designating the address mode is registered in the designation bit 25A of the program status word (PSW) register 25. For example, data "0" or "1" of the designation bit 25A corresponds to the address mode 24 bits or 31 bits, respectively. A memory address for accessing the main storage 4 is designated by the data registered in the address register designation part 19 and the displacement part 20 of an instruction operand registered in the instruction register 18. In calculating an address, the content of one of the general purpose registers 14 designated by the address register designation part 19 is summed with the address displacement value of the address displacement part 20 and, if necessary, a preselected index value by the address adder 21. The output of the result of this summation is transferred to the access control portion 10. The signal of the designation bit 25A is supplied through the selector 28 to the access control portion 10. Accordingly, a predetermined length of bits is designated by the designation bit 25A as an effective address. Where a simulation is carried out by the participation of the virtual machine monitoring region 42, the virtual machine (VM) latch 22 is set upon transition to the VM monitoring, and the program status word (PSW) register 15 and the general purpose registers 16 for the VM monitoring are caused to become effective instead of the program status word (PSW) register 25 and the general purpose register 14. The VM monitoring region 42 is constructed to operate in one of the above-described modes, such as in the 31 bit mode. When the VM monitoring region 42 is operated in the 31 bit mode, the designation bit 15A of the program status word register 15 is set to 31 bits. When the VM monitoring region 42 carries out an access to the virtual machine regions 41 so that the virtual machine monitoring region 42 represents the function of the virtual machine regions 41, it is necessary to establish an address in accordance with the address mode which is designated by the virtual machine regions 41. Hence, when the virtual machine monitoring region 42 carries out an access to a virtual machine regions 41, it is necessary to discriminate the address mode of the virtual machine regions 41 and change the mode to the discriminated address mode or to carry out the equivalent address treatment, which causes a lowering of the efficiency of the control of the virtual computing function system because of the resultant undesirable increase of the overhead. A main storage access control system for a virtual computing function system according to an embodiment of the fundamental aspect of the present invention is shown in Fig. 2. The system of Fig. 2 includes a central processor unit 1 and a main storage 4 having virtual machine (VM) regions 41 and a virtual machine (VM) monitoring region 42. The central processor unit 1 is provided with a group of general purpose registers 14 and 16, an instruction register 18, a selector 26, an address adder 21, an access control portion 10, program status word (PSW) registers 15 and 25, a selector 27, a tag register 30, and an access detection portion 31 having a selector 33, AND gates 34 and 35, and an OR gate 36. The AND gates 34 and 35 and an OR gate 36 constitute a switching portion 31A. The tag register 30 registers, for example, 16 tag bits, corresponding to the general purpose registers 16. In the tag register 30, the tag bits corresponding to general purpose register Nos. (for example) 4, 5, and 8 in the group 16 of the general purpose registers, which are expected to be the address registers for registering memory addresses for accessing the VM regions 41, are preliminarily made "1". The tag bits of the tag register 30 are selected by the selector 33 under the control of the address register designation part 19. Based on this selection, the designation, by the address register designation part 19, of one of the general purpose registers designated by the tag register 30 is detected. The AND logic of the output of the selector 33 and the designation bit 25A of the program status word register 25 is obtained by the AND gate 35. The output of the AND gate 35 is supplied through the OR gate 36 to the selector 27. The output of the selector 27, which represents the address mode designated by the virtual computing function system, is supplied to the access control portion 10. The address control portion 10 receives the address having the bit length designated by the output of the selector 27 from the address adder 21, and carries out a control of access to the main storage 4. In the operation of the system of Fig. 2, the tag register 30 has the tag bits corresponding to the general purpose registers, and predetermined bits are preliminarily set by the VM monitoring region 42 to the tag register 30. During the execution of the VM monitoring region 42, usually, the designation bit 15A (such as information of "31 bits") of the PSW register 15 is supplied as the output of the selector 27 to the access control portion 10 by the access detection portion 31. When it is detected, however, that the general purpose register designated by the tag register is designated by the address register designation part 19 concerning an instruction, the designation bit 25A (such as information of "24 bits") of the PSW register 25 is supplied as the output of the selector 27 to the access control portion 10 by the access detection portion 31. The above-described operation of the system of Fig. 2 is illustrated in Fig. 3. The usual manner is the processes of "operate with a 31 bits mode", through a determination of whether the VM regions are accessed is "NO"" to "operate with the 31 bits mode". After the detection, the general purpose register designated by the tag register is designated by the address register designation part 19 concerning the instruction, the determination of whether the VM regions are accessed is changed to "YES", and the process proceeds to "operate with a 24 bits mode". For comparison, the previous process is illustrated in Fig. 4. It is noted that, in the prior art process, the change from "31 bits mode" to the "24 bits mode" upon the access of VM regions by the VM monitoring region is carried out by the execution of a prepared program by which the upper 7 bits are cleared from "31 bits" to realize "24 bits". A main storage access control system for a virtual computing function system useful for explaining the present invention is shown in Fig. 5. This embodiment of Fig. 5 is directed to solving the problem in the previous proposal shown in Fig. 1, in which access control is carried out by the access key 15A', 25A' designated by the virtual machine computation function system for accessing the virtual machine regions 41. Usually, an access key is provided corresponding to each of the virtual machine regions VM0, VM1, and VM2, and the virtual machine monitoring region. The access to a region of the main storage is carried out after confirming the coincidence of the key. For example, a key is represented by data of 4 bits. The system of Fig. 5 includes a central processor unit 1 and a main storage 4 having VM regions 41 and a VM monitoring region 42. The central processor device 1 is provided with groups of general purpose registers 14 and 16, an instruction register 18, a selector 26, an address adder 21, an access control portion 10, PSW registers 15 and 25, a selector 27, a tag register 30, and an access detection portion 31 having a selector 33 and a switching portion (gate) 37. The tag register 30 registers, for example, 16 tag bits, corresponding to the general purpose registers 16. In the tag register 30, the tag bits corresponding to general purpose register Nos. (for example) 4, 5, and 8 in the group 16 of the general purpose registers, which are expected to be the address registers for registering memory addresses for accessing the VM regions 41, are preliminarily made "1". The tag bits of the tag register 30 are selected by the selector 33 under the control of the address register designation part 19. Based on this selection, the designation, by the address register designation part 19, of one of the general purpose registers designated by the tag register 30 is detected. The switching portion 37 is controlled by the output of the selector 33, and the access key 25A' of the virtual machine computation function system is transmitted to the output terminal of the selector 27. During the execution of the VM monitor region 42, usually the data "0" is supplied as an access key to the access control portion 10. Only when the general purpose register designated by the tag register 30 is designated as an address register for generating an access address, is a switching to the access key 25A' of the virtual machine computing function system carried out. The access control portion 10 carries out an access control on the basis of the access key supplied from the selector 27. In the operation of the system of Fig. 5, the tag register 30 has tag bites corresponding to the general purpose registers. In the tag register 30, predetermined bits are preliminarily set by the VM monitoring region 42. During the execution of the VM monitoring region, usually the access key "0" is delivered from the selector 27. When the designation, by the address register designation part 19, of the general purpose register designated by the tag register 30 is detected, a switching is carried out to deliver the access key 25A' from the selector 27. As explained above, in an embodiment of the invention a main storage access control system for a virtual computing function system includes an address register for registering memory addresses used for accessing a main storage and being operated under a plurality of address modes having different effective bit lengths concerning the memory addresses, a tag register for registering tag bits for individually designating the address registers, and a selection unit for selecting the designation of address registers designated by the tag bits by means of an operand address for an instruction which is to be executed by the program of the virtual machine monitoring region. The address mode is changed to the address mode used by the virtual computing function system by means of the output signal of the selection means.

Claims: A main storage access control system for a virtual computing function system, including a central processing unit (1) and a main storage (4), executing programs stored in virtual machine regions (41) and a virtual machine monitoring region (42) of the main storage, the programs including instructions with an address register designating portion, said central processing unit of said system comprising: an instruction register (18); address registers arranged in two groups of general purpose registers (14, 16) in the central processing unit (1), used for calculating memory addresses for accessing the main storage (4), each group of said address registers being operated under a respective one of two address modes for memory addresses having different effective bit lengths, the address register designating portion of the instructions designating one of the general purpose registers (14, 16); an access control portion (10) receiving the contents of the selected general purpose register; a first program status word (PSW) register (15) for virtual machine monitoring, and a second PSW register (25) for a virtual machine, each of said PSW registers having a respective address mode designation portion (15A, 25A); a selection (27) for supplying to said access control portion (10) either the address mode designation portion (25A) of the second PSW register, on a second signal, said selection being controlled by a virtual machine latch (22) for indicating virtual machine monitoring running; characterised by: a tag register (30) for registering tag bits indicating a mode of use of said address registers, each bit position of said tag register corresponding to one of the general purpose registers (16) of the group operating during virtual machine monitoring, the address register designating portion of the instructions designating one of the tag bits of said tag register, the tag bits having a predetermined value corresponding to ones of said general purpose registers (16) which are expected to be the address registers for registering memory addresses for accessing the virtual machine regions (41), said tag bits being preliminarily set to a predetermined value (e.g. "1") by said virtual machine monitoring region (42); and selection means (31) in the central processing unit (1), receiving the address mode designation portions (15A, 25A) of both the first and second PSW registers (15, 25), connected to said tag register (30), for generating said second signal selecting the mode of use of the one of said address registers (14, 16) designated by the address designating portion of one of the instructions in dependence upon the one of the tag bits corresponding thereto by means of an operand address of one of the instructions to be executed by a said program stored in a said virtual machine monitoring region (41), the mode of use of said address registers being determined by the second signal of said selection means (31); wherein said selection means selects the mode of use of said designated one of said address registers of the group operating during virtual machine monitoring by using the address mode designation portion (25A) of said second PSW register (25), even when said virtual machine latch (22) indicates virtual machine monitoring running.

Inventors: MATSUMOTO, TOSHIO
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G06F12
IPC codes: G06F12