FDM-TDM TRANSMULTIPLEXING SYSTEM

Abstract: An FDM-TDM transmultiplexing system for a modulation/­ demodulation device which is applicable to a regenerative re­ peating system of a satellite or a ground radio communication system is disclosed which uses chirp-z-transform. A chirp fil­ ter (102) is implemented with a digital circuit. The circuit scale of the digital chirp filter (102) increases in proportion to a square root of the total number of channels N, enhancing min­ iaturization of an FDM-TDM transmultiplexer (100A).

Description: The present invention relates to a frequency-division-multiplexing (FDM)-time-division-multiplexing (TDM) transmultiplexing system applicable to a regenerative repeating system which is associated with a satellite or a ground radio communication system. In parallel with the advance of digital communication technologies, the demand for an FDM-TDM transmultiplexer which interconnects the conventional FDM analog modulated signal system and the TDM digital signal system is increasing. As regards satellite communications, there is an increasing demand for a modulation/demodulation device capable of performing FDM-TDM conversion on board a satellite in order to transmultiplex traditional single channel per carrier (SCPC) signals and modern TDMA signals. Further, because the data rate becomes diversified with the evolution of mobile communication and business communication, a group modulation/demodulation device to be loaded has to meet requirements not only in the aspect of performance but also in that of flexibility of functions. Today, a Fast Fourier Transform (FFT)-filter method and a chirp-z-transform method are available as FDM-TDM transmultiplexing implementations. In the chirp-z-transform method, a chirp filter and a chirp signal generator have heretofore been implemented with Surface Acoustic Wave (SAW) elements. This is disadvantageous, however, since the delay time which is attainable with SAW elements is limited and, therefore, it is difficult for FDM-TDM translation to be achieved on slow signals, i.e. signals in a narrow frequency band. Concerning matching between the chirp signal generator and the chirp filter, should it be distorted, time separation between channels would be effected to bring about crosstalk between the channels. This would result in fluctuations in the characteristics of the SAW elements due to temperature as well as in long-term fluctations, deteriorating characteristics as a whole. Especially, a transmultiplexer needs an utmost stability since it is expected to process a great number of signals collectively. Concerning business communication, on the other hand, while a plurality of data rates have to be accommodated, the chance for the method using SAW elements to successfully realize a required degree of flexibility is scarce. Meanwhile, the FFT-filter method is implemented with digital circuits only and, therefore, very stable in characteristics. Although the FFT-filter method has been extensively applied to a transmultiplexer for the above reason, for N channels it requires an N-point FFT circuit and N digital subfilters with the result that the circuit is scaled up in proportion to the number of channels N. It is therefore an object of the present invention to provide an improved FDM-TDM transmultiplexing system which shows stable characteristics, is capable of accommodating various data rates, and which is feasible for miniaturization. These objects are solved with the features of the claim. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings, in which Figs. 1A and 1B are block diagrams respectively showing an FDM-TDM multiplexer and a TDM-FDM multiplexer which use the prior art FFT-filter method; Figs. 2A and 2B are block diagrams respectively showing an FDM-TDM multiplexer and a TDM-FDM multiplexer which use the prior art chirp-z-transform method; Figs. 3A to 3E are timing charts representative of operation of the FDM-TDM multiplexer which is shown in Fig. 2A; Figs. 4A to 4C are timing charts demonstrating a situation wherein crosstalk is caused by distortions of matching of the FDM-TDM multiplexer as shown in Fig. 2A; Figs. 5A and 5B are block diagrams respectively showing an FDM-TDM multiplexer and a TDM-FDM multiplexer embodying the present invention; Fig. 6 is a block diagram showing a specific construction of a chirp filter or that of a chirp signal generator which is included in the embodiment of Figs. 5A and 5B; and Figs. 7A and 7B are block diagrams respectively showing specific constructions of a complex constant multiplier and an M-input adder of Fig. 6. To better understand the present invention, a brief reference will be made to a prior art FDM-TDM transmultiplexing system, shown in the drawings. First, the prior art FFT-filter method which is one of prior art FDM/TDM transmultiplexing approaches will be described with reference to Figs. 1A and 1B. Specifically, an FDM-TDM multiplexer is shown in Fig. 1A and a TDM-FDM multiplexer in Fig. 1B. The FDM-TDM multiplexer of Fig. 1A, generally 10A, consists of a timing generator 12, mixers 14 and 16, a local oscillator 18, a π/2 phase shifter 20, analog-to-digital (AD) converters 22 and 24, a serial-to-parallel (SP) converter 26, N digital filters 28(1) to 28(N), and an N-point FFT circuit 30. Here, N is representative of the total number of channels. Likewise, a TDM-FDM multiplexer of Fig. 1B, generally 10B, consists of an N-point inverse FFT circuit 32, digital filters 34(1) to 34(N) which are matched with the digital filters 28(1) to 28(N), a PS converter 36, digital-to-analog (DA) converters 38 and 40, a π/2 phase shifter 42, a local oscillator 44, mixers 46 and 48, and a signal combining circuit 50. As for the operation of a transmultiplexer having such a construction, a reference may be made to "TDM-FDM Transmultiplexing: Digital Polyphase and FFT", IEEE Transactions on Communications, Vol. Com-22, No. 9, September 1974. Referring to Figs. 2A and 2B, the principle of chirp-z-transform is shown. Fig. 2A shows an FDM-TDM multiplexer and Fig. 2B a TDM-FDM multiplexer. In Fig. 2A, the FDM-TDM multiplexer 60A consists of a chirp filter 62, a chirp signal generator 64, a pulse generator 66, mixers 68, 70 and 72, a local oscillator 74, and a low-pass filter (LPF) 76. Likewise, the TDM-FDM multiplexer 60B of Fig. 2B consists of a chirp filter 78, a chirp signal generator 80, a pulse generator 82, mixers 84, 86 and 88, and a local oscillator 90. Details of operation of the transmultiplexer which uses chirp-z-transform are described in "Real Time Network Analyzer Employing Surface Acoustic Wave Chirp Filters", 1975 Ultrasonics Symposium Proceedings, IEEE Cat 75 CHO 994-4SU. Referring to Figs. 3A to 3E and 4A to 4C, there are demonstrated normal and abnormal operating conditions of the circuitries as shown in Figs. 2A and 2B. In these drawings, the ordinate is representative of a frequency axis and the abscissa the time axis. Assume that the pulse generator 66 has generated a sequence of impulses having a period T. As the impulse sequence is applied to the chirp signal generator 64, a repetitive signal appears at the output of the chirp generator 64, as shown in Fig. 3B. An input FDM signal is multiplied by the chirp signal in the multiplier 70 and, thereby, chirp-modulated as shown in Fig. 3C. The chirp signal is an FM signal the frequency of which sequentially lowers with the lapse of time. The chirp filter 62, on the other hand, is matched with the chirp signal generator 64 and has a group delay characteristic which increases with frequency. Hence, as shown in Fig. 3D, the chirp filter 62 produces a signal sequence which is separated channel by channel with respect to time. In this instance, the waveform of each of the discrete signals is expressed as where µ is a chirp rate and F a total frequency sweeping width. The width of 1/F substantially constitutes a pulse. In order that signal pulses on N channels may be provided during a time period T, the pulse width has to be smaller than T/N and this requires conditions F ≧ N·R Eq. (2) µ = πFR ≧ πNR² Eq. (3) where R is a baud rate of signals which is represented by R = 1/T Eq. (4) It has been customary to use SAW elements as the chirp filter 62 and chirp signal generator 64. With SAW elements, however, the delay time available is limited so that it is difficult to accomplish FDM-TDM multiplexing on slow signals, i.e., signals lying in a narrow frequency band, as previously discussed. As regards matching between the chirp signal generator 64 and the chirp filter 62, should it be distorted, time separation between channels would be effected to bring about crosstalk between the channels, as shown in Fig. 4C. This would result in fluctuations in the characteristics of the SAW elements due to temperature as well as in long-term fluctuations, deteriorating characteristics as a whole. Especially, a transmultiplexer needs an utmost stability since it is expected to process a great number of signals collectively. Concerning business communication, on the other hand, while a plurality of data rates have to be accommodated, the chance for the method using SAW elements to successfully realize a required degree of flexibility is scarce. Meanwhile, the FFT-filter method as shown in Figs. 1A and 1B is implemented with digital circuits only and, therefore, very stable in characteristics. Although the FFT-filter method has been extensively applied to a transmultiplexer for the above reason, for N channels it requires an N-point FFT circuit and N digital subfilters with the result that the circuit is scaled up in proportion to the number of channels N, as also previously described. The present invention contemplates to eliminate the drawbacks particular to the prior art schemes as stated above. Specifically, the present invention is directed to implementing the chirp filter with a digital circuit construction. Assume that an input FDM signal is made up of N frequency-multiplex signals which were subjected to FDM at frequency intervals of Δf. Assuming that N is a square number, it is represented by N = M² Eq. (5) where M is an integer. If N is not a square number, then M = [√N] + 1 Eq. (6) where the parenthesized term is representative of an integer part. The resultant degree of increase of sampling frequency becomes smaller relative to N if the latter is large. The sampling frequency necessary for signals in a band width which is expressed as F = N·Δ f = M²Δ f Eq. (7) to be complex-sampled may be F (Hz). At this instant, the impulse response of a chirp filter is produced by Assuming that the chirp ratio is the minimum value as provided by the Eq. (3), i.e., µ = π·N( Δf )² Eq. (9) then Dividing it into M subfilters, the impulse response is represented by In this instance, there holds an equation It will be seen from the above that M = √N digital tank groups suffice for the chirp filter to be completed. In the above equations, m is equal to 0, 1, 2, ..., M-1. Further, as shown in Figs. 3A to 3E and 4A to 4C, it is essential that the impulse response of a chirp signal generator be provided not only with an opposite characteristic to the Eq. (10) which is representative of a chirp filter but also with a response of finite length. Specifically, the impulse response of a chirp signal generator is produced by where In the Eq. (16), the overline signifies a complex pair. By constructing a digital circuit as stated above, it is possible to produce a chirp signal generator with an impulse response which accurately has a finite length. It is important to note that the circuit scale of the digital chirp filter increases in proportion to the square root of N, the total number of channels. Hence, even if N is increased, the circuit scale does not increase so much. Referring to Figs. 5A and 5B, an FDM-TDM multiplexer and a TDM-FDM multiplexer in accordance with the transmultiplexing system of the present invention are shown. As shown in Fig. 5A, the FDM-TDM multiplexer 100A comprises a digital chirp filter 102, a digital chirp signal generator 104, a timing generator 106, mixers 108 and 110, a local oscillator 112, a π/2 phase shifter 114, LPFs 116 and 118, AD converters 120 and 122, complex multipliers 124 and 126, and digital-to-analog (DA) converters 128 and 130. As shown in Fig. 5B, the TDM-FDM multiplexer 100B comprises AD converters 132 and 134, multipliers 136 and 138, a timing generator 140, a chirp filter 142, a chirp signal generator 144, DA converter 146 and 148, a local oscillator 150, a π/2 phase shifter 152, mixers 154 and 156, and an intermediate frequency (IF) signal combining circuit 158. The various components of the TDM-FDM multiplexer 100B each functions in the opposite direction to the associated component of the FDM-TDM multiplexer 100A. The operations of the multiplexers 100A and 100B are basically the same as those shown in the flowcharts of Figs. 3A to 3E. Referring to Fig. 6, a specific construction of the chirp filter 102 or 142 in accordance with the embodiment of Figs. 5A and 5B is shown. As shown, the chirp filter 102 or 142 includes M subfilters 160(0), ..., 160(m), ..., 160(M-1) each of which is constructed according to the Eq. (12) or (16). Each subfilter consists of an adder 162, a complex constant multiplier 164, an M-stage buffer memory 166, an M²-stage buffer memory 168, and an adder 170. The chirp filter 102 or 142 further includes sample delay elements 172(0), ..., 172(m), ..., 172(M-1) which are made up of 0, ..., m, ..., (M-1) sample delay elements. Designated by the reference numeral 174 is an M-input adder. It is to be noted that when connected as indicated by a dotted line in Fig. 6 the subfilters serve the function of chirp signal generators. Figs. 7A and 7B respectively show specific constructions of the complex constant multiplier 164 and M-input adder 174 which are included in the chirp filter of Fig. 6. Assume that by the constructions shown in Figs. 7A and 7B there are performed complex constant operations: where α and β are constants. The multiplier 164 as shown in Fig. 7A consists of constant α multipliers 174(1) and 174(4), constant β multipliers 174(2) and 174(3), and adders 174(5) and 174(6). The constant multipliers can be implemented with read only memories (ROMs) to enhance the simplicity of construction as well as the computation rate. As shown in Fig. 7B, the M-input adder 174 may generally be comprised of less than M adders 176(1) to 176(7). The construction shown in Fig. 7B is representative of a case wherein M is "8". As described above, the chirp filter in accordance with the present invention generally has a pipeline structure and can operate at a high speed. Although only the subfilters (digital tank) 160(0), ..., 160(m), ..., 160(M-1) are provided with feedback loops, high-speed operations are readily achieved due to the buffering function of the memory buffers 166. Further, systems with different data rates can be accommodated with ease merely by switching the ROMs and changing the sampling frequency. In summary, it will be seen that the present invention provides an FDM-TDM transmultiplexing system which is feasible for miniaturization since the circuit scale increases in proportion to the square root of the number of channels N. Moreover, the system is implemented with digital multiplexing functions which enhance stability with respect to characteristics and promotes the ease of adaptation to various data rates. Thus, the system is desirably applicable to a regenerative repeating system for ground and satellite communications which are increasingly diversified for business and mobile applications.

Claims: A frequency-division-multiplexing (FDM)-time-division-multiplexing (TDM) transmultiplexing system having an FDM-TDM multiplexer (100 A) and a TDM-FDM multiplexer (100 B), said FDM-TDM multiplexer (100 A) comprising: a complex frequency conversion circuit (108-114) for converting a frequency of an input signal by converting the input signal into a complex signal of a baseband; a first and a second analog-to-digital (AD) converter (120, 122) for respectively digitizing two signal sequences which are outputted by said complex frequency conversion circuit (108-114) and comprised of a real part and an imaginary part; a first chirp signal generator (104) consisting of M digital subfilters which, for a minimum square number (M²) greater than a required total number of channels, operate based on a principle of digital chirp filter; a first complex multiplier (124) for multiplying outputs of said first and second AD converters (120, 122) and an output of said first chirp signal generator (104); a first chirp filter (102) consisting of M digital subfilters (160) which, for the minimum square number (M²) greater than the required total number of channels, operate based on the principle of digital chirp filter so as to perform a convolutional integration matched to said first chirp signal generator (104) in response to an output of said first complex multiplier (124); a second complex multiplier (126) for multiplying an output of said first chirp filter (102) and an output of said first chirp signal generator (104); and a first and a second digital-to-analog (DA) converter (128, 130) for respectively analogizing two signal sequences which are outputted by said second complex multiplier (126); said TDM-FDM multiplexer (100 B) comprising: a third and a fourth AD converter (132, 134) for respectively digitizing analog input signals which are in time-divided two sequences; a second chirp signal generator (144) having the same construction as said first chirp signal generator (104); a third complex multiplier (136) for multiplying outputs of said third and fourth AD converter (132, 134) and an output of said second chirp signal generator (144); a second chirp filter (142) constructed in the same manner as said first chirp filter (102) to perform a convolutional integration matched to said second chirp signal generator (144) in response to an output of said third complex multiplier (136); a fourth complex multiplier (138) for multiplying an output of said second chirp filter (142) and an output of said second chirp signal generator (144); a third and a fourth DA converter (146, 148) for respectively analogizing two signal sequences which are outputted by said fourth complex multiplier (138); and a complex frequency conversion circuit (150-156) for converting frequencies of two signal sequences which are outputted by said third and fourth DA converter (146, 148), respectively.

Inventors: ICHIYOSHI, OSAMU C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H04J4
IPC codes: H04J1, H04J4