SEMICONDUCTOR DEVICES EMPLOYING CONDUCTIVITY MODULATION

Abstract: A semiconductor device, e.g. a lateral DMOS transistor or bipolar transistor, has a main current path (20) extending through a high resistivity body portion (1) of one conductivity type. A minority-carrier injector region (6) which may be of the opposite conductivity type is provided in the body portion (1) in the vicinity of the current path (20) and serves with an applied forward-bias to inject minority charge carriers (16) which are characteristic of the opposite conductivity type into the body portion (1) to modulate the conductivity of the current path (20). In accordance with the invention one or more further regions (8) of the opposite conductivity type are located in the part of the body portion (1) in the vicinity of the current path (20) and within a minority-carrier diffusion length of the injector region (6) and/or of each other. These further regions (8) float at a potential dependant on the minority-carrier injection (16) from the injector region (6) and serve to inject minority charge carriers (18) into areas of the body portion (1) remote from the injector region (6) so as to modulate the conductivity of these areas of the current path (20). The floating regions (8) may be located within the spread of a depletion layer (50) from a reverse-biased p - n junction (2) to increase the breakdown voltage of the junction (2). The body portion (1) may be, e.g., a MOST drain drift region or a bipolar transistor collector region or a thyristor base region.

Description: This invention relates to semiconductor devices comprising insulated gate field effect transistors, for example, lateral field-effect transistors of the DMOS type, employing conductivity modulation and relates particularly but not exclusively to such devices designed for high voltage operation. European patent application (EP-A) 0 115 098 discloses a semiconductor device comprising an insulated gate field effect transistor having a semiconductor body with a body portion forming a drain drift region of one conductivity type. A current path extends through the drain drift region to a conduction channel region of the insulated gate field effect transistor. A minority-carrier injector region forms a barrier with the drain drift region in the vicinity of the current path, and there is an electrical connection to the injector region for applying a voltage to the injector region to forward-bias the barrier whereby minority charge carriers characteristic of the opposite conductivity type are injected into the drain drift region to modulate the conductivity of the drain drift region. The device disclosed in EP-A 0 115 098 is an insulated-gate field-effect transistor of the lateral DMOS type. The drain drift region is of high resistivity and is formed by an epitaxial layer of one conductivity type on a substrate of the opposite conductivity type. A source region of said one conductivity type is provided in a device region of said opposite conductivity type. This device region provides the transistor conduction channel region below an insulated gate and forms with the drain drift region a p - n junction which is reverse-biased in operation. The injector region serves to inject minority carriers into the drain drift region when the transistor is in the on state, thus resulting in more carriers characteristic of said one conductivity type being emitted from the source region to maintain charge neutrality in the drain drift region. In this manner, the conductivity of the drain drift region is modulated resulting in a substantial reduction in the on-resistance of the device which would otherwise be high due to the high resistivity of the drain drift region. This reduction in on-resistance is achieved without degrading the breakdown voltage characteristics of the device. However, because the transistor is of the lateral type, the current path between source and drain regions extends over a significant length in the high resistivity epitaxial layer forming the drain drift region. This geometrical layout of the regions of the device confines the conductivity modulation to an area close to the injector region because injected minority carriers are removed by both the upper major surface of the epitaxial layer and by the underlying substrate. Furthermore to obtain good isolation between the active device area and the substrate the minority-carrier diffusion length in the epitaxial layer needs to be short compared with the thickness of the layer. Therefore the conductivity modulation may be ineffective over part of the current path in the drain drift region. The transistor of EP-A 0 115 098 is a four terminal device, as an extra terminal is provided for the electrical connection to the injector region. According to the present invention there is provided a semiconductor device comprising an insulated gate field effect transistor and having a semiconductor body with a body portion forming a drain drift region of one conductivity type, a drain region of said one conductivity type, a current path extending from said drain region through the drain drift region to a conduction channel region underlying an insulated gate of the transistor, a minority-carrier injector region forming a barrier with the drain drift region in the vicinity of the current path, and an electrical connection to the injector region for applying a voltage to the injector region to forward-bias the barrier whereby minority charge carriers characteristic of the opposite conductivity type are injected into the drain drift region to modulate the conductivity of the drain drift region, characterised in that at least one further region of said opposite conductivity type is present in a part of the drain drift region separating the conduction channel region from the injector region and in the vicinity of the current path through the drain drift region so as to be spaced from the injector region by a distance which is at most twice a carrier diffusion length for the minority charge carriers in the drain drift region, which further region floats at a potential dependent on the minority-carrier injection from the injector region and serves to inject minority charge carriers which are characteristic of said opposite conductivity type into an area of the drain drift region remote from the injector region. By providing in this manner at least one such further region in the vicinity of the current path in a device in accordance with the invention the minority-carrier injection is spread from the vicinity of the injector region into an area of the drain drift region remote from the injector region, so providing conductivity modulation of the current path in that area. The invention may be used to provide conductivity modulation in areas of the drain drift region even further remote from the injector region. Thus, the further region may be one of a plurality of further regions of the opposite conductivity type which are present in a part of the drain drift region separating the conduction channel region from the injector region and in the vicinity of the current path through the drain drift region so as to be spaced from each other by at most twice a carrier diffusion length for the minority charge carriers in the drain drift region, which further regions float at potentials dependent on the minority-carrier injection from the injector region and serve to inject minority charge carriers into areas of the drain drift region remote from the injector region. This permits the on-resistance of the device resulting from even a long current path in the drain drift region to be significantly reduced, even when the drain drift region has a high resistivity to provide a high breakdown voltage and has a short diffusion length to improve isolation or to increase speed of operation. The invention can be used to considerable advantage in reducing the on-resistance of a device wherein the drain drift region is of higher resistivity than a device region of said opposite conductivity type which forms a p - n junction with the drain drift region, for example as in a DMOS type insulated gate field effect transistor, wherein the p - n junction is reverse-biased in at least one mode of operation of the device, and wherein said one or more further regions are located within the spread of a depletion layer which extends in the drain drift region from the p - n junction when reverse-biased in said at least one mode of operation. By locating the one or more further regions in this manner, these further regions can serve not only in injecting minority carriers to reduce the on-resistance but also in controlling the spread of the depletion layer to reduce high electric fields and so to increase the breakdown voltage associated with the reverse-biased p - n junction. A wide variety of arrangements and geometries can be adopted for the minority-carrier injector region, the one or more further regions and (where applicable) said device region of said opposite conductivity type so that a particular arrangement compatible with the desired geometry and characteristics of a particular semiconductor device can be adopted. In devices of the lateral type having a first and second electrode connections at one major surface of the body, the current path in the drain drift region may have a significant length and the drain drift region may have a high resistivity to provide a high breakdown voltage. In this situation it is particularly advantageous to obtain a progressive spatial spread of (either or both) the minority-carrier injection and electrical field. In order to achieve this, at least some of said further regions may be arranged successively in a series extending away from the barrier formed by the injector region and/or from the p - n junction formed by the device region, successive regions of said series being spaced by at most twice said minority-carrier diffusion length from each other. When a series of such further regions is provided within the spread of a depletion layer from a reverse-biased p - n junction to increase the breakdown voltage, a particularly uniform spread of the depletion layer laterally around the p - n junction can be obtained when, in plan view, said further regions are part of an annular region structure arranged concentrically around said device region forming the p - n junction. Depending on the particular semiconductor device the injector region may be a metal layer which forms a Schottky barrier with the semiconductor material at the body surface. However, in most devices the minority-carrier injector region may be formed by a region of said opposite conductivity type in the body and forming a p - n junction barrier with the drain drift region. In order to simplify the electrode arrangement, the electrode connection to the injector region may also form a drain electrode connection of the transistor. Embodiments of the invention will now to be described, by way of example, with reference to the accompanying diagrammatic drawings, in which: Figure 1 is a plan view of part of an insulated-gate field-effect transistor in accordance with the invention; Figure 2 is a cross-section of the transistor of Figure 1, taken on the line II-II of Figure 1 and illustrating minority-carrier injection with the transistor in its on state; Figure 3 is the cross-section of Figure 2 but illustrating the depletion-layer spread with the transistor in its blocking state; and Figure 4 is a plan view of part of a device in accordance with the invention for illustrating a different geometric layout. It should be noted that all of the Figures are diagrammatic and not drawn to scale. The relative dimensions and proportions of parts of these Figures (particularly some of the thicknesses) have been shown exaggerated or diminished for the sake of clarity and convenience in the drawings. The same reference signs as used in one embodiment are generally used when referring to corresponding or similar parts in other embodiments. The device of Figures 1 to 3 comprises an insulated gate field effect transistor and has a semiconductor body 10, for example of monocrystalline silicon, with a body portion 1 forming a drain drift region of one conductivity type ( n type, in this example). Only a central area of the body 10 is shown in the Figures. A current path 20 extends through the drain drift region 1 (see Figure 2) to a conduction channel region of the insulated gate field effect transistor. In this example the current path 20 extends between first and second electrodes 11 and 12 and also extends through device regions 3, 4 and 5. The device further comprises a minority-carrier injector region 6 forming a barrier 7 with the drain drift region 1 in the vicinity of the current path 20; in this example the injector region 6 is a semiconductor region of opposite conductivity type ( p type) which is located in the drain drift region 10 and forms a p - n junction barrier 7. There is an electrical connection to the injector region 6 for applying a voltage to the injector region 6 to forward-bias the barrier 7 whereby minority charge carriers (holes, in this example; i.e. characteristic of the opposite conductivity type which is p type in this example) are injected into the drain drift region 1 (as denoted by arrows 16) to modulate the conductivity of the current path 20; in this example, the electrode arrangement is simplified by employing the electrode connection 12 of the device region 5 to provide also the connection to the injector region 6. Further regions 8 of said opposite conductivity type ( p type, in this example) are located in a part of the drain drift region 1 separating the conduction channel region from the injector region 6 and in the vicinity of the current path 20 and are spaced from the injector region 6 or from each other by distances which are at most twice a carrier diffusion length (L) for minority charge carriers in the drain drift region 1. The further regions 8 which form p - n junctions 9 with the body portion 1 have no electrical connections and float at a potential dependent on the minority-carrier injection 16 from the injector region 6. These further regions 8 serve to inject minority carriers (as denoted by arrows 18 in Figure 2) into areas of the drain drift region 1remote from the injector region 6. In this manner, conductivity modulation can occur over the whole length of the current path 20 in the drain drift region 1, i.e. both in the vicinity of and remote from the injector region 6. The device region 3 of said opposite conductivity type (p type in this example) forms with the drain drift region 1 a p - n junction 2 which is reverse-biased in one mode of operation of the device, i.e. a voltage blocking mode illustrated in Figure 3. In this mode the p - n junction 2 blocks a high voltage applied between the electrodes 11 and 12, the voltage drop being carried largely by the spread of a depletion layer 50 in the drain drift region 1. The drain drift region 1 has a significantly higher resistivity than the region 3 so as to carry this voltage drop. The one or more further regions 8 are located within the spread of this depletion layer 50 in the drain drift region 1 from the p - n junction 2 and so the regions 8 serve to relieve high electric fields in the depletion layer 30 thereby increasing the breakdown voltage of the junction 2. The device of Figures 1 to 3 is an insulated-gate field-effect transistor of the lateral DMOS type. The drain drift region 1 is lowly doped (denoted N- in Figures 1 to 3) and is present as an epitaxial layer on a p type substrate 21. There is an electrode connection 22 to the back of the substrate 21 which may be connected to the same potential as the first, that is the source,electrode 11. The regions 3, 5, 6 and 8 are formed by local doping of the layer 1 in known manner using conductivity type determining impurities. The region 5 is a highly doped drain region of the transistor (denoted N+ in Figures 1 to 3). A highly doped n type source region 4 is provided in the p type device region 3. At the surface of the layer 1 there is an insulating and passivating layer 15 having contact windows for the electrodes 11 and 12. A gate electrode 13 present on a thin part of the insulating layer 15 overlies part of the region 3 which forms the conduction channel region between the source region 4 and the drain drift region and thus forms part of the source to drain current path 20. This electrode 13 is shown in broken outline in Figure 1. In the absence of a signal applied to the gate 13 the transistor will block voltages applied between the source and drain electrodes 11 and 12 as illustrated in Figure 3. Reference 50 denotes the depletion layer from the reverse-biased p - n junction 2, whereas reference 51 denotes the depletion layer from the reverse-biased junction between the layer 1 and the substrate 21. When a signal above the threshold voltage is applied to the gate 13 the transistor is turned on and majority carriers (electrons) flow out of the source region 4 into the drain drift region 1. This is accompanied by minority carrier injection 16 and 18 which reduces the on-resistance of the device by reducing the resistivity along the length of the path 20 in the layer portion 1. The electrical connections to the electrodes 11, 12, 13 and 22 are designated as S, D, G and SS in Figures 2 and 3. Four floating regions 8 are illustrated by way of example in Figures 1 to 3. These four regions 8 are arranged successively in a series extending in one direction away from the barrier 7 formed by the minority-carrier injector region 6 and in the opposite direction away from the p - n junction 2 formed by the device region 3, see Figure 1. Successive regions 8 of this series are spaced from each other by at most 2.L (twice a minority-carrier diffusion length L in the layer portion 1). With the simple one-sided transistor geometry illustrated in Figure 1 the floating regions 8 may simply be straight parallel stripes as illustrated in the plan view of Figure 1. In a specific example of the transistor of Figures 1 to 3, the n type layer portion may have a resistivity of 40 ohm.cm. and a minority-carrier diffusion length of 10 µm (micrometres) which may be obtained by, for example, proton bombardment. The regions 3, 6 and 8 may be 10 µm deep. To improve the device isolation the epitaxial layer 1 may be several diffusion lengths thick, for example 50 µm thick. The device region 3 may be 90 µm long by 60 µm wide, each of the floating regions 8 may be 100 µm long by 15 microns wide, the injector region 6 may be 100 µm long by 25 µm wide and the regions 8 may be spaced from each other and from the regions 3 and 6 by areas of the n type layer portion 1 each of which is 15 µm wide, i.e. 1½ times the diffusion length L. The insulating and passivating layer 15 outside the area below the gate 13 may comprise, for example oxygen-doped semi-insulating polycrystalline silicon over silicon dioxide. It will be evident that other dimensions may be adopted and many modifications are possible. Thus, for example, the efficiency of the minority carrier injection 18 can be increased by reducing the spacing of the regions 8 and 6, for example to a carrier diffusion length L or less, and the spacing may vary for the different regions 8 in the different areas to control the injection 18 in these areas according to an optimum pattern along the current path 20. However, the spacing should not be too large (i.e. not greater than 2.L) or the efficiency of minority-carrier collection and reinjection by the regions 8 will be so poor as to have a negligible conductivity modulation effect in that area. The minority-carrier injector region 6 may be broken up into more than one region 6 all of which may still be contacted by the electrode 12. Furthermore, instead of each successive floating region 8 in the series being a single continuous stripe, each stripe may be broken up in its direction of length so as to form a two-dimensional array of floating regions 8 between the device region 3 and injector region 6 or regions 6. A larger or smaller number of floating regions 8 may be provided in the series, or in some devices it may be sufficient to provide merely one floating region 8 of appropriate shape. Figure 4 illustrates another possibility in which the floating regions 8 in the series are part of an annular structure 8, 8 a arranged concentrically around the device region 3. By comparison with Figures 1 to 3, the single region 30 shown schematically in Figure 4 indicates the location of the drain region 5 and injector region 6 of the lateral DMOS transistor of Figures 1 to 3. In this example there are two rings shown each of which is broken up in its direction of length so that the part 8 of each ring between the device region 3 and the injector region 6 is discontinuous with the remainder 8 a of the ring . This discontinuity ensures that most of the minority-carrier injection 18 and resulting conductivity modulation occurs in the active device area between the regions 3 and 6, whereas the annular region structure 8 and 8 a enhances the breakdown voltage of the p - n junction 2 by encouraging a uniform spread of the depletion layer 50 laterally around the junction 2 in the voltage blocking condition. The blocking characteristics of reverse-biased p - n junction 2 can also be enhanced by reducing the nett doping concentration of the floating regions 8 (and 8 a , if present) to such a level that they become significantly depleted by the depletion layer 50. Thus, a major part of each region 8 may be depleted in this manner. Furthermore, instead of a monocrystalline epitaxial layer 1 on a monocrystalline semiconductor substrate 21, the semiconductor body porton 1 of a device in accordance with the invention may be formed more cheaply as a semiconductor layer (for example of polycrystalline or amorphous semiconductor material) on a substrate 21 which is of electrically insulating material at least adjacent the semiconductor layer 1. Although such a layer 1 may have a low minority-carrier diffusion length, the use of the present invention still permits conductivity modulation to be achieved along the whole current path 20.

Claims: A semiconductor device comprising an insulated gate field effect transistor and having a semiconductor body with a body portion forming a drain drift region of one conductivity type, a drain region of said conductivity type, a current path extending from said drain region through the drain drift region to a conduction channel region underlying an insulated gate of the transistor, a minority-carrier injector region forming a barrier with the drain drift region in the vicinity of the current path, and an electrical connection to the injector region for applying a voltage to the injector region to forward-bias the barrier whereby minority charge carriers characteristic of the opposite conductivity type are injected into the drain drift region to modulate the conductivity of the drain drift region, characterised in that at least one further region of said opposite conductivity type is present in a part of the drain drift region separating the conduction channel region from the injector region and in the vicinity of the current path through the drain drift region so as to be spaced from the injector region by a distance which is at most twice a carrier diffusion length for the minority charge carriers in the drain drift region, which further region floats at a potential dependent on the minority-carrier injection from the injector region and serves to inject minority charge carriers which are characteristic of said opposite conductivity type into an area of the drain drift region remote from the injector region. A device as claimed in Claim 1, further characterised in that said one further region is one of a plurality of further regions of said opposite conductivity type which are located in a part of the body portion in the vicinity of the current path and which are spaced from each other by at most twice a carrier diffusion length for the minority charge carriers in the body portion of said one conductivity type, which further regions float at potentials dependant on the minority-carrier injection from the injector region and serve to inject minority charge carriers into areas of the body portion of said one conductivity type remote from the injector region. A device as claimed in Claim 2, further characterised in that at least some of said further regions are arranged successively in a series extending away from the barrier formed by the injector region, successive regions of said series being spaced by at most twice said minority-carrier diffusion length from each other. A device as claimed in anyone of the preceding Claims, further characterised in that a device region of said opposite conductivity type forms a p - n junction with the body portion of the one conductivity type, in that the body portion is of higher resistivity than the device region, in that the p - n junction is reverse-biased in at least one mode of operation of the device, and in that said one or more further regions are located within the spread of a depletion layer which extends in the body portion from the p - n junction when reverse-biased in said at least one mode of operation. A device as claimed in Claim 4, further characterised in that at least some of said further regions are arranged successively in a series extending away from the p - n junction formed by the device region, successive regions of said series being spaced by at most twice said minority-carrier diffusion length from each other. A device as claimed in Claim 5, further characterised in that, in plan view, said further regions are part of an annular region structure arranged concentrically around said device region of said opposite conductivity type. A device as claimed in any one of the preceding claims, further characterised in that the electrode connection to the injector region also forms a drain electrode connection of the transistor. A device as claimed in any one of the preceding Claims, further characterised in that the body portion of the one conductivity type is a semiconductor layer on a substrate. A device as claimed in Claim 8, further characterised in that the substrate is of electrically insulating material at least adjacent the semiconductor layer. A device as claimed in Claim 9, further characterised in that the semiconductor layer comprises polycrystalline or amorphous semiconductor material.

Inventors: SHANNON, JOHN MARTIN
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN, PHILIPS ELECTRONICS UK LIMITED
Application year: 1986
Main classification: H01L29
IPC codes: H01L27, H01L21, H01L29