HETEROJUNCTION BIPOLAR INTEGRATED CIRCUIT

Abstract: A heterojunction bipolar integrated circuit is disclosed which uses a heterojunction bipolar transistor with a heterojunction between an emitter region (28) and a base region (30). In this transistor, a pn junction between the base region (30, 38) and the emitter region (28) has a greater area than a pn junction between the base region (30, 38) and a collector region (36). A plurality of such heterojunction bipolar transistors are isolated on a substrate to perform logic operations in an unsaturated region.

Description: The present invention relates to a heterojunction bipolar integrated circuit which uses a heterojunction bipolar transistor with a heterojunction between its emitter and base regions to constitute an unsaturated logic circuit. It is well known that heterojunction bipolar tran­ sistors, having an emitter region formed from a material with a wider bandgap than that of the base region, offer numerous advantages over homojunction bipolar tran­ sistors, which have a homojunction between their emitter and base regions. These advantages can be summarized as follows. (1) The emitter injection efficiency can be in­ creased by making use of the difference in bandgaps, even if the ration between impurity concentrations of the emitter and base regions is small. (2) Base resistance can be reduced, since the base impurity concentration can be set to a high value as a result of (1) above. (3) Emitter junction capacitance can be reduced since the impurity concentration of the emitter region can be set to a low value. Heterojunction bipolar transistors thus offer supe­ rior high frequency and switching characteristics over homojunction bipolar transistors, and are particularly promising for use in microwave and high-speed logic circuit transistors. Fig. 1 is a simple sectional view of the structure of a heterojunction bipolar transistor used in a conven­ tional logic circuit. The transistor has the structure illustrated in order to facilitate extraction of the base electrode. In this extracted base electrode, there is a parasitic diode like the one shown in region b. The area of the junction between the base and collector regions increases due to the presence of this parasitic diode, and hence the junction capacitance between the base and collector regions also increases. Since the product of junction capacitance, between the base and collector regions, and load resistance, are the main fac­ tors determining the switching speed, an increased junc­ tion capacitance between the base and collector regions means degraded high-speed characteristics for the logic circuit composed of this type of transistor. In logic circuits of this conventional structure, then, there is a parasitic external base region (region b) on the collector region side of the transistor. As a result, the capacitance on the collector region side is several times greater than the junction capacitance bet­ ween the base and collector regions in an intrinsic transistor, thus negating much of the advantage offered by the good, high-speed characteristics of heterojunc­ tion bipolar transistors. In order to resolve this problem, H. Kroemer des­ cribes a logic circuit using inverted structure (C-top) hetero-bipolar transistor in his article, "Hetero­ structure Bipolar Transistors and Integrated Circuits", Proc. IEEE, Vol. 70, 1982, pp. 13 - 25. In the hetero­ junction bipolar transistor described, howver, an emit­ ter layer is used in common by each transistor. As a result of the specific resistance of this emitter layer, differences appear in the voltage applied to each transistor, i.e., voltage V BE applied between the base and emitter, and uniform operation of the respective transistors is compromised. It is an object of the present invention to provide a heterojunction bipolar integrated logic circuit which takes advantage of the high-speed characteristics offered by a heterojunction bipolar transistor. It is another object of the present invention to provide an integrated logic circuit constituted by in­ verted structure heterojunction bipolar transistors and capable of uniform operation. In order to achieve the above objects, a hetero­ junction bipolar transistor according to the present invention comprises: a substrate; a plurality of heterojunction bipolar transistors formed on the substrate, each having at least an emitter region consisting of a first type of semiconductor, a base region constituting a pn junction with the emitter region, and consisting of a second type of semiconductor with a bandgap narrower than that of the emitter region, and a collector region constituting a pn junction with the base region, and consisting of the first or second type of a semiconductor, the pn junction between the base and emitter regions having a larg­ er area than the pn junction between the base and collector regions; element isolating means for isolating the plurality of heterojunction bipolar transistors on the substrate; and means for connecting the plurality of heterojunc­ tion bipolar transistors with wiring and for allowing them to carry out logic operations in an unsaturated region. In the transistor constituting the logic circuit of the present invention, a parasitic external base region is formed between the base and emitter regions rather than between the base and collector regions. As described above, the doping concentration can be set at a desired level in a heterojunction bipolar tran­ sistor. Hence, the junction capacitance between the base and emitter regions can be reduced to a low level. In addition, by making the circuit an unsaturated one, variations in voltage between the base and emitter re­ gions during switching can be kept. As a result, the influence of a parasitic external base region, formed between the base and emitter regions, is significantly smaller than that of one formed between the base and collector regions. This will become clear from the following. Switch­ ing times were evaluated by computer simulation for the cases when the parasitic external base region is: (1) on the emitter region side; and (2) on the collector region side. The logic circuits tested used NTL (non-­ threshold logic), CML (current-mode logic) and CML with EF (current-mode logic with emitter follower), which perform the typical unsaturated logic operation; and DCTL (direct-coupled transistor logic) which performs the saturated logic operation. The results of calculat­ ing propagation delay time t pd , with a 5-stage ring oscillator simulation for the two cases above, are shown in Fig. 2. Ratio t pd (1)/t pd (2), between the propagation delay times of cases (1) and (2), is plotted along the axis of the ordinate in Fig. 2. It can be seen that, when the ratio t pd (1)/t pd (2) is 1, the result is the same whether the parasitic external base region is on the emitter side or on the collector side. For all the circuits, as is clear from the graph, an increased external base area brings about a reduction in ratio t pd (1)/t pd (2), and an external base region on the emit­ ter region side provides better high speed operation characteristics. This phenomenon depends on the follow­ ing reason. In case (1), a current either begins to flow in the external base region or is cut off during the ON/OFF operation. The time required for this is the delay in the rise and fall of the emitter current in an intrinsic transistor. In case (2), the emitter current rises immediately. However, because the external base region is on the collector side, switching of the cur­ rent flowing in the load is delayed. The fall of the current in the external base region is particularly slow during the OFF operation, and this leads to switching delays. Further, when the parasitic external base region is on the emitter region side as in case (1), a forward biasing of the base-emitter junction in the transistor causes a similar forward biasing of the parasitic exter­ nal base region. By making the parasitic junction of the external base region a homojunction of substances having wide bandgaps, however, the built-in voltage can be made larger than in the base-emitter junction of an intrinsic transistor. As a result, the current flowing in the parasitic external base region can be made negligibly small under DC characteristics. As is clear from Fig. 2, ratio t pd (1)/t pd (2) is clearly smaller for the unsaturated operation NTL and CML gates than for the saturated operation DCTL gate. In other words, the advantage of putting the external base region on the emitter region side is significant in unsaturated operation logic circuits. The reason for this is that in saturated operation circuits, the operating voltage range is wide and the ON/OFF time of the emitter current is too large to ignore. Thus, there is little difference between cases (1) and (2). In unsaturated operation circuits, on the other hand, the proportion of emitter charging and discharging time in switching time is extremely small. Hence, switching time is mostly determined by the discharging time of collector capacitance, so there is large difference between cases (1) and (2). In unsaturated operation circuits, case (1) is clearly advantageous. The above point will now be explained in more de­ tail. Figs. 3 and 4 show waveforms of the 5-stage ring oscillator simulations for the DCTL (saturated) and CML (unsaturated) circuits. Note the ON portions in both graphs. When the saturated circuit in ON, diode current I D and emitter current I E flow. In the rise portion, however, small impulse 10 appears and collecter current IC cannot flow. Impulse 10 is a current component gene­ rated by the emitter capacitance upon variations in vol­ tage V BE between the base and emitter. In the saturated circuit of Fig. 4 also, currents I D and I E begin to flow. However, there is no impulse in emitter current I E , and there is only a small delay in collector current I C with respect to emitter current I E . This is because, in an unsaturated circuit, the rate of change in V BE and hence the current generated by the emitter capacitance is small. When collector capacitance C C and emitter capaci­ tance C E of the conventional emitter-top (E-top) hetero­ junction bipolar transistor (HBT) and the collector-top (C-top) heterojunction bipolar transistor of the present invention are compared, the following relations are obtained: C C (E-top) > C C (C-top) C E (E-top) < C E (C-top) In an unsaturated logic circuit, as described above, the effect of emitter capacitance C E on switching speed is small. Hence, collector capacitance C C becomes a main factor determining switching speed. In other words, the C-top HBT, having a small C C value, can offer better high speed operation characteristics than the E-top HBT. In saturated logic circuits, although collector capaci­ tance C C is the main factor determining switching speed, the effect of C E cannot be ignored. Therefore, the dif­ ference in switching speeds between C-top and E-top HBTs is smaller for saturated circuits than for unsaturated circuits. Therefore, the present invention uses a heterojunc­ tion bipolar transistor formed with a parasitic external base region on the emitter region side to constitute an unsaturated logic circuit, and can therefore provide a logic circuit capable of high speed operation. In addition, according to the heterojunction bipo­ lar integrated logic circuit of the present invention, each inverted structure transistor is isolated on the surface of the substrate, thus allowing uniform opera­ tion of each transistor. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Other objects and advantages of the present inven­ tion will be apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a section view of a conventional hetero­ junction bipolar transistor; Fig. 2 is a graph showing the relationship of para­ sitic external base area/intrinsic transistor area to the ratio of propagation delay times, t pd (1)/t pd (2), for various logic circuits; Fig. 3 is a graph showing a 5-stage ring oscilla­ tion waveform for a DCTL which is a saturated logic circuit; Fig. 4 is a graph showing a 5-stage ring oscilla­ tion waveform for a CML which is an unsaturated logic circuit; Fig. 5 is a plan view of a heterojunction bipolar integrated circuit according to the first embodiment of the present invention; Fig. 6 is a sectional view taken along the line VI - VI in Fig. 5; Fig. 7 is a circuit diagram of the heterojunction bipolar integrated circuits in Figs. 5 and 6; Fig. 8 is a graph showing the relationship of para­ sitic external base area/intrinsic transistor area to propagation delay time t pd in the conventional and present invention; and Figs. 9 and 10 are diagrams for explaining a hetero­ junction bipolar integrated circuit according to another embodiment of the present invention. A first embodiment of a heterojunction bipolar in­ tegrated circuit according to the present invention will now be described with reference to Figs. 5 to 7. The heterojunction bipolar transistor of this em­ bodiment is a collector-top transistor whose uppermost layer is a collector region. The base region is con­ stituted by GaAs, and the emitter region (the portion forming a junction with the base region) in constituted by Aℓ₀.₃Ga₀.₇As, which has a wider bandgap than the base region. The heterojunction bipolar transistors of this embodiment are connected by wiring to constitute a CML (current-mode logic) which is an unsaturated logic circuit. In manufacturing a logic circuit with this hetero­ junction bipolar transistor, semiconductor layers must be sequentially grown with an epitaxial method on a semi-insulating substrate. Both MBE (molecular beam epitaxy) and MOCVD (metal organic chemical vapor depo­ sition) can be used. The example in Figs. 5 and 6 was manufactured using MBE in the following manner: First, n⁺-type GaAs layer 22, with a thickness of 5,000 Å and an impurity (Si) concentration of 2 × 10¹⁸cm⁻³, is formed on semi-insulating GaAs substrate 20. An n-type Aℓ₀.₃Ga₀.₇As layer 24, with a thickness af 3,300 Å and an impurity (Si) concentration of 3 × 10¹⁷ cm⁻³, is formed on GaAs layer 22. An n-type Aℓ x Ga₁ -x As layer (transition region) 26, with a thick­ ness of 200 Å and an impurity (Si) concentration of 3 × 10¹⁷ cm⁻³, and whose Aℓ ratio × changes continuously or in stages from 0 to 0.3, is then formed on layer 24. Layers 22, 24, and 26 constitute n-type emitter region 28. Region 28 can also be constituted by a first type of semiconductor, i.e., AℓGaAs, with a wider bandgap than the base region which is formed above this region. Since any increase in the impurity concentration of AℓGaAs is limited, however, the portion outside the area constituting the pn junction with the base region, con­ sists of a second type of semiconductor, i.e., GaAs, in this embodiment. In the claims, it is stated that the emitter region consists of the first type of semiconduc­ tor. This means, therefore, that at least the portion constituting the pn junction with the base region, con­ sists of the first type of semiconductor. It does not mean that the entire emitter region consists of the first type of semiconductor. P⁺-type GaAs layer 30, with a thickness of 1,000 Å and an impurity concentration of 3 × 10¹⁸ cm⁻³, is then formed on transition region 26, to serve as a base region. Layer 30 constitutes a pn heterojunction with emitter region 28. Be is used as the p-type impurity in this base region. An n-type GaAs layer 32, with a thickness of 3,500 Å and an impurity concentration of 1 × 10¹⁷ cm⁻³, and n⁺-type GaAs layer 34, with a thickness of 1,000 Å and an impurity concentration of 2 × 10¹⁸ cm⁻³, are then formed on the base region. Layers 32 and 34 constitute collector region 36, and a pn junction with the base region is formed. This completes the wafer formation process. Next, a CML gate is formed. First, external base region 38 is formed by selective ion implantation for the purpose of forming contacts for the base region. This ion implantation is performed, for example, using Mg, at a dose of 2 × 10¹⁴ cm⁻² and an acceleration vol­ tage of 200 KeV. The impurity is implanted as deep as the surface of AℓGaAs layer 24, which constitutes the emitter region. As a result p⁺-type AℓGaAs layer 40 is formed. Isolation region 42 is then formed to isolate the base and emitter regions in the transistor. Isolation region 44 is also formed in order to isolate the tran­ sistors. Regions 42 and 44 can be formed by the selec­ tive ion implantation of an impurity such as H⁺ or B⁺. The surface of external base region 38 is then etched to isolate region 38 and layer 34 of collector region 36. NiCr or the like is deposited on region 44 and pat­ terned to form a layer constituting load resistor 46. Etching is performed from the wafer surface to layer 22 of the emitter region, to form the contacts for the emit­ ter region. A thin AuGe layer is formed on the etched portion, and an Au layer is formed on the AuGe layer, to form emitter electrode 48. AuZn is then deposited on region 38 and patterned to form base electrode 50. An AuGe layer is formed, on GaAs layer 34, and an Au layer also, is formed thereon, to form collector electrode 52. A Ti-Pt-Au layer is then formed on the emitter, base, and collector electrodes, to form first wiring layer 54. Insulating layer 56 of SiO₂ or the like, is then formed on layer 54 by CVD or a similar method. Contact holes for connecting first wiring layer 54 to second wiring layer 58 are formed by etching. Layer 58 is then formed on the contact holes with Ti-Pt-Au or the like. This second wiring layer 58 completes the preparation of a one-gate CML circuit shown in Fig. 7. The switching characteristics of a CML gate of the present invention and a conventional CML gate, were eval­ uated using 5-stage ring oscillator simulation, and the results are shown in Fig. 8. The CML gate of the pres­ ent invention is composed of a heterojunction bipolar transistor whose base-emitter junction area is larger than its base-collector junction area, and whose base region contacts are formed above a portion of the base-­ emitter junction. The conventional CML gate is comprised of a heterojunction bipolar transistor whose base-collector junction area is larger than its base-­ emitter junction area. As is clear from the graph, even if the external base area increases, the increase in propagation delay time t pd in the embodiment of the pre­ sent invention is extremely small in the case where the intrinsic transistor area is 4 × 10 ⁻⁷ or 4 × 10⁻⁸ cm², compared with that of the conventional gate. Since the external base area is normally about twice the intrinsic transistor area, the present invention can bring about an improvement in propagation delay time of about 1/2 to 2/3 over the conventional device. In spite of this, power consumption in device of the present invention is almost the same as in the conventional device. Thus, the present invention enables significant improvements in propagation delay time without increased power con­ sumption. In the above embodiment, the base and emitter re­ gions are formed with GaAs and Aℓ₀.₃Ga₀.₇As, respective­ ly. The mole ratio of the Aℓ in the emitter region is not limited to 0.3. The present invention can be ap­ plied to cases where the base and emitter regions are formed with other semiconductor combinations, such as InGaAs and InP, InGaAs and InAℓAs, Ge and GaAs, and Si and GaP. The collector region may be formed by another type of semiconductor material. In the above embodiment, a CML is exemplified, but the present invention is equally effective when other unsaturated-type circuits, such as NTL (non-threshold logic), shown in Fig. 9, and CML(with EF) (Trf and R EF ), shown in Fig. 10, are used. In Figs. 9 and 10, R L denotes a load resistance.

Claims: 1. A heterojunction bipolar integrated circuit comprising: a substrate (20); a plurality of heterojunction bipolar transistors (Tr1, Tr2, Tr3) formed on said substrate, each having at least an emitter region (28) consisting of a first type of semiconductor, a base region (30) constituting a pn junction with said emitter region and consisting of a second type of semiconductor with a bandgap narrower than that of said emitter region, and a collector region (36) constituting a pn junction with said base region, and consisting of the first or second type of semiconductor, said pn junction between said base and emitter regions having a larger area than said pn junction between said base and collector regions; characterized by comprising: element isolating means (44) for isolating said plurality of heterojunction bipolar transistors on said substrate; and means (46, 48, 50, 52, 54, 58) for connecting said plurality of heterojunction bipolar transistors with wiring, and for allowing said transistors to carry out logic operations in an unsaturated region. 2. The circuit according to claim 1, characterized in that said substrate (20) comprises a semi-insulating semiconductor. 3. The circuit according to claim 1, characterized in that each of said plurality of bipolar transistors comprises: an emitter region (28) formed on said substrate (20); a base region (30) formed on said emitter region; and a collector region (36) formed on said base region. 4. The circuit according to claim 1, characterized in that said first type of said semiconductor, cons­ tituting said emitter region, forms a pn junction at least with said base region. 5. The circuit according to claim 4, characterized in that said first type of said semiconductor comprises AℓGaAs. 6. The circuit according to claim 5, characterized in that said first kind of said semiconductor is comprised of: a transition region (26) in which an Aℓ ratio in the AℓGaAs changes from a base region side to an emitter region side; and a region (24) in which the Aℓ ratio is fixed. 7. The circuit according to claim 1, characterized in that said heterojunction bipolar integrated circuit achieves current-mode logic operation by means of said connecting means. 8. The circuit according to claim 1, characterized in that said heterojunction bipolar integrated circuit achieves non-threshold logic operation by means of said connecting means.

Inventors: AGAKI, JUNKO C/O PAT. DIV. K.K. TOSHIBA, AZUMA, MAKOTO C/O PAT. DIV. K.K. TOSHIBA, YOSHIDA, JIRO C/O PAT. DIV. K.K. TOSHIBA
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21