OPTICAL PROVISION OF CONNECTIONS IN INTEGRATED DEVICES

Abstract: A system for establishing connections between elements integrated on a semiconductor device (14) comprises an interactive visual display (10) and light pen (28) for creating a desired interconnection pattern for the device, the device being displayed on the display. An optical pattern generator (38) utilises video signals from the display to produce an optical pattern corresponding to the interconnection pattern. The device has a layer of photoconductive material, or a layer of self developing dry silver film and electrophotographic film, capable of providing a pattern of conductive paths corresponding to the optical pattern when the device is irradiated using the optical pattern.

Description: OPTICAL PROVISION OF CONNECTIONS IN INTEGRATED DEVICES Field of the invention. This invention relates to the optical provision of connections in integrated devices. More particularly, this invention concerns the establishment of electrical connections using optical techniques and may be used for establishing new circuits for interconnecting elements in an integrated circuit (particularly wafer scale integration (WSI) circuits) or may be used for testing and checking alternative interconnection schemes. Background to the invention The creation of a new integrated circuit or the modification of an existing one is presently a time consuming and costl-y process. In WSI large amounts of microcircuitry are fabricated on a wafer mounted, intact, on a single package. The wafer may hold about two hundred unconnected VLSI circuits. In the case of WSI, the production process may give rise to unavoidable defects or faults inside the VLSI circuits ? ' if this occurs and is found, e.g. during testing, it is desirable to be able to disconnect these faulty circuits so that only good circuits are interconnected. Additionally, it is often desired to produce a dedicated logic array from an uncommitted logic array (ULA) - that is a plurality of unconnected logic elements (AND, OR gates etc) integrated on a chip. Currently this is done using a personalised metallisation layer as the final chip layer. The production costs of integrated circuits on a silicon wafer are -considerable and, using conventional techniques, the electrical performance and proper function of a chip can only be tested after establishing the hard wired interconnection pattern. There is currently no way of modifying this pattern and in the case of chip malfunction due to circuit design errors, a new production run has to be started with an improved interconnection pattern. There have been proposed methods of non reversible reconfiguration of circuitry, for example using laser link or fuse blowing techniques. With known fuse blowing techniques, connections between layers of wires may be effected but the connections are permanent once the fuse is blown and they permit only one contact per line. Using the laser link approach, a wafer is partitioned into an array of cells. The smallest replaceable unit in each cell is surrounded by a matrix of interconnected wires. This wiring matrix comprises a plurality of wafer length tracks that occupy channels between cells on both first and second level metal layers. Using a low power constant wave Argon laser, wire lines can be linked by forming a vertical weld between two normally insulated metal layers. The laser also cuts the lines when required. This approach has drawbacks of singularity, sequential access, cost and the area needed for wiring. Further, it is only suitable as a development technique for circuit prototypes, as a testing tool to isolate, provide access and reconfigure circuit sub functions on integrated circuit chips or as a yield enhancement tool. Neither this nor the fuse blowing approach provides a method for providing general reversible interconnections. It is an object of the present invention to provide a system by which integrated circuits can be created or modified quickly and checked for operational validity before the expense of producing a mask from which circuits can be produced photolithographically is incurred. Summary of the invention According to a first aspect of the present invention there is provided a system for establishing connections between elements integrated on a semiconductor device, the system comprising: means for creating data defining a desired interconnection pattern for the device; means responsive to said data for generating an optical pattern for irradiating the device; and means on the device for creating a pattern of conductive paths corresponding to the optical pattern when the device is irradiated using the optical pattern. The elements may be logic elements of a ULA, or VLSI circuit elements on a wafer. The means for creating data defining a desired interconnection pattern may comprise: display means for producing a visual display of the device or a part thereof; light pen means capable of interacting with the visual display means to introduce into the image displayed on the display visually detectable features thereby enabling a user optically to connect the displayed image of one element of the device to the displayed image of another. The light pen can thus be used interactively to introduce conductive links between different elements in the device. The detectable features maybe in the- form of brightened up regions on the display. In one embodiment, the means for generating the optical pattern comprises data processing means for generating from said data a video signal corresponding to the detectable features introduced by the light pen; scanning projection means controllable by the video signal to produce an optical image of the light pen introduced features; and focussing means for focussing the optical image from the scanning projection means onto a surface of the device. The system may comprise storage means for storing said data for use in the production of further semiconductor devices having the same interconnection 1 pattern. Preferably there is provided means for testing the device for each of a plurality of such interconnection patterns to ascertain which of the plurality of interconnection patterns is most suitable or 5 best satisfies predetermined structual and/or functional criteria. Where a computer is associated with the display means, a computer aided design system can be formed which can be used interactively for introducing the desired 10 interconnection patterns. Once a pattern has been completed on the display means, the pattern data can be translated into software into a format acceptable to the optical pattern generator. Other means for creating the optical pattern 15 include: imaging a mask onto the integrated circuit (for example see co-pending International Patent Application No. PCT/GB85/00404, published as WO86/01931 the contents of which are herein incorporated by reference) ; ?-£• stroke writing using a light beam; raster scanning with a light beam. The means on the device for creating a pattern of conductive paths may comprise a thin film of radiation sensitive material the electrical resistivity of which is 25 substantially decreased in the presence of radiation. Hence, by irradiating the device using the optical pattern, the resistivity of the film at selected regions between the elements is reduced to produce electrical connections therebetween. The material may be a 30 photoconductive material. With some photoconductors, the conductivity state remains for a while after the exposure radiation has been removed, thereby enabling the stroke writing or raster scan modes of irradiation mentioned above. These two methods are particularly advantageous 5 since they can be software . controlled. A suitable photoconductor is cadmium sulphide. Another material which may be used is an isophianaphene material which is *■ opaque and insulating in the absence of light and which becomes, reversibly, translucent and conductive when illuminated. The system preferably also provides means for 5 electrically contacting a chip carrying the device in order to provide power supplies and input signals and to read the output signals for testing purposes. If a raster scan system is used, then the software can generate the appropriate video signal. 0 If a deflected laser beam is used, based on X and Y galvos, then the galvo-driving waveform can be generated to obtain the proper stroke writing. In a preferred embodiment, where the optical pattern takes the form of a mask or image, the optical 5 pattern generator comprises means for aligning the optical pattern to the device. For this purpose, the projection of the optical pattern may be achieved by means of a high resolution objective lens, which can also be used for observing the light pattern created directly 0 on the chip. Micrometric movements in one plane can be provided for visual alignment of the chip with the projected image, and micrometric movement out of that plane can be provided for achieving proper focus. The radiation is conveniently light, although it 2^ may also be invisible radiation such as infra-red or ultra-violet, in which case alignment using conventional visual microscopy would not be possible. In this instance optically sensitive test features may be implemented on the chip. For example, such a feature might consist of a small diode provided with an electrical contact pad for probing. A light spot is created at the nominal location of the center of the diode using the pattern generator. The chip position can then be adjusted until the diode photocurrent is a • " maximum. Alignment can also be carried out using micromechanical features on the chip. In this case a signal can be detected off the chip by capturing reflected radiation. The direction of the reflected light beam changes abruptly when a micromechanical edge is met, and this will be the principle of detection. Arrays of such detection elements can be used in configurations that enable sharper and quicker alignment. Together with this, the optical beam may originally be defocussed in order to cover a large area and gradually be focussed as alignment is improved. The movement of the chip to achieve alignment could conveniently be automated in a feedback loop. Suitable alignment details are given in WO86/01931 mentioned above. The visual display unit may include a television tube or the like together with associated power supplies, scanning circuits and beam modulating circuits and conveniently the image on the display is produced by scanning the device using a television camera or the like. Scaling means using either optical or electronic techniques may be employed to determine the scaling factor between the actual real life size of the device and the display of the same on the television screen, with which the light pen is to interact, so as to introduce onto the device lines of light which are not only in the correct position but are also the correct size to just link the elements on the said device. In order to reduce parallax problems which may arise if the device is scanned by the camera at an angle other than the normal, a beam splitting device may be employed to enable the device to be viewed directly by the camera and to be selectively illuminated by means of the scanning projection system arranged for example at right angles to the axis of the camera, the light from the scanning projection system being reflected by the beam splitting device so as to be projected onto the surface of the integrated device. Alternatively a mirror may be introduced into the light path between the device and the camera. The scanning projection system may utilise a small area high intensity cathode ray tube having a short decay phosphor. When a laser beam is used, one or more motorised mirrors or other beam deflecting devices may be provided for scanning the device. By utilising a Q switch in association with the laser light source, and controlling the output from the laser thereby, so that the writing beam can be turned ON or OFF as required, it is possible to illuminate only the selected regions of the device to establish the optical pattern and hence the conductive connections required. If a colour VDU is employed, ..and the light pen. can control the colour of the introduced features in the display, different colours may be used for different connections to facilitate a check on the circuit that is displayed. Thus, for example, red might be used to denote a positive bus, blue for a negative bus and green to denote signal paths, in a typical signal processing circuit. Preferably the light pen includes controls either on the pen or associated therewith for controlling the colour of the display. The light pen preferably includes or is associated with switch means whereby the screen display can be written to, or previously introduced lines or areas can be erased, by simply pointing the light pen at the regions with the switch means appropriately actuated. It is preferred to transfer the pattern data in the appropriate format to the pattern generator at one time, and that this pattern generator contains a local memory to store this data for continuous refreshing of the projected image. Means may thus be provided for controlling transfer of the interconnection pattern data to the optical pattern generator. An operator can thus introduce into the display the connections required between various elements using the light pen, and after a visual check of the introduced links, operate the control means to transfer the electrical pulses corresponding to that data to the optical pattern generator to establish the conductive paths in the device. This enables the operator to make corrections and erase errors during the writing-in process before the signals are applied to the optical pattern generator. The invention comprehends the interconnection of discrete elements such as logic gates or of different spaced apart VLSI circuits of a WSI circuit and may be used to establish the part of or the whole electrical circuit of an integrated circuit for development and testing purposes. According to a third aspect of the invention there is provided an integrated device having means for creating a pattern of conductive paths corresponding to an optical pattern when the device is irradiated using the optical pattern, the device comprising a substrate with semiconductor junctions exposed at the surface of the substrate, said means comprising radiation sensitive material, the electrical resistivity of which is substantially reduced in the presence of radiation, deposited over the substrate whereby the conductive paths, when created, can interconnect selected ones of the semiconductor junctions. It will be appreciated that, since when the optical pattern is removed or altered the conductive paths will be destroyed or changed, it is possible to interconnect reversibly such elements for the purposes of testing or development. One application for the invention is to reversibly dedicate an uncommitted logic array (ULA) . The invention also provides an integrated device having means for creating a pattern of conductive paths corresponding to an optical pattern when the device is irradiated using the optical pattern, the device comprising a substrate with semiconductor junctions exposed at the surface of the substrate, said means comprising a self developing layer deposited over the substrate and an electrophotographic film layer over the self developing layer. In this aspect, the conductive paths are rendered permanent. The integrated devices of the invention may include a layer of amorphous silicon sandwiched between two layers of thin film transistor arrays; the amorphous silicon layer may be used for driving purposes. The invention further provides an optically actuatable switch comprising two integrated devices each having a plurality of permanently conductive strips; a layer of photoconductive material between and contacting the devices; and means for. creating respectively an optical pattern for irradiating the devices, the switch being such that there is at each junction where a strip on one of the devices meets a strip on the other of the devices a region whose conductivity depends on the state of irradiation of the photoconductive material whereby said one strip may be connected to said other strip by suitably irradiating the devices. The invention yet further provides a method of creating an interconnection pattern for connecting elements integrated on a semiconductor device, the method comprising: creating data defining a desired interconnection pattern for the device; generating from said data an optical pattern for irradiating the device; depositing on the device means for creating, when the device is irradiated using the optical pattern, a pattern of conductive paths corresponding to .the optical pattern. Brief description of the drawings For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompaning drawings, in which: Figure 1 illustrates diagrammatically one arrangement for generating the optical pattern; Figures 2a and 2b illustrate structures in accordance with embodiments of the invention; Figure 3 illustrates the device with one means for providing the optical pattern; Figure 4 is a plan view of the structure of Figure 2b in a preferred embodiment; Figure 5 is a diagram of one system for computer aided design and development; Figures 6a to 6c illustrate diagrammatically the structure and arrangement of an optical switch; and Figure 7 shows a structure for providing non-reversible connections. Description of the preferred embodiments In Figure 1 a television visual display unit 10 is used to display a picture 12 of a semiconductor device 14 and its arrangement of elements. To this end a mirror 16 is movable into a position above the device 14, the latter being illuminated from a light source 18 so as to project an image of the plate through a focussing lens 20 onto a television camera tube 22 or the like. The video signal is stored in a memory 24 typically after analogue to digital conversion. The memory may be an active device in which case a refresh loop as at 26 is provided. Alternatively, the memory may be a passive device such as a magnetic disk or magnetic tape. The purpose of the memory is to provide a long term store of the layout of the elements to enable the mirror 16 to be removed from the optical path. Alternatively, beam splitting means may be used to allow part of the light reflected from the plate 14 to be reflected orthogonally toward the television camera 22 in which event, providing it is possible to continuously illuminate the device 14 without upsetting the electrical connections (as will hereinafter be described), the memory 24 can be dispensed with. Where continuous illumination ' is envisaged, the light sensitive material to be used on the device 14 is selected so as to be insensitive to light having a wavelength equal to that emanating from the lamp 18, but which is sensitive to the wavelength of light emitted by a projection system (to be described). By using the video signal obtained from the camera 22 (or repetitively scanning the contents of the memory 24 so as to produce a video signal) for supplying to the visual display unit 10, a picture of the arrangement of the elements 80 can be obtained on the screen. In conjunction with the visual display unit 10 there is a light pen 28 connected to the unit via a lead 30. The light pen includes a switch 32 by which the pen can be activated. In use the pen is held against the screen 34 of the visual display unit 10 and if the switch 32 is depressed and the pen is moved across the surface of the screen, a brightened up trace 74, 76, 78 appears in the display. When a desired length of trace has been drawn, the pressure on the switch 32 is released causing the trace to terminate. Using a memory (not shown) within the visual display unit, and in a manner known per se, the trace signal can be stored and recirculated in synchronism with the original video signal for subsequent display so that once written into the "picture" the brightened up trace will remain. A reset button 31 may be provided, the purpose of which is to eliminate all of the trace signals from the memory and thereby remove the trace from the picture. The trace signals in the form of a video signal ■ * ■ are applied along a signal path 36 to control a projection television tube 38 the display of which is focussed by means of a lens 40 onto the surface of the device 14. By adjusting the magnification of the optical system which includes the lens 40, the size of the image formed by the optical system on the plate 14 can be adjusted until the brightened up areas in the image corresponding to the brightened up regions introduced by the light pen in the image on the screen 34, are of the correct size relative to the elements on the device 14. An alignment system may be provided to ensure that the image is correctly aligned with the device. Figure 2 illustrates in cross-section one suitable structure for the device 14. A ULA VLSI chip is 5 manufactured in the conventional way except that, in place of the metallisation layer to form the desired interconnections between elements on the chip, a photoconductive film 44 is unselectively deposited over the silicon substrate 42 with its exposed semiconductor 20 junctions 45. Subsequently irradiated portions of the film (e.g. region 47) become conductive to selectively interconnect the junctions. (In Figure 2a, logic gates 11, 13 are shown diagramatically. It will be appreciated that these will in fact be constructed by n and p layers 25 in the conventional manner.) In another structure, shown in Figures 2b and 4, a conductive layer is utilised to provide connecting pads 148, 150, 152, 154, 156, 158 Figure 4 illustrates a preferred form of three element laminate in which the n J conductive pattern is made between thin film islands of copper or the like material (these are the square elements such as 148a, 150a depicted in Figure 4). Light is used to effect the connection between selected adjacent islands or "pads' . Figure 2b shows a device 35 with a silicon substrate 42 with n and p deposits to form a resistor 100, diode 101 and transistor 102 to be interconnected. A conventional Siθ2 fl l ra 1°3 i s deposited over the substrate, followed by a metallisation layer to form the 'pads' 148, 150, 152 A photoconductive film 44, or a layer of a material such as cadmium sulphide or isophianaphene is deposited between selected pairs of metal 'pads' e.g. 148 and 150, 152 and 154. Effecting contact between pads 148 and 150 may be equivalent to interconnecting a resistor and a diode. The metallisation layer serves to permanently interconnect certain elements and to provide conductive regions which can subsequently be interconnected using the optical pattern irradiation of the photoconductive film. In this way, a group of elements may remain permanently or temporarily interconnected, depending on the properties of the interconnecting material. In addition the accuracy of the imaging system to irradiate the device using the optical pattern need not be so stringent, and the process is quicker (since less regions need to be "painted" on the display). It will be appreciated that in place of the circuit elements or logic gates as illustrated, the device could be a WSI chip with VLSI circuits to be interconnected. It will be seen that by forming an image of the device circuitry on the screen 34, and then introducing brightened up regions into the display using the light pen 28 (the brightened up regions corresponding to the regions of the original device which are to be illuminated by the. projection system 38, 40), and by adjusting the magnification of the optical system containing the lens 40 so that the brightened up regions due to the projection tube correspond in actual size to the regions in the. surface of the plate 14 which are to be illuminated and rendered conductive, it is only necessary to align the optical system with the plate 14 so that the illuminated regions fall in the precise positions required on the plate surface to effect the change in the electrical characteristics of the surface which is required to interconnect the elements. Where the light pen 28 has to be used to designate all of the interconnections, the resulting light pattern will correspond to the pattern of conductive tracks required on the surface of the device 14. In known. manner such tracking can be rendered permanent in an integrated circuit. To this end provision is made for storing in a suitable form the signal produced from the light pen interaction with the original display,- since by using an appropriately synchronised scanning projection system, these stored signals can be used subsequently in wafer production. In this way, the system can be used to test a particular circuit design which, if proved satisfactory, can then be used to manufacture several devices. As illustrated in Figure 1, the light pen signal output on path 36 may be diverted (typically via an analogue to digital converter 56) to a digital memory 58 such as a disk or tape. The system can be used to test circuits by interconnecting different elements in turn to determine which of a number of elements would be the most appropriate one ' for a given circuit by simply illuminating the junction between each element and some common point in a circuit and making the appropriate measurements or observations before extinguishing that brightened up region in the display and writing in another brightened up region corresponding to a connection between another component and the said common point. A second switch 31 similar to 32 may be provided on the light pen, for removing light pen generated pulses (as opposed to generating same) and appropriate circuits would then be provided within the visual display unit and associated controls of the unit 10 to enable both switches to be used, the first switch 32 for initiating "writing" and second switch 31 to initiate "removal" or "deletion". Preferably any such switches 31, 32 etc are push button switches which only operate when depressed. It will be apparent that either the whole or part of the integrated circuit can be reproduced on the television display on a macroscopic basis so as to allow interaction with a hand held pen thereby enabling the interconnection of semiconductor junctions at will. The light pen pattern produced as a result of interconnection can be stored and used either as a photographic mask or as a series of electrical signals to control a writing beam for forming conductive connections between junctions in subsequent silicon wafers so as to enable the original micro-circuits to be reproduced. Figure 3 illustrates another system for generating the optical pattern consisting of a dynamic optical mask 46 and a light diffusing material 48. The optical pattern can be altered in response to the optical pattern data fed from the display means to the mask at arrow A; the behaviour of this mask is similar to that of a common memory device. This arrangement is described in more detail in WO86/01931 mentioned above. AS described above, the connections made on the device are reversible: that is on removal of the radiation the connections are destroyed. It is possible to use the above system to provide permanent connections with a structure such as that of Figure 7. In the structure of Figure 7, a layer of dry self developing silver film 113 is deposited on a substrate in place of a photoconductive layer 112. This is then covered by a layer of an electrophotographic film 114. Selective exposure of the film to light creates charged regions which form a latent image of conductive paths in the dry silver film. When the silver film develops, the paths are rendered permanent. Referring to Figure 3, when using a structure according to Figure 7 in place of layers 42 and 44, the dynamic optical mask holds the pattern of desired routing which is transferred to the electrophotographic film and dry silver film to establish connections between the elements. The display of brightened up regions produced by the projection tube 38 and optical system 40 may be used to expose the electrophotographic film to form an optical pattern thereon corresponding to the interconnection pattern. Figure 5 illustrates a system where a main frame computer 121 is associated with the ' display means.10. Video signals from the VDU are processed by an emulator 120 to provide optical pattern generating signals to control the optical pattern applied to a target chip 14' . The original chip 14 is housed within the emulator where it is emulated. The emulator output is connected to the target chip 14' by, for example, a flat ribbon cable. Referring back to Figure 1, components 14, 16, 18, 20, 22, 38 and 40 will be housed in the emulator, while components 56 and 58 will form part of the mainframe 121. A printer 122 is associated with the emulator. The mainframe serves to provide data relating to parameters such as gate usage, power dissipation etc., to enable the coding areas ' and . data conversion ' areas to ■ be automatically checked and eliminated. When the system is used to dedicate ULA, prior to aligning the chip and creating the pattern on the VDU, a delay time simulation will provide an expected delay/circuit performance analysis. This point placement and routing software should allow the use of up to four numbers of gates without resorting to manual routing. Further in the development programme a final delay time simulation will occur. Actual (wire) lengths are taken into account for accurate circuit analysis. If all these previous steps are successful, the design pattern is created on the VDU and the required interconnections are provided as described above for the chip under trial. Then each of the functional blocks is tested. Each block which is tested and found to be performing to the required specification has its design transferred to the memory to subsequently generate a mask for creating further chips. This system can be used for the design of such optical masks (dynamic or fixed) for use in loading data into chips (see WO86/01931) or for personalising uncommitted hardware (e.g. logic arrays). In this application the system is simple to use and provides a fast turnaround time. The system can also be applied for reversibly establishing interconnection patterns in integrated circuits and for testing and checking alternative interconnection schemes for different architectural possibilities. The computer aided design system offers a considerable improvement in the investigations of function, performance, quality or silicon efficiency. That is, it is possible for the designer to explore, without turnaround time (the time required in conventional technology to implement a hard wired arrangement for testing) a variety of alternative architectures for a given circuit. Such an architectural investigation can result in final designs which , are much more efficient, hence more cost effective, than those obtainable using the limited exploration techniques available currently. Using the present system, once the designer is satisfied with the design, he merely arranges for that design to be stored in the memory for subsequent utilisation in the creation of masks. Figures 6a to 6c illustrate an optical switch. The switch is formed using two integrated circuit chips 200, 201 each having strips of conductive material at the metallisation level of the chip. For example (see Figure 6b) the chip 200 might carry m lines running transversely and the chip 201 might carry n lines running longitudinally. The chips will also be provided, possibly at the periphery, with the logic circuit elements required for operation of the switch. Referring to Figure 6a, a dynamic optical mask 202 is placed above the chip 200, and a further similar mask 203 is placed below the chip 201. Finally, the chips are "sandwiched" together using a layer of photoconductive or isophianaphene material 204. The switch is designed to connect any one of the m lines to any one of the n lines, and to this end at each possible junction there is provided a hook 205 (Figure 6b). The structure of the hook is shown in more detail in Figure 6c. The hook 205 consists of, for each junction, a conductive path 206 connected to one of the n lines in chip 201 and a further conductive path 207 connected to one of the m lines in chip 200. Between the two there is a channel 208 whose state of conductivity depends on the state of the photoconductive material 204. It will be apparent that, by illuminating the structure via dynamic optical layer 202 and/or 203 it is possible to connect any one of m inputs to any one of n outputs if one of the chips 200 is constructed as an input chip, while the other is an output chip. Such a switch has applications in switching high speed digitised signals, for example in telecommunication networks, since it is capable of routing an input to any output that is not busy and is also capable of routing one to a plurality of connections. The illumination sources would be controlled by the switching sequencer.

Claims: CLAIMS 1. A system for establishing connections between elements integrated on a semiconductor device, comprising: means for creating data defining a desired interconnection pattern for the device; means responsive to said data for generating an optical pattern for irradiating the device; and means on the device for creating a pattern of conductive paths corresponding to the optical pattern when the device is irradiated using the optical pattern. 2. A system as claimed in claim 1, in which the means for creating data defining a desired interconnection pattern comprises: display means for producing a visual display of the device or part thereof; and light pen means capable of interacting with the visual display means whereby visually detectable features can be introduced into the displayed image to enable a user optically to connect the. image displayed on the display of one element to the displayed image of another. 3. A system as claimed in claim 1 or 2, in which the means for generating the optical pattern comprises: data processing means for generating from said data a video signal corresponding to the detectable features introduced by the light pen; scanning projection means controllable by the video signal to produce an optical image of the light pen introduced features; and focussing means for focussing the optical image from the scanning projection means onto a surface of the device. 4. A system as claimed in claim 3, in ' which the scanning projection means comprises a cathode ray tube display. 5. A system as claimed in claim 1, in which the means 2G- for generating the optical pattern comprises a mask having regions controllable to be selectively light transmissive or non-transmissive regions and a source of radiation for irradiating the device via the mask; and data processing means for generating from said data a signal for controlling the transmissivity of said regions. 6. A system as claimed in claim 1, in which the means for generating the optical pattern comprises means for stroke writing with a light beam. 7. A system as claimed in claim 1, in which the means for generating the optical pattern comprises means for raster scanning with a light beam. 8. A system as claimed in any preceding claim which comprises storage means for storing said data for use in the production of further semiconductor devices having the same interconnection pattern or for- use in the development of further semiconductor devices. 9. A system as claimed in' any pre ' ceding claim, in which the means on the device is such as to provide paths which, are conductive only in the presence of radiation, and which are insulating or semiconductive in the absence of radiation. 10. A system as claimed in any preceding claim which comprises means for testing the device for each of a plurality of such interconnection patterns to ascertain which of the plurality of interconnection patterns is most suitable or best satisfies predetermined structural and/or functional criteria. li. A system for creating an interconnection pattern for connecting elements integrated on a semiconductor device, comprising: visual display means for producing a displayed image of the device or part thereof; means capable of interacting with the visual display means whereby visually detectable features can be introduced into the displayed image to enable a user 1 optically to connect the displayed image of one element to the displayed image of another to form an interconnection pattern; data processing means for generating from data 5 relating to the visually detectable features an optical pattern; and means for irradiating the device using the optical pattern to create on the device a pattern of conductive paths corresponding to the interconnection pattern. - •• 0 12. A method of creating an interconnection pattern for connecting elements integrated on a semiconductor device, the method comprising: creating data defining a desired interconnection pattern for the device; 1 generating from said data an optical pattern for irradiating the device; depositing on the device means for creating, when the device is irradiated using the optical pattern, a pa ' ttern of conductive paths corresponding to the optical 0 pattern. 13. An integrated device having means for creating a pattern of conductive paths corresponding to an optical pattern when the device is irradiated using the optical pattern, the device comprising a substrate with semi ^ conductor junctions exposed at the surface of the substrate, said means comprising radiation sensitive material, the electrical resistivity of which is substantially reduced in the presence of radiation, deposited over the substrate whereby the conductive paths, when created, can interconnect selected ones of the semiconductor junctions. 14. A device as claimed in claim 13, which further comprises a permanently conductive material deposited to provide regions contacting the junctions, which region 35 can be connected by the created paths. 15. An integrated device having means for creating a pattern of conductive paths corresponding to an optical pattern when the device is irradiated using the optical pattern, the device comprising a substrate with semiconductor junctions exposed at the surface of the substrate, said means comprising a self developing layer deposited over the substrate; and an electrophotographic film layer over the self developing layer. 16. An integrated device as claimed in claim 13, 14 or 15, which comprises a layer of amorphous silicon sandwiched between two layers of thin film transistor arrays. 17. An optically actuable switch comprising two identical devices each having a plurality of permanently conductive strips; a layer of photoconductive material between and contacting the devices; and means for creating respectively an optical pattern for irradiating the devices, the switch being such that, at each junction where a strip on one of the devices meets a strip on the other of the devices, there is a region whose conductivity depends on the state of irradiation of the photoconductive material whereby said one strip -may be connected to said other strip by suitably irradiating the devices. 18. A system as claimed in claim 1 or 11 substantially as hereinbefore described with reference to the accompanying drawings. 19. A method as claimed in claim 12 substantially as hereinbefore described with reference to the accompanhing drawings. 20. An integrated device having a structure- substantially as hereinbefore described with reference to Figures 2a and 2b or 7 of the accompanying drawings.

Inventors: FRY RICHARD, RAVEN ANTHONY, SIERENS WILLY MICHEL DESIRE, ULLMANN JERZY JOSEF, FRY, RICHARD, RAVEN, ANTHONY, SIERENS, WILLY, MICHEL, DESIRE, ULLMANN, JERZY, JOSEF
Applicants: PA CONSULTING SERVICES, PA CONSULTING SERVICES LIMITED
Application year: 1986
Main classification: H01L23
IPC codes: G03F7, H01L23