APPARATUS FOR DETECTING TELEVISION IMAGE MOVEMENT

Abstract: In an apparatus for detecting movement of a television image in response to frame difference data corresponding to a difference between present frame data and previous frame data, a video signal is divided into a plurality of segmental areas of each frame, a pixel or picture element is selected to represent each of the segmental areas, frame difference data are produced for each of the segmental areas by calculating differences in the position or coordinates of a pixel represent­ ative of a segmental area of a previous frame from the re­ spective picture element of the corresponding segmental area in the in the present frame, and each of the calculated dif­ ferences smaller than a predetermined magnitude, and which would be characteristic of a stationary background portion of the television image, is omitted from the frame difference data.

Description: This invention relates to apparatus for detecting television image movement. Such apparatus is particularly, but not exclusively, suitable for use in a video signal standards conversion circuit. A block matching method has been used to detect movement vectors each representing the amount and direction of movement of a television image from one frame to the next in response to frame difference data between present frame data and previous frame data. In such a block matching method, a video signal is divided into a number of segmental areas or blocks for each frame. The frame difference data are produced for each of the segmental areas by calculating differences in the positions or coordinates of picture elements representing corresponding segmental areas of successive frames. These calculations are effected by a digital computer operable in accordance with a program stored in the computer memory. In order to simplify the program arrangement and increase the signal processing speed, it has been proposed to designate a point or pixel representative of each of the segmental areas. (See our EP patent application EP-A-0 180 446 published 7 May 1986, and claiming priority from Japanese application JP-59-226604 filed 27 October 1984, and therefore falling under the terms of Article 54 (3), EPC.) The representative pixel is normally set at the centre of the segmental area. In this case, the frame difference data are produced by calculating differences in the position or coordinates of the pixel representative of a segmental area of one frame relative to the position or coordinates of the respective picture element of the corresponding segmental area of the subsequent frame. One disadvantage of such representative pixel method is that it fails to detect small movements of an object of uniform brightness. This is particularly true when the moving object appears against a distinctive background which changes greatly across the image. According to the present invention there is provided an apparatus for deriving a movement vector indicating an amount and direction of a movement in a picture defined by a television signal made up of successive intervals, the apparatus comprising: means for detecting difference data corresponding to the difference between data for a predetermined area of the picture in two of said successive intervals, wherein said successive intervals are frames of the television signal, said predetermined area is one of a plurality of segmental areas into which each of said frames is divided, and each of said segmental areas is represented by a representative picture element; gating means for gating said difference data; means for producing a control signal for said gating means which causes said gating means not to pass said difference data in response to data indicating a stationary background portion of the picture and which causes said gating means to pass said difference data in response to data indicating a moving object in the picture; means for accumulating the difference data which pass through said gating means; and means for detecting a minimum value of the accumulated difference data as an indication of said movement vector. The invention will now be described by way of example, with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a block diagram showing a previously proposed movement vector detecting circuit; Figure 2 is a diagram illustrating a small movement of an object in a television image; Figures 3 to 5 are graphs to which reference will be made in explaining the operation of the circuit of Figure 1; Figure 6 is a block diagram of a first embodiment of movement vector detecting circuit in accordance with this invention; Figure 7 is a diagram showing a segmental video signal area having a representative pixel at the centre thereof; Figure 8 is a graph to which reference will be made in explaining the operation of the movement vector detecting circuit of Figure 6; Figure 9 is a block diagram of a second embodiment of movement vector detecting circuit in accordance with this invention; Figure 10 is a diagram showing another manner in which a video signal may be divided into a plurality of segmental areas; Figure 11 is a diagram to which reference will be made in explaining disadvantages of previously proposed movement vector detecting apparatus, for example, as shown in Figure 1; Figure 12 is a block diagram showing one application of embodiment of movement vector detecting circuit according to this invention; Figure 13 is a block diagram showing a video signal conversion circuit to which an embodiment of movement vector detecting circuit according to the invention may be advantageously applied; Figures 14 to 16 are diagrams to which reference will be made in explaining the operation of circuits included in the conversion circuit of Figure 13; Figure 17 is a block diagram of an error processing circuit included in the conversion circuit of Figure 13; and Figure 18 is a diagram to which reference will be made in explaining the operation of the circuit of Figure 17. Prior to describing the embodiments of the invention, a previously proposed vector detecting circuit will be briefly described with reference to Figure 1, in order to provide a better understanding of the difficulties attendant thereto. The movement vector detecting circuit of Figure 1 includes an input terminal 1 to which a digital video signal is applied. The digital video signal is supplied from the input terminal 1 to one input of a subtracter 2 and also to a representative pixel extraction circuit 3. The extraction circuit 3 extracts a pixel or point representative of each of the segmental areas of one frame and produces pixel data indicative of the video data and the position or coordinates of the extracted representative pixel. The pixel data are fed from the extraction circuit 3 to, and stored in, a representative pixel memory 4. The stored data are read out of the representative pixel memory 4 and applied at appropriate times to another input of the subtracter 2. The data fed from the memory 4 to the subtracter 2 are previous frame data, and the digital video signal applied directly from the input terminal 1 to the substracter 2 is present frame data. The subtracter 2 produces frame difference data ΔF by calculating differences between the position or coordinates of the pixel representative of a segmental area of the previous frame and the position or coordinates of the respective picture element of the corresponding segmental area of the subsequent or present frame. The frame difference data ΔF are converted by a converter 5 into data |ΔF| representating absolute values of the respective differences. The data |ΔF| are fed to a summation circuit 6 which adds or sums the absolute values of the differences for the respective picture elements of each of the segmental areas to provide frame difference summation data Σ|ΔF|. The frame difference summation data Σ|ΔF| are fed to a minimum data detection circuit 7. The minimum data detection circuit 7 receives frame difference summation data Σ|ΔF| fed successively thereto from the summation circuit 6 while all of the segmental areas of one frame are being processed, and detects the minimum one of the received frame difference summation data Σ|ΔF| to produce a signal indicative of a movement vector which represents the amount and direction of movement of a television image from the previous frame to the present frame. This movement vector indicating signal appears at an output terminal 8. If it is assumed that, as shown in Figure 2, an object included in a television image moves in the horizontal direction from a position indicated in solid lines to a position indicated in broken lines, the described conventional movement vector detection apparatus cannot reliably detect a small movement of the object, that is, one in which the opposite end areas corresponding to the movement of the object are very small. Figure 3 depicts the frame difference summation data Σ|ΔF| when the object moves a small distance, and each segmental area includes sixty-three picture elements, that is, seven lines each having nine picture elements thereon. As can be seen from Figure 3, the minimum frame difference summation data corresponds to a zero movement vector. This means that the apparatus of Figure 1 indicates that the object remains at rest in spite of the fact that the object moves, as indicated at 9 in Figure 3. A similar problem arises when the background against which the object moves is distinct and changes greatly across the image. The reason for this will be apparent from Figures 4 and 5, in which Figure 4 shows the frame difference summation data Σ|ΔF| for a distinct background, and Figure 5 shows the frame difference summation data Σ|ΔF| for a moving object. It may be appreciated that, if an object moves against a distinct background, the frame difference summation data Σ|ΔF| will vary in a manner substantially as shown in Figure 3, which is substantially a combination of the graphs of Figures 4 and 5. A video signal to be received by an embodiment of movement vector detection circuit in accordance with the present invention is divided into a plurality of segmental video signal areas for each frame. Each segmental area includes sixty-three picture elements, that is, seven lines each carrying nine picture elements, as shown in Figure 7. Each segmental area is represented by the position or coordinates (x, y) of a representative pixel placed at the centre of the segmental area, as designated by the character X in Figure 7. The segmental areas may be defined partially to overlap each other. Referring now to Figure 6, it will be seen that an embodiment of movement vector detection circuit according to this invention includes an input terminal 11 to which a digital video signal is applied. The digital video signal is supplied from the input terminal 11 directly to one input of a subtracter 12, and also to a representative pixel extraction circuit 13. The extraction circuit 13 extracts a pixel or point representative of each of the segmental areas of one frame and produces pixel data indicative of the video data and the position or coordinates of the extracted representative pixel. Such pixel data are read into, and stored in a representative pixel memory 14. The stored data are read out of the memory 14 and applied, as previous frame data, to another input of the subtracter 12. The digital video signal applied directly from the input terminal 11 to the first mentioned input of the subtracter 12 carries present frame data which relate to the positions or coordinates of respective picture elements included in the corresponding segmental area of the present frame. Consequently, the subtracter 12 produces frame difference data ΔF by calculating differences in the position or coordinates of the pixel representative of the segmental area of the previous frame from the position or coordinates of the respective picture element of the corresponding segmental area of the present frame. The frame difference data ΔF are converted by a converter 15 into data |ΔF| representing absolute value of the respective differences. The absolute values of frame difference data |ΔF| are fed to a limiter circuit 16 which limits the values of the differences of the data |ΔF| below a predetermined value. The output of the limiter circuit 16 is applied to a minimum data detector circuit 20. The detector circuit 20 detects the position or address of the picture element for which the absolute value of the frame difference data |ΔF| is detected to be a minimum. The output of the detector circuit 20 is applied to a decision circuit 21 which determines whether or not the detected picture element is in a small vector region enclosed by the broken line in Figure 7. If the picture element is in that small vector region, then it means that the movement vector will be too small to be reliably considered and the decision circuit 21 produces a low level control signal. Otherwise, the decision circuit 21 produces a high level control signal which is applied to a switching circuit 18. The switching circuit 18 has a first input terminal 19A connected through a delay circuit 17 to the limiter circuit 16, a second input terminal 19B connected to earth or a source of zero data, and an output terminal 19C connected to a summation circuit 22. The switching circuit 18 responds to a high level control signal from the decision circuit 21 to cause engagement of the terminals 19A and 19C, and thereby permit the summation circuit 22 to receive the data |ΔF| from the limiter circuit 16. The delay circuit 17 delays the signal from the limiter circuit 16 to the terminal 19A, so as to compensate for the inherent delay in the time of arrival of the control signal at the switching circuit 18. The summation circuit 22 sums the absolute values of the data differences for the picture elements of each of the segmental areas to provide frame difference summation data Σ|ΔF|. The summation circuit 22 preferably includes a digital integrator for summing the data fed from the terminal 19C to produce frame difference summation data Σ|ΔF| for the respective picture elements of each of the segmental areas, and a memory having a number of addresses or memory sections corresponding to the number of segmental areas included in one field for storing the successively produced frame difference summation data in the respective memory sections. The switching circuit 18 responds to a low level control signal from the decision circuit 21 to cause engagement of the terminals 19B and 19C, and thereby connect the summation circuit 22 to the zero data source. This means that the frame difference data |ΔF| are omitted from the frame difference summation Σ|ΔF| when the picture element having the minimum absolute value of data difference |ΔF| is in the small vector region indicated by the dotted line in Figure 7. The frame difference summation data Σ|ΔF| are fed from the summation circuit 22 to a minimum data detector circuit 23. The minimum data detector circuit 23 receives the frame difference summation data Σ|ΔF| fed successively thereto from the summation circuit 22 while all of the segmental areas of one frame are processed, and detects the minimum one of the received frame difference summation data Σ|ΔF| to produce a signal indicative of a movement vector which represents the amount and direction of movement of a television image from the previous frame to the present frame. A counter 27 also receives the control signal from the decision circuit 21, and counts the number of occurrences of a low level control signal therefrom for each period during which all of the picture elements included in one segmental area are processed. The content of the counter 27 represents the number of frame difference data |ΔF| that are not included in, or omitted from the frame difference summation data Σ|ΔF| for a segmental area. A comparator circuit 29 compares the content of the counter 27 with a reference value fed thereto from a reference generator 28. For example, the reference value provided by the reference generator 28 may correspond to 80 percent of the number of the picture elements included in one segmental area. When the content of the counter 27 exceeds such reference value, the comparator circuit 29 supplies a low level control signal to a switching circuit 24. Otherwise, the comparator circuit 29 produces a high level control signal. The switching circuit 24 has a first input terminal 25A connected to the output of the minimum data detector circuit 23, a second input terminal 25B connected to earth or a source of zero data, and an output terminal 25C connected to an output terminal 26. The switching circuit 24 responds to a high level control signal from the comparator circuit 29 to provide a connection between the terminals 25A and 25C so that a signal indicative of the movement vector detected in the minimum data detector circuit 23 appears at the output terminal 26. The switching circuit 24 responds to a low level control signal from the comparator circuit 29 to provide a connection between the terminals 25B and 25C, so that a zero movement vector appears at the output terminal 26. It will be apparent from the above that the circuit shown in Figure 6 inhibits generation of an unreliable movement vector by zeroing the detected movement vector when a relatively great number of frame difference data are omitted from the data used in detecting a movement vector. It is further to be noted that, in the circuit of Figure 6, the switching circuit 18 forms, in effect, gating means for the data difference |ΔF| so as to supply such data difference |ΔF| to the summation circuit or accumulating means 22 for inclusion in the frame difference summation data Σ|ΔF| only when the control signal for the switching means 18, that is, the output of decision circuit 21, indicates that the segmental area of the frame then being considered does not represent a stationary background portion of the television image. In other words, the decision circuit 21 provides a high level control signal to the switching circuit 18 for supplying data difference |ΔF| to the summation circuit or accumulating means 22 only when the detector circuit 20 and the decision circuit 21 cooperate to indicate that the segmental area of the frame being considered corresponds to a moving object, and not a stationary background portion, in the television image. With the above described movement vector detecting apparatus, the minimum frame difference summation data correspond to movement of an object, as shown in Figure 8, even when the object moves against a distinct background which changes substantially across the television image. Therefore, this embodiment makes it possible to detect movement vectors with greater accuracy. Referring now to Figure 9, in which a second embodiment of a movement vector detecting apparatus according to the invention is illustrated, it will be seen that the parts or components equivalent to components shown in Figure 6 are identified by the same reference numerals in Figure 9. The apparatus of Figure 9 further includes a gate circuit 56 through which the data |ΔF| are fed from the converter 15 to a summation circuit 60. The gate circuit 56 supplies a predetermined value, for example, a quantization level 64, to the summation circuit 60 regardless of the value of the data |ΔF| fed thereto from the converter 15 whenever the picture element is determined to be in a non-movement range, that is, corresponds to a stationary portion of the background of the television image, as described later in detail. This determination is made by a circuit including a frame memory 57, a subtracter 58, and a threshold circuit 59. The frame memory 57 receives the digital video signal directly from the input terminal 11 and provides previous frame data which relate to the video data and the positions or coordinates of the respective picture elements of a segmental area included in the previous frame. The previous frame data are fed to the subtracter 58 which also receives present frame data directly from the input terminal 11. The present frame data relate to the positions or coordinates of the respective picture elements of the corresponding segmental area included in the present frame. The subtracter 58 produces frame difference data representing the difference between the present frame data and the previous frame data by calculating differences between the positions or coordinates of the picture elements of the segmental area of the previous frame and the positions or coordinates of the respective picture elements of the corresponding segmental area of the present frame. If the subtracter 58 produces a zero output or difference signal, it is established thereby that the corresponding picture element remains at rest, that is, part of a stationary background portion of the television image. In practice, due to noises or other factors, the difference signal from the subtracter 58 is not zero when a picture element remains at rest. For this reason, the output of the subtracter 58 is coupled to the threshold circuit 59 which compares the difference signal with a preferably adjustable threshold value for determining the non-movement range, and which has its output connected to the gate circuit 56 as a gating signal for the latter. The threshold circuit 59 produces a low level decision signal or output to cause the gate circuit 56 to close and to supply the predetermined value corresponding to the quantizing level 64 to the summation circuit 60 when the difference signal from the subtracter 58 is less than the adjustable threshold value. Otherwise, the threshold circuit 59 produces a high level decision signal or output to open the gate circuit 56 for passing the data |ΔF| from the converter 15 to the summation circuit 60. The output of the threshold circuit 59 is also coupled to a counter 63 which counts the number of occurrences of a low level decision signal at the output of the threshold circuit 59. The count of the counter 63 represents the number of the data |ΔF| omitted from, that is, not included in, the frame difference summation data. A comparator circuit 66 compares the content of the counter 63 with a reference value fed thereto from a reference generator 65. For example, the reference value from the reference generator 65 may correspond to 80 percent of the number of picture elements included in one segmental area. When the content of the counter 63 exceeds the reference value from the reference gernator 65, the comparator circuit 66 produces a control signal for zeroing a movement vector, as hereinafter described. The summation circuit 60 preferably includes a digital integrator for summing the data fed from the gate circuit 56 to produce frame difference summation data Σ|ΔF| for the respective picture elements of each of the segmental areas substantially in the same manner as described above in connection with the embodiment of Figure 6. The summation circuit 60 also includes a memory having a number of memory sections or addresses corresponding to the number of the segmental areas included in one field for storing the successively produced frame difference summation data in the respective memory sections. The frame difference summation data Σ|ΔF| are fed from the summation circuit 60 to a minimum data detector circuit 61. The minimum data detector circuit 61 receives frame difference summation data Σ|ΔF| fed successively thereto from the summation circuit 60 for all of the segmental areas of a frame normally to produce, at an output terminal 62, a signal indicative of a movement vector which represents the amount and direction of movement of a television image from the previous frame to the present frame. However, the minimum data detector circuit 61 responds to the control signal from the comparator circuit 66 to zero the output movement vector. This means that the minimum data detector circuit 61 exhibits generation of an unreliable movement vector when a relatively great number of frame difference data are omitted from the data used in detecting a movement vector. It will be appreciated that, in the embodiment of Figure 9, the output of the threshold circuit 59 which controls the gate circuit 56 is effective to indicate whether the segmental area of the frame being considered is put of a stationary background portion of the television image or is part of a moving object. The gate circuit 56 is opened by its control signal from the threshold circuit 59 for passing the data difference |ΔF| to the summation circuit or accumulating means 60 only when the frame memory 57, the subtracter 58 and the threshold circuit 59 cooperate to sense that the segmental area being considered is from a moving object and not a stationary background. Figure 10 shows a pattern in which the picture elements of a segmental area may be arranged to improve the capacity for detecting movement of television images having vertical strips or other patterns having high spatial frequencies. In the pattern shown in Figure 10, a pixel representative of a first segmental area and a pixel representative of a second segmental area just below or above the first segmental area are offset X/2 in the horizontal direction to provide a checkerboard-like pattern, in which X is the horizontal distance between two representative pixels adjacent to each other in the horizontal direction. Here again, the segmental areas may partially overlap each other. Figure 11 illustrates an image comprising a car that starts crossing a distinct background. When using a conventional movement vector detecting apparatus, no movement vector is detected in the region 71B and movement of the car cannot be detected until it has, at least to some extent, entered the region 71C. Since a low-pass filter is normally used to filter the video signal for suppressing sudden image changes and discontinuous movements, substantial time is required until the movement is corrected after a movement is detected in the region 71C. For these reasons, in the reproduced picture, the car appears to move in an unnatural manner, that is, as if it starts running after the application of braking. Figure 12 shows a television standards conversion system to which an embodiment of movement vector detecting apparatus according to the invention can advantageously be applied. The system of Figure 12 includes an input terminal 71 to which a high definition television (HDTV) signal is applied. The HDTV signal is supplied from the input terminal 71 to three gate circuits 72A, 72B and 72C. The gate circuit 72A serves to pass picture elements included in the left-hand region 71A in Figure 11, and the gate circuits 72B and 72C serve to pass picture elements included in the right-hand region 71B and the centre region 71C, respectively. A pulse generator 73, triggered by a suitable sync signal applied to a terminal 74, provides suitably timed gating signals to the gate circuits 72A, 72B and 72C. The centre region 71C overlaps the output image, and the left-hand and right-hand regions 71a and 71B do not overlap the output image, that is, are outside the desired output image. The outputs of the gate circuits 72A, 72B and 72C are coupled to movement vector detecting circuits 75A, 75B and 75C, respectively. Each of the movement vector detecting circuits 75A, 75B and 75C is substantially the same in structure as that described above in connection with Figure 6 or Figure 9. The movement vector detecting circuit 75A serves to detect a movement vector Va corresponding to movement of the car in the left-hand region 71A, the movement vector detecting circuit 75B serves to detect a movement vector Vb corresponding to movement of the car in the right-hand region 71B, and the movement vector detecting circuit 75C serves to detect a movement vector Vc corresponding to movement of the car in the centre region 71C (Figure 11). The movement vectors Va, Vb and Vc are all supplied to a decision circuit 76. The movement vector Vc is also supplied to a digital low-pass filter 77 which is effective to suppress sudden movement vector changes so as to minimize large jumping and discontinuous movements. The digital low-pass filter 77 is of a known type that changes its characteristics in a manner to retard the time when the movement vector falls, or to advance the time when the movement vector rises in accordance with a control signal fed thereto from the decision circuit 76. The decision circuit 76 produces the control signal for the digital low-pass filter 77 on the basis of the movement vectors Va, Vb and Vc detected for the regions 71A, 71B and 71C in Figure 11. The control signal for the digital low-pass filter 77 is generated when the object moves out of the output image or when the object moves into the output image. The type of control signal generated in the cases i to iv listed in the table below is described thereafter. CASE Va Vb Vc i to the left / to the left ii / to the right to the right iii / to the left to the left iv to the right / to the right In the above table, each sign (/) designates a movement vector that is not considered in the decision circuit 76. The object (car) moves out of the output image to the left in case i, and the object moves out of the output image to the right in case ii. When the object moves out of the output image, as in case i or ii, the decision circuit 76 provides a control signal which is effective to cause the digital low-pass filter 77 to retard the time when the movement vector falls, so as to maintain the magnitude of the movement vector in the centre region 71C (Figure 11). This is effective to suppress the tendency to decrease the magnitude of the movement vector when the object moves out of the output image, and thereby eliminates the apparent decrease in the speed of movement of the object as it moves out of the output image. The object moves into the output image from the right in case iii of the above table, and the object moves into the output image from the left in the case iv. When the object moves into the output image, the decision circuit 76 provides a control signal which causes the digital low-pass filter 77 to advance the time when the movement vector rises. Therefore, the movement vector in the region 71C can rise as soon as the object arrives at an end of the output image in entering the latter. In cases other than those listed in the above table, the characteristic of the digital low-pass filter 77 is maintained unchanged. The movement vector provided at an output terminal 78 may be used for effecting movement correction in a field number conversion circuit of a television standards conversion system, as described below. For example, as shown in Figure 13, embodiments of the invention may be applied to field number conversion when effecting standards conversion from a HDTV (high definition television) system employing 1125 lines per frame and sixty fields per second, to a PAL TV (phase alternation by line television) system employing 625 lines per frame and fifty fields per second. The television standards conversion system of Figure 13 is shown to include an input terminal 121 which receives a luminance signal included in an HDTV signal. Such luminance signal is applied through a low-pass filter 122 to an analog-to-digital (A/D) converter 123 which converts it into a corresponding digital signal. The digital signal is applied from the A/D converter 123 to a preprocessing circuit 124. The preprocessing circuit 124 utilizes a digital frequency conversion technique to convert the line number from 1125 lines to 625 lines, and also a non-interlace technique to provide, from each field of the HDTV signal simultaneously formed first and second fields each consisting of 625 lines and each displaying the same video image, but with the video images of the first and second fields being offset by 0.5 line distance. Moreover, the first and second fields produced from each field of the HDTV signal each occur at the rate of sixty per second. Thus, the preprocessing circuit 124 simultaneously provides a first digital video signal VD1 made up of only the first field and which contains 625 lines per frame and sixty frames per second, and a second digital video signal VD2 made up of only the second field and which contains 625 lines per frame and sixty frames per second. The first digital video signal VD1 is applied to a movement vector detection circuit 125, and also to a first field number conversion circuit 131. The second digital video signal VD2 is applied to a second field number conversion circuit 132 which is substantially the same in structure as the first field number conversion circuit 131. The movement vector detection circuit 125 detects movement vectors in response to the first digital video signal VD1. The non-interlace technique used in the preprocessing circuit 124 permits the movement vector detection circuit 125 to detect movement vectors at time intervals of 1/60 of a second. This is effective to improve the accuracy of detection of movement vectors and facilitate formation of interpolation signals. The movement vector detection circuit 125 produces field difference data between present field data and previous field data substantially in the same manner as described in connection with Figure 6 or Figure 9. The first field number conversion circuit 131 provides a digital video signal containing a first 625-lines per frame/50-frames per second field to one input of a switching circuit 141 which, at another input thereof, receives a second digital video signal containing a second 625-lines per frame/50-frames per second field and being provided by the second field number conversion circuit 132. The switching circuit 141 also receives a suitably generated control signal Sc which inverts at time intervals of 1/50 of a second so that the switching circuit 141 is changed-over at that rate and provides, at its output, a 625-lines per frame/50-fields per second digital luminance signal. This digital luminance signal is then applied to a digital-to-analog (D/A) converter 142 which converts it into a corresponding analog signal. The analog signal is applied from the D/A converter 142 through a low-pass filter 143 to a PAL colour encoder 144. The PAL colour encoder 144 receives additional inputs including red and blue colour difference signals R-Y and B-Y which have been each subjected to line and field-number conversion similar to that described for the luminance signal Y. The PAL colour encoder 144 supplies a composite colour television signal according to the PAL standard to an output terminal 145 which is for connection to a PAL colour television monitor or receiver. The first field number conversion circuit 131 includes a field memory 133, a movement correction circuit 134, a linear approximation circuit 135, a switching circuit 136, an error processing circuit 137, and a memory 138. The field memory 133 receives the first digital video signal VD1 from the preprocessing circuit 124 and provides, at its output, a digital video signal indicative of previous field data. The movement correction circuit 134 receives the first digital video signal VD1 indicative of present field data directly from the preprocessing circuit 124, the digital video signal indicative of previous field data from the field memory 133, and a movement vector indication signal from the movement vector detection circuit 125. The movement correction circuit 134 operates to reduce the field number by correcting movement of a moving object. This operation will be described in greater detail with reference to Figure 14, in which F1, F2, F3, F4, F5 and F6 indicate six image fields which appear in this sequence to represent uniform movement of a triangularly-shaped object from the left to the right. In each constant time interval of 1/60 of a second, the object moves a constant distance A which corresponds to the movement vector detected in the movement vector detection circuit 125. In the illustrated case, the six fields F1 to F6 are converted into five fields f1 to f5. Since the total distance of movement of the triangularly-shaped object is 5A between the fields F1 and F6, the field number can be reduced from six to five by shifting the image in the field F1 a distance (1/5)A to provide a shifted image in the field f1, shifting the image in the field F2 a distance (2/5)A to provide a shifted image in the field f2, shifting the image in the field F3 a distance (3/5)A to provide a shifted image in the field f3, shifting the image in the field F4 a distance (4/5)A to provide a shifted image in the field f4, and shifting the image in the field F5 a distance A to provide a shifted image in the field f5. Since the image in the field F6 is the same as the shifted image in the field f5, the last field F6, in effect, is removed. The image shifting operation can be realized by suitable memory address control. Although the movement correction circuit 134 can achieve complete field number conversion for images obtained during panning or tilting of a television camera if the movement vectors can be detected with high accuracy, problems could occur for images having objects moving simultaneously in various ways. Another way in which field number conversion can be effected by the movement correction circuit 134 is illustrated in Figure 15, in which F1, F2, F3, F4, F5 and F6 again indicate six image fields which appear in this sequence to represent uniform movement of an object from left to the right. In each constant time interval of 1/60 of a second, the object moves a constant distance A which corresponds to the movement vector detected in the movement vector detection circuit 125. In the illustrated case, the six fields F1 to F6 are converted into five fields f1 to f5 using previous and present field data. The field number can be reduced from six to five by halving the output signal corresponding to the sum of an image resulting from the shifting of the image in the field F1 by a distance (1/5)A, and an image resulting from the shifting of the image in the field F2 by a distance(-4/5)A to provide a shifted image in the field f1; halving the output signal corresponding to the sum of an image resulting from the shifting of the image in the field F2 by a distance (2/5)A and an image resulting from the shifting of the image in the field F3 by a distance (-3/5)A to provide a shifted image in the field f2; halving the output signal corresponding to the sum of an image resulting from the shifting of the image in the field F3 by a distance (3/5)A and an image resulting from the shifting of the image in the field F4 by a distance (-2/5)A to provide a shifted image in the field f3; halving the output signal corresponding to the sum of an image resulting from the shifting of the image in the field F4 by a distance (4/5)A and an image resulting from the shifting of the image in the field F5 by a distance (-1/5)A to provide a shifted image in the field f4; and halving the output signal corresponding to the sum of an image resulting from the shifting of the image in the field F5 by a distance A and the image in the field F6 to provide a shifted image in the field f5. Since the image provided by halving the output signal corresponding to the sum of the image in the field F6 and an image resulting from the shifting of the image in the next field F7 by a distance -A is the same as the image in the field f5, one of the images F6 and F7 is removed. Although the image resulting from the shifting of an image in the previous field by a distance (n/5)A is substantially the same as the image resulting from the shifting of an image in the present field by a distance [-(5-n)/5]A, in which n is an integer from 1 to 5, these images are desirably added, and the sum then halved, for equalizing the signal-to-noise (S/N) ratio relating to random noises produced during linear approximation and the S/N ratio relating to the random noises produced during movement correction, and also for vignetting the image when the movement vector is erroneously detected. The linear approximation circuit 135 operates to reduce the field number by calculating a weighted average of the images in two successive fields to which predetermined weights are respectively assigned. This operation will be described in greater detail with reference to Figure 16 in which F1, F2, F3, F4, F5 and F6 indicate six image fields which appear in this sequence at time intervals of 1/60 of a second. The smaller triangle in each field of Figure 16 indicates a moving object. In the illustrated case, the six fields F1 to F6 are converted by a weight (4/5) and the image in field F2 multiplied by a weight (1/5) are combined or averaged to provide an image in the field f1. Each triangle indicated in broken lines is the image in the subsequent field. The image in the field F2 multiplied by a weight (3/5) and the image in the field F3 multiplied by a weight (2/5) are combined to provide an image in the field f2. The image in the field F3 multiplied by a weight (2/5) and the image in the field F4 multiplied by a weight (3/5) are combined to provide an image in the field f3. The image in the field F4 multiplied by a weight (1/5) and the image in the field F5 multiplied by a weight (4/5) are combined to provide an image in the field f4. Finally, the image in the field F6 is used as the image in the field f5. Although linear approximation has a tendency to double or vignette a moving image, it can provide a better stationary image than movement correction. The error processing circuit 137 will now be described with reference to Figure 17 in which an input terminal 151 receives a digital video signal corresponding to the previous field F1 (Figure 18), and an input terminal 152 receives a digital video signal corresponding to the present field F2 (Figure 18). The digital video signals are applied from the terminals 151 and 152 to a subtracter 153 which produces field difference data FL corresponding to the difference between the previous and present field data by calculating differences in the positions or coordinates of the picture elements of the segmental area of the previous field fro the coordinates of the respective picture elements of the corresponding segmental area of the present field. The error processing circuit 137 also includes an input terminal 154 receiving a signal corresponding to the field f11 (Figure 18) and an input terminal 155 receiving a signal corresponding to the field f12 (Figure 18). The image in the previous field F1 is shifted a distance (2/5)A to provide an image in the field f11. The image in the present field F2 is shifted a distance (-3/5)A to provide an image in the field f12. These signals are supplied to a subtracter 156 which produces field difference data Δf by calculating differences in the positions or coordinates of the picture elements of the segmental area of the field f11 relative to the coordinates of the respective picture elements of the corresponding segmental area of field f12. The field difference data ΔFL and the field difference data Δf are compared in a comparator circuit 157. As shown in Figure 18, the images of the fields f11 and f12 are the same in respect to the position of the moving triangularly-shaped object and, thus, the field difference data Δf have no moving portion. The images of the fields F1 and F2 are the same in respect to the position of the stationary circular portion. Consequently, it can be determined that movement correction by circuit 134 is reliable when ΔFL is greater than Δf and that the movement correction is not reliable when ΔFL is less than Δf. The comparator circuit 157 produces a high level signal when ΔFL is greater than Δf and a low level signal when ΔFL is less than Δf. The output of the comparator circuit 157 is supplied to a majority logic circuit 158 which provides a decision for each of the segmental areas. More particularly, when the number of occurrences of a high level signal at the output of the comparator circuit 157 is greater than the number of occurrences of a low level signal at the output of the comparator circuit 157 for a segmental area, the majority logic circuit 158 provides a high level signal at an output terminal 159. Otherwise, the majority logic circuit 158 produces a low level signal at the output terminal 159 which is coupled to the switching circuit 136 in Figure 13. The switching circuit 136 connects the movement correction circuit 134 to the memory 138 in response to a high level control signal from the output terminal 159 to the error processing circuit 137. On the other hand, the switching circuit 136 is changed-over so as to connect the linear approximation circuit 135 to the memory 138 in response to a low level control signal from the error processing circuit 137. Therefore, movement correction by the movement correction circuit 134 is employed when a moving image is involved, and linear approximation by the linear approximating circuit 135 is employed when a stationary image is being processed.

Claims: An apparatus for deriving a movement vector indicating an amount and direction of a movement in a picture defined by a television signal made up of successive intervals, the apparatus comprising: means (13 to 17) for detecting difference data corresponding to the difference between data for a predetermined area of the picture in two of said successive intervals, wherein said successive intervals are frames of the television signal, said predetermined area is one of a plurality of segmental areas into which each of said frames is divided, and each of said segmental areas is represented by a representative picture element; gating means (18) for gating said difference data; means (20, 21) for producing a control signal for said gating means (18) which causes said gating means (18) not to pass said difference data in response to data indicating a stationary background portion of the picture and which causes said gating means (18) to pass said difference data in response to data indicating a moving object in the picture; means (22) for accumulating the difference data which pass through said gating means (18); and means (23) for detecting a minimum value of the accumulated difference data as an indication of said movement vector. Apparatus according to claim 1 further comprising means (27) responsive to said control signal for determining the incidence of non-passing of said difference data by said gating means (18), and means (24) for zeroing the detected minimum value of the accumulated difference data when said incidence exceeds a predetermined value. Apparatus according to claim 1 wherein said means (13 to 17) for detecting difference data includes subtracter means (12) having inputs receiving data for said predetermined area of the picture in a present one of said intervals and in a prior interval, respectively, and an output providing said difference data, and converting means (15) for converting the output of said subtracter means (12) into a corresponding absolute value of said difference data. Apparatus according to claim 3 wherein said means (20, 21) for producing the control signal includes detector means (20) for detecting the position of a picture element, and decision means (21) responsive to the detected position from said detector means (20) for providing said control signal. Apparatus according to claim 4 wherein said gating means (18) includes a switching circuit (18) having a first input (19A) receiving said absolute value of the difference data, a second input (19B) connected to a source of zero data, and an output (19C) selectively connected to said first and second inputs (18A, 19B) in response to said control signal from said decision means (21). Apparatus according to claim 5 wherein said means (22) for accumulating includes summing means (22) connected to said output (19C) of the switching circuit (18). Apparatus according to claim 6 further comprising a second switching circuit (24) having a first input (25A) connected to said means (23) for detecting a minimum value of the accumulated difference data, a second input (25B) connected to a source of zero data and an output, counting means (27) for counting the numbers of times said control signal causes connection of said second input (19B) to said output (19C) in the first mentioned switching circuit (18), reference means (28) for establishing a predetermined counted value, and comparator means (29) for comparing a number counted by said counting means (27) with said predetermined counted value and being operative to connect said output (25C) of said second switching circuit (24) to said second input of said second switching circuit (24) when said number counted by the counting means (27) attains said predetermined counted value, thereby to zero the detected minimum value of the accumulated difference data. Apparatus according to claim 3 wherein said means (20, 21) for producing the control signal includes memory means (57) for storing one of said intervals of the incoming television signal and providing output data for a previous interval during reception of a present interval, second subtracter means (58) having inputs receiving said incoming television signal and said output data from the memory means (57) and means (59) for thresholding a difference output of the second subtracter means (58) to provide said control signal for causing said gating means (56) to pass said difference data only when said difference output exceeds a predetermined threshold value. Apparatus according to claim 8 wherein said gating means (56) provides predetermined values to said means (60) for accumulating when said control signal causes said gating means (56) not to pass said difference data, and said means (60) for accumulating includes summing means (60) for providing a summation of the absolute values of the difference data passed through said gating means (56) and of said predetermined values. Apparatus according to claim 9 further comprising counting means (63) connected with said thresholding means (59) for receiving said control signal therefrom and counting the number of times said gating means (56) does not pass said difference data and providing a corresponding counted value, reference means (65) providing a reference value corresponding to a predetermined number, comparator means (66) for comparing said counted value with said reference value, and means connecting said comparator means (66) with said means (61) for detecting the minimum value of the accumulated difference data so as to zero the detected minimum value of the accumulated difference data when said counted value exceeds said reference value. Apparatus according to any one of the previous claims wherein said means (13 to 17) for detecting difference data includes means (13) for extracting said representative picture element for each of said segmental areas and providing data indicative of the video data and the position of said extracted representative picture element, memory means (14) for temporarily storing said data indicative of the video data and the positions of the extracted representative picture elements, and subtractor means (12) having first and second inputs receiving said television signal and data read out of said memory means (14) respectively, and an output at which said difference data are provided in correspondence to differences in the positions of the representative picture elements of respective segmental areas in a present frame and a previous frame, respectively.

Inventors: FUJITA, TADAO C/O PATENTS DIV. SONY CORP., KURITA, TAIICHIRO C/O NIPPON HOSO KYOKAI, MATSUMOTO, KUNIO C/O PATENTS DIV. SONY CORP., NINOMIYA, YUICHI C/O NIPPON HOSO KYOKAI, NISHIZAWA, TAIJI C/O NIPPON HOSO KYOKAI, OHMURA, TOSHIRO C/O NIPPON HOSO KYOKAI, OHTSUKA, YOSHIMICHI C/O NIPPON HOSO KYOKAI, TAKANASHI, KENJI C/O PATENTS DIV. SONY CORP., TANAKA, YUTAKA C/O NIPPON HOSO KYOKAI
Applicants: NIPPON HOSO KYOKAI, SONY CORPORATION
Application year: 1986
Main classification: H04N5
IPC codes: H04N5, G06T7