DUAL REDUNDANT ELECTRONIC POSTAGE METER

Abstract: A dual redundant electronic postage meter (10) and associated method is provided for increasing the reliability of meter operation, comprising a first meter module (12A) in­ cluding triple redundant memory techniques/dual redundant means (18A) and dual redundant microprocessor means (16A), a second meter module (12B) including triple redun­ dant techniques/dual redundant memory means (18B) and dual redundant microprocessor means (16B), the dual redun­ dant microprocessor means (16A) of the first meter module (12A) being adapted to be coupled to a data entry means and external output means, and the dual redundant micro­ processor means (16B) of the second meter module (12B) being adapted to be coupled to the data entry means and the external output means with the second meter module (12B) being activated in response to a failure in the operation of the first meter module (12A).

Description: BACKGROUND OF THE INVENTION The present invention relates to electronic postage meters, and more particularly to a dual redundant electronic postage meter for increasing the reliability of the meter operation. Various electronic postage meter systems have been developed, see for example, the systems disclosed in United States Patent No. 3,978,457 for Microcomputerized Electronic Postage Meter Systems, United States Patent No. 3,938,095 for Computer Responsive Postage Meter, European Patent Application 80400603.9 (EP-A-0 019 515), May 5, 1980, for Electronic Postage Meter Having Improved Security and Fault Tolerance Features, United States Patent No. 4,301,507, for Electronic Postage Meter Having Plural Computing Systems, and United States Patent No. 4,579,054, for Stand-Alone Electronic Mailing Machine. Generally electronic postage meters include some form of non-volatile memory capability to store critical postage accounting information. This information includes, for example, the amount of postage remaining in the meter for subsequent printing and the total amount of postage already printed by the meter. Other types of accounting or operating data may also be stored in the non-volatile memory, as desired. However, conditions can occur in electronic postage meters where information stored in non-volatile memory may be lost. A total line power failure or fluctuation in voltage conditions can cause the microprocessor associated with the meter to operate erratically and either cause erasure of data or the writing of spurious data in the non-volatile memory. The erasure of data or the writing of spurious data in the non-volatile memory result in a loss of critical accounting information. Since the accounting data changes with the printing of postage and is not permanently stored elsewhere, there is no way to recapture or reconstruct the lost accounting information. Under such circumstances, it is possible that a user may suffer a loss of postage funds. To minimize the likelihood of a loss of information stored in the non-volatile memory, various approaches have been adopted to insure the high reliability of electronic postage meters. It is known from the aforementioned United States Patent Nos. 3,978,457 and 4,579,054 to provide a microprocessor controlled electronic postage meter having memory architecture which includes a temporary storage memory for storing accounting data reflecting each meter transaction and a non-volatile memory to which the accounting data is transferred during the power down cycle of the meter. Another approach for preserving the stored accounting data has been the use of redundant non-volatile memories. One such redundant memory system is disclosed in United States Patent No. 4,566,406 for Frank T. Check, Jr., and entitled Electronic Postage Meter Having Redundant Memory. With such redundant memory system the two redundant non-volatile memories are interconnected with a microprocessor by way of completely separate data and address lines to eliminate error conditions. The data stored in each memory is the same, although the data may be stored in a different form in each memory, e.g., it may be coded. The data is applied to the memories simultaneously or sequentially at different times during the postage transactions. Another redundant memory system is disclosed in the aforementioned European Patent Application 80400603.9. In such patent application, the same accounting data is written into each of the two non-volatile memories, designated BAMs, by updating the specific registers of the BAMs twice during each postage meter transaction, once in temporary form and once in permanent form to minimize the loss of accounting data during microprocessor failure. EP-A-0 172 573, filed on August 22, 1985 and entitled, Electronic Postage Meter Having Multiple Non-Volatile Memories For Storing Different Historical Information Reflecting Postage Transactions, disclosed a first non-volatile memory having cumulative historical information of postage transactions written therein during the power down cycle of the meter and a second non-volatile memory having a greater data storage capacity than the first non-volatile memory for sequentially writing historical information regarding each trip cycle of the meter in a different address in the second non-volatile memory in real time as each postage transaction occurs so that two different records of historical information regarding the postage transactions are provided. EPA-0 172 574 entitled Memory Address Location System for an Electronic Postage Meter Having Multiple Non-Volatile Memories, discloses a non-volatile memory for storing data which data is used to locate the next memory address in which to write data in another non-volatile memory. EP-A-0 085 385 (Fig.6) discloses a microprocessor system for electronic postage meters which comprises two redundant microprocessors for controlling two redundant memories. US-A-4 358 823 teaches a double redundant processor comprising four CPU's and two memories. However, although the aforementioned systems have contributed to increased meter reliability, occasions may occur during meter operation when it is desirable to provide increased meter reliability. For example, if there is microprocessor failure and/or a failure of both NVMs. This invention deals both with the primary function "accounting" arithmetic process, and data storage by providing for redundant microprocessors and memory means. The methodology described allows for detecting and locating source of critical process and data storage errors. Consequently dual redundancy within a module and dual redundant modules provide a significant increase in meter reliability. SUMMARY OF THE INVENTION It is an object of the present invention to provide an ultra-reliable dual redundant electronic postage meter. It is a further object of the present invention to provide an ultra-reliable dual redundant electronic postage meter which facilitates serviceability and minimizes any possible loss of funds. It is a further object of the present invention to provide an ultra-reliable dual redundant electronic postage meter in which the control, accounting and printing functions are combined in an integrated circuit. It is a further object of the present invention to provide an ultra-reliable electronic postage meter employing triple redundancy techniques for decision making. It is a further object of the present invention to provide an ultra-reliable electronic postage meter for verifying the positional accuracy of the printwheels. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter with an event based error detection system. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter with real time control of the meter accounting functions. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter in which the memory is organized on a byte basis. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter for storing retry and switch flags in memory. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter with dual segmented ROMs. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter having dual redundant memories which are address partitioned. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter in which error detection, location and retry is utilized for error correction and decision making. Retry occurs either for a primary or secondary event. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter in which the control sum is retrieved only once, during power up of the meter. It is a still further object of the present invention to provide an ultra reliable electronic postage meter having various instructions for certain defined errors. It is a still further object of this invention that error detection/location correction will occur in "real time" during event occurrence on a transaction basis, such real time control to include error detection and location. It is a still further object of the present invention to provide an ultra-reliable electronic postage meter in which errors are corrected under defined conditions to guarantee accuracy in the data reflecting the amount of postage used (AR) and the amount of postage remaining in the meter (DR). Briefly, in accordance with the present invention, a dual redundant electronic postage meter and associated method is provided for increasing the reliability of an electronic postage meter, comprising a first meter module including dual redundant memory means and dual redundant microprocessor means. This allows for triple redundancy techniques in either error detection, localization and correction. A second meter module including dual redundant memory means and dual redundant microprocessor means, the dual redundant microprocessor means of the first meter module is adapted to be coupled to a data entry means and external output means, and the dual redundant microprocessor means of the second meter module is adapted to be coupled to the data entry means and the external output means with the second meter module being activated in response to a failure in the operation of the first meter module. Other objects, aspects and advantages of the present invention should be understood from the detailed description considered in conjunction with the drawings, as follows. BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is a block diagram illustrating a dual redundant electronic postage meter in accordance with the present invention; FIGURE 2 is an enlarged view of the dual redundant memories segmented to provide various data storage addresses; FIGURE 3 is an enlarged view of the dual segmented ROMs, segmented to provide various data storage addresses; and FIGURE 4 is a flow chart of an error detection routine for use with the dual redundant electronic postage meter of the present invention. FIGURES 5-7 are further flow charts helpful to understanding the invention. DETAILED DESCRIPTION Referring to Fig. 1, a dual redundant electronic postage meter in accordance with the present invention is illustrated generally at 10. The dual redundant electronic postage meter 10 includes a pair of identical meter modules 12A and 12B. Each meter module 12A and 12B includes a CMOS array 14A or 14B which is electrically coupled to display buffers and drivers and a power supply for reset control. The CMOS processor 16A or B has internal to the microprocessor chip both ROM and RAM. The internal ROM stores programs which enables it to control microprocessor action arithmetic and otherwise, relating to the meter operation. It defines what sequence of action takes place as regards this operation and responses determined by its sensors. It directs accounting operation (address) and data to be stored in the RAM, defines when such data is to be transferred NVM, etc. Redundant NVM memories 18A in module A or 18B in module B store critical accounting information. During power up critical accounting information in NVM transfers to "RAM". Triple redundancy per module -- a "RAM" in the microprocessor and multiple BAMs or NVM (2) allow for error localization and detection during power up/down and while power is on during the select, accounting and print phase of meter operation. The methodology enables verification of the ability to proceed to the next instruction (event) during the accounting process and verification of data integrity after arithmetic and print process. Historical data is only updated at power down. A second CMOS microprocessor 20A or 20B is also part of the meter modules 12A and 12B. This redundant microprocessor is a mirror image of microprocessor 16A or 16B. In addition to the internal ROM which has the same instruction set as 16A or b. It has a dual ROM which could be a segmented on a use basis. This ROM could be a ROM or EPROM, etc. or two ROMs. The dual ROM 24A/B serves three purposes, one segment is involved in control of external devices when used in this mode it bypasses the internal ROM. All instruction for handling any and all external devices is the system in resident in the external ROM. It also contains instructions for sharing the microprocessor if the microprocessor is being used for both activities due to a failure of the other microprocessor in module A or identically in module B. This ROM also contains all instruction which relates to methodology of switching microprocessors and control instructions as well as setting the conditions for retry, and for determining a module switch if necessary. A retry system as shown in Fig. 4 is incorporated to assure we have not responded to a strictly transient conditions. This is a real time system. Each transaction is verified before print and stored in NVM. The data integrity is checked again before the next arithmetic process. The sequence indicated in Fig. 4 allows the determination of a problem in the microprocessor and whether it is a soft or hard failure. It provides a mechanism to determine if it is in the BAMs which one of microprocessor's and whether this is a hard or soft failure. This process defines the need for a switch whether it is a microprocessor switch or a module switch. This is done as a consequence of loss of data integrity in one of the BAMs or malfunction of the microprocessor related to data integrity or incorrect instruction sequencing. Since the BAMs are battery backup or a ROM type. A momentary loss of power due to a power supply failure or line problems does not cause the loss of data from the last transaction. Total operation history is updated on a power down sequence detected at the microprocessor. It will trigger a total memory operation if power to the microprocessor is maintained. If not operation history could be lost (partially). However, since all parts are CMOS, a separate battery backup to the microprocessor will simplify the power controls necessary to the system and because of its redundance increase reliability and guarantee total transfer. The CMOS arrays 14A and 14B are electrically coupled to print head drivers, sensor-buffers and the power supply represented by numeral 26 for actuation of the stepper motors and sensors (not shown). Advantageously, a fan 26 as shown schematically in Fig. 1 may be employed to cool tile CMOS devices of the meter 10 to aid in preventing latch-up. Cooling of module itself is also possible in package cooling. In order to allow for activation of the second meter module 12B and further minimize fund loss, the second meter module memories can be updated with regard to its contents at power down or switch. The dual redundant memory means of the second meter module 12B is coupled to the output memory means of the first meter module 12A to allow this event to occur. Since both meter modules are on battery backup power as regards memory devices this process can be initiated at power down or during a switching operation. It would require no additional power maintenance procedures. Advantageously, if one of the modules 12A or 12B is or becomes defective the module 12A or 12B may be readily replaced at the customer facility by a service representative without affecting information stored. Referring to Fig. 2, the dual redundant memory 18A is illustrated including a first NVM or CMOS BAM 28A and a second NVM or CMOS BAM 30A. It should be understood that the redundant memory 18B is identical. The first and second NVMs 28A and 30A are batteryaugmented memories (BAMs) to provide real time control of accounting accuracy for data recording. Further, each memory address 32A-P and 34A-P is alternate with respect to the other memory address to provide increased data integrity and minimum interferences. It is organized on a byte basis to increase speed by providing data transfer with a single instruction. However, it should be understood that NVMs or CMOS BAMs 28A and 30A have an identical architecture and have identical data stored therein so that accuracy checks between BAMs can be made. Both NVMs are in operation to allow triple redundancy techniques to operate. Likewise with the dual redundant memory 18B. Referring to Fig. 3, the dual ROM 24A is illustrated including first ROM 36A and second ROM 38A. It should be understood that the dual ROM 24B is identical. The ROMs 36A and 38A are preferably CMOS ROMs and may be EPROMs or EAROMs, as desired. Each address 40A-M and 42A-M is segmented from the other memory addresses to provide error detection based on events and location and allow for I/0 control as well as real time transaction error detection action. Further, retry (recover) and switch (device) flags, instructions may be stored in the segmented addresses 40A-M and 42A-M of ROMS 36A and 38A, respectively, as desired, to facilitate error detectiondefine actions. If one ROM 36A or 38A fails the other ROM 36A or 38A is placed in operation. Likewise with the dual ROM 24B. The detection, localizing, error correction programs for the meter stored in the dual ROMs 24A and 24B, provide for errors that are detected based on a sequence of certain events, defined conditions which guarantee accuracy in the total amount of the meter postage used to date (AR) and the total amount of postage remaining in the meter for use (DR). Data stored in RAM relating to an accounting transaction during meter operation is written into suitable address in redundant memory on a transaction by transaction basis allowing for triple redundancy for decision making to occur. At power down, both the last transaction and relevant historical information is transferred to NVM or BAM. At power up the last relevant state of the system is written back into RAM (up). Triple redundancy is employed for each decision. Once a decision is made, a simple technique based on event is used under control of the program in the dual ROMs 24A and 24B to achieve correction or switch. The control sum for the meter which represents the sum of AR and DR is verified by a subroutine either stored in the dual ROMs 24A and 24B and is checked once during power up/power down before normal operation begins. While the meter is in operation -- power on, data verification on a a transaction by transaction basis allows triple redundancy techniques to be used to detect, locate, define and correct errors. And modify relevant component usage within the module and between modules user of A or B. Advantageously, sensors, e.g., data integrity checks, in the form of photocells, are positioned adjacent to the printwheels to verify the mechanical position thereof. Referring to Fig. 4, a flow chart is generally illustrated at 50 demonstrating a method of defining type as well as correcting errors in meter operation. Three possible failure/error events can occur and must be detected during the reading of data from memory. These failures/errors are defined as follows: Hard Failure : A physically impaired or defective component which requires the meter to immediately enter the power down cycle, if data integrity is in question, can signal a need to switch the internal microprocessor based on decision loop or module depending on device failure. Soft Failure : Data is incorrectly read due to external conditions. This may be caused by transients such as noise or similar system problems brought on by environment (temperature, voltage stress, mailing machine interactions, etc., power-down, and marginal I/0 signal. Soft Error : The data error is internal to a component (malfunction). The error is corrected (memory-based) by rewriting the data in RAM or device in question. Specifically, referring to the flow chart 50 or Fig. 4, initially, the microprocessor 16A or 16B, under control of the programs in the dual ROMs 24A or 24B, initiates a memory write sequence for writing data in selected memory addresses of the RAMs of the microprocessors 16A and 20A or 16B and 20B. After data is written in the selected addresses, the memories are read. If the data is correct, the microprocessor 16A or 16B goes to the next operation. However, if the data is not correct the memory address is reread. If the data is now correct, a soft failure is diagnosed. If the data is still incorrect, the memory address is read a third time. If the data is now correct, a soft error is diagnosed. If the data is still incorrect, a hard failure is diagnosed and localized to the component, i.e., microprocessor or redundant memories which one. A switch to redundant microprocessor internal to module is made. In Figs. 5-7 verification of operation is made and transaction completed. If one of the NVMs (BAMs) dual redundant memories 18A and 18B are incorrect it is disabled, transaction completed and then the module is switched. The system only powers down if an error is detected during the accounting process, depending on whether that specific event is retryable, or if a decision based on two correct out of three can not be made. At that point, the second module is switched on operational verified and resumes meter operation. It will also power down if the sensors, printer, etc., is jammed or not operational independent of the accounting function. This process is controlled by the CMOS array. By providing dual meter modules 12A and 12B with dual redundant memories 18A and 18B, and dual ROMs 24A and 24B, an entire back-up meter module is provided as well as back-up components within each meter module, 12A and 12B, this will regardless of errors in some of the system components minimize meter returns as result of malfunction, increase serviceability, as well as substantially eliminate any loss of funds. If a Soft Error is detected in a particular memory location, the malfunctioning component is deactivated and its dual redundant counterpart is activated, if not already operational. In operation, the meter is powered-up by actuating a switch (not shown) which enables an external power supply (not shown) to supply energy to the meter modules 12A and 12B. As a result of the programs or sets of data instructions stored in the dual ROMs 24A and 24B, a check sum routine is initiated to check the control sum. Thereafter, the meter begins operation with the accounting data previously stored in the redundant memories 18A and 18B being read into the RAMs associated with the CMOS microprocessors 16A and 20A, and 16B and 20B. The display, e.g., which may be in the form of LEDs, is actuated by the CMOS arrays 14A and 14B in response to data entered through the keyboard (not shown). The accounting data for each postal operation of the meter is stored in the RAM associated with the microprocessor 14A or 16A, or 14B or 16B. Additionally, the outputs from the CMOS arrays 14A or 14B are applied to printhead drivers to actuate the stepper motors and sensors for the printwheels. External devices interact with the meter under control of the CMOS microprocessors 20A or 20B through the opto-isolator 22A or 22B. The dual ROMs 24A and 24B supply sets of data instructions to the CMOS microprocessors 16A and 20A and 16B and 20B, respectively, in accordance with the desired operation of the meter related to I/0 and data integrity actions. The internal ROM of 16A/20A 16B/20B provides instruction relating to normal operation of the meter. The redundant memories 18A and 18B receive and store data permanently when the meter undergoes a power down cycle prior to deactivating the meter 10. It should be understood by those skilled in the art that various modifications may be made in the present invention within the scope of the appended claims.

Claims: A dual redundant electronic postage meter (10) for increasing the reliability of an electronic postage meter, comprising: a first meter module (12A) including dual redundant memory means (18A) and dual redundant microprocessor means (16A); a second meter module (12B) including dual redundant memory means (18B) and dual redundant microprocessor means (16B); said dual redundant microprocessor means (16A) of said first meter module (12A) being adapted to be coupled to a data entry means and external output means; and said dual redundant microprocessor means (16B) of said second meter module (12B) being adapted to be coupled to the data entry means and the external output means, said second meter module (12B) being activated in response to a failure in the operation of said first meter module (12A). The dual redundant electronic postage meter (10) recited in Claim 1, wherein: said first and second means meter modules (12A,B) are programmed to undergo triple redundancy prior to arriving at a decision. The dual redundant electronic postage meter (10) recited in Claim 2, wherein: said first and second meter modules (12A,B) are programmed to undergo triple redundancy prior to arriving at each accounting decision. The dual redundant electronic postage meter (10) recited in Claim 1, including: printhead driver means (26) electrically coupled to said first and second meter modules (12A,B), said printhead drive means (26) being adapted to be coupled to stepper motors which actuate the print wheels; sensor means positioned proximate to the print wheels and coupled to said first and second meter modules (12A,B) for verifying the positional accuracy of the print wheels. The dual redundant electronic postage meter (10) recited in Claim 1, wherein: said dual redundant memory means (18A,B) of said first and second meter modules (12A,B) include battery augmented memories (28A,30A) for real time control of the meter accounting functions. The dual redundant electronic postage meter (10) recited in Claim 1, wherein: said dual redundant memory means (18A,B) of said first and second meter modules (12A,B) are organized to receive and store data on a byte basis. The dual redundant electronic postage meter (10) recited in Claim 1, wherein: said dual redundant memory means (18A,B) of said first and second meter means (12A,B) are segmented with memory addresses (40A-M,42A-M) for the storage of data corresponding to retry and switch flags. The dual redundant electronic postage meter (10) recited in Claim 1, including: a first dual segmented ROM (24A) for said first meter module (12A); a second dual segmented ROM (24B) for said second meter module (12B). The dual redundant electronic postage meter (10) recited in Claim 1, including: cooling means for cooling said first and second meter modules. The dual redundant electronic postage meter (10) recited in Claim 1, wherein: said dual redundant microprocessor means (16A,B) include CMOS devices. The dual redundant electronic postage meter (10) recited in Claim 1, wherein: said dual redundant memory means (18A,B) of said first and second meter means (12A,B) each includes first address means for storing data representing the amount of postage previously used by the meter (AR), second address means for storing data representing the amount of postage remaining in the meter for use (DR), and third address means for storing data representing the sum of AR and DR, which is designated as the control sum. The dual redundant electronic postage meter (10) recited in Claim 11, wherein: the control sum may be retrieved from said dual redundant memory means (18A,B) upon request of said dual redundant microprocessor means (16A,B). The dual redundant electronic postage meter (10) recited in Claim 1, wherein: said dual redundant memory means (18A,B) include a memory address for storing data corresponding to a flag for address partitioning said dual redundant memory means (18A,B). The dual redundant electronic postage meter (10) recited in Claim 11, wherein: said dual redundant microprocessor means (16A,B) access said third address means to retrieve the control sum only during power-up of the meter. The dual redundant electronic postage meter (10) recited in Claim 8, wherein: said dual segmented ROMs (24A,24B) include a first series of data instructions for determining a hard failure, a second series of data instructions for determining a soft failure and a third series of data instructions for determining a soft error. A method for increasing the reliability of an electronic postage meter, comprising the steps of: providing a first meter module (12A) with dual redundant memory means (18A) and dual redundant microprocessor means (16A); providing a second meter module (12B) with dual redundant memory means (18B) and dual redundant microprocessor means (16B); coupling said first and second meter modules (12A,B) to a data entry means and external output means; and undergoing redundant decisional operations in response to data inputted into the data entry means. The method recited in Claim 16, wherein: the undertaking step includes triple redundancy for arriving at each decision. The method recited in Claim 16, including the step of: using triple redundancy for arriving at each accounting decision. The method recited in Claim 16, including the step of: coupling printhead driver means (26) to the first and second meter modules (12A,B); coupling the printhead driver means (26) to stepper motors which are mechanically coupled to print wheels; positioning sensor means proximate to the print wheels for verifying the positional accuracy of the print wheels. The method recited in Claim 16, including the step of: providing real time control of the meter accounting decisions. The method recited in Claim 16, including the step of: organizing the dual redundant memory means to receive and store data on a byte basis. The method recited in Claim 16, including the step of: segmenting the dual redundant memory means (18A,B) with memory addresses (40A-M;42A-M) for the storage of data corresponding to retry and switch flags. The method recited in Claim 16, including the steps of: providing a first dual segmented ROM (24A) for the first meter module (12A); providing a second dual segmented ROM (24B) for the second meter module (12B). The method recited in Claim 16, including the step of: cooling the first and second meter modules (12A,B). The method recited in Claim 16, including the step of: providing a first address in the dual redundant memory means (18A,B) for storing data representing the amount of postage previously used by the meter (AR); providing a second address in the dual redundant memory means (18A,B) for storing data representing the amount of postage remaining in the meter for use (DR); providing a third address in the dual redundant memory means for storing data representing the sum of AR and DR, which is designated as the control sum. The method recited in Claim 25, including the step of: retrieving the control sum from the dual redundant memory means (18A,B) upon request of said dual redundant microprocessor means (16A,B). The method recited in Claim 16, including the step of: storing data in the dual redundant memory means (18A,B) corresponding to a flag which address partitions the dual redundant memory means (18A,B). The method recited in Claim 25, including the step of: accessing the third address in the dual redundant memory means (18A,B) to retrieve the control sum only during power-up of the postage meter. The method recited in Claim 23, including the step of: providing a first series of data instructions in the dual segmented ROMs (24A,B) for determining a hard failure of the meter; providing a second series of data instructions in the dual segmented ROMs (24A,B) for determining a soft failure of the meter; and providing a third series of data instructions in the dual segmented ROMs (24A,B) for determining a soft error of the meter. The method recited in Claim 16, including the step of: deactivating the first meter module (12A;B) and activating the second meter module (12B;A) upon detection of an error in the first meter module (12A;B). A method for increasing the reliability of an electronic postage meter, comprising the steps of: providing a first meter module (12A) with dual redundant memory means (18A) and dual redundant microprocessor means (16A); providing a second meter module (12B) with dual redundant memory means (18B) and dual redundant microprocessor means (16B); coupling said first and second meter modules (12A,B) to a data entry means and external output means; undergoing triple redundant decisional operations in response to data inputted into the data entry means; using triple redundancy for arriving at each accounting decision; coupling printhead driver means (26) to the first and second meter modules (12A,B); coupling the printhead driver means (26) to stepper motors which are mechanically coupled to print wheels; positioning sensor means proximate to the print wheels for verifying the positional accuracy of the print wheels; providing real time control of the meter accounting decisions; organizing the dual redundant memory means (18A,B) to receive and store data on a byte basis; segmenting the dual redundant memory means (18A,B) with memory addresses (40A-M,42A-M) for the storage of data corresponding to retry and switch flags; providing a first dual segmented ROM (24A) for the first meter module (12A); providing a second dual segmented ROM (24B) for the second meter module (12B); cooling the first and second meter modules (12A,B); providing a first address in the dual redundant memory means (18A,B) for storing data representing the amount of postage previously used by the meter (AR); providing a second address in the dual redundant memory means (18A,B) for storing data representing the amount of postage remaining in the meter for use (DR); providing a third address in the dual redundant memory means (18A,B) for storing data representing the sum of AR and DR, which is designated as the control sum; storing data in the dual redundant memory means (18A,B) corresponding to a flag which address partitions the dual redundant memory means (18A,B); providing a first series of data instructions in the dual segmented ROMs (24A,B) for determining a hard failure of the meter; providing a second series of data instructions in the dual segmented ROMs (24A,B) for determining a soft failure of the meter; and providing a third series of data instructions in the dual segmented ROMs (24A,B) for determining a soft error of the meter. The method recited in Claim 31, including the step of: retrieving the control sum from the dual redundant memory means (18A,B) upon request of the dual redundant microprocessor means. The method recited in Claim 31, including the step of: accessing the third address to retrieve the control sum only during power-up of the postage meter. The method recited in Claim 31, including the step of: deactivating the first meter module and activating the second meter module upon detection of an error in the first meter module.

Inventors: WIENER, PATRICIA P.
Applicants: PITNEY BOWES INC.
Application year: 1986
Main classification: G07B17
IPC codes: B41J3, G06Q50, G06F11, G07B17