WAVEFORM PROCESSING CIRCUIT

Abstract: A wave processing circuit includes a switching circuit (3) having first and second inputs (3a, 3b) and one output (3c). The first input is adapted to receive head portions and data portions contained in tne reproduced signal from an optical head (50). The second input receives a level signal represent­ ing the level of the head portion or the level of the signal carry­ ing the head portion. The switching circuit is operable to move between a first state in which the first input and the output are connected, and a second state in which the second input and the output are connected. A control signal producer (56, 58, 60) is provided for producing a first control pulse (S2) indica­ ting the presence of the data portion. The first control pulse is applied to the switching circuit for actuating the switching cir­ cuit to establish the first state when the first control pulse is present, and to establish the second state when the first con­ trol pulse is not present, so that the switching circuit con­ tinuously produces the signal having a level within the range of the head portion. Thus, no abrupt change caused by the transient phenomena will be observed in the high pass filter connected to the switching circuit.

Description: The present invention relates to a waveform processing circuit for use, for example, in a reproducing circuit of a photomagnetic disc system. The wave form processing circuit will be described in connection with a reproducing circuit of a photomagnetic disc system, as an example. A photomagnetic disc recording and reproducing system has a laser beam generator for generating a converged laser beam having a diameter of about 1 micrometer on a disc. The disc has a laminated film which shows a photomagnetic effect. Under the recording mode, a relatively strong pulsating laser beam (high level beam) carrying information is impinged on the disc to increase the temperature of the impinged spot on the film. The spot on the film where the temperature is increased looses the coercive force so that when the spot is magnetized in a certain direction effected by a magnetic field produced around the disc by a magnetic field generator information is recorded. Under the reproducing mode, relatively weak and constant lineally-polarized laser beam (low level beam) is impinged on the disc and the reflected beam is detected by a detector. By the Kerr magnetooptical effect on the film, the reflected beam shows some inclination of the polarization face due to the change of magnetized direction of the film. When the inclination is viewed through an analyzer, a pulsating signal representing the change of the inclination can be detected by a light detector. The pulsating signal produced from the light detector will be the reproduced signal. Generally, the recording of information on the photomagnetic disc is effected on a track aligned with a plurality of sectors (Fig. 2), each sector including a head portion where the address data and other similar data are stored with a high frequency signal in a predetermined format, and a data portion, following the head portion, which is utilized for recording and reproducing the desired data at a high frequency. During the recording mode, the head portion is impinged with a low level beam to read out (reproduce) the address data and other data stored therein thereby locating the sector on the disc now being impinged with the beam. Then, the data portion following the detected head portion is impinged with the high level bean carrying information to record data. During the reproducing mode, the head portion is reproduced by the low level beam in the same manner to locate the sector now being impinged with the beam, and then, the data portion following the head portion is impinged with the low level beam to reproduce the recorded data. Accordingly, even in the recording mode, the reproducing operation is carried out for reading the address data in the head portion. The reproduced signal Sa from the light detector, such as shown in Fig. 2, contains a high frequency component signal (VD-VL) or (VP-VL) carrying wanted data and a low frequency component signal VL caused by the conversion between the optical signal and the electric signal. The head portion contains a high frequency signal (VD-VL). The data portion contains, under the recording mode, a high frequency signal (VP-VL), and under the reproducing mode, a high frequency signal (VD-VL). The signal (VP-VL) is greater than the signal (VD-VL). In order to remove the low frequency component VL, a high pass filter such as defined by a coupling capacitor Ca and a resistor Ra as shown in Fig. 1 is used. The reproduced signal as obtained from the light detector is a current signal, which is converted to a voltage signal by a suitable current-voltage converter. The reproduced signal Sa in the voltage form as produced from the current-voltage converter is applied to the high pass filter, and the filter produces a filtered signal Sb which is also shown in Fig. 2. When the input signal Sa under the recording mode is applied to the high pass filter, the high pass filter produces an output signal Sb such that the low frequency signal VL is cut off, and the high frequency signal (VD-VL) passes therethrough. But due to the transient phenomena of the high voltage signal VP, the output signal Vo will be deformed greatly. More specifically, as shown in Fig. 2, the output signal Sb gradually decreases after the receipt of the leading edge of the high voltage signal VP and gradually increases after the receipt of the trailing edge of the high voltage signal VP. In this case, since the head portion, as included in the gradual increasing line, may be located outside the dynamic range, the head portion may not be properly read in the subsequent stage, such as the signal detector. Although it is possible to widen the dynamic range to include the head portion therein, the signal becomes poor particularly when the signal is detected at the comparator. US-A-4 433 255 discloses a signal sampling gate circuit suitable for supplying signals to be sampled obtained from a plurality of signal heads in a colour videotape recorder. Because of the different amplitude levels provided by different signal heads, transient sags occur when the reading signal head changes. For eliminating such transient sags, a switching means is provided that, according to a head switch pulse, alternately connects one of two inputs with an output. Each input of the switching means is connected to a sample and hold circuit and a subsequent filter. The reading data from each signal head are levelled with respect to the data of the previous cycle provided by the same signal head. During the recording mode, the switching of the switching means has no effect, because the signals to be recorded are obtained from the same source, e.g. an antenna, and do not contain transient signal sags. It is an object of the invention to provide an electrical circuit for a signal reading/recording apparatus where the output signal is not deformed by transient phenomena due to high pass filtering high frequency signals of high amplitude when switching over between recording and reproducing modes. The problem is solved, according to the invention, with the features of claim 1, or of claim 2, respectively. These and other objects and features of the present invention will become apparent from the following description taken in conjunction with preferred embodiments thereof with reference to the accompanying drawings, throughout which like parts are designated by like reference numerals, and in which: Fig. 1 is a circuit diagram of a prior art high pass filter; Fig. 2 is a graph showing waveforms of the reproduced signal before and after the reproduced signal is applied to the high pass filter of Fig. 1; Fig. 3 is a block diagram of a photomagnetic disc system according to the present invention; Fig. 4 is a graph showing waveforms obtained at various blocks shown in Fig. 3; Fig. 5 is a graph showing a detail of a portion V shown in Fig. 4; Fig. 6 is a circuit diagram of a waveform processing circuit according to a first embodiment of the present invention; Fig. 7 is a graph showing waveforms obtained at various points in the circuit of Fig. 6; Fig. 8 is a circuit diagram of a waveform processing circuit according to a second embodiment of the present invention; Fig. 9 is a graph showing waveforms obtained at various points in the circuit of Fig. 8; Fig. 10 is a circuit diagram of an equalizer; Fig. 11 is a circuit diagram of a signal detector; Fig. 12 is a graph showing waveforms obtained at input and output of the circuit of Fig. 11; Fig. 13 is a circuit diagram of an improved signal detector; and Fig. 14 is a graph showing waveforms obtained at input and output of the circuit of Fig. 13. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 3, a photomagnetic disc system is shown which comprises an optical head 50 from which laser beam is produced onto a disc 62, a wave form processing circuit 52, equalizer 54 and signal detector 56 which are connected in series. Signal detector 56 is connected to a head portion detector 58 which is in turn connected to a timing pulse generator 60. Timing pulses S1 and S2 produced from the timing pulse generator 60 are used in the waveform processing circuit 52. The signals produced from these circuits are described below with reference to Figs. 4 and 5. Optical head 50 produces a reproduced voltage signal Sa containing high frequency head portions and high frequency data portions appearing alternately and separated with suitable intervals. The head portions and the data portions are carried on a low frequency signal VL. During the recording mode, the data portions have a relatively high amplitude, and during the reproducing mode, the data portions have a relatively low amplitude, which is the same as that of the head portions. Waveform processing circuit 52 receives the signal Sa and produces a signal Sb which is different between the recording mode and reproducing mode. Under the recording mode, the signal Sb contains only the head portions, and under the reproducing mode, it contains both the head portions and the data portions. In the waveform processing circuit 52, the low frequency signal VL is cut off, so that the head and data portions are now carried on a zero level. According to the present invention no deformation of the output signal Sb is observed which wall cause the head portion to be swung out from a predetermined range. The detail of the waveform processing circuit 52 will be described later in connection with Figs. 6-9. Equalizer 54 is provided to compensate for an undesired phase frequency response, and produces a signal Sc (Fig. 5) which is substantially the same as the signal Sb, but the waves are more standardized and the slopes are made more steep. An example of equalizer 54, defined by a transversal filter, is shown in Fig. 10 which comprises first and second delay circuits DY1 and DY2, buffer amplifiers B1, B2 and B3 and operational amplifier OP1. Other example of the equalizer is disclosed, for example, in Japanese Patent Laid-Open Publication No. 60-107736 published June 13, 1985. Signal detector 56 changes the sinusoidal high frequency wave signal contained in the head portion and data portion to a rectangular pulse signal in a binary form. Thus, signal detector 56 produces signal Sd, as shown in Fig. 5, which is provided to a data demodulator (not shown) and also to head portion detector 58. The detail of signal detector 56 will be described later in connection with Figs. 11-14. Head portion detector 58 is provided to produce a reference pulse (signal Se) upon detection of the head portion. Timing pulse generator 60, according to the first embodiment, generates control pulses S1 and S2 under the recording mode and no control pulse under the reproducing mode. Timing pulse generator 60 includes a counter or a delay circuit for counting times T1, T2, T3 and T4, shown in Fig. 4, after the reference pulse Se is generated so as to prepare control pulses S1 and S2. As apparent from Fig. 4, the control pulse S1 has a pulse duration a little greater than the duration of the data portion so as to include the data portion while the control pulse S1 is generated. The control pulse S2 has a pulse duration the same as the duration of the data portion and is synchronized with the data portion. The control pulses S1 and S2 are, used in the waveform processing circuit 52 for extracting the data portion during the recording mode. The control pulses generated in the second embodiment, such as shown in Fig. 9, are different from those of the first embodiment, but are generated in a similar manner described above, and are used for the same purpose. The timing pulse generator 60 further produces other pulses to control other circuits (not shown). Referring to Fig. 6, a first embodiment of the wave form processing circuit 52 is shown, which comprises a switching circuit having terminals 3a, 3b and 3c. Terminal 3a is connected to the optical head 50 so as to receive the signal Sa directly. Terminal 3b is connected to the optical head 50 through a series connection of a sample holding circuit 4 and a low pass filter 5. Terminal 3c is connected to a high pass filter defined by capacitor Ca and resistor Ra. The output Sb of the high pass filter is produced as the output of the waveform processing circuit 52. Sample holding circuit 4 is controlled by control pulse S1 so as to sample the signal Sa in response to the leading edge of the control pulse S1 and holds the sampled signal while the control pulse S1 is present. When the control pulse S1 is not present, the signal Sa applied to the input of sample holding circuit 4 is transmitted directly to the low pass filter 5. Switching circuit 3 is controlled by control pulse S2 such that the terminal 3c is connected to terminal 3b as shown by a real line when the control pulse S2 takes a HIGH level and it is connected to terminal Sa as shown by a dotted line when the control pulse S2 takes a LOW level. The operation of the waveform processing circuit 52 will be described below. Under the recording mode, control pulses S1 and S2 are produced. When the header portion of the input signal Sa carried on the low frequency level VL is applied, control pulse S1 or S2 is not present. Thus, the switching circuit 3 is in the position shown by a dotted line. Thus, the head portion is transmitted through terminals 3a and 3c and through the high pass filter thereby cutting the low frequency level VL. During this period, the head portion is also transmitted through the sample holding circuit 4 and low pass filter 5, it will not be transmitted through the switching circuit 3. Then, in response to the step up of the control pulse S1, the voltage level of signal Sa, which is the low frequency level VL, is sampled and held in the circuit 4. Immediately thereafter, in response to the step up of the control pulse S2, the switching circuit 3 changes its position to that shown by a real line. Thus, the sampled low frequency level VL as produced from low pass filter 5 is transmitted through terminals 3b and 3c and through the high pass filter to cut off the low frequency level VL. During this period, the data portion having a high amplitude is applied to terminal 3a, but it is not transmitted through the switching circuit 3. Then, when the control pulse S2 ends at the time when the data portion ends, the switching circuit 3 returns back to the position indicated by a dotted line. Thus, the input signal Sa is again directly transmitted through the switching circuit 3. Immediately thereafter, in response to the step down of the control pulse S1, the sample hold circuit 4 releases the sampled signal and permits the signal to pass therethrough. The sampling is effected after each head portion so that the low frequency level VL as sampled by circuit 4 can be renewed after every head portion. As apparent from the above, during the recording mode, waveform processing circuit 52 according to the first embodiment produces a signal Sb as shown by a real line in Fig. 7. On the other hand, during the reproducing mode, since control pulses S1 and S2 are not produced, as indicated by dotted lined in Fig. 7, the switching circuit 3 is always held in the position so as to connect terminals 3a and 3c as indicated by the dotted line. Therefore, the head portions and the data portions having a low amplitude are transmitted directly to the high pass filter. Referring to Fig. 8, a second embodiment of the waveform processing circuit 52 is shown, which further comprises a differential amplifier 7. A low pass filter 6 is inserted in the input side of the sample and holding circuit 4, but it can be eliminated. The non-inverting input of differential amplifier 7 is connected to receive the input signal Sa directly, and inverting input thereof is connected to receive the output of low pass filter 5. The output of differential amplifier 7 is connected to terminal 3a. In this embodiment, terminal 3b is connected to ground. In the second embodiment, control pulses S1 and S2 have different pattern. As shown in Fig. 9, the control signal S1 usually takes a HIGH level, but it instantaneously takes a LOW level in the interval between the trailing edge of the head portion and the leading edge of the data portion. This pattern of control signal S1 is present both under the recording mode and under the reproducing mode. The control signal S2 is the same at that generated in the first embodiment. In operation, under the recording mode, control signals S1 and S2 are produced. When the header portion of the input signal Sa is applied, control signal S1 is HIGH and S2 is LOW. Thus, sample and holding circuit 4 produces the low frequency level VL which has been sampled in the previous cycle of operation. Thus, differential amplifier 7 subtracts the low frequency level VL from the header portion, and produces a header portion carried on the zero level to terminal 3a. At this time, since signal S2 is LOW, the switching circuit 3 is in the position shown by a dotted line. Thus, the head portion is transmitted through terminals 3a and 3c and through the high pass filter. Then, when the control signal S1 temporarily takes a LOW level, the low frequency level VL stored in the sample and holding circuit 4 is renewed. Then, in response to the step up of the control pulse S2, the switching circuit 3 changes the position to that shown by a real line. Thus, the zero volt signal from the ground is transmitted through terminals 3b and 3c and through the high pass filter. Then, when the control pulse S2 ends at the time when the data portion ends, the switching circuit 3 returns back to the position indicated by a dotted line. Thus, the input signal Sa carried on the zero level is again transmitted through the switching circuit 3. Therefore, during the recording mode, waveform processing circuit 52 according to the second embodiment produces a signal Sb as shown by a real line in Fig. 9. On the other hand, during the reproducing mode, control signal S1 is present, but control signal S2 is not produced, as indicated by dotted lined in Fig. 9, Thus, the switching circuit 3 is always held in the position so as to connect terminals 3a and 3c as indicated by the dotted line. Therefore, the head portions and the data portions carried on the zero level as produced front differential amplifier 7 are transmitted to tie high pass filter. According to the wave form processing circuit of the present invention, since the high amplitude data portion will not pass through the high pass filter, there will be no great deformation of the filtered signal as caused by the transient phenomena. The waveform processing circuit described herein can be used in the systems other than the photomagnetic disc system. Also, the waveform processing circuit is shown so as to eliminate unwanted transient phenomena caused by the high pass filter, but the circuit may be applied to eliminate unwanted transient phenomena caused by the low pass filter. Referring to Fig. 11, an example of signal detector 56 is shown, which comprises comparator 10 having a non-inverting input 10a and an inverting input 10b. The non-inverting input 10a is connected so as to receive the signal Sc produced from equalizer 54, such as shown in Fig. 10, and the inverting input 10b is connected so as to receive a constant voltage Va1 from a constant voltage generator comprising resistors R4 and R5 connected between a voltage source of Vo and the ground. The signal Sc includes the head portion and the data portion defined by a high frequency sinusoidal wave, as shown in Fig. 12. Comparator 10 compares the sinusoidal wave Sc with a constant voltage Va1 and products a rectangular wave signal Sd of binary form carrying information. When the constant voltage Va1 aligns with the center line of the signal Sc, the rectangular wave signal will be produced with a constant duty ratio such that the duration of one HIGH level period and the duration of one LOW level period will not change. However, if the center line of the signal Sc deflects from the constant voltage Va1, as shown in Fig. 12, the rectangular wave signal will have different durations of one HIGH level period or one LOW level period, resulting in the error information. Although the signal detector 56 of Fig. 11 is applicable in the cases when the signal Sc is stable, it can not be used when the signal Sc fluctuates. Referring to Fig. 13, an improved signal detector 56 is shown which comprises an envelope detector 26 and a center line detector 27. Envelope detector 26 comprises a buffer amplifier 14, diodes D1 and D2, capacitors C1 and C2 and buffer amplifiers 17 and 20. Buffer amplifier 14 receives signal Sc and provides the output thereof to buffer amplifier 17 during the positive half cycle and to buffer amplifier 20 during the negative half cycle. Buffer amplifier 17 detects and holds the positive peak value Ve+ and buffer amplifier 20 detects and holds the negative peak value Ve-. Thus, peak values Ve+ and Ve- define an envelope of the signal Sc. Center line detector 27 comprises resistors R1, R2 and R3 having the same resistance to each other, an operational amplifier 24, and a low pass filter 25. Operational amplifier 24 produces a voltage signal Vb2 which is an average between Ve+ and Ve-. Thus, signal Vb2 can be given as follows. Vb2 = (Ve+ + Ve-) / 2 The voltage signal Vb2 is applied to low pass filter 25 so as to make the voltage signal smooth. Thus, the signal Va2 produced from low pass filter 25 closely coincides with the center line of the input signal Sc. In comparator 10, the input signal Sc is compared with the signal Va2 which closely coincides with the center line of the input signal Sc. Thus, the signal Sd produced from the comparator 10 shown in Fig. 13 will have a constant duty ratio such that the duration of one HIGH level period and the duration of one LOW level period will not change even when the input signal Sc fluctuates, as shown in Fig. 14. Thus, when signal detector 56 such as shown in Fig. 13 is employed, the data stored in the head portion, as well as in the data portion can be detected with less error, so that the control pulses S1 and S2 as produced relatively to the detection of the head portion can be generated with a high reliability and high accuracy. Although the present invention has been fully described with reference to several preferred embodiments , many modifications and variations thereof will now be apparent to those skilled in the art, and the scope of the present invention is therefore to be limited not by the details of the preferred embodiments described above, but only by the terms of the appended claims.

Claims: An electrical circuit for processing reading signals in a signal reading/recording apparatus, comprising a switching means (3) having a first input means (3a), a second input means (3b) and an output means (3c), said switching means (3) being operable to switch between a first state (L) in which said first input means (3a) and said output means (3c) are connected, and a second state (H) in which said second input means (3b) and said output means (3c) are connected; and control signal producing means (56,58,60) for producing a first control pulse (S2) being applied to said switching means (3) for actuating said switching means (3) to establish said second state (H) when said first control pulse (S2) is present, and to establish said first state (L) when said first control pulse (S2) is not present, characterized in that said first input means (3a) receives an input signal (Sa) consisting out of a first type high frequency signal having a lower amplitude, a second type high frequency signal having a higher amplitude, and a base voltage level (VL), said high frequency signals occurring successively, signal producing means (4,5) are provided for feeding to said second input means (3b) a signal (S5) corresponding to the base voltage level while the switching means (3) is in the second state (H), said first control pulse (S2) is applied to said switching means (3) for a time interval being equal to the time interval of the second type high frequency signal, whereby said switching means (3) delivers an output signal (S3) corresponding to said input signal (Sa) without said second type signal. An electrical circuit for processing reading signals in a signal reading/recording apparatus, comprising a switching means (3) having a first input means (3a), a second input means (3b) and an output means (3c), said switching means (3) being operable to move between a first state (L) in which said first input means (3a) and said output means (3c) are connected, and a second state (H) in which said second input means (3b) and said output means (3c) are connected; and control signal producing means (56,58,60) for producing a first control pulse (S2) being applied to said switching means (3) for actuating said switching means (3) to establish said second state (H) when said first control pulse (S2) is present, and to establish said first state (L) when said first control pulse (S2) is not present, characterized in that said first input means (3a) receives a differential signal provided by an output of a differential amplifier (7) having a non-inverting input and an inverting input, one of said inputs receiving an input signal (Sa) consisting out of a first type high frequency signal having a lower amplitude, a second type high frequency signal having a higher amplitude, and a base voltage level (VL), said high frequency signals occurring successively, the other of said inputs being connected to signal producing means (4,5) producing a signal (S5) being the base voltage level (VL), said first pulse (S2) is applied to said switching means (3) for a time interval being equal to the time interval of the second type high frequency signal, and that said second input means (3b) is connected to ground potential, whereby said switching means (3) delivers an output signal (S3) corresponding to said input signal (Sa) without said second type signal and without said base voltage level (VL). An electrical circuit according to claim 1 or 2, wherein said control signal producing means (56,58,60) further produces a second control pulse (S1) having a pulse duration greater than that of said first control pulse (S2) to completely cover said second type signal and said first type signal by said second control pulse (S1), and wherein said signal producing means (4,5) comprises a sample and holding circuit means (4) actuated by said second control pulse (S1) for sampling the base voltage level (VL) and holding the sampled signal while said second type signal is present. An electrical circuit according to one of claims 1-3, wherein said first type signal is a signal having an amplitude (VD-VL) less than a predetermined level and said second type signal is a signal having an amplitude (VP-VL) greater than a predetermined level. An electrical circuit according to one of claims 1-4, wherein said first type signal is a reading signal of a head portion containing address information or of a data portion, said second type signal is a writing signal of a data portion, and head portion and date portion occur alternately with a predetermined cycle. An electrical circuit according to one of claims 1-5, wherein a high pass filter (Ca,Ra) is connected to said output means (3c) of said switching means (3). An electrical circuit according to claims 5 or 6, wherein the starting time of said first control pulse (S2) is prepared with reference to said head portion. An electrical circuit according to one of claims 5-7, wherein said control signal producing means comprises a signal detector (56) for detecting binary data contained in said high frequency signal. An electrical circuit according to claim 8, wherein said detector (56) comprises: a reference voltage producing means (R4,R5;26,27) for producing a reference signal; and a comparator (10) for comparing said high frequency signal with said reference signal to produce one state of a binary signal when said high frequency signal exceeds said reference signal and the other state of the binary signal when said high frequency signal fall below said reference signal. An electrical circuit according to claim 9, wherein said reference voltage producing means comprises voltage dividing resistor means (R4,R5) for producing a predetermined constant voltage (Va1) as said reference signal. An electrical circuit according to claim 9, wherein said reference voltage producing means comprises envelope detector means (26) for detecting an envelope of said high frequency signal, and a center line detecting means (27) for detecting a center line of said envelope and producing a center line level signal (Va2) as said reference signal.

Inventors: DEGUCHI, TOSHIHISA DAIYA HAITSU GAKUENMAE, FUJI, HIROSHI, FUJIWARA, TSUNEO, IWAKI, TAKASHI, KOBAYASHI, SHOZOU
Applicants: SHARP KABUSHIKI KAISHA
Application year: 1986
Main classification: G11B20
IPC codes: G11B20, G11B5