PACKAGED SEMICONDUCTOR DEVICE

Abstract: A packaged semiconductor device, having a bed part (21), semiconductor chip (4) mounted on the bed part (21), leads (2) connected by bonding wires (6) to the internal terminals of the semiconductor chip (4), a heat sink (1) disposed under a back of the bed part (21) and with a gap of a prescribed distance between the heat sink (1) and the back of the bed part (21), and a molded layer which seals the semiconductor chip (4), bed part (21), bonding wires (6), ends of the leads (2), and the heat sink (1), characterized in that the molded layer comprises a first molded layer (3a) which seals to expose the back of the bed part (21), and a second molded layer (3b) formed to cover sides of the heat sink (1) and of the first molded layer (3a), and intermediate parts of the leads (2), and to fill the gap between the back of the bed part (21) and the heat sink (1).

Description: This invention relates to a method of manufacturing a packaged semiconductor device. In particular, it concerns the improvement of a packaged semiconductor device having a heat sink insulated from the semiconductor chip. A known configuration for power semiconductor devices with e.g. a power transistor array is that in which a plurality of semiconductor chips are mounted on one heat sink and sealed with a single layer of molded resin. In this type of semiconductor device, the individual semiconductor chips and the heat sink must be insulated from each other. For this reason, a ceramic substrate is used initially, but owing to the high cost of this substrate and problems with its workability, various substitutes are proposed. A construction for a packaged semiconductor device which did not employ a ceramic substrate is proposed. The semiconductor chip could be insulated from each other, using an ordinary metal heat sink. This construction is explained below, referring to FIGURES 1 through 4. Another example of this type of construction can be found in Patent Abstracts of Japan, vol.6, no. 230. (E-142) [1108], 16th November 1982 corresponding to P-A-57-133653. FIGURE 1 is a plan view of a heat sink 1 consisting of a metal plate of high thermal conductivity, of aluminium. Screw holes 11 are formed in this heat sink 1, for securing to a cooling body. FIGURE 2 is a plan view of a lead frame 2 patterned with thin plate of conductive metal such as copper or steel alloy. As the drawing shows, four independent bed parts 21 and lead patterns 22 are formed on lead frame 2, and these are supported by being connected to a frame 23. To obtain this construction, the semiconductor chips are die-bonded on to bed parts 21 of lead frame 2, and the necessary wire-bonding is then effected. Then the frame is placed in a metal mold die set together with heat sink 1 and transfer molding is carried out. When this is done, lead frame 2 is placed over heat sink 1 with a prescribed gap. This gap is then filled with molded resin. FIGURE 3 is a plan view showing the state after the sealing with resin. Numeral 3 in the drawing is a molded layer. FIGURE 4 is a sectional view along the line V-V in FIGURE 3. As shown in FIGURE 4, a semiconductor chip 4 is die-bonded on to bed part 21 via a solder layer 5. Bonding wires 6 are interconnected between chip 4 and lead frame 2. As the drawing shows, in this construction molded resin layer 3 is filled in the gap between lead frame 2 (in particular bed part 21) and heat sink 1, and by this means insulation is achieved between the two. Thermal dissipation characteristics in the construction described above depends on the thermal conductivity of the molded resin layer interposed between bed part 21 and heat sink 1. The resin used for molded resin layer 3 is therefore epoxy resin with its thermal conductivity Tc increased by an admixture of crystalline silica powder (Tc = 2.5 W/(m·K)) . The admixture of a large quantity of crystalline silica unavoidably increases the viscosity of this resin of high thermal conductivity used in existing packaged semiconductor devices. For this reason, voids are liable to occur, when forming resin layer 3 by transfer molding, in the resin layer which fills the space between bed part 21 and heat sink 1. These voids reduce the breakdown voltage. This tendency is proportional to the viscosity of the melting resin, and in inverse proportion to the distance between the bed part and the heat sink. The problem arose that when an attempt is made to increase the thermal dissipation characteristics by increasing the silica content, the marked generation of voids resulted in reduced breakdown voltage. Other problems caused by increased viscosity of the melting resin are greater flow resistance of the melting resin and poor bonding, with breaking of bonding wires. When an attempt is to be made to increase the silica content and yet at the same time to inhibit the generation of voids, the distance between the bed part and the heat sink must be made greater. In that case the thermal resistance of the resin layer is increased and improvement in thermal dissipation characteristics is no longer obtained. It may be noted here that when epoxy resin, containing crystalline silica, of Tc = 2.5 W/(m K) is used for the molding, with a bed 21 of 8mm x 8mm, the generation of voids made it impossible to reduce the distance between the bed part and the heat sink below 0.5mm. It is an object of the present invention to provide a method of manufacturing a packaged semiconductor device in which the distance between the bed part and the heat sink is shortened, the generation of voids is prevented, the crystalline silica content of the molded resin layer interposed between the bed part and the heat sink can be increased, and thermal dissipation characteristics are improved without decreasing the dielectric breakdown. Another object of this invention is to provide a packaged semiconductor device wherein the adhesion of the first and second molded resin layers is improved, the reliability with which the device can withstand mechanical shock is improved. A further object of this invention is to provide a packaged semiconductor device in which the mechanical strength of the bed part is increased. According the the present invention there is provided a method of manufacturing a packaged semiconductor device, said device comprising a bed part, a semiconductor chip, mounted on said bed part, leads connected by bonding wires to the internal terminals of said semiconductor chip, a heat sink disposed under a back of said bed part and with a gap between said heat sink and said back of said bed part, and a molded layer which seals said semiconductor chip, bed part, bonding wires, end of said leads, and said heat sink, the method including: forming a first molded layer to seal the bed part such that the back of the bed part is exposed; leaving a reduced gap between said first molded layer and said heat sink; forming a second molded layer by first filling said reduced gap and then covering the sides of the heat sink and the sides of the first molded layer. FIGURE 1 is a plan view of a conventonal heat sink. FIGURE 2 is a plan view of a conventonal lead frame. FIGURE 3 is a plan view of a conventonal packaged semiconductor device. FIGURE 4 is a sectional view taken along line V-V of FIGURE 3. FIGURE 5 is a sectional view of a packaged semiconductor device of a first embodiment accordance with the present invention. FIGURE 6(A) is a plan view of a packaged semiconductor device of a second embodiment accordance with the present invention, with a first molded layer applied. FIGURE 6(B) is a partial enlarged sectional view along the line B-B in FIGURE 6(A). FIGURE 6(C) is a plan view of a packaged semiconductor device of a second embodiment accordance with the present invention, with the second molded layer applied. FIGURE 6(D) is a partial enlarged sectional view along the line D-D in FIGURE 6(C). FIGURES 7(A)- (C) are partial oblique views of the first molded layer part of the second embodiment. FIGURE 8 is a sectional view showing a third embodiment of the packaged semiconductor device of the invention. FIGURES 9(a)-(e) are plan views of different examples of recesses formed in the back of the bed part in FIGURE 8 or the upper surface of the heat sink in FIGURE 8. FIGURE 10 is a plan view of the exterior of the third embodiment of FIGURE 8. FIGURE 11 is a circuit diagram showing an example of a power transistor array accordance with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGURE 5 is a sectional view of a packaged semiconductor device constituting a first embodiment of the invention. In this drawing the parts which are the same in FIGURES 1 through 4 are numbered as in those drawings. A semiconductor chip 4 is die-bonded on to a bed part 21 via a solder layer 5 such as a Pb-Sn-Ag solder alloy. Bonding wires 6 consisting of fine metal wire of Au, Al, are interconnected between chip 4 and a lead frame 2. As the drawing shows, in this construction a molded layer 3 is filled in the gap between lead frame 2 (in particular bed part 21) and a heat sink 1, and by this means insulation is achieved between the two. In this embodiment, the molded layer is of two-layer construction, made up of a first molded layer 3a and a second molded layer 3b, for example, both consisting of epoxy resin which contains crystalline silica and is of high thermal conductivity. The epoxy resin used for the first molded layer is of thermal conductivity Tc = 2.5 W/(m·K) ; that used for the second, of thermal conductivity Tc = 2.5-4.2 W/(m·K) . The size of bed part 21 is 10mm x 10mm, and the distance between the bed part and the heat sink is 0.3mm. In the manufacture of the packaged semiconductor device of this embodiment, semiconductor chip 4 is first die-bonded on to lead frame 2 and wire-bonded, in the same way as in the manufacture of the conventional device, after which a resin layer is effected by forming first molded layer 3a by means of transfer molding. Next, heat sink 1 is placed in a transfer mold die set. The lead frame formed the first molded layer is placed in the mold over the heat sink with prescribed gap. Second molded layer 3b is formed by transfer molding. In this second transfer molding, the melting resin first flows between heat sink 1 and the first molded layer, then around the outside of the first molded layer. Consequently, in this embodiment, the air between the bed part and the heat sink escapes to the outside. And this gap is filled with resin of high thermal conductivity without any voids. In the packaged semiconductor device of this embodiment, since the distance between the bed part and the heat sink is shortened to 0.3mm, or half the conventional figure, and the gap is filled with resin of high termal conductivity, the thermal resistance of the resin layer in this gap is improved from the conventional 3.4 K/W to 1.8 K/W or approximately 47%. Also, since the formation of voids in the molded layer in this gap is almost completely prevented, the problem of decreasing the dielectric breakdown does not arise. Specific devices to which the invention can be effectively applied include diode arrays, solid state relays and photocouplers, in addition to transistors and transistor arrays. As described above, since the bed part and heat sink are insulated from each other by interposing the second molded layer and the distance between the bed part and the heat sink is shortened, the outstanding effects are obtained as follows. The generation of voids between them is prevented, the crystalline silica content of the molded layer interposed between them can be increased, and thermal dissipation characteristics can thus be improved without decreasing the dielectric breakdown. As described above, the essential point of the invention is the division of the molded layer into two, with a second molded layer being formed by transfer molding after the formation of a first molded layer. Since in this case the flow of the melting resin is different from the flow in the manufacture of a conventional device, the part where air finally accumulates is not the gap between the bed part and the heat sink, but the area outside the first molded layer. The result of this is that even when highly viscous resin is used for the second molded layer, and the size of the gap between the bed part and the heat sink is reduced, the formation of voids in the resin filling the gap is prevented. It therefore becomes possible to use resin of high thermal conductivity, with a large crystalline silica content, for the second molded layer, and thereby to improve thermal dissipation characteristics without decreasing the dielectric breakdown. Also, since the first molded layer is already in place when the second molded layer is formed, there is no risk of bondings being broken even when carrying out transfer molding with highly viscous melting resin. Insulation between the semiconductor chip and the heat sink is required not only when a plurality of semiconductor chips are sealed within one package, but also in a semiconductor device in which only one semiconductor chip is sealed. When a plurality of semiconductor devices are arranged, each with its heat sink fixed to the same thermal dissipation plate, obviously they all require similar insulation. The invention has its characteristic effect, not only in the semiconductor device explained in FIGURES 1 through 4, but also when applied to a packaged semiconductor device in which a single semiconductor chip is sealed. Next, a second embodiment of the invention is explained, referring to the drawings. In this drawing the parts which are the same in FIGURES 5 are numbered as in those drawings. FIGURE 6(A) is a plan view of a component in which notches 30 are provided in four places in the periphery of first molded layer 3a. FIGURE 6(B) is a partial enlarged sectional view along the line B-B in FIGURE 6(A). In order to ensure perfect bonding with the second molded layer, these notches 30 in FIGURE 6(A) are provided at the part where lead pattern 22 is exposed by a notch. FIGURE 6(C) is a plan view of the finished embodiment, when the second molded layer is applied. FIGURE 6(D) is a partial enlarged sectional view along the line D-D in FIGURE 6(C). In the second molded layer of this second embodiment, the epoxy resin is filled the area 16a around first molded layer 3a and heat sink 1 and a gap 16b between first molded layer 3a and heat sink 1. The additional feature is that the epoxy resin also fills insides 16c of the notches in the first molded layer. Since taper 31 of notches 30 constitutes an undercut in relation to the second molded layer (the angle of the taper is preferably at least 5 o , or better sill, at least 10 o ), adhesion at the interface 32 between the first and second molded layers is improved. FIGURE 7 shows the shapes of different notches and of through-holes. The invention is not restricted to the notches 30, 30a on the periphery of the first molded layer, as shown in FIGURES 6(D) and 7(A). Through-holes 33a, 33b in the first molded layer, as shown in FIGURE 7(B) or (C), may also be used. It is evident, further, that the notches or through-holes are not restricted to those tapered to form an undercut in relation to the second molded layer, as shown in FIGURES 6(D), 7(A) and (B). And they can be stepped so as to form an undercut in relation to the second molded layer, as shown in FIGURE 7(C). The effects obtained with a double-molded packaged semiconductor device according to the invention are that since adhesion between the first and second molded layers is improved, the ability of the device to withstand mechanical shock is increased, and the interface between the two molded layers is not subject to cracking or the entry of air gaps, so that the thermal dissipation characteristics of the device are stable. Next, a detailed explanation follows of a third embodiment of the invention, referring to FIGURE 8 through FIGURE 11. In this drawing the parts which are the same in FIGURES 5 are numbered as in those drawings. In FIGURE 8, numeral 1 is a heat sink consisting of a metal plate of high thermal conductivity, of aluminium or copper plate. Numeral 21 are the bed parts of lead frame 2. Lead frame 2 is formed by the patterning of electrically conductive metal plate such as copper or steel alloys. Bed part is e.g. 10 x 10 mm. Semiconductor chip 4 are die-bonded on to it by a solder layer 5 of mounting agent such as solder alloy, and the prescribed electrical connection is made between the internal terminals of chip 4 and the end parts of lead frame 2 by wire-bonding by means of fine metal wires of Au, Al. Bed part 21, the end parts of lead frame 2, solder layer 5, semiconductor chip 4, and bonding wires 6 are sealed by means of a first molded layer 3a such that the back of bed part 21 is exposed. Heat sink 1 is disposed under the back of bed part 21 at a prescribed distance (e.g. of 0.3mm) from it, and a second molded layer 3b is formed such that it fills the gap between these, and also covers the sides of first molded layer 3a, the sides of heat sink 1, and the intermediate pats of lead frame 2. Thus molded layer 3 made up of two layers, and both layers 3a, 3b consist of epoxy resin of high thermal conductivity, containing crystalline silica. For first molded layer 3a, epoxy resin of Tc (thermal conductivity) = 2.5 W/(m·K) is used, and for second molded layer 3b, epoxy resin of higher thermal conductivity, namely Tc = 2.5-4.2 W/(m·K) . A plurality of recessed parts 7 are formed along the back of bed part 21, and a plurality of recessed parts 8 are formed on the upper surface of heat sink 1. These recessed parts 7 and 8 are pre-formed on the back of bed part 21 and the upper surface of heat sink 1 by mechanical working: for example, the recessed parts are first formed by coining, after which their surfaces are roughened by honing. FIGURES 9(a)-(e) give examples of different plane configurations of these recessed parts formed by coining. FIGURE 9(a) shows round holes; FIGURE 9(b), vertical channels; FIGURE 9(c), square holes arranged in rows; FIGURE 9(d), square holes arranged in a checkerboard pattern; and FIGURE 9(e), triangular holes. In the manufacture of the packaged semiconductor device of this embodiment, semiconductor chip 4 is first die-bonded on to lead frame 2 and wire-bonded, in the same way as in the manufacture of the first embodiment, after which a molded layer is effected by forming first molded layer 3a by means of transfer molding. Next, heat sink 1 is placed in a transfer mold. Then the resin-sealed lead frame 2 is placed over heat sink 1, with a prescribed gap between it and the heat sink, and in this state second molded layer 3b is formed by transfer molding. In this second transfer molding, the melting resin first flows between heat sink 1 and first molded layer 3a, then around the outside of heat sink 1 and first molded layer 3a. Consequently, the place where the air escapes to is the space where second molded layer 3b is formed, and the gap between heat sink 1 and first molded layer 3a is filled with resin of high thermal conductivity without any voids being formed. FIGURE 10 is a front exterior view of the product obtained when the leads are formed after the molded layer is applied in the manner described above. FIGURE 8 is a sectional view along the line A-A in FIGURE 10. In the packaged semiconductor device of the third embodiment described above, the forming of recessed parts 7 on the back of bed part 21 enlarges the area of bed part 21 in contact with second molded layer 3b, and thermal conductivity between these two 21 and 3b is thereby increased. Similarly, the forming of recessed parts 8 on the upper surface of heat sink 1 enlarges the area of heat sink 1 in contact with second molded layer 3b, and thermal conductivity between these two 3b and 1 is thereby increased. Consequently, thermal resistance Rth (J·C) between semiconductor chip 4 and heat sink 1 is greatly reduced, and the thermal dissipation characteristics of the semiconductor device are greatly improved. The forming of a plurality of recessed parts 7 on the back of bed part 21 also increases the mechanical strength of bed part 21. The difference from the first embodiment is the forming of recessed part 7 and 8: the embodiment retains all the features of the firat embodiment. The invention is not restricted to the embodiment described above. Similar effects to those of the embodiment described above are obtained when recessed parts 7 and 8 are formed only by coining, or only by honing (either wet or dry), or when recessed parts 7 are formed on the back of the bed part only, with no recessed parts 8 being formed on the upper surface of the heat sink. The Table below gives the measured data for thermal resistance Rth (J·C) between the semiconductor chip and the heat sink in each of these cases. (1) in the Table represents the first embodiment; (2)-(5) represent different combinations of the places where, and the methods by which, the recessed parts are formed, the other conditions being the same as in construction (1). It can be seen from the Table that the Rth (J·C) of construction (5) is 1.6 K/W, or approximately 0.6 times smaller than that of construction (1), representing an improvement in thermal dissipation characteristics of approximately 40%. Back of bed part Upper surface of heat sink Thermal resistance Rth (J·C) ( K/W) Coining Honing coining Honing (1) No No No No 2.7 (2) No Yes No No 2.3 (3) Yes No Yes No 2.0 (4) Yes No Yes Yes 1.9 (5) Yes Yes Yes Yes 1.6 It is confirmed, furthermore, that thermal resistance Rth (J·C) in the embodiment represented by (5) in the Table can be reduced to 1.4 K/W or less by using epoxy resin of even higher thermal conductivity (e.g. Tc = 3.6 W/(m·K) ) for second molded layer 3b. As an example of a power transistor array. FIGURE 11 shows a circuit with six Darlington-connected power transistors 60. When the invention is applied to this type of power transistor array, its good thermal dissipation characteristics made it possible to achieve higher output, even with the other conditions (package size,.) unchanged. The invention is not restricted to power transistor arrays, but is effective also when applied to diode arrays, power solid state relays, power photocouplers and the like. Again, the invention is not restricted to cases where a plurality of semiconductor chips are sealed within a single package, but is effective also when applied to a semiconductor device (power transistor, etc.) in which a single semiconductor chip is sealed. As described above, the outstanding effects that can be obtained with a packaged semiconductor device according to the invention in which the bed part and the heat sink are insulated from each other by interposing a molded layer between them, are as follows. The distance between the bed part and the heat sink is shortened, the formation of voids between them is prevented, the crystalline silica content can be increased, and thermal dissipation characteristics can be improved without decreasing the dielectric breakdown. Also, since the provision of recessed parts on the back of the bed part enlarges the area of the bed part in contact with the molded layer interposed between them and the heat sink, thermal conductivity between the bed part and heat sink is thereby increased, and thermal dissipation characteristics are further improved. When the double-molded construction described above is put into effect, the formation of voids in the gap between the bed part and the heat sink can be prevented even though this gap is made narrower and epoxy resin of high termal conductivity, with a large silica content, is used for the second molded layer, and thermal dissipation characteristics are improved without decreasing the dielectric breakdown. Furthermore, the presence of recessed parts on the back of the bed port enlarges the area of the bed part in contact with the second molded layer, resulting in a reduction in thermal resistance between the bed part and the heat sink, and in a great improvement in thermal dissipation characteristics.

Claims: A method of manufacturing a packaged semiconductor device, said device comprising a bed part (21), a semiconductor chip (4) mounted on said bed part (21), leads (2) connected by bonding wires (6) to the internal terminals of said semiconductor chip (4), a heat sink (1) disposed under a back of said bed part (21) and with a gap between said heat sink (1) and said back of said bed part (21), and a molded layer which seals said semiconductor chip (4), bed part (21), bonding wires (6) end of said leads (2), and said heat sink (1), the method including: forming a first molded layer (3a) to seal the bed part such that the back of the bed part (21) is exposed; leaving a reduced gap between said first molded layer (3a) and said heat sink (1); forming a second molded layer (3b) by first filling said reduced gap and then covering the sides of the heat sink (1) and the sides of the first molded layer (3a). A method as claimed in claim 1, wherein forming said molded layer includes forming a notch (30) in said first molded layer (3a) such that said second molded layer (3b) fills said notch. A method as claimed in claim 1, wherein forming said molded layer includes forming a through-hole (33) in said first molded layer (3a) such that said second molded layer (3b) fills said through-hole. A method as claimed in anyone of the preceding claims, further comprising forming one or more recesses (7) on the back of said bed part (21). A method as claimed in anyone of the preceding claims, further comprising forming one or more recesses (8) on said heat sink (1). A packaged semiconductor device formed by a method as claimed in any of claims 1 to 5 and in which said gap is less than 0. 5mm. A device as claimed in claim 6, in which said first molded layer (3a) has a thermal conductivity of 2. 5W/mK. A device as claimed in claim 6 or claim 7, in which said second molded layer (3b) has a thermal conductivity in the range of 2. 5-4. 2W/mK.

Inventors: EMOTO, TAKAO PATENT DIVISION, KATO, TOSHIHIRO PATENT DIVISION, KOJIMA, SHIJIRO PATENT DIVISION, MATSUMOTO, HIROSHI PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L23
IPC codes: H01L23, H01L33