LOW LEVEL CLAMP CIRCUIT

Abstract: In order to stabilize an intermediate level of a clock having at three pulse output levels by a low level clamp circuit, a first negative bias driving circuit (1) outputs a pulse with an amplitude corresponding to a first supply voltage (E cc ). The outputted pulse is clamped by a first diode (6) and then rectified/smoothed by a second diode (7) and a capacitor (8) to obtain a clamp level determining a negative bias dc output (E cc ). A second intermediate level driving circuit (2) outputs a pulse with an amplitude corresponding to a voltage lower than the first supply voltage to obtain an intermediate level clock pulse to be stabilized. The low level of the intermediate level clock is further clamped to the obtained negative bias dc output by a third diode (9). The intermediate level is stabilized against supply voltage and/or temperature fluctuations, without use of any Zener diode.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a low level clamp circuit for clamping a low level of a multilevel clock having, for example, at least three levels. More specifically, this invention relates to a low level clamp circuit suitably used for clamping a low level of a multilevel clock in which an intermediate level, in particular, is required to be stabilized, for instance when the multilevel clock is used as an image element driving clock for a charge-coupled device (CCD). Description of the Prior Art As a driving clock for a vertical register for solid image elements such as a so-called CCD imager, a three-level clock as shown in Fig. 1 is used. Where a clamping operation is used to stabilize the levels of this three-level clock, a low-level clamping operation is preferable to maintain the stability of the clamping operation, since the clamping period is short. In general, when an electric charge of the CCD image elements is transferred, the second intermediate level of a multi-level driving clock is very important. Therefore, it has been especially desirable to improve the accuracy of the second level of the driving clock. When a three-level clock as shown in Fig. 1 is clamped at its lowest level and then supplied to the CCD image element, there exist drawbacks in that the amplitude in the driving clock changes between the low level and the second intermediate level due to power supply voltage fluctuations or element characteristic fluctuations based upon temperature change. Thus, the clamped second level fluctuates while transferring the electric charge relative to the stable low level. An example of a prior art low level clamp circuit will be described as to circuit configuration and operation under the section captioned DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS. It has remained a problem in the art, however, to clamp a clocked biasing signal at a first level and accurately clamp a second level biasing signal at a value accurately related to the first level. With these problems in mind, therefore, it is the primary object of the present invention to provide a low level clamp circuit which can stably maintain the intermediate level of a multi level clamping circuit, even if the power supply voltage fluctuates or the temperature characteristics of circuit elements (eg, diodes) fluctuate, in the low level clamp circuit in which the intermediate level, ie, the second level, of an at least three multi-level clock is required to be stabilised. Further, in the circuit of the present invention, since no Zener diode is incorporated, it is possible to avert the harmful influence due to the difference in diode operation characteristics and/or the fluctuations in diode temperature characteristics of a Zener diode. It may be noted that clamping a signal to one of three levels is known, from US-A-3811053. However, the circuits disclosed in that reference operate to limit excursions in one direction of a video, picture-information containing signal to one of three levels, for the purpose of better preserving the picture-information, rather than to generate a three level clock signal. According to a first aspect of the invention, there is provided a low level clamp circuit for clamping a clock signal at at least three predefined levels, comprising:- (a) a first negative bias driving circuit for receiving a negative bias supply voltage and outputting a pulse with an amplitude corresponding to the received negative bias supply voltage in response to a first clock pulse; (b) a first diode with a first forward voltage drop; (c) a second intermediate level driving circuit for receiving a negative bias supply voltage via said first diode and outputting a clock pulse with an amplitude corresponding to the received negative bias supply voltage to be stabilised in response to the first clock pulse; (d) a second diode responsive to said first negative bias driving circuit for clamping a high level of the pulse outputted from said first negative bias driving circuit and outputting a clamped pulse; (e) a rectifying/smoothing circuit including a third diode and a capacitor responsive to the high level clamped pulse outputted via said second diode for outputting a negative bias dc output and (f) a fourth diode connected between said second intermediate level driving circuit and said rectifying/smoothing circuit for clamping a low level of the clock pulse outputted from said second intermediate level driving circuit to the rectified/smoothed negative bias dc output. The invention also provides a low level clamp circuit for clamping a clock signal at at least three predefined levels, comprising:- a source of a negative bias supply voltage; input bias driving circuit means in circuit with a source of clock signals having at least two levels to be clamped, said input bias driving circuit means including a first negative bias driving circuit for receiving said negative supply voltage and outputting a pulse corresponding to said negative bias supply voltage in response to a first clock pulse, and a second intermediate level driving circuit for receiving a negative bias supply voltage through a first diode with a first voltage drop in circuit with said negative bias supply voltage, said second intermediate level driving circuit outputting a clock pulse with an amplitude corresponding to the difference between the negative bias supply voltage and the first forward voltage drop of said diode to be stabilised in response to the first clock pulse; a clamping and smoothing circuit means for clamping a high level of the pulse outputted from said first negative bias driving circuit and outputting a clamped pulse therefrom, said clamping and smoothing circuit including a second diode responsive to said first negative bias driving circuit for clamping a high level of the pulse outputted therefrom, and a third diode responsive to the high level clamped pulse outputted via said second diode for outputting a negative bias dc output therefrom; and a fourth diode means connected between said second intermediate level driving circuit and said clamping and smoothing means for clamping a low level of the clock pulse outputted from said second intermediate level driving circuit to said clamping and smoothing means. These and other features of the invention will become apparent from the detailed description of the invention which follows, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the low level clamp circuit according to the present invention will be more clearly appreciated from the following description of the preferred embodiment of the invention taken in conjunction with the accompanying drawings in which: Fig. 1 is a waveform diagram showing an example of three-level clock pulses; Fig. 2 is a schematic circuit diagram of a prior art low level clamp circuit; Fig. 3 is a schematic circuit diagram of an embodiment of the low level clamp circuit according to the present invention; and Fig. 4 is a waveform diagram for assistance in explaining the operation of the circuit shown in Fig. 3, in which the circled symbols a to e designate each essential junction point in the circuit shown in Fig. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT To facilitate an understanding of the present invention, a brief reference will be made to an example of a prior art low level clamp circuit for a three-level clock with reference to the attached drawings. In Fig. 1, a three-level clock signal is shown, having a first low level E₁, a second intermediate level E₂, and a third high level E₃. The amplitude of the first low level is V₂, while that of the third high level E₃ is V₃. The magnitude of the second intermediate level E₂ is 0V. Such a multi-level clock is useful as a driving clock for a vertical register for solid image elements, such as in a so-called CCD imager. The respective levels of the clock signal shown in Fig. 1 are preferably clamped, such as by a prior art circuit shown in Fig. 2 for stability. In Fig. 2, a three-level clock pulse signal of any given level as shown in Fig. 1 is supplied as an input pulse signal to an input terminal 31. The dc component of the input pulse signal is blocked by a dc blocking capacitor 32 and is clamped at a low level by a clamping diode 33. However, in this clamping operation, the negative bias dc voltage for determining the clamp level is obtained as follows. An output pulse having an amplitude sufficiently higher than the pulse amplitude which lies between the first low level and the second intermediate level of the three-level clock is outputted from a negative bias driving circuit 34 and shifted to the negative side via a capacitor 35 and a diode 36. The output pulse is rectified and smoothed via a diode 37 and a capacitor 38 to obtain a sufficiently low bias dc. The output pulse at an output terminal 40 is stabilized by a Zener diode 39 having a Zener voltage corresponding to the low pulse level. A resistor 41 is in parallel with the clamping diode 33, while a resistor 42 receives the rectified and smoothed output pulse. In the circuit configuration as described above, however, the low level of the three-level clock is thus determined by the Zener voltage of the Zener diode 39. When the amplitude of the three-level clock changes due to power supply voltage fluctuations, the second intermediate level also undesirably fluctuates accordingly. In addition, there exist other problems whereby the clamp level fluctuates due to a change of the temperature characteristics of the low-level clamping diode 33 and to a difference in the operating characteristics of the Zener diode 39, and the fluctuations of the temperature characteristics of the Zener voltage of the Zener diode 39. Reference is now made to an embodiment of a low-level clamp circuit according to the present invention. The low-level clamp circuit shown in Fig. 3 shows an exemplary circuit suitably applied at a low level to a three-level clock signal used as a transferring and driving clock signal in a CCD image element in a vertical register, as explained together with Fig. 1, in which accuracy is required for the second intermediate level. In the following description, the first low level signal of the three level clock pulse shown in Fig. 1 is denoted as E₁; the second intermediate level signal thereof is denoted as E₂; the third high level signal thereof is denoted as E₃; the voltage amplitude between the first low level signal and the second intermediate level signal is denoted as V₂, which is equal to E₂ - E₁; the voltage amplitude between the second intermediate level signal and the third high level signal is denoted as V₃, equal to E₃ - E₂; and the second intermediate level E₂ is to be stabilized accurately relative to a ground potential of zero volts (0V). In Fig. 3, a clock pulse corresponding to a waveform between the first low level E₁ and the second intermediate level E₂ of the above three-level clock is supplied to an input terminal 11 of a first negative bias driving circuit 1 and an input terminal 12 of a second level driving circuit 2. Further, a pulse corresponding to the waveform of the third high level is supplied to an input terminal 13 of a third-level driving circuit 3. A negative bias voltage E cc is supplied to a voltage supply terminal 14 of the negative bias driving circuit 1 in order to obtain an output at terminal a having an amplitude V₂ between the low level E₁ and the second or intermediate level E₂. The actual output of the circuit 1 is higher than v₂ by the magnitude of a forward voltage drop V F1 of the first diode 4 as described later. Since the negative side voltage supply terminal of the negative bias driving circuit 1 is grounded, the potential E cc of the negative bias supply voltage is equal to the above voltage V cc . The supply voltage E cc is also supplied to the second level driving circuit 2 from the negative bias voltage supply terminal 14 through a first diode 4. The above voltage E cc, which is equal in magnitude to V₂ + V F1 , is so determined that the output amplitude of the driving circuit 2 may be equal to the amplitude V₂ between the first low level and the second intermediate level as shown in Fig 1. Further, a third-level supply voltage is supplied to a voltage supply terminal 15 of the third-level driving circuit 3 to obtain an output having a voltage amplitude V₃ between the second intermediate level E₂ and the third high level E₃ One terminal of a capacitor 5 is connected to an output terminal a of the negative bias driving circuit 1. An anode of a second diode 6 is connected to the other terminal of the capacitor 5, and a cathode of the second diode 6 is grounded. The second diode 6 is responsive to the first negative bias driving circuit 1 for clamping a high level of the pulse at terminal a outputted from the circuit 1 and outputting a clamped pulse at the terminal c . A cathode of a third diode 7 for rectification is connected to a junction point c between the capacitor 5 and the diode 6. An anode of the third diode 7 is grounded through a smoothing capacitor 8. At the junction point d between the third diode 7 and the capacitor 8, a negative bias dc level E DC for determining the low-level clamp level E DC is produced, and the junction point d is also connected to an anode of a fourth clamping diode 9. A terminal of a capacitor 16 is connected to an output terminal b of the second level driving circuit 2, and the other terminal of the capacitor 16 is connected to a cathode of the clamping diode 9 and an output terminal 17. A resistor 18 is connected in parallel with the clamping diode 9. It is preferable to select each diode 4, 6, 7 and 9 so as to satisfy the formula V F1 + V F4 = V F2 + V F3 , wherein V F1 , V F2 , V F3 , or V F4 denotes each of the forward voltage drops of the first to fourth diodes 4, 6, 7 and 9. The output pulse from the third level driving circuit 3 is supplied to a voltage supply terminal of the second-level driving circuit 2 through a capacitor 19, for instance, so as to be superposed upon the second intermediate level driving pulse applied to the terminal 12. In the low level clamp circuit configured as described above, when the output characteristics of the negative bias driving circuit 1 and the second level driving circuit 2 are determined to be equal to each other, a difference between the two supply voltages, that is, a voltage difference corresponding to the forward voltage drop V F1 of the first diode 4 appears between the two output pulse amplitudes of the driving circuits 1 and 2. If the assumption is made that the supply voltage appears as if it is as the amplitude of the driving circuit output pulse, the output pulse of the negative bias driving circuit 1 has a voltage V cc between ground potential (0 volts) and the negative bias supply voltage level E cc , as shown in Fig. 4a. Thus, the output pulse of the second level driving circuit 2 has an amplitude of a voltage V₂ which lies between the first low level voltage and the second intermediate level, i.e, 0 volts. For instance, if the amplitude of the voltage V₂ is 9.0V and the forward voltage drop V F1 of the first diode 4 is 0.6V, the supply voltage level E c2 to be supplied to the second level driving circuit 2 becomes 9.0V, i.e., 9.6 - 0.6, by setting the negative bias supply voltage E cc to 9.6V. Therefore, the potential difference between E c2 and the ground is 9.0V. Therefore, it is possible to obtain an output pulse at terminal b with a determined amplitude V₂, equal to 9.0V, from the driving circuit 2, as shown in Fig. 4b. Further, the output pulse with an amplitude V cc from the negative bias driving circuit 1 is fixed so that the pulse high level becomes equal to the forward voltage drop V F2 of the second diode 6 higher than the ground level because of the clamping action of the capacitor 5 and the second diode 6. Therefore, a pulse output shifted to the negative side can be obtained as shown in Fig. 4c. The low level E L of this pulse shown in Fig. 4c is 0 + V F2 - V cc ; therefore, if V F2 = 0.6V, E L = -9.0V. The output pulse shown in Fig. 4c is rectified and smoothed by the third diode 7 and the capacitor 8, so that a negative bias dc for determining the clamp level can be obtained as shown in Fig. 4d. Because of the forward voltage drop V F3 of the third diode 7, the obtained negative bias dc level E DC is raised by V F3 to a value E DC equal to E L + V F3 from the low level of E L for the pulse shown in Fig. 4c. Therefore, if V F3 = 0.6V, E DC = -8.4V, as shown in Fig. 4d. Although the output pulse with on amplitude V₂ as shown in Fig. 4b of the second level driving circuit 2 is a low-level clock signal clamped by the fourth clamping diode 9 with the negative bias dc level E DC as the clamping basis, since the low level E₁ of this clamped pulse (see Fig. 4e) becomes a level E₁ equal to E DC - V F4 , i.e., a forward voltage drop V F4 of the diode 9 lower than the negative bias dc level E DC. If V F4 = 0.6V, E₁ = -9.0V. Therefore, since the pulse amplitude V₂ shown in Figs. 4b and 4e is 9.0V, the second intermediate level E₂ of the pulse shown in Fig. 4e is set to a desired 0 V. The amplitude V₂ of the pulse shown in Fig. 4e is given by subtracting the forward voltage drop V F1 of the first diode 4 from the potential difference V cc between the negative bias supply voltage level E cc and the ground level (V₂ V cc - V F1 ). In contrast with this, since the low level E₁ of the pulse shown in Fig. 4e is given as a value E₁ equal to E DC - V F4, a forward voltage drop V F4 of the diode 9 lower than the negative bias dc level E DC , the second intermediate level can be expressed as E₂ = E₁ + V₂ = E DC - V F4 + V cc - V F1 Further, as explained with respect to Fig. 4d, since the negative bias dc level E DC can be obtained as E₁ + V F3 , and E L can be given as 0 + V F2 -V cc as shown in Fig. 4c, then E DC E L + V F3 = 0 + V F2 - V cc + V F3 Therefore, finally E₂ can be expressed as E₂ E DC - V F4 +V cc - V F1 = 0 + V F2 - V cc + V F3 - V F4 + V cc - V F1 = V F2 + V F3 - (V F1 + V F4 ) Therefore, by previously setting V F2 + V F3 and V F1 and V F4 so as to be equal to each other, it is always possible with the circuit of Fig. 3 to accurately stabilize E₂ to 0 volts, i.e., the ground level, irrespective of the fluctuations of supply voltage. Since it is readily possible to make the temperature characteristics of each of the diodes 4, 6, 7 and 9 equal to those of other diodes in such a way that the temperature characteristic fluctuations of two diodes can cancel those of other two diodes, it is possible to stably maintain the second intermediate level against the fluctuations due to temperature change. On the other hand, because the current flowing through the fourth clamping diode 9 is generally very small and the forward voltage drop V F4 is naturally slightly lowered as compared with other diodes V F1 to V F3 , it is preferable to configure the circuit so that the formula V F1 + V F4 = V F2 + V F3 can be established by using Schottky diodes each having a small forward voltage drop, for instance, as the second and third diodes 6 and 7. A difference between the amplitude V cc of the output pulse of the intermediate level driving circuit 2 and that V₂ of the output pulse of the negative bias driving circuit 1 is equal to a forward voltage drop V F1 of the first diode; the negative bias dc level obtained by high-level clamping and rectifying/ smoothing the output pulse from the negative bias driving circuit 1 corresponds to a value obtained by subtracting two forward voltage drops V F2 and V F3 of the second and third diodes from the amplitude V cc of the output pulse of the negative bias driving circuit 1; and the low level, obtained when the output pulse of the driving circuit for the intermediate level is low-level clamped with the negative bias dc level as a clamp level, corresponds to a level obtained by subtracting a forward voltage drop V F4 of the fourth diode from the negative bias dc level. Therefore, the intermediate level of the low-level clamped output pulse can be determined according to the value V F2 + V F3 - (V F1 + V F4 ) expressed by each of the forward voltage drops V F1 to V F4 of the first and fourth diodes. By low-level clamping of a multi-level clock pulse such as a three-level clock pulse, it is possible to readily maintain the intermediate level accurately and stably against the fluctuations of supply voltage and temperature, by selecting the first to fourth diodes so that the value V F2 + V F3 - (V F1 + V F4 ) can always be kept at a constant level including the temperature characteristics thereof. Furthermore, since no Zener diode such as Zener diode 39 in the prior art is used, there exists no level fluctuation due to the difference of Zener diode and/or the change of temperature characteristics thereof.

Claims: A low level clamp circuit for clamping a clock signal at at least three predefined levels, comprising:- (a) a first negative bias driving circuit (1) for receiving a negative bias supply voltage (E cc ) and outputting a pulse ( a ) with an amplitude corresponding to the received negative bias supply voltage (E cc ) in response to a first clock pulse; (b) a first diode (4) with a first forward voltage drop (V F1 ); (c) a second intermediate level driving circuit (2) for receiving a negative bias supply voltage (V 2 ) via said first diode and outputting a clock pulse ( b ) with an amplitude corresponding to the received negative bias supply voltage (E cc - V F1 ) to be stabilised in response to the first clock pulse; (d) a second diode (6) responsive to said first negative bias driving circuit (1) for clamping a high level of the pulse ( a ) outputted from said first negative bias driving circuit (1) and outputting a clamped pulse ( c ); (e) a rectifying/smoothing circuit including a third diode (7) and a capacitor (8) responsive to the high level clamped pulse ( c ) outputted via said second diode for outputting a negative bias dc output (E dc , d ); and (f) a fourth diode (9) connected between said second intermediate level driving circuit (2) and said rectifying/smoothing circuit (8) for clamping a low level of the clock pulse (b) outputted from said second intermediate level driving circuit to the rectified/smoothed negative bias dc output (E dc , d ). The low level clamp circuit as set forth in claim 1, which further comprises: a third high level driving circuit (3) for receiving a third positive bias supply voltage (V₃) and outputting a pulse to be superimposed upon the negative bias supply voltage (E cc - V F1 ) applied to said second intermediate level driving circuit in response to a second clock pulse. The low level clamp circuit as set forth in claim 1 or 2, wherein the negative bias supply voltage (E cc ) applied to said first negative bias driving circuit is equal to an addition of the negative bias voltage (V₂) applied to said second intermediate level driving circuit (2) and the first forward voltage drop (V F1 ) of said first diode (4). The low level clamp circuit as set forth in claim 1, 2 or 3, wherein said first, second, third and fourth diodes (4, 6, 7, 9) are determined so that V F1 + V F4 = (V F2 + V F3 ) can be satisfied, where V Fn denotes a forward voltage drop of each diode. The low level clamp circuit as set forth in any one of claims 1 to 4, wherein said first, second, third and fourth diodes (4, 6, 7, 9) are Schottky diodes. A low level clamp circuit for clamping a clock signal at at least three predefined levels, comprising:- a source of a negative bias supply voltage (E cc ); input bias driving circuit means in circuit with a source of clock signals having at least two levels to be clamped, said input bias driving circuit means including a first negative bias driving circuit (1) for receiving said negative supply voltage and outputting a pulse corresponding to said negative bias supply voltage in response to a first clock pulse, and a second intermediate level driving circuit (2) for receiving a negative bias supply voltage through a first diode (4) with a first voltage drop in circuit with said negative bias supply voltage, said second intermediate level driving circuit (2) outputting a clock pulse with an amplitude corresponding to the difference between the negative bias supply voltage and the first forward voltage drop of said diode (1) to be stabilised in response to the first clock pulse; a clamping and smoothing circuit means for clamping a high level of the pulse outputted from said first negative bias driving circuit and outputting a clamped pulse therefrom, said clamping and smoothing circuit including a second diode (6) responsive to said first negative bias driving circuit (1) for clamping a high level of the pulse outputted therefrom, and a third diode (7) responsive to the high level clamped pulse outputted via said second diode (6) for outputting a negative bias dc output therefrom; and a fourth diode means (9) connected between said second intermediate level driving circuit (2) and said clamping and smoothing means for clamping a low level of the clock pulse outputted from said second intermediate level driving circuit to said clamping and smoothing means. The circuit as set forth in claim 6, further including a third high level driving circuit (3) for receiving a third positive bias supply voltage and outputting a pulse superimposed upon the negative bias supply voltage applied to said second intermediate level driving circuit (2) in response to a second clock pulse. The circuit as set forth in claim 6 or 7, wherein the negative bias supply voltage applied to said first negative bias driving circuit (1) is equal to the sum of the negative bias voltage applied to said second intermediate level driving circuit and the first forward voltage drop of said first diode (4). The low level clamping circuit as set forth in claim 6, 7 or 8, wherein said first, second, third and fourth diodes (4, 6, 7, 9) are related so that the sum of the forward voltage drops of said first and fourth diodes is equal to the sum of the forward voltage drops of said second and third diodes. The clamp circuit as set forth in claim 6 wherein said first, second, third and fourth diodes (4, 6, 7, 9) are Schottky diodes. The circuit as set forth in claim 6 wherein said clamping and smoothing circuit includes a capacitor (8) in circuit with said third diode (7).

Inventors: HIROSHI, MORI
Applicants: SONY CORPORATION
Application year: 1986
Main classification: H04N5
IPC codes: H03K5, H04N5, H04N3