SECOND ORDER ALL PASS NETWORK

Abstract: A second order all pass network for wide-band signals, and comprising second and third voltage-current converting circuits (20, 10) with their respective positive input terminals supplied with input signals from an input terminal (Ti) of the network and their negative input terminals supplied without­ put signals from an output terminal (To) of the network. Afirst voltage-current converting circuit (30) has its positive input terminal supplied with a positive output of the second volt­ age-current converting circuit (20) and a negative input ter­ minal supplied with the output signals. A first capacitor (C1) is connected between the input and output terminals (Ti, To), and a second capacitor (C2) is connected between ground and the positive output of the second voltage-current con­ verting circuit (20).

Description: BACKGROUND OF THE INVENTION The present invention relates to a second order all pass network for phase compensation of signals and more particularly to a second order active all pass network suited for integration thereof into an integrated circuit (IC). Video signals having a wide frequency range are signal-treated through a plurality of filter circuit stages so that desired frequency characteristics are provided therefor. In such cases, it sometimes becomes necessary to compensate for phase characteristics. Figure 3 is a block diagram showing an example of a prior art second order all pass network which has thus far been used by the applicant for phase compensation. Referring to the drawing, reference numerals 1 and 2 denote voltage-current converting circuits formed of differential amplifiers as the fundamental component parts thereof and 3 denotes a buffer amplifier whose gain is unity. In such a circuit, when mutual conductances g m of the first and second voltage-current converting circuits 1 and 2 are set at 1/r₂ and 1/r₁, respectively, and capacitances of the capacitors C₁ and C₂ are set at c₁ and c₂, respectively, a relationship between the signal V i at the input terminal T i and the signal V₀ at the output terminal T₀ is given by where V y is a potential at the point Y and ω is the angular frequency. Eliminating V y from the above equations (1) and (2), we obtain V₀/V i = {(1 - jωc₂ r₁ + (jω)² c₁ r₁ c₂ r₂)}/ {1 + jωc₂ (r₂ - r₁) + (jω)² c₁ r₁ c₂ r₂} (3). Making r₂ = 2 r₁ in the equation (3), we obtain V₀/V i = {1 - jωc₂ r₁ + (jω)² 2 c₁ c₂ r₁²}/ {1 + jωc₂ r₁ + (jω)² 2 c₁ c₂ r₁²} (4) Accordingly, |V₀/V i | becomes constant for any magnitude of the angular frequency ω. That is, an all pass network in which a flat gain characteristic is maintained and only the phase is changed is obtained. The phase characteristic, as shown in Figure 4, is that of a second order all pass network, in which there is no phase lag at ω = 0 and a lag of 360 o at ω = ∞. If now the values of the mutual conductance (1/r₁) and the capacitances c₁ and c₂ of the capacitors are selected to satisfy ω c = (1/ √ 2 c₁ c ₂) 1/r₁ and Q = √ 2 c₁/c₂ , then the above equation (4) is reduced to V₀/V i = {(1- jω/ω c 1/Q + (jω/w c )²)}/ {1 + jω/ω c 1/Q+(jω/ω c )²} (5). This equation shows that the phase rotation becomes 180 o at ω = ω c . The characteristic as shown in the dotted line in Figure 4 is provided when the Q factor, which indicates the degree of the phase rotation, is high. The characteristic as shown in the one-dot chain line is provided when the Q factor is low. In a demodulator circuit for a video signal or the like, a second order all pass network with a low Q factor of, for example, 0.5 or so is required for compensation of the group delay characteristic of a filter. In the above described second order all pass network, if c₁ is equal to c₂, the Q factor becomes 1.414 because Q = √ 2c₁/c₂ . To make Q = 0.5 or less, the ratio c₂/c₁ must be made 8, at the lowest. However, a capacitor provided in an IC structure in general can be provided to the highest accuracy only when its capacitance is 5 to 7 PF. If it is lower than this, the effect of the error due to stray capacity becomes larger. Also, it is difficult to provide a capacitor of larger capacitance in the IC structure. If it could be made, the chip size would become larger and impracticable. Thus, the prior art second order all pass network has the problem that its Q factor is difficult to set at a desired value when it is integrated in an IC, and more particularly the second order all pass network has a low Q factor which could not be provided in an IC structure with accuracy. SUMMARY OF THE INVENTION The present invention solves these problems encountered in the prior art and has as its principal object to provide a second order all pass network wherein the capacitances of capacitors thereof can be provided at a proper value in an IC structure and whose Q factor can be selected at a desired value without difficulty. To attain the above mentioned object, the present invention provides a second order all pass network that comprises first, second and third voltage-current converting circuits each having first and second opposite polarity inputs and each having an output; the first and second converting circuits have their first input connected to said input terminal; the output of said first voltage-current converting circuit and the ouptut of said third voltage-current converting circuit are connected to said output terminal; a feedback loop connected between said output terminal and the second inputs of said first, second, and third voltage-current converting circuits; a first capacitor connected between said input terminal and said output of said first voltage-current converting circuit; and the output of said second voltage-current converting circuit is connected to said first input of said third voltage-current converting circuit and also to a terminal of a second capacitor, the other terminal of which is connected to a reference potential. The value of mutual conductance (transconductance) of the second voltage-current converting circuit has no connection with the flat gain characteristic of the all pass network but has a connection with the Q factor. Therefore, the value of the Q factor of the all pass network can be set at any desired value by varying the mutual conductance by means of a bias current supplied externally, without varying capacitances of the capacitors. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a second order all pass network of an embodiment of the invention; Figure 2 illustrates an IC circuit diagram to which the block diagram of Figure 1 corresponds; Figure 3 is a block diagram showing an internal prior art second order all pass network; and Figure 4 illustrates phase characteristics in a second order all pass network. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a block diagram showing a second order all pass network of the invention in which reference numerals 10, 20, and 30 denote voltage-current converting networks whose mutual conductances gm are set at 1/r₃, 1/r₂, and 1/r₁, respectively. Reference numeral 40 denotes a buffer amplifier whose gain is unity, and C₁ and C₂ denote capacitors for providing desired phase characteristics and Q factor. The buffer amplifier 40 can be omitted by properly arranging the structure of the voltage-current converting circuits. Considering relationships among the input signal V i , the output signal V₀, and the signal V y at the midpoint Y, we obtain the following relationships Readjusting the equations (6) and (7) to eliminate V y , we obtain V₀/V i = {1-jωc₂ r₂ r₁/r₃+(jω)² c₁ r₁ c₂ r₂}/ {1+jωc₂ r₂ (1-r₁/r₃) + (jω)² c₁ r₁ c₂ r₂} (8). If here we make r₁/r₃ = 1/2, then V₀/V i = {1-(jωc₂ r₂)/2 + (jω)² c₁ r₁ c₂ r₂}/ {1 + (jωc₂ r₂)/2 + (jω)² c₁ r₁ c₂ r₂} (9). Thus, it has become possible to attain a second order all pass network which has the flat gain characteristic similar to the above described second order all pass network. And if now we make ω c = 1 √ c₁ r₁ c₂ r₂ (10) and Q = 2 √ (r₁ c₁)/(r₂ c₂) (11), the equation (9) can be expressed the same as the above described equation (5) and the phase characteristic of the second order all pass network as shown in Figure 4 can be obtained. In the second order all pass network of the invention, while the Q factor indicating the degree of phase rotation is given by the above equation (11), the condition for the flat gain characteristic is attained by making r₃ = 2 r₁. Therefore, the value of r₂ can be freely selected with the condition that the flat gain characteristic is maintained unchanged. Therefore, even under the condition that the ratio of c₁ to c₂ is 1:1, the all pass network whose value of Q factor is freely adjustable can be materialized by selecting the ratio of r₂ to r₁ at a proper value. That is, if we make r₂/r₁ = 16 while maintaining c₁ = c₂, we can obtain Q = 0.5, and so, a second order all pass network having a low Q factor under the condition that c₁ = c₂ is achieved. Accordingly, when integrating the second order all pass network into an IC, the capacitances c₁ and c₂ of the capacitors C₁ and C₂ can be selected at around 5 to 7 PF at which the capacitors can be provided in an IC circuit with the highest accuracy, and based on this condition, an IC with an optional value of the Q factor, and specifically with a lower value of the Q factor, can be manufactured with accuracy. Figure 2 shows a circuit example of the second order all pass network showing an integrated circuit arrangement of the block diagram of Figure 1. Portion 10, 20 surrounded by a one-dot chain line indicates the portion of the first and second voltage-current converting circuits. Portion 30 indicates the portion of the third voltage-current converting circuit, and portion 40 indicates the portion of the buffer amplifier circuit. The capacitors C₁ and C₂ are designed to be approximately 6 PF in capacitance. All the voltage-current converting circuits 10, 20 and 30 are arranged in a modified Gilbert type multiplier structure, and the gm values 1/r₃, 1/r₂, and 1/r₁ are adapted to be set according to the ratios between the currents I₁, I₂ and I₃ to be adjusted by external bias resistors, and the currents I₄ and I₅ to be controlled by internal bias resistors. Accordingly, the second order all pass network having accurate phase characteristics can be provided by correcting errors in absolute resistance values of the resistors within the IC by means of the currents I₁, I₂, and I₃ which can be adjusted externally. By the way, the terminals S₁, S₂, S₃, S₄, and S₅ in Figure 2 are supplied with respective bias potentials as current sources. And, since the voltage-current converting circuits used in Figure 2 have a higher impedance, the signal V₀ is fed back to the negative input terminals of the voltage-current converting circuits, and not by way of the buffer amplifier 40. As described above, the second order all pass network according to the present invention is provided with the voltage-current converting circuits that have no connection with the flat gain characteristic, but do have a connection with the Q factor, and further, are arranged so that the Q factor of the second order all pass network can be readily set at a desired value. Consequently, a second order all pass network with a higher accuracy can be obtained, particularly when it is provided in an IC structure. Although various minor changes and modifications might be proposed by those skilled in the art, it will be understood that I wish to include within the claims of the patent warranted hereon all such changes and modifications as reasonably come within my contribution to the art.

Claims: A second order all pass network for wide-band signals, having : an input terminal (Ti) at which input signals are received; an output terminal (To) at which output signals are delivered; characterized in that it comprises first, second and third voltage-current converting circuits (10, 20, 30) each having first and second opposite polarity inputs and each having an output; the first and second converting circuits have their first input connected to said input terminal; the output of said first voltage-current converting circuit (10) and the ouptut of said third voltage-current converting circuit (30) are connected to said output terminal (To); a feedback loop connected between said output terminal (To) and the second inputs of said first, second, and third voltage-current converting circuits (10, 20, 30); a first capacitor (C1) connected between said input terminal (Ti) and said output of said first voltage-current converting circuit (10); and the output of said second voltage-current converting circuit (20) is connected to said first input of said third voltage-current converting circuit (30) and also to a terminal of a second capacitor (C2), the other terminal of which is connected to a reference potential. A second order all pass network according to claim 1, wherein said first inputs of said first, second and third voltage-current converting circuits (10, 20, 30) are positive inputs and said second inputs are negative inputs. A second order all pass network according to claim 2, wherein said output of said first voltage-current converting circuit (10) is a negative output and said outputs of said second and third voltage-current converting circuits (20, 30) are positive outputs. A second order all pass network according to claim 3, wherein said first and third voltage-current converting circuits (10, 30) have respective mutual conductances of r₁ and r₃, and wherein r₁/r₃ is selected to be substantially 1/2. A second order all pass network according to claim 4, wherein said first capacitor (C1) and second capacitor (C2) are selected to be substantially equal in capacitance. A second order all pass network according to claim 5, wherein said mutual conductances of said first and third voltage-current converting circuits (10, 30) and a mutual conductance of said second voltage-current converting circuit (20) are controlled by adjusting d.c. bias potentials supplied to their biasing circuits. A second order all pass network according to any one of claims 1 to 6, wherein the negative output of the first converting circuit (10) and the positive ouput of the third converting circuit (30) are connected to the output terminal (To); and the negative input terminals of the first, second, and third converting circuits (10, 20, 30) are also connected to the output terminal (To). A network according to any one of claims 1 to 7, wherein the network is an integrated circuit together with the first and second capacitors (C1, C2).

Inventors: YAMASHITA, NORIYUKI C/O SONY CORPORATION
Applicants: SONY CORPORATION
Application year: 1986
Main classification: H03H11
IPC codes: H04B3, H03H11