INTERMEDIATE POTENTIAL GENERATION CIRCUIT

Abstract: Two intermediate potentials (Vn1, Vn2) of small current driving capacity are generated using load elements (R3, R4) and MOS transistors (Q1, Q2), and are respectively supplied to the gates of two MOS transistors (Q3, Q4) which are series-­ connected between power sources (Vcc, Vss) and have large current driving capacity, thus obtaining an intermediate potential (VR) from a node (N3) between the MOS transistors (Q3, Q4). The MOS transistors (Q3, Q4) at the output stage are complementarily operated so as not to be turned on at the same time.

Description: The present invention relates to an intermediate potential generation circuit, which is formed in a semiconductor integrated circuit device and generates an intermediate potential from a power source voltage applied to the device. A conventional intermediate potential generation circuit formed in a semiconductor integrated circuit device has an arrangement shown in Fig. 1. Resistors R1 and R2 are series-connected between power sources Vcc and Vss to divide the power source voltage. Intermediate potential VR is obtained from a node between resistors R1 and R2. The Intermediate potential generating circuit is only used for an auxiliary circuit, and need not provide large current output. For this reason, the intermediate potential generation circuit of resistance division type shown in Fig. 1 meets the requirements of conventional semiconductor integrated circuit devices. In recent large-scale semiconductor integrated circuit devices, however, an operation method thereof is complicated, and an intermediate potential generation circuit having a large current driving capacity is required. In addition, current consumption must be kept as low as possible. However, in the intermediate potential generation circuit shown in Fig. 1, if an output current is to be increased, a large current must flow from power source Vcc to source Vss. The current from source Vcc to source Vss must be, e.g., 10 times the output current. Therefore, current consumption is considerably increased. Thus, in the conventional intermediate potential generation circuit shown in Fig. 1, both the requirements of large current driving capacity and lower current consumption cannot be satisfied at the same time. Prior art document "Patent Abstracts of Japan", vol. 6, no. 262 (P-164, 1140), 21st December 1982 & JP-A-57 157 315 discloses an intermediate potential generation circuit formed in a semiconductor integrated circuit device, which produces an intermediate potential between power source voltages applied to said device. This circuit comprises a first potential supply source, a first load element, one end of which is connected to said first potential supply source, a first MOS transistor of a first conductivity type, one end and a gate of which are connected to the other end of said first load element, a second MOS transistor of a second conductivity type, one end of which is connected to the other end of said first MOS transistor, a second load element, one end of which is connected to the other end and a gate of said second MOS transistor, a second potential supply source in the form of a ground connection connected to the other end of said second load element, a third MOS transistor of the first conductivity type, which has one end connected to said first potential supply source and a gate connected to a first node between said first load element and said first MOS transistor, a fourth MOS transistor of the second conductivity type which is connected between the other end of said third MOS transistor and said second potential supply source, and which has a gate connected to a second node between said second MOS transistor and said second load element, and an output terminal, connected to a third node between said third and fourth MOS transistors, for outputting a potential between said first and second potential supply sources. In this known intermediate potential generation circuit the first to fourth MOS transistors have threshold voltages V T of 0.9V, -0.9V and |V T | of 0.9V and 0.9V, respectively, and fifth and sixth MOS transistors are simultaneously turned on in the transistion of an output level to allow a small number of through currents to flow. These through currents amount up to several hundreds of µA, and cause great problems in circuit applications requiring low power consumption and improved micro-miniaturization. Further, in the known intermediate potential generation circuit, seventh and eighth MOS transistors constitute a constant voltage generating circuit and stabilize the potential at a fourth node. This constant voltage generating circuit is not directly relevant to a basic operation of the intermediate potential generation circuit, i.e. the intermediate potential generation circuit operates also without providing this circuit. However, since the circuit aims at stabilizing the potential at the fourth node, the current flowing through the currrent paths of the seventh and eighth MOS transistors need to be larger than that flowing through the current paths of the first and second MOS transistors and first and second load elements. Accordingly, the current consumption is high. Further, prior art document EP-A-0 145 254 published on June 19, 1985 discloses a voltage converting circuit using a single-channel MOS transistor. In a circuit with a CMOS configuration a through current occuring at the final or output stage can only be reduced but it cannot be completely prevented. It is an object of the present invention to provide an intermediate potential generation circuit with low current consumption and large current driving power, and which avoids through currents of about several hundreds of µA and which is suitable for micro-miniaturization applications. To solve this object the present invention provides an intermediate potential generation circuit as stated in claim 1. With this arrangement, an intermediate potential generation circuit with low current consumption and large current driving capacity can be provided. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a conventional intermediate potential generation circuit; Fig. 2 is a circuit diagram of an intermediate potential generation circuit according to an embodiment of the present invention; Fig. 3 is a diagram for explaining an operation of the circuit shown in Fig. 2; and Figs. 4 to 9 are circuit diagrams of intermediate potential generation circuits according to other embodiments of the present invention. Fig. 2 shows an intermediate potential generation circuit according to an embodiment of the present invention. In this circuit, resistor R3, N-channel MOS transistor Q1, P-channel MOS transistor Q2, and resistor R4 are series-connected between power source Vcc (first potential supply source) and power source Vss (second potential supply source). The gate of MOS transistor Q1 is connected to node N1 between MOS transistor Q1 and resistor R3. The gate of MOS transistor Q2 is connected to node N2 between transistor Q2 and resistor R4. The back gate of MOS transistor Q2 is connected to a node between transistors Q1 and Q2. Node N1 is connected to the gate of N-channel MOS transistor Q3, one end of which is connected to power source Vcc. Node N2 is connected to the gate of p-channel MOS transistor Q4, which is connected between the other end of transistor Q3 and power source Vss. Node N3 between transistors Q3 and Q4 is connected to output terminal 11, such that intermediate potential VR between power sources Vcc and Vss is obtained therefrom. If threshold voltages of MOS transistors Q1, Q2, Q3, and Q4 are given by Vtn1, Vtp1, Vtn2, and Vtp2, respectively, they are set to have relations: Vtn1 + |Vtp1| < Vtn2 + |Vtp2| therebetween. These relations can be obtained such that the back gate of MOS transistor Q2 is connected to the node between MOS transistors Q1 and Q2 to reduce threshold voltage Vtp1 of MOS transistor Q2. This is done to prevent MOS transistors Q3 and Q4 from being turned on at the same time. Channel widths W3 and W4 of MOS transistors Q3 and Q4 are set to be larger than channel widths W1 and W2 of MOS transistors Q1 and Q2. This is done to obtain a sufficiently large current driving capacity and to immediately restore a stable output level after variation therein occurs. The operation of the circuit shown in Fig. 2 will now be described with reference to Fig. 3. Two intermediate potentials Vn1 and Vn2 of small current driving capacity appear at nodes N1 and N2 between respective pairs of resistors R3 and R4 with MOS transistors Q1 and Q2. Assuming that resistances of resistors R3 and R4 are equal, a potential at the node between MOS transistors Q1 and Q2 is equal to an intermediate potential (Vcc/2, if Vss = 0 V) between power sources Vcc and Vss. Therefore, potential Vn1 at node N1 is a potential which is increased from Vcc/2 by threshold voltage Vtn1 of MOS transistor Q1, and potential Vn2 at node N2 is a potential which is decreased from Vcc/2 by the absolute value of threshold voltage Vtp1 of transistor Q2. Two intermediate potentials Vn1 and Vn2 enable MOS transistors Q3 and Q4 of large driving capacity, respectively. If potential Vn3 at node N3 is higher than a sum of potential Vn2 at node N2 and the absolute value of threshold voltage Vtp2 of MOS transistor Q4, MOS transistor Q4 is turned on (at this time, MOS transistor Q3 is turned off), thus decreasing output potential VR. On the other hand, if potential Vn3 at node N3 is lower than the difference between threshold voltage Vtn2 of MOS transistor Q3 and potential Vn1 at node N1, MOS transistor Q3 is turned on (at this time, MOS transistor Q4 is turned off), thus increasing output potential VR. When the above operation is repeated, output potential VR is set to fall within a range between power sources Vcc and Vss. With the above arrangement, since MOS transistors Q3 and Q4 of large driving capacity at the output stage can no longer be turned on at the same time, no large through current flows from source Vcc toward Vss through MOS transistors Q3 and Q4. A through current flowing from power source Vcc to Vss through transistors Q1 and Q2 can be sufficiently reduced by increasing the resistance of resistors R3 and R4. Although output potential VR has an unstable factor corresponding to overlap portion ΔV, where ΔV = Vtn2 + |Vtp2| - (Vtn1 + |Vtp1|), as shown in Fig. 3, threshold voltages Vtn2 and Vtp2 of transistors Q1 and Q2 can be controlled so as to decrease the unstable factor to a negligible level. A level of output potential VR can be freely set between power source Vcc and Vss in accordance with resistance R3 and R4, and threshold voltages Vtn1, Vtp1, Vtn2, and Vtp2 of MOS transistors Q1 to Q4. However, the above relations between the threshold voltages must be satisfied. As described above, since MOS transistors Q3 and Q4 of large driving capacity are alternately turned on/off so as not to be turned on at the same time, an intermediate potential generation circuit with low current consumption and large current driving capacity can be obtained. Fig. 4 shows an intermediate potential generation circuit according to another embodiment of the present invention. The same reference numerals in Fig. 4 denote the same parts as in Fig. 2, and a detailed description thereof will be omitted. In the circuit of Fig. 2, the back gate of MOS transistor Q2 is connected to the node between transistors Q1 and Q2. However, in the circuit shown in Fig. 4, the back gate of transistor Q2 is connected to node N1 between resistor R3 and MOS transistor Q1. With the above arrangement, since the relationships between the threshold voltages can also be accomplished, the same operation and effect as in the above embodiment can be obtained. As shown in Fig. 5, when potentials V1 and V2 having the relation "V1 < V2" are applied to the back gates of MOS transistors Q2 and Q4, respectively, the above relations between the threshold voltages of MOS transistors Q1 to Q4 can be satisfied. In other words, a potential of the back gate of MOS transistor Q2 need only be set to be lower than that of MOS transistor Q4. In addition, the above relations of the threshold values of MOS transistors Q1 to Q4 can also be achieved not only by arrangements in Figs. 2, 4, and 5 in which the potential at the back gate of MOS transistor Q2 is set to be lower than that of MOS transistor Q4, but also by an arrangement in Fig. 6 in which the potential at the back gate of MOS transistor Q2 is set equal to that of MOS transistor Q4, and a channel length of MOS transistor Q2 is reduced to be smaller than that of MOS transistor Q4. Alternatively, an impurity concentration of a channel region of MOS transistor Q2 can be set to be higher than that of MOS transistor Q4. In the above embodiments, a case has been exemplified wherein an n-type well region is formed in a p-type semiconductor substrate, and MOS transistors Q1 to Q4 and resistors R3 and R4 are formed in the semiconductor substrate and the well region to provide the intermediate potential generation circuit. However, when a p-type well region is formed in an n-type semiconductor substrate and MOS transistors Q1 to Q4 and resistors R3 and R4 are formed in the semiconductor substrate and the well region, the relations of the threshold voltages of transistors Q1 to Q4 can be achieved with the following arrangement: the back gate of MOS transistor Q1 is connected to the node between MOS transistors Q1 and Q2 as shown in Fig. 7, so that the potential at the back gate of MOS transistor Q1 is set to be lower than that of MOS transistor Q3. Similarly, the methods described with reference to Figs. 4 to 6 can also be used. Fig. 8 shows an intermediate potential generation circuit according to another embodiment of the present invention. The same reference numerals in Fig. 8 denote the same parts as in Fig. 2, and a detailed description thereof will be omitted. In this embodiment, MOS transistors are used as load elements. More specifically, enhancement type P-channel MOS transistor Q5 is used in place of resistor R3 in Fig. 3, and enhancement type N-channel MOS transistor Q6 is used in place of resistor R4. The gate of MOS transistor Q5 is connected to power source Vss to be kept on, and the gate of MOS transistor Q6 is connected to power source Vcc to be kept on. With this arrangement, the same operation and effect as in the above embodiments can be realized. As shown in Fig. 9, depletion type MOS transistors Q7 and Q8 can also be used as load elements. In this embodiment, the gate of depletion type P-channel MOS transistor Q7 is connected to power source Vcc, and the gate of depletion type N-channel MOS transistor Q8 is connected to power source Vss.

Claims: An intermediate potential generation circuit formed in a semiconductor integrated circuit device, which produces an intermediate potential between power source voltages applied to said device, said intermediate potential generation circuit comprising: a first potential supply source (Vcc); a first load element (R3, Q5, Q7), one end of which is connected to said first potential supply source (Vcc); a first MOS transistor (Q1) of a first conductivity type, one end and a gate or which are connected to the other end of said first load element (R3, Q5, Q7); a second MOS transistor (Q2) of a second conductivity type, one end of which is connected to the other end of said first MOS transistor (Q1); a second load element (R4, Q6, Q8), one end of which is connected to the other end and a gate of said second MOS transistor (Q2); a second potential supply source (Vss) connected to the other end of said second load element (R4, Q6, Q8); a third MOS transistor (Q3) of the first conductivity type, which has one end connected to said first potential supply source (Vcc) and a gate connected to a node (N1) between said first load element (R3, Q5, Q7) and said first MOS transistor (Q1); a fourth MOS transistor (Q4) of the second conductivity type which is connected between the other end of said third MOS transistor (Q3) and said second potential supply source (Vss), and which has a gate connected to a node (N2) between said second MOS transistor (Q2) and said second load element (R4, Q6, Q8); and an output terminal (11), connected to a node (N3) between said third and fourth MOS transistors (Q3, Q4), for outputting a potential (VR) between said first and second potential supply sources (Vcc, Vss), characterized in that the sum of absolute values of threshold voltages (Vtn1, Vtp1) of said first and second MOS transistors (Q1, Q2) is smaller than the sum of absolute values of the threshold voltages (Vtn2, Vtp2) of said third and fourth MOS transistors (Q3, Q4). A circuit according to claim 1, characterized in that a threshold voltage (Vtn1) of said first MOS transistor (Q1) is lower than a threshold voltage (Vtn2) of said third MOS transistor (Q3), and an absolute value of a threshold voltage (Vtp1) of said second MOS transistor (Q2) is smaller than that of a threshold voltage (Vtp2) of said fourth MOS transistor (Q4). A circuit according to claim 1, characterized in that a potential at a back gate of said second MOS transistor (Q2) is lower than that at a back gate of said fourth MOS transistor (Q4). A circuit according to claim 1, characterized in that a back gate of said second MOS transistor (Q2) is connected to a node between said first and second MOS transistors (Q1, Q2). A circuit according to claim 1, characterized in that a back gate of said second MOS transistor (Q2) is connected to a node (N1) between said first load element (R3, Q5, Q7) and said first MOS transistor (Q1). A circuit according to claim 1, characterized in that an impurity concentration of a channel region of said second MOS transistor (Q2) is higher than that of a channel region of said fourth MOS transistor (Q4). A circuit according to claim 1, characterized in that a channel length of said second MOS transistor (Q2) is smaller than that of said fourth MOS transistor (Q4). A circuit according to claim 1, characterized in that channel widths of said third and fourth MOS transistors (Q3, Q4) are greater than those of said first and second MOS transistors (Q1, Q2). A circuit according to claim 1, characterized in that said first and second load elements (R3, Q5, Q7, R4, Q6, Q8) respectively comprise resistors (R3, R4). A circuit according to claim 1, characterized in that said first load element (R3, Q5, Q7) comprises an enhancement type MOS transistor (Q5) of the second conductivity type, a gate of which is connected to said second potential supply source (Vss), and said second load element (R4, Q6, Q8) comprises an enhancement type MOS transistor (Q6) of the first conductivity type, a gate of which is connected to said first potential supply source (Vcc). A circuit according to claim 1, characterized in that said first load element (R3, Q5, Q7) comprises a depletion type MOS transistor (Q7) of the second conductivity type, a gate of which is connected to said first potential supply source (Vcc), and said second load element (R4, Q6, Q8) comprises a depletion type MOS transistor (Q8) of the first conductivity type, a gate of which is connected to said second potential supply source (Vss).

Inventors: OKADA, YOSHIO C/O PATENT DIVISION, SHIMIZU, MITSURU
Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-COMPUTER ENGINEERING CORPORATION
Application year: 1986
Main classification: H03H11
IPC codes: G05F3, H03H11