A WAFER-SCALE SEMICONDUCTOR DEVICE

Abstract: A method of fabricating a wafer-scale integrated circuit device, and such a device, in which a plurality of IC chips (2), each prepared with a protective film (3) over its wired surface, are placed on a substrate (4, 4'), and binder material (6) is grown to fill gaps between the chips (2) and to bind chips together on the substrate. The protective film (3) on the chips is then exposed, either by removing excess binder material (6) or by removing (all or substantially all - depending on whether or not the chips (2) are located in depressions (5) in the substrate) the substrate (4) (depending on whether the wired surfaces of the chips are initially placed downwards on the substrate, or upwards away from the substrate). The protective film (3) is then removed to expose the wired surfaces (3') of the chips. Wiring patterning (7, 9) is then formed to interconnect the chips (2) and to provide (10) for connection of the device to external circuitry.

Description: The present invention relates to a wafer-scale semiconductor device. In order to meet the increasing demand for larger scales of integration of semiconductor devices, for achieving more functions, higher speed and smaller gross size, there have been proposed many methods of integration. One method involves the use of a multi-chip module. IC (Integrated Circuit) chips are encapsulated in a so-called chip carrier, a package, having printed leads on the sides of the carrier. A plurality of chip-carriers having IC chips therein are mounted on a small ceramic mother board, a substrate, to constitute a module by means of conventional hybrid IC technology. A plurality of these modules are mounted on a big, main ceramic board. These multi-chip modules are now being used in practical applications. However, with this method, there are problems of cooling the IC chips and wiring the IC chips on the mother board. The heat dissipated in the IC chips is removed by conduction through the ceramic substrate in a chip-carrier and through the ceramic substrate of the mother board, and finally by forced air flow or liquid flow, and some heat is also removed through the main ceramic board. The amount of heat to be removed is now as much as 10W/cm², in a modern system. This means that the heat resistance of the ceramic boards cannot be ignored. Because of the requirement for high-density wiring, multi-layer ceramic boards are generally employed. The wirings in a multi-layer ceramic board are formed using refractory metal powders, such as molybdenum or tungsten, which, however, results in wirings of higher electrical resistance than other generally used wirings. High resistance of wirings, of course, has a detrimental effect on performance. In addition to these problems, satisfactory accuracy of placing of the chip carriers cannot be achieved, because the structure of a chip carrier is not suitable for precise positioning. This means that the spacing of layer-wirings cannot be chosen small enough to achieve a desired high-density integration. Another method which has been employed in an attempt to satisfy the demand for higher-scale integration involves a monolithic semiconductor fabrication technology. The size of a monolithic IC chip is now as large as 5 or 6 inches in diameter, wafer-size, for example, with as many as more than several hundreds of thousands of gates integrated on the chip. The scale of this integration is several tens to several hundreds times that of previous LSIs (Large-scale ICs). However, for this scale of integration, there are both technical and economic limits. The yield (that is the probability that no defects exist in a chip) of larger integration scale ICs decreases generally in proportion to the nth power of the yield of lower integration scale ICs, where n is the ratio of the scale of the larger integration scale IC to the scale of lower integration scale IC. Therefore, as the scale of integration of a chip becomes larger, the production yield drastically decreases, potentially fatally increasing production cost. In addition to this yield problem, the cost of masks for the relevant photo-lithography becomes extremely great, particularly when production is in relatively small quantities. These facts indicate that wafer-scale integration is almost impossible to achieve in industrial application. Therefore, there is still a desire for a means of achieving a well-designed very large-scale integration which does not suffer, or suffers to a lesser extent, the above-described technical problems, and which is subject to lesser cost problems. An embodiment of the present invention can provide a high-performance multi-chip integrated circuit, equivalent to a wafer-scale integration, but of relatively low cost. EP-A-0 110 285 discloses the mounting of electrical components, which may be unpackaged semiconductor chips, on an insulating substrate such that contact areas of the components lie in a substantially flat plane, with a conductive pattern deposited over the substrate to establish electrical connection between the components. The components are preferably mounted on the insulating substrate by encapsulation, for example by casting in epoxy resin. EP-A-0 149 317 discloses a circuit assembly including a laminar carrier, advantageously of a material thermally matched to semiconductor devices supported thereon, the surface of which is coated with a thick layer of insulating material, in which thick layer windows are etched and in which windows semiconductor devices are located. A further planarizing layer of insulating material is provided in which openings are formed to expose terminal regions of the semiconductor devices. Metallization and, perhaps, a further insulating layer is provided. Bonding pads, for external connection of circuitry, are provided on the metallization. According to the present invention, there is provided a wafer-scale semiconductor integrated circuit device, comprising:- (a) a plurality of integrated circuit chips; (b) a substrate on which the chips are mounted, each with its wired surface upwards; (c) binder material, of essentially the same material as the material of the chips, having essentially the same thermal expansion coefficient as the thermal expansion coefficient of the chips, filling the gaps between the chips, whereby the chips are bound to the substrate and to each other; (d) an electrically insulating layer formed upon the wired surfaces of the chips and upon the binder material in the filled gaps, excluding portions where terminal pads of the chips are located; (e) electrically conductive layer-wiring formed upon the insulating layer for operatively interconnecting the chip terminal pads; and (f) one or more device terminal pads, for connecting the device to external circuitry, provided in connection with the electrically conductive layer-wiring. According to the present invention, there is provided a wafer-scale semiconductor integrated circuit device comprising:- (a) a plurality of integrated circuit chips, whose wired surfaces are arranged in a plane; (b) binder material, of essentially the same material as the material of the chips, having essentially the same thermal expansion coefficient as the thermal expansion coefficient of the chips, filling the gaps between the chips, whereby the chips are bound together; (c) an electrically insulating layer formed upon the wired surfaces of the chips and upon binder material in the filled gaps, excluding portions where terminal pads of the chips are located; (d) electrically conductive layer-wiring formed upon the insulating layer for operatively connecting chip terminal pads; (e) one or more device terminal pads for connecting the device to external circuitry, provided in connection with the electrically conductive layer-wiring. According to the present invention, there is provided a method of fabricating a wafer-scale semiconductor integrated circuit device, comprising the steps of:- (a) preparing integrated circuit chips, each with its wired surface covered with silicon nitride film; (b) mounting a plurality of prepared chips on a surface of a substrate, each chip being mounted with its wired surface upwards; (c) providing electrically insulating binder material, being essentially the same material as the material of the chips, whose thermal expansion coefficient is essentially the same as the thermal expansion coefficient of the chips, to fill gaps between the chips; (d) removing excessive binder material, above and/or upon the chips, by polishing until said silicon nitride film on the chips is exposed; (e) removing the silicon nitride film to expose the wired surfaces of the chips; (f) coating the exposed surfaces of the chips, and binder material remaining in gaps between the chips, with an electrically insulating material, excluding areas where chip terminal pads are located; and (g) patterning layer-wirings upon the insulating material, to interconnect the chip terminal pads and to provide and connect device terminal pads for connection of the device to external circuitry. According to the present invention, there is provided a method of fabricating a wafer-scale semiconductor integrated circuit device, comprising the steps of:- (a) preparing integrated circuit chips, each with its wired surface covered with silicon nitride film; (b) mounting a plurality of prepared chips on a surface of a substrate, each chip being mounted with its film-covered wired surface in contact with a surface of the substrate; (c) providing electrically insulating binder material, being essentially the same material as the material of the chips, whose thermal expansion coefficient is essentially the same as the thermal expansion coefficient of the chips, to fill gaps between the chips; (d) removing the substrate by polishing until the silicon nitride film on the chips is exposed; (e) removing the silicon nitride film to expose the wired surfaces of the chips; (f) coating the exposed surface of the chips, and binder material remaining in gaps between the chips, with an electrically insulating material, excluding areas where chip terminal pads are located; and (g) patterning layer-wirings upon the insulating material, to interconnect the chip terminal pads and to provide and connect device terminal pads for connection of the device to external circuitry. According to an embodiment of the present invention, a plurality of IC chips having their layer-wired surfaces covered with silicon nitride film for chemical and physical protection are prepared. ("layer-wiring" or "layer-wired" is used here to mean an electrically conductive layer patterned on an electrically insulating layer or on an active element of an IC chip). A plurality of such IC chips are placed on a substrate, generally made of the same material as that of the IC chips, with the wired surfaces upwards. The gaps between the IC chips are filled with a binder material. The binder material has essentially the same thermal expansion coefficient as the chips, and should be electrically insulating. The binder material is the same material as that of the IC chips. The binder material is provided by a crystal-growth method, so that the IC chips are bound to each other and to the substrate wafer by the binder material. Excessive binder material, grown higher than and/or upon the IC chips, is removed by polishing to expose the silicon nitride film. The silicon nitride film is chemically removed until the layer-wirings of the IC chips are exposed. An electrically insulating layer is coated upon the exposed wired-surfaces of the IC chips as well as the surface of the binder material between the chips, excluding portions where terminal pads of the IC chips are located. Thereafter, aluminium interconnection layer-wirings are formed over the insulating layer to operatively connect the uncoated terminal pads of the IC chips and to provide input/output terminal pads for connection to external circuitry. Reference is made, by way of example, to the accompanying drawings, in which:- Figs. 1 to 7 schematically illustrate respective successive steps for fabricating a wafer-scale integrated device composed of multiple IC chips according to an embodiment of the present invention; Fig. 7 further schematically illustrates in cross-section the structure of a finished wafer-scale integrated device according to an embodiment of the present invention; Fig. 8 schematically illustrates the finished wafer-scale integrated device of Fig. 7 on a base plate; and Figs. 9 and 10 schematically illustrate steps for fabricating a wafer-scale integrated device, employed as alternatives to the steps of Figs. 3 and 4, according to another embodiment of the present invention. Examples of processes for fabricating wafer-scale integrated devices comprising multiple IC chips according to embodiments of the present invention are hereinafter described with reference to Figs. 1 to 8. For preparing IC chips, as illustrated in Fig. 1, conventional IC wafers 1, 2 ... n (each numeral indicates that a different type of IC is involved) having electrically conductive layer-wirings thereon are tested with probes (referred to as PPT (Primary Probe Test)). At the PPT stage, defective IC units on a wafer are marked to be rejected. For the electrically conductive material for layer-wiring on an IC, aluminium is generally used. Upon the surface with the layer-wirings of the chips of the wafer, there is formed a film of silicon nitride, Si₃N₄, a passivation film, by a method such as plasma CVD (Chemical Vapour Deposition), etc. During this process the temperature of the wafer is kept below 500°C so that the aluminium wiring does not melt or become an alloy. The thickness of the silicon nitride film is approximately 200 nm (2000 Angstroms). The purpose of providing this silicon nitride film is for protection of the aluminium layer-wiring from damage during subsequent mechanical and chemical polishing, which will be described below in some detail. This wafer coated with silicon nitride film is scribed into a plurality of individual IC chips. A set of IC chips, a combination of IC chips of either same or different IC types 21, 22 ... 2n necessary for constituting the required circuit in wafer-scale integration, is thus prepared. In this embodiment of the present invention, a silicon wafer made of the same material as that of the IC chips is employed as a substrate wafer 4. The prepared IC chips are placed on a surface of the substrate wafer 4, as shown in Fig. 2a, each chip with its silicon nitride covered surface upwards. On placing the IC chips, their locations are generally chosen in accordance with the principles that interconnections (which shall be described later) between the IC chips should be as short as possible and the frequency of crossings of interconnection wirings should be as low as possible. For placing the IC chips tentatively or initially, an organic adhesive may be used. However, as a rather preferable method, the substrate wafer 4 can be provided with depressions 5 formed thereon as shown in Fig. 2b. In this case each of the IC chips is placed in a respective corresponding depression. The depressions 5 are made by etching using a photo-lithography method, so that each IC chip can precisely and tightly sit in a respective depression. The depth(s) of the depressions is(are) chosen so that the top surfaces of the IC chips are higher (by one or several microns) than the surface of the substrate wafer 4 (the depth(s) also depend(s) upon the thickness of a (to be) grown silicon layer). If the thickness (height) of the IC chips is not uniform, the depth of each depression is chosen so that the wired surfaces of the chips all lie in a single plane, namely at a uniform height, when the chips are in place. Etching of different depths is carried out by selecting depressions in which additional etching is to be performed, to provide increased depth. Next, the substrate wafer 4 together with the IC chips in the depressions 5 is processed for growing a silicon layer 6 thereover, as shown in Fig. 3. During this silicon-growing process also, the temperature of the IC chips is kept low enough to avoid undesirable effects on the aluminium wirings of the IC chips. Therefore, for growing the silicon layer, a CVD method which requires an IC temperature higher than 600°C for growing polycrystalline silicon cannot be employed. Consequently, as a method not requiring such a high temperature, low temperature CVD or sputtering by PVD (Physical Vapour Deposition) may be chosen. In the PVD method, a silicon target, as a cathode, is bombarded by argon ions, causing sputtering of silicon. Thus, by PVD, polycrystalline silicon or amorphous silicon is grown to form a layer of a thickness which may be several micrometres to several hundred micrometres, according to the height of the IC chips. The gaps between the IC chips are filled by the grown silicon, which binds with both the substrate wafer 4 and the scribed sides of the IC chips, to form a solid piece, because both the substrate and the IC chips are made of the same material as that of the binder, silicon. In other words, the substrate wafer and IC chips are incorporated into a single piece of solid wafer. Hereby, some silicon may be excessively grown, taller than and/or upon the silicon nitride layers 3 of the chips. Next, the excess silicon, higher than or upon the silicon nitride 3, is removed by polishing until the silicon nitride 3 is fully exposed, as shown in Fig. 4. This polishing can be effected using a mechano-chemical method, which uses alumina powder as an abrasive material and a chemical etchant. While the excessive silicon is polished, the silicon nitride film protects the IC chips from mechanical and chemical damage, because the silicon nitride is mechanically harder than the polishing powder, the alumina powder, and chemically non-reactive with the etchant. Next, the silicon nitride 3 is removed by conventional chemical etching (not shown in the Figure), because the function of the silicon nitride layer, protection, has been performed. Even after the removal of the nitride, the surface is essentially flat, because the thickness of the removed film is as little as 200 nm (2000 Angstroms). Thus, in Figs. 5 to 8, the region where the silicon nitride existed is not shown, namely ignored, and 3' indicates aluminium layer-wiring. Next, an electrically insulating material is coated to form a layer 7 all over the polished surface. For this insulating material, conventional insulation film used for separating wiring-layers used in conventional wafer processing, such as silicon dioxide (SiO₂), silicon nitride (Si₃N₄), phospho-silicate glass (PSG) or polyimide can be employed. Next, the insulating layer 7, in particular portions where terminal pads 8 of the IC chips are located, is removed by conventional photo-lithography technology, as shown in Fig. 5. Thus, terminal pads 8 are exposed. Next, an electrically conductive layer 9 is deposited upon the insulation layer 7 as well as the exposed terminal pads 8. For the electrically conductive material, aluminium is generally used. The deposited aluminium layer is patterned by photo-lithography technology to form interconnecting wiring. Thus, interconnections between the terminal pads 8 of the IC chips 2, as well as new input/output terminal pads 10 on the insulating layer 7, as terminals for electrical connection of the wafer-scale device to external circuitry, are fabricated at the same time. A protection layer 11, made of PSG for example, may be formed upon the wired surface, excluding the input/output terminal pads 10, as shown in Fig. 7. In the description given above of this embodiment of the present invention, the aluminium wiring 9 is a single wiring layer. However, two or more wiring layers, namely multi-layer wiring, can be used as in a conventional IC process, for crossing wirings. Multi-layer wirings according to this embodiment of the present invention can be produced much less expensively than in conventional multi-chip modules, because expensive multi-layer ceramics are not necessarily used. Multi-layer wiring according to an embodiment of the present invention can also be electrically less resistive than that of the previously used multi-layer wiring on ceramics, because an electrically good conductive material, such as aluminium, is used for wiring. The locations of the IC chips are determined by the depressions made by lithography technology. Thus the positioning of the IC chips are so accurate that the distances between the aluminium wirings can be designed much finer, namely, the integration density can be elevated much higher than that of the previously proposed multi-chip module method using ICs encapsulated in chip carriers. Now, according to an embodiment of the invention, a wafer made of a single piece which is equivalent to so-called wafer-scale integration is achieved. However, this wafer may be mechanically too fragile to be itself a practical device for use. The wafer, therefore, is reinforced by being mounted on a base plate 12 made of metal or ceramic, as shown in Fig. 8. This mounting is carried out by brazing or other conventional method, depending on design requirements. Generally, a very heat-conductive metal is used for the base plate, but heat conductive ceramics such as beryllia (BeO) or silicon carbide (SiC) etc. can also be used. Any preferred connecting means, such as bonding wires 15, conventional connector terminals 14 housed in a connector 13, and external leads 16, can be provided on the base plate 12, for convenience in later assembling processes using this device. Additionally, the wafer can be hermetically encapsulated by installing a cap (not shown in the Figure) over the base plate for mechanical and chemical protection and for heat conduction. An alternative method according to an embodiment of the present invention for assembling the IC chips as a single big wafer is schematically illustrated in Figs. 9 and 10. Upon a flat surface of a big substrate wafer 4', IC chips 2 having silicon nitride surfaces thereon are placed keeping each silicon nitride surface 9 in contact with the surface of the wafer 4' in a step c' as shown in Fig. 9 in place of the former step c. Silicon is grown in the gaps between the chips 2 and upon the chips 2, by the same method as described above. The thickness of the silicon layer is chosen large enough to hold the chips, for example at least some hundreds of micrometres. Next, the excessively grown silicon layer upon the chips is removed if necessary by mechano-chemical polishing, the same method as described above. Next, the substrate wafer 4' is removed by the mechano-chemical polishing, until the silicon nitride surfaces of the IC chips are exposed, as shown by the step d' in Fig. 10, in place of the former step d. During this process, the silicon nitride film protects the chips from mechanical and chemical damage. Even after the removal of the substrate wafer 4', the IC chips are firmly bound to each other to form a single piece, equivalent to a real wafer-scale integration. Next, successively, the silicon nitride surface films 3 are removed, an electrically insulating layer is formed over the IC chips, a polycrystalline silicon layer is formed thereon, aluminium layer-wirings are fabricated on the polycrystalline silicon layer, and the resulting structure is mounted on a base plate. The relevant fabrication methods corresponding to these respective processes are the same as those described above. An advantage of this method over the first method as illustrated in Figs. 3 and 4 is that it offers better flatness of the layer-wired IC surfaces, particularly when the thickness of the IC chips to be installed on the substrate wafer 4' is not uniform. Though in Figs. 9 and 10, the IC chips are placed on the surface of the substrate wafer 4', depressions having uniform depth can be provided in advance in the surface of the substrate wafer 4', by photo-lithography technology, for positioning the IC chips precisely. Advantages of embodiments of the present invention can be summarized as follows:- 1. Prepared IC chips are all tested and defective chips rejected in advance: therefore the yield of wafer-scale integrated devices using combinations of these pretested IC chips is apparently high; 2. Freedom in designing a system is very large, because IC chips of different types are easily chosen out of ready-made types to constitute a required circuit; 3. Wirings between IC chips are fabricated upon a flat isolation layer by conventional IC technology, offering ease of provision of multi-layer wiring which results not only in greater design flexibility but also permits higher density wiring patterns, having a pitch as small as several tens of micrometres, and lower fabrication costs; 4. Conventional and existing production facilities for wafer-processing can be used for carrying into effect the present invention, thus no additional facilities are required; 5. A multi-layer ceramic substrate is not used. This contributes to reduction of material costs as well as to reduction of heat resistance for cooling the IC chips, because a silicon wafer has lower heat resistance than a ceramic wafer. A device equivalent to a wafer-scale integration is achieved according to an embodiment of the present invention by employing multiple IC chips installed on a silicon wafer. For fabricating the device, conventional IC chips, if necessary of a variety of different types, are prepared, having their aluminium-wired surfaces coated with silicon nitride film. These IC chips are placed on a substrate made of silicon keeping the wired faces upwards. The wafer may be provided with depressions in which the chips are placed for precise positioning. Upon these chips and the wafer, a silicon layer is grown for example by a PVD method. The grown silicon layer fills gaps between the placed IC chips and binds the chips to each other and to the wafer, forming a single piece of wafer. Excessively grown silicon taller than and/or upon the chips is removed by mechano-chemical polishing until the silicon nitride surfaces are exposed. During this polishing process, the silicon nitride film protects the wired surfaces from mechanical and chemical damage. The silicon nitride film is chemically removed until the aluminium wirings are exposed. An insulating layer and aluminium patterning is formed upon the exposed IC chips and filled gaps to form for example multi-layer wirings for interconnection of the chips and for input/output connections. This allows wafer-scale integration of low cost fabrication, higher density wirings and good heat-removal. An embodiment of the present invention provides a method of fabricating a wafer-scale integrated circuit device in which a plurality of IC chips, each prepared with a protective film over its wired surface, are placed on a substrate, binder material is grown to fill gaps between the chips and to bind chips together on the substrate. The protective film on the chips is then exposed, either by removing excess binder material or by removing (all or substantially all-depending on whether or not the chips are located in depressions in the substrate) the substrate (depending on whether the wired surfaces of the chips are initially placed downwards on the substrate, or upwards away from the substrate). The protective film is then removed to expose the wired surfaces of the chips. Wiring patterning is then formed to interconnect the chips and to provide for connection of the device to external circuitry.

Claims: A wafer-scale semiconductor integrated circuit device, comprising:- (a) a plurality of integrated circuit chips (2); (b) a substrate (4) on which the chips are mounted, each with its wired surface upwards; (c) binder material (6), of essentially the same material as the material of the chips, having essentially the same thermal expansion coefficient as the thermal expansion coefficient of the chips, filling the gaps between the chips, whereby the chips are bound to the substrate and to each other; (d) an electrically insulating layer (7) formed upon the wired surfaces of the chips and upon the binder material in the filled gaps, excluding portions where terminal pads of the chips are located; (e) electrically conductive layer-wiring (9) formed upon the insulating layer (7) for operatively interconnecting the chip terminal pads (8); and (f) one or more device terminal pads (10), for connecting the device to external circuitry, provided in connection with the electrically conductive layer-wiring (9). A wafer-scale semiconductor integrated circuit device comprising:- (a) a plurality of integrated circuit chips (2), whose wired surfaces are arranged in a plane; (b) binder material (6), of essentially the same material as the material of the chips, having essentially the same thermal expansion coefficient as the thermal expansion coefficient of the chips, filling the gaps between the chips, whereby the chips are bound together; (c) an electrically insulating layer (7) formed upon the wired surfaces of the chips and upon binder material in the filled gaps, excluding portions where terminal pads of the chips are located; (d) electrically conductive layer-wiring (9) formed upon the insulating layer (7) for operatively connecting chip terminal pads (8); (e) one or more device terminal pads (10) for connecting the device to external circuitry, provided in connection with the electrically conductive layer-wiring (9). A device as claimed in claim 1 or 2, wherein the binder material (6) is of grown polycrystalline silicon. A device as claimed in claim 1 or 2, wherein the binder material (6) is of grown amorphous silicon. A device as claimed in any preceding claim, wherein the electrically conductive layer-wiring (9) has a multi-layer wiring structure, in which electrically conductive wiring layers are separated by electrically insulating layer material. A device as claimed in any preceding claim, mounted on a surface of a base plate (12) with which surface a bottom surface of the device is fully in contact, whereby the device is mechanically held and heat dissipated in the device can be removed by conduction through the base plate. A device as claimed in claim 1 or any one of claims 3 to 6 read as dependent upon claim 1, wherein the substrate has depressions (5) in which the chips are located. A method of fabricating a wafer-scale semiconductor integrated circuit device, comprising the steps of:- (a) preparing integrated circuit chips (2), each with its wired surface covered with silicon nitride film; (b) mounting a plurality of prepared chips on a surface of a substrate (4), each chip being mounted with its wired surface upwards; (c) providing electrically insulating binder material (6), being essentially the same material as the material of the chips, whose thermal expansion coefficient is essentially the same as the thermal expansion coefficient of the chips, to fill gaps between the chips; (d) removing excessive binder material (6), above and/or upon the chips, by polishing until said silicon nitride film on the chips is exposed; (e) removing the silicon nitride film (3) to expose the wired surfaces of the chips; (f) coating the exposed surfaces of the chips, and binder material remaining in gaps between the chips, with an electrically insulating material (7), excluding areas where chip terminal pads (8) are located; and (g) patterning layer-wirings (9) upon the insulating material (7), to interconnect the chip terminal pads (8) and to provide and connect device terminal pads (10) for connection of the device to external circuitry. A method of fabricating a wafer-scale semiconductor integrated circuit device, comprising the steps of:- (a) preparing integrated circuit chips (2), each with its wired surface covered with silicon nitride film (3); (b) mounting a plurality of prepared chips on a surface of a substrate (4'), each chip being mounted with its film-covered wired surface (3) in contact with a surface of the substrate (4'); (c) providing electrically insulating binder material (6), being essentially the same material as the material of the chips, whose thermal expansion coefficient is essentially the same as the thermal expansion coefficient of the chips, to fill gaps between the chips; (d) removing the substrate (4') by polishing until the silicon nitride film (3) on the chips is exposed; (e) removing the silicon nitride film (3) to expose the wired surfaces of the chips; (f) coating the exposed surface of the chips, and binder material remaining in gaps between the chips, with an electrically insulating material (7), excluding areas where chip terminal pads (8) are located; and (g) patterning layer-wirings (9) upon the insulating material (7), to interconnect the chip terminal pads (8) and to provide and connect device terminal pads (10) for connection of the device to external circuitry. A method as claimed in claim 8 or 9, wherein step (b) comprises:- (i) etching the substrate in regions where chips are to be mounted, to a predetermined depth or to predetermined depths, by photo-lithography, whereby the said substrate surface is provided with depressions (5); and (ii) placing chips (2) into corresponding depressions (5). A method as claimed in claim 8, 9 or 10, wherein step (c) is accomplished by growing silicon to fill gaps between the chips. A method as claimed in claim 11, wherein the silicon growing is effected by a sputtering method employing a silicon cathode onto which positive ions are bombarded. A method as claimed in claim 11, wherein the silicon growing is effected by a chemical vapour deposition method. A method as claimed in claim 9 or any one of claims 10 to 13 read as dependent upon claim 9, additionally comprising, after step (c), the step of:- removing excessive binder material provided in step (c), by polishing. A method as claimed in any one of claims 8 to 14, additionally comprising, between steps (f) and (g) one or more cycles of the following steps:- patterning layer-wirings upon coated electrically insulating material as well as chip terminal pads, whereby the chip terminal pads are operatively interconnected and a device terminal pad is fabricated; and coating the resulting surface with an electrically insulating material, excluding portions where chip and device terminal pads are located.

Inventors: FUKUSHIMA, TOSHITAKA FUJITSU LTD. PATENT DEP.
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H01L23
IPC codes: H01L23, H01L25, H01L21, H01L27