ELECTRONIC CONTROL CIRCUIT

Abstract: An electronic control circuit for use with a varying power supply (21) such as the output from a solar collector or wind generator and a load (22) such as a battery being charged by the power supply, provides two forms of control for maximizing power transfer. Firstly, an inverter (20) with varying duty cycle is connected between supply and load and the circuit controls the duty cycle thereof to maximize power transfer and secondly a stepper motor (25) is connected to the supply to physically alter the power provided by the supply by, in the case of a solar collector for example, altering the angle of the collector relative to the sun. The cirucit compares successive measurements of the output power and generates control signals to alter the angle of the collector and modify the duty cycle. The circuit is adapted to calculate the mean maximum power position. Limit detection is included to prevent latch-up and a voltage regulator is included to override the system.

Description: ELECTRONIC CONTROL CIRCUIT 1 The present invention relates to an electronic control 2 circuit and more particularly to a control circuit for 3 maximizing power transfer between a varying power supply and 4 a load. 5 Throughout this specification the term "inverter" is 6 used to describe any manner of voltage conversion, A.C. or 7 D.C. and whether variable by duty cycle, frequency or 8 otherwise and includes switching regulators. 9 The invention has particular utility in relation to 0 photovoltaic cells when used for the purpose of charging 1 batteries but, as will become apparent hereinbelow, it is 2 not limited to this particular use. 3 A problem with photovoltaic cells is that they have 4 only one point on their voltage-current characteristic curve 5 where maximum power occurs. This also applies when they are 6 connected into modules for battery charging. Figure 1 of the 7 attached drawings shows a curve 40, of a typical 12 volt 8 module for battery charging. The maximum power point is 9 labelled Vp.Ip and occurs on the "knee" of the curve at 0 about 16 volts. Obviously the maximum power can only be 1 transferred if the battery also equals this voltage. A 2 nominal 12 volt lead-acid battery will vary from less than 3 11 volts when fully discharged to 15 or 16 volts when fully 4 charged. It is normal practice to limit or "float" the 5 battery at 14.4 volts. (Battery limits are labelled as X and 6 Y). The maximum power capability of the solar module is 7 therefore rarely realized. With a resistive load, unless the 8 load equals Vp/Ip, according to ohms law, then maximum power 9 is not transferred either. Figure 3 shows the same module 0 curve reconstructed as "power versus volts" and better 1 illustrates the effect of "clamping" the output voltage with 2 a battery - the lower the battery voltage, the lower the 3 output power. 4 It is obviously desirable that the output voltage of a 5 solar module at all times equals the voltage at which 6 maximum power transfer occurs. It is also desirable that the 7 load voltage at all times equals the voltage at which 8 maximum power transfer occurs. If there is any form of direct connection whereby the load "clamps" or controls the output of the solar module then these two statements will conflict most of the time. Attempts have been made at maximizing power transfer or tracking the Peak Power Point in a solar system but these have suffered problems including the inability to directly measure the power in the system, latch-up of controls and inefficiencies. Voltage regulation has not been an included feature. The invention also has utility in voltage regulation of a solar system. By using a controlled inverter or switching regulator in a solar system, there are advantages in tighter voltage regulation minimizing heat dissipation and in system redundancy. There are presently two types of solar regulators in use - linear and switched, and these are configured in either shunt or series connections. The linear regulator suffers from two main disadvantages:- 1. Excessive heat dissipation, 2. Costly and bulky components. The regulation, however, can be very good. The switched shunt regulator also suffers from the above two disadvantages and, being an "on/off device" has poor regulation unless very tight control of circuit hysterisis is achieved. The switched series regulator has similar regulation but without the other two disadvantages. When configured as an "incremental" regulator with multiple solar modules it approaches the operation of a linear regulator. In addition to the above, the output of a solar collector (thermal or electrical) is dependent upon its position relative to the sun. Fixed collectors will have an output which is sinusoidal throughout the period of one day due to the rotation of the earth relative to the sun. Maximum output will occur (in the middle of the day) when the sun's rays are perpendicular to the collector. During cloudy periods however, due to the scattering of solar input, more power may be available at a position not related directly to the sun such as from an adjacent white cloud or the effects of buildings, shadows or bodies of water. The output of a fixed solar collector is sinusoidal with respect to time of day as will be evident from Figure 4 of the accompanying drawings. The area enclosed by points G,H,I, & J represents the maximum theoretical gain in power if the collector is at all times perpendicular to the sun on a clear day (No allowance is made, or attempted, for atmospheric effects). The theoretical maximum gain is the difference between the area under the sine, wave and the area enclosed by points G,H,I & J. This can be found from the difference between the R.M.S. and peak values of the sine wave and is a gain of approximately 41.4%. Present types of solar collector tracking devices do not take account of all variations in the direction of solar input such as cloud or shadows and can also be complicated and costly. One known method is to use light-sensitive devices fixed at each side of the collector so that they are cast in shadow by the movement of the collector. The collector is moved depending on the presence or absence of light on these devices. The obvious disadvantage is that no other shadows may be allowed to reach the sensors other than that caused by collector movement. The sensors may also react differently to varying solar input. Another known method is to position the collector during the day to where it is expected that the sun will be. This can be done using a positional feedback device, which is costly, or by a position-controllable motor such as a stepper motor. This method also cannot compensate for variations caused by shadow or cloud and cannot guarantee maximum power at all times. Both of the above methods require control circuits separate to any output regulator and neither method provides positioning of the collector which is directly related to its power output. Accordingly, it is an object of the present invention to provide an improved electronic control circuit which avoids or overcomes at least one of the aforementioned problems or disadvantages of existing circuits. Accordingly the invention provides an electronic circuit for maximizing power transfer between a varying power supply (21) and an electrical load (22), characterized in that, said circuit includes power measurement circuitry (23) for successively measuring the output power from said supply (21), storage circuitry (27) for storing the latest measurement of said output power, a comparator (24) for comparing said latest measurement of said output power with the immediately preceding said measurement and providing an output signal 3 when said output power has decreased, control decision circuitry (31) for providing a first control signal 1 to cause variation by a predetermined amount in either one of opposite directions os control means (28,30) connected to said power supply to cause variation of the power transferred from said power supply to said load (22), said control circuitry (31) is connected to receive said output signal 3 and in response thereto provide a second control 2 signal to change the direction of said variation caused by said first control signal and limit detecting circuitry (43) for actuation when said control means reaches a predetermined limit in either said direction to cause a said change in the direction. In order that the invention may be more readily understood, one embodiment will now be described in more detail with reference to the accompanying drawings wherein: Figure 1 referred to previously is a graph of current versus voltage for a typical 12 volt solar module, Figure 2 shows the curve 40, of Figure 1 re-drawn to illustrate efficiency versus voltage and for comparison of regulators, Figure 3 shows the curve 40, of Figure 1 re-drawn as power versus volts, Figure 4 is a graph for comparison of outputs between "fixed" and "tracking" solar collectors, Figure 5 is a circuit block diagram of a solar power system using an inverter and a stepper motor with "power- maximizing" feedback and a voltage monitor for regulation according to the embodiment of the invention, Fi g ure 6 i s a bas ic f l ow chart o f the " p ower- maximizing" f eedback techn ique used in the embodiment of Figure 5 , and Figures 7A - 7D combined to provide a more detailed circuit block diagram of the solar power system shown in Figure 5. The embodiment described below enables users of photovoltaic cells to extract more power from them than present techniques. Not all circuit elements are labelled in the drawings but those elements not labelled will be readily evident to persons skilled in the art by the standard symbols used. Advances in semi-conductor technology have made it possible to develop sophisticated, but efficient, control circuits at the low power levels normally associated with photovoltaic cells. The described circuit continuously measures and adjusts the output power of a solar module to the maximum which can be transferred to the load or battery. It also on a timed basis, re-adjusts the position of the solar module relative to the sun to that which provides maximum power. Voltage regulation is also provided. Referring to Figures 5 & 6, if a variable duty cycle inverter 20 is placed between a solar module 21 and a load 22 and if the efficiency is ignored for the moment then the following formulae apply: 1. Vout - Vin X Duty Cycle 2. Vin - Vout/Duty Cycle 3. Power In « Power Out The duty cycle of control of this inverter is then adjusted to satisfy the formulae. As will be described in the full circuit description (Figures 7A - 7D) the control is varied to maintain peak output power. If Vout is "clamped" by a battery or determined by the resistance of the load 22, and the duty cycle is varied to the point of maximum power transfer, then it follows that the solar module 21 will be operating at the point of maximum power. Referring now to Figure 6, the blocks within the flow chart are labelled as follows:- 34 Measure the output power 35 Store the measurement 36 Vary the control 37 Has the output power decreased? 38 Change the direction of variation of the control 39 Has the control reached either of its limits? Referring to Figure 6, the output power is first measured and stored, the control is then varied by a known amount. The output power is again measured and compared with the previous measurement. If a decrease in output power is detected the "direction" of control variation is changed before continuing with varying the control and further measurement. This system will be referred to as "power maximizing" feedback and the described circuits as "power- maximizing" regulator and position controller. Three control signals represented 1 , 2 and 3 on the drawings are necessary within the feedback loop as follows:- 1 Vary the control, 2 Change the direction of variation, and 3 Decrease (in output power) detected. This is because the output power will "peak" at one point. A power measurement circuit 23 and comparison circuit 24 combined with a store for previous measurement.27, detect a decrease at either side of the peak point and force the control in the opposite direction. If a decrease is caused by external influences such as sunlight or load variation, the effect will be that the circuit will "track" the output power until it settles and again forces the output power to its maximum. The three control signal ' s within the feedback loop are also used to control a stepper motor 25 which drives the solar module 21, on its axis relative to the sun. A timer 26, in conjunction with main control 31 controls when the motor 25 is being used as the controlled element, within the feedback loop, instead of the inverter 20. Voltage regulation is achieved by the voltage monitor 33. The motor and inverter each have their own controls, 28 & 30 respectively. Each of these has a limit detecting circuit 43, to cause a change in direction of the control variation and prevent latch-up. The inverter control is fed by a clock 29 to set the operating frequency. A system clock 32 is used to synchronize events within the circuit. Voltage regulation is provided by the voltage monitor 33. Control signal 1 "vary the control" can theoretically be free to continuously vary in both directions and simply forced to change direction when necessary but it is more advantageous to control the "amount" of variation in synchronism with the measurement and comparison functions. Tighter control of the output results from using synchronized control signals. The ability of the present technique depends on the overall efficiency of this circuit versus others. Referring to Figures 7A - 7D, the circuit of this invention uses a high frequency switch Tl followed by an averaging L/C filter (L1,C2) to provide variable D.C. output - commonly known as a "buck" (step-down) regulator. Other types of inverter/converter can be used depending on the relationship between input voltage and desired output voltage. Recent developments in components (switches, diodes, inductor cores and capacitors) have made it possible to develop very efficient circuits exceeding 90% efficiency. On the other hand, control circuits using C-mos and other low power techniques also offer high efficiency. The circuit provided uses less than 1 watt at 12 volts and in conjunction with a high efficiency inverter makes the technique viable for systems with a total power throughput of less than 50 watts. Figure 2 shows the curve 40 from Figure 1 re-drawn to illustrate efficiency - power out/total power . available. A switched series regulator indicated by curve 41 on Figure 2 and using the same F.E.T. and blocking diode as the circuit described below would have a loss of about one watt with the illustrated power levels and, combined with the inherent inefficiency of the module, would result in a regulator with an efficiency of about 72% § 11 volts (point B on graph) to 92.5% @ 14.4 volts (point E on graph). The power-maximizing regulator (curve 42 of Figure 2) with a selected efficiency of 90% is only beaten by the switched regulator when the output voltage exceeds 13.8V (point D on graph). The difference between them from then on is only slight as the power-maximizing regulator wil-1 be operating at close to 100% duty cycle. The circuit described below is capable of measuring a change of l/256th of peak output power and will only vary the duty cycle by the amount necessary to detect this change. The loss in output power compared to the switched series regulator (curve 41) is then approximately equal to the circuit requirements plus l/256th of peak output power. Any inefficiencies above 13.8 volts are fairly insignificant as the battery will be almost fully charged. A power-maximizing regulator with an efficiency of > 92.5% would beat the switched series regulator over the entire battery voltage range. Reference should now be made to Figures 7A - 7E which is a more detailed circuit diagram of the solar power system of Figure 5. Figures 7A - 7C, the power-maximizing regulator, contains the inverter 20, the power-maximizing feedback loop elements, power measurement circuit 23, store 27, comparator 24, decision and control circuits 30 and 31, and also contains the voltage monitor circuit 33. Figure 7D - 7E is the power-maximizing position controller section and contains the timer 26, counters and motor drive circuits 28. It uses the feedback loop elements of Figure 7A - 7C. The circuit is intended for a solar power system where the voltage at peak power (Vp) of the solar module is always greater than the voltage of load 22. This enables the use of a "buck" (step-down) regulator. The main switching F.E.T. (Tl) and the blocking diode (D2) of " Figure 7A - 7C are of the types that would be used in a switched series or "incremental" regulator. The losses at 100% duty cycle are therefore similar. The circuit will be described in its two parts i.e. Figures 7A - 7C and 7D - 7E. The following is a description of Figure 7A - 7C. 1. VOLTAGE SUPPLIES Five volts and 12 volts positive are derived from the input 50 by two three-terminal regulators - U2 which is a 7805 and Ul which is a 78L12, respectively. Five volts negative is derived from the +5 supply by U3 which is a 7660 I.C. A 555 astable multivibrator U4, driving a diode pump is used to add 12 volts to the voltage at the drain (d) of Tl, and to power the gate driver I.C, U5. This enables the gate (g) of Tl to be higher than its drain and is necessary when the F.E.T., Tl, is used in the configuration shown. 2. VOLTAGE CONVERSION Because the solar module is a constant current source, and also to prevent switching pulses being seen by the voltage regulators, capacitor, Cl, is used as a filter and voltage source. The main switching F.E.T., Tl, is driven by a variable duty cycle pulse from U5 resulting in a variable width pulse at its source terminal(s). This pulse is then fed through a low-pass filter comprising LI and C2. Diode Dl returns energy stored in LI, to the load, when Tl switches off. D2 is a blocking diode to prevent reverse current from a battery at the output 52 when the circuit is off. The resulting output is a function of input voltage and duty cycle. 3. POWER MEASUREMENT I.C. U6 is a transconductance operational amplifier (3080). Its output current is proportional to the product of the voltage across its input terminals (pins 2 and 3) and the current into pin 5. The voltage across pins 2 and 3 is proportional to output current, as it is sensed by resistor R4. The current into pin 5 is proportional to output voltage - via RV1, RI. The output current of U6 is therefore proportional to output volts times output current and represents output power. To develop a voltage from the output current of U6 , it is fed into R2. Diode . D3 in parallel limits any negative swings, capacitor C3 filters the voltage across R2. This voltage is buffered by U7 to drive a meter, Ml, as a direct visual indication of output power. 4. DIGITAL CONVERSION, STORAGE AND COMPARISON U8, U9A, U10-12 form a "tracking" analog to digital (8 bit) converter. Clock pulses are supplied by U35, a 555 astable multivibrator, via U36 NAND gate. The output from U12 (pin 16) is a voltage proportional to the state of the two up/down counters -U10 and Ull. Comparator U8 compares the output from U12 with the voltage across R2. The output of U8, when latched by the flip-flop U9A, determines the direction of counters U10 and Ull, in order to make the output of U12 equal the voltage across R2. With a constant input voltage, therefore, the output of U12 will swing above and below the input voltage by an amount determined by the sensitivity of the comparator, U8 and/or the voltage steps of U12 - (ideally this will be ± 1 LSB) - U12 has an output voltage range of zero to 2.56 volts in 256 steps (8 bit) so the resolution of measurement is ± .01 volt. Each time the "Q" output of U9A goes high the state of counters U10 and Ull will digitally represent the output power. The circuit is calibrated so that peak voltage across R2 (peak output power) is never greater than 2.56 volts. If the peak output power was 33.6 watts, as per enclosed graphs, then the power measurement resolution would be approximately 130m watts (33.6 divided by 256). Each measurement is subsequently stored in the 8 bit latch, U15, via data bus 53 (see control and decision section) where it is available to be compared with the present measurement by the digital comparators U13 and U14. The A < B output (pin 7) of U14 goes high whenever the data at the outputs of U15 exceeds the state of the counters U10 and Ull. Strobing of this output and data control is explained in the control and decision section. This A < B output is the equivalent of control signal 3 "decrease (in output power) detected" which is shown on Figure 5. 5. DIGITALLY-CONTROLLED DUTY CYCLE The duty cycle is fully variable in 256 steps (8 bit) from 0 to 100%. U16 - U21 are 4 bit binary counters connected in 8 bit pairs. U16 - U19 are high speed types and are driven by a crystal controlled oscillator U22. U16 and U17 divide this clock frequency by 256 and the output of U17 (pin 12) drives the clock input of a flip-flop, U23A. When the output of U17 goes high, U23A output "Q" will go low and U18 and U19 will be "loaded" by the data at their inputs which is determined by the state of counters U20 and U21. The output of U19 (pin 12), when high, sets the output of U23A high. Because the instant that the output of U19 going high is determined by the data loaded when U17 output goes high, the timing difference between their two outputs can be controlled by U20 and U21 and will determine the duty cycle at the output of U23A. This is used, via level-shifting transistors, T2 and T3, and U5 to drive the "gate" of Tl and control the output. The outputs of U20 and U21 are controlled by two inputs - pin 15 of U20 and U21 is the clock input used to step the counters, pin 10 is the up/down control via NOR gate U24. They are reset to zero on power-up by pin 1 controlled by U25 via NOR gates and inverters. They can also be reset to zero by detection of high output voltage or held at zero by the voltage regulator (see regulation section). They can also be forced to count down by the voltage regulator. 6. CONTROL AND DECISION Each time the "Q" output of U9A goes high, a digital measurement of output power has been made. This signal is used to set the "Q" output of U26A low, which turns off gate U36, and prevents further clock pulses reaching the A to D converter. The clock will be low at this stage. When the clock goes high, U26B output "Q" will go high, having been prevented before, by the high on its "clear" input from U26A. U26B controls gates U27 and U28. U27 will now have two "highs" at its inputs, and its output, via an inverter, will cause the input of U29 to be high. If the other input 3 of U29 is high this will indicate that the new measurement (represented by U10 and Ull and present on the data bus) is less than the previous one which is stored in U15. A decrease in output power therefore causes the output of U29 to go low resulting in a high at the output of inverter U29A. This is the equivalent of control signal 2 "change direction of variation" shown on Figure 5. The "A < B" signal from U14 pin 7 is the equivalent of control signal 3 "decrease (in output power) detected" shown also on Figure 5. The "change direction" signal will remain high for the duration of the clock pulse from U35. The positive-going edge at the clock input of U23B causes its outputs to change - its "Q" output controls the direction of counters U20 and U21 via NOR gate U24. When the clock has gone low, the output of U28 will now be low instead of U27. This NAND gate controls NOR gate U30 whose output has three effects when it goes high:- 1. The data on the data bus will be stored into U15 because its strobe inputs (pins 2 and 14) are taken high. ("Store for previous measurement" on Figure 5). 2. Signal 1 "vary the control" is now high and toggles counters U20 and U21 one step-in the direction previously determined by the comparison cycle. This is the equivalent of control signal 1 "vary the control" shown on Figure 5. The duty cycle is therefore altered by one bit. 3. The preset input of U26A is taken high after a slight delay caused by R3 and C4. This makes the "Q" output of U26A go high, U26B goes low because of this high on its clear input, and NAND gate U36 is opened ready for the next clock pulse. U27 and U28 are closed and remain so until the next measurement has been made when the output of U9A goes high again. The output of U23B determines, for power-maximizing feedback, the direction in which the duty cycle is to be varied and controls U20 and U21 via NOR gate U24. It can be "overridden" by the other input to U24 which is the "decrease duty cycle" control 4 and comes from the voltage regulator section. U23B is also controlled by NOR gates, inverters and R-C networks. The "carry" output (pin 7) of U21 controls two of these NOR gates and forces a change of direction if the total count of U20 and U21 is being exceeded i.e. the duty cycle cannot suddenly overflow from 100% to zero, or from zero to 100%. This feature of the circuit is referred to elsewhere as a limit detector and shown as 43 on Figure 5. It prevents "latch-up" when no decrease in power is detected and the control variation limits are reached. When the duty cycle is being forced down by the voltage regulator and when zero is detected the NOR gates detect this and prevent further counting, effectively holding the duty cycle at zero. 7. VOLTAGE REGULATION Three comparators are used to control the output voltage within desired limits - U31 A,B, & C. They all compare the voltage at the output with a reference voltage from ZD1. If the output voltage is higher than that required, the output of the particular comparator will be high. 1. Low volts comparator U31A - This circuit is not essential to the invention and is merely an optional feature of the circuit. The output of U31A is connected to a flip- flop (U32) where it is "latched" during the power measurement phase by pulses via the two NOR gates. If, at any time, its output is low it disables the voltage regulator because there will be a "high" on the "Q" output of U32 which is connected to the "clear" input of U33 causing its "Q" output to be permanently low. The voltage is then allowed to rise as high as the "high volts" setting. This allows for automatic boost-charging of a battery which is "flat" or below the "low-volts" limit set by RV2. 2. Volts regulation comparator, U31B - The output of this comparator is latched during the power measurement phase by a pulse at the clock input of U33 - (this is done to prevent any false transients caused by the stepping of the duty cycle being misinterpreted and is not essential to the invention). When the output voltage is too high, the "Q" output of U33 will go high. This line is labelled " 4 " and causes a decrease in duty cycle. This high at the input of U24 will cause U20 and U21 to count down and overrides any signal from U23B. The output of U23B is forced low by two NOR gates connected to its "set" and "reset" inputs. The duty cycle will then decrease each time that control line 1 is pulsed by the power-measurement control circuitry. When the duty cycle has decreased to a point where the comparator U31B has gone low, the duty cycle will automatically increase because U23B was forced low and both inputs of U24 are now low causing a high on the up/down control of U20 and U21. The duty cycle will continue to increase until either the voltage comparator U31B or the power-maximizing feedback takes control again. If, however, the decrease of duty cycle did not lower the output voltage, the duty cycle would continue to decrease to zero where it would be held - the NOR gate U34 detects the zero "carry" from U21 via NOR gate and inverter and causes the "preset enable" inputs of U20 and U21 to be high until the comparator U31B goes low again. This effectively equals the "off" state of a "switched series" regulator whereas the effect of lowering and increasing the duty cycle simulates a "linear" regulator. The regulator is therefore able to work in parallel with others in a battery charging situation and automatically decide whether to operate with power-maximizing feedback, voltage regulation, or switch on and off as required. 3. High-Volts Comparator - U31C - The effect of this comparator is instantaneous. When its output goes high, the circuit is reset, via NOR gate U35, and the duty cycle is zero. This prevents unwanted high voltages at the output but it can also be used to simulate a "switched series" regulator where the output is switched off as soon as the battery voltage limit is exceeded - the difference being that "switch-on" will be gradual and may go through the "power-maximizing" or "linear" regulation phases before switch-off occurs again. The basic operation of the circuit of Figure 7D - 7E is as follows. A timer is used to switch the necessary control signals between the power-maximizing regulator of Figure 7A - 7C and the power-maximizing position controller of Figure 7D - 7E. The regulator functions normally until the timer signal comes on. The duty cycle of the regulator is held at this point to prevent it from influencing the output power. A stepper motor is then driven, once per power measurement. A decrease in output power causes the direction of the motor to change in the same manner that the direction of change of duty cycle was controlled in the regulator. If this process was left to continue, uninhibited, then the solar collector would move constantly between the two points which cause a decrease in output power i.e. moving away from maximum solar input in either direction. In order to conserve motor power dissipation and to enable sharing of the main control decision logic, the motor is turned off when the collector is positioned at the mean of these two points, as follows. Because the first decrease in power may mean that the collector is moving initially, in the wrong direction, the direction of movement is changed and the motor drive continues. On the second "change direction" signal, counters are initiated to count the number of steps until the third "change direction" signal occurs. The value now held by the counters represents the number of steps between the two positions which cause a decrease in output power. The collector is then stepped back by half this number of steps so that the collector is positioned at the mean position of maximum power output. The timer is reset by the counters reaching zero and the control signals are then used by the regulator, until the timer again initiates a tracking sequence. If, at any time during the tracking sequence, the regulator detects excess output voltage, the timer is reset and the regulator is instantly in control - the collector is left at its last position as no tracking is required when the output limits are being exceeded. If the collector reaches the limits of its travel (90° from horizontal) in either direction, a limit detecting switch causes a change in motor direction. The counters still operate to position the collector at the "mean", so if the travel limit is exceeded in both directions, the result is that the collector is positioned horizontally. This may occur during periods of very low solar input. CIRCUIT DESCRIPTION OF FIGURE 7D and 7E With reference to Figures 7A - 7C and 7D - 7E, there are seven connections between the regulator and the position control circuit, labelled K to Q. As follows. There is only one modification to the regulator - the "step duty cycle" line is interrupted at points and L to allow the timer to stop duty cycle variations. K Pulses are fed to U20 of Figure 7A - 7C to control duty cycle of the regulator. L Comes from control line " 1 " of Figure 7A - 7C and either used to step duty cycle or to step motor circuit depending on timer state. M "Change direction of variation" line " 2 ". N From "decrease duty cycle" line " 4 " - indicates that voltage limit is exceeded and resets the timer. 0 Main "reset" line " 5 " - resets the timer. P&Q Power feed from output of the regulator to motor drive bridge circuits. During normal operation of the regulator, pulses are fed into point L via inverter U41A and NAND gates U42A and U42C and out through connection point to U20 of Figure 7A - 7C of the regulator to control the duty cycle. There is one pulse per power measurement. These pulses are counted by U54 to be used as the timed signal. The motor used in this example is a two-phase stepper motor, having two coils 55 & 56. These coils are driven by identical transistor bridge circuits, Til - T22 which are driven by NOR gates U51A - U51D. These are used to turn off all motor current whilst the circuit is not in use, i.e. the regulator is operating and the timer has not triggered. These NOR gates are driven by two flip-flops, each controlled by three NAND gates at its input. The combination of NAND gates and flip-flops determine the necessary combination of phases to drive the motor. U45B determines the direction of rotation and U44A combined with two NAND gates at its output generates out of ' phase alternate pulses to step the motor. When sufficient pulses have been counted by U54 its outputs Qll and Q12 go high, causing a low at the output of U42D. This low stops further pulses being sent to the regulator by closing gate U4-2C, allows U45A and U45B flip- flops to operate by taking their preset inputs low, and opens NOR gates U51A - U51D to allow motor current. It also opens gate U42B via inverter U41F to allow pulses into U44A. The pulses from connection L therefore step the motor in a direction determined by U45B and occur for each power measurement made by the regulator. If the collector moves to a point where either the power decreases or the travel limit is exceeded, a pulse is received at the clock input of U45B via NAND gate U52A from either control line 2 or the limit switches 54, and the motor direction is changed. The "Q" output of U45B is also connected to the clock input of U45A so every second change of direction causes U45A to change state. The motor continues in the new direction stepping once for each power measurement until another "change direction" pulse arrives at U45B. Both U45A and U45B change state. The "Q" output of U45A is now low and allows binary counters U46 and U47 to operate - their count direction will be upwards as determined by the output of U45B which is connected to their up/down control inputs. The motor now changes direction again but this time each step will be counted by U46 and U47. The motor -continues to step in the new direction for each power measurement until a new "change direction" pulse causes U45B to change to a low. Counters U46 and U47 are now set to count down. U45A will still be low. The inverted outputs of U45A and U45B will both be high and these are detected by U53A, the output of which goes low. This low from U53A now allows U44B flip-flop to respond to the "step" pulses arriving at its clock input from connection L. U44B controls NAND gate U42A so that only every second "step" pulse is allowed to reach U44A and consequently the motor only steps once for every two "step" " pulses coming from the regulator. The motor now steps on every second pulse, counters U46 and U47 step down for every pulse. This process will continue until counters U46 and U47 reach zero when the carry output, "CO" of U47 will go low. While it is high it causes the output of U43D to be low which combines with the low from U53A at the inputs of U43C to produce a high at the clear inputs of U45A and U45B. This locks them in their present state and prevents them from responding to any further "change direction" signals. When the "carry" output of U47 goes low the collector will be at a position which is the "mean" of the second and third "change direction" signals. This low from U47 causes U43D to go high which resets timer U54 via NOR gate U43B and inverter U41D. U54 outputs go low and the regulator now receives its normal duty cycle step signals, until the next time that U54 initiates the motor-driven tracking sequence. At any time while the motor is being driven the regulator can take control again. A high at N will indicate that the voltage limit is being exceeded. This high will go through U43A, U41C, U43B and U41D to reset the timer and allow the regulator to receive its "step duty cycle" pulses. A high at 0 indicates the main reset is active either due to excessive output voltage from the "high-volts shutdown" comparator U31C (Figure 7C) or that the input voltage is not within desired limits and also resets the timer to prevent motor operation. The circuit is only. one way of achieving the desired result. Many parts of it can be simulated using analogue techniques (e.g. sample and hold circuit for power measurement) or by a microprocessor. Also, when charging a battery it is only necessary to maximize the output current to ensure maximum power- the circuit would work the same if only the current was measured and maximized at the output. Turning now to Figure 5 which is a block diagram of a solar power system using an inverter with the "power- maximizing" feedback circuitry described in detail in relation to Figures 7A - 7C and 7D - 7Ε, it can be seen that a controlled inverter 20, is located in a solar system between the solar module 21 and load 22. In this way it is possible to achieve the regulation attainable by linear regulators without the disadvantages mentioned in the introductory portion of this specification. It is possible to operate several regulators in parallel and achieve "incremental" operation but with better regulation. As mentioned, the circuit shown in Figures 7A - 7C and 7D - 7E incorporates the "power-maximizing" feedback technique so - 19 - that maximum power transfer is achieved until the voltage limit is reached and then the device functions as a voltage regulator and can automatically switch between the two modes of operation. There are many known methods of controlling the output of an inverter or switching regulator and it is not considered necessary to describe any of them in this document. The embodiment of Figure 5 merely shows the unique features of the present invention used in relation to a solar system. It will be evident from the above that the "power- maximizing" feedback technique has application in many areas and not just in the generation of electrical power. It can be used to maximize any electrically measurable term whether it be power, volts, current, temperature, speed, etc. provided that the device to which it is applied has a peak in its output and can be controlled by an input, or by an external device which can be controlled by the circuit. The characteristic peak in output power of a solar cell has already been described. A similar peak occurs in the output of generators and alternators, and the positioning of solar collectors and control of one of these has been shown as an example where maximum output can be realized. Input and output conditions of the circuit are altered to suit the application but the heart of the circuit - measure, store, adjust, compare, decision - in conjunction with the flow chart of Figure 6, remain the same. One further example of the uses of the present invention will be described in relation to voltage regulators. By using a (duty-cycle) controlled inverter or switching regulator and varying the duty cycle to provide the desired output voltage, the regulation of a linear regulator can be equalled. When the voltage exceeds a preset level the duty cycle is forced down. When the output voltage falls below another preset level the duty cycle is allowed to increase. The difference between the two preset levels determines the regulation - this is the same as the hysterisis used on a switched regulator. The difference is that the output does not switch off but reduces only to the amount required to fall below the lower preset and then increases to the upper preset. The duty cycle, and therefore output voltage, dithers around the average value of the two preset limits. However, if the battery is being charged by another regulator and the voltage goes above the upper limit, the duty cycle is forced down and, if the voltage does not fall below the lower limit, the duty cycle continues to decrease to zero and will not be allowed to increase again until the voltage has fallen below its lower preset limit. The other regulator(s) then has control of the output voltage and the combined regulators will then function as an incremental regulator with the possibility of either or all of them operating in the "linear" - simulating mode. The form of operation depends on the battery state, load, available charge, etc. In the provided circuit the regulator automatically functions as a "power-maximizing" regulator provided the preset voltage limit has not been exceeded and will automatically switch from one to the other depending on the output voltage. In this way, charge is optimized, regulation can be as good as a linear regulator and system redundancy for multiple charging is provided. Whilst the described embodiment shows control in two places, that is, inverter duty cycle and stepper motor control of the power source, to maximize power transfer, it will be readily evident that one or the other of these forms of control may be utilized in isolation in some uses of the invention. In a further embodiment of the invention a photovoltaic cell is mounted on a solar water heater panel and the electronic circuit described with reference to the drawings is applied to the photovoltaic cell. The stepper motor is connected to the panel to alter the angle thereof relative to the sun. The photovoltaic cell thus operates in the same way as the solar panel previously described and the output therefrom is used as the varying power supply for the purpose of providing input to the circuit of the invention. Of course the load is a dummy load in this case as the energy provided thereto is only used for measurement purposes and not as a useful power source. It will be readily apparent to persons skilled in the art that the present invention has many differing applications and whilst a number have been described in this specification, it is to be understood that they are not intended to limit the extent of usage of the present invention.

Claims: CLAIMS : 1. An electronic circuit for maximizing power transfer between a varying power supply (21) and an electrical load (22), characterized in that, said circuit includes measurement circuitry (23) for successively measuring one or more electrical parameters indicative of the output power from said supply (21) , storage circuitry (27) for storing the latest measurement of said. output power, a comparator (24)for comparing said latest measurement of said output power with the immediately preceding said measurement and providing an output signal 3 when said output power has decreased, control decision circuitry (31) for providing a first control signal 1 to cause variation by a predetermined amount in either one of opposite directions of control means (28,30) connected to said power supply to cause variation of the power transferred from said power supply to said load (22), said control circuitry (31) is connected to receive said output signal 3 and in response thereto provide a second control 2 signal to change the direction of said variation caused by said first control signal and limit detecting circuitry (43) for actuation when said control means reaches a predetermined limit in either said direction to cause a said change in the direction. 2. A control circuit as defined in claim 1, characterized in that, said control means (28,30) comprises first control means (30) including an inverter (20) connected to said power supply and second control means including a stepper motor (25) connected to said power supply, said inverter and stepper motor each causing said variation of the power transferred from said power supply to said load. 3. An electronic circuit as defined in claim 2, characterized in that, a timer (26) is provided for causing selection between said first and second control means whereby either said inverter or said stepper motor causes said variation of the power transferred from said power supply to said load. 4. An electronic circuit as defined in claim 1, characterized in that, said control means controls an 1 inverter connected between said power supply and said load, 2 said (20) inverter causing said variation of the power - 3 transferred from said power supply to said load. 4 5. An electronic circuit as defined in claim 1, * 5 characterized in that, said control means controls a stepper 6 motor (25) connected to said power supply, said stepper 7 motor causing said variation of the power transferred from 8 said power supply to said load. 9 6. An electronic circuit as defined in claim 3, 10 characterized in that, voltage regulation of said power 11 transferred is provided by means of a voltage monitor (33) 12 connected to measure the voltage of said power transferred 13 and in co-operation with said control circuitry, either to 14 decrease or switch-off the output of said inverter, or 15 switch-off the stepper motor, when said voltage exceeds 16 predetermined limits. 17 7. An electronic circuit as defined in claim 6, 18 characterized in that, said varying power supply is a solar 19 collector and said stepper motor is connected to vary the 20 position of said solar collector relative to the sun. 21 8. An electronic circuit as defined in claim 7, 22 characterized in that, said stepper motor is driven, once 23 per power measurement, said timer causes the output of said 24 inverter to be held constant during the time when said 25 stepper motor is being driven, a decrease in the output 26 power measured causes a change in the driven direction of 27 said motor, a counter is provided to count the number of 28 steps which said stepper motor is driven after the second 29 said change in direction until the _ third said change in 30 direction and logic circuitry is provided to cause the motor 31 to step back from said position of the third change in 32 direction towards the position of the second change in 33 direction by half the number of steps counted whereby said 34 solar collector is positioned at the mean position of 35 maximum power output during each actuation by said timer. 36 9. An electronic circuit as defined in claim 8, 37 characterized in that, said limit detecting circuitry 38 comprises a switching device at each limit of travel of said solar collector, said switching device causing a change in direction of rotation of said stepping motor. 10. An electronic circuit as defined in claim 6, characterized in that, said varying power supply is an electric generator and said control means is connected to the field winding of said generator to maintain the field voltage at that which produces maximum power. 11 " . An electronic circuit as defined in claim 10, characterized in that, said control means comprises a counter and a digital to analogue converter. 12. An electronic circuit as defined in claim 11, characterized in that, said control signals are caused to occur in synchronism with said measurements of output power, said inverter is a switching regulator having variable duty cycle and said first control signal is used to alter said duty cycle.

Inventors: JONES ALLAN RUSSELL, JONES, ALLAN, RUSSELL
Applicants: JONES ALLAN RUSSELL, JONES, ALLAN, RUSSELL
Application year: 1986
Main classification: G05F1
IPC codes: G05F1