HETEROJUNCTION TRANSISTOR HAVING BIPOLAR CHARACTERISTICS

Abstract: A heterojunction transistor has a first semiconductor layer (2) of a semi-insulating or a low impurity concentration, a second semiconductor layer (8) formed on the first semiconductor layer and made of such a semiconductor material that, in cooperation with the first semiconductor layer, a first energy recess for electrons and a second energy recess for holes are respectively formed at the bottom of the conduction band and at the top of the valence band to constitute a conductive channel, a fourth semiconductor layer (10) formed on part of second semiconductor layer and forming a PN-junction with the upper surface of the second semiconductor layer to inject carriers into the conductive channel, a control electrode (5) for applying an input signal to the fourth semiconductor layer, and a ground (6) and an output (7) electrode formed on the second semiconductor layer on the opposite sides of the third semiconductor layer. The second semiconductor layer may be formed of a second semiconductor layer and a third semiconductor layer (9), formed on top of the second semiconductor layer, having a smaller bandgap than the first and a smaller sum of bandgap and electron affinity than the second semiconductor layers. In operation the control electrode is blased to forward blas the P-N jonction, causing electrons to accumulate as a two dimensional electron gas in the recess at the bottom of the conduction band and holes to accumulate in the recess at the top of the valence band. The accumulated holes induce more electrons into the conduction band recess. As the high mobility electrons are swept away much faster than the holes, far more electrons are induced than holes are accumulated. Thus a device having large current amplification properties and a high mutual conductance is provided.

Description: Field of the Invention: The present invention relates to a heterojunction transistor having a high mutual conductance and operable at high speed. Description of the Prior Art: A heterojunction transistor, having an improved mutual conductance is known from EP-A-0 133 342. This device is a superlattice type semiconductor having on a semi-insulator substrate of GaAs a high purity GaAs-layer. A multilayered structure is formed on the high purity GaAs-layer, to form the superlattice type semiconductor material with high purity AlAs-layers and N-type GaAs-layers containing Si as impurities. A Schottky-gate electrode is formed on the multilayered structure with aluminium. Source and drain electrodes are formed on the multilayered structure on both sides of the Schottky-gate electrode with Au-Ge/Au-alloy. The mutual conductance of the obtained field effect transistor is 450 mS/mm at 77 K. However, in such heterojunction field effect transistor according the prior art, while at the bottom of the conduction band in the energy band structure under the gate electrode, a recess accumulating electrons exists, a recess accumulating holes does not exist, at the top of the valence band. Therefore further improvement is desired in the load driving capability and the high speed operation characteristic. Summary of the Invention: One object of the present invention is to provide a heterojunction transistor having a further improved load driving capability and high speed operation characteristic. According to the present invention there is provided a heterojunction transistor including a first semiconductor layer having a low impurity concentration, a second semiconductor layer provided on said first semiconductor layer and made of a semiconductor material of one conductivity type, whose electron affinity is smaller than that of said first semiconductor layer, a third semiconductor layer of the other conductivity type forming a PN-junction with said second semiconductor layer, a gate electrode formed on and in ohmic contact with that third semiconductor layer and a source electrode and a drain electrode formed on opposite sides of said third semiconductor layer so as to be electrically connected with the boundary surface between said first semiconductor layer and said second semiconductor layer, said second semiconductor layer having a smaller some of the electrone affinity and the forbidden band gap than said first semiconductor layer so as to form a recess at the bottom of the conduction band adapted to collect electrons at the boundary surface between said first and second semiconductor layers on the side of said first semiconductor layer and to form a recess at the top of the valence band adapted to collect holes at the boundary surface between said first and second semiconductor layers on the side of said second semiconductor layer. In the heterojunction transistor according to the present invention, when a bias voltage is applied to the control electrode so as to forward bias the PN-junction formed between the upper layer portion of the second semiconductor layer and the third semiconductor layer, electrons are accumulated in the recess at the bottom of the conduction band in the energy band structure, and thereby the conductivity of the two-dimensional electron gas is increased. Besides, positive holes are also accumulated in the recess at the top of the valence band in the energy band structure. By these positive holes also, the conductivity between the ground electrode and the output electrode is further increased. In addition, these positive holes act to collect electrons and serve to further increase the amount of electrons in the two dimensional electron gas formed in the recess at the bottom of the conduction band in the energy band structure, and as a result, the conductivity between the ground electrode and the output electrode is exponentially increased as a function of the gate bias voltage, hence a high mutual conductance is provided, and the load driving capability as well as the high speed operation characteristic can be remarkably improved. Brief Description of the Drawings: The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a cross-sectional view showing a preferred embodiment of the present invention; and Fig. 2 is a diagram of the energy band structure under the gate electrode in the preferred embodiment shown in Fig. 1. Now, a preferred embodiment of the present invention in which a heterojunction transistor is realized by using three semiconductor layers, will be explained with reference to Figs. 1 and 2. On a semi-insulating semiconductor substrate 1 is provided a first semiconductor layer 2 having its impurity minimized. On this first semiconductor layer 2 is provided a second semiconductor layer 18 having a smaller electron affinity than the first semiconductor layer 2 and a smaller sum of the electron affinity and the forbidden gap then the first semiconductor layer 2 and containing an n-type impurity, and on one portion of this second semiconductor layer 18 is provided a third semiconductor layer 19 containing a p-type impurity at a high concentration. While the material of the third semiconductor layer 19 could be any material so long as it can inject positive holes into the second semiconductor layer 18, for the purpose of enhancing the injection efficiency the same material as the second semiconductor layer 18 at the surface contiguous to the third semiconductor layer 19 or a material having a larger sum of the electron affinity and the forbidden band gap than the second semiconductor layer 18, is preferable. On the second semiconductor layer 18, a source electrode 6 and a drain electrode 7 are provided on the opposite sides of the third semiconductor layer 19. As one example which can realize the structure according to the above-mentioned preferred embodiment, there is heterojunction transistor, in which the first semiconductor layer 2 is made of high purity InP, the second semiconductor layer 18 consists of an n-AℓInAs layer of about 50 nm (500 Å) in thickness having an n-type impurity concentration of about 1 x 10¹⁸ cm⁻³ and matched in lattice with the InP (in the following it is always assumed that AℓInAs is matched with the InP ), and the third semiconductor layer 19 consists of a p⁺-AℓInAs layer of about 10 nm (100 Å) in thickness having a p-type impurity concentration of 1 x 10¹⁹ cm⁻³ or more. Now, assuming that the above-described materials were used for the respective semiconductor layers, the operation of the above-described preferred embodiment will be explained with reference to Fig. 2 which shows an energy level E c at the bottom of the conduction band, a Fermi level E F and an energy level E v at the top of the valence band, in the respective semiconductor layers 2, 18 and 19. This band diagram represents a thermal equilibrium state, and in order to facilitate understanding of the band structure, the state where two-dimensional electron gas 4 has been formed (depletion mode) is shown. In an FET for super high speed operation, under a thermal equilibrium state it is preferable to use the state where the two-dimensional electron gas 4 is not formed (enhancement mode). If a positive voltage is applied to the gate electrode 5, the junction between the p⁺-AℓInAs layer 19 and the n-AℓInAs layer 18 is forward biased. At this time, since the n-AℓInAs layer 18 has a low electron concentration and this layer is almost perfectly depleted, injection of electrons from the n-AℓInAs layer 18 to the p⁺-AℓInAs layer 19 caused by the forward bias can be almost neglected. On the other hand, injection of positive holes from the p⁺-AℓInAs layer 19 to the n-AℓInAs layer 18 is remarkable. The injected positive holes would pass through the n-AℓInAs layer 18 and would reach the boundary surface between the n-AℓInAs layer 18 and the InP layer 2, but since a barrier against positive holes is present here, the positive holes would accumulate at this boundary surface. Most of the accumulated positive holes would move to the side of the source electrode due to an electric field between the source and the gate. Also, a part of the positive holes would disappear by recombination with electrons. If positive holes accumulate at the n-AℓInAs/InP boundary surface, then two-dimensional electrons are induced at this boundary surface in accordance with the amount of the positive holes. As the induced two-dimensional electrons have a high mobility, they flow momentarily to the drain side due to the electric field between the source and the drain, and as a result, two-dimensional electrons are induced again by the positive holes. Accordingly, the positive holes injected from the p⁺-AℓInAs layer 19 would induce a large number of two-dimensional electrons before they are absorbed by the source electrode, and hence the ratio (the current amplification factor ß) of the drain current to the gate current (principally a positive hole current) becomes very large. In addition, since the number of the positive holes injected from the p⁺-AℓInAs layer 19 to the n-AℓInAs layer 18 is increased as an exponential function of the forward bias voltage (nearly corresponding to the gate voltage), the mutual conductance also increases exponentially in accordance with increase of the gate voltage, and becomes very large. In manufacture of the heterojunction transistor according to the above-described preferred embodiment, at first as a method of crystal growth, the MBE method was employed, thereby a high purity InP layer 2 of 1 µm in thickness was grown on a semi-insulating InP substrate 1, and subsequently, an n-AℓInAs layer 18 of 30 nm (300 Å) in thickness containing an Si impurity at a concentration of 1 x 10¹⁸ cm⁻³ and a p⁺-AℓInAs layer 19 containing a Be impurity at a concentration of 3 x 10¹⁹ cm⁻³ were sequentially grown. Subsequently, Aℓ was vapor deposited and patterned to form a gate electrode 5, then unnecessary p⁺-AℓInAs layer was removed by making use of the gate electrode 5 as a mask, source and drain electrodes 6 and 7 made of AuGe/Au were vapor deposited and alloyed, and thereby a transistor was completed. As a result, in a transistor having a gate length of 0.5 µm, and gate-source and gate-drain distances of 0.5 µm, the characteristics of gm = 6000 mS/mm (per 1 mm gate width) and ß = 100 were obtained. While InP/InAℓAs only was dislosed as semiconductor materials in the above-described preferred embodiment, obviously other semiconductor materials (for instance, InAs/GaAsSb) could be employed. The second and third semiconductor layers 18 and 19 in the above-described preferred embodiment need not have uniform compositions nor need not be uniformly doped. A variation of compositions and variation of doping in the thicknesswise direction could be given to the semiconductor layers. The variation of the composition is important for protection of the surface layer and for facilitating to take ohmic contact (For instance, the second semiconductor layer is gradually varied from n-AℓInAs to n-GaInAs.). The variation of the doping is important for the purpose of enhancing the injection efficiency of positive holes (the upper portion of the second semiconductor layer 18 being made to have a low impurity concentration) . In addition, with regard to formation of the source and drain electrodes, they could be formed not only on the second semiconductor layer but at a location where this semiconductor layer was dug down, or else, the third semiconductor layer was left and they could be deposited thereon. As described in detail above, according to the present invention, there is provided a heterojunction transistor in which a high degree of circuit integration is easy and the entire system can be operated at a super high speed, and so, the effects and advantages of the invention are great.

Claims: A heterojunction transistor including a first semiconductor layer (2) having a low impurity concentration, a second semiconductor layer (18) provided on said first semiconductor layer and made of a semiconductor material of one conductivity type, whose electron affinity is smaller than that of said first semiconductor layer, a third semiconductor layer (19) of the other conductivity type forming a PN-junction with said second semiconductor layer, a gate electrode (5) formed on and in ohmic contact with said third semiconductor layer and a source electrode (6) and a drain electrode (7) formed on opposite sides of said third semiconductor layer so as to be electrically, connected with the boundary surface between said first semiconductor layer and said second semiconductor layer, said second semiconductor layer having a smaller sum of the electron affinity and the forbidden band gap than said first semiconductor layer so as to form a recess at the bottom of the conduction band (E c ) adapted to collect electrons at the boundary surface between said first and second semiconductor layers on the side of said first semiconductor layer and to form a recess at the top of the valence band (E v ) adapted to collect holes at the boundary surface between said first and second semiconductor layers on the side of said second semiconductor layer.

Inventors: BABA, TOSHIO, OGAWA, MASAKI, OHATA, KEIICHI
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H01L29
IPC codes: H01L29