Nor gate with logical low output clamp

Abstract: A NOR gate consisting of a set of input FET's (Q1₁ - Q1 M ) has a clamp (12/Q2) that, when at least one of the input FET's (Q1₁-Q1 M ) is turned on, clamps the logical low level of the gate output voltage (V o ) at a value which is largely con­ stant irrespective of how many of the input FET's (Q1₁-Q1 M ) are conductive.

Description: This invention relates to logic gates suitable for semiconductor integrated circuits and in particular to a gate having: a plurality of like-polarity enhancement-mode first field-effect transistors each of which has a gate electrode for receiving a corresponding input voltage, a source and a drain; a conductor coupled to the drains for providing an output voltage; a current source coupled between the conductor and a terminal for a first supply voltage; and means coupling the sources to a terminal for a second supply voltage. The invention also relates to a programmable array comprising such a gate. Such a gate is known from JP-A 57/192,122. Logic gates are used extensively in digital integrated circuits. Figure 1 shows a conventional NOR gate formed with M identical enhancement-mode N-channel insulated gate field-effect transistors (FET's) Q1₁, Q1₂, ... and Q1 M whose (insulated) gate electrodes respectively receive M input signals voltages V I1 , V I2 , ... and V IM . The drains of FET's Q1₁ - Q1 M are connected to an electrical conductor LD that provides an output signal voltage V o as the logical NOR of input voltages V I1 - V IM . A current supply 10 consisting of a depletion-mode N-channel FET QS is source-to-drain connected between conductor LD and a terminal for a high supply voltage V DD . FET QS has its gate electrode tied to its source so as to act as a load for FET's Q1₁ - Q1 M . Their sources are connected to a terminal for a low supply voltage V SS by way of another electrical conductor LS. Use of conventional terminology for positive logic facilitates an understanding of the operation in this gate. A low voltage is a logical low referred to as logical "0". A high voltage is a logical high referred to as logical "1". Each FET Q1₁ ... or Q1 M is turned on when corresponding input V I1 ... or V IM is at a logical high voltage exceeding V SS by at least the FET threshold voltage, and vice versa . Output V o is at logical "1" when inputs V I1 ... V IM are all at logical "0" so that FET's Q1₁ - Q1 M are off. As one of inputs V I1 - V IM rises to logical "1" to turn on the corresponding one of FET's Q1₁ - Q1 M , output V o falls to logical "0". The actual logical low voltage level for output V o depends upon the number of FET's Q1₁ - Q1 M turned on. The logical "0" voltage is lower when more of FET's Q1₁ - Q1 M are conductive. This is disadvantageous in many applications because the time needed to differentially sense output V o can vary drastically from the case where on of FET's Q1₁ - Q1 M is turned on to the situation where all are conductive. To reduce the dependence on the number of gates turned on, JP 57/192,122 teaches the use of a resistive element by way of coupling means. In this way, the output voltage will be determined in part by the voltage drop caused by the current flowing through the resistive element which is independent of the number of gates. This reduces the dependence on the number of gates turned on, but only to a limited extent. From WO 85/01165, a gate according to the preamble, but with bipolar transistors instead of the first field effect transistors is known. In this circuit, the emitters of the bipolar transistors are coupled to a collector of a Schottky clamped bipolar transistor, which has its emitter connected to the terminal for the second supply voltage. The conductor is connected to the base of the Schottky clamped transistor via a parallel arrangement of a Schottky diode and a resistor. This circuit makes use of the Schottky diode characteristic and the base current - base voltage characteristic of the basis emitter junction of the Schottky clamped transistor to inhibit saturation of the bipolar transistors. DISCLOSURE OF THE INVENTION The present invention centres on a relatively simple mechanism for better clamping of the logical low output voltage of a logical gate of the foregoing type. This makes it easier to differentially sense the output signal and thereby enhances sensing speed over the prior art gate described above. The present logic gate is especially useful in applications such as programmable logic devices. More particularly, the present gate contains a plurality of like-polarity enhancement-mode first FET's. Each FET has a gate electrode for receiving a corresponding input voltage, a source and a drain. A conductor is coupled to the drains of the first FET's for providing an output voltage. A current supply is coupled between the conductor and a terminal for a first supply voltage. The sources of the first FET's are coupled to a terminal for a second supply voltage by way of a clamp. The gate according to the invention is characterized, the coupling means (LS, 12) comprise a clamp consisting of a like polarity enhancement mode second FET (Q₂), having a source connected to the terminal for the second supply voltage and a drain connected to the sources of the first FETs (Q1₁, Q1₂,.., Q1 M ), a gate of the second FET (Q₂) being directly connected to the conductor (LD) for receiving the output voltage. When at least one of the first FET's is conductive, the clamp regulates the output voltage to approach a value that is largely the same regardless of the number of first FET's turned on. The characteristics of the FET's are chosen such that the second FET is saturated when one or more of the first FET's are turned on. In saturation, the gate-to-source voltage of the second FET is substantially independent of the drain-to-source voltages of the first FET's. Consequently, the number of conductive first FET's does not significantly effect the conductive level of the second FET as long as at least one of the first FET's is turned on. This provides the clamping action. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a prior art NOR gate. Fig. 2 is a circuit diagram of an embodiment of a NOR gate in accordance with the invention. Fig. 3 is a circuit diagram of an embodiment of two-level programmable logic device utilizing NOR gates in accordance with the invention. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item for items. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 2 illustrates a NOR gate having a logical low output clamp embodying the techniques of the invention. As in Fig. 1, this gate contains identical enhancement-mode N-channel insulated-gate FET's Q1₁ - Q1 M connected between conductors LS and LD for generating output V O as the logical NOR of inputs V I1 - V IM supplied to the gate electrodes. Current supply 10 is connected between conductor LD and the V DD terminal in Fig. 2 to act as a load for FET's Q1₁ - Q1 M . Current supply 10 could, for example, be a depletion-mode resistively-connected N-channel FET as in Fig. 1. Conductor LS is coupled to the V SS terminal in Fig. 2 through a clamp 12 consisting of an N-channel enhancement-mode insulated-gate FET Q2 whose gate electrode connects to conductor LD to receive output V O . The source and drain of FET Q2 are respectively connected to the V SS terminal and conductor LS. When one or more of FET's Q1₁-Q1 M are conductive, clamp 12/FET Q2 clamps output voltage V O at a low logical value V OL that is largely the same irrespective of how many of FET's Q1₁ - Q1 M are conductive. V OL lies between V SS and V DD considerably closer to V SS . If V DD is about 5 volts greater than V SS , V OL is typically about 1 volt above V SS . The NOR gate operates in basically the same way as that of Fig. 1 except that the logical "0" value of voltage V O is clamped at V OL rather than being variable. In looking at how the clamping action occurs, assume (for convenience) that V SS is ground reference. Output V O then equals the Q2 gate-to-source voltage V GS2 . When voltage V O is at logical "0", current supply 10 provides a substantially constant current I S that flows through FET Q2 which is turned on. Each FET Q1₁, ... or Q1 M must itself be able to accommodate current I S when output V O is low since only one of FET'S Q1₁ - Q1 M may be turned on. Consider the case in which, for example, only FET Q1₁ is turned on. All of current I S flows through FET Q1₁. FET's Q2 and Q1₁ (as well as FET's Q1₂ - Q1 M ) are fabricated in such a manner that the Q2 threshold voltage V TH2 exceeds the Q1₁ drain-to-tource voltage V DS11 when FET Q1₁ is conductive but FET's Q1₂ - Q1 M are non-conductive. In Fig. 2, voltage V GS2 equals voltage V DS11 plus the Q2 drain-to-source voltage V DS2 . It follows that: V GS2 - V DS2 < V TH2 (1) Under this condition, FET Q2 is in saturation. To a good approximation, voltage V GS2 is given from the relationship: V GS2 = V TH2 + (I S /K) ½ (2) K is a constant dependent on the charge carrier mobility, the gate-dielectric capacitance, and the FET width-to-length ratio. Since output V O equals voltage V GS2 , VO is dependent only on V TH2 , I S , and K and is therefore largely independent of V DS11 . Next, consider the case in which two or more of FET's Q1₁ - Q1 M are turned on. Let FET Q1₁ be one of the conducting FET's. Current I S flows through the conductive FET's, each carrying an approximately equal portion. Because the current through FET Q1₁ is less than in the previous case, voltage V DS11 is also less. As a result, V TH2 again exceeds V DS11 . Eq. (1) is satisfied so that FET Q2 is again in saturation. Eq. (2) is similarly satisfied since current I S still flows through FET Q2. Accordingly, output V O is substantially independent of parameters relating to the conductive conditions of FET's Q1₁ - Q1 M . The result is that voltage V OL does not significantly depend on how many of FET's Q1₁ - Q1 M are turned on as long as at least one is conductive. Clamp 12/FET Q2 provides negative feedback to stabilize voltage V OL . If output V O rises slightly, FET Q2 starts to become more conductive and attempts to draw more current through those of FET's Q1₁ - Q1 M that are turned on. This acts to reduce their drain-to-source voltages so as to restore voltage V O to its previous value. The reserve occurs if output V O drops slightly. Current I S is preferably supplied at a level that is largely independent of supply V DD , temperature, and process conditions. Current supply 10 also compensates for changes in threshold V TH2 resulting from process variations. Voltage V OL is then stable over temperature, process variations, and supply V DD . If FET's Q1₁ - Q1 M are all off, output V O is high. FET Q2 does not conduct any significant current even though V GS2 exceeds V TH2 . Current supply 10 preferably includes a mechanism for clamping voltage V O at a high level V OH lying between V OL and V DD but closer to V OL . The difference between voltages V OH and V OL is typically about 1 volt. This makes the switching speed very high. Fig. 3 shows a two-level programmable logic device that utilizes the present clamping techniques in operating on N input signals I₁ - I N to generate P output signals O₁ - O p . Inputs I₁ - I N are provided to respective odd-numbered inverters W₁ - W M-1 (where M = 2N) to produce even-numbered voltages V I2 - V IM . These signals are respectively supplied to even-numbered inverters W₂ - W M to produce odd-numbered voltage V I1 - V IM-1 . Conductors LG₁ - LG M then transmit voltages V I1 - V IM to a programmable NOR array 14 consisting of S identical programmable NOR gates A₁ - A S . By virtue of DeMorgan's theorem, the combination of NOR array 14 with inverters W₁ - W M functions as a programmable AND array. High-impedance non-inverting buffers Y₁ - Y S amplify the "ANDed" output signals from gates A₁ - A S . The amplified signals are provided to a programmable NOR array 16 consisting of P identical programmable NOR gates B₁ - B p . High-impedance inverting buffers Z₁ - Z p invert the outputs from gates B₁ - B p to generate signals O₁ - O p . The combination of NOR array 16 with inverters Z₁ - Z p functions as a programmable OR array. Gates A₁ - A M and B₁ - B M are all configured in substantially the same way. Fig. 3 illustrates details for typical gate A₁ which contains FET's Q1₁ - Q1 M and Q2 configured and operational as described above for Fig. 2 except that each of FET's Q1₁ - Q1 M is a floating-gate memory FET having a programmable controllable threshold voltage. In the unprogrammed state, the threshold voltage for each of FET's Q1₁ - Q1 M is low. During programming, the threshold voltages of certain of FET's Q1₁ - Q1 M are raised to a high level, typically greater than the power supply voltage. These FET's cannot be turned on during normal operation of the device and are therefore effectively absent from gate A₁. Current supply 10 consists of enhancement-mode N-channel insulated-gate FET's Q3 and Q4 connected in series between conductor LD and the V DD terminal. Voltage V O is supplied to the source of FET Q3 whose drain provides the A₁ output signal. Reference voltages V R1 and V R2 are respectively supplied to the Q3 and Q4 gate electrodes. V R1 and V R2 are of such values that FET Q3 turns off when V O reaches about 0.4 volt above V OL (after FET's Q1₁ - Q1 M all go off). This clamps the logical high level of output V O . The capacitance on conductor LD is also decoupled from that on the A1 output conductor so as to increase the switching speed of the A1 output signal. Gate A₁ also has a capacitor C1 connected between conductor LS and the V SS supply. Capacitor C1 serves to increase switching speed but largely does not affect the operation of FET Q2. In a preferred embodiment, V SS and V DD are 0 and 4.5 - 5.5 volts, respectively. The unprogrammed threshold voltage for each of memory FET's Q1₁ - Q1 M is about 1.5 volt. The programmed threshold voltage for the memory FET's is greater than 6 volts. Capacitor C1 is 1 picofarad. Methods for manufacturing various elements of the present invention are well known in the semiconductor art. These elements are preferably fabricated in monolithic integrated circuit from according to conventional insulated-gate semiconductor techniques. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration. For example, semiconductor elements of opposite polarity to those described above may be employed to accomplish the same results. Junction FET's could generally be used.

Claims: A logic gate having: a plurality of like-polarity enhancement mode first field effect transistors (FET's) (Q1₁, Q1₂, .., Q1 M ), each of which has a gate electrode for receiving a corresponding input voltage (V I1 , V I2 ,.., V IM ), a source and a drain; a conductor (LD) coupled to the drains for providing an output voltage (V o ); a current source coupled between the conductor and a terminal for a first supply voltage (V DD ); and means (LS, 12) coupling the sources to a terminal for a second supply voltage (V SS ); characterized, in that the coupling means (LS, 12) comprise a clamp consisting of a like polarity enhancement mode second FET (Q₂), having a source connected to the terminal for the second supply voltage and a drain connected to the sources of the first FETs (Q1₁, Q1₂,.., Q1 M ), a gate of the second FET (Q₂) being directly connected to the conductor (LD) for receiving the output voltage. A gate as in Claim 1 characterized in that the second FET (Q₂) is in saturation when at least one of the first FET's (Q1₁, Q1₂, ... Q1 M ) is turned on. A gate as in Claim 2 characterized in that each FET (Q1₁, Q1₂, ... Q1 M , Q₂) is an insulated-gate FET. A gate as in Claim 3 characterized in that each first FET (Q1₁, Q1₂, ... Q1 M ) has a programmable controllable threshold voltage. A gate as in Claim 4 characterized in that each first FET (Q1₁, Q1₂, ... Q1 M ) is a floating-gate FET. A gate as in any one of the Claims 1 to 5 characterized in that the current supply includes means that, when the first FET's are all turned off, clamps the output voltage at a value between a clamped value which occurs when not all FET's are turned off and the first supply voltage, but closer to the clamped value. A programmable array comprising: a group of identical gates as in Claim 4; a like-plurality of third conductors (LG₁, LG₂, ... LG M-1 , LG M ) corresponding on a one-to-one basis to the first FET's of each gate, each third conductor coupled to the gate electrodes of all the corresponding first FET's (Q1₁, Q1₂, ..., Q1 M-1 , Q1 M ). An array as in Claim 7 including input means (W₁, W₂, ... W M-1 , W M ) for providing each consecutive pair of third conductors with voltages of opposite polarity.

Inventors: BECKER SCOTT TIMOTHY, BERGMAN MICHAEL JOHN, LEE SHUEH-MIEN, BECKER, SCOTT TIMOTHY, BERGMAN, MICHAEL JOHN, LEE, SHUEH-MIEN
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1986
Main classification: H03K19
IPC codes: H03K19