DIFFERENTIAL AMPLIFIER CIRCUIT

Abstract: A differential amplifier circuit comprising first and second input lines (B,B') to which potentials with a slight differ­ ence therebetween are to be applied, a series combination of a first load transistor (20) and a first amplifier transistor (24) pro­ vided between a supply voltage, a series combination of a second load transistor, (22) and a second amplifier transistor (26) provided between a supply voltage and activating means (28) for activating (⊘ SE ) each of the first and second amplifier transis­ tors. The control terminal of the first amplifier transis­ tor (24) being connected to the first input line (B) and the control terminal of the second amplifier transistor (26) being connected to the second input line (B'), characterized by current cutoff means (42,38,44,40) provided in association with the first and second load tran­ sistors and responsive to the potentials applied to the first and second input lines, the current cutoff means being opera­ tive to electrically isolate one of the first and second amplifier transistors from the supply voltage in response to variation in the voltage on one of the first and second input lines.

Description: The present invention relates to a differential amplifier circuit and, more particularly, to a differential amplifier circuit useful typically as a sense amplifier for use in a semiconductor memory device. A semiconductor memory device has a sense amplifier designed to detect a slight difference between the potentials on two mutually associated bit lines of a memory array which consists of a multiplicity of memory cells. Such a differential voltage between the two bit lines is detected upon amplification by the sense amplifier. The two bit lines may consist of either a pair of mutually complementary bit lines or a bit line and a dummy bit line associated therewith. In a known sense amplifier for a semiconductor memory device of, for example, the static type, one of the two sets of series connected transistors provided between the supply voltage line and the activating transistor of the amplifier must be maintained in conduction states for a substantial period of time during each of the read cycles of the device. A path of current is thus formed through one set of the series connected transistors for a substantial period of time during each read cycle. A considerably large amount of steady-state current flows to ground through this current path, thus giving rise to an increase in the amount of power dissipation by the memory device. From DE-B-2 734 987 a flip-flop circuit is known which allows the current passing through an input transistor in the on-state to be cut off by selectively discharging the electric charges accumulated in the gate electrode of a load transistor. The flip-flop circuit is constituted by a pair of input transistors, the gate electrodes of which are coupled to the drain nodes in a crossing manner, and the input voltage signal also serves as the output voltage signal. Thus, the flip-flop circuit is different in arrangement from a differential amplifier, in particular with respect to the circuit behaviour, impedance, and noise sensitivity, so that a differential amplifier circuit can not be replaced with a flip-flop circuit. A differential amplifier circuit according to the preamble part of claim 1 is disclosed in EP-A-0 149 403 in which the output nodes of two inverter circuits are coupled through a clamp circuit consisting of two transistors. However, the two inverter circuits are independent from each other and directly coupled to a voltage source, so that this amplifier circuit can not maintain a result without consumption of DC current. It is therefore a prime object of the invention to provide a differential amplifier circuit in which the path of current which would otherwise be formed unnecessarily in the circuit during each circle of operation of the circuit is cut off in response to variation in the voltage input to the circuit. This object is achieved by a differential amplifier circuit having a stand-by mode of operation and an active mode of operation, comprising first and second amplifier transistors of a first channel conductivity type, first and second load transistors, the channels thereof being respectively coupled to drain nodes of said first and second amplifier transistors for supplying electric currents thereto, respectively, and first and second input lines respectively coupled to the gate electrodes of said frist and second amplifier transistors, both of said first and second input lines remaining in a first voltage level in said stand-by mode of operation, one of said first and second input lines being changed to a second voltage level in said active mode of operation, an output voltage level being produced at one of the drain nodes of said first and second amplifier transistors, first and second switching transistors of the second channel conductivity tpye opposite to said first channel conductivity type respectively coupled between a second constant voltage source and the channels of said first and second load transistors, first and second inverter circuits respectively coupled at input nodes thereof to said second and first input lines and at output nodes thereof to gate electrodes of said first and second switching transistors, an activating transistor coupled between source nodes of said first and second amplifier transistors and a first constant voltage source and allowed to turn on in said active mode of operation, wherein the first and second load transistors are of a second channel conductivity type opposite to said first channel conductivity type, and wherein said first and second switching transistors turn on in said stand-by mode of operation and either first or second switching transistor turns off in said active mode of operation if said second or said first amplifier transistor turns on, respectively. BRIEF DESCRIPTION OF THE DRAWINGS The drawbacks of a prior-art sense amplifier and the features and advantages of a differential amplifier circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding units and elements and in which: Fig. 1 is a circuit diagram showing the circuit arrangement of a representative example of a prior-art sense amplifier for a static semiconductor memory device; Figs. 2A and 2B are timecharts showing examples of the waveforms of various voltages and currents to appear in the circuit arrangement of the sense amplifier shown in Fig. 1; Fig. 3 is a circuit diagram showing the circuit arrangement of another representative example of a prior-art sense amplifier for a semiconductor memory device; Figs. 4A and 4B are timecharts showing examples of the waveforms of various voltages and currents to appear in the circuit arrangement of the sense amplifier shown in Fig. 3; Fig. 5 is a circuit diagram showing the circuit arrangement of a first preferred embodiment of a differential amplifier circuit according to the present invention; Figs. 6A and 6B are timecharts showing examples of the waveforms of various voltages and currents to appear in the circuit arrangement of the sense amplifier circuit shown in Fig. 5; Fig. 7 is a circuit diagram showing the circuit arrangement of a second preferred embodiment of a differential amplifier circuit according to the present invention, the second embodiment being a modification of the embodiment shown in Fig. 5; DESCRIPTION OF THE PRIOR ART In Fig. 1 of the drawings, a known sense amplifier for use in a static semiconductor memory device is shown provided in association with a pair of mutually complementary bit lines B and B'. These complementary bit lines B and B' represent a multiplicity of bit lines provided in combination with word lines in a memory array consisting of a number of memory cells, though not shown in the drawings. The prior-art sense amplifier thus provided between the bit lines B and B' includes a pair of load transistors 20 and 22 each provided by a p-channel MOS (metal-oxide-semiconductor) field-effect transistor and a pair of amplifier transistors 24 and 26 each provided by an n-channel MOS field-effect transistor. The load transistors 20 and 22 have their sources connected to a voltage supply line for a positive supply voltage V DD and their drains connected to the drains of the amplifier transistors 24 and 26, respectively. Furthermore, the load transistors 20 and 22 have their gates commonly connected to the common drains of the load and amplifier transistors 20 and 24. The amplifier transistors 24 and 26 have their gates connected to the bit lines B and B', respectively, and their sources commonly connected to ground line commonly through an activating transistor 28 which is provided by an n-channel MOS field-effect transistor. The activating transistor 28 has its drain connected to the respective sources of the amplifier transistors 24 and 26 through a common node 30, its source connected to ground line, and its gate connected to a clock supply line 32 for an active-high clock signal Ø SE . The load and amplifier transistors 22 and 26 further have their gates commonly connected through a node N to an output line 34 to produce an output signal V OUT as being representative of the bit of information read out from the memory device during each read cycle. Operation of the prior-art sense amplifier thus constructed and arranged will now be described with reference to Fig. 1 and further to Figs. 2A and 2B. In Fig. 2A, lines indicated by B and B' represent the potentials which occur on the true and complementary bit lines B and B', respectively, and curve N represents the potential which occurs at the output node N. Furthermore, it is assumed for purposes of discussion that the memory cell selected during the read cycle under consideration has a logic "0" bit of information. Under such a condition, a voltage approximating the ground level V SS is to appear on the bit line B and a voltage approximating the supply voltage V DD is to appear on the complementary bit line B' during the current read cycle. At an incipient stage of the read cycle, the bit lines B and B' are precharged toward a level approximately equal to the supply voltage V DD (of, for example, 5 volts). After the bit lines B and B' are thus precharged, the potentials at the bit lines B and B' are allowed to float at a high levels approximating the supply voltage V DD . The potentials of such high levels established at the gates of the amplifier transistors 24 and 26 maintain each of the n-channel field-effect transistors 24 and 26 ready to turn on. When the memory cell storing the logic "0" bit of information is thereafter selected and is connected to the bit line pair B/ B at time t₀ (Fig. 2A), the potential on the true bit line B declines gradually toward the ground level V SS with the potential on the complementary bit line B' maintained at the level approximating the supply voltage V DD as will be seen from Fig. 2A. The clock signal Ø SE on the clock supply line 32 swings to a high level (V DD ) also at time t₀ and is supplied to the gate of the activating transistor 28, as will be also seen from Fig. 2A. The activating transistor 28 is now turned on so that the potential at the common node 30 between the amplifier transistors 24 and 26 drops from the level approximating the supply voltage V DD toward the ground level V SS through the transistor 28. With the potentials of the high levels present at the gates of the amplifier transistors 24 and 26 at time t₀, each of the n-channel field-effect transistors 24 and 26 is allowed to turn on also at time t₀. The potential at the common node being reduced to the ground level, there are created differential voltages between the bit line B and the common node 30 and between the bit line B' and the common node 30. The potential on the bit line B being on the decline as shown in Fig. 2A, the differential voltage produced between the gate and source of the amplifier transistor 24 becomes lower than the differential voltage between the gate and source of the amplifier transistor 26. It therefore follows that the channel conductance of the amplifier transistor 26 becomes higher than that of the amplifier transistor 24 with a higher potential present at the complementary bit line B' than at the true bit line B. The transistor 26 being thus higher in channel conductance than the transistor 24, the potential at the output node N drops toward a certain level (indicated by V N in Fig. 2A) at a higher rate than the potential at the drain of the amplifier transistor 24.The particular level V N to which the potential at the output node N is thus reduced is dictated by the on-state resistances of the series connected transistors 22, 26 and 28. The voltage of such a level V N produced at the output node N is supplied through the output line 34 to an external device such as typically a microprocessor (not shown) as an output signal V OUT representative of the logic "0" bit of information read out from the memory array during the current read cycle. When the differential voltage between the gate and source of the amplifier transistor 24 is thereafter reduced below the level of the threshold voltage V TN of the n-channel field-effect transistor 24, the transistor 24 is turned off as at time t₁ with the corresponding transistor 26 maintained in the conduction state. Fig. 3 shows another representative example of a known sense amplifier for use in a static semiconductor memory device. The sense amplifier herein shown is basically similar construction to the prior-art sense amplifier described with reference to Fig. 1 but is arranged in conjunction with a bit line B and a dummy bit line DB. In association with each of the dummy bit line DB is provided a dummy cell which is one of the dummy cells provided along a dummy word line, though not shown in the drawings. The bit line B and dummy bit line DB are also connected to precharge transistors though not shown in the drawings. The prior-art sense amplifier shown in Fig. 3 is provided in association with these bit line B and dummy bit line DB and comprises p-channel load transistors 20 and 22 and n-channel amplifier transistors 24 and 26 and an n-channel activating transistor 28, similarly to the sense amplifier described with reference to Fig. 1. In the sense amplifier herein shown, the load transistors 20 and 22 have their gates commonly connected to ground line to provide certain on-state resistances. Between the common drains of the load and amplifier transistors 20 and 24 and the common drains of the load and amplifier transistors 24 and 26 are provided first and second sense nodes N₁ and N₂ from which first and second output lines 36 and 36' lead to an external device such as a microprocessor (not shown). In operation, the bit line B and dummy bit line DB are precharged toward a level approximately equal to the supply voltage V DD at an incipient stage of a read cycle. When a memory cell storing, for example, a logic "0" bit of information is selected, the potential on the bit line B declines gradually toward the ground level V SS with the potential on the dummy bit line DM maintained at the level approximating the supply voltage V DD as will be seen from Fig. 4A. In Fig. 4A, lines indicated by B and DB represent the potentials which occur on the bit line B and dummy bit line DM, respectively, and curves indicated by N₁ and N₂ represent the potentials which occur at the first and second sense nodes N₁ and N₂, respectively. The clock signal Ø SE on the clock supply line 32 now swings to a high level (V DD ) and is supplied to the gate of the activating transistor 28, as will be also seen from Fig. 4A. The activating transistor 28 is now turned on so that the potential at the common hode 30 between the amplifier transistors 24 and 26 drops toward the ground level V SS through the transistor 28. With the potentials of the high levels present at the gates of the amplifier transistors 24 and 26, each of the n-channel field-effect transistors 24 and 26 is allowed to turn on. The potential at the node 30 being reduced to the ground level, a differential voltage is created between the common node 30 and each of the bit line B and dummy bit line DM. The potential on the bit line B being on the decline, the voltage thus produced between the gate and source of the amplifier transistor 24 becomes lower than the voltage between the gate and source of the amplifier transistor 26 with the result that the channel conductance of the transistor 26 becomes higher than that of the transistor 24. The transistor 26 being thus higher in channel conductance than the transistor 24, the potential at the second sense node N₂ drops at a higher rate than the potential at the first sense node N₁ toward a certain level V N2 dictated by the on-state resistances of the series connected transistors 22, 26 and 28. As the potential on the bit line B further declines, the differential voltage between the gate and source of the amplifier transistor 24 is reduced to the level of the threshold voltage of the transistor 24, the transistor 24 is turned off so that the potential at the first sense node N₁ rises toward the initial level approximating the supply voltage V DD . The differential voltage between the bit line B and dummy bit line DM is in these manners amplified into the differential voltage (V DD - V N2 ) between the first and second sense nodes N₁ and N₂. Such an amplified differential voltage V DD - V N2 is supplied to the external device as an output signal V OUT representative of the logic "0" bit of information read out from the memory array. In each of the the prior-art sense amplifiers constructed and arranged as hereinbefore described, either the load and amplifier transistors 22 and 26 or the load and amplifier transistors 20 and 24 must be maintained in conduction states for a substantial period of time during each read cycle. During each read cycle of the device, the first load and amplifier transistors 20 and 24 must be maintained conductive until a logic "1" bit of information has been read out and the load and amplifier transistors 22 and 26 must be maintained conductive until a logic "0" bit of information has been read out from the memory array. A path of current is thus formed through the series connected transistors 20, 24 and 28 or the series connected transistors 22, 26 and 28 for a substantial period of time during each read cycle. A considerably large amount of steady-state current is allows to flow through this current path even after the amplifier transistor 24 or 26 has been turned off, as will be seen from the curves shown in Figs. 2B and 4B. This gives rise to an increase in the amount of power dissipation by the memory device using the sense amplifier under consideration. DESCRIPTION OF THE PREFERRED EMBODIMENTS A differential amplifier circuit embodying the present invention is assumed to be incorporated in a semiconductor memory device having memory cells arranged in rows along a plurality of word lines and in columns along a plurality of bit lines. Of these word lines and bit lines provided in the memory device, only a pair of mutually complementary bit lines B and B' are shown Fig. 5 as being representative of the bit lines. These bit lines B and B' are connected to a row of memory cells with each of the word lines connected to a column of memory cells as well known in the art. These memory cells thus arranged in rows and columns along the bit lines and word lines are herein assumed to be of the static type by way of example. Each of these memory cells has stored therein a logic "0" or "1" bit of information if the cell is of the ROM (read only memory) type or is capable of storing such a bit of information therein if the cell is of the RAM (random access memory) type. Such a memory cell is implemented by, for example, a complementary metal-oxide-semiconductor (CMOS) device or a plurality of such devices. Though not shown in the drawings, there are further provided precharge transistors including those respectively associated with the bit lines B and B'. Each of these precharge transistors is provided by a p-channel or n-channel MOS field-effect transistor having its gate connected to a source of an active-low or active-high precharge enable signal and its source-drain current path connected to a source of, typically, a supply voltage V DD . At an incipient stage of each read cycle, the bit lines B and B' are thus precharged to a voltage approximating the supply voltage V DD through such precharge transistors. The precharge transistors are activated to turn on in response to the transition of the precharge enable signal to either a low level or a high level depending upon the type of the semiconductor device forming each precharge transistor, as also well known in the art. The differential amplifier circuit embodying the present invention is in part similar in construction and arrangement to the prior-art sense amplifier described with reference to Fig. 1 and comprises first and second load transistors 20 and 22 and first and second amplifier transistors 24 and 26. Each of the load transistors 20 and 22 is provided by a p-channel MOS field-effect transistor and each of the amplifier transistors 24 and 26 is provided by an n-channel MOS field-effect transistor. The first and second load transistors 20 and 22 have their drains connected to the drains of the first and second amplifier transistors 24 and 26, respectively. These load transistors 20 and 22 have their gates commonly connected to the common drains of the first load and amplifier transistors 20 and 24. The first and second amplifier transistors 24 and 26 have their gates connected to the true and complementary bit lines B and B', respectively, and their sources commonly connected to ground line through an activating transistor 28. The activating transistor 28, which is provided by an n-channel MOS field-effect transistor, has its drain connected to the respective sources of the first and second amplifier transistors 24 and 26 through a common node 30, its source connected to ground line, and its gate connected to a clock supply line 32 for an active-high clock signal Ø SE . The activating transistor 28 is to be driven to turn on by the clock signal Ø SE of a certain high level and the second load and amplifier transistors 22 and 26 have their gates commonly connected through a node N to an output line 34 to produce an output signal V OUT as in the prior-art sense amplifier shown in Fig. 1. In accordance with the present invention, the differential amplifier circuit shown in Fig. 5 further comprises first and second current cutoff transistors 38 and 40 each of which is provided by a p-channel MOS field -effect transistor. These first and second current cutoff transistors 38 and 40 have their sources connected to a voltage supply line for the supply voltage V DD , and their drains connected to the sources of the first and second load transistors 20 and 22, respectively. The current cutoff transistors 38 and 40 further have their gates connected to the complementary and true bit lines B' and B through first and second inverters 42 and 44 as shown. It will thus be seen that signals B and DB respectively inverted from the signals which appear on the true and complementary bit lines B and B' are to be produced at the gates of the transistors 38 and 40. Operation of the differential amplifier circuit thus constructed and arranged will now be described with reference to Fig. 5 and further to Figs. 6A and 6B. In Fig. 6A, curves indicated by DB and B represent the potentials which occur at the output terminals of the first and second inverters 42 and 44, respectively. In response to an access request signal supplied from an external source such as typically a microprocessor (not shown), the memory device is initiated into action to read out the information stored in any of the memory cells of the device. The precharge enable signal now swings to a high level or a low level and is supplied to the gate of each of the precharge transistors associated with the bit lines B and B'. Each of the true and complementary bit lines B and B' thus begins to be precharged toward a level approximately equal to the supply voltage V DD (of, for example, 5 volts). After the bit lines B and B' are fully precharged, the precharge transistors are turned off so that the potentials at the bit lines B and B' thereafter float at high levels each approximating the supply voltage V DD . With the potentials of such high levels established at the bit lines B and B', potentials of low levels approximating the ground level V SS appear at the outputs of the first and second inverters 42 and 44. Such low potential levels present at the gates of the first and second current cutoff transistors 38 and 40 maintain each of the p-channel field-effect transistors 38 and 40 in a conduction state. Furthermore, the potentials of the high levels established at the gates of the first and second amplifier transistors 24 and 26 maintain each of the n-channel field-effect transistors 24 and 26 ready to turn on. For purposes of discussion, it will be also be assumed that the memory cell selected during the read cycle under consideration has a logic "0" bit of information. With the logic "0" storing memory cell thus selected, a voltage approximating the ground level V SS is to appear on the bit line B and a voltage approximating the supply voltage V DD is to appear on the complementary bit line B' during the current read cycle. The particular memory cell storing the logic "0" bit of information is selected out of the memory cells arranged along the bit line pair B/ B and is connected to the bit line pair B/ B at time T₀ (Fig. 6A). Accordingly, the potential on the true bit line B declines after time T₀ gradually toward the ground level V SS with the potential on the complementary bit line B' maintained at the initial level approximating the supply voltage V DD as will be seen from Fig. 6A. This results in development of an increasing differential voltage between the true and complementary bit lines B and B'. The clock signal Ø SE on the clock supply line 32 swings to a high level (V DD ). also at time T₀ and is supplied to the gate of the activating transistor 28, as will be also seen from Fig. 6A. The activating transistor 28 is driven to turn on so that the potential at the common node 30 between the respective sources of the amplifier transistors 24 and 26 drops from the level approximating the supply voltage V DD toward the ground level V SS through the transistor 28. There are now created a differential voltage between the bit line B and the common node 30, viz., between the gate and source of the first amplifier transistor 24 and a differential voltage between the bit line B' and the common node 30, viz., between the gate and source of the second amplifier transistor 26. With the potentials of the high levels present at the gates of the first and second amplifier transistors 24 and 26 at time T₀, each of the n-channel field-effect transistors 24 and 26 is allowed to turn on also at time T₀. The potential on the bit line B being currently on the decline as shown in Fig. 6A, the differential voltage present between the gate and source of the first amplifier transistor 24 becomes lower than the differential voltage between the gate and source of the second amplifier transistor 26. Accordingly, the channel conductance of the second amplifier transistor 26 becomes higher than that of the first amplifier transistor 24 with a higher potential present at the bit line B' than at the bit line B. The transistor 24 being thus higher in channel conductance than the transistor 26, the charges which have been accumulated at the output node N between the common drains of the load and amplifier transistors 22 and 26 are passed to ground line through the transistors 26 and 28 at a higher rate than the charges passed to the ground line through the transistors 24 and 28. Thus, the potential at the output node N drops at a higher rate than the potential at the node between the common drains of the first load and amplifier transistors 20 and 24 toward a certain level V N dictated by the respective on-state resistances of the series connected transistors 40, 22, 26 and 28. The voltage V N now present at the output node N is supplied through the output line 34 to the external device (not shown) as an output signal V OUT representative of the logic "0" bit of information read out from the memory array during the current read cycle. With the potential of a high level established at the complementary bit line B', the first current cutoff transistor 38 is maintained in a conduction state in response to the potential of the ground level V SS present as the inverted signal DB at the gate of the p-channel field-effect transistor 38 through the first inverter 42. On the other hand, the potential which appears as the inverted signal B at the gate of the second current cutoff transistor 40 gradually rises with a consequent decrease in the voltage between the potential at the gate of the current cutoff transistor 40 and the supply voltage V DD , viz., the differential voltage between the gate and source of the second current cutoff transistor 40. The voltage between the gate and source of the transistor 40 is thus reduced below the threshold voltage V TP of the transistor 40 to cause the transistor 40 to turn off at time T₁ as shown in Fig. 6A, with the result that the current I S which is allowed to pass through the activating transistor 28 steeply drops at time T₁ as will be seen from Fig. 6B. With the second current cutoff transistor 40 turned off, furthermore, the potential at the output node N declines from the level V N to the ground level V SS immediately after time T₁ as will be seen from Fig. 6A. As the potential on the bit line B further declines, the differential voltage between the gate and source of the first amplifier transistor 24 is reduced below the level of the threshold voltage V TN of the n-channel field-effect transistor 24, the transistor 24 is turned off as at time T₂ so that the current I S through the activating transistor 28 is reduced to the zero level as will be also seen from Fig. 6B. Fig. 7 shows a second preferred embodiment of a differential amplifier circuit according to the present invention. The differential amplifier circuit herein shown features first and second activating transistors 28 and 28' in lieu of the single activating transistor 28 provided in the embodiment described with reference to Fig. 5. These first and second activating transistors 28 and 28' are provided by n-channel MOS field-effect transistors and have their drains connected to the sources of the first and second amplifier transistors 24 and 26, their sources connected to ground line, and their gates commonly connected to a clock supply line 32 for an active-high clock signal Ø SE . The activating transistors 28 and 28' are operative to have the drains of the respectively associated amplifier transistors 24 and 26 connected to ground therethrough in response to the clock signal Ø SE of a certain high level.

Claims: A differential amplifier circuit having a stand-by mode of operation and an active mode of operation, comprising: First and second amplifier transistors (24, 26) of a first channel conductivity type; first and second load transistors (20, 22), the channels thereof being respectively coupled to drain nodes of said first and second amplifier transistors for supplying electric currents thereto, respectively; and first and second input lines (B, B') respectively coupled to the gate electrodes of said first and second amplifier transistors, both of said first and second input lines remaining in a first voltage level in said stand-by mode of operation, one of said first and second input lines being changed to a second voltage level in said active mode of operation, an output voltage level being produced at one of the drain nodes of said first and second amplifier transistors, characterized by first and second switching transistors (38, 40) of the second channel conductivity type opposite to said first channel conductivity type respectively coupled between a second constant voltage source (V DD ) and the channels of said first and second load transistors; first and second inverter circuits (42, 44) respectively coupled at input nodes thereof to said second and first input lines and at output nodes thereof to gate electrodes of said first and second switching transistors; an activating transistor (28) coupled between source nodes of said first and second amplifier transistors and a first constant voltage source (GND) and allowed to turn on in said active mode of operation; wherein the first and second load transistors are of a second channel conductivity type opposite to said first channel conductivity type, and wherein said first and second switching transistors turn on in said stand-by mode of operation and either first or second switching transistor turns off in said active mode of operation if said second or said first amplifier transistor turns on, respectively.

Inventors: KOBAYASHI, YASUO, YAMAGUCHI, TAKASHI
Applicants: NEC CORPORATION
Application year: 1986
Main classification: G11C7
IPC codes: G11C7