A METHOD OF PRODUCING ISOLATED SILICON STRUCTURES

Abstract: A method of producing isolated silicon structures by forming three layers in a wafer (1) of crystalline silicon, an outer layer of silicon having n-doped areas (2), a middle layer (5) of p-type silicon, and an inner layer which consists of areas of n-type silicon (6) interspersed with areas (7) of p-type silicon, the said two areas of n-type silicon being displaced relative to one another, then anodising the p-type silicon by passing a current across the wafer, and then oxidising the porous silicon to silicon dioxide which may then be either retained as an insulator or be dissolved to separate the n-type areas on the outer layer. The areas of n-type silicon (2) in the outer layer may take the form of parallel strips separated by narrower strips (4) of p-type silicon, and in this case the inner layer preferably consists of a similar pattern the centre lines of whose p-type strips are located beneath the mid-lines of the n-type strips (2) of the outer layer.

Description: A METHOD OF PRODUCING ISOLATED SILICON STRUCTURES This invention relates to the production of silicon-based devices and particularly, though not exclusively, to silicon on silicon dioxide structures which have applicability to silicon integrated circuits. These structures are not subject to latchup and since parasitic capacitances are reduced, they are desirable for high speed operation of devices. The invention can also be used to fabricate other devices, such as silicon on air structures. The invention makes use of a stage involving the formation by anodisation of a porous silicon layer, referred to by K Imai and H Unno (IEEE Trans, Electron Devices ED-31 No 3, March 1984 pp 297-302), although the results hitherto have produced non-flat under-surfaces and, following oxidation, very thick oxide layers of non-uniform density. Further results by other workers have also not been entirely satisfactory. This invention consists of a method of producing isolated silicon structures by forming three layers in a wafer of crystalline silicon, an outer layer of silicon having n-doped areas, a middle layer of p-type silicon; and an inner layer which consists of areas of n-type silicon interspersed with areas of p-type silicon the latter areas being displaced relative to the areas of p-type silicon in the outer layer; then anodising the p-type silicon by passing a current across the wafer; and then oxidising the porous silicon to silicon dioxide which may then be either retained as an insulator or dissolved to separate the n-type silicon areas on the outer layer. The areas of n-type silicon in the said outer layer may conveniently take the form of parallel strips separated by thinner parallel strips of p-type silicon; in this case the said inner layer may consist of similar parallel strips of n-type silicon interspersed with thin strips of p-type silicon located underneath the mid-lines of the n-type strips of the outer layer. With this arrangement, while the total anodising current is constant throughout the anodisation of the p-type silicon, the current density and therefore the porosity of the porous silicon will be constant. By way of example, the invention will now be described with reference to the drawings, of which Figures 1 to 4 are transverse cross sections of four alternative structures produced in accordance with the invention and illustrating their construction before anodisation, and Figures 5 and 6 are similar cross sections illustrating alternative forms which structures of this type may take after anodisation. The embodiment illustrated in Figure 1 comprises three principal layers on the surface of a p-doped silicon wafer 1. The outer layer contains a series of parallel n-doped stripes 2, each about 0.3 micron thick and typically 42 microns wide, and having a layer 3, about 1800A thick, of silicon nitride on its outer surface and being interspersed with p-doped "passages" 4. The middle layer 5, 0.7 micron thick, is of p-doped silicon whilst the inner layer in contact with the rest of the wafer consists of a series of stripes 6 of 0.9 micron thick n-doped silicon, all parallel to the stripes 2 and separated by passages 7 of p-doped silicon located beneath the centre lines of the stripes 2. The structure so formed is then anodised in hydrofluoric acid by passing a current from the outer surface through the SUBSTITUTE SHEET passages 4 and 7 and the layer 5 to the wafer, whereupon the p-doped regions are converted to porous silicon in which substantially less silicon occupies the same volume, and is thus in a form which can be converted readily into silicon dioxide which either fills the same volume again or can be dissolved away. The location of the passages 7, equidistant from the nearest two passages 4, results in an even current density throughout the material in the layer 5 during anodisation and therefore in an even density of porous silicon. The fabrication process is in several stages: 1. The production of the outer n-doped stripes 2, which are to remain after anodisation, together with features to which subsequent masks can be aligned. For this, a 300A oxide layer is grown on to a 25 ohm.cm p-type silicon wafer having a heavily doped contact layer, after which a further 3.000A chemical vapour deposited oxide layer is deposited. After coating with a layer of photoresist, exposing it and developing it, the oxide is etched with a buffered hydrofluoric acid solution using the resist mask and the resist is subsequently removed. Visible features for the alignment of subsequent masks are produced by etching 1.000A of silicon using a solution such as "poly etch". A further 300A oxide layer is grown, whereafter 10 1;i cm~ of phosphorus is implanted at 120keV into the front face. The oxide layer is then removed in hydrofluoric acid. 2. The boron concentration beneath this is enhanced, in order to prevent the central layer 5 from being depleted to the n layers above and below, and to ensure that the layer 5 remains p-type when the inner n layer 6 is produced. A heavily doped back contact to the wafer 1 is also made. In further detail, 10 iS cm~ of boron is then implanted at 50keV into the rear face to provide contact to the wafer, and 2 x 10 iJ cm~^ of boron is implanted at 185keV into the front face. This is annealed for 21 minutes at 1,050°C in argon and, SUBSTITUTE SHEET if desired, the assembly is dipped into hydrofluoric acid to remove any oxide still present. 3. The layer of silicon nitride 3 is deposited over the surface to prevent oxidisation when the porous silicon in the middle layer 5 is oxidised. The nitride is confined to the stripes 2 by the further deposition of a 1000A low temperature chemical vapour deposited oxide layer. After photolithography, the oxide is etched and the remaining resist is removed. The nitride is then etched in phosphoric acid using the oxide as a mask, and the oxide is then removed. The nitride layer prevents oxidation of the top surface of the top silicon layer when the anodised structure is oxidised, and can be omitted in variants of the process. 4. The inner n-doped layer 6 is produced by proton implantation following etching using a photo-resist at least 2 microns thick. 2 x 10 ι:? cm~ protons are then implanted at 200keV, the resist is removed and the assembly is annealed for 30 minutes in nitrogen at 450°C. The structure is now as illustrated in Figure 1, and is ready to be anodised, using a current density of 100mAcm"" z within the layer 5 and 40% hydrofluoric acid. The result of this Is the conversion of the buried boron-doped layer into a porous silicon layer having 45% of bulk density. The anodisation is continued until the porous layers have just reached the hole in the buried n layer - this can be seen by optical microscopy. The back contact is also made using 40% hydrofluoric acid. The assentoly so formed has a layer of about 0.3 micron of n silicon doped at 2 x l0 1 cm~ J on about 0.7 micron of porous silicon formed in material doped at about 2 x 10 i/ cm" *3 . The dopant concentration in the proton-implanted layer is about 10 lβ cm~ 3 and it is about 0.7 micron thick. With the figures given above, the dopant concentration in the top layer is rather high for making current devices unless they are very small, but by adjustment the dopant concentration in the top SUBSTITUTE SHEET layers may be reduced by a factor of about 5. Many variants in detail of the above process are possible,, but typically the windows 4 are 5 microns and the windows 7 are 10 microns wide. The embodiment illustrated in Figure 2 is similar in its final form, except that the regions around the passages 7 remain p-doped throughout the thickness. The fabrication is rather different, as follows, the same reference numerals being used as before: 1. A deep n diffusion is made into a p-type wafer 1. This is achieved by firstly growing a 300A thermal oxide on a 25 ohm.cm p-type wafer, then depositing 3,000A of thermal vapour deposited oxide. After photolithography, the oxide layer is etched using a resist masking layer, the resist is removed and the silicon is etched with poly etch to 500Δ to give an alignment pattern. A 300A oxide layer is then grown, and 2 x 10 1J cm~^ of phosphorus is implanted at 120keV. This is annealed in argon for 1 hour at 1,050°C and a dry oxide grown at 1150°C for 4 hours, whereafter the oxide layer is removed. This results in the upper surface of the wafer down to the layer 6 being n-doped. 2. Boron is implanted to make the p layer 5, and the back surface of the wafer 1 is implanted to make contact to the anodising solution. This is achieved by implanting 2 x 10 ia cm~ z of boron at 185keV into the front face of the wafer, then 10 13 cm~ i: of boron at 40keV into the rear face. 3. Optionally, to lessen the requirement for accurate control of the process, a shallow n layer can be implanted to ensure that the outer layer 2 is n-doped despite the presence of the buried p layer: this is done by implanting 10 i3 cm~^ of phosphorus at 120keV into the front face. 4. Silicon nitride is deposited on to the surface to protect the outer n-layer and to seal the p-doped areas above the passages 7, and boron is implanted into the passages 4 to make contact to the p layer. To this end, a 1,800A nitride layer is deposited, followed by a 1,000A chemical vapour SUBSTITUTE SHEET deposited silicon dioxide layer. After photolithography, the oxide is etched with a resist mask, the resist is removed and the nitride is etched in phosphoric acid using the remaining oxide as the mask. 2 x 10 1J cm~'^ of boron is implanted at 55keV to produce p-doped passages 4 through to the lower p layer, the wafer is annealed for 21 minutes at 1,050°C in argon and the oxide is removed. The wafer is now ready to be anodised as described in connection with the first embodiment. An alternative process for fabrication of the structure of Figure 2 consists of firstly patterning a 7,000A deposited layer of silicon dioxide by photolithography, plasma etching the oxide and removing the resist. A further 300A oxide layer is grown, then 2.5 x lO 1 ^ of phosphorus is implanted at lOOkeV to form the n-doped stripes 2. This is annealed for 1 hour at 1050°, oxidised in a dry ambient for 6 hours at 1150° and the oxide is'stripped. 10 13 cm~^ of boron is implanted at 40keV into the back face to form the back contact and 1.5 x 10 1 ^cm~^ of boron is implanted at 280keV into the front face to form the buried layer. The front islands are then doped by implantation of 3 x 10^cm""^ of phosphorus. A 1,000A nitride layer and a 1,500A polycrystalline silicon layer are deposited, and the front windows are defined by photolithography. The silicon is plasma etched using the resist mask and the nitride is etched in either hot phosphoric or hydrofluoric acid. 5 x 10 i4i cm~ z of boron is implanted into the front face at 80keV and, after annealing in argon for 21 minutes at 1050°, the structure can be anodised. The embodiment illustrated in Figure 3 makes use of epitaxial growth and is again fabricated in several stages: 1. 3,000A of silicon dioxide is deposited on a 25 ohm.cm p-type wafer and alignment features and the position of the buried n-type layer are added by photolithography. The oxide is etched using the resist as a mask, and the resist is then removed. The silicon is then etched with poly etch or a plasma etch to 1000A. At least 2.300A of oxide should be left at the end of the etching step. 2. 5 x 10 lii cm~ i ' of phosphorus is implanted at lOOkeV. The oxide masking layer is then removed, and the wafer is annealed in argon at 1050°C for 2 hours. In this way, the inner n-type layer 6 is defined. 3. 1.2 microns of p-type silicon is then deposited at about 2 x 10 lb cm~' 3 doping to produce the middle layer 5, and after photolithography, 2 x 10 1 ^cm~' i of phosphorus is implanted at 80keV to form the outer n-doped stripes 2. The resist is then removed. 4. 10 1 asT of boron is implanted at 50keV into the back face of the wafer 1 to make the back contact. The wafer is annealed in argon at 1050°C for 45 minutes- and may then be anodised as efore. As an alternative to stages 3 and 4, a 1.6 micron p-type silicon layer doped at 5 x 10 13 cm~ a is deposited, followed by 10 1D cm~^ of boron into the back surface. After photolithography,10^cm -3 protons are implanted at 50keV, the resist is stripped and the wafer is annealed at 450° in forming gas for 30 minutes. This fabrication method uses removable donors to form the n-type layer. The structure illustrated in Figure 4 is designed for producing comparatively thick layers of silicon on porous silicon, for example for applications in which the porous silicon layer is subsequently removed. The structure is constructed in a similar manner as before, as follows: 1. Alignment features are etched as before. 2. The buried n-doped layer 6 is produced by implanting and diffusing phosphorus, for example by implanting 5 x 10^-^cm^ phosphorus at lOOkeV after photolithography, removing the resist and growing a 300A oxide layer. This is followed by annealing in argon at 1,050°C for 1 hour and in dry oxygen at 1150°C for 4 hours, after which the oxide is removed. SUBSTi i ϋ fE SHEET 3. The buried p type layer Is produced by implanting 2 x 10 1J cm- of boron at 185keV and 2 x 10 id cm" a of boron at 60keV. This is annealed for 1 hours at 1050°C in argon. 4. A lightly doped n-type epitaxial layer 2 Is deposited, for example with a dopant concentration of 5 x 10 13 cm~ d and about 10 microns thick; devices may now be made in this layer if desired. 5. Implant 10 i3 cm'"' i of boron at 50keV into the rear face and anneal in argon at 1050°C for 20 minutes. 6. Grooves 8 are then etched through the top layer to the p layer. It is important that the grooves extend to the buried p layer 5 but do not penetrate through to the lower n layer 6. The grooves may be etched by one of 3 methods, as follows: a. By plasma etching b. By means of isotropic wet etches, eg poly etch or mixtures of nitric, hydrofluoric and acetic acids, or c By anisotropic chemical etching using etches such as aqueous potassium hydroxide or EDP which stop on the (111) planes. In this case, if the grooves are suitably oriented with regard to the crystal directions so that they run parallel to where the sloping (111) planes intersect the surface, the depth of the groove can be designed to depend only the size of the slot and to be virtually independent of the etching time. In further detail, the anisotropic chemical etching method consists of firstly growing a 2000A oxide layer, etching the oxide after photolithography, using the resulting resist mask, removing the resist and then etching using, for example, the EDP anisotropic etch. 7. Finally, the buried p layer 5 may be anodised. In order to get full isolation it is desirable to anodise for a little longer than it takes for the passages 7 in the lower n layer into the wafer to be made porous. The structures described above have many potential uses. Firstly, the porous silicon can be oxidised so that the silicon regions of the upper layer of the structure become mounted on an insulator formed from silicon dioxide. Thus the porous silicon can be oxidised, for example for 30 minutes at 950°C, using a steam oxidation process. An alternative oxidation process uses 1 hour at 300°C in dry oxygen followed by 2 hours at 800 β C in steam and then 45 minutes at 1090°C in steam. This will convert it all to oxide, even if the layer extends for 50 microns under the silicon. In this way, a structure has been fabricated in which 0.2 ± 0.01 micron of silicon with a nitride capping layer and an oxidised back interface rests on 0.8 ± 0.01 micron of oxide. The oxide may be chosen to be as similar as possible in density to bulk thermal oxide, but it is generally easier to choose it to be a little porous: this has the disadvantage that it is very vulnerable to chemical attack, and if the structure is likely to be exposed to etches which contain hydrofluoric acid during subsequent processing, then capping layers must be employed to protect it. In view of the increasing prevalence of plasma processing, this is not a serious constraint. The oxide in the passages 4 through which the current enters will be the only part of the oxidised porous silicon which will be in communication with plasma, and since the passages are generally wider than the thickness of the buried p type layer, the current density at these points is generally low, leading to a resilient high silicon density material there. This effect can be enhanced by employing a low current density early in the anodisation. Depending on how long the anodisation has taken, there may be some electrical contact to the wafer via unanodised material around the passages 7 through which current passes into the wafer. This can be avoided by anodising for a little longer than is necessary simply to reach the passages. The devices can be placed with all p channel devices in one strip of silicon, and all the n channel devices on another strip. Alternatively, or additionally, trench isolation or local oxidation can be used to isolate one device from another in the same silicon strip. SUECTΓΓ .JTF 10 It is believed that defect formation at the ends of the silicon layer can be avoided if the silicon layer is detached from the substrate before the 1090° oxidation stage (see above). Thus, starting with an anodised structure which has had the 300° and 800° oxidation stages, trench isolation is performed by depositing a 1,400A nitride layer in which islands are defined by photolithography. The nitride and exposed silicon layers are plasma etched, the 1090* oxidation stage is performed and the remaining nitride is removed. If local oxidation is preferred, the silicon is not removed after the nitride and the islands are separated during the steam oxidation stage. This is less good to the extent that stresses arise during the oxidation stage before the islands are completely separated. The silicon on oxidised porous silicon structure fabricated by the above procedures can be treated as a standard substrate on which devices can be made, rather like silicon on a sapphire base, and the num er of mask steps which are specific to any circuit is small, thereby keeping down design and assembly costs. The advantages of this approach are: 1. Devices are made in high quality single crystal silicon. 2. The process is applicable to any silicon orientation. 3. All the processes needed are readily available in any semi-conductor processing facility, with the exception of anodisation, which is fairly easy. 4. The materials and process steps are cheap. 5. The silicon and oxidised porous silicon are of uniform thickness across the structure, and can be tailored to need. 6. Nearly all the silicon area is available for device fabrication. 7. The oxide thickness need not be large. A second application for this construction is a device containing insulated silicon strips produced in the way illustrated in Figures 5 and 6. The top silicon layer must SUE 11 initially be thicker than in the processes described above and a high current density or dilute hydrofluoric acid is employed during anodisation, so that a low density porous silicon film is formed in place of the middle p-doped layer 5. This is then oxidised, for example at 800°C in steam, and the oxide dissolved in hydrofluoric acid to form cavities 9 (see Figure 6). Alternatively, the porous silicon can be dissolved directly by means of an etch which dissolves silicon slowly, 10 but porous silicon quickly on account of its high surface to volume ratio. An example of such an etch is a 48 hour immersion in 40% hydrofluoric acid. Following the removal of the porous silicon layer by either of the techniques described above, the wafer is oxidised 15. until the resulting hole is filled by oxide growing from the two faces (Figure 5), the oxidation also being used to achieve local oxidisation to isolate devices within the silicon layer. In this embodiment, it is better to perform the oxidation at a higher temperature, eg 1150°: under these conditions, the 20 viscosity of the oxide is lower so that the oxide growing from the two faces is more likely to merge without a detectable join. This approach has an advantage that the oxide is of high quality and that the porous silicon (an excellent getter for 25 heavy metal ions) is completely removed, thereby reducing contamination problems. The porous silicon in the hole through which the current enters can be made to have a higher density than the other porous silicon, so that it will remain after the rest of the porous silicon has been removed and so provide a 30 planarising layer 10. In these processes it is necessary for the nitride layer to be as thin and as strain-free as possible. It can be omitted completely, but this necessitates a thicker silicon layer since the top face of the outer silicon layer also 35 oxidises when oxide is being grown in the cavity left by the ~ removal of the porous silicon. A third application is for the silicon stripe to be insulated by an air layer. A thin oxide layer II is grown on the structure illustrated in Figure 6 to passivate the silicon surfaces. The chief advantage of this is in reduced capacitance between the devices set in the silicon strips and the wafer 1, but the depth of under cut is limited (typically up to about 10 microns for a 0.3 micron layer) if the structure is not to become too fragile. Another application is for Cantilever beams for accelero eters. The construction of these is the same as that described with reference to Figure 3, with plasma etching or local oxidation followed by a wet etching with hydrofluoric acid to dissolve the silicon dioxide. Cantilever beams formed in this way have the merit over beams defined by a p++ etch stop layer, in that they are not heavily doped and can incorporate active devices and piezo resistors. Furthermore, capacltative pick up can be achieved between the beam and the substrate. The upper nitride layer may be dispensed with if the stress it produces leads to an unacceptable bending of the unsupported beams. A further application is for the formation of buried epitaxial layers. The porous silicon can be partly or completely oxidised and, optionally, removed to form the structure illustrated in Figure 6. Vapour phase diffusion can then be performed, using for example P0Cl d , borane or ceramic diffusion discs. The silicon is protected on its top surface only by a nitride layer, and a diffusion therefore enters the structure from underneath with a high dopant density close to the bottom of the top silicon layer and a diminishing concentration higher up. This may, if desired, be followed by oxidiation to fill the central region. The attraction of this approach is that it can produce buried dopant profiles which can only be produced otherwise by well controlled expltaxial processes, even if within any slit 13 the whole surface is diffused and the process is rather involved simply to produce a buried dopant layer. The process may also be deployed to produce small thin silicon chips and bars. Such chips (eg 100 microns x 200 microns) and bars (eg 100 microns x 10 cm) are required for applications such as the display device described in UK Patent Application No 8402654. The chips may be made by using the process of Figure 4 followed by removal of the porous silicon layer, either directly or after oxidising it, in order to free the silicon from the substrate. The chips may also be useful as components of chip stacks (3D integrated circuits formed by stacking a number of processed chips on top of one another). Thinner, small chips may be required for applications such as that described in UK Patent Application No 8422867. Such structures can be produced by using the structures described with reference to Figures 1-4, with trenches cut through the silicon sheet by plasma etching, or with the sheet divided up by local oxidation. The structures can be removed from the substrate by dissolving the porous silicon layer, either directly or by oxidising the porous layer and dissolving the oxide in hydrofluoric acid. SUB " ;

Claims: CLAIMS 1. A method of producing isolated silicon structures characterised by forming three layers in a wafer 1 of crystalline silicon; an outer layer of silicon having n-type areas 2; a middle layer 5 of p-type silicon; and an inner layer which consists of areas of n-type silicon 6 interspersed with areas of p-type silicon 7, the said two areas of n-type silicon being relatively displaced; then anodising the p-type silicon by passing an electric current across the wafer; and then oxidising the porous silicon so formed to silicon dioxide which may then be either retained as an insulator or dissolved to separate the n-type areas on the outer layer. 2. A method according to Claim 1 characterised in that the areas of n-type silicon 2 in the outer layer are arranged to take the form of parallel strips separated by narrower parallel strips 4 of p-type silicon. 3 A method according to Claim 2 characterised in that the inner layer is arranged to consist of similar parallel strips of n-type silicon interspersed with thin strips of p-type silicon located underneath the mid-lines of the n-type strips of the outer layer. 4. A method according to Claim 2 or Claim 3 characterised in that the anodising is carried out with the p-type strips 4 in the outer layer In contact with hydrofluoric acid. 5. A method according to any preceding claim characterised in that doping of the p-type middle layer and areas is enhanced by boron implantation. 6. A method according to any preceding claim characterised in that the n-type areas 2 of the outer layer are produced by forming a layer of silicon dioxide over the outside of the wafer; removing the silicon dioxide by photolithography from the intended location of the said areas 2; implanting phosphorus ions into the front face of the wafer at energies corresponding to the required depth; and then removing the remaining silicon dioxide. 15 7. A method according to any preceding claim characterised in that the inner n-type areas 6 are produced by proton implantation following production by photolithography of a photo-resist mask corresponding to the p-type areas 7. 8. A method according to any of Claims 1 to 4 characterised in that all three layers in the wafer 1 are firstly n-doped by phosphorus ion implantation prior to production of the middle p-type layer 5 by boron ion implantation. 9. A method according to any of Claims 1 to 4 characterised in that firstly the n-type areas 6 are formed by photolithography and phosphorus ion implantation, secondly the' middle and outer layers 5 and 2 are formed by epitaxial growth, and thirdly the outer n-type areas 2 are formed by photolithography and implantation. 10. A method according to Claim 9 characterised in that the outer n-type areas 2 are formed using proton implantation, said areas being produced by removable donors. 11. A method according to any preceding claim characterised in that electronic devices are made in the n-type areas 2 before the p-type silicon is anodised. 12. A method according to Claim 1 characterised in that the outer n-type areas 2 are separated from one another by photolithography and etching. 13. A method according to Claim 12 characterised by the use of an anisotropic etching process. 14. A method according to any of Claims 2 to 11 characterised in that all the p-type areas within the three layers are removed by anodising and oxidation except for portions along the outer p-type strips 4 which remain to form a planarising layer 10. 15. A method according to any preceding claim in which all the silicon dioxide is removed and the resulting cavities 9 are filled with silicon having a controlled dopant density using vapour phase deposition.

Inventors: BENJAMIN JOHN DAVID, KEEN JOHN MICHAEL, BENJAMIN, JOHN, DAVID, KEEN, JOHN, MICHAEL
Applicants: SECR DEFENCE BRIT, THE SECRETARY OF STATE FOR DEFENCE IN HER BRITANNI
Application year: 1986
Main classification: H01L21
IPC codes: H01L21