Power-on reset circuit arrangements

Abstract: An integrated-circuit power-on reset arrangement which starts in a known state due to transistor sizing and to a current mirror circuit (11, 12, 13) at least initially holding a bistable circuit (1, 2, 3, 4) in a predetermined one of its states.

Description: The present invention relates to power-on reset circuits. In particular but not exclusively the invention is concerned with power-on reset circuit arrangements for use in CMOS integrated circuits. The purpose of a power-on reset circuit is to initialise logic and memory elements as the power supply voltage is raised from a very low level, that is, to set such elements to a known initial state. To do this the reset circuit must itself start in a known state. Reset circuits are used for example in calculators and electronic telephone sets. The voltage at which a reset circuit is required to operate is a function of the operating voltage range of the associated circuits. If the reset circuit operates at too high a voltage, then logic and memory elements may be reset while still being supplied with a usable voltage, and in many applications the lower the voltage at which the reset circuit operates the longer the memory elements will retain stored information. Reset circuits fall broadly within two categories, those in which the power supply voltage increases rapidly so that capacitors may be used to determine the reset state, and those in which the supply voltage increases or decreases slowly so that some form of level-detector circuit is required. Circuits designed for slowly changing supply voltages can usually be modified fairly readily, by the addition of capacitors, to deal also with rapidly changing supply voltages. In some known reset circuits for dealing with slowly changing supply voltages the detection voltage level is determined by the sum of n and p channel transistor threshold voltages, plus an additional margin which may include the threshold voltage of a diode in series with the transistors. Such reset circuits are commonly referred to as sum-of-threshold circuits. However, memory elements will usually hold down to supply voltage of less than half of this sum-of-threshold voltage, so that such reset circuits tend to operate at too high a voltage. GB 2109652A discloses a power-on reset circuit, termed a memory circuit, comprising a bistable circuit and a state-setting transistor controlled by the output of a power supply voltage detection circuit, both the bistable circuit and the detection circuit utilising depletion-type transistors which are not available in standard CMOS technology. The present invention relates to a CMOS integrated-circuit power-on reset circuit arrangement comprising a pair of p-channel transistors and a pair of n-channel transistors which are cross-connected to form a bistable circuit, and a current mirror circuit arranged to provide a conductive path through a transistor effectively in parallel with one of the transistors of the bistable circuit between an output of said bistable circuit and one supply voltage conductor of the circuit arrangement, the arrangement being such that as the supply voltage rises from substantially zero value, initially leakage currents in transistors between the output and said one supply voltage conductor, and subsequently the value of current flow in the transistor which provides said current path when said current mirror circuit becomes operative, are sufficient to maintain the potential of said output of the bistable circuit substantially at the potential of said one supply voltage conductor at least until the value of said supply voltage exceeds a predetermined value. A power-on reset circuit arrangement in accordance with the present invention will now be described by way of example with reference to the accompanying drawing, which shows the circuit arrangement diagrammatically. Referring to the drawing the reset circuit comprises transistors 1 to 4 and diodes 5 and 6, which are connected to form a bistable circuit which is arranged to be energised by way of supply voltage conductors 7 and 8. The bistable circuit has a first stable state, in operation, in which a junction or node 9 is high, that is at a voltage close to that of the positive supply conductor 7, and a junction or node 10 is low, that is at a voltage close to that of the zero voltage supply conductor 8, and a second stable state in which the node 9 is low and the node 10 is high. The channels of the p-channel transistors 1 and 2 are of the same length, but the channel of transistor 1 is much wider than that of transistor 2, as indicated by the channel measurements in micrometres shown in the drawing. Thus, as indicated, the channel of transistor 1 is forty micrometres wide and eight micrometres long. Also, in respect of the channels of the n-channel transistors 3 and 4 that of the transistor 4 is much wider than that of the transistor 3. Due to these inequalities if the supply voltage between the conductors 7 and 8 rises slowly from zero the imbalance in transistor gains and leakage currents assist in forcing the bistable circuit to the first of the above-mentioned stable state, in which the node 9 is high and the node 10 is low. Two further n-channel transistors 11 and 12 form a current mirror circuit whose function is to draw a current I₂ closely equal to a current I₃ the value of which is determined by a p-channel transistor 13, the transistor 13 being a low-current low-gain device. At values of supply voltage below the sum of the threshold voltages of the transistor 2 and the diode 6, but at voltages above those at which leakage currents dominate, the value of current I₂ is greater than the value of current I₁ then flowing through the transistor 2 and the diode 6, and the node 10 is thereby held low. Thus as the supply voltage rises slowly from zero, initially the leakage currents in the transistors 1 to 4 tend to set the bistable circuit to the state in which node 10 is low. At slightly higher supply voltages the current mirror circuit tends to hold the node 10 low. When the supply voltage exceeds the sum of thresholds of the transistor 2 and the diode 6 by some margin the state of the bistable circuit itself determines whether the node 10 is low or high. An output from the node 10, for example by way of inverters 14 and 15, may be used as a reset signal, which reset signal may be removed by setting the bistable circuit to the state in which the node 10 is high, say by a suitable logic input at the node 9. The logic input is applied by means of a transistor 16 which, if conducting, will remove the reset signal when the supply voltage exceeds the sum of thresholds value referred to in the preceding paragraph. Since the threshold voltage of the transistor 2 is of the order of one volt and the threshold voltage of the diode 6 is of the order of half a volt, the value of supply voltage at which the bistable circuit will change over is of the order of one and a half volts. By comparison a known sum of thresholds reset circuit operates at supply voltages more than two volts, and with additional series diodes would operate at more than two and a half volts. The input to remove the reset condition may be an event, such as the operation of a push-button on a calculator or a telephone keypad. Alternatively the present reset circuit may be combined, as shown in the drawing, with a conventional sum of threshold circuit comprising transistors 17 to 20, which may be designed so that its output to the transistor 16 changes at supply voltages of two and a half volts between the conductors 7 and 8. With the input to transistor 17 connected to the supply conductor 8 the output from the combined circuit arrangement would hold the reset condition until the supply voltage rises above two and a half volts, but would not provide the reset on falling supply voltage until this is below one and half volts. In other words the arrangement provides hysteresis. If the input to transistor 17 is an event, as referred to above, then removal of reset by the event will be permitted if the supply voltage is above two and a half volts, but again the reset will not be provided until the supply voltage has fallen below one and a half volts. If the input to the transistor 17 is taken from the output of the inverter 15 the operation is similar to that with the input to the transistor 17 connected to the zero volt conductor 8, except that once the reset has been removed by a rising supply voltage the transistor 17 is switched off and the transistors 18, 19 and 20 draw virtually no current until the supply voltage has fallen below one and a half volts arid the reset condition has been reestablished. This minimises current consumption of the circuit arrangement in the critical range of low but viable supply voltages. Capacitors 21 and 22 serve to ensure that the circuit arrangement starts in the reset state if the supply voltage rises rapidly from zero.

Claims: A CMOS integrated-circuit power-on reset circuit arrangement comprising a pair of p-channel transistors (1, 2) and a pair of n-channel transistors (3, 4) which are cross-connected to form a bistable circuit (1, 2, 3, 4), and a current mirror circuit (11, 12, 13) arranged to provide a conductive path through a transistor (11) effectively in parallel with one of the transistors (4) of the bistable circuit between an output (10) of said bistable circuit and one supply voltage conductor (8) of the circuit arrangement, the arrangement being such that as the supply voltage rises from substantially zero value, initially leakage currents in transistors (4, 11) between the output (10) and said one supply voltage conductor (8), and subsequently the value of current flow in the transistor (11) which provides said current path when said current mirror circuit (11, 12, 13) becomes operative, are sufficient to maintain the potential of said output (10) of the bistable circuit substantially at the potential of said one supply voltage conductor (8) at least until the value of said supply voltage exceeds a predetermined value. A CMOS integrated-circuit power-on reset circuit arrangement in accordance with Claim 1 characterized in that the channel width of said one of the transistors (4) of the bistable circuit is greater than that of the other transistor (3) of the same conductivity-type in the bistable circuit.

Inventors: JONES KEITH LLOYD, JONES, KEITH LLOYD
Applicants: PLESSEY SEMICONDUCTORS LTD, PLESSEY SEMICONDUCTORS LIMITED
Application year: 1986
Main classification: H03K3
IPC codes: H03K17, H03K3