Circuit arrangement capable of centralizing control of a switching network

Abstract: In a circuit arrangement (50) for use in accessing selected addresses numbered with a preselected distance left between two adjacent ones of said selected addresses, a control circuit (56) centralizes control operation of a switching network (55) with reference to a reference one of the selected addresses and the preselected distance to make the switching network form internal paths between input and output port sets of the switching network. Alternatively, when ports of a selected one of the input and output port sets are accessed at a predetermin­ ed port interval, the control circuit controls the switching net­ work with reference to the predetermined port interval and a reference port selected from the selected port set. A leading port of the other set is determined to be connected to the reference port. A rearranging circuit may be connected to one of the input and output port sets to rearrange an order of the ports of the one port set in consideration of the port distance. The reference and leading ports may be varied in a time division fashion when a conflict of internal paths otherwise occurs in relation to the port distance.

Description: This invention relates to a circuit arrangement for use in distributing a plurality of input signals to a plurality of memory addresses, a plurality of array processors, or the like. Various attempts have been made to connect a plurality of transmission ends to a plurality of reception ends. In an information processing system comprising a central processing unit and a memory, a plurality of memory addresses of the memory are often accessed by the central processing unit so as to distribute a plurality of parallel data signals, such as vector data signals, from the central processing unit to the memory. A similar operation is also carried out in a data processing system comprising a plurality of processing array elements and a control computer for controlling all of the processing array elements. Specifically, a plurality of transmission signals may be transmitted in parallel from the control computer to selected ones of the processing array elements. Under the circumstances, a circuit arrangement or switching network must be placed between the transmission and the reception ends, such as the central processing unit, the memory, the control computer, the array elements, to form a connection path or paths therebetween. In an article contributed by D. H. Lawrie to IEEE Transactions on Computers, Vol. C-24, No. 12 (December 1975), pages 1145-1155, and titled "Access and Alignment of Data in an Array Processor," a switching network is described which comprises a plurality of consecutively numbered input ports connected to the transmission ends, a plurality of consecutively numbered output ports connected to the reception ends, and a plurality of switching elements between the input and the output ports. The switching elements are divided into a plurality of stages which are interconnected in a perfect shuffle connection manner. With this structure, each input port can selectively be connected to all of the output ports through internal paths. In order to selectively form the internal paths in the switching network, an input port number and an output port number are indicated by the transmission end to control the switching network each time when each input signal is transmitted from the transmission end to destined reception end or ends. In this event, each of the switching elements in question must calculate the input port number and the output port number in accordance with a predetermined algorithm to select a following one of the internal paths. Such operation is successively carried out in each stage for connection between input and output port indicated by the input and the output port numbers. In addition, each switching element must detect or monitor whether or not a conflict of the internal paths occurs on selection of the internal paths. This means that a complexed control circuit is indispensable to every one of the switching elements included in the switching network. This results in an increase of hardware in the switching network. Thus, control operation is decentralized or distributed to the respective switching elements. The decentralization of control operation may reduce performance of the switching network when a plurality of input signals must simultaneously be distributed to the corresponding output ports, as are the cases with the vector data signals. In the document IEEE TRANSACTIONS ON COMPUTERS, vol. C-24, no. 12, December 1975, pages 1145 - 1155 ; D.H. Lawrie : "Access and alignment of data in an array processor" the properties and constraints (e.g. conflicts) of a variety of omege networks are disclosed. It is therein mentioned that such networks can be used to connect a plurality of processors to a plurality of memory units. It is an object of this invention to provide a circuit arrangement which can reduce the amount of hardware necessary for its implementation. This object is solved by the arrangement as set out in the claims. The circuit arrangement of the type described, can dispense with complex switching elements, is suitable for simultaneous distribution of a plurality of parallel input signals, such as vector data signals, and can rapidly distribute the parallel input signals to destined output ports. A circuit arrangement to which this invention is applicable is for use in combination with a plurality of units each of which is assigned with at least one of addresses consecutively numbered among the units and is for accessing a selected ones of the addresses at a preselected distance with reference to a reference one of the addresses. The circuit arrangement comprises a control circuit for producing a group of control signals in consideration of the preselected distance and the reference address and path setting means coupled to the control circuit for setting up internal paths to access the selected ones of the addresses. A circuit arrangement as described comprises a switching network which has a set of consecutively numbered input ports and a set of consecutively numbered output ports each of which is connectible to every one of the input ports through internal paths formed in the switching network. The ports of a selected one of the input and the output port sets include a reference port and are connected from the reference port at a predetermined port interval to the ports of the other set which are arranged in numerical order. The arrangement comprises a control circuit coupled to the switching network for delivering a group of control signals to the switching network with reference to the reference port and the predetermined port interval to make the switching network connect the ports of the selected set to the ports of the other set from the reference port at the predetermined port interval. Brief Description of the Drawing: Fig. 1 shows a block diagram of a circuit arrangement according to a first embodiment of this invention together with a central processing unit and a memory; Fig. 2 shows a chart for use in describing an address allocation of the memory illustrated in Fig. 1; Fig. 3 shows a chart for use in describing operation of the circuit arrangement illustrated in Fig. 1; Fig. 4 shows a circuit diagram for use in describing a switch unit included in the circuit arrangement; Fig. 5 is a block diagram of a control circuit included in the circuit arrangement illustrated in Fig. 1; Fig. 6 is a chart for use in describing control signals produced by the control circuit; Fig. 7 is a chart for use in describing the control signals more in detail; Fig. 8 is a circuit diagram for use in describing a part of the control circuit illustrated in Fig. 5; Fig. 9 is a circuit diagram of another part of the control circuit illustrated in Fig. 5; Fig. 10 is a circuit diagram of a further part of the control circuit; Fig. 11 is a diagrammatical view for use in describing operation of the circuit arrangement on a certain condition; Fig. 12 is a similar view for use in describing operation of the circuit arrangement on another condition; Fig. 13 is a similar view for use in describing operation of the circuit arrangement on a further condition; Fig. 14 is a block diagram of a control circuit according to a modification of this invention; Fig. 15 is a block diagram for use in describing connections according to the control circuit illustrated in Fig. 14; Fig. 16 is a block diagram of a circuit arrangement according to a second embodiment of this invention; Fig. 17 is a block diagram for use in describing operation of a circuit element of the circuit arrangement illustrated in Fig. 16; Fig. 18 is a circuit diagram of the circuit element illustrated in Fig. 17; Fig. 19 is a chart for use in describing operation of the circuit arrangement illustrated in Fig. 16; Fig. 20 is a block diagram for use in describing operation of the circuit arrangement illustrated in Fig. 16; Fig. 21 is a block diagram for use in describing an objectionable conflict of internal paths occurring in a switching network on a predetermined condition; Fig. 22 is a block diagram for use in describing that operation of the circuit arrangement illustrated in Fig. 16 which is carried out on the predetermined condition; Fig. 23 is a block diagram of a circuit arrangement according to a third embodiment of this invention; Fig. 24 is a chart for use in describing control signals produced in a control circuit of the circuit arrangement illustrated in Fig. 23; Fig. 25 is a block diagram for use in describing internal paths formed in the circuit arrangement illustrated in Fig. 23 on a preselected condition; Fig. 26 is a block diagram for use in describing internal paths formed on another condition; Fig. 27 is a block diagram of a circuit arrangement according to a fourth embodiment of this invention; Fig. 28 is a block diagram of a control circuit for use in the circuit arrangement illustrated in Fig. 27; Fig. 29 is a chart for use in describing operation of a part of the control circuit illustrated in Fig. 28; Fig. 30 is a block diagram for use in describing operation of the circuit arrangement which is carried out on a prescribed condition; Fig. 31 is a block diagram for use in describing operation of the circuit arrangement which is carried out on another condition; Fig. 32 is a block diagram of a circuit arrangement according to a fifth embodiment of this invention; Fig. 33 is a block diagram of a control circuit for use in the circuit arrangement illustrated in Fig. 32; Fig. 34 is a block diagram for use in describing operation of the circuit arrangement which is carried out on a certain condition; Fig. 35 is a block diagram for use in describing internal paths formed in the circuit arrangement during a first machine cycle; Fig. 36 is a block diagram for use in describing internal paths formed in the circuit arrangement during a second machine cycle; Fig. 37 is a block diagram for use in describing internal paths formed in the circuit arrangement during a third machine cycle; Fig. 38 is a block diagram of a circuit arrangement according to a sixth embodiment of this invention; Fig. 39 is a block diagram of a control circuit for use in the circuit arrangement illustrated in Fig. 38; Fig. 40 is a block diagram for use in describing operation of the circuit arrangement which is carried out on a certain condition; Fig. 41 is a block diagram for use in describing operation of the circuit arrangement that is carried out during a first machine cycle on a specific condition; Fig. 42 is a block diagram for use in describing operation carried out in the circuit arrangement during a second machine cycle; and Fig. 43 is a block diagram for use in describing operation carried out during a third machine cycle. Description of the Preferred Embodiments: Referring to Fig. 1, a circuit arrangement 50 according to a first embodiment of this invention is interposed between a central processing unit 51 and a memory 52. In the example being illustrated, it is assumed that the central processing unit 51 delivers a plurality of parallel data signals, such as vector signals, to the memory 52 through the circuit arrangement 50. The parallel data signals are to be stored in those addresses of the memory 52 which are specified by address signals included in the parallel data signals, respectively. As to the vector signals, a leading one B of the addresses is indicated to store a leading one of the vector signals. The remaining vector signals are successively stored in the memory 52 from the leading address at a predetermined address distance. Thus, it is possible to store the vector signals in the memory 52 by indicating the leading address B and the address distance. The illustrated memory 52 has first through eighth memory units 52-1 to 52-8 which are classified into a first group of the first through fourth memory units 52-1 to 52-4 and a second group of the fifth through eighth memory units 52-5 to 52-8. The first and second groups are selectively put into an accessible state. For this purpose, the central processing unit 51 produces a group indication signal GI of two bits representative of accessible group or groups of the memory units. In other words, the group indication signal GI is indicative of structure or formation of the memory 52 and may be called a structure signal. Anyway, the group indication signal GI is specified by a binary representation of (11)₂, namely, a decimal notation of (2)₁₀ when both the first and second groups are accessible. When only the first group is accessible and the second group is not accessible, two bits of the group indication signal GI take (10)₂. Likewise, the group indication signal GI is represented by (01)₂ when the second group alone is accessible. Temporarily referring to Fig. 2 together with Fig. 1, allotment of addresses to the memory units 52-1 to 52-8 is varied with reference to the group indication signal GI. More particularly, when the group indication signal GI takes (11)₂ to put all of the memory units 52-1 to 52-8 into the accessible state, the first through eighth memory units are successively and recurrently assigned with address numbers in an ascending order from zero one by one, as illustrated in Fig. 2(A). As a result, each memory unit is assigned with integral multiples of eight as the address numbers. When the group indication signal GI takes (10)₂ to put the first through fourth memory units 52-1 to 52-4 into the accessible state, the address numbers are allotted to the first through fourth memory units 52-1 to 52-4, as shown in Fig. 2(B). Consequently, each memory unit has integral multiples of four as the address numbers. Likewise, the fifth through eighth memory units 52-5 to 52-8 become accessible when the group indication signal GI takes (01)₂, as shown in Fig. 2(C), with the address numbers counted up by four for each memory unit. On delivery of the vector signals, the central processing unit 51 illustrated in Fig. 1 can simultaneously access at maximum eight addresses placed at an invariable address number, namely, the predetermined address distance by the use of the address signals representative of the address numbers, as described before. An address distance signal D is produced by the central processing unit 51 to specify the address distance together with the group indication signal GI. Thus, the central processing unit 51 is operable to produce the address signals, the address distance signal D, and the group indication signal GI which can be produced in a usual manner in the central processing unit 51. However, they are not usually used for connections of the circuit arrangement 50. In the example, the address distance D may usually be smaller than eight, as will become clear as the description proceeds, and can be specified by three lower bits (d₀d₁d₂)₂ which are successively arranged from the most significant bit d₀. Without loss of generality, it may be presumed that first through eighth ones of the address signals are produced by the central processing unit 51 to specify first through eighth ones of the addresses for memorizing first through eighth vector signals or elements, respectively. The first address signal may be called the leading or beginning address signal B (the same reference letter being used) and is sent from the central processing unit 51 through a first line 51-1. The second through eighth address signals are sent through second through eighth lines 51-2 to 51-8, respectively. Inasmuch as the first through eighth memory units 52-1 to 52-8 can be specified by three bits, each of the first through eighth address signals may be considered as a three-bit signal. For convenience of description, three bits of the first address signal B are represented by three bits (b₀b₁b₂)₂ successively arranged from the most significant bit b₀ to the least significant bit b₂. In Fig. 1, the circuit arrangement 50 comprises a switching network 55 and a control circuit 56 for controlling the switching network 55 in cooperation with the central processing unit 51 in a manner to be described later. The switching network 55 has first through eighth input ports 11 to 18 connected to the first through eighth lines 51-1 to 51-8, respectively, and first through eighth output ports O1 to O8 connected to the first through eighth memory units 52-1 to 52-8. The switching network 55 comprises first through twelfth switch units which are depicted at SW₁ to SW₁₂ and which are divided into first through third stages. The first stage consists of the first through fourth switch units SW₁ to SW₄ while the second and the third stages consist of the fifth through eighth switch units SW₅ to SW₈ and of the ninth through twelfth switch units SW₉ to SW₁₂, respectively. The first through twelfth switch units SW₁ to SW₁₂ are connected to one another so that each input port can be connected to all of the output ports O1 to O8 through internal paths formed by the switch units. Such a connection is referred to in the art as a perfect shuffle connection. More particularly, each switch unit SW (suffix omitted) has two input paths and two output paths (depicted at OP). The input paths of the first switch unit SW₁ are connected to the first and second input ports I1 and I2. Likewise, the input paths of the second through fourth switch units SW₂ to SW₄ are connected to the third through eighth input ports I3 to I8 in pairs. The output paths of the first switch unit SW₁ are connected to the one input path of the fifth switch unit SW₅ on the one hand and to the one input path of the seventh switch unit SW₇ on the other hand. The output paths of the second switch unit SW₂ are connected to the other input path of the fifth switch unit SW₅ on the one hand and to the other input path of the seventh switch unit SW₇ on the other hand. The output paths of the third switch unit SW₃ are connected to the input paths of the sixth and the eighth switch units SW₆ and SW₈ in a similar manner. Likewise, the output paths of the fourth switch unit SW₄ are individually connected to the input paths of the sixth and the eighth switch units SW₆ and SW₈, respectively. Interconnections between the fifth through eighth switch units SW₅ to SW₈ and the ninth through twelfth switch units SW₉ to SW₁₂ are similar to those between the first through fourth switch units SW₁ to SW₄ and the fifth through eighth switch units SW₅ to SW₈. Specifically, the output paths of the fifth and the sixth switch units SW₅ and SW₆ are connected to the ninth and the eleventh switch units SW₉ and SW₁₁ while the output paths of the seventh and the eighth switch units SW₇ and SW₈ are connected to the tenth and the twelfth switch units SW₁₀ and SW₁₂, as shown in Fig. 1. In addition, the output paths of the ninth switch unit SW₉ are connected to the first output port O1 on the one hand and to the fifth output port O5 on the other hand. The output paths of the tenth switch unit SW₁₀ are connected to the second output port O2 on the one hand and to the sixth output port O6 on the other hand. Likewise, the output paths of the eleventh switch unit SW₁₁ are connected to the third and the seventh output ports O3 and O7, respectively. The output paths of the twelfth switch unit SW₁₂ are connected to the fourth and the eighth output ports O4 and O8, respectively. Anyway, the switching network 55 serves to set up internal paths between the input and the output ports I₁ to I₈ and O₁ to O₈ and may be referred to as a path setting circuit. Referring to Fig. 3 in addition to Fig. 1, the first through twelfth switch units SW₁ to SW₁₂ are controlled by first through twelfth control signals S₁ to S₁₂, respectively, which are collectively shown at S i in Fig. 1. Each of the first through twelfth control signals S₁ to S₁₂ is a single bit signal and takes a logic "1" or a logic "0" level to connect each input path thereof to either one of the output paths in a manner shown in Fig. 3. In short, the two input paths are connected straightforward to the two output paths in each switch unit when the control signal S i takes the logic "0" level. The connection may be called a straight connection. On the other hand, the two input paths are exchanged by each switch unit to be connected crosswise or diagonally to the output paths when the control signal S i takes the logic "1" level. This connection may be called a crossed connection. More particularly, each of the output path pairs OP-1 to OP-8 of the first through fourth switch units SW₁ to SW₄ can collectively be represented by OP-{(i - 1) x 2 + 1} and OP-{(i - 1) x 2 + 2}, as shown in Fig. 3(A). The output path pairs are connected to the input ports which are collectively represented by I-{(i - 1) x 2 + 1} and I-{(i - 1) x 2 + 2} when the control signal S i takes thee logic "0" level, where i = 1, 2, 3, or 4. Otherwise, each of the output path pairs is switched to I-{(i - 1) x 2 + 2} and I-{(i - 1) x 2 + 1}. Likewise, the output path pairs of the fifth and the sixth switch units SW₅ and SW₆ can be represented by OP-{(i - 5) x 2 + 9} and OP-{(i - 5) x 2 + 10} and are connected to the output paths represented by OP-{(i - 5) x 4 + 1} and OP-{(i - 5) x 4 + 3} when the control signal S i takes the logic "0" level, where i is equal to 5 or 6, as shown in Fig. 3(B). Otherwise, inner connections of the fifth and sixth switch units SW₅ and SW₆ are switched from one to another, as indicated at OP-{(i - 5) x 4 + 3} and OP-{(i - 5) x 4 + 1} in Fig. 3(B). As illustrated in Fig. 3(C), the output path pairs of the seventh and the eighth switch units SW₇ and SW₈ can collectively be represented by OP-{(i - 5) x 2 + 9} and OP-{(i - 5) x 2 + 10}, where i is equal to 7 or 8. When the control signal S i takes the logic "0" level, the above-mentioned output paths are connected to OP-{(i - 7) x 4 + 2} and OP-{(i - 7) x 4 + 4} and are otherwise switched to OP-{(i - 7) x 4 + 4} and OP-{(i - 7) x 4 + 2}. The output ports connected to the ninth and the tenth switch units SW₉ and SW₁₀ can be represented by O-(i - 8) and O-(i - 4) and are changeably connected to OP-{(i - 9) x 4 + 2} and OP-{(i - 9) x 4 + 11} in accordance with the control signal S i , where i is equal to 9 or 10, as illustrated in Fig. 3(D). Similarly, the output ports connected to the eleventh and twelfth switch units SW₁₁ and SW₁₂ can be represented by O-(i - 8) and O-(i - 4), where i is equal to 11 or 12, and are selectively connected to OP-{(i - 9) x 4 + 2} and OP-{(i - 9) x 4 + 4}, as illustrated in Fig. 3(E). Referring to Fig. 4, each of the first through twelfth switch units SW₁ to SW₁₂ is supplied with first and second switch input signals I1 and I2 together with the control signal S i and produces first and second switch output signals O₁ and O₂. The illustrated switch unit comprises a control gate 61, two pairs 62 and 63 of AND gates, and two OR gates 64 and 65. As readily understood from Fig. 4, the first and second switch input signals I₁ and I₂ are produced as the first and second switch output signals O₁ and O₂, respectively, when the control signal S i takes the logic "0" level. Otherwise, the first and second switch input signals I₁ and I₂ are produced as the second and first switch output signals O₂ and O₁, respectively. Thus, the switch unit carries out switching operation in response to the control signal S i and comprises no control circuit therein. Therefore, the illustrated switch circuit is very simple in structure. Referring to Fig. 5 afresh and Fig. 1 again, the control circuit 56 is operable in response to the group indication signal GI of two bits, the leading or first address signal B of three bits, and the address distance signal D of three bits. The address distance signal D is delivered to first, second, and third decoders 71, 72, and 73 while the first address signal B is delivered to a shift number calculator 74 for calculating a shift number determined by the leading or first address for the first one of the vector signals and by the group indication signal GI. This is because a sequence of addresses for the vector signals is arranged at each address distance represented by the address distance signal and is shifted in the memory 52 by the first address B, as will become clear later. For example, when the first address B specifies an address included in the first memory unit 52-1, no shift is necessary. Therefore, the shift number may be equal to zero. Likewise, when the first address B specifies an address included in the second through eighth memory units 52-2 to 52-8, the shift number is equal to 1, 2, ... or 7. The shift number is delivered as first, second, and third shift signals SH₁, SH₂, and SH₃, respectively. Specifically, the first shift signal SH₁ is equal to b₂ while the second and third shift signals SH₂ and SH₃ are equal to b₁b₂ and b₀b₁b₂, respectively. Referring to Figs. 6 and 7 afresh and Fig. 5 again, the first through third decoders 71 to 73 produce first, second, and third decoded signals depicted at C0, C1, and C2 in Figs. 5 and 6, respectively, in response to the address distance signal D of three bits d₀d₁d₂. The first decoder 71 decodes the address distance signal D into the first decoded signal C0 of two bits represented by C0₀ and C0₁. The two bits C0₀ and C0₁ of the first decoded signal C0 are the most significant bit and the least significant bit, respectively, and always take a binary representation of (10)₂ even when the address distance signal D is varied between (0)₁₀ and (7)₁₀, respectively, as shown in Fig. 6 and Fig. 7(A). The second decoder 72 decodes the address distance signal D into the second decoded signal C1 of five bits in accordance with an algorithm as readily understood from Fig. 6. The five bits of the second decoded signal C1 are successively numbered from the most significant bit C1₀ to the least significant bit C1₄ and are equal to d₁, 1, d ₁, 0, and d₁, respectively. As a result, the five bits of the second decoded signal C1 are varied in dependency upon the address distance signal D and take pattern illustrated in Fig. 7(B). The third decoder 73 decodes the address distance signal D into the third decoded signal C2 of eleven bits C2₀ to C2₁₀ arranged from the most significant bit thereof. As illustrated in Fig. 7(C), the eleven bits from C2₀ to C2₁₀ are equal to d₀, d₁, d₀, 1, d ₀, d ₁, d ₀, 0, d₀, d₁, and d₀, respectively, and take patterns which are illustrated in Fig. 6 and which are determined by the address distance signal D. It is readily possible to practically design the first through third decoders 71 to 73 with reference to Figs. 6 and 7. The first through third decoders 71 to 73 will not be described any longer. Referring to Fig. 8 in addition to Figs. 5 and 7, the first shift circuit 76 is supplied with the least significant bit b₂ of the first address signal B and the first decoded signal C0 of two bits represented by C0₀ and C0₁. The first shift circuit 76 comprises an input circuit 81, AND gates 82 and 83, and an OR gate 84. As readily seen from Fig. 8, the bit C0₀ is produced through the AND gate 82 and the OR gate 84 when the bit b₂ takes the logic "1" level. Otherwise, the bit C0₁ is produced through the AND gate 83 and the OR gate 84. This means that the first decoded signal C0 is shifted rightwards of Fig. 7(A) in response to the first shift signal SH₁ to produce a first shifted signal and that the least significant bit is extracted or separated from the first shifted signal. Specifically, the first decoded signal C0 is shifted by one bit rightwards in response to the bit b₂ of the logic "1" level. On the other hand, such a rightward shift is stopped in response to the bit b₂ of the logic "0" level. At any rate, the least significant bit of the first shifted signal is delivered to the first through fourth switches SW₁ to SW₄ as the first through fourth control signals S₁ to S₄, respectively. Thus, the first through fourth control signals S₁ to S₄ are common to one another. Referring to Fig. 9 together with Figs. 5 and 7, the second shift circuit 77 is operable in response to the second shift signal SH₂ formed by two lower bits b₁b₂ of the first address signal B and to the second decoded signal C1. The second shift circuit 77 comprises two circuits similar to each other, although a single circuit alone is illustrated in Fig. 9. The illustrated ones of the circuits is for shifting four bits C1₀ to C1₃ of the second decoded signal C1 in accordance with the second shift signal SH₂ to supply the fifth and sixth control signals S₅ and S₆ to the fifth and sixth switch units SW₅ and SW₆, respectively. The other circuit is for shifting four bits of the second decoded signal C1 to supply the seventh and eighth control signals S₇ and S₈ to the seventh and eighth switch units SW₇ and SW₈. More particularly, the illustrated circuit comprises two input gates 86 and 87 responsive to the two bits b₁b₂ of the second shift signal SH₂, a group 88 of four AND gates 88₁ to 88₄ connected to the input gates 86 and 87, and an OR gate 89 connected to the four AND gates. Then the bits b₁b₂ are equal to (11)₂, the bit C1₀ or C1₁ is selected by the AND gate group 88₁ and the OR gate 89. This is equivalent to the fact that the bit C1₀ and C1₁ are shifted rightwards of Fig. 7(B) by three bits to form a second shifted signal of two bits and that high and low significant bits of the second shifted signal are produced as the fifth and sixth control signals S₅ and S₆ and the seventh and eighth control signals S₇ and S₈, respectively. Likewise, the bit C1₁ or C1₂ is selected through the AND gate 88₂ by the second shift circuit 77 when the two bits b₁b₂ of the second shift signal SH₂ take (10)₂, respectively. The bit C1₁ is produced as the fifth and sixth control signals S₅ and S₆ while the bit C1₂ is produced as the seventh and eighth control signals S₇ and S₈. This is equivalent to the fact that the second decoded signal C1 shown in Fig. 7(B) is shifted rightwards by two bits to form the second shifted signal and that a least significant bit but one and the least significant bit are selected as the fifth and sixth control signals S₅ and S₆ and the seventh and eighth control signals S₇ and S₈, respectively. Similarly, the bit C1₂ or C1₃ is selected through the AND gate 88₃ in response to the two bits b₁b₂ of (01)₂. The bit C1₂ is delivered to the fifth and sixth switch units SW₅ and SW₆ as the fifth and sixth control signals S₅ and S₆ while the bit C1₃ is delivered to the seventh and the eighth switch units SW₇ and SW₈ as the seventh and eighth control signals S₇ and S₈. This means that the second decoded signal C1 shown in Fig. 7(B) is shifted rightwards by one bits to form the second shifted signal band that a least significant bit but one and the least significant bit of the second shifted signal are produced as the fifth and sixth control signals S₅ and S₆ and the seventh and eighth control signals S₇ and S₈, respectively. Responsive to the two bits b₁b₂ of (00)₂, the second shift circuit 77 selects the bit C1₃ or C1₄ through the AND gate 88₄ to produce the fifth and sixth control signals S₅ and S₆ or the seventh and eighth control signals S₇ and S₈, respectively. This implies that no shift is carried out and that the least significant bit but one and the least significant bit of the second decoded signal are selected as the fifth and sixth control signals S₅ and S₆ or the seventh and eighth control signals S₇ and S₈, respectively. Referring to Fig. 10 together with Figs. 5 and 7, the third shift circuit 78 is operable in response to the first or leading address signal B, the group indication signal GI, and the third decoded signal C2 illustrated in Fig. 7(C). The third shift circuit 78 comprises a combination of four logic circuits similar in structure to one another. Therefore, a single logic circuit alone is illustrated in Fig. 10. Each of the four logic circuits is supplied with the three bits b₀b₁b₂ of the first address signal B and two bits (m₀m₁)₂ of the group indication signal GI. A first one of the logic circuits is given eight bits of the third decoded signal C2 which are depicted at C2₀ to C2₇ while a second one of the logic circuits is given eight bits of the third decoded signal C2 which are shifted by a single bit relative to the eight bits given to the first logic circuit and which are depicted at C2₁ to C2₈. Likewise, a third one of the logic circuits is given eight bits depicted at C2₂ to C2₉ while a fourth one of the logic circuits is given eight bits depicted at C2₃ to C2₁₀. The first through fourth logic circuits are for delivering the ninth through twelfth control signals S₉ to S₁₂ to the ninth through twelfth switch units SW₉ to SW₁₂, respectively. Each logic circuit comprises three input gates collectively shown at 91, eight AND gates depicted at 92₁ to 92₈, a first OR gate 93, an additional AND gate 94, an inverter 95, and a second OR gate 96. In the example being illustrated, when two bits m₀m₁ of the group indication signal GI are equal to (10)₂, the ninth through twelfth control signals S₉ to S₁₂ take the logic "0" level in common. Similarly, when two bits m₀m₁ are equal to (01)₂, the ninth through twelfth control signals S₉ to S₁₂ take the logic "1" level in common. From this fact, it is readily understood that the ninth through twelfth switch units SW₉ to SW₁₂ carry out a similar operation when the memory units 52-1 and 52-8 (Fig. 1) are partially accessed in the manner illustrated in conjunction with Fig. 2. In other words, each bit of the third decoded signal C2 is selected in response to the three bits b₀b₁b₂ of the first address signal B only when the two bits m₀m₁ of the group indication signal GI take (11)₂. Let the two bits m₀m₁ of the group indication signal GI be equal to (11)₂. In this event, the first through fourth logic circuits select the bits C2₀, C2₁, C2₂, and C2₃ of the third decoded signal C2 through the AND gate 92₁, the first OR gate 93, the additional AND gate 94, and the second OR gate 96 when the three bits b₀b₁b₂ of the first address signal B take (111)₂. Selection of the bits C2₀, C2₁, C2₂, and C2₃ is equivalent to the fact that the third decoded signal C2 (Fig. 7(C)) is shifted rightwards by seven bits to form a third shifted signal and that four lower bits of the third shifted signal are produced as the ninth through twelfth control signals S₉ to S₁₂, respectively. In a similar manner, four bit sets, such as C2₁, C2₂, C2₃, C2₄; C2₂, C2₃, C2₄, C2₅; and the like, are selected as the ninth through twelfth control signals S₉ to S₁₂ in response to the first address signal B. As mentioned in conjunction with Figs. 8 to 10, the first through twelfth control signals S₁ to S₁₂ are produced by shifting the first through third decoded signals C0, C1, and C2 in accordance with the first address signal B in the first through third shift circuits 76 to 78. Now, operation will be described with reference to Figs. 1, 2, 5, and 7. It is assumed that the group indication signal GI takes (11)₂ to indicate all of the first through eighth memory areas 52-1 to 52-8 and that the first or leading address signal B specifies the zeroth address "0" and that the address distance D is equal to three. Under the circumstances, the line 51-1 (Fig. 1) is given the zeroth address "0" while the lines 51-2 to 51-8 are given (3, 6, 9, 12, 15, 18, and 21) calculated by successively adding three, respectively. As shown in Fig. 2(A), the above-mentioned addresses of (0, 3, 6, 9, 12, 15, 18, 21) are assigned to the memory units 52-1, 52-4, 52-7, 52-2, 52-5, 52-8, 52-3, and 52-6, respectively. Therefore, the first through eighth input ports I1 to I8 should be connected to the first, fourth, seventh, second, fifth, eighth, third, and sixth output ports O1, O4, O7, O2, O5, O8, O3, and O6, respectively. In this event, the central processing unit 51 produces the first address signal B specifying the zeroth address "0" and the address distance signal D representative of the address distance (3)₁₀. Responsive to the address distance signal D representative of the address distance (3)₁₀, the first through third decoders 71 to 73 supplies the first through third shift circuits 76 to 78 with the first through third decoded signals C0, C1, and C2 which are represented by (10)₂, (11001)₂, and (01011010010)₂, as shown in Figs. 7(A) to (C), respectively. On the other hand, the shift number calculator 74 delivers the first shift signal SH₁ of (0)₂, the second shift signal SH₂ of (00)₂, and the third shift signal SH₃ of (000)₂ to the first through third shift circuits 76 to 78 in response to the first or leading address signal B of (000)₂, respectively. In Figs. 5, 7, and 8, the first shift circuit 76 produces the first through fourth control signals S₁ to S₄ of the logic "0" level in response to the first shift signal SH₁ of (0)₂, as readily understood from Figs. 7(A) and 8. Responsive to the second shift signal SH₂ of (00)₂, the second shift circuit 77 selects the bit C1₃ or C1₄ of the second decoded signal C1. The bit C1₃ is delivered as the fifth and sixth control signals S₅ and S₆ to the fifth and sixth switch units SW₅ and SW₆. As shown in Fig. 7(B), the bit C1₃ of the second decoded signal C1 takes (0)₂ when the address distance is equal to (3)₁₀. The bit C1₄ is delivered to the seventh and eighth switch units SW₇ and SW₈ as the seventh and eighth control signals S₇ and S₈ and takes (1)₂ when the address distance is equal to (3)₁₀. Responsive to the third shift signal SH₃ of (000)₂, the third shift circuit 78 selects the bits C2₇, C2₈, C2₉, and C2₁₀ as the ninth through twelfth control signals S₉ to S₁₂, as readily understood from Fig. 10. When the address distance is equal to (3)₁₀, the bits C2₇, C2₈, C2₉, and C2₁₀ of the third decoded signal C2 are equal to (0010)₂, respectively, as illustrated in Fig. 7(C). Accordingly, the ninth through twelfth control signals S₉ to S₁₂ take (0010)₂, respectively. Referring to Fig. 11, internal paths are formed in the switching network 55 in response to the above-mentioned first through twelfth control signals S₁ to S₁₂ of (000000110010)₂. As shown in Fig. 11, the first through eighth input ports I1 to I8 are linked to the first, fourth, seventh, second, fifth, eighth, third, and sixth output ports O1, O4, O7, O2, O5, O8, O3, and O6, respectively. Thus, the input ports I1 to I8 are connected to destination ones of the output ports O1 to O8 and are therefore connected to the memory units in question. In Figs. 1, 5, 7, and 8 through 10, let the group indication signal GI be represented by (11)₂ to put all of the first through twelfth memory units 52-1 to 52-8 into the accessible states. In addition, let the first or leading address B be (3)₁₀ and the address distance D be equal to (3)₁₀. In this case, the first through third decoders 76 to 78 produce the first through third decoded signals C0 to C2 which are equal to (10)₂, (11001)₂, and (01011010010)₂, respectively, as readily understood from Fig. 7, and which are identical with the above-mentioned example. Responsive to the first address signal B of (3)₁₀, the shift number calculator 74 supplies the first through third shift circuits 76 to 78 with the first through third shift signals SH₁ to SH₃ which are representative of (1)₂, (11)₂, and (011)₂, respectively. Under the circumstances, the first shift circuit 76 (Fig. 8) selects the bit C0₀ of (1)₂ in response to the first shift signal SH₁ of (1)₁₀ to supply the first through fourth switch units SW₁ to SW₄ with the first through fourth control signals S₁ to S₄ which all take (1)₂. Supplied with the second shift signal SH₂ of (11)₂, the second shift circuit 77 (Fig. 9) delivers the bits C1₀ and C1₁ of the second decoded signal C1 to the fifth and sixth switch units SW₅ and SW₆ and to the seventh and eighth switch units SW₇ and SW₈, respectively. As shown in Fig. 7(B), the bits C1₀ and C1₁ are equal to (1)₂ and (1)₂, respectively, and serve as the fifth and sixth control signals S₅ and S₆ and the seventh and eighth control signals S₇ and S₈, respectively. Thus, all of the fifth through eighth control signals S₅ to S₈ take the logic "1" level. Responsive to the third shift signal SH₂ of (011)₂, the third shift circuit 78 (Fig. 10) selects the bits C2₄, C2₅, C2₆, and C2₇, as seen from Fig. 10, and produces the selected bits C2₄, C2₅, C2₆, and C2₇ as the ninth through twelfth control signals S₉ to S₁₂, respectively. Inasmuch as the selected bits C2₄, C2₅, C2₆, and C2₇ of the third decoded signal C2 are equal to 1, 0, 1, and 0, respectively, provided that the address distance is equal to three, the ninth through twelfth control signals S₉ to S₁₂ take (1010)₂, respectively. Thus, the first through twelfth switch units SW₁ to SW₁₂ are controlled by the first through twelfth control signals S₁ to S₁₂ of (111111111010)₂, respectively. Referring to Fig. 12, the first through twelfth switch units SW₁ to SW₁₂ of the switching unit 55 are controlled by the above-mentioned first through twelfth control signals S₁ to S₁₂ to form internal paths in the switching network 55. As shown in Fig. 12, the first through eighth input ports I1 to I8 are interconnected to the fourth, seventh, second, fifth, eighth, third, sixth, and first output ports O4, O7, O2, O5, O8, O3, O6, and O1 which are linked to the corresponding memory units 52-4, 52-7, 52-2, 52-5, 52-8, 52-3, 52-6, and 52-1, respectively. As readily understood from the first address of (3)₁₀ and the address distance of (3)₁₀, the first through eighth input ports I1 to I8 are supplied with the memory addresses of 3, 6, 9, 12, 15, 18, 21, and 24 which are assigned to the fourth, seventh, second, fifth, eighth, third, sixth, and first memory units, respectively. Therefore, these memory units are correctly connected to the first through eighth input ports I1 to I8 and are correctly accessed through the switching network 55 by the central processing unit 51. It is assumed that only the fifth through eighth memory units 52-5 to 52-8 are accessible by the central processing unit 51 while the first through fourth memory units 52-1 to 52-4 are not accessible. Therefore, the fifth through eighth memory units 52-5 to 52-8 are assigned with the memory addresses in the manner illustrated in Fig. 2(C). Let the first or leading address for a leading one of the vector signals be the third address (3)₁₀ and the address distance be equal to (3)₁₀. In this event, the first through third decoders 71 to 73 (Fig. 5) produce the first through third decoded signals C0 to C2 which are identical with those illustrated in conjunction with Fig. 12. Accordingly, the two bits C0₀ and C0₁ of the first decoded signal C0, the five bits C1₀ to C1₄ of the second decoded signal C1, and the eleven bits C2₀ to C2₁₀ of the third decoded signal C2 become equal to (10)2, (11001)2, and (01011010010)₂, respectively, as seen from Figs. 7(A) to (C), and are delivered to the first through third shift circuits 76 to 78, respectively. The first through third shift circuits 76 to 78 are supplied with the first shift signal SH₁ of (1)₂, the second shift signal SH₂ of (11)₂, and the third shift signal SH₃ of (011)₂, respectively. The first shift circuit 76 selects the bit C0₀ of the logic "1" level to produce the first through fourth control signals S₁ to S₄ each of which takes (1)₂. The second shift circuit 77 selects the bits C1₀ and C1₁ each of which takes the logic "1" level and which are produced as the fifth and sixth control signals S₅ and S₆ and the seventh and eighth control signals S₇ and S₈, respectively. On the other hand, the third shift circuit 78 is supplied with the group indication signal GI of (01)₂ because the fifth through eighth memory units 52-5 to 52-8 are accessible. In this case, the third shift circuit 78 produces the ninth through twelfth control signals S₉ to S₁₂ which all take the logic "1" level, as readily understood from Fig. 10. Referring to Fig. 13, internal paths are formed in the switching network 55 by the above-mentioned set of the first through twelfth control signals S₁ to S₁₂ which all take (1)₂. As a result, the first through eighth input ports I1 to I8 are interconnected to the eighth, seventh, sixth, fifth, fourth, third, second, and first output ports O8, O7, O6, O5, O4, O3, O2, and O1, respectively. Herein, it is noted that valid or usable ones of the address signals are given only to the first through fourth input ports I1 to I4 and specify the memory addresses of 3, 6, 9, and 12 which are assigned to the eighth, seventh, sixth, and fifth memory units 52-8, 52-7, 52-6, and 52-5, as shown in Fig. 2(C). The internal paths illustrated in Fig. 13 are correctly interconnected to the eighth, seventh, sixth, and fifth memory units 52-8, 52-7, 52-6, and 52-5, respectively, as readily understood from the above. In the example being illustrated, when the address distance is represented by an even number, the illustrated circuit arrangement 50 fails to correctly distribute the address signals to the memory units 52-1 to 52-8. Such incorrect distribution is possible by enabling the circuit arrangement 50 by the central processing unit 51 only when the address distance is represented by an odd number. Referring to Fig. 14, a control circuit 56 is applicable to the circuit arrangement according to the first embodiment of this invention and is similar to that illustrated in Fig. 5 except that the group indication signal GI of two bits m₀m₁ is supplied to a third decoder 73' which is somewhat modified from the third decoder 73 illustrated in Fig. 5 and which is coupled to a third shift circuit 78'. In Fig. 14, the illustrated third decoder 73' comprises a control signal section similar to the third decoder 73 illustrated in Fig. 5 and a logic signal section operable in response to the group indication signal GI in a manner to be described later. Therefore, the control signal section produces the third control signal C2 of eleven bits C2₀ to C2₁₀ (as shown in Fig. 6) in response to the address distance signal D of three bits b₀b₁b₂. The eleven bits C2₀ to C2₁₀ of the third decoded signal C2 are represented by d₀, d₁, d₀, 1, d ₀, d ₁, d ₀, 0, d₀, d₁, and d₀, respectively. The logic signal section comprises a plurality of circuit units each of which is similar to a part depicted at 101 in Fig. 10. The circuit units are for logically processing the respective bits of the third decoded signal C2. As a result, the eleven bits of the third decoded signal C2 pass through the circuit units as they stand when the two bits m₀m₁ of the group indication signal GI are equal to (11)₂. On the other hand, all of the eleven bits of the third decoded signal C2 are decoded into the logic "1" level when the two bits m₀m₁ of the group indication signal GI are equal to (01)₂ while they are all decoded into the logic "0" level when the two bits m₀m₁ are equal to (10)₂. The illustrated third shift circuit 78' is similar to the third shift circuit 78 illustrated in Fig. 10 except that the part 101 is removed from Fig. 10. This means that the ninth through twelfth control signals S₉ to S₁₂ are produced from the OR gate 94 (Fig. 10). With this structure, it is possible to connect the first through eighth input ports I1 to I8 to the first through eighth output ports O1 to O8 in the manner illustrated in conjunction with Fig. 11 when the two bits of the group indication signal GI are equal to (11)₂. Let the two bits m₀m₁ of the group indication signal GI be (10)₂ and the first through fourth memory units 52-1 to 52-4 be accessible by the central processing unit 51 (Fig. 1). The memory addresses are assigned to the first through fourth memory units 52-1 to 52-4 in the manner illustrated in Fig. 2(C). In this event, valid address signals are given only to the first through fourth input ports I1 to I4. It is presumed that the leading or first address signal B is indicative of the second address assigned to the third memory unit 52-3 and that the address distance D is equal to three. Referring to Fig. 15, the first through fourth input ports I1 to I4 are supplied with the memory addresses 2, 5, 8, and 11, respectively, on the above-mentioned condition. As shown in Fig. 15, the memory addresses 2, 5, 8, and 11 are assigned to the third, second, first, and fourth memory units 52-3, 52-2, 52-1, and 52-4, respectively. Therefore, the first through fourth input ports I1 to I4 must be connected to the third, second, first, and fourth memory units 52-3, 52-2, 52-1, and 52-4, respectively. In Figs. 7(A), 8, and 14, the first decoder 71 produces the first decoded signal C0 of (10)₂ in response to the address distance signal D of (011)₂. The second decoder 71 produces the second decoded signal C1 of (11001)₂, as shown in Fig. 7(B). On the other hand, the third decoder 73' (Fig. 14) produces the third decoded signal C2 of the eleven bits C2₀ to C2₁₀ which all take (0)₂, because the two bits m₀m₁ of the group indication signal GI are equal to (10)₂, respectively. Responsive to the first or leading address signal B of (010)₂, the shift number calculator 74 delivers the first shift signal SH₁ of (0)₂, the second shift signal SH₂ of (10)₂, and the third shift signal SH₃ of (010)₂ to the first through third shift circuits 76, 77, and 78', respectively. Accordingly, the first through fourth control signals S₁ to S₄ take (0)₂, as understood from Fig. 8. The fifth and sixth control signals S₅ and S₆ take (1)₂ while the seventh and eighth control signals S₇ and S₈ take (0)₂, as readily understood from Fig. 9. In addition, the ninth through twelfth control signals S₉ to S₁₂ take (0)₂ because the eleven bits C2₀ to C2₁₀ are all equal to (0)₂, as mentioned above. As a result, the first through twelfth switch units SW₁ to SW₁₂ are connected in the manner illustrated in Fig. 15. From this fact, it is seen that the first through fourth input ports I1 to I4 are connected through the circuit arrangement 50 to the memory units 52-3, 52-2, 52-1, and 52-4, respectively. Similar operation is possible by the use of the control circuit 56 illustrated in Fig. 14 when the two bits m₀m₁ of the group indication signal GI are equal to (01)₂ and will not be described any longer because the operation is similar to that illustrated in conjunction with Fig. 13. Referring to Fig. 16, a circuit arrangement 50 according to a second embodiment of this invention comprises a switching network 55 which is similar to that illustrated in Fig. 1 and which has first through eighth input ports I1 to I8 and first through eighth output ports O1 to O8. The first through eighth input ports I1 to I8 are consecutively numbered from zero to seven, respectively, and will be indicated at I(0) to I(7), respectively, as shown in Fig. 16. Likewise, the first through eighth output ports O1 to O8 are consecutively numbered from zero to seven and will be indicated at O(0) to O(7), respectively. In order to avoid confusion, the terms, such as "first," "eighth," will be omitted from the input and output ports, hereinunder. The switching network 55 comprises first through twelfth switch units SW₁ to SW₁₂ controlled by first through twelfth control signals S₁ to S₁₂ (depicted at S i in Fig. 16) like in Fig. 1. The illustrated circuit arrangement 50 has eight circuit input ports CI(0) to CI(7) consecutively numbered in a manner similar to the input ports I(0) to I(7) and connected to the input ports I(0) to I(7), respectively, and eight circuit output ports CO(0) to CO(7) consecutively numbered like the output ports O(0) to O(7). The circuit input ports CI (suffixes omitted) are connected to the central processing unit 51 (Fig. 1) while the circuit output ports CO are coupled to either the memory units 52-1 to 52-8 or array processors (not shown). A rearranging circuit 105 is placed between the output ports O(0) to O(7) and the circuit output ports CO(0) to CO(7) so as to modify connections between the output ports O(0) to O(7) and the circuit output ports CO(0) to CO(7) in a manner to be described later in detail. The rearranging circuit 105 comprises a first rearranging unit 106 between the output ports O(1), O(2), and O(4) and the circuit output ports CO(1), CO(2), and CO(4) and a second rearranging unit 107 between the output ports O(3), O(5), and O(6) and the circuit output ports CO(3), CO(5), and CO(6). The output ports O(0) and O(7) are connected direct to the circuit output ports CO(0) and CO(7), respectively. Each of the first and the second rearranging units 106 and 107 is similar in structure and operation to each other and is synchronously operated in response to a unit control signal E of a single bit. Referring to Figs. 17 and 18, description will be made as regards each of the first and second rearranging units 106 and 107. In Fig. 17, the output ports and the circuit output ports are depicted at O(u), O(v), and O(w) and CO(u), CO(v), and CO(w), respectively. As shown in Fig. 17(A), the output ports O(u), O(v), and O(w) are connected through the rearranging unit to the corresponding circuit output ports CO(u), CO(v), and CO(w), respectively, when the unit control signal E is equal to (0)₂. This implies that port numbers u, v, and w of the output ports are coincident with those of the circuit output ports. Supplied with the unit control signal E of (1)₂, the rearranging unit connects the output ports O(u), O(v), and O(w) to the circuit output ports CO(w), CO(u), and CO(v), respectively. From this fact, it is to be understood that the port numbers u, v, and w of the output ports are converted into w, u, and v, respectively. Thus, the rearranging unit serves to rearrange the output ports O(u), O(v), and O(w) in the above-mentioned manner in response to the unit control signal E of (1)₂. Referring to Fig. 18, each rearranging circuit 106 and 107 comprises an input gate circuit responsive to the unit control signal E, three pairs of AND gates connected to the input gate circuit and the output ports O(u), O(v), and O(w), and three OR gates connected to the respective pairs of AND gates and to the circuit output ports CO(u), CO(v), and CO(w), respectively. As readily understood from Fig. 18, the illustrated rearranging circuit can carry out the above-mentioned rearranging operation. Let each of the numbers u, v, and w of the output ports be given by three bits of (A₀A₁A₂)₂. When the unit control signal E takes (0)₂, the binary number A₀A₁A₂ is not changed by the rearranging unit. Accordingly, the output ports O(u), O(v), and O(w) are connected to the circuit output ports CO(u), CO(v), and CO(w), respectively. On the other hand, the binary number A₀A₁A₂ is changed into A₁A₂A₀ by the rearranging unit when the unit control signal E takes (1)₂. As a result, the output port represented by A₀A₁A₂ is connected to the circuit output port represented by A₁A₂A₀. Referring back to Fig. 16, the first rearranging unit 106 connects the output ports O(1), O(2), and O(4) to the circuit output ports CO(1), CO(2), and CO(4), respectively, in response to the unit control signal E of (0)₂. Otherwise, the output ports O(1), O(2), and O(4) are connected to the circuit output ports CO(2), CO(4), and CO(1), respectively. Likewise, the second rearranging unit 107 connects the output ports O(3), O(5), and O(6) to the circuit output ports CO(3), CO(5), and CO(6), respectively, in response to the unit control signal E of (0)₂. Supplied with the unit control signal E of (1)₂, the second rearranging unit 107 connects the output ports O(3), O(5), and O(6) to the circuit output ports CO(6), CO(3), and CO(5), respectively. Thus, this suggests that the order of 3, 5, and 6 assigned to the output ports O(3), O(5), and O(6) are rearranged into an order of 5, 6, and 3, as shown in Fig. 16. In Fig. 16, the illustrated circuit arrangement 50 further comprises a control circuit 56 for controlling the switching, unit 55 and the rearranging circuit 105. It is to be noted here that a sequence of vector signals can also be delivered to the memory 52 (Fig. 1) in a manner similar to that illustrated in conjunction with Fig. 1 by indicating a leading one of the output ports O(0) to O(7) for a leading vector signal and a port interval of the output ports through which the remaining vector signals are fed, if the vector signals are memorized in the memory 52 in the manner described with reference to Fig. 2. Under the circumstances, the control circuit 56 is supplied from the central processing unit 51 with a leading output port signal B and with a port interval signal D representative of the above-mentioned interval of the output ports. The leading output port signal B is representative of the number of the leading output port to which the input port I(0) is to be connected. The leading output port signal B serves as reference information while the port interval signal D serves as distance information. Anyway, the leading output port signal B and the port interval signal D can be represented by binary numbers of three bits b₀b₁b₂ and d₀d₁d₂, respectively, because the illustrated input and output ports are equal in number to eight, respectively. Referring to Fig. 19 together with Fig. 16, the control circuit 56 illustrated in Fig. 16 delivers the first through twelfth control signals S₁-S₁₂ to the switch units SW₁ to SW₁₂ and the unit control signal E to the first and second rearranging units 106 and 107 by carrying out logic operation in accordance with Fig. 19. Specifically, the unit control signal E takes (1)₂ only when the port interval is equal to (2)₁₀ and (6)₁₀, as shown in Fig. 19(A). Accordingly, the first and second rearranging circuits 106 and 107 rearrange the output ports in the manner described before only when the control circuit 56 is supplied with the port interval signal D of (2)₁₀ or (6)₁₀. As shown in Fig. 19(B), the control circuit 56 produces the first through fourth control signals S₁ to S₄ with reference to the least significant bit b₂ of the leading output port signal B when the unit control signal E takes (0)₂. On the other hand, the least significant bit but one b₁ of the leading output port signal B is referenced by the control circuit 56 when the unit control signal E takes (1)₂. In Fig. 19(C), it is apparent that the fifth through eighth control signals S₅ to S₈ are produced with reference to the port interval signal D, bit pairs b₀b₁ and b₁b₂ of the leading output port signal B, and the unit control signal E. Likewise, the ninth through twelfth control signals S₉ to S₁₂ are produced with reference to the port interval D, three bits b₀b₁b₂ of the leading output signal B, and the unit control signal E, as shown in Fig. 19(D). In Fig. 19(D), the ninth through twelfth control signals S₉ to S₁₂ are determined by b₂ of the leading output port signal B when the unit control signal E takes (1)₂. Referring to Fig. 20 together with Figs. 16 and 19, it is assumed that the leading output port (B) is the number (2)₁₀ of the output port O(2) and that the port interval (D) is equal to (3)₁₀, namely, (011)₂. In this case, the input ports I(0) to I(7) are to be linked to the output ports O(2), O(5), O(0), O(3), O(6), O(1), O(4), and O(7), respectively, because a relationship between the input ports I and the output ports O is given by: O = (B + I x D) mod 8, (1) and, therefore, O = (2 + I x 3) mod 8. The unit control signal E takes (0)₂ because D = (3)₁₀, as shown in Fig. 19(A). In addition, three bits b₀b₁b₂ of the leading output port B are represented by (010)₂. Accordingly, the first through fourth control signals S₁ to S₄ take (0)₂, as shown in Fig. 19(B). Inasmuch as the two lower bits b₁b₂ of the leading output port B are equal to (10)₂, namely, (2)₁₀, the fifth and sixth control signals take (1)₂ while the seventh and eighth control signals S₇ and S₈ are equal to d ₁, namely, (0)₂, as seen from Fig. 19(C). Likewise, the ninth through twelfth control signals S₉ to S₁₂ are given by d ₁, d ₀, 0, and d₀, as illustrated in Fig. 19(D) and therefore take (0)₂, (1)₂, (0)₂, and (0)₂, respectively. The first through twelfth control signals S₁ to S₁₂ mentioned above are delivered to the first through twelfth switch units SW₁ to SW₁₂, respectively. Consequently, the first through twelfth switch units SW₁ to SW₁₂ are internally connected in the manner illustrated in Fig. 20. On the other hand, the first rearranging unit 106 connects the output ports O(1), O(2), and O(4) to the circuit output ports CO(1), CO(2), and CO(4), respectively, in response to the unit control signal E of (0)₂. Likewise, the output ports O(3), O(5), and O(6) are connected to the circuit output ports CO(3), CO(5), and CO(6) through the second rearranging unit 107, respectively. As shown in Fig. 20, the input ports I(0) to I(7) are certainly connected to CO(2), CO(5), CO(0), CO(3), CO(6), CO(1), CO(4), and CO(7), respectively. Thus, eight input ports can simultaneously be switched to eight circuit output ports in the illustrated circuit arrangement 50. Similar operation is possible when the port interval (D) is equal to any other odd numbers, such as 1, 5, and 7. Referring to Fig. 21, description will be made about operation of the switching network 55 which is carried out when the port interval (D) is equal to even numbers, such as 2, 6. Let the leading output port (B) be (0)₁₀ and the port interval (D) be equal to (2)₁₀. In this event, the input ports I(4) to I(7) must be connected to the output ports common to the input ports I(0) to I(3), respectively. Therefore, the input ports I(4) to I(7) can not be connected to the output ports in question simultaneously with the input ports I(0) to I(3). Under the circumstances, it is understood that only four input ports are available when the port interval D is equal to (2)₁₀. In Fig. 21, the input port I(0) is linked to the output port O(0) through an internal path formed by the first switch unit SW₁, the fifth switch unit SW₅, and the ninth switch unit SW₉. For connection of the input port I(1) to the output port O(2), an internal path must be formed between the input port I(1) and the output port O(4) through the first, fifth, and eleventh switch units SW₁, SW₅, and SW₁₁. As shown in Fig. 21, the internal path for the input port I(1) conflicts with the internal path for the input port I(0). Similarly, internal paths for the input ports I(2) and I(3) conflict with each other at the second switch unit SW₂ and with the internal paths for the input ports I(0) and I(1) at the fifth switch unit SW₅ and the eleventh switch unit SW₁₁, as illustrated in Fig. 21. The switch units can not be operated on occurrence of such conflict. Referring to Fig. 22, it will be proved that four internal paths can be formed in the circuit arrangement 50 illustrated in Fig. 16 without any conflict of the internal paths even when the port interval (D) is equal to (2)₁₀ or (6)₁₀. In Fig. 22, let the leading output port B be (2)₁₀, namely, (10)₂, and the port interval (D) be equal to (6)₁₀, namely, (110)₂. As mentioned before, only the input ports I(0) to I(3) are accessed to form the four internal paths. In this case, the unit control signal E takes (1)₂, as shown in Fig. 19(A). According to Equation (1), the input ports I(0) to I(3) have to be connected to the circuit output ports CO(2), CO(0), CO(6), and CO(4), respectively. As shown in Figs. 19(B), (C), and (D), the first through fourth control signals S₁ to S₄ and the fifth through eighth control signals S₅ to S₈ are produced as the bit b₁ and the bits b₀b₁ of the leading output port signal B, respectively, when E = 1. From this fact, it is seen that the three bits of the leading output port signal B are shifted by one bit leftwards and that the leading output port number is divided by two into a half number of the leading output port number. This applies to the port interval (D), as shown in Fig. 19(C). Accordingly, the bits d₂, d₁, b₁, and b₂ are changed or adjusted to d₁, d₀, b₀, and b₁, respectively. The adjustment of the leading output port signal B and the port interval signal D enables similar operation to the case where the port interval (D) is equal to an odd number and therefore serves to avoid the conflict of the internal paths. Under the circumstances, only the first and second switch units SW₁ and SW₂ are connected to the input ports I(0) to I(3) and controlled by the first and second control signals S₁ and S₂ produced in the manner illustrated in Fig. 19(B). The first and second control signals S₁ and S₂ take (1) because E = (1)₂ and b₁ = (1)₂. Each of the third and fourth control signals S₃ and S₄ is identical with the first and second control signals S₁ and S₂ but it may be neglected in Fig. 22. The fifth through eighth control signals S₅ to S₈ are produced with reference to two bits b₀b₁ of the leading output port signal B and the bit d₀ of the port interval signal D in the manner shown in Fig. 19(C). Accordingly, the fifth and sixth control signals S₅ and S₆ are specified by d ₀ and take (0)₂. The seventh and the eighth control signals S₇ and S₈ are specified by (0)₂ and take (0)₂. The ninth through twelfth control signals S₉ to S₁₂ are determined by the bit b₂ of the leading output port signal B and are therefore equal to (0)₂, as shown in Fig. 19(D). Thus, the input ports I(0) to I(3) are linked to the output ports O(1), O(0), O(3), and O(2) through the internal paths, respectively, in response to the above-mentioned first through twelfth control signals S₁ to S₁₂. It is to be noted here that a half (O(0) to O(3)) of the output ports O(0) to O(7) is collectively used when the leading output port is represented by an even number. On the other hand, the remaining half of the output ports O(4) to O(7) is collectively connected to the input ports when the leading output port is represented by an odd number. This is because the ninth through twelfth control signals S₉ to S₁₂ are determined by b₂ of the leading output port signal B. Thus, the internal paths are converged into a half of the output ports O(0) to O(7) in accordance with the bit b₂ of the leading output port signal B when E = 1. In Fig. 22, the first and second rearranging units 106 and 107 are controlled in response to the unit control signal E of (1)₂ to rearrange the output ports O(1), O(2), and O(4) and O(3), O(5), and O(6) in the manner described before. Therefore, the output ports O(0) to O(3) are linked to the circuit output ports CO(0), CO(2), CO(4), and CO(6), respectively, as illustrated in Fig. 22. As a result, the input ports I(0) to I(3) are connected to the circuit output ports CO(2), CO(0), CO(6), and CO(4), respectively. Similar operation is possible when the port interval is equal to (2)₁₀. Thus, the four input ports can concurrently be connected to the circuit output ports without any conflict even when the port interval (D) is equal to (2)₁₀ or (6)₁₀. It will be understood from Fig. 19 that the input port I(0) alone is connected to a desired one of the circuit output ports CO(0) to CO(7) when D = 0 or D = 4. However, it is possible to simultaneously connect two input ports to desired circuit output ports by preparing an additional pattern for rearrangement of each rearranging unit along with the above-mentioned rearrangement pattern and by adjusting internal paths of the switching unit 55 in compliance with the additional pattern. Referring to Fig. 23, a circuit arrangement according to a third embodiment of this invention is similar to that illustrated in Fig. 16 except that a rearranging circuit depicted at 105' is intermediate between the circuit input ports CI(0) to CI(7) and the input ports I(0) to I(7) and that a switching network 55' and a control signal 56' are somewhat different from those illustrated in Fig. 16, as will become clear as the description proceeds. The switching network 55' is equivalent to the switching network 55 (Fig. 1) wherein the input ports and the output ports are upset relative to each other. The switching network 55' comprises first through twelfth switch units SW₁ to SW₁₂ which are divided into first, second, and third stages in a manner similar to that illustrated in Fig. 1. In Fig. 23, the output ports O(0) to O(7) are directly connected to the circuit output ports CO(0) to CO(7) which are omitted from Fig. 23, respectively. The first switch unit SW₁ is connected to the input ports I(0) and I(4) while the second switch unit SW₂ is connected to the input ports I(1) and I(5). Likewise, the third and fourth switch units SW₃ and SW₄ are connected to the input ports I(2) and I(6) and the input ports I(3) and I(7), respectively. The first through fourth switch units SW₁ to SW₄ (Fig. 23) may be made to correspond to the ninth through twelfth switch units SW₉ to SW₁₂ illustrated in Fig. 1 while the ninth through twelfth switch units SW₉ to SW₁₂ (Fig. 23) may be made to correspond to the first through fourth switch units SW₁ to SW₄ illustrated in Fig. 1. Therefore, connections between the first and the second stages of switch units illustrated in Fig. 23 are equivalent to those between the third and second stages of the switch units illustrated in Fig. 1. Similarly, connections between the second and third stages of the switch units illustrated in Fig. 23 are equivalent to those between the second and first stages of switch units illustrated in Fig. 1. In Fig. 23, the rearranging circuit 105' comprises first and second rearranging units 106' and 107' which are operable in response to the unit control signal E like the rearranging units 106 and 107 illustrated in Fig. 16. In short, when each circuit input port number is represented by a binary representation of three bits A₀A₁A₂, each rearranging unit connects the circuit input ports of A₀A₁A₂ to the input ports represented by A₀A₁A₂, respectively, when the unit control signal E takes (0)₂. Otherwise, the rearranging units 106' and 107' connect the circuit input ports of A₀A₁A₂ to the input ports represented by A₂A₀A₁. As a result, an arrangement or order of the circuit input port numbers 0 to 7 is rearranged by the first and second rearranging units 106' and 107'. When the unit control signal E takes (1)₂, the input ports I(1), I(2), and I(4) are connected to the circuit input ports CI(2), CI(4), and CI(1) by the first rearranging unit 106', respectively, while the input ports I(3), I(5), and I(6) are connected to the circuit input ports CI(6), CI(3), and CI(5) by the second rearranging unit 107', respectively. Each rearranging unit 106' and 107' can be realized by a logic circuit similar to that illustrated in Fig. 18. It is mentioned here that the illustrated control circuit 56' is supplied from the central processing unit (not shown in this figure) with a leading input port signal which is representative of a leading input port number and which is depicted at B. The leading input port number is assigned to a leading one of the circuit input ports that is to be connected to the output port O(0) and that is supplied with a leading one of a vector signal sequence. In addition, the control circuit 56' is also given a port interval signal representative of an input port interval at which the input ports are accessed or selected. The input port interval is usually equal to an output port interval at which the output ports are selected. The input port interval is given as a port interval signal depicted at D. In the example being illustrated, the leading input port signal B and the port interval signal D are represented in the form of b₀b₁b₂ and d₀d₁d₂, respectively, like in Figs. 1 and 16, because each of the circuit input and output ports, namely, the input and the output ports is equal in number to eight. Referring to Fig. 24 together with Fig. 23, the illustrated control circuit 56' delivers first through twelfth control signals S₁ to S₁₂ and a unit control signal E to the first through twelfth switch units SW₁ to SW₁₂ and to the rearranging circuit 105 in compliance with algorithm shown in Figs. 24. As shown in Fig. 24(A), the unit control signal E takes (1)₂ only when the port interval D is equal to (2)₁₀ or (6)₁₀, like in Fig. 19(A). The first through fourth control signals S₁ to S₄ (Fig. 24(B)) are similar to the ninth through twelfth control signals S₉ to S₁₂ illustrated in Fig. 19(D), respectively. Likewise, the fifth through eighth control signals S₅ to S₈ and the ninth through twelfth control signals S₉ to S₁₂ (Figs. 24(C) and (D)) are similar to the fifth through eighth control signals S₅ to S₈ (Fig. 19(C)) and to the first through fourth control signals S₁ to S₄ (Fig. 19(D)), respectively. Therefore, the first through twelfth control signals S₁ to S₁₂ (Fig. 24) will not be described in detail any longer. The circuit arrangement 50 illustrated in Fig. 23 is operable in a manner similar to that illustrated in Fig. 16. For example, let the leading input port signal B be (2)₁₀, namely, (010)₂ and the port interval signal D be representative of (3)₁₀, namely, (011)₂. Inasmuch as a relationship between the circuit input ports CI and the output ports O is given by: I = (B + D x O) mod 8, (2) the output ports O(0) to O(7) are to be connected to the circuit input ports I(2), I(5), I(0), I(3), I(6), I(1), I(4), and I(7) in order, respectively. Responsive to the leading input port signal B of (010)₂ and the port interval signal D of (011)₂, the control circuit 56' carries out calculation in compliance with the algorithm shown in Fig. 24 to produce the unit control signal E and the first through twelfth control signals S₁ to S₁₂. As readily understood from Fig. 24, the unit control signal E takes (0)₂ while the first through fourth control signals S₁ to S₄ are equal to (0100)₂, respectively. Likewise, the fifth and sixth control signals S₅ and S₆ are equal to (1)₂ while the seventh and eighth control signals S₇ and S₈ are equal to (0)₂, as seen from Fig. 24(C). The ninth through twelfth control signals S₉ to S₁₂ are equal to (0)₂. Referring to Fig. 25, the rearranging circuit 105' and the switching unit 55' form internal paths in response to the unit control signal E of (0)₂ and the above-mentioned first through twelfth control signals S₁ to S₁₂ of (0100)₂, (1100)₂, and (0000)₂, respectively. Since the unit control signal E is equal to (0)₂, the first and second rearranging units 106' and 107' connect the circuit input ports CI(1), (2), and (4) and (3), (5), and (6) to the corresponding input ports I(1), (2), and (4) and (3), (5), and (6), respectively. As shown in Fig. 25, the output ports O(0) to O(7) are certainly linked to the circuit input ports I(2), I(5), I(0), I(3), I(6), I(1), I(4), and I(7), respectively. Similar connection of the eight output ports can be carried out when the port interval is represented by an odd number, such as 1, 5, and 7, irrespective of the leading input port number (B). It is noted here that, when the port interval (D) is, equal to an even number, any conflict of internal paths objectionably occurs in the switching circuit 55 (Fig. 23) in a manner similar to that illustrated in conjunction with Fig. 21. However, such an objectionable conflict can be avoided by the help of the rearranging circuit 105'. In this case, four of the output ports simultaneously become usable as is the case with Fig. 22. Referring to Fig. 26, it is assumed that the leading input port signal B is indicative of (2)₁₀, namely, (010)₂ and the port interval signal D is indicative of (6)₁₀, namely, (110)₂. In this case, the circuit input ports are indicated in the order of I(2), I(0), I(6), and I(4) which are to be connected to the output ports O(0) through O(3), respectively. Responsive to the port interval signal D of (6)₁₀, the first and second rearranging units 106' and 107' are switched to rearrange connections between the circuit input ports CI(1), (2), and (4) and CI(3), (5) and (6), respectively, in the manner described in conjunction with Fig. 23. In Fig. 26, the circuit input ports CI(2), CI(4), and CI(6) in question are connected to the respective input ports I(1), I(2), and I(3) through the first and second rearranging units 106' and 107', as depicted at thick lines in Fig. 26 while the circuit input ports CI(1), CI(3), and CI(5) are connected through the first through second rearranging units 106' and 107' to the respective input ports I(4), I(5), and I(6), although not shown in Fig. 26. Thus, the rearranging circuit 105' serves to converge even number ports of the circuit input ports into the input ports I(0) to I(3) and to converge odd number ports of the circuit input ports into the input ports I(4) to I(7). This means that, when the leading input port number is an even number, the input ports I(0) to I(3) become available and, otherwise, the input ports I(4) to I(7) become available. The control circuit 56' processes the leading input port signal B and the port interval signal D by recognizing B and D as B/2 and D/2, respectively, like the control circuit 56 illustrated in Fig. 16. Anyway, the control circuit 56' supplies the first through twelfth switch units SW₁ to SW₁₂ with the first through twelfth control signals S₁ to S₁₂ which are equal to (0000)₂, (0000)₂, and (1111)₂, respectively. As a result, four of the circuit input ports can simultaneously be connected to four of the output ports O(0) to O(4) even when the port interval (D) is equal to (2)₁₀ or (6)₁₀. When the port interval (D) is equal to (0)₁₀ or (4)₁₀, a single one of the input ports I(0) to I(7) alone becomes available and can be connected to the output port O(0). However, it is possible to simultaneously connect two input ports to two of the output ports O(0) and O(1) in a manner similar to that described in conjunction with Fig. 16 even when the port interval (D) is equal to (4)₁₀. Referring to Fig. 27, a circuit arrangement according to a fourth embodiment of this invention is similar to that illustrated in Fig. 1 except that the illustrated central processing unit 51 and control circuit 56 are operated in a different manner from those illustrated in Fig. 1. In Fig. 27, the central processing unit 51 comprises a processing circuit 115 and a calculation circuit 120 operable in cooperation with the processing unit 115. The calculation circuit 120 comprises first and second calculators 121 and 122 both of which can be put into an active state or each of which can individually be put into the active state. Each of the first and second calculators 121 and 122 carries out calculation in a manner similar to each other in the active state to simultaneously produce four array elements in parallel. The four array elements may be, for example, vector elements and are assumed to be delivered through the circuit arrangement 50 to the first through eighth memory units 52-1 to 52-8 to which memory addresses are assigned in the manner illustrated in Fig. 2(A). Like in Figs. 1 and 2, the array elements are memorized in the memory units 52-1 to 52-8 at a predetermined address distance which may be called an element distance. The input ports I(0) to I(3) of the switching network 55 are supplied from the first calculator 121 with the four array elements in the order assigned to them while the remaining input ports I(4) to I(7) are supplied from the second calculator 122 with the four array elements in a like manner. The processing circuit 115 supplies the control circuit 56 with a leading address signal (depicted at B) specifying a leading address to which a leading one of the array elements is delivered from the first and/or second calculators 121 and 122. Thus, the leading address serves as a reference address and therefore may be referred to as reference information. In addition, the processing circuit 115 gives the control circuit 56 an address distance signal D indicative of the predetermined address distance of each array element from the preceding one of the array elements. Thus, the address distance signal D is representative of a displacement component between two adjacent ones of the array elements and therefore carries displacement information. Like in Fig. 1, the leading address signal B and the address distance signal D may be specified by three bits and are represented by b₀b₁b₂ and d₀d₁d₂, respectively. Furthermore, the illustrated processing circuit 115 produces first and second condition signals CS₁ and CS₂ for standing for conditions or situations of the first and second calculators 121 and 122. Specifically, the first condition signal CS₁ specifies active one or ones of the first and second calculators 121 and 122 by two bits. In this connection, the first condition signal CS₁ takes (11)₂ when both the first and second calculators 121 and 122 are in the active states. On the other hand, the first condition signal CS₁ takes (10)₂ when the first calculator 121 alone is active while it takes (01)₂ when the second calculator 122 alone is active. Thus, the first condition signal CS₁ is indicative of a structure of the calculation circuit 120 and 122 and therefore conveys structural information concerned with the calculation circuit 120. If each of the first and second calculators 121 and 122 is singly put into the active state, the memory 52 may be accessed two times by such a single calculator to deliver the eight array elements from the single calculator to the first through eighth memory units 52-1 to 52-8, respectively. In this connection, the second condition signal CS₂ is representative off the number of times or a repetition of accesses and is therefore valid only when a single one of the first and second calculators 121 and 122 is in the active state. In other words, the second condition signal CS₂ is neglected when the first condition signal CS₁ takes (11)₂. Referring to Figs. 28 and 29 together with Fig. 27, the control circuit 56 is similar in structure to that illustrated in Fig. 5 except that the third shift circuit 77 is connected to a control signal converter 125 operable in response to the first and second condition signals CS₁ and CS₂. An mentioned with reference to Figs. 3, 5, and 10, the third shift circuit 78 produces an output signal of four bits (h₀h₁h₂h₃)₂ which are arranged from the most significant bit h₀ to the least significant bit h₃ and which are successively delivered to the ninth through twelfth switch units SW₉ to SW₁₂ in order, respectively. The control signal converter 125 is operable to convert, the four bits h₀h₁h₂h₃ of the output signal sent from the third shift circuit 77 to the ninth through twelfth control signals S₉ to S₁₂ in compliance with a conversion logic shown in Fig. 29. As shown in Fig. 29, the four, bits h₀h₁h₂h₃ of the output signal of the third shift circuit 78 are produced as the ninth through twelfth control signals S₉ to S₁₂ as they stand when the first condition signal CS₁ takes (11)₂. On the other hand, the four bits h₀h₁h₂h₃ are reversed in polarity to be produced as the ninth through twelfth control signals S₉ to S₁₂ when the first condition signal CS₁ takes (10)₂ or (01)₂. In Figs. 27 and 28, let the leading address signal B specify the second address (2)₁₀, namely, (010)₂ and the address distance signal D be indicative of the address distance of (3)₁₀, namely, (011)₂. In addition, the first condition signal CS₁ is assumed to be equal to (11)₂. Furthermore, it is surmised that the first calculator 121 delivers four array elements (depicted at D₁ to D₄) to the input ports I(0) to I(3) of the switching network 55, respectively, and that the second calculator 122 also delivers four array elements (depicted at D₅ to D₈) to the respective input ports I(4) to I(7). In this event, the eight array elements D₁ to D₈ are to be stored in a sequence of addresses 2, 5, 8, 11, 14, 17, 20, and 23 which are allocated to the respective memory units 52-3, 52-6,- 52-1, 52-4, 52-7, 52-2, 52-5, and 52-8, as seen from Fig. 2(A). Therefore, the input ports I(0) to I(7) are to be connected through the switching network 55 to the respective output ports O(2), O(5), O(0), O(3), O(6), O(1), O(4), and O(7). The control circuit 56 illustrated in Figs. 27 and 28 is operable in response to the leading address signal B, the address distance signal D, and the first and second condition signals CS₁ and CS₂. Inasmuch as the first condition signal CS₁ take (11)₂, the second condition signal CS₂ may be left out of consideration, as mentioned before. The address distance signal D is delivered to the first through third decoders 71 to 73 which produce the first decoded signal C0 of two bits C0₀ and C0₁, the second decoded signal C1 of five bits C1₀, C1₁, C1₂, C1₃, and C1₄, and the third decoded signal C2 of eleven bits C2₀ to C2₁₀, as shown in Fig. 6. In the example being illustrated, the two bits C0₀ and CO₁ of the first decoded signal C0 take (10)₂. Since the address distance (D) is equal to (011)₂, the five bits C1₀ to C1₄ of the second decoded signal C1 take (11001)₂, respectively, while the eleven bits C2₀ to C2₁₀ take (01011010010)₂, respectively, as readily understood from Figs. 6 and 7. The above-mentioned first through third decoded signals C0, C1, and C2 are sent to the first through third shift circuits 76 to 78 which are supplied from the shift number calculator 74 with the first through third shift signals SH₁ to SH₃, respectively. In the example being illustrated, the first through third shift signals SH₁ to SH₃ are represented by (0)₂, (10)₂, and (010)₂, respectively, because the address distance (D) is equal to (010)₂. Under the circumstances, the first shift circuit 76 produces the logic "0" level signal as the first through fourth control signals S₁ to S₄ by selecting the bit C0₁ of the first decoded signal C0, as seen from Fig. 8. The second shift circuit 77 produces the logic "1" level signal as the fifth and sixth control signals S₅ and S₆ and the logic "0" level signal as the seventh and eighth control signals S₇ and S₈ by selecting the bits C1₁ and C1₂, respectively, in the manner described with reference to Fig. 9. The third shift circuit 78 selects the four bits C2₅, C2₆, C2₇, and C2₈ of the third decoded signal C2 in the manner described in conjunction with Figs. 7(C) and 10. The above-mentioned four bits take (0100)₂ when the address distance (D) is equal to (3)₁₀, as shown in Fig. 7(C), and are produced as the output signal of the four bits h₀h₁h₂h₃. The four bits h₀h₁h₂h₃ are sent to the control signal converter 125 responsive to the first and second condition signals CS₁ and CS₂. As shown in Fig. 29, the control signal converter 125 allows the four bits h₀h₁h₂h₃ to pass therethrough as the ninth through twelfth control signals S₉ to S₁₂ when the first condition signal CS₁ takes (11)₂. As a result, the ninth through twelfth control signals S₉ to S₁₂ take (0100)₂, respectively. Thus, the first through fourth control signals S₁ to S₄, the fifth through eighth control signals S₅ to S₈, and the ninth through twelfth control signals S₉ to S₁₂ are represented by (0000)₂, (1100)₂, and (0100)₂, respectively. Referring to Fig. 30, the switching network 55 forms internal paths in response to the first through twelfth control signals S₁ to S₁₂ mentioned above. As shown in Fig. 30, the array elements D₁ to D₄ given from the first calculator 121 (Fig. 27) are delivered to the output ports O(2), O(5), O(0), and O(3), respectively, while the array elements D₅ to D₈ are delivered to the output ports O(6), O(1), O(4), and O(7), respectively. Thus, the eight array elements D₁ to D₈ can certainly be stored in the respective memory addresses 2, 5, 8, 11, 14, 17, 20, and 23 in order. It is assumed that the first condition signal CS₁ takes (10)₂ and therefore the first calculator 121 alone is usable. In addition, let the leading address (B) and the address distance (D) be (2)₁₀ and (3)₁₀ to access the memory addresses 2, 5, 8, 11, 14, 17, 20, and 23, respectively, like in the above-mentioned example. The first calculator 121 simultaneously produces four array elements one at a time, as mentioned before. Therefore, the first calculator 121 can produce at first four preceding array elements (D₁ to D₄) to be delivered to the memory addresses 2, 5, 8, and 11 and thereafter produces, for the second time, four succeeding array elements (D₅ to D₈) to be delivered to the memory addresses 14, 17, 20, and 23, when the second calculator 122 is inactive. Such preceding and succeeding array elements are delivered through the input ports I(0) to I(3) in common. In this event, the input ports I(0) to I(3) may at first be connected to the output ports O(2), O(5), O(0), and O(3) and thereafter to the output ports O(6), O(1), O(4), and O(7). Thus, only the input ports I(0) to I(3) are enabled in the illustrated example and may be called an enabled input port set. The leading address signal B and the address distance signal D may be invariable on delivery of the preceding and the succeeding array elements. Delivery of the preceding array elements will be referred to as first delivery while delivery of the succeeding array elements, second delivery. In order to carry out the first and second deliveries, it is necessary to distinguish between the first and second deliveries. The second condition signal CS₂ serves to distinguish between the first and second deliveries and takes (0)₂ on the first delivery or (1)₂ on the second delivery. In Fig. 28, the first and second control signals CS₁ and CS₂ are supplied from the processing circuit 115 to the control signal converter 125. On the first delivery of the preceding array elements, the control signal converter 125 produces the four bits h₀h₁h₂h₃ of the output signal given from the third decoder 78 because of CS₂ = (0)₂ and CS₁ = (10)₂. Inasmuch as the four bits h₀h₁h₂h₃ are equal to (0100)₂ when B = 2 and D = 3, as mentioned before, the ninth through twelfth control signals S₉ to S₁₂ are represented by (0100)₂, respectively. The remaining first though eighth control signals S₁ to S₈ are also identical with those described in the above-mentioned example and are represented by (00001100)₂. Therefore, the switching network 55 forms internal paths identical with those illustrated in Fig. 30. On the second delivery of the succeeding array elements, the control signal converter 125 inverts the four bits h₀h₁h₂h₃ into h ₀ h ₁ h ₂ h ₃ to produce the four inverted bits as the ninth through twelfth control signals S₉ to S₁₂. Therefore, the ninth through twelfth control signals S₉ to S₁₂ are turned into (1011)₂, respectively. The first through eighth control signals S₁ to S₈ are kept unchanged on the second delivery. Referring to Fig. 31, the first through twelfth switch units SW₁ to SW₁₂ forms internal paths in response to the above-mentioned first through twelfth control signals S₁ to S₁₂ on the second delivery of the succeeding array elements D₅ to D₈. As shown in Fig. 31, paths of the ninth through twelfth switch units SW₉ to SW₁₂ are switched from those illustrated in Fig. 30 and the four succeeding array elements D₄ to D₇ are given to the output ports O(6), O(1), O(4), and O(7), respectively. Similar operation is carried out in accordance with the algorithm illustrated in Fig. 29 when the second condition signal CS₂ takes (01)₂. For example, if B = 2 and D = 3, the internal paths are formed in the switching network 55 in the manner illustrated in Fig. 31 on the first delivery and in the manner illustrated in Fig. 30 on the second delivery. Thus, the output ports connected to the first calculator 121 alternates with the output ports connected to the second calculator 122, if the leading address (B) and the address interval (D) are invariable. Referring to Fig. 32, a circuit arrangement according to a fifth embodiment of this invention is similar to that illustrated in, Fig. 1 except that the control circuit 56 (Fig. 32) is operable in response to an input port number signal N, as will presently become clear, in addition to reference or leading information and displacement or distance information. In the example being illustrated, eight array elements can be given to consecutive ones of the input ports I(0) to I(7), respectively, in a manner as exemplified in Fig. 27. A leading one of the array elements is, assigned to a leading one of the output ports while two adjacent ones of the array elements are given to two consecutive ones of the input ports and are delivered to two of the output ports remote from each other at a port interval. Under the circumstances, the reference information is specified by a leading output port number assigned to the leading output port while the distance information is specified by the port interval. The leading output port number and the port interval are given from the central processing unit 51 (not shown in this figure) to the control circuit 56 in the form of a leading port signal B of b₀b₁b₂ and a port interval signal D of d₀d₁d₂, respectively, as are the cases with the other embodiments. In this connection, the input port number signal N is indicative of an input port number assigned to an input port which is connected to the leading output port and is represented by a binary representation of three bits (n₀n₁n₂)₂. Referring to Fig. 33 together with Fig. 32, the control circuit 56 is similar to that illustrated in Fig. 5 except that the first through third shift circuits 76 to 78 are connected to first through third Exclusive OR (EX-OR) circuits 131 to 133 and that the shift number calculator 74 (Fig. 5) is removed from Fig. 33. As shown in Fig. 33, the port interval signal D is supplied to the first through third decoders 71 to 73 to be decoded into the first, second, and third decoded signals C0, C1, and C2 in the manner described in conjunction with Figs. 5 and 6. The first through third decoded signals C0, C1, and C2 are formed by two bits C0₁ and C0₂, five bits C1₀ to C1₄, and eleven bits C2₀ to C2₁₀, respectively. The first through third shift circuits 76 to 78 selects one bit of the first decoded signal C0, two bits of the second decoded signal C1, and four bits of the third decoded signal C2 with reference to the leading output port number represented by the leading port signal B. Such operation of the first through third shift circuits 76 to 78 is similar to that illustrated with reference to Figs. 7 through 10. At any rate, first through third shift result signals are sent from the first through third shift circuits 76 to 78 to the first through third Exclusive OR circuits 131 to 133, respectively. The first through third shift result signals are similar to the control signals S₁ to S₁₂ illustrated in conjunction with Figs. 8 to 10 and may therefore be of a single bit (x₀)₂, two bits (y₀y₁)₂, and four bits (z₀z₁z₂z₃)₂, respectively. The first through third shift result signals may be called first through third intermediate signals and are subjected to further processing by the first through third Exclusive OR circuits 131 to 133, respectively. Specifically, the first Exclusive OR circuit 131 is supplied with the single bit x₀ of the first shift result signal and the least significant bit n₂ of the input port number signal N and performs Exclusive OR operation to produce the first through fourth control signals S₁ to S₄. Accordingly, the first through fourth control signals S₁ to S₄ are given by: S i = z₀ ⊕ n₂ (3) where i is representative of either one of 1, 2, 3, and 4. The first through fourth control signals S₁ to S₄ are delivered to the first through fourth switch units SW₁ to SW₄ in parallel. The second Exclusive OR circuit 132 is supplied with the two bits y₀y₁ of the second result signal and the least significant bit but one n₁ of the input port number signal N to perform Exclusive OR operation and to produce the fifth through eighth control signals S₅ to S₈ given by: The fifth through eighth control signals S₅ to S₈ are sent to the fifth through eighth switch units SW₅ to SW₈ in parallel, respectively. The third Exclusive OR circuit 133 is operable in response to the four bits x₀x₁x₂x₃ and the most significant bit n₀ of the input port number signal N to perform Exclusive OR operation and to produce the ninth through twelfth control signals S₉ to S₁₂ given by: The ninth through twelfth control signals S₉ to S₁₂ are sent to the ninth through twelfth switch units SW₉ to SW₁₂ in parallel. Operation of the circuit arrangement illustrated in Figs. 32 and 33 will be described on condition that the input ports I(0) to I(7) are to be connected to the output ports O(0), O(3), O(6), O(1), O(4), O(7), O(2), and O(5) in order, respectively. Thus, the leading output port O(0) is to be connected to the input port I(0) while the two consecutive ones of the input ports are supplied with two of the array elements which are to be delivered to two of the output ports remote from each other by three. Therefore, the port interval signal D is representative of (3)₁₀, namely, (011)₂. In this event, the leading port signal B specifies the output port O(0) and is represented by (000)₂. Likewise, the input port number signal N specifies the input port I(0) and is therefore represented by (000)₂. Responsive to the port interval signal D, the first through third decoders 71 to 73 produces the first decoded signal C0 of (10)₂, the second decoded signal C1 of (11001)₂, and the third decoded signal C2 of (01011010010)₂ in compliance with the algorithm shown by Figs. 7(A), (B), and (C). Supplied with the leading port signal B of (000)₂, the first through third shift circuits 76 to 78 carry out no shift and select the lower bit (0)₂ of the first decoded signal C0, the two lower bits (01)₂ of the second decoded signal C1, and the four lower bits (0010)₂ of the third decoded signal C2 to produce (0)₂, (01)₂, and (0010)₂ as the first through third intermediate signals, respectively. The first-Exclusive OR circuit 131 carries out calculation of (0 ⊕ 0) in accordance with Equation (3) to produce the logic "0" level as the first through fourth control signals S₁ to S₄. The second Exclusive OR circuit 132 carries out calculation in accordance with Equations (4) to produce the fifth and sixth control signals S₅ and S₆ and the seventh and eighth control signals S₇ and S₈. Each of the fifth and sixth control signals S₅ and S₆ is equal to (0)₂ because y₀ = 0 and n₁ = 0. On the other hand, each of the seventh and eighth control signals S₇ and S₈ is equal to (1)₂ because y₁ = 1 and n₁ = 0. Likewise, the third Exclusive OR circuit 133 carries out calculation in accordance with Equations (5) to produce the ninth through twelfth control signals S₉ to S₁₂. Inasmuch as x₀ = 0, x₁ = 1, x₂ = 0, x₃ = 0, and n₀ = 0, the ninth through twelfth control signals S₉ to S₁₂ are given by (0010)₂, respectively. Thus, the first through fourth control signals S₁ to S₄, the fifth through eighth control signals S₅ to S₈, and the ninth through twelfth control signals S₉ to S₁₂ become (0000)₂, (0011)₂, and (0010)₂, respectively. Referring to Fig. 34, the switching network 55 is controlled by the first through twelfth control signals S₁ to S₁₂ mentioned above and forms internal paths as illustrated in Fig. 34. The illustrated internal paths certainly connect the consecutive input ports I(0) to I(7) to the output ports O(0), O(3), O(6), O(1), O(4), O(7), O(2), and O(5), respectively. When the port interval (D) is equal to an even number, such as (2)₁₀ and (6)₁₀, any conflict of internal paths objectionably occurs like in Fig. 21. In order to avoid such an objectionable conflict, the illustrated circuit arrangement 50 successively connects a part of the input ports to the output ports in a time division fashion, as will be described below. Briefly, the leading port signal B and the input port signal N are varied at every machine cycle in a manner to be described with the port interval signal D kept unchanged, if the port interval (D) is equal to an even number. Let the port interval signal D be equal to (6)₁₀, namely, (110)₂. In addition, it is assumed that the leading port signal B and the input port signal N are represented by (000)₂ and (000)₂ at a first one of the machine cycles, respectively. The leading output port number represented by the leading port signal B is increased by (6)₁₀ at every machine cycle while the input port number represented by the input port signal N is increased by one at every machine cycle, as will become clear later. During the first machine cycle, the first through third decoders 71 to 73 (Fig. 33) produce the first decoded signal, C0 of (10)₂, the second decoded signal C1 of (11001)₂, and the third decoded signal C2 of (11110000111)₂, respectively. Responsive to the above-mentioned first through third decoded signals C0, C1, and C2, the first through third shift circuits 76 to 78 produce the first through third intermediate signals of (0)₂, (01)₂, and (0111)₂, respectively. Under the circumstances, the first Exclusive OR circuit 131 gives the first through fourth control signals S₁ to S₄ each of which takes (0)₂. Likewise, the second Exclusive OR circuit 132 produces the fifth and sixth control signals S₅ and S₆ of (0)₂ and the seventh and the eighth control signals S₇ and S₈ of (1)₂ while the third Exclusive OR circuit 133 produces the ninth control signal S₉ of (0)₂, the tenth control signal S₁₀ of (1)₂, the eleventh control signal S₁₁ of (1)₂, and twelfth control signal S₁₂ of (1)₂. Referring to Fig. 35, the first through twelfth switch units SW₁ to SW₁₂ connect the input ports I(0) to I(7) to the output ports O(0) to O(7) in response to the above-mentioned first through twelfth control signals S₁ to S₁₂, respectively. As shown in Fig. 35, the input port I(0) is certainly connected to the output port O(0). During a second one of the machine cycles, the leading port number (B) is changed to (6)₁₀, namely, (110)₂ while the input port number (N) is changed to (1)₁₀, namely, (001)₂, with the port interval (D) of (6)₁₀ kept unchanged. In this event, the first through third decoded signals C0, C1, and C2 are identical with those produced during the first machine cycle and are given by (10)₂, (11001)₂, and (11110000111)₂, respectively. The first shift circuit 76 carries out no shift operation in response to the least significant bit (0)₂ of the leading port signal B and extracts the least significant bit (0)₂ from the first decoded signal C0. The second shift circuit 77 shifts the second decoded signal C1 by two bits rightwards and extracts two lower bits (10)₂ from a shift result signal. The third shift circuit 78 shifts the third decoded signal C2 by six bit rightwards and extracts four lower bits (1110)₂ from a shift result signal. The first through third Exclusive OR circuits 131 to 133 perform the Exclusive OR operations in compliance with Equations (3), (4), and (5). As a result, the first through fourth control signals S₁ to S₄ become equal to (1)₂. The fifth and sixth control signals S₅ and S₆ become equal to (1)₂ while the seventh and eighth control signals become equal to (0)₂. On the other hand, the ninth through twelfth control signals S₉ to S₁₂ take (1110)₂, respectively. Referring to Fig. 36, the first through twelfth switch units SW₁ to SW₁₂ are controlled by the first through twelfth control signals S₁ to S₁₂ of (1111)₂, (1100)₂, and (1110)₂, respectively, so as to form internal paths in the switching network 55. As shown in Fig. 36, the input port I(1) is connected to the output port O(6) during the second machine cycle. During a third one of the machine cycles, the leading port number (B) is changed to (4)₁₀, namely, (100)₂ in consideration of the port interval (6)₁₀ while the input port number (N) is changed to (2)₁₀, namely, (010)₂. Inasmuch as the port interval (D) of (6)₁₀ is kept unchanged, the first through third shift circuits 76 to 78 are supplied from the first through third decoders 71 to 73 with the first through third decoded signals C0 to C2 identical with those produced during the first and second machine cycles. The first through third shift circuits 76 to 78 produce the first through third intermediate signals in response to the least significant bit b₂, the two lower bits b₁b₂ and the three bits b₀b₁b₂ of the leading port signal B in a similar manner. As a result, the first and the second intermediate signals take (0)₂ and (01)₂, respectively, while the third intermediate signal takes (1000)₂. Responsive to the first intermediate signal of (0)₂ and the least significant bit n₂ of (0)₂, the first Exclusive OR circuit 131 performs the Exclusive OR operation to produce the first through fourth control signals S₁ to S₄ of (0)₂. Likewise, the second Exclusive OR circuit 132 produces the fifth and sixth control signals S₅ and S₆ of (1)₂ in response to the higher bit (0)₂ of the second intermediate signal and the bit n₁ of (1)₂ and also produces the seventh and eighth control signals S₇ and S₈ of (0)₂ in response to the lower bit (1)₂ of the second intermediate signal and the bit n₁ of (1)₂. In addition, the third Exclusive OR circuit 133 produces the ninth through twelfth control signals S₉ to S₁₂ which are represented by (1000)₂ in accordance with Equations (5). Referring to Fig. 37, internal paths are illustrated which are formed in the switching network 55 in response to the first through fourth control signals S₁ to S₄ of (0)₂, the fifth and sixth control signals S₅ and S₆ of (1)₂, the seventh and eighth control signals S₇ and S₈ of (0)₂, and the ninth through twelfth control signals S₉ to S₁₂ of (1000)₂. As shown in Fig. 37, the input port I(2) is certainly connected to the output port O(4) during the third machine cycle. Similar operation is successively carried out at every machine cycle with the leading port number (B) and the input port number (N) changed in the above-mentioned manner and with the port interval (D) kept unchanged. In the example being illustrated, a single one of the input ports is connected to one of the output ports at every machine cycle in a time division fashion. However, two or four input ports may simultaneously be connected to the corresponding output ports in a time division fashion, unless such connections give rise to conflict of internal paths. Referring to Fig. 38, a circuit arrangement 50 according to a sixth embodiment of this invention comprises a switching network 55' which is similar to that illustrated in Fig. 23. As shown in Fig. 38, the switching network 55' comprises the input ports I(0) to I(7), the output ports O(0) to O(7), and the first through twelfth switch units SW₁ to SW₁₂ placed between the input and output ports in the manner already described in conjunction with Fig. 23. The circuit arrangement 50 illustrated in Fig. 38 is similar in operation to that illustrated in Fig. 32. However, it is to be noted here that eight array data or elements are delivered to consecutive ones of the output ports O(0) to O(7) in order and that a leading one of the array elements is delivered to a leading one (for example, O(0)) of the output ports from a leading input port which may be either one of the input ports I(0) to I(7). In addition, two consecutive ones of the array elements are given to two of the input ports remote from each other by an input port interval. In this connection, a leading input port number assigned to the leading input port is indicated by a leading port signal depicted at B like in Fig. 32 while the input port interval is represented by a port interval signal depicted at D like in Fig. 32. Thus, the leading port signal B and the port interval signal D serve as reference information and distance information, respectively. Moreover, an output port number signal (depicted at N) is also given to the illustrated circuit arrangement 50 and is representative of an output port number assigned to the leading output port which is to be connected to the leading or reference input port. From this fact, it is to be understood that the leading output port may be changed in the illustrated circuit arrangement. In the illustrated example, the leading port signal B, the port interval signal D, and the output port number signal N can be represented by b₀b₁b₂, d₀d₁d₂, and n₀n₁n₂, respectively, because the number of each of the input and output ports is equal to eight. Supplied with the leading port signal B, the port interval signal D, and the output port number signal N, a control circuit 56 carries out operation in a manner similar to that illustrated in Fig. 32 to supply the first through twelfth control signals S₁ to S₁₂ to the switching network 55'. Referring to Fig. 39 together with Fig. 38, the control circuit 56 comprises first through third decoders 71' to 73', first through third shift circuits 76' to 78', and first through third Exclusive OR circuits 131' to 133'. In Fig. 39, the first decoder 71', the first shift circuit 76', and the first Exclusive OR circuit 131' are similar in operation to the third decoder 73, the third shift circuit 78, and the third Exclusive OR circuit 133 (Fig. 33), respectively, and serve to produce the first through fourth control signals S₁ to S₄. The second decoder 72', the second shift circuit 77', and the second Exclusive OR circuits 132' are similar to the second decoder 72, the second shift circuit 77, and the second Exclusive OR circuit 132 (Fig. 33), respectively, and serve to produce the fifth through eighth control signals S₅ to S₈. The third decoder 73', the third shift circuit 78', and the third Exclusive OR circuit 133' are similar to the first decoder 71, the first shift circuit 76, and the first Exclusive OR circuit 131 (Fig. 33), respectively, and serve to produce the ninth through twelfth control signals S₉ to S₁₂. From this fact, it is readily understood that the first decoder 71' (Fig. 39) decodes the port interval signal D into a first additional decoded signal of eleven bits in a manner shown in Fig. 7(C) while the second and third decoders 72' and 73' (Fig. 39) produce a second additional decoded signal of five bits and a third additional decoded signals of two bits in accordance with Figs. 7(B) and 7(A), respectively. For convenience of description, the first through third additional decoded signals will be indicated at C2, C1, and C0, respectively. The first through third shift circuits 76' to 78' are operated in the manners described in conjunction with the third through first shift circuits 78 to 76 illustrated in Fig. 33 to produce a first intermediate signal of four bits x₀x₁x₂x₃, a second intermediate signal of two bits y₀y₁, and a third intermediate signal of a single bit z₀, respectively. The first Exclusive OR circuit 131' is supplied with the four bits x₀x₁x₂x₃ and the most significant bit n₀ of the port number signal N to produce the first through fourth control signals S₁ to S₄ given by: Likewise, the second Exclusive OR circuit 132' produces the fifth through eighth control signals S₅ to S₈ given by: The third Exclusive OR circuit 133' produces the ninth through twelfth control signals S₉ to S₁₂ given by: S₉, S₁₀, S₁₁, S₁₂ = z₀ ⊕ n₂. (8) The first through twelfth control signals S₁ to S₁₂ are delivered to the respective switch units SW₁ to SW₁₂. It is assumed that the consecutive output ports O(0) to O(7) are connected to the input ports I(0), I(3), I(6), I(1), I(4), I(7), I(2), and I(5) in order, respectively. In this case, the leading port signal B indicates the input port number (0)₁₀ assigned to the input port I(0) while the port number signal N indicates the leading output port number(0)₁₀ assigned to the leading output port O(0) which is to be connected to the input port I(0). In addition, the port distance signal D indicates the port interval (3)₁₀, namely, (011)₂. Under the circumstances, the first decoder 71' decodes the port distance signal D of (011)₂ into the first additional decoded signal C2 of (01011010010)₂, as shown in Fig. 7(C). The second and the third decoders 72' and 73' decodes the port distance signal D of (011)₂ into the second additional decoded signal C1 of (11001)₂ and into the third additional decoded signal C0 of (10)₂ in accordance with Figs. 7(B) and 7(A), respectively. Responsive to the leading port signal B and the above-mentioned first additional decoded signal C2, the first shift circuit 71' is operated in the manner described in conjunction with the third shift circuit 73 (Fig. 33). Since B = (000)₂, the first shift circuit 71' carries out no shift operation and extracts four lower bits (0010)₂ from the first additional decoded signal C2. In a similar manner, the second and the third shift circuits 72' and 73' extract two lower bits (01)₂ and a single lower bit (0)₂ from the second and the third decoded signals, respectively. The first Exclusive OR circuit 131' performs the Exclusive OR operation in accordance with Equations (6) to produce the first through fourth control signals S₁ to S₄ which are represented by (0010)₂, respectively. The second Exclusive OR circuit 132' produces the fifth and sixth control signals S₅ and S₆ of (0)₂ and the seventh and eighth control signals S₇ and S₈ of (1)₂ in accordance with Equations (7). Likewise, the third Exclusive OR circuit 133' produces the ninth through twelfth control signals S₉ to S₁₂ of (0)₂ in compliance with Equation (8). Referring to Fig. 40, the first through twelfth switch units SW₁ to SW₁₂ are controlled by the corresponding control signals mentioned above to form internal paths in the switching network 55. As shown in Fig. 40, the consecutively numbered output ports O(0) to O(6) are actually connected from the input port I(0) to the input port I(5) at the port interval of (3)₁₀. Like in Fig. 32, an objectionable conflict takes place in internal paths when the port interval (D) is equal to an even number, such as 2, 6. In the example being illustrated in Fig. 38, a single one of the output ports is successively connected to a single one of the input ports in a time division fashion as described in conjunction with Figs. 35 to 37. Such operation is possible by renewing the leading port signal B and the output port number signal N at every machine cycle with the port interval signal D kept unchanged, like in Figs. 35 to 37. More particularly, let the port interval (D) be equal to (6)₁₀, namely, (110)₂. The leading port number (B) and the input port number (N) are assumed to be (000)₂ and (000)₂ during a first one of the machine cycles. In this event, the first through third decoded signals C2, C1, and C0 are given by (11110000111)₂, (11001)₂, and (10)₂ from which the first through third intermediate signals of (0111)₂, (01)₂, and (0)₂ are extracted by the first through third shift circuits 76' to 78', respectively. Inasmuch as the output port number signal N specifies (000)₂, the first Exclusive OR circuit 131' produces the first through fourth control signals S₁ to S₄ of (0111)₂ while the second Exclusive OR circuit 132' produces the fifth and sixth control signals S₅ and S₆ of (0)₂ and the seventh and eighth control signals S₇ and S₈ of (1)₂. Similarly, the ninth through twelfth control signals S₉ to S₁₂ become equal to (0)₂. Referring to fig. 41, the above-mentioned first through twelfth control signals S₁ to S₁₂ connect the input ports to the output ports in the illustrated manner during the first machine cycle. As shown in Fig. 41, the above-mentioned control signals assure a connection between the input port I(0) and the output port O(0). Therefore, the leading array element can be delivered from the input port I(0) to the output port O(0) during the first machine cycle. Subsequently, the leading port number (B) and the output port number (N) are renewed at a second one of the machine cycles to be changed to (110)₂ and (001)₂, respectively. The first through third shift circuits 76' to 78' are supplied with the leading port number (B) of (110)₂ and with the first through third additional decoded signals C2, C1, and C0 identical with those described in conjunction with the first machine cycle. The first shift circuit 76' shifts the first additional decoded signal by six bits rightwards to extract four lower bits from a shifted result and to produce the first intermediate signal of (1110)₂. The second shift circuit 77' produces the second intermediate signal of (10)₂ by shifting (11001)₂ by two bits rightwards to form an additional shifted result and by extracting two lower bits from the additional shifted result. The third shift circuit 78' produces the third intermediate signal of (0)₂ by carrying out no shift of (10)₂ and by selecting the least significant bit of the third additional decoded signal C0. As a result, the first through third Exclusive OR circuits 131' to 133' give the first through fourth control signals S₁ to S₄ of (1110)₂, the fifth through eighth control signals S₅ to S₈ of (1100)₂, and the ninth through twelfth control signals S₉ to S₁₂ of (1)₂. Referring to Fig. 42, the switching network 55 connects the input ports I(0) through I(7) to the output ports O(0) through O(7) in response to the above-mentioned control signals. As is apparent from Fig. 42, the output port O(1) is connected to the input port I(6) spaced from the input port I(0) by the port interval of (6)₁₀. Thus, a second one of the array elements can be delivered from the input port I(6) to the output port O(1) during the second machine cycle. During a third one of the machine cycles, the leading port number (B) and the output port number (N) are changed to (4)₁₀, namely, (100)₂ and (2)₁₀, namely, (010)₂, with the port interval (D) kept unchanged. In this event, the first through third shift circuits 76' to 78' produce (1000)₂, (01)₂, and,(0)₂ as the first through third additional decoded signals in the above-mentioned manner. Supplied with the output port number (N) of (010)₂ and with (1000)₂, (01)₂, and (0)₂, the first through third Exclusive OR circuits 131' to 133' produce the first through fourth control signals S₁ to S₄ of (1000)₂, the fifth through eighth control signals S₅ to S₈ of (1100)₂, and the ninth through twelfth control signals S₉ to S₁₂ of (0000)₂ so as to form internal paths illustrated in Fig. 43. As shown in Fig. 43, the output port O(2) is assuredly connected to the input port I(4) during the third machine cycle. Similar connection is made in a time division fashion to successively connect the input ports at the port interval of (6)₁₀. Two or four input ports can be connected to two of the output ports in a time division fashion, if no conflict takes place in internal paths. While this invention has thus far been described in conjunction with several embodiments thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, the number of each of the input ports and the output ports may be restricted to eight. Each memory unit 52-1 to 52-8 may be replaced by an array processor or the like.

Claims: A circuit arrangement (50) comprising a switching network (55) which has two sets of consecutively numbered input and output ports (I1-I8 and O1-O8); whereby either the input port set or the output port set include a predetermined reference port (B), and whereby each output port can be connected to every one of said input ports through internal paths formed in said switching network by varying said predetermined reference port and a predetermined port interval (D); the connection between input and output ports is such that said reference port (B) is connected to the leading one of the numbered ports of the other set (I1 or O1), while the consecutive ones of said numbered ports of the other set are respectively connected to the ports determined by cumulatively adding said port interval to said reference port; and characterised in that a control circuit (56) is coupled to said switching network (55) for delivering the control signals (S1 to S12) that configure the network to form said internal paths, and whereby a first means (71, 76, 74) delivers first ones (S1 to S4) of said control signals being derived from the least significant bit (b2) of the identifier of said reference port, a second means (72, 77, 74) delivers second ones (S5 to S8) of said control signals being derived from the two least significant bits (b1, b2) of said reference port identifier and from the second most significant bit (d1) of said port interval, a third means (73, 78, 74, 73', 78', 125) delivers third ones (S9 to S12) of said control signals being derived from said reference port identifier (b1 to b3), from the two most significant bits (d0, d1) of said port interval and from indication signals specifying accessible ones of said output ports (GI) or of said input ports (CS1). A circuit arrangement as claimed in claim 1, wherein the signals transmitted through said switching network are address signals, said reference port identifier (B) is a leading address and said port interval (D) is an address distance. A circuit arrangement as claimed in Claim 1 or 2, wherein said control circuit (56) comprises: decoding means (71 to 73) for decoding said predetermined port interval (d₀, d₁) into a group of decoded signals (C0, C1, C2) in compliance with a preselected algorithm determined in relation to the port interval (D) of said switching network; and control signal producing means (76 to 78) coupled to said decoding means (71 to 73) for producing said control signal group (S₁ to S₁₂) in response to said decoded signal group (C0, C1, C2) and to said reference port (B). A circuit arrangement as claimed in Claim 3, wherein said control circuit (56) is operable to deliver said control signal group to said switching network at every prescribed interval of time; said reference port (B) of the selected port set and said leading port (I1 or O1) of the other port set being varied by said predetermined port interval (D) and by one, respectively, at every prescribed interval of time in a time division fashion, should said predetermined port interval otherwise bring about conflict among the internal paths. A circuit arrangement as claimed in Claims 1 to 4 wherein said selected port set is said output port set consecutively numbered from zero to M-1; each of said output ports being connected to an input port of a number I given by: O = (B + I x D) mod M, where O is representative of the number assigned to each of said output ports; B, the number of said reference port of the selected set; and D, said predetermined port interval. A circuit arrangement as claimed in any one of Claims 1 to 5, wherein said selected set is said input port set consecutively numbered from zero to M-1; each of said input ports being connected to an output port of a number O given by: I = (B + O x D) mod M, where I is representative of the number assigned to each of said input ports; B, the number of said reference port of the selected set, and D, said predetermined port interval. A circuit arrangement as claimed in any one of Claim 1 to 6, said circuit arrangement having a plurality of consecutively numbered circuit output ports (CO0 to CO7) which are to be connected to said output ports (O0 to O7) ; said control circuit (56) being for adjusting said predetermined port interval (D) to an adjusted port interval when a conflict otherwise occurs between said internal paths and being for producing an additional control signal variable (E) in dependency on said predetermined port interval; said circuit arrangement comprising: a rearranging circuit (105, 106, 107) intermediate between said output ports (O0 to O7) and said circuit output ports (CO0 to CO7) and coupled to said control circuit for rearranging connections between said output ports and said circuit output ports in response to said additional control signal when said predetermined port interval is adjusted to said adjusted port interval. A circuit arrangement as claimed in any one of Claims 1 to 7, said circuit arrangement having a plurality of consecutively numbered circuit input ports (CI0 to CI7) which are to be connected to said input ports (I0 to I7); said control circuit (56') being for adjusting said predetermined port interval (D) of said input ports to an adjusted port interval when a conflict otherwise occurs between said internal paths and being for producing an additional control signal (E) variable in dependency upon said predetermined port interval; said circuit arrangement comprising: a rearranging circuit (105', 106', 107') intermediate between said input ports and said circuit input ports and coupled to said control circuit (56') for rearranging connections between said input ports and said circuit input ports in response to said additional control signal when said predetermined port interval is adjusted to said adjusted port interval. A circuit arrangement as claimed in any one of Claims 1 to 8, wherein said input ports are partially enabled to provide an enabled partial input port set; said control circuit being for delivering said control signals to said switching network in consideration of said enabled partial input port set. A circuit arrangement as claimed in Claim 9, wherein said enabled partial input port set is repeatedly connected to said output ports; said control circuit (56) being for delivering said control signals to said switching network with reference to said enabled partial input port set and a repetition of connection of said enabled partial input port set together with said reference port and said predetermined port interval.

Inventors: FURUI TOSHIYUKI, KADAIRA GIZO, KAJI NAOTO, KINOSHITA KOUJI, FURUI, TOSHIYUKI, KADAIRA, GIZO, KAJI, NAOTO, KINOSHITA, KOUJI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1986
Main classification: G06F12
IPC codes: G06F12