Liquid crystal device and method of driving same

Abstract: In a method of driving a liquid crystal panel using one horizontal period (1H) as a reversal period, the liquid crystal panel using a TFT as a switching element for driving the panel in units of divided blocks and comprising the block division TFT's (B-TFT), a matrix circuit for driving each block in time division, and a TFT active matrix panel; each block of the B-TFT's is further divided into two half-blocks and a control signal shifted in phase between adjacent two half-blocks is applied to time-divisionally drive the liquid crystal panel at superposed timings. High intensity lines produced at the intersection of blocks due to the charge sharing effect is eliminated to thereby enable a high quality of image.

Description: The present invention relates to a liquid crystal device in the form of a TFT active matrix panel apparatus, capable of suppressing high intensity lines produced while driving the device in units of blocks by using TFT's (thin film transistors) as switching elements. Document JP-A-59 221 183 (SEIKO EPSON KK.) discloses a liquid crystal video display device wherein an interlacing video display technique is utilized and scanning signals are provided to particular scanning electrode lines in sequential order, thereby providing an accurate video display on the basis of an active-matrix driving system using thin film transistors (TFT) or non-linear elements such as metal-insulator-metal (MIM) elements. To this end, scanning lines are interlaced in the manner in which a selective voltage is provided to every other scanning electrode during the scanning period, shifting in order by every other scanning electrode, and another selecting voltage is provided to the remaining scanning electrodes so that the period of providing this voltage to the scanning electrodes partly overlaps those of adjacent scanning electrodes both above and below. Under control of the horizontal synchronization of the video signal to be displayed, a shift register provides signals for selecting each scanning electrode in sequence by means of analog switches connected to each scanning line. Since the voltage signals being controlled to provide an overlapping period of time are sequentially applied to adjacent scanning electrodes, a flicker of the displayed video picture can be reduced, thereby obtaining an improved quality and a comfortable viewing of the picture. However, in such a known liquid crystal video display device wherein the activ matrix panel is divided into a plurality of blocks, an undesired interline capacitance exists between two adjacent internal signal lines. Due to this interline capacitance, voltages applied to two adjacent internal signal lines interfear with each other and cause an undesired variation of the resulting voltages on both internal video signal lines, if the voltages are different in magnitude. This disturbing effect appears between adjacent lines of different blocks of the active matrix panel and results from the charge sharing effect of the interline capacitance and leads to an unequal brightness of particular parts of the liquid crystal display. In particular, as shown in Fig. 3, in a conventional method of driving a liquid crystal panel having a TFT active matrix circuit, internal video signal lines of a display panel 1 are divided into a plurality of blocks. A matrix circuit 2 is provided for matrix-connection between the internal video signal lines of each block and external video signal lines having the same number of lines as the former lines. Sample/hold switching elements constructed of a B-TFT (block dividing TFT) array 3 are interposed on the respective internal video lines between the matrix circuit 2 and the display Panel 1. Control signals are supplied to the switching elements of each block to drive the display panel in time division using one horizontal period (1H) as a reversal period. Referring to Fig. 4 showing a detailed connection diagram of Fig. 3, external video signal lines D1, D2. ..., Dm are divided into m internal video signal lines S1, S2, ..., Sm per one block by the matrix circuit 2. In case of k blocks, the total number of video signal lines is m x k . Each of the internal video signal lines S1, S2 ..., Sm is grounded via a hold capacitor 10. Switching elements 11 interposed between the hold capacitor 10 and the matrix circuit 2 are driven in time division by respective block division gate drivers B1, B2, ..., Bk to output video signals to pixels. When a liquid crystal panel constructed as above is driven using one horizontal period (1H) as reversal period, a charge shift phenomenon of a so-called charge sharing effect occurs at the intersection between divided blocks, e.g., between lines Sm and S1 of Fig. 4, due to the capacitance between source lines of B-TFT's. As a result, a voltage ΔV is superposed on the video signal of line Sm so that a video signal having a larger voltage amplitude than the original video signal is output (with opposing electrode 12 being grounded). Fig. 5 illustrates the principle of the charge sharing effect, and Fig. 6 is a timing chart showing the charge sharing effect. In Fig. 5, a central broken line indicates the intersection between blocks, the block at the left of the line being called block 1 and that at the right being called block 2. The last signal line Sm of block 1 is driven by the output signal from the last source line Dm and the drive voltage B1 for the block division TFT's of block 1. The first signal line S1 of block 2 is driven by the output signal from the first source line D1 and the drive voltage B2 for the block division TFT's of block 2, source line capacitance Cm and C1 as seen from source terminal side of the block division TFT's, correspond to the video signal hold capacitor C. Interline capacitance Css producing ΔV appears between the source lines. Referring now to Fig. 6, when a gate pulse is applied to line B1, a video signal on line Dm is transferred to line Sm via the B-TFT to charge the source line capacitor Cm. After charging the source lines of block 1 to which the capacitor Cm belongs is completed, another gate pulse is applied to line B2 to thereby charge the source lines including line S1 of block 2. In this case, the charging waveforms on lines Sm and S1 at the intersection between the two blocks change as shown in Fig. 6. Particularly, ΔV shown by oblique lines is superposed on line Sm and its video signal becomes larger in amplitude than its original, while the video signal on line S1 changes at the start of reversal as shown by oblique lines. Such phenomenon results from the charge sharing effect of the source interline capacitance Css between the capacitors Cm and C1. The relationship between ΔV and V is approximately defined as in the following formula. ΔV ≒ Css/(C + Css) · V(v) (C = Cm ≒ C1) If a liquid crystal display panel as above is driven without any correction, the last lines Sm of the blocks are highly brightened so that it is quite unsuitable for a display device. It is the object of the present invention to solve the above problems and to provide a TFT active matrix panel apparatus wherein high intensity lines of blocks produced by the charge sharing effect during 1H reversal driving are suppressed thereby realizing a high quality of image. According to the invention this object is accomplished by a TFT active matrix panel apparatus provided with horizontal gate signal line electrodes, vertical video signal line electrodes and a drive unit for time-divisionally driving said vertical video signal line electrodes, said vertical video signal line electrodes being grouped into a plurality of blocks, and said drive unit comprising external video signal lines respectively connected through switching elements to the vertical video signal line electrodes in each block and control means for applying a control signal to the switching elements in each block so that the blocks of vertical video signal line electrodes are sequentially driven in a time-division drive fashion, said active matrix panel apparatus being characterized in that said control means comprises a fore part control line of energizing the switching elements in the fore part of each block and a rear part control line of energizing the switching elements in the rear part of each block, and the control signal on said rear part control line in one block partly overlaps in time with the control signal on said fore part control line in the next block. Fig. 1 is a connection diagram showing the main part of the liquid crystal device in the form of a TFT active matrix panel apparatus according to an embodiment of the present invention; Fig. 2 is a timing chart showing the operation of the device of Fig. 1; Fig. 3 is a schematic block diagram showing the liquid crystal device according to the prior art; Fig. 4 is a timing chart showing the operation of the device of Fig. 3; Fig. 5 is an equivalent circuit illustrating the charge sharing effect; Fig. 6 is a timing chart showing the operation of the equivalent circuit; and Fig. 7 is an equivalent circuit during time-division driving. The charge sharing effect occurs during the time from when a pulse is applied to turn on the B-TFT's of one block and to when another pulse is applied to turn on the B-TFT's of the next block. In Fig. 5, during turning-off of the B-TFT at line B1, line Sm keeps a potential charged in the capacitor Cm and maintains open relative to the signal source such as the source line driver of Fig. 3. When a signal is applied during this open state to the B-TFT's of the next block 2 to turn them, line S1 is enabled to receive the signal from the signal source so that the capacitor C1 is charged. Simultaneously, the signal on line S1 charges the capacitor Css and its charge is transferred to and stored in the capacitor Cm. As a result, the waveform of line Sm changes by ΔV as shown in Fig. 6. Fig. 7 is an equivalent circuit wherein line Sm maintains open and the signal source 13 is coupled to line S1. In order to eliminate or decrease ΔV, it can be considered that isolation from the signal source and connection to the signal source should not be conducted simultaneously between the lines of adjacent blocks and that the capacitance value Css and V be made small. Since the capacitance value Css is determined from the panel configuration, the remaining factors to solve the problem of ΔV are switching timings and the value V. Paying attention to the switching timings, the present invention enables to make a potential difference between signals on lines Sm and S1 very small. Particularly, the B-TFT array of switching elements of each block is further divided into two half-blocks. A switching signal line is provided for each of the half-blocks, the phase of a control signal applied to the switching elements for each of the half-blocks is shifted between adjacent half-blocks to output video signals onto the internal video signal lines at superposed timings. The embodiment of the present invention will now be described in detail with reference to the accompanying drawings. Fig. 1 is a connection diagram showing the B-TFT's and matrix circuit embodying the present invention. In this embodiment, a same display panel as a conventional one shown in Fig. 3 is used. A TFT active matrix circuit constituting a display portion, B-TFT array and matrix circuit are fabricated on a single substrate. In Fig. 1, the total number of matrix wirings is 240 which are here identified as first half 120 wirings and latter half 120 wirings. Video signal lines of one block, i.e., panel source lines are connected to 240 bit B-TFT's. The panel source lines and B-TFT's are similarly identified as first half 120 ones and latter half ones. A control signal line for turning on and off the B-TFT's of the first 120 bits of block 1 is identified as "B1-first", while a control signal line for turning on and off the B-TFT's of the latter 120 bits of block 1 as "B1-latter". Similar identification is made up to "B8-latter". Thus, the total number of panel source lines is 8 x 240. The number of gate lines (scanning lines) is 480 and the panel corresponds to a TV screen of about 7 inches. Fig. 2 is a timing chart showing the operation of the liquid crystal device of Fig. 1 wherein an NTSC television signal is used as a video signal source. The television video signal is divided into eight portions which are assigned to blocks 1 to 8 as a video signal source of the display panel, each of the blocks being divided into the first half and the latter half. In the present invention, the divided video signal is processed by controlling the output timings of the source line driver as in the following. When image data of the first 120 bits of block 1 is input, this data is output on source lines D1 to D120. Simultaneously therewith, a pulse for turning on the B-TFT's of the first 120 bits is applied to control line "B1-first" to charge the first 120 source lines of block 1. Next, when image data of the latter 120 bits of block 1 is prepared, this data is output on source lines D121 to D240. Simultaneously therewith, a pulse for turning on the B-TFT's of the latter 120 bits is applied to control line "B1-latter" to charge the latter 120 source lines of block 1. The phase of the on/off control signals on "B1-first" and "B1-latter" and so on is shifted so as to superpose by 90 phase degree between adjacent two half-blocks. Similar timings of the control signals are repeated up to block 8 to write a 1H television signal on 1920 source lines. In this case, the liquid crystal (TN liquid crystal, ferroelectric liquid crystal) is ac-driven by grounding the opposing electrode or by reversing every 1H in synchronism with the television signal. In the above liquid crystal drive, the source line waveforms in the panel shown in Fig. 2, particularly the charge/discharge waveforms of the source lines S120 and S121 at the intersection of blocks, are observed. The potential difference V on the source line S121 is very small at the time when a pulse on "B1-first" for the fource line S120 of block 1 turns off. This V corresponds to the V of the above-described approximate formula. Therefore, ΔV in the formula becomes considerably small. The potential difference ΔV at the leading edge of the source line waveform shown in Fig. 2 becomes extremely small. One block of the above embodiment may be divided into three or more. As seen from the foregoing description of the present invention, even if the charge sharing effect occurs during 1H reversal drive, the resultant potential difference can be reduced to a minimum by driving the finely divided blocks at superposed timings. Further, in case the charge speed with a B-TFT is high, the potential difference can theoretically be made zero. Thus, it is possible to eliminate high intensity lines at the intersection of blocks and provide a liquid crystal device in the form of a TFT active matrix panel apparatus capable of obtaining a high image quality.

Claims: TFT active matrix panel apparatus provided with horizontal gate signal line electrodes (G), vertical video signal line electrodes (S) and a drive unit (2, 3) for time-divisionally driving said vertical video signal line electrodes (S), said vertical video signal line electrodes (S) being grouped into a plurality of blocks, and said drive unit comprising external video signal lines (D) respectively connected through switching elements (S) to the vertical video signal line electrodes (S) in each block and control means (B) for applying a control signal to the switching elements (S) in each block so that the blocks of vertical video signal line electrodes (S) are sequentially driven in a time-division drive fashion, said active matrix panel apparatus being characterized in that said control means (B) comprises a fore part control line (B-FIRST) of energizing the switching elements (S) in the fore part of each block and a rear part control line (B-LATTER) of energizing the switching elements (S) in the rear part of each block, and the control signal on said rear part control line (B1-LATTER) in one block partly overlaps in time with the control signal on said fore part control line (B2-FIRST) in the next block.

Inventors: INOUE HIROSHI, KANNO HIDEO, MIZUTOME ATSUSHI, YAMASHITA SHINICHI, INOUE, HIROSHI, KANNO, HIDEO, MIZUTOME, ATSUSHI, YAMASHITA, SHINICHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1986
Main classification: G09G3
IPC codes: G09G3, G02F1