SEMICONDUCTOR DEVICE

Abstract: Semiconductor device having pressure contact structure for high power use, in which main electrodes formed on a semiconductor chip of planar structure are in pressure contact by means of first and second electrode blocks (29, 30) connected to a package, wherein an electrode reinforcing plate (32) is interposed between said electrode (26) and electrode block (29).

Description: SPECIFICATION Semiconductor Device FIELD OF THE INVENTION The present invention relates to a semiconductor device having pressure contact, structure for use in high power application. BACKGROUND OF THE INVENTION Generally, in a semiconductor device for high power application requiring control of a large current, neither soldering nor wire-bonding method is used, but pressure contact structure is used as a method of forming electrodes, in view of such problems as thermal fatigue on the occasion of large current conduction. Fig. 1 is a cross-sectional view of a conventional thyristor having pressure contact structure, wherein 1 denotes an n-type base layer, 2 denotes a p-type base layer, 3 denotes an n-type emitter layer, 4 denotes a p-type emitter layer, 5 denotes an anode, 6 denotes a cathode, and 7 denotes a gate electrode, and the anode 5 is made of a metal plate such as molybdenum plate or a tungsten plate, having a coefficient of thermal expansion which is similar to that of silicon, and it is brazed to a silicon substrate in view of mechanical reinforcement on the occasion of pressure contact. 8 is an electrode connecting plate made of a molybdenum plate or a tungsten plate attached to said cathode 6, and 9 and 10 are electrode blocks of the anode side and the cathode side, respectively, coupled to a package, and the blocks are generally placed in pressure contact in the directions shown by the arrows. 11 is a surface covering made of an organic substance or the like such as polyimide vanish or silicone rubber, and J» and J 2 are junctions controlling a main breakdown voltage. Semiconductor devices of an ordinary pressure contact structure employ mesa structure having these junctions J 1 and J_ terminated at the side surface. The reason why mesa structure is used in a semiconductor device of a pressure contact structure is that, in the case of planar structure the breakdown voltage characteristic of the device may be deteriorated by contamination of an insulating film covering the planar junction in brazing the anode 5, while in the case of mesa structure, surface processing of the junctions is possible after the brazing. Conventional semiconductor devices of pressure contact structure as described above involve problems such that the quality of a device is hard to be stabilized as an organic substance such as polyimide vanish or silicone rubber is used as a surface covering, and, in addition, a process becomes complicated and operation efficiency is greatly impaired as the surface processing is carried out with an electrode connecting plate made of a molybdenum plate or a tungsten plate attached thereto. DISCLOSURE OF THE INVENTION A semiconductor device according to the present invention comprises a semiconductor device of pressure contact structure, in which first and second main electrodes formed on a semiconductor chip of planar structure are in pressure contact by means of electrode blocks of the first electrode side and the second electrode side, respectively, connected to a package, wherein an electrode reinforcing plate is interposed between said first electrode and the electrode block of the first electrode side, whereby the quality of the device can be stabilized, and a semiconductor device of pressure contacts structure of a simple manufacturing process and high operation efficiency can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a thyristor having conventional pressure contact structure; Fig. 2 is a cross-sectional view of a gate turn off thyristor (hereinafter referred to as "GTO") of one embodiment of a semiconductor according to the present invention; Fig. 3 is a cross-sectional view showing another embodiment of a semiconductor device according to the present invention; Fig. 4 is a cross-sectional view showing yet another embodiment of a semiconductor device according to the present invention. BEST MODES OF CARRYING OUT THE INVENTION The embodiments of this invention will be hereinafter described with reference to the drawings. Fig. 2 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention, wherein 21 is an n-type base layer, 22 is a p-type base layer, 25 are guardring regions, 26, 27 and 28 are anode, gate electrode and cathode, respectively, formed of a metal such as Al, these forming a semiconductor chip 20 having planar structure. 29 and 30 are electrode blocks of the anode side and the cathode side, respectively, 31 is an electrode connecting plate formed of molybdenum or tungsten, etc., mounted on said cathode 28, 32 is an anode reinforcing plate formed of molybdenum or tungsten, etc, interposed between said anode 26 and the electrode block 29 on the anode side. In this GTO, the mechanical stress upon pressure contact can be buffered by interposing the anode reinforcing plate 32 between the anode 26 and the electrode block 29 on the anode side and, therefore, conventional necessity of brazing the anode is eliminated. In particular, since the semiconductor chip 20 can be made in planar structure, passivation can be performed in a wafer state, whereby necessity of surface processing of a junction using an organic substance after the brazing of the anode, which is done in a semiconductor device having conventional mesa structure, is eliminated. Accordingly, the quality of a device can be stabilized, and in addition, the operation becomes easy, especially in the case of multi chip structure in which a number of elements are obtained by cutting out one wafer. Meanwhile, since this GTO is provided with guardring regions 25 to reduce the concentration of an electric field at a curved portion A of the junction, it provides a breakdown voltage which is close to that of mesa structure, although it has planar structure itself. The storage carriers in the n-type base layer 21 are caused to disappear as the p-type emitter region 24 and the n-type base layer 21 are short-circuited by the anode 26 to form an anode-emitter short-circuited structure, thereby enabling a rapid operation. Fig. 3 is a cross-sectional view of another embodiment of a semiconductor device of the present invention, which is designed to enhance a reverse directional breakdown voltage as well as a forward directional breakdown voltage: the structure of this embodiments has guardring regions 25 formed in the n-type base layer 21 which is adjacent to both sides of the p-type emitter layer 24 of the anode side. Fig. 4 is also a cross-sectional view of yet another embodiment of a semiconductor device of the present invention, which is designed to enhance a reverse directional breakdown voltage as well as a forward directional breakdown voltage: instead of forming guardring regions 25 in the anode side as in the above embodiment shown in Fig. 3, this embodiment being structured with both sides of the p-type emitter layer extended to the surface of the cathode side. Although the above embodiments were described with regard to GTO, this invention is not limited to this, and it may be applied to a common thyristor, a transistor, or a diode. In the case of a transistor, an anode in a GTO corresponds to a collector electrode, a cathode corresponds to a base electrode, and a gate electrode corresponds to an emitter electrode, respectively. As described above, since the present invention comprises an anode reinforcing plate interposed between an anode and an electrode block of the anode side of a semiconductor chip having planar structure, passivation can be done in a wafer state, and, since there is no necessity of surface processing of the junction using an organic substance, such meritorious effects are brought about that the devices can be stabilized, the manufacturing process becomes simple, and the operation efficiency is improved. POSSIBILITY OF INDUSTRIAL UTILIZATION The present invention is utilized in a semiconductor device for high power application, such as a thyristor, transistor, and a diode.

Claims: CLAIMS (1) A semiconductor device having pressure contact structure with first and second main electrodes formed on a semiconductor chip of planar structure, being in pressure contact by means of the electrode blocks on the sides of the first main electrode and the second main electrode, respectively, connected to a package, characterized in that an electrode reinforcing plate is interposed between said first main electrode and the electrode block of the first main electrode side. (2) A semiconductor device recited in claim (1) , wherein the electrode reinforcing plate is formed of molybdenum. (3) A semiconductor device recited in claim (1) wherein the electrode reinforcing plate is formed of tungsten. (4) A semiconductor device recited in claim (1) , wherein the semiconductor chip is a thyristor, and the first and second main electrodes are an anode and a cathode, respectively. (5) A semiconductor device recited in claim (1) , wherein the semiconductor chip is a transistor, and first and second main electrodes are a collector electrode and an emitter electrode, respectively. (6) A semiconductor device recited in claim (1) , wherein the semiconductor chip is a diode, and the first and second main electrodes are an anode and a cathode, respectively.

Inventors: HAGINO HIROYASU, HAGINO, HIROYASU;
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1986
Main classification: H01L23
IPC codes: H01L21, H01L23, H01L29