Bistable circuit

Abstract: A bistable circuit comprises a flip-flop including at least one clock input, and a plurality of data inputs at least one of which is supplied with a signal at a timing independent of clocks applied to the clock input. The flip-flop also includes first and second outputs. First and second insulated gate field effect transistors are series-connected between the first out­ put of the flip-flop and a predetermined voltage terminal. The first transistor is connected to receive at its gate a signal indic­ ative of the condition of a selected one of the two outputs of the flip-flop, and the second transistor is connected to receive at its gate a control signal. When the selected one of the out­ puts assume an intermediate voltage, the first transistor is ren­ dered conductive. In addition, the second transistor is ren­ dered conductive in response to the control signal. As a result, the first and second transistors become conductive so as to lock the first output of the flip-flop at a potential of the prede­ termined voltage terminal.

Description: Background of the Invention Field of the Invention The present invention relates to a bistable circuit, and more particularly to a bistable circuit capable of stably operating even if a data signal is out of time with a clock signal. Description of relates art Bistable circuits alternatively assume two stable conditions in response to two inputs. Namely, if a signal is applied to a first input, the bistable circuit is brought into a first stable condition until a signal is applied to a second input. The two stable conditions of the bistable circuits can be regarded to correspond to binary information "0" and "1", respectively. Therefore, the bistable circuits have been used in various digital circuits such as counters, shift registers, and the likes. These bistable circuits are mainly divided into two types, i.e., the asynchronous type and the synchronous type. In the asynchronous bistable circuits, the application of an input signal triggers the bistable circuit immediately. On the other hand, in the synchronous type, changes of state will occur only at selected times, i.e., when or after a clock signal is applied. In the case of a plurality of asynchronous bistable circuits being used, uncontrolled delays are inevitable, although individually very small (typically of the order of a few nanoseconds), and these delays will introduce differential delays between signals that must travel through different numbers of logic circuits. Unwanted signal combinations may therefore appear for short periods and may be interpreted erroneously. The synchronous bistable circuits do not suffer from such a problem, because they conform to the control signals only when the clock signal is present. Therefore, the synchronous bistable circuits are widely used in logical circuits. However, the synchroneous bistable circuits involve another problem in which the outputs take an intermediate potential when the transistion of a data signal encounters the transition of a clock signal. If such an intermediate potential is outputted to the next bistable circuit, the state of the next circuit is not determined, which would result in malfunction of a circuit including the bistable circuits. EP-A-0 058 752 discloses a clock-synchronized master slave flip-flop, wherein both outputs of the master flip-flop are forcibly brought into a low level condition in case the master flip-flop outputs an intermediate level so that the condition of the slave flip-flop is maintained. For this purpose, there is provided a Schmitt trigger circuit for detecting said both outputs of the master flip-flop are at the intermediate level and for outputting the result of the detection of the master flip-flop. US-A-4 179 628 discloses a circuit which offers a preference to a resetting in an asynchronous bistable circuit having a set terminal and reset terminal. It is an object of the invention to provide a bistable circuit capable of stably operating even if a data signal is inputted in asynchronous with a clock signal. Another object of the present invention is to provide a bistable circuit which can output a logically clearly distinguishable voltage signal so that a circuit connected to the bistable circuit will not malfunction even if the transistion of the input signal to the bistable circuit encounters the transition of a clock signal applied to the same bistable circuit. This object is achieved by a bistable circuit as defined in claim 1; dependent claims are related to further developments of the invention. Specifically, the lock circuit includes first and second insulated gate field effect transistors series-connected between the first output of the flip-flop and the predetermined supply voltage. The first transistor has a gate connected to receive the signal indicative of the condition of the second output of the flip-flop, and the second transistor has a gate connected to receive the control signal. If a data signal is applied to the flip-flop in asynchronism with a clock signal, more specifically if the transition of the inputted data signal encounters the transition of the applied clock signal, the first and second outputs of the flip-flop will assume intermediate voltage conditions, respectively. With the arrangement mentioned above, however, the intermediate voltage in the predetermined one of the two outputs is applied to the first control input of the lock circuit, and then, in response to the control signal applied to the second control input, the lock circuit is rendered conductive so as to short-circuit the first output of the flip-flop to the predetermined supply voltage. As a result, the first output of the flip-flop is brought into the predetermined supply voltage. Namely, the flip-flop is forcedly caused to assume one stable condition. Therefore, the next circuit connected to the output of the flip-flop will receive the output of a logically clearly distinguishable voltage, and so, can stably operate without malfunction. In one embodiments, the gate of the first transistor is directly connected to the second output of the flip-flop. Further, the predetermined supply voltage is a source supply voltage, and the first and second transistors are n-channel transistors, respectively. In a cascade of bistable circuits, the first and second outputs of the flip-flop are respectively connected to a pair of inputs of a second flip-flop having a clock input, and the gate of the second transistor are connected to the clock input of the second flip-flop. In another embodiments, the predetermined supply voltage is a drain supply voltage and the first and second transistors are p-channel transistors, respectively. Further, the gate of the second transistor is directly connected to the clock input of the flip-flop itself. In a third embodiment, the lock circuit further includes a third insulated gate field effect transistor having a gate connected to the second output of the flip-flop and a source connected to the predetermined supply voltage, a fourth insulated gate field effect transistor having a gate connected to the first output of the flip-flop and a drain connected to a second supply voltage, and an inverter having an input connected to the drain of the third transistor and the source of the fourth transistor. The output of the inverter is connected to the gate of the first transistor. More specifically, the first predetermined supply voltage is a source supply voltage and the second supply voltage is a drain supply voltage. Further, the first to fourth transistors are n-channel transistors, respectively. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawing Figure 1 is a circuit diagram of a first embodiment of a bistable circuit in accordance with the present invention; Figure 2 is a waveform diagram showing the voltage conditions at various points in the circuit shown in Figure 1; Figure 3 is a diagram similar to Figure 1 but showing a second embodiment of the bistable circuit; Figure 4 is a diagram similar to Figure 2 but showing the waveforms in the second embodiment shown in Figure 3; Figure 5 is a diagram similar to Figure 1 but showing a third embodiment of the bistable circuit; and Figure 6 is a diagram similar to Figure 2 but showing the waveforms in the third embodiment shown in Figure 5. Description of the Preferred Embodiments Referring to Figure 1, there is shown a bistable circuit embodying the present invention. The shown bistable circuit comprises a flip-flop FF-I which includes a three-input AND circuit 1 having an output connected to one input of a NOR circuit 2. The flip-flop FF-I also includes a two-input AND circuit 3 whose output is connected to one input of another NOR circuit 4. This second NOR circuit 4 has another input connected to the output of the first NOR circuit 2, and an output connected to a second input of the first NOR circuit 2. With the above arrangement, two inputs of the three-input AND circuit 1 and one input of the two-input AND circuit 3 constitute data inputs A, B and C, respectively, and the remaining inputs of the AND circuits 1 and 3 are commonly connected to form a clock input F₁. The input A is adapted to receive a signal in asynchronism with the clock signal F₁, and the inputs B and C are adapted to receive either the same signal of logical level "0" or a pair of signals in reverse to each other, i.e., the signals "0" and "1" or the signals "1" or "0", respectively. The outputs of the two NOR circuits 2 and 4 constitute two outputs Q and Q of the fliP-flop which assume voltage conditions in reverse to each other. The outputs of this flip-flop are connected to corresponding inputs of another flip-flop FF-II which has the same construction as that of the first flip-flop FF-I except that a two-input AND circuit 5 is used in place of the three-input AND circuit 1, and which also includes a clock input F₂ applied with a clock at a timing different from the clock F₁. The flip-flops mentioned above are well-known in the art. In accordance with the present invention, furthermore, a n-channel insulated gate field effect transistor Q₁ is connected at its drain to the output Q of the NOR circuit 4 and at its gate to the output of the NOR circuit 2. A source of the transistor Q₁ is connected to a source supply voltage V ss through another n-channel insulated gate field effect transistor Q₂ whose gate is connected to the clock input F₂ of the next flip-flop FF-I. In the cascade of flip-flops as explained above, assume now that as shown in Figure 2 the inputs B and C are a high voltage and a low voltage, respectively, and the signal applied to the input A varies in asynchronism with the clock input F₁. As shown in the left half of Figure 2, when the data signal A rises up, if the clock pulse F₁ falls down, the outputs Q and Q of the flip-flop FF-I do not perfectly change their voltage conditions and consequentially remain at intermediate voltages, respectively. But, with the intermediate voltage being applied to the gate of the transistor Q₁, the transistor Q₁ is put in a conductive condition. Therefore, when a clock pulse F₂ is applied to the gate of the transistor Q₂, the transistor Q₂ is turned on, so that the output Q of the flip-flop FF-I is forcedly pulled down to the voltage V ss , i.e., the low level voltage. Therefore, the output Q of the flip-flop FF-I is forcedly pulled up to the high level voltage. Thus, when the clock input F₂ is applied, the flip-flop FF-I outputs a pair of voltages clearly distinguishable between the low level voltage and the high level voltage. On the other hand, since the flip-flop FF-II is triggered at the clock pulse F₂, the flip-flop FF-II operates without malfunction. As shown in the right half of Figure 2, if the signal A changes its condition during a period of a high level of the clock pulse F₁, the two outputs Q and Q of the flip-flop FF-I changes their conditions perfectly. At this time, since the transistor Q₂ is maintained in an off condition, the flip-flop FF-I does not suffer any influence from the transistors Q₁ and Q₂. Turning to Figure 3, there is shown a second embodiment of the bistable circuit in which the elements similar to those shown in Figure 1 are given the same reference numerals. In the circuit shown in Figure 3, the output Q of a flip-flop FF-IA is connected to a transfer gate 6 and a source of a p-channel insulated gate field effect transistor Q₁₁ whose gate is connected to the output Q of the flip-flop FF-IA. Further, the drain of the transistor Q₁₁ is connected to a drain source voltage V DD through another p-channel insulated gate field effect transistor Q₂₂ whose gate is connected to the clock input F₁₁ of the flip-flop FF-IA. The circuit shown in Figure 3 operates as follows. As shown in Figure 4, under the condition that the input B is kept at a high level and the input C is a low level, when the clock pulse pulse F₁₁ falls down from a high level to a low level, if the input A rises up from a low level to a high level, the outputs Q and Q are brought into intermediate potentials, respectively, as seen from Figure 4. In this condition, the transistor Q₁₁ is brought into a conductive condition, Then, when the control signal F₁₁ becomes a low level, the transistor Q₂₂ is rendered conductive, with the result that the output Q of the flip-flop is pulled up to the voltage V DD . In the circuit as shown in Figure 3, if the transition of the input A is separated from the transition of the control signal F₁₁, the flip-flop FF-IA will operate in a similar manner to conventional ones, and do not suffer any adverse effect from the transistors Q₁₁ and Q₂₂ because either the transistor Q₁₁ or Q₂₂ is put in an off condition. Referring to Figure 5, there is shown a third embodiment of the bistable circuit in accordance with the present invention, in which the elements similar to those shown in Figure 1 are given the same reference numerals and explanation thereon will be omitted. The following is the points differing from the first embodiment shown in Figure 1. The output Q of the NOR circuit 2 is connected to a gate of a third n-channel insulated gate field effect transistor Q₃ whose source is connected to a source supply voltage V ss . On the other hand, the output Q of the NOR circuit 4 is connected to a gate of a fourth n-channel insulated gate field effect translator Q₄ whose drain is connected to a drain supply voltage V DD . A source of the transistor Q₄ is connected at a node N to a drain of the transistor Q₃ and an input of an inverter 7 whose output is connected to the gate of the transistor Q₁. With the above arrangement, the output Q of the NOR circuit 2 and the node N (the source of the transistor Q₄) constitute a pair of outputs of the flip-flop which should be connected to the next flip-flop FF-II. In the circuit as shown in Figure 5, when the inputs B and C are a high level and a low level, respectively and when the clock signal F₁ falls down, if the input A rises up to a high level, the outputs Q and Q of the flip-flop FF-I take intermediate voltages, respectively, as seen from Figure 6. In this condition, the transistors Q₃ and Q₄ are turned on, so that the transistor Q₄ acts as a level shifter. As a result, as shown in Figure 6, the node N connected to the drain of the transistor Q₃ and the source of the transistor Q₄ will take a voltage lower than that of the output Q. Thus, the low voltage is inverted by the inverter 7 and a high voltage is applied to the gate of the transistor Q₁ so as to turn the transistor Q₁ on. On the other hand, when the clock pulse F₂ is applied to, the transistor Q₂ is turned on. Accordingly, the output Q is pulled down to the voltage V ss i.e., the low voltage. In the above mentioned circuit, the inputs of the next flip-flop FF-II are connected to the output Q of the flip-flop FF-I and the node N. Therefore, since the input of the flip-flop FF-II is isolated from the output Q of the flip-flop FF-I by means of the transistor Q₄, the flip-flop FF-II is not influenced by the operation of the transistors Q₁ and Q₂. The above three embodiments are adapted such that when the flip-flop takes intermediate voltage outputs, the two outputs Q and Q of the flip-flop are forcedly brought to levels H and L , respectively. However, it is possible to construct the bistable circuit so that when the flip-flop assumes intermediate output voltages the outputs take the conditions in reverse to the conditions mentioned above. Furthermore, in the shown embodiment, the output of the flip-flop is connected to another flip-flop. However, the output of the flip-flop can be connected to latch circuits, inverters, and other digital circuits.

Claims: A bistable circuit comprising a flip-flop (FF-I, FF-IA) having at least two data input terminals (A,B;C), a clock terminal receiving a clock signal (F1), and first and second output terminals (Q, Q ), the flip-flop (FF-I, FF-IA) operating to take in a data signal supplied to a data input terminal (A) in a period in which said clock signal is at an active level, and to generate a first output signal in accordance with a logic level of said data signal and a second output signal complementary to said first output signal at said first and second output terminals (Q, Q ), respectively, and a lock circuit, characterized in that said lock circuit includes first and second transistors (Q₁,Q₂; Q₁₁, Q₂₂) series-connected between said first output terminal (Q or Q ) and a potential terminal (V SS or V DD ) giving a first logic level, means operating in response to the level on at least one of said first and second output terminals (Q, Q ), so as to turn on said first transistor (Q₁,Q₁₁) when said first output terminal is substantially at said first logic level and to turn off said first transistor (Q₁,Q₁₁) when said first output terminal is substantially at a second logic level, said means also operating to turn on said first transistor (Q₁,Q₁₁) when said first output terminal is at an intermediate level between said first logic level and said second logic level, and means for turning on said second transistor (Q₂,Q₂₂) after said clock signal (F1) has changed from said active level to an inactive level. A bistable circuit claimed in claim 1, wherein said first transistor (Q₁) is a first insulated gate field effect transistor having a current path connected at its one end to said second output terminal ( Q ), and a gate connected to receive a signal indicative of the logic level of said first output terminal (Q), and said second transistor (Q₂) is a second insulated gate field effect transistor having a current path connected at its one end to the other end of the current path of said first insulated gate field effect transistor (Q₁) and at its other end to a potential terminal (V SS ) giving said first logic level (Low), a gate of said second insulated gate field effect transistor (Q₂) being connected to receive a second clock signal (F2) time-shifted against the clock signal (F1). A bistable circuit claimed in claim 2, wherein said gate of said first insulated gate field effect transistor (Q₁) is connected directly to said first output terminal (Q). A bistable circuit claimed in claim 1, wherein said first transistor (Q₁₁) is a first insulated gate field effect transistor having a current path connected at its one end to said first output terminal (Q), and a gate connected to receive a signal indicative of the logic level of said second output terminal ( Q ), and said second transistor (Q₂₂) is a second insulated gate field effect transistor having a current path connected at its one end to the other end of the current path of said first insulated gate field effect transistor (Q₁₁) and at its other end to a potential terminal (V DD ) giving said first logic level (High), a gate of said second insulated gate field effect transistor (Q₂₂)being connected to receive said clock signal (F11). A bistable circuit claimed in claim 4, wherein said gate of said first insulated gate field effect transistor (Q₁₁) is connected directly to said second output terminal ( Q ). A bistable circuit claimed in claims 2 or 3, wherein the lock circuit further includes a third insulated gate field effect transistor (Q₃) having a gate connected to the first output (Q) of the flip-flop and a source connected to the first voltage terminal, a fourth insulated gate field effect transistor (Q₄) having a gate connected to the second output ( Q ) of the flip-flop and a drain connected to a second voltage terminal and an inverter (7) having an input connected to the drain of the third transistor (Q₃) and the source of the fourth transistor (Q₄), the output of the inverter being connected to the gate of the first transistor (Q₁). A bistable circuit claimed in claim 6, wherein the first voltage terminal is at source supply voltage (V SS ) and the second voltage terminal is at drain supply voltage (V DD ), and wherein the first to fourth transistors (Q₁ - Q₄) are n-channel transistors, respectively. A bistable circuit claimed in claim 3, wherein the first and second outputs (Q, Q ) of the flip-flop are respectively connected to a pair of inputs of a second flip-flop (FF-II) having a clock input (F2), the gate of the second transistor (Q₂) being connected to the clock input of the second flip-flop.

Inventors: KAWAMURA FUMITO, KAWAMURA, FUMITO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1986
Main classification: H03K3
IPC codes: H03K3