DECODER FOR DIGITAL RADIO-RECEIVED DATA AND METHOD

Abstract: A system, including methods and apparatus requiring digital communication between two devices using radio fre­ quency communications to provide the link. Apparatus for decoding a digital data stream is provided, which data stream has been imposed on a base band signal where the rate of data transmission is as high as twice the frequency of the base band signal. A differential amplifier is employed to recognize the beginning and end of a segment of a wave cycle which represents a digital bit.

Description: This invention relates generally to digital data transmission and, in particular, to systems comprising methods and apparatus wherein digital communication between two devices is achieved by radio frequency transmission, with or without connecting wires, and further requiring a data transmission rate (baud rate) on the order of as much as twice as fast as the frequency of the base band signals. It is known to transmit data by interrupting an electric current or wave. The rate of data transmission, however, is limited by the frequency of the wave carrying the data. Previously, many of the techniques have required the frequency of the base band signal to exceed the rate of data transmission by at least a factor of 2 or more. The base band represents the band of frequencies occupied by a signal before it modulates the carrier frequency to form the transmitted line or radio signal. Heretofore, if the frequency of the base band was constrained below some maximum value, the rate of data transmission was also constrained. In particular, regulatory requirements for low-power, unlicensed, local radio transmitters have mandated base bands with frequencies on the order of 5 KHz. Using prior art techniques, data transmission rates on the order of only 2400 bits per second (baud) can be obtained, a rate substantially below the 9600 baud rate commonly employed in digital data transmission. It is known (from DE-A-2 833 897) to use hysteresis in a comparator in order to respond to excursions in two different senses at two input levels, and to ignore times when the input levels are zero, but this system is not helpful for processing a generally sinusoidal waveform. BRIEF SUMMARY AND OBJECTS OF THE INVENTION The disadvantages of the state of the art represented by DE-A-2 833 897, and other prior art such as US-A-4 222 008, are substantially alleviated if not overcome with the present invention which, in brief summary, can provide a rate of data transmission which is essentially twice the frequency of the carrier waves at low cost and with relatively little signal processing. The invention can be appreciated from appended Claims 1 and 6. Systems requiring digital communication between two devices can use a radio frequency wave to provide the connection. A particular example is a connection between a stationary control computer and a mobile sensor or mechanical device. The FCC has reserved a band of frequencies near 450 MHz for this purpose. In order to obtain FCC approval respective a transmitter for such data transmission, a plurality of manufacturers, such as Repco Corporation, supply modem units that shape the input signals to maintain a base band frequency essentially less than 4.5 KHz. If ordinary reception techniques are used, this process limits transmission rates of digital signals to baud rates just greater than 2400 bits per second. If higher baud rates, for example 9600 baud, are imposed on the base band signal, the output of the modulation unit of the transmitter and, therefore, the input of the data receiver, becomes almost sinusoidal. Prior art receivers require an input which is essentially a square wave, providing an "edge" to trigger logic circuits necessary to re-assemble the data. Accordingly, it is a primary object of the present invention to provide improved methods and apparatus for recovering digital data from a modulated carrier wave. Another important object of this invention is to discriminate against noise which may be caused by the method or apparatus for recovering digital data. An additional significant object is to provide an absolute value circuit to insure that all voltage transitions inputs to a latching circuit correspond to data impulses. These and other objects and features of the present invention will be apparent from the detailed description taken with reference to the accompanying drawings. Figure 1 is a three dimensional schematic showing the relationship of a presently preferred digital data decoder embodiment of the invention to other apparatus; Figure 2 is a simplified block diagram of the presently preferred digital data decoder embodiment of the invention; Figure 3 is a circuit diagram of the presently preferred data decoder embodiment of the invention; and Figure 4 is a timing diagram showing representative waveforms involved in practicing the present invention. Referring now to Figure 1 for purposes of preferred embodiment illustration, a conventional external signal source 10 imposes digital data at an appropriate rate, for example 9600 baud on a base band signal of frequency essentially equal to one-half of the baud rate. Said base band signal modulates a carrier wave of appropriate frequency, for example 450 MHz. The carrier wave is transmitted to a conventional receiver 12, for example, a Repco receiver #RDRXN6NCC. The output of the receiver 12 is communicated to a digital decoding circuit 14. The digital decoding circuit 14 produces a digital signal which is communicated to a suitable device, for example, a computer 16. Referring to Figure 2, the digital decoding circuit 14, as presently preferred, comprises seriatim a differential amplifier 18, a comparator circuit 20 and a latch circuit 22. The differential amplifier 18 produces distinct voltage spikes corresponding to voltage transitions of the waveform received from the receiver 12 accross a zero voltage. A positive voltage spike is produced whenever the waveform passes from negative to positive, and a negative voltage spike is produced whenever the waveform passes from positive to negative. The comparator circuit 20 produces two voltages, a first voltage which is interrupted whenever the output of the differential amplifier 18 exceeds a certain pre-determined value and a second voltage which is interrupted whenever the output of the differential amplifier 18 is less than a certain pre-determined value. The latch circuit 22 combines two outputs of the comparator circuit 20 into a digital data stream. Referring to Figure 3, the output of the receiver 12 is provided with a load resistor R1, chosen to balance the capacitively coupled output of discriminator circuitry contained within the receiver 12. A representative output 36 (Figure 4) from the receiver 12 comprises a digital data stream 34 which has been distorted by modulation and demodulation of a carrier wave. The output 36, is passed to the differential amplifier 18, which comprises an appropriate integrated circuit 24, [for example an LF357 available from National Semiconductor] together with resistors R2 and R3 and capacitors C1 and C2, which function in a known fashion. The integrated circuit 24 is biased to function as a differentiation device by resistor R3 and capacitor C2. Resistor R2 and capacitor C1 are provided for the purpose of limiting input band width to supress noise. Given the data stream 34, the output of the differential amplifier 18 comprises a waveform 38 (Figure 4). The maximum amplitude of waveform 38 is adjusted to a suitable value, for example, in excess of 6.5 volts positive and negative, by either adjusting the amplitude of waveform 36 at the output of receiver 12, or by chosing appropriate values for resistors R2 and R3 and capacitors C1 and C2. The output 38 of the differential amplifier 18 is communicated to the comparator circuit 20, which comprises at least two comparator components, i.e. a positive voltage comparator 26 and a negative voltage comparator 28. Comparators 26 and 28 are provided with suitable comparison voltages through resistors R4, R5 and R6 and pull-up resistors R7 and R8. A satisfactory integrated circuit for comparators 26 and 28 is an LM339 available from National Semiconductor. In the preferred embodiment, the comparison voltages are provided by a source of positive potential and a source of negative potential connected by a plurality of resistors R4, R5 and R6 in series. For example, if a positive source of + 24 volts and a negative source of - 24 volts are provided, proper values for the resistors would be 3.3 K ohms for resistor R4 and resister R6 and 8.8 K ohms for resistor R5. This will produce comparison voltages of approximately + 6.5 volts for positive comparator 22 and - 6.5 volts for negative comparator 24. Pull-up resistors R7 and R8, with associated voltage sources, are selected to provide output voltages for positive comparator 26 and negative comparator 28 at TTL signal levels, for example, + 5 volts. The function of the positive comparator 26 is to interrupt a current at the output of positive comparator 26 whenever and as long as the amplitude of waveform 38 exceeds the positive comparison voltage, for example + 6.5 volts. A representative output 40 from positive comparator is shown in Figure 4. The function of the negative comparator 28 is to interrupt a current at the output of negative comparator 28 whenever and as long as the amplitude of waveform 38 is less than the negative comparison voltage, for example - 6.5 volts. A representative output 42 from negative comparator is shown in Figure 4. The two outputs of the comparator circuit 20 are respectively applied to the inputs of a latch circuit 22. For example, in the preferred embodiment, the latch circuit may comprise two negative logic AND gates 30 and 32 connected as shown. A suitable flip-flop circuit comprising AND gates 30 and 32 is an SN74279 available fron Texas Instruments. A low logic level at the input of AND gate 30 will set the latch output to a logic level "high". The latch output is reset to "low" by a "low" logic level at the input of AND gate 32. The latch circuit output 44 (Figure 4) represents a stream of digital data corresponding to the digital input 34. The values of circuit components are not critical to the operation of the present invention. Of course, the combinations of resistors and capacitors are chosen such that the response time (or "time constant") of the differentiating circuit is compatible with the input frequency from the receiver 12. Variations and modifications may be made without departing from the present invention.

Claims: Apparatus for producing a square waveform from an input waveform (36) at an incident point (12), comprising means for communicating the input waveform to a comparator (20) arranged to compare at two different voltage levels according to the instantaneous polarity of the input waveform (36) characterized by: means (18) responsive to the input waveform to create a spiked waveform (38) having positive and negative voltage spikes each time the input waveform (36) goes positive and negative, respectively; the comparator (20) being fed with the spiked waveform (38) and thus comparing the voltage of the spikes to said levels, being two predetermined voltage comparator trip levels of opposite polarity; wherein respective constant voltage signals (40,42) are interrupted for each excursion of a respective voltage spike greater than the predetermined voltage comparator trip levels of its own polarity; and by combining means (22) arranged to integrate the two interrupted signals (40,42) into a single output square wave signal (44). Apparatus for communicating digital data at a baud rate by radio frequency comprising: radio frequency transmitter means having means for superimposing the digital data upon a baseband waveform of approximately one half the frequency of said baud rate, thereby tending to produce a composite sinusoidal waveform, and transmitting this at said radio frequency, cooperating receiver means being characterized by square wave producing apparatus according to Claim 1. Apparatus according to Claim 1 or 2 wherein the combining means (16) comprise latching means which produces a constant voltage in response to each interruption of the first interrupted voltage signal (40), and which produces zero voltage in response to each interruption of the second interrupted voltage signal (42). Apparatus according to Claim 2, wherein the digital data is represented in said input generally sinusoidal waveform (36), by each half cycle of the latter substantially representing a digital bit. Apparatus according to Claim 2 wherein the base band signal has a frequency of on the order of 4800 HZ and wherein the digital data rate is on the order of 9600 BAUD. Apparatus according to any of Claims 1-5 wherein the spiked waveform (38) is created by a differentiation circuit (18). A method for producing a square waveform corresponding to an input waveform comprising comparing the input wave with voltages to produce a two level output signal according to the sign of the input waveform, characterized by, especially for a generally sinusoidal input waveform, creating (18) positive and negative voltage spikes (38) each time the input waveform (36) goes positive and negative, respectively; communicating said positive and negative voltage spikes to first and second level comparators (26,28); comparing the voltage of said spikes to a predetermined voltage level at its own polarity, the two comparisons being of opposite polarity, respectively; issuing a constant known voltage signal at each comparator (26,28); interrupting said constant voltage signal when the respective voltage spike exceeds the predetermined voltage level at its polarity, and integrating the two interrupted voltage signals (40,42) into a single output square waveform (44) responsive to the incident generally sinusoidal waveform (36). A method for communicating digital data at a baud rate, using the producing method of Claim 7, comprising superimposing the issue digital data upon a carrier waveform having a frequency of half the baud rate, to create a generally sinusoidal waveform containing said digital data. A method according to Claim 7 or 8 wherein the integrating step further comprises initiating a constant voltage at each interruption of the voltage signal (40) at one comparator site (26) and producing zero voltage at each interruption of the voltage signal (42) at the other comparator site (28). A method according to Claim 8 wherein said base band signal has a frequency of on the order of 4800 Hz and wherein said digital data has a data transmission rate of on the order of 9600 BAUD.

Inventors: DAHL, WARREN JEFFREY
Applicants: EATON-KENWAY, INC.
Application year: 1986
Main classification: H04L27
IPC codes: H04L25, H03K5, H04L27