DIGITAL PHASE-LOCKED LOOPS

Abstract: A clock signal having a predetermined phase relationship relative to a signal element of an analog signal that repeats at a nominally fixed frequency is generated by an oscillator (9) having an oscillation frequency that depends on the value of a control signal. The input analog signal is sam­ pled under control of the clock signal, and a succession of digital words representing the ampli­ tudes of the successive samples is generated. The digital words are written into memory (14), and are digitally analyzed in order to determine the phase, within the cycle of the clock signal, of the signal element. The signal that represents the phase of the signal element relative to the clock signal is used as a control signal for controlling the fre­ quency of oscillation of the oscillator.

Description: This invention relates to digital phase-locked loops. Background of the Invention In a known type of digital television test signal generator, such as the Tektronix 1910, the various test signals are inserted into the composite color video signal in timed relationship to the sync and burst of the video signal. The test signals themselves are generated by reading digital data out of ROM under control of a clock signal at 4f SC , where f SC is the color subcarrier frequency (3.58 MHz in the case of the NTSC signal format), and converting the digital data to analog form by a digital-to-analog converter (DAC). In order for the test signals to be inserted in timed relationship to the burst of the video signal the 4f SC clock signal must have a fixed phase relationship to the color burst. Generally speaking, it is desired that the clock signal be adjustable in phase relative to the color burst, e.g. in order to allow for pre-compensation for system delays and to accommodate test signals that are encoded in ROM on different modulation axes. In the case of the Tektronix 1910 test signal generator, the desired phase relationship is established using an analog phase-locked loop. Thus, a conventional sync separator identifies sync of the video signal and opens a window during burst time while the video signal is applied to a phase detector. The analog output of the phase detector is applied to the control input of a voltage controlled oscillator (VCO), and the output of the VCO is fed back to the other input of the phase detector. Thus, the phase detector generates an error signal representative of the difference in phase between the burst and the output of the VCO, and the output of the VCO is thereby brought into phase with the burst. The VCO is used to generate the 4fsc signal. The operation of bringing the 4fsc signal into phase with burst is know as genlocking. Among the disadvantages of using a conventional analog phase-locked loop are that an analogphase-locked loop requires calibration and drifts with time and temperature. US-A-4,291,332 discloses apparatus for generating from an input analog signal having first and second signal elements that repeat at a first frequency a repetitive signal having a predetermined phase and frequency relationship to the first signal element, the input analog signal being digitized by an analog-to-digital converter under control of the repetitive signal to generate a succession of digital words, the apparatus also including: means for detecting the second signal element within the input analog signal to initially produce a write window; means for storing the succession of digital words from the analog-to-digital converter during the write window; means for processing the succession of digital words from the storing means to generate a control word, and a variable digitally controlled oscillator responsive to said control word to generate said repetitive signal with said predetermined phase and frequency relationship to said first signal element. In one aspect the invention provides an apparatus as disclosed in US-A-4,291,332 characterised by address control means arranged to control said storing means to cause successive digital words to be written from said analog-to-digital converter to said storing means during a write window, said write window encompassing said first and second signal elements, and to cause the written digital words to be read from said storing means to said processing means when said write window is closed, said processing means being arranged to adjust the position of said write window in response to the digital words from the storing means and to adjust said control word to maintain said predetermined phase and frequency relationship between said repetitive signal and said first signal element. In a preferred embodiment of the invention, an input analog signal, such as an NTSC video signal, having a signal element that repeats at a first, nominally fixed frequency (the first positive-going zero crossing of burst, repeating at line rate) is used to generate a signal at a second, higher frequency (4fsc, for example) and having a predetermined phase relationship to the repetitive signal element of the input signal. This is accomplished by using a programmable oscillator to generate a clock signal at a frequency that depends on the value represented by a control word applied to the oscillator, and using the clock signal to establish the sample times for an analog-to-digital converter (ADC), whereby a succession of digital words representing the amplitude of the analog input signal at the time of successive clock signals is generated. The digital words are then analysed to identify where, in the succession of digital words, the signal element occurs and to determine the phase angle of the clock cycle at which the signal element occurs. This phase information is used to generate the control word for the programmable oscillator and to establish the desired predetermined phase relationship between the clock signal and the signal element of the input signal. Brief Description of the Drawings For a better understanding of a preferred embodiment of the invention, and to show how she same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings in which:- Figure 1 is a block diagram of a genlock system embodying the present invention, and Figure 2 illustrates one cycle of a sinusoidal waveform. Detailed Description In the genlock system shown in Figure 1, the input reference signal (which depending on the application, may be black burst or composite program video) is applied to a clamp 2 which acts under control of a sync separator 4 to clamp the sync tip of the video signal to a predetermined potential level. The clamped video signal is bandwidth limited by a low-pass filter 5 and is applied to a six-bit ADC which samples the video signal under control of a clock provided by a programmable oscillator 8 that comprises a VCO 9 and a digital-to-analog converter (DAC) 18. In the steady state, when the control word applied to the programmable oscillator is midrange, the clock frequency is four times the frequency of the burst of the input video signal and the clock is in phase with burst. A suitable dither function may be superimposed on the samples that are digitized, in order to increase the effective resolution of the ADC 6 beyond six bits. The sync separator 4 also provides an output signal to an address control circuit 12. The address control circuit controls the addressing of a random access memory (RAM) 14, i. e. whether the RAM 14 can be written into by the ADC 6 or whether it can be read out from by a microprocessor 16. As in the case of a conventional analog genlock system, the purpose of the illustrated digital genlock system is to generate clock pulses at a predetermined frequency and in predetermined phase relationship with burst of the input reference signal. Prior to commencing acquisition, the processor contains no information concerning the location of burst, but without this information it is difficult to initially identify burst without examining the entire horizontal interval and consequently it is difficult to acquire lock. In order to alleviate this problem, when the sync separator 4 detects sync on a given line, it causes the address control to establish a write window for the RAM 14 during the next horizontal blanking interval. The sync separator may be of relatively simple design, since it is used only to aid in initial lock acquisition by setting the position of the write window relatively coarsely. Once lock has been acquired, the write window position is controlled with a high degree of precision by the microprocessor 16. The delay between the sync pulse detected by the sync separator and the opening of the write window is slightly shorter than the horizontal line interval, and consequently the write window opens before the next sync pulse. The duration of the window is chosen to be such that the window does not close until after burst. Since sync occurs nineteen subcarrier cycles before the start of burst, and burst itself lasts nine cycles, this implies that the window must be open for at least about thirty subcarrier cycles. During the write window, the six bit digital words representative of the amplitude of the clamped video signal at the sampling points established by the clock pulses from the oscillator 8 are written into the memory 14. When the window closes, the microprocessor 16 is able to address the memory 14 and carry out computations using the contents of the memory 14. The microprocessor 16 adjusts the position of the write window and adjusts the control word applied to the programmable oscillator 8. The desired position of the write window depends upon the position of the sync point (the fifty percent point of the leading edge of the horizontal sync pulse) and is determined by averaging samples taken during the sync tip and samples taken during burst. Since burst is a sinusoidal wave, the average level of the signal during burst is equal to blanking level. By sampling burst over several cycles of burst, an accurate measure of blanking level can be obtained by averaging the samples. Thus, knowing that the leading edge of sync occurs nineteen subcarrier cycles prior to the start of burst, the processor can be caused to calculate the average value of the samples that occur from, say, 20 to 24 subcarrier cycles after sync. This number then represents blanking level. Similarly, knowing that the sync tip level is reached about 250 ns after the sync point and is maintained for about 4.25 µs, the processor can be caused to average the values of the samples during this interval and generate a number representing sync tip level. The average of the two numbers then represents the level of the sync point itself. The microprocessor examines the samples that occur on the leading edge of sync (since the input video is bandwidth limited, the slew rate of the leading edge of sync is sufficiently small that at least one sample is taken on the leading edge of sync both above and below the sync point) and determines which sample occurred immediately above the sync level and which sample occurred immediately below the sync level. The microprocessor then carries out a linear interpolation to determine the time, between these two samples, at which the level of the leading edge of sync was equal to the average of the blanking and sync tip levels, and this time is then taken as the sync time. There is an unknown delay, which may exceed a half-period of burst, between sync time and the time at which the sync separator 4 provides a signal to the address control 12. During acquisition of lock, the microprocessor uses the information that it derives concerning sync time to control the position of the write window relative to sync, in order to provide correction for the error in sync time as determined by the sync separator. In addition, after lock has been acquired the microprocessor controls the position of the write window in order to compensate for drift in the sync point. Thus, if sync occurs too soon after opening of the window, on the next line the window is opened somewhat earlier, and similarly if sync occurs an unduly long time after opening, the window is opened later. In fact, the microprocessor moves the window so that the window opens an integral number of subcarrier cycles before the first zero crossing of burst, and the information that is derived concerning sync time is used to ensure that the window does not open more than one subcarrier cycle, or four clock cycles, before sync. Thus, the window is positioned with respect to both sync and burst, with burst providing a fine control and sync providing a coarse control that is overridden by burst based on whether the SC-H phase angle lies within an acceptable range. The microprocessor uses the samples that are taken during burst to calculate the phase of the clock relative to burst. It can be shown that if four samples are taken over one cycle of a sinusoidal waveform, and the values of the samples are represented by the numbers A, B, C and D (FIG. 2), then tan ⊘ = (A - C)/(B - D) where ⊘ is the phase angle between the start of the sinusoidal waveform and the first sample. Therefore, ⊘ = tan⁻¹((A - C)/(B - D)), and consequently by carrying out an arc tangent calculation the phase of the clock relative to burst can be determined. In carrying out an arc tangent calculation, it is conventional to calculate the sum of the mathematical series that defines the arc tangent. However, this calculation is quite time consuming and it is not necessary, in the case of the digital genlock system that is described, that the calculation be performed with the accuracy that is obtained by summing the series. Accordingly, an approximation is used, based on the observation that the tangent waveform is approximately linear from 0 to 45 degrees and is also approximately linear from 45 to 90 degrees. By this approximation, if the absolute value of (A - C) is greater than the absolute value of (B - D), the value of ⊘ (the phase angle at which the sample A occurs) is taken from the following Table 1: A-C positive B-D positive ⊘ = 45(B-D)/(A-C) A-C positive B-D negative ⊘ = 180-45(A-C)/(D-B) A-C negative B-D positive ⊘ = 360-45(C-A)/(B-D) A-C negative B-D negative ⊘ = 180+45(C-A)/(D-B) whereas if the absolute value of (A - C) is less than the absolute value of (B - D) the value of ⊘ is taken from the following Table 2: A-C positive B-D positive ⊘ = 90-45(B-D)/(A-C) A-C positive B-D negative ⊘ = 90+45(D-B)/(A-C) A-C negative B-D positive ⊘ = 270+45(B-D)/(C-A) A-C negative B-D negative ⊘ = 270-45(D-B)/C-A) In a conventional analog genlock system, the phase-locked loop brings the clock signal into quadrature with burst, i. e. it sets ⊘ to 90 degrees. However, it may be desired that ⊘ have a predetermined value ⊘ 0 other than 90 degrees. The microprocessor generates a control word representative of the difference between ⊘ 0 and ⊘. This digital control word representing the value of the phase angle relative to the desired phase angle is applied by the microprocessor 16 to a digital-to-analog converter (DAC) 18, which is connected to the control input 10 of the VCO9. Thus, if the clock is not in desired phase relationship with burst, the frequency of the VCO is adjusted to bring it into the desired phase relationship, and locking of the output of the VCO to burst is thereby accomplished. It will, of course, be appreciated that the number of samples that occur between sync and the first sample in the sequence of four samples (the sample that yields the value A) is known. It will be appreciated that the invention is not restricted to the particular genlock system that has been described and illustrated, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims, and equivalents thereof. The invention is not restricted to an apparatus and method by which lock is acquired to a component of the reference signal. For example, the programmable oscillator could be locked to a 3.58 MHz (or other frequency, such as 5.00 MHz) continuous wave signal. In this case, the burst of the reference signal would be examined at predetermined intervals to determine the phase relationship between burst and the clock signal generated by the programmable oscillator; and if the phase relationship were not as desired the phase of the clock signal would be adjusted relative to the continuous wave signal to achieve the desired relationship and lock would be re-established to the continuous wave signal. Moreover, the signal element of the input reference signal need not be part of burst but it could, even in the case of a video application, be some other element that repeats at line rate, such as horizontal sync. This is particularly applicable to the case where the reference signal is a monochrome signal and therefore does not include a burst component. In such a case, the programmable oscillator would be phase-locked to a continuous wave signal and a desired phase relationship would be established between the clock signals generated by the oscillator and the horizontal sync pulse. Linear interpolation is used to identify the sync point, because this provides acceptable results, but since the filter that is used for bandwidth limiting has a sin x/x impulse response, a more accurate determination would be provided if a sin x/x interpolation were done. It will also be appreciated that in order to avoid needing to use a fast ADC it would be possible to operate in equivalent time instead of peak time, taking successive samples on successive lines of the video signal. Moreover, the concept of a digital phase-locked loop is not, of course, restricted to video application.

Claims: Apparatus for generating from an input analog signal having first and second signal elements that repeat at a first frequency a repetitive signal having a predetermined phase and frequency relationship to the first signal element, the input analog signal being digitized by an analog-to-digital converter (6) under control of the repetitive signal to generate a succession of digital words, the apparatus also including: means for detecting (4) the second signal element within the input analog signal to initially produce a write window; means for storing (14) the succession of digital words from the analog-to-digital converter during the write window; means for processing (16) the succession of digital words from the storing means to generate a control word, and a variable digitally controlled oscillator (8) responsive to said control word to generate said repetitive signal with said predetermined phase and frequency relationship to said first signal element, characterised by address control means (12) arranged to control said storing means (14) to cause successive digital words to be written from said analog-to-digital converter (6) to said storing means during the write window, said write window encompassing said first and second signal elements, and to cause the written digital words to be read from said storing means to said processing means (16) when said write window is closed, said processing means being arranged to adjust the position of said write window in response to the digital words from the storing means and to adjust said control word to maintain said predetermined phase and frequency relationship between said repetitive signal and said first signal element. Apparatus as claimed in claim 1 wherein said storing means (14) is a random access memory and said processing means (16) is a microprocessor.

Inventors: EMMONS, PATTEN A., PENNEY, BRUCE J., SLATE, TIMOTHY W.
Applicants: TEKTRONIX, INC.
Application year: 1986
Main classification: H03L7
IPC codes: H03L7, H04N11, H04N9, H04N17