DATA TRANSMISSION AND DETECTION METHOD

Abstract: A data transmission system and apparatus used for recording on a recording medium an audio signal, compressed in time base with a predetermined compression ratio, together with a data signal for reproduction of the audio signal. The data signal is composed of serial data of bits. A dummy bit is provided before the head bit of the serial data with the dummy bit being in inverted relation to the head bit. A detection system and apparatus for detection of the data transmitted by the data transmission system, and a recording medium on which signals are recorded according to the data transmission system are disclosed.

Description: The present invention relates to a method of data transmission and more particularly to a method of transmitting serial data. In recently proposed video floppy systems, it is proposed to record a video signal as well as an audio signal on a magnetic sheet as the recording medium. Fig. 1 diagramatically shows both the video and audio signals present together on a magnetic sheet. For example, according to the standards on video floppies, field video signals (V) and audio signals (A1, A2) all can be recorded on a magnetic sheet for up to 50 concentric tracks in all. The audio signal is raised by time base compression into the video band and recorded in a frequency modulated form. The recording time per track is approximately 10 seconds, assuming that the audio band is 5 KHz and the time base compression ratio is 640. Also, assuming that the video band is 2.5 MHz and the time base compression ratio is 1,280, recording for approximately 20 seconds is possible. In this case, the audio signal may be completed in a single track or extended into the next track. The ring-like audio track is divided into four sectors, as shown in Fig. 2. For example, in the mode where recording for 10 seconds is possible, an amount of information for 2.5 seconds is allotted to each sector. Fig. 3 illustrates the form of an audio signal and additional signals to be recorded on a single sector. In Fig. 3, after an elapse of t₁ from time T₀, a start ID signal having a level L H higher than a reference level L₀ continues for time t₂ for obtaining the timing to read the audio signal information. After a blank of t₃, the audio signal starts. During the first interval of time t₄ the signal on a sector overlaps with that on the just preceding sector. This does not occur in the first sector corresponding to the leading portion of the audio signal. A new audio signal is for the remaining time t₅, the length of which is variable; 2.5 seconds at a maximum in the mode of 10 seconds per track, as mentioned above. After a subsequent blank of t₆, an end ID signal having a level of L L lower than reference level L₀ continues for t₇ in order to detect the end of the audio signal and to obtain the timing of reading data signal related to the subsequent audio signal. After a blank of t₈, the data interval continues for t₉. Then a blanking interval of time t₁₀ appears, the length of which is varied according to the interval of the preceding audio signal t₅, and thus one sector cycle ends. This form is basically the same in any of the sectors where the audio signal is present. The interval of the audio signal shown by t₅ is variable and selected so that the interval t₅ + t₁₀ is constant at all times. Thus the length of the audio signal determines the position of the end ID and data signals. The data signal includes, in the form of digital data, the number, on the magnetic sheet, of a track on which the audio signal is recorded, the number of the leading and subsequent tracks through which audio signals are recorded continuously, the number of the tracks through which the video signal corresponding to the audio signal is recorded, the compression ratio of the audio signal, etc. In this case, it is arranged that "1" and "0" represent levels L₀ and L L , respectively. When subjected to frequency modulation, the voltage levels L₀, L H , and L L correspond to f₀, f H and f L modulation frequencies, respectively, where f L < f₀ < f H ; for example, f₀ = 6 MHz, f H = 7MHz, f L = 5 MHz. The above data signal will now be described in more detail. Fig. 4 illustrates on enlarged scale the data signal shown in Fig. 3. In Fig. 4, reference numeral 51 denote a synchronism bits of 1 byte. Reference numerals 52-59 denote data signals of 1 byte; all of the data signals include 8 bytes in all. Of the 8-byte data for the signals 52 - 59, for example, 6 bytes for the signals 52 - 59 are used as the net data bits and 2 bytes for the remaining signals 58 and 59 are used as the CRCC (cyclic redundancy check code) for error detection. Here, 8 bytes for the signals 52 - 59, inclusive of CRCC, will be described hereinafter as the data. Thus the data signal of Fig. 4 is composed of the 1-byte synchronism bits and the 8-byte data bits. The type of the codes used is an NRZ code where low and high levels are represented by "0" and "1", respectively. The total number of bits used is 72. As described above, the net 6-byte data includes the track number of the audio signal tracks, the time compression ratio of the audio signal, the track number of the corresponding video, the track number of the leading and trailing tracks through which the audio signal continues, etc. Fig. 5 shows one example of a circuit to produce the data signal of Fig. 4. In Fig. 5, a signal generator 60 generates a start and an end ED signals and a clock signal to read a 9-byte data shift register 63. An adder 61 adds a start ID signal, an end ID signal from signal generator 60 to a data signal from shift register 63. A selector 62 selects which of the bytes of shift register 63 should be connected to the output of a controller 12 including a microcomputer. Reference numeral 63 denotes a 9-byte (= 72-bit) data shift register. The operation of the Fig. 5 circuit concerning data generation will now be described. First, controller 12 controls selector 62 so that the one-byte synchronism signal and predetermined data are written into a byte area 0 (least significant byte area) and more significant byte areas 1 - 8, respectively, of shift register 63 in bytes in parallel form sequentially from byte area 0 to byte area 8 (most significant byte area). In this case, the synchronism signal of 1 byte written into the least significant byte area 0 are represented, for example, by "01010101". As described above, the net data is written into byte areas 1 - 6 and the CRCC into byte areas 7 and 8. When this writing has been completed, controller 12, for example, enables signal generator 60 to generate a read clock signal (a) at a predetermined timing synchronous with rotation of the magnetic sheet (the timing is, for example, determined on the basis of PG signals, etc., derived by detection of rotating phase indicia attached to part of the magnetic sheet). The clock signal (a) causes the contents of shift register 63 to be read in bit serial form sequentially from byte 0 to byte 8 and a signal train having the form of Fig. 4 is obtained at the output (b) of the register 63. This output (b) of the register is added by adder 61 to the start and end ID signals (c) from signal generator 60. The output (d) of adder 61 is then synthesized with a compressed audio signal into a signal having the format shown in Fig. 3. The adder output is then subjected to precessing including emphasis, frequency modulation, etc., and recorded on the magnetic sheet via a magnetic head. In this case, if the recording speed is 1 TV field/track, the magnetic sheet will be rotated at 3,600 rpm under the NTSC system and concentric recording tracks will be formed. The leading bit output of shift register 63 is connected to the trailing end bit input thereof, which is not shown here. Thus in order to record data for one sector, data is circulated and written into the shift register 63 even after the data has been read out once, and when the second and subsequent sectors are to be recorded, the data will be read and recorded again and again. Reproduction of the signal recorded in the above mentioned manner will now be described. Here, especially, reproduction of the data will be described and reproduction of the compressed audio signal, etc., will be omitted. Fig. 6 illustrates an example of a circuit to reproduce the data. In Fig. 6, reference numeral 10 denotes a magnetic sheet. A sheet rotating motor 11 is controlled so as to rotate at 3,600 rpm in accordance with the NTSC system in view of a recording speed of 1 TV field/track. A PG detector 13 detects the rotating indicia on the sheet 10 and produces a PG signal. The circuit of Fig. 6 further includes a magnetic head 14, a reproduction preamplifier 22, a frequency demodulator 26, a deemphasis circuit 27, a voice reproduce circuit 28, an ID separator 29 which separates the start and end ID signals, a data gate pulse generator 30, a data gate 31, a data synchronism detector 32, a signal generator 33, a 8-byte data store shift register 64, and a selector 65. Shift register 64 may also be used as shift register 63 of Fig. 5. In the above structure, the FM signal picked up by magnetic head 14 out of magnetic sheet 10 is amplified by preamplifier 22 to a predetermined level and then delivered to frequency demodulator 26. The signal demodulated by demodulator 26 is deemphasized by deemphasis circuit 27 into a signal having the format shown in Fig. 3. This signal is delivered to voice reproduce circuit 28 where the audio portion of the signal is subjected to predetermined processing and then expanded into the original signal. Thus the original audio signal is reproduced. The reproduced signal from deemphasis circuit 27 is also delivered to ID separator 29 and data gate 31. The ID separator 29 is basically a low-pass filter, the cut-off frequency of which is set so that the ID signal can pass through the filter and that no audio and data signals can pass. The start and end ID signals (e) separated by ID separator 29 are delivered to data gate pulse generator circuit 30 which separates only the end ID signals on the basis of the PG signal output from PG detector 13 which detects the rotating indicia on the magnetic sheet 10. The data gate pulse generator 30 produces a data gate pulse (f) to extract only the data portion on the basis of one of the four end ID signals for the four sectors designated by controller 12. The data gate pulse (f) is delivered to data gate 31, which separates only the data signal (g), inclusive of the synchronism portion, from the reproduced signal having substantially the format of Fig. 3. The separated data signal (g) is then delivered to shift register 64 and data synchronism detector 32. Synchronism detector 32 detects the synchronism bits at the head of the incoming data signal such as is shown in Fig. 4 and is composed of a shift register, a counter, a logic gate, etc. This will be described in more detail hereinafter. The clock signal (h) which is input by signal generator 33 is, for example, 3 f sc , assuming that the bit rate is f sc /2 bits/sec (PBS), where f sc = 3.579545 MHz which is the color subcarrier frequency in the NTSC system. The counter which divides the clock signal (h) by a factor, for example, of 6 is reset by the first rise of the synchronism bits. Each of the pulses of the 6-divided clock signal is adjusted to coincide with the central position of a respective one of the synchronism bits and the thus obtained clock pulses are applied as the write clock pulses to the 8-bit shift register to write the synchronism bits thereinto. The 8 outputs of the shift register are coupled to the logic gate which outputs, for example, "1" when the register output takes the pattern "01010101". Thus when the synchronism detector 32 detects the synchronism bits of data, it outputs a detection pulse (i) which is applied to signal generator 33. This resets another divide by 6 frequency circuit in the signal generator 33 which counts down the 3 f sc . Thus signal generator 33 produces write clock signal (j), reset in timing, the pulses of which are applied sequentially to shift register 64. In response to these pulses the shift register writes thereon in a bit serial manner the bit data, for example, of 8 bytes of the data signal 52 - 59 of Fig. 4 excluding the synchronism bits of the data signal. When signal generator 33 has generated write clock pulses for 8 bytes, it delivers a write end pulse (k) to controller 12. In response to the write end pulse the controller 12 starts to read the data from shift register 64. That is, controller 12 controls selector 65 such that same selects a respective one of the bytes of shift register 64 sequentially from the least significant byte (byte 0) to the most significant byte (7) and reads the corresponding data in a bit parallel manner. When this reading has been completed, controller 12 again controls data gate pulse generator 30 so that same produces a data gate pulse (f) corresponding to the end ID signal in another sector. This causes reading operation similar to the above to be repeated. This reading operation will end when it is repeated for four sectors, i.e. four times. While the data transmission (recording) and detection (reproduction) system which forms the background techniques of the present invention has just been described, this system has the following problems. Now assume that the bit rate for data recording is f sc /2 BPS, i.e., 1.7897725 MBPS and that the rotating speed of the magnetic sheet is ideally 3,600 rpm both in recording and in reproduction. Then the read clock frequency for reproduction may be 1.7897725 MHz. However, the rotation of the magnetic sheet may contain jitter due to ununiform motor rotation. The center of the concentric recording tracks may be deviated from the center of rotation of the sheet due to changes in the accuracy of the sheet being plased on the motor spindle, for example, in recording and reproduction. In such a case, the resulting reproduced signal would contain jitter. According to the inventors' experiment, the quantity of this jitter was no less than ± 2% at its worst and the data had been recorded at a bit rate of 1.7897725 MBPS was reproduced at a bit rate fluctuating between 1.754 and 1.826 MBPS. In this case, the fluctuating period is 16.7 m sec corresponding to the magnetic sheet rotation speed at 3,600 rpm (60 Hz). On the other hand, the interval of each data bit is about 36 µ sec (for 8 bytes, the bit rate is as short as 1.7897725 MBPS). Thus if data is written when the bit rate has fluctuated to 1.754 MBPS, the write clock frequency at that time should be essentially 1.754 MHz. In this case, however, data signal is only present discretely at 90-degree intervals with a width of about 36 µ sec on a single track, the period of which is 16.7 m sec. The type of codes used is an NRZ which itself has no clock pulse components. Therefore, it is difficult to cause the write clock signal to follow the frequency at 1.754 MHz using means such as a PLL and thus there is no method other than detection of the data, i.e., or writing of same into the shift register, using a fixed-frequency clock signal of 1.7897725 MHz which is the same as that used in recording. Fig. 7 illustrates an example where the data having a bit rate of 1.754 MBPS is detected or written into the shift register using a write clock frequency of 1.7897725 MHz. As shown in Fig. 7, if the write clock frequency and the data bit rate are deviated 2 % from each other, a read error will occur midway in the byte 3 (at the fourth byte) indicated by X in Fig. 7. As described above, in the data recording and reproduction system described with respect to Figs. 4 - 6, although the write clock is reset and synchronized by the first synchronism bit, the difference between the data rate and the write clock frequency due to jitter causes the relative phase of the write clock signal to shift from the data bit to be detected primarily to the adjacent bit midway in the data train (for example, at the portion shown by X in Fig. 7). Thus an error in reading results. Asynchronous methods have been employed to eliminate, or at least reduce, such filter error. It is known to use combinations of two bits, a "stop" bit at the tail end of each segment of data and a "start" bit at the head end of each consecutive segment of data to provide means for synchronisation - so-called "start-stop" synchronism. Examples of such methods are described, for example, in French Patent Application No FR-A-2275946 and in "The Electronic Engineer", vol 31 no 2, February 1972 pages DC5 to DC7, a paper entitled "Asynchronous transmission: some basic bits of data" by S. Stuart et al. Fig. 8 shows one such example in which the synchronism bits are included because they are needed to distinguish between the data and a possible dropout of the record signal during reproduction and to indicate that data will begin next. Each unit data portion is composed of a frame including one start bit, 8 serial data bits and one stop bit arranged in this order (10 bits in all). Since such form of data train causes the start bit to reset the write clock, the error in reading due to jitter is reduced. That is, as shown in Fig. 8, each time an 8-bit data is read, the write clock is reset and synchronized by the next start bit so that each of the write clock pulses is substantially stably settled at substantially the center of a respective one of the data bits. While this method alleviates the influence of jitter, it increases redundancy; for example, 10 bytes (80 bits) are needed to record 8-byte data (64 bits). That is, 16 excess code bits are added and bit utilization measure is reduced. While the above has been described on the problems with the case in which the data signal is recorded and reproduced, together with the audio signal, on and from the magnetic sheet as an example, similar problems will occur with a data signal including especially discrete data signal blocks even in recording and reproduction on and from other recording media such as magnetic tape, or in general data transmission and reception. It is also known to use single dummy bits for data synchronisation. In United States Patent Specification No US-A-3903504 a single bit data transition is used and is inserted between segments of biphase coded data. This single bit comprises complimentary sequential pulses defining a transition edge. These pulses are of different width to those employed for coding data and are therefore readily distinguishable as constituting dummy bits. The transition edge may be either negative- or positive-going to distinguish message and data words respectively, irrespective of bit values. In United States Patent Specification No US-A-3815108, also European Patent Application No EP-A-0174807 and Japanese Patent Specification No JP-A-545313 reported in Patent Abstracts of Japan vol 3, no 26 (E-95) 6 March 1979 page 85, a single dummy bit is inserted between segments of NRZ coded data. Each single dummy bit is inserted to follow the tail end bit of a respective one of the segments, and is in inverted relationship to the respective tail end bit regardless of its value. The present invention is intended to provide a method of data transmission in which the transmitted data is modified to facilitate accurate detection even though the data bit rate following reception or reproduction may fluctuate. It is also intended to increase efficiency in data transmission, reduce bit redundancy and increase information density. Accordingly there is provided a method of data transmission comprising the following steps: a first step of dividing serial data into bit segments (1, 2, 3, 4, 5, 6); and a second step o providing a single dummy bit (start bit) for each segment; which method is characterised in that: each single dummy bit is inserted in front of the head bit (0) of a respective one of said segments (1, 2, .. ..6), which single dummy bit (start bit) is in inverted relationship to said head bit (0) regardless of the value of said head bit (0). In the drawings: Fig. 1 illustrates recording tracks on a magnetic sheet; Fig. 2 illustrates an audio track consisting of divided sectors; Fig. 3 illustrates the arrangement of an audio signal, an ID signal and a data signal contained in a single sector; Fig. 4 illustrates the details of the format of the data signal of Fig. 3; Fig. 5 is a block diagram of a circuit to generate the signal of Fig. 4; Fig. 6 is a block diagram of one example of a reproduction system to reproduce the data signal of Fig. 4; Fig. 7 illustrates an inconvenience occurring in the reproduction system of Fig. 6 in the case of the data signal of Fig. 4; Fig. 8 illustrates the details of another format of the data signal which can be employed to avoid the problem illustrated in Fig. 7; Fig. 9 illustrates one example of the format of the data signal used in an embodiment of the present invention applied to the recording and reproduction of the audio and data signals described in Figs. 1 to 4; Fig. 10 is a block diagram showing one embodiment of a circuit to produce the data signal shown in Fig. 9 together with the ID signal; Fig. 11 is a block diagram showing one embodiment of a reproduction system to reproduce the data signal shown in Fig. 9; Fig. 12 is a block diagram of a specific structure of the start bit detection circuit and signal generator of Fig. 11; Fig. 13 is a timing chart showing the inputs and outputs of main blocks of Fig. 12; and Fig. 14 is a flowchart showing the operation for reproducing the data signal shown in Fig. 9 using a microcomputer. One embodiment of the present invention will be described in which the present invention is applied to recording and reproducing of the data signal as an additional signal for recording and reproducing of the audio signal described in Figs. 1 - 4. Fig. 9 illustrates the format of the data signal used in the particular embodiment. The particular embodiment of Fig. 9 is different, for example, from the example of Fig. 8 in that the former uses no stop bit, but only a start bit provided to each 1-byte data train. In this case, the start bit is provided as a dummy data in such a manner that if the head least significant (left end) bit of a 8-bit serial data is "0", the start bit is "1" and if the head bit is "1", the start bit is "0"; i.e. inversion occurs necessarily between the start bit and the head least significant bit of the 8-bit data. This information of inversion (inversion edge) is used for resetting the clock to write data into the shift register and determining the timing of detecting each bit data. In this case, the synchronism bits are also provided to distinguish data from possible dropout pulses and to indicate that the data will start next. Fig. 10 shows an example of a circuit to generate a data signal having the format shown in Fig. 9. Note that in Fig. 10 the same reference numeral as that in Fig. 5 denotes the same element as that in Fig. 5 and that the same reference numeral with a prime in Fig. 10 denotes an element corresponding to that of Fig. 5. Assume that shift register 63', here, has a capacity of 80 bits and is used in 9 divided frames 0 - 8 for the purpose of handling data. In frame structure, only the least significant bit frame 0 contains 8 bits and other frames 1 - 8 each contains 9 bits. Thus controller 12' and selector 62' each have a structure compatible with these elements. In the above structure, data is written from controller 12' into shift register 63' via selector 62' under control of controller 12'. This writing is performed, for example, in order of frame number (low to high or reversely). In this case, controller 12' controls shift register 63' and the data output from controller 12' such that same writes the 8 synchronism bits "01010101" into frame 0, each data of 9 bits in all into a respective one of frames 1 - 6, the 9-bit data consisting of 8-bit serial data and 1-bit dummy or start data provided before the head bit of the serial data, the dummy data bit being in inverted relationship to the head bit; and each 9-bit CRCC subdata into a respective one of frames 7 and 8, the 9-bit subdata consisting of a respective one of the 8-bit halves of the 16-bit CRCC and 1-bit dummy data provided before the head bit of that 8-bit half, the just-mentioned dummy data being in inverted relationship to the 8-bit half head bit. Thus if the contents of shift register 63' at this time is followed sequentially from frame 0 or LSB side (right extreme in Fig. 9) to frame 8 or MSB side, it will be seen that the data is arranged just as shown in Fig. 7. When this writing has ended, controller 12' enables signal generator 60, in the same way as is mentioned above, to generate a write clock signal (a') at predetermined timing (determined, for example, according to the PG signal, in the same way as is mentioned above) synchronous with rotation of the magnetic sheet. These write clock pulses (a') cause the contents of shift register 63' to be read sequentially from frame 0 to frame 8 in a bit serial manner and thus the signal train having the format of Fig. 9 is obtained at the output (b) of shift register 63'. The output (b) of shift register 63' is combined at adder 61 with the start and end signals (c) from signal generator 60. The output (d) of adder 61 is then combined with a compressed audio signal, in the same way as is mentioned above, into a signal such as is shown in Fig. 3. The signal is then subjected to processing such as emphasis and frequency modulation and then recorded on the magnetic sheet via the magnetic head. Also in the particular embodiment, shift register 63' has its leading end bit output connected to its tail end bit input. Thus in order to record data for one sector, after data is read once, it is circulated and written again into shift register 63' and when the second and subsequent sectors are written sequentially, the same data is again and again read and used for recording. One example of a circuit to reproduce the signals recorded in the above manner will be described with respect to Fig. 11. Note that in Fig. 11 the same reference numeral as that in Fig. 6 denotes an element similar to that of Fig. 6 and that in Fig. 11 the same reference numeral as that in Fig. 6 but having a prime denotes an element corresponding to that of Fig. 6. In this embodiment, in order to correspond to the signal format of Fig. 9, a start bit detector 100 is provided between data synchronism detector 32 and signal generator 33'. Signal generator 33' is arranged to be reset by the output from start bit detector 100. In the illustrated structure, the processes up to separation of the data signal (g) by data gate 31 is quite the same as with Fig. 6. The data signal (g) separated by data gate 31 is delivered to shift register 64, data synchronism detector 32 and start bit detector 100. At this time, a clock signal (h) (for example, of 3 fsc Hz, assuming that the data bit rate is fsc/2 BPS) generated by signal generator 33' is applied to detector 32. On the other hand, start bit detector 100 and signal generator 33' is impressed with the data synchronism detection output (i), as a control signal, indicative of data synchronism detection (for example, a pulse output maintained high for a predetermined interval in response to the trailing edge of the last bit "1" of the "01010101" when the last bit "1" is detected) from data synchronism detector 32. Start bit detector 100 includes a flip-flop, a logic gate, etc., as will be described later. It responds to the output (i) of data synchronism detector 32 to detect the inverting edge between the start bit of the data signal (g) from data gate 31 and the following head bit of the 8-bit data bits. Upon detecting of the inverting edge, detector 100 produces a pulse (1) which is delivered to signal generator 33' thereby to reset a divide by 6 counter which produces a write clock pulses to shift register 64. On the other hand, each time signal generator 33', after reset, produces 9 write clock pulses (j) to shift register 64, i.e. one-frame processing has ended, it produces a pulse (m), synchronous with the leading edge of the start bit, to start bit detector 100 thereby to cause same to repeat detection of the inverting edge. Note that in this case, signal generator 33' interrupts the write clock pulses (j) to shift register 64 at the timing corresponding to the head of the data frame, i.e. the start bit. Thus signal generator 33' produces a write clock pulse (j) synchronous with the inverting edge between the start bit and the following head of the data and hence the start bit thereby to permit data to be written into shift register 64 correctly. When the writing of all the data for 8 frames into shift register 64 (however, the net data for 8 bytes excluding the start bits) has ended, signal generator 33' outputs a data end signal (k) in the same way as is described above. In response to this signal (k), controller 12'(12) processes data via selector 65. Fig. 12 shows one embodiment of the start bit detector 100 and signal generator 33'. In signal generator 33', an oscillator 331 generates a basic clock signal of 3 fsc (hz) which is divided by a divide by 6 counter 332 into a data writing reference clock signal (Fig. 13(I)). The outputs of counter 332 are delayed by 1/2 data bit by a timing adjusting delay circuit 338 so that the data detection points (writing points) are at the respective central positions of data bits (Fig. 13 (J)). The delayed counter outputs are then delivered as writing clock pulses to AND gate 339. On the other hand, the output of the counter 332 is delivered to a divide by 9 ring counter 333 which then outputs one pulse (Fig. 13(C)) in response to every ninth output pulse from counter 332. The output of counter 333 is delivered to start bit detector 100, to one input of AND gate 336 via inverter 335, and further to a divide by 9 ring counter 337. Ring counter 337 counts 9 output pulses from counter 333 and outputs one pulse. Ring counters 333, 337 are reset by the synchronous detection output (i) (Fig. 13 (K)) from data synchronism detector 32. The detection output (i) is input via flip-flop 334 to the other input of AND gate 336, the output (Fig. 13 (M)) of which is applied as a write clock pulse (j) to shift register 64. In start bit detector 100, OR gate 101 receives the synchronism detection output (i) (Fig. 13 (B)) and the output (Fig. 13 (C)) from data synchronism detector 32 and counter 333, respectively. The output of OR gate 101 is delayed 1/2 data bits by delay circuit 102 (Fig. 13 (D)). As described above, the output (i) of synchronism detector 32 is a signal maintained, for example, high for a predetermined interval (here, 2-bit interval) synchronously with the falling edge of the eighth bit of the 8-bit synchronism signal, as shown in Fig. 13 (B). The output of counter 333 is a signal maintained high for just the start bit interval, as shown in Fig. 13(C). It is delayed 1/2 bits by delay circuit 102 so that the rise edge of the thus delayed counter output coincides with the central position of each bit of the output of counter 333. The output of delay circuit 102 is delivered to a rise-synchronous mono-multivibrator (any mono-multivibrators used herein are hereinafter referred to as the "MONO-MULTI") 103 which then produces a pulse maintained high for just 1 bit synchronously with the rise of the output of delay circuit 102, as shown in Fig. 13 (E). The output pulse from MONO-MULTI 103 is delivered to AND gate 107. On the other hand, the data output signal (g) (Fig. 13(A)) from data gate 31 is delivered simultaneously to a rise-synchronous MONO-MULTI 104 and a fall-synchronous MONO-MULTI 105. MONO-MULTIs 104 and 105 produce a pulse synchronous with the rise of each bit of the incoming signal (g) and a pulse synchronous with the fall of each bit of the signal (g), respectively, (Figs. 13(F) and (G)), each such pulse having a width narrow enough compared with the 1-bit interval of the incoming data signal (g). These pulses are input to the other input of AND gate 107 via OR gate 106. Thus the output of AND gate 107 is a narrow pulse synchronous with the inverting edge between the start bit and the directly following head bit of the data, as shown in Fig. 13(H). This narrow pulse is applied as the start bit detection pulse (1) to signal generator 33'. In the signal generator 33', the write clock generating counter 332 is reset by the rise of the start bit detection pulse (1) (Fig. 13(H)) and hence counter 332 is reset by each inverting edge between the associated start bit and the directly following head bit of the data, and the write clock (j) is synchronized with the inverting edge. In the above, counter 332 outputs a pulse when it is reset and thereafter each time it receives 6 pulses from oscillator 331, the pulse output being in synchronous with the leading edge of each data bit. Thus in order to obtain the write clock signal (j) coincident with the central position of each data bit, the output of counter 332 is delayed 1/2 bits by delay circuit 338 using a 3 fsc clock signal from oscillator 331. Counter 333 is provided to know the head or start bit of each frame consisting of 9 bits) of the 8-frame data signal following the 8-bit synchronism signal. Inverter 335, and AND gates 336, 339 are provided to interrupt the write clock signal (j) at that start bit (see Fig. 13 (C), (L),(M)). Counter 337 is provided to know the end of the eighth frame since the number of data frames is 8, and the output of the counter 337 is delivered as the data end signal (k) to controller 12 (12'). Flip-flop 334 is provided to know the second to ninth frame data intervals following the synchronism signal out of the 9-frame data signal, inclusive of the synchronism signal (see Fig. 13 (K)). The synchronism detector 32 is composed of a shift register 27 which stores the latest 8-bit data of a data signal input thereto via data gate 31, and a one-shot multivibrator which is maintained high for a fixed time duration in response to the output of a digital comparator which compares the output of shift register 27 and the synchronism signal pattern "01010101". Fig. 14 shows the flow of the operations carried out for reading the above-mentioned data using a microcomputer. First, the registers and counters are initialized (step 1). The end edge of the end ID signal is searched to predict the position where the data signal is recorded (step 2). The data is then entered to search the syncronism bits (step 3). It is then determined whether the data level is low or not because the first one of the synchronism bits is at low level (step 4). Data is entered sequentially and the determination is repeated until the low level input is ascertained. When low level data has been entered, it is counted by a bit counter (step 5). Subsequently, data is entered sequentially (step 6). It is determined whether or not the data is at high level since the second one of the synchronism bits is at high level (step 7). Data entering and determination are repeated until high-level data bit is entered. When high-level data has been entered, it is counted by a bit counter (step 8). It is determined whether or not all the synchronism bit (8 bits) have been entered and determined (step 9). The steps 3 to 9 are repeated for input data until 8 counts are attained. For bit level sampling, 1 bit corresponds to 6 clock pulses. Level determination of the synchronism bits is performed immediately after the first clock pulse, i.e. the rising or falling edge thereof. Level determination of the start bit is performed using one clock pulse at a position jumped by 8 clock pulses from the position where the last synchronism bit is determined, i.e. at the central position of the start bit. Thus data is entered eight clock pulses after determination of all the eight synchronism bits has been completed (step 11). Since the start bit is in inverted relationship to the directly following head bit of the data, level determination is first performed on the assumption that the data level is high (step 12). If the level is not high, the level is low and thus the head bit of the data is high. Thus in order to detect a rising edge from low to high, data is sequentially entered (step 15) and level determination is performed (step 17). Steps 15 and 16 are repeated until high level is detected. The position where the data level is determined high at step 16 is directly after the low-to-high rising edge. Jump is performed by two clock pulses on the basis of the low-to-high edge change, the level is read at the central position of the head bit of the data and the level value is stored (step 17). That is, a high-level value is stored as the data. If the level is determined high at step 12, the data head bit level will be low. Thus in order to find a high-to-low falling edge, data is sequentially entered (step 13) and it is determinated whether or not the level is low (step 14). Steps 13 and 14 are repeated until low level is detected. When the level has been determined low at step 14, this means that the high-to-low falling edge has been detected. Thus jump is performed by 2 clock pulses on the basis of the position of the falling edge, the level of the head bit of the data is read and the read level value is stored; i.e., the low-level value is stored as the data (step 17). A data counter is caused to count data synchronously with the rising edge or the falling edge between the start bit and the data head bit (step 18). Jump is then performed by a total of 6 clock pulses consisting of the remain 3 bolck pulses for the head bit and the former 3 clock pulses for the first bit of the next data in order to shift the position where the data level is read from the center of the data head bit to the central position of the next data bit (step 19). Since the position where the data is read is brought to the central position of the data bit by step 19, that data level is entered (step 20), level determination is performed and the level value is stored (step 21). When the data has been stored, the data counter is caused to count one (step 22). It is determined whether or not 8 data bits have been read, inclusive of the head bit of the data (step 23). If the 8 bits have not been read yet, control passes to step 19 where jump is performed to the central position of the next data bit and data is entered again. When the central position of the data bit is read by 6-clock pulse jump on the basis of the start bit, a clock deviation such as jitter is 2%. If the number of data is 8 bits or so, no clock deviations will occur and correct jump to the central position of the data bit can be attained at all times. When the reading of the 8-bit data has been completed, byte counting is performed by one (step 24). If the 8-byte counting has not been completed, the data counter is cleared (step 26). Six-clock pulse jump is then performed to shift to the central position of the start bit of the next byte (step 27). Steps 11 to 25 are repeated to read respective data at their start bits. When the reading of the 8-byte data has been completed, the stored data is processed (step 29), thereby ending the flow. In the manner mentioned above, data can be correctly read at all times on the basis of the inverting edge between the start bit and the head bit of the data. Provision of counters eliminates the need of the stop bit. Briefly, the above embodiment eliminates the stop bit and uses only the start bit in the signal arrangement of Fig. 8. In the above, description has been made on the assumption that 8-bit data is written in the 8 bit positions of each of data frames 2 - 9 subsequent to the start bit of that frame. However, when data is not written in all the 8 bit positions, for example, in the case of 6-bit or 4-bit data, the data may be put close to the left or right in each frame, which would facilitate data processing. Especially, putting data close to the right causes the start bit to be at high level at all times. Here, whether data has been written in all the bit positions of each frame or not, a start bit is placed at the beginning of each frame. Thus in the case of putting data close to the right, no data is written in the head bit position directly following the start bit. Thus, the head bit of data may be significant or insignificant data. In the above embodiments, bit data can be detected at all times at substantially the center of each bit in spite of possible fluctuation of the data bit rate due to jitter, etc. A bit utilization measure is good for detection synchronism stipulation. In addition, since data can be handled in units of 1 byte = 8 bits, the present invention is applicable satisfactorily to a circuit using a conventional 8-bit microcomputer. Note that the data signal may be placed directly after the start ID signal instead of after the end ID signal. According to this method, data signal can be accessed very rapidly for reproduction of the recorded signal (for example, in a time base extension memory used during reproduction), audio can be rapidly reproduced satisfactorily using data signal. Especially, while, as mentioned above, the position of the end ID signal varies according to the length of the audio signal before the end ID signal, the position of the start ID signal is constant in the respective sectors. Therefore, the detection of the data signal is very easy. Alternatively, for example, if two memories each having a capacity for one sector are used, one for an even sector and the other for an odd sector, and the signals stored in the memories are read alternately in units of a sector and recorded on a magnetic sheet, no data signals are superimposed on the magnetic sheet and damaged and good recording can be performed in spite of a slight change in the timing of switching the memories. While the embodiment in which the present invention has been applied to recording and reproducing a data signal as the additional signal to the audio signal has been shown and described, it goes without saying that the present invention is not limited to such recording and reproduction alone, as pointed out above. Especially, the present invention is also effective in transmission and detection of a data signal including discrete data signal blocks. As described above in detail, according to the present invention, improved data transmission and detection systems in which each bit data of the data signal can be detected correctly in spite of possible fluctuations in the data bit rate, data can be handled in units of a byte with low redundancy and hence high information density.

Claims: A method (Fig. 9) of data transmission comprising the following steps: a first step of dividing serial data into bit segments (1, 2, ..... 6); and a second step of providing a single dummy bit (START BIT) for each segment; which method is characterised in that: each single dummy bit is inserted in front of the head bit (0) of a respective one of said segments (1, 2, .. .. 6), which single dummy bit (START BIT) is in inverted relationship to said head bit (0) regardless of the value of said head bit (0). A method as claimed in claim 1, wherein said serial data is NRZ coded. A method as claimed in either preceding claim, wherein said serial data is divided into 8-bit segments (1, 2, .... 6). A method as claimed in any one of the preceding claims, comprising: a third step wherein error detection data (CRCC: 7,8) is added to follow said serial data (1, 2, .... 6). A method as claimed in any one of the preceding claims, comprising: a fourth step wherein a sequence of synchronisation data bits (0) is added to precede said serial data (1, 2, .... 6). A method as claimed in claim 5 when depending from claim 3, wherein said sequence (0) is of 8-bits.

Inventors: KIMURA, NORIO, SAKATA, TSUGUHIDE, TAGUCHI, TOMISHIGE, TAKEI, MASAHIRO
Applicants: CANON KABUSHIKI KAISHA
Application year: 1986
Main classification: G11B20
IPC codes: G11B20, H04L7