SEMICONDUCTOR MEMORY DEVICE HAVING STACKED-CAPACITOR TYPE MEMORY CELLS AND A MANUFACTURING METHOD FOR THE SAME

Abstract: A semiconductor memory device including a plurality of stacked-capacitor type memory cells, each having a capacitor (C2) for storing data and a transfer-gate transistor (Q2) for transferring data to the capacitor. The transistor includes a gate connected to or constituted by a word line (24-2) and formed by an insulating layer (23-2), and source and drain regions (27 and 28). Each of the memory cells has a first in­ sulating layer (25-2) covering the gate of the transfer-gate tran­ sistor. The capacitor in each memory cell includes a second in­ sulating layer covering another word line (24-3) adjacent to the one word line (24-2) and having a larger thickness perpendicu­ lar to a plane of a substrate than that of the first insulating layer covering the gate, a second conductive layer (29-2) which is in contact with one (28) of the source and drain regions of the transistor, extends over the gate through the first insulating layer and covers the second insulating layer, a third insulating layer (30-2) formed on the second conductive layer, and a third conductive layer (31) extending over the third insulating layer. The semiconductor memory device also includes an addi­ tional conductive layer (29-1) directly connected to the other (27) of the source and drain regions of the transistor in the memory cell and extending onto the gate of an adjoining tran­ sistor over said first insulating layer covering thereon. Each bit line (33) is connected to the other (27) of the source and drain regions through the additional conductive layer (29-1). The semiconductor memory device further includes a peripheral circuit including transistors, each having source and drain regions (55, 56) and a gate electrode (52) which is en­ tirely covered by the second insulating layer (26). The source and drain regions are directly connected to wiring lines (58-1, 58-2). Also disclosed is a method for manufacturing a semicon­ ductor memory device having the above construction.

Description: The present invention relates to a semiconductor memory device having stacked-capacitor type memory cells for example a MIS dynamic semiconductor memory device, and a manufacturing method for the same. MIS memory cells of a one-transistor one-capacitor type are now in use in MIS dynamic memory devices and a fine lithographic technology has been developed to reduced the size of the elements of each memory cell, thereby obtaining a large capacity, highly integrated semiconductor device. However, there is a limit to the high integration and large capacity that can be obtained by size reduction alone. In addition, a size reduction of the memory cells, and accordingly, a reduction in the capacity of memory capacitors, increases the generation rate of soft errors due to radioactive rays. The shortening of a channel length in transistors also increases the occurence of harmful effects due to hot electrons and hot holes. To improve memory cells of a one-transistor one-capacitor type, stacked-capacitor type memory cells have been proposed (see: Technical Digest of the Institute of Electronics and Communication Engineers of Japan, SSD80-30, 1980, July). Each stacked-capacitor type memory cell includes a transfer-gate transistor, which is the same as that of the conventional memory cell, and a capacitor, which is an electrode extending over a thick field-insulating layer, a counter electrode extending over its own transfer-gate transistor, and an insulating layer therebetween, thereby increasing the capacitance of the capacitor. Japan Unexamined Patent Publication (Kokai) No. 55-154762, published on December 2, 1980, discloses a semiconductor memory device having stacked-capacitor type memory cells, each of which includes a capacitor formed by a dielectric layer and two opposing conductive layers on the surfaces thereof placed above a transistor region for increasing the capacitance of the capacitor while maintaining a high integration. EP-A-0 112 670 discloses another semiconductor memory device having stacked-capacitor type memory cells. In this device, the memory cell capacitor again comprises a dielectric layer and two opposing conductive layers (electrodes), and the lower conductive layer is separated from a word line by a single dielectric layer. The prior art, however, is disadvantaged by a low integration and lack of reliability, etc. These advantages will be discussed later with reference to a specific example. According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of said word lines and one of said bit lines and including a capacitor for storing data and a transistor cooperably connected to said capacitor for transferring data to said capacitor; said word lines being formed by a first conductive layer; said transistor in each said memory cell including a gate connected to or formed by one of said word lines, a gate insulating layer and source and drain regions; each of said memory cells having a first insulating layer covering said gate of said transistor, and a first insulating layer and a second insulating layer covering another word line adjacent to said one word line, the second insulating layer having a larger thickness than that of said first insulating layer covering said gate; said capacitor in each said memory cell including: a second conductive layer which is in contact with one of said source and drain regions of said transistor in the memory cell, which extends onto the gate of said transistor over said first insulating layer, and which covers said second insulating layer; a third insulating layer formed on said second conductive layer; and a third conductive layer extending over said third insulating layer; one of said bit lines being connected to the other of said source and drain regions of said transistor in each of said memory cells. An embodiment of the present invention may provide a stacked-capacitor type semiconductor memory device wherein the stacked-capacitors have an increased capacitance, and including highly integrated memory cells. An embodiment of the present invention may provide a stacked-capacitor type semiconductor memory device less liable to short-circuits between bit lines and word lines. An embodiment of the present invention may provide a stacked-capacitor type semiconductor memory device less liable to bit line breakage. An embodiment of the present invention may provide a method of manufacturing the above stacked-capacitor type semiconductor device. Preferably, the semiconductor memory device also includes an additional conductive layer directly connected to the other of the source and drain regions of the transistor in the memory cell and extending over the gate of the adjoining transistors through the first insulating layer covering the gate. Each bit line is connected to the other of the source and drain regions through the additional conductive layer. Preferably, the semiconductor memory device further includes a peripheral circuit including transistors, each having source and drain regions and a gate electrode which is entirely covered by the second insulating layer. The source and drain regions are directly connected to wiring lines. According to another aspect of the present invention, there is provided a method for manufacturing the above-specified device, including the steps of: forming the first conductive layer on an insulating layer on the substrate and the first insulating layer on said first conductive layer; patterning said first insulating layer to define the word lines of the semiconductor memory device; patterning said first conducting layer with masking by said patterned first insulating layer to form the word lines; forming the second insulating layer on the whole substrate; and etching said second insulating layer with protecting portions of said second insulating layer on the word lines to be formed thereon from the etching to expose drain and source forming regions of said transistor in said substrate so that a thickness of insulating layer, including unetched first and second insulating layers on said plurality of word lines on which said capacitor is to be formed thereon is greater than that of other insulating layers remaining after said etching on other word lines. Reference is made, by way of example, to the accompanying drawings, in which: Fig. 1 is a plane view (plan view) of a previous semiconductor memory device having stacked-capacitor type memory cells; Fig. 2 is a sectional view of the semiconductor memory device shown in Fig. 1, taken along a line X-X'; Fig. 3 is an equivalent circuit diagram of the device shown in Figs. 1 and 2; Fig. 4 is a plane view of an embodiment of a semiconductor memory device having stacked-capacitor type memory cells in accordance with the present invention; Fig. 5 is a sectional view of the semiconductor memory device shown in Fig. 4, taken along the line X-X' in Fig. 4; Figs. 6a to 6ℓ are sectional views explaining the production of the semiconductor memory device shown in Fig. 5; Figs. 7a to 7c are enlarged sectional views explaining the manufacturing process of the semiconductor memory device shown in Fig. 5; Fig. 8 is an enlarged view of the semiconductor memory device shown in Fig. 6ℓ; and Figs. 9a to 9f are sectional views explaining the production of other parts in the semiconductor memory device shown in Fig. 3. Before describing the preferred embodiments of the present invention, an explanation will be given of a previous semiconductor memory device. Figure 1 is a plane view of a previous semiconductor memory device. Figure 2 is a sectional view of the semiconductor memory device shown in Fig. 1, taken along a line X-X'. The semiconductor memory device is a stacked-capacitor type memory device, more particularly a folded bit-line type semiconductor memory device as shown by the equivalent circuit diagram in Fig. 3. Generally, in a dynamic-type memory-cell configuration, two types of systems are known; the folded bit-line type and the open bit-line type. The former type has a pair of bit lines BL₀ and BL₀ , as shown in Fig. 3, arranged in parallel with each other. Specifically, the bit line BL₀ is folded through a sense amplifier SA₀. The folded bit-line type memory device has a higher immunity to noise than the open bit-line type, because the voltage difference between the bit lines BL₀ and BL₀ is not affected by the noise voltage. In Fig. 3, references Q₁ to Q₄ designate transfer-gate transistors, C₁ to C₄ capacitors, E₀ and E₁ electrodes for each capacitor, and WL₀ to WL₃ word lines. Each memory cell consists of a capacitor and transfer-gate transistor and is arranged at an intersection defined by the bit line BL or BL and the word line WL. In Figs. 1 and 2, the folded bit-line type semiconductor memory device includes a p⁻₋type silicon substrate 1, a field silicon oxide film 2, an n⁺-type diffusion region 3a functioning as a drain of the transfer-gate transistor Q₂ , and an n⁺₋type diffusion region 4a functioning as a source of the transfer-gate transistor Q₂. The semiconductor memory device also includes gate oxide layers 5-1a and 5-2a, each being a gate of a transfer-gate transistor, first to fourth word lines 6-1 to 6-4, formed as first conductive layers and made of, for example, polycrystalline silicon PA, and first insulating layers 7-2 to 7-4 covering the first conductive layers. The semiconductor memory device further includes electrodes 8-1 and 8-2 for the capacitors, formed as second conductive layers and made of, for example, polycrystalline silicon PB, second insulating films 9-1 and 9-2 of dielectric material, and electrode 10, formed as a third conductive layer and made of polycrystalline silicon PC. In addition, the semiconductor memory device includes layer insulation films 11-1 and 11-2, a contact window 12a, and a bit line 13a of, for example, aluminum. In Fig. 2, the second insulating films 9-1 and 9-2, disposed between the opposed second and third conductive layers 8-1 (8-2) and 10, both functioning as electrodes, function as the capacitors C2 and C3. Note that the capacitors are formed in vacant spaces which extend above the adjoining word lines, in a stack form, and have a considerably large area. This large area ensures a considerably large capacitance when the semiconductor memory device is further integrated, and avoids a reduction of the gate length of the transfer-gate transistor. This increases the immunity to soft errors due to alpha (α) rays and harmful effects due to hot electrons and hot holes. The semiconductor memory device, however, still suffers from the following disadvantages. A further improvement is required in the capacitance of the capacitors in the semiconductor memory device, without increasing the area occupied by the capacitors, together with an improved integration and density of the semiconductor memory device. In addition, the connection of the bit line 13a with the second n⁺-type diffusion region 4a, which acts as the source of the transfer-gate transistor when the read operation is effected or the drain of the transfer-gate transistor when the write operation is effected, is achieved by means of the contact window 12a. The contact window 12a is formed on the diffusion region 4a by the mask aligning with the fourth insulating layer 11. In other words, the contact window 12a must be apertured at a portion between the word lines 6-1 and 6-2. In this regard, positional space margin of the mask alignment must be considered. To prevent the connection between the bit line 13a and the word lines 6-1 and/or 6-2 by inadvertent removal of the layer insulation film 11 and the insulating layer adjacent to corners of the word lines 6-1 and 6-2 during etching, etc., the distance D₁ between the adjoining word lines 6-1 and 6-2 formed by polycrystalline silicon layer PA must be further increased and, of course, the length of the diffusion region 4a must be increased. As clearly understood from the above description, this will interfere with the desired high integration. Further, the contact window 12a is deep and this tends to form a large step around the window, which increases the probability of breakage of the bit line 13a. The aforementioned Japanese Unexamined Patent Publication No. 55-154762 discloses a stacked type memory cell device in which a polycrystalline silicon pad is formed within the bit line contact area under the bit line to lessen the step around the contact window. This alleviates the problem of bit line breakage due to the step. However, this memory cell structure is not effective for reducing the marginal distance needed to prevent inadvertent short-circuits between the bit line 12a and the word lines 6-1 and 6-2 around the contact window. An embodiment of the semiconductor memory device in accordance with the present invention will now be explained. Figure 4 is a plane view of the embodiment of the semiconductor memory device according to the present invention. Figure 5 is a sectional view of the semiconductor memory device, taken along a line X-X' shown in Fig. 4. The semiconductor memory device is also a stacked-capacitor and folded bit-line type semiconductor memory device, as shown by the equivalent circuit in Fig. 3. In Figs. 4 and 5, the semiconductor memory device includes a p⁻-type silicon substrate 21, a field silicon oxide film 22, an n⁺-type diffusion region 28, an n⁺-type diffusion region 27, and gate oxide layers 23-1 and 23-2 having a normal thickness approximately 400 Å (40 nm) to 500 Å (50 nm). The diffusion regions 27 and 28 and gate oxide layers 23-1 and 23-2 form a transfer-gate transistor Q2. The semiconductor memory device also includes first conductive layers 24-1 to 24-4, each having an n⁺-type conductivity, made of polycrystalline silicon layer PA, and having a thickness of approximately 3000 Å (300 nm) to 5000 Å (500 nm), and functioning as a word line and also functioning as or connected to a gate electrode of the transfer-gate transistor with the cell area, and first insulating films 25-1 to 25-4 covering each word line 24 made of silicon oxide (SiO₂) or silicon nitride (Si₃N₄) , and having a thickness of approximately 2000 Å (200 nm). The construction set forth above substantially conforms to that shown in Figs. 1 and 2. The semiconductor memory device further includes second insulating layers 26-1A (not shown) and 26-1B covering sides of the conductive layer 24-1, 26-2A and 26-2B covering sides of the conductive layer 24-2, 26-3 covering the conductive layer 24-3 and the first insulating layer 25-3, and 26-4 covering the conductive layer 24-4 and the first insulating layer 25-3. The insulating layers 26-3 and 26-4 above the conductive layers 24-3 and 24-4 may have a thickness of approximately 4000 Å (400 nm) and function as dielectric films for forming the capacitors C2 and C3. The semiconductor memory device includes second conductive layers 29-1 to 29-3 having an n⁺-type conductivity, a thickness of approximately 1000 Å (100 nm) to 3000 Å (300 nm), and made of polycrystalline silicon PB, directly connected to the diffusion region 28 and functioning as one electrode for a capacitor, third insulating films 30-1 and 30-2 of silicon oxide or silicon nitride having a thickness of approximately 200 Å (20 nm) to 300 Å (30 nm) and also functioning as a dielectric film for forming the capacitors C2 and C3, and a third conductive layer 31 having an n⁺-type conductivity, a thickness of approximately 1000 Å to 3000 Å and made of polycrystalline silicon PC, and functioning as another electrode for the capacitor. A capacitor means consisting of the electrodes 29-2 and 29-3 and 31 and the capacitive elements 26-3 and 26-4, and 30-2 and 30-3 is arranged above the surface of the substrate in a stacked form. Other capacitor means can be further stacked, if required. The semiconductor memory device further includes an island-form conductive layer 29-1, providing an interface conductive layer. The island-form conductive layer 29-1 is made of a polycrystalline silicon layer formed simultaneously with the second conductive layers 29-2 and 29-3 through a common deposition and patterning process. Accordingly, the layer 29-1 has a thickness of approximately 1000 Å (100 nm) to 3000 Å(300 nm). The island-form conductive layer 29-1, on one hand, is directly connected to the diffusion region 27 and, on other hand, extends over the word lines 24-1 (one of the adjacent word lines other than its own gate) and 24-2 with the insulating films 25-1 and 25-2 and the insulating films 26-1B and 26-2A interposed therebetween. Reference 34 designates a contact window. In Fig. 5, the island-form conductive layer 29-1 may be formed separately from the second conductive layers 29-2 and 29-3. It may be, however, advantageously formed with the second conductive layers 29-2 and 29-3 in the same process for forming the second conductive layers 29-2 and 29-3, as will be explained later. The semiconductor memory device includes layer insulation films 32-1 and 32-2 of, for example, phosphosilicate glass (PSG) having a thickness of approximately 8000 Å (0.8 µm) to 10000 Å (1 µm), a bit line 33 of, for example, aluminum, and a protective layer 35 of, for example, phosphosilicate glass. The bit line 33 is in direct contact with the island-form conductive layer 29-1 at the contact window 34, and thus comes into electric contact with the diffusion region 27 indirectly. In Fig. 5, the second insulating layers 26-3 and 26-4 are provided above the word lines 24-3 and 24-4 in addition to the first insulating layers 25-3 and 25-4, respectively. The word lines 24-2 and 24-4 correspond to the word line 6-3 and 6-4 in Fig. 2. The insulating layers 25-3 and 25-4 correspond to the insulating layers 7-3 and 7-4. The thickness of the insulating layers 26-3 and 26-4 ,or the total thickness of layers 25-3 and 26-3, may be approximately 6000 Å (0.6 µm). This results in an increment of the capacitance of each stacked capacitor of approximately 10 to 20 percent, without increasing the area occupied in plane. In addition, the n⁺-type impurity diffusion regions 27 and 28, which are the source and drain of the transfer-gate transistor, are formed in a so-called self-alignment manner, as will be described later with reference to Figs. 6a to 6ℓ. This self-alignment allows a position margin and facilitates the manufacture of the semiconductor memory device. Furthermore, the conductive layers 24-1 and 24-2 as the word lines are covered by the insulating layers 26-1A and 26-1B, and 26-2A and 26-2B, at the sides thereof, respectively. Provision of the side insulating layers 26-1B and 26-2A prevents contact with the conductive layers 24-1 and 24-2, and the island-form conductive layer 29-1 as well as the bit line 33. As a result, a distance D₂ between the conductive layers 24-1 and 24-2 may be made shorter than the distance D₁ shown in Fig. 1, thereby obtaining a higher integration of the semiconductor memory device. Due to the provision of the island-form conductive layer 29-1, the depth of the bit line 33 at the contact window 34 may be reduced, reducing the possibility of a breakage of the bit line 33 at the contact window 34, and accordingly, improving the reliability of the device. The manufacturing method of the semiconductor memory device shown in Figs. 4 and 5 will now be explained with reference to Figs. 6a to 6ℓ. In Fig. 6a, first, the field silicon oxide layer 22 of silicon oxide (SiO₂) and having a desired thickness is formed on the p⁻-type silicon semiconductor substrate 21 having a predetermined specific resistance by a normal selective oxidation process. Then the silicon oxide layer 22, which is used as a mask during the above selective oxidation process, is removed to expose an active region 41 in which the transfer-gate transistor may be formed. Next, the gate oxide insulating layer 23 is formed on the transfer-gate transistor forming region. 41 by a thermal oxidation process. The thickness of the gate oxide insulating layer 23 is approximately 400 Å (40 nm) to 500 Å (50 nm). In Fig. 6b, first, the first polycrystalline silicon layer (PA) 24, having a thickness of about 3000 Å (300 nm) to 5000 Å (500 nm), is formed on the above substrate by a normal chemical vapor deposition (CVD) process. Next, an n-type impurity substance is introduced into the polycrystalline silicon layer 24 by, for example, an ion implantation process, to give the polycrystalline silicon layer 24 an n⁺-type conductivity. In Fig. 6c, the layer 25 of silicon oxide or silicon nitride, which has a thickness of about 2000 Å (200 nm) and may be a part of the first insulating layer, is formed on the polycrystalline silicon layer 24 by, for example, the CVD process. In Fig. 6d, first, by applying a normal patterning such as photo-lithography process the first insulating layers 25-1 to 25-4 of silicon oxide are respectively etched so as to form the conductive layers 24-1 to 24-4 as suitable for word lines. Next, the polycrystalline silicon layer 24 is etched, using the patterned silicon oxide layers 25-1 to 25-4 as the mask, to form the word lines 24-1 to 24-4. Third, the gate insulating layer 23 is etched by using as the mask, for example, the insulating layers 25-1 to 25-3 and the word lines 24-1 and 24-2, to expose regions 42-1 and 42-2, which may be a source forming region and a drain forming region, on the p⁻-type silicon semiconductor substrate 21. Simultaneously, the field insulating layer 22 between the word lines 24-3 and 24-4 thereon is also etched to a thickness equal to the thickness of the gate insulating layer 23. In Fig. 6e, a silicon oxide layer 26 as a second insulating layer having a thickness of about 4000-6000 Å (400-600 nm) is formed on the whole surface by the CVD process. In Fig. 6f, the resist process used in normal photo-lithography is applied and a photo resist protection layer 27 is formed above the word lines, for example, the word lines 24-3 and 24-4, on which further stacked capacitors can be formed. In Fig. 6g, a dry-etching process having an anisotropic etching effect in the vertical direction with respect to the substrate plane, such as a reactive ion etching (RIE) process, is applied and the whole surface is etched to reexpose the regions 42-1 and 42-2 which can be used as the source forming region and the drain forming region in the p⁻-type silicon semiconductor substrate 21, and a region 43 between the word lines 24-3 and 24-4. As a result, the word lines 24-1 and 24-2 are covered by the silicon oxide layers 25-1 and 25-2 as the first insulating layers and the silicon oxide layers 26-1A (not shown) and 26-1B, and 26-2A and 26-2B, at the sides thereof, respectively. The word lines 24-3 and 24-4, on which the stacked capacitors may be further formed, are directly covered by the silicon oxide layers 25-3 and 25-4, and are also covered by the silicon oxide layers 26-3 and 26-4, together with the silicon oxide layers 25-3 and 25-4, respectively. In Fig. 6h, by applying a selective ion-injection of the n-type impurity of the ion implantation process to the regions 42-1 and 42-2, an n⁺-type impurity diffusion region 27, which may become a source and another n⁺-type impurity diffusion region 28, which may become a drain, or vice-versa, are formed in the p⁻-type silicon semiconductor substrate 21. In Fig. 6i, first, the second conductive layer 29 of polycrystalline silicon (PB) having a thickness of about 1000 Å (100 nm) to 3000 Å (300 nm) is formed on the substrate shown in Fig. 6h by the CVD process. Next, the conductive layer 29 is ion-injected with the n-type impurity to make it conductive. Note that a portion which may act as an island-form conductive layer (region) 29-1 is formed simultaneously wish the conductive layers 29-2 and 29-3 by the above processes. Then, by applying normal photo-lithographic technology, the polycrystalline silicon layer (PB) 29 is patterned to form the electrodes 29-2 and 29-3 for the capacitors C₂ and C₃ shown in Fig. 5, which, on the one hand, are in direct contact with the diffusion region 28 and, on the other hand, extend over the adjacent word lines 24-2 and 24-3 via the first insulating layers 25-2 and 25-3 and the second insulating layers 26-2B, 26-3 and 26-4, to form the island-form conductive layer 29-1, which, on the one hand, is in direct contact with the diffusion region 27 and, on the other hand, faces the adjacent word lines 24-1 and 24-2 through the first insulating layers 25-1 and 25-2 and second insulating layers 26-1B and 26-2A enclosing the word lines 24-1 and 24-2. Note that the island-form conductive layer 29-1 extends over the adjacent word lines 24-1 and 24-2. This facilitates self-alignment for forming the contact window 34 at the following process after the layer insulation film 33 and the third insulating layer 30 are formed. In addition, by applying the CVD process, the third insulating layer 30 of silicon oxide having a thickness of about 200 Å (20 nm) is formed on the capacitor electrodes 29-2 and 29-3, the second insulating layers 26-3 and 26-4, the first insulating layers 25-1 and 25-2, and the island-form conductive layer 29-1. Portions of the insulating layer 30 on the capacitor electrodes 29-2 and 29-3 function as a dielectric film for the memory capacitors and the other portions function as a layer insulation. In Fig. 6j, first, the polycrystalline silicon layer (PC) having a thickness of approximately 1000 Å (100 nm) to 3000 Å (300 nm) is formed on the substrate shown in Fig. 6i by the CVD process. Next, the ion-implantation process is effected to make the polycrystalline silicon layer (PC) conductive, thus forming the third conductive layer 31. After that, to remove the portion of the third conductive layer 31 above the island-form conductive layer 29-1, and form an electrode 31 opposing the electrodes 29-2 and 29-3 through the third insulating layer 30, the polycrystalline silicon layer (PC) is selectively patterned by a normal photo-lithography process. In Fig. 6k, the layer insulation film 32 of, for example, phosphosilicate glass having a thickness of approximately 8000 Å (0.8 µm) to 10000 Å (1 µm), is formed on the remaining portion of the third conductive layer 31 acting as the electrodes opposing the electrodes 29-2 and 29-3, by the CVD process. Next, the contact window 34, passing through the layer insulation film 32 and the remaining third insulating layers 30-1 and 30-2 to the island-form conductive region 29-1, is formed by a normal etching process, such as photo-lithography. As a result, part of the island-form conductive region 29-1 is exposed. A thermal treatment process, i.e., glass flow process, is effected to smooth the surface of the layer insulation film 32. In Fig. 6ℓ, in accordance with the deposition process, the sputtering process, or the like, a layer of wiring material, for example, aluminum, is formed on the substrate. This is patterned in a normal manner to form the bit line 33 resistively connected (in ohmic-contact) to the diffusion region 27, at the contact window 34, by way of the island-form conductive region 29-1. Returning to Fig. 6j, the formation of portions adjacent to the island-form layer 29-2 will now be described in detail with reference to Figs. 7a to 7c. Figure 7a to 7c are enlarged sectional views of the island-form conductive layer 29 and regions adjacent thereto. In Fig. 7a, masks 50-1 and 50-2 are placed on the third conductive layer 31 except above the island-form conductive region 29-1 and adjacent portions, for example, A₁ and A₂ in Fig. 4. After that, etching is effected, whereby the third conductive layer 31, having a thickness of approximately 2000 Å (200 nm), above the island-form conductive region 29-1 is removed, as shown in Fig. 7b, exposing the surface of the second insulating layer 30 on the island-form conductive region 29. Approximately 2000 Å (200 nm) of the portions of the third conductive layer 31 at the adjacent portions A₁ and A2 is also removed simultaneously. Note, the thickness TH of the third conductive layer 31 at the adjacent portions A₁ and A₂ is larger than that above the island-form conductive region 29-1, because the former conductive layer is formed along the outer and vertical wall of the second insulating layer 25. Accordingly, it has a considerably large thickness of, for example, approximately 6000 Å to 7000 Å (600 nm to 700 nm). Therefore, the etching process must be continued until the third conductive layer 31 at the adjacent portions is fully removed. The removal of the third conductive layer 31 is unavoidably accompanied by erosion of the third insulating layer 30 on the first insulating layers 25-1 and 25-2 and the island-form conductive region 29-1. However, the speed of removal of the third insulating layer 36 is much lower than that of the third conductive layer 31. Therefore, while the thickness of the third insulating layer is reduced as shown in Fig. 7c, in the etching process of the third conductive layer 31, a small thickness of the third thin insulating layer 30' on the island-form conductive region 29-1 remains. Thus, the island-form insulating region 29-1 and corners B₁ and B₂ of the second insulating layers 26-1B and 26-2A are not completely removed. Upon completion of the above processes, the masks 50-1 and 50-2 are removed. Figure 8 is an enlarged sectional view of the semiconductor device after completion of the process shown in Fig. 6ℓ. A center portion of the third thin insulating layer 30' is removed together with a top of the island-form layer 29-1 during the etching process described in Fig. 6k. Note, first, that there is essentially no possibility of connection between the bit line 33 and the word lines 24-1 and 24-2, and next, the distance D₂ between the adjoining word lines 24-1 and 24-2 can be reduced without detrimental effect on the connection between the bit line 34 and the diffusion region 42-1 due to the island-form conductive region 29-1 extending over the first insulating layers 25-1 and 25-2 and the second insulating layers 26-1B and 26-2A over the word lines 24-1 and 24-2 and having the width W₀. In other words, even if the distance between the adjoining first insulating layers 25-1 and 25-2 is D₁ somewhat shorter than the length of the diffusion region 27, the width W₀ in which the contact window 34 may be made is substantially equal to the distance defining the adjoining word lines in the prior art. This allows high integration of the semiconductor device without the need for other processes. In addition, the depth d of the bit line 33 at the contact window 34 is reduced due to the existence of the island-form conductive region 29-1. This decreases the possibility of disconnection of the bit line around the steps of the contact window edge. Finally, the insulating layer for protection of the surface of the semiconductor device, of phosphosilicate glass or the like, is formed and a finishing process effected to produce the semiconductor device including stacked-capacitor type memory cells as shown in Fig. 5. In a semiconductor memory device including a plurality of stacked-capacitor type memory cells, wiring contact portions of sources and drains of transistors in peripheral circuits including sense amplifiers each consisting of transistors can be formed in the same construction as the above-mentioned memory cell portion. In this case, however, as the above island-form conductive layer overlaps the gate electrode, the capacitance of the gate of the transistors in the sense amplifier may increase and so the characteristic of the transistor would change. To avoid this, the wiring contact portions in question are formed in a normal construction. The processes for manufacturing the peripheral circuits, particularly the transistor portion, will be explained with reference to Figs. 9a to 9f. In Fig. 9a, the field oxide layer 22 is formed on the p⁻-type silicon substrate 21, and a transistor-forming region 51 is exposed simultaneously. The gate oxide insulating layer 23 is also formed simultaneously. The process corresponds to that of Fig. 6a. In Fig. 9b, a first polycrystalline silicon layer (PA) 52 is formed above the substrate. Then, the first polycrystalline silicon layer 52 is rendered electrically conductive by n-type impurity implantation. Part of the first insulating layer 25 is formed on the polycrystalline silicon layer 52. Next, patterning is applied to form the gate electrode, also referenced as 52, on which the first insulating layer 25 is formed. The process corresponds to that of Fig. 6d. In Fig. 9c, the second insulating layer 26 is formed on the portions of the substrate 21 and the field oxide layer 22 from which it was removed during the above patterning process. This process corresponds to that of Fig. 6e. Subsequent to this, but before the process shown in Fig. 9d, various processes are effected. The first insulating layer 25 arranged in the memory cell forming region is etched and ion-implantation performed, as in Fig. 6g. The peripheral regions are protected and remain as is (as shown in Fig. 9c). Next, in the same process as shown in Fig. 6i, the second polycrystalline silicon layer (PB) 29 is deposited on the peripheral regions. However, the portion of the polycrystalline silicon layer deposited on the peripheral regions is fully removed during the patterning process. As a result, the peripheral regions are again made as shown in Fig. 9 c. Furthermore, during the same process as shown in Fig. 6j, the third conductive layer of polycrystalline silicon (PC) 31 is deposited on the peripheral regions. Again, however, the deposited polycrystalline silicon layer is completely removed during the subsequent patterning process. At this stage, the upper layer of the insulating layer 26 on the conductive layer 52 is also eroded, as mentioned above with reference to Figs. 6j and 7a to 7c. In Fig. 9d, prior to performing the process shown in Fig. 6k, the memory cell region is covered with a protective mask. Subsequently, the portions of the second insulating layer 26 on the peripheral regions are entirely removed by the reactive ion-etching process, thus exposing transistor source- and drain-forming regions 53 and 54. The portion of the insulating layer 26 enclosing the gate electrode 52 remains. Furthermore, an n⁺-type impurity is ion-implanted into the source- and drain-forming regions 55 and 56, thereby forming n⁺-type source and drain regions 55 and 56. In Fig. 9e, during the process shown in Fig. 6k, the layer insulation film 32 of phosphosilicate glass is formed above the peripheral regions. Subsequently, contact windows 57 are formed in the source and drain regions 55 and 56. In Fig. 9f, during the process shown in Fig. 6ℓ, a wiring layer 58 is formed on the layer insulation film 32 and the apertured portions of the source and drain regions 55 and 56. Next, the wiring layer 58 is separated above the conductive layer 52 to form wiring layers 58-1 and 58-2. After that, the memory cell regions, surface protecting insulating film, etc., are formed. In the above embodiments, the first conductive layer, used for the word line or the gate electrode, and the second and third conductive layers, used for the capacitor electrodes, are made of polycrystalline silicon. These layers, particularly the first conductive layer, also may be made of a high melting point metal , which can provide a low sheet resistance, or the like. The first and second insulating layers can be formed of thermal oxide films. Note that a p⁻-type semiconductor substrate is used in the above-mentioned embodiments. However, obviously, an N⁻-type substrate can be used instead. In the above embodiments, metal oxide semiconductor (MOS) devices were described, however, the present invention may be applied to MIS devices.

Claims: A semiconductor memory device comprising: a substrate (21); a plurality of word lines; a plurality of bit lines (33); and a plurality of memory cells, each positioned at an intersection defined by one of said word lines and one of said bit lines and including a capacitor (C2) for storing data and a transistor (Q2) cooperably connected to said capacitor for transferring data to said capacitor; said word lines being formed by a first conductive layer (24-1 to 24-4); said transistor in each said memory cell including a gate connected to or formed by one of said word lines (24-2), a gate insulating layer (23-2), and source and drain regions (27 and 28); each of said memory cells having a first insulating layer (25-2) covering said gate of said transistor, and a first insulating layer (25-3) covering another word line (24-3) adjacent to said one word line (24-2); said capacitor in each said memory cell including: a second conductive layer (29-2) which is in contact with one of said source and drain regions of said transistor in the memory cell, which extends onto the gate of said transistor over said first insulating layer, and which covers said second insulating layer; a third insulating layer (30-2)formed on said second conductive layer; and a third conductive layer (31) extending over said third insulating layer; one of said bit lines being connected to the other of said source and drain regions of said transistor in each of said memory cells, characterized in that each of said memory cells has a second insulating layer (26-3) covering said another word line (24-3) adjacent to said one word line (24-2), the second insulating layer having a larger thickness than that of said first insulating layer (25-2) covering said gate. A semiconductor memory device according to claim 1, wherein said second insulating layer (26-2A, 26-2B) is also provided on both sides of said gate, and wherein said first insulating layer (25-3) is also provided on said adjacent word line (24-3), and said second insulating layer (26-3) is provided on said first insulating layer over said adjacent word line, so as to electrically isolate said word lines from said bit lines and said second conductive layer. A semiconductor memory device according to claim 1, wherein said first insulating layer is made of silicon oxide or silicon nitride and has a thickness of approximately 200 nm (2000 Å) , and wherein said second insulating layer is made of silicon oxide or silicon nitride and has a thickness of approximately 400 nm (4000 Å). A semiconductor memory device according to claim 1,2, or 3, wherein said device further comprises an additional conductive layer (29-1) directly connected to the other of said source and drain regions of said transistor in the memory cell and extending onto the gate of the transistor over said first insulating layer covering said gate, each said bit line being connected to the other of said source and drain regions through said additional conductive layer. A semiconductor memory device according to claim 4, wherein said additional conductive layer, formed on the other of said source and drain regions of said transistor and extending onto said gate of the adjoining transistor over said first insulating layer means covering said gate, has a predetermined thickness at the region extending onto the gate and a predetermined width to facilitate formation of a contact window for electrically connecting said bit line with the other of said source and drain regions through said additional conductive layer. A semiconductor memory device according to claim 4 or 5, wherein the thickness of the additional conductive layer is approximately equal to that of the second conductive layer. A semiconductor memory device according to claim 4,5 or 6, wherein the additional conductive layer in each said memory cell also extends over one of the adjacent word lines other than its own gate. A semiconductor memory device according to any preceding claim, wherein said semiconductor memory device further includes a peripheral circuit including transistors, each having source and drain regions and a gate electrode which is entirely covered by said second insulating layer, said source and drain regions being directly connected to wiring lines. A method for manufacturing a semiconductor memory device according to any preceding claim, including the steps of: forming the first conductive layer (24) on an insulating layer (23) on the substrate (21) and the first insulating layer (25) on said first conductive layer; patterning said first insulating layer (25) to define the word lines of the semiconductor memory device; patterning said first conductive layer (24) with masking by said patterned first insulating layer (25) to form the word lines (24-1 to 24-4); forming the second insulating layer (26) having a larger thickness than that of said first insulating layer (25) on the whole substrate; and etching said second insulating layer whilst protecting the portions of said second insulating layer on the word lines (24-1 to 24-4) the etching thus exposing drain and source forming regions (27,28) of said transistor in said substrate so that a thickness of insulating layer including unetched first and second insulating layers on said plurality of word lines on which said capacitor is to be formed thereon is greater than that of other insulating layers remaining after said etching on other word lines. A method for manufacturing according to claim 9, further including the steps of, forming said transistor having source and drain regions (27, 28) formed in said substrate and a gate electrode (24-2) of said first conductive layer on said substrate; forming the second conductive layer (29) extending over said second insulating layers on said word lines, said second conductive layer being in direct contact with one of said source and drain regions of said transistor and being electrically isolated from said gate electrodes and said word lines through said first and second insulating layers; removing a portion of said second conductive layer above said gate electrode, the remaining portion of said conductive layer extending over said gate electrode, to separate said second conductive layer into a capacitor electrode and an interface conductive layer having an island-form on said one of source and drain regions; forming the third insulating layer (30) of a dielectric material on at least said capacitor electrode; forming the third conductive layer (31) as another capacitor electrode on at least said third insulating layer; forming a contact window on said interface conductive layer with self-alignment; and forming said bit line connected to said interface conductive layer at said contact window. A method for manufacturing according to claim 9 or 10, further including a step of forming peripheral circuits for said plurality of memory cells, including a plurality of sense amplifiers each having at least one another transistor, said peripheral circuits forming step including the steps of, forming a conductive layer (52) corresponding to said first conductive layer (24) on said insulating layer (23), simultaneously to forming said first conductive layer, and an insulating layer corresponding to said first insulating layer (25), on said conductive layer, simultaneously to the forming of said first insulating layer; patterning said conductive layer to define a plurality of wiring lines for connecting gates of said another transistors, simultaneously to patterning of said first conductive layer; forming another insulating layer corresponding to said second layer (26) on the whole of said peripheral circuits forming region, simultaneously to forming second insulating layer; etching said another insulating layer to expose drain and source forming regions of said another transistors; forming said another transistor having source and drain regions (55, 56) and a gate electrode of said conductive layer (52); and forming other conductive layers (58-1, 58-2) in direct contact with said source and drain regions of said another transistor.

Inventors: EMA, TAIJI, YABU, TAKASHI
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21