Data transmission and detection system

Abstract: A data transmission system and apparatus used for recording on a recording medium an audio, signal, compressed in time base with a predetermined compression ratio, together with a data signal for reproduction of the audio signal. The data signal is composed of serial data of bits. A dummy bit is provided before the head bit of the serial data with the dummy bit being in inverted relation to the head bit. A detection system and apparatus for detection of the data transmitted by the data transmission system, and a recording medium on which signals are recorded according to the data transmission system are disclosed.

Description: The present invention relates to data transmission and detection systems and more particularly to a system which transmits serial bit data and a system which detects the serial bit data. Related Background Art In recently proposed video floppy systems, it is proposed to record a video signal as well as an audio signal on a magnetic sheet as the recording medium. Fig. 1 diagramatically shows both the video and audio signals present together on a magnetic sheet. For example, according to the standards on video floppies, field video signals (V) and audio signals (A1, A2) all can be recorded on a magnetic sheet for up to 50 concentric tracks in all. The audio signal is raised by time base compression into the video band and recorded in a frequency modulated form. The recording time per track is approximately 10 seconds, assuming that the audio band is 5 KHz and the time base compression ratio is 640. Also, assuming that the video band is 2.5 MHz and the time base compression ratio is 1,280, recording for approximately 20 seconds is possible. In this case, the audio signal may be completed in a single track or extended into the next track. The ring-like audio track is divided into four sectors, as shown in Fig. 2. For example, in the mode where recording for 10 seconds is possible, an amount of information for 2.5 seconds is allotted to each sector. Fig. 3 illustrates the form of an audio signal and additional signals to be recorded on a single sector. In Fig. 3, after an elapse of t 1 from time T 0 , a start ID signal having a level L H higher than a reference level L 0 continues for time t 2 for obtaining the timing to read the audio signal information. After a blank of t 3 , the audio signal starts. During the first interval of time t 4 the signal on a sector overlaps with that on the just preceding sector. This does not occur in the first sector corresponding to the leading portion of the audio signal. A new audio signal is for the remaining time t 5 , the length of which is variable; 2.5 seconds at a maximum in the mode of 10 seconds per track, as mentioned above. After a subsequent blank of t 6 , an end ID signal having a level of L L lower than reference level L 0 continues for t 7 in order to detect the end of the audio signal and to obtain the timing of reading data signal related to the subsequent audio signal. After a blank of t 8 , the data interval continues for t 9 . Then a blanking interval of time t 10 appears, the length of which is varied according to the interval of the preceding audio signal t 5 , and thus one sector cycle ends. This form is basically the same in any of the sectors where the audio signal is present. The interval of the audio signal shown by t 5 is variable and selected so that the interval t 5 + t 10 is constant at all times. Thus the length of the audio signal determines the position of the end ID and data signals. The data signal includes, in the form of digital data, the number, on the magnetic sheet, of a track on which the audio signal is recorded, the number of the leading and subsequent tracks through which audio signals are recorded continuously, the number of the tracks through which the video signal corresponding to the audio signal is recorded, the compression ratio of the audio signal, etc. In this case, it is arranged that "1" and "0" represent levels L 0 and L L , respectively. When subjected to frequency modulation, the voltage levels L 0 , L H , and L L correspond to f 0 , f H and f L modulation frequencies, respectively, where f L < f 0 < f H ; for example, f 0 = 6 MHz, f H = 7MHz, f L = 5 MHz. The above data signal will now be described in more detail. Fig. 4 illustrates on enlarged scale the data signal shown in Fig. 3. In Fig. 4, reference numeral 51 denotes synchronism bits of 1 byte length. Reference numerals 52-59 denote data signals each of 1 byte length; all of the data signals include 8 bytes in all. Of the 8-byte data for the signals 52 - 59, for example, 6 bytes for the signals 52-59 are used as the net data bits (i.e. information data) and 2 bytes for the remaining signals 58 and 59 are used as the cyclic redundancy check code (CRCC) for error detection. Here, 8 bytes for the signals 52 - 59, inclusive of CRCC, will be described hereinafter as the data. Thus the data signal of Fig. 4 is composed of the 1-byte synchronism bits and the 8-byte data bits. The type of the codes used is an NRZ code where low and high levels are represented by "0" and "1", respectively. The total number of bits used is 72. As described above, the 6-byte net data includes the track number of the audio signal tracks, the time compression ratio of the audio signal, the track number of the corresponding video, the track number of the leading and trailing tracks through which the audio signal continues, etc. Fig. 5 shows one example of a circuit to produce the data signal of Fig. 4. In Fig. 5, a signal generator 60 generates start and end ED signals and a clock signal to read a 9-byte data shift register 63. An adder 61 adds a start ID signal, an end ID signal from signal generator 60 to a data signal from shift register 63. A selector 62 selects which of the bytes of shift register 63 should be connected to the output of a controller 12 including a microcomputer. Reference numeral 63 denotes a 9-byte (= 72-bit) data shift register. The operation of the Fig. 5 circuit concerning data generation will now be described. First, controller 12 controls selector 62 so that the one-byte synchronism signal and predetermined data are written into a byte area 0 (least significant byte area) and more significant byte areas 1 - 8, respectively, of shift register 63 in bytes in parallel form sequentially from byte area 0 to byte area 8 (most significant byte area). In this case, the synchronism signal of 1 byte written into the least significant byte area 0 are represented, for example, by "01010101". As described above, the net data is written into byte areas 1 - 6 and the CRCC into byte areas 7 and 8. When this writing has been completed, controller 12, for example, enables signal generator 60 to generate a read clock signal (a) at a predetermined timing synchronous with rotation of the magnetic sheet (the timing is, for example, determined on the basis of PG signals, etc., derived by detection of rotating phase indicia attached to part of the magnetic sheet). The clock signal (a) causes the contents of shift register 63 to be read in bit serial form sequentially from byte 0 to byte 8 and a signal train having the form of Fig. 4 is obtained at the output (b) of the register 63. This output (b) of the register is added by adder 61 to the start and end ID signals (c) from signal generator 60. The output (d) of adder 61 is then synthesized with a compressed audio signal into a signal having the format shown in Fig. 3. The adder output is then subjected to precessing including emphasis, frequency modulation, etc., and recorded on the magnetic sheet via a magnetic head. In this case, if the recording speed is 1 TV field/track, the magnetic sheet will be rotated at 3,600 rpm under the NTSC system and concentric recording tracks will be formed. The leading bit output of shift register 63 is connected to the trailing end bit input thereof, which is not shown here. Thus in order to record data for one sector, data is circulated and written into the shift register 63 even after the data has been read out once, and when the second and subsequent sectors are to be recorded, the data will be read and recorded again and again. Reproduction of the signal recorded in the above mentioned manner will now be described. Here, especially, reproduction of the data will be described and reproduction of the compressed audio signal, etc., will be omitted. Fig. 6 illustrates an example of a circuit to reproduce the data. In Fig. 6, reference numeral 10 denotes a magnetic sheet. A sheet rotating motor 11 is controlled so as to rotate at 3,600 rpm in accordance with the NTSC system in view of a recording speed of 1 TV field/track. A PC detector 13 detects the rotating indicia on the sheet 10 and produces a PG signal. The circuit of Fig. 6 further includes a magnetic head 14, a reproduction preamplifier 22, a frequency demodulator 26, a deemphasis circuit 27, a voice reproduce circuit 28, an ID separator 29 which separates the start and end ID signals, a data gate pulse generator 30, a data gate 31, a data synchronism detector 32, a signal generator 33, a 8-byte data store shift register 64, and a selector 65. Shift register 64 may also be used as shift register 63 of Fig. 5. In the above structure, the FM signal picked up by magnetic head 14 out of magnetic sheet 10 is amplified by preamplifier 22 to a predetermined level and then delivered to frequency demodulator 26. The signal demodulated by demodulator 26 is deemphasized by deemphasis circuit 27 into a signal having the format shown in Fig. 3. This signal is delivered to voice reproduce circuit 28 where the audio portion of the signal is subjected to predetermined processing and then expanded into the original signal. Thus the original audio signal is reproduced. The reproduced signal from deemphasis circuit 27 is also delivered to ID separator 29 and data gate 31. The ID separator 29 is basically a low-pass filter, the cut-off frequency of which is set so that the ID signal can pass through the filter and that no audio and data signals can pass. The start and end ID signals (e) separated by ID separator 29 are delivered to data gate pulse generator circuit 30 which separates only the end ID signals on the basis of the PG signal output from PG detector 13 which detects the rotating indicia on the magnetic sheet 10. The data gate pulse generator 30 produces a data gate pulse (f) to extract only the data portion on the basis of one of the four end ID signals for the four sectors designated by controller 12. The data gate pulse (f) is delivered to data gate 31, which separates only the data signal (g), inclusive of the synchronism portion, from the reproduced signal having substantially the format of Fig. 3. The separated data signal (g) is then delivered to shift register 64 and data synchronism detector 32. Synchronism detector 32 detects the synchronism bits at the head of the incoming data signal such as is shown in Fig. 4 and is composed of a shift register, a counter, a logic gate, etc. This will be described in more detail hereinafter. The clock signal (h) which is input by signal generator 33 is, for example, 3 f sc , assuming that the bit rate is f sc /2 bits/sec (PBS), where f sc = 3.57945 MHz which is the color subcarrier frequency in the NTSC system. The counter which divides the clock signal (h) by a factor, for example, of 6 is reset by the first rise of the synchronism bits. Each of the pulses of the 6-divided clock signal is adjusted to coincide with the central position of a respective one of the synchronism bits and the thus obtained clock pulses are applied as the write clock pulses to the 8-bit shift register to write the synchronism bits thereinto. The 8 outputs of the shift register are coupled to the logic gate which outputs, for example, "1" when the register output takes the pattern "01010101". Thus when the synchronism detector 32 detects the synchronism bits of data, it outputs a detection pulse (i) which is applied to signal generator 33. This resets another divide by 6 frequency circuit in the signal generator 33 which counts down the 3 f sc . Thus signal generator 33 produces write clock signal (j), reset in timing, the pulses of which are applied sequentially to shift register 64. In response to these pulses the shift register writes thereon in a bit serial manner the bit data, for example, of 8 bytes of the data signal 52 - 59 of Fig. 4 excluding the synchronism bits of the data signal. When signal generator 33 has generated write clock pulses for 8 bytes, it delivers a write end pulse (k) to controller 12. In response to the write end pulse the controller 12 starts to read the data from shift register 64. That is, controller 12 controls selector 65 such that same selects a respective one of the bytes of shift register 64 sequentially from the least significant byte (byte 0) to the most significant byte (7) and reads the corresponding data in a bit parallel manner. When this reading has been completed, controller 12 again controls data gate pulse generator 30 so that same produces a data gate pulse (f) corresponding to the end ID signal in another sector. This causes reading operation similar to the above to be repeated. This reading operation will end when it is repeated for four sectors, i.e. four times. While the data transmission (recording) and detection (reproduction) system which forms the background techniques of the present invention has just been described, this system has the following problems. Now assume that the bit rate for data recording is f sc /2 BPS, i.e., 1.7897725 MBPS and that the rotating speed of the magnetic sheet is ideally 3,600 rpm both in recording and in reproduction. Then the read clock frequency for reproduction may be 1.7897725 MHz. However, the rotation of the magnetic sheet may contain jitter due to non-uniform motor rotation. The centre of the concentric recording tracks may be deviated from the center of rotation of the sheet due to changes in the accuracy of the sheet being placed on the motor spindle, for example, in recording and reproduction. In such a case, the resulting reproduced signal would contain jitter. According to the inventors' experiment, the quantity of this jitter was no less than ± 2 % at its worst and the data had been recorded at a bit rate of 1.7897725 MBPS was reproduced at a bit rate fluctuating between 1.754 and 1.826 MBPS. In this case, the fluctuating period is 16.7 m sec corresponding to the magnetic sheet rotation speed at 3,600 rpm (60 Hz). On the other hand, the interval of each data bit is about 36 µ sec (for 8 bytes, the bit rate is as short as 1.7897725 MBPS). Thus if data is written when the bit rate has fluctuated to 1.754 MBPS, the write clock frequency at that time should be essentially 1.754 MHz. In this case, however, data signal is only present discretely at 90-degree intervals with a width of about 36 µ sec on a single track, the period of which is 16.7 m sec. The type of codes used is an NRZ which itself has no clock pulse components. Therefore, it is difficult to cause the write clock signal to follow the frequency at 1.754 MHz using means such as a PLL and thus there is no method other than detection of the data, i.e., or writing of same into the shift register, using a fixed-frequency clock signal of 1.7897725 MHz which is the same as that used in recording. Fig. 7 illustrates an example where the data having a bit rate of 1.754 MBPS is detected or written into the shift register using a write clock frequency of 1.7897725 MHz. As shown in Fig. 7, if the write clock frequency and the data bit rate are deviated 2 % from each other, a read error will occur midway in the byte 3 (at the fourth byte) indicated by X in Fig. 7. As described above, in the data recording and reproduction system described with respect to Figs. 4 - 6, although the write clock is reset and synchronized by the first synchronism bit, the difference between the data rate and the write clock frequency due to jitter causes the relative phase of the write clock signal to shift from the data bit to be detected primarily to the adjacent bit midway in the data train (for example, at the portion shown by X in Fig. 7). Thus an error in reading results. Asynchronous methods have been employed to eliminate, or at least reduce, such filter error. It is known to use combinations of two bits, a "stop" bit at the tail end of each segment of data and a "start" bit at the head end of each consecutive segment of data to provide means for synchronisation - so-called "start-stop" synchronism. Examples of such methods are described, for example, in French Patent Application No FR-A-2275946 and in "The Electronic Engineer", vol 31 no 2, February 1972 pages DC5 to DC7, a paper entitled "Asynchronous transmission: some basic bits of data" by S. Stuart et al. Fig. 8 shows one such example in which the synchronism bits are included because they are needed to distinguish between the data and a possible dropout of the record signal during reproduction and to indicate that data will begin next. Each unit data portion is composed of a frame including one start bit, 8 serial data bits and one stop bit arranged in this order (10 bits in all). Since such form of data train causes the start bit to reset the write clock, the error in reading due to jitter is reduced. That is, as shown in Fig. 8, each time an 8-bit data is read, the write clock is reset and synchronized by the next start bit so that each of the write clock pulses is substantially stably settled at substantially the centre of a respective one of the data bits. While this method alleviates the influence of jitter, it increases redundancy; for example, 10 bytes (80 bits) are needed to record 8-byte data (64 bits). That is, 16 excess code bits are added and bit utilization measure is reduced. While the above has been described on the problems with the case in which the data signal is recorded and reproduced, together with the audio signal, on and from the magnetic sheet as an example, similar problems will occur with a data signal including especially discrete data signal blocks even in recording and reproduction on and from other recording mediums such as magnetic tape, or in general data transmission and reception. It is also known to use single dummy bits for data synchronisation. In United States Patent Specification No US-A-3903504 a single bit data transition is used and is inserted between segments of biphase coded data. This single bit comprises complimentary sequential pulses defining a transition edge. These pulses are of different width to those employed for coding data and are therefore readily distinguishable as constituting dummy bits. The transition edge may be either negative- or positive-going to distinguish message and data words respectively, irrespective of bit values. In United States Patent Specification No US-A-3815108, also European Patent Application No EP-A-0174807 and Japanese Patent Specification No JP-A-545313 reported in Patent Abstracts of Japan vol 3, no 26 (E-95) 6 March 1979 page 85, a single dummy bit is inserted between segments of NRZ coded data. Each single dummy bit is inserted to follow the tail end bit of a respective one of the segments, and is in inverted relationship to the respective tail end bit regardless of its value. An object of the present invention is to provide a data transmission and a detection system which are capable of detecting each of the bit data accurately although the data bit rate may fluctuate. Another object of the present invention is to provide, a data transmission system and a data detection system of low redundancy and high bit utilization measure. A first aspect of the present invention provides a method of detection for detecting serial bit data as set out in claim 1. A second aspect of the present invention provides an apparatus for detecting serial bit data as set out in claim 6. A third aspect of the present invention provides a recording medium as set out in claim 10. A fourth aspect of the present invention provides a method of recording as set out in claim 15. A fifth aspect of the present invention provides a recording apparatus as set out in claim 16. Other objects of the present invention will be apparent from the following description of an embodiment thereof. IN THE ACCOMPANYING DRAWINGS: Fig. 1 illustrates recording tracks on a magnetic sheet; Fig. 2 illustrates an audio track consisting of divided sectors; Fig. 3 illustrates the arrangement of an audio signal, an ID signal and a data signal contained in a single sector; Fig. 4 illustrates the details of the format of the data signal of Fig. 3; Fig. 5 is a block diagram of a circuit to generate the signal of Fig. 4; Fig. 6 is a block diagram of one example of a reproduction system to reproduce the data signal of Fig. 4; Fig. 7 illustrates an inconvenience occurring in the reproduction system of Fig. 6 in the case of the data signal of Fig. 4; Fig. 8 illustrates the details of another format of the data signal which can be employed to avoid the problem illustrated in Fig. 7; Fig. 9 illustrates one example of the format of the data signal used in preferred embodiment of the present invention applied to the recording and reproduction of the audio and data signals described in Figs. 1 to 4; Fig. 10 is a block diagram showing one embodiment of a reproduction system to reproduce the data signal shown in Fig. 9; Fig. 11 is a block diagram of a specific structure of the 2nd-byte last bit detector and signal generator of Fig. 10; and Fig. 12 is a timing chart showing the inputs and outputs of main blocks of Fig. 11. One embodiment of the present invention will be described in which the present invention is applied to recording and reproducing of the data signal as an additional signal for recording and reproducing of the audio signal described in Figs. 1 - 4. A preferred embodiment will be described with respect to Fig. 9. This embodiment is concerned with an m x n (m, n are a positive integer and n is equal to or higher than 2)-serial data transmission system which transmits the serial data with the last bit data of each nth byte of the serial data being in inverted relationship to the bit data directly before or after the said last bit data and with an error detecting data of not more than n bytes at the end of the data train. Fig. 9 shows the format of a data signal used in such embodiment. Here, the data train including 6 bytes 52 - 57 shown in Fig. 4 are divided into 3 groups, each including 2 data bytes. That is, m = 3 and n = 2. The last bit (bit 7) data of each of the second bytes 53, 55 and 57 of the respective groups is in inverted relationship to the bit data (bit 6) directly before the said last bit data; for example, when the bit 6 data is "1", the bit 7 data is "0" or otherwise when the bit 6 data is "0", the bit 7 data is "1" so that an inverting edge A is formed between these adjacent bits. Thus in this case, a maximum of 7 data bits can be accommodated in each of bytes 53, 55 and 57. Note that data does not continue to byte 59, i.e., the second byte of CRCC, so that a rule such as is mentioned above need not be applied to this byte 59. The inverting edge A is used to reset the data write clock to the shift register during data detection, i.e., to detect the bit data. Note that m = 2 and n = 3 may be used instead of m = 3 and n= 2. This combination is supported by the inventors' experimental results on the error in reading referred to in Fig. 7. The synchronism bits of byte 51 are used to distinguish a data interval from possible dropout pulses, etc., to recognise that the data train will begin next and to determine the timing of detecting each bit data of bytes 52 and 53. The data signal having the format shown in Fig. 9 can be produced by using the circuit of Fig. 5. That is, in the generation of the data signal of Fig. 4, as mentioned above, the data of bytes 53, 55 and 57 is required to be written from controller 12 to bytes 2, 4 and 6 of shift register 63 with the last bit data of each of the bytes being in inverted relationship to the bit data directly before the last bit data, as mentioned above. Other operations are similar to those described with respect to Fig. 5. One example of a circuit system to reproduce the signal formed as mentioned above and recorded on the magnetic sheet will now be described with respect to Fig. 10. In Fig. 10, the same reference numeral as in Fig. 6 denotes the same element as in Fig. 6. Also, in Fig. 10, the same reference numeral as in Fig. 6 and having a single or double prime denotes an element corresponding to that in Fig. 6. In order to handle the signal format of Fig. 9, the embodiment includes a 2nd-byte last or LSB bit detector 100' between data detector 32 and signal generator 33". This signal generator 33" will be reset by the ouptut from detector 100'. The illustrated embodiment of Fig. 10 is quite the same in operation as the system of Fig. 6 up to the separation of data signal (g) by data gate 31. The data signal (g) separated by data gate 31 is delivered to shift register 64, data synchronism detector 32 and 2nd-byte last-bit detector 100'. At this time, detector 32 is impressed with a clock signal (h) (for example, 3 f sc Hz if the data bit rate is f sc / 2 BPS generated by signal generator 33'). On the other hand, detector 100' and signal generator 33' are impressed with the data synchronism output (i) indicative of data synchronism detection (for example, a pulse output which becomes high instantaneously in response to the trailing edge of the last bit "1" of "01010101") for controlling purposes. The last-bit detector 100' detects an inverting edge (i.e., the leading edge of bit 7) between the last bit 7 of every second byte of the data signal (g) from data gate 31 and the bit 6 directly before the last bit 7 in response to the detection output (i) from data synchronism detector 32 and the data write clock signal (j') from signal generator 33". When the inverting edge has been detected, detector 100' produces a reset pulse (1') which is delivered to signal generator 33" to reset the divide by 6 counter which produces the write clock signal to shift register 64. Note that the divide by 6 counter of signal generator 33" is initially reset by the detection output (i) from data synchronism detector 32. Thus signal generator 33" generates a write clock pulse (j') synchronously with the trailing edge of the last one 7 of the synchronism bits and the leading edge of the last bit of every second byte of the data train subsequent to the last bit 7 trailing edge. The write clock pulse (j') causes data to be written correctly into shift register 64. When the writing of all the data for 8 bytes, inclusive of the CRCC, into shift register 64 has been completed, signal generator 33" outputs a data end signal (k), in the same way as is mentioned above. In response to this signal, controller 12 processes data via selector 65. However, in this case, arrangement is such that controller 12' ignores the last bit data 7 of each of bytes 2, 4 and 6 of shift register 64 and hence does not handle those last bits as data. Fig. 11 shows one embodiment of the 2nd-byte last-bit detector 100 and signal generator 33". In signal generator 33", oscillator 331 generates a reference clock signal of 3 f sc (Hz) which is divided by a divide by 6 counter 332 into a data write reference clock signal (Fig. 12 (I)). In order to set the point of detecting (writing) data at the central position of each data bit, the output of counter 332 is delivered to a timing adjusting delay circuit 338 which then delays the counter output by 1/2 bits (Fig.12 (J)). This delayed output is then delivered as a write clock signal to one input of an output control AND gate 339. A divide by 64 ring counter 340 outputs a high-level pulse when it counts 64 output or write clock pulses (j) (for 8 bits x bytes) from AND gate 339. The counter 340 output is delivered as a data end signal (k) to controller 12'-and also the reset input of a rise synchronism RS flip-flop 334. The detection output (i) of data synchronism detector 32 is applied to the set input of flip-flop 334, the Q output (Fig. 12 (K)) of which is delivered to the other input of AND gate 339. The output (Fig. 12 (L)) of AND gate 339 is delivered as a write clock signal (j) to shift register 64. The output (i) of data synchronism detector 32 which is a signal, for example as shown in Fig.12 (D), becoming high instantaneously in synchronism with the fall or trailing edge of the eighth bit (bit 7) of the 8-bit synchronism signal, is delivered along with the reset pulse (1') from 2nd-byte last-bit detector 100' via an OR gate 341, the output of which is shown in Fig. 12 (H), to the reset of counter 332 for resetting same. In the 2nd-byte last-bit detector 100', as shown in Fig. 11, the data signal (g) (Fig. 12 (A)) from data gate 31 is delivered simultaneously to rise and fall synchronism mono-multivibrators (hereinafter referred to as the "MONO-MULTI") 104 and 105, respectively, which then produce pulses synchronously with the rise and fall, respectively, of each bit of the incoming data signal (g) (Fig. 12(B) and (C)), each pulse being narrow enough compared with the 1-bit data duration. These pulses are delivererd via OR gate 106 to one input of AND gate 107. The write clock signal (j') (Fig. 12(L)) from signal generator 33" is delivered to divide by 16 ring counter 108 which outputs one pulse (Fig.12(E)) in response to the 15th pulse of the write clock signal (j') when the Q output (Fig. 12(F)) of rise synchronism RS flip-flop 109 is high, or in response to the 16th pulse of the write clock signal when the Q output is high. The counter 108 pulse output is delivered to the other input of AND gate 107. Flip-flop 109 is reset by the synchronism detection output (i) (Fig. 12(D)) from detector 32 as well as by the output from ring counter 108. The Q output (Fig. 12(F)) of flip-flop 109 is delivered as a frequency divisor switching control signal to counter 108. Counter 108 is reset by the detection output (i) from detector 32. Thus the output of AND gate 107 is a pulse (Fig.12(G)) synchronous with the leading edge of the last bit 7 of each second byte of the data train. The pulse is delivered as a reset pulse (1') to signal generator 33". In signal generator 33", the reset pulse (1') is input via OR gate 341 to the reset input of counter 332 to reset same. In this way, in signal generator 33", the write clock generating counter 332 is reset by the detection output (i) (Fig. 12(D)) from detector 32 and the rise edge of each reset pulse (1') (Fig. 12(G)) from 2nd-byte last-bit detector 100. Eventually, counter 332 is reset by the trailing edge of bit 7 of the synchronism bits and the leading edge of bit 7 of each second data byte, and the write clock signal (j') is synchronized with these edges. The counter 332 of signal generator 33" generates a pulse when reset and thereafter each time 6 clock pulses are input from oscillator 331 to the counter 332. Since the counter 332 output pulse is synchronous with the leading edge of each data bit and in order to obtain a write clock pulse (j') coincident with the central position of each data bit on the basis of that output pulse, the output of counter 332 is delayed, for example, 1/2 bits by delay circuit 338 using the 3 f sc clock signal from oscillator 331. Flip-flop 334 and counter 340 are provided to know the data interval of the 8-byte data signal, inclusive of CRCC, subsequent to the synchronism signal (Fig. 12(K)). In more detail, since the number of data bytes is 8, inclusive of CRCC, counter 340 is provided to know the end of the eighth byte. The output of counter 340 is delivered as the data end signal (k) to controller 12'. On the other hand, the counter 108 of 2nd-byte last-bit detector 100 is provided to know the last bit 7 of each second byte of the 8-byte data signal, subsequent to the 8-bit synchronism signal, inclusive of CRCC. Thus, here, the bit 6, and, as a result, the leading edge of the data bit 7, of each second data byte are arranged to be detected by a clock pulse signal (Fig.12(J)) which is obtained by imparting a 2-bit delay to the counter 332 output (Fig.12(I)) synchronous with the data bit edge, using delay circuit 338. As described with respect to Fig. 9 since data does not continue to the 8th byte of the 8-byte data, inclusive of byte 59, i.e., CRCC, it is unnecessary to define an inverting edge between bits 6 and 7 of byte 59. Thus if there is an inverting edge between bits 6 and 7 of byte 59, the last-bit detector 100 will output a reset pulse (1') in response to the inverting edge. However, if no inverting edge, it will output no reset pulse (1'). It will be obvious that this is not at all deleterious to the 8th byte if it is considered that data does not continue to the 8th byte. In the above embodiment, it is arranged that an inversion, as shown by A in Fig. 9, occurs necessarily between the last bit 7 of each second byte of a data train and the bit 6 directly before the last bit 7 and that counter 332 of signal generator 33" of Fig. 11 is reset using the inverting edge A. Alternatively, for example, as shown by B in Fig. 9 the last bit 7 of the second byte of each of a data train may be defined relative to the directly following bit, i.e., the directly following head bit 0 of the data byte such that an inversion occurs necessarily between the last bit 7 and the directly following head bit 0 and that counter 332 of signal generator 33" is reset using the inverting edge in a manner similar to that mentioned above. This may be realized solely, for example, by using the 2nd-byte last-bit detector 100' of Fig. 11 with flip-flop 109 being removed therefrom and with counter 108 operating in a divide by 16 mode at all times. Therefore, according to this modification, the structure of the detector 100' is further simplified (no flip-flop is needed) compared with the above embodiments. In addition, since the resetting of counter 332 is performed 1/2 bits (in the above embodiment, 1 and 1/2 bits) before the first data bit, i.e., bit 0, is detected, it is ensured that data is detected reliably throughout all the 2-byte bits from beginning to end. For the data train of Fig. 9, it has been described that 8-bit significant data is written in each of bytes 52, 54 and 56 and that 7-bit significant data has been written in each of bytes 53, 55 and 57 at each bit 7 location thereof. Where data is not written effectively in all of these data bits locations, for example, where 6-bit or 4-bit data is written, data may be put close to the left (to the side of bit 0) or to the right (to the side of bit 7). This would expedite data processing. Especially, if the former is applied in the previous embodiments, and if the latter is applied in the modification, the bit 7 of each second byte will be at high level at all times. That is, here, whether data is effectively written in all of the data bit locations or not, the last bit 7 of each second byte is in inverting relationship to the bit 6 directly before the bit 7 or to the bit 0 directly after the bit 7. In the above embodiments, inclusive of its modification, bit data can be detected at all times at substantially the center of the bit in spite of possible fluctuation of the data bit rate due to jitter, etc. A bit utilization measure is good for detection synchronism stipulation. In addition, since data can be handled in units of 1 byte = 8 bits, the present invention is applicable satisfactorily to a circuit using a conventional 8-bit microcomputer. Note that the data signal may be placed directly after the start ID signal instead of after the end ID signal. According to this method, data signal can be accessed very rapidly for reproduction of the recorded signal (for example, in a time base extension memory used during reproduction), audio can be rapidly reproduced satisfactorily using data signal. Especially, while, as mentioned above, the position of the end ID signal varies according to the length of the audio signal before the end ID signal, the position of the start ID signal is constant in the respective sectors. Therefore, the detection of the data signal is very easy. Alternatively, for example, if two memories each having a capacity for one sector are used, one for an even sector and the other for an odd sector, and the signals stored in the memories are read alternately in units of a sector and recorded on a magnetic sheet, no data signals are superimposed on the magnetic sheet and damaged and good recording can be performed in spite of a slight change in the timing of switching the memories. While the embodiment in which the present invention has been applied to recording and reproducing a data signal as the additional signal to the audio signal has been shown and described, it goes without saying that the present invention is not limited to such recording and reproduction alone, as pointed out above. Especially, the present invention is also effective in transmission and detection of a data signal including discrete data signal blocks. As described above in detail, improved data transmission and detection systems in which each data bit of the data signal can be detected correctly in spite of possible fluctuations in the data bit rate, data can be handled in units of a byte with low redundancy and hence high efficiency.

Claims: A method of detection for detecting serial bit data (52-59) including a plurality of information data (52-57) each of which has a predetermined number of bits for one sample and includes one or more dummy bits which produce an inverting edge (A) and the serial bit data (52-59) being preceded by a synchronisation pattern (51), the method comprising synchronising a clock signal (j') with the synchronisation pattern (51); detecting at predetermined positions the occurrence of an inverting edge (A); resynchronising the clock signal (j') with the one or more dummy bits and detecting data by ignoring the dummy bit thereby recovering the information data, characterised by the serial bit data further including error detecting data (58,59), and the method further comprising a step of detecting an inverting edge (A) between the dummy bit and a following head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or the inverting edge between an end bit of the information data (52-57) and a following dummy bit, which dummy bit is inverted relative to said head bit or said end bit regardless of the value of said head bit or said end bit, said one or more dummy bits each being provided together with information data (52-57) in units of n bytes, where n is a positive integer greater than or equal to two, at locations so as to divide the plurality of information data (52-57) of said serial bit data (52-59) into m groups of n bytes, where m is a positive integer, which dummy bit is used for generating said inverting edge (A) before said head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or after said end bit of the information data (52-57). A method of detection as claimed in claim 1 wherein said method includes a step of detecting serial bits of the serial bit data (52-59) following and based upon the detecting of said inverting edge (A). A method of detection as claimed in claim 2 wherein said step of detecting the inverting edge (A) includes resetting a generator (33") which generates a clock signal (j 1 ) to detect said inverting edge (A) thereby to read said serial bit data (52-59). A method of detection as claimed in claim 3 wherein said step of detecting serial bits of the serial bit data (52-59) includes reading the serial bit data (52-59) synchronously with said clock signal (j 1 ). A method of detection as claimed in claim 2 wherein said step of detecting serial bits of the serial bit data (52-59) includes detecting the serial bit data (52-59) at substantially the centre of each serial bit on the basis of said inverting edge (A). An apparatus for detecting serial bit data (52-59) including a plurality of information data (52-57) each of which has a predetermined number of bits for one sample to reproduce an audio signal compressed with a predetermined compression ratio the serial bit data (52-57) including one or more dummy bits which produce an inverting edge (A) and the serial bit data being preceded by a synchronisation pattern (51), the apparatus comprising: means (32,33") for synchronising a clock signal (j') with the synchronisation pattern (51); means for detecting at predetermined positions the occurrence of an inverting edge (A); means (100') for resynchronising the clock signal (j') with the one or more dummy bits and means (12',65) for detecting data by ignoring the dummy bit thereby recovering the information data (52-57), characterised by the serial bit data (52-59) including error detecting data (58,59) and the apparatus further comprising first means (100') for detecting an inverting edge (A) between a dummy bit and a following head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or the inverting edge between an end bit of- the information data (52-57) and a following dummy bit, which dummy bit is inverted relative to said head bit or said end bit regardless of the value of said head bit or said end bit, said one or more dummy bits each being provided together with information data (52-57) in units of n bytes, where n is a positive integer greater than or equal to two at locations so as to divide the plurality of information data of said serial bit data into m groups of n bytes where m is a positive integer, which dummy bit is used for generating said inverting edge (A) before said head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or after said end bit of the information data. An apparatus for detecting serial bit data as claimed in claim 6, including second means for detecting serial bits of the serial bit data (52-59) following and based upon the detecting of said inverting edge (A). An apparatus for detecting serial bit data (52-59) as claimed in claim 7 wherein said second means includes: a) generating means (33") for generating a clock signal (j 1 ) to read the serial bit data (52-59); b) resetting means (100') for resetting said generating means (33") in response to the inverting edge (A) detected by said first means; and c) reading means for reading the serial bit data (52-59) in response to said clock signal (j 1 ). An apparatus for detecting serial bit data as claimed in claim 8 wherein said generating means (33") includes a generator (33") for generating a clock signal (j 1 ) to read said serial bit data (52-59) at substantially the centre of each bit of the serial bit data (52-59). A recording medium on which an audio signal compressed in time base with a predetermined compression ratio is recorded together with a data signal which includes a plurality of information data (52-57) each of which has a predetermined number of bits for one sample, at least one dummy bit and a synchronising pattern (51) at the head of the information data (52-57) and the recording medium being characterised by error detecting data (58,59) to reproduce the audio signal in a block defined by a start signal and an end signal; wherein said data signal is composed of said serial bit data (52-59) and wherein a dummy bit is provided before a head bit of said respective information data (52-57) or error detecting dta (58,59) of the serial bit data (52-59) or after an end bit of said information data (52-57) which dummy bit is inverted relative to said head bit or said end bit regardless of the value of said head bit or said end bit, said one or more dummy bits each being provided together with information data (52-57) in units of n bytes where n is a positive integer greater than or equal to two at locations so as to divide the plurality of information data (52-57) of said serial bit data (52-59) into m groups of n bytes, where m is a positive integer, which dummy bit is used for generating an inverting edge (A) before said head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data or after said end bit of the information data (52-57). A recording medium as claimed in claim 10 being of disk form. A recording medium as claimed in claim 10 being a magnetic medium. A recording medium as claimed in claim 10 wherein said data signal also is compressed with said compression ratio. A recording medium as claimed in claim 11 including concentric tracks each including four of said blocks. A method of recording in which an audio signal is compressed in time base with a predetermined compression ratio and is recorded together with a data signal which includes a plurality of information data (52-57) each of which has a number of bits for one sample to record the audio signal in a block, the method comprising including one or more dummy bits in the information data (52-57) and adding a predetermined synchronisation pattern (51) at the head of the block characterised by adding error detecting data and defining the block by a start signal and an end signal wherein said data signal is composed of serial bit data (52-59) and wherein the dummy bit is provided before a head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or after an end bit of said information data (52-57), which dummy bit is inverted relative to said head bit or said end bit regardless of the value of said head bit or said end bit, said one or more dummy bits each being provided together with information data (52-57) in units of n bytes, where n is positive integer greater than or equal to two, at locations so as to divide the plurality of information data of said serial bit data into m groups of n bytes where m is a positive integer, which dummy bit is used for generating said inverting edge before said head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or after said end bit of the information data (52-57). A recording apparatus by which an audio signal compressed in time base with a predetermined compression ratio is recorded together with a data signal which includes a plurality of information data (52-57) each of which has a predetermined number of bits for one sample to reproduce the audio signal in a block, the apparatus comprising means (12') for including one or more dummy bits and means for adding a predetermined synchronisation pattern (51) at the head of the block characterised in that the apparatus further comprises means for including error detecting data (58-59), the block being defined by a start signal and an end signal and wherein said data signal is composed of said serial bit data (52-59) and wherein the dummy bit is provided before a head bit of the respective information data (52-57) or error detecting data (58,59) of said serial bit data (52-59) or after an end bit of said information data (52-57), which dummy bit is inverted relative to said head bit or said end bit regardless of the value of said head bit or said end bit, said one or more dummy bits each being provided together with information data (52-57) in units of n bytes, where n is a positive integer greater than or equal to two at locations so as to divide the plurality of information data (52-57) of said serial bit data (52-59) into m groups of n bytes where m is a positive integer, which dummy bit is used for generating said inverting edge before said head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit, data (52-59) or after said end bit of the information data (52-57). A reproducing apparatus for reproducing an audio signal from a recording medium as claimed in claim 12 including an apparatus for detecting serial bit data as claimed in claim 6. A recording and reproducing apparatus comprising a recording apparatus as claimed in claim 16 and a reproducing apparatus as claimed in claim 17. A serial bit data signal including a plurality of information data blocks (52-57) each of which has a predetermined number of bits and which includes one or more dummy bits which produce an inverting edge (A) and the signal having a synchronisation pattern (51) preceding the plurality of information data blocks (52-57) characterised by said signal further comprising error detecting data (58,59) and said inverting edge (A) being provided between a dummy bit and a following head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or between an end bit of the information data (52-57) and a following dummy bit, the dummy bit being inverted relative to said head bit or said end bit regardless of the value of said head bit or said end bit, said one or more dummy bits each being provided together with information data (52-57) in units of n bytes, where n is a positive integer greater than or equal to two at locations so as to divide the plurality of information data (52-57) of said serial bit data (52-59) into m groups of n bytes where m is a positive integer, the dummy bit providing said inverting edge (A) before said head bit of the respective information data (52-57) or error detecting data (58,59) of the serial bit data (52-59) or after said end bit of the information data (52-57).

Inventors: KIMURA NORIO, SAKATA TSUGUHIDE, TAGUCHI TOMISHIGE, TAKEI MASAHIRO, KIMURA, NORIO, SAKATA, TSUGUHIDE, TAGUCHI, TOMISHIGE, TAKEI, MASAHIRO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1986
Main classification: G11B20
IPC codes: G11B20, H04L25, H04L7