ELECTRONIC CONVERSION CIRCUIT

Abstract: In an electronic conversion circuit for converting an an­ alog value to digital codes or digital codes to an analog value, the circuit comprises at least two analog processing units (11A, 11B) providing conversion hold blocks. Each of the an­ alog processing units (11A, 11B) has two functions, that is, one function is to perform sampling of an analog value and to circularly convert the analog value to an output analog value in order to obtain a digital value based on the output analog value by a cyclic A/D conversion method, and the other func­ tion is to sequentially input digital codes and to convert digital codes in order to obtain an analog value.

Description: The present invention relates to an electronic conversion circuit for converting an analog value to digital codes or digital codes to an analog value. This circuit may be advantageously used in the field of measurements. Conversion of an analog value to digital codes or digital codes to an analog value is usually performed in the field of measurements. In general, a conversion circuit requires such characteristics as a high conversion speed, high resolution, small power consumption, and small quantizing errors. There is known, for example, an analog-to-digital (A/D) conversion circuit which employs a cyclic A/D conversion method. In this conventional circuit, it is necessary to provide at least one voltage conversion block, a sample hold block, and a comparison block. Accordingly, two steps of "conversion" and "sample hold" are necessary to obtain a digital one bit since the conversion is completed through these blocks as one cycle (operated successively). There are, however, problems in the conversion speed and so-called "clock feed through error" caused by an increased number of analog switches. EP-A-0 124 132 discloses a switched-capacitor circuit analog-to-digital converter using a cyclic A/D conversion method. The converter comprises a recycling unity gain integrator, and a delay circuit which is connected in a head-to-tail fashion with the integrator and constituted by a recycling unity gain buffer. The delay circuit acts to recycle, therefore to delay and store, a voltage level used in a previous bit resolution. According to a first aspect of the present invention, there is provided an analog processing unit comprising:- external connection terminals including an input terminal and an output terminal; an operational amplifier having at least a non-inverting input, an inverting input, and an output connected to said output terminal of the unit; a first switching means provided between the inverting input of said amplifier and the output terminal of the unit; a capacitor connected at one end thereof to the inverting input of said amplifier and connected at its other end to a second switching means for changing between the input terminal and the output terminal of the unit; a charging/discharging unit constituted by at least one other capacitor and a third switching means, each of said capacitors being connected at one end thereof to the inverting input of said amplifier, said other capacitor being connected at the other end to the third switching means, and the third switching means being selectively connected to one of the external connection terminals, to a reference voltage terminal or to a ground terminal; and a fourth switching means and a further capacitor, the fourth switching means being selectively connected to said reference voltage terminal or said ground terminal, one end of the further capacitor being connected to the inverting input of said amplifier and the other end of the further capacitor being connected to the fourth switching means. According to a second aspect of the invention there is provided an electronic conversion circuit for converting analog value to digital codes comprising first and second analog processing units of the kind described above, the second unit having an input terminal connected to receive an output analog value from the first unit, and the first unit having an input terminal selectively connectable to receive either an input analog value supplied to the electronic conversion circuit or an output analog value of the second unit; whereby each of the first and second units is operable alternately to sample the analog value supplied to its input terminal and to convert that analog value into an output analog value, in order to obtain digital codes representing the input analog value supplied to the electronic conversion circuit. According to a third aspect of the present invention, there is provided an electronic conversion circuit for converting digital codes to an analog value, comprising first and second analog processing units of the kind described above, the second unit having an input terminal connected to receive an output analog value from the first unit, and the first unit having an input terminal selectively connectable either to a ground terminal or to receive an output analog value from the second unit; whereby each of the first and second units is operable, under control of input digital codes, alternately to sample the analog value supplied to its input terminal and to convert that analog value into an output analog value, such that the output analog value finally obtained by the first unit is an analog representation of said digital codes. An embodiment of the present invention may provide an electronic conversion circuit for converting an analog value to digital codes or digital codes to an analog value thus enabling a high-speed conversion, high resolution, small power consumption, and small quantizing errors. An embodiment of the present invention may provide an electronic conversion circuit for converting an analog value to digital codes or digital codes to an analog value comprising at least two analog processing units, each of the analog processing units having two functions, one function being to perform sampling of the analog value and to convert the analog value to an output analog value in order to obtain a digital value based on the output analog value, and the other function being to perform sampling of the analog value and to input digital codes and to convert digital codes in order to obtain the analog value. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is a block diagram of an electronic conversion circuit, Fig. 2 is a block diagram of an electronic conversion circuit according to the present invention, Figs. 3A to 3H are detailed circuits of a analog processing unit shown in Fig. 2, Fig. 4 is a detailed block diagram of an analog-to-digital convertion circuit shown in Fig. 2, Fig. 5 is a chart for explaining the operation of circuits shown in Fig. 4, Fig, 6 is a view for explaining the operation of the shift registers and adders shown in Fig. 4, Fig. 7 is a partial circuit diagram of an adder, Fig. 8 is a function chart of the circuit shown in Fig. 7, Fig. 9 is a detailed block diagram of an analog-to-digital conversion circuit according to another embodiment of the present invention, Fig. 10 is a chart for explaining the operation of circuits shown in Fig. 9, Fig. 11 is a detailed block diagram of a digital-to-analog conversion circuit according to an embodiment of the present invention, Fig. 12 is a chart for explaining the operation of circuits shown in Fig. 11, Figs. 13A and 13B are views for explaining switch operations in response to a clock signal CLK2 shown in Fig. 12, Fig. 14 is a view for explaining the digital-to-analog conversion shown in Fig. 11, and Figs. 15A and 15B are charts for explaining a conversion range and codes of the A/D and D/A conversion in the best mode. Before describing the preferred embodiments, an explanation will be given of a previous electronic conversion circuit. Referring to Fig. 1, this type of analog-to-digital conversion circuit is called a cyclic A/D conversion method. In Fig. 1, reference number 1 represents a conversion block, 2 a sample hold block, and 3 a comparator. Reference letter V i represents an analog input voltage, V₀₀ , V₀₁ output voltages of the conversion block 1, V R a reference voltage, V R /2 a decision level voltage, and V AD a digital output. The operations of this circuit will be explained briefly hereinafter. When the analog input voltage is applied to the conversion block 1, the output voltage V₀₀, which is converted from the analog input voltage, is applied to the sample hold block 2 and the comparator 3. In the sample hold block 2, electric charges are held by the output voltage V₀₀. In the comparator, the voltage V₀₀ is compared with a half voltage of the reference voltage V R used as a decision level voltage V R /2. When the voltage V₀₀ is larger than the decision level voltage V R /2 a digit "1" is generated as a digital output V AD . When the voltage V₀₀ is smaller than the V R /2, the digit "0" is generated. These digits are also fed back to the conversion block 1 and used as a command signal for subtraction or not of the reference voltage V R . The voltage V₀₀ held in the sample hold block 2 is added to the conversion block 1 as the input voltage. In the conversion block 1, the voltage V₀₀ is added to the voltage V₀₀ which is held as the output voltage generated based on the previous input voltage, and the resultant data is then output as the output voltage V₀₁ after subtraction or without subtraction in accordance with the command from the comparator. Details of the above explanations will be given by using concrete data. In this case, the input voltage; V i = 0.875 (V) the reference voltage; V R = 1 (V) the decision level voltage; V R /2 = 0.5 (V) are previously given. Step 1. In the conversion block 1; When the analog voltage 0.875 (V) is input as the input voltage V i , the voltage 0.875 (V) occurs as the output voltage V₀₀ in the first stage. Step 2. In the comparator 3; When the voltage V₀₀ (= 0.875 V) is compared with the decision level voltage V R /2 (= 0.5 V), the voltage V₀₀ is naturally larger than the voltage V R /2, and thus the digit "1" is output as the digital output V AD . Simultaneously, this digital output V AD is fed back to the conversion block 1 so as to subtract the reference voltage V R from the resultant data. Step 3. In the sample hold block 2; An internal capacitor (not shown) is charged by the voltage V₀₀ (= 0.875 V) and this voltage V₀₀ (= 0.875 V) is applied to the conversion block 1 as the input voltage generated in the inner circuit. Step 4. In the conversion block 1; The voltage V₀₀ (= 0.875 V) from the sample hold block 2 is added to the previously held output voltage V₀₀ (= 0.875 V) and the reference voltage V R is subtracted from the above resultant data. Accordingly, Step 5. In the comparator 3; When the output voltage V₀₁ (= 0.75 V) is compared with the decision level voltage (= 0.5 V), the voltage V₀₁ is naturally larger than the voltage V R /2, and thus the digit "1" is output as the digital output V AD . Simultaneously, this digital output V AD is fed back to the conversion block 1 so as to subtract the reference voltage V R from the resultant data. Step 6. In the sample hold block 2; The internal capacitor is charged by the voltage V₀₁ (= 0.75 V), and this voltage V₀₁ (= 0.75 V) is also applied to the conversion block 1 as the input voltage generated in the inner circuit. Step 7. In the conversion block 1; The voltage V₀₁ (= 0.75 V) from the sample hold block 2 is added to the previously held output voltage V₀₁ (= 0.75 V) and the reference voltage V R is subtracted from the above resultant data. Accordingly, Step 8. In the comparator 3; When the output voltage V₀₂ (= 0.5 V) is compared with the decision level voltage (= 0.5 V), the voltage V₀₂ is naturally equal to the voltage V R /2, and thus the digit "1" is output as the digital output V AD . Simultaneously, this digital output V AD is fed back to the conversion block 1 so as to subtract the reference voltage V R from the resultant data. Step 9. In the sample hold block 2; The internal capacitor is charged by the voltage V₀₂ (= 0.5 V), and this voltage V₀₂ (= 0.5 V) is also applied to the conversion block 1 as the input voltage generated in the inner circuit. Step 10. In the conversion block 1; The voltage V₀₂ (= 0.5 V) from the sample hold block 2 is added to the previously held output voltage V₀₂ (= 0.5 V) and the reference voltage V R is subtracted from the above resultant data. Accordingly, Since the output voltage became 0 (V), the voltage conversion is completed and a digital value "111" is obtained from the comparator 3 as the digital output. As can be understood from the above explanation, in the previous analog-to-digital conversion circuit, it is necessary to provide two blocks, i.e., a voltage conversion block for obtaining a (digital) value based on the reference voltage and a sample hold block for holding the converted output voltage. Therefore, two steps are necessary to obtain one digital bit since the signal passes through the conversion block and the sample hold block as the necessary one (single) route. These two steps become obstacles to high speed analog-to-digital conversion. Moreover, because it is necessary to provide many analog switches, these many analog switches cause a so-called "clock feed through-error" when, for example, a MOS FET is used as the analog switching means. An electronic conversion circuit according to the present invention will be explained in detail hereinafter. Referring to Fig. 2, reference numbers 11A and 11B represent analog processing units. These units have the same structure and the detailed structure thereof will be explained with reference to Figs. 3A to 3H. Reference number 12 represents a control circuit and SW an input changing switch. The control circuit 12 includes at least one comparator for comparing an output voltage from the analog processing unit 11A with a decision level voltage, a series-to-parallel conversion shift register and an adder, a gate circuit for controlling the connection of switches provided in the analog processing unit, and a flip-flop circuit for latching the output from the comparator. In this embodiment of the invention, a sampling operation and conversion are repeated alternately in each analog processing unit. Therefore, two digital bits can be obtained when the signal passes through these two units as the necessary one route. In this case, the switch SW is changed between the input side and the feedback side based on a command from the control circuit 12. Referring to Figs. 3A to 3H, each analog processing unit used in the electronic conversion circuit comprises an operational amplifier OP having at least a non-inverting input terminal, an inverting input terminal and an output terminal; three capacitors C0 to C2; and four switches S1 to S4 corresponding to first to fourth switching means. The differences between these Figures lie in the connection configurations of the switches S1 to S4. Each of the capacitors C0 to C2 has an equal capacitance. The switch S3 and the capacitor C1 constitute a charging/discharging unit. V i represents the input voltage, V R represents the reference voltage, and V O represents the output voltage. OT represents the output terminal. When these circuits are used in an analog-to-digital conversion or a digital-to-analog conversion circuit, the output is obtained from the capacitor C2. In the analog-to-digital conversion, the output terminal OT is connected to a comparator in the control circuit 12. The circuits shown in Figs. 3A, 3E, and 3F are used for a sampling operation of the input voltage V i . The other circuits are used for the conversion from the input voltage to the output voltage. By changing the connections of these switches, the following output voltages V₀ can be obtained in the output terminal OT. That is, in Figs. 3B to 3D, (1) V O = 2V i - V R (2) V O = 2V i (3) V O = 2V i + V R In Figs. 3G and 3H, (4) V O = (V i + V R )/2 (5) V O = V i /2 (6) V O = (V i - V R )/2 In order to obtain the three kinds of output voltages shown in items (1) to (3), the following controls are necessary for the analog-to-digital conversion. A. In Fig. 3A, the sampling of the input voltage V i is performed as follows. switch S1: ON switch S2: to V i switch S3: to V i switch S4: to V R capacitor C0: charged by V R capacitor C1: charged by V i capacitor C2: charged by V i B. In Fig. 3B, the conversion of "-V R " (giving output voltage type (1)) is performed as follows. switch S1: OFF switch S2: to output terminal OT switch S3: to V R switch S4: to V R capacitor C0: charged by V R capacitor C1: charged by V R capacitor C2: charged by 2V i - V R In this case, the electric charge quantity of the capacitor C2 is given by 2V i - V R , based on "the principle of conservation of the charge". That is, although the electric charge quantity of the capacitor C0 is not changed, that of the capacitor C1 is changed to V R . Accordingly, the charge quantity V i - V R in the capacitor C1 is migrated to the capacitor C2, based on the above "principle". Therefore, the electric charge quantity of the capacitor C2 is given by, V i + V i - V R = 2V i - V R In this case, although each electric charge quantity is given by multiplying the capacitance by the voltage, i.e., C x V, these capacitances are omitted in the descriptions since the capacitances of each of the capacitors C0, C1 and C2 are equal. C. In Fig. 3C, the conversion of "0" (output voltage type (2)) is performed as follows. switch S1: OFF switch S2: to output terminal OT switch S3: to ground switch S4: to V R capacitor C0: charged by V R capacitor C1: to ground capacitor C2: charged by 2V i In this case, the electric charge quantity of the capacitor C2 is given by 2V i , based on the above "principle". That is, although the electric charge quantity of the capacitor C0 is held, that of the capacitor C1 is migrated to the capacitor C2, based on the above "principle". Therefore, the electric charge quantity C2 is given by, V i + V i = 2V i D. In Fig. 3D, the conversion of "+V R " (type (3)) is performed as follows. switch S1: OFF switch S2: to output terminal OT switch S3: to ground switch S4: to ground capacitor C0: to ground capacitor C1: to ground capacitor C2: charged by 2V i + V R In this case, as explained above, the electric charge quantities of the capacitors C0 and C1 are migrated to the capacitor C2, based on the above "principle". Accordingly, the electric charge quantity of the capacitor C2 is given by, V i + V i + V R = 2V i + V R As explained in items B to D, three kinds of output voltages V O can be obtained by changing the connections of the switches S3 and S4. A feature of this embodiment lies in the control of the switches S3 and S4. In order to obtain another three kinds of output voltages as shown in items (4) to (6), the following controls are necessary for the digital-to-analog conversion. In these conversions, it is necessary to perform the sampling in correspondence with each conversion of "+V R ", "0", and "-V R ". E. In Fig. 3E, the sampling of the input voltage V i is performed with respect to the conversion "+V R " as follows. switch S1: ON switch S2: to V i switch S3: to ground switch S4: to V R capacitor C0: charged by V R capacitor C1: to ground capacitor C2: charged by V i F. In Fig. 3F, the sampling of the input voltage V i is performed with respect to the conversion "0" as follows. switch S1: ON switch S2: to V i switch S3: to ground switch S4: to ground capacitor C0: to ground capacitor C1: to ground capacitor C2: charged by V i With respect to the conversion "-V R ", the sampling of the input voltage V i is performed based on the same connections as shown in Fig. 3F. G. In Fig. 3G, the conversion of "+V R " (i.e. following the sampling configuration of Fig.3E) is performed as follows. switch S1 : OFF switch S2: to output terminal OT switch S3: to output terminal OT switch S4: to ground capacitor C0: to ground capacitor C1: to output terminal OT capacitor C2: charged by (V i + V R )/2 With respect to the conversion of "0", (i.e. sampling type of Fig.3F), the procedure is based on the same connections as shown in Fig. 3G. In this case, the capacitor C2 is charged by V i /2. H. In Fig. 3H, the conversion of "-V R " is performed as follows. switch S1: OFF switch S2: to output terminal OT switch S3: to output terminal OT switch S4: to V R capacitor C0: charged by V R capacitor C1: to output terminal OT capacitor C2: charged by (V i - V R )/2 As can be understood from the above explanations, these conversions are also based on "the principle of conservation of the charge". As explained in items E to H, another three kinds of output voltages (for digital to analog conversion) can be obtained by changing the connections of the switches S3 and S4. Referring to Fig. 4, two of the circuits shown in Figs. 3A to 3D are used as the analog processing unit of the analog-to-digital conversion circuit in one embodiment of the invention. That is, reference number 11A is the same as circuit 11B, AlN is an analog input signal, and CLK1 and CLK2 are clock signals. These signals are input to an external circuit (not shown). Switches SA and SB are input changing switches, S1A to S7A and S1B to S7B are also circuit changing switches, and S8A and S8B are mode changing switches. C0A to C2A and C0B to C2B are capacitors for conversion, and OPA and OPB are operational amplifiers. These elements correspond to those of Figs. 3A to 3H. That is, switches S8A and S8B correspond to the switch S1; S1A, S2A, and S1B, S2B correspond to the switch S2; S3A to S5A, S3B to S5B correspond to the switch S3; and S6A, S7A and S6B, S7B correspond to the switch S4. Reference letters CPR1 and CPR2 are comparators, SR1 and SR2 are shift registers for series-to-parallel conversion and plus/minus code conversion, and CT is an adder. F1 and F2 are latch circuits for latching the output from the comparators, and SGT is a gate circuit constituted by AND gates A and NOR gates N. The switches shown in the circuit 11A and 11B are controlled by the outputs of these AND gates and NOR gates. When the output is high level, the corresponding switch is turned ON, and when the output is low level, the corresponding switch is turned OFF. The operation of these circuits will be explained in detail with reference to Fig. 5. In Fig. 5, a section (A) represents waveforms of the clock signals CLK1 and CLK2 and of the ON/OFF timing of the switches SA and SB. Section (B) represents the ON/OFF of each switch, and various signals. Reference numbers 1 to 4 in section (B) represent steps of operation of the circuit shown Fig. 4. The asterisks in the chart represent a value determined by depending on an input voltage AlN. In step 1; The connection configurations of the switches S1A to S8A are the same as that of Fig. 3A. That is, in this step, an input analog voltage AlN is taken into the circuit 11A through the switch SA. Accordingly, the sampling operation of the input analog voltage can be performed by this step. In this state, the capacitor C0A is charged by the reference voltage V R , and the capacitors C1A and C2A are charged by the input voltage AlN (the same as V i mentioned before). Since the switch S2A is turned ON, the input voltage AlN is input to the comparators CPR1 and CPR2 as the voltage V CMP . The voltage V CMP is compared with the decision level voltages +V R /4 (in the comparator CPR1) and -V R /4 (in the comparator CPR2). Assuming that the input voltage AlN is 3/8 (V), this voltage is larger than both decision level voltages +1/4 (V) and -1/4 (V) (in this case, the reference voltage V R is 1 (V)). Accordingly, the comparator outputs CP and CN are high (H) level. The asterisks attached to both "H" levels of the CP and CN denote that these levels are decided when the input voltage is 3/8 (V). In step 2; The circuit 11A corresponds to Fig. 3B and the circuit 11B corresponds to Fig. 3A in this step. When the switches S1A to S8A and S1B to S8B are connected as shown in the chart, the comparator output voltages CP and CN are output to the shift registers SR1, SR2 and the flip flop circuits F1, F2. In this case, the output CP is input to the shift register SR1 and the flip flop F1 and the output CN is input to the shift register SR2 and the flip flop F2. The clock signal CLK2 is "H" level, and accordingly, the switches S2B, S3B, S8B and S1A are turned ON. Moreover, the clock signal CLK2 is input to each of the AND gates A and NOR gates N, and each of the switches is then turned ON/OFF in correspondence with the "H" or "L" level of the gate output SGT. Accordingly, in the circuit 11A, the output voltage V 0A of the operational amplifier OPA is obtained based on the formula V₀ = 2V i - V R , as follows. V 0A = 2 x 3/8 - 1 = -1/4 (V) where, AlN (V i ) = 3/8 (V) In the circuit 11B, the capacitor C0B is charged up by the reference voltage V R , and the capacitors C1B and C2B are charged up by the output voltage V 0A (-1/4 V) of the operational amplifier OPA. The output voltage V 0A is input to both the comparators CPR1 and CPR2 as the input voltage V CMP , through the switch S1A. The voltage V CMP is compared with the decision level voltages +V R /4 and -V R /4. Since the reference voltage V R is 1 V, the decision level voltages become +1/4 and -1/4 (V). Therefore, as a result, +1/4 > V CMP = -1/4 ≧ -1/4 Accordingly, the output voltage CP is "L" level and the output voltage CN is "H" level. In this case, since the input voltage V i = 3/8 (V), the generated digit is given by "1". In step 3; The circuit 11A corresponds to Fig. 3A and the circuit 11B correspond to Fig. 3C. When the switches S1A to S8A and S1B to S8B are connected as shown in the chart, the output voltages CP and CN, which are obtained in Step 2, are taken into the shift registers SR1, SR2 and the flip flops F1, F2, and processed as new voltages DP and DN. In the circuit 11B, the output voltage V 0B of the operational amplifier OPB is given as follows, based on the formula V₀ = 2V i . V 0B = 2 x (-1/4) = -1/2 (V) where, V i (-1/4) is given by the previous output voltage V 0A in Step 2. The voltage V 0B (= V CMP ) is compared with the decision level voltages +1/4 and -1/4. As is obvious, both output voltages CP and CN become "L" level. Since the previous input voltage V i is -1/4 (V), the generated digit is given by "0". In step 4; The circuit 11A corresponds to Fig. 3D and the circuit 11B corresponds to Fig. 3A. When the switches S1A to S8A and S1B and S8B are connected as shown in the chart, the output voltages CP and CN, which are obtained in Step 3, are taken in to the shift registers SR1, SR2 and the flip flops F1, F2, and processed as new voltages DP and DN. In the circuit 11A, the output voltage V 0A of the operational amplifier OPA is given as follows, based on the formula V₀ = 2V i + V R . V 0A = 2 x (-1/2) + 1 = 0 (V) where, V i (-1/2) is given by the previous output voltage V 0B in Step 3. The voltage V 0A (= V CMP ) is compared with the decision level voltages. In this case, as a result, 1/4 > 0 > -1/4 Thus, the output voltage CP is "L" level and the output voltage CN is "H" level. Since the previous input voltage V i is -1/2 (V), the generated digit is given by "-1". As is obvious from the next step, the generated digit in the step 1 will occur in the next conversion. That is, since the input voltage V i is 0 (V), the generated digit is given by "0". Consequently, the analog input voltage 3/8 (V)is converted to the digits 1, 0, -1, 0. These digits are divided into two binary numbers by "code conversion" as explained below. Referring to Fig. 6, the generated digits are shown by (1, 0, -1, 0). In the shift register SR1, code converted binary numbers (1, 0, 0, 0) are stored, and in the shift register SR2, code converted binary numbers (1, 1, 0, 1)are stored. In this case, a 2's complement binary code of the numbers (0, 0, 1, 0) is used at the shift register SR2. This is because both binary numbers stored in the SR1 and SR2 can be added only in the adder CT as explained below. In the shift registers SR1 and SR2, the least significant bit (LSB) is on the right side, and the most significant bit (MSB) is on the left side. These values are added by the adder CT. The operation of the adder is explained is Figs. 7 and 8. As is obvious from the Figure, although the digits stored in the SR1 and SR2 are given by four digits, five digits have occurred due to the carry of the MSB in the shift registers SR1 and SR2. Accordingly, the fifth bit (= 1) of the MSB is inverted to "0" by using the inverter INV. Consequently, the binary number (0 1 1 0) is obtained from the output of the adder CT. This binary number is, of course, equal to the analog number 3/8. Referring to Figs. 7 and 8, this circuit and function chart are known, as is the adder. This adder is the 4 bits binary full adder MODEL MB74LS283 made by Fujitsu Limited. For example, when inputs A1, A2 are "H" level and inputs B1, B2 are "L" level, outputs Σ1, Σ2 are "L" level when on input C0 is "H" level, and when inputs A3, B3 are "L" level and inputs A4 and B4 are "H" level, outputs Σ3, Σ4 are"H" and "L" level when an input C0 is "H" level. The above explained embodiment shown in Figs. 3A to 3H may be performed (applied) when the charging/discharging unit comprises only one capacitor and corresponding switch, i.e., the capacitor C1 and the switch S3. Next, an explanation will be given of how a plurality of charging/discharging units and corresponding comparators may be provided in the analog-to-digital conversion circuit in an embodiment of the invention. In this case, it is assumed that all capacitors have equivalent capacitances. By this structure, the analog-to-digital conversion speed can be considerably increased. As explained before, two charging/discharging units are initially used, as shown in Fig. 4, and accordingly, in this case the number of capacitor can be shown by n = 2. The explanation is given regarding the number of capacitors shown by (n - 1) (n is an integer which is larger than three). In the control circuit 12, there are provided (n - 1) pieces of comparators, flip-flop circuits and gate circuits. In this case, the switch connected to the number "i" capacitor is controlled by the control signals from the gate circuit. The control signals are equivalent to the signals S3A, S4A, S5A, S3B, S4B, and S5B. The decision level voltage for the number "i" comparator is given by V R ·i/n (V). This decision level voltage V R ·i/n is compared with the V CMP , and thus it is possible to obtain resultant data of m bits (n = 2 m ) as the analog-to-digital conversion. When the input voltage V i (V R ·i/n ≦ V i < V R ·(i + 1)/n) is input to the other analog processing unit, the outputs of the comparators from number one to number i are "H" level, and outputs of the remaining comparators are "L" level. At this time, the capacitor C2 and all capacitors in the charging/discharging unit are connected to the input side. In next step, the output of the comparator is applied to the analog processing unit which is changed to the output state after conversion. As a result, the switches from number one to number i in the unit are connected to the reference voltage V R side, and remaining switches are connected to the ground side. By these connections, the output voltage V₀ is given as follows. V₀ = n·V i - i·V R In this case, the voltage range is given by 0 ≦ V₀ < V R This output range is preferable since the output voltage lies in the above range. Resultant data analog-to-digital conversion can be obtained by a priority encoder (for example, Model SN74LS148 made by TEXAS INSTRUMENTS CO.). In this case, the input terminal (signal "0" input terminal) of the priority encoder is activated, and the first output of the comparator is added to the signal "1" input to the terminal of the priority encoder. Below, the number "(n - 1)" output of the comparator is sequentially connected to the signal "n - 1" input terminal of the priority encoder. In this case, it is necessary to provide the inverter circuit between the comparator and the priority encoder in accordance with a positive logic or negative logic operation. When the number n is given by 2 m ( m is an integer which is larger than two), m bits resultant data of analog-to-digital conversion data from the MSB are obtained in the first conversion cycle, below, in every conversion cycle, m bits data from the MSB are output as the output of the priority encoder. As explained above, high speed analog-to-digital conversion can be achieved by this method. Referring to Fig. 9, the differences from the first embodiment shown in Fig. 4 lie in that the comparator CPR2, the flip-flop F2, the shift register SR2, and the adder CT are eliminated. By these modifications, the inputs of the NOR gates for the control signal S6A, S7A, S6B, S7B are connected to the flip-flop F1 instead of F2. The output of the shift register SR1 is directly sent to the output terminal except for the MSB. The MSB of the shift register SR1 is output through the invertor INV. In this comparator CPR1, one input terminal is connected to the analog processing unit and the other input terminal is connected to the ground. Referring to Fig. 10, the outputs CN and DN shown in Fig. 5 are eliminated in this embodiment. Regarding the operations from steps 1 to 4, since the same explanations as shown in Fig. 5 apply, detailed explanations thereof will be omitted. After these steps, the generated digits "1 -1 1 1" are obtained. These digits are converted to the binary number by plus/minus code conversion so that binary codes "1 0 1 1" and "0 1 0 0" are obtained. The reason for the elimination of the adder CT is as follows. That is, when the generated digits are given by "1, (-1), 1, 1", the code conversion for plus and minus becomes "1, 0, 1, 1" and "0, 1, 0, 0". However, for the code conversion for minus, the 2's complement number "1, 0, 1, 1" is used, and this binary code and the above "1, 0, 1, 1" at the code conversion for plus are added. Therefore, the above calculation can be easily performed by only shifting a digit in the shift register SR1. Consequently, it is not necessary to provide the adder in the analog-to-digital conversion circuit. However, the inverter is necessary for the MSB. Referring to Fig. 11, the switches S8A and S8B correspond to the switch S1 of Figs. 3E to 3H; S1A, S2A, and S1B, S2B correspond to the switch S2; S3A, S5A, and S3B, S5B correspond to the switch S3; and S6A, S7A, and S6B, S7B correspond to the switch S4. For a digital-to-analog conversion, the operations of the switches S1A, S2A, S3A, S5A, S8A, S1B, S2B, S3B, S5B and S8B are made regardless of the input digital code, but the operations of the switches S6A, S7A, S6B and S7B depend on the input digital code. An example of a digital-to-analog conversion will be explained with reference to Figs. 12, 13A, and 13B. Referring to Fig. 12, this chart shows a case wherein the digital value (0.101) is converted to the analog value (5/8). As shown in Fig. 13A, since the least significant bit LSB is "1", the ON/OFF of the switches S6A and S7A becomes as shown by steps 1 and 2. Similarly, since the most significant bit MSB is "1", the ON/OFF of the switches S6A and S7A also becomes as shown by steps 3 and 4. These switch configurations are the same between steps 1, 2 and step 3, 4. However, regarding the intermediate bit "0", as shown in Fig. 13B, the ON/OFF of the switches S6B and S7B becomes as shown by steps 2 and 3. In step 2, the output V 0A of the operational amplifier OPA is given based on the formula V₀ = (V i + V R )/2 as follows. V 0A = 1 2 (0 + 1) = 1 2 where, V i = 0, V R = 1 . In step 3, the output V 0B of the operational amplifier OPB is given as follows. V 0B = 1 2 ( 1 2 + 0) = 1 4 where, V i = V 0A = 1 / 2, V R = 0. In step 4, the output V 0A of the operational amplifier OPA is given as follows. V 0A = 1 2 ( 1 4 + 1) = 5 8 where, V i = V 0B = 1 4 , V R = 1 . Consequently, the analog output voltage 5/8 (V) can be obtained from the output of the operational amplifier 0PA. Referring to Fig. 14, the digital input code is given by "0·a₁ a₂ --- a n-1 a n ". The conversion of the input code to the analog value is started from the LSB, and the conversion regarding the absolute section a₁ to a n is completed by (n + 1) cycles of the clock signal CLK2. When the number n is odd, the converted analog output is obtained by the V 0A , and when the number n is even, the converted analog output is obtained by the V 0B . Referring to Figs. 15A and 15B, these charts represent a conversion range and codes of the A/D and D/A changeable converter constituted by an integrated circuit (IC). Since the resolution rate is 16 bits, 1LSB becomes V R /2¹⁵. In Fig. 15A, when the analog input voltage V i is zero volt, the output digital code is given by "0000 --- 0000". When the analog input voltage V i is V R /2 (V R is the reference voltage as explained above), the output digital code is given by "0100 --- 0000". When the input voltage V i is (+V R - 1LSB) or is larger than +V R , the output code is given by "0111 --- 1111". In Fig. 15B, contrary to Fig. 15A, when the input digital code is "0000 --- 0000", the analog output voltage V₀ is given by zero volt, and when the input digital code is "0111 --- 1111", the analog output voltage is given by (V R - 1LSB).

Claims: An analog processing unit comprising:- external connection terminals including an input terminal and an output terminal; an operational amplifier (OP) having a non-inverting input, an inverting input, and an output connected to said output terminal of the unit; a first switching means (S1) provided between the inverting input of said amplifier (OP) and the output terminal of the unit; a capacitor (C2) connected at one end thereof to the inverting input of said amplifier and connected at its other end to a second switching means (S2) for changing between the input terminal and the output terminal of the unit; a charging/discharging unit constituted by at least one other capacitor (C1) and a third switching means (S3), each of said capacitors (C2, C1) being connected at one end thereof to the inverting input of said amplifier (OP), said other capacitor (C1) being connected at the other end to the third switching means (S3), and the third switching means (S3) being selectively connected to one of the external connection terminals, to a reference voltage terminal or to a ground terminal; and a fourth switching means (S4) and a further capacitor (CO), the fourth switching means (S4) being selectively connected to said reference voltage terminal or said ground terminal, one end of the further capacitor (CO) being connected to the inverting input of said amplifier (OP) and the other end of the further capacitor (CO) being connected to the fourth switching means (S4). An analog processing unit as claimed in claim 1, wherein the external connection terminal to which the third switching means (S3) can be selectively connected, is the input terminal. An analog processing unit as claimed in claim 1, wherein the external connection terminal to which the third switching means (S3) can be selectively connected, is the output terminal. An analog processing unit as claimed in claim 1, 2 or 3, wherein all of the capacitors (C2, C1, C0) have equivalent capacitances. An electronic conversion circuit for converting analog value to digital codes, comprising first and second analog processing units (11A, 11B), each as claimed in any of claims 1-4, the second unit (11B) having an input terminal connected to receive an output analog value from the first unit (11A), and the first unit (11A) having an input terminal selectively connectable to receive either an input analog value (V i ) supplied to the electronic conversion circuit or an output analog value of the second unit (11B); whereby each of the first and second units is operable alternately to sample the analog value supplied to its input terminal and to convert that analog value into an output analog value, in order to obtain digital codes representing the input analog value (V i ) supplied to the electronic conversion circuit. An electronic conversion circuit for converting digital codes to an analog value, comprising first and second analog processing units, each as claimed in any of claims 1-4, the second unit having an input terminal connected to receive an output analog value (V OA ) from the first unit, and the first unit having an input terminal selectively connectable either to a ground terminal or to receive an output analog value (V OB ) from the second unit; whereby each of the first and second units is operable, under control of input digital codes, alternately to sample the analog value supplied to its input terminal and to convert that analog value into an output analog value, such that the output analog value (V OA ) finally obtained by the first unit is an analog representation of said digital codes. An electronic conversion circuit as claimed in claim 5, further comprising a control means constituted by at least one comparator (CPR1, CPR2) for comparing the output analog value (V CMP ) from said first or second analog processing unit (11A, 11B) with at least one decision level (¼ V R , -¼ V R ) and outputting a digital value (CP, CN) as a result of said comparison, at least one shift register (SR1, SR2) for converting a series of digital values (CP, CN) to a parallel digital value in order to obtain digital codes, and a gate circuit (SGT) for changing connections of switches in said first and second analog processing unit (11A, 11B). An electronic conversion circuit as claimed in claim 7, wherein said control means further comprises an adder circuit (CT) for adding the parallel digital value in order to obtain digital codes. An electronic conversion circuit as claimed in claim 7 or 8, wherein each of said comparators (CPR1, CPR2) has a different decision level (¼ V R , -¼ V R ).

Inventors: GOTOH, KUNIHIKO, KOBAYASHI, OSAMU
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H03M1
IPC codes: H03M1