A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Abstract: A semiconductor integrated circuit device comprising: at least two NPN transistors (5,l8) whose bases (7,l4) and emitters (8,l3) are connected to the ground and whose collectors are connected to an input terminal. One of said NPN transistors has a lower breakdown starting voltage and a higher breakdown maintaining voltage than those of the other of said NPN transistors.

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to the enhancement of the surge resistivity of the input terminal thereof. BACKGROUND ART Figure 3 shows a circuit diagram of an input portion of ASOO NAND Gate Schematic shown in page 7 of Advanced Schottky Family Application Report of Texas Instruments Corporation. In Figure 3, the reference numeral 1 designates an input terminal, the reference numeral 2 designates a PNP transistor, the reference numeral 3 designates an input schottky barrier diode (hereinafter referred to as "SBD"), the reference numeral 4 designates an input clamping SBD, and the reference numeral 5 designates an NPN transistor for increasing the surge resistivity. Figure 4 is a circuit diagram showing the portion relating to the surge resistivity extracted from the circuit of Figure 3, and Figure 5 is a cross-sectional view showing the IC structure for realizing the circuit of Figure 4. In the Figures 4 and 5, the reference numeral 6 designates an N type epitaxial layer, and this is used as the collector of the NPN transistor 5. The reference numerals 7 and 8 designate P⁺ and N⁺ layer produced on the surface of the epitaxial layer 6, respectively, and they are used as the base and the emitter of the NPN transistor 5. The reference numeral 9 designates an aluminum wiring connected to the internal circuit of the IC. The reference numeral 10 designates an aluminum wiring of the ground level. The reference numeral 11 designates an N⁺ layer provided so as to reduce the resistance component between the input terminal 1 and the collector 6. The reference numeral 12 designates an N⁺ layer provided so as to reduce the resistance component between the N⁺ layer 11 and the collector 6. The reference numeral 13 designates an N⁺ embedded layer of the ground level provided so as to prevent the operation of the parasitic element. The reference numeral 14 designates a P⁺ layer of the ground level provided to prevent the current leakage between the N⁺ embedded layers 12 and 13. The reference numeral 15 designates a P type substrate, and the reference numeral 16 designates an oxide film provided to separate the epitaxial layer 6 and the other epitaxial layer (not shown). The reference numeral 17 designates an oxide film provided to protect the surface of the epitaxial layer 6. Figure 6 shows the at breakdown voltage vs current characteristics (base-emitter short characteristics) of the NPN transistor 5. The operation of the device when the surge voltage is applied will be described. When a surge voltage is applied to the input terminal 1, if there is not provided an NPN transistor 5, an overcurrent flows through the input SBD 3, and a large power is consumed at the input SBD 3 because the breakdown voltage of the input SBD 3 is relatively high, that is, about 30 V, and the input SBD 3 is easily destroyed. Actually, there is an NPN transistor which shows the characteristics of Figure 6, and when a surge voltage is applied the NPN transistor 5 enters the breakdown state, and an overcurrent does not flow through the input SBD 3. Then, the transistor 5 shows a low breakdown maintaining voltage of about 7 V, and this voltage is sufficiently low with relative to the breakdown voltage of the input SBD 3, and a large portion of the surge current flows through the NPN transistor 5. By the way, in the transistor 5 the voltage drop at the junction portion is small and the power concentration on the junction portion is small, and the area of the junction portion is enlarged to a value larger than that of the input SBD 3, thereby reducing the power consumption per a unit area. Accordingly, even if a large current flows through the NPN transistor 5, the NPN transistor 5 is not likely to be destroyed with relative to the input SBD 3, and thus it is possible to enhance the anti input surge distraction resistivity to a great extent by using the NPN transistor 5. The input portion of the prior art semiconductor integrated circuit device is constructed in such a manner, and the input portion has a breakdown maintaining voltage of about 7 V, but in a device having this characteristics there is a possibility that this characteristics does not satisfy the regulation that the input voltage resistivity is 7 V depending on the way of use. That is to say, it is expected that a variation of about 1 V exists in the breakdown maintaining voltage, and when it is supposed that the prior art devices are produced, there may be produced a lot of devices having an input portion which has a breakdown maintaining voltage less than 7 V. Furthermore, when an input voltage larger than 35 V is applied temporarily in such a prior art device, a large current flows continuously even if the input voltage is reduced to 7 V. Although it cannot be necessarily said that such a device is out of regulation, it is quite undesirable. The search has disclosed an article "Lateral NPN protect device" published in the IBM Technical Disclosure Bulletin (Vol.23, No.2 of July 1980, pages 594/5 - New York, US) which discloses the features acknowledged as prior art in the claims hereto. SUMMARY OF THE INVENTION The present invention seeks to provide an improved semiconductor integrated circuit device with further improved surge voltage resistivity and improved breakdown maintaining voltage characteristics. According to one aspect of the present invention there is provided a semiconductor integrated circuit device adapted to the enhancement of the surge resistivity of an input terminal, comprising a first transistor whose base and emitter are connected to ground and whose collector is connected to an input terminal, for the enhancement of the surge resistivity thereof, characterised by a second transistor whose base and emitter are connected to ground and whose collector is connected to said input terminal, one of said transistors having a lower breakdown starting voltage and a higher breakdown maintaining voltage than those of the other of said transistors, said other transistor continuing to operate following a high surge voltage at a surge voltage input to said input terminal which is lower than the breakdown starting voltage that initiates operation of said one transistor, said one transistor operating in response to a low surge voltage or an input voltage which gradually rises. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:- Figure 1 is a cross-sectional view showing the input portion of a semiconductor integrated circuit device as an embodiment of the present invention; Figure 2 is a circuit diagram showing the input portion of the device of Figure 1; Figure 3 is a circuit diagram showing the input portion of a prior art semiconductor integrated circuit device; Figure 4 is a circuit diagram showing a portion relating to the surge resistivity which portion is extracted from the circuit of Figure 3; Figure 5 is a cross-sectional view showing the input portion which realises the circuit of Figure 4; Figure 6 is a diagram showing the at breakdown voltage vs current characteristics (base-emitter short characteristics) of the NPN transistor for enhancing the surge resistivity; and Figure 7 is a diagram showing the at breakdown voltage vs current characteristics (base-emitter short characteristics) of the NPN transistor for enhancing the input breakdown maintaining voltage. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the present invention in detail, reference will be particularly made to Figures l and 2. Figure 1 shows a cross-sectional view of the input portion of a semiconductor integrated circuit device as an embodiment of the present invention, and Figure 2 shows the circuit of the input portion of the device. In both Figures the reference numerals 1, 3, 5 to 11, 15 to 17 designate the same elements as those shown in Figures 4 and 5. The reference character 18 designates an NPN transistor newly added in this embodiment. The resistance component of the NPN transistor 18 is larger than the resistance component of the NPN transistor 5. The reference numeral 14 designates a P⁺ layer used as a base of the transistor 18. The reference numerals 12 and 13 designate N type embedded layers used as the collector and emitter of the transistor 18, respectively. Figure 7 shows the at breakdown voltage vs current characteristics (base-emitter short characteristics) of the PNP transistor 18. The operation of the device when a high voltage is applied to the input terminal will be described. At first, when a surge voltage of about 30 to 50 V or a voltage which relatively gradually rises up is applied to the input terminal 1, the NPN transistor 18 is broken down at the timing when the voltage of the input terminal becomes 20 to 25 V, thereby lowering the input voltage to 10 to 15 V. Then, the NPN transistor is not broken down because it has a breakdown starting voltage of about 35 V. Thereafter, when the input voltage is lowered to a value below 10 V, the NPN transistor 18 enters a state incapable of maintaining the breakdown state, and restores to the cut off state. Next, the operation when a high surge voltage is applied is considered. In this case, the rising up of the input voltage is extremely fast, and the input voltage exceeds transitorily 35 V before the NPN transistor 18 lowers the input voltage by the breakdown of the transistor 18. By this, both of the NPN transistors 5 and 18 are broken down, and a large portion of the surge current flows through the NPN transistor 5 and the NPN transistor 18 restores to the cut off state soon because the NPN transistor 5 has a lower breakdown maintaining voltage than that of the NPN transistor 18 and the resistance component of the NPN transistor 18 is larger than that of the NPN transistor 5. In this embodiment at the input portion a high surge resistivity is obtained by the NPN transistor 5 as similarly as in the prior art device, and furthermore the input portion is broken down at a relatively low voltage by a surge voltage of about 30 to 50 V or a relatively gradually rising voltage, and the device can be restored to a cut off state by a relatively high voltage. As is evident from the foregoing description, according to the present invention, an NPN transistor having a low breakdown starting voltage and a high breakdown maintaining voltage with relative to an NPN transistor provided for enhancing the surge resistivity is connected to an input terminal together with the NPN transistor in parallel with each other, whereby a semiconductor integrated circuit device having an input portion which has a high surge resistivity and a sufficiently high breakdown maintaining voltage is obtained.

Claims: 1. A semiconductor integrated circuit device adapted to the enhancement of the surge resistivity of an input terminal, comprising a first transistor (5) whose base (7) and emitter (8) are connected to ground and whose collector (6) is connected to an input terminal (1), for the enhancement of the surge resistivity thereof, characterised by a second transistor whose base (14) and emitter (13) are connected to ground and whose collector (12) is connected to said input terminal (1), one of said transistors (18) having a lower breakdown starting voltage and a higher breakdown maintaining voltage than those of the other of said transistors (5), said other transistor (5) continuing to operate following a high surge voltage at a surge voltage input to said input terminal which is lower than the breakdown starting voltage that initiates operation of said one transistor (18), said one transistor (18) operating in response to a low surge voltage or an input voltage which gradually rises. 2. A semiconductor integrated circuit device as claimed in claim 1, wherein a resistance component serially connected to said one transistor (18) is larger than the resistance of said other transistor (5). 3. A semiconductor integrated circuit device as claimed in claim 1, wherein said transistors (5, 18) are NPN transistors, comprising a P type semiconductor substrate (15), a plurality of N type embedded layers (12, 13) produced on said substrate spaced from each other, an N type epitaxial layer (6) produced on said N type embedded layers (12, 13), an oxide film (16) produced on said semiconductor substrate to separate said epitaxial layers (6) with each other, P layers (14) produced on said semiconductor substrate (15) directly below said oxide film to have a higher impurity density than that of said semiconductor substrate (15), P layers (7) produced in said epitaxial layers (6), and N layers (8) produced in said P layers (7), and said N type expitaxial layers (6) are used as the collector (6) of said lower breakdown maintaining voltage NPN transistor (5) at the input portion, said P layer (7) in said epitaxial layer (6) and said N layer (8) in said P layer (7) are used as the base (7) and the emitter (8) thereof, respectively, said P layers (14) produced in said semiconductor substrate (15) directly below said oxide film (16) is used as the base (14) of said higher breakdown maintaining voltage NPN transistor (18), and said N type embedded layers (12, 13) at the both sides of said P layer (14) is used as the emitter (13) and the collector (12) thereof, respectively.

Inventors: IIO, MASAYA
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1986
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29