APPARATUS FOR ANALYSING TWO-CHANNEL TRANSMISSION/REFLECTION CHARACTERISTICS

Abstract: Measuring signals of a frequency that changes with the lapse of time are guided to a test port (35c) of a reflection signal separator (35) via an input port (35a). To the test port (35c) is selectively connected a short-circuit element, an open element, or a through transmission path (45). The reflection signal separator (35) further has an output port (35b), and re­ flection signals sent from the test port (35c) and transmission signals via the through transmission path (45) are stored in first to third memory means (39, 40, 41) via heterodyne re­ ceivers (36, 37) having first and second levels correcting func­ tion. When an object to be measured is connected to the test port (35c), the output signals of the first and second hetero­ dyne receivers (36, 37) are calibrated by an arithmetic circuit (42) relying upon the contents of the first to third memory means (39, 40, 41), and are displayed.

Description: Technical Field This invention relates to an apparatus for analyzing 2-channel transmission/reflection characteristics, which can measure both transmission/reflection characteristics with the use of a 2-channel heterodyne type level measuring device. Background Art Fig. 1 is a block diagram showing a conventional reflection characteristic measuring apparatus with the use of a spectrum analyzer. Upon the receipt of an output signal from tracking generator 2 of a synchronous transmitter type, reflection signal separator 3 allows a reflection signal from to-be-measured circuit network 4 to be supplied to spectrum analyzer 1 which is comprised of a 1-channel heterodyne receiver. Reflection signal separator 3 is called an impedance bridge. As shown in Fig. 1, the output signal of tracking generator 2 is coupled to reflection signal separator 3 and circuit network 4 is connected to a measuring terminal side of reflection signal separator 3 so that a reflection signal from circuit network 4 is separated by separator 3 and supplied to an input terminal of spectrum analyzer 1. In this way, it is possible to measure the reflection characteristic. Here it is to be noted that circuit network 4 terminates in reflectionless terminating device 5. Fig. 2 is a block diagram for measuring the transmission characteristic of circuit network 4. This measuring circuit is comprised of tracking generator 2 and circuit network 4 to measure the transmission characteristic in circuit network 4. In the method for measuring the aforementioned transmission/reflection characteristics using the spectrum analyzer as shown in Figs. 1 and 2, the transmission and reflection characteristics cannot simultaneously be measured due to only one channel being present at the input of the spectrum analyzer. Furthermore, if a measuring signal is switched by a switching device to measure both the transmission and reflection signals, then no exact result of measurement can be obtained due to a variation in the reproducibility of the switching device and in the conditions of matching. From the article in the Microwave Journal of June 1983, "Automated coaxial measurement moves up to 40 GHz", and the Wiltron brochure, "5669 Automated scalar network analyzer system 10MHz - 40 GHz", of October 1983, a coaxial measurement system is known by which, in a frequency range between 10 MHz - 40 GHz, a measure of transmission and return loss is possible in a single set-up. The system provides calibration measurement based on the storage of measurement values obtained from open and short reflections of the system. These stored values are then used for the correction of the signals obtained during measurement of a circuit network. From the IEEE article, "An automatic precision IF-substitution vector ratio meter for the microwave frequency range", of December 1980, a dual-channel microwave vector ratio meter using super heterodyne receivers is known. This vector ratio meter does not measure reflection characteristics of a circuit to be measured. In view of this prior art, it is the object of the present invention to provide an improved apparatus for analyzing two-channel transmission/reflection characteristics, which can simultaneously measure both transmission and reflection characteristics without any switching of connections. This object is solved by the features of claim 1. Fig. 1 is a block diagram showing one form of a conventional apparatus for measuring a reflection characteristic; Fig. 2 is a block diagram showing one form of a conventional apparatus for measuring a transmission characteristic; Fig. 3 is a block diagram showing an analyzing apparatus according to one embodiment of this invention; Figs. 4 to 7 are block diagrams for explaining the operation of the embodiment of Fig. 3; Fig. 8 shows a signal waveform diagram for explaining the operation of this embodiment; Fig. 9 is a view for explaining the operation of a calibration; Fig. 10 is a block diagram showing one form of a heterodyne receiver in the embodiment of this invention which has a level correction function; Fig. 11 shows a practical circuit of a bandpass filter in Fig. 10; Fig. 12 is a graph showing the operation of a variable capacitance diode in Fig. 11; and Fig. 13 is a graph for explaining the operation of the circuit of Fig. 11. Best Mode of Carrying out the Invention As appreciated from Fig. 3, an apparatus for analyzing 2-channel transmission/reflection characteristics, i.e., one embodiment of this invention, includes signal generator 31 having mixer 32 and oscillator 33; variable local oscillator 34; reflection signal separator 35; input port 35a; output port 35b; test port 35c; first heterodyne receiver 36; second heterodyne receiver 37; analog/digital (A/D) converter section 38; first memory circuit 39; second memory circuit 40; third memory circuit 41; arithmetic operation circuit 42; display device 43; and cables 46, 47 and 48. Signal generator 31 is a transmitter for generating frequency signals which stepwise vary with time. Signal generator 31 is comprised of mixer 32 and oscillator 33. Output signals from the variable local oscillator 34 are supplied to first and second heterodyne receivers 36 and 37 as will be set forth below. A sweep frequency signal of variable local oscillator 34 is supplied to mixer 32. It is to be noted that two mutually synchronizing oscillators may be provided with respect to receivers 36 and 37 in place of variable local oscillator 34. Reflection signal separator 35 is comprised of a three-terminal directional coupler having input port 35a, output port 35b and test port 35c. Input port 35a is connected to the transmitting terminal of signal generator 31, output port 35b is connected to the input terminal of first heterodyne receiver 36, and test port 35c is coupled at the time of measurement to a to-be-measured object (44) and at the time of calibration to "through" transmission path 45, to short-circuiting element 52 or to open-circuiting element 53. First and second heterodyne receivers 36 and 37 are each comprised of a level measuring device having, preferably, a level correction function, and are used as, for example, a 2-channel spectrum analyzer or 2-channel network/spectrum analyser for measuring the levels of the two channels. The level correction function will be explained below in more detail with reference to Figs. 10 to 13. First memory circuit 39 is of such a type as to store an output signal M T of second heterodyne receiver 37 when signals of stepwise varying frequencies are applied from signal generator 31 to reflection signal separator 35, provided that "through" transmission path 45 is connected at the time of calibration to test port 35c of reflection signal generator 35. Second memory-circuit 40 is of such a type as to store an output signal M S of first heterodyne receiver 36 when signals of stepwise varying frequencies are supplied to reflection signal separator 35, provided that short-circuiting element 52, such as a short-circuiting connector, is connected at the time of calibration to test port 35c of reflection signal separator 35. Third memory circuit 41 is of such a type as to store an output signal M O of first heterodyne receiver 36 when signals of stepwise varying frequencies are supplied from signal generator 31 to reflection signal separator 31, provided that open-circuiting element 53, such as an open-circuiting connector, is connected at the time of calibration to test port 35c of reflection signal separator 35. Arithmetic operation circuit 42 is comprised of, for example, a CPU and is of such a type that, when at the time of measurement signals of stepwise varying frequencies are supplied from signal generator 31 to reflection signal separator 35 under the condition that the to-be-measured object (44) is connected to test port 35c of reflection signal separator 35, circuit 42 performs the following computation, while using the aforementioned signal for address signal generation, from output signal L DR of first heterodyne receiver 36 and output signal L DT of second heterodyne receiver 37: (L DTi - M Ti ) (2) where L DRi and L DTi denote digital signals which are output from first and second heterodyne receivers 36 and 37, respectively, when a signal of i-th frequency is applied from signal generator, provided that the to-be measured object is connected to reflection signal separator 35. M Ti , M Si and M Oi show digitized signals of the i-th frequency which are output from first and second heterodyne receivers 36 and 37 in accordance with address signals read out of first, second and third memory circuits 39, 40 and 41, respectively. Display device 43 is, for example, of a CRT type having the function of simultaneously displaying tracing patterns on at least two-channels. Display device 43 permits the simultaneous display of transmission/reflection characteristics calculated by arithmetic operation circuit 42. An explanation will be given below of calibration signals to be initially stored, under the control of circuit 42, first to third memory circuits 39 to 41. Fig. 4 is an explanatory view for explaining, for example, a short-circuiting calibration on the side of the first heterodyne receiver. Short-circuiting element 52 is manually connected to test port 35c of reflection signal separator 35. A signal which is input from signal generator 31 to reflection signal separator 35 advances from input port 35a toward test port 35c and, after reflected by short-circuiting element 52, advances toward output port 35b and is input to first heterodyne receiver 36. The level of an output signal emerging from first heterodyne receiver 36 is digitized by analog/digital converter section 38 and stored in second memory circuit 40. Now suppose that, for example, 1001 horizontal pixels are provided on display device 43 and that signals of 1001 frequencies are output from signal generator 31 to reflection signal separator 35. When, in this case, a signal of an i-th frequency f i is input from signal generator 31 to reflection signal separator 35 as shown in Fig. 4, a signal output level M Si of first heterodyne receiver 36 which has been digitized through analog-digital converter section 38 is stored at address i in second memory circuit 40. When signal generator 31 completes one sweep, the output levels of first heterodyne receiver 36 corresponding to the respective 0-th to 1000-th frequencies of signals emerging from signal generator 31 are stored at the respective addresses in second memory circuit 40. Fig. 5 is an explanatory view for showing, for example, an open-circuiting calibration on the side of the first heterodyne receiver. Open-circuiting element 53 is manually connected to test port 35C of reflection signal separator 35. As in the case of the arrangement shown in Fig. 4, when signal generator 31 completes one sweep, the output levels L oi of first heterodyne receiver 36 corresponding to the respective 0-th to 1000-th frequencies of signals emerging from signal generator 31 are stored at the corresponding addresses i in third memory circuit 41 under the control of CPU 42. Fig. 6 is an explanatory view for showing a calibration process on the side of second heterodyne receiver. In the arrangement shown in Fig. 6, "through" transmission path 45 is connected to test port 35c and output port 35b of reflection signal separator 35 is connected via the cable to first heterodyne receiver 36. Like the case of Fig. 4, when signal generator 31 completes one sweep, the output levels M Ti of second heterodyne receiver 37 corresponding to the 0-th to 1000-th frequencies of signals emerging from signal generator 31 are stored at the corresponding addresses i in first memory circuit 39. Prior to the measurement of the to-be-measured object (44), calibration signal data are initially stored in first to third memory circuits 39 to 41, respectively. Fig. 7 is an explanatory view showing a detail of a connection involved upon the measurement of to-be-measured object (44) which is connected between test port 35c of reflection signal separator 35 and the input terminal of second heterodyne receiver 37. As shown in Fig. 4, signals of 0-th to 1000-th frequencies are input from signal generator 31 to reflection signal separator 35. Now suppose that a signal from signal generator 31 to reflection signal separator 35 corresponds to the i-th frequency f i . At this time, a signal of a frequency (f₀ + f i ) as a sum of the i-th frequency f i from signal generator 31 to reflection signal separator 35 and intermediate frequency f₀ of first and second heterodyne receivers 36 and 37 is supplied to first and second heterodyne receivers 36 and 37 from variable local oscillator 34. With the output levels of first and second heterodyne receivers 36 and 37 as L DRi and L DTi , respectively, these output levels L DRi and L DTi are digitized by analog/digital converter 38 and input to arithmetic operation circuit 42. Calibration values MTi, MSi and MOi corresponding to the i-th frequency f i of an input signal from signal generator 31 to reflection signal separator 35 are read from first to third memory circuits 39 to 41 onto arithmetic operation circuit 42. Equations (1) and (2) are calculated from the output levels L DRi and L DTi and calibration values M Ti , M Si and M Oi by virtue of arithmetic operation circuit 42. A result of calculation is sent to display device 43 where it is displayed as a dot on the i-th pixel position in the horizontal direction of display device 43. Signals of the 0-th to 1000-th frequencies are input from signal generator 31 to reflection signal separator 35 to allow two lines to be traced simultaneously. Fig. 8 is a waveform diagram for explaining a normalizing function, in which curves I and II show the normalizing patterns on the side of the first heterodyne receiver. The output level wavers, as shown in curves III and IV in Fig. 8, due to, for example, the cable characteristic between the transmitting terminal of signal generator 31 and input port 35a of reflection signal separator 35, cable characteristic between output port 35b of reflection signal separator 35, the input terminal of first heterodyne receiver 36, internal frequency characteristic of reflection signal separator 35, cable characteristic between test port 35c of reflection signal separator 35 and the input terminal of second heterodyne receiver 37, and frequency characteristic (Long-Line Effect) on the cable whereby the pitch of a signal ripply over the length of the cable varies due to a mismatching among the respective terminals. A 180° phase shift occurs, as indicated by curves (I) and (II) in Fig. 8, between a short-circuiting calibration value M Si on the side of first heterodyne receiver 36 which is stored in second memory circuit 40 and an open-circuiting calibration value M Oi on the side of first heterodyne receiver 36 which is stored in third memory circuit 41. After the short-circuiting calibration value M SI and open-circuiting calibration value M Oi have been converted from the dB value to a linear value, an arithmetic mean of these calibration values is taken as shown in Equation (1), and a normalization process is performed by subtracting the means value from LDRi, so that the exactness of the value of Equation (1) is enhanced. If the degree of matching of test port 35c of reflection signal separator 35 is better, i.e., the S/N ratio is enough great, an arithmetic mean can be taken, as evident from Fig. 9, in the dB format. In Fig. 9, S denotes a signal component and N denotes a noise component resulting from the degree of matching of test port 35c. In Fig 8, the curves III and IV are indicated by M Ti and L DTi , respectively. If subtraction is made as indicated by Equation (2), then the aforementioned wavering is eliminated and thus the normalization is achieved. As a result, the exactness of the value in Equaction (2) is enhanced. The output levels of first and second heterodyne receivers 36 and 37 are, in general, in log representation. Equations (1) and (2) are, after converted from the log to the linear value, calculated in floating point arithmetic and, for log values involved, in fixed point arithmetic by virtue of arithmetic operation circuit 42. The level correction function of first and second heterodyne receivers 36 and 37 will be explained below with the use of Figs. 10 and 13. Fig. 10 is an explanatory view for one-channel, that is, the level correction of first heterodyne receiver 36, for example, in the embodiment of Fig. 3. Fig. 10 shows one form of heterodyne receiver including reference oscillator 36-1, input switching device 36-2, variable local oscillator 36-3, mixer 36-4, bandpass filter 36-5, level peak position detector 36-6, tracking circuit 36-7, peak value memory circuit 36-8, correction value calculation circuit 36-9, analog/digital converter section 36-10, reference level memory circuit 36-11, display device 36-12 and detector 36-13. As variable local oscillator 36-3 use is made of a type having a high frequency resolution, such as a synthesizing type. Reference oscillator 36-1 is coupled to variable local oscillator 36-3 in a phase-synchronizing relation and is of such a type as to stabilize their frequency and level. An output level ℓ₀ of oscillator 36-1 is initially stored in reference level memory circuit 36-11. Bandpass filter 36-5 is of a resolution bandwidth (RBW) type having, for example, variable capacity diode 61 as one of its component parts as shown in Fig. 11. The peak position of a tuning frequency of the filter varies depending upon a voltage applied to variable capacity diode 61. In Fig. 11, reference numeral 62 shows a crystal filter. Tracking circuit 36-7 serves to allow the tuning frequency, with which the output level of bandpass filter 36-5 becomes a peak, to coincide with an intermediate frequency f₀ of mixer 36-4. As set forth above, a voltage applied to variable capacity diode 61 is supplied as a means for making that frequency coincide with the intermediate frequency f₀. Level peak position detector 36-6 detects the position of a sweeping frequency with which the maximum of peak levels is output from bandpass filter 36-5 when the sweep frequency of variable local oscillator 36-3 minutely varies, for mixing, with respect to the reference level and reference frequency of reference oscillator 36-1. The position of the aforementioned sweep frequency is detected by making a comparison between the output of bandpass filter 36-5, i.e., the output M₀ of analog/digital converter section 36-10, when a center frequency f c is set to variable local oscillator 36-3 and the output of the bandpass filter 36-5, i.e., the output M₁ of analog/digital converter section 36, when the sweep frequency of variable local oscillator 36-3 is set to a frequency which is greater (or smaller) than the center frequency f c by one step. It is found that if, at this time, M₁ - M₀ > 0 , the maximum level is present on the side of a frequency greater (or smaller) than the center frequency f c by one step. Thus the sweep frequency of local oscillator 36-3 is set to a frequency greater (or smaller) than the center frequency f c by two steps. It has been found that, when at Mi+1 - Mi < 0 (i=1, 2, 3, ...) the sweep frequency is involved at one previous step, then the output level of bandpass filter 36-5 becomes maximal. This is self-evident from the fact that crystal filter 62 in bendpass filter 36-5 is unimodal in nature. The position of the aforementioned sweep frequency with which the output lovel of bandpass filter 36-5 becomes maximal can be detected by level peak position detector 36-6. Let it be assumed that the frequency with which the output level of bandpass filter 36-5 becomes maximal is deviated from intermediate frequency f₀ by Δf due to a change in ambient temperature as well as aging to cause the frequency f₀ to occur. In order to eliminate the deviation Δf of the frequency, a variable capacitance diode application voltage/frequency tuning curve as shown in Fig. 12 is found for bandpass filter 36-5 and the variable capacitance diode application voltage V₀ is found, for band-pass filter 36-5, from the curve so found. The variable capacitance diode application voltage V₀ is found from tracking circuit 36-7 of a ROM table type and then it is applied to variable capacitance diode 61 in band-pass filter 36-5. By so doing, the tuned frequency with which the output level of bandpass filter 36-5 becomes maximal becomes f₀ in the curve K₂ shown in Fig. 13. That is, the curve K₁ as shown in Fig. 13 is moved to the curve K₂ in Fig. 13 so that the tuned frequency of bandpass filter 36-5 coincides with the intermediate frequency f₀ from mixer 36-4. At this time, the output level of bandpass filter 36-5 and thus the level ℓ₁, which has been detected by detector 36-13 and digitized by analog/digital converter section 36-10, is stored in peak value memory circuit 36-8. Then, input switching device 36-2 is switched to the side of an input signal to be measured to determine that input signal. From the above explanation it is evident that, at the time of measuring the input signal, the tuned frequency of bandpass filter 36-5 coincides with, and thus is tuned to, the intermediate frequency f₀ from mixer 36-4. The output level ℓ M emerging from analog/digital converter section 36-10 at the time of measuring that input signal is input to correction value calculation circuit 36-9. Correction value calculation circuit 36-9 is, for example, of a CPU type which reads the levels ℓ₁ and ℓ₀ out of peak value memory circuit 36-8 and reference level memory circuit 36-11, respectively, and executes a correction value calculation of ℓ M - (ℓ₁ - ℓ₀) . The level ℓ M - (ℓ₁ - ℓ₀) so calculated through correction value calculation circuit 36-9 is supplied to display device 36-12 where it is displayed at, for example a CRT. Since at this time, as set out above, the tuned frequency of bandpass filter 36-5 coincides with the intermediate frequency f₀ from mixer 36-4, the deviation resulting from the detuning of bandpass filter 36-5 is completely corrected. The level ℓ M - ℓ₁ reaches a value at which respective deviations over a range from input switching device 36-2 to analog/digital converter section 36-10 have relatively been corrected. If the output level of reference oscillator 36-1 is set to be 0 dBm, then it is not necessary to provide reference level memory circuit 36-11. According to this invention, as set out above, the aforementioned transmission/reflection characteristics can be measured, through the 2-channel level measuring device, without modifying the associated interconnection. Since, during measurement, neither the associated interconnection is altered nor the switching device is employed, no matching conditions vary, offering the better reproducibility of measured data. Furthermore, the reflection measuring channel, that is, the first heterodyne receiver side has the function of performing a normalization step on the basis of the short- and open-circuiting calibration data and it is, therefore, possible to correct the transmission frequency characteristic and measuring end mismatching of the reflection signal separator, level frequency characteristic of the signal generator for measurement, loss frequency characteristic of the cable, and so on. On the other hand, the transmission measuring channel, that is, second heterodyne receiver can perform a normalizing function to correct the transmission frequency characteristic of the reflection signal separator, level frequency characteristic of the signal generator for measurement, loss frequency characteristic of the cable, and so on. It is, therefore, possible to obtain an exact result of measurement. If the level measuring device is so configured as to permit the measurement level to be automatically corrected as required, then it is possible to obtain a measuring value of high accuracy. If the bandwidth of the resolution bandwidth filter so calibrated varies so that the narrow band range may be employed, then it is possible to perform a stable measurement, with an improved S/N ratio, over a wider dynamic range.

Claims: An apparatus for analyzing transmission/reflection characteristics of an object to be measured, comprising: means (31) for generating a measuring signal whose frequency sequentially varies with time; a reflection signal separator (35) having an input port adapted to be supplied with the measuring signal, a test port and an output port; short-circuiting and open-circuiting elements (52,53) arranged to be selectively connected to the test port; a first heterodyne receiver (36) having a receiving terminal connected to the output port; a second heterodyne receiver (37) having a receiving terminal which is connected to the object to be measured; first memory means (40) for storing, in a calibration mode during a measurement mode, an output signal of the first heterodyne receiver in association with the frequency of the measuring signal when the short-circuiting element is connected to the test port; second memory means (41) for storing, in said calibration mode, an output signal of the first heterodyne receiver in association with the frequency of the measuring signal when the open-circuiting element is connected to the test port; and means (43) for allowing the output signals of said first and second heterodyne receivers which have been calibrated by an arithmetic operation device (42) to be displayed in association with the frequency of the measuring signal characterized in that a through transmission path is further provided in addition to said short-circuiting and open-circuiting elements to be selectively connected to the test port during the calibration mode; a third memory means (39) is provided for storing, during said calibration mode, an output signal of the second heterodyne receiver in association with the frequency of the measuring signal when the second heterodyne receiver is connected to the test port via the through transmission path; an enabling means (35) is further provided for enabling the receiving terminal of the second heterodyne receiver to be coupled to said test port via said through transmission path during the calibration mode, and for enabling said receiving terminal of the second heterodyne receiver to be coupled to said test port via the object to be measured during a measurement mode; and said arithmetic operation device (42) calibrates the output signals of both the first and the second heterodyne receivers in accordance with the memory contents of said first to third memory means during the measurement mode. The apparatus according to claim 1, in which said generating means includes means for generating a sweep frequency signal for varying the frequency of the measuring signal with time. Apparatus according to claim 1 or 2 in which said first and second heterodyne receivers have a level correction function.

Inventors: ITAYA HIROSHI, SAITO GORO, ITAYA, HIROSHI, SAITO, GORO
Applicants: ANRITSU CORP, ANRITSU CORPORATION
Application year: 1986
Main classification: H04B3
IPC codes: G01R27, H04B17, H04B3