IMMEDIATE INSTRUCTIONS WITH FIXED SIGN POSITION

Abstract: A computer instruction set is presented in accordance with the preferred embodiment of the present invention. Some instruc­ tions within the instruction set have immediate fields which are allowed to vary in length and fill up all unused bit positions in the instructions. A sign bit is in a fixed location for instructions within the instruction set. For example, the sign bit may be right justified with respect to the immediate field, that is the sign bit is put in the least significant (rightmost) bit position. This allows time-critical suboperations to proceed without waiting for the value of the sign bit to be located and decoded.

Description: Background and Summary of the Invention The present invention relates to the structure of instructions within an instruction set of a computer. Some computer instructions contain immediates. What is meant by an "immediate" is data embedded in an instruction itself. This data may be used as an operand in an arithmetic operation or as a displacement or offset value for calculating addresses. Immediates are stored in immediate fields which are within instructions. A sign bit within an immediate field is usually the most significant (leftmost) bit of the immediate field. A computer instruction set may have immediate fields of different lengths for different instructions within the instruction set. As a result of the above, the sign bit for immediate fields may vary in location from instruction to instruction. This can unduly increase the complexity of the instruction decoding process and can be especially burdensome if the sign bit contains information to control operations or suboperations specified by the instruction. When instructions themselves are of variable length, extensive decoding is already required to select each field of an instruction. Complexity required to extract and decode a sign bit may be negligible in relation to the decoding overhead required for each instruction. However, instruction fetching and decoding overhead required often makes variable length instructions unattractive. When instructions are of fixed length, various means to select a sign bit may be employed. For instance, multiplexors may be used to select a sign bit. However, the use of a multiplexor requires additional hardware and may add additional delay to a critical timing path. Alternatively, signed immediates may not be permitted to vary in length and must occupy the same bit positions in all instructions in which they occur. Then the customary leftmost position of a sign-bit within an immediate field would place the sign bit in the same position for each instruction. This, however, may unduly restrict the number of immediate values that may be represented. ACM Sigplan Notices, Vol. 17, No. 4, 1982, pages 39-47, ACM New York, U.S. discloses a system comprising a hardware prototype, control program and an optimising compiler. Instruction formats utilise a 32 bit architecture and subsets which include a 16 bit and a 26 bit immediate field. A paper by G.H. Katevenis entitled "Reduced Instruction Set Computer Architecture for CLIS" 1985, pages 177-199, MIT Press describes the architecture of a corresponding NMOS chip in which instruction sets are used with short-immediate and long-immediate formats. Opcodes are used as leading bits which determine the format of the shortSOURCE2 field in the short-immediate format. The present invention relates to the use of an instruction set including at least two instructions having the same bit length but having immediate fields of different bit length. The invention as claimed is characterised in that respective first and second sign bit positions in or adjacent the first and second immediate fields occupy the same relative position in the respective instructions in order to facilitate decoding. In a preferred embodiment of the invention, instruction set immediate fields are allowed to vary in length from instruction to instruction. In particular, an immediate field is allowed to fill up all unused bits in a fixed-length instruction. However, a sign bit within each immediate field is placed in a fixed position within the instruction. For example, the sign bit may be right justified, that is the sign bit is put in the least significant (rightmost) bit position of an immediate field rightmost bit where the immediate field is in a fixed location for every instruction in the instruction set which has a signed immediate value. This allows time-critical suboperations to proceed without waiting for the value of the sign bit to be located. At execution time, an immediate value may be reassembled with the sign bit in the leftmost position by appropriate computer hardware and/or software. For instance, the placement of the sign bit can be moved by merely rearranging the order of wires carrying data. The immediate value may then be sign extended to any desired number of bits. Furthermore, in accordance with the present invention in an instruction an immediate value may be placed in non-contiguous variable portions of an instruction. This is done in order to allow a fixed-length instruction to use a maximal number of bit positions within the instruction to represent immediate values without writing over fixed bit positions in other fixed fields. Brief Descriptions of the Drawings Figures 1-7 show, for an instruction set, instruction formats with embedded signed immediate fields in accordance with the preferred embodiment of the present invention. Figure 8 is a partial block diagram of a computer which executes the instruction set shown in Figures 1-7 in accordance with the preferred embodiment of the present invention. Description of the Preferred Embodiment Figures 1-7 show seven fixed length instructions within an instruction set. Instructions 10, 20, 30, 40, 50, 60, and 70 within Figures 1-7 may instruct a computer to, for instance, load data from a memory location, store data in a memory location, branch conditionally or unconditionally to a new section of code, place a long immediate value in a register or perform an arithmetic computation. In each of instructions 10, 20, 30, 40, 50, 60, and 70 fixed fields may contain values which function as, for instance, operation codes, register addresses, immediate values, suboperation codes, condition specifiers and status fields. Figure 1 shows instruction 10 having six fixed position fields 11, 12, 13, 14, 15, and 16. Instruction 10 has no immediate field. Figure 2 shows instruction 20 having five fixed position fields 21, 22, 23, 24 and 25. Instruction 20 also contains a maximal length immediate value contained in an immediate field 27 and a sign-bit field 28. Sign bit field 28 is right justified with respect to immediate field 27. Figure 3 shows instruction 30 having five fixed position fields 31, 32, 33, 34 and 35. Instruction 30 also contains a maximal length immediate value contained in an immediate field 37 and a sign-bit field 38. Sign bit field 38 is right justified with respect to immediate field 37. Fixed position field 35 is shorter than fixed position field 25 in instruction 20. Immediate field 37 has expanded to utilize the additional room in instruction 30. Figure 4 shows instruction 40 having three fixed position fields 41, 42, and 43. Instruction 40 also contains a maximal length immediate value contained in an immediate field 47 and a sign-bit field 48. Sign-bit field 48 is right justified with respect to immediate field 47. Instruction 40 has no fixed position fields corresponding to fields 34 and 35 of instruction 30. Immediate field 47 has expanded to utilize the additional room in instruction 40, caused by the reduced number of fields. Figure 5 shows instruction 50 having three fixed position fields 51, 52, 55. Instruction 50 also contains a maximal length immediate value contained in an immediate field 57, an immediate field 59 and a sign-bit field 58. Sign bit field 58 is right justified with respect to immediate field 57. For maximal utilization of available space within instruction 50, the maximal length immediate value is contained in immediate field 57, in sign bit field 58 and in immediate field 59 even though immediate field 57 and immediate field 59 are noncontiguous. Figure 6 shows instruction 60 having four fixed position fields 61, 62, 65, and 66. Instruction 60 also contains a maximal length immediate value contained in an immediate field 67, an immediate field 69 and a sign-bit field 68. Sign bit field 68 is separated from immediate field 67 by fixed position field 66. For maximum utilization of available space within instruction 60, the maximal length immediate value is contained in immediate field 67, in sign bit field 68 and in immediate field 69 even though immediate field 67, sign bit field 68 and immediate field 69 are noncontiguous with respect to each other. Figure 7 shows instruction 70 having two fixed position fields 71 and 72. Instruction 70 also contains a maximal length immediate value contained in an immediate field 77 and a sign-bit field 78. Sign-bit field 78 is right justified with respect to immediate field 77. Instruction 70 has no fixed position fields corresponding to field 43 of instruction 40. Immediate field 77 has expanded to utilize the additional room in instruction 70, caused by the reduced number of fields. Instructions 20, 30, 40, 50 60 and 70 shown in Figures 2-7 all have the same number of bits. Maximal length immediate values contained in instructions 20, 30, 40, 50, 60 and 70 have a varying bit length, depending upon the number and length of fixed position fields within each instruction. All available bit locations, not utilized by fixed location fields may be utilized to contain maximal length immediate values. In Figure 8, a computer is shown to contain an instruction and data memory 80, an instruction unit 81, an execution unit 82 and a register file 83. Typically, when executing an instruction, instruction unit 81 calculates an address of a next instruction to be executed. This address is sent via a memory address bus 85 to instruction and data memory 80. Using the received address, memory 80 locates the next instruction and sends the next instruction to instruction unit 81, execution unit 82 and register file 83 via an instruction bus 84. If the instruction requires no additional data, or if all data is contained within an immediate field, or within a plurality of immediate fields, execution unit 82 executes the instruction. If the instruction requires additional data not within an immediate field, either memory 80 or register file 83 must be accessed to obtain the data. If the data is located in memory 80, instruction unit 81 or execution unit 82 generates an address in memory 80 where the additional data may be found. The address is sent to memory 80 via memory address bus 85. Using the received address, memory 80 locates the data and sends the data to execution unit 82 via operand bus 87. If the data is located in register file 83, an address in register file 83 where the additional data may be found is usually embedded in an instruction on instruction bus 84. The address is sent to register file 83 via register address bus 86. Using the received address, register file 83 locates the data and sends the data to execution unit 82 via operand bus 87. As the addressable data stored in register file 83 is typically many magnitudes less than the addressable data stored in memory 80, retrieval of data from register file 83 is much faster than retrieval of data from memory 80. Furthermore, when no data needs to be retrieved, but all is resident within the instruction itself, execution time of the instruction is minimized. Therefore it is advantageous to provide for maximal length immediate values. Even in cases where retrieval of data from register file 83 takes no more time than extracting an immediate value embedded in the instruction itself, it is still advantageous to provide for maximal length immediate values since this minimizes the usage of the storage in register file 83, which is usually a scarce resource. The optimization of the register usage in register file 83 need not then include allocation for constant values, which may be contained in maximal length immediate values imbedded in the instruction itself.

Claims: A computer which is programmed to execute an instruction set (10-70) which includes at least first and second instructions (e.g. 20, 30) respectively containing first and second immediate values in respective first and second immediate fields (27, 37), the first and second instructions (20, 30) having the same number of bits and the first and second immediate fields (27, 37) having different numbers of bits, characterised in that respective first and second sign bit positions (28, 38) in or adjacent the first and second immediate fields (27, 37) occupy the same relative position in the respective instructions (20, 30) in order to facilitate decoding. A computer according to claim 1 in which the sign bit positions (28, 38) are to the right of the immediate values. A computer according to claim 1 or 2 in which the second immediate value has respective parts within non-contiguous immediate fields (57, 59) in the second instruction (50). A computer according to claim 3 in which the right immediate field 67 is non-contiguous with the sign bit position (68) in the second instruction (60). A method of operating a computer in which the computer is programmed with a plurality of instructions (10-70), at least some of the instructions (e.g. 20, 30) respectively containing first and second immediate fields (27, 37), the first and second instructions (20, 30) having the same number of bits and the first and second immediate fields (27, 37) having different numbers of bits, the method being characterised by specifying respective first and second sign bit positions (28, 38) in or adjacent the first and second immediate fields (27, 37) and occupying the same relative position in the respective instruction (20, 30) to facilitate decoding. A method according to claim 5 in which the sign bit positions (28, 38) are to the right of the immediate values. A method according to claim 5 or 6 in which the second immediate value has respective parts within non-contiguous immediate fields (57, 59) in the second instruction (50). A method according to claim 7 in which the right immediate field 67 is non-contiguous with the sign bit position (68) in the second instruction (60).

Inventors: LEE, RUBY BEI-LOH
Applicants: HEWLETT-PACKARD COMPANY
Application year: 1986
Main classification: G06F9
IPC codes: G06F9