MESFET DEVICE HAVING A SEMICONDUCTOR SURFACE BARRIER LAYER

Abstract: An InP MESFET having a semiconductor surface barrier layer (6) formed of GaInP or AlInP. The semiconductor surface barrier layer is formed between an active layer (4) and a gate electrode (8) and the barrier height of the gate for the semiconductor surface barrier layer is higher than the barrier height of the gate for InP. In a method of forming an InP MESFET according to the present invention, the semiconductor surface barrier layer is formed by high dose implantation of Ga or Al into the active region. Surface barrier layers formed of other compounds, for example GaInAsP or AlInAsP, which have a lattice match with InP can be formed by other methods such as epitaxial growth.

Description: MESFET DEVICE HAVING A SEMICONDUCTOR SURFACE BARRIER LAYER BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an indium phosphide (InP) metal semiconductor field-effect transistor (MESFET) , and more particularly, an InP MESFET including a semiconductor surface barrier layer, in which the barrier height across the interface of a gate electrode and the semiconductor surface barrier layer is higher than the barrier height across an interface of the gate electrode and InP without the semiconductor surface barrier layer. Description of the Related Art Field effect transistors formed on InP are suitable for applications in microwave systems, millimeter wave systems, high speed digital systems, and optoelectronics. These applications of field effect transistors, and these systems, could, for example, involve integrating an InP low noise or low power amplifier with photodetectors or microwave or millimeter wave sources. Field-effect transistors formed on InP devices are desirable because InP can be lattice matched to materials such as InGaAs and InGaAsP which are used as photodetectors, and because InP has a high breakdown voltage when compared to silicon (Si) or gallium arsenide (GaAs) . Furthermore, InP has a high radiation tolerance and the " electron velocity in InP is higher than the electron velocity in GaAs — two factors which make InP desirable for microwave and millimeter .wave applications. Moreover, optical fiber communication has an optimum frequency in the region of the bandgap of InGaAsP. MESFETs formed on InP, however, have produced poor results because of the low barrier height across the interface of the gate electrode and n-type InP. In particular, GaAs MESFETs having barrier heights of 0.8 - 0.9 eV have lower noise figures and higher gains than equivalent InP MESFETs with barrier heights of 0.45 - 0.55 eV, as set forth in "InP Schottky-Gate Field-Effect Transistors," by J. S. Barrera and R. J. Archer, IEEE Transactions on Electron Devices, Vol. Ed-22, No. 11, p. 1023 (1975) and "Ion-Implanted n-Channel InP Metal Semiconductor Field-Effect Transistor," by Gleason et al.. Applied Physics Letters, Vol. 32, p. 578 (1978). The low barrier height across the interface between a metal (gate electrode) and InP has resulted in the use of InP field-effect transistors having a metal-insulator-semiconductor sandwich structure (MISFET) . The insulator placed between the metal gate electrode and the InP semiconductor may be Si 3 N 4 , Si0 2 , A1 2 0 3 , or oxides of InP. MISFETs, however, have several disadvantages: (1) the DC characteristics of MISFETs tend to drift because of the low quality of the insulators, which can lead to changes in the operating point of an amplifier in high frequency applications, resulting in changes in the gain; (2) irregularities at the insulator- semiconductor interface reduce the electron velocities due to scattering, thereby preventing the device from operating at the highest predicted frequencies; and (3) MISFETs are inherently less radiation hardened than MESFETs, and therefore are less suitable for military and space applications. SUMMARY OF THE INVENTION An object of the present invention is to provide an InP MESFET having a semiconductor surface barrier layer, in which the barrier height across the interface of a gate electrode and the semiconductor surface barrier layer is higher than the barrier height across the interface of a gate electrode and InP without the semiconductor surface barrier layer. Another object of the present invention is to provide a method of fabricating an InP MESFET having a semiconductor surface barrier layer. The present invention is directed to an InP MESFET having a semiconductor surface barrier layer which provides a higher barrier height across the interface with the gate electrode than the barrier height across the interface of the gate electrode with InP. The present invention is also directed to a method of fabricating a MESFET having a GalnP or AllnP surface barrier layer by high dose ion implantation of Ga or Al. An InP MESFET according to the present invention includes an InP substrate, an active region, or layer, formed on the substrate, source and drain regions formed in the active region, and a GalnP or AllnP semiconductor surface barrier layer formed in, or over, the active region. A gate electrode is formed on the semiconductor surface barrier layer and source and drain electrodes are formed on the source and drain region, the barrier height across the gate electrode- semiconductor surface barrier layer interface being higher than the barrier height across the gate electrode-active region or gate electrode-InP interface. It is to be understood that the active region may be formed in the substrate by ion implantation or on the main surface of the substrate by epitaxial growth, and that the semiconductor surface barrier layer may be formed in or on the active regon. The InP MESFET of the present invention has signficiant advantages over conventional MESFETs in that it is capable of operating at higher frequencies than a GaAs MESFET in view of the higher electron velocities in InP than in GaAs, it is not subject to DC drift, and it is more radiation hardened. Moreover, based on the fact that GaP and A1P have barrier heights in the range of 1.5 eV, it is predicted that an InP MESFET including a semiconductor surface barrier layer of GalnP or AllnP will have a barrier height of approximately 0.8 - 0.9 eV. Thus, an InP MESFET including a surface barrier layer of GalnP or AllnP should have a lower leakage current and therefore less noise, and more gate control because of the ability to apply higher gate voltages than comparable InP MESFETs. The many advantages of the present invention will be apparent from the following description in conjunction with the accompanying drawings in which like reference numerals refer to like elements. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1, 2A and 2B are cross-sectional views showing various stages in the fabrication of a MESFET according to the present invention; Fig. 3A is a cross-sectional view of a first embodiment of a MESFET according to the present invention; and Fig. 3B is a cross-sectional view of a second embodiment of a MESFET according to the present invention. - - DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of fabricating an InP metal- semiconductor field-effect semiconductor device including a semiconductor surface barrier layer will be described with reference to Figs. 1, 2A, 2B, 3A and 3B. Fig. 1 illustrates a semi-insulating InP substrate 2 in which an n-type InP active region 4 is formed by implanting silicon (Si) . The Si is implanted at an energy of approximately 125 keV with a dose of approximately 5 x 10- 1 LΔ cm —1, to a depth of o approximately 2600A. Then, a semiconductor surface barrier layer 6 is formed in the active region 4. In the preferred embodiment, Ga or Al ions are implanted to form a GalnP or AllnP semiconductor surface barrier layer 6. The Ga or Al atoms are implanted at an energy of approximately 60 keV with a dose of 2 x 10 16 cm "2 or at 25 keV with a dose of 2 x 10 17 cm "2 , and the semiconductor surface barrier layer 6 has a thickness of approximately 600A. With reference to Figs. 2A and 2B, a gate electrode 8 is deposited through a mask formed by the well known "lift-off" technique. If the gate material is tungsten, the gate is deposited by electron beam deposition, while if the gate material is tungsten suicide, the suicide gate is deposited by sputtering. The gate 8 is then used as a mask to protect a portion of the semiconductor surface barrier layer 6, positioned thereunder during an etching process performed to remove selected portions of the semiconductor surface barrier layer 6, which are not protected by the gate 8. The etchant may comprise sulfuric acid, deionized water, and hydrogen peroxide in a ratio of approximately 100:5:1, resulting in an etching rate of approximately o lOOA/min. The etching time is elected so that the semiconductor surface barrier layer 6 and a small o amount (approximately 100-200 A) of the active region 4 are removed. Then, Si is implanted at an energy of approximately 50 keV with a dose of approximately 10 14 cm-2 to form n+-type highly doped source and drain regions 10 and 12 having a depth of o approximately 1000A. The highly doped source and j _0 drain regions 10 and 12 shown in Fig. 2A can be implanted through openings in a mask formed by a lift-off technique. Alternatively, source and drain regions 10' and 12', shown in Fig. 2B, can be formed using a self-aligned technique with the gate 8 j _5 functioning as a mask. After the source and drain regions 10 and 12, or 10' and 12', are implanted, the device is annealed at a temperature suitable for the formation of compounds of GalnP or AllnP; the range of 20 temperatures extending from 700°C to 850 β C. Capless annealing at a temperature of 850°C with an annealing time of 15 minutes and an AsH 3 or InAs overpressure is the preferred annealing technique. After the annealing process is completed 25 source and drain electrodes 14 and 16, shown in Figs. 3A and 3B, are deposited through a mask formed using a lift-off technique. Ohmiσ contact is established between the source and drain electrodes 14 and 16 and the source and drain regions 10 and 12, respectively, by low temperature annealing at a temperature between 0 370 and 450°C, for example. The source and drain electrodes 14 and 16 may be formed of, for example, an AuGe alloy. The device is completed by implanting iron (Fe) or oxygen (0~) ions to form the isolation 5 regions 18 and 20, shown in Fig. 3A. Alternatively, the device may be electrically isolated by mesa etching using a mask formed by a lift-off technique to" produce a device as shown in Fig. 3B. As previously stated, the preferred materials for the surface barrier layer 6 are GalnP and AllnP, which can be formed by high dose implanation of Ga or Al. Alternatively, the surface barrier layer 6 may be a new layer, rather than an implanted layer, formed of GalnAsP or AlInAsP, or any other compound or alloy comprising at least three elements selected from groups III and V of the Periodic Table and having a lattice match with InP, and for which the barrier height of the gate 8 is higher than the barrier height of the gate 8 for InP. The barrier height across the interface of the gate 8 and the semiconductor surface barrier layer 6 should be greater than 0.55 eV and preferably above 0.8 ev. The preferred materials for the gate 8 are tungsten and tungsten suicide; however, other gate materials such as aluminum, titanium, platinum, gold, multi-layer combinations of metals, and compounds such as AuGe and AuGeNi, are contemplated. The primary considerations in selecting a gate material are the structural strength and the conductivity of the material. The teachings of the present invention are set forth with reference to devices formed by the ion implantation of various layers. It is understood, however, that the teachings are equally applicable to any other known method of fabricating semiconductor devices, for example, the epitaxial growth of the various layers. In particular, in the method described above, the surface barrier layer 6 is formed by ion implantation and annealing; however, it is possible to form the surface barrier layer 6 by the epitaxial growth of a semiconductor layer having a lattice match with InP and a barrier height to metal which is higher than the barrier height of InP to-metal. The many features and advantages of the MESFET of the present invention will be apparent to those skilled in the art from the detailed specification. Further, since numerous modifications and changes will readily occur to those skilled in the art, the appended claims are intended to cover all suitable modifications and equivalents falling within the true spirit and scope of the invention.

Claims: WHAT IS CLAIMED IS: 1. A semiconductor device, comprising: an InP substrate; an active region on said InP substrate; a semiconductor surface barrier layer on a selected portion of said active region; and a gate electrode on said semiconductor surface barrier layer, the barrier height across an interface of said gate electrode and said semiconductor surface barrier layer being higher than the barrier height across the interface of said gate electrode and said active region. 2. A semiconductor device according to claim 1, wherein said semiconductor surface barrier layer comprises at least three elements selected from groups III and V of the Periodic Table. 3. A semiconductor device according to claim 2, wherein said semiconductor surface barrier layer comprises a compound selected from the group of GalnP and AllnP. 4. A semiconductor device according to claim 3, wherein said semiconductor surface barrier layer comprises a compound of GalnP formed by implanting Ga. 5. A semiconductor device according to claim 3, wherein said semiconductor surface barrier layer comprises a compound of AllnP formed by implanting Al. 6. A semiconductor device according to claim 2, wherein said gate electrode comprises tungsten. 7. A semiconductor device according to claim 1, wherein said semiconductor surface barrier layer comprises a compound selected from the group of GalnAsP and AlInAsP. 8. A semiconductor device according to claim 1, further comprising source and drain regions formed in selected portions of said active region. 9. A semiconductor device according to claim 8, further comprising source and drain electrodes formed on the respective source and drain regions, said source and drain electrodes being in ohmiσ contact with the respective source and drain regions. 10. A semiconductor device according to claim 1, wherein the barrier height across the interface of said gate electrode and said semiconductor surface barrier layer is greater than 0.55 eV. 11. A semiconductor device according to claim 1, wherein the barrier height across the interface of said gate electrode and said semiconductor surface barrier layer is at least 0.8 eV. 12. A semiconductor device, comprising: a semi-insulating InP substrate; an active region formed in said InP substrate; source and drain regions formed in selected portions of said active region; a semiconductor surface barrier layer formed in a selected portion of said active region, sa-id semiconductor barrier layer comprising a compound selected from the group of GalnP and AllnP; 5 a gate electrode formed on said surface barrier layer. 13. A method of fabricating a semiconductor device on a semi-insulating InP substrate, comprising the steps of: 0 (a) forming an active layer in the InP substrate; (b) forming a semiconductor surface barrier layer in the active layer; (c) forming a gate electrode on a portion 5 of the semiconductor surface barrier layer, the barrier height across the interface of the gate electrode and the semiconductor surface barrier layer being higher than the barrier height across an interface of the gate electrode and the active o region; (d) removing selected portions of the semiconductor surface barrier layer; (e) forming source and drain regions on selected portions of the surface of the active layer where the semiconductor surface barrier layer has been removed; and (f) annealing the semiconductor device at a temperature of at least 700°C. 14. A method according to claim 13, further comprising the step of forming source and drain electrodes on the respective source and drain regions. 15. A method according to claim 13, wherein: step (a) comprises implanting Si at approximately 125 keV with a dose of approximately 5 x 10 12 cm "2 ; step (b) comprises implanting an element selected from the group of Ga and Al at approximately 25 keV with a dose of 2 x 10 lδ to 2 x 10 17 cm "2 ; and step (e) comprises implanting Si at approximately 50 keV with a dose of approximately 10 14 cm "2 . 16. A method according to claim 13, further comprising the step of forming isolation regions to electrically isolate the semiconductor device. 17. A method according to claim 16, wherein said isolation region forming step comprises implanting ions of an element selected from the group of Fe and 0-. 18. A method according to claim 13, wherein step (d) comprises etching the selected portions of the semiconductor surface barrier layer using the gate electrode as a mask. 19. A method according to claim 13, wherein step (f) comprises annealing at approximately 850°C for approximately 15 minutes.

Inventors: AINA OLALEYE ADETORO, AINA, OLALEYE, ADETORO
Applicants: ALLIED CORP, ALLIED CORPORATION
Application year: 1986
Main classification: H01L29
IPC codes: H01L21, H01L29