DATA PROCESSING SYSTEM FOR PROCESSING UNITS HAVING DIFFERENT THROUGHPUTS

Abstract: In a data processing system including at least two processing units (4,5) having different throughputs for performing sequential access upon a main storage unit (1), the number of elements of the main storage unit simultaneously accessed by the processing units is different (Figs. 3 and 6), or the sequence of elements accessed by one of the processing units is reversed (Figs. 7 and 8), thereby substantially improving the input/output throughput for the main storage unit.

Description: The present invention relates to a data processing system including at least two processing units having different throughputs for a main storage unit. Recently, in an effort to provide a more rapid processing, vector computers have been developed. But even in such a computer, when carrying out an ultra-large scale scientific calculation, sometimes it is not possible for all of the data to be stored at the same time in a main storage unit, thus increasing the overhead of the input/output processing. Accordingly, to reduce this overhead, an extended storage unit is provided in addition to the main storage unit. Note that an extended storage control unit for the extended storage unit has a smaller throughput for the main storage unit than other units such as a vector unit. In a computer system having a plurality of processing units such as a vector unit, and an extended storage control unit having different throughputs for the main storage unit, when the processing units perform sequential access upon the main storage unit simultaneously, there may be a problem in that the throughput of one large-throughput processing unit, such as the vector unit, is reduced to that of another processing unit, such as the extended storage control unit having a small throughput, thereby reducing data processing efficiency. This will be later explained in more detail. It is an object of the present invention to provide a data processing system including at least two processing units having different throughputs in which the data processing efficiency is improved. The present invention is claimed in claim 1. According to an embodiment of the invention there is provided a data processing system as claimed in claim 1, said first processing unit including first address generation means arranged to generate an ascending address sequence for performing sequential access of elements of the main storage unit; said second processing unit including second address generation means arranged to generate addresses in descending order for performing sequential access of elements of the main storage unit. In systems embodying the invention, even when the processing units perform sequential access upon the main storage unit simultaneously, throughput reduction of a large-throughput processing unit can be avoided. The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein: Fig. 1 is a block circuit diagram of a computer system to which the present invention is applied; Figs. 2A and 2B are timing diagrams for explaining the known input/output access for the main storage unit; Fig. 3 is a timing diagram for explaining a principle of input/output access for the main storage unit according to the present invention; Fig. 4 is a diagram for explaining the formula (1); Fig. 5 is a diagram for explaining the formula (2); Fig. 6 is a detailed circuit diagram of the extended storage control unit, vector unit, and main storage control unit of Fig. 1 realising the principle of Fig. 3; Fig. 7 is a timing diagram for explaining another principle of input/output access for the main storage unit according to the present invention; and Fig. 8 is a detailed circuit diagram of the extended storage control unit, the vector unit, and the main storage control unit of Fig. 1 for realizing the principle of Fig. 7. In Fig. 1, which illustrates a computer system to which the present invention is applied, this system is comprised of a main storage unit (MSU) 1, a main storage control unit (MCU) 2, an extended storage unit (ESU) 3, an extended storage control unit (EMU) 4, a vector unit 5, a scalar unit 6, and a channel processor 7 to which a plurality of channels (not shown) are connected. The scalar unit 6 comprises a program status word (PSW) register, control registers, general registers, floating point registers, and the like to read and decode all instructions. As a result, if the scalar unit 6 recognizes instructions as scalar instructions, such scalar instructions are carried out in the scalar unit 6. Conversely, if the scalar unit 6 recognizes instructions as load/store instructions for extended storage unit 3, such load/store instructions including instruction codes, addresses, operands and the like are delivered to the extended storage control unit 4 which executes the load/store instructions. Further, if the scalar unit 6 recognizes instructions as vector instructions such as load/store instructions, such vector instructions including instruction codes, addresses, operands and the like are delivered to the vector unit 5 which executes the vector instructions. Note that the scalar unit 6, the vector unit 5, and the extended storage control unit 4 can operate independently from each other. That is, after the scalar unit 6 delivers instructions to the vector unit 5 and the extended storage control unit 4, the scalar unit 6 can process a next instruction. The extended storage control unit 4 comprises a load/store pipeline (not shown) which has an access throughput of one element per one cycle (τ) for the main storage unit 1, however, in this case, one access is carried out by every four elements per four cycles, thereby improving the access efficiency. The vector unit 5 comprises a load/store pipeline not shown) which has an access throughput of four elements per one cycle for main storage unit 1. Therefore, the throughput of the vector unit 5 is four times as large as that of the extended storage control unit 4. In Figs. 2A and 2B, which show the prior art access state, the ordinate designates time and the abscissa designates a logic storage number (LS) of the main storage unit 1. Also, when an access is made to a logic storage number LS, the line is extended toward the longitudinal direction by an LS busy time during which other accesses are forbidden and wait for this LS busy time even when such other accesses are requested. This LS busy time is, for example, 6τ. Further, an EMU access is carried out by the extended storage control unit 4, and a VU access is carried out by the vector unit 5. In Fig. 2A, the throughput of VU access by the vector unit 5 is not reduced since there is no competition between the EMU access and the VU access. In Fig. 2B, the VU access is delayed due to the LS busy time by the EMU access, until the LS busy time is "OFF". As a result, the access throughput of the vector unit 5 is reduced, accordingly, it is the same as that of the extended storage control unit 4. According to the present invention, the reduction of the access throughput of a processing unit, such as the vector unit 5, having a large throughput can be avoided. In Fig. 3, which shows one principle of an access state according to the present invention, wherein the EMU access is carried out for every n elements of the main storage unit 1. As a result, since the throughput of the EMU access is 4 elements/4τ, when every 4n elements are accessed, the period is n τ. Accordingly, there is a gap between each access of the 4n elements. Therefore, even when the VU access competes with the EMU access at the same logic storage LS, the VU access passes through a gap between the EMU accesses. The value n is an integer which satisfies the condition: n .τ ≧ ac / (a - b) (1) where a (elements/τ) is a throughput of a processing unit such as the vector unit 5 having a large throughput; b (elements/τ) is a throughput of a processing unit such as the extended storage control unit 4 having a small throughput; and c (τ) is an LS busy time. In other words, the ratio of number of elements simultaneously accessed by the two processing units is larger than The formula (1) (or (1)') is introduced by using Fig. 4. In Fig. 4, the angle Q must be larger than the angle P, so as to pass the stream of VU access through the gap of the busy LS's of EMU accesses. That is, if Q ≦ PP, the stream of the VU access is always prevented by the busy LS of the EMU access. For simplicity, when P' is used instead of P, since Q ≧ P' (> P), (n.τ - c)/n.τb ≧ 1/a, the formula (1) (or (1)') can be obtained. Thus, when the VU access completes with the EMU access at the same logic storage LS of the main storage unit 1, a delay time D due thereto is within D ≦ 3c + ac/nb (2) The formula (2) can be introduced by using Fig. 5. The delay time D is comprised of a delay time D A due to the busy LS of the EMU access and a delay time D B due to the busy LS of the vector unit 5. The maximum of the delay time D A is the LS busy time c, and the delay D B is determined by D B = 2c - ac/nb. Thus, the formula (2) can be obtained. When the throughput of the EMU access is 1 element/1τ, the throughput of the VU access is 4 elements/1τ, and the LS busy time is 6τ, Fig. 3 shows an access state where n = 12, and in this case, D A = 3τ and D B = 5τ, and accordingly, D = 8τ. Thus, when a plurality of processing units perform sequential accesses upon the main storage unit 1 simultaneously, the problem wherein the throughput of a processing unit having a large throughput is reduced and is the same as that of a processing unit having a small throughput, is resolved. In Fig. 6, which is a detailed circuit diagram of the extended storage control unit 4, the vector unit 5, and the main storage control unit 2 of Fig. 1 for realizing the principle of Fig. 3, the scalar unit 6 comprises registers 61 to 64 for controlling the extended storage control unit 4, and registers 65 to 68 for controlling the vector unit 5. Also, the extended storage control unit 4 comprises a control circuit 401 enabled by the valid signal from the register 61 of the scalar unit 6, an operation code (OPC) register 402, a start address (SA) register 403, a selector 404, a request address (RA) register 405, an +8n adder 406, an element number (EL) register 407, a selector 408, a subtraction register 409, a request control circuit 401, and a -n subtractor 411. Further, the vector unit 5 comprises a control circuit 501 enabled by valid signal from the register 65 of the scalar unit 6, an operation code (OPC) register 502, a start address (SA) register 503, a selector 504, a request address (RA) register 505, a +20 adder 506, an element number (EL) register 507, a selector 508, a subtraction register 509, a request control circuit 510, and a -4 subtractor 511. The main storage control unit 2 comprises a priority sequence determination circuit 201, connected to a start register 202, a queue stage (stack) 203 for storing addresses, a register 204, a queue stage (stack) 205, a register 206, a busy check circuit 207, 208, and eight registers 209 to 216 which are connected to the main storage unit 1 which, in this case, interleaves eight ways. Note that the main storage control unit 2 has the same configuration for each of the scalar unit 6 and the channel processor 7. The queue stage 203 stores sequential addresses ADD from the request address register 405 when the request control circuit 410 generates a request valid (REQ-VAL) signal. The queue stage 205 stores sequential addresses ADD from the request address register 505 when the request control circuit 510 generates a request valid (REQ-VAL) signal. The priority sequence determination circuit 201 receives operation code signals from the operation code registers 402 and 502, and checks the LS busy state by the busy check circuit 207, the bus conflict state, the other priority sequence conditions, and the like. As a result, the priority sequence determination circuit 201 determines an actual access to the main storage unit 1 based upon the priority sequence thereof, to set addresses in the registers 209 to 216. A write/read operation of the main storage unit 1 is started by a start signal from the register 202. If the start address (SA) of the EMU access is "10000" (HEX), the number (EL) of elements is 256, and the operation code is "STORE", the extended storage control unit 4 operates as follows. Note that, in this case, an address is allocated for each byte, and one element is comprised of 8 bytes. The control circuit 401 is enabled by the output of the register 61 of the scalar unit 6 which operates the registers 402, 403, and 407. That is, the "STORE" code of the register 62 is set in the operation code register 402, "10000" of the register 63 is set in the start address register 403, and "100" (HEX) of the register 64 is set in the element number register 407. In this case, since the selector 404 selects a path from the start address register 403 to the request address register 405, the content of the start address register 403 is transmitted via the selector 404 to the request address register 405. Similarly, since the selector 408 selects a path from the element number register 407 to the subtraction register 409, the content of the element number register 407 is transmitted via the selector 408 to the subtraction register 409. In this case, the request control circuit 410 generates a request valid (REQ-VAL) signal, and accordingly, the request address of the request address register 405 is set in the queue 203. Then, the control circuit 401 operates the selector 404 to switch the selector 404, so that a path from the request address register 405 via the +8n adder 406 to the request address register 405 is selected. Thus, every 8 n is added to the content of the request address register 405. Simultaneously, the control circuit 401 operates the selector 408, to switch the selector 408, so that a path from the subtraction register 409 via the -n subtractor 411 to the subtraction register 409 is selected. Thus, every n is subtracted from the content of the subtraction register 409. This operation is repeated until the content of the subtraction register 409 reaches zero. The vector unit 5 operates in the same way as the extended storage control unit 4, except for the +20 adder 506 and the -4 subtractor 511. That is, every n elements ( n is, for example, 8) are accessed by the extended storage control unit 406, while every 4 elements are accessed by the vector unit 5. Thus, the principle of Fig. 3 is realized. In Fig. 7, which shows another principle of an access state according to the present invention, when accessing sequential elements of the main storage unit 1, it is common to access them in an ascending order from a small logic storage LS to a large logic storage LS, however, in Fig. 7, the access sequence of one of the processing units is reversed, i.e., a descending order. In Fig. 7, the VU access is carried out by an ascending order of elements, but the EMU access is carried out by a descending order of elements. Thus, even when the VU access competes with the EMU access, a competition time is within the LS busy time c(τ), thereby assuring the throughput. In Fig. 8, which is also a detailed circuit diagram of the extended storage control unit 4, the vector unit 5, and the main storage control unit 2 of Fig. 1 for realizing the principle of Fig. 7, the extended storage control circuit 4 is similar to that of Fig. 6 except for a +8 adder 406' and a -1 subtractor 411'. That is, in this case, every one element is accessed in an ascending order by the extended storage unit 4. Also, the vector unit 5 is similar to that of Fig. 6 except for a -20 subtractor 506', and an end address calculation circuit 512. That is, in this case, every 4 elements are accessed in a descending order by the vector unit 5. Further, the main storage control unit 2 is entirely the same as that of Fig. 6. If the start address (SA) of the VU access is "10000" (HEX), the number (EL) of elements is 256, and the operation code is "STORE", the vector unit 5 operates as follows. The control circuit 501 is enabled by the output of the register 65 of the scalar unit 6 which operates the registers 502, 503, and 507. That is the "STORE" code of the register 66 is set in the operation code register 502, "10000" of the register 67 in the start address register 503, and "100" (HEX) of the register 68 is set in the element number register 507. In the end address calculation circuit 512, an end address "SA + EL*8" is calculated from the start address (SA) of the start address register 503 and the element number (EL) of the element number register 507. In this case, since the selector 504 selects a path from the circuit 512 to the request address register 505, the content of the end address calculation circuit register 512 is transmitted via the selector 504 to the request address register 505. Similarly, since the selector 508 selects a path from the element number register 507 to the subtraction register 509, the content of the element number register 507 is transmitted via the selector 508 to the subtraction register 509. In this case, the request control circuit 510 generates a request valid (REQ-VAL) signal, and accordingly, the request address of the request address register 505 is set in the queue stage 205. Then, the control circuit 501 operates the selector 504 to switch the selector 504, so that a path from the request address register 505 via the -20 subtractor 506' to the request address register 505 is selected. Thus, every -20 (HEX) is subtracted from the content of the request address register 505. Simultaneously, the control circuit 501 operates the selector 508 to switch the selector 508, so that a path from the subtraction register 509 via the -4 subtractor 511 to the subtraction register 509 is selected. Thus, every 4 is subtracted from the content of the subtraction register 509. This operation is repeated until the content of the subtraction register 509 reaches zero. Thus, the vector unit 5 accesses every 4 elements sequentially in a descending order. Note that, if the extended storage control unit 4 accesses every one element sequentially in a descending order, the vector unit accesses every 4 elements sequentially in an ascending order. As explained above, according to the present invention, even when simultaneous accesses from a plurality of processing units having different access throughputs are performed upon the main storage unit, the reduction of throughput of a processing unit having a large throughput can be avoided, and accordingly, the effect contributing to the improvement of data processing efficiency is very large.

Claims: A data processing system comprising a main storage unit (1); and at least first (5) and second (4) processing units connected to said main storage unit (1) for sequentially accessing the main storage unit (1), the first processing unit (5) having a throughput of a elements per cycle τ for said main storage unit, comprising means for simultaneously accessing a first definite number a of elements of the storage unit (1), and the second processing unit (4) having a throughput of b elements per cycle τ for said main storage unit, comprising means for simultaneously accessing a second definite number of elements of the main storage unit (1), the busy time of the main storage unit being c(τ), characterised in that the second definite number is made n.b, because n.b elements are accessed per cycle n.τ, so that the ratio nb / a of said second definite number to said first definite number is , whereby, if the access of the first processing unit competes with the access of the second processing unit, delay means (401,406) operatively connected to the first and the second processing units are arranged to delay successive accesses of the first definite number of elements of the main storage unit (1) by the first processing unit by a time D₁ being maximally the busy time c and to delay successive accesses of the second definitive numbers of elements by the second unit by a time D₂ being maximally 2c - ac/nb . A system as set forth in claim 1, wherein said first processing unit comprises a vector unit, and said second processing unit comprises an extended storage control unit. A data processing system as claimed in claim 1, said first processing unit (5) including first address generation means arranged to generate an ascending address sequence for performing sequential access of elements of the main storage unit (1); said second processing unit (6) including second address generation means arranged to generate addresses in descending order for performing sequential access of elements of the main storage unit (1).

Inventors: HOSHINO, AKIHIKO, ITOH, MIKIO, KURIBAYASHI, NOBUHIKO
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G06F13
IPC codes: G06F13