RETARGETABLE COMPILERS

Abstract: A retargetable compiler sorts data to be compiled into storage classes, therafter maps the sorted data into sections according to predetermined criteria, thereafter orders the data in each section by attribute into parcels and, finally, formats the data in each parcel according to a format defined for that parcel, incorporating data items into a dictionary under parcel identity, the parcels in a section being strictly ordered and processed, in data generation, other than the first, in that order. A data item can be consigned to more than one parcel. The compiler maps data items, by parcel from the dictionary, onto storage, calculating the byte offset for each data item as it is mapped, but one or more areas of storage can be prereserved so that no data item is mapped thereonto.

Description: The present invention relates to retargetable compilers. Most compilers are designed to take as input programs written in one specific language (e.g., FORTRAN, PASCAL, COBOL) and generate code for one specific target machine (e.g., IBM System 370). To generate code for a different target machine a significant portion of the compiler needed to be rewritten in order to build a compiler for the new target machine. The goal of a "retargetable" compiler is to make the building of a compiler for a new target machine a much simpler task. The primary outputs of a compiler program are program code and data. The functions within the compiler to provide these outputs are generally referred to as code generation and data generation, and it is with data generation that the present invention in primarily concerned. The following publications relate generally to retargetable compilers but focus on the code generation function of compilers rather than data generation:- "A Machine Independent Algorithm for Code Generation and Its Use in Retargetable Compilers", by R. S. Glanville, Ph.D. Dissertation, Departments of Electrical Energy and Computer Science, University of California at Berkley, December 1977, includes a detailed description of a design of a retargetable compiler which incorporates a retargetable code generator; Although the dissertation discusses many aspects of retargetable compilation, it does not deal with the function of retargetable data generation: "A New Method for Compiler Code Generation", by R. S. Glanville and S. L. Graham, Fifth ACM Symposium on Principles of Programming Languages, January 1978, at pages 231-240, also deals with the retargetable code generation function in a retargetable compiler. The paper relates generally to a table driven code generator in which the compiler may be retargeted to any number of processing systems by replacing the table; As above, although the paper relates generally to retargetable compilers, the paper does not address the problem of retargetable data generation: "Retargetable Compiler Code Generation", by Ganapathi, Fischer and Hennessy, ACM Computing Surveys, Volume 14, Number 4, December 1982, as above relates generally to the problem of retargetable code generation techniques for retargetable compilers; However, the paper does not address the problem of retargetable data generation. "Compilers are cut loose from hardware dependency", by Wolf et al, Electronics International, Volume 56, Number 24, 1st December 1983, pages 150-153, discusses a set of compilers for different languages which share the same basic code. Data is sorted into "areas" based on the storage classes. The parameters used for the formatting of data particular to individual target processors are kept separate from the common code. The following U.S. patents are cited for completeness. Although the patents relate generally to compiler programs, none of the patents cited below teaches nor suggests retargetable data generation. U.S. Patent 3,593,313 for Calculator Apparatus by Tomaszewski, et al; U.S. Patent 3,828,322 for Electronic Computers to DeSandre, et al; U.S. Patent 3,930,232 for Format Insensitive Digital Computer to Wallach, et al; U.S. Patent 4,126,897 for Request Forwarding Systems to Capowski, et al; U.S. Patent 4,342,081 for Tape Device Adapter to Dubuc; U.S. Patent 4,417,322 for Report Generation Control System for Text Processing Machines to Berry, et al; U.S. Patent 4,433,377 for Data Processing with Format Varying to Eustis, et al; U.S. Patent 4,435,758 for Method for Conditional Branch Execution in SIMD Vector Processors, to Lorie, et al; and U.S. Patent 4,437,184 for Method of Testing a Data Communication System to Cork, et al. According to the present invention, there is provided a compiler adapted to sort data into sections based on their storage classes, thereafter to order the data in each section by attribute into parcels and, finally, to format the data in each parcel according to a format defined for that parcel, whereby those parameters (storage class definitions, predetermined criteria, attributes and formats, for example) that are particular to individual target processors are separate from the basic compiler operating structure, which is common to data compilation for a plurality of target processors, facilitating retargetting of the compiler. Data items may be consigned to more than one parcel and incorporated into a dictionary under parcel identity, the parcels in a section being strictly ordered and processed, save for the first, in data generation, in that order. Data items are mapped, by parcel, from the dictionary, onto storage, the byte offset for each data item being calculated as it is mapped, one or more areas of storage being able to be reserved so that no data item is mapped thereonto. The compiler may self-generate, from a target specification input thereto, target dependent load modules, to form part of itself and select for current activation the one or more thereof appropriate to the currently selected target for which compilation is to be performed. The present invention will be described further by way of example with reference to a preferred embodiment thereof, as illustrated in the accompanying drawings, in which:- Figure 1 is a diagram showing phases of compiler program operation; Figure 2 is a block diagram of a retargetable compiler program showing the base compiler load modules and a number of target dependent load modules; Figure 3 is a flow chart diagram of the construction of a target dependent load module for the retargetable compiler; Figure 4 is a diagram of the organisation of data into sections and parcels; and Figure 5 is a block flow diagram of data generation in the compiler. In the drawings, like elements are designated with similar reference numbers, and identical elements in different specific embodiments are designated by identical reference numbers. Compiler programs and the construction thereof are well known to those skilled in the art. Normally, a compiler is designed to improve the efficiency of execution of an application program written in a specific high-level programming language. To enhance the value of application programs and make them migratable from one system to another, a compiler is required which can compile the application program into assembler code which can execute on different computing systems. A compiler according to the present invention, it is believes, can be "retargeted" to produce machine-specific code for any machine whose characteristics have been described to the compiler. The primary outputs of a compiler are code and data. The jobs to do this are generally referred to as code generation and data generation. Within data generation, some of the functions which must be performed are the ordering of data according to "storage class" (e.g., static data, automatic data, based data, etc), the selection of which items known to the compiler are actually to be generated, the form in which they are to be generated, and any desired ordering of items within the storage class. Frequently, too, it is necessary to precede and follow data within a storage class with special controls or information (e.g., assembler controls, linkage editor controls, boundary alignment information, etc.). These problems have been solved in the past mostly by "hard coding" the data generation and sequencing the code to produce the correct ordering. Many thousands of lines of code were required. Most compilers are constructed in terms of a number of "passes" over the source information, or "phases". Some simple compilers make only one pass over the source information while other, more complex ones, may take many passes. Figure 1 shows types of compiler phases. The concept of compiler phases is generally described in Aho and Ullman "Principles of Compiler Design", Addison Wesley, 1979, at page 5, section 1.3. To make the building of a compiler for a new target machine a simpler task requires rewriting the target-specific portions of the compiler so that they are table driven (by target-specific tables) or by replacing specific modules of code with target-specific modules. As a result, portions of the retargetable compiler are the same for all targets (Base Compiler Load Module - BCLM) and portions are unique to each supported target machine (Target Dependent Load Module - TDLM). When the compiler is invoked, the BCLM determines the target machine which the user is interested in and loads the appropriate TDLM. This is shown in Figure 2. The TDLM for a specific target is constructed from target machine specifications by use of a standard compiler and a generator facility as shown in Figure 3. The target machine is defined using macro statements which were designed for ease of communicating information about the target machine characteristics. These macros are compiled in the usual manner to produce code and tables. Some of the information is fed to a parser generator as described by Glanville and the resulting tables and code are used to build a TDLM load module. The specification and processing of the Datagen portion will be shown in more detail below. During the operation of the compiler, facilities are provided for the management of data. This includes data which was defined by the user via explicit and implicit source program declarations and data which is defined by the compiler during its operation, both by the BCLM and TDLM. Some of the data which is defined may need to be generated as output to the assembler following the operation of the compiler. The Dictionary is the primary repository of information about data during the operation of the compiler. It holds information about constant values, variables, procedures, entry points, program labels, and items which may be output to the assembler (e.g., size of automatic data). Data generation is driven by dictionary entries and therefore all information not generated as "code" must be generated by placing appropriate entries in the dictionary. The ?DIDCL (declare) and ?DIREDCL (modify) macros are provided to simplify dictionary entry definition and modification by BCLM and TDLM authors. To aid in the generation of data for the assembler, data is grouped logically into "Sections" and "Parcels" as shown in Figure 4. Sections are generally used to group data together which share certain storage and addressability characteristics and which are generally generated together for the assembler. The grouping of data into the appropriate storage class (and therefore section) is controlled by the explicit or default storage class assigned when the item was declared. Certain section characteristics may be defined by the TDLM author by using the ?SECTION and ?SECTEND macros (below). Parcels are a grouping and ordering of data within a section. When Data Generation puts out data for a section it puts out dictionary entries in order according to their parcel number (1 to 255). The allocation of dictionary items to parcel numbers is defined by the TDLM author using the ?PARCEL macros (below). The Parcel definition macro provides a way for the TDLM author to define the ordering of data for the assembler. The parcel value may also be used to help select the output format for the assembler. Thus the use of the parcel value is also a tool for generating unique "card image" sequences for the assembler which might be required by a particular TDLM (e.g. CSECT, DSECT, boundary alignment, special names, etc.). The parcel and section numbers can be used to precisely control the location and format of specific "card" types. The concept of parcels is used to help control the selection, ordering and formatting of data. Data can be selected for Data Generation by placing it on the appropriate storage class chain and by giving it a non-zero parcel value . Data with a parcel value of zero will not be mapped by the Data Map phase and will not be Data Gen'd when processing a chain. This is a way to "hide" data from Data Generation. The BCLM does this for certain types of items which by default do not require any data generation (e.g., local labels and entry points). The TDLM may use parcel 0 for items which are used only during the compilation, for items which define constant strings for output formats, or for items which the TDLM author will handle in a special manner (e.g., imbedded parameter lists generated by Codegen). Non-zero parcel values are useful for ordering the data in a data section (e.g., static storage). Through the ?PARCEL macros the TDLM author can specify the criteria by which dictionary entries are given parcel values (thus controlling their order of generation). Thus data items can be ordered for output (e.g., all 4 byte arithmetics, all 2 byte arithmetics, and so on). Parcel values can be assigned such that certain ones are reserved for special purposes (e.g., parcel 1 item causes generation of an @DATA DSECT "card"). It is the responsibility of the TDLM author to (1) define all the required "card images" for the assembler, (2) assign them to appropriate parcel values so they are generated in the correct position, (3) during exits enter appropriate entries in the dictionary to cause them to be generated, and (4) define the assembler format of the image (see below). The responsibility of the TDLM author for defining the sequence and location of special card images is similar to the job of generating the linkage convention instruction sequences. Data mapping is the function performed by the BCLM of ordering data according to parcel value and then computing the byte offset of each item as it is mapped onto storage. Items are mapped onto storage in such a way that the requested boundary requirements are met (i.e., "holes" are left if necessary to meet boundary requirements). Data are mapped by the Data Map phase just prior to Codegen. This is done so that instruction references to this data can be resolved to an absolute offset value. The TDLM can specify that spaces be left in storage when data is mapped. This is done in the section definitions using the black hole (?BLAKHOLE) macro. Items are mapped as usual, with spaces skipped as required by the TDLM. Data specified as parcel 0 are treated uniquely. They are ordered first relative to other parcel values by Data Map, but they are not mapped (offsets calculated) and they are not Datagen'ed when encountered while processing a chain. Various assemblers have different conventions for the formatting of data items. The locations, ordering and "spelling" of certain things can differ. Also the manner in which boundary alignment and "spacing" is accomplished can differ. The TDLM author must define the formats which can be generated and the selection criteria by which a format is chosen for a dictionary entry. This is done using the ?DATAFORM (formats) and ?ASMDATA (selection criteria) macros (below). In summary, this general and easily retargetable approach then allows: Storage classes to be generated in any desired order by mapping to specific section numbers; Control information related to a storage class can be specified on the section definition and, optionally, precede or follow the data for the storage class; Data items known to the compiler which should not be generated can be assigned to a parcel 0 which is never generated; Items can be efficiently packed within a storage class by selecting items with similar size characteristics and assigning them to the same parcel values and placing those with different characteristics in different parcel values; If the machine has instructions which can more efficiently access items in a particular part of storage, this can be controlled by appropriate assignment to parcel values; Any special control "cards" for an assembler or linkage editor "funny cards" can be generated if desired in the correct location by appropriate assignment to special parcel numbers; and Unique formatting requirements can be controlled by the assignment to particular section or parcel values. The approach described has been found to be very adaptable to a number of unique machine and assembler requirements. The retargetable compiler code to support this powerful approach is only a fraction of the size of the "hard coded" approach and the specification for a particular target machine is typically only about 100 lines of easily maintainable macro specification. The following are thought to be significant features:- Simple yet very general specification of the data capabilities of a target machine; and Provides ease of retargetability of the compiler data generation to different target machines; To specify the datagen component for the retargetable compiler the "TDLM author" must specify the following information so that the generator can generate the necessary pieces of the TDLM. You may wish to refer to the example and operation sections below to better understand the following description. Each of the macros described below is used to build a table of information, but the description of the operation may, for simplicity, describe the compiler operation with reference to the macros. The TDLM author must specify how the data within each section of storage is assigned to parcels. This is essentially an ordering of the data based upon the characteristics of the data. The ?SECTION macro defines the start of a section specification and the ?SECTEND macro designates the end. Within a section, the ?PARCEL macro is used to define the data characteristics which cause program data (dictionary entries) to be assigned a particular parcel number. During Dictionary Completion phase the compiler uses the table built from the ?PARCEL macros to assign a parcel number to each dictionary entry. The parcel specifications are searched in the order they were specified so that the specifications can be used to "sieve out" various types of data. Any data added to the dictionary in later phases is also assigned a parcel number in the same manner by the dictionary service routines. Judicious choices in the ordering of information and assignment of parcel numbers can be used to minimise the number of ?ASMDATA and ?DATAFORM macros described below. This is illustrated in the example. During the Data Map phase the dictionary is actually sorted in section and parcel number order so that data generation can put the items out in the order desired by the TDLM author. The data map phase also assigns offset values to each dictionary item. The ?BLAKHOLE macro is used by the TDLM author to specify any storage locations which are unavailable for assignment. The ?ASMDATA macros are used at data generation time to determine how each item (except parcel 0 items) from the dictionary is to be formatted. The "sieve" of ?ASMDATA macro statements selects a ?DATAFORM macro to be used to format the dictionary item. The ?DATAFORM macro specifies the action format of the item. The following provides a description of how the information provided by the TDLM author is used to construct the TDLM datagen information for the target machine and how this information is used during the operation of the retargetable compiler to generate data for the target machine. The source information from the TDLM author is compiled into tables, as shown in Figure 5, in a straightforward manner. These tables are then used by a number of phases of the compiler to construct the desired output information. The TDLM is generated once to build the TDLM (Target Dependent Load Module). Thereafter, whenever the compiler is invoked, the TDLM is loaded and linked into the base compiler load module. This provides the base compiler with the access to the target dependent tables needed to generate the data according to the TDLM author's specifications. The manner in which the data from the TDLM author's specifications is used is outlined in the section describing the TDLM macros. This section describes in precise detail the use of specific datagen macros and proves limited examples of their use in context. If the detailed use is not of interest to you this section may be skipped and used simply for reference. 'SECTION MACRO' The SECTION macro defines a section of data. NAME(<name>) This is the name of the section (e.g., STATIC, AUTOMATIC). STARTLBL(<label>) This provides a place for the TDLM author to define a default section start "label". This can be retrieved by the TDLM exits and its use and interpretation are up to the TDLM exit author. The <label> may be either a quoted char string or variable holding a character string. STARTVAL(<fx value>) This value will be used by the data mapping service as the starting value of the Data Generation offset. If none is specified, zero is used. The <fx value> may be either a constant value or variable holding a fixed value. 'SECTEND MACRO' The SECTEND macro defines the end of a section definition. All ?PARCEL macros between a ?SECTION and ?SECTEND apply to that section. 'PARCEL MACRO' The PARCEL macro specifies the criteria for placing a dictionary item into the specified parcel (given parcel value). The parcel definitions should be thought of as a series of "sieves" which select out items for a particular parcel. Thus, the order of parcel definitions is very important. Every one of the specified conditions must be met ("AND" relationship). "OR" relationships are specified by using multiple PARCEL macros. "NOT" conditions are handled by screening out the undesired relation with a prior PARCEL macro. If a definition appears to select items which are not desired, a prior definition may be required to "screen out" the unwanted items. More than one definition can specify the same parcel value. VALUE(fx value>) This is the number of the parcel by which parcels will be ordered by premap. CAV(<A# const>) The A#const values are compiler-defined constants which are used to indicate a specific datatype/precision. This keyword indicates the datatype requirements for items to be in the parcel. The A#-const can be a specific class/element (e.g., A#BIN31 - Binary Fixed 31) or an entire class (e.g., A#CHR - any character string item). If no CAV value is specified or A#NULL is specified then there are no datatype restrictions. PLACE(<fx value>) This indicates the minimum boundary to which each dictionary item in this parcel will be mapped by premap. The range is >=1 and <= 2**31 and it must be a power of two (1, 2, 4, 8 etc...). The default value is 1. Use of certain PLACE values may cause bytes to be skipped in storage. BDY(<relational>) This is used to specify a relational (EQ, LT, GT, LE, GE, NE). This keyword indicates that the dictionary item must meet the specified boundary relationship with respect to the default boundary for the datatype (e.g., if the bdy of the dictionary item is "word" (4) and the default is halfword (2) then the relationship GE (i.e., 4 GE 2) would be met but the relationship EQ (4 EQ 2) would not be. This keyword can be used to screen out items with high boundary requirements which might cause poor packing of data. BDYOFF(CONFORM) This keyword may be used only with BDY relationals EQ, GE or GT. It specifies that the bdy offset of the dictionary item must conform with the default bdy offset. For example, if the default bdy is (4,2) then the bdy.offsets which conform are (4,2), (8,2), (8,6), (16,2), (16,6), (16,10), etc. In order words the remainder of the item boundary divided by the default boundary must equal the default offset. D#const values are used to indicate any valid data attribute (e.g., STATIC, AUTOMATIC, NONLOCAL, ARRAY, STRUCTURE, etc.). ATTRS(<D# const list>) This keyword specifies a list of attributes which must be met for the item to be placed in the specified parcel. DEFAULT This specifies that the VALUE is also the DEFAULT value to be used if non of the parcel specifications are met. It can be specified on any of the specs, but can be specified only once per SECTION. 'BLAKHOLE MACRO' The BLAKHOLE macro specifies the criteria for skipping spaces in storage. It defines the areas to be skipped and how often they occur. Data items will then be mapped around these holes. 'THE ASMDATA MACRO' The ASMDATA (assembler data) macro specifies the criteria for selecting a specific data format and the arguments (if any) passed to it. DATAFORM(<name>) This is the name of the format (unquoted). It can be any unique name from 1 to 8 characters. It must match a format name in a DATAFORM macro. ARGS This defines the arguments passed to the format. PARCEL(<fx value>) The item must have the specified parcel value in order to be selected by this macro. BDY(<fx value>) The item must have the specified boundary value in order to be selected by this macro. BDYOFF(<fx value>) The item must have the specified boundary offset value in order to be selected by this macro. ATTRS(<D#value>) The item must have the specified attributes in order to be selected by this macro. CAV(<A#value>) The item must have the specified composite attribute value in order to be selected by this macro. DNAME(<dname) The item must have the specified dictionary name in order to be selected by this macro. 'THE DATAFORM MACRO' The DATAFORM (data format) macro specifies the format of data for the assemble. NAME(<name>) This is the name of the format (unquoted). It can be any unique name from 1 to 8 characters. FIELDS This defines the fields of the format. ARG or ARG(<fx value>) Keyword indicates that the content of this field is specified by an argument from the ?ASMDATA macro which caused this format to be selected. 'THE TDLM0000 STATEMENT' The TDLM0000 statement appears exactly once and must be the first statement coded in the Datagen TDLM definition. It replaces a normal PL/S PROC statement. It has the form: name This is the name of the Datagen module. It is pointed to by the NAME keyword on a LOADLIST macro which has "PHASE(DATAGEN)" coded. DATAGEN This keyword is coded to indicate that Datagen is being defined. Other TDLM modules will also use the TDLM0000 statement but with different keywords provided. LEVEL ( level characters ) The level of this expression transformation module is defined by the author of the TDLM. It is a character string of one to eight characters. 'Example' 'THE TDLM0099 STATEMENT' This is coded once. It replaces the "END;" statement which normally terminates a PL/S program. The statement has the following form:

Claims: A compiler adapted to sort data into sections based on their storage classes, thereafter to order the data in each section by attribute into parcels and, finally, to format the data in each parcel according to a format defined for that parcel, whereby those parameters (storage class definitions, predetermined criteria, attributes and formats, for example) that are particular to individual target processors are separate from the basic compiler operating structure, which is common to data compilation for a plurality of target processors, facilitating retargetting of the compiler. A compiler as claimed in claim 1, arranged to incorporate data items into a dictionary under parcel identity, the parcels in a section being strictly ordered and processed, in data generation, in that order. A compiler as claimed in claim 2, wherein the first parcel, which may be empty, in the order is not processed. A compiler as claimed in claim 3, arranged to be able to consign a data item to more than one parcel. A compiler as claimed in claim 2 or any claim appendent thereto, arranged to map data items, by parcel from the dictionary, onto storage, calculating the byte offset for each data item as it is mapped. A compiler as claimed in claim 5, wherein a facility is provided for reserving one or more areas of storage so that no data item is mapped thereonto. A compiler as claimed in any preceding claim, including a facility for self-generating, from a target specification input thereto, target dependent load modules, to form part of the compiler and to select for current activation the one or more thereof appropriate to the currently selected target for which compilation is to be performed.

Inventors: LAWLOR, FRANCIS DANIEL, SPENCE, THOMAS MILLS
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: G06F9
IPC codes: G06F9