READ ONLY MEMORY DEVICE

Abstract: A read only semiconductor memory device which comprises a plurality of transistor pairs (PQ mn , NQ mn ) comprising two transistors of one and the other conductivity types arranged in a matrix manner, thus allowing only one of the two transistors constituting each transistor pair to be operated to obtain a predetermined logical output. By employing a structure of the transmission gate type as the transistor pair, high speed and reliable operation for raising a potential on the output line can be realized.

Description: BACKGROUND OF THE INVENTION The present invention relates to a read only semiconductor memory device, and more particularly to a read only memory device used in a memory device constituting a CMOS gate array fabricated using the master slice approach. In general, gate array LSIs are used as circuitry having an intermediate character between microcomputers which obtain various functions utilizing software and custom made LSIs based on hard specification of users. Such gate array LSIs can obtain desired hardware functions by interconnecting several hundred to thousand of gate circuit blocks provided on a chip in advance on the basis of the users' specification, and they are ordinarily fabricated in accordance with the master slice approach to vary the wiring pattern between unit cells in the wiring area according to the kind of the products so as to meet users' design specification. Meanwhile, among recently available gate array LSIs, there are many ones such that gates are contiguously arranged also in wiring areas which have been provided between gate columns in the art to form a structure of the type comprising gates on the entire source, which is generally referred to as SOG (Sea of Gate), thereby improving the element density to assemble memory units as arbitrary positions. In this instance, the logic of the gates is realized by ROM (Read Only Memory) device. Fig. 1 is a circuit diagram illustrating one example of an essential part of a ROM of the OR type used in a conventional read only semiconductor memory device. As seen from this figure, source grounded n-channel transistors Q11, Q12, Q13, Q21,...., Q23, and Q31 to Q33 are arranged in a matrix manner. This ROM circuit is provided with word lines WL1, WL2, and WL3 commonly connected to gates of transistors of the same columns, respectively, and bit lines BL1, BL2 and BL3 commonly connected to drains of transistors of the same rows, respectively. To these bit lines BL1, BL2 and BL3, drains precharging p-channel transistors Q1, Q2 and Q3 are connected, respectively wherein their gates are commonly connected to a precharge circuit 1 and their sources are connected to a drain supply voltage V DD (which will be simply called "V DD " hereinafter). Their drains of these transistors Q11, Q22 and Q33 are 10 separated from the bit lines BL1, BL2 and BL3, respectively. In this circuit, first is to activate the precharge circuit 1 by a clock signal to place each bit line in high (H) level. In this condition, when a word line selection is made, a transistor connected to the bit line is turned on, with the result that the concerned bit line is pulled down to low (L) level. However, such a pulldown does not occur in the transistor in which the drain and the bit line are separated from each other. As a result, a memory output appears on the bit line. Accordingly, this circuit can be said as the circuit of synchronous type, giving rise to the problem in use that it is required to precisely adjust the clock for precharge and the timing of an input address signal for selection of the word line. Fig. 2 is a circuit diagram illustrating a conventional ROM circuit of the ratio type configured so that bit lines are always respectively pulled up by resistors R1, R2 and R3 instead of the precharge circuit and the p-channel transistors shown in Fig. 1. This circuit is of the asynchronous type because the bit lines are always pulled up independent of the selection of the word lines, resulting in no problem in the timing. However, this circuit has the shortcoming that a large d.c. current flows every time the address changes, resulting in large power dissipation. Fig. 3 is a circuit diagram illustrating a further conventional ROM circuit used in the gate array in the prior art. This circuit is characterized in that the transistors Q11, Q22 and Q33 for producing a predetermined output are arranged so that their sources are connected to V DD instead of separation between the drains and the bit lines as in the prior art, thus providing a ROM of the asynchronous type and having a low power dissipation. Because an output is small in this circuit, there is employed a circuit arrangement to pass each output through a p-channel transistor having a source connected to V DD and a compensation (sense-up) circuit comprising two stages of inverters, thereby allowing a slow rising of the potential on the bit line after selection of the word line to be changed into a quick and steep rising on the output line as shown in Fig. 4. However, with such a compensation circuit, when the threshold voltage V TH of the n-channel transistor shifts to an upper voltage and that of the p-Channel transistor shifts to a lower voltage due to the variation at the time of fabrication, the circuit threshold voltage V TH of the inverter becomes high. Accordingly, in the event that the H level on the bit line pulled up by the n-channel transistor of which source is connected to V DD by the selection of the word line is lowered by the circuit V TH of the inverter, there is a possibility that this circuit does not normally operate. Namely, the drawback with this circuit is that the range of the threshold voltage V TH is limited, resulting in small margin in the production and poor mass-productivity. In addition, since the memory elements are constituted using only n-channel transistors in the above-mentioned three ROM circuits, the drawback with these circuits is that the p-channel transistor is not used in the CMOS gate array, resulting in low element utilization factor. US-A-3 55 00 89 describes a complementary semiconductor matrix array in which pairs of complementary transistors form memory cells. The cell transistors are controlled by transistors of the same conductivity type whose gates are connected to complementary word lines and whose drains are connected to row lines. The row lines of the matrix connect the sources of the memory cell transistors together and the column lines connect the drains of the memory cell transistors together. The word lines are not connected directly to the gates of the memory cell transistors. EP-A-0 16 99 80 (= and FR-A-2 563 651) is a non-prepublished European application according to Art. 5413 which describes a ROM comprising complementary transistor pairs whereby complementary word lines are connected to the respective gates of the complementary transistors and bit lines are connected to the junction points of the drains. Connections between the sources of the transistors of each transistor pair are provided. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor ROM device of the asynchronous type having low power dissipation. Another object of the present invention is to provide a semiconductor ROM device having excellent mass-productivity. A further object of the present invention is to provide a semiconductor ROM device having high element utilization factor. A still further object of the present invention is to provide a semiconductor ROM device which securely operates at a high speed. The object of the invention is solved by a read only semiconductor memory device comprising: a plurality of transistor pairs arranged in a matrix manner, each transistor pair being comprised of a first transistor of one conductivity type and a second transistor of opposite conductivity type and said transistor pairs being arranged such that all first transistors are arranged in first columns and all second transistors are arranged in second columns, input lines for providing one logic state to the gates of the transistors of the first columns, complementary input lines for providing the opposite logic state to the gates of the transistors of the second columns, and output lines for connecting drains of said transistor pairs of the same rows, either one of said first and second transistors being connected to a predetermined logic state to output said predetermined logic state when this transistor is active. The object of the invention is also solved by a read only semiconductor memory device comprising: a plurality of transistor pairs arranged in a matrix manner, each transistor pair being comprised of a first transistor of one conductivity type and a second transistor of opposite conductivity type and said transistor pairs being arranged such that all first transistors are arranged in first columns and all second transistors are arranged in second columns, input lines for providing the one logic state to the gates of the transistors of the first columns, complementary input lines for providing the opposite logic state to the gates of the transistors of the second columns, and output lines for connecting drains of said transistor pairs of the same rows, wherein the transistors of a transistor pair for outputting high level logic state have common source connections and common drain connections, said common source connections being connected to one level voltage supply, and said common drain connections being connected to another level voltage supply, respectively, on said output lines, and wherein the transistors of a transistor pair for outputting low level logic state have connections such that the transistor of said opposite conductivity type pulls down the potential on said output line, when this transistor is active. Thus, there is provided a read only semiconductor memory device of the asynchronous type, and having low power dissipation and excellent area occupation ratio. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: Fig. 1 is a circuit diagram illustrating a conventional ROM device of the synchronous type; Fig. 2 is a circuit diagram illustrating a conventional ROM device of the ratio type; Fig. 3 is a circuit diagram illustrating a conventional ROM device having compensation circuitry; Fig. 4 is a graph showing a transient characteristic in the circuit shown in Fig. 3; Figs. 5 through 8 are circuit diagrams illustrating embodiments of ROM devices according to the present invention, respectively; Fig. 9A is a plan view showing a configuration of arranged transistors which are shown in Fig. 9B realized on a master chip; Fig. 9B is a circuit diagram showing a matrix arrangement having four rows and one column of the circuit shown in Fig. 8; Fig. 10 is a circuit diagram illustrating a ROM wherein each transistor pair is configured as a transmission gate; Fig. 11 is a circuit diagram illustrating an embodiment of the present invention configured as a modification of the circuit shown in Fig. 10; Fig. 12A is a configuration of arranged transistors which are shown in Fig. 12B realized on a master chip; and Fig. 12B is a circuit diagram showing a matrix arrangement having two rows and two columns of the circuit shown in Fig. 10. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 5 is a circuit diagram illustrating an embodiment of a read only semiconductor device according to the present invention. In a gate array of the master slice type n-channel transistor columns and p-channel transistor columns are arranged alternately on a master chip, ROMs of the OR type are formed. In accordance with this circuit, each transistor pair comprises n-channel and p-channel transistors commonly connected at their drains. A point at which the drains are commonly connected is connected to a bit line BL. Each gate of the n-channel transistors of the same column (first column) is connected to a word line of logic W1 and each gate of the p-channel transistors thereof is connected to a word line of the negative logic W1 . This negative logic W1 is obtained by branching the word line WL of the logic W1 through an inverter. In the transistor pairs giving the meaning of logical "1" in each column, for instance as shown in the first row and the first column, the source of an n-channel transistor NQ11 is in an open state and the source of a p-channel transistor PQ11 is connected to V DD . In contrast, in the transistor pairs giving the meaning of logical "0", for instance as shown in the second row and the first column, and the third row and the first column, sources of n-channel transistors NQ21 and NQ31 are connected to a source power supply voltage V SS (which will be simply called "V SS " hereinafter), and sources of p-channel transistors PQ21 and PQ31 are in an open state. In this circuit, when a word line WL1 is selected and the logic W1 = 1 is input, the n-channel transistors NQ21 and NQ31 are turned on, thus pulling bit lines BL2 and BL3 down to the ground level. At this time, since the p-channel transistor PQ11 which is turned on when the logic W1 is 0, raises the bit line BL1 to the V DD level, data indicative of logical "1", "0" and "0" are output on the bit lines BL1, BL2 and BL3, respectively. Fig. 6 is a circuit diagram illustrating a modification of the circuit shown in Fig. 5 wherein transistors of which sources have been placed in an open state, e.g., NQ11, PQ21 and PQ31, etc. are open also at their gates, respectively. This modification has a circuit arrangement such that the word lines are connected only to gates of transistors contributing to the formation of output data. Accordingly, this lessens the load on word lines, thus making it possible to accelerate the word line selective operation. Fig. 7 is a circuit diagram illustrating another embodiment of a ROM device according to the present invention. This circuit is configured so that the sources of the n-channel transistor and the p-channel transistor of each transistor pair are connected to V SS and V DD , respectively, and the drain of a transistor paired with each transistor producing a specified output is in an open state. For instance, when an attention is drawn to the first column, the drain of the n-channel transistor NQ11 paired with the p-channel transistor PQ11 of the transistor pair giving the meaning of logical "1" and the drains of the p-channel transistors PQ21 and PQ31 paired with the respective n-channel transistors NQ21 and NQ31 are in an open state. There exists drain capacity in the connection between the bit line and the transistor. Since this drain capacity affects readout speed, it is preferable that the drain is in an open state. In this instance, as shown in Fig. 8, the gate of each transistor of which drain is in an open state may be opened, thus reducing the load on word lines. Fig. 9A is an enlarged plan view illustrating a matrix arrangement shown in Fig. 9B which shows a portion of a ROM circuit having the same configuration as that shown in Fig. 8 realized on a master chip. N-channel transistors NQ11 and NQ12 are comprised of opposing gate electrodes 11 and 12 and n-type impurity diffusion regions 13 intersecting therewith. N-channel transistors NQ13 and NQ14 are comprised of opposing gate electrodes 14 and 15 and n-type impurity diffusion regions 16 intersecting therewith. P-channel transistors PQ11 and PQ12 are comprised of opposing gate electrodes 17 and 18 and p-type impurity diffusion regions 19. In addition, p-channel transistors PQ13 and PQ14 are comprised of opposing gate electrodes 20 and 21 and p-type impurity diffusion regions 22 intersecting therewith. Further, on the n-channel transistor column, a V SS line 23 and a W1 word line 24 are formed. On the p-channel transistor column, a V DD line 26 and a W1 word line 25 are formed. In addition, bit lines 27 (BL1), 28 (BL2), 29 (BL3) and 30 (BL4) are arranged in a lateral direction so that they pass on source regions of the n-channel and p-channel transistors. These wirings and each region are connected through contact holes, whereas no contact hole is provided in each opened portion. Fig. 10 is a circuit diagram illustrating a ROM device. In each transistor pair, respective sources and drains are commonly connected to constitute a transmission gate. A point at which drains of each transistor pair are commonly connected is connected to each bit line. For allowing the transistor pair to memorize logical "1", a point at which their sources are commonly connected is connected to V DD . For allowing the transistor pair to memorize logical "0", the source common junction is connected to V SS . Namely, when an attention is drawn to the first column in Fig. 10, the source common junction is connected to V DD in the transistor pair NQ11 and PQ11 giving the meaning of logical "1", and the source common junctions are connected to V SS in the transistor pairs NQ21 and PQ21, and NQ31 and PQ31 giving the meaning of logical "0". Such a transmission gate can perfectly perform level transmission, with the result that it is effective when raising the bit line to H level and is advantageous in the realization of bidirectional transmission. Fig. 11 shows an embodiment t of the present invention configured as a modification of Fig. 10. In this circuit, the transmission gate is used in each transistor pair used for raising a potential on the bit line, but only the n-channel transistor is used as each transistor used for pulling down a potential on the bit line. For instance, when an attention is drawn to the first column, for giving the meaning of logical "0", sources of the n-channel transistors NQ21 and NQ31 are connected to V SS , but drains of the p-channel transistors PQ21 and PQ31 are in an open state, with the result that they do not contribute to pull-down of the potential. In this embodiment, it is also possible to place the gate of each p-channel transistor which does not contribute to an output of data indicative of logical "0" in an open state, thus reducing the load on word lines. Fig. 12A is an enlarged plan view illustrating a matrix arrangement shown in Fig. 12B which shows a portion of the circuit shown in Fig. 10 realized on an actual master chip. In accordance with this configuration, since the same master chip as in Fig. 9 is used, four n-channel transistors formed by the gates 11, 12, 14 and 15 and n-type impurity diffusion regions 13 and 16 positioned at the left-half and four p-channel transistors formed by gates 17, 18, 20 and 21 and p-type impurity diffusion regions 19 and 22 positioned at the right-half are the same as those in Fig. 9. On this master chip, a word line (W1) 31, a V SS line 32, a word line (W2) 33, a word line ( W1 ) 34, a V DD line 35 and a word line ( W2 ) 36 are arranged as diffferent layers in a vertical direction, respectively. Moreover, bit lines 37 (BL1) and 38 (BL2) are formed thereon as different layers in a lateral direction, respectively. By providing suitable contacts on this chip, the circuit shown in Fig. 10 is thus realized. In the above-mentioned embodiments, ROMs of the OR type have been described. However, it is needless to say that the present invention is applicable to well known ROMs of the AND type. Although ROMs for realizing logic for gate array have been described in the above-mentioned embodiments, the present invention can be applied to ROMs as memory devices assembled into the gate array or ordinary ROMs. As described in detail, the ROM device according to the present invention is configured so that a plurality of transistor pairs each comprising a transistor of one conductivity type and a transistor of an opposite conductivity type are formed in a matrix manner, and that the transistors of the one conductivity type output one memory logic and the transistors of the other conductivity type output the other memory logic. Accordingly, the ROM device effects static operation, thus eliminating the need of the precharge and the clock operations. This ROM is essentially configured as a CMOS circuit, resulting in low power consumption. Further, there are used transistors having respective characteristics suitable for raising and pulling down a potential on the output line, leading to large operation margin. Accordingly, this results in a large production margin an improved yield. Furthermore, since p-channel and n-channel transistors which are the same in number are used, element utilization factor is high and a ROM having large capacity and small occupation area can be configured, thus providing an inexpensive and high performance read only semiconductor device.

Claims: A read only semiconductor memory device comprising: a plurality of transistor pairs (NQmn, PQmn; m,n = 1,2,....) arranged in a matrix manner, each transistor pair being comprised of a first transistor of one conductivity type and a second transistor of opposite conductivity type and said transistor pairs being arranged such that all first transistors are arranged in first columns and all second transistors are arranged in second columns, input lines (WL1, WL2, ....) for providing one logic state to the gates of the transistors of the first columns, complementary input lines ( WL1 , WL2 , ....) for providing the opposite logic state to the gates of the transistors of the second columns, and output lines (BL1, BL2, ....) for connecting drains of said transistor pairs (NQmn, PQmn) of the same rows, either one of said first and second transistors being connected to a predetermined logic state to output said predetermined logic state when this transistor is active. A read only semiconductor memory device as set forth in claim 1, wherein said one logic state represents high level logic and said the other logic state represents low level logic, said first transistor (PQmn) of said one conductivity type being operated so as to raise a potential on said output line to high level, said second transistor (NQmn) of said the other conductivity type being operated so as to pull down a potential on said output line (BL1,BL2,....) to low level. A read only semiconductor memory device as set forth in claim 2, wherein said first transistor (PQmn) of said one conductivity type is a p-channel transistor and said second transistor (NQmn) of said opposite conductivity type is an n-channel transistor. A read only semiconductor memory device as set forth in claim 3, wherein said memory device is configured as a CMOS master chip on which said p-channel and n-channel transistors (PQmn;NQmn) are regularly arranged. A read only semiconductor memory device as set forth in claim 4, wherein each of said input lines (WL1,WL2....) is a word line, and each of said output lines (BL1,BL2. ...) is a bit line. A read only semiconductor memory device as set forth in claim 5, wherein a transistor pair (NQmn,PQmn) for outputting high level logic has a p-channel transistor (PQmn) with its source connected to a drain supply voltage (Vdd), a gate connected to said word line (WL1,WL2. ...) and a drain connected to said bit line (BL1,BL2. . ..) and a transistor pair (NQmn,PQmn) for outputting low level logic has an n-channel transistor (NQmn) with its source connected to a source supply voltage (Vss), a gate connected to a word line ( WL1 , WL2 ,....) of an opposite logic to said word line and a drain connected to said bit line (BL1,BL2....). A read only semiconductor memory device as set forth in claim 6, wherein p-channel transistor (PQmn) and n-channel transistor (NQmn) of a transistor pair have a common drain connection to said bit line (BL1,BL2....). A read only semiconductor memory device as set forth in claim 6, wherein the transistor which does not produce a logic output of said transistor pairs (NQmn,PQmn) has a connection relationship such that at least one of its source and drain is not connected. A read only semiconductor memory device as set forth in claim 8, wherein the gate of said transistor (NQmn,PQmn) which does not produce a logical output is not connected to said word line (WL1,WL2,....). A read only semiconductor memory device as set forth in claim 1, wherein each of said transistor pairs (NQmn,PQmn) is representative of a unit logical output of a gate array. A read only semiconductor memory device as set forth in claim 1, wherein each of said transistor pairs (NQmn,PQmn) is representative of a unit logical output of a read only semiconductor memory unit. A read only semiconductor memory device comprising: a plurality of transistor pairs (NQmn,PQmn; m,n = 1,2,....) arranged in a matrix manner, each transistor pair being comprised of a first transistor of one conductivity type and a second transistor of opposite conductivity type and said transistor pairs (NQmn,PQmn) being arranged such that all first transistors are arranged in first columns and all second transistors are arranged in second columns, input lines (WL1, WL2, ....) for providing the one logic state to the gates of the transistors of the first columns, complementary input lines (WL1, WL2, ....) for providing the opposite logic state to the gates of the transistors of the second columns, and output lines (BL1, BL2 ) for connecting drains of said transistor pairs (NQmn, PQmn) of the same rows, wherein the transistors of a transistor pair (NQ11,PQ11, Fig.11) for outputting high level logic state have common source connections and common drain connections, said common source connections being connected to one level voltage supply (Vdd,Vss), and said common drain connections being connected to another level voltage supply (Vss,Vdd), respectively, on said output lines, and wherein the transistors of a transistor pair for outputting low level logic state have connections such that the transistor of said opposite conductivity type (NQ12,Fig.11) pulls down the potential on said output line (BL1, BL2, ....), when this transistor (NQ12) is active. A read only semiconductor memory device as set forth in claim 12, wherein said one level and the other level voltage applies represent drain and source power supply voltages (Vdd,Vss) respectively, said one logic and the other logic represent high level logic state and low level logic state, respectively, said transistor of said one conductivity type being a p-channel transistor (PQmn), said transistor of said the other conductivity type being an n-channel transistor (NQmn). A read only semiconductor memory device as set forth in claim 13, wherein said memory device is configured as a CMOS master chip on which p-channel and n-channel transistors (PQmn, NQmn) are regularly arranged. A read only semiconductor memory device as set forth in claim 14, wherein said complementary input lines ( W11 , W12 ....) are word lines logically opposite to the input lines (W11,W12,....) and commonly connected to gates of transistors of the same conductivity type of said transistor pairs (NQmn,PQmn), said output line (BL1, BL2, ....) is a bit line connected to a drain common junction of the transistor pairs (NQmn,PQmn) of the same row.

Inventors: SUZUKI, HIROAKI, UCHINO, YUKINORI 210, TOSHIBA SHINKOYASU
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: G11C17
IPC codes: H01L21, H01L27, G11C17