GATE MODULATED TRANSIMPEDANCE AMPLIFIER WITH BUFFERING FOR FOCAL PLANE ARRAY

Abstract: An improved circuit for coupling the output of a photodetector in a focal plane array to a charge coupled device. The improvement comprises amplifier means coupled between the gate of the photodetector output and an output FET for lowering the overall circuit impedance, for reducing the effect of photodetector and FET nonuniformities on the output current and for reducing the size of resistive circuit components. The amplifier may use a cascade of gate modulated FETs, at least one of which is source coupled to the photodetector output, to enhance circuit performance. The amplifiers' gain and impedance may be selectively varied by adjusting a single bias voltage.

Description: GATE MODULATED TRANSIMPEDANCE AMPLIFIER WITH BUFFERING FOR FOCAL PLANE ARRAY BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to electronic circuits and, in particular, to a circuit which will provide improved coupling of a low impedance infrared photodetector to a readout multiplexer (charge coupled device or direct readout) . 2. Description of Related Art As is generally known, the input circuit associated with a photodiode array has to overcome several problems. It is known that the input circuit impedance must be relatively low compared to the photodetector impedance (RoA product) and that the charge to be accumulated must not be so large as to overload the charge coupled device (CCD) . See e.g., U.S. Patents 4,173,723 and 4,316,103. Circuits utilizing FETs (Field effect transistors) must overcome problems caused by threshold voltages and nonuniformities associated with the use of FETs. Circuit size and configuration must be conducive to MOS fabrication. More specifically, problems arise in the spectral bands of tactical interest, i.e., the 3-5 micron and the 8-10 micron range when detector integration demands are relatively high, where the background photon flux is high, or when both scanning and staring applications must be accomplished. Furthermore, for low impedance detectors, the variation of threshold voltages across the circuit FETs causes a "DC offset" voltage across the photo¬ detector. Although the offset may be eliminated, for example, by storing the value across a capacitor, circuit complexity increases and, hence, maximum circuit density achievable for MOSFET fabrication is reduced. Prior art circuits have also attemped to negate the DC offset problem by operating the photodetector in the saturation (back bias) region; however, this approach causes large saturation and surface leakage currents which must be handled or reduced by the input circuit. In addition, detector dark currents change with the offset voltage, causing nonlinearities in the detector response and nonuniformities between detectors in an array. Further, gain variations between circuit FETs further frustrate circuit performance. In attempting to resolve the aforementioned problems, prior art circuits have utilized resistive elements and other components to drain off much of the DC component of photocurrent from the input circuit (DC suppression) and to attenuate the source/drain current of the output FET. Both approaches have increased input circuit impedance relative to low RoA product photodetectors. Another problem encountered by some such circuits is their failure to incorporate a gain loss mechanism in response to changing photocurrent levels, as might be experienced in scanning versus staring applications. It is therefore desirable to provide a circuit for reducing charge storage requirements resulting from dynamic detector applications while, at the same time, keeping the input circuit impedance low relative to low impedance photodetectors. It is further desirable to provide a circuit that will reduce the effect of photodetector and FET nonuniformities on the circuit output current. It is further desirable to provide such a circuit having a simple means for varying circuit gain and impedance. SUMMARY OF THE INVENTION Briefly described, the invention is an improved FET input circuit for coupling a photodetector in an array to a charge coupled device, the improvement comprising amplifier means connected between the photodetector output and the output FET gate for varying the circuit impedance. The amplifier means is operative to reduce the effect of photodetector and FET nonuniformities on the circuit output current. The amplifier may comprise a cascade of gate modulated FET amplifiers or may be feedback coupled to the photodetector output to further reduce the effect of FET and detector nonuniformities. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 a is schematic of a prior art circuit for coupling a photodetector in a focal plane array to a CCD. FIG. 2 shows a simple block diagram of the invention, an improvement to the FIG. 1 circuit. FIG. 3 shows a one stage embodiment of the invention. FIG. 4 shows an N-stage, cas-cade embodiment of the invention. FIG. 5 shows the preferred embodiment a 2 stage, gate modulated, bufferred transimpedance amplifier circuit. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, for a prior art circuit, radiant energy 6 is shown entering detector 10 which is coupled on one side to bias 1. Radiant energy 6 may for example be infrared radiation and detector 10 may for example be a PV HgCdTe detector, or similar low impedance detector. Detector 10 is one of a plurality of such detectors used in a focal plane array, the output of which is to be used as an input to a charge coupled device (CCD), direct readout multiplexer (dro), or similar device. The output signal from detector 10 is coupled to terminal 15 of the input circuit. Terminal 15 is coupled over one path to one end of a load resistor 22. Load resistor 22, like the other resistors of the circuits, is a polysilicon resistor and ranges from 10^-10^ ohms. The other end of load resistor 22 is coupled to a voltage bias 21. The function of the load resistor 22 and bias 21 is to provide DC suppression of the photodetector output (as discussed hereafter). Terminal 15 is coupled over another path to the gate 53 of FET 50. FET 50, and the other FETs discussed hereafter, may be for example p-channel or n-channel FETs. Source 52 of FET 50 is coupled to one end of attenuation resistor 42. The other end of attenuation resistor 42 may be coupled to voltage bias 41 or feedback coupled to terminal 15. The drain of FET 50 is coupled to the input of the CCD. In operation, the input circuit of FIG. 1 behaves as follows. Radiant energy 6 is received at photo detector 10 and coupled to terminal 15. Adjusting the input circuit biases causes detector RoA product currents, leakage currents, and part of the photodetector pedestal current to flow through the load resistor 22. By directing the DC current components through the resistor and off chip, the charge storage requirements for the input circuit are reduced. A source to drain current flows in FET 50 as a result of the bias 41 applied through resistor 42 which is coupled to source 52 of FET 50. The resistor values and bias voltages are chosen so that the range of output current is within the current handling capabilities of the CCD. The output current from virtual drain 54 changes in response to changes in the voltage at gate 53, which itself is a function of the changing DC suppressed photocurrent. In FIG. 1, the voltage across photodetector 10 is the sole means of modulating the input CCD current via the FET gate 53 and no independent means for affecting the modulation at gate 53 is included in the circuit. For low impedance photodetectors, another of the limitations of the implementation in FIG. 1 is that variations in the bias level of node 15 caused by changing photocurrent and variations in load resistor value from cell to cell causes an equivalent detector bias change. Referring to FIG. 2, a simple block diagram of an embodiment of the invention is shown. Radiant energy 6 strikes photodetector 10 which is coupled on one side to bias 1 and on another side to terminal 15. The photo¬ detector output signal flows to terminal 15 which is coupled over one path to one end of load resistor 22. Load resistor 22 is coupled at its other end to bias 21. Terminal 15 is coupled over another path to an input 32 of amplifier means 30. Amplifier means 30 is also coupled from terminal 33 thereon to a bias 31, and from an output 34 to gate 53 of the output FET 50. The source 52 of output FET 50 is coupled to a first end of attenuation resistor 42 which is coupled on a second end to bias 41. In an alternate variation of the invention, the second end of resistor 42 (R-χ) is feedback coupled to the photodetector output through terminal 15 rather than to bias 41. The drain 54 of FET 50 is coupled to the input of the CCD. Referring to FIG. 3, a schematic of a typical embodiment of the invention of FIG. 2 is shown. In FIG. 3, radiant energy 6 strikes photodetector 10 which is coupled on one side to bias 1 and on the other to terminal 15. Terminal 15 is coupled over one path to a first end of load resistor 22. A second end of load resistor 22 is coupled to bias 21. Terminal 15 is connected over another path to gate 32 of FET 30. The source 33 of FET 30 is coupled to bias 31 and the drain 34 of FET 30 is coupled to terminal 35. Terminal 35 is coupled over one path to a " first end of resistor 92. Resistor 92 is coupled on a second end to bias 91. Terminal 35 is coupled over another path to gate 53 of FET 50. The source 52 of FET 50 is coupled to a first end of attenuation resistor 42. Resistor 42 (R^) is coupled from a second end to bias 41. In another variation of the invention, resistor ' 42 is feedback coupled (buffered) from the second end to the photo¬ detector output via terminal 25, terminal 25 being coupled to or identical with terminal 15 according to design and convenience. The drain 54 of FET 50 is coupled to the input of the CCD. In operation the general embodiment of FIG. 2 as set forth in the particular circuit of FIG. 3, behaves as follows. As with the prior art circuit of FIG. 1, the photodetector is DC suppressed via load resistor ( L)22 in combination with bias 21. DC portions of the photo¬ current (Ip) are carried off chip by resistor 22. As the current Ip passes through the load resistor 22 (R L ), it establishes a voltage difference with respect to bias 21 (IpR^ , ), which causes the voltage at terminal 15 to change. Since terminal 15 is coupled directly to the gate 32 of FET 30, voltage changes at terminal 15 control the source to drain current flow through FET 30 (l£ , ). Thus, the voltage at terminal 35, which is at potential R^ II with respect to bias 91 for resistor 92 (R^) changes. Since terminal 35 is connected to the gate 53 of output FET 50, voltage charges at terminal 35 caused by photocurrent variations control the current flowing from the output FET drain to the CCD. The current input into the CCD is therefore a function of the potential difference between the bias 41 (VF) and the voltage at the gate of FET 50. The equation which relates changes in photocurrent, ΔIp, to changes in CCD current is: ΔlCCD = gmo Rp α Alp 1 + gmo RFe where gmo = transconductance of output FET Rp = attenuation resistor α = gain of amplifier = g a R-p By incorporating the gate modulated TIA in the input circuit, the input gm can be increased, offsetting the impedance of and Rp. Thus, R can be reduced while the input circuit gain, RL /R L + F is maintained. Since RL is reduced, this circuit will operate with lower RoA product detectors. Moreover, the linearity is enhanced since for a given change in photocurrent, the change in detector bias voltage is reduced by the lower value of RL used. For example, if the circuit is designed for a maximum voltage swing of 100 mv, incorporation of the amplifier with a gain of 30 will reduce this to 3.3 mv provided the load resistor value is reduced by the amount of gain. It can be seen that reduction of the load resistor 22 value due to use of the amplifier gives two beneficial effects: it reduces the bias swing across the detector previously discussed, and it permits operation with lower RoA product detectors. In addition, use of the amplifier along with the attenuation resistor Rp 42 enhances the circuits' ability to withstand DC offset voltage variations arising from the output FET. Because of the amplifier gain, the photo¬ detector can be operated at zero bias as well as in the back bias regions. In the embodiment of FIG. 1, - the input circuit gain is determined in part by the value of the load resistor. Since, for uniform operation, this is usually selected to be less than the dynamic resistance of the detector, the maximum gain achievable is limited by the photodetector impedance. In order to increase the gain the detector can be operated at higher dynamic resistance in the saturation region with some penalty in increased nonuniformity. With the embodiment of FIG. 3, the detector can be operated at the more uniform zero bias point, with lower load resistor value and can simultaneously achieve sufficient gain by virtue of the amplifier gain. Circuit performance can therefore be improved by trading nonuniformities at zero bias (thres- hold FET, etc) variations against those in the reverse bias region (detector nonuniformities). Data to date indicate that detectors are more uniform at zero bias. For p-channel FETs, threshold variations are less than those for n-channel so that zero bias operation is more feasible for p-channel FETs. It can be seen that the input circuit and amplifier gain and impedance of the amplifier can be adjusted by varying the bias 31. To a lesser extent the gain and impedance can be affected by varying bias 91. Desired output current characteristics beyond those obtainable by the prior current of FIG. 1 can be obtained by selective combinations of the resistors and the additional biases, 31 and 91. In an alternate embodiment of the invention shown in FIG. 3, the second end of attenuation resistor 42 is not connected to bias 41 but is feedback coupled to terminal 25. This feedback configuration (buffering) further reduces the effect of nonlinearities in the detector, nonuniformities between detectors in an array of detectors, and nonuniformities between circuit FETs. For example, if the amplifier has a gain A, the effective transconductance becomes gm/(l+A) and the input resistance is reduced by the same factor. As a result, the detector bias voltage swings are reduced by a factor of (1+A) and hence the effect of photodetector nonlinearities are reduced. Thus, by use of this method, only changes resulting from photocurrent changes are transmitted, eliminating nonuniformities due to detector changes with the photocurrent. Referring now to FIG. 4, there is shown a cascaded emodiment of the invention. In FIG. 4, radiant energy 6 strikes photodetector 10 which is coupled on one side to bias land on its output side to terminal 15. Terminal 15 is coupled over one path to a first end of resistor 22. Resistor 22 is coupled on a second end to bias 21. Terminal 15 is coupled over another path to amplifier means 60. Amplifier means 60 is coupled to amplifier 70 which is coupled through intermediate amplifiers to N-l amplifier 80, which is coupled to N th a plifer 90. N tn amplifier 90 is coupled to the gate 53 of output FET 50. The source of output FET 50 is coupled to a first end of resistor 42. A second end of resistor 42 is coupled to bias 41. The drain 54 of output FET 50 is coupled to the input of the CCD or DRO. Referring to FIG. 5, a schematic for a simple 2 stage buffered, gate modulated transimpedance amplifier is shown. In FIG. 5, radiant energy 6 strikes photo¬ detector 10 which is coupled on one side to bias 1 and on the other side to terminal 15. Terminal 15 is coupled over one path to a first end of load resistor 22. A second end of load resistor 22 is coupled to bias 21. Terminal 15 is coupled over another path to gate 63 of FET 60. The source 62 at FET 60 is coupled to bias 61 and the drain 64 of FET 60 is coupled to terminal 65. Terminal 65 is coupled over one path to a first end of resistor 82. Resistor 82 is coupled on its other end to bias 81. Terminal 65 is coupled over another path to the gate 73 of FIG. 70. Source 71 of FET 70 is coupled on an input side to the output of photodetector 10 at terminal 15 or an equivalent electrical point g shown as terminal 25. The drain 74 of FET 70 is coupled to terminal 75. Terminal 75 is coupled over one path to a first end of resistor 92. Resistor 92 is coupled over its other end to bias 91. Terminal 75 is coupled over another path to the gate 53 of output FET 50. The source 52 of output FET 50 is coupled to a first end of attenuation resistor 42 (Rpg) • Resistor 42 is coupled on another end to bias 41. Drain 54 of FET 50 is coupled to the input of the CCD. The circuit of FIG. 4 is capable of further optimizing the coupling of the photodetector output to the CCD through the selective combination of gate modulation, impedance lowering, gain, and buffering for the cascade. At least one of the amplifiers may be fed back to the photodetector output as shown in the simple 2 stage cascade of FIG. 5. While the invention has been described as set forth above, it will be understood that the invention may be embodied otherwise than as herein specifically illustrated and described, and that in the illustrated embodiments certain changes or more specific forms may appear without departing from the underlying idea or principles of this invention with the scope of the appended claims.

Claims: CLAIMS What is Claimed is: 1 1. For an array of low impedance photodetectors, each coupled to a charge coupled device (CCD) by a circuit of the type which includes: an output FET having a gate coupled to 5T the photodetector output and a drain for delivering the circuit output current to the CCD, the improvement to the circuit comprising: amplifier means connected between the photodetector output and the output FET gate 0 for reducing the circuit impedance. L 2. The improved circuit of Claim 1 wherein the amplifier means is adapted to reduce the effect of photodetector nonuniformities on the output current. I 3. The improved circuit of Claim 1 wherein the amplifier means is adapted to reduce the effect of DC offset voltage variations on the output current. 1 4. The improved circuit of Claim 1 wherein the amplifier means is adapted to reduce the effect of FET nonuniformities on the output current. I 5. The improved circuit of Claim 1 wherein the amplifier means includes a bias voltage for selectively varying the input circuit impedance. 6. The improved circuit of Claim 1 wherein the amplifier means includes a bias voltage for selectively varying the amplifier gain. 7. The improved circuit of Claim 1 further comprising DC suppression means coupled to the photodetector output for draining DC components of the photocurrent p from the circuit, wherein the impedance of such means may be reduced in proportion to the amplifier gain. 8. The improved circuit of Claim 1 wherein the amplifier means includes an FET. 9. The improved circuit of Claim 1 wherein the amplifier means is adapted to reduce the effect of photodetector nonlinearities on the output current. 10. The improved circuit of Claim 1 wherein the amplifier means includes N cascaded FETs having: (a) a first FET having a gate connected to the photodetector output, a source, and a drain coupled to the next FET gate; (b) r2 succeeding FETs, each having a . gate connected to the drain of the previous FET, a source, and a drain connected to the gate of the succeeding FET; and (c) an Nth FET having a gate connected to the drain of the previous FET, a source, and a drain connected to the output of the output FET gate. I 11. The improved circuit of Claim 10 wherein N equals 2. I 12. The improved circuit of Claim 10 wherein the source of at least one amplifier FET is coupled to a bias voltage for varying the amplifier gain. L 13. The improved circuit of Claim 10 wherein the source of at least one amplifier FET is coupled to a bias voltage for varying the input circuit impedance. I 14. The improved circuits of Claim 10 wherein the amplifier means is feedback coupled to the photodetector output for reducing the effect of photodetector non- linearites and nonuniformities on the output current. II 15. The improved circuit of Claim 10 wherein the the photodetector output is coupled to the source of at least one cascaded FET for reducing the effect of FET nonuniformities on the output current. 1 16. A photodetector input circuit for enhancing the coupling of the photodetector output current as an input current to a CCD or similar device, comprising: (a) an output FET having a source, a gate, 5 and a drain for delivering the CCD input current; (b) a first junction electrically coupled to the output of the photodetector; (c) a first resistor having a first end coupled to the first junction and a second end coupled 0 to a first voltage bias; (d) a second resistor having a first end coupled to the FET source and a second end coupled to a second bias voltage; (e) an intermediate amplifier comprising: (i) a second FET (SFET) having a gate, a drain, and a source, with the SFET gate coupled to the first junction, with the SFET source coupled to a bias voltage, and with the SFET drain coupled to a second junction; (ii) a third resistor having a first end coupled to the second junction and having a second end coupled to a third voltage bias; and (iii) means for coupling the second junction to the output FET gate. 17. The circuit of Claim 16 wherein the second end of the second resistor is coupled to the photodetector output. 18. The circuit of Claim 16 wherein the means for coupling the second junction to the output FET gate comprises: a third FET (TFET) having a gate coupled to the second junction, a source coupled to a bias voltage, and a drain coupled to a third junction; a fourth resistor having a first end coupled to the third junction and a second end coupled to a fourth bias voltage; and means for coupling the third junction to the output FET gate. 19. The circuit of Claim 18 wherein the source of the third FET is coupled to the photodetector output .

Inventors: WHITNEY COLIN G, WHITNEY, COLIN, G.
Applicants: HUGHES AIRCRAFT CO, HUGHES AIRCRAFT COMPANY
Application year: 1986
Main classification: H03F3
IPC codes: H03F1, H03F3, H03K17