AN INTERFACE CIRCUIT FOR CONVERTING ECL SIGNAL LEVELS TO FET LOGIC SIGNAL LEVELS

Abstract: An interface circuit for converting emitter coupled logic (ECL) signal levels to FET logic signal levels (e.g for a CMOS FET memory) comprises a small signal multiplier (20) for producing a single-ended clocking signal () for FET logic circuit operation from complementary clocking signals (CS, ) from an ECL and an FET dynamic sense amplifier (22). The multiplier (20) comprises an FET amplifier having an input FET (28) with its source and gate connected to input terminals for said complementary clocking signals. The FET dynamic sense amplifier (22) has a first input (23) for receiving a reference level (VREF) from the ECL circuit, a second input (25) for receiving a logic output signal level (ECL1) from the ECL circuit, and a clocking signal input connected to receive the single clocking signal () produced by the multiplier. In operation, the dynamic sense amplifier produces complementary FET logic signal levels (ADR, ) determined by the potential difference between the levels (VREF, ECL1) applied to its first and second inputs.

Description: This invention relates to an interface circuit for converting emitter coupled logic (ECL) signal levels to FET logic signal levels. MOS transistor memories experience delays in memory access due to the limitations of MOS technologies. Efforts have been successful in reducing delay inherent in MOS technology. The normal drive for FET memories is accomplished with transistor-transistor logic, TTL, which can swing from 0 to 5 volts. The large voltage swing results in large current swings di/dt on the leads driving the FET memory array. As the operational speed of reading and writing FET memory arrays has increas­ ed, these current swings have produced an external limitation on the signals used to drive the memory chips, while the actual internal access time of the memory has decreased from more than 100 ns to less than 20 ns. Increasing the speed of the input signals in an attempt to keep up with increasing memory speed results in more noise from large di/dt current changes and lead inductance which reduces the overall reliabil­ ity of the memory system. Emitter coupled logic (ECL) operates at much higher switching rates than TTL. Emitter coupled logic provides a nominal excursion between logic levels of ± .5 volts, and under worse case conditions a total peak to peak voltage excursion of .6 volts, with the possibility of only 0.1 volts of signals above and below the reference level, far less than the required drive levels for FET memory arrays. Accordingly, a problem arises as to how to couple low level, fast switching ECL voltage levels to FET memory address and data inputs. One suggested solution to the foregoing problem is described in Electronics, 9 September 1985 at page 94. The article describes an ECL to CMOS interface which uses BIMOS, a mixture of CMOS and bipolar technology to manufacture a single memory chip. The multiple process steps of integrating bipolar and CMOS technologies is necessarily complex and expensive and thus undesirable. Another example of a bipolar logic level to FET logic level inter­ face circuit is described in IBM Technical Disclosure Bulletin, Volume 19, No 8, January 1977, pages 2953 to 2954. This circuit provides a clocked circuit for receiving input ECL or TTL logic levels. This circuit requires three timing signals to couple the logic signals on the input nodes to higher voltages suitable for driving an FET array. No method is suggested for converting the timing signals from ECL levels to the required FET voltage levels. This invention seeks to provide an improved interface circuit for converting ECL signal levels to FET logic signal levels. An interface circuit for converting emitter coupled logic (ECL) signal levels to FET logic signal levels comprises, according to the invention, a small signal multiplier for producing a single-ended clocking signal for FET logic circuit operation from complementary clocking signals from an ECL circuit, the multiplier comprising an FET amplifier having an input FET with its source and gate connected to a pair of input terminals for said complementary clocking signals; and an FET dynamic sense amplifier having a first input for receiving a voltage reference level (VREF) from said ECL circuit, a second input for receiv­ ing a logic output signal level from said ECL circuit, and having a clocking signal input connected to receive the single clocking signal () produced by the multiplier, the dynamic sense amplifier producing, in operation, complementary FET logic signal levels (ADR, ) deter­ mined by the potential difference between the ECL levels (VREF, ECLI) applied to its first and second inputs. Such an interface circuit can be used to interface with the address or data inputs of an FET memory. Preferably, the sense amplifier includes an FET clocked differen­ tial amplifier having a pair of input nodes. The ECL reference level and ECL logic level to be converted are applied via separate gates to individual ones of the pair of nodes. The clocking signal from the multiplier enables the gates and is used to control the differential amplifier so that the amplifier assumes the state determined by the ECL logic level and reference level. The nodes are further connected by a pair of amplifier stages to output terminals forming true and complement FET logic levels, suitable for driving an address or input line of an FET semiconductor memory. How the invention can be carried out will now be described by way of example, with reference to the accompanying drawings, in which:- Figure 1A represents an FET CMOS random access memory having an ECL driven interface connected to the address and data input lines; Figure 1B is a block diagram of a preferred ECL/FET interface circuit for the ECL address and input signals of Figure 1A; Figure 2A is a schematic circuit of the dual rail input ECL portion of the clock circuit of Figure 1B; Figure 2B illustrates the dual rail ECL logic levels VCS and V applied to the multiplier circuit of Figure 2A and the difference between the dual rail ECL logic levels; Figure 3A illustrates a preferred embodiment of the sense amplifier of Figure 1B; and Figure 3B is a circuit diagram of a preferred gating circuit for connecting the multiplier circuit of Figure 2B to the sense amplifiers. Figure 1A represents an FET CMOS random access memory provided with an ECL/FET interface 8. A 64k bit array 4 contains an array of transistors which can be addressed to write or read binary data. The memory shown is row and column addressable. The interface circuit 8 may, of course, be used with other memory organisations. The structure of Figure 1A may be entirely fabricated in MOS semiconductor technology, but has the ability to interface with bipolar drive circuitry. In particular, bipolar ECL signal levels are directly interfaced with the memory. The effective interface between ECL logic and FET logic levels is accomplished by the ECL/FET interface 8 and FET/ECL interface 11. The ECL/FET interface 8 is located on the same substrate as the remaining portion of the memory, thus facilitating an entirely MOS fabricated structure. The off-chip ECL drive signals are received in the ECL/FET inter­ face 8. These drive signals, which are usual for controlling a memory, include a write signal W, column address signals, row address signals and data input DI signals. The usual memory control inputs are received on pins which are generically referred to as 25. Each of these inputs is a single ended input with respect to ground for supplying an ECL logic level. The row address and column address in a row and column addressable memory as shown in Figure 1A typically include respectively 7 and 5 signal inputs. The data input is typically 16 bits wide in a memory organised according to Figure 1A. Additional to the single ended standard ECL logic signals used to control the memory, a dual rail clock signal, CS and is received on pins 21a and 21b. The clock signal is the only signal applied via dual rail input to the ECL/FET interface. A ground connection 26 and power supply V+ connection 24 are provided for the entire chip. An additional signal received by the circuit of Figure 1A on pin 23 is a VREF signal supplied by the ECL logic. The ECL logic states are centred with respect to VREF. Thus, the ECL/FET interface includes only a single dual rail input, CS and , and a VREF input, for a maximum of two additional pins required to interface the MOS structure of Figure 1A with ECL drive logic. With these additional two pins and their associated signals, any number of single ended logic inputs may be interfaced to produce both true and complement (T and C) output logic levels. The remaining portion of Figure 1A represents the conventional structure of row and column addressable memory. A 64k bit memory array 4 has a row address driven word decoder 9 and a column address driven bit decoder 5. Each of the converted ECL logic levels is applied by the interface 8 along with the input data signals. Thus, the memory of Figure 1A is driven with FET logic levels. The sense amplifier 7 and output buffer 10 receive stored data from the 64k bit array 4 and provide them to an FET/ECL interface 11. Thus, the data stored as FET logic levels in array 4 is provided as ECL logic levels on output lines 16. Thus, the entire memory of Figure 1A is made input/output compatible with ECL logic levels. The structure of the ECL interface 8 is designed to minimise the required pin out for connections to the memory. Only one dual rail input is necessary for interfacing with the ECL logic circuitry. This dual rail input is necessary for interfacing with the ECL logic circui­ try. This dual rail input receives the chip select signal and its complement, CS and , from the ECL logic circuit connected to the ECL/FET interface. Additionally, a reference level VREF is received from the ECL logic circuit on pin 23. The remaining pins of the ECL/FET interface may be connected to standard single end ECL logic levels used for generating addresses, write commands and data transfer from ECL logic circuitry. Referring now to Figure 1B, an example of the ECL/FET interface 8 of Figure 1A is shown. The ECL interface 8 receives the dual rail chip select signals on pins 21a and 21b. From the dual rail chip select signals, there is provided a clock signal  for clocking in logic states appearing at the input of a plurality of dynamic sense amplifiers 22. Each dynamic sense amplifier 22 receives on an input thereof an ECL logic level which is to be converted to an FET logic level. Addition­ ally, the VREF level from the ECL logic circuitry establishing a refe­ rence voltage is connected to each dynamic sense amplifier 22. With only the connections shown in Figure 1B, it is possible by repeating the dynamic sense amplifier structure 22 to convert any number of single ended ECL logic inputs to a pair of true and complementary FET logic levels. As shown in Figure 1B, ECL 1 applied to pin 25 provides both a true and complementary value, which can be one bit of an address and its complement. The circuit pin out overhead utilising the ECL/FET inter­ face of Figure 1B, includes only a pin for the VREF input 23, and an additional pin for the complement of the chip select signal, , making a total two additional pins necessary to provide an ECL-compatible MOS random access memory. Referring now to Figure 2A, there is shown the clock circuitry 20 for generating a clock signal , used to clock each of the dynamic sense amplifiers 22 from the chip select signal CS and its complement, . A first N channel depletion FET 28 receives on its gate connection the CS level and level on its source connection. A P channel FET 27 serves as a load for the N channel transistor 28. The N channel FETs 29 and 31 and P channel FETs 30 and 32 are connected to provide a signal amplifier for driving the clock input of dynamic sense amplifiers 22 of the ECL/FET interface. Terminal 33 of the clock generator 20 provides the required clock signal  to each of the dynamic sense amplifiers 22. The circuit of Figure 2A is effectively a multiplier, multiplying the logic level CS to substantially an FET logic level. Referring to Figure 2B, there is shown the voltage levels representing the CS logic level and the logic level. The voltage difference between these two signal levels, as shown in Figure 2B, appears across the gate and source of the N channel depletion FET 28. The depletion implant of the channel of FET 28 is chosen so that its threshold voltage is approximately equal to VCS - V where VCS is a low ECL signal level and V is a high ECL signal level. Since the nominal ECL levels are ±.5 volts, this gives a depletion threshold of approximately -1 volt. For the case where VCS is low and V is high the gate-to-source voltage of FET 28 is 1 volt, which provides a drive voltage (gate-to-source minus threshold voltage) of 2 volts. It should be noted that the input ECL voltage levels of Figure 2B can shift up or down around the reference voltage level due to power supply variations or noise and the input ECL signal voltage under these worse case condi­ tions can be as small as 0.1 volts with regard to the reference voltage level, which is smaller than the threshold variation of an FET device. However, by bringing in the CS and dual rail and taking the diffe­ rence between these ECL voltage levels, one is only concerned with differences in the amplitudes of the two ECL input voltage levels and not the difference between the amplitude and a reference level. Since the worst case peak to peak ECL voltage is 0.6 volts, the difference between dual rail inputs CS and gives a six-fold increase in the amount of signal that would be available if only a single rail ECL input signal were available. The multiplication effect of the dual rail input signal provides sufficient signal to be detected using FET devices. In addition, the dual rail signal results in higher speed operation than would be possible with single rail operation. Having thus developed the clocking signal for the ECL/FET interface of Figure 1B, each ECL logic level to be converted to an FET level may be processed by the corresponding dynamic sense amplifier 22. Referring now to Figures 3A and 3B, there is shown the sense amplifier used for generating an FET logic level and its complement from an input ECL logic level. Figure 3B illustrates a circuit for providing additional clock signals 1 and 2, in response to the clock signal . Figure 3B includes two P channel FETs 34 and 35, serially connected with corresponding N channel FETs 36 and 37, to provide delayed clock signals 1 and 2, where 2 is the inverse of 1, delayed by the connection of FET pair 38. 1 is delayed a similar amount from  by the operation of FET pair 39. The resulting clock signals are applied to the sense amplifier of Figure 3A to establish an FET logic level at outputs 25a and 25b. Each of the sense amplifiers represented by Figure 3A includes a cross-­ coupled FET latch 41. The FET latch 41 is clocked by N channel FET 48, receiving on gate 42 a 1 clock signal. Each side of the cross-coupled latch includes a P channel FET 44, 45, clocked by P channel FETs 67, 68 serially connected with N channel FETs 46,47. The nodes 50 and 52 of latch 41, which are connected to the cross-coupled gates, may be switched to store a given input logic level. The cross-coupled latch 41 is connected via P channel FETs 67 and 68 to an FET operating potential received on pin 24. The ground connection for the FET voltage source is connected through pin 26. The operation of the FET latch 41 is such that gate transistors 53 and 54, two N channel FETs, receive the VREF voltage on pin 23 and ECL 1 logic level to be converted to an FET logic level on pin 25. Upon application of the clock signal  to gates 53a and 54a of the correspon­ ding input gate transistors 53 and 54, the logic level ECL 1 will be coupled to node 50 and the VREF potential to node 52. The dynamic sense amplifier of Figure 3A is set by clock pulses , 1 and 2. The initial part of the sensing operation commonly referred to as a slow sense, is initiated by clock  falling and turning on P channel transistor 68. After clock  falls, 1 which is connected to N channel transistor 48 rises and clock 2 which is connected to P channel transistor 67 falls. This is the fast sense part of the sense amplifier setting. The diffe­ rence between the ECL signal levels ECL1 and VREF will determine the state in which latch 41 of the dynamic sense amplifier will be set. Nodes 50 and 52 of latch 41 will set at FET voltage levels. Thus, for each clock pulse  received, the logic level ECL 1 will be gated to the node 50 and compared with VREF on node 52. The state of the latch 41 after setting represents the ECL logic state but at a voltage compatible with the FET memory structure. Each of the nodes 50 and 52 is connected to a respective amplifier chain comprising a plurality of P channel FETs, 55 through 60, serially connected with N channel FETs 61 through 66. Thus, the complement C of the ECL logic state received on pin 25 as well as the true value T of the logic state is available for driving the remaining circuitry of Figure 1A in logic levels of the FET structure. Thus, it can be seen that the ECL/FET interface of Figure 1B can be implemented with standard MOS components requiring only two additional pins from normal MOS semiconductor memory devices. The additional pin being required to carry the complement of the chip select signal, , and a voltage reference level VREF for the device. Any number of logic levels to be converted from ECL to FET compatible logic levels may be generated with the ECL/FET interface of Figure 1B without incurring additional pin-out overhead. Thus, by combining the clock circuit 20 of Figure 2A with the dynamic sense amplifier of Figure 3A, the required interface can be achieved with only the foregoing additional pin-out overhead. The following Table illustrates specific transistor structures which may be used in the implementation of the multiplier of Figure 2A and the dynamic sense amplifier of Figures 3A and 3B. The Table below gives the width to length ratio of each of the transistors. Transistors 55-60 and 61-66 represent amplification stages for coupling the nodes of latch 41 to an address true and complement drive. The transistors are selected to minimise loading on nodes 50, 52 while providing sufficient signal drive for large capacitance address inputs. Standard sense amplifier buffering techniques may be employed to carry out the required interface between nodes 50, 52 and address outputs 25b and 25a.

Claims: 1. An interface circuit for converting emitter coupled logic (ECL) signal levels to FET logic signal levels, the circuit comprising a small signal multiplier (20) for producing a single-ended clocking signal () for FET logic circuit operation from complementary clocking signals (CS,) from an ECL circuit, the multiplier comprising an FET amplifier having an input FET (28) with its source and gate connected to a pair of input terminals for said complementary clocking signals; and an FET dynamic sense amplifier having a first input (23) for receiving a voltage reference level (VREF) from said ECL circuit, a second input (25) for receiving a logic output signal level (ECL1) from said ECL circuit, and having a clocking signal input connected to receive the single clocking signal () produced by the multiplier, the dynamic sense amplifier producing, in operation, complementary FET logic signal levels (ADR, ) determined by the potential difference between the ECL levels (VREF, ECL1) applied to its first and second inputs. 2. An interface circuit as claimed in claim 1, in which the input FET of the multiplier has a conduction threshold substantially equal to the voltage difference between the complementary clocking signals for one logic state. 3. An interface circuit as claimed in claim 1 or claim 2, in which the multiplier further comprises: (a) a load FET (27) having its source-to-drain path connected in series with the source-to-drain path of the input FET (28), the load FET being of complementary type to that of the input FET and having its gate connected to a reference voltage terminal and its drain connected to a voltage supply terminal, and (b) at least one amplifier stage comprising a further pair (29, 30) of complementary FETs having their source-to-drain paths connected in series between the reference voltage terminal and the supply voltage terminal and their gates connected to the junction between the input FET and the load FET, whereby, in operation, a single clocking signal is produced at the junction between the further pairs of complementary FETs in response to the application of complementary clocking signals to the input FET. 4. An interface circuit as claimed in any preceding claim, in which the dynamic sense amplifier includes a clocked differential amplifier latch (41) having a pair of input nodes (50,52), individual gating means (53,54) for gating the ECL reference level (VREF) to one of the pair of input nodes and the ECL logic output signal level (ECL1) to the other of the pair of input nodes, the gating means being controlled by the single-ended clocking signal () and a pair of amplifier circuits (55, 56, 57, 61, 62, 63 and 58, 59, 60, 64, 65, 66) connected to individual ones of the pair of input nodes, the amplifier circuits providing the complementary FET logic signal levels (ADR, ) at their outputs (25a, 25b).

Inventors: SCHAUSTER, STANLEY EVERETT
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H03K19, H03K3