A METHOD FOR MOS TRANSISTOR MANUFACTURE

Abstract: A method for producing MOS transistors of the type having shallow, lightly doped, source/drain structure. In this method sidewall fillets (7) of n-type doped dielectric material are defined adjacent to the sides of the oxide (1) and metal electrode (3) features. These fillets (7) are then employed to provide self aligned masking during implantation of heavy dopant of either n- or p-type (9; 13). In a subsequent rapid anneal step, the implant dopant is activated and n-type dopant diffused into the substrate (5) from the fillets (7) to provide lightly doped source/drain structures (11; 15). Examples of this method are described for producing phosphorous-arsenic n<->/n<+> and phosphorus-boron p<->/p<+> source/drain structures.

Description: A METHOD FOR MOS TRANSISTOR MANUFACTURE Technical Field The present invention concerns improvements in or relating to the manufacture of Metal-Oxide-Semiconductor Field-Effect (MOS) transistors, and in particular but not exclusively, NMOS/PMOS compatible methods for CMOS circuit processing. For small (^1.5ttm) channel length transistors, a lightly doped drain structure is highly desirable. For this range of channel lengths NMOS transistors, in particular, are susceptible to threshold - voltage and gain instabilities (hot-electron effects) due to high electric fields. Electric fields in the vicinity of the drain diffusion can be much reduced by tailoring the drain dopant profile - ie. by adopting a lightly doped drain structure. Background Art In a conventional process two implant steps are used to provide the lightly doped drain structure. Usually this process comprises a heavy implant of phosphorus followed by a light implant of arsenic into silicon. Here, however, after annealing, the junction depth is deep, typically greater than 0.5jλm. It is a problem that these deep junctions degrade small channel length transistor performance, and such structures often prove to be unreliable. Disclosure of the Invention The invention provides a method for MOS transistor manufacture, a simple and alternative method that affords shallow junction structure and thus avoids the problem just discussed. In accordance with the invention there is thus provided a method for MOS transistor manufacture comprising essentially the following steps:- firstly, defining on a silicon crystal substrate a gate oxide and gate electrode; secondly, applying to the gate oxide and gate electrode a deposit of dielectric material incorporating a quantity of n-type dopant, and etching same to create a narrow sidewall; thirdly, introducing a heavy implant dose of appropriate dopant species, to produce a shallow implant adjacent to the side of the sidewall; and, fourthly, annealing to regrow the silicon crystal and to activate the implanted dopant. The method aforesaid requires no additional implantation. An implant step has thus been obviated. Instead, doped dielectric material has been used and the transistor manufacture process simplified. The action of the light implant comes from the doped dielectric. This adds dopant to the drain (and also the source) on the channel side of the drain (source). The addition of this light diffusion tends to lower electric field at the drain-channel junction and thus leads to improvement in the electrical performance of the transistor. ^ The implant species may be either p + -tyρe or n + - 5 type and the method thus is applicable to the manufacture of either PMOS or NMOS transistors - ie. it is applicable to CMOS processing. Channels of length less than or of the order 1.5^m can be exploited in transistors produced thus. 10 The invention thus improves operational reliability in small geometry transistors with no extra expense included during processing. A serious reliability hazard has thus been removed. Brief Introduction of the Drawings, 15 In the drawings accompanying this specification:- Figures 1 to 3 show in illustrative cross-section steps in the application of the inventive method to the manufacture of an NMOS transistor; and, Figure 4 is an illustrative cross-section of a PMOS 20 transistor, produced in a similar manner. Description of Preferred Embodiments So that the invention may be better understood, ■ embodiments will now be described, and reference will be made to the drawings. The description that follows is •I 25 g iven by way of example only . In the first step of the method , a gate ox ide 1 and a polysilicon gate electrode 3 are formed on the surface of a silicon substrate 5. To this structure is added a layer of doped dielectric material - for example a sputtered oxide or spin-on glass containing phosphorus, arsenic or other suitable n-type dopant. This latter layer is then etched back by a reactive ion etch (RIE) or other anisotropic wet or dry etch technique to define small geometry sidewall structures 7. - See Figure 1. At the next step of this method, arsenic ions (As + ) are implanted, a heavy dose at low energy, to produce a shallow implant 9 of enriched n-type (n + ) species. - See Figure 2. Finally, during subsequent heat treatment, the anneal stage of this process, the silicon crystal is regrown and the implanted dopant activated. - See Figure 3. During the anneal, n-type dopant is rejected by the dielectric medium 7 into the silicon 5. This property of n-type dopants in dielectric is used to dope the edge of the drain 9 facing the channel - n-type dopant diffuses in to provided a lightly-doped to enriched-doped n ~ /n + dopant profile 11, 9. For a given bias applied during device use, the n ~ /n + drain exhibits a much reduced electric field compared to n + /channel junctions alone. Where sputtered oxide is used as the dielectric material 7, and phosphorus as the n-type dopant, the latter may be included typically in the concentration 4 to 6 wt. %. Also the enriched n-type (n + ) dopant, arsenic. may be implanted at a dose on the order of lO 1 ^ - 10 l6 /cm 2 , preferably 5 x 10 l5 /cm 2 , at an energy in the range 40 to 120 keV. The anneal, which would be rapid, could be performed at a temperature of 1100 ± 50 * C for a period of between 15 and 30 sees. The doping is essentially shallow, typically 0.2^^deep. In the PMOS transistor, shown in Figure 4, a p~/p + drain profile 15, 13 has been defined. This is likewise produced using an n-type dopant in the dielectric sidewall structure 7. The latter dopant species (n-type) diffuses into the silicon 5 to counter dope the p + type species 13. The diffusion of p-type ions is faster so that no n -/p + structure is formed. Typically, in the above process, the enriched p-type (p + ) dopant can be introduced using a boron (B) or boron-fluoride (BF2) source to give a dopant concentration of lO 1 ^ to 10 1 ^/cm at energies in the range 5 to 25 keV. Choice of dielectric material, n-type dopant and anneal conditions can again be as above.

Claims: CLAIMS 1. A method for MOS transistor manufacture comprising essentially the following steps.- firstly, defining on a silicon crystal substrate (5) a gate oxide (1) and gate electrode (3); secondly, applying to the gate oxide (1) and gate electrode (3) a deposit of dielectric material incorporating a quantity of n-type dopant, and etching same to create a narrow sidewall (7); thirdly, introducing a heavy implant dose of appropriate dopant species, to produce a shallow implant (9) adjacent to the side of the sidewall (7); and, fourthly, annealing to regrow the silicon crystal (5) and to activate the implanted dopant. 2. A method, as claimed in claim 1, wherein the implant dopant species is n-type. 3. A method, as claimed in claim 2, wherein the incorporated n-type dopant is phosphorous and the implant dopant species is arsenic. 4. A method, as claimed in claim 3, wherein the implant is introduced at an energy in the range 40 to 120 keV and at a dose of 10 l5 to 10 l6 /cm 2 . 5. A method, as claimed in claim 1, wherein the implant dopant species is p-type. 6. A method, as claimed in claim 5,- wherein the incorporated n-type dopant is phosphorus and the implant dopant species is boron. 7. A method, as claimed in claim 6, wherein the implant is introduced at an energy in the range 5 to 25 keV and at a dose of lO 1 ^ to 10 l6 /cm 2 . 8. A method, as claimed in either claims 4 or 7, wherein the step of annealing is performed at a temperature of 1100 + 50 C for a period of 15 to 30 seconds. 9. A method, as claimed in any one of the preceding claims, wherein the dielectric is silicon oxide. 10. A method, as claimed in claim 9, wherein the dopant is phosphorus, which dopant is incorporated in the quantity 4 to 6 per cent by weight.

Inventors: FOSTER DAVID JOHN, PICKERING ANDREW JAMES, FOSTER, DAVID, JOHN, PICKERING, ANDREW, JAMES
Applicants: PLESSEY OVERSEAS, PLESSEY OVERSEAS LIMITED
Application year: 1986
Main classification: H01L21
IPC codes: H01L21, H01L29