SENSE AMPLIFIER CIRCUIT

Abstract: For perfect states of balance on sence nodes, there is provided a sense amplifier circuit comprising a balancing cir­ cuit capable of establishing an electrical path between not only the sense nodes but also the sense nodes and control nodes which are operable to control transistors provided between the sense nodes and a voltage supply to apply the supply volt­ age level to one of the sense nodes and remain low level on the other sense node for preparation of reading out of an ac­ cessed information. The current path simultaneously estab­ lished on the beginning of precharging prevents the sense nodes from influence of the large differential voltage on the control nodes, thereby producing the perfect balance states on all the nodes and being conducive to precise judgement on the read out information.

Description: FIELD OF THE INVENTION The present invention relates to a sense amplifier circuit, typically, that which is associated with a digit line of a memory device for quick judgement on a binary data supplied from a selected memory cell to the digit line. BACKGROUND OF THE INVENTION On a semiconductor substrate is formed a plurality of sense amplifier circuits associated with respective digit lines each connected to a plurality of memory cells to which either binary data is stored. When one of the memory cells commonly connected to a digit line is accessed during read mode, the voltage level of the digit line is varied to a certain voltage level in accordance with the binary data stored therein, and the certain voltage level appeared on the digit line is then applied to the associated sense amplifier circuit together with a reference voltage level, typically, having an intermediate voltage level between the voltage levels of the two binary data for quick judgement of the binary data read to the data line. A typical example of a known sense amplifier circuit incorporated in a dynamic random access memory device is illustrated in Fig. 1. The dynamic random access memory device is provided with a plurality of word lines and a plurality of digit lines arranged in rows and columns, however only too of the word lines and two of the digit lines are shown in Fig. 1, and are indicated by reference numerals 1, 1A, 2 and 2A, respectively. To the digit line 2 are commonly connected a plurality of memory cells one of which is indicated by reference numeral 3 and comprises an n-channel MOS transistor 6 and a storage capacitor 7 capable of storing either binary data in the form of a voltage level. The memory cell 3 is provided between the digit line 2 and the ground and gated by the decoded address signal appearing on the word line 1. To the digit line 2A are also connected a plurality of memory cells one of which is indicated by reference numeral 8 and comprises an n-channel MOS transistor 9 and a storage capacitor 10. The digit lines 2 and 2A are paired and connected to respective sense nodes N1 and N2 of a sense amplifier circuit 11. Whenever one of the memory cells connected to the digit line 2A is accessed, the digit line 2 is supplied from a reference voltage source 11 with a reference voltage of, typically, an intermediate voltage level between the voltage levels of the two binary data. On the other hand, the digit line 2A is electrically connected to a reference voltage source 12 so that the reference voltage appears on the digit line 2A whenever the stored binary data is read out from the a selected memory cell to the digit line 2. Turning to Fig. 2 which shows waveforms of signals in the sense amplifier circuit illustrated in Fig. 1, operations of the conventional sense amplifier circuit will be described on the assumption that the memory cell 3 storing the binary data 1 is accessed. Prior to decoding a set of address signals applied to the address pins of the dynamic random access memory device, a precharging signal Φ1 remains high and is applied to n-channel MOS transistors 13, 14, 15, 16 and 17. The precharge transistors 13 and 14 are provided between the sense nodes N1 and N2 and a positive voltage source Vdd, respectively, and the precharge transistors 15 and 16 are, on the other hand, provided between control nodes N3 and N4 and the positive voltage source Vdd. The precharge transistors 13, 14, 15 and 16 thus connected are applied with the precharging signalΦ1, then the precharge transistors 13, 14, 15 and 16 turn on, supplying the sense nodes N1 and N2 and the control nodes N3 and N4 with a positive voltage of a certain level. When the sense node N1 and N2 are pulled up to the certain level, the voltages of the digit lines 2 and 2A also go up to the certain level and balance with each other through the transistor 17 which is concurrently turned on by the precharging signal Φ1. After the precharging signal Φ1 goes down at time t₁, the address signals applied to the decoder circuit from the address pins are decoded, and the voltage of the word line 1 then rises for turning the MOS transistor 6 on at time t₂. When the MOS transistor 6 is turned on, the precharged digit line 2 is electrically connected to the storage capacitor 7 through the MOS transistor 7. However, the storage capacitor 7 storing the binary data 1 has been charged to a voltage level approximately equal to the certain level on the digit line 2, so that the substantial fluctuation does not take place on the digit line 2. When the word line 1 is selected, the digit line 2A is unconditionally connected to the reference voltage source 12 and then goes down to the intermediate voltage level. Thus, a paird digit lines 2 and 2A have different voltages and put a differential voltage of about 0.1 volt on the sense nodes N1 and N2 to which the different voltages are supplied from the paired digit lines 2 and 2A. After the differential voltage appears on the sense nodes N1 and N2 based on the different voltages supplied from the paired digit lines 2 and 2A, a first clock signal Φ2 goes up at time t₃ and then an n-channel active transistor 18 turns on by the agency of the first clock signal Φ2. When the active transistor 18 is turned on, a current path is established between a common node N5 and the ground, then pulling the common node down to the ground level. This causes a pair of cross coupled n-channel transistors 19 and 20 to simultaneously turn on with different channel conductances. Namely, the transistor 19 has a gate connected to the sense node N2 having the relatively low intermediate voltage level, then the channel takes place in the transistor 19 with a relatively small channel conductance. On the other hand, the transistor 20 has a gate connected to the sense node N1 having the relatively high voltage level, then the channel is produced in the transistor 20 with a relatively large channel conductance. The channels thus produced in the respective transistors 19 and 20 are different in channel conductance so that the voltage levels on the sense nodes N1 and N2 go down at different speed, then amplifying the differential voltage on the sense nodes N1 and N2. This results in a voltage level on the sense node N1 slightly lower than the certain voltage level and a voltage level on the sense node N2 approximately equal to the ground level as will be seen from the waveforms in Fig. 2. The sense amplifier circuit 11 illustrated in Fig. 1 further has a pair of cross coupled n-channel transistors 21 and 22 provided between the sense nodes N1 and N2 and the control nodes N3 and N4, respectively. The gates of the transistors 21 and 22 are cross coupled to the sense nodes N2 and N1, then the transistor 21 has a channel with a relatively small conductance but the transistor 22 has a channel with a relatively large conductance, thereby pulling the voltages of the control nodes N3 and N4 down to respective voltage levels similar to the sense nodes N1 and N2. This also results in a voltage level on the sense node N3 slightly lower than the certain voltage level and a voltage level on the sense node N4 approximately equal to the ground level. The control nodes N3 and N4 are connected to pull-up capacitors 23 and 24, respectively. If a second clock signal Φ3 goes up to a preselected positive voltage level at time t₄, the control node N3 goes up over the positive voltage level Vdd to a certain high level which causes an n-channel transistor 25 to fully turn on, thereby supplying the sense node N1 with the positive voltage level Vdd. As the control node N4 has the voltage level approximately equal to the ground level, the control node N4 remains below the supply voltage level Vdd, thereby maintaining the transistor 26 in the off condition. The transistor 26 being thus in the off condition, the sense node N2 still remains in the voltage level approximately equal to the ground level as will be seen from the waveform thereof in Fig. 2. In this manner, the initial differential voltages of about 0.1 volt is amplified, and the binary data stored in the memory cell 3 is judged and read out based thereon. The first and second clock signals Φ2 and Φ3 concurrently go down to the low levels at time t₅, then the active transistor 18 turns off and the control node N3 goes down to the previous certain voltage level lower than the supply voltage level Vdd. This results in the transistor 25 to be turned off. After the turning off of the transistor 25, the precharging signal Φ1 rises again to cause the MOS transistors 13, 14, 15, 16 and 17 to turn on at time t₆, so that the sense nodes N1 and N2 and the control nodes N3 and N4 are precharged to the certain level from the supply voltage level Vdd for preparation of subsequent read out cycle. The precharging signal Φ1 applied to the transistor 17 causes the transistor to turn on for balancing of the sense nodes N1 and N2. The conventional sense amplifier circuit, however, has a drawback in that unbalance in voltage level tends to take place and, for this reason, the sense amplifier circuit sometimes obtains undesirable results which do not reflect the initial differential voltage. This results from that the control nodes N3 and N4 has different voltage levels prior to precharging thereof, and are independently precharged through the respective transistors 15 and 16 supplied with the precharging signal Φ2. The control nodes N3 and N4 thus having the different voltage levels are then saturated to the certain voltage level at different times and need a long period of time to balance with each other as as will be understood from the waveforms in Fig. 2. As a result of the independent precharging, the unbalance in voltage is liable to take place on the control nodes N3 and N4. In addition, the precharging signal Φ1 typically has a voltage level approximately equal to the supply voltage level Vdd, so that the period of time needed tends to be prolonged. During the above described long period of time, if fluctuation of the supply voltage level Vdd takes place, the fluctuation may promote the unbalance on the control nodes N3 and N4. The sense nodes N1 and N2 are supplied with a small differential voltage of, for example, 0.1 volt, the unbalance on the control nodes N3 and N4 has significant influence on the small differential voltage, and inverts the relation of the magnitude of the voltage levels on the sense nodes N1 and N2 in some cases. US-A 4 144 590 discloses a circuit configuration similar to the prior art shown in figure 1, and the problem is, therefore, also encountered in this circuit configuration. The present invention contemplates elimination of these drawbacks which have thus been far inherent in conventional sense amplifier circuits. In accordance with the present invention there is provided a sense amplifier circuit for amplifying a differential voltage between first and second sense nodes applied with different voltages, comprising a first cross coupled circuit including first and second field effect transistors, said first and second field effect transistors being respectively coupled at the first ends thereof to the first and second sense nodes and connectable at the second ends thereof to a ground node, said first and second field effect transistors having gates respectively cross coupled to the second and first sense nodes for varying the different voltages on the first and second sense nodes toward the ground level so as to amplify the differential voltage; a second cross coupled circuit including third and fourth field effect transistors provided between the first and second sense nodes and first and second control nodes, respectively, and having gates respectively cross coupled to the second and first sense nodes for putting different voltages on the first and second control nodes, respectively, in accordance with the different voltages on the first and second sense nodes; capacitor means capacitively coupled to the first and second control nodes and activated in the presence of a first signal of a preselected voltage level for varying the voltage on one of the first and second control nodes across the preselected voltage level, the other of the first and second control nodes having a voltage level closer to the ground level than aforesaid one of the first and second control nodes prior to the application of the first signal; and a load circuit including fifth and sixth field effect transistors provided between the first and second sense nodes and a source of a preselected voltage level, respectively, and having gates respectively connected to the first and second control nodes for supplying the first or second sense node with the preselected voltage level through the fifth or sixth field effect transistor connected to aforesaid one of the first and second control nodes, a balancing circuit including seventh, eighth and ninth field effect transistors, the seventh and eighth field effect transistors being provided between the first and second sense nodes and the second and first control nodes, respectively, the ninth field effect transistor being provided between the first and second sense nodes, the seventh, eighth and ninth field effect transistors having gates turned on by a second signal posterior to the recovery of the first signal for balancing the voltages of the first and second control nodes with each other. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of a sense amplifier circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements and portions and in which: Fig. 1 is a circuit diagram showing an example of a known sense amplifier circuit; Fig. 2 is a timing chart showing waveforms of various signals appearing in the sense amplifier circuit illustrated in Fig. 1; Fig. 3 is a circuit diagram showing a preferred embodiment of a sense amplifire circuit according to the present invention; and Fig. 4 is a timing chart showing waveforms of various signals appearing in the sense amplifier circuit illustrated in Fig. 3. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 3 of the drawings, a preferred embodiment of a sense amplifier circuit 31 according to the present invention largely comprises a first cross coupled circuit provided with the transistors 19 and 20, a second cross coupled circuit provide with the transistors 21 and 22, a pulling circuit provided with the capacitors 23 and 24, a load circuit provided with the transistors 13 and 14, a precharging circuit provided with the transistors 13 and 14, and a balancing circuit provided with not only the transistor 17 but also n-channel transistors 32 and 33. The transistors 32 and 33 are provided between the control nodes N3 and N4 and intermediate nodes N6 and N7, respectively, which are arranged to be disposed on the electrical paths between the sense nodes N1 and N2 and the gates of the transistors 21 and 22 forming parts of the aforesaid second cross coupled circuit. The balancing circuit thus provided with the transistors 17, 32 and 33 is capable of establishment of an electrical path between the control nodes N3 and N4 when the precharging signal Φ1 goes to active high. Operations of the sense amplifier circuit illustrated in Fig. 3 will be described hereinunder with reference to Fig. 4 which shows the waveforms of the signals appearing in the circuit. Assuming now that an external device such as a microprocessor (not shown) supplies a random access memory device employing the sense amplifier circuits according to the present invention with a set of address signals which represent the address of the memory cell 3 storing binary data 1, the random access memory device transfers the address signals from a set of address pins to a decoder circuit (not shown) for decoding the address signals. As shown by the waveform of the precharging signal Φ1, the precharging signal Φ1 remains in active high prior to the selection of the memory cell 3. The precharging signal Φ1 thus remainning in high level is concurrently applied to the respective gates of the transistors 13, 14, 17, 32 and 33, and causes the transistors 13, 14, 17, 32 and 33 to turn on, thereby precharging the sense nodes N1 and N2 and the control nodes N3 and N4 to the certainy level and balancing the voltage levels on not only the sense nodes N1 and N2 but also the control nodes N3 and N4 with each another. After reaching the certain voltage level, the precharging signal Φ1 goes down to turn the transistors 13, 14, 17, 32 and 33 off at time t₁. The decoding of the address signals follows, and the voltage of the word line 1 then rises for turning the transistor 6 on at time t₂. When the MOS transistor 6 is turned on, the precharged digit line 2 is electrically connected to the storage capacitor 7 through the MOS transistor 7. However, the storage capacitor 7 storing the binary data 1 has been charged to a voltage level approximately equal to the certain level on the digit line 2, so that the substantial fluctuation does not take place on the digit line 2. When the word line 1 is selected, the digit line 2A is unconditionally connected to the reference voltage source 12 and then goes down to the intermediate voltage level. Thus, a paird digit lines 2 and 2A have different voltages and put a differential voltage of about 0.1 volt on the sense nodes N1 and N2 to which the different voltages are supplied from the paired digit lines 2 and 2A. After the differential voltage appears on the sense nodes N1 and N2 based on the different voltages supplied from the paired digit lines 2 and 2A, the first clock signal Φ2 goes up at time t₃ and then the active transistor 18 turns on by the agency of the first clock signal Φ2. When the active transistor 18 is turned on, a current path is established between the common node N5 and the ground, then pulling the common node down to the ground level. This causes the pair of cross coupled n-channel transistors 19 and 20 to simultaneously turn on with different channel conductances. Namely, the transistor 19 has the gate connected to the sense node N2 having the relatively low intermediate voltage level, then the channel takes place in the transistor 19 with a relatively small channel conductance. On the other hand, the transistor 20 has the gate connected to the sense node N1 having the relatively high voltage level, then the channel is produced in the transistor 20 with a relatively large channel conductance. The channel thus produced in the respective transistors 19 and 20 are different in conductance so that the voltage levels on the sense nodes N1 and N2 go down at different speed, then amplifying the differential voltage on the sense nodes N1 and N2. This results in a voltage level on the sense node N1 slightly lower than the certain voltage level and a voltage level on the sense node N2 approximately equal to the ground level as will be seen from the waveforms in Fig. 4. In a similar manner, transistors 21 and 22 forming parts of the second cross coupled circuit have respective channels with different conductances which cause the precharged control nodes N3 and N4 to go down at different speeds, then appearing on the control nodes N3 and N4 voltage levels corresponding to those on the sense nodes N1 and N2, respectively as will be seen from the waveforms in Fig. 4. A pull-up operation follows. If the second clock signal Φ3 goes up to the preselected positive voltage level at time t₄, the control node N3 goes up over the positive voltage level Vdd to a certain high level which causes the n-channel transistor 25 to fully turn on, thereby supplying the sense node N1 with the positive voltage level Vdd. As the control node N4 has the voltage level approximately equal to the ground level, the transistor 26 remains in off condition. The transistor 26 thus maintained in off condition causes the sense node N4 to stay in the voltage level approximately equal to the ground level as will be seen from the wavwform thereon in Fig. 4. In this manner, the initial differential voltage of about 0.1 volt is amplified for judgement of the binary data and reading out. After the reading out of the binary data stored in the memory cell 3, the first and second clock signal Φ2 and Φ3 concurrently go down to the inactive low level at time t₅, then causing the transistors 18 to turn off. When the transistor 18 is turned off, the common node N5 is isolated from the ground and put into the high-impedance state. The capacitor 23, on the other hand, pulls the control node N3 down to the previous voltage level with the second clock signal Φ3, so that a differential voltage takes place between the control nodes N3 and N4 as in the conventional sense amplifier circuit described hereinbefore. In order to precharge the sense nodes N1 and N2 and the control nodes N3 and N4, the precharging signal Φ1 goes up at time t₆. When the precharging signal Φ1 goes into the active high level, the transistors 13, 14, 17, 32 and 33 are turned on, electric paths are established from the voltage supply source Vdd to the control nodes N4 and N3 through the transistors 13 and 14, sense nodes N1 and N2, intermediate nodes N7 and N6 and further transistors 33 and 32,respectively. These current paths are electrically connected to each other through the transistor 17 in the on condition. This causes the control nodes N3 and N4 as well as the sense nodes N1 and N2 to be in states of perfect balance regardless of the voltage level of the precharging signal Φ1 and the fluctuation of the voltage source level Vdd as will be seen from the waveforms in Fig. 4. The sense nodes N1 and N2 and the control nodes N3 and N4 thus precisely balanced with each other at the early stage in the precharging cycle are conducive to elimination of the misinterpretation inherent in the conventional sense amplifier circuit. In addition, the sense amplifier circuit illustrated in Fig. 4 is formed with a plurality of n-channel MOS transistors, but it is possible to form a sense amplifier circuit according to the present invention with a plurality of p-channel MOS transistors. As will be understood from the foregoing description, the sense amplifier circuit according to the present invention has the balancing circuit capable of establishment of the electric path between the control nodes so that the control nodes are dependently precharged to the certain voltage level and, for this reason, balance with each other at early stage in the precharging cycle. Moreover, the sense amplifier circuit according to the present invention needs no additional transistors to form the electric path between the control nodes, then being possible to implement on a semiconductor substrate without reduction of memory cell density.

Claims: A sense amplifier circuit for amplifying a differential voltage between first and second sense nodes (N1, N2) applied with different voltages, comprising: a first cross coupled circuit including first and second field effect transistors (19, 20), said first and second field effect transistors (19, 20) being respectively coupled at the first ends thereof to the first and second sense nodes (N1, N2) and connectable at the second ends thereof to a ground node, said first and second field effect transistors (19, 20) having gates respectively cross coupled to the second and first sense nodes (N2, N1) for varying the different voltages on the first and second sense nodes (N1, N2) toward the ground level so as to amplify the differential voltage; a second cross coupled circuit including third and fourth field effect transistors (21, 22) provided between the first and second sense nodes (N1, N2) and first and second control nodes (N3, N4), respectively, and having gates respectively cross coupled to the second and first sense nodes (N2, N1) for putting different voltages on the first and second control nodes (N3, N4), respectively, in accordance with the different voltages on the first and second sense nodes (N1, N2); capacitor means (23, 24) capacitively coupled to the first and second control nodes (N3, N4) and activated in the presence of a first signal (Φ3) of a preselected voltage level for varying the voltage on one of the first and second control nodes (N3, N4) across the preselected voltage level, the other of the first and second control nodes (N3, N4) having a voltage level closer to the ground level than aforesaid one of the first and second control nodes (N3, N4) prior to the application of the first signal (Φ3); and a load circuit including fifth and sixth field effect transistors (25, 26) provided between the first and second sense nodes (N1, N2) and a source of a preselected voltage level (Vdd), respectively, and having gates respectively connected to the first and second control nodes (N3, N4) for supplying the first or second sense node (N1, N2) with the preselected voltage level (Vdd) through the fifth or sixth field effect transistor (25 or 26) connected to aforesaid one of the first and second control nodes (N3, N4), characterized by a balancing circuit including seventh, eighth and ninth field effect transistors (33, 32, 17), the seventh and eighth field effect transistors (33, 32) being provided between the first and second sense nodes (N1, N2) and the second and first control nodes (N4, N3), respectively, the ninth field effect transistor (17) being provided between the first and second sense nodes (N1, N2), the seventh, eighth and ninth field effect transistors (33, 32, 17) having gates turned on by a second signal (Φ1) posterior to the recovery of the first signal (Φ3) for balancing the voltages of the first and second control nodes (N3, N4) with each other. A sense amplifier circuit as set forth in claim 1, in which the sense amplifier circuit further comprises a precharging circuit (13, 14) provided between the first and second sense nodes (N1, N2) and the source of the preselected voltage level (Vdd) and allowed to turn on in the presence of the second signal (Φ1) for precharging the first and second sense nodes to a voltage level approximately equal to the preselected voltage level (Vdd). A sense amplifier circuit as set forth in claim 1, in which the first and second sense nodes are supplied with the different voltage from a selected memory cell (3 or 8) and a reference voltage source (12 or 11), respectively.

Inventors: KANEKO, SHOUJI, OBARA, TAKASHI
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H03K3
IPC codes: H03K3, G11C11, G11C7