SEMICONDUCTOR MEMORY DEVICE

Abstract: A semiconductor memory device having a memory cell is produced by forming a cell partitioned by an insulatinf film (12) for isolation between cells on the surface of a semicon­ ductor substrate (11), providing a first electrode layer (16) on the surface of the substrate (11) through a first insulating film (15), providing a hole (17) penetrating through the first electrode layer (16) and the first insulating film (15), and providing a second electrode layer (19) through a second insulating film (18) in a manner to extend into the hole (17) from the upward direction of the first electrode layer (16) and connect with the substrate (11), thus forming a capacitor utilizing the surface area of the substrate (11). This capacitor can be formed by adding a groove type capacitor thereto. A charge transfer transistor may be provided in the memory cell.

Description: SEMICONDUCTOR MEMORY DEVICE BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a memory cell of a capacitor improved dynamic RAM (dRAM). Recently, the integration of dRAMs has been still more improved. According to this, capacitor area of a memory cell increasingly becomes small. Such dRAMs requires the minimum value of 50 to 60 fF as the capacity of a capacitor of a memory cell in order to prevent soft error originating from a-ray. In view of this , as shown in Fig. 7, an attempt is recently made to provide a groove in a semiconductor, thus increasing the capacity of a capacitor. Namely, on the surface of a substrate 1 of a p-type silicon, an insulating film 2 for isolation between cells is provided. On the surface of the substrate 1 region (memory cell region) partitioned by the isolation insulating film 2, a transfer gate electrode 4 of e.g. a polycrystalline silicon through a gate oxide film 3. Further, a groove 5 is opened in a portion of the substrate 1 within the memory cell region. On the surface of the substrate 1 including the inner surface of the groove 5, a capacitor oxide film 6 is formed. In addition, on the capacitor oxide film 6, a capacitor electrode 7 of e.g. a polycrystalline silicon is provided. This capacitor electrode 7 extends on the insulating film 2 for isolation between cells. It is disposed over a plurality of memory cell regions. Further, on the surface of the substrate 1 at the both sides of the transfer gate electrode 4, n+ type diffusion regions 8 and 9 serving as a source and a drain are provided. Since such a dRAM can form the capacitor on the inner surface of the groove 5, it is possible to effectively increase the capacity of a capacitor without increasing the area of capacitor. Meanwhile, in order to further improve the integration of the dRAM and to maintain the capacity of the capacitor above a predetermined value to prevent soft error, it is required to deepen the depth of the groove when the structure shown in Fig 7 is employed. For instance, when --the opening portion of the groove is formed by a square pattern of e pm by e pm and the depth thereof is h pm, the area of the inner peripheral surface is expressed as (4eh + W2) In this instance, when hyper-fining with the capacity per each groove is at the predetermined value, it is required to deepen the depth h. However, when an attempt is made to deepen the depth of the groove, there occurs the problem in respect of rinse of internal surface of the groove, resulting in the difficulty from a viewpoint of mass-production. On the other hand, a scheme can be used to thin the film thickness of the capacitor oxide film, thereby maintaining the capacity of the capacitor above a predetermined value. However, the capacitor oxide film is in itself from a viewpoint of preventing degradation of a leak characteristic e.g. a tunnel current etc. due to field concentration at an edge of the groove. Accordingly, it is unable to thin the film thickness of the capacitor oxide film to much extent. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device which can be easily massproduced, which has high tolerance with respect to soft error, and which can be highly integrated. Another object of the present invention is to provide a semiconductor memory device which can maintain a predetermined capacity of a capacitor even when the integration is improved. A semiconductor memory device according to the present invention is characterized by the provision of a semiconductor substrate of a first conductivity type, an insulating film for isolation between cells provided on the surface of the semiconductor substrate, a first electrode layer provided on the surface of the substrate partitioned by the isolation insulating film through a first insulating film, a hole penetrating through the first electrode layer and the first insulating layer, and an electrode provided at least on the first electrode layer and within the hole through a second insulating layer, a portion of the electrode being connected to the substrate. The present invention can provide a semiconductor memory device which has a high tolerance with respect to soft error and which can be highly integrated. A semiconductor memory device according tQ the present invention is further characterized by the provision of a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first electrode layer formed on the first insulating film, a predetermined voltage being applied to the first electrode layer, a second insulating film formed on the first electrode layer, a second electrode layer formed on the second insulating film, and a transfer transistor for transferring charge to the semiconductor substrate and the second electrode layer, whereby the first insulating film, a portion of the semiconductor substrate below the first insulating film and the first electrode layer define a first capacitor, and the second insulating film, a portion of the first electrode layer below the second insulating film and the second electrode layer define a second capacitor, thereby using both the first and second capacitors as a cell capacitor of the memory, thus making it possible to maintain a predetermined capacity of the capacitor even when integration is improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross sectional view illustrating an embodiment of a memory cell of a dRAM according to the present invention; Fig. 2 is a cross sectional view illustrating another embodiment of a dRAM memory cell formed by adding a groove type capacitor to the embodiment shown in Fig. 1; Figs. 3 and 4 are cross sectional views illustrating further embodiments, respectively; Fig. 5 is a cross sectional view illustrating a still further embodiment formed by adding a groove type capacitor to the embodiment shown in Fig. 3; Fig. 6 is a cross sectional view illustrating a still more further embodiment formed by a transfer gate electrode to the embodiment shown in Fig. 3; and Fig.7 is a cross sectional view illustrating a memory cell of a conventional dRAM. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Initially, referring to Fig. 1, on the surface of a substrate of e.g. p-type silicon, an insulating film 12 for isolation between cells is provided. On a portion of the substrate 11 region (memory cell region) partitioned by the isolation ins-ulating film 12, a transfer gate electrode 14 of e.g. polycrystalline silicon is provided through a gate oxide film 13. On the surface of the substrate 11 of the memory cell region, first electrode layers 161 and 162 of e.g. polycrystalline silicon are provided through thermal oxide films 151 and 152 as a first insulating film. The first electrode layers 161 and 162 is disposed in a manner the one side is spaced from the transfer gate 14 by a predetermined distance and the other side extends on the isolation insulating film 12. A hole 17 is opened, penetrating through the first electrode layers 161 and 162 and the thermal oxide films and and152. On the most part of the surface of the first electrode layers 161 and 162 and within the hole 17, a secondelectrode 19 of e.g. polycrystalline silicon is provided through e.g. thermal oxide films 181 and 182 as a second insulating film. This electrode 19 is connected to an n+ type diffusion region 20 formed on the surface -of the substrate 11 through the hole 17. -A voltage is not-iapplied-to the second electrode 19 and it is placed in a floating condition. Further, on the surface at the both sides of the transfer gate electrode 14, n+ type diffusion regions 20 and 22 serving as a source and a drain are provided. A transfer gate electrode 23 is provided on the second electrode layer 19 through a SiO2 film. In accordance with the configuration stated above, by applying a predetermined voltage to the first electrode layers 161 and 162, the capacity of a capacitor in respect of one memory cell is given by the sum of the capacity of the thermal oxide films 151 and 152 between the first electrode layers 161 and 162 and the substrate and the capacity of the thermal oxide films 181 and 182 between the first electrode layers 161 and 162 and the second electrode layer 19. As a result, this structure can increase the capacity of a capacitor three to five times larger than that of the conventional planar capacitor. Accordingly, this makes it possible to extremely lessen the influence of minority carrier in the substrate produced by a-ray etc., thus improving tolerance with respect to soft error. Further, since a groove is not formed in the substrate in the above-mentioned embodiment, the problem in regard of rinse of the interior of the groove or the like can- be eliminated, thus facilitating massproduction. In the above-mentioned embodiment, the thermal oxide film is used as the second insulating film. However, the second insulating film is not limited to the thermal oxide film. For instance, a silicon nitride film, a composite film of the silicon oxide film and the silicon nitride film, a high melting point metal film or a SiO2 film of high melting point metal may be used. In the above-mentioned embodiment, a diffusion region of a conductivity type opposite to the substrate may be formed on the surface of the substrate below the first electrode layer. By the provision of the diffusion region below the first electrode layer, when voltage is applied to the electrode, a depletion layer is spreaded on the surface of the substrate near the first insulating film, thereby making it possible to prevent the capacity of a capacitor from being lowered. Fig. 2 shows another embodiment according to the present invention. This embodiment provides a semicondcutor device additionally provided with a groove type capacitor by adding a groove 31 and a capacitor oxide film 32 respectively corresponding to the groove 5 and the capacitor oxide film 6 to the embodiment shown in Fig. 7. Fig. 3 is a cross sectional view illustrating a further embodiment of a memory semiconductor device according to the present invention. On a p-type semiconductor substrate 101, an insulating film 102 for isolation between cells is formed similarly to the conventional device. On the surface of the semiconductor substrate 101, a first insulating film 110 (e.g. an oxide film) is formed. On. the first insulating film 110, a first electrode layer 111 is formed. The first electrode layer 111 extends over the isolation insulating film 102 to serve as- an electrode common to a large number of memory cells. On the first electrode layer lllt a second insulating film 112 (e.g. an oxide film) is further formed. On the second insulating film 112, a second electrode layer 113 is still further formed. According to the configuration of each memory cells, the structure of the second electrode layer 113 is different in general. As shown in Fig. 3, the second electrode layer 113 and the second electrode layer 113' belonging to the adjacent memory cell are electrically connected to each other. The first insulating film 110, a portion of the semiconductor substrate 101 below the first insulating film 110 and the first electrode layer 111 defines a first capacitor. The second insulating film 112, a portion of# the first electrode layer 111 below the second insulating film 112 and the second electrode layer 113 defines a second capacitor. These two capacitors are used together as the cell capacitor of the memory. On the semiconductor substrate 101, a transfer transistor 106 for transferring charge to the abovementioned cell capacitor is provided. This transfer transistor 106 is the same as the conventional device shown in fig. 7. Accordingly, parts identical to those in Fig. 7 are designated by the same reference numerals, respectively, and their explanation will be omitted. Both electrodes 107a and 107b of the transfer transistor 106 each comprises an n+ diffusion layer buried into the semiconductor substrate 101. One electrode 107b is connected to the semiconductor substrate 101 and also connected to the second electrode layer 113. Between the transfer gate electrode 109 and the second electrode layer 113, an isolation insulating film 114 is formed. Because a predetermined voltage is always applied to the first electrode layer 111, by controlling a voltage applied to the transfer gate electrode 109, it is possible to charge or discharge the cell capacitor. Namely, a charge supplied to the cell capacitor via the transfer transistor 106 is accumulated in a region near the first insulating film 110 within the semiconductor substrate 101 and in a region near the second insulating film 112 within the second electrode layer 113. Thus, the semiconductor device of this embodiment can maintain the capacity of a capacitor substantially twice larger than that in the conventional device without digging a groove in the semiconductor substrate. It is needless to say that it is possible to further increase the capacity of the capacitor by digging a groove in the semiconductor substrate. Fig. 4 is a cross sectional view illustrating a further embodiment of the invention. Parts identical to those of the embodiment shown in Fig. 3 are de-signated by the same reference numerals, respectively, and their explanation will be omitted. This embodiment is characterized in that an n+ diffusion layer 115 is provided below the first insulating film 110 and a diffusion layer 116 is provided below the n+ diffusion layer 115. Thus, a pn junction is formed by these two diffusion layers 115 and 116, with the result that a capacity of the pn junction can be obtained, thus further increasing the capacity of a capacitor. Fig. 5 shows a still further embodiment of the present invention. This embodiment provides a semiconductor device additionally provided with a groove type capacitor by adding a groove 131 and a capacitor oxide film 132 respectively corresponding to the groove 5 and the capacitor oxide film in Fig. 7 to the embodiment shown in Fig. 3. Fig. 6 shows a still# more further embodiment of the present invention wherein a transfer gate electrode 106A is added to the embodiment shown in Fig. 3.

Claims: CLAIMS: 1. A semiconductor memory device, characterized by comprising: a) a semiconductor substrate (11) of a first conductivity type; b) an insulating film (12) for isolation between cells provided on the surface of said semiconductor substrate (11); c) a first electrode layer (16) provided on the surface of said substrate (11) partitioned by said isolation insulating film (12) through a first insulating film (15); d) a hole (17) penetrating through said first electrode layer (26) and said first insulating film (15); and e) a second electrode layer (19) provided at least on said first electrode layer (16) and within said hole (17) through a second insulating film (18), a portion of said second electrode layer (19) being connected to said substrate through said hole (17). 2. A semiconductor memory devil as set forth in claim 1, wherein a first diffusion region (20) of a second conductivity type is provide in an area near said surface of said semiconductor substrate (11) to which an electrode (19) is connected. 3. A semiconductor memory device as set forth in claim 1, wherein a second diffusion region (22) of a second conductivity type is provided in an area near said surface of said semiconductor substrate (11) below said first insulating film (15). 4. A semiconductor memory device as set forth in claim 2 or 3, wherein a third diffusion region of said first conductivity type is provided in said semiconductor substrate (11) below said first and second diffusion regions. 5. A semiconductor memory device as set forth in claim 1, wherein a groove (31) is digged in said semiconductor substrate (11), an oxide film (32) is provided onto the inner surface of said groove (31), and a capacitor electrode layer (19) is provided at least within said groove through said oxide film (32). 6. A semiconductor memory device as set forth in claim 1, wherein a transfer gate electrode (23) is provided on said second electrode layer (19). 7. A semiconductor memory device as set forth in claim 1, wherein a transfer gate electrode is provided below said first electrode layer (16). 8. A semiconductor memory device, characterized by comprising: a) a semiconductor substrate' (10); b) a first insulating film (110) formed on said semiconductor substrate (101); c) a first electrode layer (111) formed on said first insulating film (110), a predetermined voltage being applied to said first electrode layer (111); d) a second insulating film (112) formed on said first electrode layer (111); e) a second electrode layer (113) formed on said second insulating film (112); f) a transfer transistor (106) for transferring charge to said semiconductor substrate (101) and said second electrode layer (113); ; whereby said first insulating film (110) , -a portion of said semiconductor substrate (101) below said first insulating film (110) and said first electrode layer (111) define a first capacitor,#and said second insulating film (112), a portion of said first electrode layer (111) below said second insulating film (112) and said second electrode layer (113) define a second capacitor, thus using said first and second capacitors as the cell capacitor of the memory. 9. A-semiconductor memory device as set forth in claim 8, wherein said transfer transistor (106) is comprised of a field-effect transistor formed on said semiconductor substrate (101), one electrode (107b) of said transistor being buried into said semiconductor substrate and connected thereto, said second electrode layer (113) being connected to said one electrode (107b) of said transistor (106). 10. A semiconductor memory device as, set forth in claim 9, wherein said electrode (107b) of said transistor (106) buried into said semiconductor substrate is comprised of a doped layer of a conductivity type opposite to said semiconductor substrate (101). 11. A semiconductor memory device as set forth in claim 8, 9 or 10, wherein said semiconductor substrate (10) comprises a doped layer (115) of a conductivity type opposite to said semiconductor substrate (101), and a heavily doped layer (116) of the same conductivity type as said semiconductor substrate (101) being provided below said doped layer (115) provided below said first insulating film (110). 12. A semiconductor memory device as set forthAin claim 8, 9, 10 or 11, wherein said semiconductor substrate (101) is provided with a groove (131) for increasing the capacity of a capacitor. 13. A semiconductor memory device as set forth in claim 8, wherein a groove (131) is digged into said semi- conductor substrate (101), a capacitor oxide film (132) being provided on the side walls of said groove (131), said electrode (107b) of said transfer transistor-(106) being provided on the bottom wall of said groove (131).

Inventors: MAEDA, SATOSHI 102, HILLSIDE HEIGHTS
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L27
IPC codes: H01L27