Matrix display panel

Abstract: The specification and drawings relate to liquid crystal ma­ trix display panel which is used to display a television image or the like and disclose the technology in which the pixels on a matrix are divided into at least two groups of pixels, in part­ icular, two right and left pixel groups; these pixel groups are respectively independently driven within one horizontal scan­ ning interval; thereby widening the width of the vertical scan­ ning signal and allowing the image signal to be sufficiently transferred to the liquid crystal cells; and thereby allowing a high-quality image to be displayed without causing the lack of luminance and a variation in luminance in association with the realization of a large area and a fine pitch of the display panel.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a matrix display panel having a thin film transistor and, more particularly, to a liquid crystal matrix display panel for displaying a television image or the like. Related Background Art Hitherto, there has been proposed a display panel for displaying a multivalue image, for example, a television image by use of a high-density two-dimensional matrix type liquid crystal panel (active matrix type liquid crystal panel) using a thin film transistor (hereinafter, abbreviated to a TFT). As a method of driving such a display panel, an image signal corresponding to all pixels in the horizontal direction is sampled and held within one horizontal scanning interval, and thereafter a vertical scanning signal (hereinafter, abbreviated to a gate pulse) is supplied to the gate line of the TFT, thereby allowing the image signal to be transferred to an equivalent capacitance of a liquid crystal cell and allowing the television image or the like to be displayed on the liquid crystal panel. In the above-mentioned driving method, when the television signal is of the NTSC system, one horizontal scanning interval is 63.5 µsec and the interval (horizontal blanking interval) other than the image information in one horizontal scanning interval is about 11 µsec, so that the maximum width of the gate pulse of the TFT is limited to the value which is almost as long as the horizontal blanking interval. Therefore, in the case of this gate pulse width, the image signal cannot be sufficiently transferred to the liquid crystal cell due to variations in characteristics (particularly, ON resistance) of the TFT of the matrix substrate, so that a variation in luminance of the liquid crystal panel occurs. In recent years, the area of the panel enlarges more and more, the pitch of the panel becomes finer and finer, the dimension of the TFT is miniaturized, and the wiring pattern becomes fine, so that its impedance also increases. Consequently, in the case of the above gate pulse width, a sufficient charging rate into the equivalent capacitance of the liquid crystal cell can be hardly obtained. Further, in order to narrow the amplitude of the image signal, a method wherein a voltage of a phase opposite to the image signal is applied to the opposite common electrodes has been also considered. However, in this case, it is necessary invert the common electrodes after the first gate pulse was applied, so that the condition concerned with the allowable time becomes further severe. Document GB-A-2 124 816 discloses a display apparatus comprising a dot matrix liquid crystal display panel of the twist nematic type. Moreover, the display is of a double matrix type wherein two picture element electrodes lying on each of the signal electrodes commonly provided in the direction of the width of the scanning electrodes are in opposition to each other. The double matrix system needs only half the number of scanning electrodes since therein the width of the scanning electrode is chosen over that of two dots. Furthermore, the signal electrodes of this display apparatus consist of four blocks since otherwise the used LSIs for driving the signal electrodes would be too expensive and wiring would be difficult. SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display panel having a high image quality in which even when the area of the panel is enlarged and the pitch of the panel is made fairly fine, the lack of luminance and the variation in luminance are not caused. The invention is set out in the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a constitutional diagram of an embodiment of the present invention; and Fig. 2 is a time chart for the operation of the embodiment of Fig. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a liquid crystal matrix display panel having an active matrix substrate which is driven by source and gate lines, the present invention is characterized in that the pixels on the matrix are classified into at least two groups of pixels, in particular, the pixels are divided into two right and left pixel groups, and each pixel group is respectively independently driven within one horizontal scanning interval. As the result of that the display panel is divided into first and second pixel groups in the lateral direction, the gate lines are also divided into a forward part and a backward part. The divided pixel groups are respectively driven by independent driving circuits by way of the first and second gate lines and the first and second common electrodes. According to the invention, the divided two pixel groups are independenly driven; therefore, it is sufficient to charge the liquid crystal cells of one pixel group for the horizontal scanning interval of the other pixel group. The width of the gate pulse can be widened to the time of about 1/2 of one horizontal scanning interval. By raising the charging rate of the liquid crystal cells, the image signal is efficiently transmitted to the liquid crystal cells, so that the lack of luminance and the variation in luminance due to a variation in characteristics of the TFT are not caused. An embodiment of the present invention will now be described in detail hereinbelow. Fig. 1 is a constitutional diagram of a liquid crystal display panel according to the invention and its peripheral circuits. In Fig. 1, reference numeral 1 denotes an image signal input terminal; 2 is an amplifier; 3 an inverter; 4 a change-over switch; 5 a horizontal sync signal input terminal; 6 a clock generator; 7 a horizontal shift register; 8 a vertical sync signal input terminal; 9 an inversion signal input terminal; 10-1 and 10-2 first and second vertical shift registers; and 11 a liquid crystal panel. The liquid crystal panel 11 is an active matrix liquid crystal panel which is driven by source lines S₁ to S 2m and gate lines G₁ to G n . In the invention, a group of pixels are divided by half, a matrix is constituted by the source lines S₁ to S m and gate lines G L1 to G Ln from the first vertical shift register 10-1, and another matrix is constituted by the remaining source lines S m+1 to S 2m and gate lines G R1 to G Rn from the second vertical shift register 10-2. An image signal is input from the image signal input terminal 1 and amplified by the amplifier 2. Thereafter, the amplified signal is directly transmitted to one terminal of the change-over switch 4 and is also supplied to the inverter 3, by which it is inverted and sent to the other terminal of the change-over switch 4. The change-over switch 4 switches those two signal paths in accordance with the polarity of an INV (inversion) signal from the inversion signal input terminal 9 and is driven by an alternate current manner. An HD signal (horizontal sync signal) is input from the horizontal sync signal input terminal 5. When the clock generator 6 generates a clock which is almost 2m times as large as the HD signal, the horizontal shift register 7 generates sequential scanning pulses H₁ to H 2m synchronized with the HD signal on the basis of both of the HD signal and the clock signal. The image signal to which the polarity was given by the change-over switch 4 is distributed into capacitors C₁ to C 2m by switches T₁ to T 2m in response to the sequential scanning pulses H₁ to H 2m . The source lines S₁ to S 2m are connected to the capacitors C₁ to C 2m , respectively. On the other hand, the HD signal is input as a clock to the vertical shift registers 10-1 and 10-2. These vertical shift registers 10-1 and 10-2 shift at the period of the HD signal and transmit the sequential scanning pulses synchronized with the VD signal (vertical sync signal) input from vertical sync signal input terminal 8 to the first gate lines G L1 to G Ln and the second gate line G R1 to G Rn . Respective pixels LC₁₁ to LC n·2m of the liquid crystal panel 11 are arranged on the matrices by the source lines S₁ to S 2m and the gate lines G L1 to G Ln and G R1 to G Rn . As described above, according to the invention, the gate line which has conventionally been formed by a single line is divided into the right and left parts. In addition, although not shown in Fig. 1, the common electrodes may be divided and taken out in correspondence to the gate lines in dependence on a driving method. While, the horizontal shift register 7 sequentially samples and holds the image signal into the next capacitors C m+1 to C 2m , a gate pulse is applied to one of the first gate lines G L1 to G Ln , and the data sampled and held in the capacitors C₁ to C m corresponding to the image signal of the first gate lines is transferred to the pixels LC K1 to LC Km connected to the gate line G LK and then displayed. While the horizontal shift register 7 sequentially samples and holds the image signal of the next line into the capacitors C₁ to C m , a gate pulse is applied to one of the second gate lines G R1 to G Rn , and the data sampled and held in the capacitors C m+1 to C 2m corresponding to the image signal of the second gate lines is subsequently transferred to the pixels LC K·m+1 to LC K·2m connected to the gate line G RK and then displayed. By repeating the foregoing cycle, a television image is displayed on the liquid crystal panel 11. Fig. 2 is a timing chart showing an example of the operation of the liquid crystal display panel having the foregoing peripheral circuits. In Fig. 2, the image signal is the NTSC signal as one of the television system. Sample-hold 1 and 2 denote intervals to sample and hold into the capacitors the image signal which is input to the pixels connected to the first and second gate lines, respectively. P W1 and P W2 indicate the widths of the gate pulses which are applied to the first and second gate lines. The common electrode 1 signal and common electrode 2 signal are supplied to the common electrodes corresponding to the first and second gate lines, respectively. In Fig. 2, t f and t r denote trailing time and leading time of the common electrodes, respectively. As shown in Fig. 2, by dividing the gate lines into the first and second gate lines, the gate pulse widths P W1 and P W2 can be widened from within the conventional horizontal blanking interval to the time duration of about 1/2 of the other image signal sample/ hold interval, namely, one horizontal scanning interval. These widths are about three times as long as the conventional ones. Even in the case of applying the voltage to the opposite common electrodes, the limination of the times t r and t f which are required to invert the polarity is lightened because of the foregoing reasons. In other words, although the interval of P W + t r or P W + t f is limited to an interval within the horizontal blanking interval, it is sufficient to take the time of about 1/2 of one horizontal scanning interval. The image signal held in the capacitors C₁ to C 2m is sufficiently transferred to the liquid crystal cells. The lack of luminance and the variation in luminance in association with the variation in characteristics of the TFT and with the realization of a large area and a high fine pitch of the panel are not caused and an excellent display quality can be obtained. In addition, the display panel is divided into the first and second pixel groups and each pixel group is respectively driven by the independent driving circuits. Therefore, the limitation of the driving timing is also lightened and there is also the advantage such that the burden for the driving capability of the driving circuit is also reduced. In the above embodiment, the NTSC signal has been described as an example. However, the invention is also effective in the case of displaying characters or the like by use of a frame memory or the like. As described above, according to the invention, a group of pixels of the display panel and its gate lines are divided and the gate pulse widths upon driving are widened. Thus, even if the area of the active matrix type liquid crystal display panel is enlarged and the pitch of this panel is made highly fine, the lack of luminance and the variation in luminance are not caused, and the image with a high quality can be displayed.

Claims: A display apparatus, comprising: (A) a matrix display panel including an active matrix base plate (11), said active matrix base plate (11) further comprising: a first group of transistors (LC₁₁ to LC nm ) arranged in rows columns, and a second group of transistors (LC 1m+1 to LC n2m ) arranged in rows columns, wherein in said first group of transistor (LC₁₁ to LC nm ) the gates of the transistors arranged along each row are commonly connected to a gate line (G L1 to G Ln ) for each row, and in said first group of transistors (LC₁₁ to LC nm ) the sources of the transistors arranged along the column are commonly connected to a source line (S₁ to S m ) for each column, and wherein in said second group of transistors (LC 1m+1 to LC n2m ) the gates of the transistors arranged along each row are commonly connected to a gate line (G R1 to G Rn ) for each row, and in said second group of transistors (LC 1m+1 to LC n2m ) the sources of the transistors arranged along the column are commonly connected to a source line (S m+1 to S 2m ) for each column, (B) first drive means (10-1, 10-2), further comprising: a first scan pulse generation circuit (10-1) connected to the gate lines (G L1 to G Ln ) to which the transistors in said first group of transistors (LC₁₁ to LC nm ) are connected for each row, and a second scan pulse generation circuit (10-2) connected to said second gate lines (G R1 to G Rn ) to which the transistors in said second group of transistors (LC 1m+1 to LC n2m ) are connected for each row, wherein scan pulses are alternately generated from said first and second scan pulse generation circuits (10-1, 10-2) within one horizontal scanning interval such that while the sampled and held data are being transferred to liquid crystal cells of one of said groups of transistors, the data to be transferred to liquid crystal cells of the other group of transistors is sampled and held ; and (C) second drive means (7), further comprising: a first data output circuit (H₁ to H m ) connected to the source lines (S₁ to S m ) to which the transistors in said first group of transistors (LC₁₁ to LC nm ) are connected for each column, and a second data output circuit (H m+1 to H 2m ) connected to the source lines (S m+1 to S 2m ) to which the transistors in said second group of transistors (LC 1m+1 to LC n2m ) are connected for each column, wherein data pulses are alternately generated from said first and second data output circuits (H₁ to H m , H m+1 to H 2m ) in synchronism with the generation of said scan pulses. A display apparatus according to claim 1, wherein said first data output circuit (H₁ to H m ) and said second data output circuit (H m+1 to H 2m ) respectively comprise sample-and-hold circuits for alternately sampling and holding input data. A display apparatus according to claim 1, wherein said first and second data output circuits (H₁ to H m , H m+1 to H 2m ) respectively comprise sample-and-hold circuits for alternately sampling and holding input data, and further comprising a circuit in which, while one of said data output circuits samples and holds the input data, the other of said data output circuits outputs the sampled and held data. A display apparatus according to claim 1, wherein said first group of transistors (LC₁₁ to LC nm ) and said second group of transistors (LC 1m+1 to LC n2m ) are respectively divided into right and left regions on a display screen. A display apparatus according to claim 1, wherein said transistor (LC₁₁ to LC nm , LC 1m+1 to LC n2m ) includes a thin film transistor.

Inventors: INOUE YUJI, MIZUTOME ATSUSHI, SUGANO HIDEO, YAMASHITA SHINICHI, INOUE, YUJI, MIZUTOME, ATSUSHI, SUGANO, HIDEO, YAMASHITA, SHINICHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1986
Main classification: G09G3
IPC codes: G02F1, G09G3, H04N5, G09F9, H04N3