AN OFF-GATE CIRCUIT FOR A GATE-TURN-OFF THYRISTOR

Abstract: An off-gate circuit for a GTO thyristor comprises a power source for supplying current to the circuit at a predetermined voltage, and a switching circuit connected to the power source for supplying off-gate current to the GTO thyristor of at least two different current rates.

Description: This invention relates to an off-gate circuit for a gate-turn-off thyristor (GTO thyristor). It is known from US-A-4 464 585 an off-gate circuit which is shown in Figure 1 of the accompanying drawings and Figures 2a(I)(II)(III) illustrate respective waveforms in the operation of the circuit shown in Figure 1. In Figure 1, a GTO thyristor 1 has its gate connected to one end of a secondary winding N₃ of a pulse transformer 2, and its cathode connected through diodes 7a and 7b to the other end of the secondary winding N₃. A gate power source 3 is connected through a diode 6 to one end of a primary winding N₁ of the pulse transformer 2 so as to supply gate power. The other end of the primary winding N₁ is connected to one end of a primary winding N₂ and also to one end of a capacitor 4. The other end of the primary winding N₂ is connected through a transistor 5 to the other end of the capacitor 4 and also to the negative side of the gate power source 3. Waveform 2(a)(I) represents a voltage waveform V C across the capacitor 4, waveform 2(a)(II) represents an off-gate current I OFF produced from the secondary winding N₃ of the pulse transformer 2, and waveform 2(a)(III) represents a voltage waveform V G-K between the gate and cathode of the GTO thyristor 1. At a time t O , the capacitor 4 is charged with a polarity V CO . The transistor 5 is then turned on when a base signal is fed to the transistor. The charge on the capacitor 4 is then discharged through the primary winding N₂ of the pulse transformer 2 and the transistor 5 so as to induce a voltage within the secondary winding N₃. This voltage produces an output current I OFF in the secondary winding N₃. The current I OFF is produced as a negative current between the cathode and the gate of the GTO thyristor 1. Diodes 7a and 7b prevent penetration of the on-gate current of an on-gate current circuit (not shown). During the period T OFF from the time t O to a time t₁, the base signal is fed into the transistor 5 which remains turned on. After the period T OFF , should the transistor 5 be turned off at the time t₁, an exciting current of the pulse transformer 2 flows through a path of the positive side of the gate power source 3, the diode 6, the primary winding N₁ of the pulse transformer 2, the capacitor 4, and the negative side of the gate power source 3, whereby the capacitor 4 is recharged. An equivalent circuit in this state is shown in Figure 2(b). In recent years, there has been a need for a power converter apparatus employing larger-capacity GTO thyristors. With such thyristors, one of the requirements for satisfactory operation is that the rising rate dI/dt of the gate reverse current should be large. It is known from GB-A-1583620 for a gate circuit of a gate turn-off thyristor to include a power source connected to a capacitor and for switching means to discharge the capacitor to generate an off-gate current pulse between the gate and cathode of the thyristor. The pulse has a relatively large rising rate and a relatively narrow pulse width. In addition, a second circuit generates an off-gate current pulse having a relatively small rising rate and a relatively wide pulse width. The pulses are generated together and result in a pulse supplied to the thyristor which has a relatively large rising rate and a relatively wide pulse width. Large capacity GTO thyristors have a significant switching loss which affects the thyristors thermally and, if the switching loss can be reduced, the switching frequency can be increased. It is an object of the present invention to reduce turn-off loss of a GTO thyristor. According to the present invention, a circuit for supplying turn-off current between the gate and cathode of a GTO thyristor comprises a power source; capacitor means coupled to the power source to be charged to a predetermined voltage level; and switching means for discharging the capacitor means to thereby generate an off-gate current pulse between the gate and cathode of the thyristor; characterised in that said switching means includes means for selectively discharging the capacitor means such that the increase in value of the current pulse has a first rate of change followed by a second rate of change which is a higher rate of change than the first rate of change so as to reduce turn-off loss of the thyristor. In order that the invention may be more readily understood, it will now be described, by way of example only, with reference to the accompanying drawings, in which:- Figure 3 is a schematic diagram illustrating one embodiment according to the present invention; Figures 4(a) and 4(b) are characteristic diagrams of GTO thyristors explaining the preferred embodiment of the present invention; Figures 5(I) to 5(V) are waveform diagrams of respective parts explaining the preferred embodiment of the present invention; and Figure 6(a) to 6(c) are schematic diagrams illustrating other embodiments of the present invention. Referring now to Figure 3, one embodiment of the present invention will be described. In Figure 3, parts identical to or corresponding to those in Figure 1 are designated by like reference numerals so that the description thereof will be omitted. A terminal is provided on primary winding N₂ of pulse transformer 2 to form windings N₂₁ and N₂₂. A transistor 5a is connected between the end of winding N₂₁ and the negative side of source 3 and transistor 5b is connected between the end of winding N₂₂ and the negative side of source 3. Base signals of the transistors 5a and 5b are supplied from an ON-OFF control circuit 8. A diode 9 prevents the winding N₂₂ from being short-circuited when the transistor 5a is turned on, while a diode prevents a reverse voltage from being applied to the transistor 5b. Next, operation of this embodiment will be described with reference to Figures 3, 4 and 5. In general, turn-off characteristics of GTO thyristors are such that when the off-current change rate dig/dt is lowered, the tail current becomes smaller. However, the gate power source voltage E g also becomes lower when the change rate dig/dt is lowered. When the gate power source voltage E g decreases, the fall time t f increases, and the maximum interruption current I ATO (max) tends to decrease by the amount of increased power loss caused by the lengthened fall time t f . When the change rate dig/dt is increased, both the storage time t stg and the fall time t f decrease. However, the tail current I tail increases. This relationship between t f and I tail is shown in Figure 4(a). Figure 4(b) illustrates characteristics in the case of turn-off, which represent the relationship of an anode current I A , a voltage V A-K between the anode and cathode, turn-off loss P OFF , and a voltage V G-K between the gate and cathode. Instantaneous loss upon turn-off increases in proportion to increases of the fall time or the tail current. To reduce turn-off loss, the characteristics of the GTO thyristor should be utilised in a control method, as shown in Figure 5, with respect to the circuit of Figure 3. The change rate dig/dt in the first part of the storage time t stg is made to be lowered to decrease the tail current I tail , and the change rate dig/dt in the latter part of the storage time t stg is made to be increased to decrease the fall time t f . The above control method is very effective to decrease the turn-off because the fall time t f is more influenced by the change rate dig/dt in the latter part of the storage time t stg than by that in the first part of the storage time t stg . In Figure 5, (I) shows a waveform of the voltage across the capacitor 4, (II) a base control signal S b of the transistor 5b, (III) a base control signal S a of the transistor 5a, (IV) an assumed waveform between the gate and cathode of GTO thyristor when employing the control method, and (V) an off-gate current waveform. During the period from a time t O to a time t₁, the transistor 5b is turned on, and an off-gate current of lower change rate dig/dt is produced through the windings N₂₁ and N₂₂ in series. During the period from the time t₁ to a time t₂, the transistor 5a is turned on, and an off-gate current I OFF of higher change rate is produced through the winding N₂₁. These operations are periodically repeated to perform necessary switchings. Other modified methods which do not use pulse transformers may be utilised to effect changeover from the off-gate current of lower dig/dt to the off-gate current of higher dig/dt. These modified embodiments are shown in Figures 6(a), 6(b) and 6(c), wherein parts identical to those in Figure 3 are designated by identical reference numerals, so that the description thereof may be omitted. Reference numerals 11a to 11f designate diodes, 12 designates an impedance component (here, a reactor is described, for example), 13 designates a transformer, and 14a to 14d and 15 denote diodes. In Figure 6(a) a switching component 5b functions to suppress discharge of the charge on the capacitor 4 through an impedance component 12 to produce an off-gate current of lower dig/dt. Here, the reactor is described, for example, so that the diode 15 is provided in parallel therewith to suppress the occurrence of overvoltage. However, in the case of a resistor, such a diode is unnecessary. After a specified time has elapsed, a switching component 5a is turned on to produce an off-gate current of higher dig/dt. Further, as shown in Figure 6(b), a capacitor which supplies an off-gate current that changes from a lower dig/dt to a higher dig/dt may be separated into capacitors 4a and 4b. These are provided with diodes 14c and 14d, respectively, or suppressing cross currents between the capacitors 4a and 4b. Moreover, as shown in Figure 6(c), the impedance component 12 may be replaced by a transformer 13. The transformer 13 has a tap terminal so that the charged voltage of the capacitor 4a may be made lower than that of the capacitor 4b. A plurality of power sources of different voltages also may be provided, so that the operation of switching component 5b produces an off-gate current of lower dig/dt while operation of the switching component 5a produces an off-gate current of higher dig/dt.

Claims: A circuit for supplying turn-off current between the gate and cathode of a GTO thyristor (1), said circuit comprising a power source (3); capacitor means (4) coupled to the power source to be charged to a predetermined voltage level; and switching means (5) for discharging the capacitor means to thereby generate an off-gate current pulse (I OFF ) between the gate and cathode of the thyristor (1); characterised in that said switching means (5) includes means (5a, 5b, 8) for selectively discharging the capacitor means such that the increase in value of the current pulse has a first rate of change followed by a second rate of change which is a higher rate of change than the first rate of change so as to reduce turn-off loss of the thyristor. The circuit of claim 1, wherein the switching means includes transformer means (2) coupled between the power source, the capacitor means and the GTO thyristor, and comprising windings for receiving current, and for generating the off-gate current flow in the GTO thyristor in response to the discharging of the capacitor, characterised in the provision of first and second switches, the first switch (5b) being operatively connected to the transformer means for controlling the transformer means to generate off-gate current having the first rate of change of current flow, the second switch (5a) being operatively connected to the transformer means for controlling the transformer means to generate off-gate current having the second rate of change of current flow in the GTO thyristor; and control means (8) for controlling the first and second switches to selectively cause the switching means to generate the first and second rates of change for the off-gate current. The circuit of claim 1, characterised in that the switching means includes first and second switches, the first switch (5b) being operatively connected to the capacitor means and the GTO thyristor for generating off-gate current having the first rate of change of current flow, the second switch (5a) being operatively connected to the capacitor and the GTO thyristor for generating off-gate current having the second rate of change of current flow in the GTO thyristor; and control means (8) for controlling the first and second switches to selectively cause the switching means to generate the first and second rates of change for the off-gate current. The circuit of claim 3, characterised in that the capacitor means has an associated rate of discharge and the first switch (5b) includes impedance means (12, 15) for suppressing the rate of discharge of the capacitor means to generate the off-gate current having the first rate of change of current flow. The circuit of claim 4, characterised in that the capacitor means includes first capacitor (4b) and second capacitor (4a), each being charged with the corresponding voltage; and wherein the first capacitor (4b) is operatively connected to the first switch (5b) and the second capacitor (4a) is operatively connected to the second switch (5a), the first and second switches being responsive to the first and second capacitors, respectively, to cause the switching means to generate the first and second rates of change for the off-gate current. The circuit of claim 4 or 5, characterised in that the impedance means (12, 15) includes a reactor (12) having a diode (15) connected in parallel therewith. The circuit of claim 3, characterised in that the capacitor means includes first and second capacitors (4a, 4b) chargeable with a first, lower voltage and a second, higher voltage, respectively, the first and second capacitors being charged by the power source; and wherein the first capacitor (4a) is operatively connected to the first switch (5b) and the second capacitor (4b) is operatively connected to the second switch (5a), the first and second switches being responsive to the first and second capacitors, respectively, to cause the switching means to generate the first and second rate of change for the off-gate current.

Inventors: KAWAKAMI, KAZUTO PATENT DIVISION, TSURUTA, YUKINORI PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H03K17
IPC codes: H03K17, H02M1