Field effect transistor

Abstract: A field effect transistor includes a semiconductor substrate (ll), first and second semiconductor layers (l2, 4l) formed on the semiconductor substrate, and third semiconductor layers (2l, 22, 23) located between the first and second semiconductor layers. The third semicon­ ductor layers (2l, 22, 23) have a forbidden band with narrower than those in the first and second semiconductor layers and form a quantum well. The third semiconductor layers include a doping layer (22) such as planar-doping or high doping, and a channel is formed in the third semi­ conductor layers along the quatrum well. The electrons supplied from the doped layer are confined by the quantum well and form a quasi-two-dimensional electron gas.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and particularly to a device having a quantum well in a channel structure. The channel formed along the quantum well is two-dimensional due to confinement of carriers in the quantum well. 2. Description of the Related Art Many attempts have been made to improve the characteristics of a field effect transistor FET in realizing a high transconductance (gm), in reducing a short channel effect and so on. The basic GaAs MESFET has a semi-insulator GaAs substrate, an n-GaAs layer, n⁺ layers contacting with a source and a drain respectively, source and drain electrodes, and a gate electrode. When a bias voltage is applied to the gate electrode, a depletion layer is extended to control a current flow. At this time, if a channel length is shortened, there will be caused a problem on the short channel effect. Generally when the channel length is about 1 µm or less, a threshold voltage V th of the field effect transistor is positively changed. In this case the larger the impurity concentration N in an active layer of the channel, the smaller the change of the threshold V th . Therefore, in order to reduce the short channel effect in MESFET, the active layer may be highly doped. Once the active layer is highly doped, the depletion layer is made thinner so that the gm may be improved. In the prior art device, however, the number of carriers cannot be simply increased by employing high doping due to such problems as a decrease in electron mobility and a decrease in a device withstand voltage. One prior art transistor described in Microelectronics Engineering, vol. 2, Nos 1/3, pages 34-43 in an article by C. Hamaguchi et al. entitled "Physics of nanometer structure devices", consists of a single quantum well transistor (SQWT) that features a modulation doped quantum well of substantial thickness, being formed of two GaAs layers that are respectively doped and undoped, each 250 Å (10Å= 1nm) thick. These layers lie between undoped GaAs layers of 100 Å thickness, on one of which is formed a FET structure. A paper in Applied Physics Letters, vol. 45, No 8, pages 902-904 by D. Arnold et al entitled "High performance and large current double interface modulation-doped field-effect transistors with the bulk (Al, Ga)As replaced by superlattice at the inverted interface", shows an inverted n-GaAs/AlAs superlattice composed of a doped-undoped layer sequence. Finally, a paper published in IEEE Transactions on Electron Devices, vol. ED-28, No 5, pages 505-510 by K. BOARD et al. entitled "Characteristics of planar doped FET structures" gives a theoretical discussion on the behaviour of free carriers confined within multiple doped planes and how it affects the transfer characteristics of FET device employing such a structure. SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved field effect transistor in which the number of carriers can be increased while maintaining or enhancing both the electron mobility and the device breakdown voltage. According to the present invention there is provided a field effect transistor as defined in claims 1 and 7. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a view showing the constitution of a prior art GaAs MESFET; Fig. 2 is a characteristic diagram explaining a short channel effect; Fig. 3 is a characteristic diagram explaining an energy band of the MESFET; Fig. 4 is a view showing the constitution of a field effect transistor according to an embodiment of the present invention; Figs. 5A and 5B are characteristic diagrams explaining energy band and electron distribution in the device shown in Fig. 4; Fig. 6 is a characteristic diagram explaining a subthreshold; Fig. 7 is a view showing the constitution of a field effect transistor according to another embodiment of the present invention; Figs. 8A and 8B are characteristic diagrams explaining energy band and electron distribution in the device shown in Fig. 7; Figs. 9A and 9B are enlarged illustrations of a portion of Figs. 8A and 8B; Figs. 10A and 10B are characteristic diagrams showing energy band and electron distribution of the device according to still another embodiment of the present invention; and Figs. 11A and 11B are characteristic diagrams showing energy band and electron distribution of the device according to still another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the preferred embodiments of the present invention, an explanation will be given for the prior art GaAs MESFET with reference to Fig. 1. In Fig. 1, 11 represents a semi-insulating (SI) GaAs substrate; 43 an n-GaAs layer; 51 and 61 n⁺ layers in contact with a source and a drain respectively; 52 and 62 a source electrode and a drain electrode respectively; and 7 a gate electrode. When a bias voltage is applied to the gate electrode 7, a depletion layer 44 is extended to control a channel current. At this time, if the channel length is shortened , the problem of a short channel effect may occur, as shown in Fig. 2; when the channel length is reduced to about one µm or less, a threshold voltage V th of the field effect transistor is changed as shown in Fig. 2. In this case the larger the impurity concentration N in an active layer of the channel, the smaller the change of the threshold V th . Therefore, the active layer will be highly doped in order to reduce the short channel effect. Once the active layer is highly doped, a depletion layer shown in an energy band of Fig. 3 is thinner and the number of carriers to be modulated increases, so that the gm may be improved. In the prior art device, however, the number of carriers cannot be simply increased because of the problems such as a decrease in electron mobility (whose effect leads to a decrease in electron velocity) and a decrease in a device breakdown voltage. Figure 4 shows a constitution of a field effect transistor according to an embodiment of the present invention. In Fig. 4, on a semi-insulating (SI) GaAs substrate 11, an i-AlGaAs layer 12, a quantum well region QW, an i-AlGaAs layer 41, and an i-GaAs layer 42 are formed. A mole fraction x of the AlAs in the i-AlGaAs layers 12 and 41 is generally from 0.2 to 1.0, but is selected to be, for example, 0.2 to 0.3, partly because of their quality in material. The quantum well region QW is composed of an i-GaAs layer 21, an n-GaAs layer 22, and an i-GaAs layer 23, and is also included in AlGaAs layers. The doping layer 22 in the quantum well QW is, for example, a planar doping or high doping layer. The above layers may be embodied as follows: Layers 12 and 41: These are undoped-AlGaAs layers each having a layer thickness of several hundred angstroms so that carriers cannot tunnel therethrough. Layers 21 and 23: These are undoped-GaAs layers, each having a layer thickness of several tens of angstroms. Layer 22: This is an n-GaAs layer. If a planar doping is adopted for the layer, it will be an atomic planar doping wherein an Si or Se atomic-monolayer is interposed between the i-GaAs layers, and if a high doping is adopted, the doping concentration will range from 10¹⁸ to 10¹⁹ cm⁻³. The layer thickness is virtually several tens of angstroms to about one hundred angstroms. The doping n-GaAs layer 22 is provided among the non-doping i-GaAs layers 21 and 23 on both sides thereof to prevent the dopants from diffusing toward the i-AlGaAs layers 12 and 41. The quantum well QW region composed of the layers 21, 22, and 23 (and also 12 and 41) is 100 angstroms or less in thickness to ensure the two-dimensionality in the electrons. Layer 42: This is an undoped-GaAs layer having a layer thickness of several hundred angstroms. The doping layer 22 may be formed at a position close to a heterojunction in the quantum well. Preferably, the doping layer is provided close to the heterojunctions (ten angstroms or so) since the electron mobility is enhanced due to effective separation between ionized impurity and two-dimensional electrons. In Fig. 4, the numerals 51 and 61 represent n⁺ regions of 10¹⁷ to 10¹⁸ cm⁻³ formed by an ion implantation with Si⁺ ions; 52 and 62 a source electrode and a drain electrode respectively (AuGe/Au); and 7 a gate electrode (Al). Figure 5A is an energy band diagram in which the quantum well QW is formed between the i-AlGaAs layers 41 and 12. Figure 5B shows the distribution of electrons (e) in the quantum well QW. The planar doping or high doping layer is formed in the quantum well QW. The electrons supplied from the layer are confined by heterojunctions to maintain the two-dimensionality. The thickness of the quantum well QW is virtually about 100 angstroms, to provide the two-dimensionality. The device shown in Fig. 4 has the following characteristics: (i) The number of carriers in this device can be increased with increasing sheet doping density, while carrier density in HEMT or MODFET is limited by Fermi-level crossing the bottom of conduction-band in n-AlGaAs layer. Also, excess carriers can be generated in the channel under the forward gate bias condition due to MIS operation of this device. (ii) The doping concentration in the channel is high, and electrons are confined by the heterojunctions of the quantum well QW so that a narrow channel is formed to further reduce the short channel effect in comparison with the prior art MESFET. (iii) Since the electrons are confined by a relatively high barrier of a lower heterojunction (the right heterojunction in Fig. 2), a current cutoff characteristic, so-called sub-threshold characteristic, is excellent in the vicinity of a current zero line (in the vicinity of a pinch-off). (iv) Since a gate capacitance is constant due to MIS type structure the linearity of a device characteristic' (a constant gm) will satisfactorily realize. (v) The doping is done for the GaAs layer (no ΔX-centre) so that the threshold is less affected by a temperature. (vi) Since the channel is two-dimensional, the impurity doping is limited to a part in the quantum well (especially, doped close to heterojunctions) and the carrier mobility can be maintained and improved. (vii) Since the gate electrode can be formed on a high resistance layer such as the i-GaAs layer and i-AlGaAs layer, the gate withstand voltage will be improved. Figure 7 shows a field effect transistor according to another embodiment of the present invention. In Fig. 7, on a semi-insulating GaAs substrate 11, a non-doping i-AlGaAs layer 12, a quantum well layer (QW) 2, an i-AlGaAs layer 41, and an i-GaAs layer 42 are formed and a lot of electrons, especially excess electrons screen the ionized impurity. A mole fraction x of the AlAs in the i-AlGaAs layers 12 and 41 is generally 0.2 to 1.0, and 0.2 to 0.3 in this embodiment. The quantum well layer QW 2 comprises an i-GaAs layer 25, an i-AlGaAs barrier layer 26, i-GaAs layers 27 and 29, and a doping layer 28. The doping layer 28 is a planar doping or high doping layer. The above layers may be embodied as follows: Layers 12 and 41: These are i-AlGaAs non-doping layers each having a layer thickness of several hundred angstroms so that carriers cannot tunnel therethrough. Layer 25: This is an i-GaAs non-doping layer having a layer thickness of 100 angstroms. Layer 26: This is an i-AlGaAs non-doping layer having a layer thickness of 10 angstroms (= l₁) so that carriers can tunnel. Layers 27, 28, and 29: These are GaAs layers having a total layer thickness of 20 angstroms (= l₁). The layers 27 and 29 are non-doping layers. If the layer 28 is a planar doping layer (an atomic planar doping layer where a single atomic layer or a plural atoms layer of Si or Se is interposed between i-GaAs layers), the doping concentration by impurities of Si or Se will exceed 10²⁰ cm⁻³, and if the layer 28 is a high doping layer, the doping concentration will be about 10¹⁸ - 10¹⁹ cm⁻³. The doping n-GaAs layer 28 is provided with the non-doping i-GaAs layers 27 and 29 on both sides thereof to prevent the dopants from diffusing toward the i-AlGaAs layers 26 and 41. The quantum well QW 2 comprising the layers 25, 26, 27, 28, and 29 is, for instance, 130 Å in thickness to ensure the two-dimensionality. Layer 42: This is an i-GaAs non-doping layer having a layer thickness of several hundred angstroms. In Fig. 7, the numerals 51 and 61 represent n⁺ regions of 10¹⁷ to 10¹⁸ cm⁻³ formed by an ion implantation with Si⁺ ions; 52 and 62 a source electrode and a drain electrode respectively (AuGe/Au); and 7 a gate electrode (Al). Figure 7 shows an embodiment in which the quantum well is separated into a narrow and a wide width regions by the barrier. Another schematic diagram of the device shown in Fig. 7 will be described with reference to Figs. 8A and 8B. Figure 8A is energy band diagram showing the field effect transistor of the present invention. Figure 8A shows a gate electrode 7 of Al, a cap layer 42 of i-GaAs layer, an i-AlGaAs layer 41, a quantum well QW, and an i-AlGaAs layer 12. The quantum well QW has a thin barrier 26 which is provided at an asymmetrical position such that electrons can tunnel therethrough. The quantum well QW region is separated by the barrier 26, and impurities are doped only for a narrow width region. The quantum well QW has a width of about 100 angstroms to provide the two-dimensionality. Figure 8B shows electron distribution in the well. As described above, the quantum well QW region has a thin AlGaAs barrier at the asymmetrical position thereof, so that electrons can tunnel through the barrier. As a result, the position probability density of electrons is small in the narrow width region of the quantum well, and large in the wide width region of the quantum well. Namely, a quantum level energy En (by indefinite square well potential approximation) is proportional to an inverse of Δx² (the width ΔX of the quantum well) and sensitive to the width. Actually, if the quantum wells exist independently, the different energy levels are formed according to the wells. However, once the thin barrier through which electrons can tunnel is provided between quantum wells, only a single level is formed for the wells, but no separate levels are formed respectively for the narrow width region of layers 27, 28, and 29 and the wide width region 25. As a result, as shown in enlarged views of Figs. 9A and 9B, electron distribution (hatched portion) in the narrow width region REGION-1 differs greatly from that in the wide width region REGION-2. It should be noted that, in Fig 9A, bond bending is not illustrated. The present invention utilizes the above physical phenomenon to obtain an electron layer having a high average electron mobility through a method different from that of the prior art. Namely, a high doping concentration n-layer 28 is employed in the narrow width region REGION-1 of the quantum well by a planar doping method, etc., to increase the position probability density of electron in the wide width region REGION-2, which is the non-doping layer of the quantum well, so that a high mobility electron layer will be realized. The electron layer formed is confined in the quantum well to achieve the two-dimensionality. For instance, l₁ = 20 angstroms, and l₃ = 100 angstroms. The thickness and energy height of the thin barrier in the quantum well may be selected optionally, but shall be selected such that electrons can tunnel through the barrier. The narrower the doping region of the quantum well, the larger the asymmetry between the narrow and the wide width regions, so that the whole electron mobility is improved. The heterojunctions are formed using, for example, AlGaAs/GaAs/AlGaAs layers. The structure has an improved electron mobility compared to the MESFET and is expected to realize the same electron mobility as that of a conventional HEMT or MODFET structure. Since the GaAs material (no ΔX-center) is doped, the threshold voltage is less affected by the variation of temperature and bias step. Also, since the electrons are confined by the heterojunctions, the subthreshold characteristic is improved and the short channel effect is reduced. Moreover, the electron concentration in the channel can be increased with increasing doping density and thus a narrow channel can be realized. As a result, the short channel effect can be further prevented in comparison with the prior art MESFET, and thus greatly reduced. For the similar reason, the linearity of the device characteristic is improved as well as employing MIS structure of the present invention. On the other hand, the prior art MESFET is a homojunction with a lower barrier, so that the characteristic curve of a gate voltage V gs and a drain current I d is far from linear, and the subthreshold characteristic is not enough satisfactory. In addition to the above-described embodiments, many modifications can be made for the present invention. For example, a plurality of barriers through which electrons can tunnel and a square root of a drain current Id may be provided to dope impurities only for narrow width regions among regions partitioned by the plurality of barriers. Energy band for such a modified embodiment is shown in Fig. 10A. It should be noted that, in Figs 10A and 10B, band bending is not illustrated. Electron distribution is shown in Fig. 10B. In this embodiment, two barrier layers (i-AlGaAs) 22 and 24 through which electrons can tunnel are employed. A mole fraction x of the AlAs of the i-AlGaAs barrier layers 22 and 24 may be equal with each other or may be different from each other as shown in Fig. 10A. In this embodiment, x are 0.5 and 0.2. In Fig. 10A, narrow width regions REGION-1 and REGION-3 are formed on both sides of a quantum well and are provided with doping layers 28 and 22, respectively. The width of center region REGION-2 is wider than those of both regions REGION-1 and REGION-3. The electrons will exist in the center wider region with a higher position probability density. Moreover, electrons are supplied from both of the narrow regions, so that a sheet carrier concentration Ns will be much higher than that of the embodiment shown in Figs. 9A and 9B. Figures 11A and 11B show still another embodiment of the present invention. It should be noted that, in Figs 11A and 11B, band bending is not illustrated. These show the energy band, and the electron distribution, respectively. In Fig. 11A, AlAs barrier layers are designated by 26 and 30. Electrons provided from a narrow region tend to be more concentrated toward a wide region REGION-2 than in Fig. 9. This is because the higher barrier layer produces the larger number of carriers to be transferred into the wide region due to the larger difference in electron energy level. As a result, when the higher thin barriers (barriers with larger x) are provided on both sides of the doping layer 28 in the narrow width region, the number of carriers transferred at the non-doping wide region will increase and thus a much higher electron mobility will be realized. The present invention allows a wide variety of materials for the constitution. The examples of pairs of materials having different electron affinity are InGaAs/InAlAs, Ga/CaAs, InP/InAlAs, GaAs/InGaP, GaSb/AlSb, and so on.

Claims: A field effect transistor comprising: a semiconductor substrate (11); a first semiconductor layer (12) formed on said semiconductor substrate; a second semiconductor layer (41) formed above said first semiconductor layer, said first and second semiconductor layers each having a electron affinity and each having a overall thickness such that carriers cannot tunnel therethrough; a third semiconductor layer (21, 22, 23; 25, 26, 27, 28, 29) formed between said first and second semiconductor layers with heterojunctions formed between said first and third semiconductor layers and said second and third semiconductor layers, said third semiconductor layer comprising a quantum well formed by a doped layer (22, 28) and by undoped layers (21, 23; 25, 26, 27, 29) on both sides thereof and having a forbidden bandwidth narrower than a forbidden bandwidth of said first and second semiconductor layers, and a gate electrode (7), for controlling carriers in said third semiconductor layer, formed above said second semiconductor layer, characterised in that said quantum well has a thickness of 13 nm or less; and in that said field effect transistor further comprises: a source region (51) and a drain region (61) provided on respective sides of the said gate electrode and contacting said first, second and third semiconductor layers; a source electrode (52) and a drain electrode (62) formed on said source region and said drain region respectively; and a channel formed in said third semiconductor layer along said quantum well. A field effect transistor according to claim 1, wherein said quantum well layer has a planar doped layer. A field effect transistor according to claim 1 or 2, wherein the doping concentration of said quantum well layer is more than 10¹⁸ cm⁻³. A field effect transistor according to claim 1, wherein said quantum well (21, 22, 23) is provided as a single quantum well. A field effect transistor according to claim 4, wherein said semiconductor substrate (11) is made of semi-insulator gallium-arsenide GaAs, said first and second semiconductor layers (12, 41) are made of aluminum-gallium-arsenide AlGaAs, said third semiconductor layer (21, 22, 23) is made of gallium-arsenide GaAs, and said doped layer (22) is a planar doping layer or a high doping layer. A field effect transistor according to claim 5, characterized in that a non-doping gallium-arsenide layer (21, 23) is located in both sides of said doping layer. A field effect transistor comprising: a semiconductor substrate (11); a first semiconductor layer (12) formed on said semiconductor substrate; a second semiconductor layer (41) formed above said first semiconductor layer, said first and second semiconductor layers each having an electron afinity and each having an overall thickness such that carriers cannot tunnel therethrough; a third semiconductor layer (21, 22, 23; 25, 26, 27, 28, 29) formed between said first and second semiconductor layers with heterojunctions formed between said first and third semiconductor layers and said second and third semiconductor layers, and a gate electrode (7), for controlling carriers in said third semiconductor layer, formed above said second semiconductor layer, characterised in that said third semiconductor region comprises a first sub-layer including a doped layer (28), said first sub-layer having a first thickness; a second sub-layer (25) being substantially non-doped and having a second thickness greater than the first thickness; and a barrier layer (26) formed between said first and second sub-layers, allowing a tunneling effect therethrough, thereby forming a quantum well region that is divided by said barrier, and having a forbidden bandwidth narrower than a forbidden bandwidth of said first and second semiconductor layers, said quantum well having a thickness such as to ensure a two-dimensional electron confinement therein, and in that said field effect transistor further comprises: a source region (51) and a drain region (61) provided on two sides of the said gate electrode and contacting said first, second and third semiconductor layers; a source electrode (52) and a drain electrode (62) formed on said source region and said drain region respectively; and a channel formed in said third semiconductor layer along said quantum well. A field effect transistor according to claim 7, wherein the said quantum well region (25, 26, 27, 28) is 13nm or less.

Inventors: HIKOSAKA KOHKI, HIRACHI YASUTAKE, HIKOSAKA, KOHKI, HIRACHI, YASUTAKE
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1986
Main classification: H01L29
IPC codes: H01L29