Data processing system

Abstract: A data processing system incorporating a main memory (206) for storing instructions and operands and performing data processing in a mode of microprogram control system in response to instructions read out of the main memory (206). The system translates an instruction word read out of the main memory (1, 2) into an intermediate machine word having the orthogonal format, and addresses a microprogram memory (202) in correspondence to the instruction word by analyzing the intermediate machine word. The system further incorpor­ ates a plurality of register sets so that each different task can use an individual register set, and a memory (2106) for memorizing the number of registers holding parameters used commonly among procedures corresponding to the register sets, so that the number of registers for each use can be changed arbitrarily for each register set by using the memory.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a data processing system and, particularly, to a microprogram-controlled data processing system incorporating an instruction decoder and multiple register sets, the system being suitable for constructing a microcomputer. DESCRIPTION OF THE RELATED ART Recent advanced micro-miniaturizing technology in the field of semiconductor devices, particularly MOS (Metal Oxide Semiconductor) devices has enabled upgraded functions and performance of microcomputers. In order to avoid the complexity of logics resulting from the enhanced circuit integration, the achievement of an integrated circuit by an orderly structured logic circuit is becoming the mainstream method. One practice is the microprogram control system. A microprogram-controlled data processing system is generally constructed using an instruction decoder which generates the microprogram ROM address from the instruction word. However, this system necessitates a large scale hardware for the instruction decoder, and a microprogram control system coping with this problem by elimination of the instruction decoder is proposed in Japanese Patent Unexamined Publication No. 57-203141. However, this system sets the instruction word directly in part of the microprogram ROM address information, and therefore as the instruction word length increases from 8 bits to 16 bits and to 32 bits the length of the microprogram ROM address increases with it, resulting disadvantageously in an expanded microprogram ROM address decoder. Prior art document WO-A-84 01 635 discloses a method for accelerated instruction mapping external to source and target instruction streams for near realtime injection into the latter. The corresponding apparatus includes a first and a second register, means for loading a source instruction into said first register, means responsive to the OP -code contents within said first register for loading a micro instruction control section (control word) into the second register, mapping logic conditioned by the control word in the second register for selectively copying (gating out) or computing from source instruction fields into the skeleton instruction, and means for merging the "flashed out" target instruction into the counterpart target CPU instruction stream. An object of this invention is to provide a data processing system having enhanced functions and performance. Another object of this invention is to provide a data processing system of the type or instruction decoding system which is responsive to various instruction formats. The inventive data processing system is of the type of instruction decoding system in which an instruction word (machine word) read out of the main memory is arranged into an intermediate machine instruction word in a completely orthogonal format suitable for the decoding hardware arrangement and then the intermediate machine word is decoded. An instruction word in a completely orthogonal format is defined here to be an instruction word of only one format having information bits representing operand specifiers for identifying an operation code specifying the operation to be executed and locations in the main storage containing operands. In a data processing system in general, the bit positions for the operation code and operand specifying differ depending on each instruction so that information on the operation and operands is contained in the limited instruction word with less redundancy. In the conventional system, this type of instruction has been decoded or used for microprogram ROM address generation, and therefore the system needs to incorporate a large scale address generating hardware for the decoders and the like. The inventive system performs instruction decoding by initially converting an instruction word into an instruction word of the completely orthogonal format suitable for decoding, noting the facts that the bit arrangement of instruction words which are not completely orthogonal is not completely random, but has some rule, and translation of instruction words not orthogonal into orthogonal instruction words is relatively easy, and the decoding hardware and ROM capacity can be reduced when the microprogram ROM address is generated by decording a completely orthogonal instruction word. The inventive system incorporates decoders for arranging instruction words into intermediate machine words separately for each instruction format so that decoding of intermediate machine words takes place commonly for every instruction format, with the intention that instruction words of different formats or different word length can be processed. Having the foregoing arrangement, the inventive system can deal with instruction words in different formats without modifying or adding the hardware arrangement within the processor, except for the instruction word storage and the translation unit which arranges instruction words into intermediate machine words for decoding, and the hardware arrangement used for instruction decoding can be reduced to 1/5 to 1/10 of the counterpart of the conventional instruction decoder system. As another feature of this invention, the system can process instruction words having at least two instruction formats. As described above, the present invention improves the decoding function for instructions in reading the microprogram ROM without increasing the scale of hardware. The invention can provide a high performance, high functioning data processing system without a significant increase in the hardware arrangement, but through the efficient use of the hardware resources while employing the general-purpose register system. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages of the present invention will become apparent by making reference to the following description and accompanying drawings, in which: Fig. 1 is a block diagram showing the processor in the data processing system embodying the present invention; Fig. 2 is a block diagram showing the microcomputer formed on a single semiconductor substrate by application of the inventive data processing system; Fig. 3 is a block diagram showing the arrangement of the instruction word memory/translation unit, microprogram memory control unit, decoder unit, and operation unit included in the processor shown in Fig. 1; Fig. 4 is a set of diagrams showing examples of the instruction format; Fig. 5 is a block diagram showing another embodiment of the instruction word memory/translation unit in the processor shown in Fig. 1; Fig. 6 is a block diagram showing still another embodiment of the instruction word memory/translation unit in the processor shown in Fig. 1; Fig. 7 is a block diagram showing an embodiment of the instruction word memory/translation unit derived from Fig. 6; Fig. 8 is a block diagram showing separately the functions of the instruction word memory/translation unit in Fig. 3; Fig. 9 is a block diagram showing an embodiment of the instruction word memory/translation unit shown in Fig. 8; Fig. 10 is a timing chart showing the signals at various portions of the instruction word memory/translation unit shown in Fig. 9; Fig. 11 is a block diagram showing in detail the instruction word memory means in Fig. 9; Fig. 12 is a schematic diagram of the control circuit shown in Fig. 11; Fig. 13 is a block diagram showing another embodiment of the instruction word memory means in Fig. 9; Fig. 14 is a diagram showing the control status of data input/output control on the first-in-first-out basis for the instruction word memory means in Fig. 13; Fig. 15 is a schematic diagram showing another embodiment of the memory for temporarily storing instruction words in the instruction word memory means in Fig. 11; Fig. 16 is a schematic diagram of the control circuit for controlling the input/output of the memory shown in Fig. 15; Fig. 17 is a block diagram showing an embodiment of the control circuit in the instruction word memory means in Fig. 11 for setting the head of data always at the high-order bit for the case where data in the instruction word temporary memory is handled in half-word length; Fig. 18 is a schematic diagram showing part of the flip-flop in Fig. 17: Fig. 19 is a timing chart showing the operation of the flip-flop shown in Fig. 18; Fig. 20 is a schematic diagram showing an embodiment of the code reference means, code arrangement information memory means and arrangement means shown in Figs. 8 and 9; DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 2 shows an embodiment of this invention, which is applied to a microcomputer 10 constructed on a single semiconductor substrate. The arrangement includes a central processing unit 101 as a nucleus, a main memory 102, a peripheral circuit 103 having the timer function and input/output function, a direct memory access controller 104, and an address translator 105. A processor section 20 enclosed by the dashed line in Fig. 2 will be described in detail in connection with Figs. 1 and 3. Fig. 1 shows an embodiment of the processor section 20, and it consists of an instruction word memory/translation unit 201, a microprogram memory/control unit 202 including a microprogram ROM (Read Only Memory) as a principal element, a decoder unit 203, an operation unit 204, a bus interface unit 205, a first main memory 206 operative for reading and writing, a second memory 207 operative for only reading, an address input/output buffer 2082, a data input/output buffer 2083, a clock and power supply buffer 2084, and an input/output buffer 2081 for signals, except the address/data clock and power supply, transmitted or received by the processor section 20 to/from the other functional blocks 103, 104 and 105 in Fig. 2. The following describes the processor operation from instruction fetching up to instruction execution with reference to Fig. 1. (1) Instruction fetching The contents of the program (instruction) fetching register (instruction address register) in the bus interface unit 205 are read out over the bus 212 into the main memories 206 and 207 in the processor 20 and, at the same time, into the address input/output buffer 2082 so that the contents are sent out over the bus 222 outside of the processor 20. An instruction word is read out of the first main memory 206 or second main memory 207 by being addressed by the above input onto the bus 213, or an instruction word on the bus 223 is read in through the data input/output buffer 2083 onto the bus 213. Information on the bus 213 is fed into the instruction word memory/translation unit 201. (2) Instruction latching and translation The instruction word received by the instruction memory/translation unit 201 is held in it and at the same time decoded into information to be sent to the microprogram memory/control unit 202. (3) Microinstruction read-out The microprogram memory/control unit 202 receives the information provided by the instruction word memory/translation unit 201 over the bus 231, and sends it as a microinstruction string over the bus 232. (4) Microinstruction decoding The microinstruction from the microprogram memory/control unit 202 is sent over the bus 232 into the decoder unit 203, which decodes the microinstruction into signals 233 which directly control the operation unit 204 and signals 234 which directly control the bus interface unit 205. (5) Operation execution The operation unit 204 implements data operations specified by the signals 233. The bus interface unit 205 performs the timing control for data transfer within the processor 20 or between the processor 20 and other functional blocks using the bus 211, input/output buffer 2081, bus 221 and signal lines 235 and 236. The clock and power voltage supplied to the buffer 2084 are distributed to the units using a signal line 214. Fig. 3 shows an example of the arrangement of the instruction word memory/translation unit 201, microprogram memory/control unit 202, decoder unit 203 and operation unit 204. The instruction word transferred over the bus 213 to the instruction word memory/translation unit 201 is held temporarily in the instruction word memory 301 and then transferred to the first instruction decoding means, i.e., the instruction decoder 302. Fig. 4 shows typical instruction formats of instruction words read into the instruction memory 301. (1) Operational instructions An instruction of this type implements an operation between a first operand specified by the first operand code and a second operand specified by the second operand code and stores the result in the location of the second operand. The type of operation specified in the operation code designates one of the arithmetic or logic operations. (2) Branching instructions An instruction of this type causes the program sequence to branch to the program address indicated by an operand specified by the first operand code upon fulfillment of the branch condition given in the operation code. If the branch condition is not met, the instruction causes the program sequence to proceed to the next instruction word. (3) Bit manipulating instructions An instruction of this type tests the value of a bit position specified by the bit number, i.e., a first operand, in the second operand specified by the second operand code, and memorizes the bit value. Thereafter, the instruction implements one of operations (clear, set, change, test) indicated by the bit operation type in the operation code for the specified bit, and stores the result in the corresponding bit position of the second operand when necessary. The instructions categorized in (1), (2) and (3) are systematized at the sacrifice of orthogonality due to the restriction in word length of an instruction as a result of formatting for the intended functions in a limited word length in accordance with a certain rule. The embodiment shown in Fig. 3 operates in the instruction decoder 302 to decode instruction words read out of the instruction word memory 301 so that information of various kinds necessary for the instruction execution is converted into instructions having a complete orthogonal code system (will be termed "intermediate machine words" hereinafter). Each intermediate machine word has an operation code for specifying the operation to be executed and information bits representing some operand specifier codes which identifies the location in the main memory where the operand is contained. The intermediate machine word is stored in the memory 303, and then fed to the microprogram memory/control unit 202 and the second instruction decoding means, i.e., the decoder unit 203. Some of intermediate machine words include at least one operand specifier, and information of as to whether the operand indicated by the operand specifier is a source operand or a destination operand is entirely expressed in the operation code. Among information expressing the operation code and operand specifier, information of various kinds about the intermediate machine word except for the information 3031 that needs to be decoded by the microprogram memory/control unit 202 is in one-to-one correspondence to the decoders 2031, 2032, 2033, 2034 and 2035 in the decoder unit 203 which can be controlled by the microinstruction 232 (see Fig. 3). Control signals 233 produced by these decoders in the decoder unit 203 control the operation unit 204 so as to execute an intended operation indicated by the intermediate machine word. Fig. 5 shows another embodiment of the instruction word memory/translation unit, in which there are two instruction decoders for decoding an instruction held in the instruction memory means 301 into an intermediate machine word. In case the main memory storing user programs stores instruction words expressed in two different kinds of instruction systems A and B, i.e., different instruction process (instruction functions) for the same binary instruction code, the system is provided with an instruction decoder 302 for decoding instructions in instruction system A and an instruction decoder 502 for decoding instructions in instruction system B. Information created by the instruction decoder 302 is sent over the bus 3021 to the multiplexer 503. Similarly, information created by the instruction decoder 502 is sent over the bus 5021 to the multiplexer 503. The multiplexer 503 selects one of the buses 3021 and 5021 basing on the contents of the flip-flop 504, and stores the selected contents in the memory 303. In this case, if the instructions expressed in the instruction code of instruction system A and expressed in the instruction code of instruction system B have the same process even though their binary codes are different, the two instruction decoders 302 and 502 generate exactly the same intermediate machine word. Namely, if instruction words of different instruction systems have the same instruction function, they have the same information stored in the memory 303, the most hardware 500 in the processor 20 controlled by the intermediate machine word (hardware in the processor 20 excluding the instruction memory/translation unit 201 in Fig. 2) can be used and controlled commonly by instruction words of different instruction systems. The flip-flop 504 is set to the predetermined signal level which is received at the terminal 505 and detected by the control circuit 506 when the processor 20 is reset. The terminal 505 uses the lowest-order bit of the address bus. Fig. 6 shows still another embodiment of the instruction word memory/translation unit 201, in which instruction words read into the instruction memory 301 through the bus 213 and intermediate machine words created by the instruction decoder 302 and instruction decoder 502 and stored in the memory 303, shown in Fig. 5, are stored together in the main memory 600. The main memory stores instruction codes of two instruction systems, one type of codes being fed via the instruction memory 301 to the instruction decoder 302, translated into intermediate machine words by the decoder 302, fed over the bus 3021 to the multiplexer 603, selected by the multiplexer 603 and stored in the memory 303, while another type of codes being fed through the instruction memory 601 and bus 6011 to the multiplexer 603, selected by it and stored in the memory 303. The multiplexer 603 selects one of information on the bus 3021 and bus 6011 depending on the contents of the flip-flop 604. The instruction words stored in the main memory 600 have the definition of the instruction which can switch the multiplexer 603, and by executing the instruction the flip-flop 604 can be controlled through the control line 6041. The flip-flop 604 may be controlled by detecting the signal level received at the terminal 605 by the control circuit 606 as shown in Fig. 7. The multiplexer 603 and memory 303 are designed to control the contents of the instruction memory 601 in byte (8 bits) units, allowing applications which do not need the instruction memory 601 to enter information to the multiplexer 603 in the same word length as of the bus 213. Fig. 8 is a block diagram showing separately the functions of the instruction memory/translation unit 201 shown in Fig. 3. The functions of the blocks are as follows. (1) Instruction memory means 301 This is a buffer memory for temporarily holding an instruction word read out from the main memory over the bus 213. An instruction word is read out of the main memory in advance so as to allow high-speed pipeline processing. (2) Code collation means 802 The arrangement of the operation code and operand code differs depending on each instruction word. On this account, an instruction word read out of the instruction memory means 301 over the bus 3011 is collated with the code pattern which has been defined in the code collation means 802 so that the coincidence is detected. (3) Code arrangement information memory means 803 Code arrangement information for translating an instruction word into an intermediate machine word having the orthogonal instruction format is defined and stored in this memory means. The defined arrangement information is read out of the memory means over the bus 8031 in response to the signal 8021 from the code collation means 802. (4) Arrangement means 804 In order to translate an instruction code entered through the bus 3011 into an intermediate machine word having the orthogonal instruction format, arrangement of the instruction code is carried out in accordance with information on the bus 8031. After translation, the intermediate machine word has its operation code for specifying the operation to be executed and its operand specifier for identifying the memory location containing the operand being arranged in separate bit positions. Some instructions except those which do not need operands include at least one operand specifier. Fig. 9 shows an embodiment of the instruction memory/translation unit shown in Fig. 8, and it consists of an instruction memory means 301 made up mainly of a first-in-first-out (will be termed simply "FIFO" hereinafter) memory 901 and its control circuit 911, a code collation means 802 and code arrangement information means 803 made up mainly of programmable logic arrays (will be termed simply "PLA" hereinafter), and an arrangement means 804 made up mainly of a switch array using, for example, metal oxide semiconductor (will be termed "MOS" hereinafter) transistors. Fig. 10 shows the timing relationship of signals a through j in Fig. 9 together with the basic clocks ₁ and ₂. Initially, an instruction word read out of the main memory is fed over the bus a and latched in the data buffer b. The latched data is transferred over the bus 213 to the FIFO memory 901 in synchronism with the basic clock ₂. At this time, the control circuit 911 controls the writing of data on the bus 213 into the FIFO memory through the signal line 9110. At the same time, an instruction to be executed is read out of the FIFO memory 901 onto the bus c and it is latched in the FIFO buffer 921. The code collation means 802 and code arrangement information memory means 803 are formed of dynamic PLAs 902 and 903 made solely of NMOS transistors, except for the precharging circuit and driver. On this account, an input latch 912 and output latches 913 and 914 are added. The timing of signals after the signal d has been entered to the latch 912 until the output h of the latch 913 and the output i of the latch 914 are determined is as shown in Fig. 10. The signal h is the instruction code prior to arrangement, and the signal i is arranged information. The arrangement means 804 produces a signal j by making arrangement for the signal h in accordance with the signal i. Fig. 11 shows in detail the instruction memory means in Fig. 9. The FIFO memory 901 is formed of a single-port random access memory (will be termed simply "RAM" hereinafter). The data lines 1100 are charged by the precharging circuit during the period of the basic clock ₁, and they carry data during the period of the basic clock ₂. Sense amplifiers are provided for the amplification of read-out data. The control circuit 911 consists of a write pointer (shown by WP in Fig. 11) for specifying the write location in writing an instruction word on the bus 213 into the FIFO memory 901, a read pointer (shown by RP in Fig. 11) for specifying the read location in reading out an instruction word from the FIFO memory 901, and +1 adders for incrementing the pointers. Fig. 12 is a logic circuit diagram showing in detail the control circuit 911 shown in Fig. 11. The figure shows an embodiment of the case where the FIFO memory 901 has a capacity of eight words (one word has the same word length as of the bus 213), i.e., each of the write pointer and read pointer is of three bits. A bus 9111 is provided for transferring the contents of the write pointer and read pointer. Both pointers can be reset by the RESET signal which becomes active when the FIFO memory 901 is cleared by the reset operation for the processor 20 or when a prefetched instruction in the FIFO memory is invalidated due to the execution of a branch instruction. Signal 1200 is the signal indicating that there is no memory space in the FIFO memory 901 for fetching an instruction from the main memory, i.e., the FIFO memory 901 is filled with a prefetched instruction word and there is no space physically. Signal 1201 is the signal indicating that there is a memory space of eight words available in the FIFO memory 901 for fetching instructions from the main memory, i.e., there is no instruction word prefetched in the FIFO memory 901. Signal 1202 is the incrementing signal for the write pointer, signal 1203 is the incrementing signal for the read pointer, signal 1204 is the signal outputting the value of the write pointer onto the bus 9111, and signal 1205 is the signal outputting the value of the read pointer onto the bus 9111. Fig. 13 shows another embodiment of the instruction memory means 301 in Fig. 9, in which the FIFO memory 901 is controlled by the PLA. The arrangement implements concurrently the control for fetching an instruction word from the main memory to the FIFO memory through the 32-bit bus and the control for transferring the contents of the FIFO memory to the instruction decoder in 16-bit word length. The PLA which controls the data input/output to/from the FIFO memory satisfies the FIFO control state diagram shown in Fig. 14. The PLA 1300 changes in its state in the range of ten states from S₁ to S₁₀ as shown in Fig. 14, and it becomes the S₁ state from any state by receiving the FIFO reset signal. The states S₁ and S₆ indicate that the FIFO memory 1301 is empty (indicated by E in Fig. 14), i.e., no instruction word is yet fetched to the FIFO memory. The states S₃, S₅, S₈ and S₁₀ indicate that the FIFO memory is full (indicated by F in Fig. 14) and there is no space in the FIFO memory 1301 for fetching a new instruction word. The state of the PLA (S₁-S₁₀) is memorized in the state memory 1302, which is revised by the signal 13002 when the PLA 1300 issues a new state. Fig. 15 shows another embodiment of the FIFO memory 901 shown in Fig. 11, in which the FIFO memory 901 is controlled for reading and writing through the provision of the input data word length (number of bits of the bus 213) twice the output data word length. The arrangement includes two word lines (15001 and 15002) for the read/write control of memory cells 1110. Fig. 16 is a detailed logic circuit diagram of the control circuit 1510 for controlling the input/output operation of the FIFO memory 1500 in Fig. 15. A feature of this arrangement as compared with Fig. 12 is the presence of two read pointers (RP H and RP L ), which allows the handling of data in the FIFO memory in both half-word length and full-word length. Fig. 17 shows as an example the arrangement of the control circuit for setting the head of data always at the high-order bit in handling data in the FIFO memory 1500 in half-word length. Initially, the flip-flop 1700 is reset by the signal 17001 at a time point when the FIFO memory 1500 and control circuit 1510 are reset (state 0). Thereafter, the flip-flop 1700 selects the latch 1702 for the output destination. In case data in the FIFO memory 1500 is treated in half-word length, the flip-flop 1700 is set (state 1) by the signal 17002. At this time, the flip-flop selects the latch 1701 for the output destination. In case data in the FIFO memory 1500 is treated in half-word length, the flip-flop 1700 is reset (state 0) by the signal 17002. By repeating these operations the head of data can be known. Fig. 18 shows in detail part of the flip-flop shown in Fig. 17, and Fig. 19 shows its operation on a timing chart. Fig. 20 shows an embodiment of the code collation means 802, code arrangement information memory means 803 and arrangement means 804 shown in Figs. 8 and 9. Signal lines d, e, f, g, h, i and j correspond to the signals referred to by the same symbols in Fig. 9, and their timing relationship is shown in Fig. 10. The code collation means 802 is formed of an AND-type dynamic PLA, while the code arrangement information memory means 803 is formed of an OR-type dynamic PLA. The arrangement means 804 is made of n-channel MOS transistors as shown in the figure. The most noticeable feature of the arrangement is that instead of generating signals to be input to the microprogram memory/control unit 202 and decoder unit 203, i.e., information j to be stored in the memory 303, by decoding an instruction word (signal line d) to make a new binary code (identical to information j) different completely from the instruction word, information j is created by using part of the binary code expressing the instruction word or completely arranging again the code. Another feature is that for the arrangement of the binary code of an instruction word, arrangement information is defined so that instruction words having the completely same procedure of the arrangement format will fall in the same arrangement even if their codes are completely different. This embodiment realizes the function of the conventional instruction decoder for generating the microprogram address to be inputted to the microprogram memory/control unit from the instruction word using the hardware structure about 1/5 - 1/10 in scale as compared with the conventional decoder.

Claims: A data processing system in which at least one of a plurality of instruction words including operation information for specifying an operation to be executed is an instruction word including at least one piece of operand specifying information for identifying a location of a main memory (102) at which an operand is contained, said operand being processed in response to said instruction word, said system comprising: a) instruction word memory means (301, 1500) for storing at least one instruction word obtained by one reading operation of said main memory; b) first instruction decoding means (302, 502) connected to said instruction word memory means (301, 1500) for arranging an instruction word read out of said instruction word memory means into an intermediate machine word having a completely orthogonal code and outputting said intermediate machine word; c) second memory means (303) connected to said first instruction decoding means (302, 502) wherein said second memory means stores said intermediate machine word outputted by said first instruction decoding means; and d) second instruction decoding means (2030, 2035) connected to said second memory means (303), for decoding the content of said second memory means to generate a signal for controlling an operation unit, said operation unit performing operations based on said operation information; said system being operative to extract operation information and operand specifying information included in said instruction word read from said main memory, arrange said information in said second memory means, and implement processing in accordance with contents of said second memory means. A data processing system according to claim 1, wherein said first instruction decoding means (302, 502) detects positions of operation information and operand designating information included in an instruction word and extracts the operation information and operand specifying information separately; and said second memory means (303) is connected to said instruction word memory means (301, 1500) and has predetermined bit positions for storing the operation information and operand specifying information. A data processing system according to claim 1, wherein said main memory has contents expressed in instruction words having at least two kinds of instruction formats of different instruction binary codes even though instruction functions of said instruction words are equal; said first instruction decoding means includes a plurality of instruction decoding means (302, 502) connected to said instruction word memory means (301, 1500) for detecting positions of operation information and operand specifying information included in an instruction word, and extracting operation information and operand specifying information separately, said plurality of instruction decoding means being in correspondence to a plurality of instruction formats of instruction words in said main memory, a multiplexer (503, 603) of selecting one of a plurality of outputs corresponding to said plurality of instruction decoding means, and control means (506) for controlling said multiplexer; and wherein said operand is processed in response to said instruction words having at least two instruction formats. A data processing system according to claim 3, wherein said multiplexer control means (506) controls said control means by executing an instruction in said main memory or an instruction supplied from outside said system. A data processing system according to claim 2, wherein said first instruction decoding means comprises: a first bus (3021) for transferring information which has been extracted and arranged for storing operation information and operand specifying information included in an instruction word read out of said main memory in said predetermined bit positions of said second memory; a second bus (6011) for connecting said second memory with said main memory; a multiplexer (603) operative to select one of said first bus and said second bus; and a control circuit (604, 606) operative to control said multiplexer. A data processing system according to claim 5, wherein said multiplexer control circuit (604, 606) controls said control means by executing an instruction in said main memory or an instruction supplied from outside said system. A data processing system according to claim 5, wherein said main memory for storing instructions and operands and said data processor are constructed on a single semiconductor substrate. A data processing system according to claim 1, wherein said first instruction decoding means is connected to said instruction word memory means and generates addresses of a microprogram memory by decoding said instruction word, said first instruction decoding means comprising: code collation means (802) for collating an instruction code with predetermined information to detect the coincidence; code arrangement information memory means (803) which receives a result from said code collation means and defines arrangement information for changing whole or part of the instruction code; and arranging means (804) connected to said code arrangement information memory means (803) for arranging the instruction code in accordance with said arrangement information, wherein a result from said arranging means in correspondence to said instruction code is an address of said microprogram memory. A data processing system according to claim 8, wherein at least one of said code collation means (802) and code arrangement information memory means (803) is formed of a programmable logic array (902, 903). A data processing system according to claim 8, wherein said code collation means (802) is formed of a random access read/write memory constructed of memory cells capable of detecting coincidence of a memorized value with a value on data lines. A data processing system according to claim 1, wherein said instruction word memory means (1500) sequentially stores at least one instruction word in instruction words read successively from said main memory, said instruction word memory means comprising a memory section for storing an instruction word and a control section for controlling the data read/write operation for operation for said memory section, said instruction word memory means being capable of reading out data in a data length half a data length used in a single write operation. A data processing system according to claim 11, wherein said memory control section is formed of a programmable logic array.

Inventors: BABA SHIROU, KIDA HIROYUKI, MAEJIMA HIDEO, MASUDA IKURO, BABA, SHIROU, KIDA, HIROYUKI, MAEJIMA, HIDEO, MASUDA, IKURO
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1986
Main classification: G06F9
IPC codes: G06F9, G06F15