Output circuit device with stabilized potential

Abstract: An output circuit device according to the present inven­ tion comprise first and second circuit means (1, 3) both hav­ ing first and second type MOS transistors connected in pa­ rallel, and a load capacitor means (13) connected between the output terminal and the ground for charging and dis­ charging electric charge of an output signal. The sources of said first and second type MOS transis­ tors are connected to a first and second power supply re­ spectively. The second circuit means is connected between the out­ put of said first curcuit means and an output terminal. The sources of the first and second type MOS transistors in the second circuit means are connected to the first and second power supplies respectively. The first and second type MOS transistors have a first threshold voltage level. Undershoot and overshoot phenomena are suppressed when the output potential of the first and second type MOS transistors in the second circuit means reaches the threshold voltage level.

Description: The present invention relates to an output circuit device, more particularly to an output circuit device which can realize stabilization of the output potential and the power supply potential. In the recent semiconductor devices, there has been pushed increases in the degree of integration and density to reduce the size of the chip, as well as there is observed a tendency of increasing the driving capability of transistors to make their operation fast. In order to reduce the chip size, it is necessary to make the width of the wirings formed by aluminum or the like small. By the reduction in the width of the wiring, the inductive load that exists in the wiring, namely, inductance, will have to be increased. Further, when the current driving capability is increased by increasing the size of the transistor, there will be generated problems that are caused by the increase in the inductive load of the wiring. This problem will now be described by making reference to Figs. 1 and 2. Figure 1 shows an example of configuration of a general inverter circuit that takes into account of the inductance components of the wirings for the power supply and the output. It consists of a P-channel MOS transistor (PMOS transistor) 101 and an N-channel MOS transistor (NMOS transistor) 103. The source terminal of the PMOS transistor 101 is connected to a high level voltage source V DD that supplies a potential V DD via an inductance 105 that exists in a power supply wiring made of aluminum, and the source terminal of the NMOS transistor 103 is connected to a low level voltage source V SS that supplies a potential V SS (normally OV) via an inductance 107 that exists in a power supply wiring made of aluminum. Further, the PMOS transistor 101 and the NMOS transistor 103 have both of their gate terminals connected to the input terminal IN that inputs a signal to be inverted, and at the same time, their respective drain terminals are connected to the output terminal OUT via an inductance 109 that exists in the output wiring made of aluminum, and the output terminal OUT is connected to a load capacitor 111. When a low level (potential V SS ) signal is input to the input terminal IN, the PMOS transistor 101 will become on-state and the NMOS transistor 103 will become off-state. Then, a current flows into the load capacitor 111 from the high level voltage source V DD via the PMOS transistor 101, bringing the output terminal OUT to the high level (potential V DD ). On the contrary, when a high level signal (potential V DD ) is input to the input terminal IN, the PMOS transistor 101 will be brought to off-state and the NMOS transistor 103 to on-state. Then, charge accumulated in the load capacitor flows into the low level voltage source V SS via the NMOS transistor 103, bringing the output terminal OUT to low level (potential V SS ). Therefore, by the operation described above, there will be output from the output terminal OUT a signal which is the inversion of the signal that was input to the input terminal IN. Now, in an inverter circuit with the above configuration, when the current driving capability of the transistors is enhanced by increasing the transistor size, in order to have a quickly inverted output potential, the on-resistance of the transistors become small, and there will be formed, between the high level voltage source V DD and the load capacitor 111, or between the low level voltage source V SS and the load capacitor 111, a resonance circuit that consists of the load capacitor and the inductance that exists in the power supply wiring and the output wiring. Then, as shown in Fig. 2, when the input potential changes from potential V SS to potential V DD , the NMOS transistor 103 becomes on-state, and the output potential drops from potential V DD to potential V SS due to the rapid flow of change that was accumulated in the load capacitor 111 to the low level voltage source V SS , a transient current flows in the vicinity of potential V SS , giving rise to the so-called undershoot phenomenon. On the constrary, when the output potential is raised from potential V SS to potential V DD by the rapid charging due to flow of a current to the load capacitor 111 from the high level voltage source V DD , a transient current flows in the vicinity of potential V DD , giving rise to the so-called overshoot phenomenon. As a result, the output potential varies temporarily immediately after it is inverted, giving rise to a problem of transmitting signals at erroneous potentials. Furthermore, it causes variations in the high level voltage source V DD and the low level voltage source V SS , which leads to a fear of generating malfunctions in the circuit through variations in the input and output levels of the other elements that are connected to the same power supply wiring. EP-A-0 121 217 describes an output buffer circuit which has a data input terminal which receives logic data, load and drive transistors, a driver for selectively turning on the transistors in accordance with the logic value of the logic data, a data output terminal which is connected to a power source terminal of the VDD level through a current path of the load transistor and is grounded through a current path of the drive transistor and a capacitor connected as a load to the data output terminal. The output buffer circuit further has a transition detector circuit for generating a pulse signal in response to a change in level of each of address signals and a preset circuit for supplying, in response to the pulse signal, a charge or discharge current to the capacitor while a voltage at the data output terminal is not at the VDD2 level. JP-A-58-47323 describes a circuit similar to Fig. 5 (described later) with an output between the control unit 15 and second inverting unit 3. The use of three sets of NMOS inverters results in a hysteresis circuit suited to integration. An object of the present invention is to provide an output circuit device which makes it possible to improve the stability in the output potential and the power supply potential. Another object of the present invention is to provide an output circuit device which is capable of suppressing the overshoot and the undershoot phenomena in the output potential. Another object of the present invention is to provide an output circuit device which can suppress the transient current that may be generated during charging or discharging of a load that is connected to the output terminal, by controlling the driving capability of the output circuit device in response to the output potential. The objects of the invention are solved by an output logic circuit comprising: a main logic circuit for producing a logic level at its output terminal in response to an input logic level at its input terminal, said output terminal being connected to a capacitive load; a subordinate logic circuit having first and second input terminals and an output terminal connected to the output terminal of said main logic circuit; a control logic circuit having a first input terminal connected to the output terminal of said main logic circuit, wherein said control logic circuit outputs, in response to a change in logic level at the input terminal of said main circuit, to said subordinate logic circuit such a logic signal that said subordinate logic circuit operates to output the same logic level as said main logic circuit will output in response to the change; characterized in that said control logic circuit has a second input terminal connected to the input terminal of said main logic circuit and first and second output terminals connected to the first and second input terminals of said subordinate logic circuit; said control logic circuit outputs in response to said change after a delay time; and said control logic circuit outputs, when the logic level at the output terminal of said main logic circuit becomes the same as the logic level at the input terminal of said main logic circuit, to said subordinate logic circuit such a signal that the output terminal of said subordinate logic circuit is put in a high impedance state. The main logic circuit has a first type MOS transistor and a second type MOS transistor that are connected in parallel to each other, the source of the first type MOS transistor is connected to a first power supply, the source of the second type MOS transistor is connected to a second power supply, and the gates of the first and the second type MOS transistors are connected in parallel to the input terminal. Further, the subordinate logic circuit has at least a first type MOS transistor and a second type MOS transistor that are connected in parallel to each other, as well as it is connected between the output side of the main logic circuit and the output terminal, with the source of the first type MOS transistor of the subordinate logic circuit connected to the first power supply, the source of the second type MOS transistor of the same circuit means connected to the second power supply, and the first and the second MOS transistors having a first threshold voltage level. These and other objects, features and advantages of the present invention will be more apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings. Fig. 1 is a circuit diagram for a prior art inverter circuit; Fig. 2 is a graph for showing the input and output characteristics of the inverter circuit shown in Fig. 1; Fig. 3 is a circuit diagram for a first example of an inverter circuit; Fig. 4 is a graph for showing the input and output characteristics of the inverter circuit shown in Fig. 3; Fig. 5 is a circuit diagram for a second example of an inverter circuit; Fig. 6 is a graph for showing the input and output characteristics of the inverter circuit shown in Fig. 5; Fig. 7 is a circuit diagram for a third example of an inverter circuit; Fig. 8 is a circuit diagram for a fourth example of an inverter circuit; Fig. 9 is a circuit diagram for a buffer circuit; Fig. 10 is a circuit diagram for a fifth example of an inverter circuit; Fig. 11 is a graph for showing the input and output characteristics of the inverter circuit shown in Fig. 10; Fig. 12 is a circuit diagram for a first embodiment of the inverter circuit in accordance with the present invention; Fig. 13 is a graph for showing the input and output characteristics of the inverter circuit shown in Fig. 12; Fig. 14 is a circuit diagram for a second embodiment of the inverter circuit in accordance with the present invention; Fig. 15 is a graph for showing the input and output characteristics of the inverter circuit shown in Fig. 14; Fig. 16 is a circuit diagram for a third embodiment of the inverter circuit in accordance with the present invention; Fig. 17 is a circuit diagram for the buffer circuit for a fourth embodiment of the present invention; Fig. 18 is a circuit diagram for a fifth embodiment of the inverter circuit in accordance with the present invention; and Fig. 19 is a circuit diagram for a sixth example of the inverter circuit in accordance with the present invention. Referring to Fig. 3, an inverter circuit is shown. The inverter circuit comprises a first inverting unit 1 which inverts a signal that is input from the input terminal IN, a second inverting unit 3 driving of which is controlled by the output potential, and which assists the inverting operation that is performed by the first inverting unit 1, and a load capacitor 13 which is connected to the output terminal OUT. The first inverting unit 1 consists of a first P-channel MOS type transistor (which will be called "first PMOS transistor" hereinafter) 5 and a first N-channel MOS type transistor (which will be called "first NMOS transistor" hereinafter) 7. The first PMOS transistor 5 and the first NMOS transistor 7 have their respective gate terminals connected to the input terminal IN to which is input a signal to be inverted, and their respective drain terminals connected to the output terminal OUT which outputs the signal that is inverted. Further, the source terminal of the first PMOS transistor 5 is connected to a high level voltage source V DD that supplies a potential V DD , and the source terminal of the first NMOS transistor 7 is connected to a low level voltage source V SS that supplies a potential V SS (normally 0V). The second inverting unit 3 consists of a second N-channel MOS type transistor (called "second NMOS transistor" hereinafter) 9 and a second P-channel MOS type transistor (called "second PMOS transistor" hereinafter) 11. The second NMOS transistor 9 and the second PMOS transistor 11 have both of their respective gate terminals and drain terminals connected to the output terminal OUT, the source terminal of the second NMOS transistor 9 is connected to the high level voltage source V DD , and the source terminal of the second PMOS transistor 11 is connected to the low level voltage source V SS . In addition, the output terminal is connected to the load capacitor 13. Next, the operation of the first example of an inverter with the above configuration will be described by making reference to Fig. 4. First, the case in which the input potential of the input terminal IN is changed from low level (potential V SS ) to high level (potential V DD ), as shown in Fig. 4 will be described. It should be noted that prior to this change, the first PMOS transistor 5 and the second NMOS transistor 9 were in on-state, the first NMOS transistor 7 and the second PMOS transistor 11 were in off-state, the load capacitor 13 is charged by the feeding from the high level voltage source V DD , and the output potential was in high level (potential V DD ). When the high level signal input to the input terminal IN is supplied to the respective gate terminals of the first PMOS transistor 5 and the first NMOS transistor 7, the first PMOS transistor 5 is shifted from on-state to off-state while the first NMOS transistor 7 is shifted from off-state to on-state. By the shift of the first NMOS transistor 7 to on-state, charge, that was accumulated in the load capacitor 13 that is connected to the output terminal OUT during the time when the output terminal OUT was on high level, flows into the low level voltage source V SS via the first NMOS transistor 7, causing the output potential to start dropping as shown in Fig. 4. When the output potential drops to the threshold voltage V t for the second NMOS transistor 9 and the second PMOS transistor 11, the second NMOS transistor 9 is shifted from on-state to off-state, while the second PMOS transistor 11 is shifted from off-state to on-state. Because of this, a part of the charge that has been accumulated in the load capacitor 13 flows into the low level voltage source V SS via the second PMOS transistor 11. In other words, when the input potential becomes the state of high level, charge that was accumulated in the load capacitor 13 is discharged via the first NMOS transistor alone, so that the output potential drops relatively slowly from potential V DD to potential V t . From potential V t to potential V SS , charge is discharged via both of the first NMOS transistor 7 and the second PMOS transistor 11, which means that the driving capability of the inverter circuit as a whole is increased, so that the output potential drops rapidly as shown in Fig. 4. Because of this, at the point in time when the second inverting unit 3 is to be operated, the output potential is dropped to potential V t by a partial discharge of the charge that was accumulated in the load capacitor 13. Therefore, the transient current is small compared with the case of discharging the charge accumulated in the load capacitor in one step so that the undershoot phenomenon can be suppressed. Next, the case in which the signal that is input to the input terminal IN is changed from high level to low level, while the output terminal OUT is in the low level state, will be described. When this low level signal is supplied to the gate terminals of the first PMOS transistor 5 and the first NMOS transistor 7, the first PMOS transistor 5 is shifted from off-state to on-state and the first NMOS transistor 7 is shifted from on-state to off-state. By the change to the on-state of the first PMOS transistor 5, a current flows from the high level voltage source V DD to the load capacitor 13 via the first PMOS transistor 5 which results in a start of rise in the output potential due to charging of the load capacitor 13, as shown in Fig. 4. When the output potential is raised to the threshold voltage V t of the second NMOS transistor 9 and the second PMOS transistor 11, the second NMOS transistor 9 is changed from off-state to on-state and the second PMOS transistor 11 is changed from on-state to off-state. Then, a part of the charge that is accumulated in the load capacitor 13 is supplied from the high level voltage source V DD via the second NMOS transistor 9. Namely, when the input potential changes from high level to low level state and the output potential changes from potential V SS to potential V t , charge is supplied from the high level voltage source V DD to the load capacitor 13 only through the first PMOS transistor 5 to charge the capacitor, resulting in a relatively slow rise in the output potential. During the rise of the output potential from potential V t to potential V DD , charge is supplied from the high level voltage source V DD to the load capacitor 13 to charge it via both of the first PMOS transistor 5 and the second NMOS transistor 9, so that the output potential is raised rapidly as shown in Fig. 4. Therefore, analogous to the case of the fall of the output potential, even if the output potential is raised rapidly by the operation of the second inverting unit 3, the transient current is small compared with the case of raising the output potential from potential V SS to potential V DD in one step, because the output potential is already raised to potential V t at the point in time when the second inverting unit 3 operates. Accordingly, the overshoot phenomenon can be suppressed. In Fig. 5 is shown a second example of an inverter circuit. Its special feature is that in the inverter circuit shown in Fig. 3 there is provided a control unit 15 that controls the operation of the second inverting unit 3 by means of the output potential, in the first half of the second inverting unit 3. It is to be noted that in the example and embodiments to be described in the following, the load capacitor that is connected to the output terminal OUT will be omitted from the figure. The control unit 15 consists of a CMOS circuit formed by a third P-channel MOS type transistor (called "third PMOS transistor" hereinafter) 21 and a third N-channel MOS type transistor (called "third NMOS transistor" hereinafter) 23. The third PMOS transistor 21 and the third NMOS transistor 23 have their respective gate terminals connected to the output terminal OUT, and their drain terminals connected to each other, and the source terminal of the third PMOS transistor 21 is connected to the high level voltage source V DD while the source terminal of the third NMOS transistor 23 is connected to the low level voltage source V SS . The second inverting unit 3 consists of a CMOS circuit formed by a fourth P-channel MOS type transistor (called "fourth PMOS transistor" hereinafter) 17 and a fourth N-channel MOS type transistor (called "fourth NMOS transistor" hereinafter) 19. The fourth PMOS transistor 17 and the fourth NMOS transistor 19 have their respective gate terminals connected to the drain terminals of the third PMOS transistor 21 and the third NMOS transistor 23, and their respective drain terminals connected to the output terminal OUT. The source terminal of the fourth PMOS transistor 17 is connected to the high level voltage source V DD and the source terminal of the fourth NMOS transistor 19 is connected to the low level voltage source V SS . Further, components with identical symbols as in Fig. 3 indicate the identical items and their description will be omitted. With such a configuration, the control unit 15 carries out the inversion operation by the means of threshold voltage V t for the third PMOS transistor 21 and the third NMOS transistor 23, and also carries out the control of the operation of the second inverting unit 3, so that the second inverting unit 3 will operate in the same way as in the first example. Therefore, the fall of the output potential from potential V DD to potential V t is carried out slow, whereas the drop from potential V t to potential V SS is rapid. Further, in the rise of the output potential, the increase from potential V SS to potential V t is carried out gently, whereas the rise from potential V t to potential V DD is carried out rapidly, as shown in Fig. 6. Accordingly, with such a configuration, similar effects as in the first example can be obtained. In addition, the source terminal of the fourth PMOS transistor 17 of the second inverting unit 3 is connected to the high level voltage source V DD and the source terminal of the fourth NMOS transistor 19 of the same unit is connected to the low level voltage source V SS , so that the second inverting unit 3 can carry out a full swing operation between potential V SS and potential V DD . It should be noted that in the first and second examples, the first inverting unit 1 and the second inverting unit 3 are turned on, at the time of inversion of the output potential, on the sides of potential that are mutually opposite with respect to the output potential. Because of this, to ensure the inversion operation, in the first example, the driving capability of the first PMOS transistor 5 has to be chosen higher than the driving capability of the second PMOS transistor 11, and also, the driving capability of the first NMOS transistor 7 has to be chosen higher than the driving capability of the second NMOS transistor 9. Further, in the second example, it is necessary to choose the driving capability of the first PMOS transistor 5 to be higher than the driving capability of the fourth NMOS transistor 19, as well as the driving capability of the first NMOS transistor 7 to be chosen higher than the driving capability of the fourth PMOS transistor 17. In Fig. 7 is shown a third example of an inverter circuit. The special feature of the example resides in that the control unit 15 shown in the second example is composed of a NOT gate 25, a NAND gate 27 and a NOR gate 29, to prevent, in the inverter circuit shown in the first and the second examples, the simultaneous operation of the first inverting unit 1 and the second inverting unit 3 on the opposite potential sides with respect to the output potential. The NOT gate has its input terminal connected to the input terminal IN of the inverter circuit, and its output terminal is connected to one end of the input terminals of the NAND gate 27 that has a two-input terminal, as well as to one end of the input terminals of the NOR gate 29 that has a two-input terminal. The other end of the input terminals of the NAND gate 27 and the NOR gate 29 is connected to the output terminal OUT, and the output terminal of the NAND gate 27 is connected to the gate terminal of the fourth PMOS transistor 17, while the output terminal of the NOR gate 29 is connected to the gate terminal of the fourth NMOS transistor 19. With such a configuration, it is arranged that when the output potential exceeds the threshold potential for the NAND gate 27 and the NOR gate 29, the second inverting unit 3 of the inverter circuit is activated so that the driving capability of the inverter circuit as a whole will become increased. Accordingly, its output potential will possess characteristics similar to what was shown in Fig. 4. Further, during the period from inversion of the input potential to the attainment of the threshold voltage V t for the NAND gate 27 and the NOR gate 29, the second inverting unit 3 is in the state of high impedance, and the first inverting unit 1 alone is operated. Therefore, the first inverting unit 1 and the second inverting unit 3 will never be turned on simultaneously on the opposite potential sides with respect to the output potential. It is to be noted that the components with identical symbols as in Fig. 5 indicate the identical items and their description was omitted. In Fig. 8 is shown a fourth example of an inverter circuit. In this inverter circuit a control unit 15 for controlling the second inverting unit 3 is provided in the first half of the second inverting unit 3, analogous to the inverter circuit shown in Fig. 7. The control unit 15 consists of a NOT gate, a NAND gate and a NOR gate. The NOR gate 31 and the NAND gate 33 have one ends of their respective input terminals connected to the input terminal IN, and have the other ends of their respective input terminals connected to the output terminal OUT via the NOT gate 35. The output terminal of the NOR gate 31 is connected via the NOT gate 37 to the gate terminal of the fourth PMOS transistor 17, and the output terminal of the NAND gate 33 is connected via the NOT gate 39 to the gate terminal of the fourth NMOS transistor 19. Further, the components with identical symbols as in Fig. 5 indicate the identical items and their description was omitted. With such a configuration, it is possible to obtain the input and output characteristics also similar to those of Fig. 7, and hence similar effects. In Fig. 9 is shown a buffer circuit. A special feature of the circuit exists in that the buffer operation is carried out by connecting a NOT gate 41 between the input terminal IN and the first inverting unit 1, and the overshoot and the undershoot phenomena in the rise and fall operations, respectively, of the output potential is suppressed by providing a control unit 15 in the first half of the second inverting unit 3. The control unit 15 consists of a NAND gate and a NOR gate. A NAND gate 43 and a NOR gate 45 have one ends of their respective input terminals connected to the input terminal IN, and the other ends of their respective input terminals connected to the output terminal OUT. The output terminal of the NAND gate 43 is connected to the gate terminal of the fourth PMOS transistor 17, and the output terminal of the NOR gate 45 is connected to the gate terminal of the fourth NMOS transistor 19. Components with identical symbols with those of Fig. 5 indicate the identical items and their description was omitted. With such a configuration, the second inverting unit 3 starts to operate when the output voltage exceeds the threshold voltage V t for the NAND gate 43 and the NOR gate 45, to increase the driving capability of the buffer circuit as a whole, and the rise and fall operations of the output potential are divided in two steps similar to the inverter circuit shown in Fig. 7. In Fig. 10 is shown a fifth example of an inverter circuit. A special feature of the circuit is that there is provided, for the output terminal OUT, a third inverting unit 3' that has the same configuration and mechanism as the second inverting unit 3, in parallel with the unit 3, the inversion operations of the third inverting unit 3' and the second inverting unit 3 are controlled by the control unit 15 based on the output potential, to vary the driving capability of the inverter circuit as a whole in three stages. The control unit 15 consists of a NOT gate, NAND gates, and NOR gates. The NAND gates 49 and 53 and the NOR gates 51 and 55 have one ends of their respective input terminals connected to the output terminal OUT, and the other ends of their respective input terminals connected to the input terminal IN via the NOT gate 47. The output terminal of the NAND gate 49 is connected to the gate terminal of the fourth PMOS transistor 17, and the output terminal of the NOR gate 51 is connected to the gate terminal of the fourth NMOS transistor 19. Further, the output terminal of the NAND gate 53 is connected to the gate terminal of a fifth P-channel MOS type transistor 17' that constitutes a third inverting unit 3', and the output terminal of the NOR gate 55 is connected to a fifth N-channel MOS type transistor 19'. With such a configuration, in the fall operation, for example, of the output potential, when the input potential changes from the low level to the high level, the first inverting unit 1 operates first, and the output potential drops from potential V DD to the threshold voltage V t1 for the NAND gate 53 and the NOR gate 55, when the third inverting unit 3' begins to operate. When the output potential drops further to the threshold voltage V t2 for the NAND gate 49 and the NOR gate 51, the second inverting unit 3 begins to operate. In this way, the driving capability of the inverter circuit is arranged to be increased successively. In a similar manner, in the rise operation of the output potential, too, the driving capability of the inverter circuit is increased successively. Accordingly, the inverter circuit in this example has the input and output characteristics as shown in Fig. 11, and it is possible to obtain the same effects as in the inverter circuit described in the third embodiment. In Fig. 12 there is shown an inverter circuit in accordance with a first embodiment of the present invention. A special feature of the circuit exists in that the control unit 15 that has an EXCLUSIVE-OR gate and an EXCLUSIVE-NOR gate that have different threshold voltages for the two input terminals, controls the operation of the second inverting unit 3, based on the output potential. With this, it is arranged that the fall and rise of the output potential is to take place slowly, by reducing the driving capability of the inverter circuit in the vicinity of potential V SS or potential V DD of the output potential. The control unit 15 consists of a NOT gate, an EXCLUSIVE-OR gate (called "EX.OR gate" hereinafter), an EXCLUSIVE-NOR gate (called "EX.NOR gate" hereinafter), a NAND gate, and a NOR gate. The respective input terminals of the EX.OR gate 59 and the EX.NOR gate 61, that have the threshold voltage of V t1 and V t2 for the two input terminals, respectively, are connected to the output terminal OUT, the output terminal of the EX.OR gate 59 is connected to one end of the input terminals of the NAND gate 63, and the output terminal of the EX.NOR gate 61 is connected to one end of the input terminals of the NOR gate 65. The other ends of the respective input terminals of the NAND gate 63 and the NOR gate 65 are connected to the input terminal IN via the NOT gate 57, the output terminal of the NAND gate 63 is connected to the gate terminal of the fourth PMOS transistor 17, and the output terminal of the NOR gate 65 is connected to the gate terminal of the fourth NMOS transistor 19. Further, the components with identical symbols as in Fig. 5 indicate the identical items and their description will be omitted. IN such a configuration, in the fall operation, for example, of the output potential, when the output potential lies between potentials V t1 and V t2 , a low level signal is output from the EX.NOR gate 61 to the NOR gate 65, the NOR gate 65 supplies, upon receipt of the low level signal, a high level signal to the fourth NMOS transistor 19 of the second inverting unit 3, and the fourth NMOS transistor becomes turned on. Therefore, the driving capability of the inverter circuit as a whole is increased, and the output potential drops rapidly. When the output potential lies between potentials V DD and V t1 and between potentials V t2 and V SS , the first NMOS transistor 7 alone of the first inverting unit 1 becomes turned on. The second inverting unit 3 becomes high impedance state, so that the output potential falls slowly. Further, in the rise operation of the output potential, analogous to the fall operation, only when the output potential lies between potential V t1 and potential V t2 , the driving capability of the inverter circuit as a whole is increased. Accordingly, in the inverter circuit of the present embodiment, there are obtained the input and output characteristics as shown in Fig. 13, and effects similar to the inverter circuit explained in the third example can be obtained. In Fig. 14 is shown an inverter circuit in accordance with a second embodiment of the present invention. A special feature of the circuit is that, similar to the second example, there is provided in the first half of the second inverting unit 3 a control unit 15 that controls the operation of the second inverting unit 3 based on the output potential. In the rise and the fall operations of the output potential, contrary to the input and output characteristics of the third example the output potential is first dropped or raised rapidly by increasing the driving capability of the inverter circuit as a whole, and the output potential is made to fall or rise slowly by decreasing the driving capability for the in-between. The control unit 15 consists of two NOT gates, a NAND gate and a NOR gate. The NAND gate 67 and the NOR gate 69 have one ends of their respective input terminals connected via the NOT gate 71 to the input terminal IN, and the other ends of their respective input terminals are connected via the NOT gate 78 to the output terminal OUT. Further, the output terminal of the NAND gate 67 is connected to the gate terminal of the fourth PMOS transistor 17, and the output terminal of the NOR gate 69 is connected to the gate terminal of the fourth NMOS transistor 19. In addition, the components with identical symbols as in Fig. 5 indicate the identical items and their description is omitted. With such a configuration, in the fall operation, for example, of the output potential, when the input potential changes from low level to high level, the first NMOS transistor is turned on. Until the output potential drops to the threshold voltage V t of the NOT gate 78, low level signals will be input to both of the input terminals of the NOR gate 69, so that the NOR gate supplies high level output signals to the fourth NMOS transistor 19 which will also become turned on. Accordingly, the driving capability of the inverter circuit as a whole is increased, and the output potential is lowered rapidly. When the output potential drops to potential V t , there will be input high level signals to the input terminal of the NOR gate 69 that is connected via the NOT gate 73 to the output terminal OUT. Therefore, low level output signals will be supplied from the NOR gate 69 to the fourth NMOS transistor 19, the fourth NMOS transistor 19 is turned off reducing the driving capability of the inverter circuit as a whole, leading to a slow drop of the output potential. In addition, in the rise operation of the output potential, similar to the fall operation, the driving capability of the inverter circuit as a whole is decreased when the output potential exceeds potential V t , and the input and output characteristics as shown in Fig. 15 will be obtained. In the input and output characteristics as shown in Fig. 15, although a large transient current flows in the beginning, after the output potential crosses potential V t , the driving capability is weakened and the transient current is suppressed. Because of this, when the output potential is in the vicinity of potential V DD or potential V SS , the transient current is reduced considerably so that it becomes possible to suppress the overshoot or undershoot phenomenon. Moreover, for elements such as a CMOS circuit that is operated based on the level of the input signal, it is possible to shorten the transmission time, as the output potential is lowered rapidly in the beginning. In Fig. 16 is shown an inverter circuit in accordance with a third embodiment of the present invention. In the third embodiment, the control unit 15 is formed by a circuit which is different from the circuit shown in the second embodiment, and the control on the operation of the second inverting unit 3 is arranged to be carried out in a way similar to the second embodiment. The control unit 15 consists of NOT gates, a NAND gate, and a NOR gate. One ends of the respective input terminals of the NOR gate 73 and the NAND gate 75 are connected to the input terminal IN of the inverter circuit, and the other ends of their respective input terminals are connected to the output terminal OUT of the inverter circuit. Further, the output terminal of the NOR gate 73 is connected via the NOT gate 77 to the gate terminal of the fourth PMOS transistor 17, and the output terminal of the NAND gate 75 is connected via the NOT gate 79 to the gate terminal of the fourth NMOS transistor 19. In addition, the components with identical symbols as in Fig. 5 indicate the identical items and their description is omitted. With such a configuration, it is possible to obtain the input and output characteristics that are similar to those shown in Fig. 15, and also the effects that are similar to the second embodiment. In Fig. 17 is shown an inverter circuit in accordance with a fourth embodiment of the present invention. In this embodiment, in the control unit 15 of the buffer circuit of the fourth example shown in Fig. 9, the input terminals of the NAND gate 43 and the NOR gate 45 that are not connected on the side of the input terminal IN of the buffer circuit are connected via the NOT gate 81 to the output terminal OUT of the buffer circuit, to construct the control unit 15 of the buffer circuit for this embodiment. In addition, the component with identical symbols as in Fig. 5 indicate the identical items and their description was omitted. With such a configuration, in the rise operation, for example, of the output potential, until the output potential arrives at the threshold voltage V t of the NOT gate 81, the first PMOS transistor 5 and the fourth PMOS transistor 17 are in on-state so that the output potential is raised rapidly by the increase in the driving capability of the inverter circuit as a whole. When the output potential becomes potential V t , the fourth PMOS transistor 17 becomes turned off so that the output potential is raised slowly because of the weakening of the driving capability. Further, in the fall operation of the output potential, analogous to the rise operation, the output potential falls rapidly in the beginning, but the output potential falls slowly when the output potential becomes potential V t . Accordingly, effects similar to the second embodiment can be obtained. In Fig. 18 there is shown an inverter circuit in accordance with a fifth embodiment of the present invention. A special feature of the circuit is that it is arranged to render the output terminal OUT a high impedance state by means of the signal states of the two input terminals that are provided in the inverter circuit. In Fig. 18, the gate terminal of the first PMOS transistor 5 that constitutes the first inverting unit is connected to the input terminal IN₁, and the gate terminal of the first NMOS transistor 7 is connected to the input terminal IN₂. The control unit 15 is constructed by NOT gates, a NAND gate, and a NOR gate, and one end of the input terminals of the NAND gate 83 is connected via the NOT gate 87 to the input terminal IN₁ of the inverter circuit, and the other end of its input terminals is connected to the output terminal OUT of the inverter circuit, and its output terminal is connected to the gate terminal of the fourth PMOS transistor 17. The NOR gate 85 has one of its input terminals connected via the NOT gate 89 to the input terminal IN₂ of the inverter circuit, the other end of the input terminals connected to the output terminal OUT of the inverter circuit, and its output terminal is connected to the gate terminal of the fourth NMOS transistor 19. In addition, the components with symbols identical to those in Fig. 5 indicate the identical items and their description was omitted. With such a configuration, when a high level signal is input to the input terminal IN₁ and a low level signal is input to the input terminal IN₂, both of the first PMOS transistor 5 and the first NMOS transistor 7 becomes turned off. Further, to one of the input terminals of the NAND gate 83 is input a low level signal via the NOT gate 87, and a high level signal is supplied from the output terminal of the NAND gate 83 to the gate terminal of the fourth PMOS transistor 17, and the fourth PMOS transistor 17 becomes turned off. Further, to one of the input terminals of the NOR gate 85 there is input a high level signal via the NOT gate 89, a low level signal is supplied from the output terminal of the NOR gate 85 to the gate terminal of the fourth NMOS transistor 19, and the fourth NMOS transistor 19 becomes turned off. Accordingly, when a high level signal is input to the input terminal IN₁ and a low level signal is input to the input terminal IN₂, regardless of the state of the output potential, the output terminal OUT becomes a state of high impedance. Further, when signals of the same phase are input to both input terminals of IN₁ and IN₂, there are obtained input and output characteristics that are similar to those of the inverter circuit of the third example shown in Fig. 7, and also the same effects as for the third example. In Fig. 19 there is shown an inverter circuit in accordance with a sixth embodiment of the present invention. A special feature of the circuit is that, in the control unit 15 in Fig. 18, the input terminals of the NAND gate 83 and the NOR gate 85, on the side that are not connected to the NOT gates 87 and 89, are connected via the NOT gate 91 to the output terminal OUT, to construct the control unit 15 for the inverter circuit for this embodiment. Analogous to the inverter circuit shown in Fig. 18, irrespective of the state of the output potential, it is arranged to be able to render the output terminal OUT to be a state of high impedance. Moreover, the inverter circuit of the present embodiment possesses input and output characteristics similar to those shown in Fig. 15, and is possible to obtain effects that are similar to those of the second embodiment. In addition, the components with identical symbols as in Fig. 18 indicate the identical items and their description was omitted. In summary, according to the present invention, the transient current that arises at the time of charging or discharging of the load that is connected to the output terminal is suppressed by controlling the driving capability of the output circuit device in response to the output potential. Therefore, it is possible to suppress the overshoot and the undershoot phenomena in the output potential, which permits to improve the stability of the output potential.

Claims: An output logic circuit comprising: a main logic circuit (1) for producing a logic level at its output terminal in response to an input logic level at its input terminal, said output terminal being connected to a capacitive load (13); a subordinate logic circuit (3) having first and second input terminals and an output terminal connected to the output terminal of said main logic circuit (1); a control logic circuit (15) having a first input terminal connected to the output terminal of said main logic circuit (1), wherein said control logic circuit (15) outputs, in response to a change in logic level at the input terminal of said main circuit (1), to said subordinate logic circuit (3) such a logic signal that said subordinate logic circuit (3) operates to output the same logic level as said main logic circuit (1) will output in response to the change; characterized in that said control logic circuit (15) has a second input terminal connected to the input terminal of said main logic circuit (1) and first and second output terminals connected to the first and second input terminals of said subordinate logic circuit (3); said control logic circuit (15) outputs in response to said change after a delay time; and said control logic circuit (15) outputs, when the logic level at the output terminal of said main logic circuit (1) becomes the same as the logic level at the input terminal of said main logic circuit (1), to said subordinate logic circuit (3) such a signal that the output terminal of said subordinate logic circuit (3) is put in a high impedance state. The output logic circuit of claim 1 wherein said main logic circuit (1) comprises a CMOS circuit. The circuit of claim 1, wherein said subordinate circuit (3) comprises a CMOS circuit. The output logic circuit device as claimed in claim 2, wherein said main logic circuit (1) has a first type MOS transistor (5) and a second complementary type MOS transistor (7) connected in series to each other the source of said first type MOS transistor (5) being connected to a first power supply and the source of said second complementary type MOS transistor (7) being connected to a second power supply and the gates of said first type and second complementary type MOS transistors (5,7) being connected in parallel to an input terminal (IN). The output logic circuit as claimed in claim 3, wherein said subordinate logic circuit (3) has at least a first type MOS transistor (17) and a second complementary type MOS transistor (19) connected in series to each other, the source of the first type MOS transistor (17) in the subordinate logic circuit (3) being connected to the first power supply, the source of the second complementary type MOS transistor (19) being connected to the second power supply and said first type and second complementary type MOS transistors (17, 19) having a first threshold voltage level. The output logic circuit as claimed in claim 5, wherein said control logic circuit consists of NAND and NOR gates (63, 65), each output of which being connected to each of the MOS transistors (17,19) in the subordinate logic circuit (3), an EXCLUSIVE-OR and EXCLUSIVE-NOR gate pair (59,61), each output of which being connected to respective inputs of said NAND and NOR gates (63,65) and an inverter (57) connected between the input terminal (IN) of the main logic circuit (1) and the other input of said NOR gate (65). The output logic circuit as claimed in claim 5, wherein said control logic circuit (15) comprises NAND and NOR gates (67, 69), each output of which being connected to each of the first and second type MOS transistors (17,19) respectively of the subordinate logic circuit (3) and each input of said NAND and NOR gates (67,69) being connected in parallel to each other, a first inverter (71) connected between the input terminal of the main logic circuit (1) and one input of said NAND gate (67) and a second inverter (78) connected between the output of said main logic circuit (1) and the other input of said NAND gate (67). The output logic circuit as claimed in claim 5, wherein said control logic circuit (15) consists of a NOR (73) and NAND (75) gate pair and first (77) and second (79) inverters connected respectively between each output of said NOR and NAND gate pair (73,75) and each control gate of the first type and second complementary type MOS transistors (17,19) in the subordinate logic circuit (3), one input of said NAND and NOR gate pair (73,75) being connected to the output of the main logic circuit (1) and the other input of said NAND and NOR gate pair (73,75) being connected to the input terminal of the main logic circuit (1). The output logic circuit as claimed in claim 5, wherein said control logic circuit (15) consists of a NAND (43) and NOR (45) pair and a first inverter (81), each output of said NAND and NOR gate pair (43,45) being connected to each control gate of the first and second type MOS transistors (17,19) in the subordinate logic circuit (3) and each input of said NAND and NOR gate pair (43,45) being connected in parallel to each other, an input of the NAND-gate being connected to the output of said first inverter (81) and said output logic circuit further comprises a second inverter (41) connected between the control gates of the main logic circuit (1) and the input terminal which is in turn connected to one input of said NAND and NOR gate pair (43,45). The output logic circuit as claimed in claim 5, wherein said control logic circuit (15) consists of a NAND (83) and NOR (85) gate pair and first (87) and second (89) inverters, each of one of the inputs of said NAND and NOR gate pair (83,85) being connected in parallel to each other and to the output terminal of the main logic circuit (1), each output of said NAND and NOR gate pair (83,85) being connected to each of the control gates of the first type and second complementary type MOS transistors (17,19) in the subordinate logic circuit (3) and each input of said first and second inverters (87,89) being connected to each of the input terminals respectively while each output of said first and second inverters (87,89) being connected to each of the other inputs of said NAND and NOR gate pair (83,85) respectively. The output logic circuit as claimed in claim 10, wherein said control logic circuit (15) further comprises a third inverter (91) connected between the output terminal of the main logic circuit (1) and the one input of said NAND and NOR gate pair (83,85).

Inventors: TANAKA YASUNORI, TANAKA, YASUNORI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H03K19
IPC codes: H03K19, H03K17