INTERCONNECTS FOR WAFER-SCALE-INTEGRATED ASSEMBLY

Abstract: An assembly is obtained by stacking plural wafer-scale-integrated boards made of silicon. Connections between levels of the assembly are made by optical signals transmitted directly through the silicon boards.

Description: INTERCONNECTS FOR WAFER-SCALE-INTEGRATED ASSEMBLY Background of the Invention This invention relates to integrated-circuit chips and, more particularly, to an assembly that comprises a stack of wafers each of which includes multiple interconnected chips. In * the integrated-circuit art, it is known to utilize a pattern of lithographically formed conductors on a semicon uctor wafer to interconnect a number of semiconductor chips and to connect the chips to input/output pads on the wafer. In some cases, the chips to be interconnected are mounted on the surface of the wafer or in recesses formed in the wafer surface. In other cases, the chips are fabricated in the wafer as integral parts thereof. Herein, all of these and similar arrangements, including arrangements that include more than one wafer, will be referred to as wafer-scale-integrated (WSI) assemblies. WSI assemblies are potentially faster than approaches based on individually packaged chips mounted and interconnected on a standard pr inted-circuit board. In such a standard assembly, the size of the chip package limits the density of circuits in a system. By contrast, in a WSI assembly, circuits can be packed extremely close together on a single wafer, thus avoiding the major size limitations imposed by package size and thereby enabling faster performance due to substantial decreases in chip interconnection lengths. The desire to achieve a high degree of parallelism in WSI architectures has led to the development of three-dimensional assemblies comprising stacks of wafers of the type described above. In such a stacked-wafer assembly, multiple vertical connections are provided between wafers. Heretofore, the only way proposed to make the aforedescribed vertical connections between stacked wafers in a WSI assembly has been to use mechanical 5 interconnects, as described, for example, in "A Cellular VLSI Architecture" by J. Grinberg et al , Computer, pages 69-81, January 1984. In practice, however, it has been exceedingly difficult to achieve reliable mechanical interconnects that exhibit sufficient Q.D robustness and satisfactory electrical characteristics to meet the demanding reguirements of a high-performance WSI assembly. Additionally, it has been found that a typical such assembly with mechanical interconnects is generally not easily repairable. 5 Thus, a need exists for improved interconnection technigues for WSI assemblies. Summary of the Invention Multiple wafers each including integrated- circuit chips are stacked to form a WSI assembly. Q . Connections are established between wafers in the assembly by sending optical signals from the surface of one wafer to the surface of another. In accordance with the invention, these signals are transmitted directly through the material of one or more wafers in the 5 assembly. Br ief Descr iption of the Drawing FIG. 1 i s a s impl ified schematic representation of a portion of a WSI assembl y compr is ing a chip-conta ining wafer and an assoc iated pl anar i zing 0 " member wh ich embody features o f the present invention ; F IG . 2 shows two o f the FIG . 1 arrangements together wi th a cover pl ate ; FIG . 3 represents the FIG . 2 components combined to form a stacked-wafer assembly; 5 and FIG. 4 ill ustrates in cross- section a portion of a spec i f ic il lustrative WSI assembly made in accordance with the pr inc iples o f the present invention . Detailed Description In accordance with the invention, plural WSI circuit boards are stacked and interconnected by optical-signal technigues. For purposes only of example, each board illustrated is a modified version of a known board in which multiple integrated-circuit chips are attached by face-down solder bonding to microminiature interconnections formed on the surface of a silicon wafer. Such known boards are described, for example, in "Wafer-Chip Assembly for Large-Scale Integration" by P. Kraynak et al , IEEE Transactions on Electron Devices, Vol. ED-15, No. 9, September 1968, pages 660-663; in "Silicon Packaging - A New Packaging Technigue" by C. Huang et al , IEEE Custom Integrated Circuits Conference, Rochester, New York, May 24, 1983, pages 142-143. In this embodiment of the invention, additional chips comprising optical emitters and detectors are also attached to the interconnections on the silicon wafers. In a WSI assembly comprising stacks of these modified boards, connections between boards are made by transmitting optical signals through the silicon material of the wafers between respective emitters and detectors. The board (FIG. 1) comprises a silicon wafer 10 having multiple chips solder bonded thereto. Only six of these chips, respectively designated by reference numerals 12 through 16, are shown in FIG. 1. Some of these chips comprise very-large-scale-integrated (VLSI) chips and others comprise optical emitters and/or detectors. In a schematic way, FIG. 1 also indicates, by dashed lines 18, that the chips 12 through 16 are interconnected. Illustratively, the interconnections 18 comprise lithographically formed power and ground conductors and X- and Y-signal conductors respectively disposed in spaσed-apart levels overlying the upper surface of the wafer 10. In one embodiment, the signal conductors comprise aluminum or copper lines each about 2 micrometers (ym) thick and approximately 10 μ wide. In some cases, it is advantageous to form the ground plane on the lower surface of the wafer 10. Such a particular illustrative case will be specified below in connection with the description of FIG. 4. In a WSI assembly of the type shown in FIG. 1 in which multiple chips are solder-bonded to an interconnection pattern on a wafer, the resulting single-wafer assembly has a nonplanar top exhibiting multiple protuberances. To facilitate stacking multiple such wafers, it is generally advantageous to planarize the wafer surface. This can be done, for example, by utilizing a planarizing member 20 of the type shown in FIG. 1. Illustratively, the member 20 of FIG. 1 also comprises a silicon wafer. The member 20 includes openings therethrough in exact registry with and slightly larger in size than the respective chips 12 through 16 on the wafer 10. The thickness of the wafer 20 is slightly greater than the extent by which the most protruding one of the chips 12 through 16 extends above the surface of the assembly. In that way, when the assembly and the member 20 are brought together into intimate contact, a planar surface devoid of protuberances (but with openings therein) is achieved. In other embodiments, the planarizing member 20 of FIG. 1 includes only recesses in the bottom surface thereof. These recesses are formed in respective registry with the chips 12 through 16 and are appropriately sized to accommodate the full height of . the chips. In that case, a truly planar top surface is realized when the member 20 and the wafer 10 are combined to form a composite WSI assembly. Various techniques are available for aligning the member 20 (FIG. 1) with respect to its associated chip-carrying wafer 10. One way of doing this is to include projections 22 through 24 on the wafer 10. These are designed to mate with corresponding openings (not shown in FIG. 1) formed in the bottom side of the member 20. FIG. 2 shows two composite WSI assemblies, each of the type represented in FIG. 1, designed to be stacked together. One assembly comprises planarizing member 26 and chip-carrying wafer 28. In this example, the wafer 28 includes seven chips mounted thereon in alignment with respective openings ir. the member 26. The other assembly, which, for example, includes five chips, comprises planarizing member 30 and chip-carrying wafer 32. For alignment purposes, projections 34 through 36 are included on the top surface of the member 30. These are intended to mate with correspon ing openings (not shown) formed in the bottom of the wafer 28. To complete the stacked assembly of FIG. 2, a protective cover plate may be added. Such a cover comprising a silicon wafer 38 is shown in FIG. 2. An assembled stack of wafers is depicted in FIG. 3. This particular illustrative stack includes the constituent elements described above and shown in FIG. 2. FIG. 4 represents a portion of an illustrative WSI assembly made in accordance with the invention. The depicted assembly comprises a silicon planarizing member 40 sandwiched between two chip-carrying silicon wafers 42 and 44. By way of example, each of the wafers 42 and 44 of FIG. 4 is shown as having two optical components mounted thereon. Thus, the wafer 42 includes optical- signal emitter 46 and optical-signal detector 48, whereas the wafer 44 includes optical-signal emitter 50 and optical-signal detector 52. In practice, each wafer in the WSI assembly may include a multitude of optical emitters and detectors. The emitters 46 and 50 comprise lasers or light-emitting diodes designed to provide optical output signals at a wavelength in the range of about 1.1-to- 10 μm. For signals in this range of wavelengths, silicon (even if highly doped to render it conductive) is relatively transparent. Thus, signals propagated downward by the emitter 46 toward the detector 52 will be transmitted through the silicon wafer 42 and the silicon member 40 in a relatively low-absorption way. Similarly, signals from the emitter 50 will be propagated upward through the member 40 and the wafer 42 in a low-absorption manner to impinge upon the detector 48. Illustratively, the emitters 46 and 50 of FIG. 4 may each comprise a laser unit designed to emit at 1.3 or 1.55 μm. Such a unit -may comprise, for example, an edge-emitting laser combined with a parabolic mirror in microminiature chip form. As represented in FIG. 4, the optical emitters 46 and 50 and the optical detectors 48 and 52 of FIG. 4 comprise standard discrete elements or monolithic arrays that are fabricated and tested as individual components and then mounted in place and interconnected (for example by face-down solder bonding) to associated circuitry on their respective wafers. Alternatively, the emitters or detectors may be fabricated in place in the wafers 42 and 44 as integral parts thereof. Thus, for example, silicon photodetectors can be made in that manner directly in the silicon wafers. And by, for instance, growing layers of gallium arsenide directly on the surfaces of the silicon wafers 42 and 44, optical emitters and detectors can then also be made in place as integral parts of the wafers. (See, for example, Applied Physics Letters 45(4) , pages 309-311, August 15, 1984, for a description of an AlGaAs double-heterostructure diode laser fabricated on a monolithic GaAs/Si substrate.) Each of the wafers 42 and 44 also typically includes multiple VLSI chips. In FIG. 4, these integrated-circuit chips are indicated by elements 54 and 56 which are representative of discrete individual chips that have been bonded and interconnected on their respective wafers. In some cases, all the integrated circuitry, except for interconnects, included on the wafers 42 and 44 of FIG. 4 are embodied in the form of discrete individual chips mounted thereon. In other cases, some or all "of the integrated circuitry is formed in surface portions of the wafers as integral parts thereof. For illustrative purposes, FIG. 4 exemplifies both approaches. Ad itionally, FIG. 4 schematically shows integrated-circuit portions 58 and 60 formed within the wafers 42 and 44, respectively. These portions constitute, for example, bipolar or metal-oxide- semiconductor driver circuitry respectively associated with and connected to the optical emitters 46 and 50. Surface regions 62 and 64 (FIG. 4) on the wafers 42 and 44 respectively represent multi-layer interconnection circuitry of the depicted WSI assembly. Thus, these regions include interleaved layers of insulating and conducting materials such as polyimide and aluminum or copper, as is well known in the art. Moreover, in those cases in which some circuitry is formed in the wafers themselves (see, for example, the portions 58 and 60) the regions 62 and 64 or some parts thereof may include additional layers of materials such as silicon dioxide and/or silicon nitride. Additionally, wafers 42 and 44 of FIG. 4 include ground planes 66 and 68 on the bottom surfaces thereof. These planes on the wafers 42 and 44 comprise, for example, 2-μm-thick layers of a conductive material such as aluminum or copper. To effect electrical connections between these ground planes and conductors in the surface regions 62 and 64, it is necessary that the wafers 42 and 44 or at least portions thereof be highly doped to render them conductive. As indicated in FIG. 4, the ground plane 66 is patterned to provide openings through which optical signals are propagated between the wafers 42 and 44 in the depicted WSI assembly. Such patterning typically enhances transmission by minimizing signal reflections and providing signal containment. In the course of mounting the optical components 46, 48", 50 ' and 52 of FIG. 4, it is important to maximize the signal transfer efficiency between these components and other parts of the depicted WSI assembly. Thus, for example, any highly absorptive or reflective layers in the surface region 62 underlying the components 46 and 48 are advantageously removed. Or, if the region 62 includes layers of materials such as silicon dioxide and/or silicon nitride underlying the components 46 and 48, it is generally advantageous where possible to control the thicknesses of these layers to render them substantially antireflective. This is done, for example, by controlling the thickness of the nitride layer to be an integral multiple of a quarter-wavelength of the propagating optical signals and by controlling the thickness of the oxide layer to be an integral multiple of a half-wavelength of these signals or by completely removing the oxide in the transmission region. The illustrative planarizing member 40 shown in FIG. 4 includes recesses 70 through 72 formed in the bottom surface thereof. These recesses are designed to completely encompass the respective components 56, 50 and 52 when the bottom surface of the member 40 is brought into intimate contact with the top surface of the eg ion .64. Advantageously, an antireflective coating 74 is included on the bottom surface of the member 40 (FIG. 4) . Further, a portion 76 of this layer is preferrably patterned to form a zone-plate lens for focusing optical signals emanating from the emitter 50 and directed at the detector 48. (Such lenses fabricated in integrated-circuit form are described, for example, in U. S. Patent No. 4,037,969.) Of course, the zone-plate lens 76 may be formed at other levels in the path between optical components or, if optical signal levels are adequate, may be left out altogether. When the member 40 and the chip-carrying wafer 44 of FIG. 4 are brought together in a WSI assembly, an air gap will invariably exist between at least some portions of the bottom surface of the member 40 and the top surface of the wafer 44, and between the member 40 and the wafer 42. To minimize - deleterious interference effects, any gaps that do exist are preferrably designed to be much greater than the wavelength of the propagating optical signals. Ad itionally, it may be advantageous to include a standard index-matching fluid in the gaps. The top surface of the planarizing member 40 of FIG. 4 includes, for example, a layer 78 of a material such as silicon nitride and a metallic layer 80. The layer 78 is proportioned to be antireflective, and the layer 80 is patterned to provide apertures that help to confine propagating optical beams. Additionally, a zone-plate lens 82 is formed in the layer 78 for the purpose of focusing optical signals emanating from the emitter 46 and directed at the detector 52. The structure of FIG. 4 also includes protuberances 84 through 86 and mating holes 87 through 89 utilized for the purpose of aligning the member 40 and the wafers 42 and 44. When assemblied, the depicted structure can be held together in any one of a number of standard ways. Thus, for example, a suitable mechanical clamp (not shown) may be employed for this purpose. Or an adhesive disposed on peripheral portions of the member 40 and the wafers 42 and 44 may be utilized to maintain the assembly together. In any case, the instrumentality used should allow for easy disassembly of the depicted structure. In that way, repair or modification of the WSI assembly is facilitated. Other wafers and planarizing members can be added to the structure shown in FIG. 4 to form a multi- wafer stack comprising a compact WSI assembly. Communication between the wafers 42 and 44 and such other wafers can be realized by including additional optical emitters and detectors (not shown) on the wafers 42 and 44. Also, the depicted optical elements 46, 48, 50 and 52 can be designed to be bilateral in nature, as indicated by dash lines in FIG. 4. ' WSI assemblies, as known, can take many forms, many of which can incorporate the present invention. Also, the assemblies can be made of other optically transparent materials, such as gallium arsenide.

Claims: Cla ims 1. A WSI assembl y compr is ing a stack o f wa fers , and CHARACTERIZED BY means (50) on or in the surface of at least one of said wafers (44) for emitting optical signals in a direction generally perpendicular to said surface in a wavelength range in which the wafer material exhibits relatively little absorption, and means (48) on or in the surface of another one of said wafers (42) in alignment with said first- mentioned means for detecting optical signals emitted therefrom and propagated through intervening wafe_ material . 2. An assembly as in claim 1 wherein each of said first- and second-mentioned wafers includes integrated circuitry (54, 56) and conductive lines (62, 64) interconnected with the respective one of the emitting means and detecting means included on the wafer . 3. An assembly as in claim 2 further comprising means (76) positioned in the path of optical signals propagated between said emitting and detecting means for focusing said signals. 4. An assembly as in claim 3 wherein said focusing means includes at least one zone plate lens. 5. An assembly as in claim 4 further comprising an antireflective (74) layer formed on at least one of said wafers and positioned in the path of optical signals propagated between said emitting and detecting means. 6. An assembly as in claim 5 further comprising a patterned layer (66) formed on at least one of said wafers and including an aperture in the path of optical signals propagated between said emitting and detecting means. 7. An assembly as in claim 2 further including a planarizing member (40) interposed between each adjacent pair of wafers in said stack. 8. An assembly as in claim 1 wherein each of said wafers is of silicon and said emitting and detecting means are designed to operate in the wavelength.range of approximately l.l-to-10 μm.

Inventors: HORNAK LAWRENCE ANTHONY, TEWKSBURY STUART KEENE, HORNAK, LAWRENCE, ANTHONY, TEWKSBURY, STUART, KEENE
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1986
Main classification: H01L31
IPC codes: G02B6, H01L23, H01L25, H01L31