BACK BIAS GENERATOR

Abstract: An improved back bias generator for an integrated circuit wherein a transistor circuit (34a) first acts as an isolation device during the charging phase of a charhe pump capacitor (30) and acts as a coupling device during a discharge phase of the capacitor, thus providing a higher back bias voltage (VBB) than is available from prior art circuits (Figs. 2 and 6) and wherein the charge pump capacitor is oriented in the circuit so that its source/drain terminal (node 10) cannot conduct to the substrate by way of the parasitic diode therebetween.

Description: BAC BIAS GENERATOR FIELD OF THE INVENTION The invention relates to an improved, higher voltage on-chip back bias generator for use in and with NMOS and CMOS technology. BACKGROUND OF THE INVENTION Prior art NMOS and even some CMOS integrated circuits are equipped with means for applying a negative voltage, V_ Ώ , to the substrate with respect to the ground node, V . Several beneficial effects are realized from that practice: First, junction capacitances are greatly reduced since the N+/P junctions have a minimum reverse bias equal to the back bias - D__D_, . Since the capacitance/voltage charac- teristic of a junction diode is inherently a square root function, the first few volts of reverse bias has the o largest effect on reduction of the junction capacitance. Second, threshold voltages are effected by the back bias with the largest effect again being seen during the first two volts of back bias (See Figure 1) because of the aforementioned square root capacitance/voltage relation¬ ship and also because of the fact that the surface doping is heavier than the substrate doping. Third, other transistor characteristics, such as punch through resistance, are also improved by increasing back bias. In the interest of conserving chip terminal connections, negative back bias is generally provided on-chip rather than being applied from off-chip. A typical prior art on-chip back bias generator is shown in schematic form in Figure 2. It comprises a one stage capacitive charge pump. An on-chip ring oscillator having a frequency of between five and twenty megahertz (not shown.) is used to drive node 10 through push-pull buffer 12, 14, 16. One deficiency of the device is illustrated by the fact that it does not provide a voltage swing fully equal to V cc - V gs . Transistor 14 is typically an enhancement mode transistor which causes a voltage drop of V 14 . During the positive swing of node 10 (see Figure 3 at reference numeral 11) , node 24 is clamped by the enhancement type transistor 28 to a voltage of + 2o above V . Thus capacitor 30, a depletion mode transistor with source and drain shorted together, is charged with its positive terminal (connected to node 10) equal to a value of + (V - τl4 ) volts and with its negative terminal (connected to node 24) equal to a value of + τ2 „, the forward drop through transistor 28. During the negative swing of node 10 (see figure 3, refer¬ ence numeral 20) , the positive capacitor terminal (connected to node 10) , previously at + (V cc - V_ 14 ) is pulled to zero volts and, thus, the negative capacitor 30 terminal goes to a voltage equal to - (V cc - V τl4 - V τ28 ) , if there is no charge transfer through transistor 34. If V βB is less negative than -(V cc - τl4 - V-, 2 Q - VT34) , there will be a charge transfer and V_ B_o is pulled negative through the diode connected enhancement transistor 34 until V „ reaches the above specified voltage, _ ( CC - V T14 ~ V T28 ~ V 34^ * For kack fa J- as generators in the prior art having charge storage nodes, a potentially harmful side effect is that parasitic diode 36 (shown in Figure 4) could be turned on. Any diode current will inject electrons into the substrate, which, due to long minority carrier lifetime, could diffuse to charge storage nodes and discharge those nodes. Parasitic diode 36 is in parallel with diode con¬ nected enhancement transistor 34 and thus this translates to the requirement that the gate-to-source = drain-to-source voltage drop, V τ34 (at V βS = + V τ34 ) , where V βS is the Bulk to Source (back bias voltage) between substrate and source of transistor 34, must be less than the forward voltage, V_, of N+/P diode 36. The current/voltage characteristic of the N+/P diode is logarithmic: V_ r = (k*T/q) * In (I/I S ) with I being the saturation current at zero bias (which is s proportional to the diode area) . The current/voltage characteristic of transistor 34 "diode" is a square law function V GS s< 3 uare root of I D g It is clear, then, that the requirement that V must be smaller than V__ is a matter of absolute current tolerance. • In order to minimize electron injection by forward current through diode 36, Figure 4, it is necessary to minimize forward voltage across diode 36 (VF) and/or mini¬ mize the area (size) of diode 36. Beside the above mentioned voltage deficiencies which reduce maximum back bias voltage output, the circuit shown in Figure 2 also has some current deficiencies. For a high output voltage, it is desirable to have the threshold voltage of transistors 28 and 34 as low. as possible. In addition, the threshold voltage of transistor 34 should be low in order to prevent the junction diode from turning on. During second phase 32 (see Figure 3) transistor 28 is supposed to be turned off, otherwise the charge of capacitor 30 would leak to V c __>> o _> rather than being transferred to V-._,>.]._,>. But during second phase 32, the back bias of transistor 28 is positive with a value of -,,. This positive back bias lowers the threshold voltage to such a degree that transis¬ tor 28 may turn on partially. To prevent that, the back bias for transistor 28 must be increased by reducing _ 4 . But during phase one 26 (see Figure 3) , transistor 34 may then leak. (Figure 3 also illustrates the excursions of node 24, see reference numeral 13.) The following relationship holds: V BB (max) = [V cc -V τl4 (at V βS ^4.0v + |v BB |) - V τ28 (at V βS = " V T34 < at V BS = " V T14 )] The dilemma of contradicting requirements is illustrated in the drawings of Figure 5a, 5b and 5c. It is also necessary to consider that transistor 34 usually is quite. large in order to minimize the forward voltage drop, but this usually translates to a requirement for a large diode area. Figure 5a addresses transistor 28 during phase two 32 (see Figure 3) and shows that: v ?4 - 3.5 volts, and V BB#~ 3* ° VOltS V ^+ 3.5 volts (large S/D voltage) V + 0.5 volts (positive 'back' bias) I l_ minimum leakage under above adverse condi- tions Figure 5b addresses transistor 34 during phase two 32 (see Figure 3) and shows that: V„ 4 ■ - 3.5 volts, and V SB = V DS ° ' 2 volts V T34 I- v l_ negligible (current through parasitic diode DX) which requires V ,. to be high. Figure 5c addresses transistor 34 during phase one 26 (see Figure 3) and shows that: ' V 24 = τ28 + 0.7 volts, and " V C__O = - 3.0 volts V Ώ , Ϊ_£ + 3.7 volts (high source drain voltage) V 0-3 = 0 volts (zero back bias) I_ c i minimum leakage (under above adverse condi- tions) One prior art attempt at a solution set as a goal getting the full value of V-., as a charge across capacitor 30. Referring to Figure 6, the positive terminal of capaci¬ tor 30 (connected to node 10) was charged fully to V by a bootstrap (not shown, but the circuit would be similar to that of Figure 2, reference numeral 19) to pull up gate 15 of the push-pull driver 14, and the negative terminal of capacitor 30 (connected to node 24) was clamped solidly to V s by disconnecting the gate of transistor 28 from its drain and pulling it to V cc during phase one 26 (see Figure 3). During phase two 32, the gate of transistor 28 is connected to the source (node 24) , but the pull-up of the gate cannot be disconnected and leaks large amounts of current from V__ to node 24. During phase one 26 (Figure 3) transistor 34 must isolate V.,-, from node 24 which requires negligible leakage of transistor 34 with +0.2V back bias, +0.2V V„ α and a drain source voltage of approximately CV-___> r ____> + V _ 4 ) = 4.0 volts.- This would require a relative high threshold for transistor 34, but the high threshold voltage would cause a high positive (forward bias) back bias during phase two 32 (Figure 3) for transistor 2-8. During phase one 26, transistor 28 operating conditions are as follows: V QS = 5.0 volts V DS = 0 volts During phase two 32, transistor 28 operating conditions are as follows: V G " " V T31 VOltS V & - 3.5 volts V GS (3.5 - V τ31 ) + 3.0 volts V SB = + ° ' 2 volts Transistor 31 is not only leaking during phase two 32 (Figure 3) , but it is solidly turned on with V g = - • V - V T34' V G = ° and V D = V CC resultin 9 in a V DS of approxi ¬ mately 9.0 volts, a V Ob of approximately + 0.2 volts and a V GS of approximately 3.2 volts. In :he particular prior art circuit, the geometry of transistor 31 was 6 by 14 microns, not very small. The purpose of resistor 33 was to limit the peak current (C*dv/dt) through capacitor 30 which is also the peak current through the parallel combination of transistor 34 and the junction substrate diode (not shown) if it were not for the large leakage current from V . By limiting the current through transistor 34 (by limiting the current through transistor 16) , the maximum V rq voltage drop is limited so that it (hopefully) does not exceed a V X of the junction diode. This effort to improve the voltage deficiencies of the circuit by removing the voltage drop across the clamping diode 28 appears to have introduced such a gross current deficiency that circuit performance is probably worse than prior to the "improvements". SUMMARY OF THE INVENTION The foregoing problems and shortcomings of prior art back bias circuits are resolved by the invention herein described by means of a new circuit configuration which reduces the current leakage problems to a negligible level, the new circuit comprising a charge pump capacitor having a driven end and an output end, a recharge and discharge phase, the output end being clamped to prevent it from going more positive than V during the recharge phase, and a near ideal (no forward voltage drop) output isolation device which isolates the capacitor from V during the recharge phase. Therefore, it is an object of the invention to provide a back bias circuit for an integrated circuit wherein a capacitor is charged to the full value of V r _, and substantially all of that voltage is applied to the sub¬ strate. It is another object of the invention to provide a back bias circuit for an integrated circuit wherein the voltage on the positive end of its charged capacitor is not allowed to exceed zero volts in the positive direction during a recharge phase. It is still another object of the invention to provide a back bias circuit for an integrated circuit wherein an isolation device is provided at the negative end of its charge pump capacitor and wherein the isolation device is used to isolate the capacitor from the substrate of the integrated circuit during recharge of the capacitor. It is a still further object of the invention to provide a back bias circuit for an integrated circuit wherein an isolation device is provided at the negative end of its charge pump capacitor and wherein the isolation device is used to isolate the capacitor from the substrate of the integrated circuit during recharge of the capacitor and wherein said isolation device has a minimum forward voltage drop and acts as a coupling device during a dis¬ charge phase of the capacitor. It is yet another object of the invention to reduce electron injection into the substrate by providing a reversal of the source/drain and gate connections of the charge pump capacitor in a back bias generator circuit for an integrated circuit so that the parasitic junction diode of the source/drain terminal of the capacitor will always be reverse biased, thereby preventing electron injection into the substrate. These and other aspects of the invention will be better understood by careful review of the Detailed Descrip¬ tion of the Invention, infra taken together with the draw¬ ings, in which: Figure 1 is a typical graphic portrayal of the relationship between the forward voltage drop V φ and the square root of the back bias applied to the substrate, jv „ ' , in an integrated circuit of the MOS type; Figure 2 is a schematic illustration of a typical simple back bias circuit of a type used in the prior art; Figure 3 illustrates, in graphic form, two waveforms of the prior art circuit of Figure 2; Figure 4 is a schematic diagram showing parasitic components of the circuit of Figure 2; Figure 5a is an equivalent schematic diagram of transistor 28 of Figure 2 during a second phase of operation shown in Figure 3; Figure 5b is an equivalent schematic diagram of transistor 34 of Figure 2 during the second phase of operation as shown in Figure 3; Figure 5c is an equivalent schematic diagram of the transistor 34 of Figure 2 during a first phase of operation as shown in Figure 3; Figure 6 is a more detailed schematic diagram of a prior art back bias generator; and Figure 7 is a detailed schematic diagram of the preferred embodiment of the back bias genera¬ tor circuit of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION In the discussion which follows, it will be understood that where like reference numerals are used to identify a circuit component in two or more different Figures, the components so identified perform a similar or identical function in the circuits of the two or more Figures. The preferred embodiment of the invention is depicted in schematic form in Figure 7. A square wave, which may be generated from a ring oscillator (not shown) , for example, is applied to input terminal 18 of the back bias generator of Figure 7. Input terminal 18 is connected to an input terminal of inverter 12 and to the gate terminal of transistor 16. Input terminal 18 is also connected to an input of inverting amplifier 19c, part of bootstrap circuit 19. Bootstrap circuit 19 is a digital differentiator which serves to differentiate the input square wave to provide a short negative pulse in response to the negative going signal at terminal 18. OR gate 19d is fed from input terminal 18 and from delay 19b. Delay 19b is fed from the output of inverter 19c. The source terminal of transistor 16 is connected to V gs and its drain terminal is connected to the drain and gate terminals of diode connected depletion transistor 33a. The source terminal of transistor 33a is connected to the drain terminal of transistor 14 and to the positive terminal of capacitor 30. The output terminal of inverter 12 is connected to gate 15 terminal of transistor 14 and to the positive terminal of capacitor 19a. The source terminal of transis¬ tor 14 is connected to V . The negative terminal of capaci¬ tor 19a is connected to the drain terminal of transistor 31a. The gate and source terminals of transistor 33a are connected to the gate terminal of transistor 31a. The source terminal of transistor 31a is connected to the positive terminal of capacitor 31b. The positive terminal of capacitor 31b is connected to the drain terminal of transistor 29a at node 25a and to the gate terminal of en¬ hancement transistor 28a. Input terminal 18 is also connected to the gate terminal of transistor 29a and to the negative terminal of capacitor 37. The source terminal of transistor 28a is connected to V and the drain terminal of transistor 28a is connected to the drain terminal of transistor 29a, to the negative terminal of capacitor 30 and to the drain terminal of transistor 34a. The positive terminal of capacitor 37 is connected to the drain terminal of depletion transistor 35 and to the gate terminal of transistor 34a. The drain terminal of transistor 34a is connected to the drain and gate terminals of depletion transistor 35, which is diode connected, and to Vi_s_ι3. All capacitors are transistors with common source/ drain connections, as shown. This completes the description of the circuit of Figure 7. It is helpful at this point to compare the prior art back bias generator circuit shown in the schematic diagram of Figure 6 with the preferred embodiment of the invention shown in like fashion in Figure 7. It should be noted that the circuit of Figure 7 has been modified in the following ways from that of Figure 6: 1) Current limiting resistor 33 of Figure 6 is replaced by depletion current source transistor 33a in the circuit of Figure 7.. This modification provides good control of the absolute current through transistor 34a during phase two 32 (see Figure 3) but still allows node 10 to settle much faster to its asymtotic value of zero volts. 2) Transistor 28 of Figure 6 is modified from one with a "natural" threshold to an enhancement threshold transistor 28a, as shown in Figure 7. Transistor 28a has an increased channel length of 2.4 microns as compared to 2.0 microns for transistor 28 (Figure 6) and its width is decreased from 18 microns to 8 microns since it no longer has to carry a large leakage current. 3) Pull-up transistor 31 of Figure 6 is replaced by non-leaky capacitor 31b and transistor switch 31a of Figure 7. During phase two 32 (see Figure 3) , when input node 18 goes high, transistor 29a is turned on hard by reason of its gate going positive and its source going negative. At that time, one side of capacitor 31b is equal to node 24. At the start of phase two, nodes 17 and 9 are at 5.0 volts. Then the source of transistor 31a goes to - 4.0 volts and a short time later to zero volts with its drain being held at 5.0 volts. Hence, the other side of capacitor 31b is clamped to zero volts. At the beginning of phase one, node 17 is still at 5.0 volts and node 9 is at zero volts. Then node 17 goes down to zero volts and node 9 goes up to 5.0 volts, thus switching transistor 31a turns on, causing node 27 to go to zero volts while the other side of capacitor 31b is pulled by node 24 through the grounded gate of transistor 29a to - V . Later during phase one, node 17 again goes up pulling with it node 25a through turned on transistor 31a, effectively grounding node 24 in the later half of phase one. These modifications reduce the leakage of transistor 28a to a negligible amount since it is now an enhancement transistor with longer than minimum channel length and slightly narrower width. Of course, these benefits are attained without affecting the ability of transistor 28a to clamp to V during the other phase of the input. 4) Output coupling "diode" 34 is replaced by switched transistor 34a which is turned on during the time diode 34 would have been conducting and is solidly turned off by application of negative Vbb during the period when diode 34 would not be conducting. Since 34a is now a switch¬ ed transistor with V being more than V , its size may be reduced significantly from about 750 microns to about 200 microns and still not have any significant voltage drop across it. In addition, its channel length may be increased from 2 to 3 microns so that its threshold is slightly higher and more controllable at zero volts V σ _ . This switching is accomplished by a weak current source between gate and source of transistor 34a and capacitor 37 which couples the gate of transistor 34a to input node 18. Diode connected depletion transistor current source 35 biases the average V C__rb_ of transistor 34a to zero volts so that during phase one it is negative and during phase two it is more positive than an amount equal to V . 5) Capacitor 30 is connected in the circuit so that its source/drain terminal is the positive terminal, connected to node 10 and its gate terminal is the negative terminal, connected to node 24. This is reversed from like capacitor 30 of Figures 4 and 6. This means that the N+/P- parasitic diode 36 (shown connected from node 24 to the substrate in Figure 4) from the diffusion side terminal (N+) of capacitor 30 to the substrate (P-) are always back biased and never conduct, thereby preventing electron injection by means of the current through the parasitic diode. While this reversal causes an approximate eight percent reduction in capacitance for capacitor 30, this can be easily overcome by using a physically larger capacitor, if that is deemed necessary. When the source/drain (N+) terminal of capacitor 30 is connected to node 24, that parasitic diode conducts from the negative terminal of capacitor 30 to the substrate any time the parasitic diode is forward biased and dis¬ charges dynamic nodes degrading or disabling dynamic cir¬ cuitry. With the source/drain (N+) of capacitor 30 con¬ nected to node 10, the parasitic diode is always back biased and has no appreciable effect on the circuit. The improved operation of the circuit with the reversed capacitor more than compensates for the small loss of capacitance incurred when the connections are reversed. It may be seen that the invention comprises an im¬ provement over the prior art on-chip back bias generators in that charge pump capacitor 30 is clamped during the rising edge of the input cycle and during the high steady state period to prevent its V__ connected end from going positive with respect to V during the charge cycle. During the rest of the input cycle, the clamping device is held safely off without any appreciable leakage. The charge voltage source is V rr _, the highest voltage available on the chip, and the circuit employs an enhancement type pull-up device with bootstrapped gate drive for minimum power consumption. During the discharge phase of operation (the phase which occurs on the falling edge of the input waveform and during the low steady state of the input signal) , the coupling/ decoupling device couples the capacitor to V__ without any appreciable voltage drop. During the charge cycle, capaci¬ tor 30 is charged to a voltage nearly equal to the differ¬ ence between V and V while it is effectively isolated from V . During the discharge cycle, capacitor 30 is connected between V ς<-; and the substrate to provide the maximum possible negative voltage which is nearly V BB - V SS - < V CC " V SS> ' Thus, it may be seen that on an integrated circuit with a common substrate it is possible to Gontrol a tran¬ sistor switch which has one electrode connected to a voltage more negative than V without consuming steady state current from V„ B . While the invention has been particularly shown and described herein with reference to a preferred embodi¬ ment thereof, it will be understood by those skilled in the art that various other modifications and changes may be made to the present invention from the principles of the inven¬ tion described above without departing from the spirit and scope thereof as encompassed in the accompanying claims. Therefore, it is intended in the appended claims to cover all such equivalent variations as may come within the scope of the invention as described.

Claims: AMENDED CLAIMS [received by the International Bureau on 12 August 1986 (12.08.86); orginal claims 1-16 replaced by new claims 1-18 (5 pages)] 1. An improved on-chip back-bias generator circuit for an NMOS integrated circuit using only N channel transistors, the integrated circuit being powered by voltages 'V gs and V cc and having a substrate at a voltage V , the improved circuit adapted for being driven by an output signal from an oscillator, the improvement characterized by: a charge pump capacitor having an input end and an output end thereof; means for applying a charging voltage to said input end of said capacitor, said charging voltage having a value essentially equal to a highest voltage on the integrated circuit chip; means for clamping said output end of said capacitor to a voltage essentially equal to a lowest voltage on the integrated circuit during a time when the capacitor is being charged; means for essentially isolating said output end of said capacitor from the substrate during said time when said capacitor is being charged; and means for coupling said output end of said capacitor to said substrate essentially without any voltage drop during a time when the capacitor is not being charged, said coupling means further characterized by: a switched transistor having a source terminal, a drain terminal and a gate terminal; a constant current source, said constant current source being connected between said gate terminal of said switched transistor and the substrate for biasing the average gate-to-source potential difference of the switched transistor to zero volts so that during the time said capacitor is being charged it is negative and during the capacitor non-charging time it is more positive than the switched transistor threshold voltage, said source terminal of said switched transis¬ tor being connected to said output end of said capacitor, said drain terminal of said switched transistor being connected to the substrate and said gate terminal of said switched transistor being connected via a further capacitor to the oscillator output signal terminal. 2. The improved circuit according to claim 1 wherein said highest voltage is V . 3. The improved circuit according to claim 1 wherein said lowest voltage is s _. 4. The improved circuit according to claim 1 wherein said highest voltage is V__ and the lowest voltage is V s -. 5. The improved circuit according to claim 1 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of said charge pump capacitor is a gate connection of said transistor. , 6. " " The improved circuit according to claim 2 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of said charge pump capacitor is a gate connection of said transistor. 7. The improved circuit according to claim 3 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of s3id charge pump capacitor is a gate connection of said transistor. 8. The improved circuit according to claim 4 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of said charge pump capacitor is a gate connection of said transistor. 9. An improved method of generating an on-chip back- bias voltage for an NMOS integrated circuit, the improvement characterized by the steps of: applying a highest voltage on the chip to an input end of a charge pump capacitor during a charging time of said capacitor; applying a lowest voltage on the chip to an output end of said charge pump capacitor during said charging time of said capacitor; decoupling said output end of said charge pump capacitor from a substrate of the chip during said charging time thereof; clamping said output end of said capacitor to said lowest voltage on the chip with the clamping circuit during a time the capacitor is being charged; and connecting said output end of said capacitor to said substrate of said chip during a non-charging time of said capacitor, said connecting step being accomplished by a coupling circuit further characterized by: a switched transistor having a source terminal, a drain terminal and a gate terminal; .. . a constant current source, said constant current source being connected between said gate terminal of said switched transistor and the substrate for biasing the average gate-to-source potential difference of the switched transistor to zero volts so that during the time said capacitor is being charged it is negative and during the capacitor non-charging time it is more positive than the switched transistor threshold voltage, said source terminal of said switched transis¬ tor being connected to said output end of said capacitor, said drain terminal of said switched transistor being connected to the substrate and said gate terminal of said switched transistor being connected via a further capacitor to the oscillator output signal terminal. 10. The improved method according to claim 9 wherein said highest voltage is V cc . 11. The improved method according to claim 9 wherein said lowest voltage is V g _. 12. The improved method according to claim 9 wherein said highest voltage is V cc and said lowest voltage is V ss - 13. The improved method according to claim 9 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of said charge pump capacitor is a gate connection of said transistor. 14. The improved method according to claim 10 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of said charge pump capacitor is a gate connection of said transistor. 15. The improved method according to claim 11 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of said charge pump capacitor is a gate connection of said transistor. 16. The improved method according to claim 12 wherein said input end of said charge pump capacitor is a common connection between a drain and a source of a transistor and said output end of said charge pump capacitor is a gate connection of said transistor. 17. The improved circuit according to claim 1 wherein said clamping means is further characterized by: an enhancement threshold transistor having a source terminal, a drain terminal and a gate terminal, said drain terminal of said enhancement threshold transistor being connected to said output end of said capacitor and said source terminal of said enhancement threshold transistor being connected to said lowest voltage on said chip; and a control transistor having a source terminal, a drain terminal and a gate terminal, said drain terminal of said control transistor being connected to said drain terminal of said enhanced threshold transistor, said gate terminal of said control transistor being connected to the output signal terminal of the oscillator and said source terminal of said control transistor being connected to said gate terminal of said enhanced threshold transistor. 18. The improved method according to claim 9 wherein said clamping circuit of said clamping step is further characterized by: an enhancement threshold transistor having a source terminal, a drain terminal and a gate terminal, said drain terminal of said enhancement threshold transistor being connected to said output end of said capacitor and said source terminal of said enhancement threshold transistor being connected to said lowest voltage on said chip; and a control transistor having a source terminal, a drain terminal and a gate terminal, said drain terminal of said control transistor being connected to said drain terminal of said enhanced threshold transistor, said gate terminal of said control transistor being connected to the output signal terminal- of the oscillator and said source terminal of said control transistor being connected to said gate terminal of said enhanced threshold transistor.

Inventors: LEUSCHNER HORST, LEUSCHNER, HORST
Applicants: SGS SEMICONDUCTOR CORP, SGS SEMICONDUCTOR CORPORATION
Application year: 1986
Main classification: H02M3
IPC codes: G05F3