DIGITAL-TO-ANALOG CONVERTER

Abstract: A digital-to-analog converter (DAC) converts digital input data into an analog output signal with less harmonic distortion over an entire signal-level range. An exponent value detector detects from the digital input data the number of bits by which the digital input data is to be shifted to form a mantissa part thereof. A digital shifter shifts the digital input data in accord­ ance with the output of the exponent value detector, and out­ puts the mantissa part which is then supplied to a mantissa-­ part DAC. The mantissa-part DAC comprises an R-2R resistor ladder network and outputs the result of DA conversion of the mantissa part to an exponent-part DAC. The exponent DAC analogoualy shifts the output of the mantissa-part DAC by an amount determined by the output of the exponent value detec­ tor, and outputs the shifted signal as the analog output signal of this DAC. A control circuit is provided between the digital shifter and the mantissa-part DAC, which prevents, in accord­ ance with the output of the exponent value detector, the least significant bits of the mantissa-part DAC from operatively func­ tioning to thereby decrease the number of operable bits thereof when the magnitude of the digital input data is small.

Description: This invention relates to a digital-to-analog converter for converting digital input data into an analog output signal, comprising detector means responsive to the digital input data for detecting the magnitude thereof, said detector means outputting a detection signal representative of the magnitude of said digital input data, digital-to-analog converting means of a predetermined number of bits responsive to said detection signal for converting a mantissa-part of said digital input data into an intermediate analog signal and exponent converting means responsive to said detection signal, said exponent converting means outputting said converted analog signal as the analog output signal. EP-A2-O 177 902, which was published after the priority date, and, thus, falling under Art. 54(3)EPC, describes a digital-to-analog converter (DAC) which can deal with an input data in the form of an ordinary fixed-point binary number. As shown in Fig. 1, the DAC comprises a digital shifter 1 for shifting bits I ₀ to I₁₅ of an input data D IN to extract therefrom N consecutive bits to be supplied to a mantissa-part DAC 2. A shift number detector 3 decodes a predetermined number of higher-order bits of the input data D IN to produce a signal representative of the number of bits to be shifted by the digital shifter 1 and supplies the produced signal to the digital shifter 1 and an exponent-part DAC 4. In the case where the input data D IN is represented in two's complement, the digital shifter 1 extracts the N consecutive bits in accordance with the signal fed from the shift number detector 3 in such a manner that the greater the absolute value of the input data D IN is, the higher the order of the N consecutive bits extracted from the input data D IN is. Also, the exponent-part DAC 4 produces an exponent part of the output signal V OUT in accordance with the signal fed from the shift number detector 3. With the DAC shown in Fig. 1, if the mantissa-part DAC 2 has a higher resolution (for example, a resolution of about 12 bits), the minimum step of variation of the output signal V OUT becomes smaller, so that a total harmonic distortion of the output signal V OUT of higher signal levels desirably becomes smaller. However, even though the mantissa-part DAC 2 is manufactured so as to have a 12-bit resolution, the actual accuracy thereof is 10 bits at the best. In such a case, although the low accuracy does not much affect on the higher level signals, the total harmonic distortion of the output signal of lower signal levels becomes worse. On the other hand, it is not difficult to manufacture a mantissa-part DAC having an accuracy of about 10 bits, so that it is possible to improve the total harmonic distortion of the output signal of lower signal levels by arranging the mantissa-part DAC to have a resolution of 10 bits. In this case, however, the total harmonic distortion of the output signal of higher signal levels will be deteriorated since the minimum step of variation of the higher level output signal becomes large. Thus, with the aforesaid floating-point-type DAC, the total harmonic distortion of the output signal is deteriorated in one of the higher and lower signal level ranges depending on the selection of the accuracy of a mantissa-part DAC thereof. A general-use floating point DAC is described in ELEKTRONIK, vol. 31, no. 3, February 12, 1982, pages 78 -80; G. Heinle: "Gleitkomma-D/A-Umsetzer verringert Quantisierungsfehler". This known DAC comprises detector means responsive to the digital input data for detecting the magnitude thereof, digital-to-analog converting means of a predetermined number of bits for converting a mantissa-part of said digital input data into a first analog value, means providing a second analog value corresponding to an exponent part of the digital input data and means combining the first and second analog values to form the desired analog output signal. Such a floating point DAC has a high conversion accuracy and can convert an input data of a small magnitude into an analog form with little distortion, however, it must be supplied with an input data in the form of a floating point number. Furthermore there are no means provided in order to reduce the harmonic distortion of the output signal of lower signal levels. GB-A-2 093 297 discloses a DAC comprising a decoder responsive to at least 2 bits of an input digital signal, said decoder producing an output signal indicating that the magnitude of an analog signal represented by the input digital signal is greater than a predetermined value or not. The DAC comprises further a first data selector controlled by the output signal form said decoder for selecting one of two sets of consecutive bits of said input digital signal, a first D/A converter having an external reference voltage input terminal and being responsive to the output data from said first data selector for producing an output analog signal by using a first reference voltage applied to said external reference voltage input terminal, a digital data generator for producing a predetermined digital data, a second data selector controlled by said output signal from said decoder for selecting one of a said of executive bits of said input digital signal and said predetermined digital data from said digital data generator. The DAC further comprises a second D/A converter having an external reference voltage input terminal and being responsive to the output data from said second data selector for producing an output analog signal by using a second reference voltage applied to said external reference voltage input terminal, said second D/A converter producing a voltage having a specific relationship with respect to said second reference voltage when said predetermined digital data is applied thereto via said second data selector, a D.C.-voltage source for producing a predetermined voltage which is fed to said external reference voltage input terminal of said second D/A converter as said second reference voltage, and means for producing said first reference voltage fed to said external reference voltage input terminal of said first D/A converter, said means being controlled by said output signal from said decoder for supplying said external reference voltage input terminal of said first D/A converter with the sum of said second reference voltage and the output voltage of said second D/A converter, or only said second reference voltage. More specifically there are provided two DACs and when the number of bits of the input is larger than the number of bits of the first DAC so that some bits thereof overflow, the overflow bits are processed by the second DAC. Then the output of the second DAC is inputted to the first DAC so that the first DAC is subject to the offset corresponding to the output of the second DAC thus reducing the quantization error. In other words, the step size on expansion is made substantially small enough so that the problem is resolved that quantization error occurs greatly on expansion due to the wider step sizes. There is, however, no provision to improve the total harmonic distortion of the output signal of lower signal levels. IBM TECHNICAL DISCLOSURE BULLETIN, vol. 5, no. 5, October 1962, pages 30 - 31, T.J. Harrison: "Logarithmic digital to analog converter" discloses a logarithmic digital-to-analog converter which is designed to convert the binary digital input into the logarithmic analog output. The known converter includes a counter which determines the number of the most significant bit of an 11-n input signal. This number is equal to the characteristic of the logarithm and can assume n possible levels. In order to determine the mantissa, a sufficient number of lower order bits are decoded and fed to a 2 i -level A/D converter. In the given example i has the value of 2 so that the 2 i -level A/D converter is in fact a 4-level A/D converter. However, the document is silent about the design of this converter for larger values of i, as for instance i = 16, in which case 65 536 levels must be converted. The document is especially silent about the problem of how to reduce the total harmonic distortion of output signals of lower signal levels. US-A-4 278 964 teaches a seismic playback system and especially an apparatus for converting wide dynamic amplitude range digital data recorded in floating point digital wordform, comprising a binary coded mantissa and a binary coded exponent, to an analog signal, or oscillogram, of selectively compressed and/or amplified dynamic amplitude range. The digital word, occupying a number of binary bit positions, is, in algebraic form ± AG E , where A represents the mantissa, or argument, G represents the base, or radix, of the number system used and E represents the exponent. Since base G is constant, for example at 8, the only binary bits that need to be recorded are those representing the mantissa A and the exponent E. In reconverting the digital data to analog form for making an oscillogram, it is desired to selectively amplify and/or compress the dynamic range and, yet, at the same time avoid introducing serious distortions. The function generator for reconverting the digital data to analog form is provided with a mantissa digital-to-analog converting means for converting a mantissa-part of said digital data into a first analog signal and circuit means responsive to said first analog signal to produce second analog signals, whose voltages are G E magnifications of said first analog signal, where G represents the base of the number system used and E represents the exponent. According to this prior art, the exponent part and the mantissa part are connected together via a buffer amplifier. In addition, by use of the positive and negative voltages to be changed over, this prior art system obtains the analog output. The known system is intended for displaying a stored wave-shape by an oscillograph. Therefore the data is compressed by use of the logarithmic representation whereby dealing with the input signal having a wide dynamic range. Also this document is silent about the problem of how the total harmonic distortion of the output signal of lower signal levels can be improved. It is therefore an object of the present invention to provide a DAC in which the total harmonic distortion of an output signal can be minimized over an entire range of its signal level. The digital-to-analog converter according to the invention is characterized by control means, incorporated in said digital-to-analog converting means, responsive to said detection signal for changing the number of operative bits of said digital-to-analog converting means, said control means decreasing the number of operative bits of said digital-to-analog converting means with a decrease of the magnitude of said digital input data. Examples of the present invention will now be described with reference to accompanying drawings, in which:- Fig. 1 is a block diagram of a DAC (digital-to-analog converter) before improvement; Fig. 2 is a block diagram of a DAC 10 provided in accordance with a first embodiment of the present invention; Fig. 3 is a circuit diagram of the exponent value detector 13 of the DAC 10 shown in Fig. 2; Fig. 4 is an illustration showing the relation between the bits of the input data D IN and the bits supplied to the mantissa-part DAC 22 of the DAC 10 of Fig. 2; Fig. 5 is a circuit diagram of the digital shifter 21 of the DAC 10 of Fig. 2; Fig. 6 is a circuit diagram of the exponent-part DAC 50 of the DAC 10 of Fig. 2; Fig. 7 is a chart showing total harmonic distortions of the DAC 10 and various other DACs; and Fig. 8 is a block diagram of a DAC 22a provided in accordance with a second embodiment of the invention. Fig. 2 shows a block diagram of a DAC provided in accordance with a first embodiment of the present invention. In Fig. 2, sixteen-bit digital data D IN represented in two's complement is applied to input terminals T₀ to T₁₅, wherein the sign bit thereof is applied to the input terminal T₁₅ and the LSB (least significant bit) thereof is applied to the input terminal T₀. Each of the bits I₀ to I₁₅ is passed through serially connected two inverters 11 and 12, whereby sixteen bit-data J₀ to J₁₅ equivalent respectively to the bits I₀ to I₁₅ are produced. The higher-order seven bits J₉ to J₁₅ are supplied to an exponent value detector 13 which decodes the bits J₉ to J₁₅ to produce one of seven signals S₀ to S₆ representing an exponent value of an analog output signal V OUT of this DAC 10. As shown in Fig. 3, the exponent value detector 13 comprises six exclusive-OR gates 109 to 114 to which the bits J₉ to J₁₄ are respectively supplied at one input terminals thereof. The other input terminals of the exclusive-OR gates 109 to 114 are supplied with the bit J₁₅. This exponent value detector 13 further comprises seven AND gates AN₀ to AN₆. Input terminals of each of the AND gates AN₀ to AN₆ are indicated by circles on an input signal line of the corresponding one of the AND gates. Output terminals of the exclusive-OR gates 114 to 109 are connected to the first input terminals of the AND gates AN₀ to AN₅, respectively. The output terminals of the exclusive-OR gates 109 to 114 are also connected to input terminals of inverters 116 to 121, respectively. An output terminal of the inverter 116 is connected to the first input terminal of the AND gate AN₆, and an output terminal of the inverter 117 is connected to the second input terminals of the AND gates AN₅ and AN₆. An output terminal of the inverter 118 is connected to the second input terminal of the AND gate AN₄ and the third input terminals of the AND gates AN₅ and AN₆. In a similar manner, an output terminal of the inverter 119 is connected to the input terminals of the AND gates AN₃ to AN₆, an output terminal of the inverter 120 to the input terminals of AND gates AN₂ to AN₆, and an output terminal of the inverter 121 to the input terminals of the AND gates AN₁ to AN₆. When opened, the AND gates AN₀ to AN₆ output the signal S₀ to S₆, respectively. With this exponent value detector 13, when the bit J₁₅ is "0", that is to say, when the input data D IN is a positive value, "N" of the outputted signal S N (N is any one of "1" to "6") is determined by the number of "0" bits counted from the bit J₁₄ toward the bit J₉ until a "1" bit is first detected. In other words, the "N" is determined by the number of leading "0" bits of the input data D IN . For example, when the bit J₁₅ is "0" and if only the bits J₁₃ and J₁₁ are "1", the number of leading "0" bits of the input data D IN is "1", so that the signal S₁ is outputted. On the other hand, when the bit J₁₅ is "1", that is to say, when the input data D IN is negative, the "N" of the signal S N is determined by the number of "1" bits counted from the bit J₁₄ toward the bit J₉ until a "0" bit is first detected. In other words, the "N" is determined by the number of leading "1" bits of the input data D IN . For example, in the case where only the bits J₁₀ and J₉ are "0", the number of leading "1" bits of the input data D IN is "4", so that the signal S₄ is outputted. Thus, the exponent value detector 13 determines the "N" of the signal S N based on the number of those bits of the input data D IN which are counted from the bit I₁₄ toward the bit I₉ until a bit different in state from the bit I₁₅ is first detected. In the case where a bit which is different in state from the sign bit is not detected from the bits J₁₄ to J₉, the exponent value detector 13 outputs the signal S₆ irrespective of the state of the bit J₁₅. Thus, the exponent value detector 13 selectively outputs the signal S N in accordance with the absolute value of the input data D IN represented by the bits I₁₄ to I₀, wherein the "N" becomes greater when the absolute value of the input data becomes smaller. And, when the absolute value of the input data D IN is less than "512" in decimal, the signal S₆ is always outputted. In the case where the input data D IN takes the form of an ordinary binary value, an inversion of the bit I₁₅ is applied to the exponent value detector 13 in stead of the bit J₁₅. Referring again to Fig. Fig. 2, the bits J₁₄ to J₀ are also supplied to a digital shifter 21 which shifts the supplied bits J₁₄ to J₀ by bits whose number is determined in accordance with the signals S₀ to S₆. The digital shifter 21 then outputs, from output terminals TD₀ to TD₁₀ thereof, eleven consecutive bits among the bits J₁₄ to J₀ obtained as the result of its shift operation. When supplied with the signal S₀, the digital shifter 21 outputs the bits J₄ to J₁₄ from the output terminals TD₀ to TD₁₀, respectively, and when supplied with the signal S₁, it outputs the bits J₃ to J₁₃ from the output terminals TD₀ to TD₁₀, respectively. In a similar manner, when supplied with the signal S₂, the digital shifter 21 outputs the bits J₂ to J₁₂ from the output terminals TD₀ to TD₁₀, respectively, and when supplied with the signal S₃, it outputs the bits J₁ to J₁₁ from the output terminals TD₀ to TD₁₀, respectively. And, when supplied with the signal S₄, the digital shifter 21 outputs the bits J₀ to J₁₀ from the output terminals TD₀ to TD₁₀, respectively (see arrows in Fig. 4). Also, when supplied with the signal S₅ outputted from the exponent value detector 13, the digital shifter 21 outputs the bits J₀ to J₉ from the output terminals TD₁ to TD₁₀, respectively. In this case, the digital shifter 21 outputs an indefinite signal (a "1" or a "0" signal) from the output terminal TD₀. On the other hand, when supplied with the signal S₆, the digital shifter 21 outputs the bits J₀ to J₈ from the output terminals TD₂ to TD₁₀, respectively. In this case, the digital shifter 21 outputs indefinite signals from the output terminals TD₀ and TD₁. The digital shifter 21 is constructed, for example, as shown in Fig. 5. The digital shifter 21 comprises seven columns of switches SW₀₋₀ to SW₀₋₁₀, SW₁₋₀ to SW₁₋₁₀, ...SW₆₋₀ to SW₆₋₁₀. These switches may be constituted by FETs, transistors or the like. In this case, all of the switches in the same column are closed when the corresponding one of the signals S₀ to S₆ is applied thereto. For example, the switches SW₀₋₀ to SW₀₋₁₀ in the first column are closed when the signal S₀ is supplied thereto. In this case, the bits J₁₄ to J₄ are supplied respectively to the output terminals TD₁₀ to TD₀ of this digital shifter 21. In a similar manner, when the signal S₁ is supplied to the digital shifter 21, the switches SW₁₋₀ to SW₁₋₁₀ close, so that the bits J₁₃ to J₃ are supplied respectively to the output terminals TD₁₀ to TD₀ of this digital shifter 21. And, when the signal S₆ is supplied to the digital shifter 21, the switches SW₆₋₀ to SW₆₋₁₀ close, so that the bits J₈ to J₀ are supplied respectively to the output terminals TD₈ to TD₂. Referring again to Fig. 2, shown at 22 is a mantissa-part DAC of this DAC 10 which comprises 12-stage 2R-R resistor ladder network 23. An R resistor of each of the first to twelfth stages of the ladder network 23 is composed of a resister having a resistance value of R₁, and a 2R resistor of each of the first to tenth stages of the ladder network 23 is composed of serially connected two resistors each having a resistance value of R₁. A 2R resistor of the eleventh stage of the ladder network 23 is composed of a resistor 24 of R₁ and two groups of resistors 25 and 26 each group composed of serially connected two resistors each having a resistance value of R₁, a junction point P₁ of the two groups of resistors 24 and 25 being connected to the resistor 24. Similarly, a 2R resistor of the twelfth stage of the ladder network 23 is composed of a resistor 27 of R₁ and two groups of resistors 28 and 29 each group composed of serially connected two resistors each having a resistance value of R₁, a junction point P₂ of the two groups of resistors 28 and 29 being connected to the resistor 27. The free end of the R resistor of the twelfth or the last stage of the ladder network 23 is connected to a source of voltage V DD through serially connected two resistors each having a resistance value of R₁, and also connected to the ground through serially connected two resistors each having a resistance value R₁. The 2R resistor of the first stage of the ladder network 23 is connected with serially connected two inverters 30₋₁ and 31₋₁, and the 2R resistor of the second stage of the ladder network 23 is connected with serially connected two inverters 30₋₂ and 31₋₂. This is true with respect to the 2R resistors of the third to tenth stages of the ladder network 23. Similarly, the resistor group 25 is connected with serially connected two inverters 30₋₁₁ and 31₋₁₁, and the resistor group 26 is connected with serially connected two inverters 30₋₁₂ and 31₋₁₂. This is true with the resistor groups 28 and 29. An inversion of the bit I₁₅ by the inverter 11 is supplied to an input terminal of the inverter 30₋₁, and the bits outputted from the output terminals TD₁₀ to TD₂ of the digital shifter 21 are supplied to input terminals of the inverters 30₋₁ to 30₋₁₀, respectively. The two bits outputted from the output terminals TD₁ and TD₀ are supplied to a mantissa-part-bit control circuit 40. Each of the inverters 31₋₁ to 31₋₁₄ outputs a ground level signal as "0" and a voltage equal to V DD as "1". The mantissa-part-bit control circuit 40 is provided for changing the number of operable bit-stages of the mantissa-part DAC 22. The mantissa-part-bit control circuit 40 comprises two exclusive OR gates EXOR1 and EXOR2, two NOR gates NOR1 and NOR2 and an inverter INV1. A signal M₁ outputted from the terminal TD₁, which corresponds to the eleventh bit-stage of the mantissa-part DAC 22, is supplied to one input terminal of the exclusive OR gate EXOR1. The signal M₁ is also supplied to the input terminal of the inverter 30₋₁₂, whereby a signal X is obtained at the output terminal of the inverter 31₋₁₂. The other input terminal of the exclusive OR gate EXOR1 is supplied with an output signal the NOR gate NOR1. An output of the exclusive OR gate EXOR1 is supplied to the input terminal of the inverter 30₋₁₁, whereby a signal W is obtained at the output terminal of the inverter 31₋₁₁. A signal M₀ outputted from the terminal TD₀, which corresponds to the twelfth bit-stage of the mantissa-part DAC 22, is supplied to one input terminal of the exclusive OR gate EXOR2. The signal M₀ is also supplied to the input terminal of the inverter 30₋₁₄, whereby a signal Z is obtained at the output terminal of the inverter 31₋₁₄. The other input terminal of the exclusive OR gate EXOR2 is supplied with an output signal the inverter INV1. An output of the exclusive OR gate EXOR2 is supplied to the input terminal of the inverter 30₋₁₃, whereby a signal Y is obtained at the output terminal of the inverter 31₋₁₃. The signals S₅ and S₆ are supplied to input terminals of the NOR gate NOR2, and the signal S₅ and an output of the NOR gate NOR2 are supplied to input terminals of the NOR gate NOR1. The output signal of the NOR gate NOR2 is also supplied to an input terminal of the inverter INV1. The mantissa-part-bit control circuit 40 thus constructed causes the four signals W, X, Y and Z supplied respectively to the resistor groups 25, 26, 28 and 29 to be changed in accordance with the states of the signals S₅ and S₆, as shown in Table 1. S₅ S₆ W X Y Z 0 0 M₁ M₁ M₀ M₀ 1 0 M₁ M₁ M₀ M₀ 0 1 M₁ M₁ M₀ M₀ An output signal S A of the mantissa-part DAC 22 which appears at the junction point of the 2R and R resistors of the first stage of the ladder network 23 is supplied to an exponent-part DAC 50 of seven-stage type. As shown in Fig. 6, the exponent part DAC 50 comprises seven analog switches ASW₀ to ASW₆ and a six-stage R-2R resistor ladder network 130. Each stage of the ladder network 130 comprises an R resistor of a resistance value of R₂ and a 2R resistor composed of serially connected two resistors each having a resistance value of R₂. The free end of the R resistor of the first stage of the ladder network 130 is supplied with the output signal S A of the mantissa-part DAC 22, while the free ends of the 2R resistors of all of the stages of the ladder network 130 are connected to a source of voltage V DD /2. The free end of the R resistor of the first stage of the ladder network 130 and the junction points between the R and 2R resistors of the first to sixth stages of the ladder network 130 are connected respectively through analog switches ASW₀ to ASW₆ to an output terminal 131 of this DAC 10. And, the signals S₀ to S₆ outputted from the exponent value detector 13 are supplied respectively to control terminals of the analog switches ASW₀ to ASW₆ so that one of the switches is brought into an ON state by the corresponding one of the signals S₀ to S₆ which is in the "1" state. The operation of this DAC 10 will now be described. As will be appreciated from Fig. 4, one of the signals S₀ to S₆ is outputted in accordance with the magnitude of the input data D IN . For example, when the input data D IN is in the range of between "32767" and "16384" in decimal, the signal S₀ is outputted, and when the input data D IN is in the range of between "16383" and "8192" in decimal, the signal S₁ is outputted. When the input data D IN is relatively large in magnitude, that is, when a signal level of the output signal V OUT is greater than -30dB, one of the five signals S₀ to S₄ is outputted. In this case, the signals S₅ and S₆ are both "0", so that the NOR gate NOR2 outputs a "1" signal. And therefore, the inverter INV1 and the NOR gate NOR1 both output "0", so that the exclusive OR gates EXOR1 and EXOR2 serves as mere buffers. Consequently, both of the signals W and X become equal in state to the signal M₁, and also both of the signals Y and Z become equal in state to the signal M₀. When the signals W and X are equal in state to each other, the two resistor groups 25 and 26 serve as a single resistor having a resistance value of R₁. And therefore, if the signals W and X are equal in state to the signal M₁, the application of the signals W and X to the junction point P₁ respectively through the resistor groups 25 and 26 is equivalent to an application of the signal M₁ to the junction point P₁ through a resistor of R₁. Similarly, if the signals Y and Z are equal in state to the signal M₀, the application of the signals Y and Z to the junction point P₀ respectively through the resistor groups 28 and 29 is equivalent to an application of the signal M₀ to the junction point P₀ through a resistor of R₁. Thus, when one of the signals S₀ to S₄ is outputted, the mantissa-part DAC 22 operates as a twelve-bit DAC. In this case, the digital shifter 21 outputs from the output terminals TD₁₀ to TD₀ thereof those consecutive eleven bits among the bits J₁₄ to J₀ which are selected in accordance with the one of the signals S₀ to S₄ (see the arrows shown in Fig. 4). Thus, in the case where the magnitude of the input data D IN is greater than a predetermined value, the mantissa-part DAC 22 operates as a twelve-bit DAC, so that the minimum step of variation of the output signal V OUT is rendered small, whereby the harmonic distortion thereof is minimized. When the magnitude of the input data D IN is relatively small, that is, when the output signal V OUT is not greater than -30 dB but greater than -36dB, the signal S₅ is outputted. In this case, the relation between the signal M₁ and the signals W and X is the same as that in the above case, however the relation between the signal M₀ and the signals Y and Z is changed to that shown in Table 1. More specifically, the signals Y and Z are in inversed relation in state to each other irrespective of the state of the signal M₀. In this case, if one of the two signals Y and Z is at the ground level, the other of the signals is at a source voltage level (V DD ), so that the potential at the junction point P₀ becomes equal to V DD /2. As a result, the function of the mantissa-part DAC 22 in this case becomes equivalent to that of the mantissa part DAC 22 from which the least significant bit stage is removed. In other words, the mantissa-part DAC 22 operates as a DAC of eleven-bit type. When the signal S₅ is outputted, the digital shifter 21 outputs the bits J₀ to J₉ from the output terminals TD₁ to TD₁₀, respectively, so that the lower-order ten bits of the input data D IN are supplied to the mantissa-part DAC 22. When the magnitude of the input data D IN is smaller than that in the above case, the signal S₆ is outputted from the exponent value detector 13. Consequently, the signals W and X are in inversed relation to each other, and the signals Y and Z are also in inversed relation to each other. And therefore, the potentials at the junction points P₁ and P₀ both become equal to half of the source voltage V DD , i. e., V DD /2, so that the least significant two bits are removed from the mantissa-part DAC 22. Thus, when the signal S₆ is outputted, the mantissa-part DAC 22 operates as a DAC of a ten-bit type. In this case, the digital shifter 21 outputs the bits J₀ to J₈ from the output terminals TD₂ to TD₁₀, so that the lower-order nine bits of the input data D IN are supplied to the mantissa-part DAC 22. Thus, when the magnitude of the input data D IN is small, the mantissa-part DAC 22 operates as a DAC of an eleven-bit type or a ten-bit type, so that the total harmonic distortion of the output signal V OUT is prevented from increasing. Description will now be given as to the total harmonic distortion characteristic of the above described DAC 10. Fig. 7 illustrates total harmonic distortions of various DACs in terms of signal levels of output signals thereof. In Fig. 7, areas lying between two adjacent lines inclined downwardly in the right-hand direction respectively define total harmonic distortions of DACs of ten-bit to sixteen-bit types which have no exponent-part DAC. The area between two adjacent broken lines defines the total harmonic distortion of an ordinary floating-point-type DAC which has a ten-bit type mantissa-part DAC having an accuracy of ten bits and a seven-stage exponent-part DAC. As the exponent-part DAC of this ordinary floating-point-type DAC is of a seven-stage type, the total harmonic distortion becomes flat in the region of above -36dB. The area hatched by lines inclined downwardly in the right-hand direction defines the total harmonic distortion of another ordinary floating-point-type DAC which has a twelve-bit type mantissa-part DAC having an accuracy of ten bits and a five-stage exponent-part DAC. Since the mantissa-part DAC of this ordinary floating-point-type DAC is inferior in accuracy to the mantissa-part DAC of the first-mentioned ordinary floating-point-type DAC by two bits, the total harmonic distortion is deteriorated in the region of smaller signal levels. On the other hand, the area hatched by lines inclined downwardly in the left-hand direction defines the total harmonic distortion of a still another ordinary floating-point-type DAC which has a twelve-bit type mantissa-part DAC having an accuracy of twelve bits and a five-stage exponent-part DAC (i. e., an ideal DAC of a floating-point type). As the exponent-part DAC of this ordinary floating-point-type DAC is of a five-stage type, the error in the mantissa-part DAC is rendered 1/2⁴ times smaller. And therefore, the total harmonic distortion of this ordinary floating-point-type DAC with respect to the signals below - 24dB is the same as that of the sixteen-bit DAC having no exponent-part DAC, and the total harmonic distortion thereof in the region of above -24dB is flat. With the aforesaid DAC 10 provided in accordance with the first embodiment of the invention, when the signal level is small, the number of bits of the mantissa-part DAC 22 becomes equal to ten, wherein the accuracy thereof is also ten bits. And, the number of stages of the exponent-part DAC 50 is seven in this case, so that the error in the mantissa-part DAC 22 is rendered 1/2⁶ smaller. Thus, when the signal level is below - 36dB, the aforesaid DAC 10 operates as a 16-bit DAC having no mantissa-part. When the signal level is above -24dB, the signal S₄ is outputted, so that only the five stages of the exponent-part DAC 50 operates. Consequently, the signal level of the output signal becomes greater, so that the total harmonic distortion of the DAC 10 is flat. When the signal level is between -24dB and -36dB, the number of bits of the mantissa-part DAC 22 becomes equal to eleven bits, wherein the accuracy of the mantissa-part DAC 22 is ten bits. In this case, the number of stages of the exponent-part DAC 50 is six, so that the total harmonic distortion of the DAC 10 is defined by an area in the form of steps. Thus, the total harmonic distortion of the DAC 10 according to this embodiment is defined by an area substantially equal to the area for the ideal floating-point-type DAC hatched by the lined inclined downwardly in the left-hand direction. A second embodiment of the present invention will now be described with reference to Fig. 8. A DAC 10a according to this second embodiment differs from the DAC 10 shown in Fig. 2 in the following respects: An R resistor (R1) of the last bit-stage of an R-2R ladder resistor network 23a of a mantissa-part DAC 22a is connected with a resistor network 60 of an error correction circuit 61. The resistor network 60 comprises resistors 62 to 71 each having a resistance value of R₁. The error correction circuit 61 further comprises inverters 72 to 79, NAND gates 80 to 83 and a NOR gate 84. An inversion of the bit J₁₅ by an inverter 85 is supplied to one input terminal of an exclusive OR gate 86, the other input terminal of which is connected through a resistor 87 to the source of voltage V DD . The other input terminal of the exclusive OR gate 86 is also connected to a terminal 88. If the error correction circuit 61 should work when the MSB of the input data D IN is in the state of "0", a "0" signal is applied to the terminal 88. On the other hand, if the error correction circuit 61 should work when the MSB of the input data D IN is in the "1" state, a "1" signal is applied to the terminal 88. Thus, when an error correction is required, a "1" signal is outputted from an output terminal of the exclusive OR gate 86 to the error correction circuit 61. Three input terminals 87 to 89 are provided for receiving control bits A, B and C, respectively. The control bit A is supplied together with the output signal of the NOR gate NOR2 of the mantissa-part-bit control circuit 40 to input terminals of a NAND gate 90. The control bit B is supplied together with the output signal of the inverter INV1 of the mantissa-part-bit control circuit 40 to input terminals of a NOR gate 91. Similarly, the control bit C is supplied together with the output signal of the NOR gate NOR2 to input terminals of a NAND gate 92. Output signals of the gates 90 to 92 are supplied to the error correction circuit 61 respectively through inverters 93 to 95. With this construction, when the output signal of the exclusive OR gate 86 is "1" and when both of the signals S₅ and S₆ outputted from the exponent-value detector 13 are "0", the states of the output signals of the inverters 72 to 75 vary in accordance with the states of the control bits A to C so that the voltage of an output signal S B of the mantissa-part DAC 22a is shifted as shown in Table 2. A B C shift amount 0 0 0 -V LSB /2 0 0 1 -V LSB /4 0 1 0 0 0 1 1 +V LSB /4 1 0 0 +V LSB /2 It will be appreciated from Table 2 that when the control bits A, B and C are, for example, "0", "0" and "0", respectively, the voltage of the signal S B is decreased by an amount equal to half of V LSB , wherein V LSB is a voltage which is controlled by the last-bit stage of the mantissa-part DAC 22a. When any one of the signals S₅ and S₆ is "1", the output of the NOR gate NOR2 is rendered "0", while the output of the inverter INV1 is rendered "1". As a result, the output signals of the NAND gate 90, NOR gate 91 and NAND gate 92 are rendered "1", "0" and "1", respectively, which is equivalent to the case where the control bits A, B and C are equal respectively to "0", "1" and "0". And therefore, no correction is carried out in this case. In other words, the correction of the output signal S B is performed only when the mantissa-part DAC 22a operates as a twelve-bit DAC. Although the maximum number of bits of the mantissa-part DACs 22 and 22a and the number of stages of the exponent-part DAC 61 are 12 and 7, respectively, in the aforesaid embodiments, these numbers can be changed to any desired values. Also, the number of bits of the input data D IN should not necessarily be restricted to "16". As described above, with the DAC according to the present invention, the accuracy of the mantissa-part DAC in terms of the resolution thereof can be enhanced at lower signal levels, while the minimum step of variation of the output signal of the mantissa-part is decreased at higher signal levels. With this DAC therefore, the total harmonic distortion can be decreased over a range from the lower signal levels to the higher signal levels.

Claims: A digital-to-analog converter for converting digital input data into an analog output signal comprising: (a) detector means (13) responsive to the digital input data for detecting the magnitude thereof, said detector means outputting a detection signal representative of the magnitude of said digital input data; (b) digital-to-analog converting means (22) of a predetermined number of bits responsive to said detection signal for converting a mantissa-part of said digital input data into an intermediate analog signal; (c) exponent converting means (50) responsive to said detection signal, said exponent converting means outputting said converted analog signal as the analog output signal; characterized by: (d) control means (40), incorporated in said digital-to-analog converting means, responsive to said detection signal for changing the number of operative bits of said digital-to-analog converting means (22), said control means (40) decreasing the number of operative bits of said digital-to-analog converting means (22) with a decrease of the magnitude to said digital input data. A digital-to-analog converter according to claim 1, wherein the digital input data is in the form of two's complement of the magnitude thereof, said detector means detecting the number of leading "0" bits of the digital input data when the digital input data is positive and detecting the number of leading "1" bits of the digital input data when the digital input data is negative, said detector means outputting said detected number as said detection signal. A digital-to-analog converter according to claim 2, wherein said digital-to-analog converting means comprises: digital shifting means responsive to said detection signal from said detector means for shifting the digital input data in the direction of the most significant bit thereof by bits equal in number to said detected number to form said mantissa part; and a digital-to-analog converting circuit of the predetermined number of bits for converting said mantissa part into an analog form to produce said intermediate analog signal. A digital-to-analog converter according to claim 3, wherein said digital-to-analog converting circuit comprises an R-2R resistor ladder network of the predetermined number of stages, the 2R resistors of said ladder network being supplied with said mantissa part of the digital input data, one terminal end of said ladder network on the side of the least significant bit stage thereof being supplied with a bias voltage to determine the center of range of said intermediate analog signal, said intermediate analog signal being outputted from the other terminal end of said ladder network. A digital-to-analog converter according to claim 4, wherein said control means comprises a control circuit which causes the 2R resistors of the least significant bit stages of said ladder network to be supplied with said bias voltage to thereby preventing said least significant bit stages from functioning, the number of said least significant bit stages being determined in accordance with said detection signal. A digital-to-analog converter according to claim 1, wherein said exponent converting means comprises: circuit means responsive to said intermediate analog signal to produce a predetermined number of analog signals whose voltages are 2 -n (n = 0, 1, 2, ...) magnifications of said intermediate analog signal; and switch circuit means connected to said circuit means for selectively outputting one of said predetermined number of analog signals as the analog output signal in accordance with said detection signal. A digital-to-analog converter according to claim 6, wherein said circuit means comprises an R-2R resistor ladder network connected at one end thereof to said digital-to-analog converting means. A digital-to-analog converter according to claim 4 further comprises terminal means for receiving a predetermined number of control bits and a correction circuit means connected with said one terminal end of said R-2R resistor ladder network, said correction circuit means causing said bias voltage at said one terminal end of said R-2R resistor ladder network to vary in accordance with said control bits. A digital-to-analog converter according to claim 8, wherein said correction circuit means is further responsive to a sign bit of the digital input data, and causes said bias voltage at said one terminal end of said R-2R resistor ladder network to vary in accordance with said control bits only when said sign bit is in a predetermined state.

Inventors: ISHIDA, KATSUHIKO C/O NIPPON GAKKI, KOHDAKA, TAKAYUKI C/O NIPPON GAKKI, OGATA, TAKASHI C/O NIPPON GAKKI, TAKAHASHI, TOSHIYUKI C/O NIPPON GAKKI
Applicants: YAMAHA CORPORATION
Application year: 1986
Main classification: H03M1
IPC codes: H03M1