MEMORY DEVICE

Abstract: First binary coded bits of information are read synchron­ ously from first positions in the memory and second binary coded bits of information are read from, or written in, second positions in the memory asynchronously without affecting the reading of the first bits of information from the memory. In providing for the synchronous reading of the first bits of information, a plurality of channels are sequentially activated at a frequency such as 25 megahertz. Information from a plurality of pairs of data lines are introduced into a pair of buses at a frequency corresponding to a clock frequency of 125 megacycles. The information in the buses is sampled upon the occurrence of the first polarity in synchronizing signals derived from the clock signals and having a frequency of 62.5 megahertz and is evaluated in a first pair of output lines upon the occurrence of the second polarity in the syn­ chronizing signals. The evaluation is accelerated upon the occurrence of the second polarity in the synchronizing signals, and the evaluated signals on the first pair of output lines are neutralized upon the occurrence of the first polarity in such synchronizing signals. Similarly, the information in the buses is sampled upon the occurrence of the second pol­ arity in the synchronizing signals and is evaluated in a second pair of output lines upon the occurrence of the first polarity in the synchronizing signals. The evaluated signals in the first and second pairs of output lines are then processed on an exclusive basis to insure that only one of the evaluated signals can be introduced at any one time to a resultant line.

Description: The present invention relates to a circuit for reading and writing binary coded information according to the precharacterizing part of claim 1. Random access memories are provided for storing binary coded information. These memories are versatile because the binary information at different positions in the memory can be read from the memory and because binary coded information can be written in the memory at any desired position to update information previously stored in the memory at such positions. The information read from the memory can be processed by a digital computer or a data processor to obtain certain desired operations such as the movements of a control mechanism and the information written into the memory to update the memory may be obtained from the actual movements of the control mechanism. In this way, any differences between the actual and desired movements of the control mechanism can be corrected. Random access memories now in use have certain limitations. These result in large part from limitations in the operation of the transducing system associated with the memory for reading information from the memory or writing information in the memory. One of these limitations results from the inability of the transducing system simultaneously to read information from one position in the memory and write information into a second position in the memory. A further limitation results from the limited speed in reading information from the memory or writing information in the memory. This limited speed in turn curtails the speed at which the digital computer or data processing system associated with the memory is able to process information. A third limitation results from the inability of the system to read binary coded information from the memory on a synchronous basis relative to the clock signals and simultaneously read binary coded information from, or record binary coded information in, the memory on an asynchronous basis. A considerable effort has been made over an extended number of years to provide a random access memory system which will overcome the limitations discussed in the previous paragraph. Such effort has been particularly intent in view of the rapid expansion in the uses and perfection of data processing. In spite of such efforts, the capabilities of the random access memory systems still trail the capabilities of the associated data processors and accordingly impose limitations on the operation of these data processors. From IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, December 1984, pages 999-1007, New York, U.S., R. Pinkham, et al: "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applications", a high speed dual port memory with simultaneous serial and random mode access is known. This dual port memory consists of a 64Kx1 DRAM and a 256 bit shift register. The 256 bits of one row of the DRAM can be transferred in one memory cycle in parallel to the shift register from where they can be shifted out serially while other storage cells of the DRAM are accessible simultaneously and asychronously. The advantage of said dual port memory can be seen in that the DRAM array may be read from or written in to while data is shifted simultaneously serially into or out of the shift register. EP 0 121 726 describes a dynamic storage means in which each memory cell is constituted by a capacitor. Each memory cell can simultaneously be written and read within one cycle and multiple simultaneous read outs are also possible. From Electrical Design News, Vol. 28, No. 18, 1 Sept. 1983, pages 147-154, Boston, Massachusetts, US: K.W. Pope: "Asynchronous dual-port RAM simplifies multiprocessor systems", an asychronous dual-port RAM is known which allows independent access to the memory-core for two external devices which could, for example, be two microprocessors or a microprocessor and a CRT monitor. Each external device can operate at its own clock rate. Due to the two port structure cross-talk-related problems are reduced. This dual-port RAM is described in more detail in Applications Information SY2130/SY2131 1024x8 Dual Port Random Access Memory by Synertek, published in November 1984. The respective Figure 2.5 shows the six-transistor, two-resistor cell used in the SY2130/SY2131. It is mentioned that the dual-port RAM contains a contention logic which prevents simultaneous access from both ports. The SY2130/SY2131 can, however, also be brought into a mode in which contention is ignored so that both ports are allowed to have access to the memory port at all times and, therefore, simultaneous access is possible. The six-transistor, two-resistor cell does not have means, however, for preventing disturbances caused by a reading operation from affecting a simultaneous writing operation. It is the object of the present invention, therefore, to provide a dual port memory in which each memory cell can simultaneously be accessed from both ports whereby disturbances resulting from the reading from one port are prevented from affecting a simultaneous writing operation from the other port. This object is solved by claim 1. In the following, preferred embodiments of the present invention are described in connection with the accompanying figures wherein: Figure 1 is a schematic block diagram of a random access memory and of a system for reading first bits of information from first positions in the memory on a synchronous basis relative to clock signals and simultaneously reading second bits of information from, or writing second bits of information in, second positions in the memory on an asynchronous basis without having the reading of the first bits of information from the memory affect the reading or writing of the second bits of information; Figure 2 is a block diagram of a system for producing synchronizing signals for use in the read-write-system of Figure 1; Figure 3 illustrates waveforms of clock signals which are produced by the system shown in Figure 2; Figure 4 is a diagram of circuitry which is used in the read-write-system shown in Figure 1 to read first bits of information from a first position in the memory and simultaneously read second bits of information from, or write second bits of information in, second positions in the memory without having the reading of the first bits of information from the memory affect the reading or writing of the second bits of information; Figured 5 is a diagram of circuitry for amplifying signals produced by the circuitry shown in Figure 4 and for providing the amplified signals with optimal characteristics; Figure 6 is a schematic diagram of circuitry for randomly activating a plurality of channels and for introducing to a pair of buses, in accordance with the activation of the different channels, the amplified signals produced by circuitry as shown in Figure 5; Figure 7 is a schematic diagram of circuitry for sampling signals from the buses of Figure 6 during the occurrence of a first polarity in the synchronizing signals and for evaluating the sampled signals upon the occurrence of a second polarity in the synchronizing signals and for introducing the evaluated signals to pairs of output lines; and Figure 8 is a schematic diagram of circuitry for processing the signals produced on the output lines in Figure 7 to introduce the signals from only one of the output lines to a resultant line at each instant. Figure 1 illustrates one embodiment of the invention in block form. The embodiment shown in Figure 1 includes a random access memory generally indicated at 10. The random access memory is adapted to store a plurality of bits of binary coded information in an array in which the position of each binary coded bit in the array is identified by an individual distance along a pair of coordinate axes such as an x-axis and a y-axis. The random accesss memory is adapted to provide an erasable storage of binary coded information in which the binary coded information at different positions in the memory can be constantly updated. Random access memories are commercially available which can store tens, and even hundreds, of thousands of bits of binary coded information in an array in a relatively small area. The binary coded information may be represented by logic levels of signals in which a first logic level or amplitude represents a binary "1" and a second logic level represents a binary "0". A slow port generally indicated at 12 is associated with the random access memory 10. The port 12 is adapted to read information from specified positions in the memory 10 or to write binary information in specified positions in the memory. The reading of such binary coded information from the memory 10 is indicated by an arrow 14 and the writing of such information in the memory is indicated by an arrow 16. The reading and writing of such binary coded information may occur on an asynchronous basis relative to clock signals at a suitable frequency such as 125 megahertz. A fast port generally indicated at 18 is also associated with the memory 10. As indicated by an arrow 201, the fast port 18 is adapted to read information from the memory 10 on a synchronous basis relative to the clock signals at a relatively high frequency such as frequencies of at least 125 megahertz. This frequency is considerably higher than the frequency of the signals in the slow port 12. The signals read in the fast port 18 may be introduced to a digital-to-analog converter 22 which converts the binary signals from the fast port 18 into corresponding analog signals for subsequent processing. In order to obtain the reading of signals in the fast port 18, the operation of the fast port 18 may be controlled as by a multiplexer 24. The multiplexer 24 produces signals at a reduced frequency, such as approximately twenty-five megahertz (25 mhz), on a plurality (such as 5) of lines 26. The signals in each of the lines 26 are shifted in phase relative to the signals in the other ones of the lines 26. When these signals are combined in the multiplexer 24, the output of the multiplexer is at approximately 125 megacycles. Figure 2 illustrates in block form a system for generating clock signals. The system shown in Figure 2 includes a clock signal generator 30 which produces signals at a particular frequency such as one hundred and twenty-five megahertz (125 mhz). These signals are illustrated at 32 in Figure 3. The signals from the clock generator 30 are introduced to true and false input terminals of a flip-flop 34 also having true and false output terminals. The true output terminal of the flip-flop 34 is connected to the true input terminal of a flip- flop 36. The false output signals from the flip-flop 34 are amplified and inverted by an amplifier-inverter 38 and are introduced to the false input terminal of the flip-flop 36. An output line 40 extends from the false output terminal of the flip-flop 36. Similarly, a connection is made from the false output terminal of the flip-flop 34 to the true input terminal of a flip-flop 42. The false input terminal of the flip-flop 42 receives the signals from an amplifier-inverter 44 corresponding in construction and operation to the amplifier-inverter 38. The operation of the amplifier-inverter 44 is controlled by the signals on the true output terminal of the flip-flop 34. The true output terminal of the flip-flop 42 is connected to an output line 46. The flip-flop 34 is alternately triggered to the true and false states when the signal 32 changes from a negative polarity to a positive polarity. The flip-flop 34 accordingly produces the signals 32 in Figure 3. When the flip-flop 34 is triggered to the true state, it triggers the flip-flop 36 to the true state. In the rising amplitude of the next cycle of the clock signals 32, the flip-flop 34 is again triggered to the true state. This causes a negative signal to be produced on the false terminal of the flip-flop 34. This signal is inverted by the amplifier-inverter 38 to trigger the flip-flop 36 to the false state. In this way, synchronizing signals are produced on the output terminal 40 with a frequency one-half (1/2) that of the clock signals 32 and with a polarity as indicated at 50 in Figure 3. The flip-flop 42 also produces synchronizing signals 52 with a frequency one-half (1/2) that of the clock signals 32 but with a polarity opposite to the polarity of the signals 50 in Figure 3. The signals 52 produced by the flip-flop 42 are introduced to the line 46. Figure 4 illustrates circuitry for reading information in the fast port 18 and reading information in, or recording information from, the slow port 12 in Figure 1. The circuitry shown in Figure 4 provides for the processing of information in the slow port 12 without any interference from the reading of information in the fast port 18. The circuitry shown in Figure 4 includes lines 60, 62, 64, 66, 68 and 72. The lines 60 and 66 provide signals respectively coded for logic states of "true" and "false" in a binary bit to be processed in the slow port 12. These signals are respectively indicated as "SBL n " and " SBL n ". Similarly, the lines 62 and 64 provide signals respectively coded for logic states of "true" and "false" in a binary bit to be processed in the fast port 18. These signals are respectively indicated as "FBL n " and " FBL n ". The line 72 provides signals coding for the "x" word to be processed in the slow port 12. These signals are indicated as "SWL x ". In like manner, the line 68 provides signals coding for the "x" word to be processed in the fast port 18. These signals are indicated at "FWL x ". In other words, the logic levels of signals in the lines 60 and 66 indicate the value of the n th bit in the x word in slow port and the lines 62 and 64 indicate the value of the n th bit in the x word for the fast port. The signals on the line 60 are introduced to the source of an n-transistor 75, the gate of which receives signals from the line 72. The drain of the transistor 75 is connected to the drain of a p-transistor 76 and to the source of an n-transistor 78, the drain of which is connected to a suitable reference potential such as a ground 80. The gates of the transistors 76 and 78 have a common connection with the gate of an n-transistor 82. The drain of the transistor 82 may be common with the reference potential such as the ground 80. The source of the transistor 82 is connected to the source of an n-transistor 84. The gate of the transistor 84 receives signals from the line 68 and the source of the transistor 84 receives signals from the line 62. The line 66 is connected to the source of an n-transistor 88, the gate of which receives signals from the line 72. The drain of the transistor 88 has a common connection with the drain of a P-transistor 90 and the source of an n-transistor 92. The source of the transistor 90 receives an energizing potential such as approximately +5 volts from a suitable voltage source 94, which is also connected to the source of the transistor 76. The gates of the transistors 90 and 92 have a common connection with the drain of the transistor 76, the source of the transistor 78 and the gate of a transistor 96. The drain of the transistor 90 and the source of the transistor 92 have a common connection with the gates of the transistors 76 and 78. The drain of the transistor 96 is connected to the reference potential such as the ground 80. The source of the transistor 96 and the drain of an n-transistor 98 have a common potential. The gate of the transistor 98 receives the signals on the line 68 and the source of the transistor 98 receives the signals on the line 64. Amplifiers 97 and 99 are respectively connected to the lines 60 and 66. The amplifiers are activated by signals on "Enable" lines. When the amplifiers 97 and 99 are enabled, they pass "write" signals through the amplifiers. The "write" signals passing through the amplifiers 97 and 99 respectively represent a binary "true" and a binary "false". Current sources 136 and 138 are shown in Figure 4 as being connected to the lines 62 and 64. These current sources correspond to transistors 136 and 138 in Figure 6. Resistors 124 and 126 are shown in Figure 4 as being respectively connected from the signal generators 136 and 138 to the reference potential such as ground. The resistors 124 and 126 are respectively shown as transistors 124 and 126 in Figure 6. Resistances 93 and 95 are also respectively connected between the lines 60 and 66 and the voltage source 94. The transistor 84 becomes conductive when a signal of high amplitude is produced on the line 68 to indicate the selection of a particular word, such as the "x" word, and a high signal is simultaneously produced on the line 62 (if the transistor 82 is non-conductive) to indicate a binary value of "1" for a particular bit, such as the "n" bit, in the selected word. When the transistor 84 becomes conductive, current flows through a circuit, including the line 62, the transistor 84 and the transistor 82 if the transistor 82 is conductive. This current indicates that the particular bit in the selected word has a binary value of "1". A high gate impedance in the transistor 82 isolates the current in the line 62 from the reading and recording of information in the lines 60 and 66. at the "x" word and the "n" bit. In like manner, current flows through a circuit including the line 64, the transistor 98 and the transistor 96 when a signal of high amplitude is produced on the line 68 to indicate the selection of a particular word such as the "x" word, and a signal of high amplitude is simultaneously produced (if the transistor 96 is conductive) on the line 64 to indicate a binary value of "0" for the bit , such as the "n" bit, in the FBL line in that word. A high gate impedance in the transistor 96 isolates the current in the line 64 from the reading and recording of information in the lines 60 and 66. The operation of the circuitry shown in Figure 4 may be seen from several examples. In one example, a binary value of "1" may be read by the fast port 18 in Figure 1 at the "n" bit of the "x" word. Under such circumstances, the transistors 84 and 98 may become conductive because of the introduction of a high voltage to their gates from the line 68. Because of the inter-connections between the gate of each of the transistors 76 and 90 and the drain of the other one of such transistors, the transistors 76 and 90 operate as a flip-flop. Thus, only one of the transistors 76 and 90 can be conductive at any one time. As a result, assuming that a high voltage is produced on the drain of the transistor 76, a low voltage is simultaneously produced on the drain of the transistor 90. The low voltage on the drain of the transistor 90 prevents the transistor 82 from being conductive and prevents current from flowing through a circuit including the line 62, the transistor 84 and the transistor 82. The high voltage on the drain of the transistor 76 is introduced to the gate of the transistor 96 to make the transistor 96 conductive. This causes current to flow through a circuit including the current source 138, the line 64, the transistor 98 and the transistor 96. This current causes the current normally flowing through the resistance 126 from the signal generator 138 to be reduced. However, the current normally flowing through the current source 136 and the resistance 124 continues to be maintained because of the non-conductivity of the transistor 82. This causes the voltage on the line 64 to be reduced relative to the voltage on the line 62. This voltage difference indicates a reading of a binary "1" in the fast port 18. In the next example, a binary "1" is read from the memory 10 by the slow port 12 at the "n" bit of the "x" word. Under such circumstances, a high voltage is introduced to the gates of the transistors 75 and 88 to provide for transistors to be conductive. The resultant high voltage on the source of the transistor 75 is introduced to the gate of the transistor 92 to make the transistor 92 conductive. Current accordingly flows through a circuit including the voltage source 94, the resistance 95, the transistor 88 and the transistor 92. The resultant voltage drop across the resistance 95 causes the voltage on the line 66 to be less than the voltage on the line 60. This voltage difference indicates the reading of a binary "1" by the slow port 12. The transistor 88 has a higher impedance than the transistor 92. This causes a relatively low voltage to be produced on the source of the transistor 92. This voltage is introduced to the gate of the transistor 78 to make the transistor 78 non-conductive. As a result, current cannot flow through a circuit including the line 60, the transistor 75 and the transistor 78. This maintains the voltage on the line 60 higher than the voltage on the line 66 as discussed in the previous paragraph. In the third example, a binary "1" is written in the memory 10 by the slow port 12 at the "n" bit of the "x" word. Because the "x" word is being activated, the voltage on the transistor 75 is high. At this instant, the amplifiers 97 and 99 are enabled by a signal on the "enabled" line. Upon being enabled, the "write" signal is introduced by the amplifier 97 to the line 60 as a positive voltage. At the same time, a voltage having the reference such as ground is introduced to the line 66 through the amplifier 99. This low voltage is introduced to the source of the transistor 88. A current is accordingly forced by the amplifier 99 to flow through a circuit including the voltage source 94, the transistor 90, the transistor 88 and the line 66. The high voltage on the line 60 causes the transistor 75 to become conductive so that a high voltage is produced on the source of the transistor. This voltage is introduced to the gate of the transistor 92 to make the transistor 92 conductive. Current accordingly flows through a circuit including the voltage source 94, the transistor 90 and the transistor 92. Since the transistor 90 has a considerably higher impedance than the transistor 92, this current flow causes the voltage on the source of the transistor 92 to have a potential approaching the reference potential such as ground. This voltage is introduced to the gate of the transistor 78 to maintain the transistor 78 non-conductive and thereby maintain the high potential on the source of the transistor 75. The arrangement described above is advantageous in that the same bit of information may be simultaneously read from memory 10 by the fast port 18 and the slow port 12. Actually, the fast port 18 may read the binary coded information previously recorded as the value of a particular position in the memory while the slow port 12 may be writing new binary coded information for that position in the memory. The arrangement shown in Figure 4 accomplishes this by providing the high gate impedances in the transistors 82 and 96. These high gate impedances isolate, from the slow bit lines 60 and 66 of the slow port 12, any disturbances resulting from the reading through the fast port 18 of the binary coded information from the particular position in the memory 10. As a result, when there is a time coincidence with the writing of binary coded information through the slow port 12 in the particular position in the memory, any disturbances resulting from such reading through the fast port of the binary coded information from the particular position in the memory will be prevented from affecting the writing through the slow port 12 of such binary coded information in the particular position in the memory 10 in such a time coincidence. Figure 5 illustrates circuitry for processing the currents flowing in the lines 60, 62, 64 and 66 in Figures 4 so that the signals have a common mode and the deviations of the signals from the common mode represent binary information. The circuitry shown in Figure 5 includes the lines 60, 62, 64 and 66. The lines 60 and 66 are respectively connected to the sources of n-transistors 120 and 122 having their drains connected to the voltage source 94. Connections are respectively made from the gates of the transistors 120 and 122 to the voltage source 94. The drains of the transistors 124 and 126 are respectively connected to the lines 62 and 64. The sources of the transistors 124 and 126 receive the reference potential such as the ground 80. The gates of the transistors 120 and 122 are also respectively connected to gates of n-transistors 128 and 130 and are further connected to receive a positive potential from the voltage source 94. The sources of the transistors 128 and 130 respectively receive the signals on the lines 62 and 64. The signals on the drains of the transistors 128 and 130 are respectively applied to intermediate lines 132 and 134 and are also respectively applied to the drains of p-transistors 136 and 138. The sources of the transistors 136 and 138 have a positive potential such as +5 volts applied from the voltage source 94. The gates of the transistors 136 and 138 have a voltage bias (indicated as "VPB") applied to them to bias the transistors to produce a low current. The transistors 128 and 130 respectively operate as cascode amplifiers. This causes a gain in the order of 1-1/2 to 2 to be produced in each of these cascode amplifiers when a signal is introduced to a particular one of the lines 62 and 64 associated with that amplifier. The signal produced as a result of the operation of the cascode amplifier 128 is introduced to the line 132 and the signal produced as a result of the operation of the cascode amplifier 130 is introduced to the line 134. The transistors 136 and 138 are biased, by the voltages applied to their gates, to produce a low current in the transistors at all times. The low current in the transistor 136 flows through the cascode amplifier defined by the transistor 128 and through the transistor 124 to the reference potential such as the ground 80. Similarly, the current through the transistor 138 flows through the cascode amplifier defined by the transistor 130 and through the transistor 126 to the reference potential such as the ground 80. The relatively low currents through the transistors 124 and 126 establish a common mode in the lines 62 and 64 to insure that noise in the lines is reduced. In this way, the voltage swings in these lines from the common mode represents binary information. The intermediate lines 132 and 134 are also shown in Figure 6. These lines are designated in Figure 6 as "FBLC n " and '' FBLC n . Other corresponding pairs of lines are indicated in Figure 6 at 132a and 134a, (respectively designated as "FBLC n+1 " and "FBLC n+1 "), 132b and 134b (respectively designated as "FBLC n+2 " and FBLC n+2 ") and 132c and 134c, (respectively designated as " FBLC n+3 " and " FBLC n+3 "). A plurality of channels are also indicated in Figure 7 at 140a, 140b, 140c and 140d. The channels 140a, 140b, 140c and 140d operate as the equivalent of an x-y matrix with the lines 132 and 134, 132a and 134a, etc., to select a particular bit in the memory 10. The lines 132, 134, 132a, 134a, 132b, 134b, 132c, and 134c respectively have common connections with the drains of p-transistors 142-156 (even numbers only). The signals in the channel 140a are introduced to the gates of the transistors 142 and 146; the signals in the channel 140b are introduced to the gates of the transistors 144 and 148; the signals in the channel 140c are introduced to the gates of the transistors 150 and 154; and the signals in the channel 140d are introduced to the gates of the transistors 152 and 156. The drains of the transistors 142, 144, 150 and 152 have a common connection with a bus 154 and with the drain of a p-transistor 157. Similarly, the drain of the transistors 146, 148, 154 and 156 have a common connection with a bus 158 and with the drain of a p-transistor 160. The gates of the transistors 157 and 160 are biased to produce a current of relatively low amplitude through the transistors. A voltage is applied to the sources of the transistors from the voltage source 94. The circuitry of Figure 6 constitutes a switching matrix. For example, when the amplitude of the signal on the line 132 is high and the channel 140a is energized, current flows through the bus 154 and the transistor 142. Similarly, when a signal is produced on the line 134a to represent a binary "0" and the channel 140b is activated, current flows through the bus 158 and transistor 148 and then bus 158, to. The transistors 157 and 160 operate in a common mode similar to the operation of the transistors 124 and 126 in Figure 5. As a result of their common mode operation, the transistors 157 and 160 insure that any variations in the voltages on the lines 154 and 158 represent binary coded information. As will be appreciated, the signals produced in the lines 154 and 158 represent signals read from the memory 10 by the fast port 10. The signals on the buses 154 and 158 are respectively represented as "FDB x " and " FDB x ". The buses 154 and 158 of Figure 6 are also shown in Figure 7. The synchronizing signal lines 40 and 46 of Figure 2 are also shown in Figure 7. The signals on the lines 154 and 158 are respectively introduced to the sources of p-transistors 200 and 202 and the signals on the clock line 40 are introduced to the gates of these transistors. The drain of the transistor 200 has common connections with the drain of a p-transistor 204, the drain of an n-transistor 206, the gate of an n-transistor 208 and the gate of an n-transistor 210. Similarly, connections are made from the drain of the transistor 202 to the drain of a p-transistor 214, the drain of the transistor 208, the gate of the transistor 206 and the gate of an n-transistor 216. The sources of the transistors 204 and 214 receive a positive potential from the voltage source 94. The sources of the transistors 206, 208, 210 and 216 have a common connection with the drain of an n-transistor 218. The source of the transistor 218 is common with the reference potential such as the ground 80. The gate of the transistor 218 receives the signals on the synchronizing line 40. The synchronizing line 40 is also connected to the gates of p-transistors 220, 222 and 224. The sources of the transistors 220, 222 and 224 receive a positive potential from the voltage source 94. The drain of the transistor 220 has common connections with the gate of the transistor 214 and the drain of the transistor 216 and with an output line 226. The output line 226 is designated as "DL x ". Output connections are made from the drain of the transistor 222 to the gate of the transistor 204, the drain of the transistor 210 and an output line 228. The output line 228 is designated as " DL x ". The drain of the transistor 224 has a common connection with the drain of the transistor 218. When the amplitude of the clock signal on the line 40 is low, the transistor 200 becomes conductive. A signal of high amplitude is accordingly introduced to a line 240 common to the drain of the transistor 204 and the drain of the transistor 206. This signal has a higher amplitude than the signal on a line 242 common to the drain of the transistor 214 and the drain of the transistor 208. The reason is that the transistor 202 remains non-conductive because of a low voltage on the line 158. Upon the occurrence of a positive polarity in the clock signal 50 on the line 40, the transistor 218 becomes conductive because of the introduction of the synchronizing signal to the gate of the transistor. This causes the voltage on the drain or the transistor 218 to decrease to substantially the reference potential such as the ground 80. Because of the high potential on the line 240, the transistor 208 becomes conductive and produces on its drain a potential approaching the reference potential such as the ground 80. This voltage is introduced to the gate of the transistor 206 to insure that the transistor 206 will remain non-conductive. When the voltage on the drain of the transistor 218 approaches the reference potential such as the ground 80, the transistor 210 becomes conductive because of the introduction of the high voltage to its gate from the line 240. This causes the voltage on the bus 228 to approach the reference potential such as ground. The resultant reference potential, such as the ground 80, on the gate of the transistor 204 causes the transistor 204 to become conductive. This prolongs a voltage of high amplitude on the line 240 and insures that the transistors 208 and 210 will be strongly conductive. In the next half cycle (the negative half cycle) of the synchronizing (or clock) signal 50 on the line 40, the transistors 220, 220 and 222 become conductive. When the transistors 222 and 224 become conductive, they introduce the same voltages (the voltage from the voltage source 94) to the lines 226 and 228 to assure that any difference in the potentials on these lines in the previous half cycle of the synchronizing signal is eliminated. This insures that a considerable difference in potential will be produced in the lines 226 and 228 in the subsequent half cycle (the positive half cycle) of the synchronizing signals on the line 40. When the transistor 224 becomes conductive in the negative half cycle of the synchronizing signal 50 on the line 40, it provides a positive voltage to the source of the transistor 218 to insure that the transistor will become conductive in the subsequent half-cycle (the positive half cycle) of the clock signals. When a positive signal is produced one the line 158 to indicate a binary value of "0", the signal on the line 242 has a higher amplitude than the signal on the line 240 during the negative half cycle of the synchronizing signal 50 on the line 40. As a result, when the transistor 218 becomes conductive in the next half cycle (the positive half cycle) of the synchronizing signal 50, the transistors 206 and 210 become conductive and the voltage on the line 226 approaches the reference potential such as the ground 80. The circuitry shown in detail in Figure 7 and described above is duplicated in second stages which are included within a box generally indicated at 250 and shown in the broken lines in Figure 7. However, the stages 250 receive the synchronizing signals 52 on the clock line 46. Since these signals are displaced by 180° in phase from the synchronizing signals 50 on the line 46, the signals produced on output lines produced on the lines 226 and 228. The signals on the output lines 252 and 254 are respectively indicated as "DR x " and " DR x " in Figure 7. In other words, the signals produced in the lines 154 and 158 in one half cycle of the synchronizing signals 46 in Figure 1 in the stage 250 are sampled while the signals produced on the lines 154 and 158 in the previous half cycles of the synchronizing signals 46 are evaluated in the output lines 226 and 228. In the next half of the synchronizing signals 46, the signals sampled in the stage 250 are evaluated in the output lines 226 and 228 while the stage shown in detail in Figure 8 is sampling the signals on the lines 226 and 228. The circuitry shown in Figure 8 includes the lines 226 and 228 and the lines 252 and 254. The lines 226, 228, 252 and 254 are respectively connected to the gates of transistors 270 and 272, the gates of transistors 274 and 276, the gates of transistors 278 and 280 and the gates of transistors 282 and 284. The transistors 270 and 278 are n-transistors and the transistors 274, 276, , 280, 282 and 284 are p-transistors. Connections are also respectively made from the lines 226, 228, to the drain of the transistor 272 and the drain of the transistor 280 and 284. Similarly the lines 252 and 254 are respectively connected to the drains of the transistors 280 and 284. The sources of the transistors 272, 274, 276, 280, 282 and 284 receive a positive potential such as +5 volts from the voltage source 94. The drains of the transistors 274 and 282 are respectively common with the drains of the transistors 270 and 278. A resultant line 288 extends from a common connection between the drains of the transistors 270, 274, 278 and 282. A signal of low amplitude is produced on only one of the lines 226, 228, 252 and 254 at any time to represent binary coded information and signals of relatively high amplitude are simultaneously produced on the other ones of the output lines 226, 228, 252 and 254. By way of illustration, a signal of low amplitude may be produced on the line 226 and a signal of high amplitude may be simultaneously produced on the lines 228, 252 and 254. When the amplitude of the signal on the line 226 is low, it introduces a low voltage to the source of the transistor 278. At the same time, a signal of high voltage is introduced to the gate of the transistor 278 from the line 252. This causes the transistor 278 to become conductive so that the voltage on the drain of the transistor approximates the voltage on the source of the transistor and a signal of low amplitude is produced on the resultant line 288. The low voltage on the drain of the transistor 278 also appears on the drains of the transistors 274 and 282 and the drain of the transistor 270 and prevents these transistors from becoming conductive. To insure the operation of the transistors 270, 274, 278 and 282 as discussed above, the signals on the lines 226 and 228 are respectively introduced to the transistors 272 and 276. These signals prevent the transistor 272 from becoming conductive and cause the transistor 276 to become conductive. This causes a high voltage to be produced on the drain of the transistor 276 and to be introduced to the gate of the transistor 274 to prevent the transistor 274 from becoming conductive. It may sometimes happen that a signal of low amplitude is produced on the line 228. At the same time, signals of high amplitude are produced on the lines 226, 252 and 254. The signal of low amplitude on the line 228 is introduced to the gate of the transistor 274 to make the transistor conductive. This causes the drain of the transistor 274 to have a high voltage, this voltage being introduced to the resultant line 288. At the same time, the transistors 270 and 278 are not conductive. The reason is that each of these transistors has the same voltage on its gate and its source because of the high voltages on the lines 226 and 252. The transistor 282 is not conductive because a high voltage is introduced to its gate from the line 254. The transistors 272 and 276 operate to insure that the transistors 270, 274, 278 and 282 will operate as discussed in the previous paragraphs when the line 228 has a signal of low amplitude and the lines 226, 252 and 254 have signals of high amplitude. These signals prevent the transistor 276 from become conductive and cause the transistor 272 to become conductive. The resultant high voltage on the drain of the transistor 272 insures that the transistor 270 will remain non-conductive. As will be seen, the circuit shown in Figure 8 is symmetrical in that the lines 226 and 252 have the same connections and the lines 228 and 254 have the same connections. As a result, the discussion above with respect to the introduction of a signal of low amplitude on the line 226 is applicable to the introduction of a signal of low amplitude on the line 252. Similarly, the discussion above with respect to the introduction of a signal on the line 228 is also applicable to the introduction of a signal on the line 254. The invention described above has certain important advantages. It provides for the reading of binary coded information from the memory 10 by the fast port 18 at the same time that binary coded information is read from, or written into, the memory 10 by the slow port 12. The simultaneous transducing action is obtained by the fast port 18 and the slow port 12 without obtaining any interference between the actions of the fast and slow ports. This results from the operation of the circuitry shown in Figure 4 and described above. Actually, both the fast port 18 and the slow port 12 may simultaneously read the same bit of information from the memory. The invention described above also has other important advantages. It provides for the reading of binary coded information by the fast port 18 on a synchronous basis with signals from the clock signal generator 30 but provides for the reading or writing of binary coded information by the slow port 12 on an asynchronous basis relative to the clock signals. This synchronous-asynchronous relationship between the operation of the fast port 18 and the slow port 12 is especially significant because the reading of binary coded information from the fast port 18 occurs at a high frequency such as approximately one hundred and twenty five megahertz (125 mhz). The operation of the fast port 18 also offers other important advantages in addition to those specified above. For example, the fast port 18 reads binary coded information from the random access memory 10 in each half cycle of the synchronizing signals 50 and 52 shown in Figure 3. The fast port 18 samples, in a first stage, first bits of such binary coded information in the negative half cycles of the synchronizing signals 50 and evaluates the sampled information in the positive half cycles of the such synchronizing signals. The fast port 18 samples, in a second stage identical in construction to the first stage, second bits of such binary coded information in the positive half cycles of the signals 52 and evaluates such sampled information in the negative half cycles of such synchronizing signals. In this way, the frequency of the fast port 18 in reading binary coded information from the memory 10 is effectively doubled without any loss in the ability to read such information. The stages (Figure 7) sampling and evaluating the binary coded information read by the fast port 18 from the memory 10 also operate advantageously in prolonging the evaluation of the sampled signals in the next half cycles after each such sampling. The circuitry shown in Figure 8 then introduces such evaluated signals to the resultant line 288 on an exclusive basis whereby the signal, from only one of the output lines 226, 228, 252, and 254 can be introduced to the resultant line at each instant.

Claims: Circuit for reading and writing binary coded information comprising; first signal means (12) for passing first signals having first and second logic levels respectively corresponding to binary "1" and "0"; second signal means (18) for passing second signals having first and second logic levels respectively corresponding to binary "1" and "0"; memory means (10) having a plurality of positions for storing binary coded information; first means (60,66,72,78,92,75,88) operatively coupled to the first signal means and the memory means (10) for writing binary coded information in a particular position (76,90) in the memory means (10), the information being dependent upon the logic level of the first signals from the first signal means (12), and for reading binary coded information from the particular position (76,90) in the memory means and transferring such information to the first signal means (12) as the first signals; and second means (62,64,84,98,68) operatively coupled to the memory means and the second signal means (18) for reading binary coded information from the particular position in the memory means and transferring such binary coded information to the second signal means as the second signals, said memory means comprising, at each particular position, latching means operatively coupled to the first means for operatively providing voltages to and receiving voltages from the first means in accordance with the selective one of the reading or writing operations at the particular position; and characterised in that said memory means further comprises, at each particular position; transistor means (82,96) having a first, a second and a control terminal, the first terminal being operatively coupled to the second means and the control terminal being operatively coupled to a storage node of the latching means (76,90) for isolating any disturbances resulting from the reading through the second means of the binary coded information from the particular position (76,90) in the memory means (10) such that, in a time coincidence with the writing of binary coded information through the first means to the particular position in the memory means, any such disturbances resulting from the reading through the second means of the binary coded information from the particular position in the memory means will be prevented from affecting such writing through the first means to the particular position in the memory means. Circuit according to claim 1 characterized by the transistor means (82,96) including high input impedance isolation means having an input coupled to the first means (60,66,72,78,92,75,88) and an output coupled to the second means (62,64,84,98,68). Circuit according to claim 2 characterized by the transistor means (82,96) including semiconductor means having non-conductive and conductive states and being operative in the conductive state dependent upon the signals through the first means. Circuit according to at least one of the preceding claims characterized by further comprising means for producing clock signals (30,34,38,36,42,40,46) and in that the second means (62,64,84,98,68) reads the binary coded information from the particular position (76,90) in the memory means (10) on a synchronous basis with the clock signals, and the first means (60,66,72,78,92,75,88) reads the binary coded information from, or writes binary coded information to, the particular position (76,90) in the memory means (10) on asynchronous basis relative to the clock signals. Circuit according to at least one of the preceding claims characterized by the memory means (10) being a random access memory. Circuit according to at least one of the preceding claims characterized by the circuit further comprising means for enabling a selective one of the reading through the first means of information from, and the writing through the first means of information to, the selected position (76,90) in the memory means, and means for enabling the reading of information through the second means from the selected position (76,90) in the memory means (10). Circuit according to at least one of the preceding claims characterized by the transistor means (82,96) including amplifier means having a high input impedance and having an input and an output, the input of the amplifier means being operatively coupled to the first means (60,66,72,78,92) and the output of the amplifier means being operatively coupled to the second means (62,64,84,98,68). Circuit according to at least one of the preceding claims characterized by the second means (62,64,84,98,68) including a third means (200,226,214,204,216,202,218,208,242,210,206) for sampling binary coded information read from the particular position in the memory means in alternate cycles of the clock signals and for evaluating such sampled binary coded information in other cycles of the clock signals and comprising a fourth means (250) for sampling binary coded information read from the particular position in the memory means in the other cycles of the clock signals and for evaluating such sampled binary coded information in the alternate cycles of the clock signals. Circuit according to at least one of the claims 4-8 characterized by means (34,36,38,44,42) for dividing the frequency of the clock signals by two to obtain clock signals at a reduced frequency. Circuit according to claim 8 or 9 characterized by the circuit further comprises a fifth means (124,126) for providing for a common mode rejection of noise in the binary coded information passing through the second means (62,64,84,98,68) and sixth means (128,136,130,138) for providing a low amplification of such binary coded information after the common mode rejection by the fifth means of noise in the binary coded information passing through the second means. Circuit according to claim 11 characterized by the second signal means (18) having first and second differentially connected lines (62,64) for passing the second signals, the fifth means comprising commond mode rejection means (124,126) respectively connected to the first and second differentially connected lines (62,64) to pass only the differential signals on the lines, and the sigh means comprising cascode amplifier means (128,150) respectively connected to the first and second differentially connected lines and having first and second output lines (132,134) for respectively isolating the binary coded information on the first and second output lines from the binary coded information on the first and second differentially connected lines. Circuit according to claim 11 characterized by the common mode rejection means including first and second transistors (128,130) each respectively having a source, a drain and a gate, the sources of the first and second transistors being respectively connected to the first and second differentially connected lines (62,64), the gates of the first and second transistors receiving a substantially constant biasing voltage for producing a flow of a substantially constant current through the first and second transistors and the drains of the first and second transistors being connected to a reference potential (80). Circuit according to claims 9, 10, 11 or 12 characterized by the circuit further comprising a third output line (228,226), means responsive to the binary coded information sampled and evaluated by the fifth means for producing on the third output line signals having a binary value representating such evaluated binary coded information, a fourth output line (254,252) means responsive to the binary coded information sampled and evaluated by the fourth means (250) for producing on the fourth output line signals having a binary value representing such evaluated binary coded information, a resultant line (288), and means (270,274,278,282) for introducing on an exclusive basis to the resultant line signals having a binary value corresponding to the signals produced on either the third or fourth output lines so that only one of such signals is produced on the resultant line at any one time. Circuit according to at least one of the preceding claims characterized in that said latching means comprises a flip-flop circuit. Circuit according to at least one of the preceding claims characterized in that said first means comprises seventh (60,72,75,78) and eighth (66,88,72,92) means, said second means comprises ninth (62,68,84) and tenth (64,68,98) means, a source of a reference potential (80), said flip-flop means (76,90,78,92) being operatively coupled to the seventh and eighth means for selectively providing voltages to, and receiving voltages from, the seventh and eighth means in accordance with the selective one of the reading and writing of binary-coded information from or to the particular position in the memory means, said transistor means comprising first and second transistors (82,96) each having a source, a drain and a gate, the sources of the first and second transistors being respectively connected to the ninth (84,68,62) and tenth means (64,98,68) and the gates of the first (82) and second (96) transistors being respectively coupled to the storage nodes of the flip-flop means (76,90,78,92) and the drains of the first and second transistors being connected to the source of the reference potential (80). Circuit according to claim 15, characterized by the first (82) and second (96) transistors having high gate impedances to isolate any such distrubances resulting from the reading of binary coded information through the ninth and tenth means from the particular position in the memory means (10). Circuit according to claim 15 or 16 characterized by means (34,30,44,42,38,36,40,46) for providing clock signals, means for synchronizing the operation of the ninth and tenth means with the clock signals, the operation of the seventh (60,72,75,78) and eighth (66,88,72,92) means and the flip-flop means (76,90,78,92) being asynchronous with respect to the clock signals. Circuit according to at least one of the claims 15-17 characterized by the first (82) and second (96) transistors being n-type transistors. Circuit according to claim 18, characterized by the ninth (62,68,84) and tenth (64,68,98) means including a pair of n-type transistors (84,98), the seventh (60,72,75,78) and eighth means (66,88,72,92) including a pair of n-type transistors, (75,88), and the flip-flop means (76,90,78,92) being defined by first (76,78) and second (90,92) pairs of transistors, the transistors in the first pair being cross coupled to the transistors in the second pair, one of the transistors (78;92) in each of the first and second pairs being n-type and the other of the transistors (76;90) in each of the first and second pairs being p-type. Circuit according to claim 19, characterized by each of the n-type transistors in the ninth and tenth means including a gate, a source and a drain, and means for introducing, (68) to the gates of the transistors in the ninth and tenth means, binary coded information representing the information of the particular position, means for introducing, (62,64) to the sources of the transistors in the ninth and tenth means, binary coded information representing the information of the particular position, the drains of the transistors (84,98) in the ninth and tenth means being respectively connected to the source of the first (82) and second (96) transistors. Circuit according to claim 19 or 20 characterized by each of the n-type transistors (75,88) in the seventh and eighth means including a gate, a source and a drain, means (72) for introducing, to the gates of the transistors in the seventh and eighth means, binary coded information representing the information of the particular position, means (60,66) for introducing, to the sources of the transistors in the seventh and eighth means, binary coded information, the drains of the transistors in the seventh and eighth means being connected to the flip-flop means (76,78,90,92) to control the operation of the flip-flop means in the first and second states.

Inventors: BRUNOLLI, MICHAEL J.
Applicants: BROOKTREE CORPORATION
Application year: 1986
Main classification: G11C7
IPC codes: G11C7, G11C11, G11C8