SEMICONDUCTOR MEMORY

Abstract: A semiconductor memory for writing or reading data words in response to prescribed bank address data and bit address data, each word having a prescribed amount of bits. The memory includes memory array (24) for storing the data words. The memory array (24) includes at least two memory banks (11, 12) adjacent to one another, each bank (11, 12) having a bit area corresponding to the prescribed amount of bits, buffer memory (25) for temporarily storing the data word for writing into the memory array (24) or the data word read from the memory array (24), first source (14, P, G) for applying the bank address data to the memory array (24) to access the memory banks (11, 12), second source (16) for applying the bit address data to the memory banks (11, 12) to access prescribed bit locations of the memory banks (11, 12), and logic circuit means (26, 27, 28) responsive to the bit address data for cyclically shifting the data word stored in the buffer memory (25) by an amount corresponding to the value of the received bit address data.

Description: The present invention relates to a semiconductor memory and, more particularly, to a semiconductor frame buffer memory for temporarily storing image data in bit map control type image display systems of computer installations. A display device such as a CRT (cathode ray tube) display device is is indispensable component of a computer terminal. Recently such disply devices have been improved to achieve higher resolution for use in a bit map control system. This type system allows display control of picture element units, and is commonly used in the display of graphics, as well as characters. Fig. 7 shows a computer system that uses a CRT display device 71 of the bit map control type. The computer system basically includes a processor 73, a main memory 74, a frame buffer 72 and the CRT display device 71. The frame buffer 72 is coupled to the processor 73 through a data bus 75 and to the CRT display device 71. The buffer 72 temporarily stores image data to be displayed. As the resolution power of the CRT display device 71 has been improved, and the amount of information per image has increased, a multi-bit memory has been used as the frame buffer 72. In such a multi-bit memory, one word consists of 4 bits or 8 bits, etc., rather than 1 bit. It is likely that such multi-bit memories will become more common in the future. As the bit map control type CRT display device 71 has become more common, a need has developed for an image processing apparatus that permits image rotation, enlargement, reduction, etc. on the CRT display device 71. Generally, these image processing operations must start from an arbitrary bit position on the CRT display device 71. Data in the frame buffer 72 are connected to prescribed bus lines normally in byte units (8 bits) or word units (16 bits). Thus, the system must have the capability (referred as bit boundary access function) to read or write byte data or word data starting from any bit position regardless of the location of byte or word boundaries in the frame buffer 72. More particularly, what is needed is the ability to access frame buffer 72 for reading or writing data starting from any bit position on the screen, as illustrated in Fig. 8 when various data items of single-word units of image data stored in the frame buffer are arranged in correspondence to display positions on a non-interlaced type screen. Conventionally, an apparatus for performing the bit boundary access function included a circuit employing a large number of logic elements outside the memory, i.e., the frame buffer 72. This has led problems due to the increased number of required circuits and associated higher costs. Accordingly, an object of the present invention is to provide a semiconductor memory having a bit boundary access function which is simple to construct and has a relatively low cost. We acknowledge that EP-A-0099620 discloses a system, as defined in the preamble portion of claim 1 below, comprising a CPU and a read/write memory with interconnection means which provides for data rotation allowing each data word to be written into or read from two adjacent storage locations. It is also known from US-A-3440615 to provide in a data processor a system for addressing a pair of storage units with even addresses and odd addresses respectively; the storage word relating to a given address is accessed, with the next higher storage word (in the other storage unit) automatically being accessed at the same time. The present invention provides a memory as defined in claim 1, and thereby achieves the object identified above. An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings in which: Fig. 1 is a block diagram showing an embodiment of the semiconductor memory according to the present invention; Fig. 2 is a block diagram showing the buffer memory in Fig. 1; Fig. 3 and Fig. 4 are drawings for explaining two different modes of read operation in the frame buffer of Fig. 2; Fig. 5 and Fig. 6 are drawings for explaining two different modes of write operation in the frame buffer of Fig. 2; Fig. 7 is a block diagram showing a portion of a computer system that has a bit map control type CRT display device as a terminal; and Fig. 8 is a drawing for explaining an image processing in relation to the frame buffer of Fig. 7. The present invention will now be described in detail with reference to the accompanying drawings, namely, Figs. 1 to 6. Throughout the drawings, like reference numerals and letters are used to designate like or equivalent elements for the sake of simplicity of explanation. Referring now to Fig. 1, an embodiment of the semiconductor memory according to the present invention will be described in detail. Fig. 1 shows a frame buffer for storing image data to be displayed on a CRT display device that employs the bit map control system. The buffer memory comprises an even address number memory bank (even number memory bank) 11 and an odd address number memory bank (odd number memory bank) 12. The least significant bit (LSB) A0 in address data consisting of (k + 1) number of bits A0, A1, ..., Ak is supplied to a first address bus 13 and the remaining k number of bits A1 through Ak in the address data are supplied to a second address bus 14. Assume that a data bus 15 has a capacity of transferring data of 8 bits. Bit address data BA for indicating the location of a specified bit in 8 bits data (1 word) is supplied to a bit address bus 16. The odd number memory bank 12 is supplied with address data consisting of an LSB, which is fixed at a "1" level, from a prescribed potential source P, and the remaining bits A1 through Ak from the second address bus 14, the bit address data BA from the bit address bus 16, and a bit boundary control data CTL in the form of the LSB A0 from the first address bus 13. The even number memory bank 11 is supplied with address data consisting of the LSB, which is fixed at a "1" level, from a ground potential source G, and the remaining bits from adder 17 in the form of the sum of address data A1 through Ak from the second address bus 14 and the LSB A0 from the first address bus 13. In addition, memory bank 11 receives the bit address data BA from the bit address bus 16, and the bit boundary control data CTL. The data CTL comprises the LSB A0 from the first address bus 13 inverted by an inverter 18. In this embodiment, the adder 17 and the inverter 18 are formed on one chip separate from another chip on which the even and the odd number memory banks 11, 12 are constructed. The even and the odd number memory banks 11, 12 are typically included an SRAM (static random access memory). Such an SRAM can selectively perform the write operation or the read operation of a word constituted by a plurality of bits in response to receipt of a single address data. A read/write signal R/W is supplied to both the even and odd number memory banks 11 and 12 through a read/write signal bus 19 for changing the modes banks 11 and 12 between the read operation mode or the write operation mode. Referring now to Fig. 2, the drawing shows the detail of the even or the odd number memory bank 11, 12 using the SRAM 20. In Fig. 2, the SRAM 20 comprises an internal address bus 21, an address buffer 22, an address decoder 23 and a memory cell array 24. The memory cell array 24 of the SRAM is connected to the data bus 15 through a cyclic shift and control circuit 26 and an input/output buffer 25. The cyclic shift and control circuit 26 is connected to a bit boundary control circuit 28. The input/output buffer 25 is connected to the bit boundary control circuit 28 through an output control circuit 27. The bit boundary control circuit 28 produces various control signals for controlling the cyclic shift and control circuit 26 and the input/output buffer 25 in response to the bit address data BA and the bit boundary control data CTL. Also the read/write signal R/W is applied to the output control circuit 27 from the read/write signal bus 19. The output control circuit 27 controls the output state of the input/output buffer 25. Each of the memory banks 11, 12 performs following operations: (1) cyclically shifts data read out from the SRAM 20 (referred as read-out data hereafter) leftwards or shift data to be written in the the SRAM 20 (referred as write-in data hereafter) rightward by a prescribed amount determined by the bit address data BA in response to the bit boundary control data CTL, and (2) keeps the read-out data in the high impedance state or writes the write-in data by prescribed bits in response to the bit address data BA and the bit boundary control data CTL. The operations of the memory banks 11, 12 will now be described in detail with reference to Figs. 3 through 6. (A) Read-out Operation (A)-1 : Assume that, as illustrated in Fig. 3, it is necessary to access data starting from a bit position specified by the bit address data BA in the 8 bits of data of the specified address in the even number memory bank 11, and to read-out data A (e.g., consisting of 3 bits) starting from this specified bit position in the even number memory bank 11 and data B (e.g., consisting of 5 bits) in the succeeding odd number memory bank 12. The LSB A0 of the address data on the address bus 13 is made "0" and the same remaining address bits A1 through Ak are applied to both the memory banks 11 and 12. As a result, the cyclic shift and control circuit 26 causes the byte data read out from the respective memory cell arrays 24 in the memory banks 11 and 12 to be shifted cyclically leftward by the number of bits specified by the bit address input BA. Next, the bit boundary control data CTL controls the input/output buffer 25 for causing a high impedance state for set bits of the output data bits, and a normal output state for the remaining bits. The control effected here is such that the various bit positions in the input/output buffer 25 go to the high impedance state Z or the normal output state X in the manner shown in Table 1 in response to the value of the bit address data BA and the logic level of the bit boundary control data CTL. Referring to the Table 1, if, for example, the value of the bit address data BA is "5" and the LSB A0 of the address data is "0", as the bit boundary control data CTL inputted to the even number memory bank 11 is level "1", the first through third bit positions in the input/output buffer 25 are in a normal output state X, and the data A which his been cyclically shifted by 5 bits leftward is outputted to the data bus 15 but the remaining fourth through eighth bit positions are in the high impedance state Z. For the odd number memory bank 12, the bit boundary control data CTL input is at level "0" and the first through third bit positions in the input/output buffer 25 are in the high impedance state Z. The fourth through eighth bit positions are in the normal output state X, and so data B, that has been cyclically shifted by 5 bits to the left, is outputted to the data bus 15. In this manner, therefore, required byte data consisting of the data A and B is read out onto the data bus 15. (A)-2 : In contrast to the case (A)-1, assume, as illustrated in Fig. 4, it is necessary to access data starting from a bit position specified by the bit address data BA in the 8 bits of data of the specified address in the odd number memory bank 12 and to read-out data A (e.g., consisting of 3 bits) and data B (e.g., consisting of 5 bits). In the even number memory bank 11, the LSB A0 of the address data on the address bus 13 is changed to "1", so the value of the remaining address bits A0 to Ak inputted to the even number memory bank 11 is greater by "1" than the value of the remaining address bits A1 through Ak inputted to the odd number memory bank 12. This is because the remaining bits were incremented by the value "1" of the LSB A0 of the address data. The bit shift operations in the memory banks 11 and 12 are the same as described above when the LSB A0 of the address data is "0". However, for the odd number memory bank 12, the bit boundary control data CTL inputted therein is now "1". If, for example, the value of the bit address data BA inputted therein is "5", data A in the first through third bit positions of the input/output buffer 25 is outputted, while for the even number memory bank 11 data B from the fourth through eighth bit positions in the input/output buffer 25 is outputted. This is because the bit boundary control data CTL inputted to the even number memory bank 11 is "1". The result, therefore, is that required byte data consisting of data A and B is outputted onto the data bus 15. (B) Write-in Operation (B)-1 : Assume it is necessary to receive byte data that is on the data bus 15 (it being supposed for convenience of description that this byte data comprises a data A consisting of 3 bits and a data B consisting of 5 bits) and, as illustrated in Fig. 5, to access a particular address in the even number memory bank 11 specified by the bit address data BA, and write-in the byte data such that the data A is written into the even number memory bank 11 starting from this specified bit address and the data B is written in the succeeding odd number memory bank 12. The LSB A0 of the address data on the address bit 13 is changed to "Q", so resulting in the same address bits A1 through Ak being inputted to both the memory banks 11 and 12. Consequently, in both the memory banks 11 and 12 the data taken from the data bus 15 is cyclically shifted rightward by the number of bits specified by the bit address data BA. Next, the bit boundary control data CTL causes only set bits of the shifted byte data to be written into the memory cell array 24 and prevents the remaining bits from being written. In this case, the control is such that the various bits of the shifted byte data are subjected to a write-in control X and a non-write-in control N as shown in Table 2 in response to the value of the bit address data BA and the logic level of the bit boundary control data CTL. It is seen from the Table 2 that if, for example, the bit address data BA has the value "5" and the LSB A0 of the address data is "0", the data of the first through fifth data postions of the cyclic shift and control circuit 26 is not written in, but the data A which is in the sixth through eighth positions as the result of a 5-bit cyclic shift rightwards is written into the memory cell array 24. This is because the bit boundary control data CTL inputted therein is at level "1". In the case of the odd number memory bank 12, since the bit boundary control data CTL inputted therein is at level "0", the data B which has been cyclically shifted rightward to the first fifth through positions of the cyclic shift and control circuit 26 is written into the memory cell array 24, but the remaining data in the sixth through eighth positions is not. Thus, the result is write-in of required byte data consisting of the data A and B starting from a set bit position in the even number memory bank 11 and extending into the odd number memory bank 12. (B)-2 : In contrast to the case (B)-1, assume, as illustrated in Fig. 6, it is necessary to access data starting from a bit position specified by the bit address data BA in the 8 bits of data of the specified address in the odd number memory bank 12 and, starting from this specified bit position, to effect write-in of data A in the odd number memory bank 12 and of data B in the succeeding even number memory bank 11. The LSB A0 of the address data on the address bus 13 is changed to "1", so the value of the remaining address bits A1 through Ak inputted to the even number memory bank 11 is greater by "1" than the value of the remaining address bits A1 through Ak inputted to the odd number memory bank 12. This is because the even number bank 11 is incremented by the value "1" of the LSB A0 of the address data. The bit shift operations in the memory banks 11 and 12 are the same as described above when the LSB A0 of the address data is "0". However, for the odd number memory bank 12, since the bit boundary control data CTL inputted therein is now "1", if, for example, the value of the bit address data BA inputted therein is "5", the data A which has been shifted to sixth through eighth bit positions of the cyclic shift and control circuit 26 is written in. For the even number memory bank 11, the data B which has been shifted to first through fifth bit positions in the cyclic shift and control circuit 26 also is written in. The result, therefore is write-in of required byte data consisting of the data A and B starting from a set bit position in the odd number memory bank 12 and going over into the even number memory bank 11. Since the semiconductor memory of the above embodiment has bit address 16 and the main portions of a bit boundary access function, the memory can be employed directly, as it is, for the odd number memory bank 12. If the memory is used for the even number memory bank 11, a memory system possessing a bit boundary access function can easily be achieved simply by external provision and connection of the adder 17 for adding the value of the LSB A0 of the address data to the value of the remaining address bits A1 through Ak from the address bus 14, and adding the inverter 18 for inverting the LSB A0 of the address data from the address bus 13 and supplying the inverted result to the even number memory bank 11 as the bit boundary control data CTL. It is possible to produce a semiconductor memory with a bit boundary access function without using connection of external circuits, although there are the problems of increased chip size and adder and inverter circuit redundancy on the odd number memory bank 12 if the adder 17 and the inverter 18 are formed on the memory chip. Although the above embodiment was described with reference to a semiconductor memory with a one word equals 8 bits structure, the invention is, of course, also applicable to semiconductor memories with any other bit structure. Further, although the embodiment was described with reference to a read/write semiconductor memory that can perform both the read and the write operations, the invention may be applied to a read-only semiconductor memory, in which case the read-out system is only provided with a bit boundary function. As described above, since the semiconductor memory of the present invention possesses a bit boundary access function, if it is used as, for example, a frame buffer for temporarily storing display data for a bit map control type display device, an image processing unit that can carry out processing for image rotation, enlargement and reduction, etc. on a display device may to be produced at relatively low cost.

Claims: A semiconductor memory for writing or reading data words in response to prescribed bank address data (A₀, A₁,...,A k ) and sub-location address data (BA), each data word having a prescribed number of sub-locations of equal size, the memory comprising: memory array means (24) for storing the data words, and means (26-28) responsive to the sub-location address data (BA) for controlling the operation of the memory array means (24) so as to store and rotate each data word by shifting its sub-locations a corresponding amount, so that it may be read from or written into two adjacent data word addresses, characterized in that: the memory array means (24) includes two memory banks (11, 12), each address in each bank (11, 12) having a bit area corresponding to the prescribed number of sub-locations, which are single bits, parts (A, B) of a data word may be located in different banks; and characterized further by: buffer memory means (25) having a bit length being twice the prescribed number of sub-locations, for temporarily storing a said data word for writing into the memory array means (24) or temporarily storing a said data word read from the memory array means (24); first source means (14) for applying the bank address data to the memory array means (24) to access the memory banks (11, 12); second source means (16) for applying the bit address data to the memory banks (11, 12) to access prescribed bit locations of the memory banks (11, 12); and logic circuit means (26, 27, 28) responsive to the bit address data for cyclically shifting the data parts of the word stored in the buffer memory means (25) by an amount corresponding to the value of the received bit address data, the logic circuit means (26, 27, 28) effecting control to establish special output states, and normal output states corresponding to the bits of the data word in response to the LSB (CTL) of the bank address data as well as to the values of said bit address data (BA), such that in each bit area relating to the corresponding bank in the buffer memory means (25) there is one group of adjacent bits set to the special output state (Z) and an adjacent group, comprising the remainder of the bits of that area of the buffer memory means, set to the normal output state (X), the boundary position between those bit groups (X, Z; Z, X) in each bit area being determined by the bit address data (BA), and the sequential order of the groups being determined by the LSB (CTL) of the bank address data and by the mode of transfer of the data words being reading or writing. A memory as claimed in claim 1, wherein the logic circuit means (26, 27, 28) includes an output control circuit (27) responsive to a read/write signal for changing the buffer memory means (25) between the read operation mode and the write operation mode and for determining the direction of the cyclic shifting. A memory as claimed in claim 2, characterised in that the logic circuit means (26, 27, 28) includes a control circuit (28) for said output control circuit (27) for read-out control to establish high impedance states (Z) as said special output states and to determine bit positions at which read-out is effected in response to the LSB (CTL) of the bank address data as well as to the values (BA) of the bank address data as well as to the values (BA) of said bit addresses. A memory as claimed in claim 2, characterised in that the logic circuit means (26, 27, 28) includes a control circuit (28) for said output control circuit (27) for write-in control to establish write-in states and to determine bit positions at which write-in is effected in response to the LSB (CTL) of the bank address data as well as to the values (BA) of said bit addresses.

Inventors: TANAKA, SHIGERU PATENT DIVISION TOSHIBA CORP.
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: G06F12
IPC codes: G06F12, G09G5, G06T3, G06T1