CHARGE TRANSFER DEVICE

Abstract: The invention relates to a charge-coupled device, in which the reset transistor of the output is clocked - with a positive threshold voltage - by a maximum voltage equal to the supply voltage V DD . The drain (14) of the reset transistor is adjusted by means of an auxiliary transistor (T₁) controlled by a current source (T₂) and having the same threshold voltage, whose gate (21) is applied to V DD and whose source (22) is connected to the drain (14) of the reset transistor. Due to the fact that the maximum gate voltage is equal to V DD , additional voltage sources, such as charge pumps, for generating voltages higher than V DD are superfluous.

Description: The invention relates to a charge transfer device com­ prising a semiconductor body, at a surface of which is defined a charge transport channel for storing and transporting information in the form of discrete charge packets to an output stage, which has a zone for temporarily storing and reading the charge packets and an insulated gate field effect transistor which forms a reset transistor for draining a read charge packet and preparing the said zone for storing and reading a next charge packet, this tran­ sistor comprising a source region coupled to the said zone, an in­ sulated gate connected to a clock voltage source for rendering the transistor intermittently conducting and non-conducting, and a drain region connected to means for applying a suitable drain voltage. Such a device is known inter alia from "Charge Transfer Devices" of C.H. Sequin and M.F. Tompsett, Academic Press Inc., 1975, Fi.g 3.14b, p. 53 and the associated description. The in­ vention will be explained in the following description with refer­ ence to an n -channel surface device, but it will be appreciated that the invention may also be used for p -channel devices and for devices of the buried channel type. As usual such a charge transfer device comprises a p - type silicon substrate, which is provided at the surface with a clock electrode system, which is separated from the semiconductor material by a thin insulating layer. When suitable clock voltages are applied to the clock electrodes, as is known, charge packets consisting of electrons can be passed through the charge trans­ port channel to the reading zone. This zone is constituted by an n⁺ surface zone, which is provided by diffusion or implantation in the semiconductor body at the end of the row of clock electrodes. When a charge packet is stored in the zone, this leads to a volt­ age variation which can be detected by means of an amplifier also integrated in the semiconductor body. Thus, each charge packet can be read out in a non-destructive manner. The reset transistor serves to apply the n⁺ zone to a suitable positive potential before a new charge packet is supplied. This potential should be suffi­ ciently positive so that the maximum charge packet can be stored entirely in the n⁺ zone. For this purpose, it is usual to apply the drain of the reset transistor to the highest voltage available, i.e. the supply voltage V DD , which generally amounts to +5 V. If, as usual, the reset transistor is of the enhancement type, i.e. of a type in which a positive voltage of more than O V is required at the gate electrode to render the transistor conducting, a gate voltage of more than 5 V is required to reset the said n⁺ reading zone, which constitutes the source of the reset transistor, to the supply voltage of 5 V. A specific value for the gate voltage is 8 V. Since the supply voltage is only 5 V, separate circuits, for example a charge pump, are required for this high gate voltage. If it should be possible to use a reset transistor of the depletion type, i.e. a transistor which is conducting already with 0 V at the gate electrode, the reset transistor could be operated with a clock voltage equal to the supply voltage. However, it has been found that these transistors often do not provide a sufficient insulation between the source and drain regions, even if a negative voltage is applied to the gate electrode. This may be explained as follows: In order to render the transistor non-­ conducting, a negative voltage has to be applied to the gate electrode which is so large that all electrons are removed from the implanted n -type channel between source and drain. However, it is possible that, before the n -type channel regions has com­ pletely been depleted, accumulation of holes occurs at the sur­ face. If the voltage at the gate electrode is further reduced, this will no longer influence the non-depleted part of the implanted channel, as a result of which a leakage path remains between source and drain. Since with a very small leakage current of 1 nA already a loss of charge of 10% may occur, the use of field effect transistors of the depletion type as a reset transistor is practic­ ally excluded. The invention has inter alia for its object, whilst using a field effect transistor of the enhancement type, to avoid high gate voltages. The invention is based inter alia on the re­ cognition of the fact that the gate electrode of the reset tran­ sistor can be clocked with a voltage equal to the supply voltage by reducing the potential at the drain of the reset transistor to a value lower than the supply voltage. A charge transfer device according to the invention is characterized in that the said means comprise a second insulated gate field effect transistor, which is designated hereinafter as auxiliary transistor, whose gate and drain can be applied to a fixed voltage V₁, more particularly the supply voltage, and whose source is connected to the drain region of the reset transistor and to current supply means for passing a current through the auxiliary transistor, and in that the gate of the reset transistor is connected to a clock voltage source, by means of which in the conductive state of the reset transistor the voltage V₁ is also applied to the gate of the reset transistor. The voltage of the source of the auxiliary field effect transistor provides for the reduced reset voltage which is applied to the drain of the reset transistor. Since the auxiliary tran­ sistor is conducting with a gate voltage equal to the supply voltage, the reset transistor will also be conducting with a gate voltage equal to the supply voltage. Preferably, the channel regions of the reset transistor and the auxiliary transistor have at least practically the same dimensions in order to obtain at least practically equal threshold voltages. In charge transfer devices of the type described herein, there is generally arranged between the output stages and the clock electrodes a blocking gate, which during operation is applied to a fixed voltage and serves to avoid cross-talk of the clock voltages to the reading zone. The voltage applied to this zone should be such that below this electrode is induced a potential barrier which on the one hand is sufficiently low to transfer charge from below the last clock electrode to the reading zone and on the other hand is so high that a maximum charge packet can be entirely stored in the reading zone and is not partially stored below the blocking gate. A preferred embodiment, in which a potential barrier of suitable height is obtained below the block­ ing gate also at the reduced voltage at the drain (and hence source), is characterized in that there is arranged above the charge trans­ port channel, viewed in the charge transport direction, in front of the said zone of the output stage an insulated gate, which is connected to the source of the auxiliary field effect transistor. The invention will now be described more fully with reference to a few embodiments, by way of example, and the ac­ companying diagrammatic drawing, in which: Fig. 1 shows diagrammatically a part of a charge coupled device in accordance with the invention comprising the output stage, Fig. 2 shows a potential distribution in the device shown in Fig. 1 induced in the channel during operation, Fig. 3 shows diagrammatically a second embodiment of a charge coupled device in accordance with the invention, Fig. 4 shows a diagram of the clock voltages applied to the device shown in Fig. 3. Fig. 1 shows diagrammatically a part of a charge trans­ fer device in accordance with the invention, i.e. the part com­ prising the output stage and the last two clock electrodes in front of the output stage. The device is provided in a p -type silicon body 1 having the usual thickness and composition, in which a charge transport channel 5 is defined. The body 1 is pro­ vided at the surface 2 with an electrode system which is insulated from the surface 2 by an insulating layer (not shown) of, for example, silicon oxide and/or silicon nitride. Of the electrode system the last two clock electrodes 3 and 4 are shown, which comprise a storage part 3a and 4a, respectively, and a transfer part 3b and 4b, respectively. The transfer parts 3b, 4b, which are provided on a slightly thicker oxide layer than the storage parts 3a, 4a, serve to induce a potential barrier in the semicon­ ductor body and thus to operate the device, as is known, as a two-­ phase surface CCD. The electrode 3 is controlled by a clock volt­ age ⊘₂, while the electrode 4 is controlled by a clock voltage ⊘₁. Of course, the invention is not limited to this case, but may also be used in three- or four- or multiphase CCD's, BBD's or in CCD's of the buried channel type. Moreover, it will be clear that besides the clock electrodes 3 and 4, the device may comprise a large number of further clock electrodes, which are arranged in a row in front of the electrodes 3 and 4. There is situated behind the last clock electrode the output stage having an n⁺ zone 7, in which the transported charge (electron packets) can be temporarily stored in order to be read out. For this purpose, the n⁺ zone is connected via the connection 8 shown diagrammatically to an output amplifier 9, which is con­ stituted in the present embodiment, by way of example, by a source follower comprising a field effect transistor 10. The gate of this transistor is connected via the conductor 8 to the n⁺ zone 7. The drain of the transistor 10 is connected to the supply voltage V DD . The source is connected via the resistor 11 to earth. Through the output terminal 12, the amplified output signal can be derived at the source of the transistor 10. In order to reset the n⁺ zone 7 each time to a reference level, the output stage is provided with a reset transistor having an insulated gate 13, a drain in the form of an n⁺ zone 14 and a source constituted by the zone 7. The gate electrode 13 is driven by a clock voltage ⊘ r . There is arranged between the zone 7 and the last clock electrode 4 an additional gate 16, also designated as output gate (OG), which is applied to a fixed potential. This output gate serves to prevent cross-talk of the clock voltages applied to the clock electrodes 3, 4 to the zone 7. The construction of the out­ put gate 16 is identical to that of the clock electrodes 3, 4, a part 16a being provided on thinner oxide and a part 16b being pro­ vided on thicker oxide. The semiconductor body may further be provided, for example, on the back side with a connection 17 for applying a suitable substrate voltage V SB . In contrast with what is usual, i.e. connecting the drain 14 of the reset transistor to the highest voltage, i.e. the supply voltage V DD , a lower voltage is applied to the drain. As a result, the gate 13 can be controlled by a voltage equal to the supply voltage, while circuits, which are otherwise necessary to generate voltage higher than the supply voltage, can be avoided. The reset voltage V R is generated by the cirucit 18, which mainly comprises only a series-combination of two insulated gate field effect transistors T₁ and T₂. The transistor T₁ comprises a drain 20 and a gate 21, which are both applied to the positive supply voltage V DD , and a source 22, which is connected to the drain 14 of the reset transistor through the connection 23. The transistor T₁ is supposed to have the same or at least substantially the same threshold voltage as the reset transistor 7, 13, 14. Therefore, the length/width dimensions of the transistor T₁ are equal to the length/width dimensions of the reset transistor in order to avoid that due to so-called small channel effects the threshold voltages are different. When a current of the suitable value is passed through the transistor T₁, the source 22 of the transistor T₁ is adjusted to the desired reset voltage V R , which is lower than the supply voltage V DD . Due to the fact that moreover the threshold voltages of the transistor T₁ and the reset transistor are equal or at least substantially equal, the value of the reset voltage V R is always such that, when the reset transistor is controlled by a clock voltage equal to the supply voltage V DD , the reset tran­ sistor is conducting so that the source 7 of the reset transistor can be reset accurately to the voltage V R . For adjusting the current, T₁ is connected to a second transistor T₂, whose drain 24 is connected to the source 22 of T₁, whose gate 25 is connected to the source 22 of T₁ and whose source 26 is connected to the negative supply or earth. During operation, a substrate voltage V SB of, for example, -2.5 V is applied to the p -type substrate 1. Clock volt­ ages ⊘₁, ⊘₂ having a high level of, for example, 5 V equal to the supply voltage V DD and a low level of 0 V are applied to the clock electrodes 3, 4 and to the gate 13 of the reset transistor. The potential at the node 27 between T₁ and T₂ and hence the potential at the zone 14 and the blocking gate 16 can be adjusted in a simple manner by suitably proportioning the transistors T₁ and T₂, as will be explained more fully hereinafter. The current-voltage relation of a MOS transistor can be described on approximation by the equation: I D = (V GS - V T )² (1), in which β = µ n .C ox = product of the mobility of the charge carriers and the oxide capacitance, W/L is the width-to-length ratio of the channel, V GS is the voltage difference between gate and source and V T is the threshold voltage of the transistor (see, for example: Szé "Physics of Semiconductor devices", second Ed., Wiley and Sons, New York, 1981, more particularly page 442). Specific values in usual MOS processes are: of the threshold voltage V T 1 V, and for about 20 . When the W/L ratio for the transistor T₁ is chosen = 1, the equation (1) can be re-­ written for T₁ as I D = 20(V GS -1)² = 20(5-1-V₂₇)² = 20(4-V₂₇)², in which V₂₇ is the voltage at the junction 27. When a W/L ratio of is chosen for the transistor T₂, it holds, starting from the equation (1), for the transistor T₂ that: I D = 20. (V₂₇-1)², it being assumed that T₁ and T₂ both have a threshold voltage of 1 V. Since an equally large current flows through both transistors, it follows that (V₂₇-1)² = (4-V₂₇)². A value of about 3,1 V follows therefrom for V₂₇. The current then flowing through T₁ and T₂ is about 20 µA. This value is sufficiently large to reset the zone 7 and is also suf­ ficiently large to be able to drain capacitive cross-talk. Via the connection 23, instead of 5 V a lower voltage of about 3 V is therefore applied to a drain zone 14 and hence to the reading zone 7, as a result of which a voltage of 5 V equal to the supply voltage can be applied to the gate 13 in order to reset the zone 7. In order to illustrate this, Fig. 2 shows a diagram of potentials occurring during operation at the surface 2 of the substrate 1. The positive potential is plotted in downward direction, as is usual in the technical literature. Fig. 2 il­ lustrates the situation in which the voltage of 5 V is applied to the clock electrode 3(⊘₂) and the voltage of 0 V is applied to the clock electrode 4(⊘₃). Below the clock electrode 3 a potential well is formed, in which a charge packet 29 is stored. Below the clock electrode 4(⊘₁) a potential barrier 30 is formed. The charge packet 29 can be shifted, as is known, by one position by applying to the clock electrode 4 the voltage 5 V and to the clock electrode 3 the voltage 0 V. The fixed voltage V₂₇ of about 3 V is applied to the blocking gate 16. As a result, below the electrode 16 the potential 31 is induced, which is such that, when ⊘₁ passes from 5 V to 0 V, the charged stored below the clock electrode 4 flows to the reading zone 7 across the potential levels 31. The potential level 32 of the reading zone is equal to the potential at the junction 27 when no charge packet is present. There can be stored in the potential well 32 a charge packet 33, which of course must not be so large that the charge is partly stored below the electrode 16, as a result of which a correct reading of the packet becomes impossible. On the righthand side, the charge packet 33 is limited by the potential barrier 34, which is formed when a voltage of 0 V is applied to the gate electrode 13 of the reset transistor. After reading, the voltage of 5 V equal to the supply voltage applied to the gate electrode 13 of the reset transistor and this voltage corresponds to the potential level 35. If it is assumed that the threshold voltage of the reset transistor 7, 13, 14 is equal to the threshold voltage of the transistor T₁ and hence is also equal to 1 V, it will be appreciated that the volt­ age of 5 V at the gate electrode 13, which voltage is equal to the gate voltage at the gate electrode 21 of T₁, is sufficient to guarantee that the reset transistor is closed (conducting) so that the charge packet 33 is drained. The reset transistor remains conducting until the voltage level in the zone 7 is equal to the voltage at the zone 14, i.e. the voltage at the source 22 of the - conducting - transistor T₁. In the embodiment described herein, the voltage of the gate 27 (source 22 of T₁) is also applied to the blocking gate 16a, 16. When a charge packet is transferred from the region below the clock electrode 3 to the region below the clock electrode 4, the potential well below the clock electrode 3 and the potential barrier below the clock electrode 4 are raised and reduced, respectively. There is a possibility, when the supply voltages are largely exceeded at marginal threshold voltages, that a certain amount of charge from the charge packet to be transferred via the barrier 31 is lost prematurely via the reset transistor. Fig. 3 shows a simple method of solving this problem. In principle, the solution consists in that the part 16b of the blocking gate 16 is no longer applied together with the part 16a to a fixed potential, but that only the part 16a located beside the zone 7 is applied to a fixed potential, while a varying voltage is applied to the part 16b. This varying voltage is chosen so that, when the volt­ ages at the clock electrodes are varied, a potential barrier is present below the part 16b, which barrier prevents the said loss of charge. In a simple embodiment shown in Fig. 3, the electrode part 16b has applied to it a clock voltage which has the same voltage levels of 0 and 5 V as the clock voltage ⊘₂ and is in phase opposition to ⊘ r . In Fig. 3, this is indicated symbolically by the inverter 37 (inverter circuit). Fig. 4 shows a diagram of the clock voltages ⊘₁ and ⊘₂ and the reset clock voltage ⊘ r and the clock voltage applied to the blocking gate 16b as a function of the time t . At the instant t₁ at which ⊘₁ passes from 5 V to 0 V and ⊘₂ passes from 0 V to 5 V, passes from 5 V to 0 V, as a result of which a potential barrier is formed below the electrode part 16b. When ⊘₂ is at 5 V and a potential well is formed below the electrode 4, can return to 5 V. It will be appreciated that the invention is not limited to the embodiments shown herein, but that many further modifications are possible for those skilled in the art without departing from the scope of the invention. For example, instead of the transistor T₂, a current source may alternatively be used in the circuit 18. In the embodiments described, the reset transistor is provided with a single gate electrode. Advantageously, however, the reset transistor may also be provided with two gate electrodes in order to reduce clock cross-talk.

Claims: 1. A charge transfer device comprising a semiconductor body, at a surface of which is defined a charge transport channel for storing and transporting information in the form of discrete charge packets to an output stage, which has a zone for temporarily storing and reading the charge packets and an insulated gate field effect transistor which forms a reset transistor draining a read charge packet and preparing the said zone for storing and reading a next charge packet, this transitor comprising a source region coupled to the said zone, an insulated gate connected to a clock voltage source for rendering the transistor intermittently con­ ducting and non-conducting, and a drain region connected to means for applying a suitable drain voltage, characterized in that the said means comprise a second insulated gate field effect transistor, which is designated hereinafter as auxiliary transistor, whose gate and drain can be applied to a fixed voltage V₁, more particular­ ly the supply voltage, and whose source is connected to the drain region of the reset transistor and to current supply means for passing current through the auxiliary transistor, and in that the gate of the reset transistor is connected to a clock voltage source, by means of which in the conductive state of the reset transistor, the voltage V₁ is also applied to the gate of the reset transistor. 2. A charge transfer device as claimed in Claim 1, characterized in that the reset transistor and the auxiliary tran­ sistor have channel regions of substantially the same dimensions. 3. A charge transfer device as claimed in Claim 1 or 2, characterized in that the said current supply means comprise a third insulated gate field effect transistor, whose gate electrode and whose drain are connected in common to the source of the auxiliary transistor, while the source of the third transistor can be applied to a fixed voltage. 4. A charge transfer device as claimed in Claim 3, characterized in that the third field effect transistor has sub­ stantially the same threshold voltage as the auxiliary transistor. 5. A charge transfer device as claimed in any one of the preceding Claims, characterized in that above the charge transport channel and, viewed in the charge transport direction, in front of the said zone of the output stage there is arranged an insulated gate electrode, which is connected to the source of the auxiliary filed effect transistor.

Inventors: PELGROM, MARCELLINUS JOHANNES MARIA, SLOTBOOM, JAN WILLEM
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1986
Main classification: G11C27
IPC codes: G11C19, H04N5, H01L27, H01L21, H01L29, G11C27