DYNAMIC TYPE MEMORY DEVICE

Abstract: A dynamic type memory device includes a plurality of one-­ transistor/one-capacitor type memory cells (MC-11 to MC-­ MN) which are arranged in a matrix, first bit lines (BL1-1 to BL1-M) connected to the memory cells (MC-11 to MC-MN), second bit lines BL0-1 to BL0-M), and first capacitors (C₁) re­ spectively connected to the second bit lines (BL0-1 to BL0-M) and having a capacitance equal to 1 / 2 of that of the memory cell capacitor (CS). This memory device further has second capa­ citors (C₂) respectively connected to the second bit lines (BL0-1 to BL0-M) and having a capacitance equal to 1 / 2 of that of the memory cell capacitor (CS), first switching transistors (Q₆) connected respectively between a power source terminal (VC) and the first capacitors (C₁), and second switching tran­ sistors (Q₇) connected respectively between a ground termi­ nal (VS) and the second capacitors (C₂).

Description: The present invention relates to a dynamic type memory device comprising: a plurality of memory cells each having one transistor (Q₁) and one capacitor; a plurality of first bit lines each of which being connected to the memory cells on the same column; a plurality of second bit lines; a plurality of word lines each of which is connected to the memory cells on the same row; a power source terminal to which a power source voltage is applied, and a reference potential terminal which is held at a reference potential; a plurality of first capacitors each having a capacitance equal to 1/2 of that of the capacitor of each of said memory cells; and potential setting means connecting said reference potential terminal to said second bit lines through said first capacitors in a data readout mode to set potentials of said second bit lines. A dynamic type memory device of this kind is known from EP-A-0 068 894. Other conventional dynamic type memory cells are described subsequently in more detail by reference to Figs. 1 to 4 of the enclosed drawings. According to Fig. 1, such a conventional memory device is constituted in such a manner that one end of each of paired bit lines BL and BL is connected to a sense amplifier 12, capacitor CS is connected to bit line BL through MOS transistor Q1 whose gate is connected to word line WL, and capacitor CD is connected to bit line BL through MOS transistor Q₅ whose gate is connected to dummy word line DWL. The other terminals of capacitors CS and CD are connected to fixed voltage terminal VA. The other ends of bit lines BL and BL are connected to each other by MOS transistor Q₂ and are respectively connected through MOS transistors Q₃ and Q₄ to a predetermined voltage line VCL which is kept at, for example, 1/2 VC. An equalizing signal  EQ is supplied to gates of MOS transistors Q₂ to Q₄. Capacitors CS and CD are formed to have the same capacitance. MOS transistor Q₁ and capacitor CS constitute a memory cell 11. MOS transistor Q₅ and capacitor CD constitute a dummy cell 13. The operation of the memory device shown in Fig. 1 will be described with reference to signal waveforms shown in Figs. 2(A) to 2(E). In this memory device, when equalizing signal  EQ is at a high level, MOS transistors Q₂ to Q₄ are made conductive and both bit lines BL and BL are precharged to the level of 1/2 VC. After data is written into memory cell 11, the voltage of 1/2 VC is written into dummy cell 13. After a row address strobe signal RAS is set to a low level at time t1 as shown in Fig. 2(A), when equalizing signal  EQ becomes low at time t₂ as shown in Fig. 2(C), MOS transistors Q₂ to Q₄ are made non-conductive, so that bit lines BL and BL are isolated from each other. When the potentials of dummy word line DWL and word line WL are set to a high level as shown in Figs. 2(D) and 2(B), the data in dummy cell 13 and memory cell 11 are read out and outputted onto bit lines BL and BL respectively, so that the potentials of bit lines BL and BL will change as shown in Fig. 2(E). The difference between the potentials of bit lines BL and BL is amplified by sense amplifier 12 and corresponding readout data is taken out from sense amplifier 12. Next, row address strobe signal RAS is set to a high level and the potential of word line WL is set to a low level and thereafter equalizing signal  EQ is set to a high level. Thus, MOS transistors Q₂ to Q₄ are made conductive and both potentials of bit lines BL and BL are set to 1/2 VC. After the voltage of the 1/2 VC level is written into dummy cell 13, the potential of dummy word line DWL is set low as shown in Fig. 2(D). In the memory device shown in Fig. 1, to certainly write the voltage of 1/2 VC into dummy cell 13, it is necessary to set dummy word line DWL to a high potential. A voltage step-up circuit needs to be connected to dummy word line DWL for this purpose, causing the structure or this memory device to be complicated. In addition, to write the voltage of 1/2 VC into dummy cell 13, it is necessary to hold dummy word line DWL at a high level for a predetermined time as well even after row address strobe signal RAS is set to a high level. Therefore, a special control circuit is needed to control the potential of dummy word line DWL. A memory device shown in Fig. 3 is constituted similarly to that shown in Fig. 1 except that dummy cell 13 and MOS transistors Q₃ and Q₄ are removed. This memory device operates in accordance with signal waveforms shown in Figs. 4A to 4D. Namely, in this memory device, after row address strobe signal RAS is set at a low level as shown in Fig. 4(A), equalizing signal  EQ is set at a high level as shown in Fig. 4(C). Thereafter, when the potential of word line WL is set at a high level as shown in Fig. 4(B), the data in memory cell 11 is read out and outputted onto bit lines BL and BL and the potentials of bit lines BL and BL are changed in accordance with the data read out as shown in Fig. 4(D). By equalizing the potentials of bit lines BL and BL in initial time of each readout operation as described above, data can be read out without being influenced due to the fluctuation of the power source voltage. However, data readout operation cannot be started until the potentials of bit lines BL and BL are equalized after strobe signal RAS is set at a low level, so that the access time eventually becomes long. It is an object of the present invention to provide a dynamic type memory device of the kind as described at the beginning of this description, which device can operate at a high speed with a simple constitution. This object is accomplished by the features specified in the characterizing part of claim 1. Further improvements according to the present invention are specified in the sub-claims. According to the present invention, in place of any dummy cells to hold a predetermined potential, the potential setting circuits for setting the potentials of the second bit lines through the first and second capacitors in a precharge cycle are used, so that it is not required to use any dummy word line. Therefore, there is no need to use any voltage step-up circuit and the structure of the memory device is simplified. This invention can be more fully understood from the following detailed description of a preferred embodiment when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a conventional memory device; Figs. 2(A) to 2(E) are signal waveform diagrams for explaining the operation of the memory device shown in Fig. 1; Fig. 3 is a circuit diagram of another conventional memory device; Figs. 4(A) to 4(D) are signal waveform diagrams for explaining the operation of the memory device shown in Fig. 3; Fig. 5 is a circuit diagram of a dynamic type memory device according to an embodiment of the present invention; Figs. 6A to 6F are signal waveform diagrams for explaining the operation of the memory device shown in Fig. 5; and Figs. 7A and 7B show changes of potentials of a pair of bit lines in the case where data "1" and "0" are read out from a memory cell shown in Fig. 5. Fig. 5 shows a dynamic type memory device according to an embodiment of the present invention. This memory device comprises memory cells MC-11 to MC-MN arranged in a matrix; word lines WL₁ to WL N each of which is connected to the memory cells on the same row; and a plurality of pairs of bit lines BL1-1 to BL1-M and BL0-1 to BL0-M each of which pair is connected to the memory cells on the same column. Each memory cell has a capacitor CS one end of which is connected to bit line BL1-i through MOS transistor Q1 whose gate is connected to word line WLj and the other end of which is connected to a constant voltage terminal VA. The bit lines of each pair are connected to a corresponding one of sense amplifiers SA-1 to SA-M at one end, and at the other end these bit lines are connected to each other by a corresponding one of MOS transistors Q2-1 to Q2-M. Both ends of MOS transistors Q2-1 to Q2-M are respectively connected to a constant voltage line or precharge line VB through MOS transistors Q3-1 to Q3-M and MOS transistors Q4-1 to Q4-M. Equalizing signal  EQ is supplied to gates of those MOS transistors Q2-1 to Q2-M, Q3-1 to Q3-M, and Q4-1 to Q4-M. Dummy cells or potential setting circuits PSC-1 to PSC-M are connected to bit lines BL0-1 to BL0-M in order to set the potentials of these bit lines. These potential setting circuits PSC-1 to PSC-M are constituted substantially in the same manner. A constitution of potential setting circuit PSC-1 will be described in detail. Potential setting circuit PSC-1 has capacitors C₁ and C₂ one end of which is connected to bit line BL0-1 and the other ends of which are respectively connected to power source terminal VC and a ground terminal VS through p- and n-channel MOS transistors Q₆ and Q₇. Control signals CS' and CS ' are supplied to gates of MOS transistors Q₆ and Q₇, respectively. A connecting point of capacitor C1 and MOS transistor Q₆ is connected to constant voltage line VB through a dummy word line DWL₁ and a MOS transistor Q₈. A connecting point of capacitor C₂ and MOS transistor Q₇ is connected to constant voltage line VB through a dummy word line DWL₀ and a MOS transistor Q₉. A MOS transistor Q₁₀ is connected between dummy word lines DWL₁ and DWL₀. Equalizing signal  EQ is also supplied to gates of MOS transistors Q8 to Q10. The operation of the memory device shown in Fig. 5 will be described with reference to Figs. 6A to 6F and Figs. 7A and 7B. When row address strobe signal RAS becomes low at time t0 as shown in Fig. 6A and equalizing signal  EQ becomes low at time t₁ as shown in Fig. 6D, MOS transistors Q2-1 to Q2-M, Q3-1 to Q3-M, and Q4-1 to Q4-M, and MOS transistors Q₈ to Q₁₀ of each of potential setting circuits PSC-1 to PSC-M are made non-conductive, thereby setting this memory device into the accessible state. When the potential of one of word lines WL₁ to WL N , for example, word line WL₁ is set to a high level at time t2 as shown in Fig. 6B and at the same time control signals CS' and CS ' are set to low and high levels as shown by solid and broken lines in Fig. 6C, respectively, MOS transistors Q₁ of memory cells MC-11 to MC-M1 are made conductive and the data in these memory cells are read out and outputted onto bit lines BL1-1 to BL1-M. In this case, since MOS transistors Q₆ and Q₇ are conductive, the potentials of dummy word lines DWL₁ and DWL₀ are set to high and low levels as shown by solid and broken lines in Fig. 6E, respectively. Sense amplifiers SA-1 to SA-M amplify the difference between the potentials of bit lines BL1-1 to BL1-M and BL0-1 to BL0-M and set the potentials of these bit lines BL1-1 to BL1-M and BL0-1 to BL0-M as shown in Fig. 6F in accordance with the data read out from the memory cells. In the case where data "1" is read out from memory cell MC-11, the potential of bit line BL1-1 changes from a precharge potential level VBP (= 1/2 VC) to a potential level VB₁ which is given by the following equation as shown in Fig. 7A. where, CB is a stray capacitance associated with each of bit lines BL1-1 and BL0-1. In the case where data "0" is read out from memory cell MC-11, the potential of bit line BL1-1 changes from VBP to a potential level VB₀ which is given by the following equation as shown in Fig. 7B. After time t2, namely, after the potentials of dummy word lines DWL1 and DWL0 are set to high and low levels, respectively, the potential of bit line BL0-1 changes from VBM to VBX which is obtained by the following equations. CB·VBP = CB·VBX + C₁·(VBX - VC) + C₂·VBX (3) C₁ = C₂ = ½CS (4) By substituting equation (4) into equation (3), the following equation is derived. Therefore, when data "0" or "1" is read out, the difference between the potentials of bit lines BL1-1 and BL0-1 becomes VC / 2 · CS/(CB + CS). Consequently, the same sense margin is obtained for the readout of data "1" and "0" irrespective of the level of precharge potential VBP. As described above, according to the memory device shown in Fig. 5, the data read out from the memory cell is independent of the precharge potentials of the pair of bit lines at a time just before the readout operation and the variation ranges of the signal level in the case where data "0" and "1" are read out can be made substantially equal. In addition, in this memory device, the potentials of the pair of bit lines can be equalized at a desired timing. In this case, since it takes a relatively long time for this equalizing operation, the bit lines can be precharged during this equalizing operation. In the memory device shown in Fig. 5, potential setting circuit PSC-1 is constituted by CMOS transistors Q₆ and Q₇, n-channel MOS transistors Q₈ to Q₁₀, and capacitors C₁ and C₂, so that a large occupied area is unnecessary. In addition, since control signals CS' and CS ' change synchronously with the potential change or word lines WL selected, these control signals CS' and CS ' can be easily formed in accordance with the change in potential of word lines WL. Although the invention has been described above with respect to one embodiment, the invention is not limited to only this embodiment. For example, although one end of capacitor CS of the memory cell is connected to constant voltage terminal VA in the embodiment, in place of this constitution, it may also be connected to voltage source terminal VCP to which a fluctuating voltage varying in accordance with fluctuation of power source voltage VC is applied. With this constitution, the influence on the readout data due to the fluctuation of power source voltage VC can be suppressed.

Claims: A dynamic type memory device comprising: (a) a plurality of memory cells (MC-11 to MC-MN) each having one transistor (Q₁) and one capacitor (CS); (b) M first bit lines (BL1-1 to BL1-M) each of which being connected to the memory cells on the same column and to the first input of a respective differential sense amplifier; (c) M second bit lines (BL0-1 to BL0-M) being connected to the second input of the respective differential amplifier; (d) a plurality of word lines (WL₁ to WL N ) each of which is connected to the memory cells on the same row; (e) a power source terminal (VC) to which a power source voltage is applied, and a reference potential terminal (VS) which is held at a reference potential; (f) M first capacitors (C₂) each having a capacitance equal to 1/2 of that of the capacitor (CS) of each of said memory cells (MC-11 to MC-MN); and (g) potential setting means (PSC-1 to PSC-M), connecting said reference potential terminal (VS) to said second bit lines (BL0-1 to BL0-M) through said first capacitors (C₂) in a data readout mode to set potentials of said second bit lines (BL0-1 to BL0-M); characterized in that (h) M second capacitors (C₁) are provided, each of which having a capacitance equal to 1/2 of that of the capacitor (CS) of each of said memory cells (MC-11 to MC-MN); and (i) said potential setting means (PSC-1 to PSC-M) also connect said power source terminal (VC) to said second bit lines (BL0-1 to BL0-M) through said second capacitors (C₁) in the data readout mode. A dynamic type memory device according to claim 1, characterized in that said potential setting means includes a plurality of potential setting circuits (PSC-1 to PSC-M) each including first switching means (Q₆) which is connected in series to a corresponding one of said second capacitors (C₁) between said power source terminal (VC) and a corresponding one of said second bit lines (BL0-1 to BL0-M) and second switching means (Q₇) which is connected in series to a corresponding one of said first capacitors (C₂) between said reference potential terminal (VS) and the corresponding one of said second bit lines (BL0-1 to BL0-M). A dynamic type memory device according to claim 2, characterized by further comprising a plurality of third switching means (Q2-1 to Q2-M) each of which is connected between a corresponding one of said first bit lines (BL1-1 to BL1-M) and a corresponding one of said second bit lines (BL0-1 to BL0-M); a plurality of fourth switching means (Q3-1 to Q3-M) each of which is connected between a precharge line (VB) and a corresponding one of said first bit lines (BL1-1 to BL1-M); and a plurality of fifth switching means (Q4-1 to Q4-M) each of which is connected between said precharge line (VB) and a corresponding one of said second bit lines (BL0-1 to BL0-M). A dynamic type memory device according to claim 1, characterized in that each of said first capacitors (C₂) is connected at one end to a corresponding one of said second bit lines (BL0-1 to BL0-M) and each of said second capacitors (C₁) is connected at one end to the corresponding one of said second bit lines (BL0-1 to BL0-M), and said potential setting means includes a plurality of potential setting circuits (PSC-1 to PSC-M) each including first switching means (Q₆) connected between said power source terminal (VC) and a corresponding one of said second capacitors (C₁) and second switching means (Q₇) connected between said reference potential terminal (VS) and a corresponding one of said first capacitors (C₂). A dynamic type memory device according to claim 4, characterized by further comprising a plurality of third switching means (Q2-1 to Q2-M) each of which is connected between corresponding one of said first bit lines (BL1-1 to BL1-M) and corresponding one of said second bit lines (BL0-1 to BL0-W); a plurality of fourth switching means (Q3-1 to Q3-M) each of which is connected between a precharge line (VB) and corresponding one of said first bit lines (BL1-1 to BL1-M); and a plurality of fifth switching means (Q4-1 to Q4-M) each of which is connected between said precharge line (VB) and corresponding one of said second bit lines (BL0-1 to BL0-M). A dynamic type memory device according to claim 5, characterized in that each of said potential setting means (PSC-1 to PSC-M) further has sixth switching means (Q₁₀) connected between the other ends of said first and second capacitors (C₂ and C₁) and seventh and eighth switching means (Q₈ and Q₉) connected between the other ends of said first and second capacitors (C₂ and C₁) and said precharge line (VB).

Inventors: OKADA, YOSHIO C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: G11C11
IPC codes: G11C11