SEMICONDUCTOR DEVICE WITH PROTECTIVE MEANS AGAINST OVERHEATING

Abstract: A semiconductor substrate (11) has a power region (12) and a control region (13). The control region (13) is located in the center portion of the substrate (11), and the power region (12) surrounds the control region (13) and is separated therefrom. A vertical type, MOS transistor (22), i.e., an active semiconductor element, is formed on the power region (12). An insulation film (24) is formed on part of the control region (13). A polycrystalline silicon diode (25), which functions as a heat-sensitive element, is formed on the insultation film (24). A control section comprising a lateral type, MOS transistor (26) is formed on the control region (13). The lateral type, MOS transistor (26) is connected to receive a signal from the polycrystalline silicon diode, (25). Further, a polycrystalline silicon resistor (27), which determines a circuit constant, is formed on the insultation film (24). The MOS transistor (26) protects the active semiconductor element in response to a signal suppled from said heat-sensitive element and show­ ing that the temperature of said semi-conductor substrate has risen above a predetermined value.

Description: The present invention relates to a semiconductor device according to the preamble of claim 1. A semiconductor device of that type is known from DE-A-3 007 403 . This Document discloses a semiconductor device which comprises a semiconductor substrate, at least one active semiconductor element which is formed on the semiconductor substrate in a power region thereof. Furthermore, there is provided a heat-sensitive element in the form of a transistor for detecting a respective temperature of the semiconductor substrate, wherein a protection circuit (comparator) is interrupting any further heat generation of the active semiconductor element(s) when the temperature detected by the heat-sensitive element exceeds a predetermined value. The heat-sensitive element and the protection circuit are formed on another region of the semiconductor substrate, thus forming a "control region" in the terms of claim 1. The Document EP-A-0 060 635 discloses a semiconductor device which comprises a protection element for protecting MOSFET's of the device against an external surge voltage or the like. This protection element, consequently, is formed by a diode so that it is possible that there is formed a parasitic transistor which may damage the MOSFET. In order to prevent the formation of such a parasitic transistor, an insulating film is provided between the protection element and the underlying substrate region. This Document, however, does not disclose the use of an heat-sensitive element. A drawback of the semiconductor device known from DE-A-3 007 403 , however, has to be seen in that it is impossible to trim the semiconductor substrate and the heat-sensitive element independently. Furthermore, this known semiconductor device is disadvantageous in that the heat-sensitive element, under certain circumstances, will not respond fast enough to an overheat condition in case that the temperature is rising very quickly. Hence, the thermal protection abilities of this known semiconductor device yet could be improved. It is therefore the object of the present invention to improve a semiconductor device according to the preamble of claim 1 in such a way that it is possible to completely decouple the protection circuit from any influence of the semiconductor substrate and to provide a better thermal protection response time. According to the present invention this object is solved by the advantageous measures indicated in the characterizing part of claim 1. It has been found that these measures provide a very fast response to any increase of the temperature because the center portion of the semiconductor substrate has only a poor heat-radiating characteristic so that the temperature thereof does easily rise. Thus, a better thermal protection response time is provided. By the advantageous measures of claim 1 it furthermore is possible to trim the semiconductor substrate and the heat-sensitive element independently. Thus, the present invention offers the additional advantage that the protection circuit can be completely decoupled from any influence of the semiconductor substrate. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a plan view of a semiconductor device according to one embodiment of the present invention, showing the positions of the various regions of the device; Fig. 2 is a cross-sectional view of the device, taken along line α-α in Fig. 1; Fig. 3 is an equivalent circuit diagram of the control section provided within the semiconductor device; Fig. 4 is a graph illustrating the relationship between the temperature of the junction of a power MOS transistor and the gate voltage of the transistor, and also the relationship between the temperature and the drain voltage of the transistor; Fig. 5 is a cross-sectional view of another control section which can be provided in the device of Fig. 1; Figs. 6 to 9 are graphs representing the characteristics of the polycrystalline silicon diodes used in the device of Fig. 1; Fig. 10 is a circuit diagram of still another control section; Fig. 11 is a graph showing the relationship between the gate voltage of the MOS transistor used in the control section of Fig. 10 and the temperature of the junction of the MOS transistor; and Fig. 12 is a circuit diagram of a further control section which can be used in the device of Fig. 1. Fig. 1 is a schematical plan view of a semiconductor device according to the invention, which has means for protecting the device from overheating. The device comprises semiconductor substrate 11. As shown in Fig. 1, the greater part of substrate 11 is power region 12. A semiconductor circuit including active elements is formed in power region 12. The center portion of substrate 11, which has a low heat-radiation efficiency and can easily be heated to a high temperature, is control region 13 which functions to detect temperature. Bonding pads 14 and 15 are formed on semiconductor substrate 11. Pad 14 is used to draw the gate electrodes of the active elements, and pad 15 is used to draw the source electrodes of the active elements. Fig. 2 is a cross-sectional view of the semiconductor device, taken along line α-α. Particularly, the figure shows control region 13 and that portion of power region 12 which surrounds region 13, As is shown in Fig. 2, a vertical type power MOS transistor (an active element) 22 is formed in power region 12. Other power MOS transistors (not shown) are formed in power region 12. MOS transistor 22 and other power MOS transistors (not shown) are arranged in rows and columns, and are connected in parallel, thereby forming a semiconductor circuit of multi-source structure. Insulation film 24 is formed on control region 13. A plurality of polycrystalline silicon diodes 25 are formed on insulation film 24. Diodes 25 are connected in series, thus forming a heat-sensitive element. Lateral type MOS transistor 26, polycrystalline silicon resistor 27 and constant-voltage zener diode 28 are provided around diodes 25. Transistor 26, resistor 27 and zener diode 28 form a control section. The structure of the semiconductor device will be described in greater detail, with reference to Fig. 2. Semiconductor substrate 11 is an N⁺ type silicon substrate 111. N⁻ type silicon epitaxial layer 112 is formed on the substrate 111. Deep P type diffusion layer 291 is formed in that portion of epitaxial layer 112 which corresponds to power region 12. P type diffusion layer 292, which corresponds to control region 13, is formed in a similar manner. Further, shallow P type layer 30, which corresponds to P type diffusion layer 291, is formed. Further, N⁺ type diffusion layer 31, which correspond to vertical type MOS transistor 22, is formed. N⁺ type diffusion layers 321 and 322, which correspond to lateral type MOS transistor 26, are formed. N⁺ type diffusion layer, which corresponds to constant-voltage zener diode 28, is formed. Further, P⁺ type diffusion layer 34 is formed. Power MOS transistor 22 comprises silicon epitaxial layer 112, silicon substrate 111, and drain D made or drain electrode 35. Gate G of transistor 22 is formed of polycrystalline silicon layer 37 formed on gate oxide film 36. Source S of transistor 22 is made of aluminum electrode 39 covering inter-layer insulation film 38 which in turn covers up polycrystalline silicon layer 37. When gate voltage is applied to gate G from terminal 40 through bonding pad 14, a channel is formed between silicon epitaxial layer 112 and N⁺ type diffusion layers 31 and 32. As a result, a current flows between source S and drain D, more precisely between terminals 41 and 42. As has been described, P type diffusion layer 291 is formed partly in P type diffusion layer 30, and is deeper than layer 30. Hence, power MOS transistor 22 can be protected against an excessively high voltage. P type diffusion layers 30 and 291 having this specific positional relation determine the breakdown voltage of MOS transistor 22. Lateral type MOS transistor 26 has a source formed of N⁺ type diffusion layer 321 and aluminum electrode 43, and contacting layer 321, a drain made of N⁺ type diffusion layer 322 and aluminum electrode 44, and contacting layer 322, and a gate made of polycrystalline silicon layer 46. Silicon layer 46 is formed on gate oxide film 45 which in turn is formed partly on layers 321 and 322 and partly on P type diffusion layer 292. When gate voltage is applied to the gate from terminal 47, an N channel is formed among polycrystalline silicon layer 46 and N⁺ type diffusion layers 321 and 322. As a result, a current flows between terminal 48 (source) and terminal 49 (drain). Constant-voltage zener diode 28 comprises diffusion layers 33 and 34. Aluminum electrodes 50 and 51 contact layers 34 and 33, respectively. Electrodes 50 and 51 are connected to terminals 52 and 53. Insulation film 24 of, for example, SiO₂ is formed by thermal oxidation on diffusion layer 292 occupying control region 13. Polycrystalline silicon resistor 27 and polycrystalline silicon diode 25 having a PN junction are formed on insulation film 24. Resistor 27 is made of polycrystalline silicon layer 55. Aluminum electrodes 56 and 57 contact layer 55 and are connected to terminals 58 and 59. Diode 25 has been formed by diffusing a prescribed impurity into polycrystalline silicon layer 60, thereby forming a PN junction. Aluminum electrode 61 is formed on the P type portion of layer 60, and aluminum electrode 62 is formed on the N type portion of layer 60. Electrodes 61 and 62 are connected to terminals 63 and 64. Fig. 3 is an equivalent circuit diagram showing the semiconductor device of Fig. 2. In this figure, the same numerals are used to designate the same components as shown in Figs. 1 and 2, except that numerals 271 to 273 denote polycrystalline silicon resistors, R L represents a load resistor connected to an external device, and Vdd denotes an external power source. When the temperature of silicon substrate 111 is below a predetermined value, that is, when the junction of power MOS transistor 22 is at normal temperature, transistor 22 is turned on by input voltage Vin. When the temperature of silicon substrate 111 rises above the predetermined value, that is, when the junction of power MOS transistor 22 is at excessively high temperature, the forward voltage of polycrystalline silicon diode 25, which functions as a heat-sensitive element, lowers. Diode 25 has a particular negative temperature coefficient. Hence, the more it is heated, the more its forward voltage falls. When the forward voltage of diode 25 lowers, resistor 163 raises the gate-source voltage of lateral MOS transistor 26. When its gate-source voltage rises, MOS transistor 26 is turned on. If resistor 272 has a resistance much higher than the resistance which MOS transistor 26 has while transistor 26 is on, the potential at point 40 where the drain electrode of transistor 26 is located, and where gate G of power MOS transistor 22 is coupled, will abruptly fall when the temperature of substrate 111 rises above the predetermined value. Fig. 4 shows the relationship between the gate voltage Vg and drain voltage Vd of power MOS transistor 22, on the one hand, and the temperature of the junction of this MOS transistor. When temperature of the junction rises to 130°C or (hereabout, transistor 26 is turned on, thereby quickly reducing gate voltage Vg to zero volt to protect power MOS transistor 22. To be precise, when this temperature rises to about 130°C, transistor 22 is forcibly turned off, thereby protecting the elements from break. As has been stated, polycrystalline silicon diode 25 (i.e., the heat-sensing element) and silicon resistor 27 are provided on insulation film 24 formed on control region 13. This structural feature makes it easy to trim these elements independently. Further, due to this feature, no parasitic actions occur between these elements. Moreover, since polycrystalline silicon diode 25, which functions as a heat-sensitive element, is located in control region 13, i.e., the center Portion of substrate 11, it can accurately measure the temperature rise of substrate 11 resulting from a junction temperature rise of power MOS transistor 22, and can therefore ensure a reliable protection of the elements from breakdown. The elements on insulation film 24 can be made in the same steps as power MOS transistor 22. In other words, no additional steps need to be carried out to manufacture these elements. Polycrystalline silicon resistor 27 can be trimmed. Hence, its resistance can be accurately adjusted to any reference temperature selected, after the semiconductor device has been manufactured. Alternatively, the reference temperature can be set to any desired value by forming a required number of PN junctions in polycrystalline silicon diode 27. In the above embodiment, silicon diode 25 and silicon resistor 27, both formed in control region 13, are formed on insulation film 24. All the other elements can also be formed on insulation film 24. As Further, as is shown in Fig. 5, it is possible to form lateral MOS transistor 261 on insulation film 24, and constant-voltage zener diode 28 directly on diffusion layer 292. Alternatively, lateral transistor 261 can be formed on diffusion layer 292, and zener diode 28 can be formed on insulation film 24. In the above embodiment, MOS transistors 22 and 26 have an N channel. Needless to say, they can be so formed as to have a P channel. The embodiment, i.e., the semiconductor device has an active element, that is, a power MOS transistor. This MOS transistor can be replaced by a bipolar transistor or a power IC. Further, polycrystalline silicon diode 25, which functions as the heat-sensitive element, can be replaced by a thermistor of the ordinary type. Moreover, the polycrystalline silicon resistors can be replaced by resistors made of tantalum nitride. Generally, it is difficult to manufacture diodes having the design breakdown characteristic or the design temperature characteristics when the diodes are made of polycrystalline silicon formed by depositing silicon. The polycrystalline silicon diode used in the present invention has both the design breakdown characteristic and the design temperature characteristic. It comprises a P type region and an N type region which form a PN junction. The low impurity-concentration portions or the N type and P type regions have impurity concentrations of 1 × 10¹⁹ cm⁻³ or more. In the polycrystalline silicon diode, that region of a silicon island, which will become an N type region, is doped with phosphorus, an N type impurity, and that region, which will become a P type region, is doped with boron, a P type impurity. The concentration of boron influences very much the breakdown characteristic and temperature characteristic of the diode. The concentration of boron is selected to be 1 × 10¹⁹ cm⁻³, thus imparting the desired breakdown characteristic and temperature characteristic to the diode. Hence, the diode is greatly reliable. With reference to Fig. 2, the process of forming polycrystalline diode 25 will be briefly explained. First, a polycrystalline silicon film having a thickness of about 2000 Å to about 5000 Å is formed by the CVD method on insulation film 24 which has been formed by thermal oxidation of silicon substrate 11. The silicon film is then patterned by plasma etching. Phosphorus ions are injected into the patterned polycrystalline silicon film, thereby forming an N type region. Further, boron ions are injected into that portion of the silicon film which surrounds the N type region, thus forming a P type region. Thereafter, the unfinished product is heated, thus activating the phosphorus and boron ions. An inter-layer insulation film of oxide silicon or the like is formed by the CVD method on the upper surface of the unfinished product. The polycrystalline silicon used for forming the diode of the structure described above is made up of countless crystals. Trap level exist at the interfaces among these crystals. Carriers are therefore trapped in the tap level, inevitably building up a barrier potential. This barrier potential largely depends on the quality of the polycrystalline silicon film. It will ultimately much influence the characteristics of the polycrystalline silicon diode. More specifically, the value of the barrier potential is determined by the amount of the impurity contained in the polycrystalline silicon. The greater the content of the impurity, the lower the barrier potential. Therefore, the low impurity-concentration portions of the N and P type regions forming the polycrystalline silicon diode must have a relatively high impurity concentration in order to stabilize the characteristics of the diode. Fig. 6 represents the relationship between the boron concentration of the P type region of the diode and the breakdown voltage of the diode. Fig. 7 shows the relationship between this boron concentration and the difference in breakdown voltage among the diodes. Fig. 8 illustrates the relationship between the boron concentration and the temperature coefficient of forward voltage. Fig. 9 shows the relationship between the boron concentration and the difference in temperature coefficient among the diodes. As is shown in Figs. 7 and 9, when the P type region has a boron concentration of 1 × 10¹⁹ cm⁻³ or more, the difference of breakdown voltage and the difference of temperature coefficient sharply decrease. Polycrystalline silicon diode 35, whose P type region has a boron concentration of 1 × 10¹⁹ cm⁻³, has both a design withstand voltage and a design temperature characteristic. Instead of controlling the boron concentration of the P type region of diode 35, the concentration of an N type impurity (e.g., phosphorus or arsenic) can be controlled for the purpose of imparting design withstand voltage and temperature characteristic to the diode. In this case, too, the concentration of the N type impurity is set to be 1 × 10¹⁹ cm⁻³. Fig. 10 shows another control section which is formed in control region 13. This control section comprises unit 100 for protecting the device against an excessive temperature rise, hysteresis unit 200 and gate-protecting unit 300. Unit 100 is similar to the protective unit shown in Fig. 3. To fabricate the control section of Fig. 10, polycrystalline silicon diode 25, lateral type MOS transistor 26, polycrystalline silicon resistor 27 (271 - 275), constant-voltage zener diode 28, and like are formed on control region 13, i.e., the center portion of semiconductor substrate 11, side by side in the same plane as is illustrated in Fig. 1. Polycrystalline silicon diode 25, or a heat-sensitive element, is composed of a plurality of silicon islands. The silicon islands form the PN junctions of series-connected diode elements. Hysteresis unit 200 comprises MOS transistor 70, diode 71, etc. which are formed in control region 13. MOS transistor 70 is a lateral type transistor. Unit 300 comprises a number of diodes 73 which are formed either within or without control region 13. The control section of Fig. 10 is advantageous over the control section of Fig. 3 in the following respect. In the section shown in Fig. 3, the drain of power MOS transistor 22 may oscillates when it is heated to the reference temperature or thereabout. In the control section of Fig. 10, hysteresis unit 200 gives hysteresis to the operating point of control MOS transistor 26, thereby preventing the drain of power MOS transistor from oscillating. Hence, lateral type MOS transistor 70, resistor 275 and level-shifting diode 71 cooperate to vary the potential at the point corresponding to the gate of lateral type MOS transistor 26. Gate voltage Vg of power MOS transistor 22 can thereby have such hysteresis as is illustrated in Fig. 11. The operation of the control section shown in Fig. 10 will be described in detail. As long as the temperature of silicon substrate 111 remains below the reference value, power MOS transistor 22 is on due to input voltage Vin, and MOS transistor 70 is also on. The resistance which MOS transistor 70 has in this condition is negligibly small in comparison with the resistance of resistor 275. The resistance of resistor 275 is much higher than the resistance which MOS transistor 70 exhibits when it is turned on. Therefore, the gate voltage of MOS transistor 26 is determined by the resistance of resistor 273 and the current flowing through resistor 273. When the temperature of silicon substrate 111 rises above the reference value, the forward voltage of polycrystalline silicon diode 25 (i.e., the heat-sensitive element) falls. As a result, the voltage between the ends of resistor 273 proportionately rises. When this voltage exceeds a predetermined value, MOS transistor 26 is turned on. More specifically, MOS transistor 26 is turned on when its junction temperature rises to 150°C or thereabout. Therefore, the gate voltage Vg of power MOS transistor 22 falls, and transistor 22 is turned off. Also, lateral type MOS transistor 70 is turned off. While power MOS transistor 22 is off, resistor 275 and diode 71 are connected in series to resistor 273 The resistance of this portion therefore increases. As a result, the voltage applied to the gate of MOS transistor 26 rises, and the operation temperature falls a little (to 120°C) as shown in Fig. 11. Consequently, the voltage drop in group 25 of diodes increases, whereby MOS transistor 26 is turned off. That is, sufficient hysteresis is provided, and the oscillation of power MOS transistor 22 is prevented. In other words, power MOS transistor 22 has such hysteresis that it is turned off when its junction temperature rises above 150°C, and is turned on when its junction temperature falls below 120°C. Fig. 12 shows still another control section according to the invention. This control section is, so to speak, a combination of the control section shown in Fig. 10 and unit 400 for protecting the semiconductor device against an excessively large current. Unit 400 has vertical type power MOS transistor 74. Transistor 74 is formed in the region where power MOS transistor 22 is formed. Its source electrode occupies a tiny portion of this region, i.e., 1/100 to 1/3000 of the region, and is electrically separated from transistor 22. Transistor 74 is driven by the same gate voltage as is applied to power MOS transistor 22, and outputs a small current proportional to the output current of power MOS tansistor 22. MOS transistor 75 is formed in the same substrate as other lateral MOS transistors 26 and 70. When external load R L is short-circuited, an excessively large current flows through power MOS transistor 22. Then, an excessively large current also flows into MOS transistor 74 which functions as a current-detecting element, thereby raising the gate potential of MOS transistor 75. When this gate potential reaches a threshold voltage of MOS transistor 75, a current will flow into transistor 75. As a result, the gate voltage of power MOS transistor 22 falls, and the output current of transistor 22 increases. Unit 400 has a stabilization point which is determined by circuit constants, such as the area ratio of power MOS transistor 22 to MOS transistor 74, the resistance of resistor 276, the threshold voltage of MOS transistor 75, and the ratio of the on-resistance of transistor 74 to the resistance of resistor 276. Hence, a maximum current is determined in accordance with this stabilization point. Without unit 400, the current ability of power MOS transistor 22 would indefinitely increases as the drain voltage increases. As long as the drain voltage is below a specific value (e.g., 2 volts), the current ability of transistor 22 increases in the same way as it would if unit 400 were not provided. However, once the drain voltage rises above this specific value, the drain current of MOS transistor 22 remains at a substantially constant value. Hence, even if the external load, for example, is short-circuited, the load current is limited to a specific value. The semiconductor elements and wiring of the semiconductor device can be reliably protected from an excessively large current.

Claims: A semiconductor device, comprising: [a] a semiconductor substrate (11) ; [b] at least one active semiconductor element (22) being formed on said semiconductor substrate (11) in a power region (12) thereof; [c] a heat-sensitive element (25) for detecting a respective temperature of said semiconductor substrate (11) ; and [d] a control section (13) which is interrupting any further heat generation of said active semiconductor element(s) (22) when the temperature detected by said heat-sensitive element (25) exceeds a predetermined value, [e] said heat-sensitive element (25) and said control section (13) being formed on said semiconductor substrate (11) in a control region (13) thereof; characterized in that [f] said heat-sensitive element (25) is located in the control region (13) which is substantially located in the center portion of said semiconductor substrate (11) [f1] and separated from said power region (12) ; [g] said heat-sensitive element (25) is formed on an insulating film (24) which is formed on at least a portion of said control region (13) ; and [h] said control section (13) is formed in the remaining portion of said control region (13) . Semiconductor device according to claim 1, characterized in that said heat-sensitive element (25) is comprised of a semiconductor element having a PN junction made of polycristalline silicon formed on said insulating film (24) , the forward voltage of said PN junction varying as the temperature of said semiconductor substrate (11) changes. Semiconductor device according to claim 1, characterized in that said heat-sensitive element (25) is comprised of a plurality of polycristalline silicon diodes connected in series and each having a PN junction which is made of polycristalline silicon formed on said insulating film (24) . Semiconductor device according to claim 1, characterized in that said heat-sensitive element (25) is comprised of a PN junction made of polycristalline silicon formed on said insulating film (24) , a low-impurity concentration region within the P or N region of said PN junction having an impurity concentration of at least 1 x 10¹⁹ cm⁻³. Semiconductor device according to claim 4, characterized in that said low-impurity concentration region is doped with boron. Semiconductor device according to one of claims 1 to 5, characterized in that said control region (13) comprises a plurality of resistors (217-272) , at least one of which is a polycristalline silicon resistor formed on said insulating film (24) . Semiconductor device according to one of claims 1 to 6, characterized in that said active semiconductor element (22) formed in said power region (12) is a vertical type power MOS transistor. Semiconductor device according to one of claims 1 to 7, characterized in that said control section (13) includes a lateral type MOS transistor (26) which is formed in the surface region of said semiconductor substrate (11) and which is connected to receive a signal from said heat-sensitive element (25) .

Inventors: TSUZUKI, YUKIO, YAMAOKA, MASAMI
Applicants: NIPPONDENSO CO., LTD.
Application year: 1986
Main classification: H01L27
IPC codes: H01L27, H01L23, H01L21, H01L29