ELECTRONIC APPARATUS CONTROL SYSTEMS

Abstract: An electronic apparatus control system includes a control circuit means (1) having a control program ROM for sequential­ ly communicating with a plurality of circuit blocks (30₁ to 30 n ) to be controlled by the control circuit means (1) through a bus line (3) within predetermined intervals. The control circuit means (1) selects and communicates with a specific circuit block (30 j ) in each predetermined interval.

Description: This invention relates to electronic apparatus control systems. Video and audio equipment, such as television (TV) receivers, video tape recorders (VTRs) and tape recorders, with digital control circuits, are becoming more popular. Most such digitally controlled equipment adopts an inner bus system. The inner bus system incorporates a central processing unit (CPU), an inner bus, a read only memory (ROM) and the like. Operation preset data for each circuit is stored in the ROM. In normal operation, the preset data is read out from the ROM by the CPU. The read out data is supplied to a predetermined circuit through the inner bus so as to allow the circuit to perform a predetermined operation. In such a system, each circuit also can be controlled through the CPU by external operation at a keyboard or a remote control unit. The inner bus used in such an inner bus system can use a communication scheme as disclosed in, for example, Japanese Patent Disclosure No. 57-106262. The bus line adopting this scheme is a two-wire bus line having a data line and a clock line. In electronic equipment having the above-mentioned inner bus system, adjustment procedures in manufacture and maintenance can be standardised and simplified. Therefore, the total cost, including the manufacturing cost, is expected to decrease. Figure 1 of the accompanying drawings shows the configuration of a TV receiver using the above-mentioned inner bus system to which the present invention is applicable. The TV receiver shown in figure 1 has a main CPU 1, a memory 2, an inner bus line 3, and so forth. In this arrangement, controllable circuits include an audio processing circuit 4, a video control circuit 5, a video processing circuit 6, a deflection control circuit 7, a phase-locked loop (PLL) circuit 8, and an intermediate frequency circuit 9. When the TV receiver is operative and commands are supplied from a keyboard 11 or a remote control commander 14 to the main CPU 1 through a subsidiary (sub) CPU 12 for key sensing, the main CPU 1 controls the circuits 4 to 9 in response to the commands. Upon such control operation, tuning, volume adjustment, picture adjustment or the like is performed and the adjustment result is displayed on a display section 20. The main CPU 1 constantly checks the operational states of the circuits 4 to 9 so as to allow them to operate in a predetermined state. The arrangement illustrated in Figure 1 also comprises a remote control signal receiving circuit 13, deflection coils 15 and 16, an audio output amplifier 17, a video output amplifier 18, and a cathode-ray tube 19. In the operation of controlling the TV receiver or other video equipment, when control signals are supplied from the main CPU 1 to the respective controllable circuits 4 to 9, or when the circuits 4 to 9 transmit state signals to the main CPU 1, data representing the control or state contents is transmitted together with clock signals. When the clock frequency is increased, radio interference due to noise from the clock pulses appears on the screen of the cathode-ray tube 19. In order to avoid this, data transmission is performed only during a vertical blanking interval (hereinafter referred to as a "VBLK interval") of a video or television signal. The inner bus system as described above is subject to the following problem. The VBLK interval for data transmission has a time interval of 1.17 to 1.33 milliseconds. When data is transmitted in this interval using clock signals having a frequency of 100 kHz, 117 bits of data can be transmitted during one VBLK interval. Therefore, when 1 byte of data is transmitted together with a single acknowledgement bit, 13 bytes (117/9) of data can be transmitted. In this manner, the amount of data which can be transmitted during one VBLK interval is limited and, accordingly, the number of communications which can be performed between the main CPU and the controllable circuits during one VBLK interval also is limited. When waiting time and the like is considered, in some cases the main CPU may not be able to check the operational states of all of the controllable circuits within a single VBLK interval. In such a case, the main CPU checks such circuits in the next VBLK interval. This results in a long response time. Such a long response time is undesirable in tuning, picture adjustment or the like by means of a keyboard or remote control commander. According to the invention there is provided an electronic apparatus control system comprising: control circuit means provided with a control program ROM, circuit blocks to be controlled by the control circuit means, and bus lines connected between the control circuit means and the circuit blocks, the control circuit means being operative to communicate data sequentially with the circuit blocks during predetermined intervals, characterised in that the control circuit means is operative always to select a predetermined one or more of the circuit blocks for communication immediately after the start of each said predetermined interval or each p th said predetermined interval, where p is a predetermined integer greater than or equal to two, after which the control circuit means is operative to communicate data sequentially with the circuit blocks in accordance with a predetermined sequence of addresses of the respective circuit blocks, and is responsive to said predetermined address sequence not having ended at the end of one of the predetermined intervals to communicate with the circuit blocks during the following predetermined interval commencing with the block having the next address in the sequence. If the electronic apparatus control is an apparatus for handling a television signal or signals, communication between the control circuit means and the controllable circuits or circuit blocks can be performed during vertical blanking intervals of the television signal. The control circuit means and the controllable circuits or circuit blocks may be connected through a two-wire bus line. A control system embodying the present invention may be used to control electronic apparatus which is a television receiver having an external input means for channel selection and operational control. The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a television receiver with an inner bus system to which the present invention is applicable; Figure 2 is a block diagram for explaining a mode of operation of a system embodying the present invention; Figures 3A to 3C are timing charts for explaining signal transmission in a two-wire bus line system to which the present invention is applied; Figures 4A and 4B are timing charts for explaining the mode of operation of an embodiment of the present invention; and Figure 5 is a flow chart for explaining the mode of operation of the embodiment of the present invention. Referring to Figure 2, a control circuit 1 represented by a main CPU is connected to n controllable circuits 30₁ to 30 n through a two-wire bus line 3. The bus line 3 consists of or includes a clock line 3₁ and a data line 3₂. In the two-wire bus line as shown in Figure 2, clock signals and data are transmitted through the clock line 3₁ and the data line 3₂, respectively, at timings as shown in Figures 3A to 3C. Each low level interval in Figure 3A is a VBLK interval. In this interval, clock signals are transmitted onto the clock line 3₁ as shown in Figure 3B and data is transmitted onto the data line 3₂ as shown in Figure 3C. In this embodiment, control of a specific controllable circuit 30 j is performed at first when each VBLK interval starts. For this purpose, as shown in Figure 4B, in each VBLK interval (Figure 4A) an interval j for allowing communication with the circuit 30 j is provided. Communication intervals 1 to n for other circuits 30₁ to 30 n excluding the circuit 30 j are accommodated within two VBLK intervals if the communication cycle cannot be terminated within a single VBLK interval. The intervals 1 to n can be accommodated within three or more VBLK intervals, as needed. A specific controllable circuit which is controlled at first in each VBLK interval need not be a single circuit 30 j , but can be two or more circuits. In that case, a corresponding number of communication intervals is included in each VBLK interval. In addition, communication with a specific controllable circuit need not be performed within each VBLK interval, but can be performed at every other VBLK interval or at every predetermined number of VBLK intervals. A circuit which requires a particularly fast response is selected as the specific controllable circuit 30 j . In the case of the television receiver shown in Figure 1, a best effect is obtained if control is performed with priority in response to requests from the keyboard 11, the commander 14, and the like. When a plurality of specific controllable circuits is selected in the TV receiver shown in Figure 1, then, for example, the PLL circuit 8, the IF circuit 9, the video control circuit 5, the video processing circuit 6, the keyboard 11, and a character display control circuit (not shown) can be selected. Figure 5 is a flow chart of communication between the control circuit and the controllable circuits. In a step 1, a check is made to determine if a VBLK interval has been reached. If the answer to the check made in the step 1 is YES, communication with the specific circuit 30 j is performed in a step 2. After communication with the circuit 30 j , an address parameter X is initialised to zero in a step 3, and communication with the controllable circuit 30 corresponding to the address X is performed in a step 4. After communication is terminated, the address parameter X is increased by one in a step 5, and a check is made in a step 6 to determine if the address parameter X has reached a predetermined value K. If it is determined that the address parameter X has reached the predetermined value K, this means the end of the communication cycle. Therefore, when it is determined that the address parameter X has reached the predetermined value K, a check is made in a step 10 to determine if there is a time margin for further communication. If there is no time margin, the operational flow returns to the step 1 and the next VBLK interval is awaited. If there is a time margin, the operational flow returns to the step 3. In the step 3, the address parameter X is again initialised, and the operational flow advances to the step 4. If it is determined in the step 6 that the address parameter X has not reached the predetermined value K, a check is made in a step 7 to determine if there is a time margin. If the answer to the check performed in the step 7 is YES, the operational flow returns to the step 4. If the answer to the check performed in the step 7 is NO, the next VBLK interval is awaited (step 8). When the next VBLK interval is reached, communication with the specific controllable circuit 30 j is performed (step 9) and the operational flow then returns to the step 4. In summary, according to the above-described embodiment of the present invention, in video equipment such as TV receivers, VTRs or the like with an inner bus line system, a circuit which requires a particularly fast response is controlled or checked with priority over other circuits. Therefore, efficient communication can be achieved even if communication is performed only during vertical blanking intervals.

Claims: An electronic apparatus control system comprising: control circuit means (1) provided with a control program ROM, circuit blocks (30₁ to 30 n ) to be controlled by the control circuit means (1), and bus lines (3) connected between the control circuit means (1) and the circuit blocks (30₁ to 30 n ), the control circuit means (1) being operative to communicate data sequentially with the circuit blocks (30₁ to 30 n ) during predetermined intervals, characterised in that the control circuit means (1) is operative always to select a predetermined one or more of the circuit blocks (e.g. 30 j) for communication immediately after the start of each said predetermined interval or each p th said predetermined interval, where p is a predetermined integer greater than or equal to two, after which the control circuit means (1) is operative to communicate data sequentially with the circuit blocks (30₁ to 30 n ) in accordance with a predetermined sequence of addresses of the respective circuit blocks, and is responsive to said predetermined address sequence not having ended at the end of one of the predetermined intervals to communicate with the circuit blocks during the following predetermined interval commencing with the block having the next address in the sequence. An electronic apparatus control system according to claim 1, for controlling electronic apparatus that can handle a television signal, wherein said predetermined intervals are vertical blanking intervals of the television signal. An electronic apparatus control system according to claim 2, wherein the bus lines (3) include a clock line (3₁) and a data line (3₂). An electronic apparatus control system according to claim 3, which is operative to control electronic apparatus which is a television receiver and is equipped with external input means (11,14) for channel selection and so on.

Inventors: FUJITA, KOSUKE C/O SONY CORPORATION, MOGI, TAKAO C/O SONY CORPORATION, SUEMATSU, MASAYUKI C/O SONY CORPORATION
Applicants: SONY CORPORATION
Application year: 1986
Main classification: G06F13
IPC codes: H04L7, H04N7, H04N5