Data-processing device

Abstract: A data-processing device comprises a clock generator for generating pulse signals 1 and 2, an ALU (30) capable of executing various arithmetic-logic operations in syn­ chronism with the pulse signals 1 and 2, and a control unit for generating a control signal (S10) which causes the ALU (30) to execute an arithmetic-logic operation according to an instruction. This data-processing device further includes a transfer switch (54) for causing the ALU (30) to execute an arithmetic-logic operation, which is for generating output data equal to input data, during the idle cycle.

Description: This invention relates to a data-processing device, and, more particularly, to a data-processing device capable of accepting, for example, AIM (AND Immediate Data). In general, an ALU in a CPU performs the following operations during the execution of various instructions: an arithmetic-logic operation designated by each instruction; an operation for the changing of flags; and an operation for addressing. During the cycles in which no operations are executed, viz. during the idle cycles, meaningless or invalid data exists in the ALU. In developing CPUs, one of the key problems is how to realize instructions which can be executed with the minimum number of execution cycles and the highest efficiency, using the limited hardware of internal buses and registers. As matters stand, the effective execution of instructions cannot easily be realized without additional hardware such as temporary registers and internal busses. A method for executing the index mode of AIM (AND Immediate Data) will now be described. This instruction makes a logical product of the contents of a RAM and immediate data, and stores the logical product in the RAM. More specifically, the AIM instruction is a composite instruction made up of the following three functions: (1) storing the RAM data in an accumulator; (2) making the logical product of the data in the accumulator and the immediate data, and storing the logical product in the accumulator; and (3) storing the accumulator data in the RAM. Ordinarily, the instruction of the index mode has a format of two bytes, in which the first byte is for an operation code and the second byte is for index offset data. The AIM instruction is formed of three bytes, in which one additional byte is for the operand of the immediate data. To execute this instruction at high speed, numerous registers are required. With hardware having a limited number of registers, however, it is very difficult to speed up the execution of the instruction while maintaining a satisfactory level of the practicability of the data-processing device. Prior art document "Journal of Digital Systems", Vol. 5, No. 3, 1981, pages 203-250, discloses a data processing device comprising clock generating means in the form of a data processor, where an operating clock rate is indicated for driving processor slices, executing means capable of executing various instructions and having an arithmetic-logic unit (ALU) for performing arithmetic and logic operations, and control means for controlling the executing means. During a specific instruction the control means is capable of causing the arithmetic unit to produce an output data equal to the input data as a result of an arithmetic-logic operation corresponding to a "dummy" OR operation in order to accomplish a data transfer, through the ALU, from one processor register to another one. Further, prior art document "Computer Design", Vol. 23, No. 3, 03/84, pages 213-223, describes a microprogramming and bit-slice architecture wherein in an operation cycle, a control bit is assigned to enable the content of a memory address register (MAR) to an address bus and read a next instruction. In a decode cycle a CPU, otherwise idle, is used to increment an old program counter and load MAR in readiness for next instruction fetch. Therefore, the fetch and execution parts of a macroinstruction are overlapped, resulting in increased speed. It is an object of the present invention to provide a data-processing device capable of effectively executing instructions, without the need to increase the number of registers. To solve this object the present invention provides a data processing device as specified in claim 1. In the data processing device according to the present invention, the arithmetic-logic unit can be used as a data register during the idle cycles. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a block diagram of a data-processing device of an embodiment according to the present invention; Figs. 2A and 2B show instruction-word formats of the instructions of the index mode executed by the data-processing device of Fig. 1; Fig. 3 shows, in block form, the detail of a portion of the execution circuit shown in Fig. 1; and Figs. 4 and 5 show a sequence of controls in which the control unit of Fig. 1 controls logic components according to the AIM instruction. A data-processing device according to an embodiment of the present invention will now be described, with reference to Figs. 1 to 5. Fig. 1 schematically illustrates a circuit of this data-processing device. As is shown in Fig. 1, this device includes such logic components as clock generator 10, control unit 12, execution circuit 14, memory unit 16, instruction register 18, and instruction decoder 20. In this embodiment these logic components are packaged into one LSI chip. Pulse signals 1 and 2 of the same frequency are generated as a clock signal, by clock generator 10. Pulse signals 1 and 2 are set to have a specific phase difference, and the interval between two successive leading edges of pulse signal 1 is used for a machine cycle. Each machine cycle corresponds to the period of time required for completing the execution of one arithmetic-logic operation, which is performed by execution circuit 14. Pulse signals 1 and 2 are supplied to control unit 12, execution circuit 14, memory unit 16, instruction register 18, and instruction decoder 20. In order to control execution circuit 14, memory unit 16, and instruction register 18, control unit 12 is provided with signal generators for generating various types of control pulses. Pulse signals 1 and 2 are used as a reference when each control pulse is generated. Each control pulse is generated in a specific sequence, by control unit 12. Programmed in control unit 12, are several sequences which correspond to the type of instructions accepted by this data-processing device. Any of these sequences can be selected by the output signal of instruction decoder 20. Control unit 12 also has a reset terminal for receiving a reset signal from an external source. When the control unit is supplied with this reset signal, it conducts a procedural control process, to begin data processing. Under the control of unit 12, execution circuit 14 accesses memory 16 and reads out the operation code of the initial instruction therefrom. The address signal is fed from execution circuit 14 to memory unit 16 via 16-bit address bus AB. The output data of memory unit 16 is supplied to 8-bit data bus DB. The readout operation code is latched into instruction register 18 and decoded by instruction decoder 20. Control unit 12 causes execution circuit 14 to execute the processing according to the decoded signal. The logic components other than control unit 12 will now be described in detail. Memory unit 16 is formed of read-only memories (ROM) and random-access memories (RAM), or only random-access memories (RAM), and has an address space of, for example, 64K bytes, for storing the execution program and data. The execution program includes various instructions required for the specific data processing to be performed. These instructions are stored in successive memory locations of memory unit 16. Each instruction has instruction words whose number corresponds to a specific addressing mode, such as an extend mode, a direct mode, or an index mode. The index mode will now be described. The instruction, e.g. ADDA instruction, denoting the ordinary index mode, which is used for processing the data in the accumulator (which will be described later), is described in a 2-byte format, as is shown in Fig. 2A. As is shown, the operation code and the index offset data are assigned to the first and second bytes, respectively. The instruction, for example, an AIM instruction, denoting the special index mode, which is used for processing immediate data, is described in a 3-byte instruction word format. The operation code, index offset data, and immediate data are assigned to first, second, and third bytes, respectively. Any of the memory locations of memory unit 16 is selected by the related address signal generated by execution circuit 14. Read and write operations of data for memory unit 16 are controlled by the R/ W signal from control unit 12. Data bus DB transfers data bidirectionally between execution circuit 14 and memory unit 16. Instruction register 18 is connected to data bus DB, for latching the specific operation code of each instruction, which is read out from memory unit 16, onto data bus DB. The latching operation of instruction register 18 is controlled by a control pulse from control unit 12. Instruction decoder 20 decodes the data (i.e., operation code) latched by instruction register 18, and supplies it to control unit 12. All the lines in buses DB, BI, BL, BH, BX, and BY (to be described later) are periodically precharged to a predetermined potential, for example 5V, by a precharging circuit (not shown). The precharging of buses BI, BL, BH, BX, and BY is performed in response to each pulse signal 2, and the precharging of bus DB is performed in response to each pulse signal 1. Signal transfer is performed by selectively discharging the lines in each bus. Address bus AB is not involved in the precharge operation and is capable of transferring data for substantially the entire period of each machine cycle. Fig. 3 shows a portion of execution circuit 14 in detail. Execution circuit 14 comprises ALU 30, accumulator register 32, PH and PL registers 34A and 34B, incrementor/decrementor registers 36A and 36B, temporary registers 38 and 40, and XH and XL registers 42A and 42B. ALU 30 performs the arithmetic-logic operation of 8-bit data. Registers 32, 34A, 34B, 38, 40, 42A, and 42B can each store 8-bit data. PH and PL registers 34A and 34B form 16-bit program counter 34, XH and XL registers 42A and 42B form 16-bit index register 42, and incrementor/decrementor registers 36A and 36B form address counter 36. Execution circuit 14 further includes high-order address bus BH, low-order address bus BL, intermediate bus BI, X-input data bus BX, and Y-input data bus BY. The high-order portion AH of address bus AB is connected to address bus BH, and the low-order portion AL is connected to address bus BL, via selector 56 and intermediate bus BI. Selector 56 is controlled by control signal S16 from control unit 12, data bus BX is connected to the X-input port of ALU 30, and data bus BY is connected to the Y-input port of ALU 30. The output port of ALU 30 is connected to Y-input data bus BY and intermediate data bus BI, via selector 44. Selector 44 supplies the output data of ALU 30 to either bus BY or bus BI, under control of control signal S1 from control unit 12. Data bus DB is connected to intermediate bus BI and Y-input data bus BY, via selector 46. Selector 46 supplies the data from data bus DB to either bus BI or bus BY, under control of control signal S2 from control unit 12. Y-input data bus BY is connected to data bus DB, via transfer switch 48. Transfer switch 48 transfers data from bus BY to bus DB, under control of control signal S3 from control unit 12. Intermediate bus BI is connected to X-input data bus BX, via transfer switch 50. Transfer switch 50 bidirectionally transfers data between buses BI and BX, under control of control signal S4 from control unit 12. Low-order address bus BL is connected to X-input data bus BX, via transfer switch 52. Transfer switch 52 bidirectionally transfers data between buses BL and BX, under control of control signal S5 from control unit 12. Accumulator register 32 is connected to X-input data bus BX, and Y-input data bus BY. The data input/ output operation of register 32 is controlled by control signal S6. PH register 34A is connected to high-order address bus BH and the output port of I/D register 36A. PL register 34B is connected to low-order address bus BL and the output port of I/D register 36B. The data input/ output operations of registers 34A and 34B are controlled by control signals S7 and S8, respectively. I/D registers 36A and 36B are connected to high-order and low-order address buses BH and BL, and intermediate bus RI respectively. The data input/output operations of I/D register 36A and 36B are controlled by respective control signals S9 and S10. Temporary register 38 is connected to high-order address bus BH. The data input/ output operation of register 38 are controlled by control signal S11. Temporary register 40 is connected to intermediate bus BI and Y-input data bus BY. The data input/output operations of register 40 are controlled by control signal S12. XH register 42A is connected to high-order address bus BH, and XL register 42B is connected to X-input data bus BX. The data input/output operations of registers 42A and 42B are controlled by control signals S13 and S14, respectively. Control signals S6 to S14 are generated by control unit 12. ALU 30 receives control signal S17 from control unit 12 and also receives pulse signals 1 and 2 from the clock generator. Control signal S17 designates the type of arithmetic-logic operation to be executed by ALU 30. ALU 30 simultaneously latches the data on X-input and Y-input data buses BX and BY, in response to pulse signal 1, and executes the designated operation. ALU 30 also supplies, to selector 44, the data resulting from the operation, in response to pulse signal 2. Accumulator register 32 is used for storing data in the execution of, for example, an instruction of the ordinary index mode. In this case, the data in accumulator register 32 is supplied to the X-input of ALU 30, and is then processed together with the data supplied, from memory unit 16, to the Y-input of ALU 30. Program counter 34 is used for storing the data representing one memory address in memory unit 16. PH register 34A stores the high-order byte of of this address, while PL register 34B stores the low-order byte thereof. I/D registers 36A and 36B of address counter 36 are respectively used for pre-storing the one-byte data supplied to PH register 34A and PL register 34B. Before storing this data, the aforementioned registers perform one of the following operations on the data supplied from respective bus: (a) increment the data by "1"; (b) decrement the data by "1"; or (c) perform no transformation of the data. Control signals S9 and S10 control the above three operation functions of I/D registers 36A and 36B, in addition to the input/output of the data. Temporary registers 38 and 40 are general registers for temporarily storing data. Specifically, temporary register 38 is used for temporarily storing the contents of XH register 42A, for example. Temporary register 40 is used for temporarily storing, for example, the immediate data. Index register 42 is used for addressing the 256-bytes data area of memory unit 16. For example, reference data representing the initial address of the data area is preset in index register 42. This reference data is cooperated with 8-bit index offset data, in the execution of an index mode instruction. More specifically, the content of XL register 42B is added to the index offset data, by ALU 30, in order to obtain an address of RAM data. This data-processing device further comprises transfer switch 54 for supplying data "00" (hexadecimal number) to the X-input of ALU 30. The conduction of transfer switch 54 is controlled by control signal S15 supplied from control unit 12. Transfer switch 54 is connected between X-input data bus BX and the ground terminal which is set to 0V potential, for example. When transfer switch 54 is turned on, the transfer lines of bus BX are discharged to have a potential of 0V. By means of this discharge, the X-input data of ALU 30 is forcibly set to "00". In this embodiment, preset data are supplied from the memory unit 16 to the corresponding registers during the execution of the program instruction. However, the data may also be supplied, via any one of the buses from an external source. In this case, control unit 12 is externally controlled, via an external control terminal. One operation of this data-processing device will now be described, with reference to Figs. 4 and 5. In this operation, the control unit controls the necessary logic components in a specific sequence corresponding to the AIM instruction. Fig. 4 shows the operation for every machine cycle. Fig. 5 shows the control signals generated during the corresponding machine cycle. It is assumed that program counter 34 has stored the address data of a first instruction word (or the operation code) of the AIM instruction which will be read out from memory unit 16, in the coming cycle 1. Cycle 1 The high-order byte and the low-order byte of this address data are supplied to memory unit 16, via buses BH, AH, and buses BL, AL and selector 56, under the control of signals S7, S8, and S16, respectively. At this time, the operation code of the AMI instruction is read out from memory unit 16 to instruction register 18, is decoded by instruction decoder 20, and is supplied to control unit 12. In response to this decoded signal, control unit 12 begins the control of execution circuit 14 based on that signal. The high-order byte of the address data is supplied, under the control of signal S9, to I/D register 36A, via address bus BH, while the low-order byte is supplied, under the control of signal S10, to I/D register 36B, via address bus BL. At this time, the content of address counter 36 is incremented by "1", under the control of signals S9 and S10. When the content of register 36B is "FF" (hexadecimal), this increment operation causes the content of register 36B to change to "00" and to add "1" to the content of register 36A. Cycle 2 The data in I/D registers 36A and 36B are supplied, under the control of signals S9, S10, and S16, to memory unit 16, as address data for the second instruction word (or index offset data), via address buses BH, AH, and address buses BL, AL and selector 56, respectively. Memory unit 16 reads out the index offset data from the designated address location, onto data bus DB. On the other hand, I/D registers 36A and 36B respectively latch the data on buses BH and BL, under the control of signals S9 and S10. The latched data of address counter 36 is incremented by "1", under the control of signals S9 and S10. Cycle 3 The data in I/D registers 36A and 36B are supplied, under the control of signals S9, S10 and S16, to memory unit 16, as the address data for the third instruction word (or the immediate data) of the AIM instruction, via address buses BH and AH, address buses BL and AL, and selector 56, respectively. At this time, transfer switch 54 is turned on under the control of signal S15, and the data "00" (hexadecimal number) is supplied to X-input data bus BX. On the other hand, the index offset data readout in cycle 2 is supplied from data bus DB to Y-input data bus BY, via selector 46, under the control of signal S2. ALU 30 adds together the index offset data supplied to the Y-input port, and the data "00" supplied to the X-input port, under the control of signal S17. Then, the immediate data is read out from the designated address location of memory unit 16, onto data bus DB. At the same time, I/D registers 36A and 36B respectively latch the data on buses BH and BL, under the control of signals S9 and S10. The content of address counter 36 is then incremented by "1", under the control of signals S9 and S10. Cycle 4 The contents of I/D registers 36A and 36B are loaded, under the control of signals S9 and S10, into PH register 34A and PL register 34B, respectively, as the address data for fetching the next instruction word of the AIM instruction. The address data is kept stored in program counter 34 until the start of the fetch cycle of the next instruction word of the AIM instruction. On the other hand, the immediate data on data bus DB is stored, under the control of signals S2 and S12, in temporary register 40, via selector 46 and intermediate bus BI. In parallel with these operations, the content of XL register 42B is supplied to X-input port of ALU 30 via X-input data bus BX, under the control of signal S14. The data representing the result of addition is fed back to the Y-input port of ALU 30 via selector 44 and Y-input data bus BY, under the control of signal S1. ALU 30 adds the content of XL register 42B supplied to X-input port and the data representing the result of addition, supplied to Y-input port (i.e. index offset data), under the control of signals S17. The content of register 42B is further supplied to I/D register 36B via X-input data bus BX, transfer switch 52, and address bus BL, and is stored in I/D register 36B, under the control of signals S14, S5, and S10. The content of XH register 42A is supplied to temporary register 38 and I/D register 36A, via address bus BH, and is stored in respective registers, under the control of signals S13 and S11. Then, the content of I/D register 36A is incremented by "1". Cycle 5 The data representing the result of the arithmetic-logic operation performed in cycle 4 is supplied, as the low-order address data of the RAM data, from ALU 30 to memory unit 16, via selector 44, intermediate bus BI, selector 56, and address bus AL, under the control of signals S1 and S16. If this result data contains a carry, the content of I/D register 36A is supplied to memory unit 16 via address bus BH and address bus AH, as the high-order address data of the RAM, under the control of signals S9. On the other hand, if it has no carry, the content of temporary register 38 is supplied to memory unit 16, via address buses BH and AH, under the control of signal S11. Memory unit 16 reads out data from the address location designated by this RAM data address, and applies it to data bus DB. The high-order byte of the RAM data address is supplied, under the control of signal S9, to I/D register 36A via address bus BH, and is stored in I/D register 36A, while the low-order byte is supplied, under the control of signal S10, to I/D register 36B, via intermediated bus BI, and is stored in register 36B. Cycle 6 The contents of I/D registers 36A and 36B, i.e. the address of RAM data, are supplied to address buses BH and BL, under the control of signals S9 and S10. The data on data bus DB is supplied to the X-input port of ALU 30, via selector 46, intermediate bus BI, transfer switch 50, and X-input data bus BX, under the control of signals S2 and S4. The content of temporary register 40, i.e. immediate data, is supplied to the Y-input port of ALU 30 via Y-input data bus BY, under the control of signal S12. ALU 30 performs an AND operation with respect to the RAM data and immediate data, under the control of signal S7. The data on address buses BH and BL is latched by I/D registers 36A and 36B, as address data for RAM data, under the control of signals S9 and S10. Cycle 7 The contents of I/D registers 36A and 36B are supplied, under the control of signals S10, S16 and S9, to memory unit 16, via address buses BH, AH and address buses BL, AL and selector 56, respectively. The result of the operation performed in cycle 6 is supplied, under the control of signals S10, S1, and S3, from ALU 30 to memory unit 16, via selector 44, Y-input data bus BY, transfer switch 48, and data bus DB. Memory unit 16 stores this data in the address location designated by the content of address counter 36. The execution of the AIM instruction ends at this point. Cycle 8 The contents of PH and PL registers 34A and 34B of program counter 34, are supplied, under the control of signals S7 and S8, to address buses BH and BL, respectively, as the address data for the first instruction word of the next instruction. In this embodiment, ALU 30 performs an addition in cycle 3. In this addition, the value of index offset data is not changed. In other words, ALU 30 functions as a register for storing index offset data, in cycle 3. This data-processing device can, therefore, execute the AIM instruction in seven machine cycles. Supposing that ALU 30 does not perform addition of "00" (hexadecimal) and the index offset data, and that the number of registers is limited to the number in the embodiment of the present invention, then the execution of the AIM instruction requires twelve machine cycles. The reason for this is that the index offset data has to be temporarily stored in memory unit 16, in order to prevent the data in the accumulator register from being erased. The addressing of memory unit 16 undesirably requires more machine cycles than in this present invention. If the instruction-word format of the AIM instruction is arranged in the order of operation code, immediate code, and index offset data, the AIM instruction can be executed in the same number of cycles as in this embodiment. However, the instruction of the ordinary index mode is written in the instruction-word format, in the order of operation code, and index offset data. The format thus arranged forms an irregular format. This is not practical, since coding errors are more likely to occur when a programmer does manual assembling. As has been described above, according to the present invention, the AIM instruction can be executed without the need to increase the number of registers. While in the embodiment, memory unit 16 is formed in the same chip, together with the other logic components, it may be formed in a separate chip, with the wiring being similar to the above instance. In the embodiment described above, ALU 30 is controlled to perform an addition when the data of "00" (hexadecimal) is supplied to the X-input port of ALU 30 by means of transfer switch 54. However, ALU 30 can be controlled to perform a subtraction or "OR" operation. In addition, transfer switch 54 can be connected between data bus BX and the power source terminal which is set to 5 V potential, in order to supply the data of "FF" (hexadecimal) to the X-input port of ALU 30. When the data of "FF" is supplied by means of transfer switch 54, ALU 30 is controlled to perform an "AND" operation. In the embodiment, the data of "00" (hexadecimal) and the index offset data are added together in cycle 3. However, it is possible to add the index offset data to the content of XL register 52B in cycle 3, and add the result to the data of "00" in cycle 4.

Claims: A data processing device comprising: memory means (16) for storing data and a plurality of various instructions, at least one of said instructions being a specific instruction having an operation code word and at least two additional instruction words being stored in succession in said memory means (16); bus means (AB, DB) for data transfer; execution means (14), connected via said bus means (AB, DB) to said memory means (16), for performing a sequence of operations to execute an instruction fetched from said memory means (16), said executing means (14) including arithmetic-logic means (30) for performing arithmetic-logic operations and temporary registers (38, 40) for storing data, control means (12, 18, 20), connected via said bus means (AB, DB) to said memory means (16) and said execution means (14) for controlling the operation sequence of said execution means (14) according to the fetched instruction; and clock generation means (10), connected to said execution means (14) and said control means (12, 18, 20), for generating a clock signal defining machine cycles during each of which an operation of said execution means (14) is performed, wherein during an idle cycle, meaningless or invalid data normally exists in said arithmetic-logic means (30), characterized in that when executing said specific instruction, said control means (12, 18, 20) fetches one after another said operation code and said at least two instruction words of said specific instruction from said memory means (16), and controls said arithmetic-logic means (30) to produce output data equal to the input data fetched from memory means (16) during the previous machine cycle, as a result of an arithmetic-logic operation performed during an idle cycle in which one of said instruction words of said specific instruction is fetched, whereby said arithmetic-logic means (30) serves as a register for said input data during that idle cycle. A data processing device according to claim 1, characterized in that said control means (12, 18, 20) includes: an instruction register (18) for storing the operation code of the fetched instruction; an instruction decoder (20) for decoding the operation code stored in said instruction register (18) to detect the specific instruction; and a control circuit (12) for controlling said arithmetic-logic means (30) to produce the output data equal to the input data as a dummy operation during the idle cycle, upon detection of the specific instruction. A data processing device according to claim 2, characterized in that said arithmetic-logic means (30) is controlled to effect the dummy operation on the second word during the idle cycle and an arithmetic-logic operation on the third word during a machine-cycle subsequent to said idle cycle. A data processing device according to claim 3, characterized in that said at least two additional instruction words of said specific instruction are an index offset data, and immediate data, respectively. A data processing device according to claim 3 or 4, characterized in that said control circuit (12) includes a data supply section (54) for supplying predetermined data, and in that said arithmetic-logic means (30) includes first and second inputs which receives the second word and predetermined data during said idle cycle. A data processing device according to claim 5, characterized in that said predetermined data is a plurality of Boolean zeroes, and in that said dummy operation is one of addition, subtraction, and "OR" operations. A data processing device according to claim 5, characterized in that said predetermined data is a plurality of Boolean ones, and in that said dummy operation is an "AND" operation.

Inventors: KYUMA YURIKO PATENT DIVISION, KYUMA, YURIKO PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: G06F7
IPC codes: G06F9, G06F7