CURRENT OUTPUT CIRCUIT

Abstract: A bipolar transistor circuit is disclosed, which receives input voltage signals (125,126) and outputs a current I₀ of a polarity in accordance with the input signals and of a predetermined amplitude. This circuit includes a first current source (Q₄, Q₅) producing a first reference current, an output terminal, bipolar switching transistors (Q₉-Q₁₂) coupled between the first current source and the output terminal (124) and controlled by the input voltage signals to supply to the output terminal an output current of a first polarity which has an amplitude of the first reference current minus a base current of the switching transistor or integer times of that amplitude, a current producing circuit (Q₁₃, Q₁₄) producing a current that is substantially equal to the base current of the switching transistor, and a second current source (Q₈) connected to the output terminal and producing a second reference current of a second polarity which has an amplitude of the first reference current minus the amplitude of the current produced by the current producing circuit. The present invention thus provides a well-balanced output current which is suitable to charge and discharge a load capacitor with the same amount of charges.

Description: BACKGROUND OF THE INVENTION The present invention relates to a current output circuit according to the preamble parts of claims 1 and 2. Such a circuit is employed as a charging/discharging control circuit of a load capacitor, for example. More specifically, when input signals take a first combination of voltage levels, the circuit outputs a current of one polarity which, for example, charges the load capacitor, and when the input signals take a second combination, the circuit outputs a current of the opposite polarity having the same amplitude which, for example, discharges the load capacitor. According to prior art, such a circuit includes first, second and third current sources and first and second switches. The first current source is connected between one of power terminals and an output terminal to which a load is connected. The first switch and the second current source are connected in series between the output terminal and the other power terminal, and the second switch and the third current source are also connected in series therebetween. Each of the first to third current sources produces a reference current of the same value, and first and second switches are controlled by input signals, respectively. When the input signals take the first combination of voltage levels, the first and second switches are turned OFF. Accordingly, the current produced by the first current source is supplied to the output terminal as a positive current. When the input signals take the second combination of voltage levels, both of the first and second switches are turned ON. At this time, the current of the first current source is counteracted by that of the second current source, so that the current of the third current source is supplied to the output terminal as a negative current. When the input signals take the third combination of levels, only one of the first and second switches is turned ON. The current of the first current source is counteracted by the current of second or third current source and the output terminal is supplied with no current. For a high speed operation, each of the switches is favorably composed of a bipolar transistor. The bipolar transistor requires a base current to take a conductive state, and hence its collector and emitter currents are different from each other. For this reason, the current of the first current source is not counteracted completely. Assuming that the value of the current of each current source is I and the value of the base current is I B , the positive output current has an amplitude of I and the negative output current has an amplitude of (I-2 IB ). When only one of the first and second switches is turned ON, the output terminal is supplied with a small current having an amplitude of I B . Thus, the prior art circuit has unbalanced output currents of opposite polarities. From "Bipolar and MOS analog integrated circuit design" by Alan B. Grebene, John Wiley & Sons, New York, 1984, pp. 170, 171, 174-177 it is known to connect base and collector of an imput transistor to each other via the base-emitter part of an other transistor to make the collector currents of input and output transistors of a current mirror equal to each other. A current output circuit according to the preamble parts of claims 1 and 2 is disclosed in JP-A-60-090 424 in patents abstracts of Japan, volume 9, No. 214 (E 345) 1963, September 26, 1985. In this device the current from a current mirror of current force type is made equal to current from a current mirror of current sink type. However, the problem is not mentioned that the current from a switching transistor is different from the current of the current mirror of current sink type due to the base current of the transistor. "IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-16, No. 6, December 1981, pp. 639-647 " is related to the problem to make the collector and emitter currents of a first transistor equal to each other. For this purpose, the base of a further transistor is connected to the emitter of the first transistor to add a base current to the emitter current of the first transistor. Therefore, a possible combination of this document with the above mentioned document requires two additional transistors and two current sources. It is therefore an object of the invention to provide a current output circuit which has well-balanced output currents and in which affection of the base current is avoided. This object is achieved by current output circuits having the features mentioned in claims 1 or 2; the dependent claims are related to further developments of the invention. According to the invention the output current of the current mirror circuit is made equal to each of the collector currents of the first transistors. For this purpose, a control node is provided in the current mirror circuit and the base current of the second transistor is supplied to the control node to allow the current mirror circuit to produce the output current that is equal to the collector current of the first transistor. Therefore, according to the present invention only one transistor for compensation is required so that the circuit construction is simplified. When all the switching means is made OFF not to provide any current path between the output terminal and the first current producing means, the output terminal outputs a current of one polarity from the subtracting means. The output current has an amplitude of the first amplitude minus the second amplitude. When any one of the switching means is made ON to provide a single current path of the first current to the output terminal, a current having an amplitude of the first amplitude minus the second amplitude is to flow. Since this amplitude is equal to that of the current from the subtracting means, the output terminal is supplied with substantially no current. When two of the switching means is switched ON to provide two current paths of the first current, the output terminal outputs a current of the opposite polarity and having the same amplitude (of the first amplitude minus the second amplitude) as that of the output current of the one polarity in the first case. If three or more of the first current-producing means and the switching means are respectively provided, the output current of the opposite polarity can have an amplitude of twice or more integer times of that of the output current of the one polarity by making three or more switching means ON. Thus, the circuit according to the present invention has well-balanced output current characteristics. Moreover, it is possible to make the output current zero. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a block diagram showing an embodiment of the prevent invention; Fig. 2 is a circuit diagram showing a phase locked oscillator employing as a charge pump circuit a circuit according to another embodiment of the present invention; Figs. 3A to 3C are timing charts for explaining an operation of the circuit shown in Fig. 2; and Fig. 4 is a circuit diagram showing still another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS With reference to Fig. 1, an embodiment of the present invention is shown in a block form. the circuit according to this embodiment includes an output terminal 1 connected to a load circuit 8, two switch circuits 2 and 3, two current mirror circuits 4 and 5, a reference current generator 6, a compensation current generator 7, and input terminals 9. The reference current source 6 generating a reference current I. The current mirror circuit 4 responds to the reference current I supplied to its input end 4-1 and produces at its four output ends 4-2 to 4-5 output currents having the substantially same value. In this embodiment, the output currents at the output ends 4-2 to 4-5 are substantially equal to the reference current I, and therefore denoted by "I", respectively. If desired, the output currents may be different from the reference current I. The first switch circuit 2 is connected between the output terminal 1 and the first output end 4-2, and the second switch circuit 3 is connected between the output terminal 1 and the second output end 4-3. Each of the switch circuits 2 and 3 has a control terminal C connected to each input terminal 9, and is turned ON when such an input voltage is applied to the input terminal 9 that makes a switching current I C follow through the control terminal C. The switching current I C flows into the output end of the current mirror 4 as a part of the output current I. Therefore, each of the switch circuits 2 and 3 draws from the output terminal 1 a current having a value of (I-I C ) when turned ON. when the switches 2 and 3 are in an OFF state, they produces no current. The output current at the third output end 4-4 of the current mirror 4 is supplied to an input end 7-1 of the compensation current generator 7 which produces a compensation current at its output end 7-2. The compensation current has a value that is substantially equal to that of the switching current I C , and is thus denoted by "I C ". The fourth output end 4-5 of the current mirror 4 and the output end 7-2 of the current generator 7 are connected respectively to an input end 5-1 and a control end 5-3 of a second current circuit 5 which produces an output current at its output end 5-2 in response to the currents I and I C . The output current at the output end 5-2 takes a value of (I-I C ) as shown in Fig. 1 and is supplied to the output terminal 1 via a conductive path provided between the output end 5-2 and the output terminal 1. When the switching current I C is not supplied to both of the switches 2 and 3 to turn them OFF, the output terminal 1 is disconnected from the output ends 4-2 and 4-3 of the current mirror 4. The current (I-I C ) at the output end 5-2 of the current mirror 5 is thereby supplied through the output terminal 1 to the load 8. When the switches 2 and 3 are supplied with the switching current I C , they provide current paths between the output terminal 1 and the output ends 4-2 and 4-3 to draw the current of (I-I C ), respectively. The current drawn by the switch 2 is substantially equal to the current supplied from the current mirror 5. Therefore, the switch 3 draws the current of (I-I C ) from the load 8 via the output terminal 1. In other words, the load circuit 8 is supplied with -(I-I C ) current. When only one of the switches 2 and 3 receives the switching current I, substantially all current drawn by the turned-ON switch is supplied only from the current mirror 5. The load 8 is thereby supplied with no current to be disconnected from the output terminal 1 with respect to current. Thus, the load circuit 8 is supplied with a current of (I-I C ), -(I-I C ), or 0 (zero) in accordance with ON/OFF states of the switches 2 and 3. With reference to Fig. 2, a phase locked oscillator 100 is shown, in which the circuit 12 according to another embodiment of the present invention is used as a charge pump circuit (called hereinafter "CP"). A voltage controlled oscillator (VCO) 10 as a frequency variable oscillator generates an oscillation signal f OUT which is in turn supplied to a first input terminal of a phase comparator (PC) 11. The PC 11 also has a second input terminal supplied with an input signal f IN and compares the phases between the signals f IN and f OUT to produce phase comparison outputs V₁ and V₂. The CP 12 responds to the comparison outputs V₁ and V₂ and charges, discharges or disconnects a low-pass filter (LPF) 13. The output V₃ of the LPF 13 is fed back to the VCO 10. The frequency of the oscillation signal f OUT is thereby controlled so that the phase thereof is locked to that of the input signal f IN . In the CP 12, the comparison outputs V₁ and V₂ derived from the PC 11 are supplied respectively through input terminals 125 and 126 to the bases of NPN transistors Q₁₀ and Q₁₂ whose collectors are connected in common to an output terminal 124. The transistors Q₁₀ and Q₁₂ cooperate respectively with NPN transistors Q₉ and Q₁₁ to constitute a differential circuit. The common emitter connection of the transistors Q₉ and Q₁₀ and that of the transistors Q₁₁ and Q₁₂ are connected respectively to the collectors of NPN transistors Q₄ and Q₅. The bases of the transistors receive a bias voltage V B from a bias source 122 and the collectors thereof are connected to a power supply terminal 123 receiving a positive voltage +V. The emitters of the transistors Q₄ and Q₅ are grounded via resistors R₃ and R₄ and the bases thereof are connected in common to the base of an NPN transistors Q₁. The emitter of the transistor Q₁ is grounded via a resistor R₁ and the collector thereof is connected to a current source 121 generating a reference current I ref . The collector of Q₁ is also connected to its base via a base-emitter path of an NPN transistor Q₂ having its collector connected to the terminal 123. Accordingly, the transistors Q₁, Q₂, Q₄ and Q₅ constitutes a current mirror circuit, so that the transistors Q₄ and Q₅ produces their collector current relative to the reference current I ref . In this embodiment, the resistors R₁, R₃ and R₄ are designed to take the same resistance value and the transistors Q₁, Q₄ and Q₅ have the same emitter area. Therefore, the collector currents of the transistors Q₄ and Q₅ are substantially equal to the reference current I ref , and thus denoted by "I ref ". When the comparison output V₁ is larger in voltage than the bias voltage V B , the transistors Q₉ and Q₁₀ are turned OFF and ON, respectively. At this time, the collector current I ref of the transistor Q₄ is equal to the emitter current of the transistor Q₁₀ that is equal to the sum of its base and collector currents. Accordingly, the base and collector currents I B and I C of the transistor Q₁₀ take values of I ref /h FE and (I ref -I B ), respectively, where h FE represents a current gain of the transistor Q₁₀. Since the CP 12 is fabricated as an semiconductor integrated circuit device, all NPN transistors are matched with one another and thus take the substantially same current gain h FE . All PNP transistors are also matched with one another. Similarly, when the comparison output V₂ is larger in voltage than the bias voltage V B to turn the transistor Q₁₂ ON, the base and collector currents of Q₁₂ takes values of I ref /h FE and (I ref -I B ), respectively. An NPN transistor Q₃ has it base connected to the base of the transistor Q₁ and its emitter grounded via a resistor R₂. The emitter area of the transistor Q₃ is equal to that of Q₁, and the resistor R₂ is equal to the resistor R₁. Therefore, the collector current of Q₃ is substantially equal to the reference current I ref , and thus denoted by "I ref ". The collector of the transistor Q₃ is connected to the collector of a PNP transistor Q₆ and to the base of PNP transistor Q₇. The emitter of the transistor Q₆ is connected via a resistor R₅ to the terminal 123 and the base thereof is connected to the collector of Q₇ and to the base of a PNP transistor Q₈. The collector of the transistor Q₇ is grounded. The emitter of the transistor Q₈ is connected via a resistor R₆ to the terminal 123 and the collector thereof is connected to the output terminal 124. The transistors Q₆ to Q₈ and the resistors R₅ and R₆ constitutes a current mirror circuit. The sizes of Q₆ to Q₈ are the same and the resistance values of R₅ and R₆ are equal to each other. Two NPN transistors Q₁₃ and Q₁₄ and a resistor R₇ are provided as a base current compensation circuit in accordance with the present invention. The transistor Q₁₃ has the same emitter area as the transistor Q₁ and its base connected to the base of Q₁. The resistor R₇ has the same resistance value as the resistor R₁ and is connected between the emitter of Q₁₃ and the ground. Therefore, the collector current of the transistor Q₁₃ is made substantially equal to the reference current I ref , and thus denoted by "I ref ". The collector of Q₁₃ is connected to the emitter of the transistor Q₁₄ whose collector is connected to the terminal 123. The base of Q₁₄ is connected to the emitter of the transistor Q₈. As already mentioned above, the current gains of the transistors Q₁₀, Q₁₂ and Q₁₄ are equal to one another. Therefore, a current having a value of I ref /h FE is supplied from the terminal 23 via the resistor R₆ to the transistor Q₁₄ as a base current I B . In other words, a part of a current that is to flow through the transistor Q₄ flows into the transistor Q₁₄. As a result, the collector current of the transistor Q₈ takes a value that is smaller than the reference current I ref by the base current I B . This value is thus represented by (I ref -I B ). Referring to Figs. 3A to 3C, a circuit operation of Fig. 2 will be described below. There are three relationships between phases of the oscillation signal f OUT and the input signal f IN . The first relationship is that the phase of the oscillation signal f OUT is coincident with that of the input signal f IN as shown in Fig. 3A. The PC 11 inverts the first comparison output V₁ from a high level to a low level in synchronism with the leading edge of the oscillation signal f OUT that appears during a high level period of time of the input signal. The first comparison output V₁ is returned to the high level in synchronism with the falling edge of the input signal f IN . At this time, the PC 11 inverts the second comparison output V₂ from the low level to the high level. The output V₂ is returned to the low level in synchronism with the leading edge of the oscillation signal f OUT that appears within a low level period of time of the input signal f IN . As a result, a low level period of time of the first output V₁ and a high level period of time of the second output V₂ are made equal to each other in the first phase relationship, as shown in Fig. 3A. When the first and second output V₁ and V₂ take the high level and the low level, respectively, the transistor Q₁₀ is turned ON and the transistor Q₁₂ is turned OFF. Only the transistor Q₁₀ produces its collector current of (I ref -I B ) level. The transistor Q₈ also produces its collector current of (I ref -I B ) level. Accordingly, an output current I₀ supplied via the output terminal 124 to the LPF 13 takes a zero level as shown in Fig. 3A. In other words, the LPF 13 is disconnected from the terminal 124 with respect to current. When both of the outputs V₁ and V₂ take the low level to turn both of the transistors Q₁₀ and Q₁₂ OFF, the collector current of the transistor Q₈ is supplied via the output terminal 124 to the LPF 13. That is, the LPF 13 is charged by a current having a value of (I ref -I B ) as shown in Fig. 3A. When both of the outputs V₁ and V₂ take the high level, both of the transistors Q₁₀ and Q₁₂ produce the collector current of (I ref -I B ) level. Since the collector current of the transistor Q₁₀ is counteracted by the collector current of the transistor Q₈, the transistor Q₁₂ draws the (I ref -I B ) level current from the LPF 13 via the output terminal 124. In other words, the current having a value of -(I ref -I B ) is supplied to the LPF 13 to discharge it, as shown in Fig. 3A. Since the charging and discharge periods of time are equal to each other, the output V₃ of the LPF takes a first level represented by "V L1 " in Fig. 3A to maintain the first phase relationship between the oscillation signal f OUT and the input signal f IN . The second phase relationship is that the phase of the oscillation signal f OUT delays as shown in Fig. 3B. In this case, the charging period of time of the LPF 13 is made longer than the discharging period of time thereof, as apparent from the outputs V₁ and V₂ shown in Fig. 3B. The output V₃ of the LPF 13 thus takes a second level denoted by "V L2 " in Fig. 3B and larger than the first level V L1 . The oscillator 10 is thereby controlled so that the phase of the oscillation signal f OUT is advanced by the second level output V₃. The third phase relationship is that the phase of the oscillation signal f OUT advances as shown in Fig. 3C. The discharging period of time of the LPF 13 is therefore made longer than the charging period of time. The output V₃ of the LPF 13 is thereby changed to a third level represented by "V L3 " in Fig. 3B and smaller than the first level V L1 . As a result, the phase of the oscillation signal f OUT is made coincident with that of the input signal f IN . Referring to Fig. 4, still another embodiment of the present invention will be described, wherein the same constitutents as those in Fig. 2 are denoted by the same reference numerals and symbols to omit their further explanation and only the charge pump circuit is shown. In Fig. 4, the base current compensation circuit is composed of two NPN transistors Q₂₀ and Q₂₁, three PNP transistors Q₂₂ to Q₂₄ and three resistors R₂₀ to R₂₂. The transistor Q₂₀ has its base connected to the base of the transistor Q₁ and its emitter grounded via the resistor R₂₀ and the emitter area thereof is equal to that of the transistor Q₂₀. The resistor R₂₀ has the same resistance value as the resistor R₁. Therefore, the transistor Q₂₀ produce its collector current that is substantially equal to the reference current I ref . The transistor Q₂₁ has its emitter connected to the collector of Q₂₀ and its collector connected to the terminal 123. Accordingly, the base current of the transistor Q₂₁ takes a value of I ref /h FE , and thus denoted by "I B ". The transistors Q₂₂ to Q₂₄ and the resistors R₂₁ and R₂₂ constitute a current mirror circuit receiving the base current I B of the transistor Q₂₁ as its input current. The current gain of this current mirror circuit, i.e. the ratio of the output current to the input current, is designed to be 1. As a result, the collector current of the transistor Q₂₄ has a value that is substantially equal to the base current of Q₂₁, and thus denoted by "I B ". The collector of the transistor Q₂₄ is connected to the emitter of the transistor Q₃ to supply the base current I B to the resistor R₂. Accordingly, the transistor Q₃ produces its collector current having a value of (I ref -I B ). This collector current is produced as an input current to the current mirror circuit composed of the transistors Q₆ to Q₈ and the resistors R₅ and R₆. As a result, also in this embodiment, the transistor Q₈ produces the (I ref -I B ) level current.

Claims: A current output circuit comprising a plurality of input terminals (125, 126), receiving input signals (VI, V2), a first current mirror circuit (Q6-Q8, R5, R6) having an output end and an input end receiving a first reference current having a first value (Iref), an output terminal (124), a plurality of first transistors (Q10, Q12) each having a base coupled to one of said input terminals and a collector-emitter current path connected between said output terminal and reference current providing means, and means (conductive path between Q8 and 124) for coupling the output end of said first current mirror circuit to said output terminal, characterized in that said reference current providing means comprises a second current mirror circuit (Q1-Q5, Q13, R1-R4, R7) having an input end supplied with a second reference current and producing at a plurality of first output ends and at a second output end first currents each having said first value (Iref), that said current output circuit further comprises a second transistor (Q14) of the same conductivity type as said first transistors having a base, an emitter connected to the second output end of said second current mirror circuit and a collector connected to a potential point (+V), and that said first current mirror circuit (Q6-Q8, R5, R6) has a control end supplied with the base current (IB) of said second transistor (Q14) and produces at the output end a second current having a second value (Iref-IB) that is smaller than said first value by said base current of said second transistor (Fig. 2). A current output circuit comprising a plurality of input terminals (125, 126), receiving input signals (VI, V2), a first current mirror circuit (Q5-Q8, R5, R6) having an input end and an output end, an output terminal (124), a plurality of first transistors (Q10, Q12) each having a base coupled to one of said input terminals and a collector-emitter current path connected between said output terminal and reference current providing means, and means (conductive path between Q8 and 124) for coupling the output end of said first current mirror circuit to said output terminal, characterized in that said reference current providing means comprises a second current mirror circuit (Q1-Q5, Q20, R1-R4, R20) having an input end supplied with a reference current, a plurality of first output ends, a second output end, a control end and a third output end coupled to the input end of said first current mirror circuit and producing at the first and second output ends first currents each having a first value (Iref), and that said current output circuit further comprises a second transistor (Q21) of the same conductivity type as said first transistors having a base, an emitter connected to the second output end of said second current mirror circuit and a collector connected to a potential point (+V), means (Q23-Q24, R21, R22) for supplying the base current (IB) of said second transistor to the control end of said second current mirror circuit to cause said second current mirror circuit to produce at the third output end a second current having a second value (Iref-IB) that is smaller than said first value by said base current of said second transistor, and means (conductive path between Q3 and Q6) for supplying said second current to the input end of said first current mirror circuit (Fig. 4). The current output circuit as claimed in claim 1 characterized in that said first current mirror circuit includes a third transistor (Q8) of an opposite conductivity type of said first transistors having a collector connected to said output terminal, an emitter connected through a first resistor (R6) to said potential point and a base, a fourth transistor (Q6) of the said oppositive conductivity type having a collector supplied with said second reference current, an emitter connected through a second resistor (R5) to said potential point and a base connected to the base of said fourth transistor, and means (Q7) for coupling the base and collector of said fourth transistor, and that the emitter of said third transistor (Q8) is connected to the base of said second transistor (Q14) to receive said base current (IB). The current output circuit as claimed in claim 2, characterized in that said second current mirror circuit includes a third transistor (Q3) of the same conductivity type as said first transistor having an emitter connected through first resistor (R2) to a reference point (GND) and supplied with said base current (IB) of said second transistor (Q21), a base and a collector, a fourth transistor (Q1) of said same conductivity type having a collector supplied with said reference current, and emitter connected through a second resistor (RI) to said reference point and a base connected to the base of said third transistor, and means (Q2) for connecting the base and collector of said fourth transistor. The current output circuit as claimed in claim 4 characterized in that said base current of said second transistor (Q21) is supplied to the emitter of said third transistor (Q3) through a third current mirror circuit (Q22, Q23, Q24, R21, R22). The current output circuit as claimed in claim 1 , 2, 3 or 4, wherein each of said reference current has said first value.

Inventors: SATA, HIROSHI C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H03K17
IPC codes: H03L7, H03F3, H03K4, H03K17