DRIVE CIRCUIT FOR FAST SWITCHING OF DARLINGTON-CONNECTED TRANSISTORS

Abstract: Prior circuits for rapidly switching Darlington-connected transistors between on and off states have accomplished relatively fast switching by applying reverse base drive to the transistors to quickly sweep the excess carriers therefrom. However, such circuits have not accomplished the required degree of reduction of turn off time and have induced localized ''hot spots'' in the base-collector junctions of the transistors. In order to overcome these problems, a drive circuit (26) according to the present invention includes first (40) and second (48) power sources of first and second polarities, a turn-on network (38) coupled between the first power source (40) and the control electrode of a driver transistor (Q4) of a Darlington-connected pair (Q4-Q6) for selectively turning on the transistor pair, turn-off capacitors (C4, C5, C6) coupled between the turn-on network (38) and the control electrodes of each of the transistors (Q4-Q6) and a turn-off network (46) coupled between the capacitors (C4-C6) and the second power source (48) for coupling the second power source (48) to the capacitors (C4-C6) to rapidly turn off the transistors (Q4-Q6). Means (C2, C3) are included for providing a dwell interval between operation of the turn-on network (38) and operation of the turn-off network (46) to allow recombination of excess carriers in the transistors (Q4-Q6) to minimize the incidence of localized hot spots.

Description: Drive Circuit for Fast Switching of Darlington-Connected Transistors Description Technical Field The present invention relates generally to switching circuits, and more particularly to a drive cir¬ cuit for rapidly switching transistors connected in a Darlington configuration. Background Art There are numerous applications in which it is necessary to rapidly turn on and off high-current-capa¬ city power switches to control the power delivered to a load. For example, in an inverter operated in a pulse width modulated (PWM) mode of operation, it may be neces- sary to cycle power switches carrying a high magnitude of current at a 30 kilohertz switching frequency. Typical¬ ly, these power switches comprise Darlington-connected bipolar power transistors. At present, the specified storage time of these transistors is on the order of 5 to 7 microseconds. This storage time adversely affects the maximum switching frequency for these transistors and may render them unsuitable for certain applications. Prior attempts at reducing the turn-off time of Darlington power switches have relied upon the appliσa- tion of a reverse bias to the base-emitter junction of one or both transistors at the time of turn-off to rapid¬ ly deplete excess carriers therein. For example, Seager U.S. Patent No. 3,697,783 discloses transistor switching circuitry that includes a first gating circuit coupled to the base of an input transistor and a second gating cir- -2- cuit coupled to the base of an output transistor. The output transistor is driven on in response to a gating signal by the input transistor and the second gating cir¬ cuit. During the time the transistors are on, a voltage is built up on a capacitor coupled between the second gating circuit and the base of the output transistor. When the gating signal changes state, a switch is closed to couple the capacitor between the base and emitter electrodes of the output transistor to deplete the number of excess carriers therein so that turn-off can occur in rapid fashion. Other types of circuits for decreasing the turn-off time of a power switch are disclosed in Akamatsu U.S. Patent No. 4,239,988, Inami et al U.S. Patent No. 3,971,961, Carlsen II U.S. Patent No. 4,234,805 and Baker U.S. Patent No. 4,210,826 (see Fig. 7 and column 14, line 51 through column 15, line 53) . Prior types of circuits for decreasing the turn-off time of power switches have serious limitations. In the case of circuits like Seager, discussed above, localized "hot spots" or secondary breakdown effects can arise in the base-collector junctions of the transistors due to the rapid depletion of excess carriers. These "hot spots" not only reduce the efficiency of the tran- sistor but also increase the chances of failure thereof. Also, these prior circuits have not achieved the required switching speeds and have not reduced switching losses to an acceptable degree. Disclosure of Invention . In accordance with the present invention, a drive circuit for use with Darlington-connected transis¬ tors accomplishes rapid and efficient switching of such transistors while minimizing the occurrence of "hot spots". More particularly, the drive circuit of the present invention accomplishes rapid switching of driver and driven transistors connected together in a Darlington configuration. The circuit includes a first power source which develops voltage of a first polarity, a turn-on gating network coupled to the base electrode of the driv¬ er transistor for selectively applying the first polarity voltage to first and second turn-off capacitors coupled between the turn-on gating network and the base of the driven and driver transistors, respectively, a 1' second power source that develops voltage of a second polarity opposite the first polarity and a turn-off gating network for selectively coupling the second power source to the turn-off capacitors. During the time the first power source is coupled to the turn-off capacitors, the tran¬ sistors are turned on and a voltage is stored by the ca¬ pacitors. When the second power source is coupled to the capacitors, an augmented voltage of the second polarity greater than the voltage developed by the se.cond power source is applied to the base of the driver and driven transistors to rapidly turn off same. In the preferred embodiment, the first polarity and the second polarity voltage are alternately applied to the transistors to switch the transistors between con¬ ducting and nonconducting states. Means are included for providing a dwell interval between application of the first polarity voltage and application of the second po- larity voltage to the transistors during which neither voltage is applied thereto. During this dwell interval, recombination of excess carriers in the transistors oc¬ curs so that the incidence of localized "hot spots" in the base-collector junction of the transistors is reduced when the second polarity voltage is subsequently applied to the transistors. In one embodiment of the invention, means are provided between the capacitor and the emitter of the driver transistor for preventing current flow in a direc¬ tion which causes the driver transistor to operate in a reverse conduction mode. This feature in turn minimizes the possibility of short circuiting of the driven tran- sistor. This possibility is further minimized through the use of means for operating the driver transistor at or slightly below the edge of saturation when such tran¬ sistor is on. The drive circuit of the present invention is capable of reducing the turn-off time of Darlington-con¬ nected bipolar transistors to less than three microsec¬ onds so that such transistors can be used in high power, high switching frequency applications. Brief Description of the Drawings Fig. 1 is a block diagram illustrating a motor drive circuit with which the present invention may be used; Fig. 2 is a combined block and schematic dia¬ gram of the inverter shown in Fig. 1; Fig. 3 is a block diagram of circuitry for operating one of the switches S1-S6 shown in Fig. 2; Fig. 4 is a more specific combined schematic and block diagram of a portion of the circuitry shown in Fig. 3; Fig. 5 is a set of waveform diagrams illustrat¬ ing the operation of the circuitry shown in Fig. 4; and Fig. 6 is a diagram similar to that of Fig. 4 illustrating an alternative embodiment of the invention. Best Mode for Carrying Out the Invention Referring now to Fig. 1, there is illustrated a motor drive circuit with which the present invention may be used. The motor drive circuit comprises a generator 10 which is driven by a variable speed source of motive power (not shown) . The generator 10 develops polyphase AC power which is coupled to a rectifier circuit 12 that converts the AC power into positive, negative and ground voltages on DC power buses 14a,14b,14c, respectively. The power buses 14 are in turn coupled to an inverter 16 which converts the DC power into constant frequency poly¬ phase AC power which is delivered to a motor 18. It should be noted that the motor drive circuit shown in Fig. 1 is exemplary only, in the sense that the present invention may be used with other types of cir¬ cuits requiring high power and fast switching capability. Referring now to Fig. 2, the inverter 16 in¬ cludes first through sixth power switches S1-S6 which are coupled in a three phase bridge configuration. Anti-par- allel diodes D1-D6 are coupled across the switches S1-S6, as is conventional. The inverter 16 shown in Fig. 2 is intended for use as a neutral-clamped pulse width modulated (PWM) in¬ verter in which the maximum output voltage swing devel- oped at phase outputs 20A,20B,20C is limited to one-half the voltage across the DC power buses 14a, 14b. Such an inverter is disclosed in Glennon U.S. Patent Application Serial No. 531,037, filed September 12, 1983, entitled "Neutrally Clamped PWM Inverter" (Docket No. B01383-AT1- USA) , assigned to the assignee of the instant application and the disclosure of which is hereby incorporated by reference. It should be noted that the instant invention may be used in other switching circuits, such as chop¬ pers, circuits using proportional base drive circuits or any other circuits using transistors connected in a Dar- lington configuration. The inverter 16 shown in Fig. 2 includes three bi-directional switches 22a,22b,22c which are coupled between the phase outputs 20A-20C, respectively, and the power bus 14c. The switches S1-S6 and the bi-directional switches 22 are in turn operated by a switch control 24 to cause generation of the appropriate AC waveform for operating the motor 18. Referring now to Fig. 3, there is illustrated a portion of the switch control 24 shown in block diagram form in Fig. 2. The circuitry shown in Fig. 3 comprises a drive circuit 26 for operating the power switch SI. It should be noted that duplicate circuitry is provided in the switch control 24 to operate the switches S2-S6 and, if desired, the switches 22. The circuitry shown in Fig. 3 receives a PWM control signal which is developed by a conventional PWM amplifier (not shown) . The PWM control signal is isolat¬ ed by an isolation circuit 30 and is coupled to a driving stage 32 that develops a gating signal on a pair of lines 34,36 from the isolated PWM control signal. The line 34 is in turn coupled to a turn-on gating network 38 which is coupled to a first power source 40. The first power source develops voltage of a first or positive polarity which is selectively coupled by the turn-on network 38 via a pulse shaping circuit 42 to the power switch SI so that forward base drive is applied thereto. This selec¬ tive application of power to the power switch SI turns the switch on to couple the DC voltage on the power bus 14a, Fig. 2, to the phase output 20A. The line 36 from the driving stage 32 is cou¬ pled to a turn-off gating network 46 which is separate from the turn-on gating network 38,48. The turn-off net¬ work 46 is in turn coupled to a second power source which develops voltage of a second polarity opposite the first polarity. This second polarity voltage is selectively applied by the turn-off network 46 via pulse shaping cir¬ cuitry 50 to the power switch SI so that reverse base drive is applied thereto to turn same off. It should be noted that the first and second power sources 40,48 may in fact comprise the outputs of the rectifier circuit 12 on the buses 14a,14b, 'if de¬ sired. Referring now to Fig. 4, there is illustrated in greater detail the turn-on and turn-off gating net¬ works 38,46, the pulse shaping circuits 42,50 and the power switch SI. The gating signal from the driving stage 32 comprises complementary signals, i.e. the signal on the line 34 is high wheri the signal on the line 46 is low, and vice versa. If desired, the two lines may be re¬ placed by a single line with an inverter coupled thereto to provide the complementary outputs. In either case, a high state signal on the line 34 (and hence a low state signal on the line 46) eventually results in the switch SI being in the on state while the reverse condition, i.e. a high state signal on the line 46 and a low state signal on the line 34, eventually results in the switch SI being in the off state. The line 34 is coupled through a resistor Rl to the control electrode of a switch Ql which is a part of the turn-on gating network 38. The control electrode of the switch Ql is also coupled by a capacitor Cl and a resistor R2 to the positive power supply 40. Main current electrodes of the switch Ql are coupled between the positive power source 40 and a main current electrode of a first turn-off switch or transis¬ tor Q2 which is a part of the turn-off gating network 46. A junction 60 between the switches Ql and Q2 is coupled through the pulse shaping circuitry 42 to the control or base electrode of a driver transistor Q4 which comprises a part of the switch SI. The junction 60 is also coupled through the pulse shaping circuitry 50 to the control or base electrode of a second transistor Q5 which is also part of the switch SI. The switch Si also includes a third transistor Q6 which is Coupled in parallel with the transistor Q5 and which together comprise a driven transistor of the switch SI. The two transistors Q5 and Q6 may be replaced by a single driven transistor, if desired. The control or base electrodes of the transis¬ tors Q5 and Q6 are coupled to one of the main current electrodes (i.e. the emitter electrode) of the driver transistor Q4 while 'the collector main current electrodes of the transistors Q4-Q6 are coupled together to one end of a load 61. The other end of the load 61 is coupled to the emitter main current electrodes of the transistors Q5 and Q6. The turn-off gating network 46 includes, as previously noted, the first turn-off transistor Q2 which is coupled to the line 46 by a resistor R3. A delay ca¬ pacitor C2 and resistor R4 are coupled between the con¬ trol electrode of the switch Q2 and the second or nega- tive power source 48. The line 46 is also coupled by a resistor R5 to the control electrode of a second turn-off switch or transistor Q3. A delay capacitor C3 and a resistor R6 are coupled between the control electrode of the switch Q3 and the second or negative power source 48. It should be noted that, in the preferred em¬ bodiment, the switches Q1-Q3 comprise power FET's, al- though they may be other types of power switches, if de¬ sired. The switch Q3 is coupled to the base of the transistor Q5 through a first turn-off capacitor C4 and a resistor R7. A voltage divider consisting of resistors R8 and R9 is coupled between the base of the transistor Q4 and the negative power supply 48. The junction be¬ tween the resistors R8 and R9 is coupled to the base of the transistor Q5. These resistors bias the transistors Q4 and Q5 for proper operation of same. The operation of the circuitry illustrated in Fig. 4 will now be described with reference to the wave¬ forms of Fig. 5. Assume that immediately prior to time t = t_, the switch SI is off thereby resulting in a rela¬ tively high voltage V__ across the switch SI and a rela- tively low magnitude' of load current I τ J- . At time t = t n u, the driving stage 32 develops a high state output on the line 34 and a low state output on the line 46. The switch Ql is thereby turned on, in turn coupling the pos¬ itive voltage from the first power source 40 to the base of the transistor Q4 through components in the pulse shaping circuit 42 comprising resistors R10-R12 and sec¬ ond and third turn-off capacitors C5 and C6. The result¬ ing forward base drive current I- •D,A, into the base of the transistor Q4 rises exponentially following the time t n and reaches a peak at a time t = t, . Moreover, forward base drive current is supplied through a diode D7, a re¬ sistor R13 and a capacitor C4 to the base of the transis¬ tor Q5. This current, . designated I B? , also rises expo- nentially following the time t = t 0 and reaches a peak at or near the time t = t,. The base currents I βl and I B2 rapidly turn on the transistors Q4-Q6, in turn lowering the voltage V-- to a saturated value ^ C ~-SA and allow:i - n 9 the load current I τ to rise to a high value. Following the time t = t., the current I-, de¬ cays in exponential fashion. The current I B1 reaches a steady state value I Bls at a time t = t_, which steady state value is determined by the resistance of the resis- tor Rll. At this point, the capacitors C5 and C6 are charged to a high voltage with polarity as indicated in the figure. Also in the time period following the time t = t.., the current I_ 2 through the capacitor C4 eventu- ally drops to a zero level. The current I_ 2 decay ' s at a substantially slower rate than the current I_ 2 due to the relative values of the components RIO, R12, R13, C4, C5 and C6. Once the current ! -„_->--_. has dropped to zero, the voltage across the capacitor C4 reaches a high value, typically within a Couple of volts of the voltage provid¬ ed by the first power source 40. At time t = t,, the gating signal from the driving stage 32 reverses state, i.e. a high state signal is developed on the line 46 while a low state signal is developed on the line 34. This reversal of states of the gating signal substantially immediately turns off the transistor Ql. However, the transistors Q2 and Q3 are not turned on until a dwell interval or delay period has elapsed following the time t = t,. This dwell interval or delay period is provided by means including the resis¬ tors R3-R6 and the capacitors C2 and C3 coupled to the control electrodes of the transistors Q2 and Q3 which together delay the application of the second polarity voltage to the transistors Q4-Q6. In the preferred em¬ bodiment, the ■ well interval is one-half microsecond in duration, although it may be made longer or shorter, as desired. The purpose of this dwell interval, during which none of the transistors Q1-Q3 is on and therefore no base drive is applied to the transistors Q4-Q6, is to allow recombination of excess carriers in the transistors Q4-Q6 prior to the application of reverse base drive thereto. This recombination period reduces the number of excess carriers in the base-collector junctions of the transistors Q4-Q6 so that, when reverse base dr'ive is applied thereto to quickly turn off same, the incidence of localized hot spots is substantially reduced. This in turn increases the efficiency of the devices and reduces the chance of failure thereof. At the end of the dwell interval at time t = t., the transistors Q2 and Q3 turn on, in turn apply¬ ing reverse base drive to the transistors Q4-Q6. More specifically, when €he transistor Q2 turns on, the base current I-, increases exponentially in a negative direc¬ tion through a diode D8 and the transistor Q2 to the sec¬ ond power source 48. Also, the voltage drop across the transistor Q3 decreases to a low level, effectively cou- pling substantially all of the voltage across the capaci¬ tor C4 and the voltage developed by the second power source 48 in a reverse direction across the base-emitter junction of the transistors Q5 and Q6. The capacitor C4 therefore comprises means for providing an augmented vol- tage of the second polarity greater than the voltage de¬ veloped by the second power source 48 to the base-emitter junctions of the transistors Q5 and Q6 to quickly turn off same. A similar result is accomplished in terms of the transistor Q4 by operation of the transistor Q2. That is, turn on of the transistor Q2 causes the capaci¬ tors C5 and C6 to provide an augmented voltage of the second polarity to the base-emitter junction of the tran¬ sistor Q4 to rapidly turn off this transistor. Subsequent to the time t = t,, the load current I T decreases rapidly and the voltage V CE across the tran¬ sistors Q4-Q6 rises. The base currents I_, and I β2 reach maximum reverse values at or around a time t = t_ and thereafter decay to substantially a zero level as the excess carriers are swept out of the bases of these tran¬ sistors. The circuitry shown in Fig. 4 is especially useful to quickly turn off the transistors Q4-Q6. How¬ ever, it has been found that, under a certain operating condition, the transistor Q4 could operate in the reverse conduction mode. This was found to occur when a rela¬ tively low magnitude of load current I_ was conducted by the transistors Q5 and .Q6. In this case, the base cur¬ rent I_ D_t- supplied through the capacitor C4 caused reverse current flow through the emitter and collector electrodes of the transistor Q4. This operation could, in turn, cause short circuiting of the transistors Q5 and Q6. Specifically, it can be seen that: V CEQ5 or Q6 = V CEQ4 + V BEQ5 or Q6 When the transistors Q5 and Q6 are fully saturated, the value V n _ 6 is approximately 1 volt. Moreover, when the transistor Q4 operates in the reverse conduction mode, the value v -. Eo4 may approach -1 volt. Under this condition, then, the value V 0 _ may approach zero, resulting in destruction of one or both of these transis¬ tors. As previously mentioned, the circuit shown in Fig. 4 encounters this difficulty only when relatively light loads are being driven by the switch SI. The cir¬ cuit otherwise performs satisfactorily and hence is ap- propriate for those applications where light loads will not be driven. Referring now to Fig. 6, there is illustrated an alternative embodiment of the present invention which is capable of driving all types of loads, including light loads, without risk of destruction of the transistors Q4-Q6. Elements common to the embodiments shown in Figs. 4 and 6 are assigned like reference numerals. As was noted with respect to the embodiment shown in Fig. 4, each of the transistors Ql, Q2 and Q3 is operated so that a dwell interval or delay period is in¬ terposed between turn off of the transistor Ql and turn on of the transistors Q2 and Q3. Moreover, the diode D7 and the capacitor C4 are provided so that a voltage is built up across the capacitor C4 when the transistors Ql and Q4-Q6 are on. 'However, a diode D10 is provided to prevent current flow in a direction which causes the driver transistor Q4 to operate in the reverse conduction mode when this transistor is on. Instead, charging cur¬ rent for the capacitor C4 flows through a resistor R14 and a diode Dll to ground. Then, following the dwell interval after turn off of the transistor Ql, at which point the transistors Q2 and Q3 are turned on, reverse base drive current flows through the diode D10, a resis¬ tor R15, the capacitor C4 and the transistor Q3 to the second power source 48. The capacitor C4, as noted with respect to the previous embodiment shown in Fig. 4, therefore supplies the augmented voltage of the second polarity across the base and emitter junctions of the transistors Q5 and Q6 to quickly turn off same. It should be noted that a resistor R16 and di¬ ode D12 are coupled across the capacitor C4 to maintain the reverse bias voltage across the base-emitter junc¬ tions of the transistors Q5,Q6 for the entire turn-off period. This, in turn, increases the immunity of the transistors against inadvertent turn-on in response to large changes of collector to emitter voltage during this period. Means are also provided for operating the tran- sistor Q4 substantially at or slightly below the edge of saturation to further minimize the possibility of opera¬ tion in the reverse conduction mode. Such means compris¬ es a circuit known as a "Baker clamp" comprising diodes D13, D14 and D15 which bias the base-collector junction of the transistor Q4 so that the transistor operates, when on, in the quasi-saturation or desaturation mode. In effect, the value v CESAm of the transistor Q4 is slightly increased to minimize the possibility of opera¬ tion in the reverse conduction mode. By adding an addi- tional diode D16, shown in dotted lines in Fig. 6, one can further reduce the probability of operation in the reverse conduction mode by the transistor Q4. In effect, this diode will cause V r L-,. τ r : -,.b„A 1 . m -t of the transistor Q4 to fur- ther increase to cause operation at a point further below the edge of saturation. While the Baker clamp and the diode D16 in¬ crease the power dissipation of the circuit, it is felt that this disadvantage is outweighed by the protection afforded against destruction of the expensive power tran- sistors Q5 and Qβ. There are additional differences in the circuit in Fig. 6 over that shown in Fig. 4. The capacitors C5 and C6 are replaced by a capacitor C7 which is coupled across the diode D8. The capacitor C7 accomplishes the same function of the capacitor C5 and C6, i.e. to provide an augmented reverse bias voltage across the transistor Q4 to quickly turn off same. The resistor R12, shown in Fig. 4, is omitted to prevent reverse voltage build up across the capacitor C7 while the transistor Q2 is on. In addition, a pair of resistors R17 and R18 are coupled in series between the switches Ql and Q2 and a resistor R19 is coupled between the switch Ql and the diode D14. These resistors function as current limiters. Also, appropriate biasing circuitry comprising diodes D17 and D18, zener diodes Zl and Z2 and resistors R20 and R21 are provided to limit the reverse bias across the base-emitter junctions of the transistors Q4-Q6. Corresponding circuitry is also included in Fig. 4 but is not shown therein for simplicity. The embodiment shown in Fig. 6 is effective to rapidly switch the transistors Q4-Q6 between on and off states while at the same time preventing reverse conduc- tion of the transistor Q4 which may cause short circuit¬ ing of the transistors Q5 and Q6.

Claims: Claims 1. A drive circuit for rapidly switching tran- 2 sistors each having a control electrode and a pair of main current electrodes and connected in a Darlington 4 configuration whereby the control electrode of a driven transistor is coupled to one of the main current elec- £ ■ trodes of a driver transistor and the other of the main current electrodes of the driver transistor is coupled to 8 one of the main current electrodes of the driven transis¬ tor, comprising: 10 a first power source developing voltage of a first polarity; 12. " a turn-on gating network coupled between the first power source and the control electrode of the driv- 14 er transistor for selectively applying the first polarity voltage to the transistors to turn on same; 16 a second power source developing voltage of a second polarity opposite the first polarity; and 18 a turn-off gating network coupled between the second power source and the transistors for selectively 20 applying the second polarity voltage to the transistors to turn off same. 2. The drive circuit of claim 1, further in- 2 eluding first and second turn-off capacitors coupled be¬ tween the gating networks and the control electrodes of 4 the driven and driver transistors, respectively, for pro¬ viding an augmented voltage of the second polarity great¬ s ' er than the voltage developed by the second power source to the transistors for quickly turning off same. 3. The drive circuit of claim 1, wherein the turn-on gating network and the turn-off gating network are responsive to a gating signal which assumes one of two states whereby the transistors are on when the gating signal is in a first state and are off when the gating signal is in a second state and wherein the turn-off gat¬ ing network includes means for delaying application of the second polarity voltage to the transistors for a de¬ lay period following a transition of the gating signal from the first to the second states to allow recombina¬ tion of excess carriers in the transistors. 4. The drive circuit of claim 3, wherein the turn-off gating network includes first and second turn- off transistors each having a control and main current path electrodes wherein the control electrodes of the driver and driven transistors are coupled to a main cur- rent path electrode of the first and second turn-off transistors, respectively, and the control electrodes of the first and second turn-off transistors receive the gating signal. 5. The drive circuit of claim 4, wherein the delaying means comprises first and second capacitors cou¬ pled to the control electrodes of the first and second turn-off transistors, respectively. 6. The drive circuit of claim 1, wherein the ' _ turn-off gating network includes separate first and sec¬ ond means for applying the second polarity voltage to the driver and driven transistors, respectively. 7. The drive circuit of claim 6, wherein each of the first and second applying means comprises a tran¬ sistor controlled by a gating signal. 8. The drive circuit of claim 2, further in¬ cluding a diode coupled between the first capacitor and the control electrode of the driven transistor for pre¬ venting current flow in a direction which causes the driver transistor to operate in a reverse conduction mode when such transistor is on. 9. The drive circuit of claim 1, further in¬ cluding means for operating the driver transistor at sub¬ stantially the edge of saturation when the first polarity voltage is applied to the transistors. 10. The drive circuit of claim 9, wherein the operating means comprises a first diode coupled between the turn-on gating network and the control electrode of the driver transistor and a second diode coupled between the control electrode and the other of the main current electrodes of the driver transistor. 11. A base drive circuit for rapidly switching a driver and a driven transistor connected together in a Darlington configuration, each transistor including a base electrode and collector and emitter electrodes, com¬ prising: a first power source developing voltage of a first polarity; a turn-on gating network coupled to the base electrode of the driver transistor for selectively apply- ing the first polarity voltage to the transistors to turn on same; a pair of turn-off capacitors each coupled be¬ tween the turn-on gating network and the base of one of the driven and driver transistors; a second power source developing voltage of a second polarity opposite the first polarity; and a turn-off gating network including a first switch coupled between the turn-off capacitor coupled to the base of the driver transistor and the second power source and a second ' switch coupled between the turn-off capacitor coupled to the base of the driven transistor and the second power source whereby the first and second switches are selectively simultaneously closed to apply augmented voltages of the second polarity greater than the voltage developed by the second power source to the base of the driver and driven transistors to thereby ra¬ pidly turn off same. 12. The base drive circuit of claim 11, where¬ in the first polarity voltage and the -second polarity voltage are alternately applied to the transistors and further including means for providing a dwell interval between application of the first polarity voltage and application of the second polarity voltage to the tran¬ sistors during which neither voltage is applied thereto to allow recombination of excess carriers in the tran¬ sistors. 13. The base drive circuit of claim 12, where¬ in the first and second switches in the turn-off gating network comprise first and second turn-off transistors, respectively, each having a control electrode and wherein the providing means comprises first and second delay ca¬ pacitors coupled to the control electrodes of the first and second turn-off transistors, respectively. 14. The base drive circuit of claim 13, fur¬ ther including a diode coupled between one of the turn- off capacitors and the emitter of the driver transistor for preventing current flow in a direction which causes the driver transistor to operate in a reverse-conduction mode. 15. The drive circuit of claim 11, further in¬ cluding means for operating the driver transistor at the edge of saturation when the first polarity voltage is applied to the transistors. 16. The base drive circuit of claim 15, where- in the operating means comprises a first diode coupled between the turn-on gating network and the base electrode of the driver transistor and a second diode coupled be¬ tween the base electrode and the collector electrode of the driver transistor. 17. A base drive circuit for rapidly switching a driver and a driven transistor connected together in a Darlington configuration, each transistor including a base electrode and collector and emitter electrodes, com¬ prising: means for alternately applying forward and re¬ verse base drive to the transistors to turn the transis- tors on and off; and means for providing a dwell interval between application of the forward and reverse base drive during which no drive is applied to the transistors to allow recombination of excess carriers therein. 18. The base drive circuit of claim 17, where- in the applying means comprises a turn-on gating network coupled to the base electrode of the driver transistor and a turn-off gating network coupled to the bases of both transistors. 19. The base drive circuit of claim 18, where- 2 in the turn-on gating network and the turn-off gating network are responsive to a gating signal which assumes 4 one of two states whereby the driver and driven transis¬ tors are on when the gating signal is in a first state 6 and are off when the gating signal is in a second state and wherein the providing means comprises means for de- g laying application of the reverse base drive to the tran¬ sistors for a delay period following a transition of the 0 gating signal from the first to the second states. 20. The base drive circuit of claim 19,'where- 2 in the turn-off gating network includes first and second turn-off transistors each having a control and main cur- 4 rent path electrodes wherein the base electrodes of the driver and driven transistors are coupled to a main cur- 6 rent path electrode of the first and second turn-off transistors, respectively, and the control electrodes of the first and second turn-off transistors receive the gating signal. 21. The base drive circuit of claim 21, where- 2 in the delaying means comprises first and second capaci¬ tors coupled to the control electrodes of the first and 4 second turn-off transistors, respectively. 22. The base drive circuit of claim 18, fur- ther including first and second turn-off capacitors cou¬ pled between a junction between the turn-on network and the turn-off network and the base of the driven and driv¬ er transistors, respectively, for quickly turning off the transistors. 23. The base drive circuit of claim 22, fur- ther including a diode coupled between the first turn-off capacitor and the emitter of the driver transistor to prevent current flow in a direction which causes reverse conduction of the driver transistor. 24. A base drive circuit for rapidly switching a driver and a driven transistor connected together in a Darlington configuration, each transistor including a - base electrode and collector and emitter electrodes, com¬ prising: a turn-on network coupled to the driver tran¬ sistor for selectively turning on same; a turn-off network coupled to the turn-on net¬ work and to the transistors for selectively turning off same; and means coupled between the turn-on network and the driver transistor for preventing operation of the driver transistor in the reverse conduction mode. - 25. The base drive circuit of claim 24, where- in the preventing means comprises a diode coupled between the emitter of the driver transistor and the turn-on net- work for preventing current flow into such emitter.

Inventors: DHYANCHAND P JOHN, SHEKHAWAT SAMPAT S, DHYANCHAND, P., JOHN, SHEKHAWAT, SAMPAT, S.
Applicants: SUNDSTRAND CORP, SUNDSTRAND CORPORATION
Application year: 1986
Main classification: H03K17
IPC codes: H02M7, H03K17