A METHOD OF THE PRODUCTION OF A METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND SAID TRANSISTOR

Abstract: A method of the production of a metal semiconductor field effect transistor particularly comprising steps of form­ ing a layer which will be a buffer layer of Al x Ga (1 x) As in a predetermined region of the semi-insulating semiconductor substrate using a mask pattern by selective Al ion implanta­ tion, and annealing the semi-insulating semiconductor sub­ strate comprising the said layer, whereby the said layer become the buffer layer of Al x Ga (1 x) As. Various characteris­ tics of the MESFET with the said buffer layer can be improved.

Description: The present invention relates to a method for the production of a metal semiconductor field effect transistor, and is applicable to the production of a GaAs metal semiconductor field effect transistor with a short gate length. Jap. Jnl. of Applied Physics, Vol. 22, suppl. no. 22-1 (1983), pp. 365-369, describes MESFETS comprising a semi-insulating substrate of GaAs, a buffer layer of AlGaAs on the substrate, an active layer of GaAs on the buffer layer, and a metal gate electrode connected to the active layer by a Schottky contact. Source and drain electrodes are positioned at respective sides of the gate electrode. Patent Abstracts of Japan Vol.8, no. 84 (E-239)(1521), 18th April 1984 and JP-A-59 4085 describes MESFETS comprising a semi-insulating substrate of GaAs, a GaAs channel layer on the semi-insulating substrate and layers of AℓGaAs and Si-added AℓGaAs on the channel region. Gate, Source and Drain electrodes are disposed on the Si-added AℓGaAs layer. Use of implanted highly doped source and drain regions and implanted channel regions is discussed in Electronics Letters, Vol. 19 (1983) No. 15, pp. 598-600. A metal semiconductor field effect transistor (referred to as MESFET hereinafter), which is a Schottky gate type field effect transistor, is adopted as an active element for amplifying a signal at ultra high frequency with relatively high gain and provides an active element for oscillations of high frequency. It has been known to those skilled in the art that the MESFET has superior performance compared with the other types of transistors when the MESFET is used as a fundamental element in an integrated circuit operated at ultra high speed. More particularly, the GaAs MESFET, whose semi-insulating semiconductor substrate is made of GaAs, has been a notable device as an alternative to Si devices being used extensively now, since the GaAs MESFET has a superior performance and a simple structure. In general, GaAs MESFETS are fabricated as follows. First of all, an electrical conductive semiconductor layer, which is generally called "active layer", is formed in a semi-insulating GaAs substrate by implantation of impurity ions such as Si⁺ into the GaAs substrate. Moreover, in order to reduce the parasitic resistance, further impurity ions are doped with a relative high concentration in the region of the GaAs substrate adjacent to the source and the drain electrodes, then the MESFET is annealed at a high temperature so as to activate the doped ions. Then, after a source electrode, a drain electrode, and a gate electrode are formed on the GaAs substrate, thus the GaAs MESFET is fabricated. Recently, with a refractory gate electrode and a dummy gate electrode, a high impurity concentration region is self-alignedly formed adjacent to the gate region, then the fabricated MESFET has a high electrical performance. Fig. 1 shows a structure of a conventional MESFET which has been extensively used. As shown in Fig. 1, an active layer 22 is formed on a high resistivity or semi-insulating semiconductor crystal substrate 21, and a Schottky gate electrode 24, a source electrode 27 of ohmic contact and a drain electrode 28 of ohmic contact are respectively formed on the upper surface of the active layer 22. The electrical performance of the MESFET is represented by following transconductance gm and cut-off frequency f T . gm = K(V g -V t ) (1) f T = gm/(2πCgs) (2) where K = (Zεµ)/(2aLg) (3) V g is the gate voltage. V t is the threshold voltage of the MESFET. Cgs is the capacitance between the gate electrode 27 and the source electrode 28. ε is the dielectric constant of the semiconductor substrate 21. µ is the mobility of the carrier. a is the thickness of the active layer 23. Lg is the gate length. Z is the gate width. With the greater transconductance of the MESFET, the MESFET has a more current amplification performance and can drive a greater capacitive load at a high speed, moreover, with a higher cut-off frequency f T , the MESFET can switch at a higher speed. That is, with the greater transconductance gm and the higher cut-off frequency, the MESFET has higher performance. In order to increase the transconductance gm, the gate length Lg of the MESFET is shortened, then the smaller capacitance Cgs between the gate electrode and the source electrode is obtained, therefore, the higher cut-off frequency is obtained. From the viewpoint, there have been investigations to improve the MESFET performance by decreasing the gate length Lg. However, the MESFET with the shorter gate length Lg causes the short-channel effects which harm the performance of the GaAs MESFET, wherein the short-channel effects are the problems that the transconductance gm cannot increase as expected, the threshold voltage of the MESFET varies, and the current cut-off characteristic is inferior. More particularly, the short-channel effects noticeably occur in the self-aligned MESFET whose high impurity concentration region is adjacent to the gate region. The short-channel effects are said to be caused by a substrate leakage current between the high impurity concentration regions formed at both sides of the gate region through the semi-insulating semiconductor substrate. As described above, in order to obtain a higher performance of the MESFET, it is necessary to shorten the gate length Lg and suppress the aforementioned short-channel effects. In order to suppress the short-channel effects, a method was suggested which forms a p-type layer 29 with an opposite polarity to the n-type active layer 23, in the region between the active layer 23 and the semi-insulating semiconductor substrate 21 as shown in Fig. 2. The known methods of forming the p-type layer 29 are as follows; (a) Mg ion implantation method described in "Submicron-gate self-aligned GaAs FET with p-type barrier layer fabricated by ion implantation ", IEEE the 42nd Annual Device Research Conference, Santa Barbara, CA, paper V1B-5, 1984 by K. Matsumoto et al. (b) C and O ions implantation method described in "The effect of substrate purity on short-channel effects of GaAs MESFET's", IEEE Proceedings of the 16th Conference Solid State Devices and materials (Kobe), pp. 395-398, 1984 by H. Nakamura et al. (c) Be ion implantation method described in "Below 10 ps/gate operation with buried p-layer SAINT FET's", Electron Letters, vol. 20, no. 25/26, pp. 1029-1031, 1984 by K. Yamasaki et al. In the above methods, a pn junction is formed between a p-type layer and a n-type layer, and the potential barrier formed by the pn junction can suppress the aforementioned substrate leakage current. In addition, another method for suppressing the substrate leakage current was suggested as shown in Fig. 3. In this method, a buffer layer 30 is formed between the active layer 22 and the semi-insulating semiconductor substrate 21, wherein the buffer layer 30 is made of a semiconductor such as Al 0.3 Ga 0.7 As with a small electron affinity and a wider forbidden energy band than those of GaAs. In the MESFET with the buffer layer 30, the difference of the electron affinity between the n-type GaAs active layer 22 and the Al 0.3 Ga 0.7 As buffer layer 30 causes a potential barrier which is a discontinuous portion of conduction band as shown in Fig. 6(A), electrons are confined in the GaAs active layer 22 by the potential barrier, thereby the substrate leakage current can be suppressed. In order to form the buffer layer 30, first of all, an Al 0.3 Ga 0.7 As buffer layer is formed in a semi-insulating GaAs substrate 21 by an epitaxial growth method such as molecular beam epitaxial growth method, or metal organic chemical vapor epitaxial growth method etc., a GaAs active layer 22 is formed above the Al 0.3 Ga 0.7 As buffer layer 30. The MESFET with a buffer layer formed by molecular beam epitaxial growth method was described in "Characteristics of Submicron Gate GaAs FET's With Al 0.3 Ga 0.7 As Buffers: Effects of Interface Quality", IEEE Electron Device Letters, Vol. EDL-3, No. 2, 1082 by W. Kopp et al, furthermore, the MESFET with a buffer layer formed by metal organic chemical epitaxial growth method was described in IEEE Proceedings of the 14th Conference on Solid State Devices, Tokyo, 1982 by K. Ohata et al. The aforementioned p-type layer formation can effectively suppress the substrate leakage current which mainly causes the short-channel effect, however, the p-type layer which is not completely depleted may increase the parasitic capacitance, as a result, the p-type layer may harm the high speed characteristic of the MESFET. Therefore, it is necessary to form the p-type layer by correctly controlling the profile of the p-type layer, that is, precisely controlling the condition of implantation when implanting the ion. Even if the p-type layer with an ideal profile of the ion is formed by precisely controlling the condition of implantation, there is a problem that it is difficult to control the profile of the p-type layer precisely during the annealing process since it has not been known how the thermal diffusion activates the impurity ion in the annealing process. The p-type layer formation increases the dose of the impurity ion and increases the impurity scattering effect to the electron in the active layer, thereby the electron mobility in the active layer decreases. As a result, there may be a problem that the gradient of the rising part in the static voltage-current characteristic of the MESFET becomes small due to electron mobility in the active layer. On the other hand, the AlGaAs buffer layer formation can effectively suppress the substrate leakage current as well as the p-type layer formation methods. Al x Ga (1-x) As is mixed crystal semiconductor of AlAs and GaAs, various material constant, such as lattice constant, forbidden energy band, and electron affinity etc. can be changed by changing the mole fraction of the mixed crystal semiconductor. In the MESFET with a hetero junction of Al x Ga (1-x) As and GaAs, an ideal hetero interface can be obtained almost without lattice mismatching, since the lattice constant of AlAs is almost similar to the lattice constant of GaAs, wherein the lattice constant of GaAs is 5.65 A, whereas the lattice constant of AlAs is 5.66 A. Therefore, the MESFET with the ideal hetero interface has advantage that increment of the electron scattering due to the lattice mismatching can be prevented. It is necessary to control the thickness of the active layer precisely which is formed by epitaxial growth method, because the threshold voltage of GaAs MESFET depends on the thickness of the active layer. In addition, in order to form a number of MESFETS with a constant threshold voltage in integrated circuits, it is necessary to form the active layer with an uniform thickness over the whole area of a wafer with a large diameter such as 2 inches. However, it is impossible to form the active layer with a uniform thickness over the whole area of a wafer by the prior art. This difficulty is an obstacle to the manufacture of a number of MESFETs having the uniform active layer by an integrated circuit technique. A further difficulty being inherent in the prior art MESFET is in that only one sort of threshold voltage can be obtained in the MESFET with the active layer formed by the conventional epitaxial growth method, for example, only depletion type MESFETs can be provided on one common substate. Therefore, there may be a restriction of the circuit construction and the problem that it is necessary to form a separation between two adjacent elements. In the aforementioned epitaxial growth method, not only the apparatus is very large, but also the production process is very complex, and the throughput is very slow. Therefore, there is the problem that the cost and performance of the MESFET may depend on the epitaxial growth process. Moreover, in an integrated circuit comprising GaAs MESFET, Direct coupled FET logic, which is called "DCFL" below, has been a important device, since the integration density is higher and also the dissipation power is smaller than the other sort of logic circuit. However, the logic swing of the DCFL is limited by the Schottky barrier height of the GaAs MESFET. In a example, the logic swing of the conventional DCFL is only 0.6 V, therefore, the conventional DCFL has a disadvantage that the conventional DCFL becomes unstable by the dispersion of the threshold voltage, as a result, a large scale integrated circuit with the DCFLs can not be provided. In order to obtain a larger logic swing than the DCFL, a few improvements have been developed by circuit techniques such as buffered FET logic and source coupled FET logic. These logic circuits have disadvantages that the dissipation power is high and the number of elements are necessary for fabricating a gate circuit than that of the aforementioned DCFL. Therefore, it is difficult to provide a large scale integrated circuit comprising buffered FET logic, or source couple FET logic. Moreover, recently, it is suggested that a thin active layer with a high impurity concentration is used in order to increase a transconductance gm of the MESFET, however, the thin active layer with a higher impurity concentration leads to an inferior Schottky characteristic since the gate leakage current increases. An essential object of the present invention is to provide a method for the production of MESFETs in which a buffer layer to improve various operation characteristics of the MESFET can easily be provided at a precise level in the substrate. Another object of the present invention is to provide a method for the production of MESFETs which is suitable for fabricating short length MESFETs in the form of a large scale integrated circuit suppressing short-channel effects. According to the invention, there is provided a method for the production of a metal semiconductor field effect transistor comprising steps of: forming a first mask pattern (11) made of at least one material of:resist, SiO₂, Ti, W, Mo, or Ni, on one portion of an upper surface of a semi-insulating semiconductor substrate (1) of GaAs; forming a first layer (2) which will be a buffer layer of Al x Ga (1-x) As in a region of the semi-insulating semiconductor substrate (1) defined by said first mask pattern (11) by selective A1 ion implantation; forming a second layer (3') for an active layer of GaAs in a region of the semi-insulating semiconductor substrate defined by said first mask pattern (11) by selective ion implantation; removing the first mask pattern (11); forming a gate electrode (4) of a metal on the upper surface of the semi-insulating semiconductor substrate (1), wherein the metal is made of a material forming a Schottky contact to GaAs; forming a second mask pattern (12) made of at least one material of: resist, SiO₂, Ti, W, Mo, or Ni on one portion of an upper surface of a semi-insulating semiconductor substrate (1) of GaAs; forming regions (6') for high impurity concentration regions at both sides of the said gate electrode in regions of the semi-insulating semiconductor substrate (1) defined by the second mask pattern (12) by ion implantation; removing the second mask pattern (12); annealing the semi-insulating semiconductor substrate (1) comprising the said first and the said second layers and regions, whereby the said first and the said second layers (3') become the buffer layer (2) of Al x Ga (1-x) As and the active layer (3) of GaAs, respectively, and also the said regions (6') become the high impurity concentration regions (6); and forming a source electrode (8) and a drain electrode (9) on the upper surface of the high impurity concentration regions (6), respectively. For a better understanding of the invention, and to show how the same can be carried into effect, reference will now be made by way of example to the following figures in which: Fig. 1 is a cross sectional view of a first conventional MESFET, Fig. 2 is a cross sectional view of a second conventional MESFET with a p-type layer, Fig. 3 is a cross sectional view of a third conventional MESFET with a buffer layer formed by epitaxial growth method, Figs. 4(A) through 4(H) are cross sectional views showing a production process of a first preferred embodiment of a MESFET with a buffer layer formed under an active layer according to the present invention, Figs. 5(A) through 5(H) are cross sectional views showing a production process of a second preferred embodiment of a MESFET with a buffer layer formed above an active layer according to the present invention, Fig. 6(A) is a schematic potential diagram of a MESFET comprising a n-type GaAs active layer and an Al 0.3 Ga 0.7 As buffer layer, showing a potential barrier at the hetero interface between the active layer and the buffer layer and the carrier confinement effect, and Fig. 6(B) is a schematic potential diagram of a MESFET comprising a p-type GaAs active layer and an Al 0.3 Ga 0.7 As buffer layer, showing a potential barrier at the hetero interface between the active layer and the buffer layer and the carrier confine effect. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Referring to Figs. 4(A) through 4(H), a production process for a first preferred embodiment of a MESFET according to the present invention will be described below, wherein the MESFET has a buffer layer 2 formed between an active layer 3 and a semi-insulating semiconductor substrate 1. First of all, a resist mask pattern 11 is deposited on an upper surface of a semi-insulating semiconductor substrate 1 made of GaAs, except for an area where a MESFET will be formed, by photolithography method, as shown in Fig. 4(A). Next, Al ions are implanted in the substrate 1 through the mask pattern 11 as shown in Fig. 4(B), to make, an ion implanted layer 2' with a predetermined thickness ℓ2 which acts as a buffer layer 2 later in a predetermined depth ℓ3a from the upper surface of the semi-insulating semiconductor substrate 1. The dose of the ion implantation is 2×10¹⁶ cm⁻² and the acceleration energy is 200 keV, and the predetermined depth ℓ3a corresponds to the thickness of the active layer 3 formed later. Subsequently, Si⁺ ions are implanted into the substrate 1 from above through the mask pattern 11 to develop a layer 3' with a predetermined depth ℓ3a as shown in Fig. 4(C) between the upper surface of the semi-insulating semiconductor substrate 1 and the layer 2'. The dose of the Si⁺ ions is 2x10¹² cm⁻² and the acceleration energy is 60 keV. Moreover, the mask pattern 11 is ashed by using O₂ plasma. As shown in Fig. 4(D), after a refractory Schottky contact electrode layer 4' such as WSi with a thickness ℓ4 of approximately 5000 Å using metallic material is formed on the whole upper surface of the semi-insulating semiconductor substrate 1 and above the layer 3' by a known method, a resist mask pattern 5 is formed by photolithography method on one portion of the upper surface of the contact electrode layer 4' at a position above a region where a Schottky gate electrode 4 is formed later. Then, as shown in Fig. 4(E), the Schottky gate electrode 4 is formed by etching the unnecessary parts of the electrode layer 4' using the resist mask pattern 5 by reactive ion etching method. Furthermore, as shown in Fig. 4(F), after a resist mask pattern 12 is deposited on the upper surface of the semi-insulating semiconductor substrate 1 except for a surface area of the MESFET, by photolithography method, Si⁺ ions are implanted from above into the layers 3' using the mask pattern 12 and the Schottky gate electrode 4 so that layers 6' with a predetermined thickness ℓ6a are formed at both sides of the layers 3' below the Schottky gate electrode 4 for providing high impurity concentration layers 6 which will be described later. In a preferred embodiment, the Si⁺ ions are implanted at a dose of 4.0×10¹³ cm⁻² and an acceleration energy of 150 keV. The thickness ℓ6a of the Si⁺ ion implanted layer 6' may be larger than the thickness ℓ3a and smaller than the thickness (ℓ3a + ℓ2). In other word, the Si⁺ ion implanted layers 6' may be formed up to the upper half region of the layer 2'. Then, the resist mask pattern 12 is ashed by using O₂ plasma. Subsequently, as shown in Fig. 4(G), a protective film layer 7 such as a SiN film with a predetermined thickness 7 of approximately 1200 Å is deposited on the upper surface of the semi-insulating semiconductor substrate 1 and on the gate electrode 4 by plasma CVD method, thereafter an activation annealing step is performed in an atmosphere of N₂ gas at 800 o C for 20 minutes, thereby the implanted Si⁺ impurity ions are activated, resulting in layer 3' becoming the GaAs active layer 3 and the layers 6' becoming the high impurity concentration region layers 6. Also the Al ion implanted layer 2' is crystallized. As a result, the buffer layer 2 made of Al x Ga (1-x) As is formed under the GaAs active layer 3 and between both of the high impurity concentration region layers 6. Then, the protective film layer 7 is removed. Finally, after a resist mask pattern (not shown) is deposited by photolithography method on the upper surface of the semi-insulating semiconductor substrate 1 except for a surface area of the source and the drain electrodes 8 and 9, a metal material such as AuGe etc. which is connectable with GaAs by ohmic contact is deposited on the upper surface of the semi-insulating semiconductor substrate 1 using the resist mask pattern as the mask by known method. Subsequently, the unnecessary metal material is removed by lift-off method. Then, the remaining metal material is alloyed by sintering at 400°C for approximately 5 minutes, thereby the source and the drain electrodes 8 and 9 are formed on the required upper surface of the semi-insulating semiconductor substrate 1, resulting in fabricating the MESFET with the Al x Ga (1-x) As buffer layer 2 situated below the active layer 3, as shown in Fig. 4(H). In the aforementioned production process of the first preferred embodiment of the MESFET according to the present invention, the step of the selective Al ion implantation need not be performed after forming the resist mask pattern 11 and before the Si⁺ ion implantation for forming the layer 3', the step of the selective Al ion implantation may be performed before the annealing step shown in Fig. 4(G), and after the Si⁺ ion implantation for forming the layer 3' which wall be the active layer 3 shown in Fig. 4(C), or after the Si⁺ ion implantation for forming the layers 6' which will be the high impurity concentration region layers 6 shown in Fig. 4(F). In the steps of forming the mask patterns 11 and 12, resist is used as the mask pattern, however, the other material such as SiO₂, Ti, W, Mo, or Ni may be used as the mask pattern. In the step of the Al ion implantation, the value x can be changed by changing the dose of the Al ion, thereby the MESFET with the buffer layer of Al x Ga (1-x) As can be fabricated. The value x may preferably be in the range of 0.2 to 0.5, and the value may more preferably be 0.3. In the steps of forming the layers 3' and 6', Si⁺ is used as the impurity ion, however, other impurity ions may be used. Fig. 6(A) and Fig. 6(B) show the potential barrier at the hetero interface between the n-type and the p-type GaAs layers and the Al 0.3 Ga 0.7 As buffer layer and the carrier confinement effect. In Figs. 6(A) and 6(B), Ec1 and Ec2 are the lowest potential of conduction band, Ev1 and Ev2 are the lowest potential of valence band, therefore, the potential difference Eg1 between Ec1 and Ev1 and the potential difference Eg2 between Ec2 and Ev2 are the widths of the forbidden energy band. E F denotes the Fermi energy and x denotes the electron affinity. In the fabricated MESFET with the n-type GaAs active layer 3 and the Al x Ga (1-x) As buffer layer 2, as shown in Fig. 6(A), carrier in the n-type GaAs active layer 3 cannot go to the GaAs semi-insulating semiconductor substrate 1 since the potential barrier is formed between the n-type GaAs active layer 3 and the Al x Ga (1-x) As buffer layer 2, the carrier is confined in the n-type GaAs active layer 3. On the other hand, up to now, an n-type active layer with higher electron mobility has been generally used as active layer of GaAs MESFET, however, GaAs MESFET comprising a p-type active layer has been investigated, to provide future C-MESFET of GaAs (like Si CMOS). In the fabricated MESFET with the p-type active layer 3 and the Al x Ga (1-x) As buffer layer 2, as shown in Fig. 6(B), carriers in the p-type GaAs active layer 3 cannot go to the GaAs semi-insulating semiconductor substrate 1 since the potential barrier is formed between the p-type GaAs active layer 3 and the Al x Ga (1-x) As buffer layer 2, therefore the carriers are confined in the p-type GaAs active layer 3. The aforementioned carrier confinement effect can suppress the aforementioned short-channel effects, and the fabricated MESFET with the buffer layer 2 has more transconductance gm and a higher cut-off frequency f T than the conventional MESFET without the buffer layer 2. Moreover, impurity scattering which is problem when p-type layer is formed is no problem, since Al is neutral type impurity in GaAs. It is said that impurity hardening occurs and dislocation (etch pit) density decreases by Al implantation when GaAs bulk-crystallizes, the annealing process leads to reduction of the dislocation (etch pit) density, thereby dispersion of the threshold voltage may be reduced. Second Embodiment Referring to Figs. 5(A) through 5(H), a production process of a second preferred embodiment of a MESFET according to the present invention will be described below, wherein the MESFET has a buffer layer 10 formed between an active layer 3 and an upper surface of a semi-insulating semiconductor substrate 1. The layer which serves as the Al x Ga (1-x) As buffer layer can be formed in a region near to the upper surface of the semi-insulating semiconductor substrate 1 by selective Al ion implantation at a reduced acceleration energy as compared with the acceleration energy in case of the first preferred embodiment of the MESFET. That is, for example, the distance of the Al ion implantation at an acceleration energy of 20 keV is approximately 250 Å, therefore, the buffer layer can be formed by ion implantation at the smaller acceleration energy. Moreover, the buffer layer can be formed in a region nearer to the upper surface of the semi-insulating semiconductor substrate 1 than the aforementioned region by ion implantation through a proper insulating film layer such as SiN film layer. First of all, as shown in Fig. 5(A), after an insulating film layer 13 with a predetermined thickness ℓ13 of approximately 1000 Å such as SiN film is formed on a whole upper surface of a semi-insulating semiconductor substrate 1 made of GaAs, a resist mask pattern 11 is deposited on one portion of the upper surface of the insulating film layer 13 positioned above a region where a MESFET will not be formed, by photolithography method. Next, as shown in Fig. 5(B), a layer 10' with a predetermined thickness ℓ10 which will be the buffer layer 10 later is formed in a region of the semi-insulating semiconductor substrate 1 under the upper surface of the semi-insulating semiconductor substrate 1 by selective Al ion implantation using the resist mask pattern 11 at a dose of 8x10¹⁶ cm⁻² and an acceleration energy of 30 keV through the insulating film layer 13. Then, as shown in Fig. 5(C), a layer 3' with a predetermined thickness ℓ3b which will be the active layer 3 is formed under the layer 10' by selective Si⁺ ion implantation using the resist mask pattern 11 at a dose of 8×10¹² cm⁻² and an acceleration energy of 60 keV. Moreover, the mask pattern 11 is ashed by using O₂ plasma and the insulating film layer 13 is removed by using buffered HF. Then, as shown in Fig. 5(D), after a refractory Schottky contact electrode material 4' with a thickness ℓ4 of approximately 5000 Å such as WSi is formed on the whole upper surface of the semi-insulating semiconductor substrate 1 and above the layer 10' by a known method, a resist mask pattern 5 is formed on one portion of the upper surface of the metal material 4' positioned above a region where a gate electrode 4 will be formed later by photolithography method. Then, as shown in Fig. 5(E), the Schottky gate electrode 4 is formed by etching the unnecessary electrode material 4' using the resist mask pattern 5 by reactive ion etching method. Furthermore, as shown in Fig. 5(F), after a resist mask pattern 12 is deposited on the upper surface of the semi-insulating semiconductor substrate 1, except for a surface area where the MESFET is formed, by photolithography method, layers 6' with a predetermined thickness ℓ6b, which will be high impurity concentration region layers 6, are formed at the both side of the layer 3' which will be the active layer 3 and under the upper surface of the semi-insulating semiconductor substrate 1 by Si⁺ ion implantation using the resist mask pattern 12 and the gate electrode 4 as a mask at a dose of 4.0×10¹³ cm⁻² and an acceleration energy of 150 keV, wherein the thickness ℓ6b is longer than the thickness ( ℓ10 + ℓ3b ). Then, the resist mask pattern 12 is ashed by using O₂ plasma. As shown in Fig. 5(G), after a protective film layer 7 with a predetermined thickness ℓ7 of approximately 1200Å such as SiN film is deposited on the upper surface of the semi-insulating semiconductor substrate 1 and on the gate electrode 4 by plasma CVD method, an activation annealing is performed in N₂ gas at 800°C for 20 minutes, thereby the implanted Si⁺ impurity ions are activated, the layers 3' and 6' become the GaAs active layer 3 and the high impurity concentration region layers 6, respectively, and also the Al implanted layer 10' are crystallized, as a result, the buffer layer 10 made of Al x Ga (1-x) As is formed under the gate electrode 4 and between both of the high impurity concentration region layers 6. Then, the protective film layer 7 is removed. Finally, after a resist mask pattern not shown is deposited on the upper surface of the semi-insulating semiconductor substrate 1, except for a surface area where the source and the drain electrodes 8 and 9 will be formed later, by photolithography method, a metal material which is connected with GaAs by ohmic contact such as AuGe etc. is deposited on the upper surface of the semi-insulating semiconductor substrate 1 using the resist mask pattern as the mask by known method, the unnecessary metal material which will not be the source and the drain electrodes 8 and 9 is removed by lift-off method. Then, the remaining metal material is alloyed by sintering at 400°C for approximately 5 minutes, thereby the source and the drain electrodes 8 and 9 are formed on the required upper surface of the semi-insulating semiconductor substrate 1, resulting in fabricating the MESFET with the Al x Ga (1-x) As buffer layer 10, as shown in Fig. 5(H). In the aforementioned production process of the second preferred embodiment of the MESFET according to the present invention, the step of the selective Al ion implantation need not be performed after forming the resist mask pattern 11 and before the Si⁺ ion implantation for forming the layer 3', the step of the selective Al ion implantation may be performed after the Si⁺ ion implantation for forming the layer 3' which will be the active layer 3 shown in Fig. 5(C) arid before the gate electrode formation step shown in Fig. 5(D). In the steps of forming the mask patterns 11 and 12, resist is used as the mask pattern, however, other materials such as SiO₂, Ti, W, Mo, or Ni may be used as the mask pattern. In the step of the Al ion implantation, the value x can be changed by changing the dose of the Al ion, thereby the MESFET with the buffer layer of Al x Ga (1-x) As can be fabricated. The value x may preferably be in the range of 0.2 to 0.5, and the value x may more preferably be 0.3. In the steps of forming the layers 3' and 6', Si⁺ is used as the impurity ion, however, other impurity ions may be used. In the fabricated MESFET with the Al x Ga (1-x) As buffer layer 10 formed between the gate electrode 4 and the GaAs active layer 3, the gate potential barrier is higher than the conventional MESFET without the buffer layer 10. Therefore, in the DCFL comprising the fabricated MESFET with the buffer layer 10, a higher logic swing can be applied across the gate electrode 4 and the source electrode 8, and a higher margin for applying the gate voltage can be obtained even if the MESFET has a more dispersion of the threshold voltage than the conventional MESFET without the buffer layer 10, thereby a large scale integrated circuit comprising the MESFET can be obtained. For example, in a 4 kbits static RAM consisted of DCFLs comprising the GaAs MESFETs with a Schottky barrier height of 0.7 V, it is said that less dispersion of the threshold voltage of a normally off type FET may be required than 30 mV in order to obtain a complete memory operation. If the 4 kbits static RAM is consisted of the GaAs MESFET with a Schottky barrier height of 1.1 V, a less dispersion of the threshold voltage of normally off type FET is required than 50 mV in order to enable correct memory operation, therefore, the wider range of the dispersion of the threshold voltage can be obtained than the conventional DCFL comprising the MESFET without the buffer layer 10. In the second preferred embodiment of the MESFET, the Al x Ga (1-x) As buffer layer 10 is formed above the active layer 3 by replacing Al with Ga, the remaining Ga can operate as acceptor, the carrier density on the upper surface of the active layer 3 may be less than the conventional MESFET without the buffer layer 3, thereby the Schottky characteristic may be improved, resulting in the improvement of the MESFET. In the method of the production mentioned above, the position and thickness of the buffer layer of Al x Ga (1-x) As and the active layer of GaAs can be more precisely controlled by selective ion implantation than the conventional epitaxial growth method etc., so that a MESFET with less dispersion of the threshold voltage can be provided. Two type MESFET of enhancement type and depletion type MESFETs can be formed on the same wafer by selectively controlling the dose of impurity ions, thereby the production method of the MESFET is suitable for a production method of a large scale integrated circuit. Furthermore, the buffer layer formation of Al x Ga (1-x) As under the active layer GaAs can suppress the short-channel effects. Moreover, the buffer layer formation of Al x Ga (1-x) As above the active layer GaAs can obtain a higher gate barrier height and a less gate leakage current of the MESFET than the conventional MESFET without the buffer layer, resulting in a Schottky characteristic improvement.

Claims: A method for the production of a metal semiconductor field effect transistor comprising steps of: forming a first mask pattern (11) made of at least one material of: resist, SiO₂, Ti, W, Mo, or Ni, on one portion of an upper surface of a semi-insulating semiconductor substrate (1) of GaAs; forming a first layer (2) which will be a buffer layer of Al x Ga (1-x) As in a region of the semi-insulating semiconductor substrate (1) defined by said first mask pattern (11) by selective Al ion implantation; forming a second layer (3') for an active layer of GaAs in a region of the semi-insulating semiconductor substrate defined by said first mask pattern (11) by selective ion implantation; removing the first mask pattern (11); forming a gate electrode (4) of a metal on the upper surface of the semi-insulating semiconductor substrate (1), wherein the metal is made of a material forming a Schottky contact to GaAs; forming a second mask pattern (12) made of at least one material of: resist, SiO₂, Ti, W, Mo, or Ni on one portion of an upper surface of a semi-insulating semiconductor substrate (1) of GaAs; forming regions (6') for high impurity concentration regions at both sides of the said gate electrode in regions of the semi-insulating semiconductor substrate (1) defined by the second mask pattern (12) by ion implantation; removing the second mask pattern (12); annealing the semi-insulating semiconductor substrate (1) comprising the said first and the said second layers and regions, whereby the said first and the said second layers (3') become the buffer layer (2) of Al x Ga (1-x) As and the active layer (3) of GaAs, respectively, and also the said regions (6' ) become the high impurity concentration regions (6); and forming a source electrode (8) and a drain electrode (9) on the upper surface of the high impurity concentration regions (6), respectively. A method for the production of a metal semiconductor field effect transistor as defined in claim 1, wherein the said first layer is formed by a selective Al ion implantation at a dose of 2×10¹⁶ cm⁻² and an acceleration energy of 200 keV, the said second layer is formed by a selective Si⁺ ion implantation at a dose of 2×10¹² cm⁻² and an acceleration energy of 60 keV, the said regions are formed by Si⁺ ion implantation at a dose of 4×10¹³ cm⁻² and an acceleration energy of 150 keV, and the said semi-insulating semiconductor substrate comprising the said first and the said second layers and regions is annealed in N₂ gas at 800°C for 20 minutes, whereby the said buffer layer of Al x Ga (1-x) As is formed under the said active layer of GaAs. A method for the production of a metal semiconductor field effect transistor as defined in claim 2, wherein x is in the range of 0.2 to 0.5. A method for the production of a metal semiconductor field effect transistor as defined in claim 2, wherein x is 0.3. A method for the production of a metal semiconductor field effect transistor as defined in claim 1 further comprising the steps of: depositing a film layer of SiN with a thickness of approximately 100 nm on the upper surface of the semi-insulating semiconductor substrate before forming the said first mask pattern; and removing the said film layer of SiN after forming the said first and the said second layers and before forming the said gate electrode, wherein: the said first layer is formed by a selective Al ion implantation at a dose of 8x10¹⁶ cm⁻² and an acceleration energy of 30 keV; the said second layer is formed by a selective Si⁺ ion implantation at a dose of 8x10¹² cm⁻² and an acceleration energy of 60 keV; the said regions are formed by Si⁺ ion implantation at a dose of 4x10¹³ cm⁻² and an acceleration energy of 150 keV; and the said semi-insulating semiconductor substrate comprising the said first and the second layers and the said regions is annealed in N₂ gas at 800 o C for 20 minutes, whereby the said buffer layer of Al x Ga (1-x) As is formed above the active layer of GaAs. A method for the production of a metal semiconductor field effect transistor as defined in claim 5, wherein x is in the range of 0.2 to 0.5. A method for the production of a metal semiconductor field effect transistor as defined in claim 6, wherein x is 0.3.

Inventors: NAKAJIMA, SHIGERU C/O OSAKA WORKS OF SUMITOMO
Applicants: SUMITOMO ELECTRIC INDUSTRIES LIMITED
Application year: 1986
Main classification: H01L21
IPC codes: H01L21, H01L29