PROTECTED MOS TRANSISTOR CIRCUIT

Abstract: This protected MOS transistor circuit has p-type semiconductor substrate , power terminal (VSS), input MOS transistor (32), resistor (38B) connected to the gate electrode of transistor (32), and MOS tran­ sistor (40) which has a gate electrode connected to ter­ minal (VSS) and a current path connected between power terminal (VSS) and the junction of resistor (38B) and the gate electrode of input MOS transistor (32). This protected MOS transistor circuit further has resistor (38A) connected in series with resistor (38B), and pn-­ junction diode (42) connected reversely between terminal (VSS) and the junction between resistors (38A and 38B).

Description: The present invention relates to a protected MOS transistor circuit and, more particularly, to a MOS transistor integrated circuit having a protecting cir­ cuit for obviating rupture of the gate oxide of the MOS transistor on the same semiconductor substrate. It is known that a relatively high voltage supplied to the gate of a MOS transistor becomes a cause of the rupture of a gate oxide. This rupture causes a per­ manent electrical short between the gate and the substrate on which the MOS transistor is formed. Fig. 1 shows a conventional input protecting cir­ cuit for a MOS transistor integrated circuit. This pro­ tecting circuit protects the gate oxide of input MOS transistor 10 of the integrated circuit against rupture due to a surge voltage. For example, in a defect in­ spection process, the input terminal 12 of the integ­ rated circuit accidentally receives a surge voltage from something charged, for example, to 2000 to 3000 V. Therefore, this protecting circuit is provided in the front stage of input MOS transistor 10. As shown in Fig. 1, this protecting circuit has resistor 14 connected between the gate of MOS tran­ sistor 10 and input terminal 12. Resistor 14 is formed, for example, of a polycrystalline silicon layer formed over a semiconductor substrate through a field oxide film of 0.6 µm interposed therebetween or a diffused layer formed in the substrate and has resistance R. The protecting circuit further has MOS transistor 16 having the same characteristics as MOS transistor 10. The gate of transistor 16 and and one end of a current path are connected to power terminal VSS set to a reference poten­ tial. The other end of the current path of transistor 16 is connected to junction 18 between resistor 14 and the gate of transistor 10. A wiring for connecting resistor 14 to transistor 10 is insulatively formed on a semiconductor substrate to form a parasitic capacitance C together with the substrate. The resistance R of resistor 14 and the parasitic capacitance C form a time constant circuit of time constant τ = CR. The voltage of junction 18, i.e., the gate potential of transistor 10 gradually varies due to the time constant circuit after the surge voltage is supplied to terminal 12. Transistor 16 is conducted when the potential variation arrives at a predetermined level. At this time, a punch-through current or a sur­ face breakdown current flows from junction 18 to power terminal VSS to cause the charge stored in capacitance C to discharge. The voltage variation of the gate of tran­ sistor 10 is saturated at sufficiently low level as com­ pared with the peak value of the surge voltage. Thus, the gate oxide of transistor 10 is not applied from the gate with a high electric field, to prevent its rupture. However, the construction of the conventional input protecting circuit is not suitable for further micromi­ niaturization of the MOS transistors of the integrated circuit. The microminiaturization has the undesired effect that it can interfare with the task of bringing the circuit constants of the protecting circuit to suitable values. Fig. 2 shows an equivalent circuit of the protect­ ing circuit in Fig. 1. Resistor 20 shown in Fig. 2 corresponds to transistor 16 in a conductive state and has spreading resistance Rb. Resistance Rb is specified according to the substrate in which the MOS transistor integrated circuit is formed. The electric field intensity in the gate oxide of the MOS transistor depends upon the gate voltage of the MOS transistor and the thickness of the gate oxide. It is known that rupture of the gate oxide normally occurs at the electric field intensity higher than 7 or 8 MV/cm. When the gate oxide of transistor 10 is reduced to the thickness, for example, of 0.02 µm to 0.03 µm by microminiaturization, the gate voltage of transistor 10 is limited to 30 V, at the maximum, to avoid rupture of the gate oxide. The gate voltage of transistor 10 in the steady state is ordinarily repre­ sented by the following equation (1): VC = (Rb/R + Rb)VO ... (1) where VO is a surge voltage applied to input terminal 12. Since it is not possible to vary the value of resistance Rb when setting the VC under necessary con­ ditions for preventing the gate oxide of transistor 10 from rupturing, resistance R must be increased as com­ pared with that value it would have had before the micro­ miniaturization. However, the increase in resistance R is not preferred, due to the decrease in the response speed when the integrated circuit is operated, and causes the following disadvantages. The voltage drop across resistor 14 increases proportionally to resistance R. Thus, when resistor 14 is formed of a polycrystalline silicon layer, an insulation breakdown might occurs in a field oxide film under the polycrystalline silicon layer. On the other hand, when resistor 14 is formed of a diffused layer, there might also be a junction break­ down between the diffused layer and the semiconductor substrate. Particularly in case of the junction break­ down, it can occur at a voltage drop lower than that in case of the insulation breakdown. The value of resistance R of resistor 14 which can firmly prevent the gate oxide of transistor 10 from rup­ turing will be designated. For example, when a surge voltage is 3000 V, spreading resistance Rb is 50 ohms and the gate voltage of transistor 10 is 20 V, resistance R is necessarily 7.45 kΩ or higher, as per equation (1). On the other hand, the value of resistance R of resistor 14 which can reliably prevent a field oxide film from insulatively breaking down will be designated. For example, when the upper limit of an applying voltage, capable of holding the electric field intensity between the field oxide films of 0.6 µm less than 7 MV/cm, is 400 V from the MIL standard test, the resistance is necessarily 1 KΩ or less. As a result, when resistance R is set to 7.45 kΩ or higher in order to effectively obviate the rupture of the gate oxide of transistor 10, the field oxide film insulatively breaks down. On the contrary, when resist­ ance R is set to 1 kΩ or lower in order to reliably prevent the field oxide film from insulatively breaking down, rupture of the gate oxide of transistor 10 occurs. If the voltage of junction 18 in not sufficiently re­ duced, not only the possibility of rupture of the gate oxide of transistor 10 occurs, but also, the surge with­ standing voltage of transistor 16 decreases. Fig. 3 is an equivalent circuit of a testing cir­ cuit of MIL standards. This testing circuit has resis­ tor 22 of 1.5 kΩ and capacitor 24 of 100 pF, which are connected in series between terminal 12 and terminal VSS in the test operation. Capacitor 24 is charged while switch 26 is opened. The charge stored in capacitor 24 is applied as a surge voltage to terminal 12 at the moment that switch 26 is closed. The MIL standards prove a sufficient practical use if the integrated cir­ cuit has a surge withstanding voltage of 1200 V. An object of the present invention is to provide a protected MOS transistor circuit which can firmly pre­ vent the rupture of the gate oxide of an input MOS transistor without causing trouble to an input protecting circuit and is also suitable for microminiaturization. According to the present invention, there is pro­ vided a protected MOS transistor circuit comprising a semiconductor substrate, a reference terminal set to the substrate potential, an input terminal supplied with an input voltage, an input MOS transistor having a gate electrode insulatively formed over the substrate, first and second resistors insulatively formed over the substrate and connected in series between the input ter­ minal and the gate electrode of the input MOS tran­ sistor, a first diode reversely connected between the reference terminal and the node of the second resistor and the gate electrode, and a second diode reversely connected between the reference terminal and the node of the first resistor and the second resistors. This invention can be more fully understood from the following detailed description when taken in con­ junction with the accompanying drawings, in which: Fig. 1 shows a conventional input protecting cir­ cuit for a MOS transistor integrated circuit; Fig. 2 shows an equivalent circuit of the input protecting circuit shown in Fig. 1; Fig. 3 shows an equivalent circuit of a testing circuit used for the surge withstanding test of the input protecting circuit in Fig. 1; Fig. 4 shows a protected MOS transistor integrated circuit according to one embodiment of the present invention; Figs. 5 and 6 are views showing an equivalent cir­ cuit of the protected MOS transistor integrated circuit in Fig. 4 for describing the operating state of the input protecting circuit of the integrated circuit; Fig. 7 shows a plane pattern of a diode in Fig. 4; Fig. 8A shows the sectional construction of a diode in Fig. 4; Fig. 8B shows the sectional construction of the diode-connected MOS transistor in Fig. 4; Fig. 9 shows a diode of a plane pattern different from the diode in Fig. 4; and Fig. 10 shows a protected MOS transistor integrated circuit according to another embodiment of the present invention having two pn-junction diodes. One embodiment of the present invention will now be described with reference to Fig. 4. Fig. 4 is a circuit diagram of a protected MOS transistor integrated circuit. The integrated circuit has function unit 30 formed on a single semiconductor substrate (not shown) such as a P-­ type silicon substrate. Unit 30 has a plurality of MOS transistors interconnected to obtain the desired func­ tion. The MOS transistors have, for example, gate oxides of 0.02 µm. Each MOS transistor has a source and drain formed in a depth of about 0.3 µm in the substrate. Input MOS transistor 32, shown in Fig. 4, is one of these MOS transistors. The gate of transistor 32 is connected to input terminal 36 through protecting cir­ cuit 34 to receive an input signal used in unit 30. Protecting circuit 34 is provided to protect the gate oxide of transistor 32 from rupture when a surge voltage such as, for example, 3000 V is momentarily applied to terminal 36. Circuit 34 has resistors 38A, 38B, 38C connected in series between terminal 36 and the gate of transistor 32. More particularly, one end of resistor 38A is connected to terminal 36, and the other end is connected through resistor 38B to one end of resistor 38C. The other end of resistor 38C is con­ nected to the gate of transistor 32. Each of resistors 38A to 38C is formed of a polycrystalline silicon layer which is formed over the substrate through a field oxide film interposed therebetween. The field oxide film has a thickness of about 0.1 µm. Resistor 38A is set, for example, to a resistance of 1 kΩ in a range of 500 Ω to 1.5 kΩ. Resistor 38B is set, for example, to a resist­ ance of 250 Ω in a range of 100 Ω to 300 Ω. Resistor 38C is set, for example, to a resistance of 100 Ω to 200 Ω. Protecting circuit 34 further has MOS transistor 40 having the same construction as transistor 32, and pn-junction diode 42. The gate and one end of the current path of transistor 40 are connected to power terminal VSS, set to reference potential equal to the substrate potential. The other end of the current path of transistor 40 is connected to node 44 between resis­ tor 38B and resistor 38C. The cathode of diode 42 is connected to node 46 between resistor 38A and resistor 38B, and the anode is connected to terminal VSS. Tran­ sistor 40 has, similarly to transistor 32, n-type dif­ fused regions formed in p-type silicon substrate in a depth of about 0.3 µm. Diode 42 has an n-type diffused region formed in the substrate in a depth deeper than the diffused regions of transistors 32, 40. The depth of the n-type diffused region is set to 0.5 µm to 2.0 µm. The n-type diffused region contacts with the p-type sub­ strate so as to form the contact area of 2000 µm² to 3000 µm². Thus, diode 42 has a higher breakdown voltage than transistor 40. Fig. 5 is an equivalent circuit after transistor 40 and pn-junction diode 42 are conducted. Resistors 40A, 42A shown in Fig. 5 respectively represent spreading resistances in the substrate. Resistor 40A is connected between node 44 and the substrate, and resistor 42A is connected between node 46 and the substrate. When terminal 36 receives surge voltage VO, voltage VO is divided in accordance with the resistances of resistors 38A, 38B, 42A, 40A and applied to node 44 as voltage VC. Now, the value of voltage VC will be obtained by calculation. Assume that the current flowing in resis­ tor 38A is I, the current flowing in resistor 42A, is I1, the current flowing in resistor 40A is I2, the resistan­ ces of resistors 38A, 38B are respectively R1, R2, and the resistances of resistors 42A, 40A are respectively Rb. Current I2 is equal to the value produced by dividing voltage VC of node 44 by resistance Rb of resistor 40A and represented by the following equation (2): I2 = VC/Rb ... (2) The voltage drop of resistor 42A is equal to that in a series circuit of resistor 38B and resistor 40A, and the following equation (3) is formed: Rb·I1 = (R2+Rb)I2 ... (3) Current I is equal to the value produced by dividing surge voltage VO by the combined resistance of resistors 38A, 38B, 42A, 40A and represented by the following equation (4): I = VO/(R1+(Rb(R2+Rb)/Rb+(R2+Rb))) ... (4) Since current I is branched to currents I1 and I2, the following equation is satisfied: I = I1+I2 ... (5) The case where resistor 38A is 1 kΩ, surge voltage VO is 3000 V, resistors 42A, 40A are set to 50 Ω, and voltage VC is set to 20 V for firmly preventing the rup­ ture of the gate oxide of transistor 32 will now be con­ sidered. The resistance R2 of resistor 38B in this case will be obtained: When 50 Ω is substituted for Rb and 20 V is sub­ stituted for VC in the equation (2), the following equation (6) is obtained: I2 = 20/50 = 0.4 [A] ... (6) Further, the value of current I2 obtained in the equation (6), i.e., 0.4 A and 50 Ω of Rb are substituted in the equation (3), current I1 is represented by the following equation (7): I1 = (0.4/50) (R2+50) ... (7) I1 of the equation (7) and I of the equation (4) are substituted for the equation (5), the following equation (8) is obtained: (0.4/50) (R2+50)+0.4 = 3000/(1000+(50/(R2+50)/50+(R2+50)) ... (8) In the equation (8), (R2+50) is substituted by γ, the equation (8) can be represented as below: (0.4/50)γ+0.4 = 3000/(1000+(50γ)/50+γ) ... (9) The equation (9) can be represented as the following quadratic equation with respect to γ: 8.4γ²-2180γ-13000 = 0 ... (10) When the equation (10) is solved with respect to γ, γ has the value of about 309.5. Resistance R2 is equal to the value produced by subtracting this value by 50, and is resultantly 259.5 Ω. Thus, the resistance of resistor 38B in Fig. 4 is set to 250 Ω, near this value. Therefore, if the surge voltage of 3000 V is applied to terminal 36 when resistances R1, R2 of resistors 38A, 38B are respectively set to 1 kΩ, 250 Ω, voltage VC of node 44 is limited to a sufficiently low value. Thus, the gate oxide of the transistor is protected against rupture. Fig. 6 is an equivalent circuit when transistor 40 and diode 42 are nonconductive. In Fig. 6, capacitor C1 represents the parasitic capacitance of node 46, which mainly depends on the junction capacitance between the diffused region of diode 42 and the substrate. Capa­ citors C2, C3 respectively represent the parasitic capa­ citances of nodes 44 and 48. The capacitance of node 48 mainly depends on the gate capacitance of transistor 32. In the embodiment described above, diode 42 has a diffused region deeper than that corresponding to the source and drain of transistor 32. Therefore, diode 42 is stronger than transistor 32 against junction break­ down. Though higher voltage than in node 44 is applied to node 46, this voltage cannot cause breakdown of the pn-junction of diode 42. Since diode 42 has a sufficiently large junction area, capacitor C1 has a larger capacitance. Therefore, capacitor C1 effectively reduces the peak voltage of node 46 in cooperation with resistor 38A. Further, since the capacitance of capacitor C1 is large, resistor 38A can be set to a relatively small resistance. There­ fore, an input signal is not remarkably delayed due to an excessively large time constant in this portion when the integrated circuit is operated. The peak voltage of node 44 is similarly effec­ tively reduced in cooperation with resistor 38B and capacitor C2, and the peak voltage of node 48 is effec­ tively reduced in cooperation with resistor 38C and capacitor C3. In other words, protecting circuit 34 can effectively prevent the rupture of the gate oxide of transistor 32 without disturbing the high speed opera­ tion of the integrated circuit. In the embodiment described above, resistor 38A is formed not of the diffused layer formed in the semicon­ ductor substrate but of the polycrystalline silicon layer formed through a field Oxide film on the substrate. The reason is as will be described below. Resistor 38A directly receives a surge voltage applied to terminal 36. The breakdown voltage of pn-junction is in general low. Thus, when resistor 38A is formed of the diffused layer, a breakdown current is initially flowed through the diffused layer from input terminal 36 to the sub­ strate when a surge voltage is supplied to the input terminal. Since this current is concentrated to a spe­ cific part of the junction between the diffused layer and the substrate, the junction of this portion is readily broken down. Once the rupture occurs, the dif­ fused layer cannot serve as resistor 38A. On the other hand, when resistor 38A is formed of the polycrystalline silicon layer and a relatively thick field oxide film is interposed between the polycrystalline silicon layer and the substrate, resistor 38A has sufficiently high withstanding voltage as compared with the case that it is formed of the diffused layer. Fig. 7 shows a plane pattern of a diode 42 of the above-mentioned embodiment. Fig. 8A shows a sectional construction of diode 42, and Fig. 8B shows a sectional construction of transistor 40. N-type diffusion region 50 shown in Fig. 8A is formed in depth D1 in p-type semiconductor substrate 52 to form a diode 42 in cooperation with substrate 52. On the other hand, n-type diffusion regions 54A, 54B in Fig. 8B are formed in depth D2 in substrate 52 to form source and drain of transistor 40. Depth D1 is set to a value larger than depth D2. Impurity-doped polycrystal­ line silicon layer 56 is formed by depositing on region 50 and field oxide film 58. Layer 56 is patterned as resistors 38A, 38B as shown in Fig. 7, and layer 56 is provided with a resistance capable of directly contact­ ing layer 50. Remaining layer 56 is also used as the gate electrodes of transistors 40 and 32 and resistor 38C as shown in Fig. 8B. Region 50 has a substantially square shape in a plane as shown in Fig. 7. Region 50 has length L in direction X from terminal 36 toward transistor 32 and length W in direction Y perpendicular to the direction X. In the embodiment described above, length L is set to a value shorter than length W. In this case, an electric field concentrated to diode 42 is alleviated to improve the breakdown withstanding voltage. Fig. 9 is an application example of diode 42 in Fig. 4. In Fig. 9, length L of diffused layer 50 is equal to or longer than length W. In this case, the parasitic capacitance and the parasitic resistance due to the pn-junction of diode 42 are provided to protect circuit 34 in a distributed constant manner. When a surge voltage is applied to one end of the layer 56 in direction X, the peak value of the surge voltage is gradually reduced in accordance with the distance from the end of layer 56. The charge is effectively dis­ charged from the polycrystalline silicon layer to the substrate. According to the embodiment described above, when a surge voltage is applied to the input terminal, the voltage applied to the gate of the input transistor con­ nected to the terminal can be reduced without rupture of the input protecting circuit itself, thereby improving the surge withstanding voltage. Further, the input surge of high voltage can be sufficiently suppressed without deteriorating the response characteristic of the integrated circuit. The present invention is not limited to the par­ ticular embodiments described above. Various other changes and modifications may be made within the spirit and scope of the present invention. For example, in the embodiments described above, transistor 40 is used as a protecting element. However, a gate control diode having no source nor drain of the MOS transistor may be used. Further, transistor 40 may be substituted for pn-­ junction diode 60 of the same construction as diode 42 as shown in Fig. 10. According to the present invention as described above, in the semiconductor integrated circuit having the input protecting circuit, the voltage applied to the gate of the input transistor connected to the input ter­ minal can be reduced without rupture of the input pro­ tecting circuit itself when a surge voltage is applied to the input terminal, thereby improving the surge withstand voltage.

Claims: 1. A protected MOS transistor circuit comprising: a semiconductor substrate (52), a reference terminal (VSS) set to the substrate potential, an input terminal (36) supplied with an input voltage, an input MOS transistor (32) having a gate electrode (56) insulatively formed over said substrate (52), resistive means insulatively formed over said substrate (52) and connected between said input terminal (36) and the gate electrode of said input MOS transistor (32), and discharge means connected between the reference terminal (VSS) and the gate of said input MOS transistor (32), characterized in that said resistive means includes first and second resistors connected in series between said input ter­ minal (36) and the gate of said input MOS transistor (32) and said discharge means includes first diode means (40; 60) reversely connected between said reference ter­ minal (VSS) and the node of said second resistor (28B) and the gate of said input MOS transistor (32) second diode means (42) reversely connected between said refer­ ence terminal (VSS) and the node of said first and second resistors (28A, 28B). 2. A protected MOS transistor circuit according to claim 1, characterized in that said second diode means (42) comprises a threshold voltage higher than said first diode means. 3. A protected MOS transistor circuit according to claim 2, characterized in that said first diode means is a MOS transistor (40) having source and drain regions formed in the first depth in said substrate (52), and a gate electrode formed insulatively over said substrate (52) and connected to a reference terminal (VSS). 4. A protected MOS transistor circuit according to claim 3, characterized in that said second diode means is a pn-junction diode (42) having a diffusion region (50) formed in a second depth deeper than the first depth in said substrate (52). 5. A protected MOS transistor circuit according to claim 4, characterized in that said resistive means includes a third resistor (38C) connected between said second resistor and the gate electrode of the input MOS transistor (32). 6. A protected MOS transistor circuit according to claim 5, characterized in that said first resistor is formed of an impurity-doped polycrystalline silicon layer (56). 7. A protected MOS transistor circuit according to claim 5, characterized in that said first, second and third resistors are formed of a single polycrystalline silicon layer (56). 8. A protected MOS transistor circuit according to claim 4, characterized in that said first resistor is set to resistance of 500 Ω to 1.5 kΩ, said second resis­ tor is set to resistance of 100 to 300 Ω, and said pn-­ junction diode includes a diffusion region of the depth of 0.5 µm to 2.0 µm and a pn-junction area of 2000 µm² or larger.

Inventors: ARIIZUMI, SHOJI PATENT DIVISION, KONDO, TAKEO PATENT DIVISION, MASUOKA, FUJIO PATENT DIVISION, SEGAWA, MAKOTO PATENT DIVISION, SUZUKI, YOUICHI PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L27
IPC codes: H01L27, H02H7, H03F1, H01L29