SEMICONDUCTOR INTEGRATED CIRCUIT

Abstract: In a semiconductor integrated circuit (10) comprising an internal circuit (9), an oscillating circuit (1) generating a basic clock signal for operating the internal circuit (9) when the internal circuit is operated in a usual mode, a pair of terminals (Toscin, Toscout) connected to the input side and output side of the oscillating circuit (1), respectively, an oscillator (8) being connected between the above pair of terminals (Toscin, Toscout) when the internal circuit (9) is operated in a usual mode, a reset terminal (Treset) through which a reset signal for resetting the internal circuit is supplied from outside the integrated circuit (10) to the internal circuit, and a test circuit (3, 4, 5) for operating the internal circuit (9) in a test mode; the test circuit supplies a clock signal for testing from outside the integrated circuit to the internal circuit (9) through one of the above pair of terminals (Toscout) when signals of a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals (Toscin) and the reset terminal (Treset).

Description: The present invention relates to a semiconductor integrated circuit , more particularly, but not necessarily exclusively, a DTMF (dual tone multi frequency)/pulse dialer for use in a telephone circuit. Generally, a semiconductor integrated circuit used as a DTMF/pulse dialer comprises an internal circuit having a circuit for a DTMF dialer and a circuit for a pulse dialer, and an oscillating circuit generating a fundamental or basic clock signal for operating the internal circuit when the internal circuit is operated in a usual mode. Further, the semiconductor integrated circuit has a predetermined number of pins (for example, eighteen) each of which functions as a terminal. In this connection, the pins are provided for several purposes: i.e., input pins for supplying input signals from a keyboard or keypad to the internal circuit in accordance with the operation of the keys provided on the keyboard; output pins for transmitting output signals from the internal circuit to a switching system; a pair of pins for the oscillating circuit which are connected to the input side and output side of the oscillating circuit respectively; a pin for supplying an external reset signal to the internal circuit; and a pair of pins for supplying power from power source to the semiconductor integrated circuit. The internal circuit operates as a DTMF dialer or as a pulse dialer selectively, in accordance with a control signal input to one of the input pins. When the internal circuit operates as the DTMF dialer, the signal output from the internal circuit is an analog signal including frequency components corresponding to the operated key. Namely, the frequency components are determined in accordance with the position (i.e., the row and the column) on the keyboard or keypad where the operated key is arranged. Thus, an analog signal sequentially including the frequency components in accordance with the sequentially operated keys is output from one of the output pins and transmitted to the switching system. In this connection, the operational speed of the DTMF dialer is high, and the circuit for the DTMF dialer provided in the internal circuit is operated by receiving the fundamental clock signal, the frequency of which is a high value of, for example, 3.58 m.c. (megacycles) (3.58 MHz), from the above-mentioned oscillating circuit. Contrary to this, when the internal circuit operates as the pulse dialer, the signal output from the internal circuit is a digital signal including a number of pulses which corresponds to the number indicated on the operated key. Thus, if three keys, numbered "1", "2", and "0", are sequentially operated, for example, a digital signal as shown in Fig. 4 is output from one of the output pins and transmitted to the switching system. In this connection, the operational speed of the pulse dialer is low compared to the operational speed of the DTMF dialer. As an explanation of this phenomenon regarding the signal shown in Fig. 4, each of the time lengths of the predigital pause t₁ and the interdigital pause t₂ is set to about 1 s. (sec), and the cycle time of one pulse t₃ is set to about 100 ms. (milli-sec). Therefore, it is necessary to operate the circuit for the pulse dialer provided in the internal circuit by using the clock signal, the frequency of which is a low value of, for example, 2 kc (kilocycles) (2 kHz). However, as described above, the frequency of the fundamental clock signal generated from the oscillating circuit is set to the high value of, for example, 3.58 MHz, in order to operate the circuit for the DTMF dialer in the internal circuit. Therefore, it is necessary to supply the clock signal to the circuit for the pulse dialer in the internal circuit by dividing the frequency of the fudamental clock signal, generated from the oscillating circuit, through a frequency divider. Under the above-mentioned background, for known circuits, when the tests of the functions of the internal circuit (especially the functions of the circuit for the pulse dialer in the internal circuit) are carried out, the above-mentioned clock signal obtained by dividing the frequency of the fundamental clock signal generated from the oscillating circuit is also used as the clock signal for testing. In this connection, it is necessary to perform several kinds of tests in order to test the functions of the internal circuit. Namely, it is necessary to test the function of each key in the DTMF dialer mode and in the pulse dialer mode by testing each key to determine whether or not the correct signal corresponding to the operated key is output from the predetermined output pin. In addition, it is also necessary to test the function of a redial key by determining whether or not the correct signal is output again when the redial key is operated. However, in a known circuit,as the internal circuit (especially the circuit for the pulse dialer) is operated by the above-mentioned clock signal, the frequency of which is divided through the frequency divider, in the test mode as well as in the usual mode, a problem arises in that a long time is needed to perform the several tests as mentioned above and, as a result, the efficiency of production is remarkably lowered, especially when the tests of the functions of the internal circuit are carried out during the process of mass production. To solve this problem, consideration has been given to providing an exclusive terminal for testing besides the above-mentioned generally existing pin terminals and to supplying a clock signal for testing to the internal circuit through that exclusive terminal. However, in this case it becomes necessary to provide an additional pin terminal for testing on each chip and, as a result, the size of the device is increased. GB-A-2 060 958 discloses a semiconductor integrated circuit in which a square-wave generator supplies equifrequency clock signals, two of which are switchably connected to an internal circuit. An external terminal is provided for applying test signals which can be switchably connected to the internal circuit in place of the internally-generated clock signals. The integrated circuit is used, for example, in an electronic clock. According to the present invention, there is provided a semiconductor integrated circuit comprising:- an internal circuit; an oscillating circuit for generating a basic clock signal for operating said internal circuit when said internal circuit is operated in a usual mode; a frequency divider for dividing the basic clock signal, provided between said internal circuit and said oscillating circuit; a pair of terminals respectively connected to an input side and an output side of said oscillating circuit, an external oscillator being connected between said pair of terminals when said internal circuit is operated in a usual mode; said semiconductor integrated circuit being characterized in that said circuit is further provided with a test circuit for operating said internal circuit, said test circuit comprising a switching circuit which selectively closes a first signal path supplying said basic clock signal to said internal circuit through said frequency divider in a usual mode or a second signal path supplying an external clock signal for testing, provided from a signal source separate from said oscillating circuit to said internal circuit, directly in a test mode. An embodiment of the present invention may allow testing of the functions of an internal circuit in a semiconductor integrated circuit at a high speed and thereby shorten the time for testing, without providing an additional terminal for testing but by using only generally existing terminals (namely, a reset terminal and a pair of terminals for the oscillating circuit). According to an embodiment of the present invention, there is provided a semiconductor integrated circuit comprising an internal circuit; an oscillating circuit generating a fundamental clock signal for operating the internal circuit when the internal circuit is operated in a usual mode; a pair of terminals connected to the input side and output side of the oscillating circuit respectively, an oscillator connected between the above pair of terminals when the internal circuit is operated in the usual mode; a reset terminal through which a reset signal for resetting the internal circuit is supplied from outside of a chip to the internal circuit; and a test circuit for operating the internal circuit in a test mode, the test circuit supplying a clock signal for testing from outside of the chip to the internal circuit through one of the above pair of terminals when signals having a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals and the reset terminal. An embodiment of the present invention may provide a semiconductor integrated circuit having a test circuit for testing an internal circuit; more particularly, a semiconductor integrated circuit having a test circuit for a high-speed testing of the functions of the internal circuit. One of the uses to which such a semiconductor integrated circuit may be put is as a DTMF (dual tone multi frequency)/pulse dialer provided in a telephone circuit; the dialer having two circuits, namely, a circuit for the DTMF dialer and a circuit for the pulse dialer, on one chip, and performing two functions selectively, namely, the functions of a DTMF dialer and the functions of a pulse dialer. According to the above construction of the present invention, it is possible to carry out the test for the internal circuit at a high speed by directly supplying the clock signal having the predetermined frequency from outside of the chip to the internal circuit through one of a pair of terminals for the oscillating circuit (a terminal connected to the output side of the oscillating circuit, for example), when signals having a predetermined level are supplied from outside the chip to the test circuit through each of the other one of the above pair of terminals (a terminal connected to the input side of the oscillating circuit, for example) and the reset terminal. Reference is made, by way of example, to the accompanying drawings, in which: Figure 1 is a circuit diagram illustrating an example of a known semiconductor integrated circuit; Fig. 2 is a circuit diagram illustrating one embodiment of the semiconductor integrated circuit according to the present invention; Fig. 3 is a circuit diagram illustrating an example of the switching circuit provided in the semiconductor integrated circuit shown in Fig. 2; and Fig. 4 is a diagram illustrating an example of the wave form of the output signal output from the internal circuit provided in the semiconductor integrated circuit shown in Fig. 2. In order to clarify the background of the present invention, an example of a known semiconductor integrated circuit such as the above-mentioned DTMF/pulse dialer, is shown in Fig. 1. In Fig. 1, reference numeral 1 is an oscillating circuit which generates a fundamental or basic clock signal having a frequency of, for example, 3.58 MHz. Reference numeral 2 is a frequency divider which divides the frequency of the fundamental clock signal generated from the oscillating circuit 1, and this frequency-divided clock signal is supplied through the signal path P to the internal circuit 9 to operate the circuit such as the pulse dialer provided in the internal circuit 9. The fundamental clock signal generated from the oscillating circuit 1 also is directly supplied through the signal path Q to the internal circuit 9 to operate the circuit such as the DTMF dialer provided in the internal circuit 9. Reference numeral 10' designates a chip on which the semiconductor integrated circuit comprising the above-mentioned oscillating circuit 1, frequency divider 2, a feedback resister 63, and internal circuit 9 are provided. A predetermined number of pin terminals are provided on the chip 10', and only three pin terminals (i.e., a reset terminal Treset and a pair of terminals Toscin and Toscout each of which is connected to the input side and the output side of the oscillating circuit 1) are shown in Fig. 1. When the internal circuit 9 is operated in the usual mode, the reset terminal Treset is set to a low level, and the oscillating circuit 1 is operated by connecting the oscillator 8 (a crystal oscillator, for example) from outside of the chip 10' between the terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillating circuit 1. In this connection, a feedback resistor 63 is connected between the input side and output side of the oscillating circuit 1, and the oscillating circuit 1 operates as, for example, a NOR gate. When the oscillating circuit 1 operates, the fundamental clock signal generated from the oscillating circuit 1 is supplied through the frequency divider 2 and the signal path P to the circuit for the pulse dialer provided in the internal circuit 9. The fundamental clock signal generated from the oscillating circuit 1 also is directly supplied through the signal path Q to the circuit for the DTMF dialer provided in the internal circuit 9. During this period, the power-down signal PD for the internal circuit 9 is set to a low level by setting the reset terminal Treset to a low level, and as a result, the internal circuit 9 is released from the power-down state. When it is desired to set the internal circuit 9 to a power-down mode, a predetermined high level signal is supplied from outside to the reset terminal Treset. Thereby, the level of both the output side and input side of the oscillating circuit 1 becomes low, and as a result, the oscillating circuit 1 is brought to a reset state. Simultaneously, the power-down signal PD is set to a high level, and as a result, all parts of the internal circuit 9 are also reset to the initial state (non-operating state). In such a prior art semiconductor integrated circuit, the above-mentioned clock signal obtained by dividing the frequency of the fundamental clock signal, generated from the oscillating circuit 1, through the frequency divider 2 is also used as the clock signal for testing, especially when tests of the functions of the circuit for the pulse dialer provided in the internal circuit 9 are carried out. Thus, as described above, a problem arises in that a long time is needed to perform the several kinds of tests, and as a result, the efficiency of the production is remarkably lowered, especially when the tests of the functions of the internal circuit 9 are carried out during the process of mass production. The present invention is intended to solve such a problem, and Fig. 2 shows a circuit diagram illustrating one embodiment of the semiconductor integrated circuit according to the present invention. As shown in Fig. 2, the semiconductor integrated circuit according to this embodiment comprises an oscillating circuit 1 generating the fundamental clock signal, having a frequency of, for example, 3.58 MHz ; the frequency divider 2; a switching circuit 3, a NAND gate 4, and an AND gate 5 forming parts of a test circuit; feed back resistors 61 and 62, respectively connected to the input side and output side of the oscillating circuit 1; an N channel type MOS transistor 7; and the internal circuit 9 such as the above-mentioned DTMF/pulse dialer; all of which are provided on the same chip 10. A predetermined number of pin terminals are provided on the chip 10, but only three pin terminals (namely, a reset terminal Treset and a pair of terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillating circuit 1) are shown in Fig. 2. The switching circuit 3 switches two signal paths A and B selectively in accordance with the level of a control signal CNT output from the NAND gate 4 for testing. When the internal circuit 9 is operated in the usual mode, the reset terminal Treset is set to a low level, and the oscillating circuit 1 is operated by connecting the oscillator 8 (a crystal oscillator, for example) from outside of the chip 10 between the terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillating circuit 1. In this period, as the reset terminal Treset is set to a low level, the level of the NAND gate 4 (namely, the level of the control signal for testing CNT) becomes high. Then, the switching circuit 3 closes the signal path A in accordance with the high level of the above control signal CNT. Thus, the fundamental clock signal generated from the oscillating circuit 1 is supplied through the frequency divider 2 and the signal path A to the circuit for the pulse dialer provided in the internal circuit 9. Also, the fundamental clock signal generated from the oscillating circuit 1 is directly supplied through the signal path C to the circuit for the DTMF dialer provided in the internal circuit 9. Accordingly, as described above, the circuit for the pulse dialer in the internal circuit 9 is operated by the clock signal obtained by dividing the frequency of the fundamental clock signal, generated from the oscillating circuit 1, through the frequency divider 2, the frequency of which clock signal is, for example, 2 kHz. In this connection, the internal circuit 9 operates as the DTMF dialer or as the pulse dialer selectively, in accordance with the control signal input from one of the input pin terminals not shown in the drawings. Next, when the internal circuit 9 is set to the test mode in order to test the functions of the internal circuit 9, the oscillator 8 is disconnected from the terminals Toscin and Toscout, and the reset terminal Treset and the terminal Toscin connected to the input side of the oscillating circuit 1 are set to a high level. Then a clock signal for testing, the frequency of which clock signal for testing is set to 1/2 x 3.58 MHz , for example, is supplied from outside of the chip to the internal circuit 9 through the terminal Toscout connected to the output side of the oscillating circuit 1. In this case, namely, in the test mode, the output level of the NAND gate 4 (namely, the level of the control signal for testing CNT) is set to a low level by setting the terminals Treset and Toscin to a high level, and therefore, the switching circuit 3 closes the signal path B in accordance with the low level of the above control signal CNT. As a result, the clock signal input from the terminal Toscout for testing is directly supplied to the circuit for the pulse dialer provided in the internal circuit 9 through the signal path B, without passing through the frequency divider 2. Therefore, the tests of the functions for the pulse dialer can be carried out at a high speed by using the clock signal for testing having the frequency value of, for example, 1/2 x 3.58 MHz , as above-mentioned. Also, the above clock signal for testing is directly supplied to the circuit for the DTMF dialer provided in the internal circuit 9, through the signal path C, and therefore, the tests of the functions for the DTMF dialer also can be carried out at a high speed. In this connection, the tests for a part of the internal circuit 9 (a receiving circuit for a key input signal, for example) are carried out by the clock signal passing through the signal path B, even when the tests for the DTMF dialer are carried out. Also, in the test mode, as the input side of the oscillating circuit is maintained at a high level as described above, the oscillating circuit 1 is brought to a non-operating state, and further, as the output level of the AND gate 5 is set to a low level, the internal circuit 9 is released from the power-down state. Next, when the internal circuit 9 is set to the power-down state, the reset terminal Treset is set to a high level, and thereby, the N channel type transistor 7 is turned ON. Therefore, both the input side and output side of the oscillating circuit 1 are set to a low level by connection to ground via feedback resistors 61,62, and the oscillating circuit 1 is brought to a non-operating state. Further, as the output level of the NAND gate 4 becomes high, the output level of the AND gate 5, namely, the level of the power-down signal PD, becomes high, and as a result, the internal circuit 9 is brought to the reset state by the above power-down signal PD having a high level. Figure 3 is a circuit diagram illustrating an example of the switching circuit 3 shown in Fig. 2. As shown in Fig. 3, the switching circuit 3 comprises OR gates 31, 33, a NAND gate 34, and inverters 32 and 35. When the level of the control signal CNT output from the NAND gate 4 becomes high in the usual mode, the output level of OR gate 31 is maintained at a high level, and thus, the fundamental clock signal supplied from the oscillating circuit 1 through the frequency divider 2 and the signal path A is transmitted to the internal circuit 9 through the OR gate 33 and the NAND gate 34. In this connection, the clock signal output from the switching circuit 3 is brought into phase with the clock signal input to the switching circuit 3 by providing the inverter 35 connected to the output side of the NAND gate 34. Contrary to this, when the level of the control signal CNT output from the NAND gate 4 becomes low in the test mode, the output level of OR gate 33 is maintained at a high level and, thus, the clock signal for testing supplied from outside of the chip through the terminal Toscout and the signal path B is transmitted to the internal circuit 9 through the OR gate 31 and the NAND gate 34. The clock signal output from the switching circuit 3 in the test mode also is brought into phase with the clock signal input to the switching circuit 3 by providing the inverter 35 connected to the output side of the NAND gate 34. As described above, according to the present invention, it is possible to test the functions of the internal circuit provided in the semiconductor integrated circuit at a high speed during the process of production and to raise the efficiency of the production line without providing an additional and exclusive terminal for testing, thus avoiding an increase in the size of the device.

Claims: A semiconductor integrated circuit (10) comprising:- an internal circuit (9); an oscillating circuit (1) for generating a basic clock signal for operating said internal circuit when said internal circuit (9) is operated in a usual mode; a frequency divider (2) for dividing the basic clock signal, provided between said internal circuit (9) and said oscillating circuit (1); a pair of terminals (T oscin , T oscout ) respectively connected to an input side and an output side of said oscillating circuit (1), an external oscillator (8) being connected between said pair of terminals when said internal circuit (9) is operated in a usual mode; said semiconductor integrated circuit (10) being characterized in that said circuit is further provided with a test circuit (3, 4, 5) for operating said internal circuit (9), said test circuit, (3, 4, 5) comprising a switching circuit (3) which selectively closes a first signal path (A) supplying said basic clock signal to said internal circuit (9) through said frequency divider (2) in a usual mode or a second signal path (B) supplying an external clock signal for testing, provided from a signal source separate from said oscillating circuit (1) to said internal circuit, directly in a test mode. A semiconductor integrated circuit according to claim 1, wherein said external clock signal for testing is supplied to said internal circuit (9) through one of said pair of terminals (T oscin , T oscout ). A semiconductor integrated circuit according to claim 1 or 2, wherein said switching circuit (3) selectively closes each of said first and second signal paths (A, B) in accordance with a level of a control signal (CNT) for testing generated in said test circuit. A semiconductor integrated circuit according to claim 3, further comprising a reset terminal (T reset ) through which an external reset signal for resetting said internal circuit is supplied to said internal circuit (9), wherein said control signal (CNT) for testing is generated by logically processing external signals supplied to said test circuit through each of the other one of said pair of terminals (T oscin , T oscout ) and said reset terminal (T reset ). a semiconductor integrated circuit according to claim 1, 2, 3 or 4, wherein in the usual mode, said basic clock signal is also supplied directly to said internal circuit (9). A semiconductor integrated circuit according to any one of claims 1 to 5, wherein said internal circuit (9) comprises a dual tone multi frequency circuit and a pulse dialer circuit. A semiconductor integrated circuit according to claim 6, wherein in the usual mode, said pulse dialer circuit receives said basic clock signal through said frequency divider (2), and said dual tone multi frequency circuit receives said basic clock signal directly, and wherein in the test mode, both said pulse dialer circuit and said dual tone multi frequency circuit receive said external clock signal directly.

Inventors: GOTOH, KUNIHIKO, SAITO, TADAHIRO
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H04M1
IPC codes: H04M1, G01R31, H01L27, H01L21