CMOS encoder circuit

Abstract: An encoder circuit comprising a plurality of input lines (80a-80h) on each of which is to appear a logic "1" or "0" signal bit, a plurality of output lines (82a-82d), a first set of transistors (3) of a first conductivity type, each of the first set transistors having a control terminal connected to each of the input lines (80a-80h) and input and output terminals connected between each of the output lines (82a-82d) and a supply voltage source, a second set of transistors (1) of a second conductivity type opposite to the first conductivity type, each of the second set transistors having a control terminal connected to each of the input lines (80a-80h) and input and output terminals between each of the output lines (82a-82d) and ground, and a plurality of logic inverter devices (2) each connected between each of the input lines (80a-80h) and each of the transistors of one of the first and second conductivity types.

Description: FIELD OF THE INVENTION The present invention relates to complementary metal-oxide-semiconductor logic circuits and, more particularly, to an encoder circuit implemented by a complementary metal-oxide-semiconductor logic network (hereinafter referred to as CMOS logic network. BACKGROUND OF THE INVENTION There are several types of encoder circuits implemented by transistor-transistor logic networks, including those of the static type and those of the dynamic type using CMOS logic. Problems are however encountered in each of such known encoder circuits and have resulted from the fact that the transistor-transistor logic networks forming the encoder circuits must be composed of large numbers of active devices. In the case of dynamic encoder circuits, there is required provision of precharge arrangements, transistor-transistor logics and encoder output hold circuits, all of which also use large numbers of active devices in addition to the transistors forming the encoder circuits per se . The use of such a large number of active devices for an encoder circuit requires the provision of a large device area to implement the encoder circuit on a single semiconductor chip and would further impose significant limitation in reducing the cycle speed achievable by the encoder circuit. One of these types of encoder is described for example in US-A-3 945 000. It is the object of the invention to avoid the above mentioned drawbacks and to provide an encoder circuit having a small device area and cycle time. This object is achieved by an encoder circuit as defined in the claim. According to the present invention each of the p-channel type field effect transistors and the associated n-channel type field effect transistors exclusively provides a conduction path between either power voltage or ground voltage line and the output. If an input signal line allows the associated p-channel type field effect transistor to turn on for coupling the associated output line with the power voltage line, there is no n-channel type field effect transistor in the conduction path, and the complementary signal produced by the associated inverter is supplied to the n-channel field effect transistor only when no p-channel type field effect transistor is provided in association with the input signal line. Thus, only one field effect transistor of either p-channel type or n-channel type field effect transistor is coupled between either power voltage or ground voltage line and the associated output line, and only one logic gate or an inverter propagates the input signal to the associated n-channel type field effect transistor. As a result, the signal path is minimized, and only one field effect transistor is gated with the input signal or the complementary signal thereof. Such a small number of stages accelerates production of the output signal, and achieves high speed encoding operation. BRIEF DESCRIPTION OF THE DRAWINGS The drawbacks of prior-art encoder circuits and the features and advantages of an encoder circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a schematic circuit diagram showing an example of a prior-art static-type encoder circuit composed of logic NAND gates; Fig. 2 is a schematic circuit diagram showing an example of a prior-art static-type encoder circuit composed of logic NOR gates; Fig. 3 is a circuit diagram showing schematic circuit diagram showing an example of a prior-art dynamic-type encoder circuit using logic NOR gates; Fig. 4 is a circuit diagram showing a preferred embodiment of an encoder circuit according to the present invention; Fig. 5 is a block diagram showing a preferred example of an interrupt control circuitry incorporating the encoder circuit illustrated in Fig. 4; Fig. 5A is a block diagram showing, to an enlarged scale, a portion of the interrupt control circuitry illustrated in Fig. 5; and Fig. 5B is a view similar to Fig. 5A but shows another portion of the interrupt control circuitry illustrated in Fig. 5. DESCRIPTION OF THE PRIOR ART Figs. 1 to 3 of the drawings show typical examples of prior-art encoder circuits implemented by transistor-transistor logic networks to which the present invention generally appertains. The encoder circuits shown in Figs. 1 and 2 are of the static type and the encoder circuit shown in Fig. 3 is of the dynamic type, all the encoder circuits shown being assumed to be 8-bit input and 4-bit output designs, by way of example. The encoder circuit shown in Fig. 1 consists of 4-input first, second and third NAND gates 10 a , 10 b and 10 c and a 6-input fourth NAND gate 10d arranged in conjunction with eight, first to eight input lines 12 a , 12 b , 12 c , ... 12 h and four, first to fourth output lines 14 a , 14 b and 14 c . The first NAND gate 10 a has its four input terminals respectively connected to the second, fourth, sixth and eighth input lines 12 b , 12 d , 12 f and 12 h and its output terminal connected to the first output line 14 a . The second NAND gate 10 b has its four input terminals respectively connected to the first, fourth, fifth and eighth input lines 12 a , 12 d , 12 e and 12 h and its output terminal connected to the second output line 14 b . The third NAND gate 10 c has its four input terminals respectively connected to the first, second, third and eighth input lines 12 a , 12 b , 12 c and 12 h and its output terminal connected to the third output line 14 c . The fourth NAND gate 10 d has its sixth input terminals respectively connected to the second to seventh input lines 12 b to 12 g and its output terminal connected to the third output line 14 c . As is well known in the art, each of these NAND gates 10 a , 10 b , 10 c and 10 d is operative to produce at its output terminal a signal of a logic "1" in the presence of a logic "0" signal at least one of its input terminals and a signal of a logic "0" only in the presence of logic "1" signals at all of its input terminals. As is also well known in the art, each of the NAND gates 10 a , 10 b and 10 c typically includes a total of four n-channel field-effect transistors connected in series with an n-channel field-effect transistor serving as a load transistor and, likewise, the fourth NAND gate 10 d typically includes a total of sixth n-channel field-effect transistors connected in series with an n-channel field-effect transistor serving as a load transistor. The encoder circuit shown in Fig. 2 consists of 4-input first, second and third NOR gates 16 a , 16 b and 16 c and a 2-input fourth NOR gate 16d arranged in conjunction with eight, first to eighth input lines 18 a , 18 b , 18 c , ... 18 h and four, first to fourth output lines 20 a , 20 b and 20 c . The first NOR gate 16 a has its four input terminals respectively connected to the first, third, fifth and seventh input lines 18 a , 18 c , 18 e and 18 g and its output terminal connected to the first output line 20 a . The second NOR gate 16 b has its four input terminals respectively connected to the second, third, sixth and seventh input lines 18 b , 18 c , 18 f and 18 g and its output terminal connected to the second output line 20 b . The third NOR gate 16 c has its four input terminals respectively connected to the fourth to seventh input lines 18 d to 18 g and its output terminal connected to the third output line 20 c . The fourth NOR gate 16 d has its two input terminals respectively connected to the first and eighth input lines 18 a and 18 h and its output terminal connected to the third output line 20 c . As well known in the art, each of these NOR gates 16 a , 16 b , 16 c and 16 d is operative to produce at its output terminal a signal of a logic "0" in the presence of logic a "1" signal at least one of its input terminals and a signal of a logic "1" only in the presence of logic "0" signals at all of its input terminals. As also well known in the art, each of the NAND gates 16 a , 16 b and 16 c typically includes a total of four p-channel field-effect transistors connected in series with a p-channel field-effect transistor serving as a load transistor and, likewise, the fourth NAND gate 16 d typically includes two n-channel field-effect transistors connected in series with a p-channel field-effect transistor serving as a load transistor. On the other hand, the dynamic encoder circuit shown in Fig. 3 includes 2-input first to eighth NOR gates 22 a to 22 h . These eight NOR gates 22 a to 22 h are connected each at one input terminal to first to eighth input lines 24 a to 24 h and at the other input terminals jointly to an encode enable signal supply line 26 for supplying an encode enable signal S EE . The first NOR gate 22 a has its output terminal connected to the gates of two n-channel field-effect transistors 28 and 30 each having its source connected to ground as shown. The second NOR gate 22 b has its output terminal connected to the gate of an n-channel field-effect transistor 32 having its source connected to ground. The third NOR gate 22 c has its output terminal connected to the gates of n-channel field-effect transistors 34 and 36 each having its source connected to ground. The fourth NOR gate 22 d has its output terminal connected to the gate of an n-channel field-effect transistor 38 having its source connected to ground. The fifth NOR gate 22 e has its output terminal connected to the gates of two n-channel field-effect transistors 40 and 42 each having its source connected to ground. The sixth NOR gate 22 f has its output terminal connected to the gates of two n-channel field-effect transistors 44 and 46 each having its source connected to ground. The seventh NOR gate 22 g has its output terminal connected to the gates of three n-channel field-effect transistors 48, 50 and 52 each having its source connected to ground. Furthermore, the eighth NOR gate 22 h has its output terminal connected to the gates of two n-channel field-effect transistors 54 and 56 each having its source connected to ground. On the other hand, the encode enable signal supply line 26 is further connected through an inverter 58 to the gates of four p-channel precharge field-effect transistors 60, 62, 64 and 66 each having its source connected to a supply voltage source (V DD ) which is symbolically represented in the form of a bubble. The n-channel field-effect transistors 28, 34, 40 and 48 having their gates connected to the first, third, fifth and seventh NOR gates 22 a , 22 c , 22 e and 22 g and the p-channel precharge field-effect transistor 60 connected through the inverter 58 to the encoder enable signal supply line 26 have their drains connected to a first encoder output line 68 a . The n-channel field-effect transistors 32, 36, 44 and 50 having their gates connected to the second, third, sixth and seventh NOR gates 22 b , 22 c , 22 f and 22 g and the p-channel precharge field-effect transistor 62 connected through the inverter 58 to the encoder enable signal supply line 26 have their drains connected to a second encoder output line 68 b . The n-channel field-effect transistors 38, 42, 46, 52 and 54 having their gates connected to the fourth, fifth, six, seventh and eighth NOR gates 22 d , 22 e , 22 f , 22 g and 22 h and the p-channel precharge field-effect transistor 64 connected through the inverter 58 to the encoder enable signal supply line 26 have their drains connected to a third encoder output line 68 c . Furthermore, the n-channel field-effect transistors 30 and 56 having their gates connected to the first and eighth NOR gates 22 a and 22 h and the p-channel precharge field-effect transistor 66 connected through the inverter 58 to the encoder enable signal supply line 26 have their drains connected to a fourth encoder output line 68 d . The first to fourth encoder output lines 68 a to 68 d terminate in an encoder output hold circuit 70 which has four output terminals 72 a , 72 b , 72 c and 72 d as shown. The encode enable signal S EE is an active-low logic signal and activates each of the p-channel precharge field-effect transistors 60, 62, 64 and 66 through the inverter 58 when swung to a high level prior to each encoding cycle of operation for precharging each of the output lines 68 a to 68 d to a level approximating the supply voltage V DD . During precharge cycles of operation with the encode enable signal S EE thus swung to high level, each of the first to eighth NOR gates 22 a to 22 h is conditioned to produce a logic "0" output signal so that all of the n-channel field-effect transistors 28 to 56 included in the encoder circuit are held in non-conduction state. There are problems in each of the known encoder circuits implemented by transistor-transistor logic networks. Each of the NAND gates 10 a to 10 d or the NOR 166 a to 16 d of the prior-art static encoder circuit shown in Fig. 1 or 2 is usually composed of a plurality of n-channel or p-channel driver field-effect transistors in addition to a load transistor as discussed previously. The use of such a large number of active devices for an encoder circuit not only requires the provision of a large total device area to implement the encoder circuit on a single semiconductor chip but would make it difficult to significantly reduce the cycle time achievable by the encoder circuit. On the other hand, the known dynamic encoder circuit of the configuration shown in Fig. 3 requires not only the driver transistors 28 to 56 but also a large number of field-effect transistors for forming the NOR gates 22 a to 22 h and the precharge arrangement including the inverter 58 and p-channel transistors 60 to 66 as well as the active devices for forming the encoder output hold circuit 70. This also requires the provision of a large device area to implement the encoder circuit on a single semiconductor chip and would further make it difficult to reduce the cycle time of the encoder circuit. Fig. 4 of the drawings show a preferred embodiment of an encoder circuit according to the present invention to overcome these problems of prior-art encoder circuits implemented by transistor-transistor logic networks. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 4 of the drawings, a CMOS encoder circuit embodying the present invention is assumed as being implemented by an eight-bit input and four-bit output designs by way of example. The encoder circuit is thus shown provided in conjunction with first to eighth input lines 80 a , 80 b , 80 c , ... 80 h and four encoder output lines 82 a , 82 b , 82 c and 82 d . Of these four encoder output lines, the lines 82 a and 82 d in particular are assumed to be LSB (least significant bit) and MSB (most significant bit) lines, respectively. The first input line 80 a is connected to the gates of two p-channel field-effect transistors 84 and 86 and through an inverter 88 to the gates of two n-channel field-effect transistors 90 and 92, each of the p-channel transistors 84 and 86 having its source connected to a supply voltage source and each of the n-channel transistors 90 and 92 having its source connected to ground. The second input line 80 b is connected to the gates of three p-channel field-effect transistors 94, 96 and 98 and through an inverter 100 to the gate of one n-channel field-effect transistor 102, each of the p-channel transistors 94, 96 and 98 having its source connected to the supply voltage source and the n-channel transistor 102 having its source connected to ground. The third input line 80 c is connected to the gates of two p-channel field-effect transistors 104 and 106 and through an inverter 108 to the gates of two n-channel field-effect transistors 110 and 112, each of the p-channel transistors 104 and 106 having its source connected to the supply voltage source and each of the n-channel transistors 110 and 112 having its source connected to ground. The fourth input line 80 d is connected to the gates of three p-channel field-effect transistors 114, 116 and 118 and through an inverter 120 to the gates of one n-channel field-effect transistor 122, each of the p-channel transistors 114, 116 and 118 having its source connected to the supply voltage source and the n-channel transistor 122 having its source connected to ground. On the other hand, the fifth input line 80 e is connected to the gates of two p-channel field-effect transistors 124 and 126 and through an inverter 128 to the gates of two n-channel field-effect transistors 130 and 132, each of the p-channel transistors 124 and 126 having its source connected to the supply voltage source and each of the n-channel transistors 130 and 132 having its source connected to ground. Likewise, the sixth input line 80 f is connected to the gates of two p-channel field-effect transistors 134 and 136 and through an inverter 138 to the gates of two n-channel field-effect transistors 140 and 142, each of the p-channel transistors 134 and 136 having its source connected to the supply voltage source and each of the n-channel transistors 140 and 142 having its source connected to ground. The seventh input line 80 g is connected to the gates of one p-channel field-effect transistor 144 and through an inverter 146 to the gates of three n-channel field-effect transistors 148, 150 and 152, the p-channel transistor 144 having its source connected to the supply voltage source and each of the n-channel transistors 148, 150 and 152 having its source connected to ground. Furthermore, the eighth input line 80 h is connected to the gates of two p-channel field-effect transistors 154 and 156 and through an inverter 158 to the gates of two n-channel field-effect transistors 160 and 162, each of the p-channel transistors 154 and 156 having its source connected to the supply voltage source and each of the n-channel transistors 160 and 162 having its source connected to ground. The p-channel field-effect transistors 94, 114, 134 and 154 having their gates respectively connected to the second, fourth, sixth and eighth input lines 80 b , 80 d , 80 f and 80 h have their drains jointly connected to the first encoder output line 82 a . The n-channel field-effect transistors 90, 110, 130 and 148 having their gates respectively connected through the inverters 88, 108, 128 and 146 to the first, third, fifth and seventh input line 80 a , 80 c , 80 e and 80 g also have their drains jointly connected to the first encoder output line 82 a . The p-channel field-effect transistors 84, 116, 124 and 156 having their gates respectively connected to the first, fourth, fifth and eighth input lines 80 a , 80 d , 80 e and 80 h have their drains jointly connected to the second encoder output line 82 b . The n-channel field-effect transistors 102, 112, 140 and 150 having their gates respectively connected through the inverters 100, 108, 138 and 146 to the second, third, sixth and seventh input line 80 b , 80 c , 80 f and 80 g also have their drains jointly connected to the second encoder output line 82 b . The p-channel field-effect transistors 86, 96 and 104 having their gates respectively connected to the first, second and third input lines 80 a , 80 b and 80 c have their drains jointly connected to the third encoder output line 82 c . The n-channel field-effect transistors 122, 132, 142, 152 and 160 having their gates respectively connected through the inverters 120, 128, 138, 146 and 158 to the fourth to eighth input line 80 d to 80 h also have their drains jointly connected to the third encoder output line 82 c . The p-channel field-effect transistors 98, 106, 118, 126, 136 and 144 having their gates respectively connected to the second to seventh input lines 80 b to 80 g have their drains jointly connected to the fourth encoder output line 82 d . The n-channel field-effect transistors 92 and 162 having their gates respectively connected through the inverters 88 and 158 to the first and eighth input line 80 a and 80 h also have their drains jointly connected to the fourth encoder output line 82 d . Fig. 4 shows not only the circuit arrangement of the transistors and logic inverters implementing the encoder circuit embodying the present invention but also the layout of such devices integrated on a single semiconductor substrate (not shown). The semiconductor integrated circuit structure formed on the substrate thus largely consists of an n-channel field-effect transistor zone 1 within which the n-channel field-effect transistors are located, an inverter zone 2 within which the logic inverters are located, and a p-channel field-effect transistor zone 3 within which the p-channel field-effect transistors are located, as indicated by broken lines. The n-channel and p-channel zones 1 and 3 are formed on both sides of the inverter zone 2 which thus intervenes between the n-channel and p-channel zones 1 and 3 as shown. One specific mode of operation of the encoder circuit thus constructed and arranged will be hereinafter described on the assumption that a digital input signal "10111111" is applied to the circuit through the input lines 80 a to 80 h . Thus, there is a signal bit of a logic "0" level appearing at the second input line 80 b alone with a logic "1" signal bit applied to each of the other input lines 80 a and 80 c to 80 h . In the presence of the logic "0" bit at the second input line 80 b of the shown circuit, each of the p-channel field-effect transistors 94, 96 and 98 is activated to turn on, providing a current path from the supply voltage source to each of the first, third and fourth encoder output lines 82 a , 82 c and 82 d . Among the n-channel field-effect transistors, only the n-channel field-effect transistor 102 associated with the second input line 80 b and second encoder output line 82 b is activated to turn on in response to the logic "1" bit appearing at the output terminal of the associated inverter 100. All the other n-channel field-effect transistors remain in non-conduction state in the presence of logic "1" signal bits at the output terminals of the associated inverters 88, 108, 120, 128, 138, 146 and 158. Thus, each of the first, third and fourth encoder output lines 82 a , 82 c and 82 d is connected to the supply voltage source and isolated from ground and is thus charged to a logic "1" state. On the other hand, the second encoder output line 82 b which remains disconnected from the supply voltage source is connected to ground through the n-channel field-effect transistor 102 and is therefore shifted to a logic "0" state. A four-bit binary signal encoded in the form of "1011" is thus produced in response to the digital input signal "10111111". In a like manner, a four-bit binary signal encoded in the form of "0011" will be produced in response to a digital input signal "11011111" with each of the p-channel field-effect transistors 104 and 106 turned on in association with the third and fourth encoder output lines 82 c and 82 d , respectively, and each of the n-channel field-effect transistors 112 and 110 turned on in association with the first and second encoder output lines 82 a and 82 b , respectively. Similarly, a binary signal encoded as "1000" will be produced in response to a digital input signal "11111101" with only the p-channel field-effect transistor 144 turned on in association with the fourth encoder output line 82 d and each of the n-channel field-effect transistors 148, 150 and 152 turned on in association with the first, second and third encoder output lines 82 a , 82 b and 82 c , respectively. As will be appreciated from the foregoing description, the encoder circuit embodying the present invention necessitates only four p-channel and n-channel field-effect transistors, viz., transistors of a number equal to the output lines and a single inverter for each of the input lines. An encoder circuit according to the present invention can thus be implemented simply by a number of field-effect transistors equal to the product of the number of the input lines and the number of the output lines and a number of inverters equal in number to the input lines. There is, furthermore, no need to use logic NAND or NOR gates each of which may consist of a series of transistors equal in number to the input lines used, as is the case in each of the conventional encoder circuits shown in Figs. 1 and 2. This will contribute to significant reduction of the total device area of the encoder circuit implemented on a single semiconductor chip. It may also be noted that the encoder circuit operates simply on a single worst, viz., time-consuming signal bit which is applied to only one of the inverters to produce the required encoder output signal. Thus, an encoder circuit according to the present invention is advantageous not only for its potentiality to permit significant reduction of the total device area required to implement the encoder circuit on a single semiconductor chip but for the significantly shortened cycle time achievable of the encoder circuit. Fig. 5 of the drawings shows an example of an interrupt control circuitry to which an encoder circuit according to the present invention is applied. As shown in Fig. 5 and at an enlarged scale in Fig. 5A, the interrupt control circuitry comprises an interrupt priority decision circuit 170 having eight input terminals 172 a , 172 b , 172 c , ... 172 h and eight output terminals 174 a , 174 b , 174 c , ... 174 h . The priority decision circuit 170 is operative to produce a logic "0" signal bit at only one of its output terminals 174 a , 174 b , 174 c , ... 174 h and a logic "1" signal bit at each of the remaining output terminals depending upon the level of the interrupt priority determined for each digital signal supplied to the circuit 170 through the input terminals 172 a , 172 b , 172 c , ...172 h . Such an interrupt priority decision circuit 170 per se is well known in the art and, as such, no detailed circuit arrangement thereof is herein shown. A logic signal thus including only one logic "0" bit thus appears at the output terminals 174 a , 174 b , 174 c , ... 174 h of the priority decision circuit 170 and is transmitted on one hand to an eight-input NAND gate 176 having an output terminal connected to a microprocessor 178 (CPU) and on the other hand to an interrupt jump address generator circuit 180. The interrupt jump address generator circuit 180 has incorporated therein an encoder circuit constructed and arranged as hereinbefore described with reference to Fig. 4. Accordingly, the address generator circuit 180 has eight input terminals respectively connected to the output terminals 174 a , 174 b , 174 c , ... 174 h of the priority decision circuit 170 and four output terminals 182 a , 182 b , 182 c and 182 d as shown. One of eight bits of the binary signal input to the NAND gate 176 being of a logic "0" state, the NAND gate 176 normally supplies a logic "1" output signal requesting the microprocessor 178 for an interrupt. When the interrupt thus requested is granted by the microprocessor 178, an interrupt grant signal S IG of a logic "1" state is supplied to one input terminal of a two-input NAND gate 184, the other input terminal of which is responsive to an interrupt jump address timing signal S AT . If this interrupt jump address timing signal S AT is of a logic "1" state, then the NAND gate 184 is conditioned to produce a logic "0" output signal, which is supplied on one hand directly and on the other hand after inversion by an inverter 186 to a jump address read circuit 188. The jump address read circuit 188 comprises first, second, third and fourth clocked inverter networks 190 a , 190 b , 190 c and 190d connected to the output terminals 182 a , 182 b , 182 c and 182 d , respectively, of the interrupt jump address generator circuit 180 and further to the output terminals of the NAND gate 184 and inverter 186. The four clocked inverter networks 190 a , 190 b , 190 c and 190 d all have similar circuit arrangements so that the detailed circuit construction of only the first clocked inverter network 190 a is herein shown. As illustrated to an enlarged scale in Fig. 5B, the first clocked inverter network 190 a consists of a series combination of p-channel field-effect transistors 192 and 194 and n-channel field-effect transistors 196 and 198. The p-channel field-effect transistor 192 has its gate connected to the output terminal 182 a of the interrupt jump address generator circuit 180 and its source connected to a supply voltage source which is also symbolically represented by a bubble. The n-channel field-effect transistor 194 has its gate connected to the output terminal of the NAND gate 184, its source connected to the drain of the transistor 192 and its drain connected to a node 200. The p-channel field-effect transistor 196 has its gate connected to the output terminal of the inverter 186 and its drain connected to the node 200. The n-channel field-effect transistor 198 has its gate also connected to the output terminal of the NAND gate 184, its drain connected to the source of the transistor 196, and its source connected to ground as shown. In the description to follow, those elements of each of the second, third and fourth clocked inverter networks 190 b , 190 c and 190 d will be referred to with the same reference numerals as those of the transistors 192, 194, 196 and 198 and node 200 of the first clocked inverter network 190 a thus constructed. The jump address read circuit 188 further comprises first, second, third and fourth n-channel field-effect transistors 202, 204, 206 and 208 which have their gates jointly connected to the output terminal of the inverter 186, each of these transistors having its source connected to ground. There is further provided a data bus which comprises eight data line 210 a , 210 b , 210 c , ... 210 h . The first and second data line 210 a and 210 b are connected to the drains of the field-effect transistors 202 and 204, respectively. The third data line 210 c is connected to the node 200 in the first clocked inverter network 190 a and likewise each of the fourth, fifth and sixth data lines 210 d , 210 e and 210 f is connected to the similar node in each of the second, third and fourth clocked inverter networks 190 b , 190 c and 190 d . The seventh and eighth data line 210 g and 210 h are connected to the drains of the field-effect transistors 206 and 208, respectively. In the presence of a logic "0" signal at the output terminal of the NAND gate 184 as above noted, the p-channel field-effect transistor 194 in the first clocked inverter network 190 a and its counterpart in each of the second, third and fourth clocked inverter networks 190 b , 190 c and 190 d are turned on. Furthermore, the n-channel field-effect transistor 196 in the first clocked inverter network 190 a and its counterpart in each of the second, third and fourth clocked inverter networks 190 b , 190 c and 190 d are turned on in response to the logic "1" output signal from the inverter 186. On the other hand, there is a certain four-bit binary signal such as "1011" at the output terminals 182 a , 182 b , 182 c and 182 d of the interrupt jump address generator circuit 180 in the presence of an eight-bit digital signal such as "10111111" at the output terminals 172 a , 174 b , 174 c , ... 174 h of the interrupt priority decision circuit 170. The four-bit binary signal "1101" thus generated by the jump address generator circuit 180 is fed to the four clocked inverter networks 190 a to 190 d of the jump address read circuit 188. Thus, a logic "1" signal bit is applied from the first output terminal 182 a of the address generator circuit 180 to the gates of the p-channel and n-channel field-effect transistors 192 and 198 of the first clocked inverter network 190 a . Likewise, a logic "1" signal bit is applied from each of the second and fourth output terminal 182 b and 182 d of the address generator circuit 180 to the gates of the transistors 192 and 198 in the second and fourth clocked inverter networks 190 b and 190 d , respectively. Concurrently, a logic "0" signal bit is applied from the third output terminal 182 c of the address generator circuit 180 to the gate of the transistors 192 and 198 of the third clocked inverter network 190 c . The p-channel field-effect transistor 192 of the first clocked inverter network 190 a and its respective counterparts in the second and fourth clocked inverter networks 190 b and 190 d are thus allowed to remain in non-conduction state, while the transistor 192 of the third clocked inverter network 190 c is activated to turn on. Furthermore, the n-channel field-effect transistor 198 of the first clocked inverter network 190 a and its respective counterparts in the second and fourth clocked inverter networks 190 b and 190 d are turned on, and the transistor 198 of the third clocked inverter network 190 c is allowed to remain in non-conduction state. Thus, all the field-effect transistors of the four clocked inverter networks 190 a , 190 b , 190 c and 190 d are turned on, except for the p-channel field-effect transistor 192 in the first clocked inverter network 190 a and its counterparts in the second and third clocked inverter networks 190 b and 190 d and the n-channel field-effect transistor 198 of the third clocked inverter network 190 c . Under these conditions, the node 200 in the first clocked inverter network 190a is connected to ground through the transistors 196 and 198 and is disconnected from the supply voltage source by the p-channel field-effect transistor 192. The nodes 200 in the second and fourth clocked inverter networks 190 b and 190 d are also grounded and disconnected from the supply voltage source. On the other hand, the node 200 in the third clocked inverter network 190 c is isolated from ground by means of the transistor 198 of the inverter network 190 c and is connected to the supply voltage source through the transistor 192 of the network 190 c . A logic "0" signal corresponding to ground level thus appears at the third, fourth and sixth data lines 210 c , 210 d , 210 f while a logic "1" signal corresponding to the supply voltage level appears at the fifth data line 210 e . On all the other data lines, viz., the first, second, seventh and eighth data lines 210 a , 210 b , 210 g and 210 h are provided logic "0" signals with the n-channel field-effect transistors 202, 204, 206 and 208 turned on in response to the logic "1" output signal from the inverter 186. Accordingly, there appears a binary signal in the form of "00001000" on the eight-bit data bus consisting of the lines 210 a to 210 h . In the interrupt control circuitry hereinbefore described, the four-bit binary signal output from the encoder circuit described with reference to Fig. 4 is used as the output signal from the interrupt jump address generator circuit 180 and the individual bits of such a signal are supplied to the clocked inverter networks 190 a , 190 b , 190 c and 190 d , respectively. The p-channel field-effect transistor 194 and n-channel field-effect transistor 196 of each of these clocked inverter networks depend for their operation on the logic state at the output terminal of the NAND gate 184 provided in association with the inverter networks 190 a , 190 b , 190 c and 190 d . Thus, the field-effect transistors 194 and 196 of each clocked inverter network could not be turned on unless the NAND gate 184 is conditioned to produce a logic "0" output signal. Meanwhile, it may happen that a high-impedance state is established on any of the output terminals 182 a , 182 b , 182 c and 182 d of the jump address generator circuit 180 so that the p-channel and n-channel field-effect transistors 192 and 194 of the associated clocked inverter network is activated to turn on by a floating voltage appearing at the particular output terminal of the circuit 180. Since the field-effect transistors 194 and 196 of the clocked inverter network could not be turned on in the absence of a logic "0" signal at the output terminal of the NAND gate 184 as above noted, there could not be a current path created from the supply voltage source to ground through the particular inverter network. The interrupt control circuitry shown in Fig. 5 is further characterized in that the NAND gate 184 operable as above could not be conditioned to produce a "0" output signal except when the binary signal output from the interrupt priority decision circuit 170 includes one, and only one logic "0" signal bit. This means that the jump address read circuit 188 is enabled to read the binary output signal from the jump address generator circuit 180 when, and only when the binary signal output from the interrupt priority decision circuit 170 includes a single logic "0" signal bit. Under such a condition, each bit of the four-bit binary signal output from the jump address generator circuit 180 uniquely has either a logic "0" state or a logic "1" state so that the jump address read circuit 188 could not read a high-impedance state from the address generator circuit 180. While it has been assumed that the encoder circuit shown in Fig. 4 is such that the encoder circuit is enabled to operate in response to an input digital signal including only one logic "0" bit, such an encoder circuit may be modified to be enabled when supplied with a digital signal including only one logic "1" bit. For this purpose, the circuit arrangement of Fig. 4 may be modified so that the eighth input lines 80 a , 80 b , 80 c , ... 80 h for the encoder circuit are connected to the n-channel field-effect transistors directly (viz., without intervention of the inverters 88, 100, 108, 120, 128, 138, 146, 158) and through inverters to the p-channel field-effect transistors.

Claims: An encoder circuit comprising a) a plurality of input lines (80a to 80h) supplied with input data bits each being of a binary logic level, b) a plurality of output lines (82a to 82d) to which an output signal is supplied, and c) an encoder unit coupled between said plurality of input lines (80a to 80h) and said plurality of output lines (82a to 82d) and responsive to said input data bits for producing said output signal, said encoder unit comprising: a plurality of first field effect transistors (84/86, 94/96/98, 104/106, 114/116/118, 124/126, 134/136, 144, 154/156) of a first channel conductivity type having respective source-to-drain paths connected between a supply voltage source and one of said plurality of output lines (82a to 82d), a plurality of logic gates (88/100/108/120/128/138/146/158) having a respective input node connected to one of said plurality of input lines; a plurality of second field effect transistors (90/92, 102, 110/112, 122, 130/132/140/142/148/150/152, 160/162) of a second channel conductivity type opposite to said first channel conductivity type, said plurality of second transistors having respective gate electrodes being connected to the output node of one of said plurality of logic gates and having respective source-to-drain paths coupled between a reference voltage source and one of said plurality of output lines, characterized in that c-1) the gates of the said plurality of first transistors are connected to one of the said plurality of input lines, c-2) the said plurality of logic gates are operative to invert said input data bits for producing complementary input data bits, c-3) each input line is operationally coupled to each output line through exactly one of said first or second field effect transistors.

Inventors: MACHIDA TOSHIAKI, MACHIDA, TOSHIAKI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H03M7