LIQUID CRYSTAL DISPLAYS

Abstract: An active matrix addressed liquid crystal display is described, each liquid crystal cell (21) within the display having two electrodes (23, 25) each carried on a surface of a different one of two insulating plates. Each cell (21) is connected via a respective transistor (27) to a pair of address lines (29, 31, 33, 35, 37, 39) each address line within a pair being connected to different cells (21) within the array, and each line within a pair being carried on a different plate. Synchronised electrical pulses are applied to the address lines to switch on selected cells (21) within the array, the sense of the pulses on one of the lines being periodically changed.

Description: This invention relates to liquid crystal displays, and in particular to liquid crystal displays of the kind comprising a two dimensional array of liquid crystal cells, each cell having two electrodes each carried on a surface of a respective one of two plates, each cell being switchable by means of electrical signals applied to a respective pair of electrical address lines connected to the cell, each address line within a pair being connected to a different plurality of cells within the array. To overcome the problems of multiplexing the address lines in such a display, i.e. in order to identify uniquely the cell to be switched at any one time and to prevent partial switching of other cells connected to one of the pairs of address lines, it is known to connect each cell to its respective pair of address lines via a respective electrical switch, for example a thin film transistor, i.e. the so-called "active matrix addressing" approach. EP-A-193759, which was published after the priority date of the present application, discloses such a display comprising an array of pixels, each of which is constituted by a respective single liquid crystal cell. Each cell has a pair of electrodes carried by first and second parallel plates. Each cell is addressed by a first address line on one of the plates and a second address line on the other plate. The cell electrode on the latter plate is connected to the second address line via a respective transistor. DE-A-2904596 discloses a display which comprises two substantially parallel plates, and a two-dimensional array of pixels constituted by liquid crystal cells each having a first electrode carried by one of the plates and a second electrode carried by the other plate. A set of first address lines and a set of second address lines are provided on one of the plates, together with a plurality of transistors each associated with a respective one of the cells. Synchronised electrical pulses of periodically reversing polarity are applied to a selected first address line and a selected second address line to switch the pixel associated with those lines. Figure 1 is a schematic circuit diagram of part of a known active matrix addressing display. Referring to Figure 1, the display comprises an array of liquid crystal cells, each cell 1 being represented in the figure as a capacitor. One electrode 3 of each cell is carried on the inner surface of a first insulating plate, this plate being transparent, the electrode 3 being the size of a pixel of the display, and being made of a transparent conductor such as indium tin oxide. The other electrode 5 of each cell 1 is defined on the opposing surface of a second insulating plate, this surface carrying a conductive layer effective to form an earth plane, all components carried on this second plate being shown as dotted in the figure. In respect of each cell 1, there is provided a re­ spective n channel thin film field effect transistor 7 carried on the first plate. One main electrode of each transistor, hereinafter referred to as a drain for con­ venience, is connected to the electrode 3 of the cell 1, whilst the gate and other main electrode of transistor 7 hereirafter referred to as a source for convenience, are connected to a selected gate address line 9, 11 or 13 and a selected source address line 15, 17 or 19 respectively within a grid of address lines in the form of conductive tracks on the first plate, the gate lines 9, 11, 13 ex­ tending at right angles to the source lines 15, 17, 19 as indicated in the figure. In use of the display, appropriate synchronised gate and source voltage pulses are applied to a selected pair of gate and source address lines, the sense of the pulses to the source line being periodically changed to avoid electrolysis of the liquid crystal being addressed. This then selectively switches on the one transistor 7 which is connec­ ted to both the selected address lines. The capacitor constituted by the cell 1 connected to the selected tran­ sistor 7 is then able to charge up to the voltage required to give a usual response in the liquid crystal cell, the capacitor then being isolated when the transistor is sub­ sequently switched off, the charge held on the capacitor being effective to switch the cell in the sense of changing the reflectivity of the liquid crystal and thus producing the required pixel image. Such a known display suffers from the disadvantage, however, that there will necessarily be n sites on the plate array where the conducting tracks constituting the gate and source address lines cross each other. Such overlaps are prone to give short-circuits if the insulator between the two conductors is faulty, or open circuits if one of the conductive tracks breaks where it is taken over the edge of the insulator. It is an object of the present invention to provide a liquid crystal display of the kind specified in which each liquid crystal is addressed via a respective transistor means, but wherein the number of overlap regions of the address lines is reduced. According to the present invention there is provided a liquid crystal display, comprising two substantially parallel plates; a two-dimensional array of pixels constituted by liquid crystal cells, each cell having a first electrode carried by one of the plates and a second electrode carried by the other plate; a plurality of first address lines ; a plurality of second address lines; a plurality of transistor means each associated with a respective one of the cells; and means to apply synchronised electrical pulses to a selected one of the first address lines and a selected one of the second address lines so as to switch the pixel associated with those two lines, the pulses applied to the selected lines being such that the polarity of the voltage applied to the pixel reverses periodically; characterised in that said first address lines are carried by one of the plates and said second address lines are carried by the other plate; and in that each pixel is constituted by a plurality of said liquid crystal cells. Embodiments of the invention will now be described, by way of example, with reference to Figures 2 to 6 of the accompanying drawings, in which: Figure 2 is a schematic circuit diagram of a part of a display according to the invention; Figure 3 illustrates the voltage waveforms applied to the display; Figures 4 and 5 illustrate schemes for driving a display according to the invention; and Figure 6 is a schematic plan view of the circuit elements of a part of a display according to the invention. Referring firstly to Figure 2, as in the prior art display described herebefore with reference to Figure 1, the display comprises an array of liquid crystal cells again represented as capacitors 21. The electrodes 23, 25 of each cell are formed on the opposing surfaces of a pair of parallel insulating plates, all components carried on the second of the plates being shown dotted. Unlike the prior art display however, one electrode 23 of each cell is connected to the nominal source of a respective n channel thin film field effect transistor 27 carried on the same plate as the electrode 23. The other electrode 25 of each cell is defined within one of a series of parallel conductive tracks 29, 31, 33 carried on the second plate. The gate and nominal drain of each transistor 27 is connected to a selected pair of conductive tracks running parallel to each other across the first plate, but at right angles to the tracks carried on the second plate, alternate tracks across the first plate constituting gate address lines 35, 37, 39 and earth lines 41, 43. Referring now also to Figure 3, in use of the display, a driving voltage V g with respect to earth is applied to a selected gate line or lines whilst a driving voltage V s with respect to earth is applied to selected source line or lines. Thus the selected cells 21 will be charged to a voltage cell equal to the turn on voltage of the cells, alternation of the sense of the voltage pulses on the source lines causing the polarity of the voltage applied across the selected cells to periodically alter so as to avoid electrolysis of the cells. Thus by a display in accordance with the invention, the problem of overlapping address lines on one of the plates is avoided. The gate lines 35, 37, 39 and the earch lines 41, 43 may be connected to edge connectors at different edges of the first plate, or alternatively a suitable edge connector may be used to provide electrical connection to all the lines 35, 37, 39, 41, 43 at a single edge of the plate, the edge connector having linked earth pins. In yet another alternative display the earth lines 41, 43 may be arranged to pass beyond the connector for the gate lines 35, 37, 39. It will be appreciated however, that even if it is convenient in some circumstances to provide a bus bar for linking the earth lines 41, 43, the bus bar crossing over or under the gate lines 35, 37, 39 the number of overlap regions is still vastly reduced over those necessary in the prior art display, only one such overlap being required for each row within the array. It will also be appreciated that the edge connectors may be replaced by driving circuit and shift register chips mounted around the periphery of the display, with soldered contacts being made to the earth and gate lines. In a more complex form of device operation, the lines 41, 43 can be operated with appropriate bias pulses. This can be used to improve display performace, or to enable transistors with less favourable electrical characteristics to be used. As shown in Figure 5, the gate and earth lines may be formed on the same side of the electrode 23, allowing a larger cell electrode area. Referring now to Figure 6, each pixel of the display is constituted by two individual liquid crystal cells. Thus for each pixel under each column source line carried on the second plate there are formed on the first plate two electrodes 43, 45 lying side by side each connected to the same row gate line carried on the first plate by a respective transistor 47, 49. In the event of failure of one of the transistors 47, 49, the cell connected to the surviving transistor may still be switched. The source lines 29, 31, 33 on the second plate are formed as conductive stripes of the same width as the electrode 23. It is however advantageous to narrow down the stripes in the region of the gate and earth lines 35, 41 as shown in order to minimise the capacitance loading of the transistors. It is also particularly advantageous that individual conductive tracks 42 be formed between the gate lines 35, 37, 39 and each transistor 27. Where a transistor 27 is found to be faulty, it is then possible to disconnect the faulty transistor from the gate line by severing the corresponding individual track by, for example, use of a high definition laser. It will be appreciated that whilst in the prior art display, and in the displays in accordance with the invention described by way of example, only four liquid crystal cells are shown, in practice the displays will have 1000×600 or more cells, displays in accordance with the innvetion having particular advantages in displays having large numbers of liquid crystal cells. Furthermore, whilst in the prior art display and in the displays in accordance with the invention described by way of example an n channel thin film field effect transistor is used to connect each cell to its respective pair of address lines, a p channel thin film field effect transistor, or indeed any appropriate transistor means, may be used. It will also be appreciated that whilst in the display described herebefore by way of example, the liquid crystal cells are contained between a pair of insulating plates, a display in accordance with the invention may be formed in which one plate of the display is a semiconductor crystal in which electrical switches are fabricated.

Claims: 1. A liquid crystal display, comprising two substantially parallel plates; a two-dimensional array of pixels constituted by liquid crystal cells (21), each cell having a first electrode (25) carried by one of the plates and a second electrode (43, 45) carried by the other plate; a plurality of first address lines (29, 31, 33); a plurality of second address lines (35,41; 37,43); a plurality of transistor means (47, 49) each associated with a respective one of the cells; and means to apply synchronised electrical pulses to a selected one of the first address lines and a selected one of the second address lines so as to switch the pixel associated with those two lines, the pulses applied to the selected lines being such that the polarity of the voltage applied to the pixel reverses periodically; characterised in that said first address lines are carried by one of the plates and said second address lines are carried by the other plate; and in that each pixel is constituted by a plurality of said liquid crystal cells. 2. A display according to Claim 1, characterised in that the transistor means is in the form of a thin film transistor (47, 49) carried by said other plate. 3. A display according to Claim 1 or Claim 2, characterised in that each first address line (29, 31, 33) is a stripe (25) of substantially the same width as a pixel of the display. 4. A display according to Claim 3, in which the width of each stripe (25) is reduced in regions where it crosses the lines (35, 41) carried on said other plate. 5. A display according to any preceding claim, in which each transistor means (47, 49) is connected to the associated second address line (35, 37) via an individual conductive track (42) which may be severed in the event of failure of the transistor means.

Inventors: HILSUM, CYRIL, VAN DE POEL, RENE JAN, Van de Poel, René Jan
Applicants: THE GENERAL ELECTRIC COMPANY, P.L.C.
Application year: 1986
Main classification: G02F1
IPC codes: G09G3, G02F1, G09F9