MICROPROCESSOR ASSISTED MEMORY TO MEMORY MOVE APPARATUS

Abstract: An apparatus for controlling data movement between a peripheral and a data processing system, comprises a memory (30) for storing data, wherein the memory com­ prises a plurality of memory modules. Each memory module corresponds to an assigned area of a first memory map, the first memory map being duplicated into a plurality of mir­ rored memory maps. Each mirrored memory map corre­ sponds to a predefined operation, a composite of the first memory map and the plurality of mirrored memory maps forming a total memory space. Each memory location within the total memory space is defined by a unique memory space address. A processor (10) performs a pseudo opera­ tion in response to a first control signal from the peripheral (40) indicating data is available for being moved. A logic circuit generates at least one control signal in response to the pseudo operation such that a predetermined data move­ ment operation occurs.

Description: The present invention relates to a memory access control circuitry in a data processing system according to the preamble of claim 1 and accomplishes information movement or data transfer within the data processing system between a memory unit and a peripheral controller with the processor being involved in assisting the information movement. In present data processing systems a time critical data movement problem is frequently encountered when data are transferred from a buffer in a peripheral controller to an ordered array of sequential locations in a memory unit of the random access type (RAM). In present data processing systems, the peripheral controller is usually equipped with a control line to indicate that data in its buffer register are ready to be transferred. This control line is usually connected to an interrupt terminal of the Processor. Upon the occurrence of a data ready signal at the interrupt terminal, the Processor causes a plurality of operations to be performed. These operations include saving the state of the data processing system. Data is moved from the buffer of the peripheral controller to an internal register of the Processor. Next, an index register is loaded with a previously saved pointer, and then the data is moved from the internal register to a location in RAM pointed to by the index register. The quantity in the index register is incremented and saved for the next data movement, and finally the data processing system is restored to the state existing before the interrupt occurred. If there is sufficient time to execute all of these steps before the peripheral controller has a data over-run, this method of data movement is simple and works very well. But, as data transfer speeds increase, especially in high density floppy, winchester or communications applications, the Processor will run out of time to perform all of the above operations before the next byte or word of data is available. A data transfer control method is known from the Japanese published patent application 59-72532 (A) (see Patent Abstracts of Japan, Vol.8, No.179 (P-295) 1616, August 17, 1984) providing a direct mutual transfer of data between storage and a peripheral device controller. In the addressing scheme the address bits of highest significance are used to select a certain memory segment in a memory map for the data transfer from memory to peripheral or vice versa. Since in this kind of data transfer the processor should not be involved with the task of data buffering, the data bus to the processor is interrupted (opened) and only a data bus connection between memory and peripheral control unit is maintained. A "no-operation" instruction is described as not performing any operations but merely putting an address and read/write control signals on the bus. Key in this structure is a NOP-generator which in the memory map has address spaces that are data storage and image-related address spaces. Thus address spaces of the memory modules (RAM and ROM) are mirrored to the NOP address space. The circuitry selects both the NOP-generator and the RAM-module at a time and sets an address space of the RAM equal to the NOP. The peripheral device controller performs read/write operations of a byte every time the NOP selection signal is inverted and supplied to the controller. Despite the fact that in this structure the data are transferred directly and mutually with an accelerated processing speed the circuitry is still complex in that it requires a special NOP-generator and switching operations to isolate the data bus from the processor. Hence, there is still a need to provide a circuitry for performing the desired data movement at the high speed transfer rates required in the aforementioned applications which circuitry is less komplex than the circuitry which is provided for the above mentioned method. Therefore, it is an object of the present invention to provide an improved circuitry to perform high-speed data move operations in a data processing apparatus. This and other objects are achieved by a circuitry as characterized in claim 1 and will become more apparant when taken in conjunction with the following description and attached drawings showing a preferred embodiment of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a block diagram of a data processing system in which the present invention can be employed; Figure 2 shows a defined memory map of the preferred embodiment of the present invention; Figure 3 shows a block diagram of physical memory of the preferred embodiment of the present invention; Figure 4, which is comprised of Figures 4A and 4B, shows input and output connections to a multiplexer for switching control signals thereby activating the appropriate circuitry to accomplish the desired operation; Figure 5 shows a logic block diagram of enable logic; and Figure 6 shows the steps in an interrupt routine performed by a microprocessor of the data processing system of the preferred embodiment of the present invention to initiate the data move operation. DETAILED DESCRIPTION Referring to Figure 1, there is shown a block diagram of a data processing system in which the present invention can be employed. A microprocessor (up) 10 is operatively connected to a bus 20, having data and address lines. A memory 30 and a peripheral controller 40 are also operatively connected to the bus 20. A peripheral device 45 is operatively connected to the peripheral controller 40. Although, the preferred embodiment of the present invention specifically shows a disk controller and a disk device for the peripheral controller 40 and the peripheral 45, respectively, it will be understood by those skilled in the art that the present invention is applicable to a wide variety of peripheral controllers and peripheral devices. The peripheral controller 40 includes a buffer (or peripheral register) 41 which temporarily stores data from the bus 20 or from the peripheral 45. The discussion hereinunder focuses on transfers between the peripheral controller 40 and the data processing system, i.e., the memory 30 and the microprocessor 10, to specifically cover the peripheral controller 40 - data processing system interface rather than the peripheral controller 40 - peripheral device 45 interface Referring to Figure 2, there is shown a memory map of the preferred embodiment of the present invention. The memory 30 (also referred to herein as memory modules) of the data processing system of the preferred embodiment of the present invention is mapped to four 16K segments, the four segments forming a total memory space. Sixteen address lines A₁₅ - A₀ where A₀ is the least significant bit, are utilized in bus 20. The upper 16K segment (locations C000 - FFFF hexadecimal, all memory locations given herein are in hexadecimal) is mapped to include a 4K ROM from locations F000 - FFFF, and 8K RAM from locations D000 to EFFF, and an I/O register at location C000. For this defined upper 16K segment of memory, address bits A₁₅ and A₁₄ are both a logic one. This upper 16K segment of memory is also referred to herein as the first 16K segment of memory. The next, or second, 16K segment of the defined memory map from location 8000 to BFFF includes a 4K ROM image, an 8K RAM image, and an I/O register image which mirrors (or duplicates) the first 16K segment. In the second 16K segment of defined memory, A₁₅ is a logic one and A₁₄ is a logic zero. The third 16K segment of the defined memory map from locations 4000 to 7FFF also includes a 4K ROM image, an 8K RAM image and an I/O register image which mirrors the upper 16K segment. In the third 16K segment of defined memory, A₁₅ is a logic zero and A₁₄ is a logic one. The fourth (or lower) 16K segment of the defined memory map from locations 0000 to 3FFF is not utilized in the preferred embodiment of the present invention. The second 16K segment of memory is addressed when a data movement is to be performed from the peripheral register 41 to RAM memory, and the third 16K segment of memory is addressed when a data move operation is to be performed from memory to the peripheral register 41. This operation will be described in further detail hereinunder. The addresses 0000-FFFF are the memory space addresses within the total memory space. Referring to Figure 3, there is shown a block diagram of the first segment of physical memory 30 of the preferred embodiment of the present invention. The first segment of memory 30 of the preferred embodiment of the present invention includes a 4K ROM memory module 30-3 having real addresses 000 - FFF, a first 4K RAM1 memory module 30-1 having real addresses 000 - FFF, and a second 4K RAM2 memory module 30-2 having real addresses 000 - FFF and further having pseudo addresses 1000 - 1FFF. Address lines 21, A₁₁ - A₀ of bus 20, are operatively connected to the corresponding 12 terminals of the ROM 30-3, RAM1 30-1 and RAM2 30-2. These 12 address lines which carry the corresponding address signals from microprocessor 10 are sufficient to address any location within a 4K space. A₁₅, and A₁₄ are the upper bits utilized to address one of the 16K segments, and A₁₃, A₁₂ are utilized to address a module within the selected 16K segment. In order to avoid memory accesses to a location within the multiple 4K modules, an enable signal is coupled from control logic 50. The control logic 50 generates the proper enable signal by decoding address information contained on address lines A₁₅ - A₁₂, the control logic 50 to be described in detail hereinunder. An enable signal from control logic 50 is also coupled to an enable terminal, E, of peripheral register 41. Data lines 22 of bus 20 are connected to the corresponding data terminals, D, of the ROM and RAM memory modules and the data terminals of the buffer module in which peripheral register 41 is located. It will be understood that if more than a single peripheral register 41 is utilized in the peripheral controller 40, address lines 21 can be coupled to corresponding address terminals of the peripheral registers (not shown) in order to address a single peripheral register. Referring to Figure 4A and 4B, which together make up Figure 4, there is shown a block diagram of a multiplexer, MUX, 51 which switches the control signals from the control logic 50 to the appropriate memory module 30 and/or peripheral register 41, thereby achieving the desired operation. The microprocessor read strobe signal is connected to input terminal A0, C0, B1, A2, B2, and C3. Input terminal B0, C1, C2, and B3 are tied to a logic zero which is effectively a disabling signal. The microprocessor write strobe signal is connected to input terminals A1 and A3. The output of MUX 51, outputs 0 - 3 are connected to the RAM/ROM read strobe terminal of the memory modules 30, RAM write strobe terminal of RAM 30-1, 30-2, peripheral read strobe terminal, and peripheral write strobe terminal, respectively. Address signals A₁₅ and A₁₄ are utilized to select between input terminals A, B, and C, in accordance with the table of Figure 4B. In a normal operation by the microprocessor 10 in which the microprocessor is accessing the memory modules 30 and/or the peripheral register 41, the microprocessor is addressing memory space in which A₁₅ and A₁₄ are a logic one. Hence, the A input terminals of MUX 51 are selected. In this case the microprocessor read strobe signal is coupled to the RAM/ROM read strobe terminal and is also coupled to the peripheral read strobe terminal via output terminal 2. Hence, normal reads are made from the ROM 30-3, RAM 30-1, 30-2, or the peripheral register 41 by the microprocessor 10. When write operations are performed, the microprocessor 10 again addresses address space is which A₁₅ and A₁₄ are both a logic one and the write strobe signal is coupled to the RAM write strobe terminal or the peripheral write strobe terminal as a function of the particular address, thereby performing normal write operations to the RAM 30-1, 30-2 or the peripheral register 41. In an I/O operation, the microprocessor 10 also acts as a controller. When the peripheral register 41 has data to be transferred, assuming a read operation of the peripheral device 45, the data ready signal is generated by the peripheral controller 40, thereby interrupting the microprocessor 10. The microprocessor 10 then causes the data stored in peripheral register 41 to be directly inputted into memory bypassing the operation of reading the data into an internal register of the microprocessor and then outputting the data into memory 30. The microprocessor performs a "dummy read" of the RAM address in which the data is to be stored. The address space addressed is the second 16K of the defined memory map in which A₁₅ and A₁₄ are a logic one and a logic zero, respectively. This causes the B input terminals of MUX51 to be selected. The "dummy read" from the microprocessor causes the read strobe signal to be coupled via input B1 to the RAM write strobe terminal. The microprocessor "dummy read" also causes the read strobe signal to be coupled via input B2 to the peripheral read strobe terminal, the peripheral write strobe being disabled by the logic zero input via input B3. Hence, the peripheral operation is a read, or output of the data, the data being placed on the data lines 22 and the RAM accepts the data that is present on the data lines 22 and is written into the RAM at the address specified on the address lines, the address being the address of the "dummy read" operation. Hence, data is transferred directly from the peripheral register 41 into the RAM and bypasses the transfer of the data into the microprocessor 10. RAM1 30-1 and RAM2 30-2 both have addresses corresponding to the address on the address line but only a single RAM, i.e., either RAM1 or RAM2, is selected as a function of the enable signal. The generation of the proper enable signal to select the correct RAM, i.e., RAM1 or RAM2, will be discussed hereinunder. When a write operation from memory to the peripheral register 41 is to be performed, the microprocessor performs a "dummy read" operation of the address in memory to be read, and addresses the third 16K area in which A₁₅ is a logic zero and A₁₄ is a logic one, this area having been defined as the data move from memory to the peripheral, this having been described in conjunction with Figure 2 above. In this memory space input terminals C are selected. In this case the microprocessor "dummy read" causes the microprocessor read strobe signal to be coupled to the RAM read terminal and also causes the microprocessor read strobe signal to be coupled to the peripheral write terminal. Hence, the data is placed on the data lines 22 from the RAM and the data present on the data lines 22 is written into the peripheral register 41. Again, the enable signals coupled to the memory modules 30 cause data from a single RAM 30-1, 30-2, or ROM 30-3 to place data on the data lines 22. This operation again bypasses the microprocessor having to read the data into an internal register and then outputting the data to the peripheral controller 41. The logic zero connected to the input terminals assures the control signal is zero, disabling the particular function. The D input terminals of MUX51 are not utilized in the preferred embodiment of the present invention. Referring to Figure 5, there is shown a block diagram of enable logic 52 of the control logic 50. The enable logic 52 generates an enable signal for each of the memory modules 30-1, 30-2, 30-3, and for the peripheral register 41, the enable signal being coupled to the corresponding enable terminal, E, of each module. When the microprocessor 10 is accessing the memory modules 30 or the peripheral register 41, the first 16K address space is utilized and A₁₅ and A₁₄ are both a logic one, enabling a first (2:4) decoder 53. The decoder decodes the signals associated with address lines A₁₃ and A₁₂. These two signals identify the particular module being addressed. Hence when A₁₃ is a logic zero and A₁₂ is a logic zero, the peripheral register 41 is being addressed by the microprocessor, and the enable signal is coupled to the peripheral register 41 via an OR gate 57. When A₁₃ and A₁₂ are both a logic one, the ROM module 30-3 is being addressed and the enable signal is directly coupled to the ROM. When the RAM is being addressed by the microprocessor 10, for address locations between D000 and DFFF, A₁₃ is a logic zero and A₁₂ is a logic one, thereby generating an enable signal which enables OR gate 55 allowing accesses to RAM1 30-1. Similarly, when the microprocessor is addressing memory locations E000 through EFFF of RAM the first decoder 53 decodes A₁₃ as a logic one and A₁₂ as a logic zero generating an enable signal which enables OR gate 56 thereby allowing accesses to RAM2 30-2. In the movement of data between the peripheral register 41 and the RAMS 30-1, 30-2, a second (2:4) decoder 54 is enabled which enables either RAM1 30-1 or RAM2 30-2 as a function of the address information signals on address lines A₁₃ and A₁₂, the corresponding enable signal being coupled to the OR gate 57 for enabling the peripheral register 41 and the corresponding RAM1 or RAM2. A read or write operation of the peripheral register 41 or the RAM 30-1, 30-2 is a function of the control signals from the multiplexer 51. Referring to Figure 6, there is shown the operations performed by the interrupt routine of the microprocessor. As discussed before, when the peripheral register 41 is full and contains data ready to be transferred, the data ready signal is generated and is coupled to the interrupt terminal of the microprocessor 10. The microprocessor performs the operations of the interrupt routine of Figure 6. Namely, a first overhead operation is performed which requires saving the machine state and initializing a pointer which defines the memory location in which the data is to be stored. A "dummy read" is then performed to the location in which a data access is to be made, the location being defined in address bits A₁₃ - A₀. The address space addressed by bits A₁₃ - A₀ is sufficient to address any location within the defined 16K. A₁₅ and A₁₄ are included in the address signals placed on the address lines 21 which define which operation is to be performed, the type of operation being equated to one of four 16K areas as defined by the memory map as discussed above. Once the "dummy read" operation is performed, the second overhead operation is executed which essentially restores the pointer and restores the machine state. Then the interrupt routine is exited and the microprocessor continues to perform or execute its application program or task which was underway prior to the interrupt. In the preferred embodiment of the present invention, a Motorola 68000 microprocessor is utilized, and the steps required to perform the various overhead operation are minimized. This reduces the amount of overhead, thereby reducing the amount of time within the interrupt routine. This reduction in overhead allows the microprocessor to perform its task and also act as a direct memory access controller and not encounter an over-run condition. (An over-run condition occurs when the next piece or quantum of data is available in the peripheral register 41 before the microprocessor has had a chance to move the previous piece of data.) It will be understood by those skilled in the art that outputting data from memory 30 to the peripheral register 41 a similar operation is performed. Namely, a data request signal from the peripheral register is coupled to the microprocessor 10 which results in an interrupt to the microprocessor 10. A "dummy read" in the interrupt routine is then performed from the third 16K memory space in which A₁₅ is a logic zero and A₁₄ is a logic one.

Claims: Memory access control circuitry in a data processing system which includes: a memory (30) comprising a plurality of addressable locations (16 kBytes) for storing data in different memory modules (RAMs 30-1, 30-2, ROM 30-3), peripheral units (45) coupled to a peripheral controller (40) comprising a peripheral register (41) which subsequent to the issuance of a data request signal receives data read from said memory (30) and which subsequent to the issuance of a data ready signal transfers data for writing into said memory (30), said data request and data ready signals being generated by said peripheral controller (40) whenever occasion arises, a processor (10) capable of responding to the said data request and data ready signals whenever they are received from said peripheral controller (40), a bus (20) coupling together said memory, said peripheral controller (40) and said processor (10) for direct data transfer between the said units (10, 30, 40), said bus comprising a data bus (22) for transferring the data between the said units (10, 30, 40), and an address bus (21) for the transfer of address bits, a first subgroup (14) of the total available (16) address bits representing the address access bits (A₁₃ - A₀) sufficient in number to access all of said memory locations (16 kBytes), and a second subgroup (2) of the total available (16) address bits representing the address control bits (A₁₅, A₁₄) for enabling direct transfer of data over said data bus (22), a control logic circuit (50) to enable the access to the data in said memory (30) and/or in said peripheral register (41), said control logic circuit comprising a multiplexer (51) steering, under control of said address control bits (A₁₅, A₁₄), read/write signals (µP read and µP write strobe), supplied to its inputs (A0-3, B0-3, C0-3), to the units involved in said data transfer to effect reading and writing of said data from or into the accessed storage locations of said units involved and transferring said data over the data bus (22), and address decoder means (52) responsive (at E of 53/54) to different configurations of said address control bits (A₁₅, A₁₄) to determine by this configuration the mode of data transfer between the units involved and to deliver, at output terminals (55, 56, 57) of the said address decoder means, output signals fed to the enable terminals (E of 30/41) of the memory modules and of the peripheral register to enable these to be operational and respond to the said read/write signals (RAM/ROM read, RAM write, peripheral read, peripheral write) delivered by said multiplexer (51), whereby a first of said configurations of the said address control bits (A₁₅="1"; A₁₄="1") enables the processor (10) to access in a normal data transfer mode the memory (30) or the peripheral register (41) for reading data therefrom or supplying data thereto, a second of said configurations of said address control bits (A₁₅="1"; A₁₄="0") effects direct memory access in a first direct access data transfer mode (MOVE PER ---> MEM) whereby data are transferred from said peripheral register (41) to said memory (30), and a third of said configurations of said address control bits (A₁₅="0"; A₁₄="1") effects direct memory access in a second direct access data transfer mode (MOVE MEM ---> PER) whereby data are transferred from said memory (30) to said peripheral register (41), and whereby whenever the first configuration of said address control bits (A₁₅="1"; A₁₄="1") is valid, only one decoder means output terminal delivers an enable signal to the units (30-1 or 30-2 or 30-3 or 41) involved, and whenever the second or third configuration of said address control bits (A₁₅, A₁₄ = "1 0" or "0 1") is valid, two decoder means output terminals deliver enable signals to the said units coupled thereto to effect direct transfer of data over said data bus (22) between the two units so enabled, and whereby data transfer in the two direct access transfer modes is performed without resorting to an internal register of said processor (10), characterized in that the processor (10) in response to the receipt of the said data request or data ready signals performs an interrupt routine (Fig. 6) which includes a read command (Overhead 2: "dummy read") by which a first set of address access bits (A₁₁ - A₀) is applied to said address bus (21) to identify the storage locations in said memory (30) for data access, and a second set of at least two address access bits (A₁₃, A₁₂) is applied to the address decoder means (52) of the control logic circuit (50) to enable the access to the data in said memory (30) and/or in said peripheral register (41), the said address control bits (A₁₅, A₁₄) are applied to said address decoder means (52) of the control logic circuit (50) for the determination of the mode of data transfer between the units involved, and read and write strobe signals (µP read and µP write) are generated which are supplied to the inputs (A0-3, B0-3, C0-3) of the multiplexer (51) for their steering, under the control of the address control bits, to the units involved in said data transfer, and further characterized in that the said decoder means (52), in response to the second and third configurations of said address control bits (A₁₅, A₁₄ = "1 0" or "0 1"), steers the said at least two address access bits (A₁₃, A₁₂), after their decoding (2:4), to the said decoder means output terminals in such different ways that whenever the second configuration of said address control bits (A₁₅, A₁₄ = "1 0") is valid, two decoder means output terminals deliver enable signals to the respective units coupled thereto, and whenever the third configuration (A₁₅, A₁₄ = "0 1") is valid, another pair of decoder means output terminals deliver enable signals to the respective units coupled thereto to effect the direct transfer of data over said data bus (22) between the two units without disrupting the connective integrity of said data bus (22) with the processor (10). Memory access control circuitry according to claim 1, characterized in that the output terminals (⊘ - 3) of said multiplexer (51) are coupled to said memory modules (RAM1, RAM2, ROM; 30-1, 30-2, 30-3) and to said peripheral register (41) for transferring to them the read/write strobe control signals, whereby a first output (⊘) delivers a first (RAM/ROM) read strobe signal to those memory modules which are capable of delivering stored data; a second output (1) delivers a first (RAM) write strobe signal to those memory modules which are capable of accepting data for storage; a third output (2) delivers a second (peripheral) read strobe signal to the peripheral register (41) to initiate the reading of data therefrom; and a fourth output (3) delivers a second (peripheral) write strobe signal to the peripheral register (41) to initiate the writing of data therein. Memory access control circuitry according to claim 1, characterized in that said decoder means (52) comprise a first decoder (53) whose output terminals (00, 11, 10, 01) are respectively coupled to each of said memory modules (30-1, 30-2, 30-3) and said peripheral register(41), and a second decoder (54) whose output terminals (10, 01) are respectively coupled always to the peripheral register (41) and to a different memory module (01 of 54 via 55 to 30-1 and via 57 to 41; 10 of 54 via 56 to 30-2 and via 57 to 41). Memory access control circuitry according to claim 2, characterized in that the multiplexer (51) provides output signal combinations as follows: the first read strobe signal and the second read strobe signal in response to a read control signal (µP read) and to the said one configuration (A14/A15 = 11) of said address control bits; the first write strobe signal and the second write strobe signal in response to a write control signal (µP write) and to the said one configuration (A14/A15 = 11) of said address control bits; the second read strobe signal and the first write strobe signal in response to a read control signal (µP read) and to the said second configuration (A14/A15 = 0 1) of said address control bits; and the second write strobe signal and the first read strobe signal in response to a read control signal (µP read) and to the said third configuration (A14/A15 = 1 0) of said address control bits. Memory access control circuitry according to any one of the preceding claims, characterized in that the peripheral controller (40) produces data ready control signals when the data is to be transferred between the peripheral register (41) and the memory (30), whereupon the processor (10) performs an interrupt routine and together with the read control signal (µP read) produces the required address access and address control signals (A⊘ - A15) to access the respective memory module to effect the data transfer with respect to the peripheral register (41). Memory access control circuitry according to any one of the preceding claims, characterized in that the desired storage location in a memory module which is activated through a select control signal at its enable terminal is addressed through the address access bit (A₁₁-A₀) signals sent over the address bus lines (21) whereby so many address access bits are provided in the said first set of address bits as are required to address the memory module selected (12 bits A₁₁-A₀ for a memory space of 4 kBytes). Memory access control circuitry according to claim 6, characterized in that the memory (30) comprises at least two random access modules (RAM 30-1, 30-2) and at least one read-only memory module (ROM 30-3), each of these memory modules having a plurality (4 kBytes) of addressable locations which are addressed by a plurality of address access bits (A₁₁-A₀) commensurate in their number to unequivocally address the total address space available in each memory module.

Inventors: FREIMARK, RONALD J., ROSE, STEVEN A.
Applicants: HONEYWELL INC.
Application year: 1986
Main classification: G06F13
IPC codes: G06F13