METHOD AND APPARATUS FOR ADJUSTING A DIGITAL EQUALIZING FILTER IN SIMULTANEOUS ADAPTIVE ECHO ELIMINATION AND ADAPTIVE ELIMINATION OF NOISE CAUSED BY INTERSYMBOL INTERFERENCE

Abstract: A method and apparatus for adjusting a digital equalizing filter (U) in a hybrid circuit in a telecommunication system for transmitting digital information in duplex on a single line pair with simultaneous adaptive echo elimination and adaptive elimination of noise caused by intersymbol interference, where a first and a second compensation signal (ê(t), î(t)), which are respectively dependent on the stored parameters of a digital balance filter (B) and the equalizing filter (U), are subtracted from a received signal (a(t) + e(t) + i(t)) to form a difference signal (r(t)) which is compensated for noise respectively caused by echoes and intersymbol interference, the balance filter parameters being corrected with the aid of a correction signal ( epsilon Bk) dependent on the difference signal (r(t)). The equalizing filter parameters are adjusted with the aid of a further correction signal ( epsilon Uk) formed by the balance filter correction signal ( epsilon Bk) and the first compensation signal (ê(t)) such that the further correction signal ( epsilon Uk) will substantially agree with the balance filtercorrection signal ( epsilon Bk), but obtain the value zero when the first compensation signal (ê(t)) and the balance filter correction signal ( epsilon Bk) are both positive simultaneously or negative simultaneously. There is thus prevented the correction sequence of the equalizing filter parameters when the balance filter parameters are changed in a direction such that the absolute amount of the estimated echo (ê(t)) increases.

Description: METHOD AND APPARATUS FOR ADJUSTING A DIGITAL EQUALIZING FILTER IN SIMULTANEOUS ADAPTIVE ECHO ELIMINATION AND ADAPTIVE ELIMINATION OF NOISE CAUSED BY INTERSYMBOL INTERFERENCE TECHNICAL FIELD The invention relates to a method and apparatus for adjusting a digital equalizing filter at a hybrid circuit in a telecommunication system for transmitting digital information in duplex over a single line pair, with simultaneous adaptive echo elimination and adaptive elimination of noise caused by intersymbol interference, a first and a second compensation signal being subtracted from a received signal to form a difference signal, where the first signal is dependent on the stored parameters of a digital balance filter and the second signal is dependent on corresponding parameters of said equalizing filter, the difference signal being compensated for noise caused by echoes and intersymbol interference, and where the parameters of the balance filter are corrected with the aid of a first correction signal which varies in response to - the difference signal. BACKGROUND ART Adaptive echo elimination and adaptive elimination of noises caused by intersymbol interference are usually resorted to in telephony and data communication technology for improving transmission quality. Echo noises come from the signal of the local transmitter and occur as leakage signals in hybrid circuits as well as echoes at the remote end and in inhomogenous lines. Noises caused by intersymbol interference come from the signal from the remote end and occur particularly at transmission on inhomogenous lines. To reduce the effect of these two kinds of noise it is already known to utilize a balance filter and an equalizing filter of the digital type. With guidance from a given number of digital data symbols sent from the local transmitter, the balance filter forms an estimation of the expected value of the echo, and with guidance from a given number of the latest received digital data symbols the equalizing filter forms an estimate of the expected value of the intersymbol interference. The estimates formed by the filters are subtracted from the received signal, the difference signal being subsequently utilized for determining the value of the received data symbols and for correcting the filter parameters. These parameters are adjusted automatically so that the deviations between the true and the estimated echo and between the true and the estimated intersymbol interference will be as small as possible. After the adjustment of the parameters they are not altered at all or only insignificantly. It is then usual to say that the filters have converged. In certain cases the convergence time for a balance filter or an equalizing filter will be of comparatively long duration or it may even be impossible to achieve convergence. An advantageous convergence method solely for a balance filter is described in tha Swedish patent application No 8106444-6. In simultaneous adaptive echo elimination and adaptive elimination of noises which are caused by intersymbol interference there are, however, special problems with adjusting the filter parameters, due to the residue echo signal usually being much greater than the signal from the remote end before the filters have converged. This causes the equalizing filter to adjust itself in principle as a further balance filter, with the consequence that convergence will be slow and uncertain. The problem is discussed in an article published in "IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS", VOL SAC-2, NO 2, MARCH 1984, pp 314-323. In 'THE BELL SYSTEM TECHNICAL JOURNAL", VOL 58, No 2, FEBRUARY 1979, pp 491 - 500 the adjustment of the filter parameters is analyzed with the condition that the received data is perfectly regenerated, which is very unlikely, according to the above. DISCLOSURE OF INVENTION The object of the present invention is to achieve secure and rapid convergence with a method and apparatus of the kind given in the introduction. This is achieved by the correction process of the equalizing filter parameters being prevented when the balance filter parameters are changed in a direction such that the absolute amount of the first compensation signal depending on these parameters increases. This means that the equalizing filter parameters are not adjusted before the balance filter parameters have been adjusted sufficiently, whereby the tendency of the equalizing filter to adjust itself as a further balance filter is avoided. The distinguishing features of the invention are disclosed in the claims. BRIEF DESCRPTION OF DRAWINGS The invention will now be described in detail with reference to the drawings, whereon Figure 1 is a principle sketch of a conventional apparatus for simultaneous adaptive echo elimination and adaptive elimination of noises caused by inter¬ symbol interference, Figure 2 is a principle sketch of an apparatus improved in accordance with the present invention, and Figures 3-6 are more exhaustive block diagrams of different embodiments of the invention. BEST MODES FOR CARRYING OUT THE INVENTION Figure 1 is a principle sketch of a conventional apparatus for simultaneous adaptive echo elimination and adaptive elimination of noises occurring due to intersymbol interference. A data sequence b. consisting of "ones" and "zeros" is supplied to a transmitter unit S implemented as a code converter for converging the data sequence to a signal b(t) e.g. one that is biphase coded. The signal b(t) is applied conventionally to a line L via a hybrid circuit G for transmission to a receiver at the remote end. A simultaneously received signal a(t) sent from the remote end, this signal being superimposed with noises caused by echoes e(t) stemming from the local end signal b(t) and by intersymbol interference i(t) stemming from the remote end signal a(t), is filtered in a receiver filter F and subsequently applied to a subtraction circuit SI. The output signal e(t) and i(t) respectively from a balance filter B and an equalizing filter U are subtracted in the subtraction circuit SI from the received and filtered signal, to compensate the latter for noises caused by echoes and intersymbol interference. In practice, the outputs of the filters B and U are connected to the circuit SI via their respective digital-analogous converters, which has not been noted in the figure, however. The difference signal r(t) from the circuit SI is applied to a sampling circuit SH, which sends a data sequeπcy π , the values of which correspond to the values of the signal r(t) at the sampling instants. The sequence r. is quantized in a quantization circuit Q, which is assumed to be a comparator, for the sake of simplicity, and which decides whether the sample values are greater or less than zero. The quantization circuit output signal a. constitutes an estimate of the value of data a. sent from the remote end, and is applied to an unillustrated receiver. The parameters of the filters are corrected with the aid of a correction signal ε . , which in the simplest case agrees with the sequence r. from the sampling circuit SH. For example, the corrections may take place in response to the result of corrections between the error signal ε . and the transmitted sequence b. or between ε . and the received estimated sequence a. . Methods for this will be understood from the articles mentioned above and the Swedish patent specification mentioned above. In an apparatus of this kind including a balance filter and an equalizing filter there is, however, as mentioned above, great risk that the filters have long and uncertain convergence. Figure 2 is a principle sketch of an apparatus improved in accordance with the invention. The apparatus differs from the one according to Figure 1 in that a block K has been connected between the sampling circuit SH and equalizing filter U for correction of the correction signal ε 0 f the latter. The filters will thus obtain correction signals which are not always identical, and therefore these signals are denoted εB. and ε U. hereinafter. According to the inventive concept, the correction signal εU. of the equalizing filter U is formed by the correction signal ε B. of the balance filter B and the balance filter output signal e(t), i.e. the estimated echo, such that u. is given a positive value if ε B. has a positive value simultaneously as " e(t) has a negative value, a negative value if εB. has a negative value simultaneously as e(t) has apositive value and otherwise the value zero. What is new and specific is that the correction signal ε U. of the equalizing filter U is thus given the value zero, not only when the correction signal ε ~ B. of the balance filter B is zero, but also when the balance filter correction filter has the same sign as the filter output signal e(t). This results in that the correction sequence of the equalizing filter U is prevented when the parameters of the balance filter B are changed in a direction such that the absolute amount of the signal e t) increases. This happens when the estimated echo is changed in a positive direction from a positive value or in a negative direction from a negative value. A more detailed block diagram of a first embodiment of the invention is illustrated in Figure 3. The embodiment agrees with the embodiment in Figure 1 according to the mentioned Swedish patent specification 8106444-6, with regard to the balance filter B and the adjustment circuits for it. There is thus utilized a multiplication circuit Ml, a subtraction circuit S2, a sign-forming circuit-SGl, an addition circuit A, a reference unit V, which supplies a variable reference value v(k), and correction units KV, KB. With the aid of these there is formed a sign signal sign (f. ) of the difference f. between the sampled sequence r. and the product of the estimated data sequence a. and the variable reference value v(k), with the correction signal ε _3. of the balance filter B being subsequently formed as the sum of this sign signal and the value of a. . The reference value v(k) and the balance filter parameters are corrected with the aid of the correction units KV, KB in a manner apparent from the patent specification mentioned. As is also apparant from this, the reference levels in the reference unit may possibly control the levels in the quantizer Q as indicated by the dashed connection between the reference unit V and the quantizer Q. The equalizing filter parameters are corrected with the aid of a correction unit KU, which may be of an implementation identical to the balance filter correction unit KB. The communication between the reference unit V and the correction units KB and KU is not necessary and has therefore been drawn dahsed. The convergence is accelerated, however, if there is this communication. The sign signals sign ( εβ. ) and sign (e(t)) are formed in the block K by the balance filter correction signal ε B. and the balance filter output signal e(t) in respective sign-forming circuits SG2 and SG3. The difference between these sign signals is formed in a subtraction circuit S3, the equalizing filter correction signal u k being subsequently formed as the product of this difference and the absolute value of the signal ε B. with the aid of an absolute value-forming circuit AB and a multiplication circuit M2. The table below shows how the equalizing filter correction signal ε U. is dependent on the b.alance filter correction signal ε Q. and the balance filter output signal ett). It will be seen from the table that ε U. has the same sign as ε B. when ε B. and e(t) have different signs, ε U. is zero when ε B^ is zero and when ε B. and e(t) have the same sign. εB. is positive when the received sample r^ is simultaneously positive and greater than the variable reference value v(k), equal to zero when -the absolute amount of the sample r. is less than the absolute amount of the reference value v(k) and negative when the sample r. is simultaneously negative and less than the reference value v(k). Figure 4 is a block diagram of a second embodiment of the invention. In this the balance filter correction signal ε B. is formed in a somewhat more simple way than in the embodiment according to Figure 3. There is thus no addition circuit A, resulting in that the value of the correction signal ε B. will either be +1 or -1 but never zero. In this embodiment the block K merely comprises the sign-forming SG3 and the subtraction circuit S3. The dependence on εB. and e(t) of the equalizing filter correction signal ε U k will be seen from the table below. A third embodiment of the invention is illustrated in Figure 5. This embodiment differs from the one according to Figure 3 in that adaptive gain regulation is applied. Here, one input of the multiplication circuit Ml is supplied with a fixed reference voltage G instead of the variable reference voltage v(k). The voltage v(k) is multiplied by the sample values r k in a further multiplication circuit M3, instead. The gain will be adjusted so that r k multiplied by V[< will be approximately equal to a k multiplied by G. This apparatus is otherwise implemented in the same way as that in Figure 3, and therefore its function will substantially agree with that of the apparatus in Figure 3. The dependence of the correction signal ε U k on ε B k and e(t) also agrees with the corresponding dependence in the apparatus of Figure 3. A fourth embodiment of the invention is illustrated in Figure 6. This is partly based on a principle known from the IEEE article, e.g. the Figure 10. Adaptive gain regulation is applied, as with the embodiment according to Figure 5. However, in contradistinction to this embodiment there is utilized the output signal from an analogue-digital converter AD, the input of which obtains the input signal of the quantizer Q as the correction signal ε B k for the balance filter B. The values of the correction signal ε B k may thus vary continuously. The block K has the same implementation as in Figure 5. The dependence on ε B k and e(t) of the correction signal ε U k is shown in the table below. The ratio between the correction signals ε U k and ε B k (+2) apparent from the tables shown in conjunction with the different embodiments may naturally be changed by suitable modification of the circuits. The essential and common distinguishing feature in all the embodiments is that ε U. is given the value , "V zero when B and e(t) are both simultaneously positive or negative. It is also conceivable to introduce an analogue digital converter after the receiver filter F for subsequently solely utilizing digital circuits.

Claims: CLAIMS 1 Method of adjusting a digital equalizing filter (U) at a hybrid circuit in a telecommunication system for transmitting digital information in duplex over a single line pair with simultaneous adaptive echo elimination and adaptive elimination of noise caused by intersymbol interference, where a first and a second compensation signal, the first signal (eXt)) being dependent on the stored parameters of a digital balance filter (B) and the second (Kt)) being dependent on corresponding parameters of said equalizing filter (U), are subtracted from a received signal (a(t) + e(t) + i(t)) to form a difference signal (r(t)) which is compensated respectively for noise caused by echoes and intersymbol inter- ference and where the balance filter parameters are corrected with the aid of a first correction signal ( ε B k ) dependent on said first difference signal (r(t)), characterized in that the equalizing filter parameters are adjusted with the aid of a second correction signal (ε U. ) formed by said first correction signal ( ε B k ) and by said first compensation signal (e(t)) such that is is given a positive value when the first correction signal ( ε B. ) has a positive value simultaneously as the first compensation signal (e(t)) has a negative value, in that it is given a negative value for the reverse relationship and in that it is otherwise given the value zero, whereby the correction sequence for the equalizing filter para¬ meters is prevented when the balance filter parameters are changed in a direction such that the absolute amount of the first compensation signal (e(t)) increases. 2 Apparatus for carrying out the method in accordance with claim 1 for adjusting a digital equalizing filter (U) at a hybrid circuit in a tele¬ communication system for transmitting digital information in duplex over a single line pair with simultaneous adaptive echo elimination and adaptive elimination of noise caused by intersymbol interference, where a first and a second compensation signal, the first signal (e(t)) being dependent on the stored parameters of a digital balance filter (B) and the second signal (lit)) being dependent on corresponding parameters of said equalizing filter (U), are subtracted from a received signal (a(t)+e(t)+i(t)) to form a difference signal (r(t)) which is compensated respectively for noise caused by echoes and intersymbol interference, and where the balance filter parameters are corrected with the aid of a first correction signal ( εB ) dependent on said difference signal (r(t)) characterized in that the equalizing filter parameters are adjusted with the aid of a second correction signal (ε U. ) formed by a circuit arrangement (K) which obtains said first correction signal (ε B. ) and said first compensation signal (eXt)) and is implemented such that this second correction signal ( ε U is given a positive value when the first correction signal ( εB k ) has a positive value simultaneously as the first compensation signal Ce(t)) has a negative value, and that it is given a negative value for the reverse condition and that it is otherwise given the value zero, whereby the correction sequence for the equalizing filter parameters is prevented when the balance filter parameters are changed in a direction such that the absolute amount of the first compensation signal (e(t)) increases.

Inventors: BAUER ANDERS GUSTAV, BAUER, ANDERS, GUSTAV
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET L M ERICSSON
Application year: 1986
Main classification: H04B3
IPC codes: H04B3