SWITCHING CIRCUIT HAVING HIGH SPEED/POWER RATIO

Abstract: A logic inverter or NOR circuit exhibits push-pull output characteristics by employing a saturated (T3) feedback technique. This approach allows for emitter follower like up level drive (by T2) and transient low impedance down level drive (through T1 and T3). The disclosed saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation.

Description: Background of the Invention and Prior Art This invention relates to logic circuits and more particularly to transistor switching circuits having a high speed and a low power consumption. In the development of data processing equipment, extensive effort is being directed to integrated circuits having improved speed capabilities and speed/power factor. VLSI logic circuits are often required to drive high output load capacitance which is comprised of the capacitance due to circuit fan-out and also the capacitance of the interconnection metalization which can be substantial. In particular, as the logic circuit density and chip size increases for VLSI technologies, the requirement exists for logic circuits having the capability to drive high-capacitance on-chip loads at acceptable speed/power factors. Prior art bipolar logic circuits such as DTL, TTL and ECL must operate at high power levels if low delay is required at high load capacitance. This relationship is due to the fact that active drive is available for only one output transition, while the other transition depends on the time constant of the output load resistance and capacitive load. A technique to achieve good capacitive drive is to incorporate a push-pull circuit in the output. The push-pull circuit is well known to the art and is used extensively in off-chip drivers and also in complementary NPN/PNP bipolar circuits. The logic circuit in accordance with the subject invention exhibits push-pull output characteristics by employing a saturated feedback technique. This approach allows for emitter follower like up level drive and transient low impedance down level drive. The saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation. As with other circuits containing push-pull outputs, the logical dot function is to be avoided, to eliminate a circuit contention problem. There is a very sizeable number of logic circuits known to the art. It is to be appreciated with reference to the subject invention, that the following art is not submitted to be the only prior art, the best prior art, or the most pertinent prior art. Background Art U.S. Patents 3,183,370 entitled "Transistor Logic In Circuits Operable Through Feedback Circuitry In Nonsaturating Manner" granted May 11, 1965 to K.M. Trampel. 3,518,449 entitled "Integrated Logic Network" granted June 30, 1970 to D.H. Chung. 3,699,355 entitled "Gate Circuit" granted October 17, 1972 to C.F. Madrazo et al. 4,237,388 entitled "Inverter Circuit" granted December 2, 1980 to J. Nokubo et al. 4,321,490 entitled "Transistor Logic Output For Reduced Power Consumption And Increased Speed During Low To High Transition" granted March 23, 1982 to R.W. Bechdolt. Summary of the Invention The primary object of the invention, as claimed, is to provide an improved logic circuit. A further object of the invention is to provide a logic circuit having a high speed/power ratio. A still further object is to provide a logic circuit having enhanced ability to drive a highly capacitive load. A still further object of the invention is to provide a logic circuit for driving a highly capacitive load where said logic circuit has an emitter follower like up level drive and transient low impedance down level drive. A logic circuit capable of driving high on-chip capacitance at enhanced speed/power ratio is disclosed. This desirable circuit feature is accomplished by optimizing the logic signal swing (approx. 600mV) and providing active drive for both charging and discharging the load capacitance. By utilization of an output feedback path containing a saturated transistor, circuit rising and falling delays are improved and power dissipation is reduced. These and other features and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings. Brief Description of the Drawings FIG. 1, in accordance with the invention, discloses the saturated feedback logic circuit and the input and output steady state signal characteristics. FIG. 2 discloses the rising input and falling output waveforms and the equivalent circuit of FIG. 1. FIG. 2 also shows the load current path for discharging the load capacitance (CL). FIG. 3 discloses the falling input waveform and input current (IP) discharge, enhanced by input undershoot of duration τ, and the corresponding output waveform. FIG. 4 discloses the equivalent circuit of FIG. 1 and DC current flow for V-in = 1.25V. FIG. 4 also shows the corresponding output waveform illustrating the threshold (0.85V) of the next logic circuit when the input voltage changes from a logical 1 to 0. FIG. 5 discloses a multi-input version of the saturated feedback logic circuit in accordance with the invention. FIG. 5 also discloses exemplary values of the resistors in the circuit. Description of the Preferred Embodiment The internal logic NOR gate illustrated in FIG. 1 is designed as an inverting push-pull type circuit with speed depending on the load capacitance. Each T designates a transistor, D a diode, R a resistor, and a double arrowhead symbol refers to a Schottky diode. Power dissipation is preserved due to the changing emitter impedance of the input device, T1 or T4, as the output voltage changes. The inclusion of T3, and the R1 and R2 voltage divider reduces the emitter load of transistor T1 during the time that the output is at the logical 1 level (high level) and when it transverses to the logical zero level (low level). This results in very low impedance from to ground when the input A rises to the 1 level, causing the output to fall very fast. Once the output is at the 0 level, T3 must turn off; therefore the emitter load of T1 changes to RE (∼ 750 Ohms) and preserves the power dissipation. Due to the low impedance transiently exhibited by the circuit output, excellent capacitive load driving capability is realized. Circuit Operation Discussion of circuit operation is limited to input A and assumes input B at ∼ 0.65V. Assume input A (FIG. 1) is at a logical 0 (∼ 0.65V); T1 cannot conduct, thus causing D1, RF and T2 to conduct, therefore output is at the logical 1 level (+1.25V). With up, resistor divider R1 and R2 is chosen to cause T3 to conduct; its low output impedance (T3 is operated in saturation) in parallel with RE results in a total emitter load to T1 of: RE′ = RE//0.03K = ∼ 30 0hms. As input A rises through a threshold of ∼ 0.85V, T1 begins to conduct a current in the range of 1 to 2 mA depending on the load capacitance. As the current direction through RF reverses, T2 is cut off. The input and output waveforms and circuit current paths are illustrated in FIG. 2. Inspecting FIG. 2 we see the output voltage has a transient excursion of ∼ -1.0 Volt. This ΔV is determined by the indicated path consisting of the voltage drop across RF, the VCE of T1 and the VCE of T3 (saturated). This is a desirable condition which enhances the speed of the next internal gate as illustrated in FIG. 3. The transient undershoot of 0.45V below the 0.65V level for τ ns causes the charge to be pulled out of the base of T1 (next internal gate) resulting in its rapid turn off. The time period τ is easily controlled by selecting the level of saturation for T3 via R1/R2 design and/or the T3 base-collector area and/or doping concentration. As previously stated, by this design technique, very fast output down going delays are achieved as a result of saturated feedback (T3). It should also be noted that due to the saturated feedback the circuit input threshold voltage is effected. For a logical zero input level (0.65V), T3 is saturated and the input voltage only has to rise ∼ 200mV (to 0.85V) to switch T1. This factor also improves the rising input to falling output circuit delay. Consider input A is now up at ∼ +1.25V and output is down at ∼ +0.65V; T1 is conducting such that RE is chosen to conduct a current level to support the conduction of both D1 and T2, as illustrated in FIG. 4. Since D1 and T2 are designed to conduct in the steady state (output down), the junction capacitances of D1 and T2 are essentially precharged. When input A falls resulting in T1 turning off (very fast), D1 and T2 can rapidly supply the current required to switch the output to a logical 1 level. As previously stated, due to the saturated feedback technique, output only has to rise to ∼ 0.85V before the threshold of the next stage is achieved which enhances circuit performance. Inspecting the circuit in FIG. 1, chip active area may be preserved by the integration of D1 and T1 within the same collector bed. Resistors R1 and R2 may be ion implant type, RC and RE can be P-type and the feedback resistor RF (100 Ohms) could be an extension of the collector bed of D1 and T1. Further, the Schottky diodes shown are not essential for the operation of the circuit as described, and they may be eliminated, if desired. While the invention has been particularly described with reference to the preferred embodiment, it will be understood by those skilled in the art that the foregoing and other changes and details may be made therein without departing from the scope of the invention as defined in the claims.

Claims: 1. A logical binary circuit having a high speed/power ratio and particularly adapted for driving a highly capacitive load (CL), said logical binary circuit characterized by comprising: first active circuit means (T2) for charging said highly capacitive load from a first potential level to a second potential level, where the absolute magnitude of said second potential level is approximately twice the voltage magnitude of said first potential level; and second active circuit means (T1+T3) for discharging said highly capacitive load from said second potential level to said first potential level, through a transiently low impedance path. 2. A logical binary circuit as recited in claim 1, wherein said first active circuit means includes a charging circuit path (T2, R1, R2) for charging said highly capacitive load, and said second active means includes a discharging circuit path (RF, T1, T3) for discharging said highly capacitive load, and said logical binary circuit being further characterized in that a portion (R2) of said charging circuit is employed in preconditioning said discharging circuit (T3). 3. A logical binary circuit as recited in claim 1 or 2, further characterized in that the load capacitance is discharged through a path containing an input transistor (T1 or T4, TA, TB or TN). 4. A logical inverter circuit as recited in a previous claim, characterized by comprising: first, second and third transistors (T1-T3), said first, second and third transistors each having an emitter, base and collector, the emitter of the first transistor connected to the collector of the third transistor, the collector of the second transistor connected to a first source of potential (+2.1V), and the emitter of the third transistor connected to a second source of potential (GND); an input terminal for receiving a binary input A, said input terminal connected to the base of the first transistor; a first resistor (R1) connected between the emitter of the second transistor and the base of the third transistor; a second resistor (R2) connected between the base of the third transistor and the second source of potential; a third resistor (RE) connected between the emitter of the first transistor and the second source of potential; a fourth resistor (RF) connected between the collector of the first transistor and the emitter of the second transistor; a fifth resistor (RC) connected between the base of the second transistor and the first source of potential; a diode (D1) connected between the base of the second transistor and the collector of the first transistor; and an output terminal for providing the binary output , said output terminal connected to the emitter of the second transistor. 5. An inverter circuit, as recited in claim 4, wherein the potential difference between the said first source of potential and the said second source of potential is in the order of 2.1 Volts. 6. An inverter circuit, as recited in claim 4 or 5, wherein said first resistor has a resistance in the order of 4,000 Ohms, said second resistor has a resistance in the order of 10,000 Ohms, said third resistor (RE) has a resistance in the order of 750 Ohms, said fourth resistor (RF) has a resistance in the order of 100 Ohms, and said fifth resistor (RC) has a resistance in the order of 1330 Ohms. 7. A logical binary circuit, providing the logical binary output () in response to binary inputs A, B through N, where the number of inputs is a positive integer greater than one and less than seven, said logical binary circuit comprising: first, second through Nth parallel transistors (TA, TB through TN), each of which having an emitter, base and collector; first, second through Nth input terminals, each of which respectively receiving a binary input A, B through N, and each of said first, second through Nth input terminals respectively connected to the base of said first, second through Nth parallel transistors; first connection means connecting in common the collectors of said first, second through Nth parallel transistors; second connection means connecting in common the emitters of said first, second through Nth parallel transistors; said first connection means replacing the collector and said second connection means replacing the emitter of one specific transistor in the circuit of claim 4 or 5, said one specific transistor being designated the first transistor (T1) therein and being replaced herein by the N parallel transistors. 8. A logical binary circuit, as recited in claim 4 or 7, wherein the magnitude of the resistance value of the first (R1), second (R2), third (RE), fourth (RF) and fifth (RC) resistors have the following relationship one to another: RF<RE<RC<R1<R2. 9. A logical binary circuit as recited in a previous claim, wherein the potential difference between said first and second sources of potential is approximately 2.1 Volts and the binary logical voltage levels are approximately 0.65 Volts and 1.25 Volts relative to the second source of potential.

Inventors: GAUDENZI, GENE J., REEDY, DENNIS C.
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H03K19, H03K17