Gate turn-off thyristor with independent turn-on/off controlling transistors

Abstract: A gate turn-off thyristor (10) has first and second MOSFETs (Q1, Q2) serving as turn-on and turn-off con­ trolling devices, respectively. A p type semiconductor layer (26a, 26b) is additionally formed in an n type substrate (16) functioning as a first base in such a manner as to overlap a p type second base layer (18). The additional layer (26a, 26b) is different from the second base (18) in impurity concentration, thereby causing the resistivity of the second base (18) to be smaller than that of the additional layer (26a, 26b). The first MOSFET (Q1) has an n type source layer (28) formed in the additional layer (26a) to define a surface portion of the additional layer (26a) positioned between the source layer (28) and the first base layer (16) as a channel region (CH1) of the first MOSFET (Q1). A turn-­ on gate layer (34) is provided to cover a surface region of the first base (16) and the channel region (CH1) of the first MOSFET (Q1).

Description: The present invention relates to a gate turn-off thyristor and, more particularly, to a gate turn-off thyristor having independent transistor elements for controlling the turn-on and turn-off of the thyristor. Heretofore, it is known to provide, in addition to a turn-on controlling transistor element, a transistor element for exclusively controlling the turn-off of high power gate turn-off thyristors (GTO thyristors). For example, according to V.A.K. Temple, "MOS CONTROLLED THYRISTORS (MCT'S)" IEEE IEDM Tech. Digest, pages 282-285 (1984), a GTO thyristor having an n-channel turn-on controlling FET and a p-channel turn-off controlling FET is disclosed in Fig. 4 of this reference. In this thyristor, the p-channel FET is switched to a conductive state in response to a drive voltage application to a gate electrode, and the n type emitter layer and the p type base layer of the GTO thyristor are electrically short-circuited therebetween, thereby controlling the turn-off of the thyristor. According to the GTO thyristor, it is, however, difficult to effectively control the turn-off operation. This is because the turn-off current hardly flows due to a lateral resistance inherent in a p type base layer in the region of the p type base layer (e.g., the central portion of the GTO thyristor) relatively remote from a channel region (off-channel) where the turn-off current initially starts flowing, resulting that the turn-off is delayed in this region. More specifically, according to this example, the surface portion of the p type base layer, which becomes conducted when the GTO thyristor is turned off with the p type region (formed in the n type emitter layer) of high impurity concentration via the off-channel, functions also as a turn-on channel. In other words, the surface portion of the p type base layer of low impurity concentration is used directly as the on-channel of the turn-on controlling FET. Therefore, it is not allowed to alter the resistivity of the turn-on channel to a low value. Because, if the impurity concentration of the surface portion of the p type base layer is high enough to reduce the resistivity of the p type base layer, the threshold voltage level of the turn-on channel increases, thereby making it impossible to drive the turn-on of the thyristor effectively. Further, according to the conventional GTO thyristor with the turn-on and turn-off controlling FETs, its withstand voltage cannot be enhanced as required. In the thyristor, it is necessary to set the resistivity of the n type base layer to a relatively high value (i.e., low impurity concentration) in order to enhance the withstand voltage of the thyristor. However, if this is so, the resistivity for the turn-off current will inevitably increase, thereby reducing the current capacity at the turn-on time. It is known from Patent Abstract of Japan, Vol. 9, No. 181 (E-331) (1904), 1985 & JP-A-6053078 to provide a gate turn-off thyristor comprising an n-base layer a p-emitter layer (anode layer), a plurality of p-base regions and n-emitter layers (cathode layer). The p-emitter layer and the p-base regions are formed on opposite surfaces of the n-base layer. In each p-base region is an n-emitter layer formed. The GTO also features MOS transistors formed on the cathode side of the device for turning on and turning off the thyristor. Each turn-on MOSFET forms a current channel between an n-base layer and an n-emitter layer via a p-base region when the gate electrode is brought to a positive voltage. When the turn-off gate electrode is brought to a negative voltage, a short-circuit is established between the p-base and the n-emitter. We also acknowledge that EP-A-0017980 discloses a GTO thyristor with a MOSFET for gate turn-on. The turn-on channel is formed in a lightly doped region adjacent a p-base region. On the other hand, a power device with MOS-controlled emitter shorts is disclosed by M. Stoisiek et al., Siemens Forschungs- und Entwicklungsberichte, vol. 14, no. 2 pages 45-49 (1985). A low doping concentration is used for the channel region of a turn-off MOSFET. It is an object of the present invention to provide a new and improved gate turn-off thyristor which can be effectively driven to turn-on and turn-off at a high speed and has excellent basic characteristics such as gate sensitivity and current capacity. In order to attain the above object, the invention provides a GTO as defined in Claim 1 of this specification. The invention, and its objects and advantages, will become more apparent in the detailed description of preferred embodiments presented below. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows in plan main parts of a gate turn-off (GTO) thyristor having turn-on/off controlling MOSFETs of the same channel type in accordance with a first embodiment of the invention; Fig. 2 is a sectional view of the GTO thyristor as taken along line II-II of Fig. 1 (not drawn to scale); Fig. 3 is a sectional view of a semiconductor device including a main GTO thyristor and the GTO thyristor shown in Fig. 1 used as an auxiliary thyristor for driving the main GTO thyristor (not shown to scale); Fig. 4 shows in plan a GTO thyristor with turn-on/off controlling MOSFETs of different channel types in accordance with a second embodiment of the invention; and Fig. 5 is a sectional view of the GTO thyristor as taken along line V-V of Fig. 4 (not drawn to scale). Referring now to Figs. 1 and 2, there is shown a gate turn-off thyristor or GTO thyristor 10 of a first embodiment of the present invention. Fig. 2 shows in plan the sectional construction of a GTO thyristor as taken along U-shaped line II-II of Fig. 1. In Fig. 2, insulation layers are omitted from the illustration so as to make it easy to understand visually the essential portion of a complicated plan construction of the device. As shown in Fig. 2, GTO thyristor 10 has a conventional "pnpn laminated layer structure" formed of p type emitter 12, n type bases 14 and 16, p type base 18 (or 18') and n type emitter 20. The p type base of thyristor 10 is divided, as shown in Fig. 1, into two p type layers 18 and 18' (the surface region of a linear n type base is exposed therebetween). N type emitter 20 is divided, as shown in Fig. 1, into a plurality of layer components having a rectangular slender planar shape. Conductive layer 22 is formed on emitter 12, and serves as anode electrode A (first main electrode). Conductive layer 24 has a layer component formed on emitter 20, and is conducted directly with emitter 20 to thereby serve as cathode electrode C (second main electrode). Thyristor 10 has MOSFETs Q1 and Q2 for independently controlling the turn-on/off of the thyristor. Turn-on controlling MOSFETs Q1 and Q1' are respectively formed in p type semiconductive layers 26a and 26b additionally formed in the peripheral region of p type base 18 of thyristor 10. The layers 26 are shallower than p type base 18, and their resistivity is set to be larger than that of layer 18 of the body of thyristor 10. Layers 26 are formed, after the diffusing step of the impurity in the layer 16 for forming base 18, by diffusing the same conductivity type of impurity in layer 16 at different impurity concentration (smaller impurity concentration). Therefore, layers 26 can function substantially as part of the p type base of thyristor 10. N type semiconductive layers 28 and 30 of high concentration are formed in space in layer 26a. Layer 28 in linearly extended along the peripheral edge of the p type base (and hence parallel with the short sides of emitter 20 of rectangular slender shape). Layer 30 is extended vertically to layer 28 to become parallel to the long sides of emitter 20. Conductive layer 32 is formed on p type base 26a so as to electrically connect layers 28 and 30 and to short-circuit additional p type base layer 26. Layer 32 thus functions as the source electrode (or amplifying gate electrode) of MOSFET Q1. Conductive layer 34 is formed above base 16 so as to cover the surface region of n type base 16 between p type bases 18 and 18'. Layer 34 is insulated from layers 16, 18, 26 and 28 by gate insulation layer 36. Thus, conductivity modulation type n channel MOSFET Q1 is constituted which has n⁺ type layer 28 as a source, conductive layer 34 as a turn-on controlling gate (hereinafter abbreviated to "ON-gate") and an upper surface region of layer 26a disposed directly under layer 36 as channel region CH1. N⁺ type semiconductive layers 28' and 40 are formed in layer 26b in a similar manner, and short-circuited with layer 26b (see Fig. 2) by electrode layer 32'. ON-gate layer 34' and gate insulation layer 26' are formed similarly to FET Q1 to obtain conductivity modulation type n channel MOSFET Q1' (in Fig. 2, layer 28' is the same as layer 28, but shown by a "dash" for the convenience of illustration. Similar comments are to be made with respect to layers 32', 34' and 36'.) . ON-gates 34 and 34' of FETs Q1 and Q1' are connected to gate turn-on controlling gate terminal G1. An external drive voltage for controlling the turn-on of thyristor 10 is applied to terminal G1. Turn-off controlling gate layer 50 (hereinafter abbreviated to "OFF-gate") is formed above layer 18 to extend along the long sides of a rectangular n type emitter and to substantially self-align with layers 20 and 30. OFF-gate layer 50 covers, as best depicted in Fig. 2, the surface regions of layers 26a and 18 disposed between n⁺ type emitter 20 and n⁺ type layer 30. OFF-gate layer 50 is insulated from layers 18, 20, 26, 30 by gate insulation layer 52. Therefore, n channel MOSFET Q2 is composed which has n⁺ type layer 30 as a drain, and the upper surface region of p type layers 18 and 26a, which is positioned between layers 20 and 30 and disposed directly under layer 52, as channel region CH2. MOSFET Q2 functions as a turn-off controlling transistor. (It is not always necessary that the right end of layer 26 shown in Fig. 2 extends to be positioned under layer 50. It is sufficient that layer 26 at least partially overlaps layer 30.) In a similar manner gate insulation layer 54 and OFF-gate layer 56 are stacked on p type base layer 18. Thus, n channel MOSFET Q2' is formed which has n⁺ type layer 40 as a drain, and the upper surface regions of layers 18 and 26b positioned between layers 20 and 40 and disposed directly under gate insulation layer 54 as channel region CH2'. ON-gates 50 and 56 of FETs Q2 and Q2' are connected to gate turn-on controlling terminal G2, to which an external drive voltage for controlling the turn-off of thyristor 10 is applied. As described above, since electrode layer 32 is connected with n⁺ type layers 28 and 30, source (28) of ON-gate MOSFET Q1 is electrically conducted with p type layers 18 and 26a. Similarly, source 28' of MOSFET Q1' and layers 18 and 26b are electrically conducted with one another by electrode layer 32'. Therefore, layer 32 and 32' functions as an amplifying gate electrode. The GTO thyristor of the construction described above was experimentally produced by the present inventors by a fabrication process which will be described below. An n type silicon wafer for forming layer 16 was first prepared. The resistivity of this wafer was 120 to 150 ohm-cm, and its thickness was set to 350 micrometers. Wafer 16 was subjected to the diffusion process of n type and p type impurities to thereby form n type base 14 of high concentration having 30 micrometers thick and p type emitter 12 of high concentration having 30 micrometers thick in one surface portion of wafer 16. Subsequently, a p type impurity was diffused in the opposite surface portion of wafer 16 to form p type base layer 18. Then, a thermal oxidizing step was achieved to form gate insulation layers 36, 52 and 54 of 100 nanometer thick on the wafer. Polycrystalline silicon layers were deposited on layers 36, 52 and 54 to the abovementioned layers 34, 50 and 56. Then, with layers 34, 50, 56 as parts of masks, n type emitter 20, p type sub-bases 26a and 26b, and n+ type semiconductive layers 28, 30, 40 were sequentially formed on the surface portions of wafer 16. After an insulation layer was formed to cover the layers 34, 50 and 56, metallic layers 22 and 24 functioning as the anode and cathode electrodes, and metallic layer 32 serving as an amplifying gate electrode were formed to complete the GTO thyristor with independent turn-on/off controlling MOSFETs. An operation mode relative to the turn-on/off control of the GTO thyristor of one embodiment of the present invention will be described. When thyristor 10 is to be turned on, a positive voltage is applied to common ON-gate terminal G1 of MOSFETs Q1 and Q1'. Thus, MOSFETs Q1 and Q1' are rendered conductive, and electrons are thus implanted from sources 28 and 28' of MOSFETs Q1 and Q1' through regions CH1 and CH1' to n type base layer 16. As a result, the source current of MOSFET Q1 is supplied through electrode layer 32 top type base 18 and sub-base 26a. Simultaneously, the source current of MOSFET Q1' is supplied through layer 32' to p type base 18 and sub-base 26b. Therefore, GTO thyristor 10 can be turned on. Alternatively, when GTO thyristor 10 is to be turned off, the potential of common terminal G1 of MOSFETs Q1 and Q1' is forcibly set to zero, and a positive voltage is applied to common terminal G2 of MOSFETs Q2 and Q2'. Thus, FETs Q1 and Q1' are rendered nonconductive, and MOSFETs Q2 and Q2' are rendered conductive. Therefore, n type emitter 20 of GTO thyristor 10 is conducted via regions CH2 and CH2' of MOSFETs Q2 and Q2' with drains 30 and 40 of MOSFETs Q2 and Q2'. Since drains 30 and 40 are always conducted with base 18 and sub-base 26 by electrode layer 32, n type emitter 20 is short-circuited with p type base 18 and sub-base 26. As a result, thyristor 10 can be turned off. According to the embodiment device of the invention, p type base layer 18 of GTO thyristor 10 and p type sub-base layer 26 including the source of turn-on controlling MOSFET Q1 and the drain of turn-off controlling MOSFET Q2 are formed in independent fabricating steps to have different impurity concentrations. Therefore, the resistivity of p type base 18 of GTO thyristor 10 can be reduced without decreasing the resistivity of p type layer 26 corresponding to channel CH1 of MOSFET Q1. In other words, the resistivity of the p type channel region of MOSFET Q1 can be maintained high in desired degree, and yet the resistivity of p type base layer 18 can be sufficiently reduced without affecting adverse influence thereto. Channel CH2 of turn-off controlling FET Q2 is composed by the surface portion of base 18 of relatively high impurity concentration (low resistivity) . Therefore, the turn-on performance of thyristor 10 can be maintained satisfactory and the erasing propagation of turn-off current of thyristor 10 can be accelerated without deteriorating the dv/dt rating and the basic characteristics of current capacity of thyristor 10. Consequently, the turn-off speed can be improved without deteriorating the turn-on performance of thyristor 10 to thereby improve the turn-off capability. Since OFF-gate channel regions CH2 and CH2' are provided at both long sides of n type emitter 20 having a rectangular plan shape, the turn-off of GTO thyristor 10 simultaneously starts at both long sides of n type emitter 20. This means that the effective channel width for the turn-off current is long and hence a short-circuiting resistivity for turning off the thyristor 10 is extremely small. Therefore, time required for the entire turn-off current to completely disappear can be shortened to further improve the turn-off performance of GTO thyristor 10. In the embodiment described above, the source current of MOSFET Q1 (or Q1') functions as the base current of GTO thyristor 10 which is turned on. Thus, the gate sensitivity of thyristor 10 can be improved in accordance with the same principle of the case of an amplifying gate thyristor. Main thyristor 60 shown in Fig. 3 is turn-on driven in response to the turn-on operation of auxiliary thyristor 10. More specifically, when auxiliary thyristor 10 is turned on in the above-described manner, the cathode current of thyristor 10 is supplied as a base current through short-circuiting electrode layers 74a and 74b of main thyristor 60 to p type base layer 62 thereof. Main thyristor 60 is then turned on by the supply of the base current. On the other hand, when main thyristor 60 is turn-off driven, a positive voltage is simultaneously applied to OFF-gate terminal G2 of auxiliary thyristor 10 and OFF-gate electrodes 72a and 72b of main thyristor 60. Thus, auxiliary thyristor 10 is turned off in the above-described manner. At this time, in main thyristor 60, an n channel is formed under gate electrode 72 to short-circuit n type emitter 64 of thyristor 60 with p type base 62, thereby turning off thyristor 60. Therefore, according to the device in Fig. 3, since the base current of main thyristor 60 is amplified in two stages at the turn-on time of thyristor 60, the turn-on gate sensitivity of the GTO thyristor can be further improved as compared with the construction in Fig. 1. GTO thyristor 80 of a second embodiment of the present invention is shown in Figs. 4 and 5. MOSFETs Q3 and Q4 of different channel types (i.e., n channel type and p channel type) are combined to form one MOS gate for controlling the turn-on/off of thyristor 80. In a sectional view of Fig. 5, the same reference numerals as in the first embodiment in Fig. 2 denote the same parts in the second embodiment, and the detailed description thereof will be omitted. P type base layers 82 and 82' (only layer 82 is seen in Fig. 5) split in a similar manner to p type bases 18 and 18' of Fig. 1 and an type emitter layer 84 of high concentration having a rectangular slender plan shape are formed in n type base layer 16. P type layers 86a and 86b are formed to have different (smaller) impurity concentration in the diffusing step separately from the diffusing step for forming layer 82 at the short side of layer 82. Layers 86a and 86b function as a part of p type base. N type source layer 88 is formed in p type sub-base layers 86a and 86b (layer 88 in layer 86b is shown with a "dash" in Fig. 5). Gate electrode layer (i.e., an ON-gate) 90 is formed to extend straightly as shown in Fig. 4 and to cover the surface portion (channel region CH3) of p type subbase layer 86a interposed between n type source 88 and n type base 16. ON-gate 90 is insulated from substrate 16 by gate insulation layer 92. Straight planar-shaped conductive layer 94 is formed insulatively above ON-gate 90. Layer 94 is also formed on wafer 16 to electrically connect p type base 86a and n type source 88 to thereby form n channel type conductivity modulation MOSFET Q3 for controlling the turn-on of thyristor 80. Other turn-on controlling n channel type conductivity modulation MOSFET Q3' has a construction similar to that of MOSFET Q3. MOSFETs Q3 and Q3' form an amplifying gate portion at turn-on time of thyristor 80 similar to the previous embodiment. P type semiconductive layers 100a and 110b serving as source regions are formed in both side regions of the long side of n type emitter 84 of GTO thyristor 80. N type semiconductive layer 102 of high concentration is formed to be in contact with source layers 100a and 100b in the central region of n type emitter 84. Conductive layer 104 is formed to directly contact layers 100a and 100b with layer 102 to function as cathode electrode C of thyristor 80. In Fig. 4, cathode C is formed to cover OFF-gates 110 and 112, though most is omitted for the purpose of simplification of illustration. Gate insulation layer 106 is formed to cover the surface portion (channel region CH4) of n type emitter 84 interposed between one p type source 100a and p type base 82. Gate insulation layer 108 is formed to cover the surface portion (channel region CH4') of n type emitter 84 interposed between other p type source 100b and p type base 82. Conductive layers 110 and 112 are formed on insulation layers 106 and 108 to thereby form p channel type conductivity modulation MOSFETs Q4 and Q4' for controlling the turn-off of thyristor 80. As apparent from Fig. 4, conductive layers 110 and 112 are extended along long sides of n type emitter 84, and coupled with each other at a position not shown in Fig. 5 to function as the OFF-gates of thyristor 80. MOSFETs Q3 and Q3' form amplifying gate portions at turn-off time of thyristor 80 similarly to the previous embodiment. Gates (i.e., OFF-gates) 110 and 112 of MOSFETs Q3 and Q3' are connected in common to ON-gates 90 and 90' of MOSFETs Q3 and Q3', and connected to only one turn-on/off control terminal G. Since p type source layers 100a and 100b of MOSFETs Q4 and Q4' are connected by the cathode electrode 104 of thyristor 80 to n type layer 102 which functions as part of n type emitter 84, p type source layers 100a and 100b are always maintained at the same potential as emitter 84 of thyristor 80. According to the second embodiment of the invention, when GTO thyristor 80 is turned on, a positive voltage is applied to gate terminal G. At this time, ON-gates 90 and 90' are excited, and n channel MOSFETs Q3 and Q3' are rendered conductive. As a result, the source current of MOSFETs Q3 and Q3' is supplied as a base current to p type base 82 of thyristor 80 to thereby turn on thyristor 80. The turn-on operation of thyristor 80 is similar to that in the first embodiment shown in Fig. 1. On the other hand, when thyristor 80 is turned off, gate terminal G is applied with a negative voltage. Thus, OFF-gates 110 and 112 are excited, and p channel MOSFETs Q4 and Q4' are rendered conductive. As a result, n type emitter 84 of thyristor 80 is short-circuited with base 82 to turn off thyristor 80. According to this embodiment device, and FET having a channel type different from that of FET Q3 (or Q3') for controlling turn-on is used as turn-off controlling FET Q4 (or Q4'), thyristor 80 can be controlled to turn on or turn off by the application of a voltage to only one terminal. Therefore, the construction of the voltage application for controlling the turn-on/off of thyristor 80 can be simplified. In a single control gate terminal construction, p channel regions CH4 and CH4', where the turn-off current of thyristor 80 starts flowing, are, unlike the abovementioned conventional device, to be in noncontact with n channel regions CH3 and CH3' of MOSFETs Q3 and Q3' of the ON-gate. Therefore, it can prevent the turn-off current from flowing simultaneously through n channel regions CH3 and CH3' of FETs Q3 and Q3' of the ON-gate. Further, since p type sub-base layer 86 which includes source 88 of turn-on controlling FET Q3 (or Q3') is formed by fabricating step separate from fabricating step of p type base layer 82 of the main body of thyristor 10, the resistivity of p type base 82 of thyristor 80 can be reduced to the desired degree without decreasing the resistivity of p type regions 86 for FETs Q3 and Q3'. The resistivity further decreases in the overlapped portion of base 82 and layers 86a and 86b. This contributes to the improvement in the turn-off capability by accelerating the erasing propagation of the turn-off current of thyristor 80 in layer 82. In the embodiment device, the source current of conductivity modulation type MOSFET Q3 (or Q3') functions as the base current of GTO thyristor 80 at turn-on time, so that the gate sensitivity of thyristor 80 can be improved similarly to the previous embodiment.

Claims: A gate turn-off thyristor (10, 80) having a semiconductive substrate (16) of a first conductivity type serving as a first base layer having a surface region, a first emitter layer (12) and a second base layer (18, 82) both of a second conductivity type formed on opposing surfaces of said substrate (16), and a second emitter layer (20, 84) of the first conductivity type is formed in said second base layer, an additional semiconductor layer (26, 86) of the second conductivity type which has a surface region in contact with said first base layer (16), and extends into said second base layer (18, 82) and which is different from said second base layer in impurity concentration, whereby said second base layer (18, 82, 126) has a smaller resistivity than said additional layer; a first field effect transistor (Q1,Q3) for turning on said thyristor and having a source layer (28, 88) formed in said additional layer to define a surface portion of said additional layer positioned between said source layer and said first base layer as a channel region (CH1, CH3) of said first transistor, and a first gate layer (34, 90) insulatively provided above said substrate to at least partially cover the surface region of said first base layer and the channel region of said first transistor; a second field effect transistor (Q2, Q4) for short-circuiting said second base layer and said second emitter layer with each other to thereby turn off said thyristor (10, 80), said second transistor having a channel region (CH2) of which the main part is a surface portion of said second base layer, a source layer (20, 100), and a second insulated gate (50, 56; 110, 112) overlying said channel region of said second transistor; said second emitter layer (20, 84) at least partially having a substantially rectangular slender planar shape defined by long and short sides, said channel region of said first transistor (Q1, Q3) extending substantially parallel to the short sides, and said channel region of said second transistor (Q2, Q4) extending parallel to the long sides of said second emitter layer; and said thyristor further comprises a conductive layer (32, 94) formed on said second base layer and serving as a source electrode, said conductive layer causing the source layer of said first transistor (Q1, Q3) and the drain layer of said second transistor (Q2, Q4) to be electrically connected together with said second base layer while being electrically separated from said second emitter layer (20, 84). A thyristor according to Claim 1, characterized by further comprising: a second impurity-doped semiconductor layer (102) of the first conductivity type formed in said second emitter layer (84) and serving as a part of said second emitter layer (84). A thyristor (10 in Figure 2) according to Claim 1 characterized in that said first and second transistors are same in channel conductivity type as each other, and that said second transistor (Q2) has a source (20), a drain (30) defining a surface portion (CH2) of said second base layer (18) positioned between said drain and said second emitter layer (20) as the channel region of said second transistor, and a semiconductor layer (30) of the first conductivity type in an overlapping region of said second base layer (18) and said additional layer (26) between said second emitter layer (20) and said source (28) of said first transistor (Q1), said semiconductor layer (30) serving as said drain of said second transistor (Q2). A thyristor (80 in Figure 5) according to Claim 1 characterized in that said first and second transistors are different in channel conductivity type from each other, that said second transistor (Q2) has a source (100a) and a drain (82) defining a surface portion (CH4) of said second emitter layer (84) positioned therebetween, and that said thyristor further comprises: a first impurity-doped semiconductor layer (100a, 100b) of the second conductivity type in said second emitter layer (84) to serve as said source (100) of said second transistor (Q4); and a second conductive layer (104) on said second emitter layer (84), for connecting said source (100) with said second emitter layer (84) to serve as a cathode electrode of said thyristor. A thyristor (80) according to Claim 4, characterized in that said first and second gates (90; 110, 112) are electrically connected together to simultaneously receive a voltage for controlling the turn-on and turn-off of said thyristor.

Inventors: NAKAGAWA AKIO PATENT DIVISION, SHINOHE TAKASHI PATENT DIVISIO, NAKAGAWA, AKIO PATENT DIVISION K.K. TOSHIBA, SHINOHE, TAKASHI PATENT DIVISION K.K. TOSHIBA
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L29
IPC codes: H01L29