METHOD OF MANUFACTURING INTEGRATED CIRCUITS

Abstract: A method of manufacturing integrated circuits in which a number of conductive test structures (7) for monitoring electromigration are formed at different points on the wafer on which the integrated circuits (1) are being manufactured. Electrical connections (5) are formed between the test structures (7) on the wafer, and the resistance of the current path constituted by the structures (7) and connections (5) is monitored to determine whether any of the test structures (7) have failed.

Description: Method of manufacturing integrated circuits This invention relates to methods of manufactur¬ ing integrated circuits. Electromigration of conductive tracks has been identified as a major reliability hazard in integrated circuits particularly in VLSIs. As the resistance to electromigration of the circuit depends on a number of factors such as conductive track composition, morphology etc. it is not always possible to control this during the manufacture of an integrated circuit, and it is therefore necessary to assess electromigration resistance routinely on a batch-to-batch basis during the manufacture of the circuit. To do this it is known to incorporate a number of conductive test structures on the wafer on which a number of integrated circuits are formed during the manufacture of the circuits. As each structure must be individually bonded up in order to be tested to determine whether electromigration has caused failure of the structure, however, this proceedure is necessarily slow and thus expensive. It is an object of the present invention to provide a method of manufacturing integrated circuits wherein this problem is alleviated. According to the present invention a method of manufacturing integrated circuits includes the steps of: forming a plurality of conductive test structures for monitoring electromigration each at a different point on the wafer on which the integrated circuits are formed; forming electrical connections between the structures on the wafer; and monitoring an electrical parameter of the current path constituted by the structures and the connections and using the value of the electrical para- meter to determine whether any of the test structures have failed. Thus in a method in accordance with the invention individual testing of each test structure is not required, and thus bonding to each structure is not necessary. Preferably the electrical connections are such that a current path is maintained in the event of one of the test structures becoming open circuit. It is thus possible to continue to monitor for the failure of any further test structures. The electrical parameter is suitably resistance. The connections preferably include resistances. Preferably the conductive test structures and connections are formed within wafer scribe channels. One method of manufacturing an integrated circuit in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 is a schematic diagram of part of a wafer includixig, the integrated circuit at a stage during the manufacture of the circuit; and Figure 2 is an equivalent circuit of an electro¬ migration test structure incorporated on the wafer of Figure 1. Referring to Figure 1, the method includes forming a number of conventional integrated circuits, indicated as 1, upon a wafer, the circuits being separated from each other by scribe channels 3 formed within the wafer in the usual manner. In respect of each row of circuits 1 across the wafer, there is provided in an adjacent scribe channel a conductive track 5 running across the wafer this being deposited on the wafer at the same time as the conductive tracks within the circuits 1. Electromigration test stripes 7 are defined at intervals along the length of the track 5, usually one such stripe being provided in respect of each integrated circuit 1. Each stripe 7 is arranged to pass over a number of steps 9 formed on the wafer so as to simulate the conditions under which a con¬ ductive track is prone to become open circuit. A respective polysilicon resistor 11 is deposited next to each stripe 7, the conductive track 5 being arranged to connect each resistor 11 in parallel with its adjacent stripe 7. Thus the equivalent circuit for the structure within each scribe channel 3 is as shown in Figure 2 where R M1 to R MN represent the stripes 7 associated with each inte¬ grated circuit 1, in a row across the wafer, and R p , to R represent the resistors 11 provided in respect of each stripe 7- The value of resistance of each of the resistors R p _ to R pM is designed to be much greater than the resistance of each stripe R. M,l_ to R.M,.N τ . At suitable times during the manufacturing of the wafer, electrical connections are made at each end of each track 5 such that current of a suitable value to electrically stress the stripes 7 may flow through the track 5, and the resistance across the track 5 is monitored. In the event that one of the stripes 7 has failed by becoming open circuit, an increased value of resistance will be monitored. As the parallel arrangement of resistors 11 and stripes 7 enables current to flow through the remaining stripes 7, any further failures may also be monitored, the total number of failures being indicated by the increase in resistance monitored across the track. It will be appreciated that each test stripe 7 will normally run over a variety of topological features on the wafer so as to give a worst case situation. It will also be appreciated that many other test structures may be designed, for example for monitoring closed circuits due to electromigration. It will also be appreciated that whilst it is particularly convenient to form the test structures and connections within the scribe channels of the wafer, as they do not then take up space on the wafer, they may be formed on other portions of the wafer.

Claims: CLAIMS 1. A method of manufacturing integrated circuits in which a plurality of conductive test structures (7) for monitoring electromigration are formed each at a different point on the wafer on which the integrated circuits (1) are formed, the method being characterised in that it includes the steps of: forming electrical connections (5) between the structures (7) on the wafer; and monitoring an electrical parameter of the current path constituted by the structures ( 7) and the connect- ions (5,11) and using the value of the electrical para¬ meter to determine whether any of the test structures (7) have failed. 2. A method according to Claim 1 in which the electrical connections (5,11) are such that a current path is maintained in the event of one of the test structures (7) becoming open circuit. 3. A method according to either of the preceding claims in which the electrical parameter is resistance. 4. A method according to any one of the preceding claims in which the connections include resistance (11). 5. A method according to any one of the preceding claims in which the conductive test structures (7) and connections (5,11) are formed within wafer scribe channels (3) .

Inventors: PITT MICHAEL GEOFFREY, PITT, MICHAEL, GEOFFREY
Applicants: GEN ELECTRIC CO PLC, THE GENERAL ELECTRIC COMPANY, P.L.C.
Application year: 1986
Main classification: H01L21
IPC codes: G01R31, H01L21, H01L23, H01L27