ADDRESS CONTENTION ARBITRATOR FOR MULTI-PORT MEMORIES

Abstract: For detecting and resolving address contention between ports of a multi-port memory address signals (A a0 - A a(n-1) ) arriving at a first port (A) are compared with delayed address signals (A b0D - A b(n-1)D ) from a second port (B). If a match occurs, the second port (B) is given priority. Similarly address signals (A b0 - A b(n-1) ) arriving at the second port (B) are compared with delayed address signals (A a0D - A a(n-1)D ) arriving at the first port (A). If a match occurs in the comparison, the first port (A) is given priority.

Description: ADDRESS CONTENTIONARBITRATORFOR The present invention relates to multi-port electronic memories and more particularly to systems for detecting and arbitrating contention between the ports thereof. A block of electronic memory is typically organized into individual memory locations each of which contain one or more binary digits (bits). Each such location has associated therewith an address. rn order to read information from a particular memory location or to write information into that memory location, that location address is transmitted to the memory on an address bus. The address signal is typically provided as an n bit signal where n is a positive integer. Often a particular application will require that more than one processor, or other type of circuitry, be allowed to access memory locations in the same block of memory. Various approaches have been used in order to allow this. Under one approach circuitry is provided to give each circuit requiring access to the block of memory exclusive access at certain times. While this will work in some circumstances under other circumstances a preferrable arrangement would be to allow all circuits requiring such access to have it simultaneously. Memory circuits which allow a plurality of external circuits access to memory locations within the same block of memory at the same time are called dual or multi-port memories. Such memories will have a plurality of address inputs and a plurality of data input output (I/O) ports. One data I/O port is associated with each address input. If a read operation is to be performed, circuitry associated with the memory will provide the value stored in the memory at the location specified on the address bus to the I/O port associated with that address bus. Similarly, if a write operation is to be performed the value arriving at an I/O port is stored in the memory at the location specified on the associated address bus. Such an arrangement will work under most circumstances. However, if two circuits both having access to the memory attempt to access the same memory location within that memory at the same time, problems may arise. The situation may be particularly acute if one of the circuits attempts to write information into a memory location while the other circuit is either reading from or writing to that same location. In order to prevent problems from arising under those circumstances circuitry must be provided to determine which circuitry attempted to access the memory location first and to provide a busy signal to the other circuit. This busy signal prevents that circuit from accessing the memory until the first circuit has completed its process. This problem is solved by the invention as characterized in claim 1. The present invention provides a system for detecting address contention and resolving such contention in a multi-port memory. In an embodiment having two ports, designated port A and port B, the system works by comparing the address signals arriving at port A with a delayed version of the address signals which arrived at port B. If, when the address signals first arrive at port A, a match is found, address contention exists. Furthermore, since the port B address signals used in the comparison were delayed, clearly the port B address signals had to be there first in order for the match to occur. Therefore, a busy signal is generated for port A until port B completes its access of the memory location. Similar circuitry is provided for comparing current address signals at port B with delayed address signals from port A. This circuit in turn generates busy signals, when required, for port B. The system may be expanded for use with more than two ports by providing additional delay and comparison circuits. Further details and improvements are described in the subclaims. The invention is explained in detail by reference to an embodiment shown in the drawings; wherein Figure 1 shows the arrangement for conditioning address signals for comparison; Figure 2 shows an example of a delay circuit which could be used with the invention; and Figure 3 shows the address comparison and busy signal generator of the invention. The present invention will be described for a two port memory. Those skilled in the art will readily see that it is not limited to such use, however, and could be used in systems having more than two ports. Furthermore, each address will be assumed to have n bits where n is a positive integer. Although only four address lines are shown for each address port, typically n would be greater than four. The address signals arriving at the port A address input will be designated AaO, Aal, Aa(n-l) The delayed version of those signals will be designated AaODt AalDt ..., Aa(n#l)D. Similar designations are used for the address signals arriving at the port B address input. In the system of Figure 1 the signal AaO arrives and is applied to signal line loan. Signal line 10a0 is electrically connected to time delay generator 12a0 and to output region 14a0. Time delay generator 12a0 is electrically connected to output region 16a0. Therefore, the original address signal AaO is available at output region 14a0 and the delayed address signal AaoD is available at output region 16a0. Similarly, delayed versions of the remaining address signals arriving at the port A address inputare also produced and provided at appropriate output regions. Likewise, the remaining original address signals arriving at the port A address input are provided at their appropriate output regions. As also shown in Figure 1 similar current and delayed address signals are provided for those address signals arriving at the port B address input. Figure 2 illustrates an example of an electronic system which could be used as an electronic delay such as delay generator 12a0 of Figure 1. In this embodiment the delay is simply two electronic inverters 18aO and 20a0 The gate delay of the inverters is sufficient to be the delay for the invention. The use of two inverters to provide the delay is preferred in most systems because inverters may be easily provided. The invention is not limited to the use of a pair of inverters, however, and other methods of providing the delay may be used. Turning now to Figure 3 the system for determining whether address contention exists, and resolving it if it does, is shown. In Figure 3 are shown a series of EXCLUSIVE OR gates, 22abc, 22abel, 22,bar 22ab(n-l)r 22boa01 22ball 22bar and 22ba(n-l)¯ In Figure 3 the use of the subscript ab indicates that the undelayed a signal is combined with the delayed b signal in that EXCLUSIVE OR gate, and the use of the subscript ba indicates the opposite. The number in each subscript indicates the order number of the address bit which is combined in that EXCLUSIVE OR gate. Following this convention EXCLUSIVE OR gate 22ab0 combines the current signal Aa0 and the delayed signal Ab0D. If the signals Aa0 and AbOD are both zero or both one the output of EXCLUSIVE OR gate 22ab0 will be zero. If the signals Aa0 and AbOD differ from one another, however, the output of EXCLUSIVE OR gate 22ab0 will be equal to one. Similarly, the other EXCLUSIVE OR gates produce output signals based on the input signals received. The outputs from each of EXCLUSIVE OR gates 22ab0 through 22ab(n-1) serve as input signals to NOR gate 24ab. Similarly, the output signals from EXCLUSIVE OR gates 22ba0 through 22ba(n-1) serve as input signals to NOR gate 24ba. Furthermore, the output signal from NOR gate 24boa serves via line 27 as an input signal for NOR gate 24ab and the output signal from NOR gate 24 serves via line 28 as an input signal to NOR gate 24ba. Each of NOR gates 24ab and 24ba have provided thereto as additional input signals CEb and CEa, respectively. Not all memory systems use the CEa and CEb signals, and they are not required by the invention. Therefore, the invention will first be described without these signals. According to the standard operation of a NOR gate if any input signal to either of NOR gates 24ab or 24ba is one the output of that NOR gate will be zero. If all of the inputs to either of NOR gates 24ab or 24ba are equal to zero the output of that NOR gate will be equal to one. The operation of the system of Figure 3 will now be explained, assuming that initially no address contention exists. When that is the case, at least one of the bits presented at port A must differ from the corresponding bit presented at port B. Therefore, at least one of EXCLUSIVE OR gates 22ab0 through 22ab(n-l) must receive differing input signals, and thus provide an output signal equal to one. Therefore, at least one of the input signals to NOR gate 24ab must be equal to one causing NOR gate 24ab to have an output signal equal to zero. Similarly, NOR gate 24ba must receive at least one input signal equal to one and so will produce an output signal equal to zero. If a memory operation is initiated by a call through port B, a memory location address will be transmitted to the port B address input. That address is applied to input lines Abo through Ab(n-l). A short time later that same address will be applied, in delayed form, to lines AbOD through Ab(n#l)D. If a memory operation is then initiated through port A, the address called will be applied to input lines Aa0 through A(n#l). If the same memory location has been addressed through both ports A and B the input signals to each of EXCLUSIVE OR gates 22ab0 through 22ab(n-l) will be either two ones or two zeros. Therefore, each of EXCLUSIVE OR gates 22ab0 through 22ab(n-l) will produce an output signal equal to zero. As explained previously, NOR gate 24ba is producing an output equal to zero also. Therefore, all input signals to NOR gate 24ab are equal to zero and thus that NOR gate produces an output signal equal to one. This signal is used as a busy signal to prevent port A from having access to the requested memory location until port B has completed its access. Furthermore, the fact that the output signal from NOR gate 24ab is used as an input signal to NOR gate 24ba insures that NOR gate 24ba will continue to receive at least one input signal equal to one even after the delayed address sent to port A arrives at the input lines to EXCLUSIVE OR gates 22ba0 through 22ba(n-l) In that way, port B will not receive a busy signal. The above description explains how the present invention detects memory contention and resolves it in favor of port B, if port B were the first port to be addressed. Similarly, contention would be detected and resolved in favor of port A if port A were the first port to be addressed. If the two ports are simultaneously addressed both will attempt to produce a busy signal and allow access to the other port. In theory this could cause the system to lock out all futher attempted memory accesses. In realty, however, even if NOR gates 24ab and 24ba were designed to be identical, processing variations would be expected to cause NOR gates 24ab and 24ba to differ enough so as to prevent such lock out. Specifically, one of those gates will typically have greater capacitance than the other. The gate with higher capacitance will be able to force the other to a zero output value. This design could be left to chance so that either port A or port B would have precedence in a simultaneous addressing situation, or one gate or the other could be intentionally designed to have greater capacitance, insuring that all memories produced would have a preselected one of ports A and B having precedence. The discussion above has not dealt with the signals CEa and CEb. These are chip enable signals which are used in some, but not all, memory systems. Signal CEa is equal to zero when a memory operation is occurring through port A and equal to one if no such operation is occurring. Similarly, CEb is equal to zero if a memory operation is occurring through port B and is equal to one if no such operation is occurring. If the memory system in which the invention is to be used utilizes such chip enable signals, signal CE, should be connected via line 29 to NOR gate 24 and signal CE should be connected via line 30 to a NOR gate 24boa as is shown in Figure 3. when this is done a port is not considered to have begun addressing the memory until the proper address location has been tran i tted to that port and the associated chip enable signal has gone to a value of zero. As explained previously, this discussion has described a system for detecting and resolving memory contention in a dual port ram. Those skilled in the art will readily see that the same system could be used with more than two ports. If a third port, port C, were added a similar circuit would be provided to resolve contention between A and C. A third similar circuit would be required to resolve contention between ports B and C. Thus any number of ports could be accomodated under the present invention, simply by providing circuits to resolve contention between each pair of ports.

Claims: Claims: 1. Address contention detection and arbitration system for a memory having at least first (A) and second (B) ports, said first and second ports being adapted to receive first and second address signals, respectively, c h a r a c t e r i z e d b y (12ao 12a(n-1)) and second (12b0 - 12 delay means for producing first and second delayed address signals from said first (Aa0 - Aa(n-l)) and second (Abo - Ab(n-1)) address signals, respectively; b) first comparison means (22ab0 -22ab(n-l)) for comparing said first address signal with said second delayed address signal and generating a busy signal for said first port if said first address signal and said second delayed address signal are identical; ; c) second comparison means (22 - 22 for comparing bao ba(n-i)# said second address signal with said first delayed address signal and generating a busy signal for said second port if said second address signal and said first delayed address signal are identical; d) first suppression means (27) to prevent said first com parison means from generating a busy signal for said first port (A) when said second comparison means is generating a busy signal for said second port (B); and e) second suppression means (28) to prevent said second comparison means from generating a busy signal for said second port (B) when said first comparison means is generating a busy signal for said first port (A). 2. The system of claim 1, c h a r a c t e r i z e d i n t h a t said first and second address signals are n bit binary digital signals, where n is a positive integer, and each of said comparison means (22) includes n EXCLUSIVE OR gate. 3. The system of claim 2, c h a r a c t e r i z e d i n t h a t each of said EXCLUSIVE OR logic gates has first and second inputs and an output, said EXCLUSIVE OR gate of said first comparison means (22abc 22- 22ab(n-i)#being adapted to accept a signal representative of one bit of said n bits of said first address signal on said first input and a corresponding bit of said n bits of said second delayed address signal on said second input, and each of said EXCLUSIVE OR gates of said second comparison means being adapted to accept one bit of said n bits of said second address signal on said first input and one bit of said n bits of said first delayed address signal on said second input. 4. The system of claim 3, c h a r a c t e r i z e d i n t h a t each of said first and second comparison means includes a combining logic gate (24ab; 24bay 5. The system of claim 4, c h a r a c t e r i z e d i n t h a t said combining logic gates (24ab' 24ba) are NOR logic gate means having a plurality of inputs, each of said outputs of said EXCLUSIVE OR logic gates (22abc - 22ab(n 1)) of said first comparison means (22 b) being electrically connected to one of said inputs of said first comparison NOR gates (24ab), and each of said outputs of said EXCLUSIVE OR gates (22bay - 22ba(n-i)# ) of said second comparison means (22ba) being electrically connected to one of said inputs of said second comparison NOR gates (24ba). 6. The system of claim 5, c h a r a c t e r i z e d i n t h a t said first suppression means comprises an elec trically conducting means (27) electrically connecting said second comparison NOR gate (24ba) output (26ba) with one gate ba of said inputs of said first comparison NOR gates (24ab) and said second suppression means includes an electrically con ducting means (28) electrically connecting said first com parison NOR gate (24ab) output (26 b) with one of said in puts of said second comparison NOR gate (24ba). An address contention detection and arbitration system for a memory having first and second ports, said first and second ports being adapted to receive first and second address signals, respectively, each of said address signals being an n bit binary digital signal where n is a positive integer, c h a r a c t e r i z e d b y A) first #12ab0 - 12ab(n-1)# ) and second (12ba0 - 12 means for producing first and second delayed address signal from said first and second address signals, respectively; ; B) first plurality of EXCLUSIVE OR logic gates (22 abO 22ab(n-1)), each of said EXCLUSIVE OR logic gates of said first plurality thereof having first and second input means and output means, each of said first input means of said EXCLUSIVE OR logic gates of said first plurality thereof being adapted to accept as an input signal one bit of said n bits of said first address signal and each of said second input means of said EXCLUSIVE OR logic gates of siad first plutality thereof being adapted to accept as an input signal a corre sponding bit of said n bits of said second delayed address signal; ; C) second plurality of EXCLUSIVE OR logic gates (22, 22 (n-l) )r each of said EXCLUSIVE OR logic gates of said second plurality thereof having first and second input means and output means, each of said first input means of said EXCLUSIVE OR logic gates of said second plutality thereof being adapted to accept as an input signal one bit of said n bits of said second address signal and each of said second address signal and each of said second input means of said EXCLUSIVE OR logic gates of said second plurality thereof being adapted to accept as an input signal a corresponding bit of said n bits of said first delayed address signal; ; D) first NOR logic gates (24ab) having a plurality of input means and an output means, each of said output means of said EXCLUSIVE OR logic gates of said first plurality thereof being electrically connected to one of said input means of said first NOR logic gates; E) second NOR (24boa) logic gates having a plurality of input means and an output means, each of said output means of said EXCLUSIVE OR gates of said second plurality thereof being electrically connected to one of of said input means of said second NOR logic gates; F) first electrical conducting means (27) electrically connecting said second NOR logic gate (24ba) output (26ba) with one of said first NOR logic gates input means; and G) second electrical conducting means (28) electrically connecting said first NOR logic gate (24ab) output (26ab) with one of said second NOR logic gate means in put means. 8. The system of one of the preceding claims, c h a r a c terized by H) said first (A) and second (B) ports having associated therewith respectively, first (cue)and second (CEb) chip enable signal input means7 I) first electrical connecting means (29) provided between said second chip enable signal input (CEb) and one of said first NOR gate (24ab) inputs; and J) second electrical connecting means (30) provided between said first chip enable signal input (CE ) and one of a said inputs of said second NOR gate (24ba).

Inventors: HWANG, YUN-SHENG
Applicants: HONEYWELL INC.
Application year: 1986
Main classification: G06F13
IPC codes: G06F15, G11C8, G06F12, G06F9, G06F13