SYNCHRONIZING CIRCUIT FOR A PLURALITY OF POWER UNITS

Abstract: The circuit layout as claimed includes as many synchronizing units (US) as the number of the power units (UA). Each synchronizing unit (US) has been designed to receive an activation signal (CA) on its input, to be connected to the other units through of a first and a second bus (CSM, SM), and to deliver to the output a synchronizing clock signal (CK) for the respective power unit (UA). The first synchronizing unit (US) which receives said activation signal (CA) is qualified as master unit and applies a predetermined polarity to the first bus (CSM) and a clock signal to the second bus (SM) in order to synchronize the other units which, in response to the detection of said polarity on the first bus, are characterized as slave unit.

Description: SYNCHRONIZING CIRCUIT FOR A PLURALITY OF POWER UNITS The invention relates to a circuit for synchronizing a plurality of power units one with another, particularly of the type used in power stations for telecommunication systems. Usually the latter are constituted by a plurality of power units (such as inverters, etc.) connected in parallel one with another. The parallel connection is used when ' the power station has to generate such a power that a single power unit could not supply and therefore the required power is supplied by a plurality of power units connected in parallel one with another. Besides the units necessary to provide the operating power, at least one additional unit is usually required in order to have a hot, active reserve in case of failure of one of the said operative units. In almost all applications there is the problem that the said ' units must be synchronized one with another and/or with the electrical power distribution line (i.e: the mains). In particular synchronizing operations are necessary when the said units are DC-DC converters because, in case of a phase difference among the single units, low frequency interferences which lap over the useful signal may be registered. On the other hand, when the said power units are inverters, the synchronizing means are absolutely necessary, either to avoid damages hereinafter described , or to overcome the technical troubles which may arise from the switching power station - power distribution line. It is useful to point out that the inverters are constituted by units adapted to receive a direct current on the input and to deliver an output alternating current having the same characteristics of the power distribution line. The above mentioned switching must be carried out however with phase continuity, otherwise the single units will be pulled in to the mains at differentiated speed and cause a phase irregularity of the single units which compose the power station. The inverters of the latest generation are characterized by the fact that they have an output impedance that is sensibly low in order to approximate the characteristics of an ideal voltage generator. Said characteristic implies a perfect synchronism among the inverters of a same station, because if one of them is not in phase with the remaining units, the power delivered by the remaining units is reversed into the unit which is out of phase with a possible damage to the same. According to some well known solutions the synchronization troubles above mentioned may be solved by sending to a common branch point the clock signals generated by the single inverters. A reference clock signal is thus created on the said branch point that in working condition has a frequency equal to the arithmetical average of the inverters' frequencies. The devices are synchronized on the reference clock signal. This system presents however the inconvenience that the pulling in field for the different oscillators must be limited in order to maintain the average frequency within acceptable values/ Furthermore, the connection or disconnection of an inverter causes a frequency transient on the inverters actually operating. Other solutions., that are also well known, provide the generation of a master clock signal through a central oscillator on which the single inverters are synchronized. This solution does not present the inconvenience relating of the connection transient described above, (because the inverter is connected once the synchronization has been adjusted), but on the other hand the following trouble may arise: - it requires a slave oscillator, operating in phase with the master oscillator in order to carry out the switching with phase continuity, when necessary; it introduces limits to the system's reliability due to the circuits provided for the master-slave switching; - the cost of the structure described above (master oscillator, slave oscillator, switching circuits) constitutes a heavy item in the cost of the station when it is composed by only two inverters. The invention as claimed is intended to solve the problem of realize a circuit without the inconveniences mentioned above and at the same time it is suitable to switch the load to the electrical power distribution line without creating phase differences among the single inverters of the power station. For this purpose and according to the invention the circuit provides the connection of the respective synchronizing unit to " each power unit. Each of the said units has been designed to receive an activation signal on its input, to be connected to the other units by means of a first and a second bus and to deliver to the output the synchronizing clock signal for the relative power unit. The first synchronizing unit which receives said activation signal is characterized as the master unit, by applying a predetermined polarity to the first bus and delivering a clock signal to the second bus in order to synchronize the other units which are characterized as slave units, as response to the detection of the polarity. When the master receives a disconnection instruction on its input, it modifies the polarity on the first bus and qualifies the synchronizing unit, whose output clock signal has its phase shift anticipated in. comparison to -that of the other units, as the master unit. The circuit as claimed in the invention is characterized by the fact that each slave unit constitutes a standby unit redily available to replace the master unit with the following advantages: possibility of large pulling-in fields; high frequency stability of the master clock; - no centralized circuits on which the system's reliability depends; no cost increases when the station is constituted by only two power units. Further characteristics of the invention will be made clear by the following description relating to an example of the invention and completed by the attached figures where: fig. 1 shows the block diagram of a power station having the circuit as claimed by the invention; fig. 2 shows in detail one of the synchronizing units US of fig. 1; figs. 3 and 4 show wave forms relating to the synchronizing unit US illustrated in fig. 2. In fig. 1, the reference UA,, UA 2 ,... UA indicates as many power units which, together with the circuit according to the invention, are part of a power station for telecommunications systems feeding a load Z. Said circuit provides the presence of ιι synchronizing units US,, US 2 US , each of which is designed to provide a synchronizing clock signal CK,, CK 2 ,...,C for the respective power unit. Each synchronizing unit US has been designed to receive an activation signal CA on its input, as well as to be connected to the remaining units by means of a first and second bus CSM and SM. The first unit which receives the activation signal CA on its input acts as a master unit and is so qualified by applying a predetermined polarity to the first bus CSM and sending its own clock signal to the second bus SM. The other units, when activated, detect the said polarity on the' first bus CSM and are characterized as slave units by synchronizing its own clock signal with the clock signal* of the second bus SM. In the event of the master unit being subject to failure or if it is intentionally disconnected, it changes the polarity present on the first bus CSM, thus enabling one of the remaining units to be qualified as master. The slave units detect the presence of said polarity variation: in particular said variation is detected by the US unit whose output clock has its phase shift anticipated in comparison to the clock signals of the remaining units. Said unit is characterized therefore as master unit, it resets the polarity on the first bus and delivers its own clock signal to the second bus, which is qualified as master synchronizing clock signal. If two or more units detect the absence of the master unit at the same time and all of them are characterized as such, their respective oscillators tend to drift towards their own nominal frequencies and as a consequence, after just a few instants, the unit having the clock signal anticipated in comparison to that of the other units will be qualified as master unit. The invention as claimed provides also the possibility of synchronizing the power station to the electrical power distribution line, and for this purpose there is also a third and a fourth bus, hereinafter referred to as mains synchronism control CSR and mains synchronism SR. When synchronization to the mains is required, the CSR signal is activated, and this situation is taken by the master module which synchronizes its own oscillator to the clock signal present on the fourth bus SR. The master unit then delivers a clock signal, synchronized to the SR clock signal, to the second bus SM thus determining, as a consequence, the synchronization as well of the slave units. Fig. 2 illustrates in detail one of the synchronizing units US, shown in fig. 1. Said unit includes a phase locking circuit PLL, multiplexing means MMX, master-slave characterizing means CMS and bus driving means MPB. The phase locking circuit PLL provides the presence of a phase ' comparator PC and of a voltage controlled oscillator VCO to the output of which a frequency divider DV is connected. The PC unit receives the external clock signal CKE on the first input and the internal clock signal CKI on the second input, this latter signal being available at the output of the frequency divider DV. In diagrams A and B of fig. 3, a hypothetic phase relationship between the CKE sequence pulses and the CKI sequence pulses is illustrates, as well as the signals delivered by the PLL unit in response to the reception of the said sequences. The CKI pulses' lenght has been on purpose varied in order to better evidence the PLL unit operation. In particular, the PC unit delivers to the first output U, (see diagram C) a pulse sequence with a duration that is proportional to the interval of time between the transition of the CKE signal and the transition of the CKI signal. Pulses with a duration proportional to the interval of time between a positive transition of the CKE signal and a positive transition of the CKI signal, having a positive sign or a negative sign if the CKE signal is anticipated, or delayed, in comparison to the CKI signal, are available at the output U 2 (see diagram D). The VCO unit receives a signal V on its input which determines a modification of the frequency of the CKI signal aiming to cancel any deviations from the CKE signal's frequency. The PLL circuit described above is characterized in that it has a very high loop gain with consequent low immunity to interferences. The invention includes the presence of means adapted to l mit the PLL's dinamic loop gain when the mains synchronism control CSR is active, thus increasing the circuit's immunity to any interference present on the mains synchronism SR: in fact, said interference could cause negative effects to the power unit UA in operation. The means described above are a part of the multiplexing means MMX and are adapted in such a way as to chop the signal available at the PLL's output U 2 by means of an electronic switch I, controlled by the pulses corresponding to the output of a monostable circuit MN adapted to receive the PLL's output U,. The pulses corresponding to the output of the MN unit are illustrated in diagram E of fig. 3. The signal V reaches the VCO unit through a first multiplexer MT, which receives the pulses from the U 2 output of the PC unit on its first and second input, the pulses from the switch I output on its third input and a monitoring voltage V , (through a first and second resistance R, and R 2 and stabilized by a Zener diode DZ), on its fourth input. The external clock signal CKE reaches the PC unit through a second multiplexer MT 2 , which receives the mains synchronism SR pulses on its third input, and the master synchronism SM pulses on its first, second and fourth inputs. The multiplexers MT, and MT 2 receive signals coming from the master-slave qualifying means CMS on their control inputs. The activation control CA, a mains synchronism control CSR and a master synchronism control CSM are delivered to the input of the master-slave qualifying means CMS. The CSR control reaches the first control input of the MT, and T 2 units through an inverter circuit I,. The CA control reaches the second control input of the MT, and MT 2 units through a logical sum circuit 0, which receives the output Q of a bistable circuit FF of the D type on its second input. The bistable circuit FF receives the internal clock CKI on its data input, and the same internal clock CKI on its timing input through a logical sum circuit 0 2 which receives the SM pulses on its second input through an inverting circuit I 2 . The FF unit has the enabling input connected to the output of another logical sum unit 0 3 which receives the said CA control on its first input and on its second input the output of a logical product circuit A, adapted to receive through an inverting circuit I 3 the CSM control signal as well as the output Q of FF. The bus driving means MPB include a first, and second transistor T, and T 2 having the emitter and collector connected in series respectively to said first and second bus. The base of T, is connected to the output Q of FF by means of a resistance R,, and also to the emitter by means of a resistance R,. The base of T 2 , on the other hand, is connected to the output Q of FF by means of a logical product circuit A 2 and a resistance Rg. The A 2 unit receives the clock signal CKI on its second input. A resistance R & 5 is connected between the base and the emitter of T 2 . The operation of the structure as described above is hereinafter described using of the waveforms illustrated in fig. 4, wherein diagram a) shows the activation signal CA which, when the unit is disconnected, presents a high logical value. o Let us assume that the unit in question is the first unit activated and that the mains synchronism signal CSR is active so as to synchronize the said unit to the electrical power distribution line. The signal CSR is illustrated in diagram b) of fig. 4. 5 In these conditions, the mains synchronism pulses SR correspond to the output of MT 2 , while the pulses available at the output of the switch I correspond to the output of MT,. In relation to the phase difference between the internal clock CKI and the external clock CKE, said pulses determine the charge or discharge of a condenser 0 (not illustrated) present in the VCO unit and correct the frequency of the CKI pulses until it coincides with that of the CKE = SR pulses. When the activation control CA assumes logical value zero, the FF unit is enabled to transfer the logical levels present on its data 5 input (see diagram c of fig. 4) to output Q in correspondence with the positive transitions of the pulses available at the output of . the 0 2 (see diagram d). As the pulses applied to the timing input of FF are delayed in comparison to the pulses applied to the data input (as the former pass through the 0 2 unit), on the first positive transition of the pulses available at the output of the latter unit, the activation of the Q output of FF is registered (see diagram e) and consequently the conduction of the transistor T, which applies a zero polarity to the first bus CSM (see diagram f) . The output Q of FF also determines the enabling of the A 2 unit which sends the CKI pulses, provided by the PLL unit, to the second bus SM (see diagram g). The presence of said zero polarity on the first bus CSM is detected by the remaining units on the activation of the relative CA signal. The delivery of the SM signal present on the second bus and at the output of MT 2 and of the signal available at the U 2 output of PLL to the output of MT, occours in fact in said units In this manner the slave units are synchronized with the SM pulses provided by the master unit, and as the latter s synchronized with the SR pulses, a synchronization of all the units with the SR pulses is obtained. If the mains synchronism signal CSR is switched off, the master unit delivers the voltage V to the output of MT, and the clock signal, provided by the respective PLL unit, to the output of 2 . The presence of the resistance R 2 and the internal capacity of the VCO unit, assure therefore that the PLL unit (associated to the master unit) gradually tends to oscillate at its nominal frequency thus avoiding the danger of sudden phase shifts. When the master unit receives a switching off instruction (CA signal with logical value one) FF is no more enabled and generates a logical value zero which cuts off the transistor T, . The slave units detect the presence of polarity "one" on the CSM bus and the unit whose CKI clock has an anticipated phase is qualified as master unit. As all the units have a phase coincidence, it may be that two or more units are characterized as master and consequently their respective PLL units tend to shift towards their nominal frequency. When this phase difference between the said units become an appreciable entity (see diagram h of fig. 4 where the clock CKI' of a generical unit is shown) only the unit having its phase anticipated remains qualified as master. When there is no master unit, a signal obtained from the sum of the clock signals of all the units is registered at the output of the 0 2 unit (see diagram i); said signal, reaching the timing input of FF, enables the unit which has an anticipated phase to keep output Q active (see diagram 1), while the output Q' of the FF unit, whose clock CKI' has its phase delayed, is disconnected as illustrated in diagram m). The circuit as claimed fully meets the requirements evidenced at the beginning of this description as it is adapted to synchronize a plurality of power units each with the other and to the electrical power distribution line and it further avoids that many units remain qualified as master unit before that the phase difference among the single units assumes values that could cause the troubles mentioned before.

Claims: CLAIMS 1) Synchronizing circuit for a plurality of power units, especially for telecommunications systems, characterized by the fact that each power unit (UA,, UA 2 UA ) is associated to a respective synchronizing unit (US,, US 2 ,...,US ), by the fact that each of these latter units has been designed to receive an activation signal (CA) on the input, to be connected to the remaining units through a first and a second bus (CSM and SM) and to deliver a synchronizing clock signal (CK) to the respective power unit (UA) by the fact that the first synchronizing unit (US) which receives said activation signal (CA) on its input is qualified as master unit and applies a predetermined polarity to the first bus (CSM) and a clock signal to the second bus (SM) adapted to synchronize the remaining units which, in response to * the detection of said polarity on the first bus (CSM), are qualified as slave units, and by the fact that when the master synchronizing unit receives a switching off signal on the input, it modifies the polarity on the first bus (CSM) thus enabling the unit whose output clock signal (CK) has ' the phase anticipated in comparison with the others, to be qualified as master unit. 2) Circuit as described in claim 1 characterized by the fact that each of said synchronizing units (US) is also connected to the remaining units by means of a third and a fourth bus (CSR and SR) which respectively receive a mains synchronism (CSR) and a clock signal (SR) that is synchronized with the electrical power distribution line, further characterized by the fact that when the mains synchronism signal (CSR) is operating, the master unit synchronizes the clock available on its output with said mains synchronism clock signal (SR), as response to the detection of such event. 3) Circuit as described in claims 1 and 2 characterized by the fact that each synchronizing unit (US) provides the presence of the following characteristic elements: - a phase locking circuit (PLL) designed to receive the clock signal (CKE), present on the second or on the fourth bus (SM or SR), on its first input, the clock signal (CKI) on its second input and the monitoring signal (V) of the respective oscillator on its third input, furthermore designed to deliver to a first output (U,) a sequence of pulses with a lenght proportional to the time interval between a transition of the signal applied to its first input and a transition of the signal applied to its second input, and to its second output (U 2 ) pulses whose the lenght is proportional to the time interval between two positive transitions of the signals applied to said first and second input and whose sign is positive or negative if the signal (CKE) applied to its first input is anticipated or delayed in comparison to the signal applied to its second input (CKI); 5 - multiplexing means (MMX) having their input connected to said' second and fourth bus (SM, SR) as well as to said first and second output (U, , U 2 ) of the phase locking circuit (PLL) and also having their outputs connected to said first and third input (CKE, V) of the phase locking circuit; o - master-slave characterizing means (CMS) having their input connected to said first and third bus (CSM, CSR) , designed to receive said activation signal (CA) on their input as well as to deliver to the output the monitoring signals of said multiplexing means (MMX); 5 - bus driving means (MPB) to which receive on the input the clock signal (CK) available on the output of the phase locking circuit (PLL) and designed to send said clock signals to the second bus (SM), as well as to apply said polarity to the first bus (CSM), when an output (Q) of the master-slave 0 characterizing means (CMS) is operating. 4) Circuit as described in claim 3 characterized by the fact that said multiplexing means (MMX) provide the following characteristic elements: 5 - a first multiplexer (MT,) designed to receive the signal available on the second output (UJ of the phase locking • circuit (PLL) on its first and second input, the same signal chopped on its third input and a monitoring voltage (V ), stabilized by a Zener diode (DZ) through a first and second resistance (R,, R 2 ) on its fourth input; a chopping switch (I) whose input is connected to the second output of the phase locking circuit (PLL) and whose output is connected to the third input of the first multiplexer (MT,); a monostable circuit (MN) whose input is connected to the first output (U,) of the phase locking circuit (PLL), while the output reaches the control input of said chopping switch (I); a second multiplexer (MX 2 ) having its first, second and fourth input connected to said second bus (SM) and its third input connected to said fourth bus (SR). 5) Circuit as described in claim 3 characterized by the fact that said master-slave characterizing means (CMS) provide the following characteristic elements: a D type bistable circuit (FF) designed to receive the puTses (CKI) generated by the phase locking circuit (PLL) at the data input; a first logical sum circuit (0,) designed to receive the output (Q) of the bistable circuit on the first input and said activation signal (CA) on its second input; a second logical sum circuit (0 2 ), having the output connected to the timing input of the bistable circuit (FF), whose first input receives the clock signal (CKI) generated by the phase locking circuit (PLL), while the second input is connected to the second bus (SM); a third logical sum circuit (0,) whose output is connected to the enabling input of the bistable circuit (FF), whose first input receives said activation signal (CA) while the second input is connected to the output of a first logical product unit (A,) having its inputs .connected to the inverted output of the bistable circuit (FF) and to said first bus (CSM). 6) Circuit as described in claim 3 characterized by the fact that said bus driving means (MPB) provide the following characteristic elements: a first transistor (T,) having the emitter and the collector connected in series to the first bus (CSM) and having the base connected to the output of the bistable circuit (FF); - a second logical product circuit (A 2 ) whose first input receives the clock signal (CK) generated by the phase locking circuit (PLL), while the second input is connected to the output (Q) of the bistable circuit (FF); a second transistor (T 2 ) having the collector and the emitter connected in series to the second bus and having the base connected to the output of the second logical product circuit (A 2 ).

Inventors: LENTINI SALVATORE, PATTI GIUSEPPE, LENTINI, SALVATORE, PATTI, GIUSEPPE
Applicants: ITALTEL SPA, ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI S.P.A
Application year: 1986
Main classification: H02J3
IPC codes: H02J1, H02J3, H04J3