LIGHT CONTROL CIRCUIT OF AN OPTICAL DISC SYSTEM

Abstract: A light control circuit of an optical disc system controls the light intensity from a laser diode (LD) at a read power level even if a write data operation is performed. The light control circuit comprises a light controller (2, 3, 5) which energises the laser diode and controls its light output at a predetermined level sufficient for reading data from the optical disc in response to a signal from a photodiode (PD). A transistor circuit (6, 8) su­ perimposes energisation of the laser diode in addition to the energisation by the light controller, at a second predetermined level sufficient for writing data to the optical disc. A subtract­ ing circuit (9, 10), operable synchronously with the superim­ posed energisation circuit, subtracts a third predetermined lev­ el, corresponding to the electrical power supplied by the super­ imposed energisation circuit to the laser diode, from the signal of the photodiode. The circuit may also include a reference value setting circuit (21, 4, 16, 7, 14) for automatically finding and determining reference values of a read power level, a write power level and a subtraction value.

Description: This invention relates to an optical disc system for optically performing data writing and reading. More particularly, it relates to a light control circuit of an optical disc system which controls the level of beam energy emitted from a light emitting element at a predetermined rated level. An optical disc system used as a large-capacity external memory device for a data processing unit can record at a density more than ten times that of the recording density attainable by a conventional magnetic disc system. Data recording in an optical disc system is accomplished, for example, by applying a strong laser beam from a laser diode at an intensity corresponding to 5 to 10 mW as an optical beam having a write power level to a recording film on an optical disc medium to form holes (pits) on the recording film by thermal reaction. This recording can alternatively be accomplished by changing the crystal state of the recording film. The data written in the optical recording medium can be read out from the intensity of the reflected beam obtained when a weak laser beam emitted from the laser diode at an intensity corresponding, for example, to about 1 mW, is applied to the recording film as an optical beam having a read power level. In order to obtain a stable laser beam at power levels such as the write power level and the read power level, the emission intensity of the laser diode is monitored by a photodiode, and a laser control circuit controls the emission power of the laser diode in response to the monitored current therethrough. The laser diode has inherent characteristics, and when the laser diode is used for an optical disc system, these inherent characteristics are adjusted so that a substantially constant write power level and read power level can be obtained. A simple control circuit is needed in which the above-mentioned adjustment and control for always obtaining a constant write power level and read power level can be easily accomplished. An object of the present invention is to provide a light control circuit for an optical disc system having a light emitting element used for writing data to, and reading data from, an optical disc, for performing precise automatic power control at a read level of the light emitting element even if the write operation is effected by the light emitting element. According to the present invention, there is provided a light control circuit of an optical disc system having an optical disc for storing data, a light emitting element for writing data to and reading data from the optical disc, and a light sensing element for sensing light from the light emitting element; characterised by light control means for energising the light emitting element and for controlling the light output, of the light emitting element at a first predetermined level sufficient for reading data from the optical disc in response to a signal from the light sensing element; means for superimposed energisation of the light emitting element, in addition to the energisation by the light output controlling means, at a second predetermined level sufficient for writing data to the optical disc, when data are to be written to the optical disc; and subtracting means operable synchronously with the superimposed energisation means, for subtracting a third predetermined level corresponding to the electrical power supplied by the superimposed energisation means to the light emitting element from the signal of the light sensing element. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of an embodiment of a light control circuit in accordance with the invention; Fig. 2 is a graph illustrating the relationship between driving current and emission intensity of a laser diode used in the circuit of Fig. 1; Fig. 3 is a graph representing a write power level and a read power level of the laser diode; Fig. 4 is a block schematic diagram of a microprocessor unit used in the circuit of Fig. 1; Fig. 5 is a circuit diagram of another embodiment of a light control circuit in accordance with the invention; Figs. 6a and 6b together form a flow chart illustrating an operation for determining reference values of the light control circuit shown in Fig. 5; Fig. 7 is a circuit diagram of a further embodiment of a light control circuit in accordance with the invention; and Figs. 8a and 8b together form a flow chart illustrating an operation for determining reference values of the light control circuit shown in Fig. 7. A first embodiment of a laser control circuit in accordance with the invention will now be described in detail with reference to Figs. 1 to 3. The circuit shown in Fig. 1 for controlling the driving of a laser diode in an optical disc system includes a laser diode unit 1, a photodiode current adjustment unit 2, a read power level detection unit 3, a D/A converter 4, a read power level current adjustment unit 5, a write power level current adjustment unit 6, a D/A converter 7, a write power level setting unit 8, a write power level current subtraction setting unit 9, a write power level current subtraction unit 10, a level shift unit 11, and a microprocessor unit (MPU) 21. The hermetically-sealed laser diode unit 1 comprises a laser diode (LD) which emits a beam of a read power level, for example at an intensity corresponding to about 1 mW, and a beam of a write power level, for example at an intensity corresponding to 5 to 10 mW, and a photodiode (PD) for monitoring the intensity of the beam emitted from the LD. The photodiode current adjustment unit 2 comprises a variable resistor RV1 for adjusting the monitoring current flowing through the PD to a predetermined value at the time of initial setting. The read power level detection unit 3 comprises an operational amplifier 31, fixed resistors R1 and R2, and a feedback capacitor C1. The read power level detection unit 3 detects a PD voltage taken from the photodiode current adjustment unit 2, and outputs a voltage corresponding to the read power level set by the D/A converter 4 in response to the detected PD voltage. The voltage output from the D/A converter 4 is defined in advance by the microprocessor unit 21 so that the output power of the LD provides the read power level. The read power level current adjustment unit 5 comprises a transistor TR1, a coil L and a fixed resistor R3, and adjusts the driving current of the LD so that a beam of the read power level is emitted therefrom. The write power level current adjustment unit 6 comprises two transistors TR2 and TR3 with coupled emitters, and a fixed resistor R4, and adjusts the driving current of the LD so that a beam of the write power level is emitted therefrom. The transistors TR2 and TR3 are connected so that a differential operation is performed so as to realise high-speed operation. The D/A converter 7 is set to a predetermined output by the microprocessor unit 21 so that the LD within the unit 1 emits light corresponding to the write power level. The write power level setting unit 8 comprises a transistor TR4 and a fixed resistor R5 and sets a reference write power level for the write power level current adjustment unit 6 so that the LD emits laser beams in response to the write power level set at the D/A converter 7. The write power level current subtraction setting unit 9 consists of a transistor TR5 and a variable resistor RV2 and sets a reference subtraction value corresponding to the output from the D/A converter to the write power level current subtraction unit 10. The write power level subtraction unit 10 consists of two transistors TR6 and TR7 and a fixed resistor R6, which are differentially connected so as to realize a high-speed operation, and this unit 10 subtracts the above set write power level current from the PD current on which write power level current is superimposed the read power level current. The level shift unit 11 includes a logical product circuit AND, two zener diodes D1 and D2 and resistors R7 and R8 and adjusts the biases of the transistors TR2, TR3, and TR7 of the write power level current adjustment unit 6 and the write power level current subtraction unit 10 so that the write power level current adjustment unit 6 and the write power level subtraction unit 10 are operated according to the write data. For example, the current supplied to the LD when writing data is applied is a pulse waveform as shown in Fig. 2. The ordinate of Fig. 2 indicates the emission quantity (mW) of the LD and the abscissa of Fig. 2 indicates the current applied to the LD. Reference symbol CV represents the inherent characteristic curve of the LD, reference symbol P WR represents the write power level, reference symbol P RD stands for the read power level, reference symbol I WR stands for the level of the current flowing in the LD when writing data, and reference symbol I RD represents the level of the current flowing in the LD when reading data. The PD voltage obtained by monitoring the intensity of beams emitted from the LD by the PD has a waveform as shown in Fig. 3. Namely, the PD voltage has a waveform obtained by superimposing a pulse waveform having an amplitude of the write power level P WR on the constant read power level P RD . When the write frequency is 3.7 MHz, the width of the write pulse is 50 to 70 nsec. The LD has inherent characteristics, and if there are great changes in the write power level and read power level emitted from the LD, these have an adverse influence on the read and write data quality and the like. Accordingly, an initial setting is performed by adjusting the variable resistor RV1 of the PD current adjustment unit 2 so that a substantially constant write power level and read power level are always obtained irrespective of the characteristics of the LD. More specifically, the variable resistor RV1 is adjusted so that LD is caused to emit laser beams at a certain power by metering by means of a power meter or synchroscope corrected in the state completed as an optical head (not shown), the output voltage of the PD is maintained at a certain level, and the variable resistor RV1 is locked by a fixative, to fix it in this state. In the circuit shown in Fig. 1, an automatic power control (APC) circuit is constructed by the PD in the LD unit 1, the PD current adjustment unit 2, the read power level detection unit 3, and the D/A converter 4. More specifically, the reference value of the power level is applied to a non-inverted input terminal of an amplifier 31 from the D/A converter 4, and the detection value of the PD is applied to an inverted input terminal of the amplifier 31 as a feedback signal. Accordingly, the amplifier 31 supplies a current corresponding to the deviation of the detection value of the PD and the reference value to the LD in the LD unit 1 through the transistor TR1, and the LD is caused to emit laser beams having an amplitude corresponding to the reference value. In principle, since the LD is always actuated at the read power level, this operation of the APC is effected at the read power level. Thus, the read power of the LD is provided through the read power level current adjustment unit 5 under the operation of the APC. The write power is obtained by additionally supplying a current, to be superimposed on the current flowing in the LD through the read power level current adjustment unit 5, through the write power level current adjustment unit 6, and the write power level setting unit 8. Namely, a control voltage capable of supplying a current to be superimposed as the write power level is given in advance from the transistor TR4 in the write power level setting unit 8 via the D/A converter 7. When writing data, by giving a write data signal W/RD and a write gate signal W/RG to the level shift unit 11 from MPU 21, the write power level current adjustment unit 6 is energized. More specifically, the transistor TR2 is turned ON. Thus, a current corresponding to the write power level, to be superimposed, flows through the LD, the transistor TR2, the transistor TR4, and the resistor R5, whereby the LD is caused to emit output beams of the predetermined write power level according to the write data. When the operation of the APC at the time of writing the data is taken into consideration, the APC circuit, per se,fulfills a control for obtaining the reference value set by the D/A converter 4, and therefore, if the LD is actuated at the above-mentioned write power level, the APC circuit reduces the current flowing through the LD via the transistor TR1 to obtain the read power level. At this time, the output beam amplitude of the LD is reduced to the read power level, and therefore, when writing data, output beams at the write power level cannot be obtained. To avoid this phenomenon, a means for by-passing the operation of the APC when writing data is adopted in the conventional circuit. In the embodiment, the operation of the APC is continued even when writing data. More specifically, the write power level current subtracting setting unit 9 and the write power level current subtraction unit 10 are provided, and these circuits are actuated synchronously with the writing operation, and the reading of the PD corresponding to the current supplied to the LD when superimposed on the current corresponding to the write power level is subtracted through the transistor TR7 in the write power level current subtraction unit 10, the transistor TR5 in the write power level current subtraction setting unit 9 and the resistor RV2 from the current flowing through the PD and applying it to the read power level detection circuit 3. Of the reading of the PD, the current applied as the feedback signal to the inverted input terminal of the amplifier 31 in the read power level detection unit 3 corresponds to the read power level. As a result, even when writing data, the APC functions to maintain the read power level without any influence from the write pulse. Where this automatic adjustment function is set so that the predetermined APC function is exerted, the voltage corresponding to the write power level, from which the current is to be subtracted, is applied to the transistor TR5 from the D/A converter 7, and the subtraction adjustment is achieved by adjusting the variable resistor RV2 in the write power level current subtraction setting unit 9, and to fix this state, the variable resistor RV2 is locked by a fixative. Conversely, in the circuit shown in Fig. 1, an operation for locking the variable resistors is necessary, and the automation of a test, such as a printed circuit board test, becomes difficult. Furthermore, a reduction of the number of test steps and a reduction of the cost cannot be attained. If the LD is replaced or other LDs having other characteristics are used, the above troublesome adjustment is required. MPU 21 sets the reference values through the D/A converters 4 and 7 and energizes the write power level current adjustment unit 6 and write power level current subtraction setting unit 10 through the level shift unit 11. MPU 21 has a structure shown in Fig. 4 and performs the above operation. The microprocessor 21 includes, for example, a data bus buffer DBB, an address bus buffer ABB, an A register, a B register, an arithmetic and logic unit ALU, an instruction register 1, an input/output interface, and a control circuit CONT. The microprocessor 21 used may be, for example, Intel 8031. The ROM 93 stores programs tables of data for the above operation. The oscillator 94 generates a clock signal CLK which is applied to the control circuit CONT in the microprocessor 21. The D/A converters 4 and 7 for setting the reference value may be replaced by variable resistors or the like. Furthermore, when the level shift unit 11 is directly driven by the write data, the MPU 21 can be omitted. A second embodiment for solving the problem concerning the adjustment and fixation of the variable resistor RV2, which is involved in the first embodiment, will now be described with reference to Fig. 5. Figure 5 shows a light control circuit of the second embodiment. In addition to the circuit unit blocks 1 through 11 illustrated in Fig. 1, and except for the PD current adjustment unit 2, this control circuit includes, instead of the PD current adjustment unit 2, a PD current/voltage conversion unit 12 for converting the current flowing through the PD to a voltage at a predetermined ratio, and an analog switch 13 disposed between the PD current/voltage conversion unit 12 and the read power level detection circuit unit 3 to cut off the output of the PD current/voltage conversion unit 12 while the D/A converter 4 is set by the microprocessor unit (MPU) 21 at the PD voltage at which the output of an A/D converter 16 indicates the read power level, to thereby stop the function of the read power level detection unit 3. The control circuit shown in Fig. 5 further includes a D/A converter 14 set by the MPU 21 to determine the PD voltage value where the output of the A/D converter 16 indicates the read power level, an analog switch 15 disposed between the write power level setting unit 8 and the write power level current subtraction setting unit 17 to turn ON the operation of the write power level current subtraction setting unit 17 while the D/A converter 14 sets the PD voltage where the output value of the A/D converter 16 indicates the read power level, and the A/D converter 16 for setting the PD voltage at each time and informing the MPU 21 of the set PD voltage. Note, the first automatic control, that is, read power level control, is accomplished by the read power level detection unit 3 and read power level current adjustment unit 5, and second automatic power control, that is, write power level control, is accomplished by the write power level setting unit 8 and write power level current subtraction setting unit 17. The PD current/voltage conversion unit 12 includes fixed resistors R9 through R13 for converting the PD current to a voltage at a predetermined ratio and switches 22 for short-circuiting each of the fixed resistors R9 through R13, for example, duplex switches, short bars, or analog switches. In the embodiment illustrated in the drawinqs, duplex switches are used. The fixed resistors R9 through R13 of the PD current/voltage conversion unit 12 are weighed by 1, 2, 4, 8 and 16, respectively, at the time of designing. ON-OFF setting of the switches 22 is effected when assembling the system or before a test. More specifically, the emission power of the LD and the PD currents differ among the LD units 1, and because of large errors, these elements cannot be directly used. Accordingly, the characteristics are determined in advance, and based on the characteristic data, the combination of the preliminarily weighed resistance values of the fixed resistors R9 through R12 is determined by the switches 22 so that the output voltage of the PD upon emission with a certain power, that is, the value set at the A/D converter 16 by the A/D conversion, is kept constant. Thus, the relationship between the emission power of the LD and the PD voltage is determined so that, for example, when the emission power is 1 mW, the PD voltage is 0.5 V. Since the emission power and the PD current are in a 1 to 1 correspondence, as the emission power is changed, a corresponding PD voltage is obtained. The foregoing processes are carried out before the delivery of products, and the following processes may be made when the system is actually used, for example, when the power source is turned ON or when an optical disc is exchanged. The first automatic power control, i.e. the above APC, processing unit having a function of automatically adjusting the emission power of the PD by the feedback of the read power level, such as the read power level direction unit 3 or read power level current adjustment unit 5, that is, the first APC processing unit which acts so that when the emission power of the LD is changed by a rise in the temperature or the like, as indicated by the dot line in Fig. 3, the change is cancelled to return the dot line to the solid line in Fig. 3, is turned OFF by the analog switch 13. Note, the analog switch 13 is turned ON and OFF by the microprocessor 21. Furthermore, while the function of the first APC processing unit is turned OFF by the analog switch 13, the MPU 21 sets data to the D/A converter 4 so that a value converted by the A/D converter 16 is equal to the PD voltage indicating the specified power of about 1 mW for reading. The set value of the D/A converter 4 is supplied to the base of the transistor TR1 through the operational amplifier 31 acting as a voltage follower when the APC is OFF, whereby the transistor TR1 is turned ON and the emitter voltage, voltage VEE1, and the current determined by the fixed resistor R3 are supplied to the LD to realize the first APC process. The operation of adjusting the emission power at the write power level will now be described. In this case, since a power capable of writing of data is output, the power level is defocussed so that data writing becomes impossible. Since pulse modulation of the emission is effected when writing data, as shown in Fig. 2, the PD voltage is determined according to the duty cycle ratio of the pulse. For example, where the pulse emission power is 10 mW and the duty ratio is 50%, and the read power is 1 mW at 0.5 V/mW, the PD voltage is determined as follows: {[(10 mW - 1 mW)/2] + 1 mW} x 0.5 = 2.75 V. The value of the D/A converter 7 is set by the MPU 21 so that the output of the A/D converter 16 becomes equal to this value. Note, the write power level is changed by proportionally changing this value. Then, the write power level current subtraction unit 10 for subtracting the current corresponding to the superimposed write power level emission from the PD current is actuated. More specifically, the analog switch 15 is turned ON and the second APC unit including the write power level current subtraction setting unit 17 is turned ON, and the set value of the D/A converter 14 is determined so that the value of the A/D converter 16 indicates the PD voltage of the read power level. Note, this voltage value is 0.5 V. Finally, the first APC processing unit is turned ON and the set value of the D/A converter 14 is adjusted again, whereby the output value of the A/D converter 16 is equal to the read power level value of 0.5 V. As shown in Fig. 5, the MPU 21 receives the data of the A/D converter 16, gives predetermined set values to the D/A converters 4, 7, and 14, actuates the analog switches 13 and 15, and gives the write gate signal W/RG and write data signal W/RD to the level shift circuit unit 11. The operations of MPU 21 and the circuit shown in Fig. 5 will now be described with reference to the flow chart of Fig. 6. Step 001 (S001) MPU 21 turns OFF the analog switch 13 to turn OFF the APC, whereby the amplifier 31 is maintained as a voltage follower and the input voltage applied to the non-inverted input terminal is directly output. Step 002 (S002) The read output data of the D/A converter 4 is initially set at zero (0). Step 003 (S003) The D/A converter 4 applies the analog voltage based on the output data to the non-inverted input terminal of the amplifier 31. The voltage of the applied polarity is applied from the amplifier 31 to the base of the transistor TR1. Where the output voltage of the D/A converter 4 is zero, the transistor TR1 is turned OFF and the LD is not energized. As the output voltage of the D/A converter 4 is increased, as described below, the LD emits beams at an amplitude corresponding to the output voltage of the D/A converter 4. Step 004 (S004) The emitted light of the LD is detected by the PD and the detected value is converted to a digital value by the A/D converter 16 and supplied to the MPU 21. Steps 005 and 006 (S005 and S006) MPU 21 determines whether or not the A/D-converted detected value of the PD has reached the read power level. If the detected value has not reached the read power level, 1 is added to the output data of the D/A converter 4 and the routine returns to step 003 (S003). The operations of steps S003 through S006 are repeated until the detected value of the PD reaches the read power level. Step 010 (S010) When the detected value of PD reaches the read power level, the MPU 21 supplies such an output to the AND gate of the level shift unit 11 that the write gate signal W/RG is turned ON and the write data signal W/RD is turned ON, whereby the write power level current adjustment unit 6 and write power level setting unit 10 are energized through the level shift unit 11. Namely, the transistors TR2 and TR7 are turned ON, and through the transistor TR2, the LD is placed in the state where emission to the write power level is possible. Note that a read power level reference value determined through the above procedures is supplied to the noninverted terminal of the amplifier 31 through the D/A converter 4. Step 011 (S011) The MPU 21 sets an initial write output data, i.e. zero, to the D/A converter 7. Step 012 (S012) The analog voltage based on the write output data is applied to the gate of the transistor TR4 of the write power level setting unit 8 through the D/A converter 7, whereby the write current is supplied to the LD through the transistor TR2 of the write power level current adjustment unit 6 and the LD is energized to emit laser beams at a level exceeding the read power level. Step 013 (S013) The emitted light of LD is detected by the PD and the detected value is converted to a digital value by the A/D converter 16 and supplied to MPU 21. Steps 014 and 015 (S014 and S015) MPU 21 determines whether or not the detected value of the PD has reached the write power level. If the detected value has not reached the write power level, 1 is added to the write output data of the D/A converter 7 and the routine returns to step S012. The operations of steps S012 through S015 are then repeated until the detected value of the PD reaches the write power level. Through the above operation, a write power level reference value is determined. The determined reference value is output from the D/A converter 7. Step 020 (S020) When the detected value of the PD reaches the write power level, the MPU 21 sets the same value as the final write data of the D/A converter 7 at the D/A converter 14, whereby a state is attained wherein, when writing data, the amplitude of the write pulse shown in Fig. 3 can be subtracted from the write power level current subtraction unit 10 through the write power level current subtraction setting unit 17. Step 021 (S021) The MPU 21 turns ON the analog switch 15 to actuate the write power level current subtraction setting unit 17 and write power level current subtraction unit 10. Step 022 (S022) The D/A converter 14 supplies the analog voltage based on the write output data to the transistor TR5 of the write power level current subtraction setting unit 17 to subtract the superimposed write current. According to the output voltage of the D/A converter 14, the LD emits laser beams at the subtracted current, i.e., at the read power level. Step 023 (S023) The light emitted from the LD is detected by the PD, and the detected value is converted to a digital value by the A/D converter 16 and supplied to the MPU 21. Steps 024 and 025 (S024 and S025) The MPU 21 determines whether or not the detected value of the PD has been reduced to the read power level, and if the detected value is not reduced to the read power level, 1 is subtracted from the output data of the D/A converter 14 and the routine returns to step S022. The operations of steps S022 through S025 are repeated until the detected value of PD is reduced to the read power level. Step 030 (S030) If the detected value of PD is reduced to the read power level, the MPU 21 applies an output to the AND gate of the level shift unit 11 such that the write gate signal W/RG is turned OFF and the write data signal W/RD is turned OFF to deenergize the write power level current adjustment unit 6 and write power level setting unit 10. Step 031 (S031) By automatically setting the read power level and write power levels by the foregoing operations, the MPU 21 turns ON the analog switch 13, and accordingly, turns ON the APC. In brief, when the APC is turned OFF (S001), the read power level is determined (S002 through S006) and the write power level is determined (S010 through S015), and the so-determined reference values of the read power level, the write power level and the subtraction current are set at the D/A converters 4, 7, and 14. After the reference values are automatically determined in the foregoing manner, the APC is turned ON and the normal operation becomes possible. According to the above-mentioned embodiment, automation of the test of the laser control circuit, reduction of the number of test steps, and a reduction of the cost can be easily accomplished. Moreover, according to the present embodiment, an exchange of LD units can be easily performed and a predetermined emission power can be always obtained. Another embodiment of the present invention will now be described with reference to Fig. 7. In a light control circuit shown in Fig. 7, analog switches 53 and 55 and a PD current adjustment unit 12′ are arranged instead of the analog switches 13 and 15 and the PD current adjustment unit 12 of the laser control circuit shown in Fig. 5. A balancing circuit 50 including resistors R58 through R61 and an operational amplifier 51 are arranged between the PD current adjustment unit 12′ and read power level detection unit 3′. The A/D converter 167 is not directly connected to the PD but is connected to the output terminal of the PD current adjustment unit 12′. Furthermore, the transistor TR7 of the write power level current subtraction unit 10 is not directly connected to PD but is connected to the input terminal of the amplifier 31. The D/A converter 4 is connected to the non-inverted input terminal of the amplifier 31 through a resistor R62 and is also connected to the reversible input terminal of the amplifier 51 through the resistor R60. In Fig. 5, the embodiment in which a positive and negative bipolar power source is used is illustrated. However, in the present embodiment, a monopolar power source is used. For example, the power source voltages are 12 v (V CC ), 10 V (V AA ), 5 V (V CT ), 5 V (V DD ) and 0 V (V EE ). V CT corresponds to the ground level in Fig. 5. The output voltage range of the D/A converters 4, 7 and 14 is ,between V EE and V AA . Since a monopolar power source is used, resistors R59 and R60, R63 and R64, and R69 and R70 of resistor networks 50, 57 and 59 are additionally provided. The resistance value of the resistor R59 is equal to that of the resistor R60. This relationship also applies to the resistors R63 and R64, and R69 and R70. Moreover, since the monopolar power source is used, the internal circuit of the level shift unit 11′ is different from that shown in Fig. 5, but since the operation principle is the same as in Fig. 5, an explanation thereof is omitted. Other circuit arrangements are the same as in the circuit shown in Fig. 5. The operations of the control circuit shown in Fig., 7 will now be described with reference to the flow chart of Fig. 8. Step 100 (S100) MPU 21 turns ON the analog switch 53, whereby a capacitor C1 connected in parallel to the amplifier 31 is by-passed from the amplifier 31 and the amplifier 31 is caused to act as a voltage follower. Namely, the voltage applied to the non-inverted input terminal of the amplifier 31 is applied to the transistor TR1 through the amplifier 31. Step 101 (S101) MPU 21 turns OFF the analog switch 55, whereby the output of the D/A converter 4 is applied to the noninverted input terminal of the amplifier 31 through the resistor R62 of the resistance network 57. Step 102 (S102) The read output data of the D/A converter 4 is initially set at zero. Step 103 (S103) The D/A converter 4 applies the analog output voltage based on the read output data to the noninverted input terminal of the amplifier 31. Since the amplifier 31 is in the state as the voltage follower, the applied analog voltage is applied to the gate of the transistor TR1. Accordingly, the transistor TR1 is driven by the analog output voltage from the D/A converter 4 and the LD is caused to emit laser beams in the power level corresponding to the analog output voltage from the D/A converter 4. Step 104 (S104) The light emitted from LD is detected by the PD, and the detected value is converted to a digital quantity by the A/D converter 16 and is supplied to the MPU 21. Steps 105 and 106 (S105 and S106) The MPU 21 determines whether or not the A/D-converted value of PD has reached the read power level. If the detected value of PD has not reached the read power level, 1 is added to the read data of the D/A converter 4 and the routine returns to step S103. The operations of steps S103 through S106 are repeated until the detected value of the PD reaches the read power level. The foregoing operations are the same as the above-mentioned operations of steps S002 through S006. In short, the read power level is determined by the foregoing operations. Step 110 (S110) When the detected value of the PD arrives at the read power level, the MPU 21 applies an output to the AND gate of the level shift unit 11′ such that the write data signal W/RD is turned ON and the write gate signal W/RG is turned ON, and the transistor TR2 of the write power level current adjustment unit 6 and the transistor TR7 of the write power level setting unit are turned ON through the level shift unit 11′, whereby the state is attained where the LD can emit laser beams to the write power level through the transistor TR2. Note that a read power level reference value determined above is supplied to the non-inverted input terminal of the amplifier 31. Step 111 (S111) The MPU 21 sets an initial write data, i.e. zero, to the D/A converter 7. Step 112 (S112) The analog voltage based on the write output data is applied to the gate of the transistor TR4 of the power level setting unit 8 through the D/A converter 7. The current corresponding to the voltage applied to the gate of the transistor TR4 flows through the LD, the transistor TR2, the transistor TR4, and the resistor R5 to cause the LD to emit laser beams at a level exceeding the read power level. Step 113 (S113) The light emitted from the LD is detected by the PD, and the detected value is converted by the A/D converter 16 and supplied to MPU 21. The transistor TR7 in the write power level current subtraction unit 10 is not directly connected to the PD and the A/D converter 16 makes the A/D conversion of the reading of the PD where subtraction of the current is not performed. Steps 114 and 115 (S114 and S115) The MPU 21 determines whether or not the detected value of PD has reached the write power level. If the detected value of PD has not reached the write power level, 1 is added to the write out data of the D/A converter 7 and the routine returns to step S112. The operations of steps S112 through S115 are repeated until the detected value arrives at the write power level. The foregoing operations of steps S110 through S115 are substantially the same as the above-mentioned operations of steps S010 through S015. By these operations, a write power level reference value is determined and the determined write power level reference value is output from the D/A converter 7. Step 120 (S120) The MPU 21 turns OFF the write gate signal W/RG and turns OFF the write data signal W/RD to deenergize the write power level current adjustment unit 6 and write power level setting unit 17 through the level shift 11′, and therefore, the LD is not allowed to emit laser beams at the write power level but is caused to emit laser beams at the reference read power level given to the amplifier 31 from the D/A converter 4. Steps 121 through 123 (S121 through S123) MPU 21 drives the D/A converter 7 so that the output value of the D/A converter 4 is at the read power level. Furthermore, the analog switch 55 is turned ON by the MPU 21 to drop the voltage of the non-inverted input terminal of the amplifier 31 to the level V CT . On the other hand, the analog switch 53 is turned OFF to bring the capacitor C1 connected in parallel to the amplifier 31 into the operation-possible state, whereby the APC circuit is actuated. The operations of the PD current adjustment unit 12′, balancing circuit 50, and read power level detection unit 3′, which constitute the APC circuit, will now be described. The reference value of the read power level is applied to the inverted input terminal of the amplifier 51 through the resistor R60 from the D/A converter 4. On the other hand, the detected value of the PD is applied to the balancing circuit 50 through the PD current adjustment unit 12′. The balancing circuit 50 acts so that when the reference value from the D/A converter 4 reaches agreement with the detected value of the PD, the output is reduced to zero when balancing. The output from the balancing circuit 50 is applied to the read power level current adjustment unit 5 through the read power level detection unit 3′ to automatically adjust LD at the reference read power level. Step 124 (S124) The MPU 21 energizes the write power level current adjustment unit 6 again through the level shift unit 11′, whereby the LD is caused to emit laser beams at the reference write power level determined at steps S112 through S115 and output from the D/A converter 7. It must be noted that the present embodiment is different from the above-mentioned embodiment in that, at this point, the APC circuit functions. Namely, since the APC circuit performs the APC function at the read power level, if the LD emits laser beams at the write power level, the APC circuit reduces the emission level to the read power level, with the result that the output level of the LD is reduced, irrespective of the write mode. Steps 130 through 134 (S130 through S134) The MPU 21 sequentially renews the quantity of the superimposing write power level to be subtracted from the reading of the PD through the D/A converter 14 from an output of the balancing circuit 50. The reading of the PD after subtraction of the superimposed write power level is A/D-converted by the A/D converter 16, and the foregoing operations are repeated until the value obtained by the conversion is restored to the read power level. By detecting the restoration to the read power level, a reference value of the subtraction value at the D/A converter 14 is determined. Step 135 (S135) The write circuits 6 and 10 are deenergized through the level shift unit 11′. By the foregoing operations, the reference read power level value, reference write power level value and reference current subtraction value are automatically determined, and these values are output from the D/A converters 4, 7 and 14, respectively. The present embodiment shown in Figs. 7, 8a and 8b will now be compared with the embodiment shown in Figs. 5, 6a and 6b, with reference to the characteristic diagram of Fig. 2. In the embodiment shown in Fig. 5, for example, when the read current IRD corresponding to the read power level P RD of 1.0 mW is 55 mA and the write current I WR corresponding to the write power level P WR of 10 mW is 75 mA, the D/A converter 4 outputs a voltage corresponding to 55 mA and the D/A converter 7 outputs a voltage corresponding to 75 mA. On the other hand, in the present embodiment, of the curve CV shown in Fig. 2, the portion of a gentle inclination which is not used for the read/write emission is omitted because the portion is not utilized for setting the D/A converters. Namely, in the present embodiment, if the reference current I₀ is 50 mA, a voltage corresponding to about 5 mA is output from the D/A converter 4 and a voltage corresponding to about 25 mA is output from the D/A converter 7. Therefore, in anticipation of a margin, the full span of the D/A converter 4 is adjusted to the quantity corresponding to 10 mA and full span of the D/A converter 7 is adjusted to the quantity corresponding to 40 mA. In contrast, in the embodiment shown in Fig. 5, the full span of the D/A converter 4 should be adjusted to the quantity corresponding to 40 mA and full span should be adjusted to the quantity corresponding to 100 mA, if D/A converters having the same bit length are used. Therefore, in the present embodiment shown in Fig. 7, the resolving power per bit is improved to 1/4 in the D/A converter 4 and to 2/5 in the D/A converter 7. Accordingly, precise control of the read power level is especially improved in the present embodiment. In the above embodiments, a laser diode is used as the light emitting element and a photodiode is used as the light sensing element. However, other types of light emitting elements and light sensing elements can be utilised.

Claims: 1. A light control circuit of an optical disc system having an optical disc for storing data, a light emitting element (LD) for writing data to and reading data from the optical disc, and a light sensing element (PD) for sensing light from the light emitting element; characterised by light control means (2,3,5) for energising the light emitting element and for controlling the light output of the light emitting element at a first predetermined level sufficient for reading data from the optical disc in response to a signal from the light sensing element; means (6,8) for superimposed energisation of the light emitting element, in addition to the energisation by the light output controlling means, at a second predetermined level sufficient for writing data to the optical disc, when data are to be written to the optical disc; and subtracting means (9,10) operable synchronously with the superimposed energisation means, for subtracting a third predetermined level corresponding to the electrical power supplied by the superimposed energisation means to the light emitting element from the signal of the light sensing element. 2. A circuit according to claim 1, characterised in that the light emitting element comprises a laser diode (LD) having a substantially linear characteristic with respect to current flowing therethrough and intensity of light emitted therefrom; and in that the first and second predetermined levels are defined on the substantially linear characteristic and the substantially linear characteristic is biased from the origin. 3. A circuit according to claim 1 or claim 2, characterised in that the light sensing element comprises a photodiode (PD). 4. A circuit according to claim 3, characterised in that the laser diode (LD) and the photodiode (PD) are incorporated in a unit (1) with a hermetic seal. 5. A circuit according to any preceding claim, characterised in that the light control means comprises a circuit (2) for converting a current flowing through the light sensing element (PD) to a corresponding voltage, a circuit (3) which receives the voltage from the current-to-voltage converting circuit and the first predetermined level and determines the deviation between the voltage and the first predetermined level, and a circuit (5) which provides a current corresponding to the deviation from the deviation-determining circuit to the light emitting element (LD), so that the light emitting element emits light having an intensity corresponding to the first predetermined level. 6. A circuit according to claim 5, characterised in that the current-to-voltage converting circuit (2) comprises a plurality of switches (22) and a plurality of resistors (R10-R13), and a combination of closed and open states of the switches determines a predetermined converting ratio of the current-to-voltage conversion. 7. A circuit according to claim 5, characterised in that the current-to-voltage converting circuit (2) comprises a variable resistor (RV1). 8. A circuit according to any one of claims 5-7, characterised in that the current-providing circuit (5) comprises a transistor to a control electrode of which the deviation is fed and another electrode of which is connected to the light emitting element. 9. A circuit according to any one of claims 5-8, characterised in that the superimposed energisation means (6,8) comprises first and second transistors (TR2, TR3), control electrodes of which are energisable for a write operation, an electrode of each said transistor being commonly coupled to the corresponding electrode of the other transistor, another electrode of one transistor being connected to a common connection of a terminal of the light emitting element (LD) and the current-providing circuit (5), and another electrode of the other transistor being connected to another terminal of the light emitting element. 10. A circuit according to claim 9, characterised in that the superimposed energisation means (6,8) further comprises a third transistor (TR4) connected to the common connection of the first and second transistors (TR2,TR3) and a control electrode of which is supplied with a voltage corresponding to the second predetermined level. 11. A circuit according to any preceding claim, characterised in that the subtracting means (9,10) comprises fourth and fifth transistors (TR6,TR7) control electrodes of which are energisable for a write operation, an electrode of each said transistor being commonly coupled to the corresponding electrode of the other transistor, another electrode of one transistor being connected to a common connection of a terminal of the light sensing element (PD) and the current-to-voltage converting circuit (2), and another electrode of the other transistor being connected to a terminal of the light emitting element (LD). 12. A circuit according to claim 11, characterised in that the subtracting means (9,10) further comprises a sixth transistor (TR5) connected to the common connection of the fourth and fifth transistors (TR6,TR7), and a control electrode of which is supplied with a voltage corresponding to the third predetermined level. 13. A circuit according to any preceding claim, characterised by reference value setting means (21, 4, 16, 7, 14), operatively connected to the light control means (2,3,5), the superimposed energisation means (6,8), the subtracting means (9,10) and the light sensing element (PD), for continuously finding and determining the first to third predetermined levels in response to the characteristic of the light emitting element (LD) and setting the determined levels as said predetermined levels fed to the corresponding means at an adjustment time which is not a normal operation time, the predetermined levels being defined with respect to an origin of a light intensity/current characteristic of the light emitting element where current flowing through the light emitting element is substantially zero. 14. A circuit according to any one of claims 5-9, characterised by reference value setting means (21,4,16,7,14) operatively connected to the light control means (2,3,5), the superimposed energisation means (6,8), the subtracting means (9,10) and the light sensing element (PD), for continuously finding and determining the first to third predetermined levels in response to the characteristic of the light emitting element (LD) and setting the determined levels as said predetermined levels fed to the corresponding means at an adjustment time which is not a normal operation time; and balancing means (50), operatively connected between the current-to-voltage converting circuit (12′) and the deviation determining circuit (5), for outputting a balanced output between a predetermined level and an output from the current-to-voltage converting circuit at the first predetermined level; the deviation determining circuit being used for determining a first predetermined level during an adjustment time, the determined first predetermined level being supplied to the balancing means as a reference value and the deviation calculation circuit functioning as an amplifier in a normal operation, the predetermined levels being defined with respect to an origin of a light intensity/current characteristic of the light emitting element where the current flowing through the light emitting element is near to a current providing the first predetermined level. 15. A circuit according to claim 14, characterised in that the balancing means (50) includes a resistor (R58) connected to the current-to-voltage converting circuit (12′) and an amplifier (51) having a first input connected to the resistor and a second input having an inverted polarity relative to the first input for receiving the first predetermined level and an output connected to the deviation determining circuit (5). 16. A circuit according to any one of claims 13-15, characterised in that the reference value setting means includes a processor unit (21); an analog-to-digital (A/D) converter (16) for converting the voltage of the light sensing element to a digital value and feeding the digital value to the processor unit; and digital-to-analog (D/A) converters (4,7,14) for feeding the predetermined values corresponding to data from the processor unit to the corresponding means; and in that the processor unit finds and determines by feeding data to the D/A converters and by reading the voltage from the light sensing element, under a predetermined operation sequence. 17. A circuit according to claim 16, characterised in that the reference value setting means further includes switching means (13) for substantially disabling and restoring the light control means and switching means (15) for deenergising and energising the superimposed energisation means and the subtracting means. 18. A method for setting reference values of a light control circuit according to claim 13, characterised by the steps of substantially disabling the light control means (2,3,5); continuously changing data through a first D/A converter (4) until a read level of the light sensing element (PD) reaches the first predetermined level and determining a first reference value for the first predetermined level; energising the superimposed energisation means (6,8); continuously changing data through a second D/A converter (7) until a read level of the light sensing element reaches the second predetermined level and determining a second reference value for the second predetermined level; energising the subtracting means (9,10) and setting the second reference value to a third D/A converter (14) for initial data; continuously decreasing the data for outputting from the third D/A converter until a read level of the light sensing element reaches the first predetermined level and determining a third reference value for the third predetermined level; and restoring the operation of the light control means. 19. A method for setting reference values of a light control circuit according to claim 14, characterised by the steps of substantially disabling the deviation determining circuit (3) in the light control means; continuously changing data through a first D/A converter (4) until a read level of the light sensing element (PD) reaches the first predetermined level and determining a first reference value for the first predetermined level; energising the superimposed energisation means (6,8); continuously changing data through a second D/A converter (7) until a read level of the light sensing element reaches the second predetermined level and determining a second reference value for the second predetermined level; deenergising the superimposed energisation means and setting the second reference value to a third D/A converter (14) for initial data; restoring the light control means and energising the superimposed energisation means; continuously decreasing the data for outputting from the third D/A converter until a read level of the light sensing element reaches the first predetermined level land determining a third reference value for the third reference level, whereby the predetermined levels are defined with respect to said origin of the characteristic of the light emitting element.

Inventors: FUTAMATA, AKIO, MINAMI, AKIRA
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: G11B7
IPC codes: G11B7, G11B19