TEMPERATURE COMPENSATED CMOS TO ECL LOGIC LEVEL TRANSLATOR

Abstract: A CMOS to ECL interface circuit includes a pair of series connected complementary transistors (14, 16) having input CMOS logic levels applied to their gates and output ECL logic levels derived from the junction point of their source-drain paths. The transistors (14, 16) are connected between power supply terminals (VA, VB) which are coupled to the outputs of an OR-NOR gate (20) included in the same temperature environment as the ECL logic circuits serviced by the interface circuit. Thus, temperature compensation is achieved since the power supply applied to the power supply terminals (VA, VB) of the interface circuit automatically tracks variations in the ECL output logic level resulting from temperature variations.

Description: TEMPERATURE COMPENSATED CMOS TO ECL LOGIC LEVEL TRANSLATOR Technical Field This invention relates to CMOS to ECL interface circuits of the kind including: input means adapted to receive CMOS logic level signals; interfacing means coupled to said input means and adapted to translate said CMOS logic level signals to ECL logic level signals and including a pair of supply voltage terminals; and output means adapted to supply said ECL logic level signals to serviced ECL devices. Background Art To couple a CMOS circuit to an ECL circuit the difference between the output voltages from the one circuit and the input voltages .needed by the second circuit must be " generated by some form of interfacing circuit. The logic level "1" of a CMOS circuit will approach the power supply value, which may be about -3 volts, and the logic level "0" will be near the reference or ground level. On the other hand, the logic level "1" of an ECL circuit will approach -0.8 volts and the logic level "0" will approach -1.6 volts. If the interfacing circuit derives its power from the CMOS circuit any difference in temperature between the CMOS and the ECL circuit can cause a variance in the response level of the ECL circuit due to the shifts in electrical characteristics as a function of temperature. U.S. Patent No. 4,453,095 discloses a CMOS to ECL interface circuit for a five volt CMOS logic swing, including a CMOS inverter having an output coupled to the base electrode of an NPN transistor, which provides an ECL logic swing output at the emitter, which is coupled via a termination resistor to a voltage supply source. The U.S. Patent also discloses an interface circuit for a CMOS logic circuit having a two volt CMOS logic swing, including a CMOS inverter having an output connected to one input of a differential pair of bipolar transistors. The differential pair has an output connected to the base of a bipolar transistor whose emitter provides * the desired ECL output. U.S. Patent No. 4,533,842 discloses a logic level translator for converting TTL logic levels to ECL logic levels incorporating a temperature compensating circuit. The logic level translator includes a differential pair of bipolar transistors, the base electrode of one transistor of the pair being supplied with a threshold voltage. The threshold voltage is supplied by a bandgap reference voltage generator which utilizes resistors having positive and negative temperature coefficients, whereby the generated threshold voltage is rendered independent of temperature. Disclosure of the Invention It is an object of the present invention to provide a CMOS to ECL interface circuit of the kind specified, adapted to compensate for temperature variations. Therefore, according to the present invention, there is provided a CMOS to ECL interface circuit of the kind specified, characterized by ECL circuit means located in the same temperature environment as said serviced ECL logic devices and coupled to said pair of supply voltage terminals to provide supply voltages for said interfacing means, which supply voltages track the variations of ECL output logic level of said serviced ECL logic devices as a function of temperature. Brief Description of the Drawings One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of the preferred embodiment of the invention; and Fig. 2 is a table indicating the typical voltage conditions present at like labeled parts of the circuit of Fig. 1. Best Mode for Carrying Out the Invention Referring to Fig. 1, a CMOS logic device 10 is adapted to be connected to service ECL logic de¬ vices in a fan out fashion via an output terminal VQ. A CMOS logic circuit 12 is connected between a refer¬ ence potential VCC and a supply voltage VSS to provide at its output a CMOS logic level signal denoted VI, which signal has two logic states with voltage levels of 0 volts and -3.3 volts, respectively. An inter¬ facing circuit, comprised of complementary field effect transistors 14 and 16, which may be formed using discrete devices or as part of the CMOS logic device 10, receives the signal VI and translates the signal to corresponding ECL logic level signals. The signal VI is coupled to the gates of transistors 14 and 16, which transistors have their source-drain paths connected in series between a pair of supply voltage terminals VA and VB. The terminal VQ is connected to the junction point between the source- drain paths of the transistors 14, 16. In order to drive an ECL logic circuit the voltages appearing on the terminal V Q should, for the two logic states, have the values of -0.8 volts and -1.6 volts corresponding to the ECL "high" and "low" logic levels respectively. Because the voltage responses of the serviced ECL logic devices, coupled to the output Vg, vary somewhat as a function of temperature it is most desirable to have the voltages representing the logic levels vary in a directly proportional manner with the voltage responses of the serviced ECL logic circuits. In the present embodiment, this is accomplished by using one of the unused ECL logic gates that is exposed to the same temperature environment as the other ECL logic gates serviced by the CMOS device 10. Although various logic gates may be utilized to accomplish the same function, namely that of pro¬ viding an output voltage which varies as a direct function of temperature, an OR-NOR gate is shown in the preferred exemplary embodiment. In the preferred embodiment, the OR-NOR gate is provided with a reference (ground) terminal VCC and a terminal VEE for receiving a -5.2 volt supply voltage. Four transistors- of the NPN type, labeled Ql through Q4, form the OR-NOR gate and are connected such that the emitter of Q3, which is the NOR output, is connected to the terminal VA with the emitter of Q4, which is the OR output, being connected to the terminal VB. The emitters of transistors Ql and Q2 are connected by means of a 779 ohm resistor to the VEE supply. A reference potential source 22, having a value of -1.3 volts, is connected to the base of transistor Q2. The base of transistor Ql is connected by means of a 50 K ohm resistor to the terminal VEE. A 220 ohm biasing resistor connects the collector and base of transistor Ql and Q3, respectively, to the reference potential VCC. In a like manner a biasing resistor of 245 ohms connects the base of transistor Q4 and the collector of transistor Q2 to the reference potential VCC. Two 510 ohm resistors are connected, one each, to the conductors connected to the terminals VA and VB at one end and at the other end to a -2 volt power supply. Two 1 microfarad capacitors are also connected, one each, between the conductors and ground. In operation, the transistor Q3 is biased ON with a one diode voltage drop appearing between its base and its emitter which thereby places a voltage of approximately -0.8 volts at the terminal VA. The base of transistor Ql is held opened and is connected by a 50 K ohm resistor to the -5.2 volt supply VEE. The transistor Ql is maintained in an OFF condition. Transistor Q3 is biased ON by the VREF supply of -1.3 volts which is more positive then the -5.2 volt VEE supply. With transistor Q2 ON, collector current through the 245 ohm resistor develops a potential of approximately -0.8 volts at the base of transistor Q4, thus turning Q4 on since it has a one diode voltage drop between its base and emitter. The emitter current of transistor Q4, flowing through the 510 ohm resistor, causes a voltage of -1.6 volts to appear at the terminal VB. Fig. 2 is a chart which lists the voltage levels appearing at like designated locations on the circuit of Fig. 1. V1H corresponds to the "high" logic level of the signal appearing at the output of the CMOS logic circuit 12. V1L corresponds to the "low" logic level. In a like manner, the voltage levels VOH and VOL correspond to the "high" and "low" voltage levels on the output of V Q . The use of the complementary outputs of the unused ECL logic NOR circuit to provide the voltages VA and VB alleviates the temperature tracking problem as VA and VB will automatically track the variations of the ECL output logic level as a function of temperature.

Claims: CLAIMS : 1. A CMOS to ECL interface circuit, including: input means adapted to receive CMOS logic level signals; interfacing means (14, 16) coupled to said inputs means and adapted to translate said CMOS logic level signals to ECL ' logic level signals and including a pair of supply voltage terminals (VA, VB) ; and output means adapted to supply said ECL logic level signals to serviced ECL devices, characterized by ECL circuit means (20) located in the same temperature environment as said serviced ECL logic devices and coupled to said pair of supply voltage- terminals (VA, VB) to provide supply voltages for said interfacing means (14, 16), which supply voltages track the variations of ECL output logic level of said serviced ECL logic devices as a function of temperature. 2. A CMOS to ECL circuit according to claim 1, characterized in that said ECL circuit means (20) includes an OR-NOR gate (20) having first and second outputs connected respectively to said first and second supply voltage terminals (VA, VB) , to provide said supply voltages for said interfacing means (14, 16). 3. A CMOS to ECL interface circuit according to claim 2, characterized in that said first output is an OR output and is adapted to supply a low ECL logic level signal and said second output is a NOR output and is adapted to supply a high ECL logic level signal. 4. A CMOS to ECL interface circuit according to claim 3, characterized in that a pair of resistors are respectively coupled between said OR and NOR outputs and a source of supply potential. 5. A CMOS to ECL interface circuit according to claim 4, characterized in that a pair of capacitors are connected between ground and said pair of supply voltage terminals (VA, VB) . 6. A CMOS to ECL interface circuit according to claim 1, characterized in that said interfacing means includes a pair of complementary field effect transistors (14, 16) having their source- drain paths connected in series between said supply voltage terminals (VA, VB), in that the gate electrodes of said pair of transistors (14, 16) are connected in common to said input means and in that the junction point between the source-drain paths of said pair of transistors (14, 16) is connected to said output means.

Inventors: LAUFFER DONALD KEITH, SANWO IKUO JIMMY, LAUFFER, DONALD, KEITH, SANWO, IKUO, JIMMY
Applicants: NCR CO, NCR CORPORATION
Application year: 1986
Main classification: H03K19
IPC codes: H01L27, H03K19