THERMAL ETCHING OF A COMPOUND SEMICONDUCTOR

Abstract: A process for thermally etching a CaAs substrate prior to molecular beam epitaxy comprises the steps of: heating the GaAs substrate to above 750°C.- at which temperature both Ga and As are evaporated from the GaAs substrate- whilst irradiating it with an As molecular beam, thereby removing contamination adhering to the surface of the GaAs substrate. As the substrate evaporates it carries with it the contamina­ tion. The process can be performed by an apparatus comprising a prechamber (2), in which the surface is evaporated, connected to a growth chamber (6), in which an epitaxial layer is grown.

Description: The present invention relates to a process for carrying out a thermal-etching treatment of a GaAs semiconductor substrate to be used in molecular beam epitaxy. More particularly, it relates to a process for the thermal removal of surface carbon, carbide or other carbon compounds from a substrate. A molecular beam epitaxy (MBE) technique with compound semiconductors such as GaAs is often used for the fabrication of high speed devices such as high electron mobility transistors (HEMT), and it is well known that a carrier depletion layer is formed around an interrupted growth interface and a substrate epitaxial interface. Such a depletion layer sometimes degrades the performance of the devices. Therefore, cleaning of the substrate in the MBE chamber prior to the epitaxial growth process is very important to an improvement of the quality of the epitaxial films. The major contaminations on a GaAs substrate after chemical etching and loading in to an MBE chamber are oxygen and carbon from carbon dioxide (CO₂) or hydrocarbons. This is discussed in an article entitled "Interface and doping profile characteristics with molecular-beam epitaxy of GaAs:GaAs voltage varactor", which appeared in J. Appl. Phys. 45(4) April, 1974. Oxygen can be thermally removed by heating the substrates to about 530°C. However, this does not remove other contamination especially carbon, carbides or other carbon compounds from GaAs substrate. Further, when a semiconductor crystalline layer is epitaxially formed on a surface of a GaAs substrate in a state wherein carbon atoms, and other contamination is present the carbon and other contamination act as acceptors so that an interfacial level between the GaAs substrate and the semiconductor crystalline layer is formed. To avoid the effect of the formation of the interfacial level, the formation of thick buffer layer is necessary. This takes a long time and thus throughput decreases. US-A-3992233 describes a process for thermal-etching treatment of a GaAs substrate comprising heating the GaAs substrate in a treatment chamber whilst irradiating a surface of the GaAs substrate with an As molecular beam to remove contamination adhering to the GaAs substrate by evaporating a part of it and then subjecting the substrate to further processing steps without it leaving the treatment chamber. In this example the further processing that takes place is the deposition of alternate monologues of caesium and oxygen to form a photocathode. The substrate must be heated to a temperature above 620°C and in the particular example is heated to a temperature of 700°C. According to this invention such a process is characterised in that the substrate is heated to a temperature higher than 750°C, at which temperature both Ga and As evaporate from the GaAs substrate, and in that the further processing steps consist of epitaxial growth by molecular beam epitaxy on the cleaned surface of the substrate. The present invention provides a process for thermal-etching treatment of a GaAs substrate for use in molecular beam epitaxy wherein carbon is thermally removed and the surface defect density between the substrate and an epitaxial layer is removed. An advantage of the present invention is that it enables only a thin buffer layer to be provided on which a semiconductor crystalline layer having good properties and less defects is subsequently formed and this increases production throughput. A particular example of the present invention will now be described with reference to the accompanying drawings; in which:- Figure 1 is a diagram illustrating evaporation As from surface of a GaAs compound; Figure 2 is a graph showing the dependence of the thermal etching rate on the substrate temperature at an As₄ pressure; Figure 3 is a graph showing the dependence of the amount of the carrier depletion on the etching depth; Figure 4 is a graph showing the dependence of the carbon concentration on the depth removed by the thermal etching at 720°C and 750°C; Figure 5 is a diagram illustrating how the surface contamination is removed by evaporating a part of the GaAs surface; Figure 6 is a diagram of apparatus suitable for the process; Figure 7 is a cross-section through a wafer produced by the present invention; and, Figure 8 is a graph showing the mobility and sheet concentration of a two dimensional electron gas (2DEG) as a function of the thickness of a GaAs buffer layer. In order to find the dependence of the thermal etching rate on a GaAs substrate with the arsenic pressure, the present inventor experimented as follows. The (100)GaAs substrate was degreased in trichloroethylene, and rinsed in sequence with methanol and deionized water. The substrate was then chemically etched in H₂SO₄:H₂O:H₂O₂, rinsed with deionized water, dried with dry nitrogen gas, and mounted on an Mo block using solder. The thermal etching was carried out in the growth chamber at a substrate temperature of 720°C, 750°C, and 780°C with an As₄ pressure of 2x10⁻³Pa (1.5 x 10⁻⁵ Torr). The substrate temperature was measured by a calibrated infrared pyrometer. As shown in Figure 2, the etching rates were remarkably increased in accordance with the substrate temperature; i.e., approximately 2 nm/min (20Å/min) at 720°C, 6nm/min (60Å/min) at 750°C, and 18nm/min (180Å/min) at 780°C, with an As₄ pressure of 2x10⁻³Pa (1.5 x 10⁻⁵) Torr. It can be seen that the etching rate remarkably increases at a temperature above 750°C. The inventor also found that the increment of the etching rate as a function of the temperature is almost the same as the vapour pressure of the Ga. The present inventor then studied the dependence of the carrier depletion on the etching depth. Si doped n-GaAs layer was grown on an Si doped GaAs substrate at a rate of 1 µm/h at a substrate temperature of 640°C. The doping levels of the epitaxial layer and the substrate were 8 x 10¹⁶ cm⁻³. The thickness of the epitaxial layer was approximately 1 µm. The depth of etching was varied from 0µm to 0.1µm (0 Å to 1000 Å) by changing the etching time at the temperatures of 720°C and 750°C. The dependence of the carrier depletion on the etching depth is also shown in Fig. 3. The possibilities of the origin of the carrier depletion are the trap formation and the carrier compensation caused by the As evaporation loss and/or the contamination on the initial substrate surface. DLTS measurement was performed to detect deep trap levels near the thermally etched and non-etched interfaces. The total concentration of the trap levels of non-etched interfaces obtained was less than 1 x 10¹⁰ cm⁻², which is much less than the amount of the carrier depletion (10¹² cm⁻²). Therefore, the deep traps may not be the origin of the carrier depletion at the interface. The concentration of the remaining carbon at the substrate-epitaxial layer was detected by SIMS measurement using Cs⁺ bombardment. Figure 4 show the dependence of the carbon concentration on the depth removed by the thermal etching at 720°C and 750°C. The concentration of the carbon at the interface without thermal etching was 5.5 x 10¹³ cm⁻². The carbon concentration was reduced to 5.3 x 10¹² cm⁻² by the etching at 750°C. On the other hand, the concentration of the carbon contamination did not depend on the etching depth in the case of a low etching temperature of 720°C. Even though the substrate was etched to 0.1µm (1,000 Å) at the temperature of 720°C, the amount of remaining carbon atoms was 8.3 x 10¹³ cm⁻². The above results show that there is good correspondence between the concentration of the carbon contamination detected by the SIMS measurement (shown in Fig. 4) and the amount of the carrier depletion measured by the C-V technique (shown in Fig. 3). Therefore, the carbon contamination remaining on the substrate is considered to be the main cause of the formation of the carrier depletion. The carbon is present even though the substrate is carefully etched with H₂SO₄ etchant and rinsed with deionized water. Since carbon is a shallow acceptor in GaAs, it will compensate donors. When a GaAs substrate is thermally etched above 750°C, carbon (CO₂ , C n H 2n+1 , etc.) contamination on the substrate surface may be removed by evaporating Ga and/or GaAs molecules, as shown in Fig. 5. The thermal etching technique was applied to the cleaning the GaAs substrate in the growth of selectively doped (SD) GaAs/N-Al 0.3 Ga 0.7 As heterostructures of Figure 7 by using an apparatus shown in Figure 6. In Figure 6, a GaAs substrate 10 adhered to a 25 molybdenum (Mo) block (not shown)by an Indium (In) solder is introduced into a substrate exchanging chamber 1. Then, the chamber 1 is degassed to 1.3x10⁻⁵Pa to 1.3x10⁻⁴Pa (10⁻⁷ to 10⁻⁸ Torr) and a gate valve 12 is opened. The GaAs substrate 10 is then moved to a prechamber 2, for preparing the substrate, maintained at a pressure of approximately 2.7x10⁻⁷Pa (2 x 10⁻⁹ Torr) and provided with an As molecular beam source 5. When the As molecular beam is irradiated the degassed pressure in the prechamber 2 is lowered to 1.3x10⁻⁵Pa (10⁻⁷ Torr). The GaAs substrate 10 on a substrate holder 4, which can be heated, is heated at approximately 750°C for about 3 minutes while the As molecular beam is irradiated, in which the As pressure is 2x10⁻³Pa (1.5 x 10-5 Torr), and subsequently, the temperature is lowered at a rate of 20°C/min to about 300°C so that the GaAs substrate 10 can be moved to a growth chamber 6. The reason for As molecular beam irradiation is to compensate for the eliminated arsenic atoms caused by the heat treatment 750°C or more. In the growth chamber 6, a GaAs/AlGaAs semiconductor epitaxial layer is grown on the GaAs substrate 10 at about 680°C. Reference numerals 7, 8 and 9 denote a substrate holder, an As molecular beam source, and a Ga molecular beam source, respectively. Figure 7 shows a cross-sectional view of an wafer produced by a process according to the present invention. As shown in Figure 7, a 0.3 µm thick GaAs buffer layer 22 is formed on a semi-insulating GaAs substrate 21. Then, a 6nm (60 Å) thick Al 0.3 Ga 0.7 As spacer layer 23 is formed on the GaAs buffer layer 22, and subsequently, a 90nm (900Å) Si-doped (1 x 10⁻¹⁸ cm⁻³) n - type Al 0.3 Ga 0.7 As electron carrier layer 24 and a 20nm (200 Å) Si-doped (1 x 10¹⁸ cm⁻³) n-type GaAs electrode contact layer 25 are formed on the spacer layer 23. Another example of the embodiment in the thermal etching of the present invention is that the GaAs substrate 10 is heated at 780°C for about 1.5 minutes under 2x10⁻³Pa (1.5 x 10⁻⁵) Torr As pressure. Furthermore, another example is that the GaAs substrate 10 is heated at 770°C for about 9 minutes under 6.7x10⁻³Pa (5 x 10⁻⁵ Torr) As pressure. Figure 8 is a graph showing the mobility (µ) and sheet concentration (n s ) of two dimensional electron gas (2 DEG) obtained by Hall measurements at 77k as a function of the thickness of the GaAs buffer layer. The two dimensional electron gases (2 DEG) is generated at the interface between the GaAs buffer layer 22 and the AlGaAs spacer layer 23. Moreover, the mobility (µ) and the sheet concentration (n s ) of 2 DEG of the sample grown on a non-etched substrate provided with a 0.6 µm GaAs buffer layer produced by a conventional process are also shown in Figure 8 (open circles). As the thickness of the GaAs buffer layer decreased to less than 0.1 µm, the quality of the 2 DEG was extremely degraded for the thermally etched (present invention) and the non-etched (conventional process) substrate. For a buffer layer in the range of from 0.1 µm to 0.4 µm, however, it is clear that the thermal etching of the substrate improved the quality of the 2 DEG in SD heterostructures. The mobility and the sheet concentration of the 2 DEG with the GaAs buffer layer having a thickness of 0.2 µm grown on the thermally etched substrate according to the present invention were 90,000 cm²/Vs and 5.0 x 10¹¹ cm⁻² at 77k. On the other hand, the values of the 2 DEG grown on the non-etched substrate according to a conventional process were approximately 60,000 cm²/Vs and 4.0 x 10¹¹ cm⁻² at 77k. The main cause of the reduction of the 2 DEG with a thin buffer layer from 0.1 to 0.4 µm may be the carrier depletion at the substrate-epitaxial interface. The main cause of the carrier depletion is considered to be the carbon (CO₂, C n H 2n+1 ) contamination existing on the initial growth surface. Thus it is considered that the thermal etching process according to the present invention caused a large improvement in the quality of the 2 DEG in SD GaAs/N - Al 0.3 Ga 0.7 As heterostructures with a very thin GaAs buffer layer (0.2 µm).

Claims: A process for thermal-etching treatment of a GaAs substrate for use in a molecular beam epitaxy, comprising heating the GaAs substrate in a treatment chamber whilst irradiating a surface of the GaAs substrate with an As molecular beam to remove contamination adhering to the GaAs substrate by evaporating a part of it and then subjecting the substrate to further processing steps without it leaving the treatment chamber; characterised in that the substrate is heated to a temperature higher than 750°C, at which temperature both Ga and As evaporate from the GaAs substrate, and in that the further processing steps consist of epitaxial growth by molecular beam expitaxy on the cleaned surface of the substrate. A process according to claim 1, wherein the As molecular beam is irradiated at an As beam intensity of 2x10⁻³Pa (1.5 x 10⁻⁵ Torr). A process according to claim 1 or 2, wherein the contamination includes carbon dioxide or carbon hydride. A process according to any one of the preceding claims, wherein after removal of the contamination a thin GaAs buffer layer is formed on the substrate.

Inventors: SAITO, JUNJI
Applicants: FUJITSU LIMITED
Application year: 1986
Main classification: H01L21
IPC codes: C30B23, H01L29, H01L21