DIGITAL AUTOMATIC FLIGHT CONTROL SYSTEM WITH DISPARATE FUNCTION MONITORING

Abstract: A channel of an automatic flight control system utilises dual identical digital processors (21; 22). Active task modules (56,57,58;76,77,78) and monitor modules (59,60,61;79,80,81) therefor are included in the processors. The active task modules and the monitor modules are arranged so that an active task module in one processor has a corresponding monitor module in the other processor where the corresponding modules perform disparate functionality over disjoint computation paths with respect to each other. The monitor module tests to determine if the aircraft is performing in a manner prohibited by the functionality controlled by the associated task module.

Description: This invention relates to automatic flight control systems utilising digital flight control computers, particularly with respect to reducing safety hazards resulting from generic design errors in the software or the computer processor(s). Automatic flight control systems are constrained by U.S. Federal Air Regulations to provide safe control of the aircraft throughout the regimes in which the automatic flight control system is utilised. Any failure condition which prevents continued safe flight and landing must be extremely improbable. Present day regulations require a probability of less than 10⁻⁹ failures per hour for flight-critical components. A flight-critical portion of an automatic flight control system is such that the failure thereof will endanger the lives of the persons aboard the aircraft. For example, components of an automatic flight control system utilised in automatically landing the aircraft may be designated as flight-critical, whereas certain components utilised during cruise control may be designated as non-critical. Generally, the safety level of components of the system is determined by analysis and testing procedures familiar to those skilled in the art. Such procedures are often referred to as verification and validation. Automatic flight control systems utilising analogue computers and components had been prevalent in the art wherein it had been completely practical to perform the verification and validation procedures to certify conformance of such systems to the safety requirements of the U.S. Federal Air Regulations. Traditionally, such analogue systems implemented independent control of the aircraft axes by utilising, for example, independent pitch and roll control channels. Certification analysis was facilitated by the axis independent control. A known technique for enhancing automatic flight control system reliability is that of dual redundancy. Dual redundancy is the utilisation of two identical channels with cross-channel monitoring to detect a failure in one of the channels. Although such systems are effective against random faults which affect only one channel, cross-channel monitoring does not provide effective detection of generic faults. A generic fault is defined as a fault that is inadvertently designed into a component such that all components generically have this fault and respond in a defective manner. When identical components having a generic fault are in respective redundant channels, the cross-channel monitoring detects the same, although erroneous, output from both channels and therefore does not detect the error. Such generic faults are also denoted as design errors. In present day technology, stored program digital computers are supplanting the analogue computer of the prior art technology. It has generally been found that a digital computer including the hardware and software is of such complexity that the verification and validation analysis for certification in accordance with U.S. Federal Air Regulations is exceedingly more time consuming, expensive and difficult than with the analogue computer. The level of complexity and sophistication of the digital technology is increasing to the point where analysis and proof of certification to the stringent safety requirements is approaching impossibility. To further exacerbate the difficulty, current day digital flight control computers perform all of the computations for all of the control axes of the aircraft in the same computer unlike in the analogue computer approach where the control of the aircraft axes was provided by separate respective channels. A further problem engendered by the introduction of the programmed digital computer technology into automatic flight control systems is that the extensive software required is susceptible to generic design errors. An error can arise in the definition phase of software preparation as well as in the coding thereof. A generic design error can occur in the attendant assembler or compiler as well as in the micro-code for the processor. For example, an error in a microcircuit chip mask for the micro-code, as well as for the processor or associated components can propagate into all of the systems constructed using the mask. In the prior art, in order to satisfy the stringent safety requirements of the U.S. Federal Air Regulations, exhaustive verification and validation was often utilised to prove the absence of such generic design faults in the software as well as in the processor hardware to the required level. It will be appreciated that such verification and validation procedures are exceedingly time consuming and expensive. For the reasons given above, it will be appreciated that redundant identical channels of digital data processing with cross-channel monitoring may not detect hardware and software generic design errors so that reliability can be certified to the required level. Furthermore, with the increasingly complex and sophisticated digital processing being incorporated into automatic flight control systems, it is approaching impossibility to prove by analysis the absence of such generic errors to the levels required by the U.S. Federal Air Regulations. It will be appreciated that in a digital flight control channel, including a Flight Control Computer, sensors, and Input/Output (I/O) apparatus, all of the processing for all aircraft axes is performed in the same computer and critical as well as non-critical functions are controlled by the same channel. Thus, the entire channel must be certified in accordance with the "extremely improbable" rule discussed above with respect to flight-critical aspects of the system. Thus, even those portions of the system utilised for performing non-critical functions must be certified to the same level as the critical portions since the non-critical portions are within the same computation complex as the critical portions. In order to overcome these problems, the automatic flight control technology has only recently advanced to the concept of dissimilar redundancy. In dissimilar redundancy, dissimilar processors perform identical tasks utilising dissimilar software with cross-channel monitoring to detect failures. With this approach, a generic error designed into the processor or software of one channel will not exist in the processor or software of the other channel and the cross-channel monitoring will detect the discrepancy. In this prior art arrangement, the redundant computers are generally dissimilar in hardware and architecture, utilise dissimilar software, compilers or assemblers and often utilise different hardware and software design teams. In this prior art arrangement, each dissimilar computer requires its own full set of software for performing all of the flight control and flight director functions performed by the system, as well as requiring its own assembler or compiler and ancillary development apparatus and personnel. Such software and the like in modern sophisticated jet transports tend to be exceedingly extensive and consequently expensive. Multiple complete sets of dissimilar software for a system adds undesirably to the cost thereof. Additionally, in such systems, design changes to software or processor may result in a significant impact on the safety level of the system. The present invention is defined in the appended claims and the above disadvantages of the prior art are obviated by an automatic flight control system responsive to sensors that provide sensor signals in accordance with flight conditions experienced by the aircraft, the aircraft having control means such as aerodynamic control surfaces, throttle controls and the like for controlling the flight conditons of the aircraft. Each channel of the automatic flight control system comprises a digital computer having a computer input responsive to the sensor signals, a program memory and a computer output. A program is stored in the program memory of the computer, the program comprising a plurality of first program segments which are executed by the computer for performing a plurality of tasks that generate command signals for controlling the aircraft flight conditions. The program further includes a plurality of second program segments associated with the first program segments, respectively, for monitoring the performance of the first program segments, respectively, each second program segment performing a mutually disparate task over mutually disjoint computation paths with respect to the associated first program segment. Two, preferably similar, processors are utilised in each channel where a first program segment is executed by one of the processors and the corresponding second program segment is executed by the other processor. The disparate task performed by a second program segment comprises a plurality of tests to determine if the aircraft is performing in a manner in which it would not be permitted to perform in accordance with the function controlled by the corresponding first program segment. The automatic flight control system channel further comprises means for controlling repeated iterations of the program and means for assuring that each of the second program segments is executed by the computer during each iteration of the program. An automatic flight control system in accordance with the invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a schematic block diagram illustrating a channel of the automatic flight control system implemented in accordance with the present invention, Figure 2 is a schematic block diagram illustrating details of processor A of Figure 1, and Figure 3 is a schematic block diagram illustrating details of processor B of Figure 1. Referring to Figure 1, a block schematic diagram of a single channel 10 of the automatic flight control system is illustrated. The complete system may include two such channels in a dual channel configuration. In a single channel arrangement, the automatic flight control system is fail passive and the dual channel arrangement provides fail operative performance. The channel 10 includes a set of analogue sensors 11 comprising the required complement of sensors that provide analogue signals for use in controlling the aircraft. The set of analogue sensors 11 includes conventional attitude, rate and acceleration sensors as well as other devices such as control wheel force sensors which are conventionally utilised in modern jet transports. The sensors 11 may include such devices as directional and vertical gyroscopes, rate gyrocopes and accelerometers. The sensor set 11 may additionally include conventional radio guidance equipment such as VOR, ILS and MLS systems as well as navigational systems for providing steering data. The sensor set 11 may also include inputs from the aircraft control surface position transducers as well as engine sensors and feedback signals from the aircraft servos and inputs from such devices as radio altimiters and the like. The channel 10 also includes a complement of digital sensors 12. The digital sensors 12 may include conventional attitude and heading reference sensors as well as a conventional digital air data computer for providing such parameters as barometric altitude, total air temperature, air speed, dynamic pressure and the like. The digital sensors 12 may also include other equipment such as a digital DME receiver as well as discrete inputs from, for example, the panel push buttons. The outputs of the analogue sensors 11 are applied to a conventional multiplexer 13 via an electrical data path 14. The output of the multiplexer 13 is applied to conventional analogue-to-digital converter 15 and 16. The outputs of the digital sensors 12 are applied via an electrical data path 17 to digital data receivers 18 which include buffers for entering the digital data into the system. The analogue signals from the analogue sensors 11 are applied via the analogue-to-digital converters 15 and 16 and respective electrical data paths 19 and 20 to the input ports of respective digital computers 21 and 22. The computers 21 and 22 are denoted as processor A and processor B, respectively. The processors 21 and 22 provide multiplexer control signals on buses 23 and 24, respectively, to the multiplexer 13 for controlling the multiplexer 13 to individually select analogue sensor signals for inputting into the respective processors 21 and 22 in accordance with the processor requirements as controlled by the programs stored therein. The digital input data from the digital sensors 12 are applied via the digital data receivers and buffers 18 and an electrical data path 25 to a further data input port of the processors 21. The digital data on the data path 25 is also applied to a further data input port of the processor 22. The processor 21 provides a receiver control signal on a bus 26 to the digital data receivers and buffers for selectively inputting the appropriate digital data from the sensors 12 into the processors 21 and 22 in accordance with the program flow of the processor 21. The control signals on the bus 26 controls the receivers and buffers 18 so as to appropriately sequence the data from the digital sensors 12 to the processors 21 and 22. The digital processors 21 and 22 are preferably identical and of conventional architecture, and are of the general purpose, medium scale design, a variety of which are commercially procurable in specifically constructed computers for airborne analysis and control for automatic flight control and flight director applications. Preferably, an FZ-800 digital flight control computer commercially procurable from the Avionics Division of the Aerospace and Marine Group of the Sperry Corporation may be utilised in implementing the system. The FZ-800 computer is based on the Zylog Z-8002 microprocessor. Further details with respect to the internal arrangement of the digital processors 21 and 22 and the programs stored therein will be discussed below with respect to ensuing figures. The processor 21 provides an output via a data path 27 to a servo driver control system 28. The servo driver control system 28 provides outputs to servos 29 via a servo cut-off relay switch 30. The servo driver control system 28 and the servos 29 may be of the conventional electrical torque motor and linkage type for control of the aircraft aileron, elevator, rudder and trim control surfaces as well as for providing control for the automatic throttle system. Alternatively, the servos and actuators may be of the conventional electro-mechanical or electro-hydraulic variety. The servo driver control 28 and servos 29 are schematically representative of the conventional complete three axis control apparatus for the aircraft control surfaces and automatic throttle system commonly utilised in modern air transports. Primarily, the processor 21 directly controls the servos of the system and is part of the servo loop. In this configuration, the servos 29 provide feedback signals as inputs (not shown) in the analogue sensor set 11 and the processor 21 drives the servos, so controlled, to null. Alternate servos utilised by the system may be of the self-contained, closed-loop configuration containing internal feedback loops. In both arrangements, the processor 21 provides a command signal to the servo drive control 28, which is configured to provide the appropriate drive format for the applicable servo configuration. The processor 21 also provides a servo enable signal on a bus 31 via an AND gate 32 to activate the servo cut-off switch 30. The processor 21 provides a servo disabling signal on the bus 31 in accordance with monitoring functions, to be described, resident in the processor 21. For reasons to be described, the processor 21 includes program segments which determine the certain blocks of software are repetitively executed. The processor 21 outputs A-processor monitor signal on a bus 33 in accordance with the continuous iterations of these software blocks. The processor monitor signal on the bus 33 is applied to a hardware monitor 34 which operates in conjunction with the processor monitor software resident in the processor 21. Such processor monitoring hardware and software may be implemented as disclosed in US-A-4,115,847. The output of the monitor 34 is applied as an input to the AND gate 32 for actuating the servo cut-off 30 in the event program blocks resident in the processor 21 fail to be executed repetitively. Although the preferred embodiment of the invention was described in terms of utilising the processor monitor system described in said US-A-4,115,847, other processor monitor systems may be utilised to the same effect to assure that program blocks resident in the processor 21 are repetitively executed. In a manner similar to that described above with respect to the processor 21, the processor 22 provides outputs 35, 39 and 40 which provide the functions described above with respect to the outputs 27,31 and 33, respectively, from the processor 21. Additionally, the processor 22 has a servo driver control system 36, servos 37 and servo cut-off control 38 associated therewith in a manner similar to that described above with respect to the processor 21. It will be appreciated that the servo cut-off switches 30 and 38 are enabled and disabled simultaneously via the AND gate 32 in accordance with the signals on the conductors 31 and 39 and the output of the monitor 34. A failure indication on any input to the AND gate 32 results in disabling the servos 29 and 37 by opening the servo cut-off switches 30 and 38. It will also be appreciated that the FZ-800 computer includes all of the components of Figure 1 except the elements 11, 12, 14, 17, 29 and 37. The processors 21 and 22 store program blocks which operate upon the signals from the sensors 11 and 12 and provide output signals and commands via conductors 27 and 35 to actuate the servo driver control systems 28 and 36. The processors 21 and 22 store the active function control modules for effecting the operative tasks to be performed by the system. The processors 21 and 22 also include monitor modules for the tasks, respectively. If a task control module is resident in the processor 21, the corresponding monitor module is stored in the processor 22, and similarly if a task control module is resident in the processor 22, the corresponding monitor module is stored in the processor 21. Real-time clocks (not shown) within the computers 21 and 22 control repeated iterations of the stored programs so as to effectively provide continuous control of the aircraft. In accordance with the invention, the task function control module and the corresponding monitor module have disparate functionality and disjoint computation paths with respect to each other. Referring now to Figure 2, in which like reference numerals indicate like components with respect to Figure 1, the A processor 21 of Figure 1 is illustrated depicting the basic internal construction thereof. The processor 21 includes an input/output (I/O) control unit 50 which provides the input porting for the digital signals on the data paths 19 and 25 of Figure 1 and also provides output signals on the buses 23, 26, 27, 31 and 33 as discussed above with respect to Figure 1. The digital computer 21 includes program storage 51, data storage 52, an arithmetic and logic unit (ALU) 53 and a control unit 54, all interconnected with respect to each other and with the I/O control unit 50 for two-way communication therebetween via a bus 55. It will be appreciated that the internal configuration of the computer 21 is of a conventional design and will therefore only briefly be described to facilitate an understanding of the invention. The program memory 51 has stored therein the operative program for performing all of the functions required by the A processor of the automatic flight control system 10 illustrated in Figure 1. The program is generally arranged in segments or modules as schematically illustrated by the blocks 56 to 63. The operative program includes active function or task modules A1, A2, ...., AN associated with reference numerals 56-58 and also includes monitor modules B1, B2, ...., BM for reasons to be clarified. The monitor modules are denoted by the reference numerals 59-61. The operative program also includes a task and monitor sequence control block 62 by which the task and monitor modules are called and sequenced in accordance with the program flow desired for the operative functionality of the automatic flight control system 10 (Figure 1) in which the processor 21 is utilised. The operative program stored in the program memory 51 also includes modules for performing unmonitored tasks as schematically represented by the block 63. These tasks are of a type that do not affect flight safety or air worthiness, whereby a malfunction of one of these tasks will not have undesirable results. Such unmonitored tasks may comprise mode logic, certain message management functions and certain gain programming functions which are not necessary for flight safety. Details of the structure and operation of the program stored in the program memory 51 will be described hereinbelow. The data memory or storage 52 is utilised for storing the constants used by the program as well as containing predetermined locations for the storage of the various types of data provided by the sensors 11 and 12 of Figure 1. The control unit 54 includes a program counter 64 and a plurality of registers 65 and the arithmetic and logic unit 53 includes the circuits necessary for performing the arithmetic and logical operations for the computer 21. In a manner well understood in the art, the control unit 54, as indexed by the program counter 64, sequentially fetches the instructions of the program from the program memory 51 and controls the computer 21 to perform the instructions, fetching data from the data memory 52 when required. The combination of the control unit 54 and the arithmetic and logic unit 53 is often referred to as the central processor unit (CPU) which is designated by the reference numeral 66. The arithmetic and logic unit 53 is utilised under the control of the control unit 54 to perform the conventional arithmetic and logical operations as required by the program. The I/O control unit 50 accepts data from the inputs 19 and 25 and provides data to the outputs 27 and 33 as well as timing and control signals on the outputs 23, 26 and 31 under the control of the control unit 54 as commanded by the program instructions stored in the program memory 51. If any of the monitor modules 59-61 detects a failure, the processor 21 provides a disabling signal on the conductor 31 to disable the servos 29 and 37 via the AND gate 32 and the servo cut-off switches 30 and 38 of Figure 1. Referring now to Figure 3, in which like reference numerals indicate like components with respect to Figure 1, the B processor 22 is illustrated depicting the basic internal construction thereof. The structure of the computer 22 is substantially identical to that of the computer 21 described above with respect to Figure 2. The computer 22 of Figure 3 includes components 70-86 corresponding functionally and structurally to the components 50-66, respectively, described above with respect to Figure 2. It should be noted, however, that the I/O control unit 70 does not provide an output comparable to the output 26 of Figures 1 and 2 since it is the A processor 21 and not the B processor 22 which provides control of the digital data receivers and buffers 18 of Figure 1. The program memory 71 of the processor 22 contains the active task of function modules B1, B2, ...., BM denoted by the reference numerals 76-78. These program modules control the active automatic flight control system tasks to be performed by the B processor 22. The program storage 71 also includes monitor modules A1, A2, ...., AN denoted by the reference numerals 79-81. If one of the monitor modules 79-81 detects a failure, a disabling signal is provided on the conductor 39 via the I/O control unit 70 to disable the servos 29 and 37 via the AND gate 32 and the servo cut-off switches 30 and 38 of Figure 1. Referring now to Figures 2 and 3, the A processor 21 of Figure 2 contains the active task modules A1 - AN and the B processor 22 of Figure 3 contains the respectively corresponding monitor modules A1 - AN. Each of the monitor modules of the B processor 22 monitors the correspondingly designated task module of the A processor 21. In a similar manner, the task modules BM of the B processor 22 are monitored by the monitor modules B1 - BM, respectively, of the A processor 21. In accordance with the invention, each task module in one of the processor 21, 22 and the corresponding monitor module in the other processor 22, 21 provide disparate functionality with respect to each other over disjoint computation paths. The functionality of each task module is determined by the required or desired performance of the module, whereas the corresponding monitor module functionality is determined by performance exhibited or events occurring that are prohibited by the task module; for example, the aircraft being controlled to perform beyond predetermined limits. Generally, in the preferred embodiment of the invention, the task modules in the A processor 21 contain the automatic trim control functions as well as the flight guidance functions of the system and the monitor modules of the B processor 22 provide the respective monitors therefor. The task modules in the B processor 22 contain the active control functions for the aileron, elevator and rudder for control about the roll, pitch and yaw axes of the aircraft, each such module containing the amplitude, rate and accceleration limits applied in controlling the excursions of the aircraft throughout its flight envelope. The corresponding monitor modules for the three axes control functions are resident in the A processor 21. Although in the preferred embodiment of the invention a specific distribution of tasks is described in the separate identical processors 21 and 22, it will be appreciated that other distributions of tasks can be envisaged in practicing the invention as claimed. Assurance, however, should be provided that all of the monitor modules are performed. This assurance is provided by the processor monitor 34 and associated software within the processors 21 and 22 as described above with respect to Figure 1. It will also be appreciated that in performing the processor monitoring function, the monitor block 34 of Figure 1 is utilised in conjunction with various operations performed by software modules interspersed among the tasks and monitor blocks of Figures 2 and 3 in the manner illustrated in US-A-4,115,847. The processor monitoring structure and operation of US-A-4,115,847 is separately utilised in each of the processors to assure that the monitor modules contained therein are executed during each iteration of the program. With respect to the active function control modules and the corresponding monitor modules, the following are included in the preferred embodiment of the invention. The task A1 module 56 of the processor 21 of Figure 2 represents the automatic trim function of the system and the monitor A1 module 79 of the processor 22 provides the monitoring functions therefor. The automatic trim function performed by the A processor 21 provides control signals to the appropriate servo driver control 28 (Figure 1) to actuate the trim servos 29 (Figure 1) so as to null the torque on the elevator control surface hinge pins to zero. The automatic trim function reduces the servo control forces on the elevator to zero by positioning the trim tab or trim stabiliser so as to effect the torque null with respect to the elevator. The corresponding monitor module 79 in the B processor 22 tests for a trim run-away condition and for a trim inoperative condition. The trim run-away condition is a hazardous, prohibited trim system output resulting in opposed trim conditions where the elevator surface and the trim surface are running in opposite directions. The trim inoperative condition is also a hazardous, prohibited condition. The monitor A1 module 79 of the B processor 22 of Figure 3 determines operability of the trim servo drive by utilising a direct end-around output from the servo drive to the analogue sensor inputs 11 of Figure 1. This connection is not illustrated in Figure 1. Thus, it will be appreciated that the active trim function module 56 and the corresponding monitor module 79 exhibit disparate functionality over disjoint computation paths. The active trim function is involved in positioning the trim surface whereas the monitoring module is concerned with detecting specific undesired operation and conditions. The B1 task module 76 in the B processor 22 of Figure 3 provides the automatic flight control system active roll axis control function and the B1 monitor module 59 of the processor 21 of Figure 2 provides the monitor therefor with disparate functionality and disjoint computation paths with respect to the B1 task block 76. The task block 76, utilising the I/O control 70, inputs the data for performing the active roll axis control function; such data including roll angle, roll body rate and air data signals such as dynamic pressure for controlling the programming of gains with respect to the sensitivity of the aileron control surfaces. The roll control law utilised in the active roll axis control function includes limits on the roll angle and roll rate to maintain the aircraft within normal performance manoeuvre boundaries. The B1 monitor module 59 in the A processor 21 monitors for over limits in displacement and rate and for roll control which is in the wrong direction. The B1 monitor module 59 has access to the polarity and amplitude of the roll servo motor voltage as well as the aircraft roll angle and rate. The B1 monitor 59 assesses the roll displacement and rate with respect to the direction of the roll servo drive to determine if the aircraft is exhibiting an out-of-limits condition. For example, if, due to an error the B processor 22 issues servo drive signals to roll the aircraft beyond the roll angle limit, the A processor 21 would discern this beyond-limits condition and would then assess the roll rate to determine if the roll rate was in a direction to decrease the roll error. If the roll rate is not in the direction to return the aircraft to within roll angle limits, the B1 monitor module 59 would then assess the output of the roll servo motor to determine whether or not the servo was attempting to return the aircraft to within limits. If the roll servo is not endeavouring to return the aircraft to within limits, the A processor 21 issues a disabling signal on the conductor 31 to actuate the servo cut-off switches 30 and 38 via the AND gate 32 of Figure 1. Thus the B1 monitor 59 of the processor 21 determines if the aircraft is exhibiting behaviour prohibited by the active control function of the B1 task module 76 of the processor 22. In this manner, the modules 59 and 76 control disparate functionality over disjoint computation paths. The active control function for the pitch axis is also performed by the B processor 22 of Figure 3, for example, by the B2 task module 77. The corresponding monitor module is performed by the A processor 21 of Figure 2 by, for example, the B2 monitor module 60. The required input data acquired through the I/O control includes the pitch angle and pitch body rate from the attitude system. The input data also includes gain programming signals from the air data system such as true and calibrated air speed as well as dynamic pressure utilised to control the sensitivity of the system to the wind loading of the pitch control surfaces as a function of speed. The pitch control law includes limits on pitch angle and pitch body rate as well as an effective G-limit programmed as a function of true air speed with respect to pitch angle and pitch body rate. The disparate monitoring function associated with pitch axis control is resident in the A-processor 21 as controlled, for example, by the B2 monitor module 60. The B2 monitor module 60 assesses closure of the pitch loop embodied in the B processor 22. Closure is the process of bringing the control loop of the aircraft into alignment with the issued command. Closure is effected when there is a zero servo error signal condition. If the servo error signal is non-zero, then the pitch rate and servo drive are assessed with respect to polarity to determine if control is in process to effect closure. For example, the pitch command issued from the guidance control is compared to the actual aircraft pitch attitude to determine if there is an error in excess of a predetermined tolerance. If such error is detected, the polarity of the pitch rate is assessed to determine if it is in the appropriate direction to reduce the attitude error. If the polarity of the pitch rate is not appropriate, then the polarity of the servo drive is assessed to determine if the servo is endeavouring to drive the loop to closure. Failure of all of these tests is defined as a faulted condition and the servos 29 and 37 (Figure 1) are disconnected via the servo cut-off switches 30 and 38. The B2 monitor module 60 of the processor 21 also determines if the active pitch axis control function is causing normal acceleration in excess of the G-limit. The monitor inputs servo data and normal acceleration data via the I/O control unit 50 and assesses the normal acceleration data for an over limit condition by cross correlating the actual normal acceleration with the servo feedback to determine if the servo output is the cause of the excessive normal acceleration. If the servo is causing the condition, the system is disconnected via the servo cut-offs 30 and 38 of Figure 1. The B processor 22 of Figure 3 also includes the active functionality of the yaw damper which provides servo drive control for the aircraft rudder. The yaw damper may, for example, be controlled by a task B3 module in the program memory 71 of the processor 22. The corresponding monitor function would then be performed by a monitor B3 module resident in the program memory 51 of the processor 21 of Figure 2. The active task module in the B processor 22 controls coordination of the turn manoeuvre and stabilisation of the aircraft about the yaw axis in straight and level flight. The yaw damper also includes a function to limit the rudder servo position authority. The turn coordination, yaw damping stabilisation and servo authority limiting are gain programmed as a function of airspeed and dynamic pressure. These functions are performed in the B processor 22 in response to a yaw body rate signal, a lateral acceleration signal, a roll attitude signal and a pitch attitude signal from the attitude system as well as airspeed and dynamic pressure data from the air data system accessed by the B processor 22 of Figure 3 through the I/O control unit 70. In turn coordination, the yaw damper provides the amount of yaw body rate so as to null the lateral acceleration in order to maintain the composite force vector aligned with the vertical axis of the aircraft. In performing the yaw stabilisation function, the yaw body rate is nulled so as to prevent oscillation of the aircraft about the yaw axis resulting from gust disturbances. This yaw damping function is gain programmed as a function of airspeed and dynamic pressure data to decrease the sensitivity of the system as airspeed increases because of the increased sensitivity of control surfaces, especially the rudder control surface, as a function of airspeed. The limiting function of the yaw damper bounds the servo position authority so as to limit the yaw acceleration of the aircraft to a predetermined maximum. Rudder displacements are limited as a function of dynamic pressure such that oscillatory or hardover outputs of the rudder are limited in amplitude so that the yaw acceleration maximum is not exceeded. The yaw damper monitor in the A processor 21 of Figure 2 detects excessive side loading of the aircraft and excessive motion of the rudder servo actuator due to the non-damped conditions where, for example, the yaw damper increases rather than relieves the side loading on the aircraft. Whenever the yaw damper provides an incorrect output, side slip of the aircraft occurs which is detected via the lateral acceleration signal. The lateral acceleration signal is assessed for excess G's of side loading and is correlated with the rudder servo actuator feedback to determine if the actuator is causing the side slip condition. This assessment is performed on the basis of polarity in the manner described above with respect to the pitch and roll axes. Thus it will be appreciated that the yaw damper active function and the corresponding monitor perform disparate functions over disjoint computation paths. Programs for insertion into the program memories 51 and 71 of the respective processors 21 and 22 are included in the Appendix filed with the original application for this patent and published in the first publication of the application, namely, EP-A-0207611. The Appendix was deleted from the application prior to final publication of this specification but remains in the Patent Office file of the application for this patent. The programs are formatted into the modules described above with respect to the active tasks and monitors associated with the trim, roll, pitch and yaw functions described. The programs are in assembly language code for the Z-80002 microprocessor as discussed above. The disparate functionality and disjoint computation paths, as discussed above, provide effective isolation of design errors with respect to both the software modules and the hardware. This isolation extends through the design process to the definition stage. The separation of functionality provides protection from failures within the processors, such that no single failure in processor hardware or software can cause both a task and its corresponding monitor to be disabled simultaneously. When a monitor module detects a failure, a servo enable signal on the conductor 31 or the conductor 39 (Figure 1) will actuate the servo cut-offs 30 and 38. It will be appreciated that two program modules which perform mutually disparate functions over disjoint computation paths and which do not access common subroutines, or input/output routines, and which cannot be driven into common interrupt loops are extremely unlikely to generate common-point malfunctions due, for example, to common software design or definition errors, processor or microcode design errors and compiler or assembler errors. The software monitors test both hardware and software for malfunctions and by utilising appropriate automatic flight control system performance criteria, can detect both faults and design errors in hardware as well as in software. With the present invention, because of the disparate functionality and disjoint computation paths, it is extremely unlikely that a generic fault will affect a task and its corresponding monitor simultaneously so that the fault is not detected. The above described embodiment of the invention has been explained in terms of utilising the processor monitor of US-A-4,115,847 to assure the repetitive performance of the software modules of the system. It will be appreciated that the techniques of US-A-4,115,847 may be applied only to the monitor modules. The active task modules are highly visible and are therefore monitored through the operation of the system. The monitors, however, tend to be invisible functions until needed and therefore may be latently inoperative. The processor monitor of US-A-4,115,847 will detect an inoperative monitor module. It will also be appreciated that because of the utilisation of the present invention, a fully monitored, automatic flight control system channel is provided having fail passive performance. Two such channels provide fail operative performance.

Claims: An automatic flight control system for aircraft having sensor means (11,12) for providing sensor signals in accordance with flight conditions experienced by the aircraft and having aircraft control means (29,37) for controlling the flight conditions of the aircraft in response to aircraft control command signals, one channel of the automatic flight control system comprising digital computer means (21;22) having computer input means (50;70) responsive to the sensor signals, program memory means (51,71) and computer output means (50,70), computer input coupling means (13,15,16,18) for coupling the sensor means to the computer input means and computer output coupling means (27;35) for coupling the computer output means to the aircraft control means for providing the aircraft control command signals thereto, the computer means (21;22) having a program stored in the program memory means (51;71) comprising a plurality of first program segments (56,57,58;76,77,78) for execution by the computer means to control the computer means to perform a plurality of tasks, respectively by operating on the sensor signal to generate the aircraft control command signals that control the aircraft flight conditions and to provide aircraft control command signals to the computer output means, the program further including a plurality of second program segments (59,60,61;79,80,81), each corresponding to, and for monitoring the performance of, a respective first program segment, characterised in that each second program segment performs a mutually disparate task over mutually disjoint computation paths with respect to the first program segment corresponding thereto, the computer means comprising first and second processor means (21;22) with each first program segment (56,57,88;76,77,78) being executed by one of the first and second processor means, with the corresponding second program segment being executed by the other of the first and second processor means, and with each second program segment monitoring the performance of the respective first program segment by performing a task which tests if the aircraft is performing flight conditions prohibited by the task performed by the corresponding first program segment, the computer means also comprising means (62;82) for controlling repeated iterations of the program, and means (34) for assuring that all of the second program segments are executed during each iteration of the program. A system according to claim 1 characterised in that the first and second processor means (21;22) are similar digital computers, each having computer input means (50;70) responsive to the sensor signals, program memory means (51;71) and computer output means (27,35). A system according to claim 2 characterised in that the assuring means comprises first and second assuring means for assuring that all of the second program segments (59,60,61;79,80,81) stored in the program memory means (51;71) of the first and second digital computers (21;22) respectively, are executed during each iteration of the program. A system according to any of the preceding claims, characterised in that it further includes disabling means (32,30;32,38) coupled to the computer means (21;22) and to the assuring means for disabling the aircraft control means in response to either the computer means or to the assuring means. A system according to claim 3 characterised in that it further includes disabling means (32,30;32,38), coupled to the first and second processing means (21,22) and to the first and second assuring means for disabling the aircraft control means (29;37) in response to either the first processing means (21), the second processing means (22), the first assuring means or the second assuring means.

Inventors: DAVIDSON, DALE DEAN, ENDRUD, DOUGLAS GENE
Applicants: HONEYWELL INC.
Application year: 1986
Main classification: G06F15
IPC codes: G06F11, G05D1, B64C13, G06F19