METHOD OF AND APPARATUS FOR ERROR MODIFICATION FOR VIDEO DATA

Abstract: A method of error modification for component video data, on the playback side of a digital VTR of Y, C R , and C B component system, to define a range of values that can be taken by the data judged to be erroneous by its error flag, based on the data judged to be correct by its error flag, and, when the error data is present outside the range, to modify the error data so that the same may take the value within the range of the values allowed for the same to take and then be output. By this arrangement, when the Y, C R , and C B signals are converted into playback R, G, and B signals, the same are adapted not to exceed the range of values for the same to take.

Description: The present invention relates to a method of error modification for video data of the Y, C R , and C B component system constituted of a luminance signal and two color difference signals and more particularly to a method of modification processing for residual error data that have been uncorrectable in a data correction process. A method for component digital coding of a video signal to be practiced in digital TV studios has been proposed which uses a sampling frequency of 13.5 MHz for the luminance signal Y and the sampling frequency of 6.75 MHz for each of the color difference signals C R (= R - Y) and C B (= B - Y), i.e., the so-called 4:2:2 component coding system. The sampling structure of this system is understood to be in a spatially static, perpendicularly crossing lattice form (orthogonal) as shown in Fig. 4 and therein sampling positions of the Y signal represented by black dots and those of the C R and C B signals represented by white dots are in common, or cosite. Quantization is carried out in accordance with the 8-bit linear quantization system (256 levels), and the quantization levels of peak levels corresponding to each of the Y, C R and C B signals are specified as shown in Fig. 5, that is, the black level for the Y signal is defined to be 16 in quantization level and the white peak level to be 235 and the maximum color difference levels for each of the C R and C B signals are defined to be 16 and 240 in quantization level. The Y, C R and C B signals are in the following relationship with the three primary color signals R, G, and B: Conversely, the R, G, and B signals are expressed with the Y, C R and C B signals as shown in the following formulas (2): In the prior art digital VTRs of the 4:2:2 component system; the Y, C R and C B signals are recorded and reproduced such that the above mentioned conditions are satisfied as shown in Fig. 6. An R signal converted into 8-bit digital data, for example, is supplied from an input 31 to a matrix circuit 34, a G signal converted into 8-bit digital data, for example, is supplied from an input 32 to the matrix circuit 34, and a B signal converted into 8-bit digital data, for example, is supplied from an input 33 to the matrix circuit 34. In the matrix circuit 34, the R, G, and B signals are matrixed in accordance with the above formulas (1) into Y, C R , and C B signals and these signals are supplied to a record/playback circuit 35. On the record side of the record/playback circuit 35, the data are encoded with error correcting codes and recorded in a recording medium as the Y, C R , and C B component signal data. On the playback side of the record/playback circuit 35, the data recorded in the recording medium are reproduced, the reproduced Y, C R , and C B signals are subjected to an error correction process, and data uncorrectable by the error correction process are subjected to an error concealment process, and the thus provided output is supplied to a dematrix circuit 36. In the dematrix circuit 36, the reproduced Y, C R , and C B signals are matrixed in accordance with the above mentioned formulas (2) and the playback R, G, B signals are generated and outputted. Figs. 7A and 7B indicate relationship between the signals that are converted through the R, G, and B signals → Y, C R , and C B signals conversion and the reproduced Y, C R , and C B signals → playback R, G, and B signals conversion performed in the matrix circuit 34 and the dematrix circuit 36. Fig. 7A expresses the R, G, and B signals in a cubic manner assuming that the amplitude of each signal takes the value between 0 and 1 and taking the R signal in the z axis, the G signal in the y axis, and the B signal in the x axis. The cube in Fig. 7A is transformed into the cube as indicated in Fig. 7B through mapping of one-to-one correspondence performed in the matrix circuit 34 in accordance with the formulas (1) defining the transformation. In Fig. 7B, the Y signal is represented by the y axis, the C B signal represented by the z axis, and the C R signal represented by the x axis. The transformation is made like this: Fig. 8A is a projection drawing of the cube in Fig. 7B on the (Y - C R ) plane, Fig. 8B is a projection drawing of the cube in Fig. 7B on the (Y - C B ) plane, and Fig. 8C is a projection drawing of the cube in Fig. 7B on the (C R - C B ) plane. As is apparent from Figs. 8A, 8B, and 8C, when the amplitude of the R, G, and B signals is assumed to take values between 0 and 1, the domains of the values to be taken by the corresponding signals Y, C R , and C B are given by the following formulas (3): And, the cube indicated in Fig. 7B is transformed again into the cube indicated in Fig. 7A through mapping of one-to-one correspondence performed in the dematrix circuit 34 in accordance with the formula (2) defining the transformation. In the digital VTRs of the 4:2:2 component system as described above, the input R, G, and B signal data,each taking amplitude values 0 - 1 independently of one another, are converted by matrixing into the corresponding Y, C R , and C B signals, which are then provided with error correcting codes and recorded. And, on the playback side, the error correction is made for the signals and if there are some uncorrectable residual error data, error concealment is done for them. Here, when considering the range (domain) of the values that the Y, C R , and C B signals can take, these values cannot be of arbitrary magnitude and independent of one another but are related with each other and subject to some restriction predetermined by their relationship with the R, G, and B signals. In the prior art digital VTRs, however, the Y, C R , and C B signals were treated as independent variables having the domains as indicated in the above mentioned formulas (3). Thus, for example, when the Y signal out of the reproduced Y, C R , and C B signals was correct and Y = 1 and, therefore, the results C R = 0 and C B = 0 must be obtained as a necessary consequence, it could sometimes happen that such erroneous data as C R = 0.5 and C B = 0.5 resulted when some error was produced in the course of the record -- playback process. If such Y, C R , and C B signals were converted by the dematrix circuit of the prior art digital VTR into R, G, and B signals, their values would become R = 1.5, G = 0.64, and B = 1.5. Thus, it followed that the playback R, G, and B signals that could not fundamentally exist were output, and as a result an abnormally bright red or blue color, for example, was produced and the quality of the picture was thereby greatly impaired. Even if action was taken forcibly to limit the amplitude of the R, G, and B signals within the range between 0 and 1, it was unable to modify the error data so as to have their right values. And, once the conversion into the R, G and B signals was made, it was difficult to modify the signals so as to restore their right values since the error information for the data had already been lost. Accordingly, a primary object of the invention is, in a method for modifying residual erroneous data, to provide an error modification method for component video data through which a combination of the Y, C R and C B signal data not allowed to be existing will be modified so that the data may be brought into a specific region where the data is allowed to exist and thereby improve the quality of the played back picture. According to the present invention, there is provided a method of error modification of video data comprising the steps of: receiving cosite-sampled Y, C R and C B component video signal data and error flags provided for each of said component video signal data, detecting whether or not the data judged to be erroneous by said error flag is present in a specific region of values which is defined based on the data judged to be correct by said error flag; and modifying the data judged to be erroneous by said flag, when the same is detected to be outside said specific region, so that the same becomes data within said specific region. The invention also provides apparatus for error modification of video data comprising: means adapted to receive cosite-sampled Y, C R and C B component video signal data and error flags provided for each of said component video signal data, means adapted to detect whether or not the data judged to be erroneous by said error flag is present in a specific region of values which is defined based on the data judged to be correct by said error flag; and means adapted to modify the data judged to be erroneous by said flag, when the same is detected outside said specific region, so that the same becomes data within said specific region. In a practical implementation of the invention, a ROM 7 is supplied with the data for the Y, C R and C B signals together with error flags FY, F R and F B for these data. In the ROM 7, the range (domain) of the values that are allowed to be taken by the residual error data judged to be erroneous by the error flag and unable to be corrected is defined based upon the data judged to be correct by the error flag, it is detected whether or not the error data is present within the range, and, when the error data is present outside the range, the error data is modified so that the same may take the value in the vicinity of the central value of the values that are allowed for the data to take. The thus obtained Y, C R and C B signals are supplied to the dematrix circuit and converted by matrixing into R, G and B signals, and so, the output R, G and B signals never exceed the domain of allowed values therefor from 0 to 1. The invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which:- Figure 1 is a block diagram showing an embodiment of the present invention; Fig. 2 is a block diagram used for explanation of an embodiment of the invention; Fig. 3 is a schematic diagram used for explanation of an embodiment of the invention; Figs. 4 and 5 are schematic diagrams used for explanation of the prior art to the present invention; Fig. 6 is a block diagram used for explanation of the prior art to the present invention; Figs. 7A and 7B are schematic diagrams used for explanation of the prior art to the present invention; and Figs. 8A, 8B, and 8C are schematic diagrams used for explanation of the prior art to the present invention. A preferred embodiment of the invention will be described below with reference to accompanying drawings. Fig. 1 shows the structure of an embodiment of the invention and the structure is connected to the output side of an error concealment circuit 22 on the playback side of a digital VTR as indicated in Fig. 2. Reproduced component signals Y, C R , and C B read out from a recording medium are supplied to an error correction circuit denoted by 21 in Fig. 2. In the error correction circuit 21, error correction for each of the Y, C R , and C B signal data is performed and, if some error data were then uncorrectable, error flags are set for the error data and the reproduced signals and the error flags F Y , F CR , and F CB together are supplied to the error concealment circuit 22. According to the error flags, the residual error data left uncorrected by the correction process in the error correction circuit 21 are subjected to an error concealment process by interpolation or the like in the error concealment circuit 22, and the data which have undergone the error concealment process together with the error flags F Y , F CR , and F CB are then supplied to an error modification circuit 23. In the error modification circuit 23, the range of values that are allowed to be taken by the error data judged to be erroneous by the error flag is defined based upon the data judged to be correct by the error flag and it is detected whether or not the error data is present in the specific region. Namely, it is judged whether or not the R, G, and B signals and the Y, C R , and C B signals are in the relationship to satisfy the predetermined conditions. If the error data is present in the specific region defined based on the data judged to be correct, the error data is allowed to be output as it is, and if the error data is present outside the specific region, the error data is modified so as to take the value in the vicinity of the central value in the specific region and put out. The output of the error modification circuit 23 are supplied to a dematrix circuit (not shown) and converted by matrixing therein to be output therefrom as playback R, G, and B signals. Fig. 1 is a drawing showing a concrete example of the error modification circuit 23. In this arrangement, in order not to enlarge the scale of the circuit, it is adapted such that the error modification is performed using the four high-order bits, as the representative values, of the reproduced component signals of eight-bit digital data. For example, the Y signal data is supplied from the error concealment circuit 22 to an input terminal 1. An error flag F Y indicating whether or not the Y signal data is erroneous is supplied from the error concealment circuit 22 to an input terminal 2. The C R signal data is supplied from the error concealment circuit 22 to an input terminal 3. An error flag F CR indicating whether or not the C R signal data is erroneous is supplied from the error concealment circuit 22 to an input terminal 4. The C B signal data is supplied from the error concealment circuit 22 to an input terminal 5. An error flag F CB indicating whether or not the C B signal data is erroneous is supplied from the error concealment circuit 22 to an input terminal 6. The four high-order bits of the eight-bit Y signal data supplied to the input 1 are applied to the ROM 7 and the four low-order bits are delivered to the output terminal 11 directly. The error flag F Y supplied to the input terminal 2 is applied to the ROM 7. The four high-order bits of the eight-bit C R signal data supplied to the input 3 are applied to the ROM 7 and the four low-order bits are delivered to the output terminal 13 directly. The error flag F CR supplied to the input terminal 4 is applied to the ROM 7. The four high-order bits of the eight-bit C B signal data supplied to the input 5 are applied to the ROM 7 and the four low-order bits are delivered to the output terminal 15 directly. The error flag F CB supplied to the input terminal 6 is applied to the ROM 7. In the ROM 7, data modification is applied to the error data that are judged to require the data modification, and the four-bit Y signal data passed through the ROM 7 is output to the output terminal 11, the four-bit C R signal data passed through the ROM 7 is output to the output terminal 13, and the four-bit C B signal data passed through the ROM 7 is output to the output terminal 15. In the event that the modification has been applied to the Y signal data, a flag F YE indicating that fact is output to an output terminal 12; likewise, when the modification has been applied to the C R signal data, a flag F CRE indicating that fact is output to an output terminal 14, and when the modification has been applied to the C B signal data, a flag F CBE indicating that fact is output to an output terminal 16. These flags are used in the succeeding stage when necessary. For example, in an arrangement in which the error modification circuit as indicated in Fig. 1 is provided in the preceding stage to the error concealment circuit 22, these flags are supplied to the error concealment circuit 22 in the succeeding stage. The operation of the ROM 7 will be described below with reference to the following Table 1 which indicates all the possible combinations of the error flags that are applied to the ROM 7. Referring to the Table 1, O indicates that the data corresponding to the error flag is correct and × indicates that the data corresponding to the error flag is erroneous. Combination of Error Flags Case F Y F CR F CB a O O O b O O × c O × O d × O O e O × × f × O × g × × O h × × × In the case a of the Table 1, all the data for the component signals Y, C R , and C B are judged to be correct and these data not modified in the ROM 7 and are output as they are. In the case b of the Table 1, the Y signal data and the C R signal data are judged to be correct and the C B signal data is judged to be erroneous. In this case, according to the relationship between the Y, C R , and C B signals and the R, G, and B signals defined by the previously mentioned formula (2), the C B signal data must be within the range defined by and therefore, the range of the values to be taken by the C B signal data to be output is judged to be defined by (1 / 0.194) (Y - 0.509 · C R - 1.0) ≦ C B ≦ (1 / 0.194)(Y - 0.509 · C R ) Y - 1.0 ≦ C B ≦ Y. And, it is judged whether or not the C B signal data is within the above range, and if the C B signal data is within the range, the same is output as it is. If the C B signal data is outside the range, the C B signal data is modified so as to take the value in the vicinity of the central value of the range. By way of example, when the Y signal data judged to be correct is at the quantization level of 56, the values that the C R and the C B signal data can take are defined to be within the region as indicated by O in Fig. 3 according to the predetermined relationship. In the case b of the Table 1, since the C R signal data is judged to be correct, the range of the values that the C B signal data can take is restricted within narrower limits, namely, restricted within the domain between 120 and 216 in representative quantization level. Therefore, if the C B signal data is within this range, the C B data is output as it is, and if the same is outside the range, the C B signal data is modified so as to take the central value 168 of the range and then output. In the cases c and d of the Table 1, the range of the values that the data judged to be erroneous can take is defined by the data that are judged to be correct as in the above described case b and it is judged whether or not the data is in this range. The data is output as it is if the data is within this range, and if the same is outside the range, the data is modified so as to take the value in the vicinity of the central value of the range of the values allowed for the data to take and then output. In the case e of the Table 1, the Y signal is judged to be correct and the C R signal data and the C B signal data are judged to be erroneous. In this case, according to the relationship between the Y, C R , and C B signals and the R, G, and B signals as defined by the formulas (2), it is judged that the values C R and C B to be taken by the C R signal data and the C B signal data must be within the range defined by - Y ≦ C R ≦ 1 - Y - Y ≦ C B ≦ 1 - Y - Y ≦ - 0.509 C R - 0.194 C B ≦ 1 - Y. Further, it is judged whether or not the C R signal data and the C B signal data are present within the mentioned range. If both the C R signal data and the C B signal data are present within the range, the C R signal data and the C B signal data are both output as they are. If either of the C R signal data and the C B signal data is present outside the range, the data outside the range is modified so as to take the value in the vicinity of the central value of the range of the values allowed for the data to take and output. If both the C R signal data and the C B signal data are out of the range, these data are modified so as to take the value adjacent to the central value of their respective ranges of the values for the data to take and then output. In the case where the Y signal data judged to be correct is at the representative quantization level of 56, for example, the values that the C R signal data and the C B signal data can take are defined within the region as indicated by O in Fig. 3. If the C R signal data and the C B signal data judged to be erroneous are both present within the region indicated by O , these data are output as they are without being modified. In the case where some data is present outside the region indicated by O , for example, when the C R signal data is at the representative quantization level of 120 and the C B signal data is at the representative quantization level of 56, the C R signal data is judged to be correct since this C R signal data is within the range of values that the same can take. According to this C R signal data, the values that the C B signal data can take are restricted within narrower limits and the C B signal data is thus modified so as to take the value adjacent to the central value of the range, namely, 168. In the case where the C R signal data is at the quantization level of 40, and the C B signal data is at the quantization level of 216, both the C R signal data and the C B signal data are out of the range of the values they can take, and so, they are modified so as to take the values adjacent to the central values of the regions indicated by O , namely, C R = 136 and C B = 152. When the combination of the error flags applied to the ROM 7 is as shown in the case f or g of the Table 1, the region for the numbers that two data judged to be erroneous can take is defined by the data judged to be correct the same as in the case e mentioned above, and the data are output as they are if the error data are in the region, and if the error data are outside the region, the error data are modified so that they may take the values adjacent to the central values of the ranges of the values that the respective error data can take and be brought into the region. In the case h of the Table 1, all the data are detected to be erroneous and therefore judged to be uncorrectable. In this case, all the data are output as they are. According to the present invention, in the error modification circuit, the range of the values that can be taken by the residual uncorrectable error data judged as such by the error flag is defined according to the data that is judged to be correct by the error flag in accordance with the predetermined relationship between the R, G, and B signals and the Y, C R , and C B signals, it is detected whether or not the error data is within the range, and if the error data is outside the range, the error data is modified so as to take the value adjacent to the central value of the values allowed for the data to take. Thus, when the modified reproduced signals Y, C R , and C B are converted into R, G, and B signals, the same will never exceed the amplitude values they had at the time they were input, and therefore the quality of the played back picture can be improved.

Claims: A method of error modification of video data comprising the steps of: receiving cosite-sampled Y, C R and C B component video signal data and error flags provided for each of said component video signal data, detecting whether or not the data judged to be erroneous by said error flag is present in a specific region of values which is defined based on the data judged to be correct by said error flag; and modifying the data judged to be erroneous by said flag, when the same is detected to be outside said specific region, so that the same becomes data within said specific region. A method according to claim 1 in which said component video data are of digital form and the detecting step comprise the step of using the upper significant bits of said component video data for modification of said error data. Apparatus for error modification of video data comprising: means adapted to receive cosite-sampled Y, C R and C B component video signal data and error flags provided for each of said component video signal data, means adapted to detect whether or not the data judged to be erroneous by said error flag is present in a specific region of values which is defined based on the data judged to be correct by said error flag; and means adapted to modify the data judged to be erroneous by said flag, when the same is detected outside said specific region, so that the same becomes data within said specific region. Apparatus according to claim 3, in which said detecting means comprises a memory means (7) which is operative to compare said input component video data with said specific region. Apparatus according to claim 4, in which at least upper significant bits of said input component video data items are supplied to said memory means (7). Apparatus according to claim 5, in which said memory means is controlled to substitute a centre value of a region of correct data values on the detection of the error in at least one of the input component video datas. Apparatus according to any one of claims 4 to 6, in which said error flags are supplied to said memory means (7) for identification of the video data items to be modified.

Inventors: TAKAO, ABE SONY CORPORATION, TETSUO, OGAWA SONY CORPORATION
Applicants: SONY CORPORATION
Application year: 1986
Main classification: H04N9
IPC codes: H04N9, H04N11