CURRENT SWITCHING DIGITAL-TO-ANALOG CONVERTER

Abstract: An n-bit current switching digital-to-analog converter of the type in which each weighted current I k , k=1, ..., n, of a set of n weighted currents has an associated current steering switch, said digital-to-analog converter comprises: a plurality of input means (201,203,205,209), each input means coupled to an associated current steering switch (211), each input means (201,203,205,209) inputting a data signal representative of one bit of an n-bit data word, at a predetermined data rate, to said associated current steering switch, said current steering switch (211) responsive to said data signal to conduct I k to a first summing rail (RAIL) when the data signal is of a first value and to conduct I k to a second summing rail (RAILBAR) when the data signal is of a second value; current source means (1) coupled to said current steering switches (211) for providing said set of n weighted currents; and sampling means (9) coupled to the first and second summing rails (RAIL, RAILBAR) for providing a first and second output (321,317), respectively, said first and second output (321,317) representing a sample of the summed currents on the first and second summing rails (RAIL, RAILBAR) after the current has settled to a steady-state value and prior to a succeeding data transition.

Description: Background of the Invention The present invention relates to an n-bit current switching digital-to-analog converter in accordance with the precharacterizing part of Claim 1. Such a digital-to-analog converter is known from IEEE Journal of Solid-State Circuits, Volume Sc-13, No. 6, December 1978, pages 746 - 753, IEEE, New York, U. S.; J. A. SCHOEFF.: "A Microprocessor-Compatible High-Speed 8 Bit DAC". A DAC consists essentially of a set of analog current-steering switches each controlled by one of the DAC's digital inputs. In an n-bit current switching DAC the digital input is an n-bit binary number, or word, and each bit has a corresponding weighted current. The weighted currents I₁, ..., I n are related by I k = 2k⁻¹I, where k is an integer in the range of 1 ≦ k ≦ n, where the k t h weighted current corresponds to the k t h bit of the n-bit binary word and where k = 1 corresponds to the least significant bit. For each bit which is equal to "1" a corresponding weighted current is coupled to the output of the DAC and for each bit which is equal to "0" a corresponding weighted current is not coupled to the output of the DAC. In this manner the current at the output of the DAC is the sum of the individual weighted currents coupled to the output of the DAC and the magnitude is proportional to the n-bit word input to the DAC. All DACs have an inherent limitation that may cause troublesome transients or glitches to be superimposed on the DAC output signal. When a new input word is applied to the DAC input to replace the previous word, proper operation of the DAC requires a simultaneous change of logic states on all digital inputs. In practical digital systems, however, the arrival of logic signals at the DAC inputs will always be somewhat skewed, mainly due to non-uniform delays in the individual logic signal source circuitry and interconnecting wiring. Further, individual switch cells may turn on faster than other switch cells, turn on faster than off or off faster than on, or in some cases a mixture of both. During the time when logic inputs are changing (skew time), the analog portion of the DAC will produce a glitch. The glitch will be most severe at the time of the major carry -- when all logic inputs are changing. For a DAC the single-count transition between 011 ... 111 and 100 ... 000 could produce an intermediate logic state (e.g., the worst case) of 000 ... 000 or 111 ... 111 during the skew interval. This momentary logic input will force the analog output of the DAC to slew towards either voltage extreme for the duration of the skew time. The higher the rate of succession of digital words (i.e., the shorter the duration of each word at the DAC's input) the more significant the glitch becomes. This skew time (caused by unequal turn-on/off times and bit transmission delays) can be minimized if all logic bits are loaded into a clocked storage register before transfer to the DAC. The simultaneous transfer of all bits into the DAC will limit skew times to those of the register and the DAC switches. Typically the register consists of a set of latches or master-slave flip-flops inserted between the digital inputs and the analog switches and is usually located in the immediate physical vicinity of the analog switches, preferably on the same monolithic chip. The DAC digital data inputs drive the data inputs of the master-slave flip-flops and the flip-flop outputs in turn drive the analog switches. The clock inputs of the flip-flops are all driven by a common clock signal whose phase is chosen so that its positive transition occurs prior to the most advanced data transition (the master-slave flip-flops are assumed to be positive-edge-triggered). The positive transition in the clock signal results in a transition in the flip-flop output signals which updates the output signals to become copies of the flip-flop input data. Because the flip-flops are all clocked by a common clock signal, the inputs to the analog switches occur simultaneously with negligible skew between the inputs and the DAC's output current controlled by the analog switches changes smoothly from a value representing one digital word to a valve representing the next digital word. However, this method of glitch removal has a drawback which may largely defeat the original purpose of the flip-flops, i.e., the removal of unwanted glitches from the DAC output signal. Since the flip-flops are positive-edge-triggered, the negative going edge of the clock represents an unavoidable "unused" transition of the clock signal. Due to the finite switching speeds of the flip-flops this unused clock transition cannot be moved arbitrarily close to the active transitions, but must occur somewhere near the center of the word interval, i.e., in the center of the interval between two active transitions. Consequently the unused clock transition will occur after the analog switch has settled and the DAC output current is being utilized. Due to crosstalk between the flip-flops and the analog switches and elsewhere on the chip, the unused clock transition will cause a disturbance (glitch) in the DAC output (analog output). An additional spike or glitch may be generated in the DAC output when the DAC input changes state causing an internal switching in the DAC. The internal switching creates a transient overshoot or undershoot at the leading or trailing edge of an output transient. The amplitude of the glitch can be significant when compared to the size of a step being made. For low bandwidth (slow) systems the time that the glitch exists may be very short compared to the total duration of the step and conventional low pass filtering may be utilized to satisfactorily remove the glitches. In high bandwidth (fast) systems, where the glitch may comprise a significant portion of the step duration, other means must be employed to eliminate the glitch. One such means comprises a sample and hold circuit in which the output of the DAC is sampled just prior to the end of the word interval, when the output has stabilized, and this value held during the glitch of the next step. A new sample is then taken after the DAC output has settled to the new value in the next word interval. Use of sample and hold systems may present several significant drawbacks. One limitation in a sample and hold system is the minimum acquisition time (i.e., the time required for the previous value to become the new value). The time to switch from sample to hold must be fast enough to decouple the sample and hold circuit from the following glitch. The decay rate of the storage element, typically a capacitor, during the hold period must be small enough to produce negligible error. Further, feedthrough from the sample switch to the storage element may generate spiking much larger than the size of the steps in the DAC output thereby defeating the purpose of the sample and hold circuit. The DAC known from the above mentioned IEEE-Journal of Solid-State Circuits comprises a data latch shown in Fig. 1 on page 747 and in detail in Fig. 4 on page 749 being enabled to latch the data bits D0 to D7 when any of the signals chip select, write and data enable goes high. The timing diagram of these signals is shown in Fig. 2 on page 747. The specification of the system interface timing is described on the same page: Data hold time, data setup time and data write time. Problems or solutions concerning glitch of the data signals before the data latch are not specifically described. The data latch receives no specific clock signal. The proper timing of CS-, W- and DE- and the stability of the data signals during the data setup time can be assured by the associated microprocessor system. IEEE Int. Solid-State Circuits Conference, 13.02.1985 describes a DAC employing multiple data input technic. Complementary data signals and interleaved clock signals are implemented. The three most significant data input bits are decoded by segment decoders distributing them to specific current switches. This prior art document teaches that a glitch energy of 20 psV is achieved without input latches and glitcher, i.e. the small glitch energy is achieved by a special segment decoding scheme. It is the object of the present invention to provide a high speed monolitic current switching digital-to-analog converter (DAC) which is able to eliminate feed-through of the previously unused clock edge and to avoid any perturbation in the DAC output. The above object is solved in accordance with the invention by the features characterized in Claim 1. The dependent claims characterize advantageous developments thereof. The DAC integrated circuit (IC) comprises input ECL to MOS level shift clock and data converters, clock drivers, differential dual latch multiplexer data latches and high speed current switching cells. The DAC IC is designed for use in a 12-bit sampled DAC system which includes an NMOS buffer IC, external precision current sources and a gallium-arsenide (GaAs) sampler IC. The DAC system operates at a 134 Mbyte data rate providing an analog output with a spurious content of less than -65 dB which settles to 1/2 least significant bit (LSB) in less than 4 ns. The DAC IC performs data synchronization and high speed current steering of binary weighted precision currents to a pair of differential output summing rails called RAIL and RAILBAR. The current switching cells utilize supplementary weighted currents to overcome the effects of long settling times due to parasitic capacitances as disclosed in U. S. Patent No. 4,405,916 issued to Thomas Hornak and Gary L. Baldwin on September 20, 1983 which is incorporated herein by reference. The data driver accepts ECL level data and provides complementary (i.e., 180° out of phase) MOS level data inputs to dual differential latches. The output of the dual latches is coupled to a differential multiplexer which selects the data to be coupled to the differential current switching cells. The dual latches and multiplexers require complementary clocks at one-half the data clock rate. Thus, effectively, data is latched at each transition or edge of the clock pulse rather than at only the positive (negative) going edge of the clock as in prior art systems. This eliminates feedthrough of the previously unused clock edge and hence any perturbation in the DAC output as is seen in the prior art. The DAC utilizes an external current source to establish the required precision weighted currents at the DAC output. The buffer IC provides additional isolation between the precision current source and the DAC IC current switching cells to achieve fast switching in the digital to analog conversion process. This buffers the impedance of the current source and decreases the capacitance seen by the DAC IC thereby decreasing the DAC settling time and increasing DAC speed. The sampler IC comprises a low distortion differential GaAs sampler to sample the output of the DAC to remove any spurious signals or noise that may be present in the DAC output due to the DAC's nonlinear slewing and settling. The sampling switch is an on/off switch, rather than a sample and hold circuit. The sample switch has no holding capacitor to charge resulting in faster on/off switching and less error. Further, there is no error introduced by capacitor discharge between samples. The sampler is operated at the data clock rate. The sampler IC includes a three-stage, ac coupled GaAs pre-amp which decreases the data clock pulse rise/fall time (hence increasing the slew rate) from approximately 1 ns to 200 ps and provides complementary outputs to a dc coupled level shift buffer stage which drives the sampler. The sampler is a differential, triple balanced architecture which steers the DAC's two outputs -- RAIL and RAILBAR -- alternately to a load resistor via a balancing transformer (balun) and to ground (or to a power supply return line via a dummy load resistor). The three ICs making up the DAC system are mounted in an 89 pin, pin grid array multilayer ceramic package. The GaAs sampler IC mounts to the ceramic package floor, and a heat sink covers the back side of the package base. The package base acts as a multilayer RF substrate connecting the sampler IC, DAC IC and supporting components such as the NMOS buffer IC, chip resistors and chip capacitors. Description of the Drawings Figure 1 is a block diagram of a digital-to-analog converter system according to the principles of the present invention. Figure 2 is a functional block diagram illustrating the architecture of one of the twelve cells of the DAC IC shown in figure 1. Figures 3A and 3B illustrate logic diagrams for a conventional NOR latch and a NOR data multiplexer. Figure 4 is a schematic diagram of the GaAs clock driver preamp shown in Figure 1. Figure 5 is a schematic diagram of the GaAs differential sampler circuit shown in Figure 1. Figure 6 is a timing diagram for the DAC system shown in Figure 1. Figure 7 is a block diagram of a multiplexed dual digital-to-analog converter system according to the principles of the present invention. Description of the Preferred Embodiment Referring now to Figure 1, a digital-to-analog conversion system (DAC) 10 according to the principles of the present invention is illustrated. The DAC 10 comprises a monolithic NMOSFET current switching DAC IC 7, an NMOSFET buffer IC 5 and a gallium arsenide (GaAs) sampler IC 9 mounted in a multilayer, co-fired ceramic package. Clock driver preamp 15 provides the clock signal for sampler 9. The circuitry for the sampler clock driver preamp 15 is included on the sampler IC 9 chip. Included in the DAC 10 is a precision current source 1 and an output balun 11; the balun 11 provides a single-ended ac output on line 13 from the complementary differential outputs of the sampler 9. The data in 19 comprises ECL level, single ended 12-bit words. Latch clock 17 inputs a complementary ECL clock at one-half the frequency of the rate of input data. The sampler clock 21 is a complementary ECL signal at the same rate as the data clock. Referring now to Fig. 2, a functional block diagram of the DAC IC 7 for a single bit is illustrated. The DAC IC 7 comprises a set of 12 such circuits or cells plus associated circuitry (not shown) to provide dynamic biasing. One clock driver 207 provides the latch clock signal to all 12 cells. The data driver 201 accepts a single-ended ECL data bit input on line 217 which is converted to complementary MOS level outputs to drive the dual data latches 203 and 205. The clock driver 207 accepts complementary ECL latch clock inputs, CLK and CLKBAR on lines 219 and 221 respectively, at one-half the data rate and provides complementary MOS latch clock outputs, CLK and CLKBAR on lines 215 and 213 respectively, to the data latches 203 and 205 and the multiplexer 209. The input data is latched into latch A 203 on the rising edge of the latch clock (CLK output on line 215 from clock driver 207) and is latched into latch B on the falling edge of the latch clock (rising edge of CLKBAR output on line 213 from clock driver 207). The output of latch A 203 is coupled to the A input port of multiplexer 209 and the output of latch B 205 is coupled to the B input port of multiplexer 209. The multiplexer 209 selects which latch outputs will drive the switch cell 211. The multiplexer 209 inputs A SEL and B SEL are clocked by the same clock driver 207 output, CLK and CLKBAR, which clocks latch A 203 and latch B 205, respectively. After the rising edge of CLK, latch A 203 is holding data and the multiplexer 209 selects the latch A 203 output; after the falling edge of CLK (the rising edge of CLKBAR), latch B 205 is holding data and the multiplexer 209 selects the latch B 205 output. When the latch clock changes state at either edge, the latch that was holding data becomes transparent and the latch that was transparent latches the data set-up at its inputs. The multiplexer "reads" the output of each latch only after that output is holding a steady state value; at the same time, it blocks the output of the opposite latch. The clock feedthrough of the prior art associated with the previously "unused" falling edge of the latch clock will not occur in the multiplexer 209 outputs driving the precision current switch cell 211. The operation of the switch cell 211 is described in the aforementioned U.S. Patent No. 4,405,916 and will not be described here. The output of the DAC IC 7 on RAIL and RAILBAR (as shown in Fig. 2) is dc coupled to a high speed monolithic GaAs current steering sampler 9 (as shown in Fig. 1). NOR transparent latch and NOR multiplexer configurations illustrated in Figures 3A and 3B respectively are utilized in the DAC IC 7. Complementary NOR logic was chosen in order to maximize logic symmetry and minimize glitches. Typically, complementary logic tends to produce lower amplitude glitches of shorter duration than single-ended logic and minimizes coupling to the outputs. The sampler 9 (as shown in Fig. 1) comprises a current steering differential switch which is on the same monolithic chip as the sampler clock driver preamp 15. Also included on the same chip are resistive biasing for the ac coupled preamp 15 and thirty-one diodes to provides static and dynamic protection for the GaAs circuitry. The diodes (as shown in Figs. 4 and 5) clamp chip inputs to prevent turn on transients and excursions in power supplies and other external circuitry from damaging the on-chip devices. Referring now to Fig. 4, the clock driver preamp 15 comprises a three-stage differential, ac coupled GaAs preamp, a dc level shift buffer and turn on protection circuitry. The preamp decreases the rise and fall time of the clock signal from approximately 1 ns to 200 ps, and the dc level shift buffer sets the clock signal voltage swing to the appropriate levels for the sampler circuit. The sample clock input 400 is coupled via capacitors 439 and 441 to the gates of GaAs FETs 401 and 403 which are connected to form a first common source differential amplifier stage with load resistors 438. FETs 405, 407 and 409, 411 form the second and third stages of the three-stage preamp. FETs 437 in the drain circuit of the second and third stages serve as resistive loads for the stages. FETs 417, 419, 421, 423 and 425, 427 buffer and isolate the common source circuits of each stage. Each stage is ac coupled to the next stage by coupling capacitors 443. The output of the third stage 409, 411 is ac coupled to the level shift buffer 413, 415. The level shift buffer 413, 415 input is a complementary clock signal at -1 volt dc bias. The output of the level shift buffer 413, 415 on lines 323 and 325, is a complementary clock signal with a four volt swing from 0.7 volt to 4.7 volt and rise and fall times of 200 ps. The output is dc coupled on lines 323 and 325 to the differential sampling switch (as shown in Fig. 5). The buffer stage utilizes resistive loads in the drain circuit for minimum output offset to provide well-balanced complementary outputs. The gate dimensions of FETs 413 and 415 are matched with the resistive loads to provide optimum turn on time for the triple balanced sampling switch 9 (as shown in Fig. 1). Referring now to Fig. 5, the current steering sampler switch 9 is made up of twenty 235 micron gate GaAs FETs and provides a true on/off switch rather than a sample and hold circuit. The sampler switch 9 is balanced to a differential input, RAIL and RAILBAR, balanced differential output, OUT and OUTBAR, and balanced to the complementary sampler clock or control signal on lines 323 and 325. This provides a linear output signal with maximum rejection of sampler clock feedthrough and all non-linear components at least 68 dBc down. FETs 313 and 315 form a common source differential switch which switches the RAIL, line 339, input between OUT, line 321, and a "throwaway" NULL or ground (power supply return) line, line 319. Similarly, FETs 309 and 311 form a second differential switch which switches the RAILBAR, line 341, input between OUTBAR, line 317, and the "throwaway" NULL or ground (power supply return) line, line 319. The complementary sampler clock is dc coupled on lines 323 and 325 to the FET gates. When the clock signal on line 323 goes high, the clock on line 325 goes low insuring that when FETs 309 and 315 are on, FETs 311 and 313 are off. FETs 331 and 333 in the common source circuits of FETs 309, 311 and 313, 315, respectively, isolate the switches from common drain node (RAIL and RAILBAR in the DAC, as shown in Fig. 2) capacitance to reduce switching time of the switches. FETs 301, 303 and 305, 307 comprise a second set of "nonswitching" switches which function to reduce spurious feedthrough of the sample clock due to the gate-drain capacitance of the FETs. A rising clock voltage on line 323 turns on FET 315 and couples a pulse of current via the gate-drain capacitance of FET 315 into the OUT, line 321, node. At the same time the complementary clock on line 325 provides a falling voltage at the gate of FET 307 which couples a balancing pulse of current via the gate-drain capacitance of FET 307 out of the OUT, line 321, node. Similarly, the gate-drain capacitance of FET 301 compensates the gate-drain capacitance of FET 309 and the gate-drain capacitances of FETs 303 and 305 compensate for the gate-drain capacitances of FETs 311 and 313. The "non-switching" switches balance the effects of sampler clock feedthrough in the "switching" switches to provide a sampler that is not drive level, voltage level or delay sensitive. In this embodiment, the test leads 343 and 345 are left unconnected and allowed to float. The outputs of the sampler switch 9 are coupled to a balun 11 (as shown in Fig. 1) wherein the complementary ac outputs are subtracted. The balun provides a single-ended output with excellent linearity and low spurious signal content. The balun also rejects other undesirable system noise. Referring now to Figs. 2 and 6, waveform 601 is the data input to the DAC data driver 201 (as shown in Fig. 2) and waveforms 602 and 603 are the clock and clockbar, respectively, inputs to clock driver 207 (i.e., the DAC clock). The data registers 203 and 205 function as ordinary positive edge triggered latches. Since complementary (180 degrees out of phase) clocks 602 and 603 at one-half the data rate are utilized to trigger the dual latches, 203 and 205, data is effectively latched on both the positive and the negative edge of the clock. Data is allowed to change immediately after any clock transition (i.e., zero hold time), but all data must be valid for at least 2 ns prior to the next clock edge for data to be latched ( 2 ns set-up time 613). The delay 617 from clock edge to DAC output transitions is 2 ns maximum and the DAC output 605 is valid and settled to within one-half LSB of the final value within 4 ns 619 maximum after transition of the clock, clockbar edge. By delaying (or advancing) the clock signals 602 and 603, differences in the electrical paths between the data 601 and the clock 602, 603 can be compensated for to achieve maximum performance of the DAC. The ECL input complementary clocks are buffered to MOS logic levels in the clock driver 207. The clock driver 207 consists of four dc coupled gain stages with a slew capability of 5 volts within 1 ns. The sampler clock driver preamp 15 (as shown in Figure 1) provides complementary clocks 606 and 607 of the proper voltage swing and slew rate (on lines 323 and 325 as shown in Fig. 5) from the ECL sample clock 400 (as shown in Fig. 4). The sampled portion 615 of the DAC output 605 is substantially free of glitches generated within the DAC IC 7. The sampler hold time 621 is nominally 0.75 ns and a maximum of 1.25 ns. The sampler delay 623 from a sampler clock edge to sampler output is nominally 1.0 ns and 1.25 ns maximum. The output of the sampler is illustrated as wave-form 609. In another embodiment, two or more DACs may be coupled to a multiplexing sampler switch to form a push-pull system or to increase the sampling and data rates. Referring now to Figure 7, two identical DAC systems, DAC 1 703, buffer 707 and current source 711 and DAC 2 705, buffer 709 and current source 713 are coupled to the sampler 701. DAC 1 703 and DAC 2 705 each has its own clock and data inputs, CLOCK 1 on line 719 and DATA 1 on line 717 and CLOCK 2 on line 723 and DATA 2 on line 721, respectively. In the described embodiment DAC 1 703 and DAC 2 705 are current switching DACs having an architecture similar to that of the DAC system described herein above; however, other DAC architectures may be utilized to form a similar multiplexed DAC system. Referring now to Figures 5 and 7, the sampler 9 (as shown in Figure 1 and 5) may be utilized in the dual DAC system illustrated in Figure 7 as the multiplexing sampler switch 701. DAC 1 and DAC 2, 703 and 705, have differential outputs RAIL and RAILBAR (as shown in Figure 2) represented by lines 727 and 729, respectively. One of the DACs, DAC 2 705, for example, is connected to the RAIL 339 and RAILBAR 341 inputs of the sampler switch 9. The other DAC, DAC 1 703 in this example, is connected to the test leads 343 and 345. FET switches 301, 303, 305 and 307 are connected to the complementary sample clocks on lines 323 and 325 180 degrees out of phase with FET switches 309, 311, 313 and 315, respectively (as shown in Fig. 5). For example, when the sample clock on line 325 is going positive, FET 301 is turned on directing the weighted current on test lead 343 to OUTBAR on line 317 and FET 311 is turned on directing any current on RAILBAR line 341 to the throwaway NULL on line 319. Since the sample clock on line 323 is 180 degrees out of phase with the sample clock on line 325, FETs 303 and 309 are turned off. FET switches 305 and 313 and 307 and 315 function similarly. In the above described manner, the outputs of the two DACs 703 and 705 are multiplexed on to the output, OUT on line 321 and OUTBAR on line 317, of the sampler 9 while the mutual compensation of the gate-drain capacitances, described hereinbefore, is maintained. In similar fashion, additional DACs may be multiplexed to provide increased sampling rates and data rates.

Claims: An n-bit current switching digital-to-analog converter in which each weighted current I k , k = 1, ..., n, of a set of n weighted currents has an associated current steering switch, said digital-to-analog converter comprising: A plurality of input means including data latch means for latching the bits of the input digital signals and current source means coupled to the current steering switches for providing said set of n weighted currents, characterized in that each input means comprises: Data driving means (201) receiving an associated data bit of an n-bit data word and providing at its output a pair of complementary data signals representative of said associated data bit; a pair of data latches (203, 205) coupled to the data driving means (201) for latching said complementary data signals in response to associated first and second latch clocks (213, 215) being 180 degrees out of phase and providing a data latch rate being one-half the input data rate, for effectively latching data on both positive and negative edges of the clock; and multiplexer means (209) coupled to said pair of latches (203, 205), said multiplexer means (209) being responsive to the first and second latch clocks for selecting and coupling the desired data signal from said pair of latch means (203, 205) to the associated current steering switch (211), wherein a data signal representative of one bit of an n-bit data word is input at a predetermined data rate to said associated current steering switch to conduct I k to a first summing rail (RAIL) when the data signal is of a first value and to conduct I k to a second summing rail (RAILBAR) when the data signal is of a second value; and that the digital-to-analog converter further comprises sampling means (9) being coupled to the first and second summing rails (RAIL, RAILBAR) for providing a first and second output (321, 317), respectively, said first and second outputs (321, 317) representing a sample of the summed currents on the first and second summing rails (RAIL, RAILBAR) after the current has settled to a steady-state value and prior to a succeeding data transition. An n-bit current switching digital-to-analog converter as in Claim 1 wherein: Said input means further comprises a latch clock input means (207) for receiving a complementary ECL level latch clock input (219, 221) and providing said first and second latch clocks (213, 215) at complementary MOS levels to drive said pair of latches (203, 205) and said multiplexer (209); said data driving means (201) receiving an ECL level data signal representing said associated data bit of said n-bit word and then provides said data signal, with complementary MOS level representing said associated data bit; said pair of latches (203, 205) comprise a pair of differential latch means coupled to said data driving means (201) and to said latch clock input means (207), said pair of differential latches (203, 205) responsive to said complementary latch clocks such that one latch means of said pair of latch means (203, 205) will latch said data signal representative of a first associated data bit on a rising edge of said first latch clock and the other latch means of said pair of latch means (203, 205) will latch said data bit on the falling edge of said first latch clock; and said mulitplexer means (209) comprises a differential multiplexer means (209) coupled to said pair of differential latch means (203, 205) and to said latch clock input means (207), said differential mulitplexer means (209) responsive to the complementary first and second latch clocks for selecting and coupling the desired data signal from said pair of differential latch means (203, 205) to the associated current steering switch (211). An n-bit current switching digital-to-analog converter according to Claims 1 or 2 wherein said sampling means (9) comprises: A first switch (313, 315) having a switch input (339) and a first switch output (321), said switch input (339) coupled to the first summing rail (RAIL), said first switch (313, 315) being responsive to a sample clock signal (21), the sample clock rate being equal to the input data rate, for conducting a first input current to the first switch output (321) when said sample clock signal (21) is of a first value and to conduct input current to a null load (319) when said sample clock signal (21) is of a second value, said first input current comprising the sum of I k , k = 1, ..., n, present on the first summing rail (RAIL); a second switch (309, 311) having a switch input (341) and a second switch output (317), said switch input (341) coupled to the second summing rail (RAILBAR), said second switch (309, 311) being responsive to the sample clock signal (21) to conduct a second input current to the second switch output (317) when the sample clock signal (21) is of said first value and to conduct said second input current to the null load (319) when the sample clock signal (21) is of said second value, said second input current comprising the sum of I k , k = 1, ..., n, present on the second summing rail (RAILBAR); a third switch (305, 307) coupled to the first switch output (321), said third switch (305, 307) responsive to the sample clock signal (21) to subtract from the first switch output (321) a current sufficient to cancel any current introduced to said first switch output (321) by said sample clock signal (21) resulting from effects of the first switch (313, 315) parasitic capacitances so that the net current at said first switch output (321) is equal to said first input current when the sample clock signal (21) is of said first value and is zero when the sample clock signal (21) is of said second value; and a fourth switch (301, 303) coupled to the second switch output (317), said fourth switch (301, 303) responsive to the sample clock signal (21) to subtract from the second switch output (317) a current sufficient to cancel any current introduced to said second switch output (317) by said sample clock signal (21) resulting from the effects of the second switch (309, 311) parasitic capacitances so that the net current at said second switch output (317) is equal to said second input current when the sample clock signal (21) is of said first value and is zero when the sample clock signal (21) is of said second value. An n-bit current switching digital-to-analog converter as in Claim 3, wherein said first switch (313, 315) and said second switch (309, 311) comprise identical switches, each identical switch comprising: A first transistor (315) coupling the switch input (339) to the switch output (321), said first transistor (315) responsive to the sample clock signal (21) to conduct the input current to the switch output (321) when the sample clock signal (21) is of said first value; and a second transistor (313) coupled to the switch input (341) and to the null load (319), said second transistor (313) responsive to the sample clock signal (21) to conduct the input current to the null load (319) when the sample clock signal (21) is of said second value. An n-bit current switching digital-to-analog converter as in any one of the above Claims, wherein said sampling means (9) includes: Amplifier means (15) for receiving a complementary clock signal and providing said sample clock signal (21), the sample clock signal (21) comprising a pair of complementary clock signals (323, 325); and buffer means (413, 415) coupled to the amplifier means (15) for adjusting the sample clock signal (21) voltage swing to the required levels for driving said sampling means (9). An n-bit current switching digital-to-analog converter as in Claim 5, wherein said amplifier means (15) comprises a three-stage (401, 403; 405, 407; 409, 411) AC-coupled differential amplifier. An n-bit current switch digital-to-analog converter as in Claim 6, wherein each stage of said three-stage amplifier comprises a pair of field effect transistors connected to form a common source differential amplifier stage. An n-bit current switching digital-to-analog converter as in any one of Claims 4, 5, 6 and 7, wherein said first and second transistors (315, 313) comprise field effect transistors, the source of each said first and second transistors (315, 313) connected to a common connection, said common connection coupled to the respective switch input, the first (323) of said pair of complementary sample clock signals (323, 325) coupled to the gate of the first field effect transistor (315) and the second (325) of said pair of complementary sample clock signals (323, 325) coupled to the gate of the second field effect transistor (313), said first and second field effect transistors (315, 313) connected to form a common source differential switch. An n-bit current switching digital-to-analog converter as in Claim 8, wherein buffer means (333) are interposed between said common connection and said switch input (339) for buffering said switch input (339) from effects of input parasitic capacitance to decrease switching time of the switch. An n-bit current switching digital-to-analog converter as in any one of the above claims, wherein said field effect transistors comprise gallium arsenide transistors.

Inventors: BALDWIN, GARY, HALLGREN, ROBERT B., HORNAK, THOMAS, IVES, FRED HERBERT
Applicants: HEWLETT-PACKARD COMPANY
Application year: 1986
Main classification: H03M1
IPC codes: H03K17, H03M1, H03K19