COMPLEMENTARY FET DELAY/LOGIC CELL

Abstract: An integrated circuit comprises a pass transistor (M40) connected to the input of a complementary inverter pair. Means (403) are included to supply to the complementary inverter a reduced voltage, as compared to the signal voltage supplied to the gate of the pass transistor. In this manner, the switching threshold of the inverter is reduced, allowing a single conductivity type of pass transistor to be advantageously used. In one embodiment, the reduced voltage is obtained by a diode-connected enhancement type field effect transistor, producing a threshold voltage drop. In another embodiment, means for supplying three power supply voltages are utilized. A delay stage for a shift register can advantageously be implemented by the present technique. Transmission gate logic circuits can also be implemented by the present technique.

Description: COMPLEMENTARY FET DELAY/LOGIC CELL Background of the Invention 1. Field of the Invention - The present invention relates to a circuit implemented in complementary field effect transistor technology that is suitable for performing logical operations and delay functions. 2. Description of the Prior Art It is known to use complementary field effect transistor (referred to as "CMOS") technology to provide various circuit functions, e.g., shift registers and logic circuits. As described hereinafter, prior known such circuits suffer from complexity and high cost. The present invention provides such circuits with less complexity. Summary of the Invention We have invented a circuit comprising one or more field effect pass transistors of a single conductivity type connected to the input of a complementary inverter. A signal voltage of a given magnitude is applied to the gates of the transistors. A lower voltage is applied across the sources of the complementary transistors in the inverter. In one embodiment, the lower voltage is obtained from a field effect transistor having its gate connected to its drain, thereby obtaining a threshold voltage drop. Brief Description of the Drawings FIG, 1 shows a prior art NMOS logic circuit. FIG. 2 shows a prior art NMOS logic circuit using depletion mode transistors. FIG. 3 shows a prior art shift register cell. FIG. 4 shows a shift register cell implemented according to the present technique. FIG. 5 shows a transmission gate logic function implemented by one embodiment of the present technique. FIG. 6 shows logic function implemented by an alternate embodiment of the present technique. FIG. 7 shows an embodiment of the present technique utilizing p-channel pass transistors. FIG. 8 shows typical d-c switching characteristics of a complementary inverter at two voltage supply level. Detailed Description Shift registers that comprise a multiplicity of delay stages, or cells, are widely used for performing a variety of tasks in integrated circuits. For example, to perform a fast Fourier transform (FFT), the data is inputted into a long shift register, typically comprising over a thousand stages. The data is moved through the stages synchronously with a system clock that controls the transfer of the data from one stage to the next. Output taps can be provided at various points along the shift register. These taps provide an amount of delay of the data, as referenced to the input, that corresponds to the tap position. For example, a shift register clocked at a rate of one megahertz provides for one microsecond of delay per stage. Taps spaced at 250, 500, and 750 stages from the input .then provide for delays of 250, 500, and 750 microseconds, respectively, with reference to the input. To implement a shift register in complementary field effect transistor (e.g., CMOS) technology, the con iguration of FIG. 3 has been used. This provides that a given cell (e.g., cell 1) comprise two complementary inverters M32-M33 and M36-M37. These are separated from each other, and from inverters in neighboring cells, by complementary transistors M30-M31 and M34-M35. The data is inputted to the input node 300 common to n-channel transistor M30 and p-channel transistor M31 , which are referred to as "pass transistors". It will be recognized that whether a given electrode of an individual pass transistor is considered a source or a drain depends on whether a high or low voltage data signal is present on input node 300 at any given time. The convention used herein is that the electrode of the pass transistors connected to the input node (300) is the "source", while the electrode connected to the inverter input node (301) is the "drain". Normally, the sources and drains of a given field effect transistor are physically identical. A master clock signal, MC, is applied to the gate of M30, and its complement, MC, is applied to the gate of M31. When MC goes to a high voltage level, and MC goes low, the voltage level present at input node 300 is passed to node 301, and hence to complementary inverter transistors M32, M33. These serve to invert the data input signal, so that a high voltage input produces a low voltage output at node 302, and vice- versa. This inverted data signal at node 302. is applied to pass transistors M34, M35, which are clocked by a slave clock and its complement, SC and SC, respectively. The slave clock is delayed, typically by one-half clock period, from the master clock. Hence, the data signal appears at node 303 approximately 1 clock period later than at input node 300. The data signal is then again inverted by complementary inverter pair M36, M37, and applied to the next delay cell. It can be seen that this prior art technique utilizes two pass transistors, one n-channel and the other p-channel, per inverter. This is because a n-channel transistor is best for passing a low voltage level to the inverter (i.e., to node 301), and a p-channel transistor is best for passing a high voltage level. That is, there is always one of the pass transistors operating in the saturation region, which provides that the associated inverter transistors are turned hard "on" or "off", except during the transition from one level to another. This is desirable to minimize power consumption of the inverter. However, this technique requires the generation and routing around the shift register of the four clock signals, MC, MC, SC, and S ~ C. This is a considerable complication of the shift register design, and requires significant space on an integrated circuit for the appropriate signal generators and clock signal lines. One design simplification known in the art is to simply eliminate one set of pass transistors (e.g., the p-channel ones), in order to simplify the layout and eliminate the need for the complement clocks {MC, S ~ C " ) and associated lines. This presents an input "1" to the next inverter of about Vdd-Vth, where Vth is the threshold of the (NMOS) pass transistor. In some cases, the voltage reduction across the pass transistor is even greater, due to an increase in back-gate bias on the pass transistor as its input terminal ("source") goes positive due to the data signal. The degraded signal leaves both the NMOS and PMOS inverter transistors turned on. Hence, this results in an increase in the power consumption of the shift register. It is known to form the (NMOS) pass transistor so as to have a lower threshold voltage than that of the corresponding conductivity (NMOS) inverter transistor, so as to reduce this loss of drive voltage. However, that requires extra processing steps. It is desirable to have an improved technique for implementing a clocked shift register in complementary (e.g., CMOS) technology. Another area that utilizes field effect transistors as pass elements is so-called transmission gate logic. In that technique, the pass transistors are configured to perform logical operations on two or more logical input signals. The logical output is then provided to the complementary inverters, as before. In this manner, a building block approach to logical system design is possible. An advantage of this technique over certain other logic circuit techniques is a reduction in power consumption. However, prior art transmission gate logic implemented in CMOS technology also required two sets of pass transistors, one n-channel and the other p-channel, to adequately drive the inverters. While it is also possible to use only one type of pass transistor (e.g., n-channel) to implement logic functions, this also results in an undesirable increase in power consumption. Note that in earlier generation technologies, prior to CMOS, all the transistors were necessarily of a single conductivity type. For example, NMOS provided only n-channel devices. A clocked logic circuit might then be implemented as indicated in FIG. 1 , wherein three power supply voltages, 0, +5, and +12 volts were typically present. All of the transistors for the circuit shown are of the enhancement type, wherein a positive gate-to-source voltage, VGS, was required to allow conduction between the source and drain. Hence, to provide for load elements, the transistors were typically either diode connected (M11) or biased with a gate voltage more positive than the drain voltag.e (M14). An input clock signal having 5 and 0 volt levels is shown applied to the gate of M10. The output of this inverter, at node 11, then assumes the levels of about 0 to 11 volts, assuming that M11 has a threshold of 1 volt, which subtracts this amount from the 12 volt power supply level. This clock signal is then applied to the gate of pass transistor M12, which has a 0 to 5 volt data signal applied to its source. Hence, a clocked data signal having a 0 to 5 volt level appears at the drain of M12, and the gate of inverter M13. The output of this inverter is then 5 to 0 volts. The use of only two power supply voltage levels (e.g., 0 to 5 volts) is also known for circuits using enhancement mode load transistors, In that case, a boosted clock voltage has been applied to the gate of the pass transistor (M12). However, this requires means for generating a boosted voltage in excess of the power supply voltage. Numerous other configurations of this illustrative type have also been used. A later generation NMOS technology utilized depletion mode field effect transistors as loa... elements. These devices conduct source-drain current even when VGS = 0 volts; e.g., when the gate of the device is connected to its source. This technology allowed a significant simplification in system design, since only two power supply voltages, typically 0 to 5 volts, were required. Referring to FIG. 2, an illustrative circuit logically equivalent to that of FIG.1 is shown. Since load devices M21 and M24 are essentially resistive between source and drain when connected as shown, the full 5 volt power supply voltage is available to pull up the drain of inverter transistors M20 and M23. That is, there is no threshold voltage drop to subtract from the power supply voltage. By the proper choice of the ratio of device sizes between a load element and its associated inverter transistor, a desired switching threshold could be obtained. However, a significant disadvantage of the depletion mode NMOS technology was the consumption of static power through the load transistor (M21 , M24) when the associated inverter transistor (M20, M23) was turned on. The development of CMOS technology essentially solved the problems noted for the prior NMOS technologies, in that a two voltage power supply could be used, and static power consumption substantially reduced. However, the freedom to chose a desired switching threshold for an inverter by simply choosing the size ratio between load and switching transistors was lost. This is because in a CMOS inverter, the conduction of both transistors is then determined primarily by their threshold voltages, since both the n-channel and p-channel devices are typically enhancement mode types. Normally, it is desired that the magnitude of the thresholds be approximately equal. However, equal threshold voltages imply that the switching threshold of complementary inverter is at one-half the power supply voltage, or about 2.5 volts for a 5 volt supply. When implementing pass-transistor circuits in CMOS, this leads to the problems noted above, which typically lead to the requirement for both p- and n- channel pass transistors. Hence, it is desirable to have an improved technique for implementing pass-transistor circuits in complementary (e.g., CMOS) technology. The following detailed description relates to a technique for implementing delay and/or logic functions using field effect pass transistors. In the present technique, a reduced voltage is applied across a - 1 - complementary inverter, as compared to the gate voltage applied to the one or more pass transistors connected to the input thereof. The relative reduction in the switching threshold of the inverter allows for more complete switching, and consequently a reduction in the power consumption, even with pass transistors of only a single conductivity type. Referring to FIG. 4, a delay state is shown implemented according to one embodiment of the invention. A binary data signal havig a given voltage swing between logic levels is applied to pass transistor M40. A clock signal CK having a first voltage swing (e.g., 0 to 5 volts) is applied to the gate of M40. The data signal passes through M40 when the channel conducts in response to CK, and is applied to the input node 401 of a complementary inverter comprising p-channel transistor M42 and n-channel transistor M41. A n-channel transistor M43 having its gate and drains connected together provides a threshold of voltage reduction across the inverter, as compared to the voltage between the positive and negative power potentials, Vdd and Vss respectively. This voltage reduction causes an approximately comparable reduction in the switching threshold for the complementary inverter; see FIG. 8. As shown, curve 30 represents the output versus input d-c characteristics of the inverter operating at 5 volts, and curve 81 shows the characteristics at the reduced voltage. As used herein, the term "switching threshold" refers to the input voltage on the complementary inverter at which the output voltage assumes one-half of the voltage across the complementary transistor pair. This latter voltage is measured at the source of the p-channel inverter transistor with reference to the source of the n-channel inverter transistor; e.g., Vdd-Vss (FIG. 3), or from node 403 to Vss (FIG. 4). Since the threshold voltages and conductances of the n- and p- channel transistors have been assumed to be the same, at 1.5 volts, for illustrative purposes, the switching threshold then changes from 2.5 volts (curve 30) to 1.75 volts (curve 81). This lowering of switching threshold then provides for improved switching of the inverter when only n-type pass transistors are connected to the input. The input-output characteristic curves are somewhat different under actual switching conditions, due primarily to capacitive loading on the various nodes that are undergoing voltage transitions. The net effect is usually to increase the input voltage change necessary to produce a given change in the output voltage. A further effect relates to the difference in threshold voltages for the p- and n-channel transistors of the inverter. If the p-channel device has a lower magnitude threshold than the n-channel device, then the switching threshold increases relative to the voltage of the negative power supply voltage (Vss) applied to the inverter, and vice-versa. For example, if Vth = 1 volt for the p-channel device, and Vth = 1.5 volts for the n-channel device, then the switching threshold is at 2.75 volts for an inverter operating at 5 volts thereacross (FIG. 3), and at 2 volts for an inverter with 3.5 volts thereacross (FIG. 4). The amount of back- gate bias can also effect the threshold of a given device. For example, if M43 is located in a p-tub at Vss potential, then the positive voltage of its source relative to the tub causes an increase in the threshold. Thus, if the threshold of M41 is 1.2 volts, then that of otherwise identical M43 will be higher, perhaps about 1.8 volts. An advantage of the present technique can be seen by considering a logic signal applied to input node 400 in FIG. 4. Assume that the voltage swing produced by this input signal is 0 to 5 volts, as could be the case if interfacing with other portions of an integrated circuit, or with an external circuit operating at standard levels. Then, when a positive clock signal (e.g., 5 volts) is applied to the gate of M40, a positive logic signal at 400 is allowed to pass through the channel of M40 to node 401. A threshold voltage drop will occur across M40 , so that the signal level will be 5-1.5=3.5 volts at node 401. Referring again to FIG. 8, it is seen that a 3.5 volt signal is sufficient to turn the inverter hard on, so that the output drops to essentially 0 volts. Note that if the full 5 volt power supply voltage were across the inverter, the p-cahnnel inverter transistor M42 would be just at its threshold, and hence subject to sub-threshold current leakage, which increases d-c power consumption. Furthermore, in that case any increase in the threshold of M40 as compared to M42 would cause M42 to conduct even more. Hence, the present technique also provides for increased protection against processing variations that can lead to a differential threshold shift between p- and n- channel devices. Furthermore, the pass transistor (e.g., an n-channel type) may have the same threshold as the inverter transistor of the corresponding conductivity type (n-channel) for simplified processing. This threshold may be the same magnitude as that of the other conductivity type (p-channel) inverter transistor if desired. Note that when the input logic signal goes lo (0 volts), then M40 passes this level substantially unchanged to node 401, so that 41 is turned hard off, and M42 hard on. Hence, a high (3.5 volt) signal appears at output node 402. The 0 to 3.5 volt output voltage swing at node 402 is passed through pass transistor M44 when the CK: signal is high. If CK is at least a threshold voltage drop (of M44) greater than this 3.5 volt high signal level, then the high signal at node 402 will be passed substantially unchanged to node 404 of the second complementary inverter pair, M45-M46. The operation of this inverter, often referred to as the "slave" portion, is then identical to that of the "master" portion previously described. Hence, the data is passed from node 400 to node 405 in synchronism with one cycle of the clock. Note that the 3.5 volt high level of the logic signal will remain unchanged through successive delay cells if the gates of successive pass transistors are also be at the same clock level (e.g., 5 volts) as applied to M40 and M44. Hence, no additional threshold voltage drops will occur through the pass transistors. Upon reaching the last delay stage, the logic signal may be regenerated to the full power supply level, e.g., 0 to 5 volts, if desired. This may be accomplished by various techniques known in the art, including the signal to a complementary operating at the full (5 volt) power supply level. The foregoing has described the present technique for use with clocked stages. However, the application of the present technique to so-called transmission gate logic circuits is also po'ssible, and included herein. Referring to FIG. 5, the logical signals X and X are applied to the gates of M51 and M52, respectively. These logic signals need not be in synchronism with a clock signal, but may be if desired. The logic signal Y is applied to the source of M51, and Y is applied to the source of M52. The result is that the logic function X exclusive or Y is generated at node 52, and hence its complement, X exclusive nor Y, appears at node 53, the output of the complementary inverter. Similar advantages relating to minimizing current flow and power consumption are obtained as for the delay stage. More complex logic functions can be built utilizing the present technique: see, for example, "Cascading Transmission Gates to Enhance Multiplier Per ormance", R.R. Shively et al, IEEE Transactions on Computers, Vol. C-33, pp. 677-679 (1984). The foregoing has utilized the threshold voltage drop of a FET to generate the lower voltage across the complementary inverter, as compared to the voltage swing applied to the gate of a pass transistor connected to the input thereof. This recognizes that such a threshold voltage drop is nearly ideal for shifting the switching threshold of the inverter to a lower voltage value, allowing the use of a pass transistor of only a single conductivity type. However, an alternate embodiment of the present technique utilizes the voltage differences that ace commonly available, or proposed, in various integrated circuit operating environments. For example, in emitter coupled logic (ECL) circuits, the voltages are 0, -2, 0, and -5.2 volts. Note that these differences may be referenced to any level, and thus can be equivalently expressed as +2.0, 0, and -3.2 volts, etc. Referring to FIG. 6, a pass transistor M60 has applied to its gate a signal X that has the binary values of 0 and -5.2 volts. Applied to the source of M60 is a signal Y that typically has the values of -2 and -5.2 volts. The voltage on the source of p-channel transistor M62 is -2 volts, and that on the source of n-channel transistor M61 is -5.2 volts. Hence, the voltage across the complementary inverter pair M61-M62 is 3.2 volts, whereas the voltage swing applied to the gate of the pass transistor M60 is 5.2 volts. The lowering of the voltage thusly provides an even greater reduction in the switching threshold of the complementary inverter that is typically obtained with a threshold drop transistor. Note that the output swing of the inverter is -2 to -5.2 volts. This output signal may be applied to succeeding logic stages, as before. Another suitable set of voltages for practicing the present technique uses the 0 and 5 volt levels, as discussed above, for supplying the 0 to 5 volt swing on the gates of the pass transistors. Then, a power supply voltage of about 3.3 volts, which is proposed as a new standard for M.OS integrated circuits, is applied across the complementary inverter. A further advantage of the foregoing voltage levels is that the logic signal may be easily regenerated to 0-5 volt levels, or 0 to -5.2 volt levels, for interfacing with circuits that operate with these standard levels. Still other voltage levels are possible. Typically, the voltage applied across the sources of the complementary inverter transistors is at least 10 percent less than the magnitude (voltage difference between 0 and 1 levels) of the signal applied to the gate of the pass transistor. The foregoing has illustrated the present technique with n-channel pass transistors. However, it can also be utilized with p-channel pass transistors. Referring to FIG. 7, p-channel pass transistor M70 has a clock signal applied to its gate, which allows it to pass a logic signal therethrough when the clock is in a low voltage state. The clock levels are typically 0 to 5 volts as before. The logic signal is thus passed to complementary inverter pair M73-M72, which has a reduced voltage thereacross due to p-channel dropping transistor M71. Note that a threshold voltage drop is obtained across M71 , producing a level of Vss + Vth at the source of M72. Then, assuming for example that Vss - 0 volts, Vdd = 5 volts, and Vth = 1.5 volts as before, a logic voltage swing of 1.5 to 5 volts appears at output node 72. This signal may then be applied to succeeding stages, as before. The foregoing has also noted the use of NMOS and PMOS type transistors. However, other insulated gate field effect transistor (IGFET) types are also possible, as well as junction types. In general, circuitry using enhancement mode types of transistors of any technology benefit from the present technique. In addition, the foregoing has illustrated the use of one voltage-dropping transistor per inverter stage for the embodiment of FIGS. 4, 5, and 7. It is alternately possible to share a voltage dropping transistor among two or more inverters. For example, a single transistor may be used to provide the reduced voltage across all (or several) of the complementary inverters on a given integrated circuit chip or wafer.

Claims: Claims 1. An integrated circuit comprising at least one pass field effect transistor connected to the input of a complementary inverter comprising a p-channel field effect transistor, CHARACTERIZED IN THAT said integrated circuit comprises means (CK) for applying to the gate of said pass transistor a signal having a first magnitude between binary states, and further comprises means (403) for applying across the sources of the field effect transistors of the complementary inverter a d-c voltage having a second magnitude that is substantially less than said first magnitude. 2. The integrated circuit of claim 1 wherein said d-c voltage is obtained by means of an enhancement type field effect transistor having its gate connected to its drain at a node adapted to contact a first power supply voltage level, and having its source connected to the source of the -filed effect transistor in said inverter that has the opposite channel conductivity type as said enhancement type. 3. The integrated circuit of claim 2 wherein said enhancement type field effect transistor supplies said d-c voltage to only one complementary inverter. 4. The integrated circuit of claim 2 wherein said enhancement type field effect transistor supplies said d-c voltage to more than one complementary inverter. 5. The integrated circuit of claim 1 wherein said signal applied to the gate of said pass transistor is a clock signal. 6. The integrated circuit of claim 1 further comprising (Fig. 7) at least one additional pass transistor (M74) having its source connected to the output node of said complementary inverter, and having its drain connected to the input node of a second complementary inverter. 7. The integrated circuit of claim 6 further comprising means for applying to the gate of said pass transistor a clock signal, and means for applying to the gate of said additional pass transistor a complement clock signal, whereby a clocked delay stage is obtained. 8. The integrated circuit of claim 1 further comprising means for applying a first logic signal to the gate of said pass transistor, and means for applying a second logic signal to the drain of said pass transistor. 9. The integrated circuit of claim 1 wherein said means for applying said d-c voltage comprise connection means adapted to contact a power supplying a d-c voltage of said second magnitude. 10. The integrated circuit of claim 1 wherein said at least one pass transistor is a n-channel transistor that has a threshold voltage (Vth) that is substantially equal to the threshold voltage of said n-channel field effect transistor of said inverter. 11. The integrated circuit of claim 1 wherein said at lease one passs field effect transistor is a p-channel transistor that has a threshold voltage (Vth) that is substantially equal to the threshold voltage of said p- channel field effect transistor of said inverter. 12. The integrated circuit of claim 1 wherein said pass field effect transistor, said p-channel field effect transistor, and said n-channel field effect transistor are all enhancement type transistors. 13. The integrated circuit of claim 10 wherein the magnitudes of the threshold voltages of said transistors are substantially equal to one another.

Inventors: DIMYAN MAGID YOUSRI, JOSEPH SAUL JOSHUA, KRAKOW WILLIAM TOMPKINS, PEDERSEN RICHARD ALAN, DIMYAN, MAGID, YOUSRI, JOSEPH, SAUL, JOSHUA, KRAKOW, WILLIAM, TOMPKINS, PEDERSEN, RICHARD, ALAN
Applicants: AMERICAN TELEPHONE & TELEGRAPH, AMERICAN TELEPHONE & TELEGRAPH COMPANY
Application year: 1986
Main classification: H03K19
IPC codes: G11C19, H03K5, H03K19