A SELF-SEQUENCING LOGIC CIRCUIT

Abstract: A programmable, sequential logic array for performing logical operations within a memory array (28), comprising: an input storage array (24) having addressable locations for storing input control words; input means (40,34) for receiving a plurality of input signals (on 38) and control words from said input storage array and producing signals indicating the relationship between conditions of said input signals and conditions represented by said control words; output means (36,38) for providing binary output signals; an output storage array (28) having addressable locations for storing output control words for controlling a state of said output means; a next address storage array (22) for identifying a next address from one of plurality of fields within said next address array; address generation means (46,30) for receiving address signals from said said next address storage array and for applying said address signals to address circuits of said input storage array, said output storage array, and said next address storage array; and coding means for coding status of lines comprising an input/output interface for selectively ignoring predetermined status conditions, control means connecting the input means to the output means and responsive to signals produced by the input means to enable the output means to respond to selected output control words to selectively change outputs, and a subroutine control random access storage array for providing signals to the control means to control execution of subroutines.

Description: The present invention relates to self-sequencing logic circuits implemented in random access storage. A self-sequencing logic circuit, if able to respond adequately to inputs is capable of performing controller functions within a greater combination of which it is a part. If implemented in random access storage it has, other things being equal, the potential for flexibility and change. If implemented as fixed logic circuits, it can be expected to be faster than a random access storage counterpart, if lacking in flexibility. There is much art in this area and the following are systems representative thereof, with accompanying comment in relation to the present invention as set forth in the claims. US-A-4,357,678 discloses an arrangement in which a random access memory is used for performing logic functions. However, the arrangement requires that the entire array be searched sequentially on each functional cycle, and this slows the operation considerably. Further, US-A-4,357,678 teaches a system which multiplexes inputs and outputs and does not provide for logic controlled feedback from output to input. US-A-4,348,737 includes a random access memory array for performing logic functions which requires an entire array to be searched sequentially once every functional cycle as does US-A-4,357,678. The logic array according to the present invention does not require a search of the entire array for each cycle as does the arrangement of either referenced patent and thus the array of the present invention provides a much faster operation than does either of the other arrangements. IBM Technical Disclosure Bulletin, Volume 17, Number 10 March 1975, page 2867, describes array logic implemented within a random access memory with a feedback system where the outputs directly generate the next address to be accessed in the RAM. The article describes an array logic RAM which is very restricted in its operation and does not provide the flexibility which is provided by the logic array of the present invention. US-A-4 075 707 discloses an extension to the kind of arrangement just described, increasing flexibility by providing three uses of - three definitions of the meaning of - the bit pattern currently output from the storage array. However there is still only the single storage array which still provides one output bit pattern per presented address. US-A-4,336,60l describes a rewritable program logic array which is dynamically alterable during processing by loading a word pattern of bit personalities to realise specific logic functions into memory cells of current mode logic by splitting a conventional RAM of current mode logic into two parts, a search part and a read part. The logic in memory for the AND functions on the array can be conducted by using one of the multi-emitters of a transistor in each current mode logic memory cell and an emitter of a referenced transistor in each of the sense drive circuits in the read mode of the rewritable program logic array. The structure according to US-A-4,336,60l requires a specific technology, namely CML, to implement the logic in memory functions whereas no specific technology is required to realise the present invention. US-A-4,237,542 describes a programmable logic array of the well-know type which does not employ a random access memory for its implementation as does the array in accordance with the present invention. US-A-3,8l8,452 describes a fusable link programmable logic array for use in designing digital systems. The patent does not teach the use of random access memory to perform logic functions as does the arrangement of the present invention. US-A-3,829,846 describes a multi-function logic module employing read only associative memory arrays. The logic system of the patent does not show the use of random access memories as does the arrangement of the present invention. CLARE, "Designing Logic Systems Using State Machines", 1973; McGraw-Hill Book Company, at pages 76-90, describes a programmable logic structure implemented in a random access memory. However, the various structures shown by CLARE are limited in application in that feedback between output and input must be hard wired for specific functions as compared to the feedback system of the present invention which is implemented by a feedback array. Further, the CLARE structure does not permit subroutines to be implemented as does the present invention. Additionally, Clare avoids the use of "don't care" conditions on inputs and "don't change" conditions on outputs by limiting operation to one (1) input line per state. That is, Clare sorts multiple simultaneous inputs with a hardware data selector and has no way of assuring that those input lines already tested, are still in the same state. Clare ignores inputs by selecting a tied input and treats outputs as full-width outputs without the ability to selectively change the same. Although the prior art shows similar functions and use of random access memory to implement program logic arrays, none of the prior neither individually nor in any combination thereof teaches the present invention as claimed herein. In particular, a fixed logic implementation can happily wait on the arrival of the next clock till whenever, whereas, a random access storage implementation, as in CLARE, for example, dies without a next address or is forced by timing constraints to a default address. Therefore, to obtain flexibility and the capacity to wait, the present invention provides a self-sequencing logic circuit comprising an input storage array having addressable locations for storing input control words; input logic receiving control words from the input storage array and also input signals and producing signals indicating the relationship between conditions represented by the input signals and conditions represented by the control words; output logic providing binary output signals; an output storage array having addressable locations for storing output control words for controlling the state of the output logic; a next address storage array identifying a next address from one of plurality of fields within the next address array; address generating logic receiving address signals from the next address storage array and applying such address signals to address circuits of the input, output and next address storage arrays; and control logic connecting the input logic to the output logic and responsive to signals produced by the input logic to enable the output logic to respond to selected output control words. Put another way, there is disclosed hereinafter a programmable, sequential logic array for performing logical operations within a memory array, comprising: an input storage array having addressable locations for storing input control words; input means for receiving a plurality of input signals and control words from said input storage array and producing signals indicating the relationship between conditions of said input signals and conditions represented by said control words; output means for providing binary output signals; an output storage array having addressable locations for storing output control words for controlling a state of said output means; a next address storage array for identifying a next address from one of plurality of fields within said next address array; address generation means for receiving address signals from said said next address storage array and for applying said address signals to address circuits of said input storage array, said output storage array, and said next address storage array; and control means connecting said input means to said output means and responsive to signals produced by said input means to enable said output means to respond to selected output control words. The present invention will be described further by way of example with reference to an embodiment thereof as illustrated, together with an example of one item of prior art, in the accompanying drawings in which:- Figure 1 is a block diagram of a prior art programmable logic array implemented by a combination of random access memory and read only storage; Figure 2 is a block diagram of one form of programmable logic system according to the present invention; Figure 3 is a logic diagram, partly in the form of a table, of one form of interface gating means used in the system of Figure 2; and Figure 4, in sections 1,2 and 3, is a circuit board lay-out diagram of the logic system of Figure 2. The selected example of a prior art logic array, shown in Figure 1, is that of Figure 5.15, page 81, of the referenced CLARE article and includes an address generator section and an output section. Part of the address generator section is located in the random access storage of the output section and includes a TEST field and a LINK field. The system is arranged to move to a state defined by LINK field T if the TEST field matches the qualifiers entered into a selector or, unavoidably, as an automatic default, to that state which is logically NEXT to the current state. CLARE also references (Figure 5.13) an alternative in which there are two LINK fields and no NEXT operation, but the parallel default limitation obtains. These prior art systems include a read only storage for decoding the addresses so generated. In either arrangement, CLARE indicated a preference for bit-sequential testing, so that, if an early bit has not settled, even though it is on the point of so doing, the arrangement will per force branch away from the path that the tested bit would have indicated. Turning to the present invention, illustrated in varying degrees of detail in Figures 2, 3 and 4, a array of four logical (though seven physical, see Figure 4) random access storage arrays 22, 24,26,28 are arranged, in combination with supporting logic, to perform the functions of a programmable logic array. The four RAM arrays 22, 24, 26 and 28 are all addressed in parallel by an output from address counter 20. The contents of the four arrays 22, 24, 26 and 28 are read out corresponding to the address contained in address counter 30. A functional cycle from input to output is comprised of two parts (an A-part and a B-part). In the A-part, the array contents pointed to by the address counter 30 are read, though not all necessarily used, and then, conditionally, in the B-part,the contents pointed to by the next consecutive address are similarly read, the address counter being updated by part thereof or returned to its A-part value. The values for updating the address counter come from the next state array 22, which is divided into portions A and B, where the A portion of the array stores a next address corresponding to a compare on the A-part of a cycle and the B portion of the array stores a next address corresponding to a compare on the B-part of a cycle. During the A- part of a cycle, the contents of input array 24, at location A thereof, are compared with input lines 38 bit by bit by exclusive OR (XOR) 40. Similarly, the contents of the corresponding A location of the feedback array 26 are compared, by XOR 42 with the current output on lines 32. If a true compare exists in both cases, XORs 40 and 42 both produce a true signal to AND gate 34. AND gate 34 produces a true signal to control gates 44 and 46 in respective data paths to the output 32 and the address counter 30. The contents of location A in output array 28 are gated to output register 36 by gates 44, and the contents of location A in the next state array 22 are gated by gates 46 to address counter 30. This results in the four arrays, 22, 24 26 and 28 being addressed at the A portion of a new current cycle. If the compare fails on either the input from lines 38 or feedback from lines 32, the address counter 30 is incremented by one and the B-part of the cycle is entered so that the counterpart B locations of the arrays 22, 24, 26 and 28 are selected. A compare on both input and feedback results in the B data being transferred to the output 32 and address counter 30. If the compare fails on either count in the B cycle, address counter is decremented by one and another A-B cycle is started at the same address location. This means that the current state remains unchanged until a full compare is obtained on some subsequent A-B cycle, and this depends on changes to the input on lines 38. The compare is shown in detail in Figure 3 and accompanying Table 1. Two bits, A1 and A2, are used in the input array 24 and feedback array 26 to represent one four-state functional bit as shown in Table 1. Table 1 describes the coding mechanism of the present arrangement which permits the selective ignoring of a predetermined status condition represented by code 00 (don't care) for bits A1 and A2. The other three states represent;- code 01 0, code 10 1, and code 11 no match, since for these paired state values, a compare is prohibited no matter what the input values are. Two bits are also used in output array 28 to change one functional output bit according to the following Table 2: Table 2 The result of the arrangement is that outputs can be made to change in response to inputs, in the same way as is done in a fixed circuit program logic array, and in a worst case time interval of twice the cycle time of the random access memory or erasable programmable read only memory used, which are nominally in the 70-300 nano-second range. The response time can be reduced to one array cycle if the number of arrays is doubled, allowing the A and B data to be in separate arrays. The detailed logic of the preferred embodiment of the present invention as described with reference to Figure 2 is shown in Figures 4.1, 4.2 and 4.3 Figures 4.1, 4.2 and 4.3 contain specific component and interconnection information and provide sufficient detail to enable a person skilled in the art to reproduce a logic system in accordance with the present invention.

Claims: A self-sequencing logic circuit comprising an input storage array (24) having addressable locations for storing input control words; input logic (40) receiving control words from the input storage array and also input signals (on 38) and producing signals indicating the relationship between conditions represented by the input signals and conditions represented by the control words; output logic (36) providing binary output signals; an output storage array (28) having addressable locations for storing output control words for controlling the state of the output logic; a next address storage array (22) identifying a next address from one of plurality of fields within the next address array; address generating logic (46,30) receiving address signals from the next address storage array and applying such address signals to address circuits of the input, output and next address storage arrays; and control logic (44) connecting the input logic to the output logic and responsive to signals produced by the input logic to enable the output logic to respond to selected output control words. A circuit as claimed in claim 1, further including an output state storage array (26) having addressable locations for storing output state definitions and output state logic (42), connected to the output (32) and to the output state storage array to test for the output to correspond to the addressed output state definition currently addressed in the output state storage array, together with AND logic (34), responsive to both the input logic and the output state logic, to enable the address generation logic when the input and output states meet the specified criteria. A circuit as claimed in claim 2, wherein the fields of the next address storage array identified by an address define sets of potential new addresses and a new address is generated by selecting one of a predetermined set of potential new addresses, the address generating logic including an address counter (30) and selective gating (46) connecting the output of the next address storage array to the address counter when enabled, the gating being enabled by the AND logic (34) if and only if there is a particular correspondence between the input, feedback and generated signals, or else, to dwell, without gating any output via control logic (44) until such a particular correspondence is detected. A circuit as claimed in either claim 2 or claim 3, wherein the selective gating is arranged to increment/decrement the address counter, if there is no detected correspondence, and to reset the address counter to the accessed value in the address storing random access storage, if correspondence is detected, the data of a set in any storage being located at logically adjacent addresses. A circuit as claimed in claim 4, wherein the output data in the output storage array (28) is similarly arranged and located by set. A circuit as claimed in any of claims 2 to 5, wherein the input storage array and the output state storage array are, or are effectively, comprised of four state cells, thus providing "don't care", "1", "0" and "no match" outputs.

Inventors: PEARSON, KENNETH ARNOLD, ZUCKER, LARRY REED
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: G05B19
IPC codes: H03K19, G06F7, G06F17