IMPROVEMENTS TO DIGITAL PHASE-LOCKED LOOP CIRCUITS

Abstract: The digital phase-locked loop circuit extracts the clock signal from a serial flow of coded data by operating so as to deter­ mine the phase of the received signal and comparing this phase with that of a locally-generated signal. The error signal obtained from the comparison is digitally filtered and used to correct the phase of local signal. Besides it is stored and used to effect corrections even in absence of the data flow at the input or in presence of a long zero sequences.

Description: The present invention relates to apparatus for data transmission systems and more particularly it refers to improvements to digital phase-locked loop circuits for synchronizing a local clock signal generated by a local oscillator with the frame of an input signal, comprising a transition detector of the input signal, a first counter of the local oscillator signal, started or blocked by the opposite transitions of the input signal, a second counter of the local oscillator signal, enabled by one kind of input signal transition to transfer the executed count to its output, a circuit, able to supply at its output signals relating to the sign of the phase difference between the local oscillator signal and the input signal, operating on counts executed by the first and second counters, and a digital filter of the signals relating to the sign of the phase difference, whose output signals are used to increment or decrement the second counter, in order to obtain at the output of the latter the regenerated clock signal. As known, a problem encountered in digital transmission between distant points (e.g. between a satellite and an earth station) or between near points (e.g. between a telephone exchange and a subscriber) is the receiver synchronization to the transmitter. This operation is required of every receiving apparatus to correctly estimate the electrical levels of the received signal. In fact the optimum sampling instant can be determined only by knowing signalling period boundaries, i.e. the period in which a single elementary information is transmitted. Said instant is the instant at which the effects of noise and distortions introduced by the transmission channel are minimum, and hence the probability of a correct estimate of the received symbol is maximum. This problem is resolved by the use of devices which automatically correct frequency differences and cause the signalling period of the received signal to coincide with that of the locally-generated signal, used as frequency reference. In this case, the information on the signalling period of the transmitted signal is extracted from the received data flow by the receiver, overcoming the distortions introduced by the channel and frequency and phase differences between remote and local clock generators. Once this information has been obtained a signal, duly-positioned within the signalling period, can be generated to estimate the logic level of the received signal. Up to now the device generally used has been the phase-locked loop (or PLL), consisting of a phase comparator, a loop filter and a controlled oscillator (e.g. a VCO = voltage-controlled oscillator). The phase comparator determines phase differences between the input signals and the local reference; the detected phase error is filtered, so as to reduce noise, and is sent to the controlled oscillator, which accordingly adjusts the frequency of the locally-generated signal. In the past these three components were implemented by analog techniques. With the coming of digital techniques a progressive introduction of digital devices into PLL has been noticed. First a sample-and-hold circuit was introduced after the filter, so as to permit the use of a digital VCO. Afterwards the phase comparator and the filter have been rendered digital, thus implementing an all-digital PLL, the socalled DPLL (digital phase-locked loop). In a type of embodiment of DPLL, the phase error is determined by evaluating the lead or the lag of the signal emitted by the local generator in comparison with that emitted by the remote generator: such estimate is effected whenever the received signal traverses predetermined electrical thresholds. The error signal, proportional in amplitude and sign to the phase difference, is filtered and used to perform the necessary corrections to the local generator. One of the main problems presented by these types of DPLL is that due to synchronism loss when there is a low content of level transitions in the received signal, more particularly when there are long sequences of equal symbols or when the same signal is absent on the line for short periods. That entails a delay in the detection of the optimal sampling instant at the arrival of the successive valid signals, owing to the time necessary to correctly extract the synchronism signal. A DPLL is known from US-A 4 280 099, which DPLL operates at a frequency n times the frequency of the input digital signal which is a digital signal having the non-return-tube-zero (NRZ) format. This system can not also operate on analog signals and particularly can not memorize the phase error to be used for corrections of the local oscillator frequency during long zero sequences, leading to the possibility of a respective malfunction. These disadvantanges are overcome by use of line encoders, which increase the number of transitions, with consequent increase in the information contents on the phase behaviour. However, a high number of transitions entails the necessity of accurately filtering the estimated error, in order to obtain a reliable value of the signal to be used for correcting the local generator. That allows jitter effect minimization. However, the filtering operation requires complex devices and algorithms, which is obtained to the detriment of convergence speed and integration ease. Another way of overcoming the disadvantage of synchronism loss is that provided for digital telephone exchanges in the connection with higher hierarchical level exchanges. Such method as described in "Synchronization system for telephone and data networks" by R.W. Slabon et alii, ISS81 pages 41.B 3.1-6, consists of storing the information on frequency difference between remote and local clock and using it in case of malfunctioning. The information and its management require, however, the use of a high-sized processor, owing to the foreseen use domain. The disadvantages above are overcome by the improvements to digital phase-locked loop circuits, provided by the present invention, which offer: possibility of integration without too large a number of gates; high jitter reduction; high resolution and rapid estimate of the received signal phase; possibility of use also with non-expensive frequency references (non selected quartz or ceramic oscillators); absence of initial or periodical adjustments; possibility of use of the device in different applications by duly dimensioning its parameters; possibility of operation also during a long absence of useful signal. The present invention is characterized in that it further comprises a counter of correction signals, incremented or decremented in function of the signs of the signals outgoing from the digital filter, a frame signal counter counting Nt frames, whose overflow signal enables correction signal counter to present at its output the count executed, and a logic circuit, which stores the count of the correction signal counter and presents at its output signals indicating the number and sign of corrections, uniformly time-distributed in the sequence of Nt frames on the basis of the counts at the correction-signal and frame-signal counter outputs, the correction signals supplied by the logic circuit being used to increment or decrement the second counter of the local oscillator signal. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawing in which: Fig. 1 is a block diagram of the circuit provided by the invention; Fig. 2 is a block diagram of the circuit denoted by LC in Fig. 1. The improvements to digital phase-locked loop circuits described hereinafter consist of real-time storage of the frequency difference between the remote and local clock, of its continuous updating and of its use in order to perform the necessary frequency adjustments to the local clock. The circuit thus improved presents three main operating phases: an activation phase a storage phase a normal operation phase. In the first phase the circuit performs solely the phase locking to input signal, operating as a normal digital phase-locked loop. The duration of such a phase depends on the speed at which the circuit phase-locks the input signal. The second phase begins when the incoming-signal phase has already been estimated and the corrections at the loop-filter output give actual information on the frequency difference between the remote and local clocks. This phase lasts Nt frames; Nt value must be long enough to allow a valid estimate of clock drift. At the end of Nt frames the number of corrections and its sign are stored to be used afterwards. In the third phase the circuit updates every Nt frames the estimate of the frequency difference and performs the already-stored additional corrections, uniformely distributed along Nt frames. As a consequence, during the normal operation it acts in two ways, performing phase estimate and correction, as well as a frequency estimate and correction. In the absence of transitions, phase corrections cease, but the circuit continues to operate by using the stored frequency. The block diagram of the phase-locked circuit according to the invention is shown in Fig. 1. The received signal, wherefrom timing is to be extracted, is present on wire 1 and the frame synchronism signal on wire 11. A threshold comparator CP receives at the input the signal on wire 1, compares it with a threshold voltage or with two symmetrical ones with respect to zero, depending on whether the signal is binary or is a three-level one, and supplies at the output on wires 2 and 3 the information relating to transitions of rising or falling edges of the pulses. A signal indicative of the rising-edge transition, present on wire 2, is used as a starting signal of a counter CC, which is stopped by a successive signal indicative of the falling-edge transition. This counter counts with modulus N, whose magnitude depends on the accuracy demanded in the phase estimate, the pulses supplied by the local clock on wire 4. Of course they present a frequency equal to N times the symbol frequency of the received signal. The clock signal on wire 4 accesses also a counter CB, still of modulus N, which freely counts and transfers the counted value to the output on connection 5 when the information relating to the falling-edge transition appears on wire 3. Counts supplied by CC and CB are then sent to a block OM, which executes the following operation err = N/2 - (B-C/2) where B and C denote the counts supplied by CB and CC respectively. The value err obtained represents the phase difference between the signal of local counter CB and the input signal. Block OM consists of two binary adders, the first of which adds count B to count C, which is sign-inverted and deprived of the least significant bit in order to execute a divide-by-two operation. The result is sent to the second adder, which inverts its sign and adds it to the predetermined value N/2. Only the sign bit of variable err is used, and sent through wire 7 to a variable-modulus up/down counter CD and stored. At each frame the counter is examined; if it has reached positive or negative overflow value, the corresponding signals are sent on wire 8 to counter CB, which is then decremented or incremented. Counter CD acts on phase error as a simple first-order digital filter. During activation and storage phases the counting modulus assumes a low value, while during the normal operation a higher value is used. In such a way the stability condition is quickly attained in the first two phases and a better filtering of the error signal is obtained in the third phase. In addition, an Nt modulus up/down counter CE is decremented or incremented at each frame, if counter CD has reached positive or negative overflow values. After Nt frames, hence, counter CE contains the number of positive or negative corrections performed. The enabling signal for CE is the overflow signal supplied on wire 10 by a counter CF, still with modulus equal to Nt. Counter CF counts the frame pulses sent on wire 11 and supplies the count obtained on connection 12, then it is reset. This connection goes to a logic circuit LC together with connection 14, on which there is the count effected by counter CE, and with wire 13 on which there is the sign bit of count of the same counter CE. Every Nt frames a convenient number of correction pulses, uniformely spaced in time, are made available at LC output on wire 8. Said pulses cause counter CB to decrement or increment and hence cause a frequency correction of the output signal on wire 16. In case of high frequency drifts between the oscillators, a correction pulse may appear on wire 8 at every frame. Counting modulus of counter CD is varied under the control of a counter CG, which emits a signal on wire 15 at the second overflow of counter CF on wire 10. In fact the intialization and the storage phases end at the first and second overflows respectively, and then the normal operating phase begins. The bit synchronism signal, useful to decode the received symbols, is extracted from counter CB when it attains value N/2 and is presented at the output on wire 16. Logic circuit LC is represented in detail in Fig.2. It is composed of a programmable counter CH, of two registers RA and RB, consisting of log₂ Nt cells, of as many AND gates A₁, A₂ ... A n and of as many differentiators D1, D2, ..., Dn as the register cells, and of an OR gate PO with the inputs connected to AND gate outputs. At the end of the storage phase the content of counter CE (Fig. 1) is stored in counter CH through connection 14. During the normal operating phase, on the contrary, every Nt frames counted by CF (Fig. 1) the sign of the count supplied by counter CE (Fig. 1) on wire 13 is examined and used to increment or decrement CH contents. The contents of CH is used to load register RA, but is inverted thus as to exchange the most significant bits with the least significant ones. Register RB is normally loaded with CF contents (Fig. 1), present on connection 12. The bits of the corresponding cells of the two registers are sent to as many AND gates A1, A2, ... An, and all the AND outputs to normal differentiators D1, D2, ... Dn, so as to supply pulse signals in correspondence with logic-level transitions. All the differentiator outputs are sent to an OR gate PO, at whose output there is a sequence of uniformely-spaced pulses, whose number is equal to the corrections to make within the Nt frames. The logic level of the pulses, whereupon increment or decrement of LC-controlled counters depends, is determined by the sign of the number contained in CH. When the signal, wherefrom synchronism signals are to be extracted, does not present a frame of its own, and hence the corresponding signals to be sent on wire 11 to CF input (Fig. 1) are not available, a suitable generator is to be added, capable of supplying signals with a suitable frequency with respect to the symbol frequency. It is clear that what described has been given only by way of non-limiting example. Variations and modifications are possible without going out of the scope of the invention.

Claims: A digital phase-locked loop circuit for synchronizing a local clock signal (4) generated by a local oscillator with the frame of an input signal (1), comprising a transition detector (CP) of the input signal, a first counter (CC) of the local oscillator signal, started or blocked by the opposite transitions of the input signal, a second counter (CB) of the local oscillator signal, enabled by one kind of input signal transition to transfer the executed count to its output (5), a circuit (OM), able to supply at its output (7) signals relating to the sign of the phase difference between the local oscillator signal and the input signal, operating on counts executed by the first and second counters, and a digital filter (CD) of the signals relating to the sign of the phase difference, whose output signals (8) are used to increment or decrement the second counter (CB), in order to obtain at the output (16) of the latter the regenerated clock signal, characterized in that it further comprises a counter (CE) of correction signals (8), incremented or decremented in function of the signs of the signals outgoing from the digital filter (CD), a frame signal counter (CF) counting Nt frames, whose overflow signal (10) enables correction signal counter (CE) to present at its output (14) the count executed, and a logic circuit (LC), which stores the count of the correction signal counter (CE) and presents at its output (8) signals indicating the number and sign of corrections, uniformly time-distributed in the sequence of Nt frames on the basis of the counts at the correction-signal (CE) and frame-signal (CF) counter outputs, the correction signals supplied by the logic circuit being used to increment or decrement the second counter (CB) of the local oscillator signal. A digital phase locked loop circuit as in claim 1, characterized in that said logic circuit (LC) comprises a programmable counter (CH), loaded with the count supplied by correction signal counter (CE) and incremented or decremented depending on the logic level of the signal representative of the count sign of the correction signal counter (CE), a first register (RA), loaded with a binary number obtained by inverting the bit positions of the number present at the output of said programmable counter (CH), a second register (RB) loaded with the count supplied by said frame signal counter (CF), a plurality of AND gates (A1, A2, ..., An), each having an input connected to the output of a cell of the first register and the other to the corresponding one of the second register, a plurality of differentiators (D1, D2, ..., Dn) connected to the outputs of said AND gates, and an OR gate (PO), whose inputs are connected to the outputs of the differentiators and whose output (8) is connected to the terminal to increment or decrement the second counter (CB). A digital phase-locked loop circuit as in claim 1 or 2, characterized in that said frame signals are extracted from the input signal. A digital phase-locked loop circuit as in claim 1 or 2, characterized in that said frame signals are locally generated.

Inventors: AMBROSIO, RENATO, MOGAVERO BRUNO, CARLO
Applicants: CSELT CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A.
Application year: 1986
Main classification: H04L7
IPC codes: H04L7, H03L7