HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING SAME

Abstract: A heterojunction bipolar transistor having excellent high-­ frequency characteristics is manufactured by forming a semi-­ insulating semiconductor layer on a collector (or emitter) layer, removing a part of the semi-insulating semiconductor layer to form a cut portion so that the collector layer is exposed at the cut portion, growing a base layer on the semi-insulating semi-­ conductor layer, on a slant wall of the cut portion and on the exposed part of the collector layer, and growing an emitter (or collector) layer on the base layer. A base layer may be preliminary formed on the semi-insulating semiconductor layer before forming the cut portion. Energy band gap of the emitter is greater than that of the base.

Description: 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor and a method of manufacturing the transistor. 2. Description of the Prior Arts Typically, any conventional npn-type bipolar transistor is provided with an n⁺-type collector which is formed on an n-type silicon substrate by means of epitaxial growth, a p-type base formed on the n⁺ collector by means of diffusion, and an n-type emitter formed on the p-type base either by means of diffusion or by applying alloy. Likewise, any conventional pnp-type bipolar transistor can also be formed in the manner similar to the above. Each of these bipolar transistors incorporates emitter, base, and collector, which are commonly made of a single semiconductive material, i.e., silicon. Operation speed of a transistor, which relates to the high-frequency characteristics, depends on the time constants for charging/discharging of emitter-base and base-collector junction capacitances and on the transit time of electrons between emitter and collector. Maximum oscillation frequency Fmax of a bipolar transistor is expressed as: Fmax = √ Ft/(8πRbCc) (1) where Ft: cutoff frequency Rb: base resistance Cc: collector capacitance Accordingly, the smaller the collector capacitance and the base resistance, the better the high-frequency characteristics is. Cutoff frequency Ft has a specific relationship with the transit time of electrons between emitter and collector, which is expressed as: Ft = 1/(2πτ) (2) τ = τe + τb + τc + τcc (3) τe (transit time of electrons through depletion layer of emitter) = Rb (Cc + Ce + Cp) τb (transit time of electrons through base) τc (transit time of electrons through collector) τcc (time needed for charging depletion layer of collector) = (Re + Rc) (Cc + Cp) where Ce: emitter capacitance Cp: parastic capacitance Re: emitter resistance Rc: collector resistance Consequently, the smaller the emitter capacitance, the shorter is the time needed for electrons to pass through emitter, thus resulting in improved high-frequency characteristics. As a matter of course, the narrower the base width, the shorter is the time needed for electrons to pass through the base, thus also resulting in improved high-frequency characteristics. Nevertheless, any of the conventional arts still fails to securely produce such a transistor having less junction capacitance and short base-width in addition to satisfactory ohmic contact by the simple structure based on the simplified manufacturing - method as described above. Therefore, it is not possible for the conventional arts to produce transistors featuring satisfactory high-frequency characteristics. Incidentally, it is known that satisfactory high-frequency characteristics can be securely obtained by a heterojunction bipolar transistor, in which the emitter is formed with a specific semiconductor having an energy band gap greater than that of the base to lower the base resistance. Typical heterojunction bipolar transistors are disclosed in No. US-A- 2,569,347, US-A- 3,413,533, US-A- 3,780,359, and an article entitled "Heterostructure Bipolar Transistors and Integrated Circuits" written by Herbert Kroemer, Proceedings of The IEEE, Vol. 70, No. 1, Pages 13 through 25, issued in 1982. The essence of these prior arts is to make up the band of the emitter-base junction by applying a properly selected material so that the band does not substantially act as a barrier to electrons but acts as a large barrier to holes which move from the base to the emitter. As a result, carrier density (hole density) of the base can be significantly increased. This effectively reduces the base resistance, thus realizing an extremely high maximum oscillation frequency Fmax. Typical one of this type of transistors incorporates emitter made of Al x Ga 1-x As, and base and collector which are respectively made of GaAs. However, the junction capacitance still remains large by merely lowering the base resistance. Further, if the base width is narrowed, the electrode cannot easily be drawn out and eventually the external base resistance will increase. Consequently, these heterojunction bipolar transistors cannot satisfactorily improve the high-frequency characteristics. Japanese Patent Publication No. 55-3829 discloses an improved method for extracting base electrode. In this method, n-type collector layer, p-type base layer and n-type emitter layer are respectively formed on a GaAs substrate by applying liquid-phase epitaxial method. Next, a part of the n-type collector layer is exposed by mesa etching, and then a p-type Al x Ga 1-x As layer is formed on the exposed part by liquid-phase epitaxial method for extracting base electrode. Thereafter, a collector electrode on the collector layer, a base electrode on the p-type Al x Ga 1-x As layer, and an emitter electrode on the emitter layer are formed. However, the method proposed by this prior art still has some problems. Concretely, a parastic junction capacitance produced between the emitter and the later-formed base-electrode-extraction p-type Al x Ga 1-x As layer will cause an increase of the junction capacitance between the emitter and base, and yet, no improvement is done for the junction capacitance between the base and collector. If the emitter were formed before forming the collector on the emitter, the junction capacitance between the base and collector would be reduced, but the junction capacitance between the base and emitter will increase, thus badly affecting the high frequency characteristics. An article entitled "GaAs/(Ga, Al)As Heterojunction Bipolar Transistors with Buried Oxygen-Implanted Isolation Layers" written by P. M. Asbeck et al., IEEE Electron Device Letters, Volume EDL-5, No. 8, pages 310-312 (1984) discloses a new structure and its fabrication process of a heterojunction bipolar transistor to reduce the base-collector junction capacitance and the base resistance. In this method, oxygen-implanted regions are fabricated between the external bases and external collectors by oxygen-implantation and thick external base regions are fabricated by Be ion-implantation. As the oxygen-implanted regions have less carrier density, the junction capacitance is reduced. Also, thick external base regions have less base resistance. Therefore the high frequency characteristics are improved. However, the method proposed by this prior art still has some problems. Concretely, the resistivity of the oxygen-implanted region is not as high as that of the epitaxially-grown region. Also, the resistivity of the Be-implanted region is not as low as that of the epitaxially-grown Be-doped region. U.S. Patent 4,380,774 discloses a new structure and its fabrication process of a heterojunction bipolar transistor to reduce the base-collector junction capacitance and the base resistance. In this method, boron-implanted regions are fabricated between the external bases and external collectors by boron-implantation, and thick external base regions are fabricated by Ge evaporation. As the boron-implanted regions have less carrier density, the junction capacitance is reduced. Also, thick external base regions have less base resistance. Therefore, the high frequency characteristics are improved. However, the method disclosed by this prior art has some problems. Concretely, the resistivity of the boron-implanted region is not as high as that of the epitaxially-grown region. Also, the resistivity of the Ge-evaporated region is not as low as that of the epitaxially-grown Be-doped region. As is clear from the foregoing explanation, it is quite difficult for any conventional art to securely produce transistors featuring small junction capacitance, narrow base width, and small external base resistance. Consequently, the transistors produced by the conventional arts cannot have fully satisfactory high-frequency characteristics. SUMMARY OF THE INVENTION In the light of the disadvantages inherent to the transistors manufactured by the prior art as described above, an object of the present invention is to provide a novel structure of a heterojunction bipolar transistor and a related manufacturing method, featuring small junction capacitance, narrow base width, small external base resistance, and easy base electrode extraction. To securely achieve the above object, the present invention provides a method of manufacturing a heterojunction bipolar transistor comprising the steps of: forming at least a collector (or emitter) layer on a semiconductor substrate; forming a semi-insulating semiconductor layer on said collector (or emitter) layer; removing a part of said semi-insulating semiconductor layer to form a cut portion so that said collector (or emitter) layer is partly exposed at said cut portion; epitaxially growing a base layer on said semi-insulating semiconductor layer to be a first external base layer, on slant wall of said cut portion to be a second external base layer, and one the exposed portion of said collector (or emitter) layer to be a base; epitaxially growing an emitter (or collector) layer on said base layer; and forming an emitter (or collector) electrode, a base electrode and a collector (or emitter) electrode on said emitter (or collector) layer at a portion in said cut portion, said first external base layer and said collector (or emitter) layer, respectively, wherein energy band gap of said emitter layer is greater than energy band gap of said base. Implementation of this method securely realizes a novel structure of heterojunction bipolar transistor, as defined in claim 1, featuring easiness of base electrode extraction, low external base resistance, extremely narrow base width, and small collector and emitter capacitances. The present invention will be better understood from the detailed description given hereinbelow in connection with the accompanying drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional diagram of a heterojunction bipolar transistor reflecting a preferred embodiment of the present invention; FIGs 2 through 4 are sectional diagrams showing structures in respective steps for manufacturing the heterojunction bipolar transistor in FIG. 1; and FIGs 5 and 6 are respectively sectional diagrams of heterojunction bipolar transistors reflecting other preferred embodiments of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Preferred Embodiment) FIG. 1 is a sectional diagram of a heterojunction bipolar transistor as a first preferred embodiment of the present invention. Referring to FIG. 1, the heterojunction bipolar transistor comprises a semi-insulating GaAs substrate 1, a first collector layer (which is substantially an electrode extraction layer) 2 of n⁺-type GaAs, a second collector layer 3 of n-type GaAs, a first base layer (which is substantially an electrode extraction layer or first external base layer) 4 of p-type GaAs, a second base layer 5 of p-type GaAs, a first emitter layer 6 of n-type Al x Ga 1-x As (where x = 0.3), a second emitter layer (which is substantially an electrode extraction layer) 7 of- n⁺-type GaAs, a collector electrode 8, a base electrode 9, an emitter electrode 10, and a semi-insulating GaAs semiconductor layer 11. In this structure, the second collector layer 3, the second base layer 5 and the first emitter layer 6 correspond to the so-called "collector", "base" and "emitter, respectively, of the transistor. Energy band gap of GaAs is 1.42 eV, and energy band gap of Al x Ga 1-x As (x > 0) is larger (e.g. 1.80 eV when x = 0.3) than that of GaAs. Therefore, in the above structure the energy band gap of the first emitter layer (emitter) 6 is larger than that of the second base layer (base) 5. This relationship is always satisfied under the condition of x > 0. Accordingly, as described before, carrier concentration of the base can be higher than that of the emitter, resulting in reduction of the base resistance. In this embodiment, carrier concentration of the emitter is 5 x 10¹⁷/cm³, and that of the base is 1 x 10¹⁹/cm³. Thickness of each layer is as follows: Semi-insulating GaAs substrate 1 400 µm n⁺-type GaAs first collector layer 2 400nm (4000 Å) n-type GaAs second collector layer 3 200nm (2000 Å) p-type GaAs first base layer 4 400nm (4000 Å) p-type GaAs second base layer 5 40nm (400 Å) n-type Al x Ga 1-x As first emitter layer 6 150nm (1500 Å) n⁺-type GaAs second emitter layer 7 150nm (1500 Å) Semi-insulating GaAs semiconductor layer 11 500nm (5000 Å) Note: Layers 2 through 7 and 11 are respectively formed by means of molecular beam epitaxy (MBE). Next, a method of manufacturing the FIG. 1 embodiment will be decribed. As shown in FIG. 2, layers 2, 3, 11 and 4 are formed to be the predetermined thicknesses on the semi-insulating GaAs substrate 1 using molecular beam epitaxy. Next, a resist mask 12 is formed on the layer 4 by conventional photolithography, and then, using the resist mask 12, as shown in FIG. 3, a part of the second collector layer 3 is exposed by partially etching the first base layer 4 of p-type GaAs and the semi-insulating GaAs semiconductor layer 11. This portion will hereafter be referred to as "cut portion". At this time, the second collector layer 3 may be partly etched as shown by a broken line in FIG. 3. The etching of the GaAs layers can be done by using a solution containing a mixture of H₂SO₄-H₂O₂-H₂O. By using a substrate having surface orientation (001) as the GaAs layers, the tilt angle of the etched slant wall surfaces of the layers 4 and 11 can be made smaller than 90°, more specifically nearly 45° as seen from the crystallographic orientation <110> as shown in FIG. 3. Next, the resist 12 is removed with acetone, and then the second base layer 5 of 40nm (400Å) p-type GaAs, the first emitter layer 6 of 150nm (1500Å) n-type Al x Ga 1-x As and the second emitter layer 7 of 150nm (1500Å) n⁺-type GaAs are grown in turn by molecular beam epitaxy as shown in FIG. 4. The grown-up second base layer 5 is formed on the exposed part of the second collector layer 3, the slant surfaces of the semi-insulating semiconductor layer 11 and the first base layer 4, and the upper surface of the first base layer 4. The part of the second base layer 5 formed on the exposed part of the collector layer 3 functions as a base, whereas the part of the second base layer 5 formed on the upper surface of the first base layer 4 functions as a first external base layer where the base electrode 9 will be formed. This first external base layer and the first base layer 4 jointly function as an external base resistor. The part of the second base layer 5 formed on the slant surfaces of the semi-insulating semiconductor layer 11 and the first base layer 4 functions as a second external base layer for electrically connecting the first external base layer and the part functioning as the base. Since the tilt angle is nearly 45°, the electrical connection can be secured satisfactorily. A variety of tilt angles can be obtained by properly selecting the crystal orientation and the wet-etching solution. However, it is quite necessary to grow the second base layer 5 on the slant surfaces without causing a disconnection between the part formed on the exposed collector 3 and the first base layer 4. To securely realize this, at least a part of the slant surfaces should be tilted less than 90°. This can be realized by properly combining the crystal orientation and the wet-etching solution. Next, the part where the first base layer 4 (which is substantially the electrode extraction layer) exists is partially etched by photolithography using a solution of a mixture of H₂SO₄-H₂O₂-H₂O so that the first and second base layer 4 and 5 and the first collector layer 2 are partially exposed. Next, the resist is removed with acetone. Thereafter, the emitter electrode 10 is formed on the second emitter layer 7 at the cut portion above the part functioning as the base (where the first base layer 4 and the semi-insulating semiconductor layer 11 have been removed. Further, the base electrode 9 and collector electrode 8 are formed on the exposed base layer 5 and collector layer 2, respectively. The electrodes 10, 9 and 8 are formed by ordinary photolithography, vacuum evaporation and heat treatment. According to the structure of the heterojunction bipolar transistor embodied by the present invention, collector capacitance Cc is the sum of the junction capacitance of the pn junction part between the layers 3 and 5 and the junction capacitance of the junction part between the layers 11 and 3. Generally, capacitance Cpn of the pn junction is expressed as follows: where A: area of the junction part q: charge N A1 : acceptor concentration of p-type semiconductor N D2 : donor concentration of n-type semiconductor ε₁: dielectric constant of p-type semiconductor ε₂: dielectric constant of n-type semiconductor, and Vb: bias voltage Accordingly, it is understood that, when a significant difference is present between the concentrations of acceptor and donor, the junction capacitance Cpn can be determined approximately by smaller one of the concentrations. In the first preferred embodiment of the present invention, the acceptor concentration of the p-type GaAs base layer is 1 · 10¹⁹/cm³ and the donor concentration of the n-type GaAs collector layer is 5 · 10¹⁶/cm³. Accordingly, the junction capacitance is approximately expressed as follows: On the other hand, since the acceptor concentration of the semi-insulating GaAs layer is at most 1 · 10¹⁵/cm³, the junction capacitance between the n⁺-type GaAs layer and the semi-insulating GaAs layer is proportional to the square root of this acceptor concentration, and thus the value of this junction capacitance is significantly smaller than that given by the formula (5). The ratio of these junction capacitances approximately corresponds to the ratio of the thickness of the depletion layer formed on the collector and the thickness of the semi-insulating semiconductor layer. In the present embodiment, since the thickness of the collector depletion layer is about 250nm (2500Å) and the thickness of the semi-insulating semiconductor layer is 500nm (5000Å), the collector capacitance at the portion where the semi-insulating semiconductor layer exists is reduced to one-half the case in which no semi-insulating semiconductor layer exists. Even when using a p-type Al y Ga 1-y As substrate instead of the p-type GaAs substrate, the junction capacitance, which is determined by the lower carrier concentration, remains almost unchanged. Due to those reasons mentioned above, by forming the semi-insulating semiconductor layer between the p-type GaAs layer for extracting the base electrode and the n-type GaAs collector layer as in the present embodiment, the collector capacitance can be significantly reduced. Emitter capacitance Ce in the present embodiment is proportional to the junction area of the re-grown emitter and the base. Since this junction area is identical to the mesa-etching area of the emitter, it can be determined by the dimensions of the photolithography mask, and can be set at the minimum dimensions of the mask. Since the emitter portion is processed by mesa etching, the structure of the present embodiment has a small parastic capacitance. Further, since energy band gap of the emitter is larger than that of the base, carrier concentration of the base can be made higher, and therefore the base resistance can be reduced. Further, the width of the present embodiment is extremely short, i.e., 40nm (400Å). The base transit time τb needed for electrons to pass through the base of a bipolar transistor is expressed as follows: τb = Lb/Ve (6) where Lb: base width Ve: velocity of electrons passing through the base Consequently, the high-frequency characteristics based on the base transit time of electrons can be improved drastically. In addition, since the base electrode extraction part (the first external base layer), whose thickness is a sum of those of the first base layer 4 and the second base layer (the base) 5, is thicker than that of the second base layer (the base) 5, the base resistance at this part, i.e. the external base resistance, can be extremely reduced. In other words, since the base is thinner than the first external base layer, the external base resistance can be reduced with maintaining the short base transit time. This also contributes to the improvement of the high-frequency characteristics. As was initially expected, the heterojunction bipolar transistor of the present embodiment showed a variety of advantageous features. First, the introduction of the semi-insulating semiconductor layer resulted in sharp reduction of the collector capacitance by about 43%. In addition, since the parastic capacitance is negligible and minimum dimensions of mask can be applied, the emitter capacitance was reduced. Furthermore, an ideal ohmic electrode could be formed on the extremely thin 40nm (400Å) base. Consequently, the base transit time was reduced by 70% compared with the conventional one with 150nm (1500Å) base width. Also, the external base resistance was reduced by 30%. As a result, when employing the same minimum dimensions, the heterojunction bipolar transistor of the present embodiment proved to have sharply improved high-frequency characteristics compared to any conventional heterojunction bipolar transistors, indicating sharp improvement of cutoff frequency Ft by about 25% and maximum oscillation frequency Fmax by about 56%. The first preferred embodiment has 40nm (400Å) base width for example. However, a still thinner base can be realized by applying molecular beam epitaxy. Furthermore, an extremely thin base can be produced also by applying metalorganic chemical vapor-phase epitaxy (MO-CVD) for example. In addition, the first preferred embodiment employ GaAs-Al x Ga 1-x As (x > 0), which is one of the group III-V compound semiconductors as the semiconductor. However, it is also possible to employ other group III-V compound semiconductor materials such, for example, as InP-InGaAs. When using InP-InGaAs, a heterojunction bipolar transistor with an emitter having a larger energy band gap than that of a base can be produced by using InP as the emitter material and In 0.53 Ga 0.47 As as the base material. In the first preferred embodiment, x = 0.3 as Al concentration is used, but, Al concentration can be chosen freely in the range of x > 0, in which energy band gap of Al x Ga 1-x As is larger than that of GaAs. Likewise, in the first preferred embodiment, GaAs is used for the semi-insulating semiconductor layer. It is suggested that, if Al y Ga 1-y As (y > 0), which has less dielectric constant than that of GaAs is used, the collector capacitance can be reduced more, thus eventually further improving the high-frequency characteristics. Dielectric constant of GaAs is 13.1, while that of AlAs (y = 1) is 10.1, for example. If y a 0 in Al y Ga 1-y As, it apparently is GaAs used in the first embodiment. Therefore, the material usable for the semi-insulating semiconductor layer can be generally expressed as Al y Ga 1-y As (y ≧). Also, the first preferred embodiment has n-type emitter and collector, and p-type base. It is also possible to replace the emitter and collector by the p-type and the base by the n-type. (Second preferred embodiment) The first preferred embodiment has a structure in which the collector was formed before forming the emitter above it. This relationship can be reversed by first forming the emitter before forming the collector above it. Such a structure is shown in FIG. 5. Only the positions of the emitter and the collector are reversed, whereas exactly identical structure and production method are applied to the remaining parts. The same description can be applied to this second embodiment by merely exchanging the emitter capacitance with the collector capacitance in the foregoing description. In other words, in the second preferred embodiment the emitter capacitance can be sharply decreased by the presence of the semi-insulating semiconductor layer, and the collector capacitance is determined by the minimum dimensions of the mask, and yet, reducing the parastic capacitance. The second preferred embodiment introduces the exactly same effects as to the base resistance and the extraction of the base electrode as those in the first preferred embodiment. As a result, the second preferred embodiment proved to have achieved significant improvement of the high-frequency characteristics almost identical to the first preferred embodiment. (Third preferred embodiment) The first preferred embodiment provides a method which forms the first base layer preliminarily on the semi-insulating semiconductor layer. However, even if this layer is absent, the third preferred embodiment provides the identical effect of improved junction capacitance. The structure of the third preferred embodiment shown in FIG. 6 can be produced by applying the same method as the first preferred embodiment except that the first base layer is not formed. Compared with any of the conventional heterojunction bipolar transistors available today, the third embodiment also sharply decreases the junction capacitance, so that it also proved to have significantly improved high-frequency characteristics.

Claims: A heterojunction bipolar transistor comprising: at least a collector (or emitter) layer (3) provided on a semiconductor substrate (1); a semi-insulating semiconductor layer (11) provided on said collector (or emitter) layer, said semi-insulating semiconductor layer having a cut portion where said semi-insulating semiconductor layer is partly removed so that said collector (or emitter) layer is partly exposed; a base layer (5) provided on the exposed portion of said collector (or emitter) layer; a first external base layer (4) provided on said semi-insulating semiconductor layer; a second external base layer (5) provided on a slant wall of said cut portion of said semi-insulating semiconductor layer and connecting said base layer and said first external base layer; and an emitter (or collector) layer (6) formed on said base layer, wherein the energy band gap of said emitter layer is greater than the energy band gap of said base layer. The heterojunction transistor according to claim 1, wherein group III-V compound semiconductor material is used for said layers (3-6, 11). The heterojunction bipolar transistor according to claim 1, wherein Al x Ga 1-x As (x > 0), GaAs and Al y Ga 1-y As(y ≧ 0) are used for said emitter layer (3, 6), said base layer (5) and said semi-insulating semiconductor layer (11), respectively. The heterojunction bipolar transistor according to claim 1, wherein said base layer (5) is thinner than said first external base layer (4). A method of manufacturing a hetero-junction bipolar transistor comprising the steps of: forming at least a collector (or emitter) layer (3) on a semiconductor substrate (1); forming a semi-insulating semiconductor layer (11) on said collector (or emitter) layer; removing a part of said semi-insulating semiconductor layer to form a cut portion so that said collector (or emitter) layer is partly exposed at said cut portion; epitaxially growing a base layer (4, 5) on said semi-insulating semiconductor layer to be a first external base layer (4), on-slant wall of said cut portion to be a second external base layer (5), and on the exposed portion of said collector (or emitter) layer to be a base; epitaxially growing an emitter (or collector) layer (6) on said base layer; and forming an emitter (or collector) electrode (10), a base electrode (9) and a collector (or emitter) electrode (8) on said emitter (or collector) layer at a portion in said cut portion, said first external base layer and said collector (or emitter) layer, respectively, wherein energy band gap of said emitter layer is greater than energy band gap of said base. The method according to claim 5, wherein said first external base layer (4) is preliminarily formed on said semi-insulating semiconductor layer (11) before forming said cut portion, said cut portion being formed by removing a part of said first external base layer and said semi-insulating semiconductor layer. The method according to claim 6, wherein GaAs and Al y Ga 1-y As (y ≧ 0) are used for said first external base layer (4) and said semi-insulating semiconductor layer (11), respectively, and wherein said cut portion is formed by wet etching. The method according to claim 6, wherein group III-V compound semiconductor material is used for said layers (3-6, 11). The method according to claim 6, wherein Al x Ga 1-x As (x > 0), GaAs and Al y Ga 1-y As (y ≧ 0) are used for said emitter layer (3, 6), said base layer (4, 5) and said semi-insulating semiconductor layer (11), respectively. The method according to claim 5, wherein Al y Ga 1-y As (y ≧ 0) is used for semi-insulating semiconductor layer (11), and wherein said cut portion of said semi-insulating semiconductor layer is formed by wet etching.

Inventors: EDA, KAZUO, INADA, MASANORI, OTA, YORITO
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1986
Main classification: H01L29
IPC codes: H01L21, H01L29