N CHANNEL MOS TRANSISTOR WITH LIMITATION OF PUNCH-THROUGH EFFECT AND FORMATION PROCESS THEREOF

Abstract: The zone of the substrate (1) between the two source and drain areas (10,11) and the zones (9) around said areas are implanted in depth with high-concentration P dope. In this manner the possibility of punching through is greatly limited without alteration of the electrical character­ istics of the transistor. The transistor can be the conventional or the LDD type.

Description: The present invention relates to an N channel MOS transistor with limitation of punch-through effect and formation process thereof. By punch-through effect is meant direct con­ duction between source and drain areas which occurs by interaction of the emptied zones near sources and drains when supply voltage is too great for the transistor. The current trend is to use very small N channel transistors (1.5 µm) maintaining a relat­ ively high supply voltage (5 volt). Transistors of this size made with conventional structures and processes (NMOS H2 type) have punch-through voltages near supply voltage so that the possibility of punching through is quite high. The situation cannot be improved by increasing the dope concentration in the substrate because this is known to result in detrimental effects for MOS devices from other viewpoints. A known compromise solution is to increase the P doping concentration only in the zone between the joints, between the source and drain areas, leaving unchanged the rest of the substrate. This is achieved in particular with a double implan­ tation of boron with two different energies which gives rise to a high-concentration layer of the desired depth. But this is a basically unsatis­ factory solution because if the high-dope surface layer is too thin it cannot contain the widening of the zones emptied in the sparingly doped part of the substrate, resulting in the possible interaction and passage of punch-through current in depth. If the high-concentration zone is deepened there is a return to the drawbacks which prevent the use of a highly doped substrate. Also known is increasing the concentration of P dope around the source and drain areas, thus creating D-MOS type structures, since it is between these two areas that interaction takes place. But in this case there is surface formation between the two joint areas of adjacent zones with different P doping which create control and threshold voltage determination problems. In view of this state of the art the object of the present invention is to accomplish an N channel MOS transister capable of displaying marked limitation of the punch-through effect, i.e. high priming voltage of the direct conduction between the source and drain areas without the drawbacks of known solutions. In accordance with the invention said object has been achieved by means of an N channel MOS transistor comprising a substrate with low P doping and two source and drain areas with N doping separated by a surface zone of the sub­ strate which describes the N channel characterized in that the surface zone of the substrate between the two source and drain areas and the deep zones around said areas are implanted with high-concen­ tration P doping. In this manner the device has on its surface a uniform concentration of P dope in the substrate zone lying between source and drain and zones with high concentration of P dope surrounding the source and drain regions to contain the extension of the emptied zones. It appears clearly that the device in accor­ dance with the invention is the fruit of an appropriate and advantageous combination of the teachings of the two known solutions described above. In this case the higher concentration of P dope accomplished in depth in the zone between the source and drain areas prevents the higher con­ centrations of said dope around the aforesaid areas from modifying and making uneven the surface concentration in the channel area. The threshold voltage is thus well defined and easily con­ trolled. It is important to note that the innovative characteristics of the device in accordance with the invention lend themselves not only to a conventional transistor but also to an LDD (low doped drain) transistor, which is currently used for many applications. This makes it possible to considerably broaden the area of application of the present invention. In accordance with the invention there has also been developed a process for formation of the aforesaid device which will be described in detail below as an example with reference to the annexed drawings wherein: FIGS. 1-6 show the various stages of a process in accordance with the invention for the formation of a conventional N channel MOS transistor accom­ plished with the requisites of limitation of the punch-through effect in accordance with the pres­ ent invention; and FIGS. 7-8 show variants of the above process for formation of an LDD transistor still having the aforesaid requisites. FIG. 1 shows a substrate 1 with low P⁻ doping on which were deposited preliminarily a layer 2 of silicon oxide and a layer 3 of silicon nitride. By means of etching and with the aid of appropriate photoresistive masking the dual layer of oxide-nitride 2-3 is limited to a restricted area as illustrated in FIG. 2 at the sides of which is implanted insulating boron indicated by the sign +. Then field oxidation, removal of residual nitride and gate oxidation are performed in succession to obtain the structure shown in FIG. 3 which consists of a low P⁻ doping substrate 1 with insulating implantation 4 and a layer 5 of silicon oxide with enlarged areas 6 which are termed field oxide. The zone of the substrate 1 between the field oxide areas 6 is then subjected to implantation of channel boron 7 (high concentration P doping) and depositing of a layer of polysilicon 8 (FIG. 4). By means of etching and with the aid of appropriate photoresistive masking the polysilicon 8 is removed outside a restricted central gate area at the sides of which in alignment with the residual polysilicon and the oxide areas 6 is performed implantation of high energy and con­ centration boron 9 (P doping) which penetrates deeply in substrate 1 as shown in FIG. 5. Implantation energy is selected in such a manner as to reach a depth greater than that of the previous implantation 7. Finally, again between the aforesaid areas, implantation of arsenic is performed to form source and drain areas 10 and 11 which produces the final structure illustrated in FIG. 6. According to this structure the zone 7 of the substrate between the two source and drain areas 10 and 11 has high P doping and the zones 9 around the areas 10 and 11 are doped in a similar manner. This limits the punch-through effect and at the same time ensures preservation of the normal electrical characteristics and in particular con­ trol and setting of the threshold voltage. The transistor illustrated in FIG. 6 obtained at the end of a process which may be considered conventional up to the stages of FIG. 4 and new in the succeeding stages is an N channel MOS transis­ tor of basically conventional type apart from the limitation of the punch-through effect introduced in accordance with the present invention. It is possible however to foresee application of the principles of the invention to an LDD (low doped drain) transistor which in this case after the stage shown in FIG. 6 has silicon oxide side spacers 12 (FIG. 7) at the sides of which is performed another high-concentration arsenic im­ plantation 13 (N⁺). In this manner the final structure illustrated in FIG. 8 is obtained. It should be noted that while the process described with reference to the drawings is basically an N-MOS process nothing prevents the main steps of said process as illustrated in FIGS. 5-6 being fully applicable with comparable results to the accomplishment of an N channel transistor in a CMOS technology.

Claims: 1. N channel MOS transistor comprising a substrate with low P doping (1) and two source and drain areas (10, 11) with N doping separated from a surface zone (7) of the substrate (1) which describes the N channel characterized in that both the surface zone (7) of the substrate (1) between the two source and drain areas (10, 11) and the deep zones (9) around said areas (10, 11) are implanted with high concentration P doping. 2. Process for the formation of a transistor in accordance with claim 1 comprising preparation of a low P⁻ doping substrate (1) with superimposed field oxide (2), implantation of high-concentrat­ ion P dope (7) in a superficial part of said substrate (1), superimposition of a gate area (8) on a central zone of said substrate part with P doping (7), deep implantation of dope P (9) at the sides of said gate area (8) and beneath said implantation of P dope (7) in said surface part of the substrate, and implantation of N dope (10, 11) at the sides of said central zone of the substrate and above said deep implan­ tation of P dope (9). 3. Process in accordance with claim 2 for formation of an LDD transistor in accordance with the present invention characterized in that it comprises the subsequent formation of spacers (12) at the sides of the gate area (8) and implantation of N⁺ (13) dope in the substrate (1) at the sides of said spacers (12) and above said deep implantation of P dope (9).

Inventors: CAPPELLETTI, PAOLO, TOSI, MARINA
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1986
Main classification: H01L29
IPC codes: H01L29, H01L21