A PCM recording and reproducing apparatus

Abstract: A pulse code modulated (PCM) data recording apparatus is modified to facilitate hand-cut edition of data recordings. The order of data recorded in blocks is chosen to increase the "cross-fading" interval that may be provided during the editing of PCM recordings to enhance the ability for burst-error correction. Data interleaving is provided so that as data is recorded on a number of parallel recording tracks (1 to 8) of a recording medium, odd number designated data (W₁, W₃, ... W₁₁) is each preceded by a corresponding delayed odd number designated data (W₁′, W₃′, ... W₁₁′) on each respective track (5,6,... 4), and correction data (C₃, C₁) is spaced between even number designated data (W₀,W₂,... W₁₀) and odd number designated data (W₁, W₃, ... W₁₁).

Description: The present invention relates to a method of pulse code modulation (PCM) recording, recording apparatus therefor recording tapes bearing recorded data and reproducing apparatus therefor. The problem of correcting interpolating and smoothing signals reproduced from hand-cut edited i.e. spliced recorded tape is addressed and is resolved by providing a modified recording format compatible with an increase in the cross fading period in which smoothing is applied. By way of background reference will first be made to a PCM recording and reproducing apparatus of conventional construction. This is shown in figure 1. In the apparatus shown two channels of analogue signals are input via terminal 9 to an analogue digital converter 10. This analogue digital converter 10 is followed by an encoder circuit 11 and a track sharing circuit 12. The output side of the tracking sharing circuit 12 is connected to a number of separate track channels in each of which there is provided: a respective modulation circuit 13, 14 to 15; a respective recording amplifier 16, 17 to 18; and a respective recording head 19, 20 to 21. In the reproducing part of this apparatus there are provided a like plurality of track channels each of which comprises: a respective reproduction head 22, 23 to 24; a respective reproduction amplifier 25, 26 to 27; a respective demodulation circuit 28, 29 to 30; and a respective time axis correction circuit (hereinafter referred to as a "TBC circuit") 31, 32 to 33. The respective track channels are connected to a decoder circuit 34 which in turn is connected to a digital to analogue converter 35. This digital to analogue converter 35 is connected to an analogue signal output terminal 36. Description of operation of this apparatus will now be given. Firstly, in the recording part of the apparatus, an analogue signal input at the input terminal 9 is converted into digital data by the analogue to digital converter 10 and error correction and detection codes C2 inspection data and C1 inspection data, respectively, are added thereto by the encoder circuit 11 to provide means of detecting and correcting errors such as might arise from imperfections in the recording tape. A control signal is added to the encoded signal by the track sharing circuit 12 and encoded signals are shared amongst the plurality of track channels. In these track channels the respective encoded signals are modulated by the modulation circuits 13, 14 to 15 and the pulse code modulated (PCM) data produced is of a form which is suitable for recording the same onto recording tape. Synchronisation and control signals are added and the respective PCM signals are recorded on the tape via the recording amplifiers 16, 17 to 18 and the recording heads 19, 20 to 21. In the recording part of the apparatus, signals reproduced by the reproduction heads 22, 23 to 24 are amplified by the reproduction amplifiers 25, 26 to 27 and the synchronisation signals are detected and protected by the demodulation circuits 28, 29 to 30 and clocks are reproduced. Those clocks and the data from which the synchronisation signals are separated are sent to the TBC circuits 31, 32 to 33. In the TBC circuits 31, 32 to 33 jitters and wow flutters are removed from the reproduced data, and the data is sent to the decoder circuit 34. In the decoder circuit 34 error detection and correction of the data is conducted making use of the C1 and C2 inspection data. This data is converted into analogue signal by the digital to analogue converter 35 and is output from the output terminal 36. It is noted that the control signal is used for control of emphasis and clock frequency. A clock signal is sent to the analogue to digital converter 10 and the digital to analogue converter 35 and clocks of other frequency from a clock generator 37 are applied to the track sharing circuit 12 the modulation circuits 13, 14 to 15 and the TBC circuits 31, 32 to 33. Reference will now be made to the frame and block construction of PCM data time shift and convolution interleave patterning encoder circuit arrangement and illustrated concept of cross fading shown in figures 2 to 6. Figures 2, 3 and 6 are reproduced from a paper entitled "On the signal format for the improved professional use two channel digital audio recorder" which was presented at the 79th Convention, 1985, October 12 to 16 organised by the Audio Engineering Society, pp 1 to 8 (Reference 1). Typical frame and block construction of PCM recording data is shown in figures 2(a) and (b), respectively. The frame construction comprises a total of 360 bits including 16 bits of synchronisation signal, 8 bits of control signal, 320 bits of PCM data or C2 inspection data and 16 bits of C1 inspection data. The block configuration shown is for an eight track recording tape and is compiled from six frames of PCM data and two frames of corresponding C2 inspection data. It is noted that the PCM data and corresponding C2 inspection data is not frame constituted in order of appearance but is time shifted and interleaved so as to diversify burst errors which occur due to dropouts such as occur during reproduction. Figure 3 shows the time shift and interleave pattern. A/D converted data is generated in the order W o , W₁, W₂,... These reference characters W refer to one word of data which in this case is of 32 bits comprising sixteen bits from each of the two input channels. The PCM data shown with dashes W₁', W₃', ..., W₁₁' are antecedent words of data which precede each of the odd data words W₁, W₃, ... W₁₁ by a time interval of d₁. Reference characters C₀, C₁, C₂ and C₃ represent the C2 inspection data generated from even data W₀, W₂, .., W₁₀ and antecedent odd data W₁', W₃', .., W₁₁'. Figure 4 shows the data time shift and convolution interleave delay sequence. The time shifting and convolutional interleaving operation will now be described with reference to this figure. First of all, the A/D converted data are separated by alternate application of a time delay d₁ into even designated data W 12i , W 12i+2 , ... and delayed odd data W 12i+1 , W 12i+3 , ... Following this separation the even data and the delayed odd data are encoded to produce corresponding C2 error correction data. In the present case n = 4 error correction data codes C 4i+3 , C 4i+2 , C 4i+1 and C 4i are produced for every twelve successive data words W 12i to W 12i+11 . Subsequently the delayed odd data and two out of four data codes C 4i+3 and C 4i+1 are delayed by a further delay d₂. Various delays d₃ to seven d₃ are then applied to the data words and correction codes as shown in figure 4. In particular integer multiples 0, 1 and 2 of the interleave delay d₃ are applied to the first three even data words W 12i , W 12i+2 and W 12i+4 , respectively and to the first three odd words W 12i+1 , W 12i+3 and W 12i+5 , respectively. Multiple increments 4, 5 and 6 of the interleaved delay d₃ are applied to the remainder even data words W 12i+6 , W 12i+6 , W 12i+8 and W 12i+10 , respectively and the odd data words W 12i+7 , W i2i+11 , respectively. A multiple increment 3 of the interleave delay d₃ is applied to two of the error correction codes C 4i and C 4i+1 and the multiple increment 7 of the interleave delay d₃ is applied to the remainder two error correction codes C 4i+2 and C 4i+3 . The convolutional interleave encoding of each succession i of the twelve data words W 12i to W 12i+11 is performed in a cycle period T and the time shift delays d₁ and d₂ and interleave d₃ have in this case the values 20T, 160T and 20T, respectively. It is noted that the time interval spanning the compilation of an entire frame or block is 5T. Respective frame timings 0 to 60 are shown in figure 3. The data is arranged as shown in figure 3. The even number PCM data and the odd number PCM data are time shifted apart from each other to enable correction by mean value interpolation using previous and following data values and this can accommodate burst errors arising. Furthermore, both even data and odd data are dispersed by different multiple increment interleave delays. This is so that abnormal sounds are not generated when odd and even data are corrected when it is not possible to make correction by reference to the C2 correction data. In the time shift and interleave pattern shown in figure 3 the order of presentation is one in which three even data words W₀, W₂, W₄ are followed by the first error correction code C₀ in turn followed by a remainder three even words W₆, W₈, W₁₀. The last even data word W₁₀ is followed by a second error correction code C₂. After a separation delay this code is followed by the first three odd words W₁, W₃ and W₅ a spacing interval and the remainder three odd data words W₇, W₉ and W₁₁. The remainder two error correction codes C₁, C₃ are synchronous with the third odd data word W₅ and the sixth and last odd data word W₁₁, respectively. It is noted that the spacing between the last even word W₁₀ and the first odd data word W₁ is twelve frames or 60 T. Figure 5 shows a block diagram of the encoder circuit 11 of the PCM recording and reproducing apparatus just described. This comprises a memory 65, a memory control circuit 66 arranged to control operation of the memory and encoders 67 and 68 for generating error detection codes, i.e. C1 inspection data and error correction codes, i.e. C2 inspection data. These encoders are subject to control by the memory control circuit 66. In order to simplify the memory control circuit 66 it is desirable that the capacity of the memory is divided into 61 block portions and that the data from the A/D converter 10 are successively recorded at the positions of W₀, W₁, W₂ ... as shown in figure 3. In this system, the C2 encoding is then conducted by taking out the data in the order W₀, W₁, W₂ from the memory 65 thereby to conduct C2 encoding and the C2 inspection data produced is then stored in the memory 65. Several frames of C2 encoded data are stored and C1 encoding is conducted by the C1 encoder 67 to generate the C1 inspection data. The encoded data C2 is sent to the track sharing circuit 12. The properties of this conventional PCM recording and reproducing apparatus will now be described. As apparent from figure 3 the C2 encoded data is diversified to 61 blocks at equal intervals, i.e. every four blocks from the error correction ability when an error is generated at every block becomes that of sixteen blocks because four errors can be corrected in the case where the error is detected by the C1 code and corrected by the C2 code. For example, in such a case where the Reed Solomon code on a Galoia field (2⁸) dealing with eight bits as one unit (one symbol) is used as the C₂ error correction code. Figure 6 shows how hand cut editing is treated. Suppose two recording tapes are connected together at a splice point. When reproduction is conducted, tape 1 on the left is reproduced in the order from usual reproduction section A through an error correction section B and finally an error correction section C. Conversely the signal reproduced from the second tape, tape 2, is reproduced in the reverse order to that above, i.e. from error correction section C to error correction section B to the usual reproduction section A. Herein, the error correction section B is a section where the original signal can be recovered by conducting an error correction reliant on detection by the C1 error detection codes and correction using the C2 correction codes. Error correction section C is a section where errors are corrected by interpolation based on adjacent even data or odd data. Error correction sections C overlap as can be seen in figure 6. By conducting a fade-out of the signal of the first tape, tape 1, and a fade-in of the signal of the second tape, tape 2, and summing both signals, a "cross-fading" is performed and by this means the reproduced signal in the vicinity of the splice can be smoothed. The section over which this cross-fading can be conducted is determined by the data arrangement. As mentioned the interval between the last even word and the first odd word amounts to twelve blocks only in the arrangement shown. Specific values of the parameters will now be mentioned. Thus, for a sampling frequency of 48 kHz and a frame constituted of 10 x 2 and data words arranged on six tracks, the frequency of one block becomes 48/(10x6) = 0.8 kHz. Accordingly the time interval of twelve blocks cross-fading is 12/0.8 = 15 milliseconds. Actually errors are generated in the neighbourhood of the splice and this time interval is truncated even further. In summary, in the conventional PCM recording and reproducing apparatus described only twelve blocks can be taken as the cross-fading section for accommodating hand cut editing. The apparatus described cannot cope with a situation where a longer cross-fading time is required. A different arrangement of data words and error correction codes is disclosed in GB-A-2082356 (Reference 2). As therein disclosed the PCM data is arranged in the order of even data words, error correction codes, and odd data words. The application of this arrangement to splice editing of PCM recorded tape is suggested. The PCM data sequence is divided into even data and odd data sequences and separate error correction encoding is provided with respect to each of these sequences. One of the data sequences is then delayed a predetermined time with respect to the other data sequence. The distance between adjacent odd words and the distance between adjacent even words is then increased by applying the disclosed technique to each sequence. The present invention is intended as a solution to the problems aforesaid and as an alternative to the method, apparatus and formatted recording tape disclosed in Reference 2. In particular it is intended to increase the time interval over which cross-fading can be performed within a constraint of not increasing memory capacity. A method of pulse code modulation (PCM) recording, a recording apparatus, a recording tape, and a reproducing apparatus each in accordance with the present invention are defined in claims 1, 6, 12 and 14. The preamble of each of these claims is directed to Reference 1. In the preferred embodiment of the invention described below, the burst error correction ability is not lowered below that achieved in the arrangement described in Reference 1. The above defined method is applicable not only to a situation where the error correction codes are separated into two equal numbers n₁, n-n₁ but in general. The most advantage effects are obtained when the first delay d₁ and the incremental interleave delay, third delay d₃ are related as follows: d₁ = (n-n₁) x d₃ with the proviso that the second time shift delay d₂ and the incremental interleave third delay d₃ are unequal d₂ ≠ d₃. In the accompanying drawings: Fig. 1 is a block diagram showing a multi-track PCM recording and reproducing apparatus of conventional construction; Fig. 2 is a diagram showing a frame/block construction of a PCM recording and reproducing apparatus which is known and which is employed in the preferred embodiment; Fig. 3 is a diagram showing a conventional time shift and interleave pattern for the arrangement of data on tape; Fig. 4 is a diagram showing an encoding and data interleaving sequence for the pattern shown in the previous figure; Fig. 5 is a block diagram showing an encoder circuit of a conventional PCM recording and reproducing apparatus; Fig. 6 is a diagram showing how signal can be reproduced when handcut editing has been performed; Fig. 7 is a diagram showing a time shift and interleave pattern embodying the present invention; and Fig. 8 is a diagram showing an encoding and data interleaving sequence for obtaining the pattern shown in the preceding figure. A description of a preferred embodiment of the invention now follows. This description is given by way of example only. In this preferred embodiment the frame and block construction adopted is that shown in and described with reference to figure 2. Figure 7 shows the time shift and interleave patent of PCM data recorded on tape. In the arrangement shown two C2 inspection data, i.e. error correction codes C₃ and C₁ are arranged following all six of the dispersed even data words W₀, W₂, ..., W₁₀. Each of the even data words and these two error correction codes are spaced by four frame/block intervals each. After a delay of a further twelve frame/block intervals error correction code C₁ is followed by the first even data word W₁. All six odd data words follow from this point in time at equal intervals of four frame/block spacing. The remainder two inspection data, i.e. correction codes C₂ and C₀ also are delayed and are coincident with the last but one and last of the six odd data words, i.e. data words W₉ and W₁₁. It will be noted that the spacing between the last even word W₁₀ and the first odd word W₁ amounts to as many as 20 frame/block intervals, i.e. 100 T. This it will be noted is a much increased period available for cross-fading. The method of generating the data pattern of figure 7 will now be described with reference to figure 8 which shows the encoding and the data interleaving sequence of this embodiment. First even data words (W 12i , W 12i+2 , .., W 12i+10 ) and odd data words (W 12i+1 , W 12i+3 , .., W 12i+11 ) are separated by a first delay of d₁ which is applied alternately to the sequence of data words W 12i to W 12i+11 . In figure 7, the antecedent odd data words, i.e. those which precede each of the odd data words W 12i+1 , W 12i+3 , .. W 12i+11 , are denoted by dashes: W₁', W₃', ... W₁₁'; ... Following this C2 encoding is conducted against the even data and the antecedent odd data and a number n, in this embodiment n=4, of C2 inspection data, i.e. error correction codes C 4i+3 , C 4i+2 , C 4i+1 , and C 4i are generated. Subsequently a further and second time delay d₂ is given to the delayed odd data W 12i+1 , W 12i+3 , .., W 12i+11 and a selected number (n-n₁), in this embodiment two, of the C₂ inspection data, i.e. two correction codes C 4i+2 and C 4i . Subsequently integer multiple increments of the interleave and third delay d₃ integer multiples 0 to 7 as shown in figure 8 to obtain the data arrangement shown in figure 7. The pattern of data interleaving is repeated once every twelve data words. It is noted that the increment multiples of the interleave delay d₃ applied increases monotonically from 0 to 6 for each succession i of six even data words W 12i , W 12i+2 , ..,W 12i+10 and the succession i of the alternate six delayed and further delayed odd data words W 12i+1 , W 12i+3 , .., W 12i+11 . Incremented interleave delays of three d₃ are applied to two of the error correction codes C 4i and C 4i+1 and multiple increment delays of seven d₃ are applied to the remainder two error correction codes C 4i+2 and C 4i+3 . In this embodiment each word comprises 32 bits composed of 16 bits from each two channels. The sequence shown in figure 8 is repeated 5 = 320/(2x16x2) times per frame because two words W 12i and W 12i+7 are arranged on each track. As in the prior art sequence discussed above, the post encoding time shift delay, second time delay d₂ and the incremental interleave delay d₃ have values 160 T and 20 T. The pre-encoding time shift delay, first delay d₁ is of a different value, having the value 40 T. The encoder circuit for obtaining such a modified data arrangement is obtained merely by changing the memory control circuit 66 of the encoder circuit 3 shown in figure 5 and previously described. This memory control circuit 66 is changed so that the time shift and interleave delays of figure 8 are applied. The memory capacity for storing the process data remains 61 blocks and there is therefore no need to change the memory 65 for one of larger memory capacity. Furthermore the decoder circuit 34 can be easily obtained by constituting a sequence which is the reverse to that shown in figure 8. The PCM recording and reproducing apparatus just described has the following properties. That is, the burst error correction ability amounts to sixteen block errors as before. The cross fade period of the splice is increased to 20 blocks interval between the last even data word W₁₀ and the first odd data word W₁, a notable improvement. For a sample frequency of 48 kHz this is an interval of 25 milliseconds and this is 1.7 times that obtained previously by the conventional device. As is evident from the foregoing description, the C2 inspection data are separately arranged at equal intervals (d₃) in two groups, one group subsequent to all six even data words and the other group subsequent to all six antecedent odd data words. The odd data words are spaced an optimum distance apart from the even data words. The implementing apparatus has no greater memory capacity yet is capable of obtaining optimum burst error correction and results in an increase in the interval available for cross-fading. In the preferred embodiment just described, the number n₁ of the C2 inspection data arranged subsequent to all six even data words and the number n -n₁ arranged subsequent to all six antecedent odd data words are equal in number and d₁ is equal to twice d₃. Even where the subdivision of C2 inspection data i.e. error correction codes is unequal similar effects can be obtained. Notably, under the constraint of a constant memory capacity, i.e. d₁ ≯ (n-n₁) x d₃, optimum effects are obtained when the first time delay d₁ and the third time delay d₃ are related as follows: d₁ = (n -n₁) x d₃. This is subject to the proviso that the second and third time delays are unequal: d₂ ≠ d₃. By the way as the C2 error correction code a Reed Solomon code on a Galoia field (2⁸) dealing with eight bits as a unit (a symbol) is used. The codes which are adopted in DAT (digital audio tape) text are equivalent ones to this Reed Solomon code. When the bit number of one symbol is increased the single processing ability of the error correction encoder and decoder are enhanced, but adversely the size of the hardware is enlarged. When GF (2¹⁰) is used instead of GF (2⁸) the size of the hardware becomes about four times larger, and this is impractical. Accordingly, usually a code of eight bits per symbol is used. However, the code interleaving must be conducted at a word unit as described above, and the relationship between the word and the symbol should be considered in conducting the interleaving. European Patent No. 0220033 pursuant to application No. 86307872.1, the parent patent application hereof, concerns a pulse code modulated (PCM) data recording apparatus in which sampling frequency and frame frequency signals are derived from a common master clock circuit.

Claims: A method of recording digital audio signals onto a recording tape, in which method pulse code modulated (PCM) data words are recorded onto a number Tr of tape tracks and pulse code modulated error correction codes are recorded onto a plurality of other tape tracks, which method comprises: applying alternately a first time delay d₁, d₁ ≠0, to a succession of digital data words (W 12i to W 12i+11 : i = 0,1,...) to introduce a time shift between even words (W 12i , W 12i+2 , .., W₁₂+₁₀ : i = 0, 1, ...) and odd words (W 12i+1 , W 12i+3 , .. W 12i+11 : 1 = 0,1,...); encoding the even words (W 12i , W 12i+2 , ..., W 12i+10 : i = 0, 1, ...) and the delayed odd words (W 12i+1 , W 12i+3 ,..., W 12i+11 : i = 0,1,...) to generate a plurality n of error correction codes (C 4i to C 4i+3 : i = 0; i=1; ...) for each succession of 2 Tr digital data words (W 12i to W 12i+11 : i = 0; i=1; ..); applying a second and further time delay d₂ to the delayed odd words (W 12i+1 , W 12i+3 , ..., W 12i+11 : i = 0,1) to introduce a further time shift between the even words (W 12i , W 12i+2 , .., W 12i+10 : i = 0,1,..) and the odd words (W 12i+1 , W 12i+3 , .., W 12i+11 : i = 0,1,..); applying a convolutional interleave to the even words (W 12i , W 12i+2 , .., W 12i+10 : i = 0,1,..) and the same convolutional interleave to the odd words (W 12i+1 , W 12i+3 , .., W 12i+11 : i = 0,1,..) in which convolutional interleave, respective different interleave delays are applied to respective even words (W 12i , W 12i+2 , .., W 12i+10 : i =0,1,..) and to respective further delayed odd words (W 12i+1 , W 12i+3 , .., W 12i+11 : i = 0,1,..), the respective different interleave delays differing by integer multiple increments of a third time delay d₃; applying respective delays between the error correction codes (C 4i to C 4i+3 : i = 0,1,...) to introduce time shift and to effect interleave; sharing each plurality Tr of interleaved even words (W 12i , W 12i+2 , .., W 12i+10 : i = 0; i = 1; ..) and each plurality Tr of time-shifted and interleaved odd words (W 12i+1 , W 12i+2 , .., W 12i+10 : i = 0; i = 1; ..) amongst Tr channels; sharing each plurality n of interleaved error correction codes amongst a plurality of other channels; pulse code modulating and amplifying the words (W 12i ; W 12i+1 ; ...; W 12i+11 : i = 0,1, ..) in each of the Tr channels, and the codes (C 4i , C 4i+2 ; C 4i+1 ; C 4i+3 : i = 0, 1, ..) in each other channel; and recording the modulated and amplified words (W 12i ; W 12i+1 ; ...; W 12i+11 : i = 0,1,...) and codes (C 4i , C 4i+2 ; C 4i+1 , C 4i+3 : i =0,1,...) together with synchronisation and control signals and error detection codes frame-by-frame, on respective and corresponding ones of the Tr Tape tracks and the other tape tracks; which method is characterised in that: the convolutional interleave applied to the even words (W 12i , W 12i+2 , ..., W 12i+10 : i = 0; 1; ..) and the further delayed odd words (W 12i+1 , W 12i+1 , .., W 12i+11 : i = 0; 1; ...) and the respective delays applied to the error correction codes (C 4i to C 4i+3 : i = 0;1; ...) are such that the PCM data words (W 12i to W 12i+11 : i = 0; 1; ...) and error correction codes (C 4i to C 4i+3 : i = 0;1;) are arranged in a consecutive order of Tr respective even words (W 12i , W 12i+2 , .. W 12i+10 ), an integer number n₁ : 0 ≤ n₁ < n of each respective plurality n of the error correction codes (C 4i to C 4i+3 : i = 0; i = 1; ..), Tr antecedent odd words (W' 12i+1 , W' 12i+3 , ..W' 12i+11 ) which precede each respective one of said respective Tr odd words (W 12i+1 , W 12i+3 , ..W 12i+11 )by said first time delay d₁, and the remainder number n-n₁, of each respective plurality n of said error correction codes (C 4i to C 4i+3 : i = 0; i = 1; ...) at delays which differ by one unit increment of said third time delay d₃ under a constraint that no increase in memory capacity is required : d₁ ≯ (n-n₁) d₃. A method as claimed in claim 1 wherein: the first, second and third delays, d₁, d₂ and d₃ respectively are related as follows: d 1 = (n-n 1 ) d 3 ; d 2 ≠ d 3 . A method as claimed in claim 2 wherein: the number n₁, and the remainder number n-n₁ of error correction codes (C 4i to C 4i+3 : i=0; i=1; ...) are equal. A method as claimed in claim 3 wherein n=4, n₁ = n-n₁ = 2 and d₁ = 2d₃. A method as claimed in claim 4 wherein: Tr=6; d 1 = 40[T]; d 2 = 160[T]; & d 3 = 20 [T]; where T is the period of the convolutional interleave which is performed for each succession 2Tr=12 of consecutive data words (W 12i to W 12i+11 : i=0; i=1;..). Recording apparatus for recording digital audio signals onto a recording tape and by which means pulse code modulated (PCM) data words can be recorded onto a number of tape tracks and pulse code modulated (PCM) error correction codes can be recorded onto a plurality of other tape tracks, which apparatus comprises: first time delay means (65,66) for applying alternately a first time delay d₁, d₁ ≠0, to a succession of digital data words (W 12i to W 12i+11 : i = 0,1,...) to introduce a time shift between even words (W 12i , W 12i+2 ,, .., W₁₂+₁₀ : i = 0, 1, ...) and odd words (W 12i+1 , W 12i+3 , .. W 12i+11 : i = 0,1, ...); encoding means (68), responsive to said first time delay means, for encoding the even words (W 12i , W 12i+2 , ..., W 12i+10 : i = 0, 1, ...) and the delayed odd words (W 12i+1 , W 12i+3 , ..., W 12i+11 : i = 0,1,...) to generate a plurality n of error correction codes (C 4i to C 4i+3 : i = 0; i=1; ...) for each succession of 2 Tr digital data words (W 12i to W 12i+11 : i = 0; i=1; ..); second time delay means (65,66), responsive to said first time delay means (65,66) for applying a second and further time delay d₂ to the delayed odd words (W 12i+1 , W 12i+3 , ..., W 12i+11 : i = 0,1) to introduce a further time shift between the even words (W 12i , W 12i+2 , .., W 12i+10 : i = 0,1,..) and the odd words (W 12i+1 , W 12i+3 , .., W 12i+11 : i = 0,1,..); interleave means (65,66), responsive to said second time delay means, for applying a convolutional interleave to the even words (W 12i , W 12i+2 , .., W 12i+10 : i = 0,1,..) and the same convolutional interleave to the odd words (W 12i+1 , W 12i+3 , .., W 12i+11 : i = 0,1, ..) in which convolutional interleave, respective different interleave delays are applied to respective even words (W 12i , W 12i+2 , .., W 12i+10 : i =0,1,..) and to respective further delayed odd words (W 12i+1 , W 12i+3 , .., W 12i+11 : i = 0,1,..), the respective different interleave delays differing by integer multiple increments of a third time delay d₃; error correction code delay means (65,66) responsive to said encoding means (68) for applying respective delays between the error correction codes (C 4i to C 4i+3 : i = 0,1,...) to introduce time shift and to effect interleave; track-sharing means (12) connected to said interleave means and said error correction code delay means (65,66) for sharing each plurality Tr of interleaved even words (W 12i , W 12i+2 , .., W 12i+10 : i = 0; i = 1; ..) and each plurality Tr of time-shifted and interleaved odd words (W 12i+1 , W 12i+2 , .., W 12i+2 , .., W 12i+10 : i = 0; i = 1; ..) amongst Tr channels and for sharing each plurality n of interleaved error correction codes amongst a plurality of other channels; and a plurality Tr channels and other channels, connected to said track-sharing means (12) each including PCM modulation means (13-15), amplification means (16-18) and a recording head (19-21); which apparatus is characterised in that: said first time delay means (65,66), said interleave means (65,66) and said error correction code means (65,66) are adapted such that the PCM data words (W 12i to W 12i+11 : i = 0; 1; ...) and error correction codes (C 4i to C 4i+3 : i = 0;1;) are arranged in a consecutive order of Tr respective even words (W 12i , W 12i+2 , ..W 12i+10 ), an integer number n₁ : 0 ≤ n₁ < n of each respective plurality n of the error correction codes (C 4i to C 4i+3 : i = 0; i = 1; ..), Tr antecedent odd words (W' 12i+1 , W' 12i+3 , ..W' 12i+11 ) which precede each respective one of said respective Tr odd words (W 12i+1 , W 12i+3 , ..W 12i+11 ) by said first time delay d₁, and the remainder number n-n, of each respective plurality n of said error correction codes (C 4i to C 4i+3 : i = 0; i = 1; ...) at delays which differ by one unit increment of said third time delay d₃ under a constraint that no increase in memory capacity is required : d₁ ≯ (n-n₁) d₃. Recording apparatus as claimed in claim 6 wherein: the first and second time delay means (65,66) are operable to apply delays d₁ & d₂ respectively and the interleave means (65,66) is operable to apply consecutive delays differing by one unit increment of the third delay d₃, which delays d₁, d₂, d₃ are related as follows: d 1 = (n-n 1 ) d 3 ; d 2 ≠ d 3 . Recording apparatus as claimed in claim 7 wherein said error correction code delay means (65,66) is operable to apply respective delays such that number n₁ and remainder number n-n₁ of each number n of the error correction codes (C 4i to C 4i+3 ; i=0; i=1; ..) are equal. Recording apparatus as claimed in claim 8 wherein n=4, n₁ = n-n₁ =2 and d₁ = 2d₃. Recording apparatus as claimed in claim 9 wherein Tr=6; d₁ = 40[T]; d₂ = 160[T]; & d₃ = 20 [T]; where T is the period of the convolutional interleave which is performed for each succession 2Tr=12 of consecutive data words (W 2i to W 12i+11 : i=0; i=1;..). Recording apparatus as claimed in any one of the preceding claims 6 to 10 wherein: said first and second time delay means, said interleave means, and said error correction code delay means, consist in a memory (65) and a memory control (66) arranged to control said memory (65). A recording tape having a plurality Tr of tracks on which are recorded PCM data words (W 12i to W 12i+11 : i = 0,1,..) representing digital audio signals and a plurality of other tracks on which are recorded PCM error correction codes, (C 4i to C 4i+3 : i=0,1,..) wherein on each track respective pluralities of the PCM data words (W 12i to W 12i+1 : i=0,1,..) and the PCM error correction codes (C 4i to C 4i+3 : i=0,1,..) are preceded by respective synchronisation and control signals and followed by respective error detection codes and constitute respective frames, in which frames PCM data words (W 12i to W 12i+1 : i=0,1,..) and PCM correction codes (C 4i to C 4i+3 : i=0,1,..) are dispersed in accordance with an interleave pattern, characterised in that: said PCM data words (W 12i to W 12i+11 : i = 0; i = 1; ..) and PCM correction codes (C 4i to C 4i+3 : i = 0; i = 1; ...) are dispersed in accordance with an interleave pattern in which they are arranged in a consecutive order of Tr respective even words (W 12i , W 12i+2 , ..W 12i+10 ), an integer number n₁ : 0 ≤ n₁ < n of each respective plurality n of the error correction codes (C 4i to C 4i+3 : i = 0; i = 1; ..), Tr antecedent odd words (W' 12i+1 , W' 12i+3 , ..W' 12i+11 ) which precede each respective one of said respective Tr odd words (W 12i+1 , W 12i+3 , ..W 12i+11 ) by said first time delay d₁, and the remainder number n-n, of each respective plurality n of said error correction codes (C 4i to C 4i+3 : i = 0; i = 1; ...) at delays which differ by one unit increment of said third time delay d₃ under a constraint that no increase in memory capacity is required : d₁ ≯ (n-n₁) d₃. A recording tape as claimed in claim 12 having 8 tracks (1-8), on 6 (2-6) of which are recorded the PCM data words (W 12i to W 12i+1 : i=0,1,..) and on 2 (1,8) of which are recorded the PCM error correction codes, (C 4i to C 4i+3 : i=0,1,..) wherein each of 6 even PCM data words (W 12i , W 12i+2 , .., W 12i+10 : i=0; i=1; ..) are recorded on the second to seventh tracks (2-7) at intervals of 4 frames starting from each zeroth frame; two error correction codes (C 4i+3 , C 4i+1 : i=0; i=1;..) for each of four error correction codes (C 4i to C 4i+3 : i=o,i=1;..) encoded for 6 even and 6 odd PCM data words (W 12i to W 12i+11 : i=0,i=1;..) are recorded on the first and eighth tracks (1,8) at intervals of four frames following each last even word (W 12i+10 : i=0;i=1; ..); each 6 odd PCM data words (W 12i+1 , W 12i+3 , W 12i+11 : i=0; i=1; ..) are recorded on the fifth to seventh tracks (5- 7) and second to fourth tracks (2-4) at intervals of four frames starting from each fortieth frame; and two remaining error correction codes (C 4i+2 , C 4i : i=0;i=1;..) for each of four codes (C 4i to C 4i+3 : i=0; i=1;..) are recorded on the first and eighth tracks (1,8) at intervals of four frames ending at the sixtieth frame. A pulse coded modulated data reproducing apparatus suitable for producing analogue signal from the recording tape claimed in claims 12 or 13, said apparatus comprising a decoder (34) operable to perform a sequence of operations that is the reverse of the sequence of operations of applying time delays, encoding, and interleaving specified in claim 1.

Inventors: ONISHI KEN C O MITSUBISHI DENK, SUGIYAMA KAZUHIRO C O MITSUBIS, ONISHI, KEN, C/O MITSUBISHI DENKI K.K., SUGIYAMA, KAZUHIRO, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1986
Main classification: G11B20
IPC codes: G11B27, G11B20