DYNAMIC MEMORY WITH IMPROVED ARRANGEMENT FOR PRECHARGING BIT LINES

Abstract: A dynamic memory which can precharge a pair of bit lines accurately to a potential of half a power voltage and has an improved detection characteristics of data read-out is disclosed. The dynamic memory is of the type that a precharge potential of a pair of bit lines is generated by short-circuiting the pair of bit lines after the pair of bit lines are discriminated into the power voltage and a reference voltage. A compensation capacitor is provided for the pair of bit lines. The compensation capacitor is charged to the power voltage and the charged compensation capacitor is operatively connected to the pair of bit lines when they are short-circuited thereby to raise the potential on the bit lines to half the power voltage.

Description: BACKGROUND OF THE INVENTION: The present invention relates to a dynamic memory composed of semiconductor elements, and more particularly to a circuit for precharging bit lines of the dynamic memory. Dynamic memories employing one-transistor type memory cells have been dominantly utilized as large capacity memories. The one-transistor type memory cell is comprised of a storage capacitor and a transfer gate MOS transistor connected between the storage capacitor and a bit line and having a gate coupled to a word line. In order to achieve high sensitivity detection of a stored signal in a selected memory cell, a differential type sense amplifier is provided for each pair of bit lines. Prior to access operation, each pair of bit lines are precharged to a power voltage. Then, one of a pair of bit lines is subjected to change in potential due to a content of a selected memory cell while a charge stored in a dummy cell storing intermediate amount of charge of the respective charged corresponding to logics "1" and "0" states of a memory cell is applied to the other bit line of the bit line pair. Then a sense amplifier is enabled to amplify the difference in potential between the bit lines of the bit line pair such that one of the bit line pair such that one of the bit lines is discharged from the power voltage to a ground potential while the other bit line maintains the power voltage. Recently, an improved technique for precharging bit lines was proposed. According to this technique, after potentials on a pair of bit lines are discriminated into the power voltage V cc and a ground potential, the pair of bit lines are short-circuited. Thus, the potential of the pair of bit lines are set approximately to half the power voltage i.e. 1/2 V cc due to charge division by the pair of bit lines. This technique is advantageous in that a power consumption of a memory can be significantly reduced, and it is possible to eliminate a dummy cell which has been necessitated to operate a sense amplifier. However, in a bit line pair, a potential of the higher potential side bit line is of half the power voltage or less when amplification by a differential sense amplifier is completed. Therefore, in order to re-write the power voltage to the selected memory cell storing "1" for refreshing "1" of the selected memory cell and to raise the higher potential side bit line to the power voltage for subsequent short-circuiting explained above, the higher potential side bit line is raised in potential to the power voltage V cc by an active pull-up circuit employing a boasting capacitor through which the power voltage is applied to the higher potential side bit line. However, when a pair of bit lines are short-circuited, the boosting capacitor is also connected to the pair of bit lines, especially to the higher potential side bit line. Also in this instance, certain regions of transistors of the sense amplifier is connected to the short-circuited bit lines to impose a capacitance thereon. Accordingly, the resultant potential remaining on the pair of bit lines does not reach the exact half the power voltage but takes a value less than it. As a result, the voltage set at the pair of bit lines shifts from a center value between the power voltage which is stored in a "1" storing memory cell and the ground potential which is stored in a "0" storing memory cell. Thus, a differential voltage between the precharged potential of a bit line and a potential stored in a selected memory cell is different according to whether the selected memory cell stores "1" or "0". This means that operational margin for a sense amplifier varies according to the content stored in a selected memory cell, resulting in unstable operation. SUMMARY OF THE INVENTION: It is an object of the present invention to provide a dynamic memory provided with an improved arrangement for precharging a pair of bit lines accurately to the half the power voltage. This object is achieved by a memory as defined in claims 1, 4 and 7, respectively. The dependent claims are related to further developments of the invention. According to the present invention, charge stored in the compensation capacitor compensates a potential drop due to a capacitance of the boost capacitor and a capacitance of the common node and raises a potential on the short-circuited bit lines to the half the power voltage effectively. The capacitance of the compensation capacitor is selected to the sum of the capacitances of the boost capacitor and the common node. According to the present invention, the pair of bit lines are accurately precharged to half the power voltage, sense of a signal stored in a selected memory cell can be performed with a high-sensitivity and increased stability. DETAILED DESCRIPTION OF THE DRAWINGS: Fig. 1 is a schematic circuit diagram showing a major part of a dynamic memory according to a prior art; Fig. 2 is a timing chart showing operation of the circuit of Fig. 1; Fig. 3 is a schematic circuit diagram showing a major part of a dynamic memory according to a first embodiment of the invention; Fig. 4 is a timing chart showing operation of the circuit of Fig. 3; Fig. 5 is a schematic circuit diagram showing a dynamic memory according to a second embodiment of the present invention; and Fig. 6 is a schematic circuit diagram showing a dynamic memory according to a third embodiment of the present invention: DETAILED DESCRIPTION OF THE INVENTION: Fig. 1 shows a major part of a dynamic memory according to a prior art. MOS field effect transistors (MOSTs) Q₁ and Q₂ having gates and drains cross-coupled at nodes N₁ and N₂ and sources commonly connected to a common node N c and a discharge MOST Q₁₂ form a known flip-flop type sense amplifier. A pair of bit lines B and B are connected to the nodes N₁ and N₂, respectively. A plurality of word lines WL₁, WL₂ or the like intersect with the bit lines. Memory cells MC each comprised of a transfer MOST Q M and a storage capacitor C M are connected to the bit lines and word lines in a known way. MOSTs Q₃, Q₄, Q₅ and Q₆ and a boost capacitor C₁ form an active pull-up circuit for the bit line B while MOSTs Q₇, Q₈, Q₉ and Q₁₀ and a boost capacitor C₂ form another active pull-up circuit for the bit line B . A MOST Q₁₁ connected between the nodes N₁ and N₂ short-circuits between the pair of bit lines B and B so as to precharge them with an intermediate voltage of the power voltage V cc and a ground potential (GND), after a potential difference between the pair of bit lines are amplified and discriminated into V cc and GND. Referring to Fig. 2, operation of the circuit of Fig. 1 will be described. A pulse  B changes from a low (GND) level to a high level (V cc ) so that MOST Q₁₁ is rendered conductive at T₁. Accompanied by this, the bit lines B and B which have been of V cc and GND respectively change to the same intermediate voltage V R as a reference for operating the sense amplifier. While in parallel with this change, a pulse  P is raised to V cc at a time T₂. Accordingly, output ends of the boost capacitors C₁ and C₂ are charged to V cc . In this instance, gates and sources of MOSTs Q₆ and Q₁₀ are biased at V R and hence MOSTs Q₆ and Q₁₀ are not conducting to ensure the precharge of the output ends of the capacitors C₁ and C₂. The pulses  B and  P change to a low level at a time T₃, to complete a reset precharge period T R . Then, at a time T₄ one of word lines, e.g. WL₂ is selected and the bit line B is lowered in potential slightly due to "0" level stored in a selected memory cell with the bit line B remaining at V R . Then, a pulse  s is raised at a time T₅ to render MOST Q₁₂ conductive. Thus, the lower potential side bit line B is discharged to GND without materially discharging the higher potential side bit line B by the flip-flop composed of MOSTs Q₁ and Q₂. In this instance, MOST Q₁₀ becomes conductive due to the discharged level of the bit line B and therefore the capacitor C₂ arranged for the lower potential side bit B is discharged, while charge of the capacitor C₁ is maintained. Subsequently, a pulse  A is raised at a time T₆ so that a gate potential of MOST Q₄ is raised above V cc through the capacitor and MOST Q₆ assumes a conductive state. Therefore, the power voltage V cc is applied to the higher potential side bit line B through MOSTs Q₄ and Q₅ thereby to achieve pulling-up of the bit line B to V cc in potential. While the capacitor C₂ has been discharged and MOST Q₁₀ has been conductive so that a gate potential cannot be raised by  A . Therefore, MOST Q₈ remains non-conductive so that the power voltage V cc is not applied to the lower potential side bit line B . Thus, the potential difference between the bit lines B and B is extended to V cc . Then, the pulses  A and  S are changed to GND potential at a time T₇ to complete an access cycle. In the following, a practical value of V R obtained in the circuit of Fig. 1 will be discussed. The pair of bit lines B and B are designed to have the same capacitance "C B ". After completion of pulling-up, a pair of bit lines B and B prima-facially seem to become the potential V R of 1/2 V cc due to charge division expressed as: However, this assumption is not practically correct by the following reason. As is clear from Fig. 1, when a pair of bit lines B and B are short-circuited, the node NC and the boost capacitor C₂ are also connected to the short-circuited bit lines B and B . Therefore, electric charge of the bit line B of V cc is divided by not only the bit lines B and B but also the capacitor C₂ and a capacitance of the node N c . Therefore, representing the capacitance of the capacitor C₁ (C₂) as "C A " and the capacitance of the node N c as "C S ", a practical value of the voltage V R is determined by the following equation (1): As a result, it should be understood that the practical value of V R is lower than the half the power voltage. In a practical dynamic memory, values of C B , C A and C S are 0.5 pF, 0.05 pF and 0.1 pF, respectively. Therefore, the value of V R becomes about 0.43 V cc which is lower than 1/2 V cc . As is well known, it is desirable to select the value of V R at a center value (1/2 V cc ) of two potentials V cc and GND corresponding to "1" and "0" information stored in a memory cell. In the case where the value of V R is lower than 1/2 V cc , the potential difference V D1 between V R and a potential (V cc ) of a "1" storing memory cell becomes large while the potential difference V D0 between V R and a potential (GND) of a "0" storing memory cell becomes small, as shown in Fig. 2. This means that operation margin of a sense amplifier is changed according to the content of a selected memory cell, resulting low operation stability. Referring to Fig. 3, a dynamic memory according to a first embodiment of the invention will be explained. In Fig. 3, portions corresponding to those in Fig. 1 are designated by the same references. According to the embodiment, in place of MOST Q₁₁ in Fig. 1, MOST Q₂₀ connected between the bit line B and the common node N C and MOST Q₂₁ connected between the bit line B and the node N C are provided for short-circuiting the bit lines B, B and the node N C . A compensation capacitor C X is provided according to the invention. A MOST Q₂₃ is provided for charging an output end of the capacitor C X to V cc in response to a pulse  PA and a MOST Q₂₂ operatively connects the output end of the capacitor C X to the node N C in response to the pulse  B . According to this arrangement, when the bit lines B, B , the node N C , the capacitor C₁ or C₂ and the capacitor C X are short-circuited in response to the pulse ₀ for generating V R on the bit lines B and B , after the capacitor C X is charged to V cc . Therefore a resultant value of V R on the bit lines B and B is denoted by the following equation (2): Then, if the following relation (3) is fulfilled, C X ≒ C A + C S (3) a value of V R becomes approximately 1/2 V cc . Therefore, the capacitance of the capacitor C X is selected to have a value corresponding to the sum of the capacitance of the capacitor C₁ (C₂) and the capacitance of the node N C . Referring to Fig. 4, operation of the circuit of Fig. 3 will be described. Prior to a time T₂, the capacitor C X is charged to V cc through MOST Q₂₃ in response to  PA , while the pulse  B is raised to V cc at a time T₁ so that the pair of bit lines B and B , the node N C and the capacitor C₂ are short-circuited by MOSTs Q₂₀ and Q₂₁ so that the potential on the bit lines B and B becomes a potential which is lower than 1/2 V cc similarly to the case of Fig. 1. Then, MOST Q₂₂ becomes conductive in response to the rise of  C to connect the output end of the capacitor C X to the short-circuited bit lines B and B . According to this, as explained by the equations (2) and (3), the potential on the bit lines B and B shifts to 1/2 V cc (V R '), achieving a precharge of the bit lines B and B . At a time t₄, the capacitors C₁ and C₂ are precharged to V cc in response to  P , similarly to the circuit of Fig. 1. Then, a content of a selected memory cell is applied to the bit line B at a time T₇ so that the bit line B is reduced slightly in potential due to "0" content of the selected memory cell. Then, the sense amplifier and the active pull-up circuits are sequentially enabled by  S and  A at a time T₈ and a time T₉, respectively in the same manner as in Fig. 1 to achieve an access operation. According to this invention, prior to an access operation from T₇, the bit iines B and B are accurately precharged to 1/2 V cc , and therefore the voltage difference V D1 ' between the precharge voltage V R ' and the potential of a "1" storing memory cell and the voltage difference V D0 ' between V R ' and the potential of a "0" storing memory cell are made equal from eath other. Thus, a high-sensitive and stable amplifying operation is obtained. In a 256 k-bit dynamic memory, a value of C S and the capacitance C A of the capacitors C₁, C₂ are 0.1 pF and 0.05 pF, respectively, then the value of capacitance of the capacitor C X is selected to 0.15 (C X = C A + C S = 0.05 + 0.1) pF, in this case. Fig. 5 shows a second embodiment of the present invention. This embodiment is obtained by directly connecting the output end of the capacitor C X to the pair of bit lines B and B by MOST Q 20' and Q₂₁ in place of MOSTs Q₂₀ to Q₂₂ in Fig. 3. According to this embodiment, MOST Q₂₂ and the pulse  C are obviated. As far as the capacitance of the capacitor C X is determined according to the equation (3), this embodiment also provides the same effect. Timing relations of the respective pulses in this circuit are substantially the same as those in Fig. 3. Referring to Fig. 6, a third embodiment of the present invention will be described. This embodiment is featured in that the common nodes NC₁ to NC n of a plurality sense amplifiers for a plurality pairs of bit lines B₁, B , to B n , B n are connected in common and MOST Q₁₂' for enabling the sense amplifiers in response to  S and MOSTs Q₂ and Q₂₃ and the capacitor C X ' are connected to the commonly connected nodes NC₁ to NC n , as illustrated. In this case, the capacitance of the capacitor C X ' is selected "n" times the sum of the capacitance C A of each capacitor C₁, C₂ and the capacitance C S of each node (NC₁ to NC n ), "n" being the number of the sense amplifiers. Therefore, for a 256 k-bit dynamic memory, the number "n" of the sense amplifiers is 1024, then the value of C X ' becomes as follows: C X ' = 1024 x (C A + C S ) = 1024 x (0.05 + 0.1) ≒ 154 pF As has been described above, according to the present invention, a pair of bit lines B and B are accurately precharged to 1/2 V cc . Therefore a dynamic memory having a high-sensitivity can be obtained.

Claims: A dynamic memory comprising a pair of bit lines (B, B ), amplifying means (Q₁,Q₂,Q₁₂) having a pair of input/output nodes and at least one internal node capacitance (Cs), means for connecting said pair of bit lines to said pair of input/output nodes, first means for operatively enabling said amplifying means thereby to discriminate potentials on said pair of bit lines into first and second voltages, second means (Q₂₀,Q₂₁) for operatively short-circuiting said pair of bit lines after said amplifying means is disabled by said first means, said internal node capacitance being connected to said pair of bit lines when said pair of bit lines are short-circuited, characterized by capacitor means (Cx), third means (Q23,Vcc,PA) for charging said capacitor means (Cx) before said pair of bit lines are short-circuited, and fourth means (Q₂₂,c) for transmitting charge accumulated in said capacitor means (Cx) to said pair of bit lines (B, B ) when said pair of bit lines are short-circuited, said capacitor means (Cx), third means and fourth means being adapted to compensate for a deviation of the potential to which the pair of bit lines (B, B ) are precharged by short-circuiting the bit lines, said deviation being due to said internal node capacitance (Cs). The dynamic memory according to claim 1, in which said capacitor means (Cx) has a capacitance substantially equal to said internal node capacitance (Cs). The dynamic memory according to claim 1, said amplifying means (Q₁,Q₂,Q₁₂) includes a flip-flop circuit and a pair of pull-up circuits (Q₃,Q₄,Q₅,Q₆,C₁;Q₇,Q₈,Q₉,Q₁₀,C₂) provided for said pair of bit lines. A dynamic memory of the type having a pair of bit lines (B, B ), first and second sense nodes, a common node (Nc), a first transistor (Q₁) having a source-drain path connected between said first sense node and said common node (Nc) and a gate connected to said second node, a second transistor (Q₂) having a source-drain path connected between said second sense node and said common node (Nc) and a gate connected to said first node, means for connecting one of said pair of bit lines to said first sense node, means for connecting the other of said pair of bit lines to said second sense node, means (Q₂₀,Q₂₁) for operatively short-circuiting said pair of bit lines (B, B ), wherein said common node (Nc) is connected to said pair of bit lines (B, B ) when said pair of bit lines is short-circuited, a pair of pull-up circuits (Q₃,Q₄,Q₅,Q₆,C₁;Q₇,Q₈, Q₉,Q₁₀,C₂) coupled to said pair of bit lines, each of said pull-up circuits including a first capacitor (C₁,C₂) one of said pull-up circuits coupled to one of said pair of bit lines having a higher potential raising said one bit line of higher potential to a power potential (Vcc), the first capacitor of the other of said pair of pull-up circuits coupled to the other bit line of a lower potential being electrically connected to said pair of bit lines when said pair of bit lines (B, B ) are short-circuited by said short-circuiting means (Q₂₀,Q₂₁); characterized by comprising a second capacitor (Cx), first means for operatively charging one end of said second capacitor to said power voltage (Vcc) before said pair of bit lines are short-circuited, and second means for connecting said one end of said second capacitor to said pair of bit lines when said pair of bit lines are short-circuited, said capacitor means (Cx), first means and second means being adapted to compensate for a deviation of the potential to which the pair of bit lines (B, B ) are precharged by short-circuiting the bit lines, said deviation being due to said capacitances of said common node and the first capacitor. The invention as claimed in claim 4, in which a capacitance of said second capacitor (Cx) is selected to the sum of capacitances of said common node (Nc) and said first capacitor. The invention as claimed in claim 4, in which said short-circuiting means includes a third transistor (Q₂₀) having a source-drain path coupled between one of said bit lines and said common node (Nc) and a fourth transistor (Q₂₁) coupled between the other of said pair of bit lines and said common node (Nc). A dynamic memory comprising a plurality of pairs of bit lines (B, B ), a plurality of amplifying means (Q₁,Q₂,Q₁₂') provided for said plurality of pairs of bit lines, each of said amplifying means connected to each pair of bit lines (B, B ) to operatively amplify potentials on said pair of bit lines into first and second voltages and including an internal capacitance, means for enabling said plurality of sense amplifiers simultaneously a plurality of first means provided for said plurality of pairs of bit lines, each of said first means (Q₂₀,Q₂₁;Q₂₀',Q₂₁') operatively short-circuiting each pair of bit lines (B, B ) after potentials on said each pair of bit lines are amplified by said amplifying means (Q₁,Q₂,Q₁₂'), said internal capacitance of each of said amplifying means being connected to the associated pair of bit lines when said associated pair of bit lines are short-circuited, characterized by capacitor means (Cx'), second means (Q₂₃) for charging said capacitor means (Cx') before said plurality of sense amplifiers are enabled, and third means for operatively connecting said capacitor means (Cx') to said internal nodes of said amplifying means when each pair of bit lines are short-circuited, said capacitor means (Cx'), second means and third means being adapted to compensate for a deviation of the potential to which the pair of bit lines (B, B ) are precharged by short-circuiting the bit lines, said deviation being due to said internal capacitances of said plurality of amplifying means. The dynamic memory according to claim 7, in which said capacitance means (Cx) has a capacitance substantially equal to a total capacitance of said internal capacitances.

Inventors: MUROTANI, TATSUNORI
Applicants: NEC CORPORATION
Application year: 1986
Main classification: G11C11
IPC codes: G11C11