CONTROL CIRCUIT OF RASTER SCANNING DISPLAY UNIT

Abstract: A control circuit of a raster scanning display unit has an address converting part disposed between a video memory (2) and a read address generating part, said address con­ verting part (5) judging whether or not the area in concern is an area where superposed display is effected. Based on a result of the judgement, the control circuit transfers an ad­ dress from the read address generating part as it is when the area in concern is outside said area, while it adds, when within said area, a difference between a head storage ad­ dress of superposing display data and that of superposed display data to the address from said read address generat­ ing part to transfer into the video memory (2).

Description: The present invention relates to a control circuit of a raster scanning display unit according to the preamble of claim 1. A control circuit of a display unit of this type is known is for example Japanese Laid-Open Patent Publication No. 60-22184. Let us describe here the control circuit with reference to Fig. 1. Fig. 1 is an illustration partly depicting a control circuit of a display unit. In the figure, designated at 1 is a CRT controller, 2 is a video memory for storing display data, and 3 is a parallel/serial converter for converting paralled data to serial data, from which a VIDEO signal is delivered. Designated at 4 is a dot clock generator circuit with which the above-described VIDEO signal is synchronized. Successively, let us describe a CRT controller 1 in detail. Designated at 101a, 101b, ...101h are a register, respectively, each of which holds a display start address. Likewise, designated at 102a, 102b, ...102h are a registr, respectively, each of which holds the number of rasters to be displayed. Designated at 103 and 104 are respectively a selector for outputting a desired one among a plurality of input signals, 105 is a counter for designating which input signal is outputted to the selecters 103 and 104, 106 is a counter for providing an address signal of a video memory 2, 107 is a counter for counting a raster signal, 108 is a counter for providing an address signal of the video memory 2, 109 is selector for providing an address signal of the video memory 2, 110 is a mode register for holding two modes of a write mode where display data is written in the video memory 2 and a read mode where display data is read from the video memory 2, 111 is a frequency divider for generating one pulse at every x dot clock with use of a dot clock provided from a dot clock generator circuit 4 as an input signal. An output signal from the frequency divider 111 is hereafter called an address clock (in addition, x dot data is enterd into one address of the video memory 2). Likewise, designated at 112 is a frequency divider for generating one pulse at each y address clock with use of an address clock provided from the frequency divider circuit 111 as an input signal. An output signal from the frequency divider 112 is hereafter called a raster clock (in addition, x.y dot data is displayed per one raster). Let us then describe the control circuit so arranged with referencwe to Fig. 1 First, write operation into the video memory 2 will be described. To write display data of A, B,... H shown in Fig. 2(a) into the video memory 2, a CPU (not shown) sets address data to the counter 108. An address being set here is a head address N1 of a write area. In addition, the CPU switches the mode register 110 to a write mode, An output signal from the counter is delivered to an address line 6 while the mode register 110 is operated in the write mode, and hence the above-described head address is supplied to the video memory 2. Hereupon, display data is provided to a data line 8, while a write signal provided to a control line 7, both from a circuit (not shown) of the CRT controller 1. Finished write operation into one address, the counter 108 is incremented by +1 to permit the display data to be written into the next address. Written the display data 1 into the video memory 2 in such a manner, address data is again set to the counter 108. The address being set here is the head address N2 of the next writer area. Hereafter, display data B is likewise written into the video memory 2. Display data A, B,...H are written in succession into the video memory 2 in this way. In order to read any display data from the video memory 2 and display it as shown in Fig. 2, the CPU (not shown) sets display start addresses N1, N2, ...Nm to the registers 101a, 101b,...101h; respectively. Moreover, raster numbers n1, n2, ..., nm to be displayed are set to be registers 102a, 102b,...102h. Furthermore, the counter 105 is reset to permit an output signal from the register 101a to be delivered from the selector 107, while an output signal from the register 102a to be delivered from the selector 104, and these outputs are set to the respective counters 106, 107, Thus, N, and n1 shown in Fig. 2(a) are respectively set to the counters 106 and 107. In addition, the mode register 110 is switched to a read mode. An output signal from the counter 106 is delivered onto the address line while the mode register 110 is operated in the read mode. Hereupon , a read signal is provided onto the control line 7 from the circuit (not shown) of the CRT controller 1. Any display data is hereby read from the video memory 2, and delivered onto the data line 8. The above data is converted to serial data through the parallel/serial converter 3 to provide a VIDEO signal. Issued one address display data (x dot) from the parallel/serial converter 3 as the VIDEO signal, the frequency divider 111 provides one pulse. Hereby, the counter 106 is incremented by +1. Thus, any display data is read from the next address (N1+1) of the video memory 2. Read in such a way display data (x.y dot) corresponding to one raster from the video memory 2, the counter 107 is decremented by -1. When the value of the counter 107 gets "0" (read operation for the display data A of Fig. 2(a) is finished), the counter 105 is incremented by +1, whereby an output signal from the register 101b is delivered from the selector 103, while an output signal from the register 102b delivered from the selector 104, both output signals are respectively set to the counters 106, 107. Accordingly, N2 and n2 of Fig. 2(a) are respectively set to the counters 106 and 107. Thereafter, the display data B is read in the same manner from the video memory 2. Display data on and after B are also likewise read. As a result, a plurality of the independent display informations A, B,.. H can be displayed on a signal display screen at the same time. Document GB 21 44 952 A describes a multiwindow display circuit of a raster scanning display unit. It comprises a picture information memory, conventional address counters for generating a read address of the picture information memory in synchronism with an address clock and an address converter provided between the picture information memory and the address counters. The address converter includes a judging part for judging whether or not the area concerned is a window where a superposed display is effected. Bias registers are provided for storing a difference between a head storage address of superposing display data and a head storage address of superposed display data. Further a full adder for adding an output signal from bias registers to an output signal from said address counter is provided. It is the object of the present invention to provide a control circuit capable of displaying single display information while permitting it to be superposed on another independent display information. This object is solved by the control circuit according to claim 1. The above and the objects, features and advantages of the present invention will become more apparent from the folowing description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative example. Fig. 1 is a circuit block diagram illustrating in part a control circuit of a display unit; Fig. 2 is a view for illustrating operation of the control circuit of Fig. 1; Fig. 3 is a block diagram of a display unit according to the present invention; Fig. 4 is a detailed block diagram of an address converter part shown in Fig. 3; Fig. 5 to 8 are respectively a view illustrating operation of the circuit of Fig. 4; Fig. 9 is a detailed circuit block diagram of another address converter part; Fig. 10 is a view illustrating operation of the circuit of Fig. 9; and Fig. 11 is a view illustrating shift operation of display information. Operation of a control circuit of a raster scanning display unit according to the present invention will be described with reference to Figs. 3 to 5. Blocks designated by the numerals 1 to 4 in Fig. 3 are the same as those shown in Fig. 1. In the same figure, designated at 5 is an address converting part, whose details are shown in Fig. 4. As shown in Fig. 4, the numerals 51, 52, 53 and 54 are respectively a register, which holds positional information of a screen area where display informations are superposed. Let us here describe the positional information, with reference to Fig. 5. Fig. 5(a) depicts a display state on the screen, while Fig. 5(b) shows a storage state of display data in the video memory 2. As shown in Fig. 5, A designates an area of displaying display data A'; B1 an area of displaying display data B1'; H an area of displaying display data H'. Na shows a head address of the area in which the display data A' is stored. Likewise, Nb shows a headaddress of the area in which the display data B' is stored. Na1 designates a head address of an area where displays are superposed. In addition, Nb1 is a head address of an area where the superposed diplay data B'1 is stored. As shown in Fig. 5(a), the area B1 where superposition of displays is effected is designated by four parameters: a parameter (e) for showing a vertical position; a parameter (c) for showing a height; a parameter (b) for showing a width; and a parameter (d) for showing a horizontal position. The parameters (c) and (e) are represented by raster numbers, while the parameters (b) and (d) by corresponding address numbers of the video memory 2. The registers 51, 52, 53, and 54 respectively hold complements of the parameters (e), (c), (d), and (b). Here, let us again describe Fig. 4. In the figure, designated at 55 and 56 are selectors, and 57, 58, 59 and 60 are counters, for which one corresponding to TI-made SN 74163 for example is employed. In addition, the counters 57 and 58 comprise a combination of a prescribed number of counters. Designated at 61, 62, 63, and 64 are inverters, 65, 66 are two-input NOR gates, 67 is a three-input AND gate, 68 is a selector, 69 is an adder, 70 is a register which holds a difference (Nb1-Na1) between the Nb1 and Na1 of Fig. 5(b), "HL" is a high level signal, and "SYNC" is a vertical synchronization signal of the display unit, "DATA" is a data signal from a CPU (not shown), "CLK1" is the raster clock being an output signal from the frequency divider circuit 112 of Fig. 1 "CLK2" is the address clock being an output signal from the frequency divider circuit 111 of Fig. 1, "MDISP" is a signal to instruct displays to be superposed, which is availabel from the CPU not shown, "ADD" is an output signal from the selector 109 of Fig. 1, and "VADD" is an address signal of the video memory 2. Then, operation of the address converting part 5 will be described. (1) A case to display the display data B1' on the display area A (superposed display of the display data B1'). The MDISP signal is set to "1" for effecting superposed display. In addition, complements of the parameters (e), (c), (d), and (b) are set to the registers 51,52, 53, and 54 (The data is available from the CPU not shown). Started display operation, the VSYNC signal gets "0". Hereby, an output signal from the register 51 is supplied to an input terminal D of the counter 57 via the selector 55. In addition, the VSYNC signal is supplied to a load terminal L of the counter 57 via the inverter 61 and the two-input NOR gate 65, so that data supplied to the data input terminal D is loaded to the counter 57 in synchronism with the CLK1. Accordingly, a "0" signal is delivered from output terminals Qc, Qd of the counter 59 and a "0" signal is delivered from the three-input AND gate 67. Hereby, the selector 68 allows an ADD signal to pass therethrough. The counter 57 is counted up one by one in synchronism with the CLK1. As the counter 57 counts the CLK1 by a value of the parameter (e), a signal "1" is provided from a carry terminal CA of the counter 57, and a signal "0" (load signal) is supplied to the load terminal L of the counter 57 via the two-input NOR gate 65. Since the VSYNC signal gets "0" only upon starting display and otherwise "1", an ouput signal from the register 52 has been supplied to the data input terminal D of the counter 57 via the selector 55. Accordingly, data held in the register 52 is loaded into the counter 57 by the load signal in synchronism with the CLK1. In addition, a signal "1" from the carry terminal CA of the counter 57 is supplied to a count enable terminal T of the counter 59, whereby the counter 59 is incremented by +1 in synchronism with the CLK1. Thus, a signal "1" is delivered from the output terminal of the counter 59. The counter 57 again counts up the CLK1 in synchronism therewith one by one. As the counter 57 counts the CLK1 by a value of the parameter (c), a signal "1" is delivered from the carry terminal CA of the counter 57, and is supplied to the count enable terminal T of the counter 59. Hereby, the counter 59 is incremented by +1 in synchronism with the CLK1. Accordingly, signals "1", "0" are respectively delivered from the output terminals Qc, Qd of the counter 59. Delivered the signal "1" from the output terminal Qc of the counter 59, a "0" signal is supplied to an enable terminal D of the counter 59 via the inverter 63 for stopping count operation thereafter. Thus, the signals "1", "0" are delivered without interruption respectively from the output terminals Qc, Qd. The output signal from the output terminal Qc becomes "0" after the VSYNC signal becomes "0", i.e., after the first display is finished and the next display is started. While, as the CLK1 signal gets "0", "0" signals are provided from the output terminals Qc, Qd of the counter 60 in synchronism with the CLK2, and thereby a "0" signal is delivered from the three-input AND gate 67. Hereby, the selector 68 is adapted to permit only an ADD signal to pass therethrough. The counter 58 counts up one by one in synchronism with the CLK2 by a value of the parameter (d), a "1" signal is provided from the carry terminal CA of the counter 58, and thereby a "0" signal (load signal) is supplied to the load terminal L of the counter 58 via the two-input NOR gate 66. Thereupon, the output signal from the register 54 has been supplied to the data input terminal D of the counter 58 via the selector 56. Accordingly, the data held in the register 54 is loaded to the counter 58 owing to the load signal in synchronism with the CLK2. In addition, the signal "1" from the carry terminal CA of the counter 58 is also supplied to the count enable terminal T, whereby the counter 60 is updated by +1 in synchronism with the CLK2. Thus, a signal "1" is delivered from the output terminal Qd of the counter 60. The counter 58 again counts up one by one in syunchronism with the CLK2. As the counter 58 counts the CLK2 by a value of the parameter (b), a signal "1" is provided from the carry terminal CA of the counter 58, and thereby a signal "1" is supplied to the enable terminal T of the counter 60. Hereby, the counter 60 is updated by "1" in synchromism with the CLK2. Thus, signals "1", "0", are delivered respectively from the output terminals Qc, Qd of the counter 60. Delivered the signal "1" from the output terminal Qc of the counter 60, a signal "0" is supplied to the enable terminal p of the counter 60 via the inverter 64 for stopping the count operation therafter. Thus, signals "1", "0" are delivered without interruption respectively from the output terminals Qc, Qd. The output signal from the output terminal Qc gets "0" after the CLK1 signal becomes "0", i.e., when the operation transfers to the next raster. The operation described above is summarized as follows: (a) The signal "1" from the output terminal Qd of the counter 59 is provided only within a period of time of (c) of Fig. 5(a). Otherwise, "0" is provided. (b) The signal "1" from the output terminal Qd of the counter 60 is provided only within a period of time of (b) of Fig. 5(a). Otherwise, "0" is provided. The MDISP signal is "1" as described above. Consequently, an output from the three-input AND gate 67 is "1" within a range of a dotted chain line of Fig. 5(a), and otherwise "0". Hereby, only an ADD signal passes through the selector 68 in the area outside the single dot-chain line within the display area A, while only the output signal from the adder 69 passes through the selector 68 within the single dot-chain line. Namely, the display data A' is displayed in the area outside the single dot chain line in the display area A of Fig. 5(a), while the display data B' displayed within the single dot chain line. Moreover, since the difference (Nb1-Na1) between Nb1 and Na1 of Fig. 5(b) is held in the register 70 as described before, the output from the adder 69 gets Nb1 when the address shown by the ADD signal is Na1. (2) A case of displaying the display data B1' of Fig. 5(b) on another location in the display area A (movement of a location of superposing displays). To display the display data B1' of Fig. 5(b) (display data B1' of Fig. 6(b), new data is set to the registers 51, 53, and 70 prior to storing the display. The data, as described before, includes the vertical positional information (parameter(e)), horizontal positional information (parameter(d)), and the difference (Na1-Na2) between the Nb1 and Na2 of Fig. 6(b). (3) A case of displaying display data B2' other than the display data of Fig. 5(b) on the display area B1 of Fig. 5(a) (the location of the superposed display is left behind as it is, but data of superposed display is exchanged). To display the display data B2' of Fig. 7(b) on the display area B1 of Fig. 5(a) (display area B1 of Fig. 7(a)), new data is set to the register 70 prior to starting the display. The data is the difference (Nb2-Na1) between the Nb2 and Na1 of Fig. 7(b) as described efore. (4) A case wherein data to be displayed on the display area of Fig. 5(a) is A1'. Na' is set to the register 101a of Fig.1 as a display starting address prior to starting the display. Moreover a difference (Na-Na') between Na and Na' is estimated and added into the contents of the register 70 (a+Na-Na'). Refer to Fig. 8 thereon. (5) A case of changing the size of the display area B1 of Fig. 5(a). New data is set in the registers 52, 54 prior to starting the display. The data is the height information (parameter(c))and the width information(parameter(b)) as described before. In succession, another example of the address converting part 5 will be described with reference to Figs. 9 and 10. In Fig. 9, designated at 500 is an address converting part, and 501,502, 503, and 504 are respectively registers. These registers serve to hold address information of the video memory 2. Let us describe here the address information with reference to Fig.10. Fig. 10(a) shows a display state on the screen, while Fig. 10(b) a storage state of display data in the video memory 2. In the figures, designated at A is an area to display the display data A', B1 is an area to display the display data B1', H is an area to display the display data H' Na is a head address of the area having the display data A' stored therein, Nb is likewise a head address of the area having the display data B' stored therein, Na1 is a head address of the area where superposed display is effected, Na2 is a final address of a first raster of the area where superposed display is effected, Na3 is a final address of the area where superposed display is effected, and Nb1 is a head address of the area where the superposing display data B1' is stored.The register 501 holds the above address Na1, while the register 502 holds the next address (Na3+1) of the above address Na3. Likewise, the register 503 holds the next address (Na2+1) of the above address Na2, while the register 504 holds the difference (Nb1-Na1) between the Nb1 and Na1 similarly with the register 70 of Fig. 4. Let us here again describe Fig. 9. Designated at 505 is a register for holding an address clock number of the raster of the display data A' of Fig. 10(b), 506, 507, 508 and 509 are respectively a comparator, 510, 511, and 512 are a selector, 513, 514, and 515 are an adder, 516, 517 are a register, 518, 519 are a latch, and 520 is a three-input AND gate having the same function as that of the three-input gate 67 of Fig. 4. Then, operation of the address converting part 500 will be described. The MDISP signal is set to "1" to effect the superposed display. Moreover, the Na1, Na3, Na2, Nb1-Na1, and y are respectively set to the registers 501, 502, 503, 504, and 505. Started the display, the Na1 and Na2 are respectively set to the registers 516, 517 in synchronism with the CLK2 (raster clock). This is done every time the CLK2 arrives. Then, the latch 518 has been reset, and the selectors 510, 511 has allowed output signals from the resisters 501, 503 to pass therethrough. Changed the ADD signal to the Na1, a coincidence signal is delivered from the comparator 506 to set the latch 518, whereby a signal "1" is provided from the latch 518. In addition, a coincidence signal is delivered also from the comparator 508 to set the latch 519, whereby a signal "1" is provided from the latch 519. Hereby, the selector 512 allows an output signal from the adder 515 to pass there through, whereby the VADD signal gets Nb1 to permit the display data B1' to be displayed on the display area B1. Changed the ADD signal to Na2+1, a coincidence signal is issued from the comparator 509 to reset the latch 519 whereby a signal "0" is delivered from the latch 519. Accordingly, an output signal from the three-input AND gate 520 gets "0" . Hereby, the selector 512 allows the ADD signal to pass therethrough, whereby the VADD signal is changed to Na2+1, and hence the display data A' is again displayed. Finished the display of one raster, the CLK2 is supplied to the registers 516, 517. Hereby, an output signal (Na1+y) from the adder 514 is set to the register 517. In addition, when the latch 18 has been set, the selectors 510, 511 respectively allow the output signals from the adders 513, 514 to pass therethrough. Changed there the add signal to (Na1+y), the latch 519 is again set to permit the display data B1' to be displayed. While, changed the ADD signal to ( Na2+1+y ), the latch 519 is set to permit the display data A' to be displayed. With the above operation being repeated, the ADD signal finally gets Na3+1. Thereupon, a coincidence signal is issued from the comparator 507 to reset the latch 518. Hereby, the display data A' is displayed on the display area A thereafter. In succession, a movement, a smooth movement in particular, in the display information will be described, (1) When employing the address converting part 5 of Fig. 4. The contents of the registers 51, 52, 53, 54 and 70 may be changed every time the VSYNC signal is issued. For example, where only the display location is changed as shown by the arrow l1 of Fig. 11, the contents of the registers 51, 53, and 70 may be changed. Namely, the parameters (e), (d), and (a) may be changed. In addition, when the display data is changed as shown by the arrow l2 of the figure leaving the display location as it is, only the contents of the register 70, i.e., only the parameter (a) may be changed. Moreover, when the display data to be superposed is changed as shown by the arrow l3, the contents of the register 70 i.e., the parameter (a) may be changed. (but, in that case, the contents of the register 101a of Fig. 1 must be changed in order from Na to Na') (2) When employing the address converting part 500 of Fig. 9. The contents of the registers 501, 502, 503, and 504 may be changed every time the VSYNC signal is issued. For example, when only the display location as shown in arrow ℓ1 of Fig. 11 is changed, the contents of the registers 501, 502, 503, and 504 may be changed. In addition, when the display data is changed as shown by the arrow l2 leaving the display location as it is, only the contents of the register 504 may be changed. Moreover, when the display data to be superposed is changed as shown by the arrow l3, only the contents of the register 504 may be changed (but, in that case, the contents of the register 101 of Fig. 1 must be changed in order from Na to Na').

Claims: A control circuit of a raster scanning display unit comprising; (1) a video memory (2) for storing display data; (2) a read address generating part (1) for generating a read address of the video memory (2) in synchronism with an address clock; and (3) an address converting part (5, 500) provided between the video memory (2) and the read address generating part (1), including; (a) a judging part for judging whether or not the area in concern is an area where superposed display is effected, (b) memory means (70, 504) for storing a difference between a head storage address of superposing display data and a head storage address of superposed display data (c) an adder (69, 515) for adding an output signal from said memory means to an output signal from said read address generating part; characterized by (d) selector means (68, 512) employing an output signal from said read address generating part and an output signal from said adder (69, 515) as input signals, and delivering any one of said input signals, wherein the selector means delivers the output signal available from said adder (69, 515) when the area in concern is an area where superposed display is effected; and said judging part consisting of; (aa) first memory means (501) for storing head address N1 of a prescribed area in which superposed display data is stored; (ab) second memory means (502) for storing a value N3 yielded by adding 1 to a final address of said prescribed area; (ac) third memory means (503) for storing, when a width of an area where superposed display is effected is reduced to the number of address clocks being b, a value N2=N1+b yielded by adding said b to said head address N1; (ad) fourth memory means (505) for storing a value y representing the width of one raster by a corresponding number of address clocks; (ae) latch means (518), said latch means being set when an address from the read address generating part gets said N1, and being reset when gets N3; (af) fifth memory means (516) for storing said N1 when said latch means (518) is reset, and storing a value yielded by adding y to the output value from the fifth memory means (516) every time a raster clock is issued after said latch means (518) is set; (ag) sixth memory means (517) for storing said N2 when said latch means (518) is set, and for storing a value yielded by adding y to the output value from the sixth memory means (517) every time a raster clock is issued after said latch means is set; (ah) a first comparator (508) for comparing an output signal from said fifth memory means with an address signal from said read address generating part; (ai) a second comparator (509) for comparing an output signal from said sixth memory means with an address signal from said read address generating part; (aj) second latch means (519), said second latch means being set by a coincidence signal from said first comparator while being reset by a coincidence signal from said second comparator; and (ak) designation means for designating that the area in concern is an area where superposed display is effected where said two latch means are both set.

Inventors: SATO, NOBUYUKI OKI ELECTRIC INDUSTRY CO. LTD.
Applicants: OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1986
Main classification: G09G1
IPC codes: G09G5