IMPROVEMENTS TO THE SYSTEMS FOR BIDIRECTIONAL DIGITAL TRANSMISSION WITH ECHO-CANCELLATION

Abstract: The improvements to the system for bidirectional digital transmission with echo-cancellation allow the measurement of the received data signal (4) and the automatic adaptation of the attenuator (SA) and of the line equalizer (EQ). They are implemented by using circuits already present in a conventional system, as well as auxiliary circuits (SL, LC).

Description: The present invention relates to transmission of digital data and speech signals on a subscriber line and more particularly concerns improvements to the systems for bidirectional digital transmission with echo cancellation. It is known that most high-speed digital-transmission systems (e.g. 144 kbit/s), designed to operate on subscriber's lines within the national or private networks, require an equalizer of the received signal. In fact, the transmission line introduces attenuations of different value depending on the frequency of the transmitted signal, which thus results distorted. Besides, the receiver must present the possibility of adjusting the gain, since the transmission line has a different length dependent on the subscriber's distance from the exchange, and hence the introduced attenuations are different and cannot be predetermined. A continuous or step manual adjustment requires the intervention of an operator during the installation, and, owing to possible variations in the line characteristics, during the operation. The high cost of such interventions and the necessity of keeping in time the best system performances render the use of automatic gain controls particularly advantageous, in order to obtain an automatic receiver adaptation to the amplitude of the received data signal. In order to automatically carry out the operation above the amplitude is to be precisely estimated. According to the known solutions, such estimate is carried out by measuring the dc voltage obtained from the signal submitted to a non-linear operation, usually a detection of the envelope obtained by rectifying, possibly followed by a low-pass filtering operation. However, these operations present a number of disadvantages, due both to low sensitivity of non-linear components when handling very weak signals, and to the dispersion of the characteristics of the components themselves. In fact, non-linear components with strictly equal parameters, i.e. such as to ensure a good repeatability in the accuracy and sensitivity properties of the detector, cannot be achieved by present integrating techniques. There is also the difficulty of reproducing a precise reference voltage, the voltage to be measured may be compared with. The drawbacks above are overcome by the improvements to the systems for bidirectional digital transmission with echo-cancellation, provided by the present invention, which allow a high accuracy of the automatic gain control in the system receiver, without presenting the problems of repeatability and sensitivity due to the limitations of technological processes. They prove of particular interest in transmission systems based on echo-cancelling technique, since for the invention embodiment components already present in the structure can be used; namely the digital-to-analog converter, the threshold comparator and other circuits, which, being dimensioned in function of the system, present a sensitivity and dynamic range certainly compatible with the signal to be processed and with the accuracy required. The present invention relates to a system for bidirectional digital transmission with echo-cancellation, of the type comprising: an encoder to encode in line code the data signal at its input; a hybrid to transfer to the line the data signal supplied by the encoder and to transfer from the line the data signal received; a remotely-controllable attenuator; a remotely-controllable equalizer; an echo canceller to supply an estimated-echo signal, correlated with the encoded data signal and with a digital signal supplied by a threshold comparator; an adder to sum the received data signal, supplied by said attenuator and equalizer, to the estimated echo signal supplied by a digital-to-analog converter; said threshold comparator to detect zero crossings of the signal supplied by said adder; a double threshold comparator to detect positive and negative threshold crossings of the signal supplied by said adder; a decoder to decode the signal supplied by said double threshold comparator and to supply at the output the data signal received; a time base circuit; such a system is known from EP-A- 0071 192. The system of the invention is defined by the characterizing features of claim 1. These and other features of the present invention will be apparent from the following description of a preferred embodiment thereof, given by way of example and not in a limiting sense, with reference to the annexed drawing showing a block diagram of a system for bidirectional digital transmission on a two-wire line with echo-cancellation and automatic gain control. The continuous data flow to be sent to transmission line 3 arrives on wire 1 and the corresponding timing signal on wire 21. They access a circuit CO, where they are duly encoded in the desired line code. The encoded data, present on wire 2, are simultaneously sent to hybrid HC and to echo-canceller EC. The signal to be transmitted is sent through the hybrid partly on the two-wire line 3, partly on a balance load and, due to anavoidable unbalance and reflections along the line, onto wire 4 connected to the input of receiving end. Also the useful signal, arriving from the remote transmitter, is present on wire 4. This signal accesses a step attenuator SA, controlled by the signal on wire 9, and hence, through wire 6, step equalizer EQ, controlled by the signal on wire 8. The signal equalized by EQ is sent through wire 7 to an adder SO, by which it is added to the estimated echo-signal supplied on wire 10 by a digital-to-analog converter DA, in order to cancel the interference produced by the local transmitter on the useful signal. A threshold comparator ZC detects zero crossings of the signal present on wire 12, connected to SO output, supplying at the output on wire 13 a digital flow for the estimate of echo-signal. A double comparator DC is also connected to wire 12. DC compares with a positive and negative threshold the received signal, which usually has three levels, and supplies at the output on wire 23 a digital flow wherefrom a decoding circuit DE recovers the transmitted data signal. Said signal is made available at the output on wire 17, with the phase determined by the clock signal present on wire 16. Echo-canceller EC processes according to a suitable algorithm the signal on wire 13 and the signal to be transmitted on wire 2, and supplies digital estimated-echo signal on wire 14 to the already-described converter DA. The timing signals for the main system blocks are generated by a time-base circuit BT and are made available at the output on wire 15. It extracts the synchronism information from the signal present on wire 23 at the output of comparator DC. Let us see now how the just-described conventional transmission system is modified according to the invention. It is worth noting that the adjustments of step attenuator SA and equalizer EQ are effected only in the initial transmission phase, since the transmission line parameters are supposed to undergo negligible temperature-induced variations during transmission. In the transmission systems with echo-cancellation technique, the starting procedures usually provide a training phase during which the initial canceller updating is effected. Since during this phase no operative signal is present on the line, a time interval can be dedicated to the amplitude measurement of the received signal. This initial phase is detected and controlled by a logic circuit SL, which receives on connection 18 the information on the channel activity state and enables echo-canceller EC, through wire 19, to updating operations. Besides, in a suitable time interval of the initial phase it starts the procedure for the measurement of the maximum amplitude of the received signal, using known methods in the domain of circuits for analog-to-digital conversion. To do that, SL controls through wire 20 a logic circuit LC, containing a sequencial circuit apt to emit an increasing digital sequence on wire 14. By driving the input of converter DA by such a sequence, at the analog output connected with wire 10 a voltage ramp is obtained with accuracy equal to ±1/2 LSB (LSB = less significant bit). This voltage ramp is added by SO to the signal received from the remote terminal, no interference being generated by the local transmitter, inactive in this initial phase. As long as the voltage ramp has a value inferior to the amplitude of the received signal, which has a null dc component, the signal at the output of SO assumes both positive and negative values and comparator ZC detects the respective zero crossings. When the ramp amplitude equals and then exceeds the received signal amplitude, transitions stop. A transition detector, contained in circuit LC, receives the signal supplied on wire 13 by comparator ZC and when the transitions stop reads the digital value attained by the ramp, with an accuracy of ±1/2 LSB. A correspondence matrix contained in LC supplies over wires 8 and 9 the suitable commands for attenuator SA and equalizer EQ, on the basis of the digital value obtained from the measurement of the amplitude of the received signal. These circuits are as a consequence adjusted to the signal level and to the line conditions for the link duration. Another already-known method, used in the domain of analog-to-digital converters, is no longer based on the use of linearly-increasing digital sequences, and hence on comparisons of the received signal with voltage ramps, but on the use of digital values with halved increment after each addition (dichotomic method). In this case logic circuit LC supplies a predetermined number of digital values with positive or negative increments dependant on whether zero crossings at the output of comparator SC have been found or not. A binary digit relative to received signal amplitude is obtained at each comparison, and, hence, adjustments of attenuator SA and equalizer EQ can be carried out through the correspondence matrix. After these operations the initial phase ends and the usual bidirectional transmission can begin. Logic circuit LC communicates occurred gain adjustment to circuit SL through wire 22, the echo-canceller is enabled again through wire 19 and the external transmission devices are informed through connection 18 that the system is ready to transmit. It is clear that what described has been given only by way of non limiting example. Variations and modifications are possible without going out of the scope of the invention.

Claims: A system for the bidirectional digital transmission, with echo-cancellation, of the type comprising: an encoder (CO) to encode in line code the data signal at its input (1); a hybrid (HC) to transfer to the line (3) the data signal supplied by the encoder (CO) and to transfer from the line the data signal received; a remotely-controllable (9) attenuator (SA); a remotely-controllable (8) equalizer (EQ); an echo canceller (EC) to supply an estimated-echo signal (14), correlated with the encoded data signal (2) and with a digital signal (13) supplied by a threshold comparator (ZC); an adder (SO), to sum the received data signal, supplied by said attenuator and equalizer, to the estimated-echo signal (14) supplied by an digital-to-analog converter (DA); said threshold comparator (ZC) to detect zero crossings of the signal supplied by said adder; a double threshold comparator (DC) to detect positive and negative threshold crossings of the signal supplied by said adder; a decoder (DE) to decode the signal supplied by said double threshold comparator and to supply at the output the data signal received; a time base circuit (BT); characterized in that it further comprises a first and a second logic circuit (SL,LC) said first logic circuit (SL), being arranged, the basis of the information on the link time phase received at the input (18), to alternatively enable (19,20) said echo canceller (EC) or the second logic circuit (LC), so that said digital-to-analog converter (DA) receives respectively (14) either the estimated-echo signal or, during an initial phase of the link, a suitable digital sequence generated by said second logic circuit (LC) which, converted into analog form, is added in said adder (SO) to the received data signal; said second logic circuit (LC), which receives at the input (13) the information on the zero crossings supplied by the threshold comparator, being adapted to generate at a suitable instant, control signals (9, 8) for said attenuator (SA) and for said equalizer (EQ), in order to control the transmission system gain, said control signals being correlated to the amplitude of the received data signal (4), and also to generate and to send a signal (22) of gain adjustment occurence to said first logic circuit (SL), which re-enables the echo canceller (EC), inhibits the second logic circuit (LC) and communicates (18) the availability of the system to transmission operations. A system according to claim 1, characterized in that said suitable sequence is a linearly-increasing digital sequence from which a voltage ramp is obtained at the output of said digital-to-analog converter (DA), the end of zero crossings detected by said threshold comparator (ZC) determining said suitable instant, during which there is present at the output (14) of the second logic circuit (LC) a digital value representative of the amplitude of the data signal received. A system as in claim 1, characterized in that said suitable sequence is a digital sequence with successive increments or decrements of value equal to half the preceding one, said suitable instant being determined by the end of a predetermined number of additions carried out in said adder (SO), the digital value representative of the amplitude of the received data signal consisting of the succession of zero crossings supplied by said threshold comparator (ZC). A system as in claim 3, characterized in that said second logic circuit (LC) is arranged to emit successive signals (14) with an increment or decrement with respect to the preceding value according to the type of zero crossings supplied by said threshold comparator. A system as in claim 1, characterized in that the correlation between said control signals (9, 8) and the amplitude of the received data signal (4) is obtained through a correspondence matrix.

Inventors: AMBROSIO, RENATO, BROSIO, ALBERTO, FAUSONE, ALFREDO, TOFANELLI, ADLER
Applicants: SIP SOCIETA ITALIANA PER L'ESERCIZIO TELEFONICO P.A.
Application year: 1986
Main classification: H04L5
IPC codes: H04B3, H04L5