DIGITAL ZERO-IF SELECTIVITY SECTION

Abstract: A digital Zero-IF Selectivity Section (DZISS) (20, 20'). The DZISS of the present invention teaches a topology that facilitates realization in both transmitter (20') and receivers (20). In the preferred low-speed embodiment, the digital filters (32, 32', 33, 33') are comprised of cascaded filter sections (64a-64d) employing decimation (66) to reduce the data rate. In the preferred high-speed embodiment, the digital filters (32, 32', 33, 33') are more sophisticated as at least the first filter section (64') is decomposed to enable high-speed operation. Decimation (66) is also employed on the high-speed embodiment to allow subsequent circuitry to operate at a lower data rate thus consuming less power. In an alternate embodiment, applicable to the low-speed and high-speed preferred embodiments, sections of the digital low pass filters (100A, 100B) are time multiplexed (104) effectuating a cost and space savings.

Description: DIGITAL ZERO-IF SELECTIVITY SECTION Background of the Invention This invention relates generally to intermediate frequency circuits and more particularly to digital intermediate frequency circuits where the intermediate frequency is zero Hertz. Historically, intermediate frequency (IF) sections have been employed in transmitters and receivers to perform the major portion of a radio's selectivity since it may be technically difficult, or cost prohibitive, to develop sufficiently selective filters at the transmitted or received frequency. Transceivers may have more than one IF section. For example, some receivers employ two IF sections for recovering the transmitted information. These receivers are generally referred to as dual conversion receivers, whereas a single IF receiver would be referred to as a singular conversion receiver. Generally, any receiver with an intermediate frequency of zero Hertz is referred to as a direct conversion receiver. Analog implementations of direct conversion receivers suffer from a variety of detriments including local oscillator (LO) radiation, which results from imperfect reverse isolation through the mixers, and may desense nearby receivers. Further, radio desense performance can be degraded by nonlinear effects in the mixers causing self-mixing of on-and off-channel signals which creates DC offsets and audio distortion. Also, in an application involving the reception of frequency modulated (FM) signals, the direct conversion analog receiver has no means of limiting the zero-IF signal. This causes unpredictable performance in fading and other adverse conditions. The aforementioned dual conversion receiver alleviates some of the direct conversion problems. The additional isolation obtained by a dual conversion receiver solves the LO radiation problem. However, the solution is achieved at the cost of an additional mixer and local oscillator, in addition to a narrow band (generally crystal) filter to achieve the required isolation. Further, having a traditional IF section prior to the DC-IF section essentially band-limits the incoming signal to one channel. Thus, the self-mixing products caused by the nonlinear effects of the mixers generally will not fall into the passband of the filter in a dual conversion receiver. Although the dual conversion receiver solves many of the problems experienced by the direct conversion receiv¬ er (although at additional cost and size requirements) , the dual-conversion receiver experiences other detriments. As previously mentioned, the direct conver- sion FM receiver cannot limit the zero-IF signal. Thus, the use of unconventional detection methods are required. The typical solution to this problem is to up-convert the zero-IF signal to a third IF frequency where it can be limited and detected using conventional circuits. Up- converting requires another local oscillator, additional mixers and a summing circuit..- Further,. up-converting creates yet another problem. The quadrature paths in an analog receiver cannot be perfectly balanced for amplitude and phase characteristics because of the nonexact performance of the mixers and filters. Thus, a beat-note is (created due to imperfect cancellation in the summer) which degrades hum and noise performance and causes audio distortion. A proposed solution to this problem is to phase lock the LO to an incoming pilot signal. This necessitates additional circuitry at the transmitter to transmit the pilot signal and also requires additional circuitry at the receiver to develop the phase lock loop and pilot filters. Lastly, the phase lock loop lock-time and pull-in range become critical receiver parameters. Although the above discussion has concerned receivers, similar problems are experienced in transmitter IF sections, even though transmitter IF topologies are generally different than those employed in receivers. Generally, any analog implementation of an IF section will experience temperature and part-to-part variations that may degrade the IF section performance. Therefore, a need exists for an IF section that is insensitive to part and temperature variations and solves the above mentioned problems experienced in analog implementations of IF sections. Summary of the Invention In practicing the present invention, a digital quadrature local oscillator is employed to generate digitized discrete-time amplitude pulses of sine and consine waveforms which are then combined with an input signal in a digital quadrature mixer. In a receiver, the digital quadrature mixer down-converts the input signal to occupy a frequency band centered about zero Hertz. Subsequent digital filtering removes any unwanted mixing components so that only the signal centered about zero Hertz is communicated to any recovery circuitry in the receiver. In a transmitter, the digital quadrature mixer up-converts a digitally filtered input signal to occupy a frequency band centered about the selected frequency of the local oscillator signals. Therefore, it is an object of the present invention to provide a digital zero-IF selectivity section that alleviates the aforementioned problems experienced in analog implementations. It is a further object of the present invention to provide a digital zero-IF selectivity section having a topology that can be used for both transmitters and receivers. It is yet a further ob ect of the present invention to provide a digital zero-IF selectivity section capable . of operating at high sampling rates. Accordingly, these and other objects are achieved in the present digital zero-IF selectivity section which may be used in a transmitter -or receiver. The digital zero-IF approach avoids all the above mentioned problems. The mixers are perfectly linear, and the two quadrature paths may be matched perfectly. A conventional first IF section is not required in the digital implementation and the dynamic range of the digital zero-IF section can be made as large as necessary by selecting appropriate data word lengths. Digital FM detection can be performed directly at DC eliminating the need to up-convert to a third IF, and the need for a phase-locking arrangement to a pilot signal. Brief Description of the Drawings The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may be understood by reference to the following description taken in conjunction with the accompanying drawings, and the several figures of which like referenced numerals identify like elements and in which: Figure 1 is a block diagram of a digital zero-IF selectivity section especially adapted for use in a receiver; Figure 2 is a block diagram of the digital zero-IF selectivity section especially adapted for use in a transmitter; Figure 3 is a block diagram of the digital quadrature LO of Figures 1 and 2; Figure 4a is a block diagram of the digital lowpass filters of Figure 1; Figure 4b is a block diagram of the digital low pass filters of Figure 2; Figure 5 is a block diagram of one of the lowpass filter sections of Figure 4a or Figure 4b-; Figure 6 is graphical representation of the response of the digital low pass filter section of Figure 5. Figures 7a-c are graphical representations of a filter decomposition technique and resulting filter response; Figure 8 is a graphical representation of a combining filter technique used in the prior art; Figures 9a-b are graphical representations of the combining filter technique and filter response as taught by the present invention; Figure 10 is a graphical representation of a decomposed and combined filter response as taught by the present invention; Figure 11 is an embodiment of a digital low pass filter section having the response shown in Figure fθ; Figures 12a-c are time domain and frequency domain representations of exemplary signals appearing at point A of Figure 1 ; Figures 13a-c are time domain and frequency domain representations of exemplary signals appearing at point B of Figure 1 ; Figures 14a-c are time domain and frequency domain representations of exemplary signals appearing at point C of Figure 1 ; Figures 15a-c are time domain and frequency domain representations of exemplary signals appearing at point D of Figure 1 ; Figure 16 is a block diagram of a receiver employing the digital zero-IF selectivity section of Figure 1 ; Figure 17 is a block diagram of a transmitter employing the digital zero-IF selectivity section of Figure 2; Figure 18 is a block diagram of an alternate embodi¬ ment of the digital zero-IF selectivity section where the digital lowpass filters are divided into high speed and low speed sections and the low speed sections are time multiplexed which effectuate a cost and space savings. Detailed Description of the Preferred Embodiment Referring now to Figure 1 , a digital zero-IF selectivity section (DZISS) is depicted in block diagram form, which has been constructed in accordance with the present invention and, further, which is especially adapted for use in a receiver. Basically, DZISS 20 is comprised of an in-phase -mixer 22, a quadrature-phase mixer 24, a digital quadrature LO 26 (providing an in-phase LO signal 28 and a quadrature phase LO signal 30) , two digital lowpass filters .32 and 32' , and a clock source 34. To employ the DZISS circuit in a receiver, identical digital information may be applied to both the in-phase mixer 22 and the quadrature-phase mixer 24 at input ports 36 and 38 respectively. Generally, ports 36 and 38 are not single lines, but are in fact multiple lines representing an L-bit digital word. The actual length of the digital word used in any given application is dependent upon many factors, including: the resolution required, the dynamic range required and the sampling frequency of the received signal. For example, a word length of 12 bits is considered to have an acceptable performance in receiving a typical radio signal sampled at 20MHz. Mixers 22 and 24 have as a second input quadrature LO lines 28 and 30 respectively. As previously mentioned, these LO signals are not single connections, but are M-bit discrete time representations of signals that are 90° apart in phase (i.e., sine and cosine waveforms) . Mixers 22 and 24 perform an arithmetic multiplication of the L-bit input word and the M-bit LO word, rounding the result to form an N-bit output word that is applied from output ports 37 and 39 (of mixers 22 and 24) to the digital lowpass filters input ports 40 and 42 respectively. The digital word length parameters, L, M and N may be selected to yield acceptable noise performance. As the digital word is lengthened, more quantization levels are available to represent the signal. The smaller quantization increments lead to improved noise performance as is well understood in the art. This process is analogous to an analog implementation of a mixer producing sum and difference sine and cosine products in an analog mixer. However, all the aforementioned problems of an analog mixer are avoided in a digital implementation because of the perfect linearity of the mixers. The dig ital word resultant from the aforementioned multiplication is applied to digital filters 32 and 32' to band-limit the received frequency spectrum. Digital filter 32 and 32' are identical in structure and may be formed from a recursive filter topology which will be hereinafter described in greater detail. Following the filtering process, the digital signals are output through ports 41 and 43 and sent on to any digital demodulating structure that may be employed. For example, it may be advantageous to effectuate digital demodulation by the use of a programmable digital signal processor (DSP) . Referring now to Figure 2, the DZISS, here configured for operation in a transmitter, is depicted in block diagram form. The digital signals to be transmitted would be applied to ports 47 and 51 of lowpass filters 33 and 33' which band-limits the spectrum of the signals and applies them to input ports 36 and 38 of mixers 22 and 24, respectively. As previously described, mixers 22 and 24 accept as a second input LO signals 28 and 30, respectively. The up-converted digital signal is output at ports 37 and 39 which may then be sent to any conventional summing circuit where the signals would be arithmetically added (binary addition) as is well known in the art. The information signal may then be converted to analog form through a D-to-A converter and transmitted by conventional means. From the foregoing discussion it should become apparent that a simple "inversion" of the input/output data flow of mixers 22 and 24 and selection of digital low pass filters are all that is required to change the DZISS topology from a receiver configuration to a transmitter configuration or vice-versa. Thus, the DZISS 20 of Figures 1 and 2 afford a simple, inexpensive and universal IF section that may be readily employed by both receivers and transmitters. Referring now to Figure 3, digital quadrature LO 26 is depicted in block diagram form. Implementation of a DZISS hinges on the ability to generate accurate and stable discrete time representations of sine and cosine waveforms for the quadrature .mixing process. Thus, the digital quadrature LO 26 is a key component of the DZISS. Traditional techniques, such- as the digital feedback oscillator, use multipliers in the feedback path thereby causing a severe limitation in the operating speed of the oscillator. More advanced techniques, such as the direct ROM (read only memory) look-up approach, utilize the fact that sine and cosine waveforms can be expressed in real and imaginary parts of the unit magnitude complex phasor eJ2 π fc(nT) j where f c is the desired carrier frequency and nT is the discrete time variable (T equals the sampling period which is equal to 1 /sampling rate). However, the direct ROM approach simply stores all possible phasor values which may result in large ROM requirements if the number of desired frequencies, and hence, the number of required phasors , is large. Often this large ROM requirement becomes prohibitive in a digital quadrature LO implementation due to cost and size requirements. The disclosed invention uses a factored-ROM approach utilizing the fact that the phase angle of the unit magnitude phasor can be broken into a complex product of coarse and fine phasors. Thus, the unit magnitude phasor eJ0 can be represented as e-J^c • e-^f. Therefore, the unit magnitude phasor can be realized by having separate coarse-value phasors and fine-value phasors stored in ROM which are multiplied together to get the discrete time sine and cosine values required for the quadrature mixers. The advantage of this 'factoriza- tion is that the amount of ROM necessary to store the coarse-value and fine-value phasors is greatly reduced from that required of the direct ROM look-up approach. The expense paid for this ROM size reduction is the introduction of circuitry to perform the complex multiplication of coarse and fine phasors. Generally, a complex multiplication can be implemented with four multipliers and two adders. By judicious selection of the fine-value phasor, and recalling that the cosine of a small angle can be approximated by one, the ROM for the cosine fine-value phasor can be eliminated. Further, by approximating the small angle cosine values as one, two multipliers can be eliminated 'from the multiplication structure required to generate a complex product. This results in both a cost and size savings in the factored- ROM implementation. Referring now to Figure 3, the digital quadrature LO 26, as implemented using the factored-ROM approach, is depicted in block diagram form. Frequency information, in the form of an M bit binary number proportional to the desired frequency, is loaded into the channel frequency latch 44. Channel frequency latch 44 may be realized in many different forms. For example, assuming that M=20, five cascaded 74LS175's (Quad D flip-flops), manufactured by Motorola, Inc., and others, provide an acceptable implementation. Those skilled in the art will appreciate that channel frequency latch 44 may be loaded by various means. For example, in a single frequency radio the. channel frequency latch could be permanently loaded with a single binary number. For multiple frequency radios, channel frequency latch 44 could be loaded from an EPROM or ROM look up table or calculated and latched by a microprocessor. The output of channel frequency latch 44 is coupled to a binary summer 46. It will be understood by those skilled in the art that the following discussion of digital quadrature LO 26, all coupling lines inbetween the functional blocks are in fact multi-bit binary words and not single connections. The output of adder 46 is coupled to phase accumulator 48. Phase accumulator 48 can be implemented .is an M bit binary latch which is used to hold the address of the next location of ROM to be addressed. Thus, the output of phase accumulator 48 is coupled to cosine coarse-value ROM 50, sine coarse-value ROM 52, and sine fine-value ROM 54 (recall that fine-value cosine ROM is not required as it is being approximated by one). Further, the output of phase accumulator 48 is fed back into summer 46 to be added (modulo 2*^) to the binary nimiber representing the channel frequency information located in the channel frequency latch 44. The output of phase accumulator 48 is updated once every clock pulse which is generally the sampling frequency. The result of this binary addition, is that phase accumulator 48 is holding the binary sum (proportional to phase) of the last address plus a binary vector contained in the channel frequency latch. This number indicates the next address to be required to create the quadrature LO signals 28 and 30. In actual implementation, the binary word output from phase accumulator 48 is partitioned into two segments, such that only the higher order bits of phase accumulator 48 are sent to ROM 50 and 52, and the lower order bits are sent to ROM 54. As previously stated, these bits are the addresses for the ROM locations. Upon receiving an address, ROM's 50, 52 and 54 output the digital binary word located at the received address on their respective output ports. The digital quadrature signals are then arithmetically generated from the three binary numbers. To generate the cosine waveform (i.e., the real component of the complex waveform) , the outputs of sine coarse-value ROM 52 and sine fine-value ROM 54 are first multiplied in multiplier 56. The output of multiplier 56 is fed to summing circuit 60 where it is subtracted (2's complement form) from the output of cosine coarse-value ROM 50. This arithmetic process yields the cosine-value which is output on port 28 and coupled to quadrature mixer 22 of Figure 1. To generate the sine values of the digital quadrature LO the outputs of the cosine coarse-value ROM 50 and sine fine value ROM 54 are multi¬ plied in multiplier 58. Both multiplier 56 and 58 may be realized as, for example, an MPY016K manufactured by TRW, Inc. The output of multiplier 58 is fed to a summing circuit 62 where it is summed with the output of sine coarse-value ROM 52. Summing circuit 62 outputs via connection 30 the discrete time sine value digital word which is coupled to quadrature mixer 24 of Figure 1. Therefore, since the discrete time values of the sine and cosine signals are calculated mathematically, perfect 90° phase control is achieved using minimal ROM space. The amount of coarse-value ROM required can be further reduced by taking advantage of symmetries in the cosine and sine waveforms, and thereby storing only the values of the unit magnitude phasor residing in the first octant (i.e., the first 45°) of the phasor unit circle. Those skilled in the art will appreciate that the unit magnitude phasor represents sine or cosine values rotating through 360°. Due to the symmetrical nature of sinusoidal waveforms, the values of the cosine and sine waveforms over the first octant of the unit circle are identical to the values of these waveforms over any other octant, except for possible sign changes and reversal of roles (i.e., sine becomes cosine and vice versa). There- fore, the only coarse-value phasors that are required are those in the first octant provided there is an indicator of which octant the phasor is currently residing, and there is circuitry present to negate (i.e., change sign) and/or exchange the outputs of coarse-cosine ROM 50 and coarse-sine ROM 52 according to the current octant. An octant indicator is readily implemented using three binary bits of the ROM address. For example, the three most-significant-bits (MSB's) could be used to indicate the octant, and the remaining bits used to address the ROM for the coarse-valued phasor. Thus, the. factored ROM LO reduces the ROM area while maintaining acceptable frequency resolution. For example, to implement a digital quadrature LO 26 that operates at 20 MHz, the coarse-value ROM's 50, 52 could each be implemented in a 32 x 1 6 ROM and the f ine-value s ine ROM 54 could be implemented in a 1 28 x 8 ROM. This would result in frequency resolution of approximately 600 Hz using approximately 2000 bits of ROM. The factored-ROM configuration is preferred for operation at high sampling rates, since, except for the phase accumulator, there is no circuitry connected in a feedback manner. This allows the rest of the LO circuitry (especially multipliers 56 and 58, which represent the main speed bottleneck) to be pipelined to achieve a very high operating rate. Pipelining would consist of introducing latches at certain critical points, such as within the multipliers themselves, as is well understood in the art. Thus, a factored-ROM L0 is described which outputs M-bit discrete time digital quadrature signals which exhibit a selected frequency. Referring now to Figure 4a, the digital lowpass filter 32 is depicted in block diagram form. Those skilled in ' the art will appreciate that digital filter 32 and 32' of Figure 1 are in fact identical filters and are differentiated only to facilitate the discussion of the DZISS disclosed by the present invention. All digital filter structures are made up of basi¬ cally the three same components: adders, multipliers, and delay circuits (generally latches or RAM) . The factors affecting the performance of a digital filter all have to do with the fact that the various parameters of the filters are quantized, that is, they have finite precision rather than the infinite precision available in analog filters. The finite precision of a digital filter basically gives rise to three major performance effects that must be controlled in any implementation of a digital filter. Coefficient roundoff is one of these effects. The constant valued coefficients found in a digital filter determine its frequency response. The result of rounding these coefficients so that they may be represented digitally in a finite number of bits causes a permanent , predictable change in the filter response. This is analogous to changing the RLC values in an analog filter; however, digital filters do not suffer the detriment of temperature variations as in analog filters. Generally, the higher the Q of the filter (i.e. narrow bandwidth filters compared to the sampling rate) the more the frequency response is distorted by coefficient rounding, unless special structures are employed. Judicious selection of the filter structure is of key importance in light of the fact that IF filters are generally extremely narrow band, or high-Q, filters. Round-off noise is another of the performance characteristics that must be controlled in a digital filter. Data entering a digital filter has, of course, been rounded to a finite number of bits, and it is almost always necessary to perform additional roundings at certain points within the filter. Such rounding operations create an error or noise signal in the digital filter. For example, if the digital word length used in a filter is 16 bits and the coefficients are represented in 10 bits each multiplication operation would create a would create a 25 bit product, which must be rounded to 16 bits before the result may be put back into memory. The last major effect that is controlled in a digital filter is the overflow level. The fact that data samples are represented in a finite number of bits means that there is a maximum allowable absolute value associated with every node in the filter which, if exceeded, results in an overflow phenomenon (generally wrap-around if 2's complement binary arithmetic is used). This largest allowed data value, coupled with the level of roundoff noise described previously, determines the dynamic range of the filter. Several conventional structures are available to implement digital filters. A straight forward design approach is to cascade sections of first or second order direct-form filters until the desired filter order is achieved. The advantages of this method are its simplicity, regularity, and ease of actual filter design. However, the conventional approach also suffers from many detriments mostly stemming from the fact that high precision (for example 16 bit) filter coefficient representation is required to implement a narrowband filter. This necessitates highly complex multiplications (for example 16 x 20 bits) be performed in the feedback paths of the filter sections. The multiplications place severe speed and time limitations on the operation of the filters. Further, pipelining, a common technique used to speed logic circuits, cannot be employed in feedback loops. Lastly, high precision high speed multipliers consume tremendous amounts of power. Referring now to Figure 4a, the digital lowpass filter employed in the DZISS is depicted in block diagram form. In the preferred low-speed embodiment, the digital lowpass filter 32 may be comprised of four cascaded lowpass filter sections 64a-d which are identical in topology and do not employ multipliers. Between lowpass filter section 64a and 64b is sampling rate reducer 66. Sampling rate reducer 66 may be realized in many forms. For example, if the digital word length is 24 bits, then four cascaded 74LS174'S (Hex D flip-flops) manufactured by Motorola, Inc., and others, provide an acceptable implementation. Those skilled in the art will appreciate that any number of digital filter sections may be employed and that sampling rate reduction may be used between any and all filter sections. Further, filter sections having identical topologies are not required but simply facilitate the actual implementation. High speed digital logic circuits consume high power. Therefore it is advantageous to reduce the sampling rate of the digital signal as early as possible to lower the power consumption of the sections following the sampling reduction point. The present invention brings the sampling rate reduction into the filter structure inserted immediately after the first filtering section. Further sampling rate reduction is often employed after digital lowpass filter 32 and prior to the audio demodulation section of a radio receiver. Sampling rate reduction, commonly referred to as "decimation" in digital signal processing terminology, consists simply of discarding all but a select subset of the previous output samples. Since decimation is equivalent to resampling at a lower rate, those skilled in the art will appreciate that the bandwidth of the signal being resampled must be less than that of the higher-rate signal by an amount necessary to prevent aliasing. Decimation is generally desirable because a given subsequent operation may often be realized with less circuitry if it operates at a lower speed. Further, for CMOS (complementary metal-oxide semiconductor) technology power consumption is reduced at lower operating speeds. The narrowband digital filters 32 and 32' of the present invention thus permit all subsequent circuitry to operate at an advantageously reduced rate. Referring now to Figure 4b, taken in conjunction with Figure 4a, the digital low-pass filter of Figure 2 is depicted in block diagram form. Basically, digital lowpass filter 33 is formed by rearranging digital lowpass filter 32 of Figure 4a. However, the sampling rate is increased in a transmitter. Accordingly, sampling rate increaser 69 is disposed between digital lowpass filter sections 64D and 64A to provide low-speed operation until the final filtering section thereby., minimizing power consumption. Sampling rate increaser 69 may be implemented as sample and hold circuits which output the same sample continuously until a next sample is received. This "interpolation" process can increase the sampling frequency of a digital signal N times by repeating the held sample N-1 times until the next sample is received. Interpolation does introduce sin(x)/x distortion however, in practice, this may be easily removed through equalization in previous audio processing stages as is well known in the art. Referring now to Figure 5, a digital lowpass filter section 64 is depicted in block diagram form. The filter employed in the DZISS is a recursive filter (i.e., the output signal is feedback, scaled, and summed at strategic points in the filter structure) having a narrow bandwidth and optimized for high-speed and low-sensitivity to the previously described detrimental effects of parameter quantization on digital filters. Basically, the digital lowpass filter 64 consists of 4 adders (2's complement) 68a-d, 2 digital latches 70a-b and 2 binary shifters 72a-b. As mentioned previously in the discussion of the digital quadrature LO 26, the individual connections of lowpass filter 64 as described in Figure 5 are multi-bit digital words and not single electrical lines. The input signal is applied to the input of subtracting circuit 68a. A second input to subtractor 68a is taken from digital latch 70b which is fed back from the output of the filter circuit. The difference (2's complement) result of subtractor 68a is next applied to the input of bit shifter 72a which presents the shifted first sum signal as one input of summer 68b. Bit shifter 72a shifts all bits of the data word outputted from subtractor 68a to the right (i.e., toward the least significant bit) by Na bits, effecting multiplication by a coefficient equal to 2"^ a . This bit shift may be implemented by an appropriate routing of the data lines from subtractor 68a to adder 68b. Thus, high operating speed of digital filter section 64 is facilitated, since there is no time delay associated with bit shifter 72a, as there would be in a coefficient multiplication implemented by a conventional multiplier circuit. Summer 68b adds to the shifted first sum signal the last output of summer 68b as held in latch 70a. Further, the last or previous output of summer 68b is applied to subtractor 68c. A second input to subtractor 68c is taken from digital latch 70b which, as previously mentioned, is taken from the output of the digital filter. The result of subtractor 68c is applied to bit shifter 72b which is coupled to summer 68d. Bit shifter 72b shifts all bits of the data word outputted from subtractor 68c to the right by Nfc bits, effecting multiplication by a coefficient equal o 2~Nb. Bit shifter 72b also facilitates high operating speed since no time delay is incurred. The parameters N a and N^ associated with bit shifters 72a and 72b, respectively, control the frequency response of digital filter section 64, and may be chosen to yield the response appropriate to the intended application. Summer 68d adds the second shifted sum signal to the previous output of 68d as held in latch 70b. The output of latch 70b is also the output of the digital lowpass filter section 64 and represents a band-limited representation of the input signal that was previously applied to the input of summing circuit 68a. From the foregoing discussion, those skilled in the art will appreciate that while multiplerless digital filters greatly increase the operating speed of the DZISS., the digital filters remain the predominate limitation on the DZISS operating speed. Accordingly, the present invention employs decimation immediately after the first filter section (see Figure 4a). However, decimation provides relief only to subsequent logic sections. Clearly, the first filter section must operate at a substantially higher data rate. Depending on the actual application, this operating speed burden on the first filter section may not be detrimental. However, in those applications where operating speed is a critical parameter, a need exists to relieve the burden of the first filter section, and thus, provide reliable high- speed operation. Accordingly, in the preferred high-speed embodiment, the present invention employs a "decomposed" first digital filter section. Filter decomposition techniques have been discussed, for example, by M. Bellanger, G. Bonnerot and M. Goudreuse in a paper entitled "Digital Filtering by Polyphase Network: Application to Sample- Rate Alteration and Filter Banks" , IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol ASSP-24, No. 2, April 1976. Referring now to Figure 6, an exemplary magnitude verses frequency plot of digital low pass filter section 64 is graphically depicted. As illustrated in Figure 6, digital low-pass filter section 64b provides a very narrow pass-band (several kHz) , and a stop-band extending to 10MHz. As with any digital filter, the response for fs/2 to fs (where fs is the sampling frequency) is the mirror image of that from zero hertz to fs/2 (here from 0 to 10 MHz). Thus, this example assumes a digital low pass filter operating at 20 MHz band-limiting a signal centered at zero Hertz. Referring now to Figures 7a-b, the decomposition technique is graphically illustrated showing the "poles" and "zeros" of the z-transform of the filter's transfer function positioned in the unit circle in the z-plane ^ Figure 7a shows two poles representing the filter- response described previously in Figure 6. The following description pertains to decomposition by a factor of two. Those skilled in the art will appreciate that other factors are possible. The original filter may be decomposed into two or more decomposed sections that will subsequently operate at a lower speed. The first step is to split the original filter Into two substantially identical filters by projecting the two poles through the origin as shown in Figure 7b. The filter magnitude verses frequency plot associated with Figure 7b is shown in Figure 7c. The decomposed filter of Figure 7c may operate approximately half as fast as the filter of Figure 6 thus effectuating a fifty percent reduction in operating speed. Examination of the filter responses in Figures 6 and 7c reveals that the reduced operating speed has modified the filter response. Those skilled in the art will appreciate that this change is caused by the introduction of the two additional poles in the transfer function as graphically illustrated in Figure 7b. Thus, it is necessary to compensate for the two additional poles if the original response is to be recovered. Referring now to Figure 8, the generally accepted compensation technique is graphically depicted. Basical¬ ly, the two poles added to decompose the original filter are "covered" (compensated for) by two corresponding zeros. Those skilled in the art will appreciate that adding two poles and corresponding zeros to any filter transfer function does not change the actual filter response, and therefore, the decomposed filter sections (now having four poles and two zeros) will have the same filter response as the original high speed filter section as shown in Figure 6. However, the present invention deviates from this generally accepted technique to achieve a practical implementation while contemporaneously achieving acceptable performance. Referring now to Figures 9a-b the combining (compensati g) technique employed in the present invention is graphically depicted. Departing from traditional practice, the present invention relocates the compensation zeros on 'the unit circle equidistant from the poles to be compensated at the point Z=-1 in the Z-plane. The predominant reasoning for this is that by positioning the two zeros at this point the coefficients of the compensating filter become 1, 2 and 1. That is, they become simple powers of two which can .be implemented by the shifting technique previously described in conjunction with shifters 72a and 72b of Figure 5. Those skilled in the art will appreciate the ease of realization and high operating speed capability of a digital filter possessing power of two coefficients. The filter response associated with the two unit-circle zeros is graphically depicted in Figure 9b. It should become apparent that in departing from an exact pole covering the reconstructed filter response will be somewhat modified. Referring now to Figure 10, the reconstructed filter response is shown. The unit circle relocation of the compensating zero creates a response imperfection at 10 MHz (see Figure 10 viewed in conjunction with Figure 6). In practice however, this imperfection is not significant and, as previously mentioned, affords a more readily realizable implementation of the combining filter. Referring now to Figure 11, in conjunction with the foregoing discussion and Figures 6-10, the decomposed filter structure is shown. A high speed multi-bit digital signal is applied to digital low-pass filter section 64' at the input to demultiplexer 65a. Demultiplexer 65a has two output ports to which route the input digital words in a alternating manner. _ Thus, since only every other digital word is present on either output port of demultiplexer 65a, the output data rate is one-half the input data rate. The data words are coupled to decomposed digital filters 66a and 66b which operate in parallel. Therefore, in each branch of low pass filter section 64' , two poles of filtering are employed, however, the operating speed has been reduced by fifty percent. After being filtered, the digital words are combined into a filtered version of the input data stream by multiplexer 65b. Thus, multiplexer 65b outputs a signal at the original input data rate. As previously discussed the combined filtered data words must pass through compensating or combining filter 67 so that the overall response of low pass filter section 64' is substantially the same as low pass filter section 64 of Figure 4a. It should be apparent that combining filter 67 operates at a higher data rate. Although facially this may appear inconsistant with the purpose of filter decomposition, recall from the foregoing " discussion that the filter coefficients of combining filter 67 are simple powers of two by virtue of the filter zero placement on the unit circle (see Figure 9a) . Therefore, the filter actually realized requires less circuitry due to the resulting coefficients, and thus, can readily operate at substantially twice the data rate of the original low pass filter section 64. Thus, the unit circle placement balances the need for an appropriate filter response and a practical filter realization. Digital low pass filter section 64' can be readily used in place of section 64 to provide a higher speed embodiment of DZISS 20. Generally, decimation is employed immediately after the first digital low pass filter section 64a (see Figure 4a) and accordingly, subsequent sections need not be decomposed provided an appropriate decimation rate is employed. The decomposition technique as embodied in digital filter section 54' affords an increase in operating speed capability of approximately 2-to-1. Those skilled in the art will appreciate that more extensive decompositions are possible (e.g., four parallel sections rather than two) , which would allow even higher operating speed. Thus, a tradeoff between operating speed and circuit complexity is made possible with this decomposition technique. As an example of the operation of the DZISS, the following discussion describes the demodulation of a tone transmitted to a receiver having a DZISS. Referring now to Figures 12a-c in conjunction with Figure 1, an input waveform is shown as a function of time in Figure 12a. This waveform would be applied to both input ports 36 and 38 of quadrature mixers 22 and 24. Although appearing as a continuous analog sinusoid, the waveform in Figure 12a is actually a series of discrete time finite amplitude samples as illustrated in Figure 12b. Figure 12b is an exploded time segment taken along the line 5-5 of Figure 12a. Thus, Figure 12b illustrates a portion of these discrete amplitude samples which occur at a spacing of 1/f s (where f s is the sampling frequency). Figure 12c illustrates the frequency spectrum (magnitude only) associated with the waveform of Figure 12c. The frequency spectrum of the s ignal appears wi thin the band-limited frequency region of +f s /2 as seen in Figure 1 2c. Referring now to Figure 13a-c in conjunction with Figure 1 , the digital quadrature LO signals are presented as a function of time and frequency. Figure 13a depicts cosine signal 28 which is provided from digital quadrature LO 26. As in Figure 12, Figure 13a is actually a series of finite amplitude samples closely spaced at 1/f s . Sine waveform B, generated- from digital quadrature LO 26 is seen in Figure 13b. These two waveforms constitute the complex waveform of the LC signal wherein the real component is the cosine waveform and the imaginary component is the sine waveform. The frequency spectrum of this complex waveform is depicted in Figure 13c. Referring now to Figures 14a-c taken in conjunction with Figure 1 , the signal waveforms at point C of Figure 1 are depicted. Figure 14a depicts, as a function of time, the output of in-phase mixer 22. Figure 14b depicts the time domain information signal from quadrature-phase mixer 24. Those skilled in the art will appreciate that each component contains a sum and difference frequency. The LO frequency is selected such that the difference frequency falls within the pass-band of digital low-pass filters 32 and 33. As previously mentioned, although appearing continuous in nature, the waveforms of Figure 14a and 14b are in fact discrete- amplitude pulses. The frequency spectrum associated with these waveforms is depicted in Figure 14c. Figure 14c illustrates the spectrum of Figure 12c which has been shifted by the frequency of ^0 * Figure 14c also contains a dashed representation of the passband response of the digital lowpass filters 32 and 33 to which the Figures of 14a and 14b are next applied. Referring now to Figures 15a-c taken in conjunction with Figure 1 , the output waveforms of the digital lowpass filters 32 and 32' are depicted as they would be seen at reference point D' of Figure 1. The digital lowpass filters have removed the higher sum frequency component of Figure 14c and have passed only the f^ Q - f Q signal. Again, these signals are in fact discrete amplitude pulses and not continuous waveforms. As can be seen in Figures 15a and 15b the recovered signals are still in phase quadrature at reference point D. These signals are now passed through output ports 40 and 42 to whatever audio demodulation section that may be employed in the receiver. The complex frequency spectrum associated with the signals of Figures 15a and 15b is depicted in Figure 15c. A mathematical representation of the transmitted tone demodulation of Figures 12-15, -is expressed below in terms of the unit magnitude phaser. The real and imaginary components of the unit magnitude phaser are expressed in terms of sine and cosine waves. A simple transmitted tone applied to point A can be represented as follows: = a/2 (ej J 2πfot e -j J 2πfot,. This signal is applied to quadrature mixers 22 and 24, together with the digital quadrature LO signals 28 and 30 respectively. The digital quadrature LO signal, complex waveform, can be expressed mathematically as follows: B - t ( / t. \ ) - ej J 2πfl η ot = cos2 „πf. t, +, j.sin2τrfl_ot ' The multiplication product output of mixers 22 and 24 is applied to digital lowpass filters 32 and 32' . The signals represented at point C can be represented as follows: C _ ,(+, ,) = a/ ,2r, [-e j J 2 τr ( f η lo + f o .) ^ t+e j J 2 τr ( f l. o -f o .) t. ]. = a/2 [ cos 2π ( f l. o +f o) t + cos 2. τr . + j a/2 [sin2τr (f. + f )t + sin 2π(f, -f )t] lo o lo o Lastly, the output waveform present at terminals 40 and 42 can be represented as follows: D(t) = a/2 e^ 27T(f lo- f o )i = a/2 cos 2π(fl,o-fo)t + j a/2 sin 2π(fl,o-fo)t Thus, the demodulation of a transmitted tone received by a receiver employing a DZISS section has been described both graphically and mathematically. Referring now to Figure 16, an exemplary block diagram of a receiver employing a DZISS is shown. Basi¬ cally, the received radio frequency signal would be de¬ tected on the antenna 74 and presented to preselector 76. Preselector 76 comprises an amplifier and a bandpass filter which may be implemented as a helical or ceramic filter as is well known in the art. The band-limited signal from preselector 76 is next applied to sample and hold circuit 78. Sample and hold 78 may also perform the function of converting the received analog signal into digital form. Those skilled in the art will appreciate that this function may be implemented in separate blocks of a sample and hold followed by a conventional A to D; however, for the purposes of this illustration they can be considered to be one in the ' same. In addition to the speed limitations previously described for lowpass filters 32 and 32' , the operating speed of sample and hold (and A-to-D) 78 will determine the maximum speed of the receiver (i.e. the faster the sample and hold circuit 78 can operate the higher the frequency bandwidth of the receiver) . The output of sample and hold circuit 78, although represented as a single line, is in fact a multi-bit digital word as previously described in conjunction with various sections of DZISS 20. These signals are split (identically) and applied to quadrature mixers 22 and 24 and the DZISS circuit operates, as previously described, to output a band-limited recovered signal centered at zero Hz. The output signal is applied to sampling rate reducers 80a and 80b to lower the sampling rate, and hence the required power consumption of the following circuitry. This decimation process is also performed in digital lowpass filters 32 and 32' as previously described. Once the sampling rate has been lowered to an acceptable level (for example from 100 MHz to 100 kHz), the signals, still in phase quadrature, are applied to demodulation and audio recovery circuit 82. Demodulation and audio circuit 82 can be implemented in one of many known techniques and in particular may be a programmable digital signal processor (DSP) as is well known in the art. The output of demodulation and audio circuit 82 may then be applied to an audio power amplifier and speaker to present the recovered audio to the receiver operator. Thus, a digital receiver employing the DZISS of the present invention is described. Referring now to Figure 17, an illustrative block diagram of a transmitter employing the DZISS of the present invention is shown. Basically, an input signal is applied to audio and modulator circuit ' 84, The input signal may be a voice signal. If so, audio and modulator circuit 84 may include an analog-to-digital converter. Conversely, the voice may have been previously converted to digital form prior to the audio and modulator block 84 eliminating the A-to-D requirement. Alternatively, the input signal may already be in digital form if it were generated, for example, by a voice synthesis circuit. A further function of audio and modulation block 84 is to split the audio signal into quadrature paths. These quadrature paths are applied separately to sampling-rate increasing circuits 86a and 86b. The increased sampled signal is now applied to digital lowpass filters 33 and 33' respectively. The filters band-limit the digital signals in the same manner as previously described in conjunction with- Figure 2. The band-limited signals are now applied to_ quadrature mixers 22 and 24 in addition to the .quadrature LO signals from digital quadrature LO 26. The output signals of quadrature mixers 22 and 24 are summed (2's complement) in summing circuit 88 and applied to D-to-A circuit 90. The output of D-to-A 90 consists of a series of discrete finite-width amplitude pulses, which are smoothed into a continuous waveform by lowpass filter 91 , which is coupled to the output port of D-to-A 90. The output of low pass filter 91 , now a continuous analog signal, is applied to power amplifier 92 to have the signal power increased by an appropriate amount depending predominantly upon the required range of the transmitter. The amplified signal is again band-limited by bandpass filter 94 to transmit only that portion of the spectrum that contains the information signal and not pollute the surrounding spectrum. The band-limited signal is broadcast through antenna 96 as is well understood in the art. Thus a transmitter employing the DZISS of the present invention is described wherein the digital signal is converted back to analog form immediately prior to transmission. Referring now to Figure 18, an alternate embodiment of the DZISS for use in a receiver is depicted in block diagram form. As previously described, the input signal applied to connections 36 and 38 are applied as a first input to multipliers 22 and 24. A second input to quadrature mixers 22 and 24 are the digital quadrature LO signals 28 and 30, respectively. The N-bit multiplied products of mixers 22 and 24 are next applied to a single section of the digital lowpass filter previously described in Figure 5. Digital lowpass sections 100a and 100b provide two poles of filtering to each quadrature path by either the high-speed realization as shown in Figure 11 or as embodied in Figure 5 for lower data rates. " After passing through filter sections 100a and 100b, the digital words are communicated to sampling rate reducers 102a and 102b respectively. The outputs of sampling rate reducers 102a and 102b are now applied to and 102b are now applied to time multiplexing circuit 104. Basically, if the sampling rate is reduced by an appropriate amount, the last three sections of the digital lowpass filter can be time shared since there is so much time available between samples from the high speed section to the low-speed sections. This represents a significant cost and size savings in that three second order digital lowpass filter sections need not be implemented. Since digital lowpass sections 106a-c process lower speed digital information, the clock speed driving then must be appropriately lowered. Therefore, clock 34 is applied to divider 110 to lower (by an amount comparable to sampling rate reducer 102a and 102b) the clock speed so that synchronization can be maintained. The output of filter section 106c is a band-limited digital signal of N bits identical to the signals at 40 and 42 of Figure 1 (although they are time multiplexed) . The output of filter section 106c is applied to time demultiplexing circuit 108 which separates the signals back into their original quadrature paths (although they are now appropriately band-li ited) , and outputs them on output ports 40 and 42 respectively. Thus, by choosing an appropriate decimation rate a significant cost and space savings for implementing the DZISS of the present invention is disclosed. While a particular embodiment of the invention has been described and shown, it should be understood that the invention is not limited thereto since many modifications may be made. It is therefore contemplated to cover by the present application any and all such modifications that may fall within the true spirit and scope of the basic underlying principles disclosed and claimed herein. hat is claimed is:

Claims: Claims 1. A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device, comprising, in combination: clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90° in phase; means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz; and first and second digital filtering means, coupled to said digital quadrature mixing means and to said clock means, for selectively band-limiting the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals. 2. A digital zero-IF selectivity section circuit operating on a first and second input signal in a transmitter device, comprising, in combination: clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete time signal leads said second digitized discrete time signal by 90° in phase; first and second digital filtering means, coupled to the first and second input signals and said clock means, for selectively band-limiting the frequency spectrum of said first and second input signals thereby providing first and second filtered input signal; and means for digital quadrature mixing said first and second filtered input signals and said first and second digitized signals to provide first and second digitized output signals. 3. The circuit of claim 1, wherein said digital oscillator means further comprises: binary addressing means having an input port for receiving a frequency informatin signal and an additional input port coupled to said clock means to provide a binary address signal; binary storage means coupled to said binary addressing means for providing a plurality of stored binary signals; and combining means constructed and arranged to combine said stored binary signals for providing said first and second digitized discrete-time signals. 4. The circuit of claim 1 , wherein said digital quadrature mixing means further comprises: first and second discrete mixing means each coupled to said input signal and a respective one of said first and second digitized discrete-time signals to provide said first and second digitized output signals. 5. The circuit of claim 1, wherein said digital filtering means further comprises: at least two digital filter sections cascaded together for achieving a selective order digital filter and intercoupled by sample rate reducing means for reducing the operating speed of subsequent logic sections. 6. The circuit of claim 3, wherein said first binary storage means comprises a plurality of single bit storage means. 7. The circuit of claim 3, wherein said third, fourth and fifth binary storage means comprise read-only-memory. 8. The circuit of claim 4, wherein said first and second mixing means comprise digital multipliers. 9. The circuit of claim 5, wherein said digital filter sections do not employ digital multipliers. 10. The circuit of claim 5, which further includes: first and second periodic clock signal means wherein said second clock signal has a period approximately equal to at least twice the period of said first clock signal; demultiplexing means, coupled to the input signal for demultiplexing the input signal into at least two demultiplexed signals; first filtering means for filtering said demultiplexed signals providing at least two filtered demultiplexed signals; multiplexing means for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal; and second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal which represents a selectively band-limited portion of said input signal. 11. The circuit of claim 9, wherein said digital filter sections further comprises: first binary summing means coupled to an input signal and a second binary delayed signal for providing a first binary sum signal; first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal; second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal; first binary storage means coupled to said second binary sum signal for providing said first binary delayed signal; third binary summing means coupled to said first binary delayed signal and said second delayed binary signal for providing a third binary sum signal; second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal; fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal; second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal. 12. The circuit of claim 11, wherein said second binary delayed signal comprises the digital filter output signal. 13. The circuit of claim 2, wherein said digital oscillator means further comprises: binary addressing means having an input port for receiving a frequency information signal and an additional input port coupled to said clock means to provide a binary address signal; binary storage means coupled to said binary addressing means for providing a plurality of stored binary-signals; and combining means constructed and arranged to combine said stored binary signals for providing said first and second digitized discrete-time signals. 14. The circuit of claim 2, wherein said digital quadrature mixing means further comprises: first and second discrete mixing means each coupled- respectively to said first and second input signals and a respective one of said first and second digitized discrete-time signals to provide said first and second digitized outpt signals. 15. The circuit of claim 2, wherein said digital filtering means further comprises: at least two digital filter section cascaded together for achieving a selective order digital filter and intercoupled by sampling rate increasing means, to increase the operating speed of subsequent' logic sections. 16. The circuit of claim 13, wherein said first binary storage means comprises a plurality of single bit storage means. 17. The circuit of claim 18, wherein said third, fourth and fifth binary storage means comprise read-only-memory. 18. The circuit of claim 14, wherein said first and second mixing means comprise digital multipliers. 19. The circuit of claim 15, wherein said digital filter sectins do not employ digital multipliers. 20. The circuit of claim 15, which further includes: first and second periodic clock signal means wherein said second clock signal has a period approximately equal to at least twice the period of ;-said first clock signal; ' demultiple ing means, coupled to the input signal for demultiplexing the input signal into at least two demultiplexed signals; first filtering means for filtering said demultiplexed signals providing at least two filtered demultiplexed signals; multiplexing means, for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal; and second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal which represents a selectively band-limited portion of said input signal. 21. The circuit of claim 19, wherein said filter further comprises: first binary summing means coupled to an input signal and a 'second binary delayed signal for providing a first binary sum signal; first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal; second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal; first binary storage means coupled to said second binary sura signal for providing said first binary delayed signal; third binary summing means coupled to said first binary delayed signal and said second shifted binary signal for providing a third binary sum signal; second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal; fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal; second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal. 22. The circuit of claim 21 wherein said second binary delayed signal comprises the digital filter output signal. 23. In a receiver for receiving and periodically presenting a received digital input signal to an intermediate frequency section, the improvement comprising: clock means for providing a periodic clock signal; a digital oscillator means, coupled to clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90° in phase; means for digital quadrature mixing the digital input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero hertz; and first and second digital filtering means, coupled to said digital quadrature mixing means and to said clock means, for selectively band-limiting the frequency spectrum of said first and second digitized output signals providing first and second filtered digitized output signals. 24. In a transmitter which periodically presents a first and second digital input signal to an intermediate frequency section, the improvement comprising: first and second digital filtering means, coupled respectively to the first and second digital input signals, for providing a first and second filtered digital output signal; clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete time signal leads said second digitized discrete time signal by 90° in phase; means for digital quadrature mixing said filtered digital output signals and said first and second digitized output signals for providing first and second output signals such that at least said first and second output signals occupy a -band-limited predetermined frequency range. 25. A digital zero-IF selectivity section for use in a receiver, comprising, in combination: clock means for providing a periodic first clock signal; means for dividing the frequency of said clock signal to provide a second clock signal; second generating means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by .90° in phase; means for digital quadrature mixing the input signal and said first and second digitized signal for providing first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz; first and second digital filtering section means respectively coupled to said first and second digitized output signals and each coupled to said clock means for providing first and second filtered digitized output signals; first and second data sampling reducer means respectively coupled to said first and second filtered digitized output signals for providing first and second reduced rate data signals; multiplexing means coupled to said first and second reduced rate data signals to provide a multiplex output signal; third digital filtering section means coupled to said second clock signal and said multiplex output signal to provide a first filtered multiplex signal; fourth digital filtering section means coupled to said second clock signal and said first filtered multiplex signal to provide a second filtered multiplex. ' signal; fifth digital filtering section means coupled to said second clock signal and said second filtered multiplex signal to provide a third filtered multiplex signal; and demultiplexing means coupled to said second clock signal and said third filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.

Inventors: JASPER STEVEN C, LAMBERT KATHERINE H, LONGLEY LESTER A, JASPER, STEVEN, C., LAMBERT, KATHERINE, H., LONGLEY, LESTER, A.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1986
Main classification: H04B1
IPC codes: H03B27, H03B28, H03C3, H03D1, H03D7, H03H17, H04B1