NETWORK FOR MESSAGE SWITCHING BETWEEN A PLURALITY OF PROCESSING UNITS

Abstract: A network for message switching between h processing units, to each of which a serial transmission channel (256 Kbit/s) is connected, is described herewith. Said network comprises h input interface facilities (B-IN) designed to memorize a plurality of messages and furthermore, also designed to output an access request (ra) onto a common bus (8 Mbit/s) to which there are likewise h output interface facilities (B-OU) connected. When one of the said input interface facilities receives a consent signal (cs) it outputs a message onto the bus which is memorized by the output interface facilities with an indicator that coincides with the one specified in a predetermined byte of said message (fig. 3).

Description: The present invention relates to a network for message switching, in a particularly fast manner, between a plurality of processing units to each of which there is a serial transmission channel connected. Henceforth in the following description the switching network in question will be illustrated with reference to a switched telephone exchange of the digital type, wherein each processing unit is encased in its respective module of the exchange and the messages are constituted by signal messages. However, said network may be advantageously used for switching messages between any type of processing unit complex. Modern digital type telephone exchanges, in other words of the type suitable to switch vocal and/or data signals in the form of PCM signals (Pulse Code Modulation), are so designed as to include the presence of a plurality of input/output modules, to each of which a predetermined number of users and/or a predetermined number of trunk lines can be connected. Each of the said modules comprises a processing unit for analysing the signalling criteria associated to the voice and/or data signals, and also to structure them in the form of messages which shall be switched between the modules. As is a well know fact, in modern digital switched exchanges, switching operations concerning vocal and/or digital signals are carried out by means of a connection network on the basis of the indications contained in the signal messages. The connection network is preferentially constituted by switching modules which in turn also include a processing unit. Switching operations of signal messages can be carried out by using predetermined channels of the connection network, or by means of a switching network that is separate from the connection network. However it must be kept in mind that use of the connection network for switching signal messages involves the introduction of delays in the times necessary for crossing the network which are fundamentally caused by the times required to carry out connection network pre-patterning operations. In some circumstances the crossing times mentioned above are not compatible with the times required for correct operation of the switched exchange. The fact must also be kept in mind that realization of a signal message switching network that is separate from the connection network, makes it possible to avoid the above described inconveniency concerning the transit times of messages, but also involves overcoming certain technical problems such as the following: a) switching messages with a number of words (bytes) that differs from message to message; b) switching messages which are output from the single modules in a non cyclic manner and according to a rhythm (the number of messages in a time unit) which differs from module to module, thus avoiding the danger of losing messages; c) synchronize the output module and the destination module with each other; d) allow a generical message to be sent to a single destination module, as also to a group of modules or to all the modules; e) guarantee scanning of all modules in a predetermined time interval; f) carry out useful functions for diagnosis of the switched message network and of the organs linked up to it. The aim of the present invention is to realize a fast switching network of the signal messages, that is separated from the connection network, and has the aforementioned requisites. Therefore the object of the present invention is a network for message switching between a plurality h of processing units, which includes the presence in combination of the following characteristic elements: - h input interface facilities, each of which is designed to be connected to a channel output from its respective processing unit, to memorize a plurality of messages, to activate a first output after memorizing at least one message, to make an active signal available on a second output for the complete duration of a message excepting during its last byte, to output a message on a third output in reply to receiving an enabling signal; - multiplexing facilities designed to receive the first, second and third output of the said input interface facilities on their input, and to connect the same to their own first, second and third output on the basis of the patterns that the address bits applied to their own monitoring inputs have; - scanning facilities, designed to forward the said address bits to the multiplexing facilities, to stop, or begin scanning operations again, in reply to picking up the enabling of the first output, or alternatively in reply to picking up the disenabling of the second output, of the multiplexing facilities; - decoding facilities, designed to receive the address bits available on the outputs of the scanning facilities on their input, and furthermore, also designed to provide the said input interface facilities with enabling signals; - h output interface facilities, each of which can be connected to an channel entering its respective processing unit, and receive the messages corrisponding to the third output of the multiplexing facilities and also designed to memorize them if the indicator present in a predetermined byte of the message coincides with the indicator assigned to said facilities. Further characteristics of the invention will be made clear by the description given henceforth which refers to a form of embodiment given purely as an example without intending to limit the scope of the invention in any way, and complete with the attached drawings in which: - fig. 1 shows the block diagram of a digital type switched exchange with a message switching network (MDM) made according to the invention; - fig. 2 shows the structure of a signal message; - fig. 3 shows the block diagram of the message switching network MDM in fig. 1; - fig. 4 illustrates one of the input interface facilities B-IN shown in fig. 3, in detail; - fig. 5 illustrates one of the output interface facilities B-OU shown in fig. 3, in detail; - fig. 6 illustrates the CO unit shown in fig. 3, in detail. In fig. 1 the block diagram of a digital type switched telephone exchange which uses the message switching network MDM for switching signal messages is illustrated. The voice and/or data signals are on the other hand switched by a connection network RC which, in a preferred form of embodiment, is of the type comprising n levels of switching, wherein each level is constituted by its respective switching module MC₁, ..., MC n . The MDM network realized according to the present invention is ideal for switching the messages which are input into it by means of h 256 Kbit/s serial transmission channels, onto the same number of output channels. Still observing fig. 1 it can be noticed that n of the h channels of the MDM unit are connected to the same number of switching modules MC of the connection network RC, one channel is used by a supervisor module embodied in the MDM unit itself (see fig. 3), and the remaining (h - n) -1 channels are connected to the same number of input, output modules MI, MU of the switched exchange. In particular, the input modules MI send the voice (and/or data) signals, that is to say the signal messages, to the output modules MU, by means of the connection network RC, or by means of the message switching network MDM. Therefore, the MI modules can pre-process the signalling criteria concerning the users (and/or junction lines) connected to them and organize it in message form, and said messages will then be output onto their respective serial transmission channel, which in a preferred form of embodiment has a speed of 256 Kbit/s. Transmission and receive operations concerning the messages both by the input-output modules and the switching modules, are all clocked by the MDM unit which forwards a clock signal CK to each module by means of its own respective wire. It must be kept in mind that, for reasons of clarity and simplicity, the MI modules have been drawn separate from the MU modules in the figs: in actual fact there is always both an MI module and its corrisponding MU module positioned on the same plate so a single wire provides the clock signal both for the input module and its corrisponding output module. The format of the messages that are received by the MDM unit is illustrated in fig. 2. It must be borne in mind that as long as there is no request to transmit the messages a flag (signal word) with a predetermined pattern is sent onto the above mentioned channel. The first byte of the message is the destination point DP indicator, followed by further information such as the priority code PR, and the length indicator LI, the user field UF and the CRC code which constitutes the cyclic redundancy code through which any errors introduced by the transmission medium can be picked up. On the basis of the indicator specified in the DP field, the MDM unit forwards each message onto the respective 256 Kbits/s transmission channel connected to the module (MU or MC or MS) that constitutes the message's destination. Fig. 3 illustrates the block diagram of the MDM unit shown in fig. 1 and which includes the presence of h input interface facilities B-IN₁, ..., B-IN h , connected to their respective 256 Kbit/s serial transmission channels. In particular, the channels output from the respective switching modules MC₁, ..., MC n are connected to the facilities B-IN₁, ..., B-IN n , the supervision facilities MS are connected to the B-IN h facilities, and the input modules MI (h-n)-1 are connected to the remaining facilities B-IN (h-n)-1 Each of the said B-IN modules has been designed to: - memorize a plurality of messages; - activate an output ra when at least one message is present in its internal memory, thus outputting an access request to a common bus; - output a message when it receives a consent signal cs at a speed V less than K . h (where said parameters assume for example the following values: K = 256, h = 128, V = 8 Mbit/s); - output an active signal on an output ms for the whole of the duration of the outputting of the message on the 8 Mbit/s transmission channel, excepting only during the last byte of the message when said signal shall be disactivated. The outputs of each B-IN unit are sent onto the respective inputs of a multiplexer MX₁ the output of which corrisponds therefore to an 8 Mbit/s bus, an access request bus ra and a message in course bus ms . The latter two buses reach a scanning circuit SC the function of which is to cyclically scan all the B-IN units - modifying in a sequential manner the addresses applied onto the monitoring input of MX₁ - and to stop the scanning whenever it reveals the presence of an access request on the ra bus. The addresses available on the output of the SC unit are also input into a decoding circuit DC, the h outputs of which corrispond to the consent signals cs for determining the outputting of a message by the B-IN unit in question during that phase of the scanning operations. When the signal on the ms bus is disactivated (last byte of the message), a one step increase is registered in the SC unit, which in this manner begins scanning of the B-IN units once again. There are h output interface facilities B-OU₁, ..., B-OU h connected to the 8 Mbit/s bus which have suitable facilities for analysing the DP field of the messages which are input to them and which are likewise designed to enable memorization of the same if the DP field coincides with the indicator associated to each B-OU unit. Similarly, to the B-IN facilities, the B-OU₁, ..., B-OU n facilities are connected to the MC₁, ..., MC n modules. The B-OU h facilities are connected to the supervision facilities MS, whilst the remaining B-OU (h-n)-1 facilities are connected to the output modules MU. From the aforegoing description the manner in which the said switching operations are carried out can easily be deduced. In fact a message coming from any single B-IN unit can be forwarded to any buffer B-OU after transiting on the 8 Mbit/s bus. Said messages are then sent, by means of a 256 Kbit/s channel, to the output module to which they are directed, or alternatively to the connection network RC, or to the supervisor facilities MS. The supervisor facilities MS comprise a monitoring unit CO and a control circuit CC. The CO unit is for receiving signals from each of the input interface facilities B-IN, from the scanner SC, and from a unit C-CRC - designed to monitor the cyclic redundancy code CRC - that indicate their condition, and is also for memorizing the state that said units should have in the absence of abnormal operating conditions, and will also compare the signals received with those memorized. If any lack of identity is found, the CO unit generates an interrupt request directed to the control circuit CC, implemented for example with a microprocessor of a commercial type; in reply to this event, the latter unit sets off a procedure for pointing out the unit to which the abnormal condition refers and for starting consequent actions such as for example determining the forwarding, by means of the CO unit, of predetermined signals to the B-OU units, as will be made more clear henceforth with reference to fig. 5. The CC unit uses the couple of interface units B-IN h and B-OU h connected to it for switching messages with any input-output module MI-MU or alternatively with any switching module MC. This switching of messages is necessary for example to carry out program loading operations in the processing units in the above mentioned modules, in order to carry out cyclic monitoring, etc. The monitoring circuit of the cyclic redundancy code C-CRC is connected to the 8 mbit/s bus as well as to the ms bus and its function is to analyse the CRC field of the messages (see fig. 3) which transit along the 8 Mbit/s bus in order to pick up the presence of any errors introduced during the switching operations. In the presence of an error the C-CRC unit activates its own output and said activation is picked up by the CO unit of the supervisor facilities which, on the basis of the address available on the output of the scanner SC, picks up the indicator of the B-IN unit to which the abnormality causing the error picked up is to be attributed. The MDM unit also includes the presence of timing facilities UT designed to supply a clock signal CK both to the modules and to its own inner organs (CO, SC, etc.), which permits synchronization of the switching operations of the signal messages. One of the input interface facilities B-IN is illustrated in detail in fig. 4: these include the presence of a first recognition circuit CR₁ of predetermined binary patterns transiting on the relevant 256 Kbit/s serial channel. In particular they include the presence of facilities for recognizing the pattern of a loop control lo , the pattern indicating idle state id on the transmission medium, and for making the said signal ms available. The 256 Kbit/s channel is also input into a serial-to-parallel converter SP₁ the outputs of which are forwarded to the same number of inputs of a buffer memory MB₁ designed to memorize a predetermined number of messages. The outputs of the MB₁ unit are input to a parallel-to-serial converter PS₁ the output of which is corrisponded by an 8 Mbit/s transmission channel. The writing and reading addresses of the MB₁ unit are respectively supplied to a write counter CS₁ and a read counter CL₁ by mùeans of a multiplexer MX₂. Said operations are in fact carried out in time division at the rhythm (eg. 500 n.secs.) defined by a signal r/w₁ supplied by timing circuits (not illustrated). The B-IN unit also includes the presence of a message counter CM and a first comparison circuit CF₁ designed to output an overflow alarm signal ov₁ when the number of messages memorized in the MB₁ unit is such as to exceed a predetermined fraction of the total memorizing capacity. When the ms signal (indicating the presence of a message in the 256 Kbit/s channel) is found on the output of the recognition circuit CR₁, the counter SC₁ is enabled to start counting; this latter unit receives a signal CK′ on its count input which has a frequency that is eight times less than that of the 256 Kbit/s serial channel, thus determining the counting of the bytes of the message and therefore enabling memorizing operations in the MB₁ unit. When the ms signal assumes logical value zero (last byte of the message) a one step increase is registered in the message counter CM, which activates its own ra output, thus showing in this manner that there is at least one message ready to be transmitted present in the MB₁. When the scanning facilities SC (fig. 3) pick up the said access request and output the said consent signal cs , the CL₁ unit is enabled for counting, and a clock signal CK″ that has a frequency eight times lower than the speed of the data being output from the PS₁ unit is input into the said CL₁ unit. The cs signal is also forwarded onto the counting input at the back of the message counter CM which, after reading of one message, decreases its own contents by one step. In order to avoid the scanner remaining associated to a generical B-IN unit in whose MB₁ unit there are for example a large number of messages memorized, with the consequent stopping of scanning operations for a noticeable time interval, the B-IN units are designed to output only one message at a time. This makes it possible to guarantee scanning of all the B-IN units in a predetermined time interval, but can give rise to a possible state of accumulation of messages (overflow). For this purpose the presence of the said CF₁ unit has been included, which is designed in such a manner as to activate the output ov₁ when the content of the CS₁ unit differs from the content of the CL₁ by a predetermined entity. Activation of the id and/or ov₁ signals is therefore an indication of the existence of an abnormal state either on the transmission medium or in the MB₁ memory respectively; said signals are forwarded to the monitoring unit CO (see fig. 3) by means of the said wire in . Fig. 5 shows one of the output interface facilities B-OU in fig. 3 in detail. This unit includes the presence of a multiplexer MX₃, to one input of which the aforementioned 8 Mbit/s bus is connected, whilst on its other input there is the 8 Mbit/s transmission channel which - in a concrete form of embodiment - corrisponds to the output of the B-IN unit associated to the B-OU unit in question. The MX₃ unit receives the bit lo on its monitoring input; said bit is available on the output of the MB₁ memory (see fig. 4), and if active, connects the output of the 8 Mbit/s transmission channel to MX₃, thus determining a loop connection of a B-OU unit and a B-IN unit. If the lo bit is not active, the MX₃ unit determines transiting of the messages present on the 8 Mbit/s bus and these are examined by a plurality of recognition circuits CR₂, CR₃, and CR₄. In particular, the CR₂ unit is designed in such a manner as to activate its own output if the DP field of the message which corrisponds to the output of MX₃ coincides with an address wired on the CR₂ unit itself. On the other hand, the CR₃ and CR₄ circuits' function is to permit forwarding of the same message - for example for maintenance purposes - to all the B-OU units or to a predetermined group of the B-OU units respectively. For this purpose the CR₄ circuit receives the indicator of the message destined to be sent to a predetermined group of modules from the monitoring circuit CO by means of said wire ou , and if the indicator coincides with the one specified in the message's DP field, excitation of the relevant output is registered. On the other hand, forwarding of a message to all the modules is carried out by wiring a predetermined address on all the CR₃ units and sending a message along the 8 Mbit/s bus wherein the DP field coincides with the aforementioned address. A logical sum circuit OR₁ is connected to the outputs of the CR₂, CR₃ and CR₄ units, which activates its own output if in at least one of the units described above, comparison operations have given positive results. When this latter condition happens, enabling of a buffer memory MB₂ is registered, which receives on its data input, the output of a serial-to-parallel convertor SP₂ which is connected to the output of MX₃, and on its address input the outputs of a multiplexer MX₄. The outputs of a write counter CS₂ and a read counter CL₂ are input into this latter multiplexer and it is monitored by a signal r/w₂ which determines the alternance of write and read operations according to a predetermined cycle (eg. 500 n.secs). The CS₂ unit is enabled by the ms signal and receives the said clock signal CK″ on its count input, whilst the CL₂ unit is enabled by a signal al supplied by a microprogrammed unit MM. This latter unit is monitored by the signal ms ′, available on the output of the MB₂ unit, which enables reading operations for the whole duration of a message and is also monitored by the CO unit in fig. 3 ( ou wire). Similarly there is a second comparison circuit CF₂ associated to the CS₂ and CL₂ units which activates a first output ov₂ or alternatively a second output tf , when the contents of the CS₂ unit differ by a predetermined entity from the contents of the CL₂ unit (overflow state), or alternatively when a state of coincidence is registered; this latter state indicates the fact that all the messages present in the CL₂ unit have been transmitted. In consideration of the fact that the protocol which regulates the sending of messages being output from the B-OU units requires the outputting of a predetermined number of flags between two consecutive messages, in reply to picking up the flag transmission signal tf being output from CF₂ the MM memory synchronizes a signal generator GS and modifies the monitoring signal of a multiplexer MX₅. This latter unit receives the output of the PS₂ unit on one of its inputs, and on a second and third input, typical patterns of said flag signal fl and typical patterns of said id signal (idle), respectively. Therefore sending of the fl signal by the GS unit is synchronized by the MM unit by means of outputting a flag start signal sf . In particular the MM unit is piloted by the said CF₂ unit (and consequently the said buffer memory MB₂) under normal operating conditions, or by the said CO unit under particular operating conditions. Fig. 6 illustrates in detail the CO unit shown in fig. 3 to which the bus of the monitoring circuit CC, an input wire in and an output wire ou are connected. It must be borne in mind that in fig. 3 the B-IN units have been shown as being separate from the B-OU units for reasons of simplicity; in actual fact, in practical embodiment, there is a B-IN unit and a corrisponding B-OU unit mounted on the same plate, and consequently, the signals (eg. id , ov₁, ov₂, etc.) which are to be sent to the CO unit are all conveyed onto the in wire, whilst the signals output from the CO unit are conveyed onto the ou wire. In detail, each of the h B units has access to the in wire on a time division basis and transfers a digital word wherein each bit expresses the logical level that the signals described above have in the instant being considered. The CO unit includes the presence in combination of the following characteristic elements: - a network present state memory MSA, comprising h memory zones, which memorizes the state of each single unit of the network in the instant under consideration; - a network at rest state memory MSR, comprising h memory zones, which memorizes the state that the single units of the network must have in the absence of abnormal operating conditions; - an interrupt masking memory MMI, comprising h memory zones, the function of which is to determine masking of the interrupt requests after they have been picked up by the CC unit; - a network instructions memory MCR, comprising h memory zones, for receiving the instructions to be sent to the single units of the network by means of the ou wire; - a multiplexer MX₆ which outputs a binary pattern for addressing the memories described above; - a multiplexer MX₇ which has its output connected to the input of the present state memory MSA; - a counter CN the outputs of which are connected to an input of the MX₆ multiplexer; - an address register RI the inputs of which are connected to the bus of the CC unit and the outputs of which are connected to the other input of the MX₆ multiplexer; - an instruction register RC, with its input connected to the bus of the CC unit, for receiving and decoding the instructions output by the CC unit and destined to the said memories as well as to the said MX₆ and MX₇ multiplexers; - writing facilities (schematically illustrated by registers RS₁, RS₂, RS₃ and RS₄) which have their inputs connected to the bus of the CC unit and their outputs connected respectively to the inputs of the MX₇ multiplexer, of the network at rest state memory, of the interrupt masking memory, of the network instructions memory; - reading facilities (schematically illustrated by registers Rl₁, R₂, RL₃ and RL₄), which have their outputs connected to the bus of the CC unit and likewise their inputs connected respectively to the output of the network present state memory, the output of the network at rest state memory, the output of the interrupt masking memory, the output of the network instructions memory; - and exclusive OR circuit EX to receive on its input the in wire as well as the output of the network at rest state memory; - a logical product circuit AND, to receive on its input the output of the EX circuit as well as the output of the interrupt masking memory; - an interrupt generator GRI connected to the output of the AND unit. Operation of the circuital structure mentioned above can be described as follows: a) digital words expressing the state of the single units of the switched network in the instant being considered, reach the MSA memory by means of the MX₇ multiplexer. Said words are written in the h memory zones, at the address specified by the binary pattern corrisponding to the output of the CN unit: said addresses are scanned in a sequential manner and scannings follow one another with a predetermined cyclicity of duration; b) said digital words are also compared, by means of the EX unit, with the contents of the MSR unit which defines the pattern that the said words should have in the absence of abnormal operating conditions; c) if the EX unit picks up a lack of identity, it activates its own output thus determining the sending of an interrupt request by the GRI unit; d) after the CC unit has picked up said request, it determines masking of it - by means of the MMI unit which disenables the AND unit each time the EX unit represents the abnormal condition that has determined the sending of the interrupt request as described above - and starts a reading operation by the MSA unit in order to pick out the unit to which the abnormal state refers; e) after a reading operation by the MSA unit and/or other events - such as for example the intervention of an operator - the CC unit sends predetermined instructions to the units of the message switching network by means of the MCR memory and the ou wire (eg.: indicators of the fact that the message is to be sent to a predetermined number of modules, as previously specified with reference to the CR₄ unit in fig. 5). For maintenance purposes the CC unit has the possibility of writing control words in the MSA, MSR, MMI and MCR memories and - after having read the same - of gathering useful information regards their operation. In order to carry out said operation, the CC unit carries out the following operations: - it supplies the RI register with the address of the memory location where a data write operation is to be carried out; - it supplies the instruction register RC with a digital word structured in such a manner that the multiplexers MX₆ and MX₇ output the contents of the RI register and of the RS₁ register respectively; - it supplies the registers RS₁, ..., RS₄ with digital words to write in their respective memories, which receive a write instruction from the RC register; - after the writing cycle has been completed, it starts off the reading cycle by forwarding the address of the memory cells being used in the operation to the RI register, by forwarding a read instruction to the RC register and by gathering the digital words from the RL₁, ..., RL₄ registers emptied into them by their respective memories. The network according to the invention satisfies the requisites announced at the beginning of this text in as much as it can: a) switch messages with a number of bytes that may differ from message to message thanks to the use of said message present signal ms ; b) avoid the danger of there being a loss of messages thanks to the presence of the CF₁ and CF₂ units which pick up the existence of overflow states thus allowing, in this manner, the supervisor facilities to activate predetermined functions (eg. in the presence of the ov₁ state the supervisor facilities inhibit the sending of further messages by the module connected to the B-IN unit to which the ov₁ refers). On the other hand, in the presence of an ov₂ state the supervisor facilities inhibit advancement of the scanner SC for a predetermined time interval, thus preventing other B-IN units from sending messages to the B-OU unit - to which the ov₂ refers - and consequently allowing elimination of the messages accumulated in the MB₂ unit; c) synchronize the outputting module and the destination (receiving) module with one another thanks to the presence of the said UT unit which sends the CK clock to the MI-MU, MC, MS modules; d) permit the sending of a message to a single destination module as also to a group of modules thanks to the presence of said recognition circuits CR₂, CR₃ and CR₄; e) guarantee scanning of all the modules in a predetermined time interval thanks to the fact that the input interface facilities B-IN send a single message at a time to the output interface facilities B-OU. Thanks to the characteristic in question it is possible to guarantee a more or less constant MDM unit crossing time by the messages that reach the B-IN unit; f) carry out useful functions for diagnosis of the message switching network and connected organs, thanks to the presence of the recognition circuit CR₁ (which makes the idle signal id and the loop signal lo available), of the multiplexer MX₃ (it allows carrying out of a loop operation) and of the supervisor facilities MS and C-CRC (they permit verification of the state of all the B-IN units).

Claims: 1) Network for switching messages between a plurality h of processing units, characterized in that it includes the presence in combination of the following characteristic elements: - h input interface facilities (B-IN₁, B-IN₂, ..., B-INH) each of which is designed to be connected to a (256 Kbit/s) channel output from its respective processing unit (MI-MU, MC, MS), to memorize a predetermined number of messages, to activate a first output (ra) after memorizing at least one message, to make an active signal (ms) available on a second output for the complete duration of a message, excepting during its last byte, to output a message on a third output in reply to receiving an enabling signal (cs); - multiplexing facilities (MX₁) designed to receive the first, second and third output of the said input interface facilities (B-IN) on their input, and to connect the same to their own first, second and third output on the basis of the patterns that the address bits applied to their own monitoring inputs have; - scanning facilities (SC), designed to forward the said address bits to the multiplexing facilities (MX₁), to stop, or begin scanning operations again, in reply to picking up the enabling of the first output (ra), or alternatively in reply to picking up the disenabling of the second output (ms), of the multiplexing facilities (MX₁); - decoding facilities (DC), designed to receive the address bits available on the outputs of the scanning facilities (SC) on their input, and furthermore, also designed to provide the said input interface facilities with enabling signals (cs); - h output interface facilities (B-OU₁, ..., B-OU₂, ..., B-OUh), each of which can be connected to a (256 Kbit/s) channel entering its respective processing unit (MI-MU, MC, MS), and receive the messages corrisponding to the third output of the multiplexing facilities (MX₁) and also designed to memorize them if the indicator present in a predetermined byte of the message coincides with the indicator assigned to said facilities. 2) Network as described in claim 1 in which the said processing units are part of a digital type telephone exchange comprising a connection network structured on n levels for switching vocal and/or data signals, characterized in that n of the said h units constitute the processors associated to n switching modules whilst the remaining h - n units constitute the processors encased in the h - n input-output modules of the switched exchange. 3) Network as described in claims 1 and 2 characterized in that one of the said h - n processing units constitutes the processor (CC) of supervisor facilities (MS) which also comprise a monitoring circuit (CO) designed to receive (in) signals indicating the state of the single network units, to compare said signals with reference signals, to output an interrupt request towrds the relevant processing unit (CC), to activate predetermined functions in the output interface facilities (B-OU). 4) Network as described in claims 1, 2 and 3, characterized in that each of the said h input interface facilities (B-IN) include the presence in combination of the following characteristic elements: - a first recognition circuit (CR₁), connected to said channel (256 Kbit/s), designed to make said active signal (ms) available on a first output for the whole duration of a message excepting only the last byte, a signal (id) available on a second output in reply to recognition of the idle state of the transmission channel, a signal (lo) available on a third output in reply to recognition of a loop instruction situated in a predetermined byte of the message; - a first serial-to-parallel convertor (SP₁) connected to said transmission channel; - a first buffer memory (MB₁) connected to the outputs of the serial-to-parallel convertor and to the first and third outputs (ms, lo) of said first recognition circuit (CR₁); - a first write counter (CS₁) enabled by the signal (ms) available on the first output of the recognition circuit and made to advance by a clock signal CK′ with a frequency k times less than the transmission speed of messages that reach the first serial-to-parallel convertor, k being the number of bits forseen in each byte of the message; - a message counter (CM) of the front/back type, designed to increase its own contents by one step ahead in reply to picking up each signal (ms) available on the first output of the first recognition circuit, and also designed to decrease its own content by one step in reply to receiving the said enabling signal (cs) supplied by the scanning facilities (SC) and further designed to activate one of its own outputs (ra) if its own content is other than zero; - a first read counter (CL₁) which is made to advance by a clock signal CK″ when the said enabling signal (cs) is active, where CK″ has a frequency K times less than the speed of the messages that transit on said first output (8 Mbit/s) of the multiplexing facilities (MX₁); - a second multiplexer (MX₂), designed to send the outputs of the said first write counter (CS₁ or the outputs of the said first read counter (CL₁), according to the logical level of a signal (r/w₁) applied to a monitoring input of its own to the said first buffer memory (MB₁); - a first comparison circuit (CF₁) designed to activate one of its own outputs (ov₁) when the contents of the first write counter (CS₁) differ from the contents of the first read counter (CL₁) by a predetermined entity; - a first parallel-to-serial convertor (PS₁) connected by its output to the first buffer memory (MB₁). 5) Network as described in claims 1, 2 and 3, characterized in that each of the said h output interface facilities (B-OU) include the presence in combination of the following characteristic elements: - a second serial-to-parallel convertor (SP ) designed to receive on its inputs the messages available on the third output (8 Mbit/s) of the multiplexing facilities (MX₁); - a second, a third and a fourth recognition circuit (CR₂, CR₃ and CR₄) designed to activate their own output if they pick up a coincidence between an indicator associated/sent to them and an indicator (DP) specified in a predetermined byte of the messages input to them; - a logical sum circuit (OR₁) connected to the output of the second, third and fourth recognition circuit (CR₂, CR₃ and CR₄); - a second write counter (CS₂) enabled by the said signal (ms) available on the second output of the multiplexing facilities and made to advance by the said clock signal CK″; - a second buffer memory (MB₂) designed to memorize the bits available on the outputs of the second serial-to-parallel convertor (SP₂) as well as said signal (ms), at the addresses supplied by said second write counter, when the output of said logical sum circuit (OR₁) is active; - a second parallel-to-serial convertor (PS₂) designed to receive the outputs of said second buffer memory (MB₂) on its inputs; - a second read counter (CL₂) enabled by a signal (al) supplied by a microprogrammed memory (MM) and made to advance by said clock signal CK′; - a third multiplexer (MX₄) designed to send the outputs of the second write counter (CS₂) or of the second read counter (CL₂) according to the logical level of a signal (r/w₂) applied to its own monitoring input, to the said second buffer memory (MB₂); - a second comparison circuit (CF₂ to activate a first output (ov₂) or alternatively a second output (tf) when the contents of the second write counter (CS₂), or of the second read counter (CL₂), differs by a predetermined entity, or alternatively coincides; - a microprogrammed memory (MM) designed to have input into it the second output (tf) of the second comparison circuit (CF₂), predetermined instructions (id, fl) of the supervisor facilities (MS), as well as an output (ms′) of said second buffer memory (MB₂), and furthermore, designed to also make available on its outputs the enabling signal (al) of the second read counter, monitoring signals for a fourth multiplexer (MX₅) as well as a flag start signal (sf) to synchronize a signal generator (GS); - a signal generator (GS) designed to make available on a first output (f1) synchronized by said flag start signal (sf), or on a second output (id), binary patterns that coincide with said flag signal, or alternatively with said idle signals; - a fourth multiplexer (MX₅) designed to have the output of the second parallel-to-serial convertor (PS₂) input into it, as well as the first and second outputs of said signal generator (GS), and likewise designed to have the outputs of said microprogrammed memory (MM) input to its monitoring input. 6) Network as described in claim 3 characterized in that said monitoring circuit (CO) includes the presence in combination of the following characteristic elements: - a network present state memory (MSA), comprising h memory zones, which memorizes the state of each single unit of the network in the instant under consideration; - a network at rest state memory (MSR), comprising h memory zones, which memorizes the state that the single units of the network must have in the absence of abnormal operating conditions; - an interrupt masking memory (MMI), comprising h memory zones, the function of which is to determine masking of the interrupt requests after they have been picked up by the relevant processing unit (CC); - a network instructions memory (MCR), comprising h memory zones, for receiving the instructions to be sent to the single units of the network by means of the output wire (ou) of the supervisor facilities (MS); - a fifth multiplexer (MX₆) which outputs a binary pattern for addressing the memories described above; - a sixth multiplexer MX₇ which has its output connected to the input of the present state memory (MSA); - a counter (CN) the outputs of which are connected to an input of the fifth multiplexer (MX₆); - an address register (RI) the inputs of which are connected to the bus of the relevant processing unit (CC) and the outputs of which are connected to the inputs of the fifth multiplexer (MX₆); - an instruction register (RC), for receiving and decoding the instructions output by the relevant processing unit (CC) and destined to the said memories (MSA, MSR, MMI, MCR) as well as to the said fifth and sixth multiplexers (MX₆ and MX₇); - writing facilities (RS₁, RS₂, RS₃ and RS₄) which have their inputs connected to the bus of the relevant processing unit (CC) and their outputs connected respectively to the inputs of the sixth multiplexer (MX₇), of the network at rest state memory (MSR), of the interrupt masking memory (MMI), of the network instructions memory (MCR); - reading facilities (RL₁, R₂, RL₃ and RL₄), which have their outputs connected to the bus of the relevant processing unit (CC) and likewise their inputs connected respectively to the output of the network present state memory (MSA), the output of the network at rest state memory (MSR), the output of the interrupt masking memory (MMI), the output of the network instructions memory (MCR); - an exclusive OR circuit (EX) to receive on its input (in) said signals indicating the state of the single units of the network as well as the output of the network at rest state memory (MSR); - a logical product circuit (AND), designed to receive on its input the output of the exclusive OR circuit (EX) as well as the output of the interrupt masking memory; - an interrupt generator (GRI) connected to the output of the unit (AND). 7) Network as described in claim 5 characterized in that the said output interface facilities (B-OU) include the presence of a seventh multiplexer (MX₃) designed to send the messages available on the third output (8 Mbit/s bus) of the multiplexing facilities or alternatively the messages available on the output (8 Mbit/s) of an input interface unit (B-IN) associated to said output interface unit, to the second serial-to-parallel converter, according to the logical level of a bit (lo) available on the output of the first buffer memory (MB₁). 8) Network as described in claim 1 characterized in that it includes the presence of timing facilities (UT) which can supply a clock signal both to the said modules (MI-MU, MC, MS) and to single units of the network (MDM). 9) Network as described in the aforegoing claims characterized in that the messages described above have a field in which a code for revealing errors has been inserted, also characterized in that it includes a error revealing circuit (C-CRC) which has its input connected to the first and second output of the multiplexing facilities (MX₁) and likewise has its output connected to the input wire (in) of the supervisor facilities (MS). 10) Network as illustrated in the aforegoing description and in the attached drawings as also any isolated or combined parts of the same.

Inventors: POLI, ROBERTO
Applicants: ITALTEL SOCIETA ITALIANA  TELECOMUNICAZIONI S.P.A.
Application year: 1986
Main classification: H04Q11
IPC codes: G06F15, H04Q11