PROCESS FOR FORMING SIDEWALLS

Abstract: A process for forming sidewalls for use in the fabrication of semiconductor structures, where the thin, vertical sidewalls are "image transferred" to define sub-micron lateral dimensions. First, a patterned resist profile (13A, 13B) with substantially vertical edges is formed on a substrate (11, 12) on which the sidewalls are to be created. Then, the profile is soaked in a reactive organometallic silylation agent to silylate the top and the vertical edges of the resist to a predetermined depth, thereby rendering the profile surfaces (15S, 15T) highly oxygen etch resistant. In a subsequent anisotropic RIE process, the top (15T) of the profile and the unsilylated resist are removed, leaving the silylated vertical edges (15S), that provide the desired free-standing sidewalls, essen­ tially unaffected.

Description: The invention relates to a process for forming sidewalls for use in the fabrication of structures with sub-micron lateral dimensions and to the implementation of this process to produce very narrow line width structures. The invention is particularly useful in the fabrication of semiconductor devices, including those used in opto-electronic technologies. There has been a dramatic increase in the use of integrated circuits (IC) over the last decade which resulted in an increasing demand for greater complexity, higher operating speeds, and smaller device dimensions in the ICs. A number of methods are known to increase the integration density of integrated circuits. Considerable improvements have been achieved mainly by decreasing photolithographic defect densities. By using electron and X-ray exposure methods instead of the hitherto used light radiation, a progress was made in the direction of a higher resolution. There were furthermore efforts to reach very narrow line widths in the 1 µm range and less by extending conventional lithographic processes, avoiding the cost-intensive techniques of electron and X-ray lithography. With the technique of plasma or reactive ion etching for etching metals, semi-conductive and dielectric materials, further developments took place in the direction of very narrow line widths, and consequently toward improved device performance. A number of publications and patents describe the so-called sidewall technology by means of which structures in the sub-micron range can be made. In US Pat. No. 4,256,514, a method for forming a narrow dimensioned region on a silicon body is described that involves forming , on the silicon body, regions having horizontal surfaces and substantially vertical surfaces. A thin conformal layer is formed both on the horizontal and substantially vertical surfaces. Reactive ion etching is applied to the layer to remove the horizontal layer while leaving the vertical layer substantially intact. These vertical sidewalls define very narrow dimensioned regions on the silicon body. A further development is disclosed in US Pat. No. 4,502,914. Here, structures of a polymeric layer with horizontal and substantially vertical surfaces are first made on a substrate. Thereupon, a conformal silicon nitride or oxide layer is plasma deposited and subjected to reactive ion etching methods such that its horizontal regions and the polymeric structures are removed, with merely the narrow regions of the silicon nitride or oxide layer that had originally been arranged adjacent the vertical surfaces of the polymeric structures remaining. The vertical sidewall structures are then converted into a mask with the same dimensions but consisting of a different mask material. The basic concept of using a sidewall stud of sub-micron width as a mask for processing underlying layers, i.e., the "image transfer" concept, has also been applied in a process described in the IBM Technical Disclosure Bulletin article "Method for Making Sub-Micron Dimensions in Structures Using Sidewall Image Transfer Techniques" (Vol. 26, No. 9, February 1984, pp. 4587-4589). This process involves the deposition of a conformal Si₃N₄ layer over a resist pattern and subsequent reactive ion etching which leaves a Si₃N₄ sidewall of a very well controlled width at the vertical resist edges. Removal of the resist results in the self-standing studs which can be used to, e.g., define a FET gate of sub-micron gate length. Another sidewall technique that can be employed to produce sub-micron features is described in IBM Technical Disclosure Bulletin article "Precision-Sub-Micron-Dimensioned Mask for X-Ray Lithography" (Vol. 24, No. 7B, December 1984, pp. 4115-4117). Here, the oxide that grows on the vertical walls of patterned polysilicon films is used as a mask. In contrast to these known processes, where the sidewalls are formed on the vertical surfaces of a profile, the sidewalls formed with the process disclosed by the present invention and which eventually determine the sub-micron dimensions, are produced within the vertical surfaces of a polymeric resist profile. The sidewalls are produced in a silylation process which makes the exposed polymeric material of the profile substantially more etch resistant. The sidewall thickness is determined by the parameters of the silylation process. The rather complex hitherto known technique of forming thermally stable pattern and subsequently depositing the conformal layer, from which the sidewalls are obtained, is eliminated. Silylation is defined as the replacement of an active hydrogen of a protic material (-OH, -NH, -SH) with a substituted silicon atom. The silylation of organic compounds is a technique that has been known since about forty years but has only more recently been used to alter the development rate of resist and to improve the reactive ion etch (RIE) resistance in O₂ plasma by the incorporation of silicon. Silylation processes as well as the polymeric materials and silylation agents that can be used have been described in quite a number of references, some that are representative of the art with regard to the application of silylation techniques in IC fabrication, are given below. US Pat. Appl. Ser. No. 679,527 describes a method for producing multi-layer plasma-developable resists which are capable of providing sub-micron resolution. The upper portion of a layer of polymeric material that had been exposed to patterned radiation is converted into a dry etch resistant form using a silylation process. Polymeric materials that can be employed, are defined. US Patent No. 4,552,833 relates to a process for producing a negative tone resist image. The image is produced by the successive steps of: first, exposing a film to a pattern of radiation, the film having such a composition that, after exposure to the radiation, it contains a polymer, which reacts with an organometallic reagent; then, treating the exposed film with the organometallic reagent; and, finally, developing a relief image by further treating the exposed film with an oxygen plasma. Preferred polymers and organometallic reagents are given. In US Pat. Appl. Ser. No. 713,370, a method for creating multilayer patterned films is disclosed wherein at least one layer is etch resistant. This layer is obtained by silylating a patterned polymeric film in an organometallic reagent. The pattern is subsequently transferred using an oxygen plasma or equivalent dry-etch method. US Pat. Appl. Ser. No. 713,509 describes a process for obtaining plasma resistant polymeric materials as well as their use in lithography. The materials are prepared by reacting a polymeric material with an organometallic silylation agent such as hexamethylcyclotrisilazane (HMTCS). The above cited references are representative of the present use of silylation techniques in the fabrication of integrated circuits. These known processes are used to form etch resistant silylated resist layers but do not suggest any application in the formation of sidewalls as proposed in the present invention. It is the main object of the invention to extend the use of conventional lithographic techniques to dimensions in the sub-micron range by utilizing silylation techniques to produce etch resistant profile surfaces and by subsequently utilizing an anisotropic etch process to produce sub-micron sidewalls. The invention as claimed is intended to meet the above objective. This is achieved by using a process that comprises the steps of depositing, on a substrate, a patterned layer of polymeric resist comprising active hydrogen (-OH, -NH, -SH), the resist forming a profile with substantially vertical edges where the sidewalls are to be formed, treating the resist with a reactive organometallic silylation agent to substitute active hydrogen with silicon atoms, i.e., to silylate the top and the substantially vertical edges of the profile to a predetermined depth thereby rendering the profile surfaces highly oxygen dry etch resistant, and anisotropic oxygen dry etching to remove the silylated resist at the top of the profile and, thereafter, the unsilylated resist, leaving the silylated substantially vertical edges of the profile, that form the desired sidewalls, essentially unaffected. The advantages offered by the inventive process are mainly that it requires fewer and less critical process steps: standard resists can be used to form the patterned profile since only low temperature (below 100 °C) process steps are employed, and the complex high temperature and time-consuming CVD deposition process, hitherto required for the deposition of the conformal layer, is replaced by the very simple, uncritical silylation process that can take place at room temperature. Providing the same resolution and reproducibility as obtainable with the best known processes, the new process permits substantial reduction in process complexity, tooling needs and processing time thus resulting in substantial cost saving. One way of carrying out and applying the invention is described in detail below with reference to drawings which illustrate one specific embodiment and in which FIG. 1 is a cross-sectional representation of a sub-micron line width structure produced in accordance with the invention, FIG. 2A-2G are illustrations of the steps of the process used to fabricate the structure shown in FIG. 1, FIG 3 is a diagram illustrating, for the employed silylation process, the linear relationship between the silylation time and the resulting sidewall width. Referring now to the drawing and first to FIG. 1 thereof, there is shown a sub-micron structure 10 which consists of a pattern of sub-micron width metallization lines 12S on semiconductor body 11. The lines are produced employing the process of the present invention which provides for the formation of sidewalls using silylation techniques. The sidewalls then serve as a mask to define the location and the sub-micron lateral dimensions of the metal lines. In the embodiment herein described, the lines consist of a metal and may e.g. form refractory gates of MESFET's. The invention can, however, also be utilized to produce non-metallic structures. In FIGS. 2A-2G the steps of the process used to fabricate the structure 10 of FIG. 1 are illustrated in detail. The successive steps are listed in Table I indicating the correspondence between the steps and the drawings. Step No. Description of Process Step Fig. Starting point: a substrate consisting of a semiconductor body covered with a metal layer. 2A 1 Spinning of a resist layer; followed by pre-baking and pattern exposure 2B 2 Resist development to form vertical edge profiles; followed by rinsing, drying, baking. 2C 3 Soaking in a silylation solution to increase the etch resistance of the resist down to a predetermined depths; followed by cleaning, drying, post-baking. 2D 4 Anisotropic etch (RIE) of the resist profile leaving only the silylated vertical portions forming the sidewalls. 2E 5 Anisotropic etch (RIE) of the metal layer portions not protected by the sidewall masks. 2F 6 Removal of the sidewalls leaving the desired sub-micron metallization pattern. 2G While the following description is primarily directed to the fabrication of the structure shown in FIG. 1, this description is only exemplary of the inventive process. It should be noted that the process of forming sidewall masks using silylation techniques can be employed in a wide variety of applications some of which will be mentioned further below, and that the thicknesses and other dimensions, the materials used as well as the process parameters chosen for the specific process described herein, are selected for clarity of illustration and are not to be interpreted in a limiting sense. Most individual process steps that are used, e.g., to deposit layers of different materials, to expose, to develop or to etch, are well known and can be performed employing conventional equipment and techniques. They are, therefore, not explained in greater detail herein. Referring now to FIG. 2A, the fabrication process is initiated starting from a semiconductor wafer 11 with a diameter of about 30 mm and covered with a metal layer 12 of 0.2 µ thickness. In the described example, the semiconductor material was Gallium-arsenide (GaAs), the metal tungsten silicide (WSi x ). This structure, cleaned and dried, serves as the "substrate" on which the sidewall masks are to be formed that are subsequently used to define the desired sub-micron pattern in metallic layer 12. In a first step, illustrated in FIG. 2B, a layer of a positive photoresist 13 of about 900 nm thickness is spin deposited (at 6000 rpm, 30 s), pre-baked for 20 minutes at 90°C, and then exposed to a light pattern (wavelength 300 nm, 10 mW/cm², 30 s). The resist chosen is AZ 4110, a Shipley product, that is widely available. Suitable for the process are all resists with a novolak resin, i.e., virtually all positive resists. Next, in step 2, the photoresist 13 is developed for 30 seconds using AZ 400K developer diluted with H₂O (1:4). This results in resist profiles 13A, 13B, having horizontal top surfaces and substantially vertical edges as illustrated in Fig. 2C. The structure so far produced is then rinsed (H₂O, more than 2 min) to remove the remaining developer, dried, and baked for 20 minutes at 90°C. Subsequently, reference is now made to FIG. 2D, the structure is soaked in a silylation solution Xylene:HMCTS:NMP (89:10:1) for 5 minutes at 20°C. This third step results in the silylation of all surfaces 15S, 15T of the resist profiles 13A, 13B down to a depth of 0.1 µm whereby the silylated resist becomes substantially more resistant to a subsequent oxygen etch process. Contrary to previously known sidewall techniques, these etch resistant silylated layers are formed within the resist profile rather than applied to the profile surfaces. The silylation agent used in the described example is a hexamethylcyclotrisilazane (HMCTS), which is stable in aprotic solvents, and safe for use in manufacturing. It reacts with novolak resin contained in the resist, forming a cross-linked insoluble polymer, incorporating silicon in the polymer matrix for RIE resistance. The reaction, in a spun pre-baked resist, is probably diffusion limited and depends on time, concentration and temperature. A variety of agents can be used provided they are suitable to replace the hydrogen in the resist with silicon atoms from the agents. Examples are, e.g., given in US Pat. Appl. Ser. No. 713,509. The amount of NMP (= n-Methyl pyrrolidone) in the silylation solution substantially determines the speed of the silylation process. One volume %, as in the example, leads to required times in the range of 5 to 20 minutes (at 20°C), depending on the desired silylation depth. The temperature also plays an important role. After rinsing the profile in Xylene for 5 seconds at room temperature to remove silicon from the surfaces, it is dried with dry nitrogen, and post-baked for 5 min at 90°C. In step 4, the structure is subjected to an anisotropic oxygen (O₂) reactive ion etch (RIE) (at 1.3 Pa, with 0.3W/cm²) as schematically indicated in FIG. 2E by arrows 20. This removes first, the silylated resist 15T at the top of the profiles 13A, 13B and subsequently, the unsilylated resist material down to the underlying metal layer 12. Etching through the silylated layer at the top of the profile is slow, etching through the unsilylated region proceeds much faster. This etch process is controlled using a laser and point detection (EPD) technique. The time required is about 30 min which includes a 20% overetch (EPD+20%) for the removal of residuals, e.g., resist material from the top surfaces that contain silicon. After this RIE step, the structure shown in FIG. 2E remains: the silylated vertical portions 15S of resist profiles 13A, 13B form the desired sidewalls that can be used as a mask to define sub-micron lateral dimensions in the underlying layer or layers, i.e., in the example herein described, in WSi x layer 12. In the next process step 5, the sidewall "image" is transferred to WSi x layer 12 as illustrated in FIG. 2F. In an anisotropic etch process, indicated by arrows 21, the exposed portions of layer 12, i.e., those not covered by the sidewalls 15S, are removed. A SF₆ RIE process, again at 1.3 Pa and 0.3W/cm², can be used. In the final sixth process step, the sidewalls 15S are stripped (for 10 min in NMP at 80°C). The resulting structure, shown in FIG. 2G, corresponds to that of FIG.1. As with known sidewall techniques, the above described process results in the formation of sidewalls at each substantially vertical slope of the profile. In situations where not all sidewalls are needed for the subsequent image transfer, the undesired sidewalls can be removed in a trimming process (following the anisotropic etch of the resist in step 4). This is done in an O₂/10% CF₄ RIE process using a trim mask to define the regions where the sidewalls are to remain. Such trim techniques are well known in the art. As will be apparent from the above process description, the thickness of the obtained sidewalls is determined by the silylation depth, i.e., the thickness of the resist material that has become highly oxygen etch resistant. In order to obtain highly accurate, reproducible sub-micron dimensions, a good control of the silylation process, particularly the silylation depth, is of utmost importance. The diagram of FIG. 3 illustrates the relationship between the silylation time, i.e., the time the resist profile is subjected to the silylation solution, and the resulting silylation depth, the latter corresponding to the width of the sidewalls eventually obtained. For a AZ 4110 photoresist, a silylation solution Xylene:HMCTS:NMP (89:10:1) and a temperature of 20°C, line 31, drawn from measured values 32, illustrates the linear dependence. The diagram shows that the resist silylation technique is a reliable and particularly simple process not requiring complex and expensive apparatus. It is a room temperature process. The new sidewall formation process has been described as applied in the fabrication of sub-micron metal line structures. It should however be apparent that there is a wide variety of other applications, particularly in but not restricted to the fabrication of semiconductor devices for use in integrated circuits or opto-electronic structures. Examples of structures that may be produced are sub-micron gates in refractory gate MESFET structures and laser structure gratings. In summary, the new sidewall process allows for image transfer in the fabrication of structures with lateral dimensions in the sub-micron range. The process requires fewer and substantially less critical steps, less complex apparatus and shorter process times than hitherto known sidewall techniques and, furthermore, its controllability and reproducibility has been shown to be very good.

Claims: Process for forming sidewalls for use in the fabrication of structures with sub-micron lateral dimensions, characterized in that the process comprises the steps of: depositing, on a substrate (11, 12), a patterned layer of polymeric resist comprising active hydrogen (-OH, -NH, -SH), the resist forming a profile (13A, 13B) with substantially vertical edges where the sidewalls are to be formed, treating the resist with a reactive organometallic silylation agent to substitute active hydrogen with silicon atoms, i.e., to silylate the top and the substantially vertical edges of the profile to a predetermined depth thereby rendering the profile surfaces (15S, 15T) highly oxygen dry etch resistant, and anisotropic oxygen dry etching (20) to remove the silylated resist at the top of the profile (15T) and, thereafter, the unsilylated resist, leaving the silylated substantially vertical edges (15S) of the profile, that form the desired sidewalls, essentially unaffected. A process as claimed in claim 1, wherein the reactive organometallic silylation agent used is a hexamethylcyclotrisilazane (HMCTS). A process as claimed in claim 2, wherein the resist is treated in a silylation solution comprising Xylene, HMCTS and n-Methylpyrrolidone (NMP). A process as claimed in claim 3, wherein the solution comprises Xylene, HMCTS and NMP, respectively amounting to 89, 10 and 1 volume %. A process as claimed in claim 4, wherein the resist treatment with the silylation agent takes place at a temperature of between 15 and 25°C. Process for fabricating line pattern of sub-micron dimensions on a semiconductor body, characterized in that it comprises the steps of: depositing a film (12) of the material from which the line pattern is to be formed on the semiconductor body (11), depositing , on the film (12), a patterned layer of polymeric resist comprising active hydrogen (-OH, -NH, -SH), the resist forming a profile (13A, 13B) with substantially vertical edges, treating the resist with a reactive organometallic silylation agent to substitute active hydrogen with silicon atoms, i.e., to silylate the top and the substantially vertical edges of the profile to a predetermined depth thereby rendering the profile surfaces (15S, 15T) highly oxygen dry etch resistant, anisotropic oxygen dry etching (20) to remove the silylated resist at the top of the profile (15T) and, thereafter, the unsilylated resist, leaving the silylated, substantially vertical edges (15S) of the profile, that form free-standing sidewalls, essentially unaffected, anisotropic etching (21) to remove those portions of said film (12) that are not covered by the sidewalls (15S), and removal of the sidewalls (15S) to obtain the desired line pattern. A process as claimed in claim 6, wherein the film (12) from which the line pattern is to be formed consists of a metal. A process as claimed in claim 7, wherein the film (12) consists of tungsten silicide (WSi x ). A process as claimed in claim 6, wherein, after the anisotropic oxygen dry etching step, selected portions of the sidewalls are removed in a trimming process, leaving only those sidewalls that correspond to the line pattern which is to be formed in the underlying layer (12).

Inventors: BUCHMANN, PETER LEO, VAN ZEGHBROECK, BART JOZEF, VETTIGER, PETER
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1986
Main classification: G03F7
IPC codes: H01L21, G03F7