CLOCK SYNCHRONIZING CIRCUIT INCLUDING A VOLTAGE CONTROLLED OSCILLATOR

Abstract: A clock synchronizing circuit includes first means for separating a clock component from a digital modulated wave and filtering the clock component, second means responsive to a clock signal for sampling the output of the first means to produce a two-level signal, and voltage controlled oscillator means for generating the clock signal, the phase and the frequency of the voltage controlled oscillator means being controlled by the output of the second means.

Description: Background of the Invention The present invention relates to a clock synchronizing circuit and, more particularly, to a clock synchronizing circuit for use with a demodulator in a digital carrier wave transmission system. In a demodulator applicable to a digital carrier wave transmission system, a clock signal must be provided in order that a demodulated analog signal may be sampled at optimum points and thereby converted to a digital signal, i.e. regenerated digital signal. A prior art clock synchronising circuit adapted for recovery of the clock signal comprises clock separating means, a limiter, a phase comparator, and a voltage controlled oscillator (VCO). The clock separating means serves to separate a clock component from a digital modulated wave (e.g. PSK wave or QAM wave) or a demodulated analog signal while the limiter is adapted to limit the amplitude of the separated clock component. The phase comparator compares an output of the limiter and that of the VCO in terms of phase, producing an error voltage which is proportional to the phase difference. Controlled by the error voltage, the VCO varies oscillation frequency thereof until the error voltage becomes minimum, that is, until a clock signal recovered by the VCO is brought into synchronism with the separated clock component. The recovered clock signal synchronized as stated is used to sample the previously mentioned demodulated signal. While the prior art clock synchronizing circuit requires the limiter thereof to be furnished with, among others, a small amount of AM/PM conversion, it is difficult to realize a limiter with a small amount of AM/PM conversion at the present stage of the art. Although such a limiter may be implemented with a high-speed IC gate, it is expensive and needs delicate adjustments. In EP-A-118 119, there is disclosed a timing recovery or synchronising circuit employing a regenerated timing signal which contains a negligible amount of jitter components and which maintains optimum timing without the need for phase adjustment. In EP-A-141 946, there is described a re-sampling circuit for a binary signal which contains a jitter component. It is not concerned with a clock or timing recovery circuit. It is an object of the present invention to provide a clock synchronizing circuit which is capable of producing a clock signal with a minimum of jitter without resorting to a limiter circuit, while reducing the circuit scale and, therefore, the costs. A clock synchronizing circuit to be described comprises first means for separating a clock component from a digital modulated wave or a demodulated signal of the digital modulated wave and filtering the clock component, second means for sampling the output of the first means responsive to a given clock signal to produce a two-level signal, and voltage controlled oscillator means for generating the clock signal with a phase and a frequency of the voltage controlled oscillator means controlled by the output of the second means. Brief Description of the Drawings The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which: Fig. 1 is a block diagram of a demodulator using a prior art clock synchronizing circuit; Fig. 2 is a block diagram of a demodulator using a first embodiment of the clock synchronizing circuit in accordance with the present invention; Fig. 3 shows waveforms useful for describing the operation of a flip-flop 211 which is included in the circuit of Fig. 2; Fig. 4 is a demodulator to which a second embodiment of the present invention is applied; Fig. 5 is a block diagram showing a third embodiment of the present invention; and Fig. 6 is a block diagram showing a fourth embodiment of the present invention. Detailed Description of the Invention Referring to Fig. 1, a demodulator using a prior art clock synchronizing circuit 2 is shown. As shown, the clock synchronizing circuit 2 is made up of a quadrature detector 1 for coherently detecting a multi-level quadrature modulated IF signal (e.g. QAM wave) I by a reference carrier wave recovered thereinside so as to produce baseband signals Bp and Bq, a clock synchronizing circuit 2 for recovering a clock signal C₁ out of the baseband signals Bp and Bq, and analog-to-digital (A/D) converters 3 and 4 for sampling and shaping respectively the baseband signals Bp and Bq by the clock signal C₁ to produce data signals Dp and Dq. The clock synchronizing circuit 2 comprises a full-wave rectifiers 201 and 202 adapted to full-wave rectify the baseband signals Bp and Bq, respectively, an adder 203 for mixing outputs of the rectifiers 201 and 202, a tank circuit (or bandpass filter) for narrow-band filtering an output of the adder 203, a limiter 205 for limiting the amplitude of an output of the tank circuit 204, a phase comparator 206 for comparing the phase of an output of the limiter 205 and that of the clock signal C₁, a low pass filter (LPF) for filtering an output of the phase comparator 206, and a voltage controlled oscillator (VCO) 208. In operation, the multi-level baseband signals are non-linearly operated by the full-wave rectifiers and others, so that a clock component separated appears at the output terminal of the adder 203. The tank circuit 204 suppresses to a certain extent the jitter which is contained in the clock component. The jitter present in the output of the tank circuit 204 consists of an AM component and a PM component. In order that the AM component may be prevented from being converted to a PM component due to imperfection of the subsequent stage of the circuitry, the limiter 205 is provided for suppressing the AM component. The phase comparator 206 compares the phase of the output of the limiter 205 and that of the output of the VCO 208. The output of the phase comparator 206 is applied via the LPF 207 to the VCO 208 to control the output phase of the latter, so that the clock signal C₁ outputted by the VCO 208 is phase-locked to the output of the limiter 205. The prior art clock synchronizing circuit constructed and operated as described above has the previously stated shortcomings. Referring to Fig. 2, a demodulator to which a clock synchronizing circuit in accordance with a first embodiment of the present invention is applied is shown. In Fig. 2, the same structural elements as those of Fig. 1 are designated by like reference numerals. The demodulator comprises a quadrature detector 1 for producing baseband signals Bp and Bq responsive to an IF signal I, a clock synchronizing circuit 21 in accordance with the present invention adapted to recover a clock signal C₂ from the baseband signals Bp and Bq, and A/D converters 3 and 4 adapted to sample and shape, respectively, the base band signals Bp and Bq in response to the clock signal C₂ thereby producing data signals Dp and Dq. As shown, the clock synchronizing circuit 21 is made up of full-wave rectifiers 201 and 202, an adder 203, a tank circuit 204, a D-type flip-flop 211 having an input terminal D to which a signal prepared by superposing a bias voltage Vb to an output of the tank circuit 204 is applied and a clock input terminal C to which the clock signal C₂ is applied, an LPF 207 to which a signal appearing at an output terminal Q of the flip-flop 211 is applied, and a VCO 208 adapted to produce the clock signal C₂. The demodulator of Fig. 2 will be operated as follows. The quadrature detector 1 coherently detects the IF signal I to produce baseband signals Bp and Bq which are respectively associated with the quadrature components of the IF signal I. The signals Bp and Bq are respectively sampled and shaped by the A/D converters 3 and 4 responsive to the clock signal C₂, thereby being converted to two sequences of data signals Dp and Dq. As previously stated in relation to Fig. 1, the tank circuit 204 of the circuit 21 outputs a clock component. The DC voltage level of the clock component is adjusted by the bias voltage Vb, which is superposed thereon and, then, sampled by the flip-flop 211 timed to the clock signal C₂. The output terminal Q of the flip-flop 211 becomes a ONE if the sampled value is greater than a predetermined threshold value of the flip-flop 211 and a ZERO if the former is smaller than the latter. Fig. 3 shows waveforms useful for describing the operation of the flip-flop 211. As the input at the input terminal D is varied as represented by curves a , b and c , the output at the output terminal Q assumes logical values as shown in Table 1 below. TERMINAL D INPUT TERMINAL Q OUTPUT a ONE & ZERO WITH SAME PROBABILITY b ONE c ZERO The output at the terminal Q, therefore, represents a phase comparison characteristic which in turn is representative of a phase relationship between the input at the terminal D and the clock signal C₂. Consequently, if the Q output of the flip-flop 211 is applied via the LPF 207 to the VCO 208 as a control signal, the clock synchronizing circuit 21 of Fig. 2 will be normally operable as a clock synchronizing circuit. In Fig. 3, it will be apparent that if the DC voltage level of the D input of the flip-flop 211 has been adjusted to the threshold level, the Q output remains unchanged despite any change in the clock component level of the D input. That is, the sampling means (flip-flop 211) in accordance with the present invention has a limiting function in addition to the phase comparing function. As described above, the clock synchronizing circuit 21 in accordance with the first embodiment recovers the clock signal C₂ from the baseband signals Bp and Bq and allows jitter, which is contained in the signal C₂, to be suppressed by the limiting function of the flip-flop 211 as well as by the tank circuit 204 and LPF 207. Fig. 4 shows a demodulator to which a clock synchronizing circuit in accordance with a second embodiment of the present invention is applied. In Fig. 4, the same structural elements as those of Figs. 1 and 2 are designated by like reference numerals. As shown, the demodulator comprises a quadrature detector 1, a clock synchronizing circuit 22 in accordance with the present invention which is adapted to recover a clock signal C₃ from an IF signal I, and A/D converters 3 and 4 adapted to sample and shape baseband signals Bp and Bq in response to the clock signal C₃ to thereby produce data signals Dp and Dq. The clock synchronizing circuit 22 includes an envelope detector 221 which is a substitute for the full-wave rectifiers 201 and 202 and adder 203 of Fig. 2. From a digitally modulated IF signal a clock component can be separated by subjecting it to envelope detection or like non-linear operation. Thus, the envelope detector 221 separates a clock component from an IF signal I. Responsive to the clock component, the tank circuit 204, flip-flop 211, LPF 207 and VCO 208 function each in the same manner as discussed in relation to the clock synchronizing circuit 21. As discussed above, the clock synchronizing circuit 22 in accordance with the second embodiment recovers the clock signal out of the IF signal I. The circuit 22, like the circuit 21, is successful in suppressing jitter to a minimum. Generally, in a phase-locked loop which includes a limiter therein, the limiter serves as a high gain amplifier when an input signal is absent. In this condition, the influence of leak of an output of a VCO to the input of the limiter becomes substantial so that the oscillation frequency of the VCO is apt to become deviated from its center oscillation frequency. For this reason, in an initial state where an input signal has been entered, the deviation between the frequency of the input signal and the oscillation frequency of the VCO is so great that a substantial period of time is needed for pull-in, or tuning, to be completed. Another embodiment of the present invention which constitutes a solution to such a problem will be described with reference to Fig. 5. In Fig. 5, a clock synchronizing circuit 23 comprises in addition to the structural elements of the circuit 22 of Fig. 4 a signal detector 231 whose output becomes a ONE when an output of the tank circuit 204 is present and a ZERO if otherwise, an OR/NOR gate 232 to which an output of the signal detector 231 is coupled, a NOR gate 233 to which an OR output of the gate 232 and an output of the flip-flop 211 are fed, and a NOR gate 234 to which a NOR output of the gate 232 and the own output are applied. The outputs of the NOR gates 233 and 234 are routed to the LPF 207. The circuit 23 further comprises a VCO 235 which is opposite in the polarity of control voltage to the VCO 208 of the circuit 22. In operation, so long as the IF signal I is digitally modulated in an normal manner and the tank circuit 204 produces a clock component (normal operation), the input to the OR/NOR gate 232 is a ZERO so that the output of the NOR gate 234 is a ZERO and the output of the NOR gate 233 is an inverted version of the output of the flip-flop 211. In this situation, the clock synchronizing circuit 23 is allowed to operate in the same manner as the previously discussed circuit 22. Conversely, while the clock output from the tank circuit 204 is absent, the input to the OR/NOR gate 232 is a ONE with the result that the output of the NOR gate 233 is a ZERO which inhibits the output of the flip-flop 211. Meanwhile, because one of the inputs to the NOR gate 234 is a ZERO and the other is the own output which is fed back, the output of the gate 234 is held at a certain constant value. This constant output of the gate 234 is substantially equal to a voltage which the NOR gate 233 produces in a normally operating condition (if not equal, the output level of the NOR gate 234 is adjustable through an external circuit), the free oscillation frequency of the VCO 235 therefore being substantially equal to that which would hold under a normally operating condition. As described above, the clock synchronizing circuit 23 in accordance with the third embodiment is operable in the same manner as the circuit 22 so long as the IF signal I is digitally modulated in a normal manner, while when the tank circuit 204 does not produce a clock component maintaining the frequency of the clock signal C₄ at the free oscillation frequency of the VCO 235. This effectively cuts down the pull-in time. Fig. 6 shows a clock synchronizing circuit which recovers a clock signal from the baseband signals and shortens the pull-in time. In Fig. 6, the clock synchronizing circuit 24 comprises in addition to the structural elements of the circuit 21 of Fig. 2 the signal detector 231, OR/NOR gate 232 and NOR gates 233 and 234, which are included in the circuit 23 of Fig. 5. The circuit 24 is operable in the same manner as the circuit 23. While the present invention has been shown and described in relation to a digital carrier transmission system, it will be apparent that it is similarly applicable to a digital baseband transmission system. In summary, it will be seen that the present invention provides a clock synchronizing circuit with a minimum of jitter without resorting to a high-speed IC gate and other expensive elements. This advantage is derived from the use of a D-type flip-flop or like inexpensive sampling means which bifunctions as a limiter and a phase comparator.

Claims: A clock synchronizing circuit comprising: first means (221, 204) for separating a clock component from a digital modulated wave(I); phase comparing means (211) for detecting a phase difference between said clock component and a clock signal(C3) to generate a control signal; voltage controlled oscillator means (207, 208) for generating said clock signal with a phase and a frequency of said voltage controlled oscillator means controlled by the control signal; analogue-to-digital converter means responsive to the clock signal and demodulated signals (Bp, Bq) of the digital modulated wave for outputting digital signals (Dp, Dq); characterized in that said phase comparing means comprises; DC bias supplying means for supplying a bias voltage (V b ) to said clock component and generating a biased clock component; and second means (211) responsive to the clock signal for sampling the biased clock component to produce the control signal, said bias voltage being adjusted to a threshold level of said second means, whereby the second means (211) provides both a limiting and a phase comparing function. A clock synchronizing circuit as claimed in claim 1, wherein said first means comprises an envelope detector (221) for envelope-detecting the digital modulated wave, and a tank circuit (204) for filtering the output of said envelope detector. A clock synchronizing circuit as claimed in claim 1, wherein said second means comprises a D-type flip-flop (211). A clock synchronizing circuit as claimed in claim 1, further comprising a signal detector (231) for detecting the output of said first means, and means (232, 233, 234) for selectively applying the output of said second means and a given constant voltage to said voltage controlled oscillator means. A clock synchronizing circuit comprising: first means (201, 202, 203, 204) for separating a clock component from demodulated signals (Bp, Bq) of a digital modulated wave(I); phase comparing means (211) for detecting a phase difference between the clock component and a clock signal(C2) to generate a control signal; voltage controlled oscillator means (207, 208) for generating said clock signal with a phase and a frequency of said voltage controlled oscillator means controlled by the control signal; analogue-to-digital converter means (3, 4) responsive to said clock signal and the demodulated signals for outputting digital signals (Dp, Dq); characterized in that said phase comparing means comprises; DC bias supplying means for supplying a bias voltage (V b ) to said clock component and generating a biased clock component; and second means (211) responsive to the clock signal for sampling the biased clock component to produce the control signal, said bias voltage being adjusted to a threshold level of said second means, whereby the second means (211) provides both a limiting and a phase comparing function. A clock synchronizing circuit as claimed in claim 5, further comprising a quadrature detector (1) for quadrature-detecting the digital modulated wave(I) to produce the demodulated signals (Bp, Bq). A clock synchronizing circuit as claimed in claim 6, wherein said first means comprises rectifiers (201, 202) for full-wave rectifying respectively two demodulated signals which are outputted by said quadrature detector, an adder (203) for combining outputs of said rectifiers, and a tank circuit (204) for filtering the output of said adder to provide said clock component. A clock synchronizing circuit as claimed in claim 5, wherein said second means comprises a D-type flip-flop (211). A clock synchronizing circuit as claimed in claim 5, further comprising a signal detector (231) for detecting the output of said first means, and means (232, 233, 234) for selectively apply the output of said second means and a given constant voltage to said voltage controlled oscillator means.

Inventors: YOSHIDA, YASUHARU C/O NEC CORPORATION
Applicants: NEC CORPORATION
Application year: 1986
Main classification: H04L7
IPC codes: H04L7, H03L7, H03K5, H04L27