VIDEO SIGNAL PROCESSING APPARATUS

Abstract: A video signal processing apparatus incorporates a 1H or 2H (H: horizontal synchronization period) delay circuit (3). The output of the delay circuit (3) is fed back to the input thereof so as to average the noise, thus raising the signal S/N ratio. The feedback line includes a nonlinear processing circuit (8) with a small gain when the signal input has a low vertical correlation, whereby the signal S/N ratio is improved without causing delay of the colour signal in the vertical direction nor deterioration of resolution of the luminance signal.

Description: The present invention relates to a video signal processing apparatus for use in a video tape recorder (VTR). To raise the S/N ratio of the video signal processed in VTR's, a recursive filter has been used for video signal processing. The recursive filter involves a delay circuit for delaying the video signal by 1H or 2H (H: horizontal synchronization period). The filter feeds output of the delay circuit back to the input thereof to average the signal noise, thus raising the video signal S/N ratio. With the conventional circuit construction, however, when the video signal has a low vertical correlation, i.e. when the signal input to the recursive filter shows a sudden change, the filter cannot follow the output change promptly. If such a circuit is used in processing colour signals, a delay in colour change causes a downward colour offset (colour offset in a downward direction on the TV screen due to the colour signal delay with respect to the luminance signal). If the luminance signal is processed with this circuit, the vertical resolution will deteriorate. A noise reduction circuit for a video signal is disclosed in GB-A-2141303 (corresponding to DE-A-3412529), in which a circuit 12 delays an input video signal by a predetermined delay time equal to an integer multiple of the horizontal scanning period, a first circuit 14 adds the input video signal and the delayed video signal, a circuit 13 subtracts the input video signal from the delayed video signal, a noise clipping circuit 15 eliminates the noise component at zero dc level of an output signal of the circuit 13, and produces a signal having a waveform corresponding to a correlation error which is introduced in an output signal of the first circuit 14. A second circuit 16 adds the output signals of the first circuit 14 and the noise clipping circuit 15 to produce the output video signal (a portion of this may be added to the input video signal to produce a further reduction in noise). A noise suppression circuit for a video signal is disclosed in GB-A-2098023 and comprises a subtracting circuit 5, a nonlinear circuit 23, an adder circuit 9 and a delay circuit 15. The nonlinear circuit 23 is given a transfer factor equal to unity for signals applied to it having low amplitude values, the transfer factor decreasing towards zero with increase in amplitude of the applied signal. A system for reducing or suppressing the noise components in a TV signal is disclosed in US-A-4302768. In the system, the component representative of the difference between the as-input (or as-received) TV signal and the TV signal which has been delayed by one horizontal scanning period is derived. The difference component is then subjected to amplitude limitation, and the noise components in the TV signal reproduced by a VTR or the like are removed or suppressed by a comb filter comprising the as-input TV signal and the amplitude-limited difference component. It is an object of the present invention to provide a video signal processing apparatus that does not cause the downward colour offset when passing the carrier chrominance signal through a recursive filter which incorporates 1H or 2H delay circuit. It is also an object of the present invention to provide a video signal processing apparatus which does not cause downward colour offset when passing the chrominance difference signal through a recursive filter incorporating a 1H or 2H delay circuit, and which does not cause deteriorated vertical resolution when passing the luminance signal through the recursive filter. To achieve the above objects, the present invention provides a video signal processing apparatus comprising: a delay circuit (3) for delaying an input signal by a predetermined time; a first operational circuit (4) for conducting an addition or subtraction operation between an output signal of said delay circuit and an input video signal; a nonlinear processing circuit (9) which receives an output signal of said first operational circuit and generates first and second output signals, characterised in that the first output signal generated by the non-linear processing circuit has a gain of K that decreases with an increase of the absolute value of the level of the output signal of said first operational circuit and becomes zero when said absolute value exceeds a specified value, the second output signal having a gain of 1/2 (1 + K); and in that the processing apparatus further comprises a second operational circuit (2) for conducting an addition or subtraction operation between said first output signal of said nonlinear processing circuit and said input video signal and outputting the operation result to the input of said delay circuit; and a third operational circuit (6) for conducting an addition or subtraction operation between said second output signal of said nonlinear processing circuit (9) and said input video signal. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1(a) is a block diagram showing a first embodiment of the present invention; Figures 1(b) and 1(c) are charts showing input/output characteristics of the nonlinear processing circuit in the first embodiment of the present invention; Figure 2(a) is a chart showing the frequency characteristics and the carrier chrominance signal spectrum of the first embodiment of the present invention; Figure 2(b) is a chart showing the frequency characteristics and the spectrum of colour difference or luminance signal of the second embodiment of the present invention; Figure 3 is a block diagram showing a second embodiment of the present invention; Figure 4 is a block diagram showing a third embodiment of the present invention; and Figure 5 is a block diagram showing a fourth embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the accompanying drawings. Figure 1 (a) is a block diagram showing the first embodiment of the color signal processing apparatus according to the present invention. Figures 1 (b) and 1 (c) show the input/output output (I/O) characteristics of the nonlinear processing circuit in the first embodiment. In this case, the input video signal is the NTSC carrier chrominance signal. The carrier chrominance signal is inputted through an input terminal 1 and enters a subtractor 2 which subtracts an output signal of a nonlinear processing circuit 8 from the input carrier chrominance signal. The output signal of the subtractor 2 enters a 1H delay circuit 3. The output signal of the 1H delay circuit 3 is added to the carrier chrominance signal by an adder 4. The output signal of the adder 4 is fed to nonlinear processing circuits 5 and 8 which constitute a nonlinear processor 9. The output signal of the nonlinear processing circuit 8 is fed back to the subtractor 2. The output signal of the nonlinear processing circuit 5 is subtracted from the carrier chrominance signal by a subtractor 6. The output signal of the subtractor 6 is fed to an output terminal 7. The nonlinear processing circuits 5 and 8 are assumed to have linear characteristics with gains of 1/2 (K + 1) and K, respectively. The transfer function G₁ (S) from the input terminal 1 to the output terminal of the adder 4 is expressed by the following formula: The transfer function G₀ (S) from the input terminal 1 to the output terminal 7 is expressed by the following formula: The transfer function G₁ (S) provides a comb filter characteristic having peaks at the frequencies of integral multiples of the horizontal synchronization frequency fH, and nodes at the frequencies of (integer + 1/2) multiples of fH. The transfer function G₀ (S) provides a comb filter characteristic having peaks at the frequencies of (integer + 1/2) multiples of the horizontal synchronization frequency fH and nodes at the frequencies of integral multiples of fH. In Figure 2 (a), the frequency characteristic is indicated by the curve and the carrier chrominance signal spectrum by the shades, with frequency along the axis of abscissa and gain along the axis of ordinate. As shown in Figure 2 (a), since energy of the carrier chrominance signal spectrum concentrates at the frequencies of (integer + 1/2) multiples of fH, the carrier chrominance signal spectrum alone is outputted to the output terminal 7, whereby the color signal S/N ratio is improved. G₁ (S) has peaks at the frequencies of integral multiples of the horizontal synchronization frequency, the spectra at which frequencies increase when the carrier chrominance signal has a lower vertical correlation. Accordingly, a non-correlation signal is obtained at the output terminal of the adder 4. The non-correlation signal is then fed back to the subtractor 2 through the non-linear processing circuit 8. The above description is based on the assumption that the non-linear processing circuit 8 has a constant gain of K. The constant gain will result in a constant feedback even with a large output signal of the adder 4, or with a low vertical correlation, and therefore will cause a downward color offset when color changes in the vertical direction. In this embodiment of the invention, non-linear characteristics are given to the gains of the non-linear processing circuits 5 and 8 to prevent the downward color offset. Figures 1 (b) and 1 (c) show the I/O characteristics of the non-linear processing circuit 8 and 5, respectively, employed in the present embodiment of the invention. As shown in Figure 1 (b), the non-linear processing circuit 8 provides a limitter characteristic so that it has no output when the input signal level is high. Specifically, when the color signal correlation is low, the input signal level to the nonlinear processing circuit 8 becomes large so that the nonlinear processing circuit 8 does not produce an output signal to be fed back to the delay circuit 3. Because of the absence of the signal feedback, the present embodiment is free from downward color offset. Moreover, according to the first embodiment of the invention, the nonlinear processing circuit 5 is set to have a gain of 1/2 (l + K) for the gain of K of the nonlinear processing circuit 8. With an input signal level of "3", for instance, the nonlinear processing circuit 8 outputs "1". In this case, the value of K is "1/3" (K = 1 ÷ 3 = 1/3). Hence, the gain of the non-linear processing circuit 5 for the input level of "3" is "2/3" as the result of the calculation of 1/2 (1 + 1/3). The output signal of the circuit 5, which is the product of the input "3" and the gain "2/3", is therefore "2". Thus, the output signal of the nonlinear processing circuit 5 for each input level can be set according to the I/O characteristic of the nonlinear processing circuit 8. The reason for setting the I/O characteristic of the nonlinear processing circuit 5, as described above, is to attain "1" as a peak gain of G₀ (S). When the carrier chrominance signal is a PAL signal, a 2H delay circuit is used in place of the 1H delay circuit because the carrier chrominance signal provides correlation at intervals of 2H. The non-linear processing circuit 8 may have a gain which decreases as the input signal level absolute value increases and which becomes zero when the input signal level absolute value exceeds a specified value. The non-linear processing circuit 5 may have a gain expressed as 1/2 (1 + K), where K is the gain of the non-linear processing circuit 8. The circuits having such gains can be easily realized by known art. The embodiment of Figure 1 (a) can better be realized by a digital circuit. The 1H delay circuit 3 can be configured by a shift register. The non-linear circuits 5 and 8 are each configured by a read-only memory (ROM). The output signal of the adder 4 is applied to the ROM as an address signal, and the ROM outputs a data signal stored in the address specified by the address signal. By use of the ROM, any non-linear characteristic can be easily realized for each of the non-linear circuits 5 and 8. A second embodiment of the present invention will now be described referring to Figure 3 which shows an example of the present invention applied for processing a demodulated chrominance difference signal or a luminance signal. The R-Y signal and B-Y signal are examples of the chrominance difference signals. The signal processor circuit for one of the two chrominance difference signals is shown in Figure 3; the other chrominance difference signal is processed in a separate but identical signal processor circuit as shown in Figure 3. The chrominance difference signal inputted through the input terminal 1 enters a subtractor 2 which subtracts an output signal of the nonlinear processing circuit 8 from the input chrominance difference signal. The output signal of the subtractor 2 enters the 1H delay circuit 3. The output signal of the 1H delay circuit 3 is subtracted from the input chrominance difference signal by a subtractor 10. The result is then inputted to the nonlinear processing circuit 5 and to the nonlinear processing circuit 8 from which the signal is fed back to the subtractor 2. The output signal of the nonlinear processing circuit 5 is subtracted from the input chrominance difference signal by the subtractor 6, the result being outputted to the output terminal 7. Similar to the previous embodiment, the nonlinear processing circuits 5 and 8 are assumed to have linear characteristics, with gains of 1/2 (K + 1) and K, respectively The transfer function H₁ (S) from the input terminal 1 to the output terminal of the subtractor 10 is expressed by the following formula: The transfer function H₀ (S) from the input terminal 1 to the output terminal 7 is expressed by the following formula: The transfer function H₁ (S) provides a comb filter characteristic having peaks at the frequencies of (integer + 1/2) multiples of the horizontal synchronization frequency fH and nodes at the frequencies of integral multiples of fH. The transfer function H₀ (S) provides a comb filter characteristic having peaks at the frequencies of integral multiples of the horizontal synchronization frequency fH and nodes at the frequencies of (integer + 1/2) multiples of fH. In Figure 2 (b), the frequency characteristic of H₀ (S) is indicated by the curve and the chrominance difference signal (or luminance signal) spectrum by the shades, with frequency along the axis of abscissa and gain along the axis of ordinate. As indicated in Figure 2 (b), since energy of the chrominance difference signal spectrum concentrates at the frequencies of integral multiples of fH, the chrominance difference signal spectrum alone is outputted to the output terminal 7, whereby the color signal S/N ratio is improved. The second embodiment of the invention is also free from downward color offset which could occur in the absence of vertical correlation of the chrominance difference signal, as well as from vertical resolution deterioration. The principle for preventing downward color offset and vertical resolution deterioration is not described here because it is the same as in the first embodiment. Moreover, according to the second embodiment of the invention, since two chrominance difference signals are processed by the separate but identical circuits, it is possible prevent downward color offset for both hue and saturation factor variations only by taking appropriate measures against the downward color offset according to the vertical correlation of each chrominance difference signal level. A third embodiment of the invention will now be described with reference to Figure 4. A nonlinear processing circuit 12 corresponds to the nonlinear processing circuit 8 of the first embodiment. A nonlinear processing circuit 12, an adder 11 and a coefficient circuit 13 correspond to the non-linear processing circuit 5 of the first embodiment. Providing that a coefficient of the coefficient circuit 13 is "1/2" and the gain of the nonlinear processing circuit 12 is K, the gain between the outputs of the adder 4 and adder 11 is 1 + K, and therefore the gain between the outputs of the adder 4 and the coefficient circuit 13 is 1/2 (1 + K). The gain between the outputs of the adder 4 and adder 11 of the third embodiment corresponds to the gain of the nonlinear processing circuit 5 of the first embodiment, in which gain is 1/2 (1 + K) assuming that the gain of the nonlinear processing circuit 8 is K, as described earlier. Thus, with the nonlinear processing circuit 12, adder 11 and coefficient circuit 13, assuming the function of the nonlinear processing circuit 5 of the first embodiment, the third embodiment yields the same effect as the first embodiment while involing only one nonlinear processing circuit. Specific operation of the third embodiment is omitted here because it is the same as that of the first embodiment. The embodiment of Figure 4 can also better be realized by a digital circuit in the similar way to the first embodiment. The 1H delay circuit 3 can be configured by a shift register. The non-linear circuit 12 can be configured by a ROM. The coefficient circuit 13 can be configured by a shift register or a multiplier. Figure 5 is a block diagram of a fourth embodiment of the present invention. The fourth embodiment is comparable to the second embodiment. The subtractor 10 is used in place of the adder 4. The operation of the fourth embodiment is completely the same as that of the second embodiment and therefore omitted here.

Claims: A video signal processing apparatus comprising: a delay circuit (3) for delaying an input signal by a predetermined time; a first operational circuit (4) for conducting an addition or subtraction operation between an output signal of said delay circuit and an input video signal; a nonlinear processing circuit (9) which receives an output signal of said first operational circuit (4) and generates first and second output signals, characterised in that the first output signal generated by the non-linear processing circuit (9) has a gain of K that decreases with an increase of the absolute value of the level of the output signal of said first operational circuit and becomes zero when said absolute value exceeds a specified value, the second output signal having a gain of 1/2 (1 + K); and in that the processing apparatus further comprises a second operational circuit (2) for conducting an addition or subtraction operation between said first output signal of said nonlinear processing circuit (9) and said input video signal and outputting the operation result to the input of said delay circuit (3); and a third operational circuit (6) for conducting an addition or subtraction operation between said second output signal of said nonlinear processing circuit (9) and said input video signal. Apparatus as claimed in claim 1, wherein said delay circuit (3) delays the input signal by 1H or 2H (H: horizontal synchronization period). Apparatus according to claim 1 or 2, wherein the nonlinear processing circuit (9) comprises a first nonlinear circuit (8) that receives an output signal of said first operational circuit (4) and has a gain of K which decreases with an increase of the absolute value of the level of the output signal of said first operational circuit and becomes zero when said absolute value exceeds a specified value; and a second nonlinear processing circuit (5) that receives the output signal of said first operational circuit (4) and has a gain of 1/2 (1 + K). Apparatus as claimed in claim 1, 2 or 3, wherein said input video signal is a carrier chrominance signal modulated by a chrominance sub-carrier. Apparatus as claimed in claim 1, 2 or 3, wherein said input video signal is a chrominance difference signal demodulated in the basic band or a luminance signal. A video signal processing apparatus comprising: a delay circuit (3) for delaying an input signal by a predetermined time; a first operational circuit (4) for conducting an addition or subtraction operation between an output signal of said delay circuit and an input video signal; a nonlinear processing circuit (12) that receives an output signal of said first operational circuit (4), characterised in that the circuit (12) has a gain which decreases with an increase of the absolute value of the level of the output signal of said first operational circuit and becomes zero when said absolute value exceeds a specified value; and in that the apparatus further comprises a second operational circuit (2) for conducting an addition or subtraction operation between an output signal of said nonlinear processing circuit (12) and said input video signal and outputting the operation result to the input of said delay circuit (3); an adder circuit (11) for adding the output signal of said nonlinear processing circuit (12) to the output signal of said first operational circuit (4); a coefficient circuit (13) for multiplying an output signal of said adder circuit by a predetermined coefficient; and a third operational circuit (6) for conducting an addition or subtraction operation between an output signal of said coefficient circuit and said input video signal. Apparatus as claimed in claim 6, wherein said delay circuit (3) delays the input signal by 1H or 2H (H: horizontal synchronization period). The video signal processing apparatus as claimed in claim 6 or 7, wherein said coefficient of said coefficient circuit (13) is 1/2. Apparatus as claimed in claim 6, 7, or 8, wherein said input video signal is a carrier chrominance signal modulated by a chrominance sub-carrier. Apparatus as claimed in claim 6, 7 or 8, wherein said input video signal is a chrominance difference signal demodulated in the basic band or a luminance signal.

Inventors: HONJO, MASAHIRO, MATSUMOTO, TOKIKAZU, NAKAGAWA, YUKIO
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1986
Main classification: H04N5
IPC codes: H04N5, H04N9