Driving circuit of a liquid crystal display device

Abstract: There is provided a semiconductor device using a molybdenum-tantalum alloy having a tantalum composition ratio of 30 to 84 atomic percent. Using this Mo-Ta alloy, there is provided an electrode interconnection material comprising a multi-layered structure having an underlying metal film having a crystalline form of a body-centered cubic system and overlying a molybdenum-­ tantalum alloy film having a tantalum composition ratio of above 84 atomic percent. Further using this Mo-Ta alloy, there is provided a display device driving cir­ cuit substrate comprising an insulating substrate, a plurality of address lines (11) and data lines (13) intersecting each other on the substrate, the address line (11) being formed of a molybdenum-tantalum alloy having a tantalum composition ratio of 30 to 84 atomic percent, a plurality of thin-film transistors (15) each formed at an intersection of said address and data lines (11, 13) and having its gate electrode (17) connected to an address line (11) and its source electrode (18) con­ nected to data line (13), and a plurality of display electrodes (21) connected to the drain electrode (19) of the thin-film transistor (15).

Description: This invention relates to a driving circuit of a liquid crystal display device. Recently, attention has been focused on an active matrix type liquid crystal display device in which a thin-film transistor (TFT) using an amorphous silicon (a-Si) film is employed as a switching element. This is because, if a TFT array is formed using an amorphous glass substrate and a-Si film producible at low temperatures, it is possible to implement an inexpensive panel display device (flat type television) of a larger screen, higher quality and higher definition. Where an inverted staggered TFT is adopted having, for example, a glass substrate, gate electrode interconnection on the substrate and insulating film and a-Si film on the gate electrode interconnection, since the thin semiconductor film and data line are formed on the gate electrode and address line irrespective of their restricted thickness, it is necessary to form a thin electrode interconnection of an adequately small thickness. In the formation of a multi-layered structure an underlying electrode interconnection is tapered at the stepped edge to prevent breakage of the overlying layer. For this reason, the following requirements are needed: for example, the workability; formability of a stable oxide film as a gate insulating film; and resistance to, for example, sulfuric acid and hydrogen peroxide at a subsequent washing step. Conventionally, as a gate electrode interconnection material which satisfies the aforementioned requirements, use has been made of various metal films, such as tantalum and titanium. In order to attain a larger image screen and high definition, a material is desired which has a smaller electrical resistance, better workability and excellent resistance to chemicals at the subsequent step. These characteristics are required for source and drain electrode interconnection materials if a staggered TFT structure is adopted in which source and drain interconnections are formed on a substrate. A similar problem also arises from a liquid crystal display device which is not of an active matrix type. In order to obtain a greater image screen on an active matrix type display device using the smallest possible display pixels, fine and longer gate and data lines are necessary as signal lines to TFT. Furthermore, the resistance must be made adequately smaller so as to eliminate waveform deformation resulting from the delay of a pulse signal. Where an active matrix type liquid crystal display device of greater image screen and high definition is achieved, use is made of a much greater number of thin film transistors. In an array of 400 address lines x 400 data lines, for example, 160000 pixels are required. It is difficult to completely manufacture so many thin-film transistors in an array, involving various faults, such as a short-circuiting among the interconnection layers in a multi-layered film structure, short-circuiting of a capacitor, open-circuiting of the interconnection and faults of the thin-film transistor. If a point fault is allowed for the display device, it is possible to readily remedy the open-circuiting of the interconnection layers. That is, even if the address line is broken, it can be remedied by supplying a signal from each end of the address line. The short-circuiting of the capacitor which is stored with a signal voltage can be avoided because, if the OFF resistance of the thin-film transistor is made great enough and if the resistivity of the liquid crystal is made great, it is not necessary to provide such a capacitor. The short-circuiting between the interconnection layers causes a fatal defect and if, for example, a short-circuiting occurs between the address and data lines a line fault occurs along the interconnection layer, failing to readily remedy such defect. As a method for preventing short-circuiting between the layers in the multi-layered structure, a driving circuit according to the preamble of claim 1 has been proposed in Japanese Patent Publication (Kokoku) JP-A-60-54478 which forms address lines and gate electrode of tantalum, anodically oxidizes the surface of the resultant structure and deposits a SiO₂ or Si₃N₄ film. According to this method the resistance of the address lines is increased due to the anodic oxidation of tantalum. In a thin-film transistor structure of, for example, 220 x 240 pixels for a 44 x 60 mm image screen, if a 150 nm-thick address line of tantalum with a line resistance of about 60 KΩ is oxidized down to about 70 nm (700 Å), then the line resistance becomes about 110 KΩ. For an increasing line resistance waveform distortion becomes greater due to delay of an address pulse signal. As a result, a time discrepancy occurs between the writing of data into the input terminal and final end of the address line, thus impairing the uniformity of image quality. If the thickness of the tantalum film is increased, then the line resistance can be reduced, but the tantalum film begins to peel for too thick a tantalum film, providing cause for the open-circuiting of the data line. Molybdenum is known as a material whose resistance is smaller than tantalum. Since molybdenum has a poor resistance to chemicals and cannot be washed in a mixture solution of a sulfuric acid and hydrogen peroxide and since a better insulating film cannot be formed on the surface, no adequate characteristic is provided which is required for the address lines at the active matrix substrate. Mo-Ta alloys for use as electrical contacts and interconnections in semiconductor devices are known from US-A-3754168. From JP-A-58-7864 it is known that forming gate electrodes of semiconductor devices of more than two types of high melting point alloy layers, including Mo-Ta alloys, results in electrodes of low resistance and thus enables high speed operation by shortening an access time. An object of the present invention is to provide a driving circuit for a liquid crystal display device with improved characteristics. This object is met by a driving circuit according to claim 1. According to this invention, the material of the gate electrode/address line is smaller in resistivity than those metals such as Ta, Mo and Ti and even smaller than MoSi₂. It has also workability, better resistance to various treating liquids and excellent ohmic junction with a semiconductor, such as silicon. Tantalum has two kinds of crystal structures: a tetragonal type and body centered cubic type. Ta of the tetragonal system is referred to as β-Ta with a lattice constant of a O = 0.534 nm (5. 34 Å) and c O = 0.994 nm (9. 94 Å) and the resistivity of the deposited thin film is ρ = 180 to 200 µΩ·cm. That thin film usually assumes such a crystalline form. Ta of a body-centered cubic lattice is referred to as an α-Ta with a lattice constant of a O =0.33nm (3. 30 Å) and resistivity of the deposited thin film is ρ = 10 to 150 µΩ·cm. Bulk is formed usually in such a crystalline form. α-Ta is markedly small in resistivity. α-Ta is very difficult to treat in the form of a thin film due to its unstable resistance, its greater resistance temperature coefficient of 100 to 300 ppm/°C, its readiness to crack, its uneven surface, its peelability and so on. The Mo-Ta alloy is of a thin-film type and easily treatable in the form of the thin film as in β-Ta but still has a small resistivity characteristic as in α-Ta. It may be considered that the mixing of Mo into Ta gives a crystalline structure of a body-centered cubic lattice type as in the case of the α-Ta to provide an α-Ta and Mo alloy with a smaller resistance. The Mo-Ta alloy usually assumes a tetragonal structure, in the case of a thin film, within a greater Ta composition ratio range (more than 84%). If, on the other hand, an Mo-Ta alloy film is multi-layered on an underlying metal film of a body-centered cubic type, the alloy film takes on a body-centered cubic structure in the case of a greater Ta composition ratio range (more than 84%) due to the specific crystalline structure on the underlying metal film like the epitaxial growth of crystal. As a result, a low-ohmic electrode interconnection can be realized irrespective of the value of the Ta composition ratio. According to this invention, since the address interconnection and gate electrode are prominently lower in resistance in the driving circuit of the display device, an address signal propagation delay time can adequately be decreased even if a high definition is attained on a greater image screen. Furthermore, the resistance can be reduced without increasing the thickness of the address interconnection layer and taper etching can also be effected readily, thus preventing a breakage of the overlying data line. An anodic oxidation film of a better quality can be formed for the address line and gate electrode of this invention. For this reason, a multi-layered insulating film of the anodic oxide film and SiO₂ film formed by, for example, a CVD (Chemical Vapor Deposition) is employed as a gate insulating film, and at the intersection of the address and data lines a thin semiconductor film is formed on that gate insulating film to provide an insulating interlayer. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is an equivalent circuit diagram of an active matrix type liquid crystal display device; Fig. 2 is an enlarged plan view showing a major portion of an active matrix substrate in Fig. 1; Fig. 3 is a cross-sectional view, as taken along line A-A' in Fig. 2, showing the active matrix substrate with no underlying metal film used; Figs. 4A to 4B are cross-sectional views, as taken along lines A-A' and B-B' respectively in Fig. 2, showing a variation in the gate insulating film; Fig. 5 is a cross-sectional view, as taken along line A-A' in Fig. 2, with an underlying metal film used showing an embodiment of the invention; Fig. 6 shows a comparison in resistivity between an electrode interconnection material for a multi-layered structure and a single-layered structure; and Figs. 7A and 7B show the X-ray diffraction data of an electrode interconnection material for a multi-layered structure and that of a single-layered structure. Various metal or alloy films were systematically experimented for an electrode interconnection material for a semiconductor device, with the use of an a-Si film, polycrystalline silicon film, or single crystalline silicon substrate. As a result of the experiments, it has been found that, within a restricted composition range of Ta and Mo, an interconnection material is obtained which, upon comparison with the Ta or Mo film for a conventional interconnection in terms of its electrical resistance, has a lower electrical resistance, as well as excellent characteristics in terms of its workability, oxide film formation and ohmic contact property in relation to the silicon. For Ta exceeding 84 atomic percent, the resultant alloy film manifests a better workability, as well as a better oxide film forming property and better acid-resistance with a mixed solution, but involves a greater electrical resistance. Before explaining an embodiment of this invention, comparison will be made in various characteristics between an Mo-Ta alloy film per se and other electrode interconnection film materials. In this connection reference should be invited to the following Table, noting that in relation to the contents of Mo and Ta in Table their decimal point et seq. are cancelled. Respective electrode interconnection films are formed at room temperature by virtue of a sputtering method. As evident from the Table, a Mo-Ta alloy film, after deposited at room temperature, reveals a smaller resistivity than those of Ti, Cr, β-Ta and MoSi₂ films and, for less than 84 atomic percent of Ta in particular, than an Mo film. The alloy film, when heat-treated after that deposition step, manifests a still lower resistivity. Furthermore, the alloy film also shows an excellent dry-etching workability as in the case of an MoSi₂ film and allows a ready formation of a taper. No better thermal oxidation film is obtained for the Mo, Ti and Cr film. The Mo-Ta alloy film shows an excellent thermal oxidation and, in addition, an excellent resistance to a mixture solution of H₂SO₄ and H₂O₂ which has extensively been used as a washing liquid. It has further been found that the Mo-Ta alloy film has a better compatibility with silicon due to its excellent ohmic contact with Si and its low reactivity with an SiO₂. Evaluation was made, by a rating of o (better), ▵ (somewhat better) and x (poor), for the dry etchability of a CF₄ system and for taper angle controllability by the dry etching of the CF₄ system. For a thermal oxidation film formation, evaluation was made as to whether or not an oxide film free from any pinholes was obtained at a temperature of about 400°C with a breakdown electric field of above 3 x 10⁶ V/cm and leakage current density of 1 x 10⁻⁸ A/cm². For the formation of an anodic oxidation film, evaluation was made as to whether or not a pinholeless oxide film was obtained at a temperature of above 400°C with a breakdown electric field of above 3 x 10⁶ V/cm and leakage current density of below 1 x 10⁻⁸ A/cm². For an ohmic contact with silicon, evaluation was made as to whether or not an interface is formed by a complete MoSi₂ of a better ohmic contact and, for a no-reactivity with the oxide film, evaluation was made as to whether or not a reaction occurred at a temperature of about 400°C. Fig. 6 shows a comparison in resistivity between an Mo-Ta alloy film formed as a single-layered film on a glass substrate by a sputtering method and a multi-layered film with an Mo-Ta alloy film formed on an underlying Mo film. When the composition ratio of Ta exceeds 84 atomic percent for the single-layered film, the resistivity increases abruptly. Even when the composition ratio of Ta is increased (to more than 84 atomic percent) for a multi-layered film, the resistivity is not increased. This is a marked difference upon comparison with the single-layered film. The film may be formed by the sputtering method, as well as by, for example, an electron beam evaporation method. Since the underlying metal film primarily determines the crystal structure of the overlying Mo-Ta alloy film, it is only necessary for the underlying metal film to have a thickness of above 10 nm (100 Å). As the body-centered cubic lattice type metal, use may be made of V, Cr, Fe, Nb, Mo and W whose lattice constant is similar to that of Mo and Ta, as well as an Mo-Ta alloy whose Ta composition ratio is within a range of 0 to 84 atomic percent. Figs. 7A and 7B show the results of the X-ray diffractions of a single-layered Mo-Ta alloy film (above 84% of Ta) and multi-layered Mo/Mo-Ta film (above 84% of Ta), respectively. From these it has been confirmed that the single-layered Mo-Ta alloy film with above 84% of Ta is of a tetragonal type whereas the multi-layered film with the Mo film as an underlying film is of a body-centered cubic type. Such a difference in their crystalline structures is responsible for a marked difference in the resistivities in Fig. 6. Fig. 1 is an equivalent circuit diagram of an active matrix type liquid crystal display device using an inverted staggered type TFT. Address lines 11 (11₁, 11₂, ..., 11 m ) and data lines 13 (13₁, 13₂, ..., 13 n ) are arranged as a matrix array on glass substrate 1 with TFT 15 (15₁₁, ..., 15 mn ) placed in a corresponding intersection. TFT 15pq (p=1, 2, ..., m; q=1, 2, ..., n) has its gate electrode 17pq connected to address line 11p, its source electrode 18pq to data line 13q and its drain electrode 19pq connected to liquid crystal cell 14pq via pixel electrode 21pq. Capacitor 23pq, though shown in Fig. 1, can be omitted. Gate electrode 17pq is formed, in reality, integral with address line 11p. Fig. 2 is an enlarged plan view showing one pixel area (21₂₂) in the substrate in Fig. 1. A liquid crystal display device is manufactured as follows. Reference is invited to Fig. 3. An Mo-Ta alloy film was deposited by sputtering on glass substrate 1 and the resultant structure was patterned by a PEP (photo-engraving process) to form gate electrode 17. Gate electrode 17 was formed of the same material as that of address line 11 (See Fig. 1) and formed, by the same process, integral with the address line. In order to prevent a possible step breakage on gate electrode 17 and on the address line at that step their edges were tapered. For this reason, a ready taper etching step was able to be performed using a resist and CF₄ + O₂. Gate electrode 17 of this embodiment was 200 nm in thickness and 30 µm in width, noting that the gate electrode has a thickness the same as that of the address line. Then 200 nm-thick Si₃N₄ film 31 was formed, as a gate insulating film, on the resultant structure. Then 300 nm-thick undoped a-Si film 33, 50 nm-thick n⁺ type a-Si film 35 and 50 nm-thick Mo film 37 were formed in that order. These three layers were left by etching at the thin-film transistor section and at the respective intersection of address line 11 and data line 13 on address line 11. What is important at this step was a process before gate insulating film 31 was deposited. The gate electrode was subjected by PEP to a patterning and a larger amount of organic (the left resist, for example,) and inorganic contaminants was present in the surface of the gate electrode. A washing step was carried out by immersing the glass substrate into a mixture solution of H₂SO₄ and H₂O₂ with the gate electrode formed on the glass substrate. The gate electrode of the Mo-Ta alloy film revealed an adequate corrosion- and etching-resistance to a washing liquid. Then, display electrode 21 for the respective pixel was formed by a 150 nm-thick ITO (indium tin oxide) film. Finally, the resultant structure was subjected to an Aℓ-film deposition and patterning to form data line 13 and continuous source electrode 41 and drain electrode 43. In this case a liquid crystal layer, if sandwiched between the active matrix substrate and opposite electrode substrate, provides a liquid crystal display device. If the washing step is inadequate, a faulty breakdown voltage occurs between the drain, source and gate electrode and thus an interlayer short-circuiting occurs, causing, for example, a line defect on an image display. Adequate washing was able to be done due to the chemical corrosion resistance. It was, therefore, evidenced possible to prevent occurrence of such a defect. Although Si₃N₄ film 31 has been explained as being deposited as a gate insulating film on gate electrode 17, it is helpful to form a thermal oxidation film on the surface of gate electrode 17 prior to the deposition of the Si₃N₄ film. In actual practice, after the gate electrode has been formed, 160 nm-thick oxide film was formed by a thermal oxidation process for one hour at 400°C in an oxygen atmosphere under atmospheric pressure. The thermal oxidation film had a breakdown electric field of above 5.2 x 10⁵ V/cm and specific dielectric constant of 23. Where subsequent to the formation of the thermal oxidation film the Si₃N₄ film is deposited to provide a gate insulating film, it is possible to effectively prevent such a defect resulting from the layer-to-layer short-circuiting. Furthermore, the second insulating film can be thinned, thus offering an advantage of lowering the threshold voltage of TFT's. Forming a thermal oxidation film on the whole gate interconnection area or intersected interconnection, not to mention that gate electrode area, prevents defects resulting from the interlayer short-circuiting at that intersection in particular. A good-quality oxide film can be formed by anodically oxidizing the gate electrode and the other surface. Figs. 4A and 4B show a variation in which the surface of a gate electrode is anodically oxidized, Fig. 4A being a cross-sectional view as taken along line A-A' in Fig. 2 and Fig. 4B being a cross-sectional view as taken along line B-B' in Fig. 2. Subsequent to the formation of address line 11 and gate electrode 17, anodic oxidation film 118 was formed on the surface of the resultant structure, noting that the anodic oxidation was conducted in 0.01 wt% citric acid solution according to this invention. Then 200 nm-thick SiO₂ film 132 was formed by a plasma enhanced CVD on the whole surface of the resultant structure. Then undoped a-Si film 33, n⁺ type a-Si film 35 and Mo film 37 were sequentially formed with their thicknesses the same as those shown in the previous embodiment. Display electrode 21, source electrode 41 and drain electrode 43 were formed in the same way. A thin-film transistor was formed with anodic oxidation film 118 and SiO₂ film 132 as a gate insulating film. In the respective intersection of address line 11 and data line 13, a multi-layered film of a-Si film 33, n⁺ type a-Si film 35 and Mo film 37 is formed on an insulating film of anodic oxidation film 118 and SiO₂ film 132 to provide an insulating interlayer. An embodiment of the driving circuit of a liquid crystal display device according to the invention will be described below with reference to Fig. 5. A gate electrode integral with the address line was formed, as a multi-layered film of 30 nm-thick Mo-Ta alloy film (80% of Ta) 217a as an underlying metal film and 170 nm-thick Mo-Ta alloy film (95% of Ta) 217b as an overlying metal film, on glass substrate 1. Subsequent to the formation of the gate electrode, washing was carried out in the same way as in the previous embodiment. 150 nm-thick SiO₂ film as a gate insulating film was deposited by the CVD method on the surface of the resultant structure. Then 300 nm-thick a-Si film (undoped) 33 and 50 nm-thick a-Si film of an n⁺ type were sequentially deposited on the surface of the resultant structure, thus forming an island pattern at the TFT area. Source electrode 41 and drain electrode 43 were formed as an Aℓ layer on the surface of the resultant structure, noting that source electrode 41 was formed integral with data line 13 as set forth above. Subsequent to the formation of the island-like a-Si film, ITO pixel electrode 21 was formed adjacent to that a-Si film and drain electrode 43 was electrically connected to pixel electrode 21. In this way a liquid crystal display device was fabricated which had a surface area of 19.2 cm x 25.6 cm, pixel pitch of 400 µm and address line of 30 µm in width. In this embodiment, address line 11 had a resistance of 12.8 KΩ. In this connection it is to be noted that an address line was formed by the other materials and it is found that, in these other materials, Ti, Cr, Mo, Ta and Mo-Ta alloy (60% of Ta) were 200.5 KΩ, 55.4 KΩ, 22.6 KΩ, 100.9 KΩ and 19.2 KΩ, respectively. It is, for example, possible to obtain an Mo-Ta alloy by a co-sputtering method with the Mo target and Ta target. It is also possible to obtain a similar alloy film through a thermal decomposition by organic gases containing an Mo and Ta. The circuit of the invention can not only make use of an Si film, such as an a-Si film, polycrystalline silicon film and single crystalline Si film but also of another semiconductor material film, such as a CdSe, Te, GaAs, GaP film.

Claims: A driving circuit of a liquid crystal display device, comprising: an insulator substrate (1); a plurality of address lines (11) and data lines (13) intersecting each other on said substrate formed with an insulation layer (31) therebetween, a plurality of thin-film transistors (15) each formed at an intersection of said address and data lines, each of the transistors having a gate electrode integral with an address line, a source electrode (41) integral with a data line, and a drain electrode (43); each of said thin-film transistors (15) including a semiconductor thin film (33) formed over said gate electrode with said insulating layer (31) serving as a gate insulating film; and a plurality of display electrodes (21) connected to the drain electrodes of the thin-film transistors; characterized in that the gate electrode integral with the address line is formed as a multi-layered structure including a first layer (217b) directly overlying a second layer (217a), said first layer (217b) being formed of molybdenum-tantalum alloy containing more than 84 atomic % of tantalum, said second layer (217a) having a thickness above 10 nm and being made of a metallic material having a body-centered cubic lattice structure and a lattice constant similar to that of molybdenum and tantalum. A driving circuit according to claim 1, wherein said metallic material of said second layer (217a) is selected from the group consisting of V, Cr, Fe, Nb, W, Mo, and a molybdenum-tantalum alloy containing 0 to 84 atomic % of tantalum. A driving circuit according to claim 1 or 2, wherein said gate insulating film comprises an anodic oxidation film or thermal oxidation film. A driving circuit according to any one of the preceding claims, wherein said drain and source electrodes (41, 43) are formed of aluminium

Inventors: DOHJO MASAYUKI C O PATENT DIVI, IKEDA MITSUSHI C O PATENT DIVI, OANA YASUHISA C O PATENT DIVIS, DOHJO, MASAYUKI C/O PATENT DIVISION, IKEDA, MITSUSHI C/O PATENT DIVISION, OANA, YASUHISA C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1986
Main classification: H01L23
IPC codes: H01L27, H01L23