CONTROL CIRCUIT OF THE POWER TRANSISTOR IN A DC/AC CONVERTER

Abstract: The control circuit comprises a transformer adapted to send to the base of the power transistor a current which is proportional to the current flowing through the collector. The circuit further comprises a first transistor (TS1) fit to control the power transistor (TS5) by means of a second and a third transistor (TS2 and TS3). The power transistor's (TS5) collector is connected to the collector of the third transistor by means of a resistance (R7), having further the base connected to a negative supply source (-Vc) by means of a first diode (DD6) and a field effect transistor (TS4). The gate electrode of said transistor is connected to the first transistor's (TS1) collector by means of a second diode (DD1) and to the power transistor's collector by means of a third diode (DD2).

Description: CONTROL CIRCUIT OF THE POWER TRANSISTOR IN A DC/AC CONVERTER DESCRIPTION The present invention refers to a control circuit of a power transistor, particularly suitable for use in the direct current / alternate current converters (DC/AC), i.e. a circuit adapted to draw from a DC source (for example, a battery) an alternate current capable of feeding a load (for example, in case of a black-out in the electric power distribution line). The conversion performed by such circuits requires a chopping ir, said direct current by means of the power transistor which, within a determined period T for the determining of the converter's working frequency, lies in conduction state for a time interval To„n and is kep r t in a cut-off state for a time interval T -- (where T + T = T). In the specific technique the interval T Q with respect to the time interval T is referred to as "conduction time". The specific technique refers even to a "conduction angle" when the time intervals mentioned above are regarded as angular displacements. In the direct current/direct current converters (DC/DC) said power transistor is normally controlled in a "proportional way", i.e. the current supplied to the transistur's base has a value proportional to the current which flows through the collector. Such a control in the DC/DC converters is more convenient either for the costs of the implementation means or the easiness of said means. Said control function in DC/AC converters requires on the contrary the overcoming of some technical problems, such as: counterpolarization of the power transistor's Base during the time interval T --; working function with high conduction angles (about 80%-90%); working function with high switching frequencies. Taking into consideration the counterpolarization it is useful to note that the use of said converters requires more power transistors - connected for example in a "bridge" configuration - which work in pairs in ON/OFF-state. The pair of transistors in OFF-state is in fact subject to the flowing of an inverse current which, when the other pair of transistors is in ON-state, may cause a damage to all the other transistors, as hereafter better specified. The proportional control function used in the DC/AC converters requires the identification of technical solutions to prevent the flowing of said inverse current. As regards the conduction angle mentioned above, it it necessary to point out that the DC/AC converters cannot accept conduction angles of 50% - 60%, which are normally used in the DC/DC converters. The current efficiency of a converter depends on the conduction angle: the output current presents en average value eq^ual to Ton/T.VB and a Ton/T ratio of 50% causes therefore a current loss of 50% in comparison with the current available when the ratio above reaches a value of 100%. It is further to notice that the working with conduction angles of 50% requires the use of switching elements so shaped as to be crossed by a current of double rate, but causing however an i crease in the switching losses and a decrease in the real efficiency. The conduction angle is however limited by the transformer which is required in order to realize the proportional control above. Said transformer requires however the fulfillment of the ratio V. 1.Ton = V«Z.Tof-f-, where V,1 and V„ c represents a positive and a negative current respectively, having a value coincident with the magnetizing current, respectively demagnetizing current, of said transformer's core. The maximum rate that the current V„ can reach is defined ly the inverse current applied to the transistor and therefore the time interval T /T cannot reach values higher than 50% / 60% if suitable means are not used to p even the damage of the transistor when a high demagnetizing current is registered. As regards the switching frequency (1/T) it is to note that said parameter is limited by the "storage time", i.e. the time used by the power transistor to pass to a cut-cff state once the control signal has been disactivated. It is necessary v to remember that during 3 the time interval Ton the transistor can store electric charges in a quantity proportional to the current intensity applied to its base and therefore the passage of the transistor to the OFF-state takes place - after the disactivation of the control signal - with a delay which in the specific technique is called "storage time", that is the time used by the transistor for the "elimination" of the charges previously accumulated. As the converter can work at a frequency the higher it is the lower the storage time is, it results that the operation with high frequencies requires suitable means to limit the number of the electric charges stored and/or suitable means to speed up the elimination mentioned above. Purpose of the present invention is the realisation of a control circuit adapted to solve the technical problems mentioned above by using circuit arrangements particularly simple and cheap. The present invention relates therefore to a control circuit of the power transistor in a direct current / alternate current transformer comprising a transformer suitable to send to the base of said power transistor a current proportional to the current which flows through the collector. The circuit also comprises a first transistor adapted to control the power transistor by means of a second and a third transistor. The power transistor has the collector connected to the collector of the third transistor by means of a resistance, having further the base connected to a negative power source by means of a first diode and of a field effect transistor. The gate electrode of said transistor is connected to the collector of the first transistor by means of a second diode and to the collector of the power transistor by means of a third diode. Further characteristics of the invention can be taken from the description hereafter which refers to a non-limiting example shown in the enclosed figures, whereas: figure 1 shows the basic diagram of a DC/AC converter of a well-known type; figure 2 shows the control circuit of one of the T transistor of figure 1, realised according to the invention. The basic diagram of a DC/AC converter is shown in figure 1 ana it is mainly constituted by four transistors connected each to the other in a bridge configuration. The pair of transistor T, and T, has to generate the positive half-period of the output signal while the pair of transistor T and T 3 has to generate the negative half-period. In particular the transistors T, and T, receive at their input a signal modulated according to the PW law, while the transistors T 2 and T« receive at their input a frequency signal at 50 Hz. To each transistor a corresponding diode D is parallel connected, , having the function to enable the energy recovery in the time interval during which the pair of transistor, to which the diodes are associated, are in cut-off state. When, for example, during the generation of the negative half-period of the signal V , which allows the energy recovery, the transistor T, is in cut-off state and through the diode D, a current is flowing to the battery which polarizes the transistor's junctions, in such a way that an inverse current can flow through the transistor T,. When the conduction of T 2 is registered, the inverse current causes a damage to T« and subsequently to T,. This trouble does not exist when said inverse current is prevented from flowing, as better specified in figure 2, where the control circuit of one of the transistors mentioned above is illustrated, for example T,, which in this figure corresponds to TSg. In figure 2, the control signal, modulated for example according to the PWM law, is applied to the base of a transistor TS,, which controls said power transistor TS r by means of a second and a third transistor TS 2 and TS-. The base of transistor TS- is connected to a negative power source by means of a field effect transistor (FET) TS.. The resistances R, and R 2 should polarize the base of said transistor TS 2 , the resistance R- should limit the current flowing through TS , while the resistance R. polarizes the base of TS,. Two further resistances R 5 and R g are further provided in order to protect the base of transistors TS 3 and TS 5 respectively. The capacitors C, and C 2 should provide a filter function for the current which should be chopped by The working of said circuit is illustrated hereafter, with a p r articular attention to the time intervals To_n, and Tof-f- of the control signal as well as to the transit time among the time intervals. During the time interval T -^ the transistors TS,, TS J TS 3 and TS 5 are in cut-off state, while the FET TS. is in conduction state, providing in this way the connection of the base of TS, and - by means of the diode DD β - the base of TS 5 to a negative power source. In this way, during the time interval T --, the transistor TS 5 as well as the transistor driver TS- are counterpolarized and no troubles should therefore arise in connection with the flowing of said inverse current. When the control signal of transistor TS, becomes active, a transition between the time interval of T OT-T~ and To_n, in TS C 5 is registered. Said signal causes in fact the saturation of TS, and therefore the conduction of the transistors TS 2 and TS . The collector of transistor TS- is connected to the collector of transistor TS 5 by means of a resistance R 7 , through which a high intensity current flows and reaches the base of TS 5 causing its saturation in a very short time. The emitter current impulse crosses the winding N, of the transformer TR', which provides the proportional control, and flows to the winding N 2 according to the ratio ,/N 2 : said current flows therefore to the base of TS g through a diode DD 5 and the transistor TS-,. The current Ic which flows through the collector of TS g causes the sending to the base of TS 5 of a further current rate, which is subject to the ratio N , /N 2 « During the time interval T the transistors TS,, TS Λ , TS, and TSg are therefore in a conduction state, while the transistor TS. is in cut-off state; a diode DD- is connected between the emitter of TS 2 and the collector of TS, and said diode is directly polarized and allows therefore the flowing only of the current necessary to keep the transistor TS 3 in saturation-state. Said transistor is therefore crossed by a current proportional to the current Ic, having a value Ic.N,/N 2 , where N,/N 2 represents the minimum guaranteed gain. It is necessary to remember that the transistors' gain depends on the current which flows through them and that said gain represents a minimum value guaranteed by the manufacturers. In practice most transistors have a gain higher than the minimum guaranteed and it is possible to reach higher values when there are low current values. In brief, as the current necessary to keep a transistor in saturation-state depends on the gain of said transistor, if the transistor works with a gain as high as possible it is possible to use a limited control current and to. limit therefore the quantity of the electric charges stored in the base. In practice, said result is reached if the transistor receives a current which is proportional to its effective gain. According to the invention, the fulfillment of the condition mentioned above is guaranteed by said resistance R 7 which in case of a possible oversaturation of TSr sends part of the base's current to the collector and forces the transistor to operate with its effective gain, by reducing therefore the control current and consequently the quantity of the electric charges stored in the base. Once the control signal of the transistor TS, is disactivated, said transistor is in cut-off state and the FET TS. passes therefore from the cut-off state to the conduction-state; this fact causes the flowing through the base cf TS, of a negative current and determines its cut-off state. The base current of TSr becomes negative. During the time interval in which the transistor TS, is in cut-off state and TSr in conduction-state, part of the current coming from N 2 flows to the collector of TSr (through the diode DD 5 and R 7 ) and part is recovered to the condenser C, by means of a diode DD.. The gate of FET TS. is connected to the collector of TSς by means of a diode DD 2 : at the end of the storage time, when the transistor TSr starts its unsaturation, its collector's current suddendly rises, causing the increase of the current at the gate of TS.. The control voltage applied to FET rises with the same gradient of the current in the collector of TSr, by causing the flowing of a negative current during the unsaturation and by eliminating therefore the remaining electric charges from the base of TSr, in a very short time, during the fall time TF which follows the storage time before cited. When the transistor TSr is in cut-off state, the diode DDr - which is counterpolarized - becomes an open circuit and isolates in this way the transistors TS, and TSr from the other part of the circuit, allowing the demagnetizing of the core of transformer TR' at high voltage V 2 . The diode DDr releases therefore the circuit from the inverse current which can be accepted by the transistors TS, and TSr, allowing the working with conduction angles at 80% - 90%. According to what above stated, it is evident that the circuit realised according to the invention fulfills the specific requirements , as: transistors TS3 and TS5 are counterpolarized during the time interval T - f , by means of FET TS. which connects the relative bases to a negative power source; it is possible to work with conduction angles at 80%-90%, by means of the diode DD 5 which isolates the winding N„ from the other part of the circuit, enabling in this way the demagnetizing of TR' at very high voltages; It is possible to operate with high switchirg frequencies by means of the resistance R , through which an initial current impulse flows in order to cause the immediate saturation of TSr, obtaining in this way low switching losses. Said resistance further performs a drainage function during the time interval T- avoiding therefore the oversaturation of said transistor, which is operated with its effective gain. In this way it is possible to reduce the control current value and consequently the quantity of the electric charges stored, by reducing therefore even the storage time. The diode DD 2 further controls TS. in such a way as to adjust the flowing of the negative current to the base of TSr by rapidly eliminating the electric charges stored in the base It allows - once the storage function is terminated - the reduction of the fall time (TF) as well as of the losses during the switching off phase.

Claims: CLAIMS 1. The control circuit for a power transistor in a DC/AC converter, comprising a transformer adapted to send to the base of said power transistor a current proportional to the current which flows through the collector, characterized in that it comprises a first transistor (TS,) adapted to control the power transistor (TSg) by means of a second and a third transistor (TS, L. and TS 3,), in that the power transistor's (TSr) collector is connected to the collector of the third transistor (TS,) by means of a resistance (R 7 ) and its base is connected to a negative power source (-Vc) by means of a first diode (DDg) and a field effect transistor(TS.) , and characterized in that the transistor TS. has the gate electrode connected to the collector of the first transistor (TS,), by means of a second diode (DD,), and to the power transistor's collector by means of a third diode (DD 2 ). 2. Circuit as claimed under claim 1 characterized in that the winding of the transformer (TR'), crossed by said proportional current, is connected to the base of the power transistor (TSr), by means of a fourth diode (DDr) and said third transistor (TS,), and further connected to the positive armature of a condenser (C,) by means of a fifth diode (DD 4 » 3. Circuit as claimed under claim 1 characterized in that the emitter of the second transistor (TS 2 ) is connected to the collector of the third transistor (TS,) by means of a sixth diode (DD,). 4. Circuit according to the above description and to the attached drawings as well as any single or combined parts of it.

Inventors: LENTINI SALVATORE, PATTI GIUSEPPE, LENTINI, SALVATORE, PATTI, GIUSEPPE
Applicants: ITALTEL SPA, ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI S.P.A.
Application year: 1986
Main classification: H02M7
IPC codes: H02K16, H02M7, H03K17