PROGRAMMABLE DATA-ROUTING MULTIPLEXER

Abstract: A multiplexer for use in a digital subscriber controller having a number of analog ports and digital ports which can be programmed via an external microprocessor to establish time-division multiplexed bidirectional data paths between three subscriber-selected ports designated as "sources" and three subscriber-selected ports designated as "destinations". Among the ports is a line-interface port having two kilobit-per­ second channels on which analog/digital data is received from and transmitted onto the network transmission line. Among the digital ports is a three-channel serial port and a two-channel microprocessor interface port. An analog port is also provided at which a variety of audio transducers may be connected. The data-routing multiplexer consists of three sec­ tions, each comprising a plurality of registers connected to a single internal bus on which time-division-multiplexed signals are generated and received by particular subscriber-­ selected registers, each register within a section serving as either a generator or a receiver for the internal bus for a part­ icular digital channel. An extension of the internal bus is con­ nected to the analog port. A set of three control registers stores the subscriber-selected sources and destinations. Con­ trol signals are generated therefrom which affect the sub­ scriber-selected interconnection of registers within the data-­ routing multiplexer with the internal bus. The multiplexer fac­ ilitates maintenance and testing of the digital subscriber con­ troller by permitting a loopback path to be established for a device connected to a port by simply designating a path hav­ ing that port as both its source and distination.

Description: The present invention relates to a programmable data-routing multiplexer. A related invention is described in our co-pending European Patent Application No. 86305537 which claims priority of US Patent Application 759622. of 26.07.85 (issued as 4,635,255). Telephonic subscriber lines today are increasingly employing all-digital networks for both voice and data transmission so as to provide the utmost in signal integrity and flexibility inherent in digital networks. Further benefits accorded to the subscriber include the more efficient provision of existing and new services, such as telephony, packet and circuit-switched data, telemetry, electronic mail, alarm signalling, telex, facsimile, and banking transactions over the same medium, thereby greatly reducing equipment and space requirements. Additionally, benefits accrue to the telephone company in terms of increased revenue derived from the provision of these new services, and simplified management resulting from all services operating on a single (digital) network. To provide an interface to such all-digital voice/data networks on the subscriber's premises, the prior art employs discrete and/or expensive custom circuitry which lacks the flexibility to meet changing subscriber needs. Furthermore, such circuitry encourages proliferation of incompatible implementations which vary in physical, electrical and line protocol characteristics. Additionally, the prior art interfaces occupy large amounts of space, have high power consumption thereby generating considerable heat which requires cooling apparatus and lack the reliability of monolithic integrated circuitry. The article "Controller chips pair up in S interface for ISDN systems" in "Electronic Design" dated 13 December 1984 (Vol.32 No. 25 pages 157 to 170) discloses the arrangement of two CMOS integrated circuit devices for providing "S" interfaces for ISDN links. The programmable data-routing multiplexer to be described allows the subscriber ready-access to the various data-handling facilities provided by all-digital voice/data telecommunication networks. The multiplexer is intended for use in a subscriber controller which can be programmed by the subscriber via an external 8-bit microprocessor to perform a number of functions by giving simultaneous access to two 64-kilo-bit per second (kbs) voice/data channels and a 16-kbs data control channel. Voice-band signals are digitized at the subscriber's terminal and transmitted over one of the 64-kbs channels. The multiplexer provides a programmable interface within a controller containing six other functional units so that a subscriber may connect a variety of audio transducers at an analog port of the controller, connect a digital transducer at a time-multiplexed digital port, and connect a subscriber-programmable microprocessor at an external bus terminal of the controller. Through programming of the microprocessor, the subscriber can cause the multiplexer to establish bidirectional data flow between any of the ports and the line interface to the telecommunication network. Among the functional units within the controller which can be interconnected via the multiplexer to be described are a line interface unit which connects the controller via a pair of isolation transformers to the network transmission line; a data link controller which receives data channel information from the line interface unit and transmits subscriber-generated data channel information to the line interface unit for subsequent transmission over the network; a main audio processor which provides analog-to-digital and digital-to-analog conversion of the audio signals received at, and transmitted to, respectively, the analog port of the controller; a microprocessor interface which permits subscriber control of the function and data paths within the controller; and a serial data port of the multiplexer. The multiplexer to be described as commanded by the subscriber via the external microprocessor, establishes data paths between several possible source and destinations including the line interface unit, the main audio processor, the microprocessor interface and the serial port. Furthermore, the subscriber-programmable multiplexer controls the time-multiplexing of the two voice/data serial channels. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a functional block diagram of a digital subscriber controller (DSC) employing the programmable multiplexer of the instant invention; Fig. 2 illustrates the logical data bus structure of a DSC which can be configured by the multiplexer of the present invention by programming from an external microprocessor; Fig. 3 illustrates the physical data bus structure internal to a DSC which can be configured by the multiplexer of the present invention by programming from an external microprocessor; Fig. 4 is a block diagram of the programmable multiplexer 170 of the instant invention; Figs. 5A, 5B and 5C comprise is a block diagram of the programmable data routing multiplexer 840 portion of the programmable multiplexer of the instant invention; and Figs. 6A and 6B comprise a logic diagram of the MCR1-3 portion of the programmable data-routing multiplexer of the instant invention. DESCRIPTION OF THE PREFERRED EMBODIMENT A. DSC Architecture The programmable multiplexer of the present invention is shown in an exemplary application within a digital subscriber controller (DSC) 34 consisting of seven functional blocks, as illustrated in Fig. 1. The DSC provides digital subscriber access to a telephone network. The DSC is compatible with the CCITT I-series recommendations at reference points "S" and "T". Accordingly, the user of the DSC according to the present invention may utilize terminal equipment (TE) which conforms to international standards. The DSC 34 is the subject of a related copending application U.S. Serial No. 759,622, filed July 26, 1985, on behalf of Alan T. Clark, Hadi Ibrahim and Arthur F. Lange, entitled "Digital Suscriber Controller", and assigned to the assignee of the instant application. A detailed description of the DSC 34 of Fig. 1, other than the programmable data-routing of the instant invention multiplexer shown thereon as MUX 170 is contained in the above-referenced copending application. The related, copending application is hereby incorporated by reference. With reference to Fig. 1, DSC 34 provides a 192 kbs full-duplex digital path for bit-streams received via an isolation transformer (not shown) on a four-wire "S" interface at terminals LIN1 and LIN2, and transmitted on the four-wire interface from terminals LOUT1 and LOUT2. The DSC separates the received bit-stream into B1 and B2 channels (each 64 kbs), and D channel (16 kbs). The B channels are routed to different ones of the functional blocks illustrated in Fig. 1 under user control via the multiplexer 170 of the present invention. The D-channel is partially processed at the Level 2 in the DSC 34 and passed via a microprocessor interface (MPI) 100 to a programmable microprocessor (not shown) for additional processing. The DSC 34 supports both of the two major CCITT recommendations, "point-to-point" and "point-to-multipoint" subscriber configurations, to meet both PBX and public applications. With reference to Fig. 1, the DSC 34 includes a line interface unit (LIU) 110, connected to the terminals LIN1 and LIN2, which contains a receiver section 120 and a transmitter section 130. The receiver section 120 consists of a receiver filter, a digital phase-lock loop (DPLL) for clock recovery, two slicers for detecting high marks and low marks of the incoming bit-stream frames, and a frame recovery circuit for frame synchronization. Receiver 120 converts the incoming pseudo-ternary encoded bit stream into binary before conducting it to the other blocks of the DSC 34, illustrated in Fig. 1, via a bus 140. The receiver 110 also performs D-channel access protocol to resolve potential contention when the DSC 34 is operating in the "point-to-multipoint" configuration. The transmitter section 130 consists of a binary-to-pseudo-ternary encoder and a line driver which receives signals on the bus 140 and causes an outgoing bit stream to be generated therefrom at the LOUT1 and LOUT2 terminals of the DSC 34. This outgoing bit stream is as specified in the CCITT recommendations for the "S" interface. The LIU 110 conforms to the CCITT recommendations for level 1 activation and deactivation on the "S" interface. This is achieved by transmitting, and decoding, the standard CCITT "Info" signals. The LIU 110 is also responsive to a signal on a hook switch (HSW) terminal of the DSC 34. The HSW terminal receives a signal indicative of the off-hook or on-hook condition of the handset. The DSC 34 also includes a data link controller (DLC) 150 connected to the bus 140 which partially processes the 16-kbs D-channel received via the LIU 110. The partial processing of the layer 2 of the protocol includes flag detection and generation, zero deletion and insertion, frame check sequency processing for error detection, and some addressing capability. The external microprocessor 38 initializes the DLC 150 and performs higher level protocol processing. When the DSC 34 is in the receive mode, D-channel data is conducted from the LIU 110 to the DSC 150, via bus 140, and then to the microprocessor interface (MPI) 100 for transmission from a set of eight data terminals (D0, D1, D2, D3, D4, D5, D6, and D7) of the DSC 34 to the external microprocessor. When the DSC is in the transmit mode, D-channel data is conducted from MPI 100 to the LIU 110 via DLC 150 for transmission on the D-channel over the "S" interface. A main audio processor (MAP) 160 contained within the DSC 34 performs digital-to-analog (D/A) conversion within a D/A section 162 and analog-to-digital (A/D) conversion within an A/D section 164 and digital filtering of the signals present in the DLC 34 in a receive/transmit filters section 166. Analog audio signals can be applied to MAP portion of the DSC 34 at earphone terminals (EAR1 and EAR2), two general analog inputs (AINA, AINB, AGND) and analog voice signals are generated by the MAP portion at loudspeaker terminals (LS1 and LS2). The MAP 160 transmits and receives digital signals on the bus 140 carrying digital representations of audio signals received at the EAR1, EAR2, AINA, or AINB terminal or to be generated at the LSI and LS2 terminals, respectively. The data-routing multiplexer (MUX) 170 of the instant invention is externally programmable via the external microprocessor and, in response, controls the multiplexed bit-streams on the B1 and B2 channels which are received and transmitted to external peripheral devices from the DSC 34 at a serial-B input (SBIN) terminal of the DSC 34 and a serial-B output (SBOUT) terminal of the DSC 34, respectively. The MUX 170 can be programmed to establish a variety of different signal paths via the bus 140 having source and destinations, including: the SBIN terminals, the SBOUT terminal, the MPI 100, the LIU 110, and the MAP 160. The MUX 170 of Fig. 1 selectively routes the 64 kbs B1 and B2 channels among the MPI 100, the LIU 110, and the MAP 160, with internal logical channels designated thereon as Ba (for the MAP), Bb and Bc (for the MPI), Bd, Be and Bf (for the B-serial port), and B1 and B2 (for the LIU). The D-channel data is routed to the DLC 150 directly from the LIU 110. B. DSC Programmable Internal Bus Structure The MUX 170 of the present invention contains three multiplexer control registers (MCR1, MCR2, and MCR3), which can be programmed via the MPI 100 to direct data flow along subscriber-selected bidirectional data paths shown functionally in Fig. 1 as bus 140. B.1 Logical Bus Structure The MUX 170 can establish those bidirectional paths between the eight MUX logical ports B1, B2, Ba, Bb, Bc, Bd, Be, and Bf, shown in Fig. 2, as controlled by the contents of MCR1, MCR2, and MCR3. These MCRs are externally programmed to connect any two of the eight logical B-channel ports together by writing an appropriate channel code into the corresponding MCR. Each of the MCR1, MCR2, and MCR3 receives a pair of four-bit channel codes, which, in accordance with Table I, below, specifies the logical channel interconnections. For instance, the assignment to MCR1 of the channel codes 0001 and 0100 would establish a bidirectional channel connection of B1 and Bb. A loopback connection can be established by assigning the same pair of channel codes to a particular MCR. For instance, to effect a test of the MAP 160 portion of the DSC 34 by way of the analog output (EAR1 or EAR2) and the analog input (AINA or AINB) an assignment to MCR3 of the channel codes 0011 and 0011 would establish a loopback connection by MUX 170. MCR1, MCR2, and MCR3 Channel Codes Code Channel 0000 No connection 0001 B1 (LIU) 0010 B2 (LIU) 0011 Ba (MAP) 0100 Bb (MPI) 0101 Bc (MPI) 0110 Bd (Serial B Port Channel 1) 0111 Be (Serial B Port Channel 2) 1000 Bf (Serial B Port Channel 3) B.2 Internal Physical Bus Structure The bus structure internal to the DSC 34, shown functionally as bus 140 on Fig. 1 is illustrated in Fig. 3. Shown thereon are the B-channel bidirectional data paths B1 and B2, Ba, Bb and Bc, Bd, Be and Bf referred to in section B.1, above, designated 200, 202, 204 and 206, respectively, on Fig. 3. In addition, shown on Fig. 3 are three control busses 208, 210 and 212 which interconnect ports DA 7-o, DB 7-o and MP1STRT 6-o , respectively of the MPI 100 with the ports DA 7-o , DB 7-o and MP1STRT 6-o of the LIU 110, the DLC 150, the receive/transmit filters 166 of MAP 160, and the MUX 170. The contents of the MCR1, MCR2, and MCR3 registers determines the particular interconnection implemented on data busses 200, 202, 204 and 206, as described in Section B.1, above, in accordance with Table I. The manner in which the subscriber programs the MCR1, MCR2, and MCR3 registers, as well as the other user-accessible registers within the DSC 34 is described in Section C, below. As shown in Fig. 3, an analog-to-digital (A/D) 162 section of MAP 160 is connected to the receive/transmit filters 166 section of MAP 160 by a bus 214, and a digital-to-analog (D/A) 164 section to the filters 166 by a bus 216. A D-channel bidirectional data path 218 interconnects LIU 110 and DLC 150 and a D-channel bidirectional data path 220 interconnects DLC 150 and MPI 100. C. The Microprocessor Interface The DSC 34 includes a number of programmable registers and filters which can be accessed via the microprocessor interface (MPI) 100. A detailed description of the MPI 100 is contained in the related, co-pending application entitled "Digital Subscriber Controller" referred to above, and is hereby incorporated by reference. D. The Programmable Data-Routing Multiplexer With reference to Fig. 2, the MUX 170 of the instant invention serves as a junction for the eight DSC 34 logical channels B1, B2, Ba, Bc, Bd, Be, and Bf shown thereon. Of these, Bd, Be and Bf form the serial port of the DSC 34 and are integral with the MUX 170. The subscriber can, as will be described below, cause the MUX 170 to route the information on any selected three of these logical channels, the "sources", to any other selected three logical channels, the "destinations". The channels B1 and B2 are separated within the receiver 120 of the LIU 110 portion of the DSC 34 and received therefrom via bus 200 (Fig. 3) by MUX 170. Channels B1 and B2 are recombined by time-multiplexing within the transmitter 130 of the LIU 110 portion of the DSC 34 after reception via bus 200 from MUX 170. MUX 170 performs time-multiplexing and demultiplexing of the Bd, Be and Bf channels which form the serial port of the DSC 34. The Ba channel is conducted to the MAP 160 portion of the DSC 34 and the Bb and Bc channels are conducted to the MPI 100 portion of the DSC 34. The programming of the MUX 170 is performed within the MPI 100 portion of the DSC 34 via the DA 7-o 208 and DB 7-o 210 control busses. The architecture internal to the MUX 170 of the instant invention is illustrated in the block diagram of Fig. 4. As shown, the MUX 170 includes six major portions: a register address decode portion 810 receiving the multiplexer address signals MP1STRT 6-o via bus 212 (Fig. 3) as well as multiplexer read and write MP2READ, MP2WRITE signals generated by MPI 100. Register address decode portion 820 generates read and write signals therefrom for the three multiplexer control registers (MCR1, MCR2 and MCR3). These signals are conducted from address decode 810 via six signal lines collectively denoted 812 to the portion of MUX 170 denoted 820 containing the multiplexer control registers MCR1-3, where they are used to read and write to MCR1-3, as will be described below. The MCR1-3 also receive data control signals on the DB 7-o bus 210 from the MPI 100 and the resulting sense and data control signals are conducted via a set of seven signal lines, collectively denoted as 822 and 824, respectively, to a data routing multiplexer portion 840 of MUX 170, where they are used to establish the data paths selected by the subscriber via the MPI 100 as will be explained below, in connection with the internal structure of the data routing multiplexer portion 840. The data routing multiplexer 840 receives the data signals on time-division multiplexed B1 and B2 channels from LIU 110 via signal line 200. The data signals on the Bb and Bc channels are connected to the data routing multiplexer 840 from MPI 100 via the bidirectional DA 7-o bus 208, as will be explained below, and the time-multiplexed serial data port 206 integral to the MUX 170 is connected to the data multiplexer 840 via a serial I/O controller 850 and two signal lines 852 and 854 leading from serial I/O controller 860 to data multiplexer 840. The LU1Tbf-e timing signals generated by the LIU 110 are conducted to the data routing multiplexer 840 and serial I/O controller 850 portions of MUX 170 via a set of three signal lines collectively denoted 856. MX1Tbe-f signals generated within serial I/O controller 850 are conducted to MUX 170 via a set of three signal lines collectively denoted 858. Data routing multiplexer 840 also receives Read Bb (RDBB), Write Bb (WRBB), Read Bc (RDBC) and Write Bc (WRBC) signals generated by the MPI 100. A read/write buffer portion 860 of MUX 170 receives Bb and Bc time-multiplexed data signals on the DA 7-o bus 208 from the MPI 100 which are conducted via a set of eight signal lines, denoted collectively as 862 to the data multiplexer portion of MUX 170, where they are used to establish the data paths selected by the subscriber via MPI 100 as will be explained below, in connection with the internal structure of the data routing multiplexer 840. Read/write buffer 860 receives the Read Bb (RDBB), Write Bb (WRBB), Read Bc (RDBC) and Write Bc (WRBC) signals generated by the MPI 100. The construction and design of all the elements of MUX 170 shown in Fig. 4, other than the data routing multiplexer portion 840, is conventional and well known to those skilled in the art. The architecture internal to the data routing multiplexer 840 of the present invention shown, respectively, in Figs. 5A, 5B and 5C consists of the three major sections generally denoted 841, 842 and 843 thereon. The portion of the data routing multiplexer 840 denoted 841 comprises the MPI 100 interface portion consisting of channels Bb and Bc. The portion of the data routing multiplexer 840 denoted 842 comprises the integral serial port interface of the MUX 170 consisting of channels Bd, Be and Bf, and the portion denoted 843 comprises the LIU 110 interface portion consisting of channels B1 and B2. Those signal lines shown entering or leaving data routing multiplexer 840 vertically connect only to the portion 841, 842 or 843 shown, whereas the signal lines 822, 824 and 204 shown entering or leaving block 840 horizontally connect to all portions 841, 842 and 843, thereof. As shown in Fig. 5A, the MPI interface 841 portion includes four eight-bit registers 900, 902, 904 and 906 which are connected in parallel via eight signal lines collectively denoted 908 which connect in a parallel manner to the eight bidirectional signal lines 862 (Fig. 4), which conduct signals on the DA 7-o bus 208 via the read/write buffer 860. The eight write terminals (inputs) of registers 900 and 902 and the eight read terminals (ouputs) of registers 904 and 906 are interconnected in this parallel manner. The eight read terminals (outputs) of registers 900 and 902 are connected in parallel to the write terminals (inputs) of registers 904 and 906, respectively, by eight signal lines collectively denoted 910 and 912, respectively. The eight signal lines 910 and 912 each connect in a parallel manner to the eight bidirectional signal lines of bus 204. Registers 900 and 902 receive the MX2SEBB and MX2SEBC sense signals, respectively, generated by multiplexer control registers MCR1-3 820 and conducted to the data routing multiplexer 840 via signal lines 822. By appropriate time-division multiplexing performed within MCR1-3 block 820, the parallel eight bits of the Bb, or Bc, channel signal received on the DA 7-o bus 208 from MPI 100 via read/write buffer 860 and bus 862, which has previously been written either to eight-bit register 900 or register 902, respectively, will be placed onto the eight-bit wide bus 204 via signal lines 910 or 912, respectively, for conveyance on that portion of bus 204 connected to the Ba channel of MAP 160 directly connected thereto. This eight-bit contents will also be made available to any of the channels Ba, Bc, Bd, Be, Bf, B1 or B2 which can be connected to the portion of the bus 204 shown in Fig. 7 as determined by the contents of MCR1-MCR3 820 as programmed by the subscriber in accordance with Table I above, as will be described hereinafter. The parallel eight bits of the Bb, or Bc, channel signal received on the DA 7-o bus 208 from MPI 100 via read/write buffer 860 and bus 862, will be written to register 900, register 902, respectively, upon application of the WRBB signal, WPBC signal, respectively, and upon application at a clock terminal 900 and 902 of a phase one (PH1) synchronizing clock generated by a master clock (not shown) within DSC 34. In a similar manner, the eight-bit contents of registers 904 and 906 can be placed onto the DA 7-o bus 208 via bus 862 and buffer 860 for conveyance to MPI 100 and their contents may be written from the eight-bit wide bus 204, under control of the RDBB or RDBC signals, respectively, and the MX2DEBB or MX2DEBC data enable signals, respectively. By subscriber-programming of MCR1-MCR3 820 in accordance with Table I, above, the MPI interface 841 portion of data routing multiplexer 840 can establish bidirectional data paths including the Bb and Bc channels between the MPI 100 and the various other elements of the DSC 34 described in connection with Fig. 3, above. The serial port interface 842 portion (Fig. 5B) of data routing multiplexer 840 includes two sets of three eight-bit registers 914, 916 and 918; and 920, 922 and 924, each set of which is interconnected in parallel via eight signal lines collectively denoted 926 and 928, respectively, in Fig. 5B. The write terminals (inputs) to registers 914, 916 and 918 are interconnected in this parallel manner and connected in parallel to the eight output terminals of a serial-to-parallel register 930 via eight signal lines collectively denoted 932. The read terminals (outputs) of registers 920, 922 and 924 are likewise connected in parallel to each other as well as the eight input terminals of a parallel-to-serial register 934 via eight signal lines collectively denoted 936. The eight read terminals (outputs) of registers 914, 916 and 918 are connected in parallel to the eight write terminals (inputs) of registers 920, 922 and 924, respectively, by eight signal lines collectively denoted 938, 940 and 942, respectively. The eight signal lines 928, 940 and 942 each connect in a parallel manner to the eight bidirectional signal lines of bus 204. Serial-to-parallel register 930 receives at an input terminal the incoming data on serial channels Bd, Be and Bf applied at the serial port 206 of MUX 170 and conducted therefrom via signal line 852 from serial I/O controller 850 which is connected to serial port 206. A synchronizing clock signal generated by LIU (LU1SCLKN) portion 110 of DSC 34 at the simultaneous application of a PH2 clock signal are applied to register 930 to provide synchronization of the serial signals applied to the input of register 930 with the generation of the eight parallel signals at the outputs of register 930 subsequently conducted via signal lines 932 to registers 914, 916 and 918. Parallel-to-serial register 934 receives at eight parallel inputs signals on signal lines 936 from registers 920, 922 and 924 from which are generated serial signals at an output terminal connected to serial I/O controller 850 via signal line 854. This outgoing data forms channels Bd, Be and Bf at serial port 206. A synchronizing clock signal generated by the LIU 100 (LU1SCLKD) and the simultaneous application of a PHI clock applied to AND gate 936 is, in turn, applied to register 934 to provide the synchronization of the parallel signals applied to the inputs of register 934 with the generation of the serial outputs thereof. The operation of the serial port interface portion 842 of data routing multiplexer 840 is controlled by signals LU1Tbd, LU1Tbe and LU1Tbf and the PH2 clock applied to AND gates 915, 917 and 919 and sense signals MX2SEBD, MX2SEBE and MX2SEBF applied to registers 914, 916 and 918, respectively, to write to bus 204 from, or read from the serial port to, respectively, these registers, much as described in connection with the registers 900 and 902 of the MPI interface portion 841 of multiplexer 840. Signals MX1Tbf, MX1Tbe and MX1Tbd and data enable signals MX2DEBD, MX2DEBE and MX2DEBF applied to registers 920, 922 and 924, respectively, are used to read from bus 204, or write to the serial port, respectively, from these registers, much as described in connection with the registers 904 and 906 of the MPI interface 841. The LIU interface portion 843 (Fig. 5C) of data-routing multiplexer 840 includes a set of two eight-bit registers 944 and 946, and a set of two parallel-to-serial registers 948 and 950. The eight read terminals (outputs) of registers 944 and 946 are connected in parallel to the eight write terminals (inputs) of parallel-to-serial registers 948 and 950, respectively, by eight signal lines collectively denoted 952 and 954, respectively. The eight signal lines 952 and 954 each connect in a parallel manner to the eight bidirectional signal lines of bus 204. The eight write terminals (inputs) of registers 944 and 946 are connected in parallel to the eight output terminals of serial-to-parallel registers 956 and 958, respectively, via a set of eight serial lines collectively denoted 960 and 962, respectively. Serial-to-parallel registers 956 and 958 receive at an input terminal the incoming data on serial channel B1 and B2, respectively, conducted to the MUX 170 from LIU 110 signal lines 100. A snychronizing clock signal (LU1RDATA) generated by the LIU 110 of DSC 34 is applied gated via AND gates 957 and 959, respectively, with the PH2 clock signal to registers 956 and 958 to provide synchronization of the serial signals applied to the input terminals of registers 956 and 958 with the generation of the eight parallel signals at the outputs of registers 956 and 958, respectively, subsequently conducted via signal lines 960 and 962, respectively, to registers 944 and 946, respectively. Parallel-to-serial registers 948 and 950 receive clock signals (LU1CXB1 and LU1CXB2, respectively) generated by the LIU 110 gated via and gates 949 and 951, respectively, with the PH2 clock signal to provide synchronization of the eight parallel signals applied at their input terminals with the generation of the serial signals at the outputs of registers 948 and 950, respectively, and subsequently conducted via signal lines to form the outgoing data on serial channel B1 and B2, respectively, conducted via signal lines 100 to the LIU 110. The operation of the LIU interface portion 843 of data routing multiplexer 840 is controlled by signals MX1TS applied to registers 944 and 946 and sense signals MX2SEB1 and MX2SEB2 applied to registers 944 and 946, respectively, to write to bus 204 from, or read from the B1, B2, respectively, channel, much as described in connection with the registers 900 and 902 of the MPI interface portion 841 of multiplexer 840. Data enable signals MX2DEB1 and MX2DEB2 applied to registers 948 and 950, respectively, and clock signals LU1CXB1 and LU1CXB2 respectively, are used to read from bus 204, or write to the B1 channel, B2 channel, respectively, from these parallel-to-serial registers, much as described in connection with the registers 904 and 906 of the MPI interface 841. By external programming of the MCR1-3 portion 820 of the MUX 170 in accordance with Table I, above, the sense enable signals and data enable signals, discussed in connection with the data routing multiplexer portion 840 of MUX 170, will be generated by MCR1-3 portion 820 and received by data routing multiplexer 840 via signal lines 822 and 824 which will establish a bidirectional data path between any three of the following 64 kbs logical channels as a source and any three as a destination: Ba via the portion of bus 204 connecting the MAP 160 to the remainder of bus 204 shown interconnecting all three portions 841, 842 and 843 of data routing multiplexer 840 in Fig. 4; Bb and Bc via the bus 862 interconnecting the MPI interface portion 841 and MPI 100; Bd, Be and Bf via the signal lines 852 and 854 interconnecting the serial interface portion 842 and the serial port integral with MUX 170; and B1 and B2 via the signal lines 200 interconnecting the LIU interface portion 843 and the LIU 110 of DSC 34. The source and destination selection is effected by the subscriber as will now be described in connection with the MCR1-3 portion 820 of of MUX 170. Architecture internal to the MCR1-3 portion 820 is illustrated in Figs. 6A and 6B. The set of three eight-bit multiplexer control registers (MCR1, MCR2, MCR3) 970, 972 and 974, respectively, are interconnected in parallel as shown in Fig. 6A. Each of their eight write (input) terminals interconnected in a parallel fashion via a set of eight signal lines collectively denoted 976 and each of their eight read (output) terminals interconnected in a parallel fashion by a set of eight signal lines collectively denoted 978. The eight signal lines 976 also connected in a parallel fashion to the eight signal lines forming the bidirectional DB 7-o bus 210 which is connected to the MPI 100. The registers MCR1 970, MCR2 972, and MCR3 974, receive a Write enable and a read enable signal WRMCR1 and RDMCR1, WRMCR2 and RDMCR2, and WRMCR3 and RDMCR3, respectively, generated by the register address decode 810 portion of MUX 170, and received therefrom via signal lines 812. A phase one (PH1) clock signal generated by a master clock section of the DSC 34 (not shown) is applied to a clock (CLK) enable input terminal of the MCR1-3, 970, 972 and 974. This PH1 signal is used to synchronize writing to the registers. Clock signals MX1MCR10, MX1MCR20 and MXMCR30 generated by a time slot generator portion of the decode 810 portion of MUX 170 are applied to a second clock enable input terminal of the MCR1, MCR2 and MCR3, respectively, to synchronize reading from the registers 970, 972 and 974, respectively. As shown in Fig. 6B, the eight signal lines 978 are also connected in a parallel manner to the eight input terminals of a pair of 2:1 multiplexers 980 and 982. Multiplexer 980 has four output terminals which may be selectively interconnected in a parallel fashion to its four input terminals receiving the contents of the most-significant (ms) four bit positions of the MCR1-3 970, 972 and 974 or its four input terminals receiving the contents of the least-significant (ls) four bit positions of the MCR1-3 970, 972 and 974. Selection is time division multiplexed by the state of a binary-valued signals MX1TS35 and MX1TS46 generated by the time slot generator portion of decoder 810 applied to the multiplexer 780. In a similar manner, multiplexer 982 has four output terminals which can selectably be connected to the contents of the ms four bit positions of the MCR1-3 or their ls four bit positions. Selection is time-division multiplexed as determined by the signals MX1TS35 and MX1TS46 so that when the ms four bits are selected for output on multiplexer 980, the ls four bits are selected for output on multiplexer 982 and, conversely when the ls four bits are selected for output on multiplexer 980, the ms four bits are selected for output on multiplexer 982. As illustrated in Fig. 6B, the (true) signal at each output terminal of multiplexer 980 is conducted to an inverter 984a, 984b, 984c and 984d respectively, and the true and complemented signals generated by multiplexer 980 are used within a one-of-eight combinational logic circuit comprising eight NAND gates 986 which generate a signal in accordance with the inputs consisting of certain ones of the true or complemented signals of the four ms or four ls bit positions of MCR1 970, MCR2 972 or MCR3 974 selected by multiplexer 980, as will be appreciated by those skilled in the art. The resulting signal generated by the seven of the HAND gates 986 is conducted to a respective one of a set of eight inverters, the output signal generated by those seven inverters, being the sense enable signals MX2SEBB,MX2SEBC, MX2SEBD, MX2SEBE, MX2SEBF, MX2SEB1 AND MX2SEB2, conducted via signal lines 822 to data-routing multiplexer portion 840 to establish the three bidirectional data paths described above. A second one-of-eight combinatorial logic circuit comprising four inverters 988a-d, eight NAND gates 990a-f and eight inverters similarly generates the seven data enable signals selected by multiplexer 982; MX2DEBB, MX2DEBC, MX2DEBD, MX2DEBE, MX2DEBF, MX2DEB1 AND MX2DEB2, conducted via signal lines 824 to data-routing multiplexer 840 to establish the remaining three bidirectional/data paths. The "BA" signals derived from the eight gates and inverters one in each of the above cases, as discussed above, carried on the bus 204 to the MAP 160. The result of MCR1-3 portion 820 of MUX 170 is to generate time-division multiplexed sense and data enable signals synchronized by the PH2 clock signal which reflect the subscriber's selection of data routing via the eight logical channels to be performed within MUX 170. The MPI 100 generates address signals MP1STRT 6-o on bus 212 which permit the subscriber's selection of the three-logical-channel-to-three-logical-channel interconnection described above to be entered into the three MCR1-3 registers 970, 972 and 974. Register address decode portion 810 of MUX 170 generates from MP1STRT 6-o and the MP2READ and MP2WRIT2 signals generated by MPI 100, the WRMCR1, RDMCR1, WRMCR2, RDMCR2, and WRMCR3, RDMCR3 signals conducted to the MCR1 , MCR2 and MCR3 registers, respectively, via signal lines 812. These MCR1-3 write and read signals permit the routing information generated by the subscriber and passed therefrom to the data-routing multiplexer 840 from MPI 100 via the DB 7-o bus 210 to be entered into the appropriate MCR1-3 register in response to the WRMCR1, WRMCR2 and WRMCR3 signal generated by decode 810, as will be appreciated by those skilled in the art. Time-division multiplexer signals MX1MCR10, MX1MCR20 and MX1MCR30 generated internally within the time-slot generator portion of decode 810 and applied to MCR1, MCR2 and MCR3, respectively, cause the data-routing information on bus 210 to be entered to via signal lines 976, or sensed from via signal lines 978, a given MCR register only during its allocated time-division slot. The contents of the ms four bits of each MCR1-3 register 970,972 and 974 signify the logical channel source, in accordance with the code shown in Table I, above, and the ls four bits signify the logical channel destination, again, in accordance with Table I. The subscriber's selection of data-routing among the channels will accordingly be entered into MCR1, MCR2 and MCR3 via MPI 100 and the time-division multiplex data enable and sense enable signals MX2DEBB, MX2DEBC, MX2DEBD, MX2DEBE, MX2DEBF, MX2DEB1, MX2DEB2 and MX2SEBB, MX2SEBC, MX2SEBD, MX2SEBE, MX2SEBF, MX2SEB1, MX2SEB2 generated by MCR1-MCR3 portion 820 of MUX 170 will cause the registers 900, 902, 914, 916, 918, 944, 946, respectively, and registers 904, 906, 920, 922, 924, 948, 950, respectively, to transfer data to and from, respectively, that portion of bus 204 shown in Fig. 5, implementing the three subscriber-selected source and destinations, as described in connection with the data routing multiplexer 840, above.

Claims: A programmable multiplexer (170) for use in a digital subscriber controller (34) having clock means for generating timing signals and a plurality of interface means (110,160), for connecting analog and digital devices to said controller, and including control logic and microprocessor interface means (100) responsive to subscriber commands for generating control signals (MP1STRT, MP2READ, MP2WRITE) representative of subscriber-selected source-destination combinations, said source and said destination being subscriber-selected ones of said plurality of interface means, said programmable multiplexer being characterised by: control register means (810,820), responsive to said control signals generated by said control logic and microprocessor interface means for generating a plurality of time-division-multiplexed data-routing signals (MX2SEB, MX2DEB) therefrom, indicative of said subscriber-selected sources and destinations, each said time-division of said data-routing signal comprising a time-multiplexed source portion (MX2SEB) and a destination portion (MX2DEB) and data-routing multiplexer means (840), connected to said plurality of interface means and responsive to said time-division multiplexed data-routing signals for establishing a time-division multiplexed data path between each said subscriber-selected source-destination combination. A programmable multiplexer according to Claim 1, characterised in that said data routing multiplexer means (840) is connected to a predetermined one of said interface means via a data bus (204), and in that said data bus has a portion which is internal to said data routing multiplexer means. A programmable multiplexer according to Claim 2 characterised in that; said data-routing multiplexer means includes a plurality of first plural-bit register means (900,902,904,906) each having a plurality of input terminals and a plurality of output terminals, a predetermined first plurality (900,902) of said first plural-bit register means is connected with their input terminals in parallel with the output terminals of a predetermined second plurality (904,906) of said first plural-bit register means and in parallel to said control logic and microprocessor interface means; each of said predetermined first plurality of said first plural-bit register means is connected with its output terminals in parallel with the input terminals of a predetermined one of said predetermined second plurality of said first plural-bit register means and in parallel to said data bus portion internal to said data-routing multiplexer means; each said first plural-bit register means has a control terminal connected to said control register means (810,820) and responsive to said time-division multiplexed data-routing signals (MX2SEB, MX2DEB), said first predetermined plurality of first plural-bit register means is arranged for storing in parallel data received from said control logic and microprocessor means and generating data on said data bus in response to reception of predetermined ones of said data-routing signals, and said second predetermined plurality of first plural-bit register means is arranged for storing in parallel data received from one of said subscriber-selected interface means via said data bus portion internal to said data-routing multiplexer means and generating said data to said control logic and microprocessor interface means in response to reception of predetermined ones of said data-routing signals. A programmable multiplexer according to Claim 2 or 3 characterised in that said controller has a first serial interface means (850); and characterised in that said data-routing multiplexer means includes: serial-to-parallel register means (930) having an input terminal connected to said first serial interface means and a plurality of output terminals (932) responsive to said clock means for generating in parallel at said output terminals data signals representative of time-multiplexed serial signals applied at said input terminal, parallel-to-serial register means (934) having an output terminal connected to said first serial interface means and having a plurality of input terminals (936), responsive to said clock means for generating at said first serial interface means time-multiplexed signals representative of parallel data signals applied at said input terminals, a plurality of second plural-bit register means (914,916,918,920,922,924) each having a plurality of input terminals and a plurality of output terminals, a predetermined first plurality (914,916,918) of said second plural-bit register means is connected at their input terminals in parallel with the output terminals of said serial-to-parallel register means (930), a predetermined second plurality (920,922,924) of said second plural-bit register means is connected at their output terminals in parallel with the input terminals of said parallel-to-serial register means (934), each of said first predetermined plurality of said second plural-bit register means is connected at its output terminals in parallel with the input terminals of a predetermined one of said second predetermined plurality of said second plural-bit register means and in parallel to said data bus portion internal to said data-routing multiplexer means, each of said predetermined plurality of second plural-bit register means has a control terminal connected to said control register means (820) and responsive to said time-division multiplexed data-routing signals (MX2SEB, MX2DEB), said first predetermined plurality of second plural-bit register means is arranged for storing in parallel data received from said serial interface means and generating data on said data bus in response to reception of predetermined ones of said data-routing signals, and said predetermined second plurality of second plural-bit register means is arranged for storing in parallel data received from one of said subscriber-selected interface means via said data bus portion internal to said data-routing means and generating said data to said serial interface means in response to reception of predetermined ones of said data-routing signals. A programmable multiplexer according to Claim 2, 3 or 4, characterised in that said controller has a plurality of serial interface means, and characterised in that said data-routing multiplexer means (840) includes: a plurality of further serial-to-parallel register means (956,958) each having an input terminal connected to a predetermined one of said serial interface means (110) and a respective plurality of output terminals (960,962), and each responsive to said clock means, for generating in parallel at said output terminals data signals representative of time-multiplexed serial signals applied at said input terminal; a plurality of further parallel-to-serial register means (948,950) each having an output terminal connected to a predetermined one of said serial interface means (110) and a respective plurality of input terminals, and each responsive to said clock means, for generating at said output terminal time-multiplexed signals representative of parallel data signals applied at said input terminals; a plurality of third plural-bit register means (944,946) each having a plurality of input terminals and a plurality of output terminals, each of said third plural-bit register means being connected at their input terminals in parallel with the output terminals of a respective one of said further serial-to-parallel register means (956,958), each of said third plural-bit register means being connected at its outputs to the inputs of a respective one of said plurality of further parallel-to-serial register means (948,950), the outputs of said third plural-bit register means are further connected in parallel to said portion of said data bus internal to said data-routing means, and each of said third plural-bit register means has a control terminal connected to said control register means (820) and responsive to said time-division multiplexed data-routing signals (MX2SEB) for storing in parallel data received from a respective predetermined one of said plurality of further serial interface means and generating said data on said data bus in response to reception of predetermined ones of said data-routing signals. A programmable multiplexer according to any preceding claim, characterised in that said control register means (810,820) comprises: register address decode and time slot generator means (810) responsive to said clock means, address control signals (MP1STRT) generated by said control logic and microprocessor interface means (100), for generating therefrom a plurality of multiplexer control register read signals (RDMCR) and a plurality of multiplexer control register write signals (WRMCR); and addressable multiplexer control register means (970,972,974) responsive to said read and write signals, and further responsive to data control signals (DB) generated by said control logic and microprocessor interface means, for generating therefrom said time-division-multiplexed data-routing signals (MX2SEB, MX2DEB) representative of said subscriber-selected source-destination combinations. A programmable multiplexer according to Claim 6 characterised in that said multiplexer control register means (820) receives said data control signals (DB) from said control logic and microprocessor interface means via a control bus (210) and in that; said addressable multiplex control plural-bit register means (970,972,974), each has a plurality of input terminals and a plurality of output terminals, are interconnected in parallel at their output terminals, and interconnected in parallel at their input terminals and to said control bus, and each said register means is each further responsive to said clock means, for storing said data control signals (DB) in parallel in said multiplex control register means having the address represented by a predetermined write signal, and for generating on said parallel output terminals time-multiplexed code control signals in response to reception of predetermined ones of said clock signals and a predetermined read signal; and further characterised by a plurality of two-to-one multiplexer means (980,982) each having a plurality of input terminals connected in parallel with said parallel interconnection of said output terminals of said multiplex control register means and each having a plurality of output terminals, each being responsive to multiplex control signals (MXITS3, MXITS4) applied at control terminals thereof, for selectably generating at said output terminals the signals applied at a predetermined first plurality of said input terminals or the signals applied at a predetermined second plurality of said input terminals; and data-routing signal generating means (984,986,988,990) connected to said two-to-one multiplexer means for generating said time-division multiplexed data-routing signals (MX2SEB, MX2DEB) representative of said subscriber-selected source-destination combinations. A programmable multiplexer according to Claim 6 or 7, characterised in that said controller (34) is connected to at least a first (B1), second (B2), third (Ba), fourth (Bb), fifth (Bc), sixth (Bd), seventh (Be) and eighth (Bf) interface means, and in that said addressable plural-bit multiplex control register means (970,972,974) comprise at least three registers each capable of storing eight binary digits (bits) each register having eight input terminals and eight output terminals, in that said two-to-one multiplexer means (980,982) each having eight input terminals arranged in a most-significant to a least-significant terminal and four output terminals and can selectably generate at said four output terminals the signals applied at said four most-significant input terminals or at said four least-significant input terminals, and in that said time-division multiplexed data-routing signal generated by said data-routing signal generating means are in accordance with the following relationship: Second Code Control Signal Subscriber-Selected Source/Destination 0000 No connection 0001 First Interface Means 0010 Second Interface Means 0011 Third Interface Means 0100 Fourth Interface Means 0101 Fifth Interface Means 0110 Sixth Interface Means 0111 Seventh Interface Means 1000 Eighth Interface Means whereby an eight-bit signal comprising a first four-bit portion being one of said second code control signals and a second four-bit portion being one of said second code signal generated by said control logic and microprocessor interface means is stored in one of said addressable control registers and said first four-bit portion is conveyed to said data-routing signal generating means via said two-to-one multiplexer means causing said data-routing from said subscriber selected source corresponding to said first code control stored in said most-significant portion of said control register and said second four-bit portion in a subsequent time-division is conveyed to said data-routing signal generating means via said two-to-one multiplexer means causing said data-routing to said subscriber-selected destination corresponding to said second code control stored in said least-significant portion of said control register.

Inventors: CLARK, ALAN T., LANGE, ARTHUR F.
Applicants: ADVANCED MICRO DEVICES, INC.
Application year: 1986
Main classification: H04Q11
IPC codes: H04M11, H04Q3, H04J3, H04M3, H04Q11